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    "path": ".gitignore",
    "content": "# Quartus generated files and folders\n*.rpt\n*.done\n*.rpt\n*.smsg\n*.summary\n*.ddb\ndb/\nincremental_db/\nout/\noutput_files/\ngreybox_tmp/\n\n# Quartus workspace file: stores window position, dock state etc.\n*.qws\n\n# ModelSim files and folders\ntranscript\n*.mti\n*.wlf\n_*\n_temp/\n_primary.*\n*.prw\n*.psm\n*.vstf\nmgc_location_map\n\n# Generic backup files\n*~\n*.bak\n\n# Visual Studio temporary files\n*.suo\n*.tss\n*.user\nobj/\nDebug/\nRelease/\n*.DotSettings\n\n# ZMAC assembler output directory\nzout/\n"
  },
  {
    "path": "cpu/alu/alu.bdf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  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320)\n)\n(connector\n\t(pt 1808 304)\n\t(pt 1800 304)\n)\n(connector\n\t(pt 2048 312)\n\t(pt 2032 312)\n)\n(connector\n\t(pt 2048 216)\n\t(pt 2048 312)\n)\n(connector\n\t(pt 1888 312)\n\t(pt 1880 312)\n)\n(connector\n\t(text \"result_hi[3]\" (rect 1696 341 1708 395)(font \"Arial\" )(vertical))\n\t(pt 1712 400)\n\t(pt 1712 296)\n)\n(connector\n\t(text \"result_hi[2]\" (rect 1784 341 1796 395)(font \"Arial\" )(vertical))\n\t(pt 1800 400)\n\t(pt 1800 304)\n)\n(connector\n\t(text \"result_hi[1]\" (rect 1864 341 1876 395)(font \"Arial\" )(vertical))\n\t(pt 1880 400)\n\t(pt 1880 312)\n)\n(connector\n\t(text \"result_hi[0]\" (rect 1944 341 1956 395)(font \"Arial\" )(vertical))\n\t(pt 1960 400)\n\t(pt 1960 320)\n)\n(connector\n\t(pt 2048 400)\n\t(pt 2048 488)\n\t(bus)\n\t(color 0 0 255)\n)\n(connector\n\t(text \"db_low[3]\" (rect 1872 169 1884 215)(font \"Arial\" )(vertical))\n\t(pt 1896 216)\n\t(pt 1896 240)\n)\n(connector\n\t(pt 2256 344)\n\t(pt 2256 216)\n)\n(connector\n\t(pt 2240 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\"Arial\" ))(text \"May 18, 2014\" (rect 56 3 149 19)(font \"Arial\" (font_size 10)))(border))\n\t(section (rect 241 41 320 60)(text \"REV\" (rect 2 1 25 13)(font \"Arial\" ))(text \"1.4\" (rect 43 3 64 19)(font \"Arial\" (font_size 10)))(border))\n\t(drawing\n\t)\n)\n"
  },
  {
    "path": "cpu/alu/alu.bsf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"symbol\" (version \"1.2\"))\n(symbol\n\t(rect 16 16 272 464)\n\t(text \"alu\" (rect 5 0 21 14)(font \"Arial\" (font_size 8)))\n\t(text \"inst\" (rect 8 432 25 444)(font \"Arial\" ))\n\t(port\n\t\t(pt 0 32)\n\t\t(input)\n\t\t(text \"alu_oe\" (rect 0 0 37 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"alu_oe\" (rect 21 27 58 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 32)(pt 16 32))\n\t)\n\t(port\n\t\t(pt 0 48)\n\t\t(input)\n\t\t(text \"alu_shift_in\" (rect 0 0 64 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"alu_shift_in\" (rect 21 43 85 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 48)(pt 16 48))\n\t)\n\t(port\n\t\t(pt 0 64)\n\t\t(input)\n\t\t(text \"alu_shift_left\" (rect 0 0 73 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"alu_shift_left\" (rect 21 59 94 73)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 64)(pt 16 64))\n\t)\n\t(port\n\t\t(pt 0 80)\n\t\t(input)\n\t\t(text \"alu_shift_right\" (rect 0 0 80 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"alu_shift_right\" (rect 21 75 101 89)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 80)(pt 16 80))\n\t)\n\t(port\n\t\t(pt 0 96)\n\t\t(input)\n\t\t(text \"alu_core_R\" (rect 0 0 64 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"alu_core_R\" (rect 21 91 85 105)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 96)(pt 16 96))\n\t)\n\t(port\n\t\t(pt 0 112)\n\t\t(input)\n\t\t(text \"alu_core_V\" (rect 0 0 66 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"alu_core_V\" (rect 21 107 87 121)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 112)(pt 16 112))\n\t)\n\t(port\n\t\t(pt 0 128)\n\t\t(input)\n\t\t(text \"alu_core_S\" (rect 0 0 64 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"alu_core_S\" (rect 21 123 85 137)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 128)(pt 16 128))\n\t)\n\t(port\n\t\t(pt 0 144)\n\t\t(input)\n\t\t(text \"alu_bs_oe\" (rect 0 0 59 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"alu_bs_oe\" (rect 21 139 80 153)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 144)(pt 16 144))\n\t)\n\t(port\n\t\t(pt 0 160)\n\t\t(input)\n\t\t(text \"alu_parity_in\" (rect 0 0 71 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"alu_parity_in\" (rect 21 155 92 169)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 160)(pt 16 160))\n\t)\n\t(port\n\t\t(pt 0 176)\n\t\t(input)\n\t\t(text \"alu_shift_oe\" (rect 0 0 69 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"alu_shift_oe\" (rect 21 171 90 185)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 176)(pt 16 176))\n\t)\n\t(port\n\t\t(pt 0 192)\n\t\t(input)\n\t\t(text \"alu_core_cf_in\" (rect 0 0 84 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"alu_core_cf_in\" (rect 21 187 105 201)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 192)(pt 16 192))\n\t)\n\t(port\n\t\t(pt 0 208)\n\t\t(input)\n\t\t(text \"alu_op2_oe\" (rect 0 0 66 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"alu_op2_oe\" (rect 21 203 87 217)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 208)(pt 16 208))\n\t)\n\t(port\n\t\t(pt 0 224)\n\t\t(input)\n\t\t(text \"alu_op1_oe\" (rect 0 0 66 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"alu_op1_oe\" (rect 21 219 87 233)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 224)(pt 16 224))\n\t)\n\t(port\n\t\t(pt 0 240)\n\t\t(input)\n\t\t(text \"alu_res_oe\" (rect 0 0 63 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"alu_res_oe\" (rect 21 235 84 249)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 240)(pt 16 240))\n\t)\n\t(port\n\t\t(pt 0 256)\n\t\t(input)\n\t\t(text \"alu_op1_sel_low\" (rect 0 0 96 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"alu_op1_sel_low\" (rect 21 251 117 265)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 256)(pt 16 256))\n\t)\n\t(port\n\t\t(pt 0 272)\n\t\t(input)\n\t\t(text \"alu_op1_sel_zero\" (rect 0 0 101 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"alu_op1_sel_zero\" (rect 21 267 122 281)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 272)(pt 16 272))\n\t)\n\t(port\n\t\t(pt 0 288)\n\t\t(input)\n\t\t(text \"alu_op1_sel_bus\" (rect 0 0 96 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"alu_op1_sel_bus\" (rect 21 283 117 297)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 288)(pt 16 288))\n\t)\n\t(port\n\t\t(pt 0 304)\n\t\t(input)\n\t\t(text \"alu_op2_sel_zero\" (rect 0 0 101 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"alu_op2_sel_zero\" (rect 21 299 122 313)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 304)(pt 16 304))\n\t)\n\t(port\n\t\t(pt 0 320)\n\t\t(input)\n\t\t(text \"alu_op2_sel_bus\" (rect 0 0 96 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"alu_op2_sel_bus\" (rect 21 315 117 329)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 320)(pt 16 320))\n\t)\n\t(port\n\t\t(pt 0 336)\n\t\t(input)\n\t\t(text \"alu_op2_sel_lq\" (rect 0 0 84 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"alu_op2_sel_lq\" (rect 21 331 105 345)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 336)(pt 16 336))\n\t)\n\t(port\n\t\t(pt 0 352)\n\t\t(input)\n\t\t(text \"alu_op_low\" (rect 0 0 66 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"alu_op_low\" (rect 21 347 87 361)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 352)(pt 16 352))\n\t)\n\t(port\n\t\t(pt 0 368)\n\t\t(input)\n\t\t(text \"alu_sel_op2_neg\" (rect 0 0 96 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"alu_sel_op2_neg\" (rect 21 363 117 377)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 368)(pt 16 368))\n\t)\n\t(port\n\t\t(pt 0 384)\n\t\t(input)\n\t\t(text \"alu_sel_op2_high\" (rect 0 0 99 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"alu_sel_op2_high\" (rect 21 379 120 393)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 384)(pt 16 384))\n\t)\n\t(port\n\t\t(pt 0 400)\n\t\t(input)\n\t\t(text \"clk\" (rect 0 0 15 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"clk\" (rect 21 395 36 409)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 400)(pt 16 400))\n\t)\n\t(port\n\t\t(pt 0 416)\n\t\t(input)\n\t\t(text \"bsel[2..0]\" (rect 0 0 51 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"bsel[2..0]\" (rect 21 411 72 425)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 416)(pt 16 416)(line_width 3))\n\t)\n\t(port\n\t\t(pt 256 32)\n\t\t(output)\n\t\t(text \"alu_zero\" (rect 0 0 49 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"alu_zero\" (rect 186 27 235 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 256 32)(pt 240 32))\n\t)\n\t(port\n\t\t(pt 256 48)\n\t\t(output)\n\t\t(text \"alu_parity_out\" (rect 0 0 80 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"alu_parity_out\" (rect 155 43 235 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 256 48)(pt 240 48))\n\t)\n\t(port\n\t\t(pt 256 64)\n\t\t(output)\n\t\t(text \"alu_high_eq_9\" (rect 0 0 82 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"alu_high_eq_9\" (rect 153 59 235 73)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 256 64)(pt 240 64))\n\t)\n\t(port\n\t\t(pt 256 80)\n\t\t(output)\n\t\t(text \"alu_high_gt_9\" (rect 0 0 79 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"alu_high_gt_9\" (rect 156 75 235 89)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 256 80)(pt 240 80))\n\t)\n\t(port\n\t\t(pt 256 96)\n\t\t(output)\n\t\t(text \"alu_low_gt_9\" (rect 0 0 76 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"alu_low_gt_9\" (rect 159 91 235 105)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 256 96)(pt 240 96))\n\t)\n\t(port\n\t\t(pt 256 112)\n\t\t(output)\n\t\t(text \"alu_shift_db0\" (rect 0 0 76 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"alu_shift_db0\" (rect 159 107 235 121)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 256 112)(pt 240 112))\n\t)\n\t(port\n\t\t(pt 256 128)\n\t\t(output)\n\t\t(text \"alu_shift_db7\" (rect 0 0 76 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"alu_shift_db7\" (rect 159 123 235 137)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 256 128)(pt 240 128))\n\t)\n\t(port\n\t\t(pt 256 144)\n\t\t(output)\n\t\t(text \"alu_core_cf_out\" (rect 0 0 93 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"alu_core_cf_out\" (rect 142 139 235 153)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 256 144)(pt 240 144))\n\t)\n\t(port\n\t\t(pt 256 160)\n\t\t(output)\n\t\t(text \"alu_sf_out\" (rect 0 0 60 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"alu_sf_out\" (rect 175 155 235 169)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 256 160)(pt 240 160))\n\t)\n\t(port\n\t\t(pt 256 176)\n\t\t(output)\n\t\t(text \"alu_yf_out\" (rect 0 0 60 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"alu_yf_out\" (rect 175 171 235 185)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 256 176)(pt 240 176))\n\t)\n\t(port\n\t\t(pt 256 192)\n\t\t(output)\n\t\t(text \"alu_xf_out\" (rect 0 0 60 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"alu_xf_out\" (rect 175 187 235 201)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 256 192)(pt 240 192))\n\t)\n\t(port\n\t\t(pt 256 208)\n\t\t(output)\n\t\t(text \"alu_vf_out\" (rect 0 0 60 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"alu_vf_out\" (rect 175 203 235 217)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 256 208)(pt 240 208))\n\t)\n\t(port\n\t\t(pt 256 224)\n\t\t(output)\n\t\t(text \"test_db_low[3..0]\" (rect 0 0 99 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"test_db_low[3..0]\" (rect 136 219 235 233)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 256 224)(pt 240 224)(line_width 3))\n\t)\n\t(port\n\t\t(pt 256 256)\n\t\t(output)\n\t\t(text \"test_db_high[3..0]\" (rect 0 0 101 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"test_db_high[3..0]\" (rect 134 251 235 265)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 256 256)(pt 240 256)(line_width 3))\n\t)\n\t(port\n\t\t(pt 256 240)\n\t\t(bidir)\n\t\t(text \"db[7..0]\" (rect 0 0 42 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"db[7..0]\" (rect 193 235 235 249)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 256 240)(pt 240 240)(line_width 3))\n\t)\n\t(drawing\n\t\t(rectangle (rect 16 16 240 432))\n\t)\n)\n"
  },
  {
    "path": "cpu/alu/alu.v",
    "content": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and other software and tools, and its AMPP partner logic \n// functions, and any output files from any of the foregoing \n// (including device programming or simulation files), and any \n// associated documentation or information are expressly subject \n// to the terms and conditions of the Altera Program License \n// Subscription Agreement, Altera MegaCore Function License \n// Agreement, or other applicable license agreement, including, \n// without limitation, that your use is for the sole purpose of \n// programming logic devices manufactured by Altera and sold by \n// Altera or its authorized distributors.  Please refer to the \n// applicable agreement for further details.\n\n// PROGRAM\t\t\"Quartus II 64-Bit\"\n// VERSION\t\t\"Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\"\n// CREATED\t\t\"Fri Nov 07 19:44:45 2014\"\n\nmodule alu(\n\talu_core_R,\n\talu_core_V,\n\talu_core_S,\n\talu_bs_oe,\n\talu_parity_in,\n\talu_oe,\n\talu_shift_oe,\n\talu_core_cf_in,\n\talu_op2_oe,\n\talu_op1_oe,\n\talu_res_oe,\n\talu_op1_sel_low,\n\talu_op1_sel_zero,\n\talu_op1_sel_bus,\n\talu_op2_sel_zero,\n\talu_op2_sel_bus,\n\talu_op2_sel_lq,\n\talu_op_low,\n\talu_shift_in,\n\talu_sel_op2_neg,\n\talu_sel_op2_high,\n\talu_shift_left,\n\talu_shift_right,\n\tclk,\n\tbsel,\n\talu_zero,\n\talu_parity_out,\n\talu_high_eq_9,\n\talu_high_gt_9,\n\talu_low_gt_9,\n\talu_shift_db0,\n\talu_shift_db7,\n\talu_core_cf_out,\n\talu_sf_out,\n\talu_yf_out,\n\talu_xf_out,\n\talu_vf_out,\n\tdb,\n\ttest_db_high,\n\ttest_db_low\n);\n\n\ninput wire\talu_core_R;\ninput wire\talu_core_V;\ninput wire\talu_core_S;\ninput wire\talu_bs_oe;\ninput wire\talu_parity_in;\ninput wire\talu_oe;\ninput wire\talu_shift_oe;\ninput wire\talu_core_cf_in;\ninput wire\talu_op2_oe;\ninput wire\talu_op1_oe;\ninput wire\talu_res_oe;\ninput wire\talu_op1_sel_low;\ninput wire\talu_op1_sel_zero;\ninput wire\talu_op1_sel_bus;\ninput wire\talu_op2_sel_zero;\ninput wire\talu_op2_sel_bus;\ninput wire\talu_op2_sel_lq;\ninput wire\talu_op_low;\ninput wire\talu_shift_in;\ninput wire\talu_sel_op2_neg;\ninput wire\talu_sel_op2_high;\ninput wire\talu_shift_left;\ninput wire\talu_shift_right;\ninput wire\tclk;\ninput wire\t[2:0] bsel;\noutput wire\talu_zero;\noutput wire\talu_parity_out;\noutput wire\talu_high_eq_9;\noutput wire\talu_high_gt_9;\noutput wire\talu_low_gt_9;\noutput wire\talu_shift_db0;\noutput wire\talu_shift_db7;\noutput wire\talu_core_cf_out;\noutput wire\talu_sf_out;\noutput wire\talu_yf_out;\noutput wire\talu_xf_out;\noutput wire\talu_vf_out;\ninout wire\t[7:0] db;\noutput wire\t[3:0] test_db_high;\noutput wire\t[3:0] test_db_low;\n\nwire\t[3:0] alu_op1;\nwire\t[3:0] alu_op2;\nwire\t[3:0] db_high;\nwire\t[3:0] db_low;\nreg\t[3:0] op1_high;\nreg\t[3:0] op1_low;\nreg\t[3:0] op2_high;\nreg\t[3:0] op2_low;\nwire\t[3:0] result_hi;\nreg\t[3:0] result_lo;\nwire\t[3:0] SYNTHESIZED_WIRE_0;\nwire\t[3:0] SYNTHESIZED_WIRE_1;\nwire\t[3:0] SYNTHESIZED_WIRE_2;\nwire\t[3:0] SYNTHESIZED_WIRE_3;\nwire\tSYNTHESIZED_WIRE_35;\nwire\t[3:0] SYNTHESIZED_WIRE_5;\nwire\t[3:0] SYNTHESIZED_WIRE_7;\nwire\t[3:0] SYNTHESIZED_WIRE_8;\nwire\tSYNTHESIZED_WIRE_9;\nwire\t[3:0] SYNTHESIZED_WIRE_10;\nwire\t[3:0] SYNTHESIZED_WIRE_11;\nwire\t[3:0] SYNTHESIZED_WIRE_12;\nwire\t[3:0] SYNTHESIZED_WIRE_13;\nwire\t[3:0] SYNTHESIZED_WIRE_14;\nwire\t[3:0] SYNTHESIZED_WIRE_15;\nwire\t[3:0] SYNTHESIZED_WIRE_16;\nwire\tSYNTHESIZED_WIRE_17;\nwire\t[3:0] SYNTHESIZED_WIRE_18;\nwire\tSYNTHESIZED_WIRE_36;\nwire\tSYNTHESIZED_WIRE_20;\nwire\t[3:0] SYNTHESIZED_WIRE_21;\nwire\tSYNTHESIZED_WIRE_23;\nwire\t[3:0] SYNTHESIZED_WIRE_24;\nwire\tSYNTHESIZED_WIRE_37;\nwire\tSYNTHESIZED_WIRE_26;\nwire\t[3:0] SYNTHESIZED_WIRE_27;\nwire\tSYNTHESIZED_WIRE_29;\nwire\tSYNTHESIZED_WIRE_30;\nwire\tSYNTHESIZED_WIRE_31;\nwire\tSYNTHESIZED_WIRE_32;\nwire\t[3:0] SYNTHESIZED_WIRE_33;\nwire\t[3:0] SYNTHESIZED_WIRE_34;\n\n\n\n\nassign\tdb_low[3] = alu_bs_oe ? SYNTHESIZED_WIRE_0[3] : 1'bz;\nassign\tdb_low[2] = alu_bs_oe ? SYNTHESIZED_WIRE_0[2] : 1'bz;\nassign\tdb_low[1] = alu_bs_oe ? SYNTHESIZED_WIRE_0[1] : 1'bz;\nassign\tdb_low[0] = alu_bs_oe ? SYNTHESIZED_WIRE_0[0] : 1'bz;\n\nassign\tdb_high[3] = alu_bs_oe ? SYNTHESIZED_WIRE_1[3] : 1'bz;\nassign\tdb_high[2] = alu_bs_oe ? SYNTHESIZED_WIRE_1[2] : 1'bz;\nassign\tdb_high[1] = alu_bs_oe ? SYNTHESIZED_WIRE_1[1] : 1'bz;\nassign\tdb_high[0] = alu_bs_oe ? SYNTHESIZED_WIRE_1[0] : 1'bz;\n\n\nalu_core\tb2v_core(\n\t.cy_in(alu_core_cf_in),\n\t.S(alu_core_S),\n\t.V(alu_core_V),\n\t.R(alu_core_R),\n\t.op1(alu_op1),\n\t.op2(alu_op2),\n\t.cy_out(alu_core_cf_out),\n\t.vf_out(alu_vf_out),\n\t.result(result_hi));\n\nassign\tdb[3] = alu_oe ? db_low[3] : 1'bz;\nassign\tdb[2] = alu_oe ? db_low[2] : 1'bz;\nassign\tdb[1] = alu_oe ? db_low[1] : 1'bz;\nassign\tdb[0] = alu_oe ? db_low[0] : 1'bz;\n\nassign\tdb[7] = alu_oe ? db_high[3] : 1'bz;\nassign\tdb[6] = alu_oe ? db_high[2] : 1'bz;\nassign\tdb[5] = alu_oe ? db_high[1] : 1'bz;\nassign\tdb[4] = alu_oe ? db_high[0] : 1'bz;\n\n\nalu_bit_select\tb2v_input_bit_select(\n\t.bsel(bsel),\n\t.bs_out_high(SYNTHESIZED_WIRE_1),\n\t.bs_out_low(SYNTHESIZED_WIRE_0));\n\n\nalu_shifter_core\tb2v_input_shift(\n\t.shift_in(alu_shift_in),\n\t.shift_left(alu_shift_left),\n\t.shift_right(alu_shift_right),\n\t.db(db),\n\t.shift_db0(alu_shift_db0),\n\t.shift_db7(alu_shift_db7),\n\t.out_high(SYNTHESIZED_WIRE_34),\n\t.out_low(SYNTHESIZED_WIRE_33));\n\n\nalways@(posedge clk)\nbegin\nif (alu_op_low)\n\tbegin\n\tresult_lo[3:0] <= result_hi[3:0];\n\tend\nend\n\nassign\talu_op1 = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_3;\n\nassign\tSYNTHESIZED_WIRE_17 =  ~alu_op_low;\n\nassign\tdb_low[3] = alu_op2_oe ? op2_low[3] : 1'bz;\nassign\tdb_low[2] = alu_op2_oe ? op2_low[2] : 1'bz;\nassign\tdb_low[1] = alu_op2_oe ? op2_low[1] : 1'bz;\nassign\tdb_low[0] = alu_op2_oe ? op2_low[0] : 1'bz;\n\nassign\tdb_high[3] = alu_op2_oe ? op2_high[3] : 1'bz;\nassign\tdb_high[2] = alu_op2_oe ? op2_high[2] : 1'bz;\nassign\tdb_high[1] = alu_op2_oe ? op2_high[1] : 1'bz;\nassign\tdb_high[0] = alu_op2_oe ? op2_high[0] : 1'bz;\n\nassign\tSYNTHESIZED_WIRE_5 =  ~op2_low;\n\nassign\tSYNTHESIZED_WIRE_7 =  ~op2_high;\n\nassign\tSYNTHESIZED_WIRE_12 = op2_low & {SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_35};\n\nassign\tSYNTHESIZED_WIRE_11 = {alu_sel_op2_neg,alu_sel_op2_neg,alu_sel_op2_neg,alu_sel_op2_neg} & SYNTHESIZED_WIRE_5;\n\nassign\tSYNTHESIZED_WIRE_14 = op2_high & {SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_35};\n\nassign\tSYNTHESIZED_WIRE_13 = {alu_sel_op2_neg,alu_sel_op2_neg,alu_sel_op2_neg,alu_sel_op2_neg} & SYNTHESIZED_WIRE_7;\n\nassign\tSYNTHESIZED_WIRE_16 = SYNTHESIZED_WIRE_8 & {SYNTHESIZED_WIRE_9,SYNTHESIZED_WIRE_9,SYNTHESIZED_WIRE_9,SYNTHESIZED_WIRE_9};\n\nassign\tSYNTHESIZED_WIRE_15 = {alu_sel_op2_high,alu_sel_op2_high,alu_sel_op2_high,alu_sel_op2_high} & SYNTHESIZED_WIRE_10;\n\nassign\tSYNTHESIZED_WIRE_8 = SYNTHESIZED_WIRE_11 | SYNTHESIZED_WIRE_12;\n\nassign\tSYNTHESIZED_WIRE_10 = SYNTHESIZED_WIRE_13 | SYNTHESIZED_WIRE_14;\n\nassign\talu_op2 = SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16;\n\nassign\tSYNTHESIZED_WIRE_35 =  ~alu_sel_op2_neg;\n\nassign\tSYNTHESIZED_WIRE_9 =  ~alu_sel_op2_high;\n\nassign\tdb_low[3] = alu_res_oe ? result_lo[3] : 1'bz;\nassign\tdb_low[2] = alu_res_oe ? result_lo[2] : 1'bz;\nassign\tdb_low[1] = alu_res_oe ? result_lo[1] : 1'bz;\nassign\tdb_low[0] = alu_res_oe ? result_lo[0] : 1'bz;\n\nassign\tdb_high[3] = alu_res_oe ? result_hi[3] : 1'bz;\nassign\tdb_high[2] = alu_res_oe ? result_hi[2] : 1'bz;\nassign\tdb_high[1] = alu_res_oe ? result_hi[1] : 1'bz;\nassign\tdb_high[0] = alu_res_oe ? result_hi[0] : 1'bz;\n\nassign\tSYNTHESIZED_WIRE_3 = op1_low & {alu_op_low,alu_op_low,alu_op_low,alu_op_low};\n\nassign\tSYNTHESIZED_WIRE_2 = {SYNTHESIZED_WIRE_17,SYNTHESIZED_WIRE_17,SYNTHESIZED_WIRE_17,SYNTHESIZED_WIRE_17} & op1_high;\n\n\nalways@(posedge SYNTHESIZED_WIRE_36)\nbegin\nif (SYNTHESIZED_WIRE_20)\n\tbegin\n\top1_high[3:0] <= SYNTHESIZED_WIRE_18[3:0];\n\tend\nend\n\n\nalways@(posedge SYNTHESIZED_WIRE_36)\nbegin\nif (SYNTHESIZED_WIRE_23)\n\tbegin\n\top1_low[3:0] <= SYNTHESIZED_WIRE_21[3:0];\n\tend\nend\n\n\nalways@(posedge SYNTHESIZED_WIRE_37)\nbegin\nif (SYNTHESIZED_WIRE_26)\n\tbegin\n\top2_high[3:0] <= SYNTHESIZED_WIRE_24[3:0];\n\tend\nend\n\n\nalways@(posedge SYNTHESIZED_WIRE_37)\nbegin\nif (SYNTHESIZED_WIRE_29)\n\tbegin\n\top2_low[3:0] <= SYNTHESIZED_WIRE_27[3:0];\n\tend\nend\n\nassign\tdb_low[3] = alu_op1_oe ? op1_low[3] : 1'bz;\nassign\tdb_low[2] = alu_op1_oe ? op1_low[2] : 1'bz;\nassign\tdb_low[1] = alu_op1_oe ? op1_low[1] : 1'bz;\nassign\tdb_low[0] = alu_op1_oe ? op1_low[0] : 1'bz;\n\nassign\tdb_high[3] = alu_op1_oe ? op1_high[3] : 1'bz;\nassign\tdb_high[2] = alu_op1_oe ? op1_high[2] : 1'bz;\nassign\tdb_high[1] = alu_op1_oe ? op1_high[1] : 1'bz;\nassign\tdb_high[0] = alu_op1_oe ? op1_high[0] : 1'bz;\n\nassign\tSYNTHESIZED_WIRE_36 =  ~clk;\n\nassign\tSYNTHESIZED_WIRE_37 =  ~clk;\n\n\nalu_mux_2z\tb2v_op1_latch_mux_high(\n\t.sel_a(alu_op1_sel_bus),\n\t.sel_zero(alu_op1_sel_zero),\n\t.a(db_high),\n\t.ena(SYNTHESIZED_WIRE_20),\n\t.Q(SYNTHESIZED_WIRE_18));\n\n\nalu_mux_3z\tb2v_op1_latch_mux_low(\n\t.sel_a(alu_op1_sel_bus),\n\t.sel_b(alu_op1_sel_low),\n\t.sel_zero(alu_op1_sel_zero),\n\t.a(db_low),\n\t.b(db_high),\n\t.ena(SYNTHESIZED_WIRE_23),\n\t.Q(SYNTHESIZED_WIRE_21));\n\n\nalu_mux_3z\tb2v_op2_latch_mux_high(\n\t.sel_a(alu_op2_sel_bus),\n\t.sel_b(alu_op2_sel_lq),\n\t.sel_zero(alu_op2_sel_zero),\n\t.a(db_high),\n\t.b(db_low),\n\t.ena(SYNTHESIZED_WIRE_26),\n\t.Q(SYNTHESIZED_WIRE_24));\n\n\nalu_mux_3z\tb2v_op2_latch_mux_low(\n\t.sel_a(alu_op2_sel_bus),\n\t.sel_b(alu_op2_sel_lq),\n\t.sel_zero(alu_op2_sel_zero),\n\t.a(db_low),\n\t.b(alu_op1),\n\t.ena(SYNTHESIZED_WIRE_29),\n\t.Q(SYNTHESIZED_WIRE_27));\n\nassign\talu_parity_out = SYNTHESIZED_WIRE_30 ^ result_hi[0];\n\nassign\tSYNTHESIZED_WIRE_30 = SYNTHESIZED_WIRE_31 ^ result_hi[1];\n\nassign\tSYNTHESIZED_WIRE_31 = SYNTHESIZED_WIRE_32 ^ result_hi[2];\n\nassign\tSYNTHESIZED_WIRE_32 = alu_parity_in ^ result_hi[3];\n\n\nalu_prep_daa\tb2v_prep_daa(\n\t.high(op1_high),\n\t.low(op1_low),\n\t.low_gt_9(alu_low_gt_9),\n\t.high_gt_9(alu_high_gt_9),\n\t.high_eq_9(alu_high_eq_9));\n\nassign\tdb_low[3] = alu_shift_oe ? SYNTHESIZED_WIRE_33[3] : 1'bz;\nassign\tdb_low[2] = alu_shift_oe ? SYNTHESIZED_WIRE_33[2] : 1'bz;\nassign\tdb_low[1] = alu_shift_oe ? SYNTHESIZED_WIRE_33[1] : 1'bz;\nassign\tdb_low[0] = alu_shift_oe ? SYNTHESIZED_WIRE_33[0] : 1'bz;\n\nassign\tdb_high[3] = alu_shift_oe ? SYNTHESIZED_WIRE_34[3] : 1'bz;\nassign\tdb_high[2] = alu_shift_oe ? SYNTHESIZED_WIRE_34[2] : 1'bz;\nassign\tdb_high[1] = alu_shift_oe ? SYNTHESIZED_WIRE_34[1] : 1'bz;\nassign\tdb_high[0] = alu_shift_oe ? SYNTHESIZED_WIRE_34[0] : 1'bz;\n\nassign\talu_zero = ~(db_low[2] | db_low[1] | db_low[3] | db_high[1] | db_high[0] | db_high[2] | db_low[0] | db_high[3]);\n\nassign\talu_sf_out = db_high[3];\nassign\talu_yf_out = db_high[1];\nassign\talu_xf_out = db_low[3];\nassign\ttest_db_high = db_high;\nassign\ttest_db_low = db_low;\n\nendmodule\n"
  },
  {
    "path": "cpu/alu/alu_bit_select.bdf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"graphic\" (version \"1.4\"))\n(pin\n\t(input)\n\t(rect 24 32 200 48)\n\t(text \"INPUT\" (rect 133 0 161 10)(font \"Arial\" (font_size 6)))\n\t(text \"bsel[2..0]\" (rect 9 0 55 12)(font \"Arial\" ))\n\t(pt 176 8)\n\t(drawing\n\t\t(line (pt 92 12)(pt 117 12))\n\t\t(line (pt 92 4)(pt 117 4))\n\t\t(line (pt 121 8)(pt 176 8))\n\t\t(line (pt 92 12)(pt 92 4))\n\t\t(line (pt 117 4)(pt 121 8))\n\t\t(line (pt 117 12)(pt 121 8))\n\t)\n\t(text \"VCC\" (rect 136 7 156 17)(font \"Arial\" (font_size 6)))\n)\n(pin\n\t(output)\n\t(rect 712 136 888 152)\n\t(text \"OUTPUT\" (rect 1 0 39 10)(font \"Arial\" (font_size 6)))\n\t(text \"bs_out_low[3..0]\" (rect 90 0 170 12)(font \"Arial\" ))\n\t(pt 0 8)\n\t(drawing\n\t\t(line (pt 0 8)(pt 52 8))\n\t\t(line (pt 52 4)(pt 78 4))\n\t\t(line (pt 52 12)(pt 78 12))\n\t\t(line (pt 52 12)(pt 52 4))\n\t\t(line (pt 78 4)(pt 82 8))\n\t\t(line (pt 82 8)(pt 78 12))\n\t\t(line (pt 78 12)(pt 82 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    "content": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and other software and tools, and its AMPP partner logic \n// functions, and any output files from any of the foregoing \n// (including device programming or simulation files), and any \n// associated documentation or information are expressly subject \n// to the terms and conditions of the Altera Program License \n// Subscription Agreement, Altera MegaCore Function License \n// Agreement, or other applicable license agreement, including, \n// without limitation, that your use is for the sole purpose of \n// programming logic devices manufactured by Altera and sold by \n// Altera or its authorized distributors.  Please refer to the \n// applicable agreement for further details.\n\n// PROGRAM\t\t\"Quartus II 64-Bit\"\n// VERSION\t\t\"Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\"\n// CREATED\t\t\"Mon Oct 13 12:21:31 2014\"\n\nmodule alu_bit_select(\n\tbsel,\n\tbs_out_high,\n\tbs_out_low\n);\n\n\ninput wire\t[2:0] bsel;\noutput wire\t[3:0] bs_out_high;\noutput wire\t[3:0] bs_out_low;\n\nwire\t[3:0] bs_out_high_ALTERA_SYNTHESIZED;\nwire\t[3:0] bs_out_low_ALTERA_SYNTHESIZED;\nwire\tSYNTHESIZED_WIRE_12;\nwire\tSYNTHESIZED_WIRE_13;\nwire\tSYNTHESIZED_WIRE_14;\n\n\n\n\nassign\tbs_out_low_ALTERA_SYNTHESIZED[0] = SYNTHESIZED_WIRE_12 & SYNTHESIZED_WIRE_13 & SYNTHESIZED_WIRE_14;\n\nassign\tbs_out_low_ALTERA_SYNTHESIZED[1] = bsel[0] & SYNTHESIZED_WIRE_13 & SYNTHESIZED_WIRE_14;\n\nassign\tbs_out_low_ALTERA_SYNTHESIZED[2] = SYNTHESIZED_WIRE_12 & bsel[1] & SYNTHESIZED_WIRE_14;\n\nassign\tbs_out_low_ALTERA_SYNTHESIZED[3] = bsel[0] & bsel[1] & SYNTHESIZED_WIRE_14;\n\nassign\tbs_out_high_ALTERA_SYNTHESIZED[0] = SYNTHESIZED_WIRE_12 & SYNTHESIZED_WIRE_13 & bsel[2];\n\nassign\tbs_out_high_ALTERA_SYNTHESIZED[1] = bsel[0] & SYNTHESIZED_WIRE_13 & bsel[2];\n\nassign\tbs_out_high_ALTERA_SYNTHESIZED[2] = SYNTHESIZED_WIRE_12 & bsel[1] & bsel[2];\n\nassign\tbs_out_high_ALTERA_SYNTHESIZED[3] = bsel[0] & bsel[1] & bsel[2];\n\nassign\tSYNTHESIZED_WIRE_12 =  ~bsel[0];\n\nassign\tSYNTHESIZED_WIRE_13 =  ~bsel[1];\n\nassign\tSYNTHESIZED_WIRE_14 =  ~bsel[2];\n\nassign\tbs_out_high = bs_out_high_ALTERA_SYNTHESIZED;\nassign\tbs_out_low = bs_out_low_ALTERA_SYNTHESIZED;\n\nendmodule\n"
  },
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    "path": "cpu/alu/alu_control.bdf",
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    "path": "cpu/alu/alu_control.v",
    "content": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and other software and tools, and its AMPP partner logic \n// functions, and any output files from any of the foregoing \n// (including device programming or simulation files), and any \n// associated documentation or information are expressly subject \n// to the terms and conditions of the Altera Program License \n// Subscription Agreement, Altera MegaCore Function License \n// Agreement, or other applicable license agreement, including, \n// without limitation, that your use is for the sole purpose of \n// programming logic devices manufactured by Altera and sold by \n// Altera or its authorized distributors.  Please refer to the \n// applicable agreement for further details.\n\n// PROGRAM\t\t\"Quartus II 64-Bit\"\n// VERSION\t\t\"Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\"\n// CREATED\t\t\"Tue Oct 21 20:41:52 2014\"\n\nmodule alu_control(\n\talu_shift_db0,\n\talu_shift_db7,\n\tctl_shift_en,\n\talu_low_gt_9,\n\talu_high_gt_9,\n\talu_high_eq_9,\n\tctl_daa_oe,\n\tctl_alu_op_low,\n\talu_parity_out,\n\tflags_cf,\n\tflags_zf,\n\tflags_pf,\n\tflags_sf,\n\tctl_cond_short,\n\talu_vf_out,\n\tiff2,\n\tctl_alu_core_hf,\n\tctl_eval_cond,\n\trepeat_en,\n\tflags_cf_latch,\n\tflags_hf2,\n\tflags_hf,\n\tctl_66_oe,\n\tclk,\n\tctl_pf_sel,\n\top543,\n\talu_shift_in,\n\talu_shift_right,\n\talu_shift_left,\n\tshift_cf_out,\n\talu_parity_in,\n\tflags_cond_true,\n\tdaa_cf_out,\n\tpf_sel,\n\talu_op_low,\n\talu_core_cf_in,\n\tdb\n);\n\n\ninput wire\talu_shift_db0;\ninput wire\talu_shift_db7;\ninput wire\tctl_shift_en;\ninput wire\talu_low_gt_9;\ninput wire\talu_high_gt_9;\ninput wire\talu_high_eq_9;\ninput wire\tctl_daa_oe;\ninput wire\tctl_alu_op_low;\ninput wire\talu_parity_out;\ninput wire\tflags_cf;\ninput wire\tflags_zf;\ninput wire\tflags_pf;\ninput wire\tflags_sf;\ninput wire\tctl_cond_short;\ninput wire\talu_vf_out;\ninput wire\tiff2;\ninput wire\tctl_alu_core_hf;\ninput wire\tctl_eval_cond;\ninput wire\trepeat_en;\ninput wire\tflags_cf_latch;\ninput wire\tflags_hf2;\ninput wire\tflags_hf;\ninput wire\tctl_66_oe;\ninput wire\tclk;\ninput wire\t[1:0] ctl_pf_sel;\ninput wire\t[2:0] op543;\noutput wire\talu_shift_in;\noutput wire\talu_shift_right;\noutput wire\talu_shift_left;\noutput wire\tshift_cf_out;\noutput wire\talu_parity_in;\noutput reg\tflags_cond_true;\noutput wire\tdaa_cf_out;\noutput wire\tpf_sel;\noutput wire\talu_op_low;\noutput wire\talu_core_cf_in;\noutput wire\t[7:0] db;\n\nwire\tcondition;\nwire\t[7:0] out;\nwire\t[1:0] sel;\nwire\tSYNTHESIZED_WIRE_0;\nwire\tSYNTHESIZED_WIRE_1;\nwire\tSYNTHESIZED_WIRE_2;\nreg\tDFFE_latch_pf_tmp;\nwire\tSYNTHESIZED_WIRE_20;\nwire\tSYNTHESIZED_WIRE_21;\nwire\tSYNTHESIZED_WIRE_7;\nwire\tSYNTHESIZED_WIRE_8;\nwire\tSYNTHESIZED_WIRE_9;\nwire\tSYNTHESIZED_WIRE_10;\nwire\tSYNTHESIZED_WIRE_11;\nwire\tSYNTHESIZED_WIRE_12;\nwire\tSYNTHESIZED_WIRE_13;\nwire\tSYNTHESIZED_WIRE_14;\nwire\tSYNTHESIZED_WIRE_15;\nwire\tSYNTHESIZED_WIRE_16;\nwire\tSYNTHESIZED_WIRE_22;\nwire\tSYNTHESIZED_WIRE_18;\n\nassign\talu_op_low = ctl_alu_op_low;\nassign\tdaa_cf_out = SYNTHESIZED_WIRE_21;\nassign\tSYNTHESIZED_WIRE_22 = 0;\nassign\tSYNTHESIZED_WIRE_18 = 1;\n\n\n\nassign\tcondition = SYNTHESIZED_WIRE_0 ^ SYNTHESIZED_WIRE_1;\n\n\n\nassign\tdb[7] = SYNTHESIZED_WIRE_2 ? out[7] : 1'bz;\nassign\tdb[6] = SYNTHESIZED_WIRE_2 ? out[6] : 1'bz;\nassign\tdb[5] = SYNTHESIZED_WIRE_2 ? out[5] : 1'bz;\nassign\tdb[4] = SYNTHESIZED_WIRE_2 ? out[4] : 1'bz;\nassign\tdb[3] = SYNTHESIZED_WIRE_2 ? out[3] : 1'bz;\nassign\tdb[2] = SYNTHESIZED_WIRE_2 ? out[2] : 1'bz;\nassign\tdb[1] = SYNTHESIZED_WIRE_2 ? out[1] : 1'bz;\nassign\tdb[0] = SYNTHESIZED_WIRE_2 ? out[0] : 1'bz;\n\nassign\talu_shift_right = ctl_shift_en & op543[0];\n\nassign\talu_parity_in = ctl_alu_op_low | DFFE_latch_pf_tmp;\n\nassign\tSYNTHESIZED_WIRE_2 = ctl_66_oe | ctl_daa_oe;\n\nassign\tsel[0] = op543[1];\n\n\nassign\tout[1] = SYNTHESIZED_WIRE_20;\n\n\nassign\tout[2] = SYNTHESIZED_WIRE_20;\n\n\nassign\tout[5] = SYNTHESIZED_WIRE_21;\n\n\nassign\tout[6] = SYNTHESIZED_WIRE_21;\n\n\nassign\talu_shift_left = ctl_shift_en & SYNTHESIZED_WIRE_7;\n\nassign\tSYNTHESIZED_WIRE_21 = ctl_66_oe | alu_high_gt_9 | flags_cf_latch | SYNTHESIZED_WIRE_8;\n\nassign\tSYNTHESIZED_WIRE_9 = flags_hf2 | alu_low_gt_9;\n\nassign\tSYNTHESIZED_WIRE_8 = alu_low_gt_9 & alu_high_eq_9;\n\nassign\tSYNTHESIZED_WIRE_20 = SYNTHESIZED_WIRE_9 | ctl_66_oe;\n\nassign\tSYNTHESIZED_WIRE_0 =  ~op543[0];\n\nassign\tsel[1] = op543[2] & SYNTHESIZED_WIRE_10;\n\nassign\tSYNTHESIZED_WIRE_12 = alu_shift_db0 & op543[0];\n\nassign\tSYNTHESIZED_WIRE_13 = alu_shift_db7 & SYNTHESIZED_WIRE_11;\n\nassign\tshift_cf_out = SYNTHESIZED_WIRE_12 | SYNTHESIZED_WIRE_13;\n\nassign\tSYNTHESIZED_WIRE_16 = ctl_alu_core_hf & flags_hf;\n\nassign\tSYNTHESIZED_WIRE_15 = SYNTHESIZED_WIRE_14 & flags_cf;\n\nassign\talu_core_cf_in = SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16;\n\nassign\tSYNTHESIZED_WIRE_14 =  ~ctl_alu_core_hf;\n\n\nalways@(posedge clk)\nbegin\nif (ctl_eval_cond)\n\tbegin\n\tflags_cond_true <= condition;\n\tend\nend\n\n\nalu_mux_4\tb2v_inst_cond_mux(\n\t.in0(flags_zf),\n\t.in1(flags_cf),\n\t.in2(flags_pf),\n\t.in3(flags_sf),\n\t.sel(sel),\n\t.out(SYNTHESIZED_WIRE_1));\n\n\nalu_mux_4\tb2v_inst_pf_sel(\n\t.in0(alu_parity_out),\n\t.in1(alu_vf_out),\n\t.in2(iff2),\n\t.in3(repeat_en),\n\t.sel(ctl_pf_sel),\n\t.out(pf_sel));\n\n\nalu_mux_8\tb2v_inst_shift_mux(\n\t.in0(alu_shift_db7),\n\t.in1(alu_shift_db0),\n\t.in2(flags_cf_latch),\n\t.in3(flags_cf_latch),\n\t.in4(SYNTHESIZED_WIRE_22),\n\t.in5(alu_shift_db7),\n\t.in6(SYNTHESIZED_WIRE_18),\n\t.in7(SYNTHESIZED_WIRE_22),\n\t.sel(op543),\n\t.out(alu_shift_in));\n\n\nalways@(posedge clk)\nbegin\nif (ctl_alu_op_low)\n\tbegin\n\tDFFE_latch_pf_tmp <= alu_parity_out;\n\tend\nend\n\nassign\tSYNTHESIZED_WIRE_7 =  ~op543[0];\n\nassign\tSYNTHESIZED_WIRE_11 =  ~op543[0];\n\nassign\tSYNTHESIZED_WIRE_10 =  ~ctl_cond_short;\n\n\nassign\tout[3] = 0;\nassign\tout[7] = 0;\nassign\tout[0] = 0;\nassign\tout[4] = 0;\n\nendmodule\n"
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    "path": "cpu/alu/alu_core.bdf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  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    "path": "cpu/alu/alu_core.bsf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"symbol\" (version \"1.2\"))\n(symbol\n\t(rect 16 16 176 176)\n\t(text \"alu_core\" (rect 5 0 54 14)(font \"Arial\" (font_size 8)))\n\t(text \"inst\" (rect 8 144 25 156)(font \"Arial\" ))\n\t(port\n\t\t(pt 0 32)\n\t\t(input)\n\t\t(text \"op1[3..0]\" (rect 0 0 49 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"op1[3..0]\" (rect 21 27 70 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 32)(pt 16 32)(line_width 3))\n\t)\n\t(port\n\t\t(pt 0 48)\n\t\t(input)\n\t\t(text \"op2[3..0]\" (rect 0 0 49 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"op2[3..0]\" (rect 21 43 70 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 48)(pt 16 48)(line_width 3))\n\t)\n\t(port\n\t\t(pt 0 64)\n\t\t(input)\n\t\t(text \"cy_in\" (rect 0 0 30 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"cy_in\" (rect 21 59 51 73)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 64)(pt 16 64))\n\t)\n\t(port\n\t\t(pt 0 80)\n\t\t(input)\n\t\t(text \"S\" (rect 0 0 8 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"S\" (rect 21 75 29 89)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 80)(pt 16 80))\n\t)\n\t(port\n\t\t(pt 0 96)\n\t\t(input)\n\t\t(text \"V\" (rect 0 0 9 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"V\" (rect 21 91 30 105)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 96)(pt 16 96))\n\t)\n\t(port\n\t\t(pt 0 112)\n\t\t(input)\n\t\t(text \"R\" (rect 0 0 8 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"R\" (rect 21 107 29 121)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 112)(pt 16 112))\n\t)\n\t(port\n\t\t(pt 160 32)\n\t\t(output)\n\t\t(text \"result[3..0]\" (rect 0 0 60 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"result[3..0]\" (rect 79 27 139 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 160 32)(pt 144 32)(line_width 3))\n\t)\n\t(port\n\t\t(pt 160 48)\n\t\t(output)\n\t\t(text \"cy_out\" (rect 0 0 38 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"cy_out\" (rect 101 43 139 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 160 48)(pt 144 48))\n\t)\n\t(port\n\t\t(pt 160 64)\n\t\t(output)\n\t\t(text \"vf_out\" (rect 0 0 36 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"vf_out\" (rect 103 59 139 73)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 160 64)(pt 144 64))\n\t)\n\t(drawing\n\t\t(rectangle (rect 16 16 144 144))\n\t)\n)\n"
  },
  {
    "path": "cpu/alu/alu_core.v",
    "content": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and other software and tools, and its AMPP partner logic \n// functions, and any output files from any of the foregoing \n// (including device programming or simulation files), and any \n// associated documentation or information are expressly subject \n// to the terms and conditions of the Altera Program License \n// Subscription Agreement, Altera MegaCore Function License \n// Agreement, or other applicable license agreement, including, \n// without limitation, that your use is for the sole purpose of \n// programming logic devices manufactured by Altera and sold by \n// Altera or its authorized distributors.  Please refer to the \n// applicable agreement for further details.\n\n// PROGRAM\t\t\"Quartus II 64-Bit\"\n// VERSION\t\t\"Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\"\n// CREATED\t\t\"Mon Oct 13 12:17:04 2014\"\n\nmodule alu_core(\n\tcy_in,\n\tS,\n\tV,\n\tR,\n\top1,\n\top2,\n\tcy_out,\n\tvf_out,\n\tresult\n);\n\n\ninput wire\tcy_in;\ninput wire\tS;\ninput wire\tV;\ninput wire\tR;\ninput wire\t[3:0] op1;\ninput wire\t[3:0] op2;\noutput wire\tcy_out;\noutput wire\tvf_out;\noutput wire\t[3:0] result;\n\nwire\t[3:0] result_ALTERA_SYNTHESIZED;\nwire\tSYNTHESIZED_WIRE_0;\nwire\tSYNTHESIZED_WIRE_1;\nwire\tSYNTHESIZED_WIRE_5;\nwire\tSYNTHESIZED_WIRE_3;\n\nassign\tcy_out = SYNTHESIZED_WIRE_3;\n\n\n\n\nalu_slice\tb2v_alu_slice_bit_0(\n\t.cy_in(cy_in),\n\t.op1(op1[0]),\n\t.op2(op2[0]),\n\t.S(S),\n\t.V(V),\n\t.R(R),\n\t.result(result_ALTERA_SYNTHESIZED[0]),\n\t.cy_out(SYNTHESIZED_WIRE_0));\n\n\nalu_slice\tb2v_alu_slice_bit_1(\n\t.cy_in(SYNTHESIZED_WIRE_0),\n\t.op1(op1[1]),\n\t.op2(op2[1]),\n\t.S(S),\n\t.V(V),\n\t.R(R),\n\t.result(result_ALTERA_SYNTHESIZED[1]),\n\t.cy_out(SYNTHESIZED_WIRE_1));\n\n\nalu_slice\tb2v_alu_slice_bit_2(\n\t.cy_in(SYNTHESIZED_WIRE_1),\n\t.op1(op1[2]),\n\t.op2(op2[2]),\n\t.S(S),\n\t.V(V),\n\t.R(R),\n\t.result(result_ALTERA_SYNTHESIZED[2]),\n\t.cy_out(SYNTHESIZED_WIRE_5));\n\n\nalu_slice\tb2v_alu_slice_bit_3(\n\t.cy_in(SYNTHESIZED_WIRE_5),\n\t.op1(op1[3]),\n\t.op2(op2[3]),\n\t.S(S),\n\t.V(V),\n\t.R(R),\n\t.result(result_ALTERA_SYNTHESIZED[3]),\n\t.cy_out(SYNTHESIZED_WIRE_3));\n\nassign\tvf_out = SYNTHESIZED_WIRE_3 ^ SYNTHESIZED_WIRE_5;\n\nassign\tresult = result_ALTERA_SYNTHESIZED;\n\nendmodule\n"
  },
  {
    "path": "cpu/alu/alu_flags.bdf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  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1016)\n\t(pt 496 1016)\n)\n(connector\n\t(pt 368 1208)\n\t(pt 384 1208)\n)\n(connector\n\t(pt 384 1208)\n\t(pt 384 1224)\n)\n(connector\n\t(pt 368 1256)\n\t(pt 384 1256)\n)\n(connector\n\t(pt 384 1256)\n\t(pt 384 1240)\n)\n(connector\n\t(pt 384 1240)\n\t(pt 400 1240)\n)\n(connector\n\t(pt 384 1224)\n\t(pt 400 1224)\n)\n(connector\n\t(pt 272 1216)\n\t(pt 304 1216)\n)\n(connector\n\t(pt 304 1200)\n\t(pt 288 1200)\n)\n(connector\n\t(pt 304 1248)\n\t(pt 256 1248)\n)\n(connector\n\t(pt 304 592)\n\t(pt 232 592)\n)\n(connector\n\t(pt 288 1200)\n\t(pt 288 1176)\n)\n(connector\n\t(pt 288 1176)\n\t(pt 816 1176)\n)\n(connector\n\t(pt 816 1176)\n\t(pt 816 1240)\n)\n(connector\n\t(pt 304 1328)\n\t(pt 304 1360)\n)\n(connector\n\t(pt 320 1328)\n\t(pt 304 1328)\n)\n(connector\n\t(pt 704 1240)\n\t(pt 704 1352)\n)\n(connector\n\t(pt 704 1352)\n\t(pt 936 1352)\n)\n(connector\n\t(pt 936 1416)\n\t(pt 936 1352)\n)\n(connector\n\t(pt 744 1240)\n\t(pt 704 1240)\n)\n(connector\n\t(pt 728 1400)\n\t(pt 760 1400)\n)\n(connector\n\t(pt 824 1408)\n\t(pt 856 1408)\n)\n(connector\n\t(pt 304 1120)\n\t(pt 256 1120)\n)\n(connector\n\t(pt 384 1064)\n\t(pt 384 1080)\n)\n(connector\n\t(pt 384 1080)\n\t(pt 400 1080)\n)\n(connector\n\t(pt 368 1112)\n\t(pt 384 1112)\n)\n(connector\n\t(pt 384 1112)\n\t(pt 384 1096)\n)\n(connector\n\t(pt 384 1096)\n\t(pt 400 1096)\n)\n(connector\n\t(pt 400 1088)\n\t(pt 200 1088)\n)\n(connector\n\t(pt 200 1136)\n\t(pt 408 1136)\n)\n(connector\n\t(pt 456 1136)\n\t(pt 480 1136)\n)\n(connector\n\t(pt 480 1104)\n\t(pt 496 1104)\n)\n(connector\n\t(pt 480 1136)\n\t(pt 480 1104)\n)\n(connector\n\t(pt 464 1088)\n\t(pt 496 1088)\n)\n(connector\n\t(pt 560 1096)\n\t(pt 624 1096)\n)\n(connector\n\t(pt 368 104)\n\t(pt 384 104)\n)\n(connector\n\t(pt 384 104)\n\t(pt 384 120)\n)\n(connector\n\t(pt 368 152)\n\t(pt 384 152)\n)\n(connector\n\t(pt 384 152)\n\t(pt 384 136)\n)\n(connector\n\t(pt 384 120)\n\t(pt 400 120)\n)\n(connector\n\t(pt 384 136)\n\t(pt 400 136)\n)\n(connector\n\t(pt 304 96)\n\t(pt 288 96)\n)\n(connector\n\t(pt 304 112)\n\t(pt 272 112)\n)\n(connector\n\t(pt 304 160)\n\t(pt 256 160)\n)\n(connector\n\t(pt 200 56)\n\t(pt 272 56)\n)\n(connector\n\t(pt 200 72)\n\t(pt 256 72)\n)\n(connector\n\t(pt 288 96)\n\t(pt 288 72)\n)\n(connector\n\t(pt 288 72)\n\t(pt 816 72)\n)\n(connector\n\t(pt 200 192)\n\t(pt 600 192)\n)\n(connector\n\t(pt 464 128)\n\t(pt 624 128)\n)\n(connector\n\t(pt 704 168)\n\t(pt 912 168)\n)\n(connector\n\t(pt 200 40)\n\t(pt 728 40)\n)\n(connector\n\t(pt 872 40)\n\t(pt 912 40)\n\t(bus)\n)\n(connector\n\t(pt 304 1104)\n\t(pt 216 1104)\n)\n(connector\n\t(pt 216 1104)\n\t(pt 216 144)\n)\n(connector\n\t(pt 384 272)\n\t(pt 400 272)\n)\n(connector\n\t(pt 272 264)\n\t(pt 304 264)\n)\n(connector\n\t(pt 288 248)\n\t(pt 304 248)\n)\n(connector\n\t(pt 288 208)\n\t(pt 288 248)\n)\n(connector\n\t(pt 368 256)\n\t(pt 400 256)\n)\n(connector\n\t(pt 384 304)\n\t(pt 368 304)\n)\n(connector\n\t(pt 256 312)\n\t(pt 304 312)\n)\n(connector\n\t(pt 384 272)\n\t(pt 384 304)\n)\n(connector\n\t(pt 200 296)\n\t(pt 304 296)\n)\n(connector\n\t(pt 464 264)\n\t(pt 496 264)\n)\n(connector\n\t(pt 808 568)\n\t(pt 816 568)\n)\n(connector\n\t(text \"db[4]\" (rect 839 552 863 564)(font \"Arial\" ))\n\t(pt 816 568)\n\t(pt 872 568)\n)\n(connector\n\t(pt 816 640)\n\t(pt 840 640)\n)\n(connector\n\t(pt 840 640)\n\t(pt 912 640)\n)\n(connector\n\t(pt 792 1240)\n\t(pt 816 1240)\n)\n(connector\n\t(text \"db[0]\" (rect 836 1224 860 1236)(font \"Arial\" ))\n\t(pt 816 1240)\n\t(pt 872 1240)\n)\n(connector\n\t(pt 200 1264)\n\t(pt 232 1264)\n)\n(connector\n\t(pt 232 1264)\n\t(pt 304 1264)\n)\n(connector\n\t(pt 920 1416)\n\t(pt 936 1416)\n)\n(connector\n\t(pt 936 1416)\n\t(pt 952 1416)\n)\n(connector\n\t(pt 272 936)\n\t(pt 272 1072)\n)\n(connector\n\t(pt 272 1072)\n\t(pt 272 1216)\n)\n(connector\n\t(pt 200 144)\n\t(pt 216 144)\n)\n(connector\n\t(pt 216 144)\n\t(pt 304 144)\n)\n(connector\n\t(pt 256 984)\n\t(pt 256 1120)\n)\n(connector\n\t(pt 256 1120)\n\t(pt 256 1248)\n)\n(connector\n\t(pt 272 56)\n\t(pt 272 112)\n)\n(connector\n\t(pt 272 112)\n\t(pt 272 264)\n)\n(connector\n\t(pt 272 264)\n\t(pt 272 424)\n)\n(connector\n\t(pt 272 424)\n\t(pt 272 560)\n)\n(connector\n\t(pt 272 560)\n\t(pt 272 800)\n)\n(connector\n\t(pt 272 800)\n\t(pt 272 936)\n)\n(connector\n\t(pt 256 72)\n\t(pt 256 160)\n)\n(connector\n\t(pt 256 160)\n\t(pt 256 312)\n)\n(connector\n\t(pt 256 312)\n\t(pt 256 472)\n)\n(connector\n\t(pt 256 472)\n\t(pt 256 608)\n)\n(connector\n\t(pt 256 608)\n\t(pt 256 848)\n)\n(connector\n\t(pt 256 848)\n\t(pt 256 984)\n)\n(connector\n\t(pt 784 536)\n\t(pt 784 552)\n)\n(connector\n\t(pt 496 280)\n\t(pt 480 280)\n)\n(connector\n\t(pt 200 344)\n\t(pt 312 344)\n)\n(connector\n\t(pt 480 280)\n\t(pt 480 336)\n)\n(connector\n\t(pt 480 336)\n\t(pt 464 336)\n)\n(connector\n\t(pt 360 344)\n\t(pt 400 344)\n)\n(connector\n\t(pt 384 368)\n\t(pt 384 328)\n)\n(connector\n\t(pt 384 328)\n\t(pt 400 328)\n)\n(connector\n\t(pt 728 104)\n\t(pt 768 104)\n)\n(connector\n\t(pt 768 104)\n\t(pt 768 112)\n)\n(connector\n\t(pt 816 72)\n\t(pt 816 128)\n)\n(connector\n\t(pt 704 128)\n\t(pt 704 168)\n)\n(connector\n\t(pt 688 128)\n\t(pt 704 128)\n)\n(connector\n\t(pt 704 128)\n\t(pt 744 128)\n)\n(connector\n\t(pt 792 128)\n\t(pt 816 128)\n)\n(connector\n\t(text \"db[7]\" (rect 838 112 862 124)(font \"Arial\" ))\n\t(pt 816 128)\n\t(pt 872 128)\n)\n(connector\n\t(pt 624 160)\n\t(pt 600 160)\n)\n(connector\n\t(pt 768 248)\n\t(pt 768 256)\n)\n(connector\n\t(pt 728 248)\n\t(pt 768 248)\n)\n(connector\n\t(pt 704 368)\n\t(pt 704 272)\n)\n(connector\n\t(pt 288 208)\n\t(pt 816 208)\n)\n(connector\n\t(pt 816 208)\n\t(pt 816 272)\n)\n(connector\n\t(pt 384 368)\n\t(pt 704 368)\n)\n(connector\n\t(pt 704 368)\n\t(pt 912 368)\n)\n(connector\n\t(pt 792 272)\n\t(pt 816 272)\n)\n(connector\n\t(text \"db[6]\" (rect 838 256 862 268)(font \"Arial\" ))\n\t(pt 816 272)\n\t(pt 872 272)\n)\n(connector\n\t(pt 688 272)\n\t(pt 704 272)\n)\n(connector\n\t(pt 704 272)\n\t(pt 744 272)\n)\n(connector\n\t(pt 728 40)\n\t(pt 728 104)\n)\n(connector\n\t(pt 728 104)\n\t(pt 728 248)\n)\n(connector\n\t(pt 872 40)\n\t(pt 872 128)\n\t(bus)\n)\n(connector\n\t(pt 872 128)\n\t(pt 872 272)\n\t(bus)\n)\n(connector\n\t(pt 600 160)\n\t(pt 600 192)\n)\n(connector\n\t(pt 560 272)\n\t(pt 624 272)\n)\n(connector\n\t(pt 624 304)\n\t(pt 600 304)\n)\n(connector\n\t(pt 600 192)\n\t(pt 600 304)\n)\n(connector\n\t(pt 728 416)\n\t(pt 768 416)\n)\n(connector\n\t(pt 768 416)\n\t(pt 768 424)\n)\n(connector\n\t(pt 728 248)\n\t(pt 728 416)\n)\n(connector\n\t(pt 728 416)\n\t(pt 728 536)\n)\n(connector\n\t(pt 816 384)\n\t(pt 816 440)\n)\n(connector\n\t(text \"flags_yf\" (rect 700 424 742 436)(font \"Arial\" ))\n\t(pt 688 440)\n\t(pt 744 440)\n)\n(connector\n\t(pt 872 272)\n\t(pt 872 440)\n\t(bus)\n)\n(connector\n\t(pt 872 440)\n\t(pt 872 568)\n\t(bus)\n)\n(connector\n\t(pt 792 440)\n\t(pt 816 440)\n)\n(connector\n\t(text \"db[5]\" (rect 841 424 865 436)(font \"Arial\" ))\n\t(pt 816 440)\n\t(pt 872 440)\n)\n(connector\n\t(pt 496 472)\n\t(pt 624 472)\n)\n(connector\n\t(pt 624 728)\n\t(pt 200 728)\n)\n(connector\n\t(pt 624 696)\n\t(pt 520 696)\n)\n(connector\n\t(pt 496 848)\n\t(pt 624 848)\n)\n(connector\n\t(pt 496 472)\n\t(pt 496 504)\n)\n(connector\n\t(pt 496 504)\n\t(pt 496 848)\n)\n(connector\n\t(pt 728 792)\n\t(pt 768 792)\n)\n(connector\n\t(pt 768 792)\n\t(pt 768 800)\n)\n(connector\n\t(pt 728 536)\n\t(pt 728 792)\n)\n(connector\n\t(pt 816 760)\n\t(pt 816 816)\n)\n(connector\n\t(text \"flags_xf\" (rect 696 800 737 812)(font \"Arial\" ))\n\t(pt 688 816)\n\t(pt 744 816)\n)\n(connector\n\t(pt 872 568)\n\t(pt 872 816)\n\t(bus)\n)\n(connector\n\t(pt 792 816)\n\t(pt 816 816)\n)\n(connector\n\t(text \"db[3]\" (rect 838 800 862 812)(font \"Arial\" ))\n\t(pt 816 816)\n\t(pt 872 816)\n)\n(connector\n\t(pt 496 1016)\n\t(pt 496 984)\n)\n(connector\n\t(pt 496 984)\n\t(pt 624 984)\n)\n(connector\n\t(pt 728 928)\n\t(pt 768 928)\n)\n(connector\n\t(pt 768 928)\n\t(pt 768 936)\n)\n(connector\n\t(pt 728 792)\n\t(pt 728 928)\n)\n(connector\n\t(pt 816 896)\n\t(pt 816 952)\n)\n(connector\n\t(pt 704 952)\n\t(pt 704 992)\n)\n(connector\n\t(pt 688 952)\n\t(pt 704 952)\n)\n(connector\n\t(pt 704 952)\n\t(pt 744 952)\n)\n(connector\n\t(pt 872 816)\n\t(pt 872 952)\n\t(bus)\n)\n(connector\n\t(pt 792 952)\n\t(pt 816 952)\n)\n(connector\n\t(text \"db[2]\" (rect 837 936 861 948)(font \"Arial\" ))\n\t(pt 816 952)\n\t(pt 872 952)\n)\n(connector\n\t(pt 704 1096)\n\t(pt 704 1144)\n)\n(connector\n\t(pt 688 1096)\n\t(pt 704 1096)\n)\n(connector\n\t(pt 704 1096)\n\t(pt 744 1096)\n)\n(connector\n\t(pt 816 1032)\n\t(pt 816 1096)\n)\n(connector\n\t(pt 872 952)\n\t(pt 872 1096)\n\t(bus)\n)\n(connector\n\t(pt 872 1096)\n\t(pt 872 1240)\n\t(bus)\n)\n(connector\n\t(pt 792 1096)\n\t(pt 816 1096)\n)\n(connector\n\t(text \"db[1]\" (rect 836 1080 860 1092)(font \"Arial\" ))\n\t(pt 816 1096)\n\t(pt 872 1096)\n)\n(connector\n\t(pt 728 1072)\n\t(pt 768 1072)\n)\n(connector\n\t(pt 768 1080)\n\t(pt 768 1072)\n)\n(connector\n\t(pt 200 1152)\n\t(pt 592 1152)\n)\n(connector\n\t(pt 592 1152)\n\t(pt 592 1128)\n)\n(connector\n\t(pt 624 1128)\n\t(pt 592 1128)\n)\n(connector\n\t(pt 200 632)\n\t(pt 592 632)\n)\n(connector\n\t(pt 232 1432)\n\t(pt 288 1432)\n)\n(connector\n\t(pt 232 1480)\n\t(pt 288 1480)\n)\n(connector\n\t(pt 232 1488)\n\t(pt 232 1480)\n)\n(connector\n\t(pt 232 592)\n\t(pt 232 1264)\n)\n(connector\n\t(pt 232 1264)\n\t(pt 232 1432)\n)\n(connector\n\t(pt 200 1464)\n\t(pt 288 1464)\n)\n(connector\n\t(pt 200 1448)\n\t(pt 288 1448)\n)\n(connector\n\t(text \"clk\" (rect 583 128 597 140)(font \"Arial\" ))\n\t(pt 624 144)\n\t(pt 576 144)\n)\n(connector\n\t(text \"clk\" (rect 582 272 596 284)(font \"Arial\" ))\n\t(pt 624 288)\n\t(pt 576 288)\n)\n(connector\n\t(text \"clk\" (rect 583 440 597 452)(font \"Arial\" ))\n\t(pt 624 456)\n\t(pt 576 456)\n)\n(connector\n\t(text \"clk\" (rect 584 696 598 708)(font \"Arial\" ))\n\t(pt 624 712)\n\t(pt 576 712)\n)\n(connector\n\t(text \"clk\" (rect 583 816 597 828)(font \"Arial\" ))\n\t(pt 624 832)\n\t(pt 576 832)\n)\n(connector\n\t(text \"clk\" (rect 583 952 597 964)(font \"Arial\" ))\n\t(pt 624 968)\n\t(pt 576 968)\n)\n(connector\n\t(text \"clk\" (rect 584 1096 598 1108)(font \"Arial\" ))\n\t(pt 624 1112)\n\t(pt 576 1112)\n)\n(connector\n\t(pt 728 1216)\n\t(pt 768 1216)\n)\n(connector\n\t(pt 768 1224)\n\t(pt 768 1216)\n)\n(connector\n\t(pt 728 928)\n\t(pt 728 1072)\n)\n(connector\n\t(pt 728 1072)\n\t(pt 728 1216)\n)\n(connector\n\t(pt 384 600)\n\t(pt 384 584)\n)\n(connector\n\t(pt 384 584)\n\t(pt 400 584)\n)\n(connector\n\t(pt 368 552)\n\t(pt 384 552)\n)\n(connector\n\t(pt 384 552)\n\t(pt 384 568)\n)\n(connector\n\t(pt 400 568)\n\t(pt 384 568)\n)\n(connector\n\t(pt 704 632)\n\t(pt 704 576)\n)\n(connector\n\t(pt 704 576)\n\t(pt 688 576)\n)\n(connector\n\t(pt 592 608)\n\t(pt 624 608)\n)\n(connector\n\t(pt 592 632)\n\t(pt 592 608)\n)\n(connector\n\t(text \"clk\" (rect 583 576 597 588)(font \"Arial\" ))\n\t(pt 624 592)\n\t(pt 576 592)\n)\n(connector\n\t(pt 520 576)\n\t(pt 520 696)\n)\n(connector\n\t(pt 464 576)\n\t(pt 520 576)\n)\n(connector\n\t(pt 520 576)\n\t(pt 624 576)\n)\n(connector\n\t(pt 200 1576)\n\t(pt 744 1576)\n)\n(connector\n\t(pt 744 1416)\n\t(pt 744 1576)\n)\n(connector\n\t(pt 200 1600)\n\t(pt 840 1600)\n)\n(connector\n\t(pt 840 1424)\n\t(pt 840 1600)\n)\n(connector\n\t(pt 760 1416)\n\t(pt 744 1416)\n)\n(connector\n\t(pt 856 1424)\n\t(pt 840 1424)\n)\n(connector\n\t(pt 248 1392)\n\t(pt 248 1416)\n)\n(connector\n\t(text \"sel[0]\" (rect 206 1376 233 1388)(font \"Arial\" ))\n\t(pt 200 1392)\n\t(pt 248 1392)\n)\n(connector\n\t(text \"sel[1]\" (rect 204 1400 231 1412)(font \"Arial\" ))\n\t(pt 200 1416)\n\t(pt 248 1416)\n)\n(connector\n\t(text \"sel[1..0]\" (rect 251 1400 291 1412)(font \"Arial\" ))\n\t(pt 288 1416)\n\t(pt 248 1416)\n\t(bus)\n)\n(connector\n\t(pt 632 1400)\n\t(pt 616 1400)\n)\n(connector\n\t(pt 616 1288)\n\t(pt 616 1400)\n)\n(connector\n\t(pt 200 1552)\n\t(pt 616 1552)\n)\n(connector\n\t(pt 616 1432)\n\t(pt 616 1552)\n)\n(connector\n\t(pt 632 1432)\n\t(pt 616 1432)\n)\n(connector\n\t(pt 600 1288)\n\t(pt 616 1288)\n)\n(connector\n\t(pt 616 1288)\n\t(pt 912 1288)\n)\n(connector\n\t(pt 632 1416)\n\t(pt 600 1416)\n)\n(connector\n\t(pt 400 1416)\n\t(pt 536 1416)\n)\n(connector\n\t(pt 200 1360)\n\t(pt 304 1360)\n)\n(connector\n\t(pt 304 1360)\n\t(pt 408 1360)\n)\n(connector\n\t(pt 536 1304)\n\t(pt 520 1304)\n)\n(connector\n\t(pt 520 1432)\n\t(pt 536 1432)\n)\n(connector\n\t(pt 200 1528)\n\t(pt 520 1528)\n)\n(connector\n\t(pt 520 1304)\n\t(pt 520 1432)\n)\n(connector\n\t(pt 520 1432)\n\t(pt 520 1528)\n)\n(connector\n\t(pt 464 1232)\n\t(pt 520 1232)\n)\n(connector\n\t(pt 520 1232)\n\t(pt 520 1288)\n)\n(connector\n\t(pt 536 1288)\n\t(pt 520 1288)\n)\n(connector\n\t(pt 536 1448)\n\t(pt 504 1448)\n)\n(connector\n\t(pt 408 1360)\n\t(pt 408 1440)\n)\n(connector\n\t(pt 408 1440)\n\t(pt 440 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10)))\n(text \"Zero Flag\" (rect 512 192 575 208)(font \"Arial\" (font_size 10)))\n(text \"N Flag\" (rect 512 1040 556 1056)(font \"Arial\" (font_size 10)))\n(text \"Sign Flag\" (rect 512 80 576 96)(font \"Arial\" (font_size 10)))\n(text \"Y Flag\" (rect 512 392 556 408)(font \"Arial\" (font_size 10)))\n(text \"X Flag\" (rect 512 768 554 784)(font \"Arial\" (font_size 10)))\n(text \"H Flag\" (rect 512 528 556 544)(font \"Arial\" (font_size 10)))\n(text \"Force set\" (rect 768 1440 822 1454)(font \"Arial\" (font_size 8)))\n(text \"Force complement\" (rect 856 1448 959 1462)(font \"Arial\" (font_size 8)))\n(text \"Primary latch\" (rect 536 1240 609 1254)(font \"Arial\" (font_size 8)))\n(text \"Secondary latch\" (rect 528 1368 621 1382)(font \"Arial\" (font_size 8)))\n(title_block\n\t(rect 808 1624 1065 1676)\n\t(name \"title-custom-small\")\n\t(section (rect 0 35 256 51)(text \"DATE\" (rect 2 0 30 12)(font \"Arial\" ))(text \"June 21, 2014, 2016\" (rect 56 3 171 17)(font \"Arial\" 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  },
  {
    "path": "cpu/alu/alu_flags.bsf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"symbol\" (version \"1.2\"))\n(symbol\n\t(rect 16 16 280 560)\n\t(text \"alu_flags\" (rect 5 0 56 14)(font \"Arial\" (font_size 8)))\n\t(text \"inst\" (rect 8 528 25 540)(font \"Arial\" ))\n\t(port\n\t\t(pt 0 32)\n\t\t(input)\n\t\t(text \"ctl_flags_oe\" (rect 0 0 69 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"ctl_flags_oe\" (rect 21 27 90 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 32)(pt 16 32))\n\t)\n\t(port\n\t\t(pt 0 48)\n\t\t(input)\n\t\t(text \"ctl_flags_bus\" (rect 0 0 76 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"ctl_flags_bus\" (rect 21 43 97 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 48)(pt 16 48))\n\t)\n\t(port\n\t\t(pt 0 64)\n\t\t(input)\n\t\t(text \"ctl_flags_alu\" (rect 0 0 71 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"ctl_flags_alu\" (rect 21 59 92 73)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 64)(pt 16 64))\n\t)\n\t(port\n\t\t(pt 0 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\"Arial\" (font_size 8)))\n\t\t(line (pt 264 144)(pt 248 144))\n\t)\n\t(port\n\t\t(pt 264 160)\n\t\t(output)\n\t\t(text \"flags_cf\" (rect 0 0 47 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"flags_cf\" (rect 196 155 243 169)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 264 160)(pt 248 160))\n\t)\n\t(port\n\t\t(pt 264 32)\n\t\t(bidir)\n\t\t(text \"db[7..0]\" (rect 0 0 42 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"db[7..0]\" (rect 201 27 243 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 264 32)(pt 248 32)(line_width 3))\n\t)\n\t(drawing\n\t\t(rectangle (rect 16 16 248 528))\n\t)\n)\n"
  },
  {
    "path": "cpu/alu/alu_flags.v",
    "content": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and other software and tools, and its AMPP partner logic \n// functions, and any output files from any of the foregoing \n// (including device programming or simulation files), and any \n// associated documentation or information are expressly subject \n// to the terms and conditions of the Altera Program License \n// Subscription Agreement, Altera MegaCore Function License \n// Agreement, or other applicable license agreement, including, \n// without limitation, that your use is for the sole purpose of \n// programming logic devices manufactured by Altera and sold by \n// Altera or its authorized distributors.  Please refer to the \n// applicable agreement for further details.\n\n// PROGRAM\t\t\"Quartus II 64-Bit\"\n// VERSION\t\t\"Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\"\n// CREATED\t\t\"Sat Dec 10 09:01:30 2016\"\n\nmodule alu_flags(\n\tctl_flags_oe,\n\tctl_flags_bus,\n\tctl_flags_alu,\n\talu_sf_out,\n\talu_yf_out,\n\talu_xf_out,\n\tctl_flags_nf_set,\n\talu_zero,\n\tshift_cf_out,\n\talu_core_cf_out,\n\tdaa_cf_out,\n\tctl_flags_cf_set,\n\tctl_flags_cf_cpl,\n\tpf_sel,\n\tctl_flags_cf_we,\n\tctl_flags_sz_we,\n\tctl_flags_xy_we,\n\tctl_flags_hf_we,\n\tctl_flags_pf_we,\n\tctl_flags_nf_we,\n\tctl_flags_cf2_we,\n\tctl_flags_hf_cpl,\n\tctl_flags_use_cf2,\n\tctl_flags_hf2_we,\n\tctl_flags_nf_clr,\n\tctl_alu_zero_16bit,\n\tclk,\n\tctl_flags_cf2_sel_shift,\n\tctl_flags_cf2_sel_daa,\n\tnhold_clk_wait,\n\tflags_sf,\n\tflags_zf,\n\tflags_hf,\n\tflags_pf,\n\tflags_cf,\n\tflags_nf,\n\tflags_cf_latch,\n\tflags_hf2,\n\tdb\n);\n\n\ninput wire\tctl_flags_oe;\ninput wire\tctl_flags_bus;\ninput wire\tctl_flags_alu;\ninput wire\talu_sf_out;\ninput wire\talu_yf_out;\ninput wire\talu_xf_out;\ninput wire\tctl_flags_nf_set;\ninput wire\talu_zero;\ninput wire\tshift_cf_out;\ninput wire\talu_core_cf_out;\ninput wire\tdaa_cf_out;\ninput wire\tctl_flags_cf_set;\ninput wire\tctl_flags_cf_cpl;\ninput wire\tpf_sel;\ninput wire\tctl_flags_cf_we;\ninput wire\tctl_flags_sz_we;\ninput wire\tctl_flags_xy_we;\ninput wire\tctl_flags_hf_we;\ninput wire\tctl_flags_pf_we;\ninput wire\tctl_flags_nf_we;\ninput wire\tctl_flags_cf2_we;\ninput wire\tctl_flags_hf_cpl;\ninput wire\tctl_flags_use_cf2;\ninput wire\tctl_flags_hf2_we;\ninput wire\tctl_flags_nf_clr;\ninput wire\tctl_alu_zero_16bit;\ninput wire\tclk;\ninput wire\tctl_flags_cf2_sel_shift;\ninput wire\tctl_flags_cf2_sel_daa;\ninput wire\tnhold_clk_wait;\noutput wire\tflags_sf;\noutput wire\tflags_zf;\noutput wire\tflags_hf;\noutput wire\tflags_pf;\noutput wire\tflags_cf;\noutput wire\tflags_nf;\noutput wire\tflags_cf_latch;\noutput reg\tflags_hf2;\ninout wire\t[7:0] db;\n\nreg\tflags_xf;\nreg\tflags_yf;\nwire\t[1:0] sel;\nreg\tDFFE_inst_latch_hf;\nwire\tSYNTHESIZED_WIRE_0;\nwire\tSYNTHESIZED_WIRE_1;\nwire\tSYNTHESIZED_WIRE_2;\nwire\tSYNTHESIZED_WIRE_3;\nwire\tSYNTHESIZED_WIRE_4;\nwire\tSYNTHESIZED_WIRE_5;\nwire\tSYNTHESIZED_WIRE_6;\nwire\tSYNTHESIZED_WIRE_7;\nreg\tSYNTHESIZED_WIRE_39;\nwire\tSYNTHESIZED_WIRE_8;\nwire\tSYNTHESIZED_WIRE_9;\nwire\tSYNTHESIZED_WIRE_10;\nwire\tSYNTHESIZED_WIRE_11;\nwire\tSYNTHESIZED_WIRE_12;\nwire\tSYNTHESIZED_WIRE_13;\nwire\tSYNTHESIZED_WIRE_14;\nwire\tSYNTHESIZED_WIRE_15;\nwire\tSYNTHESIZED_WIRE_16;\nwire\tSYNTHESIZED_WIRE_17;\nwire\tSYNTHESIZED_WIRE_18;\nwire\tSYNTHESIZED_WIRE_19;\nwire\tSYNTHESIZED_WIRE_20;\nwire\tSYNTHESIZED_WIRE_21;\nwire\tSYNTHESIZED_WIRE_22;\nreg\tDFFE_inst_latch_sf;\nwire\tSYNTHESIZED_WIRE_23;\nreg\tDFFE_inst_latch_pf;\nreg\tDFFE_inst_latch_nf;\nwire\tSYNTHESIZED_WIRE_24;\nwire\tSYNTHESIZED_WIRE_25;\nwire\tSYNTHESIZED_WIRE_26;\nwire\tSYNTHESIZED_WIRE_27;\nwire\tSYNTHESIZED_WIRE_28;\nwire\tSYNTHESIZED_WIRE_29;\nwire\tSYNTHESIZED_WIRE_40;\nwire\tSYNTHESIZED_WIRE_32;\nwire\tSYNTHESIZED_WIRE_33;\nwire\tSYNTHESIZED_WIRE_34;\nwire\tSYNTHESIZED_WIRE_35;\nwire\tSYNTHESIZED_WIRE_36;\nwire\tSYNTHESIZED_WIRE_37;\nreg\tDFFE_inst_latch_cf;\nreg\tDFFE_inst_latch_cf2;\nwire\tSYNTHESIZED_WIRE_38;\n\nassign\tflags_sf = DFFE_inst_latch_sf;\nassign\tflags_zf = SYNTHESIZED_WIRE_39;\nassign\tflags_hf = SYNTHESIZED_WIRE_23;\nassign\tflags_pf = DFFE_inst_latch_pf;\nassign\tflags_cf = SYNTHESIZED_WIRE_24;\nassign\tflags_nf = DFFE_inst_latch_nf;\nassign\tflags_cf_latch = DFFE_inst_latch_cf;\nassign\tSYNTHESIZED_WIRE_38 = 0;\n\n\n\nassign\tSYNTHESIZED_WIRE_10 = db[7] & ctl_flags_bus;\n\nassign\tSYNTHESIZED_WIRE_17 = alu_xf_out & ctl_flags_alu;\n\nassign\tSYNTHESIZED_WIRE_20 = db[2] & ctl_flags_bus;\n\nassign\tSYNTHESIZED_WIRE_19 = pf_sel & ctl_flags_alu;\n\nassign\tSYNTHESIZED_WIRE_2 = db[1] & ctl_flags_bus;\n\nassign\tSYNTHESIZED_WIRE_23 = DFFE_inst_latch_hf ^ ctl_flags_hf_cpl;\n\nassign\tSYNTHESIZED_WIRE_22 = db[0] & ctl_flags_bus;\n\nassign\tSYNTHESIZED_WIRE_21 = ctl_flags_alu & alu_core_cf_out;\n\nassign\tSYNTHESIZED_WIRE_8 =  ~ctl_flags_cf2_we;\n\nassign\tSYNTHESIZED_WIRE_24 = SYNTHESIZED_WIRE_0 ^ ctl_flags_cf_cpl;\n\nassign\tSYNTHESIZED_WIRE_1 = alu_sf_out & ctl_flags_alu;\n\nassign\tSYNTHESIZED_WIRE_9 = alu_sf_out & ctl_flags_alu;\n\nassign\tSYNTHESIZED_WIRE_5 = ctl_flags_nf_set | SYNTHESIZED_WIRE_1 | SYNTHESIZED_WIRE_2;\n\nassign\tSYNTHESIZED_WIRE_37 = SYNTHESIZED_WIRE_3 & SYNTHESIZED_WIRE_4;\n\n\nassign\tSYNTHESIZED_WIRE_32 = SYNTHESIZED_WIRE_5 & SYNTHESIZED_WIRE_6;\n\nassign\tSYNTHESIZED_WIRE_6 =  ~ctl_flags_nf_clr;\n\nassign\tSYNTHESIZED_WIRE_7 =  ~ctl_alu_zero_16bit;\n\nassign\tSYNTHESIZED_WIRE_4 = SYNTHESIZED_WIRE_7 | SYNTHESIZED_WIRE_39;\n\nassign\tSYNTHESIZED_WIRE_27 = ctl_flags_cf_we & nhold_clk_wait & SYNTHESIZED_WIRE_8;\n\nassign\tSYNTHESIZED_WIRE_29 = ctl_flags_cf2_we & nhold_clk_wait;\n\nassign\tSYNTHESIZED_WIRE_12 = db[6] & ctl_flags_bus;\n\nassign\tSYNTHESIZED_WIRE_34 = SYNTHESIZED_WIRE_9 | SYNTHESIZED_WIRE_10;\n\nassign\tSYNTHESIZED_WIRE_3 = SYNTHESIZED_WIRE_11 | SYNTHESIZED_WIRE_12;\n\nassign\tSYNTHESIZED_WIRE_36 = SYNTHESIZED_WIRE_13 | SYNTHESIZED_WIRE_14;\n\nassign\tSYNTHESIZED_WIRE_40 = SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16;\n\nassign\tSYNTHESIZED_WIRE_35 = SYNTHESIZED_WIRE_17 | SYNTHESIZED_WIRE_18;\n\nassign\tSYNTHESIZED_WIRE_33 = SYNTHESIZED_WIRE_19 | SYNTHESIZED_WIRE_20;\n\nassign\tSYNTHESIZED_WIRE_11 = alu_zero & ctl_flags_alu;\n\nassign\tSYNTHESIZED_WIRE_26 = SYNTHESIZED_WIRE_21 | SYNTHESIZED_WIRE_22;\n\nassign\tdb[7] = ctl_flags_oe ? DFFE_inst_latch_sf : 1'bz;\n\nassign\tSYNTHESIZED_WIRE_14 = db[5] & ctl_flags_bus;\n\nassign\tdb[6] = ctl_flags_oe ? SYNTHESIZED_WIRE_39 : 1'bz;\n\nassign\tdb[5] = ctl_flags_oe ? flags_yf : 1'bz;\n\nassign\tdb[4] = ctl_flags_oe ? SYNTHESIZED_WIRE_23 : 1'bz;\n\nassign\tdb[3] = ctl_flags_oe ? flags_xf : 1'bz;\n\nassign\tdb[2] = ctl_flags_oe ? DFFE_inst_latch_pf : 1'bz;\n\nassign\tdb[1] = ctl_flags_oe ? DFFE_inst_latch_nf : 1'bz;\n\nassign\tdb[0] = ctl_flags_oe ? SYNTHESIZED_WIRE_24 : 1'bz;\n\nassign\tSYNTHESIZED_WIRE_13 = alu_yf_out & ctl_flags_alu;\n\nassign\tSYNTHESIZED_WIRE_0 = ctl_flags_cf_set | SYNTHESIZED_WIRE_25;\n\nassign\tSYNTHESIZED_WIRE_16 = db[4] & ctl_flags_bus;\n\nassign\tSYNTHESIZED_WIRE_15 = alu_core_cf_out & ctl_flags_alu;\n\nassign\tSYNTHESIZED_WIRE_18 = db[3] & ctl_flags_bus;\n\n\nalways@(posedge clk)\nbegin\nif (SYNTHESIZED_WIRE_27)\n\tbegin\n\tDFFE_inst_latch_cf <= SYNTHESIZED_WIRE_26;\n\tend\nend\n\n\nalways@(posedge clk)\nbegin\nif (SYNTHESIZED_WIRE_29)\n\tbegin\n\tDFFE_inst_latch_cf2 <= SYNTHESIZED_WIRE_28;\n\tend\nend\n\n\nalways@(posedge clk)\nbegin\nif (ctl_flags_hf_we)\n\tbegin\n\tDFFE_inst_latch_hf <= SYNTHESIZED_WIRE_40;\n\tend\nend\n\n\nalways@(posedge clk)\nbegin\nif (ctl_flags_hf2_we)\n\tbegin\n\tflags_hf2 <= SYNTHESIZED_WIRE_40;\n\tend\nend\n\n\nalways@(posedge clk)\nbegin\nif (ctl_flags_nf_we)\n\tbegin\n\tDFFE_inst_latch_nf <= SYNTHESIZED_WIRE_32;\n\tend\nend\n\n\nalways@(posedge clk)\nbegin\nif (ctl_flags_pf_we)\n\tbegin\n\tDFFE_inst_latch_pf <= SYNTHESIZED_WIRE_33;\n\tend\nend\n\n\nalways@(posedge clk)\nbegin\nif (ctl_flags_sz_we)\n\tbegin\n\tDFFE_inst_latch_sf <= SYNTHESIZED_WIRE_34;\n\tend\nend\n\n\nalways@(posedge clk)\nbegin\nif (ctl_flags_xy_we)\n\tbegin\n\tflags_xf <= SYNTHESIZED_WIRE_35;\n\tend\nend\n\n\nalways@(posedge clk)\nbegin\nif (ctl_flags_xy_we)\n\tbegin\n\tflags_yf <= SYNTHESIZED_WIRE_36;\n\tend\nend\n\n\nalways@(posedge clk)\nbegin\nif (ctl_flags_sz_we)\n\tbegin\n\tSYNTHESIZED_WIRE_39 <= SYNTHESIZED_WIRE_37;\n\tend\nend\n\n\nalu_mux_2\tb2v_inst_mux_cf(\n\t.in0(DFFE_inst_latch_cf),\n\t.in1(DFFE_inst_latch_cf2),\n\t.sel1(ctl_flags_use_cf2),\n\t.out(SYNTHESIZED_WIRE_25));\n\n\nalu_mux_4\tb2v_inst_mux_cf2(\n\t.in0(alu_core_cf_out),\n\t.in1(shift_cf_out),\n\t.in2(daa_cf_out),\n\t.in3(SYNTHESIZED_WIRE_38),\n\t.sel(sel),\n\t.out(SYNTHESIZED_WIRE_28));\n\nassign\tsel[0] = ctl_flags_cf2_sel_shift;\nassign\tsel[1] = ctl_flags_cf2_sel_daa;\n\nendmodule\n"
  },
  {
    "path": "cpu/alu/alu_mux_2.bdf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  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  },
  {
    "path": "cpu/alu/alu_mux_2.bsf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"symbol\" (version \"1.2\"))\n(symbol\n\t(rect 16 16 112 112)\n\t(text \"alu_mux_2\" (rect 5 0 66 14)(font \"Arial\" (font_size 8)))\n\t(text \"inst\" (rect 8 80 25 92)(font \"Arial\" ))\n\t(port\n\t\t(pt 0 32)\n\t\t(input)\n\t\t(text \"in0\" (rect 0 0 16 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"in0\" (rect 21 27 37 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 32)(pt 16 32))\n\t)\n\t(port\n\t\t(pt 0 48)\n\t\t(input)\n\t\t(text \"in1\" (rect 0 0 16 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"in1\" (rect 21 43 37 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 48)(pt 16 48))\n\t)\n\t(port\n\t\t(pt 0 64)\n\t\t(input)\n\t\t(text \"sel1\" (rect 0 0 23 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"sel1\" (rect 21 59 44 73)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 64)(pt 16 64))\n\t)\n\t(port\n\t\t(pt 96 32)\n\t\t(output)\n\t\t(text \"out\" (rect 0 0 17 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"out\" (rect 58 27 75 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 96 32)(pt 80 32))\n\t)\n\t(drawing\n\t\t(rectangle (rect 16 16 80 80))\n\t)\n)\n"
  },
  {
    "path": "cpu/alu/alu_mux_2.v",
    "content": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and other software and tools, and its AMPP partner logic \n// functions, and any output files from any of the foregoing \n// (including device programming or simulation files), and any \n// associated documentation or information are expressly subject \n// to the terms and conditions of the Altera Program License \n// Subscription Agreement, Altera MegaCore Function License \n// Agreement, or other applicable license agreement, including, \n// without limitation, that your use is for the sole purpose of \n// programming logic devices manufactured by Altera and sold by \n// Altera or its authorized distributors.  Please refer to the \n// applicable agreement for further details.\n\n// PROGRAM\t\t\"Quartus II 64-Bit\"\n// VERSION\t\t\"Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\"\n// CREATED\t\t\"Mon Oct 13 12:10:35 2014\"\n\nmodule alu_mux_2(\n\tsel1,\n\tin1,\n\tin0,\n\tout\n);\n\n\ninput wire\tsel1;\ninput wire\tin1;\ninput wire\tin0;\noutput wire\tout;\n\nwire\tSYNTHESIZED_WIRE_0;\nwire\tSYNTHESIZED_WIRE_1;\nwire\tSYNTHESIZED_WIRE_2;\n\n\n\n\nassign\tSYNTHESIZED_WIRE_2 = in0 & SYNTHESIZED_WIRE_0;\n\nassign\tSYNTHESIZED_WIRE_1 = in1 & sel1;\n\nassign\tout = SYNTHESIZED_WIRE_1 | SYNTHESIZED_WIRE_2;\n\nassign\tSYNTHESIZED_WIRE_0 =  ~sel1;\n\n\nendmodule\n"
  },
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    "path": "cpu/alu/alu_mux_2z.bdf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  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    "path": "cpu/alu/alu_mux_2z.bsf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"symbol\" (version \"1.2\"))\n(symbol\n\t(rect 16 16 160 112)\n\t(text \"alu_mux_2z\" (rect 5 0 73 14)(font \"Arial\" (font_size 8)))\n\t(text \"inst\" (rect 8 80 25 92)(font \"Arial\" ))\n\t(port\n\t\t(pt 0 32)\n\t\t(input)\n\t\t(text \"a[3..0]\" (rect 0 0 35 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"a[3..0]\" (rect 21 27 56 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 32)(pt 16 32)(line_width 3))\n\t)\n\t(port\n\t\t(pt 0 48)\n\t\t(input)\n\t\t(text \"sel_a\" (rect 0 0 30 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"sel_a\" (rect 21 43 51 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 48)(pt 16 48))\n\t)\n\t(port\n\t\t(pt 0 64)\n\t\t(input)\n\t\t(text \"sel_zero\" (rect 0 0 49 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"sel_zero\" (rect 21 59 70 73)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 64)(pt 16 64))\n\t)\n\t(port\n\t\t(pt 144 32)\n\t\t(output)\n\t\t(text \"Q[3..0]\" (rect 0 0 37 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"Q[3..0]\" (rect 86 27 123 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 144 32)(pt 128 32)(line_width 3))\n\t)\n\t(port\n\t\t(pt 144 48)\n\t\t(output)\n\t\t(text \"ena\" (rect 0 0 21 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"ena\" (rect 102 43 123 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 144 48)(pt 128 48))\n\t)\n\t(drawing\n\t\t(rectangle (rect 16 16 128 80))\n\t)\n)\n"
  },
  {
    "path": "cpu/alu/alu_mux_2z.v",
    "content": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and other software and tools, and its AMPP partner logic \n// functions, and any output files from any of the foregoing \n// (including device programming or simulation files), and any \n// associated documentation or information are expressly subject \n// to the terms and conditions of the Altera Program License \n// Subscription Agreement, Altera MegaCore Function License \n// Agreement, or other applicable license agreement, including, \n// without limitation, that your use is for the sole purpose of \n// programming logic devices manufactured by Altera and sold by \n// Altera or its authorized distributors.  Please refer to the \n// applicable agreement for further details.\n\n// PROGRAM\t\t\"Quartus II 64-Bit\"\n// VERSION\t\t\"Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\"\n// CREATED\t\t\"Fri Oct 31 21:18:33 2014\"\n\nmodule alu_mux_2z(\n\tsel_a,\n\tsel_zero,\n\ta,\n\tena,\n\tQ\n);\n\n\ninput wire\tsel_a;\ninput wire\tsel_zero;\ninput wire\t[3:0] a;\noutput wire\tena;\noutput wire\t[3:0] Q;\n\nwire\t[3:0] SYNTHESIZED_WIRE_0;\nwire\tSYNTHESIZED_WIRE_1;\n\n\n\n\nassign\tSYNTHESIZED_WIRE_0 = a & {sel_a,sel_a,sel_a,sel_a};\n\nassign\tena = sel_a | sel_zero;\n\nassign\tQ = SYNTHESIZED_WIRE_0 & {SYNTHESIZED_WIRE_1,SYNTHESIZED_WIRE_1,SYNTHESIZED_WIRE_1,SYNTHESIZED_WIRE_1};\n\nassign\tSYNTHESIZED_WIRE_1 =  ~sel_zero;\n\n\nendmodule\n"
  },
  {
    "path": "cpu/alu/alu_mux_3z.bdf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  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  },
  {
    "path": "cpu/alu/alu_mux_3z.bsf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"symbol\" (version \"1.2\"))\n(symbol\n\t(rect 16 16 160 144)\n\t(text \"alu_mux_3z\" (rect 5 0 73 14)(font \"Arial\" (font_size 8)))\n\t(text \"inst\" (rect 8 112 25 124)(font \"Arial\" ))\n\t(port\n\t\t(pt 0 32)\n\t\t(input)\n\t\t(text \"a[3..0]\" (rect 0 0 35 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"a[3..0]\" (rect 21 27 56 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 32)(pt 16 32)(line_width 3))\n\t)\n\t(port\n\t\t(pt 0 48)\n\t\t(input)\n\t\t(text \"sel_a\" (rect 0 0 30 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"sel_a\" (rect 21 43 51 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 48)(pt 16 48))\n\t)\n\t(port\n\t\t(pt 0 64)\n\t\t(input)\n\t\t(text \"b[3..0]\" (rect 0 0 35 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"b[3..0]\" (rect 21 59 56 73)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 64)(pt 16 64)(line_width 3))\n\t)\n\t(port\n\t\t(pt 0 80)\n\t\t(input)\n\t\t(text \"sel_b\" (rect 0 0 30 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"sel_b\" (rect 21 75 51 89)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 80)(pt 16 80))\n\t)\n\t(port\n\t\t(pt 0 96)\n\t\t(input)\n\t\t(text \"sel_zero\" (rect 0 0 49 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"sel_zero\" (rect 21 91 70 105)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 96)(pt 16 96))\n\t)\n\t(port\n\t\t(pt 144 32)\n\t\t(output)\n\t\t(text \"Q[3..0]\" (rect 0 0 37 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"Q[3..0]\" (rect 86 27 123 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 144 32)(pt 128 32)(line_width 3))\n\t)\n\t(port\n\t\t(pt 144 48)\n\t\t(output)\n\t\t(text \"ena\" (rect 0 0 21 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"ena\" (rect 102 43 123 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 144 48)(pt 128 48))\n\t)\n\t(drawing\n\t\t(rectangle (rect 16 16 128 112))\n\t)\n)\n"
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  {
    "path": "cpu/alu/alu_mux_3z.v",
    "content": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and other software and tools, and its AMPP partner logic \n// functions, and any output files from any of the foregoing \n// (including device programming or simulation files), and any \n// associated documentation or information are expressly subject \n// to the terms and conditions of the Altera Program License \n// Subscription Agreement, Altera MegaCore Function License \n// Agreement, or other applicable license agreement, including, \n// without limitation, that your use is for the sole purpose of \n// programming logic devices manufactured by Altera and sold by \n// Altera or its authorized distributors.  Please refer to the \n// applicable agreement for further details.\n\n// PROGRAM\t\t\"Quartus II 64-Bit\"\n// VERSION\t\t\"Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\"\n// CREATED\t\t\"Fri Oct 31 21:08:42 2014\"\n\nmodule alu_mux_3z(\n\tsel_zero,\n\tsel_a,\n\tsel_b,\n\ta,\n\tb,\n\tena,\n\tQ\n);\n\n\ninput wire\tsel_zero;\ninput wire\tsel_a;\ninput wire\tsel_b;\ninput wire\t[3:0] a;\ninput wire\t[3:0] b;\noutput wire\tena;\noutput wire\t[3:0] Q;\n\nwire\t[3:0] SYNTHESIZED_WIRE_0;\nwire\tSYNTHESIZED_WIRE_1;\nwire\t[3:0] SYNTHESIZED_WIRE_2;\nwire\t[3:0] SYNTHESIZED_WIRE_3;\n\n\n\n\nassign\tSYNTHESIZED_WIRE_3 = a & {sel_a,sel_a,sel_a,sel_a};\n\nassign\tQ = SYNTHESIZED_WIRE_0 & {SYNTHESIZED_WIRE_1,SYNTHESIZED_WIRE_1,SYNTHESIZED_WIRE_1,SYNTHESIZED_WIRE_1};\n\nassign\tSYNTHESIZED_WIRE_1 =  ~sel_zero;\n\nassign\tSYNTHESIZED_WIRE_0 = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_3;\n\nassign\tena = sel_a | sel_b | sel_zero;\n\nassign\tSYNTHESIZED_WIRE_2 = b & {sel_b,sel_b,sel_b,sel_b};\n\n\nendmodule\n"
  },
  {
    "path": "cpu/alu/alu_mux_4.bdf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  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  },
  {
    "path": "cpu/alu/alu_mux_4.bsf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"symbol\" (version \"1.2\"))\n(symbol\n\t(rect 16 16 128 144)\n\t(text \"alu_mux_4\" (rect 5 0 66 14)(font \"Arial\" (font_size 8)))\n\t(text \"inst\" (rect 8 112 25 124)(font \"Arial\" ))\n\t(port\n\t\t(pt 0 32)\n\t\t(input)\n\t\t(text \"sel[1..0]\" (rect 0 0 44 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"sel[1..0]\" (rect 21 27 65 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 32)(pt 16 32)(line_width 3))\n\t)\n\t(port\n\t\t(pt 0 48)\n\t\t(input)\n\t\t(text \"in0\" (rect 0 0 16 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"in0\" (rect 21 43 37 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 48)(pt 16 48))\n\t)\n\t(port\n\t\t(pt 0 64)\n\t\t(input)\n\t\t(text \"in1\" (rect 0 0 16 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"in1\" (rect 21 59 37 73)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 64)(pt 16 64))\n\t)\n\t(port\n\t\t(pt 0 80)\n\t\t(input)\n\t\t(text \"in2\" (rect 0 0 16 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"in2\" (rect 21 75 37 89)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 80)(pt 16 80))\n\t)\n\t(port\n\t\t(pt 0 96)\n\t\t(input)\n\t\t(text \"in3\" (rect 0 0 16 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"in3\" (rect 21 91 37 105)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 96)(pt 16 96))\n\t)\n\t(port\n\t\t(pt 112 32)\n\t\t(output)\n\t\t(text \"out\" (rect 0 0 17 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"out\" (rect 74 27 91 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 112 32)(pt 96 32))\n\t)\n\t(drawing\n\t\t(rectangle (rect 16 16 96 112))\n\t)\n)\n"
  },
  {
    "path": "cpu/alu/alu_mux_4.v",
    "content": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and other software and tools, and its AMPP partner logic \n// functions, and any output files from any of the foregoing \n// (including device programming or simulation files), and any \n// associated documentation or information are expressly subject \n// to the terms and conditions of the Altera Program License \n// Subscription Agreement, Altera MegaCore Function License \n// Agreement, or other applicable license agreement, including, \n// without limitation, that your use is for the sole purpose of \n// programming logic devices manufactured by Altera and sold by \n// Altera or its authorized distributors.  Please refer to the \n// applicable agreement for further details.\n\n// PROGRAM\t\t\"Quartus II 64-Bit\"\n// VERSION\t\t\"Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\"\n// CREATED\t\t\"Mon Oct 13 12:05:38 2014\"\n\nmodule alu_mux_4(\n\tin0,\n\tin1,\n\tin2,\n\tin3,\n\tsel,\n\tout\n);\n\n\ninput wire\tin0;\ninput wire\tin1;\ninput wire\tin2;\ninput wire\tin3;\ninput wire\t[1:0] sel;\noutput wire\tout;\n\nwire\tSYNTHESIZED_WIRE_8;\nwire\tSYNTHESIZED_WIRE_9;\nwire\tSYNTHESIZED_WIRE_4;\nwire\tSYNTHESIZED_WIRE_5;\nwire\tSYNTHESIZED_WIRE_6;\nwire\tSYNTHESIZED_WIRE_7;\n\n\n\n\nassign\tSYNTHESIZED_WIRE_4 = SYNTHESIZED_WIRE_8 & SYNTHESIZED_WIRE_9 & in0;\n\nassign\tSYNTHESIZED_WIRE_7 = sel[0] & SYNTHESIZED_WIRE_9 & in1;\n\nassign\tSYNTHESIZED_WIRE_5 = SYNTHESIZED_WIRE_8 & sel[1] & in2;\n\nassign\tSYNTHESIZED_WIRE_6 = sel[0] & sel[1] & in3;\n\nassign\tout = SYNTHESIZED_WIRE_4 | SYNTHESIZED_WIRE_5 | SYNTHESIZED_WIRE_6 | SYNTHESIZED_WIRE_7;\n\nassign\tSYNTHESIZED_WIRE_8 =  ~sel[0];\n\nassign\tSYNTHESIZED_WIRE_9 =  ~sel[1];\n\n\nendmodule\n"
  },
  {
    "path": "cpu/alu/alu_mux_8.bdf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  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    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"symbol\" (version \"1.2\"))\n(symbol\n\t(rect 16 16 128 208)\n\t(text \"alu_mux_8\" (rect 5 0 66 14)(font \"Arial\" (font_size 8)))\n\t(text \"inst\" (rect 8 176 25 188)(font \"Arial\" ))\n\t(port\n\t\t(pt 0 32)\n\t\t(input)\n\t\t(text \"sel[2..0]\" (rect 0 0 44 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"sel[2..0]\" (rect 21 27 65 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 32)(pt 16 32)(line_width 3))\n\t)\n\t(port\n\t\t(pt 0 48)\n\t\t(input)\n\t\t(text \"in0\" (rect 0 0 16 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"in0\" (rect 21 43 37 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 48)(pt 16 48))\n\t)\n\t(port\n\t\t(pt 0 64)\n\t\t(input)\n\t\t(text \"in1\" (rect 0 0 16 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"in1\" (rect 21 59 37 73)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 64)(pt 16 64))\n\t)\n\t(port\n\t\t(pt 0 80)\n\t\t(input)\n\t\t(text \"in2\" (rect 0 0 16 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"in2\" (rect 21 75 37 89)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 80)(pt 16 80))\n\t)\n\t(port\n\t\t(pt 0 96)\n\t\t(input)\n\t\t(text \"in3\" (rect 0 0 16 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"in3\" (rect 21 91 37 105)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 96)(pt 16 96))\n\t)\n\t(port\n\t\t(pt 0 112)\n\t\t(input)\n\t\t(text \"in4\" (rect 0 0 16 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"in4\" (rect 21 107 37 121)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 112)(pt 16 112))\n\t)\n\t(port\n\t\t(pt 0 128)\n\t\t(input)\n\t\t(text \"in5\" (rect 0 0 16 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"in5\" (rect 21 123 37 137)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 128)(pt 16 128))\n\t)\n\t(port\n\t\t(pt 0 144)\n\t\t(input)\n\t\t(text \"in6\" (rect 0 0 16 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"in6\" (rect 21 139 37 153)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 144)(pt 16 144))\n\t)\n\t(port\n\t\t(pt 0 160)\n\t\t(input)\n\t\t(text \"in7\" (rect 0 0 16 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"in7\" (rect 21 155 37 169)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 160)(pt 16 160))\n\t)\n\t(port\n\t\t(pt 112 32)\n\t\t(output)\n\t\t(text \"out\" (rect 0 0 17 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"out\" (rect 74 27 91 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 112 32)(pt 96 32))\n\t)\n\t(drawing\n\t\t(rectangle (rect 16 16 96 176))\n\t)\n)\n"
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    "path": "cpu/alu/alu_mux_8.v",
    "content": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and other software and tools, and its AMPP partner logic \n// functions, and any output files from any of the foregoing \n// (including device programming or simulation files), and any \n// associated documentation or information are expressly subject \n// to the terms and conditions of the Altera Program License \n// Subscription Agreement, Altera MegaCore Function License \n// Agreement, or other applicable license agreement, including, \n// without limitation, that your use is for the sole purpose of \n// programming logic devices manufactured by Altera and sold by \n// Altera or its authorized distributors.  Please refer to the \n// applicable agreement for further details.\n\n// PROGRAM\t\t\"Quartus II 64-Bit\"\n// VERSION\t\t\"Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\"\n// CREATED\t\t\"Mon Oct 13 12:04:13 2014\"\n\nmodule alu_mux_8(\n\tin0,\n\tin1,\n\tin2,\n\tin3,\n\tin4,\n\tin5,\n\tin6,\n\tin7,\n\tsel,\n\tout\n);\n\n\ninput wire\tin0;\ninput wire\tin1;\ninput wire\tin2;\ninput wire\tin3;\ninput wire\tin4;\ninput wire\tin5;\ninput wire\tin6;\ninput wire\tin7;\ninput wire\t[2:0] sel;\noutput wire\tout;\n\nwire\tSYNTHESIZED_WIRE_20;\nwire\tSYNTHESIZED_WIRE_21;\nwire\tSYNTHESIZED_WIRE_22;\nwire\tSYNTHESIZED_WIRE_12;\nwire\tSYNTHESIZED_WIRE_13;\nwire\tSYNTHESIZED_WIRE_14;\nwire\tSYNTHESIZED_WIRE_15;\nwire\tSYNTHESIZED_WIRE_16;\nwire\tSYNTHESIZED_WIRE_17;\nwire\tSYNTHESIZED_WIRE_18;\nwire\tSYNTHESIZED_WIRE_19;\n\n\n\n\nassign\tSYNTHESIZED_WIRE_12 = SYNTHESIZED_WIRE_20 & SYNTHESIZED_WIRE_21 & SYNTHESIZED_WIRE_22 & in0;\n\nassign\tSYNTHESIZED_WIRE_14 = sel[0] & SYNTHESIZED_WIRE_21 & SYNTHESIZED_WIRE_22 & in1;\n\nassign\tSYNTHESIZED_WIRE_13 = SYNTHESIZED_WIRE_20 & sel[1] & SYNTHESIZED_WIRE_22 & in2;\n\nassign\tSYNTHESIZED_WIRE_15 = sel[0] & sel[1] & SYNTHESIZED_WIRE_22 & in3;\n\nassign\tSYNTHESIZED_WIRE_17 = SYNTHESIZED_WIRE_20 & SYNTHESIZED_WIRE_21 & sel[2] & in4;\n\nassign\tSYNTHESIZED_WIRE_16 = sel[0] & SYNTHESIZED_WIRE_21 & sel[2] & in5;\n\nassign\tSYNTHESIZED_WIRE_18 = SYNTHESIZED_WIRE_20 & sel[1] & sel[2] & in6;\n\nassign\tSYNTHESIZED_WIRE_19 = sel[0] & sel[1] & sel[2] & in7;\n\nassign\tout = SYNTHESIZED_WIRE_12 | SYNTHESIZED_WIRE_13 | SYNTHESIZED_WIRE_14 | SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16 | SYNTHESIZED_WIRE_17 | SYNTHESIZED_WIRE_18 | SYNTHESIZED_WIRE_19;\n\nassign\tSYNTHESIZED_WIRE_20 =  ~sel[0];\n\nassign\tSYNTHESIZED_WIRE_21 =  ~sel[1];\n\nassign\tSYNTHESIZED_WIRE_22 =  ~sel[2];\n\n\nendmodule\n"
  },
  {
    "path": "cpu/alu/alu_prep_daa.bdf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  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    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"symbol\" (version \"1.2\"))\n(symbol\n\t(rect 16 16 184 112)\n\t(text \"alu_prep_daa\" (rect 5 0 82 14)(font \"Arial\" (font_size 8)))\n\t(text \"inst\" (rect 8 80 25 92)(font \"Arial\" ))\n\t(port\n\t\t(pt 0 32)\n\t\t(input)\n\t\t(text \"low[3..0]\" (rect 0 0 49 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"low[3..0]\" (rect 21 27 70 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 32)(pt 16 32)(line_width 3))\n\t)\n\t(port\n\t\t(pt 0 48)\n\t\t(input)\n\t\t(text \"high[3..0]\" (rect 0 0 51 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"high[3..0]\" (rect 21 43 72 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 48)(pt 16 48)(line_width 3))\n\t)\n\t(port\n\t\t(pt 168 32)\n\t\t(output)\n\t\t(text \"low_gt_9\" (rect 0 0 53 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"low_gt_9\" (rect 94 27 147 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 168 32)(pt 152 32))\n\t)\n\t(port\n\t\t(pt 168 48)\n\t\t(output)\n\t\t(text \"high_gt_9\" (rect 0 0 55 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"high_gt_9\" (rect 92 43 147 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 168 48)(pt 152 48))\n\t)\n\t(port\n\t\t(pt 168 64)\n\t\t(output)\n\t\t(text \"high_eq_9\" (rect 0 0 59 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"high_eq_9\" (rect 88 59 147 73)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 168 64)(pt 152 64))\n\t)\n\t(drawing\n\t\t(rectangle (rect 16 16 152 80))\n\t)\n)\n"
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  {
    "path": "cpu/alu/alu_prep_daa.v",
    "content": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and other software and tools, and its AMPP partner logic \n// functions, and any output files from any of the foregoing \n// (including device programming or simulation files), and any \n// associated documentation or information are expressly subject \n// to the terms and conditions of the Altera Program License \n// Subscription Agreement, Altera MegaCore Function License \n// Agreement, or other applicable license agreement, including, \n// without limitation, that your use is for the sole purpose of \n// programming logic devices manufactured by Altera and sold by \n// Altera or its authorized distributors.  Please refer to the \n// applicable agreement for further details.\n\n// PROGRAM\t\t\"Quartus II 64-Bit\"\n// VERSION\t\t\"Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\"\n// CREATED\t\t\"Mon Oct 13 12:01:36 2014\"\n\nmodule alu_prep_daa(\n\thigh,\n\tlow,\n\tlow_gt_9,\n\thigh_eq_9,\n\thigh_gt_9\n);\n\n\ninput wire\t[3:0] high;\ninput wire\t[3:0] low;\noutput wire\tlow_gt_9;\noutput wire\thigh_eq_9;\noutput wire\thigh_gt_9;\n\nwire\tSYNTHESIZED_WIRE_0;\nwire\tSYNTHESIZED_WIRE_1;\nwire\tSYNTHESIZED_WIRE_2;\nwire\tSYNTHESIZED_WIRE_3;\nwire\tSYNTHESIZED_WIRE_4;\nwire\tSYNTHESIZED_WIRE_5;\n\n\n\n\nassign\tSYNTHESIZED_WIRE_4 =  ~high[2];\n\nassign\tSYNTHESIZED_WIRE_1 = low[3] & low[2];\n\nassign\tSYNTHESIZED_WIRE_3 = high[3] & high[2];\n\nassign\tSYNTHESIZED_WIRE_0 = low[3] & low[1];\n\nassign\tlow_gt_9 = SYNTHESIZED_WIRE_0 | SYNTHESIZED_WIRE_1;\n\nassign\tSYNTHESIZED_WIRE_2 = high[3] & high[1];\n\nassign\thigh_gt_9 = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_3;\n\nassign\tSYNTHESIZED_WIRE_5 =  ~high[1];\n\nassign\thigh_eq_9 = high[3] & high[0] & SYNTHESIZED_WIRE_4 & SYNTHESIZED_WIRE_5;\n\n\nendmodule\n"
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  {
    "path": "cpu/alu/alu_select.v",
    "content": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and other software and tools, and its AMPP partner logic \n// functions, and any output files from any of the foregoing \n// (including device programming or simulation files), and any \n// associated documentation or information are expressly subject \n// to the terms and conditions of the Altera Program License \n// Subscription Agreement, Altera MegaCore Function License \n// Agreement, or other applicable license agreement, including, \n// without limitation, that your use is for the sole purpose of \n// programming logic devices manufactured by Altera and sold by \n// Altera or its authorized distributors.  Please refer to the \n// applicable agreement for further details.\n\n// PROGRAM\t\t\"Quartus II 64-Bit\"\n// VERSION\t\t\"Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\"\n// CREATED\t\t\"Mon Oct 13 11:59:39 2014\"\n\nmodule alu_select(\n\tctl_alu_oe,\n\tctl_alu_shift_oe,\n\tctl_alu_op2_oe,\n\tctl_alu_res_oe,\n\tctl_alu_op1_oe,\n\tctl_alu_bs_oe,\n\tctl_alu_op1_sel_bus,\n\tctl_alu_op1_sel_low,\n\tctl_alu_op1_sel_zero,\n\tctl_alu_op2_sel_zero,\n\tctl_alu_op2_sel_bus,\n\tctl_alu_op2_sel_lq,\n\tctl_alu_sel_op2_neg,\n\tctl_alu_sel_op2_high,\n\tctl_alu_core_R,\n\tctl_alu_core_V,\n\tctl_alu_core_S,\n\talu_oe,\n\talu_shift_oe,\n\talu_op2_oe,\n\talu_res_oe,\n\talu_op1_oe,\n\talu_bs_oe,\n\talu_op1_sel_bus,\n\talu_op1_sel_low,\n\talu_op1_sel_zero,\n\talu_op2_sel_zero,\n\talu_op2_sel_bus,\n\talu_op2_sel_lq,\n\talu_sel_op2_neg,\n\talu_sel_op2_high,\n\talu_core_R,\n\talu_core_V,\n\talu_core_S\n);\n\n\ninput wire\tctl_alu_oe;\ninput wire\tctl_alu_shift_oe;\ninput wire\tctl_alu_op2_oe;\ninput wire\tctl_alu_res_oe;\ninput wire\tctl_alu_op1_oe;\ninput wire\tctl_alu_bs_oe;\ninput wire\tctl_alu_op1_sel_bus;\ninput wire\tctl_alu_op1_sel_low;\ninput wire\tctl_alu_op1_sel_zero;\ninput wire\tctl_alu_op2_sel_zero;\ninput wire\tctl_alu_op2_sel_bus;\ninput wire\tctl_alu_op2_sel_lq;\ninput wire\tctl_alu_sel_op2_neg;\ninput wire\tctl_alu_sel_op2_high;\ninput wire\tctl_alu_core_R;\ninput wire\tctl_alu_core_V;\ninput wire\tctl_alu_core_S;\noutput wire\talu_oe;\noutput wire\talu_shift_oe;\noutput wire\talu_op2_oe;\noutput wire\talu_res_oe;\noutput wire\talu_op1_oe;\noutput wire\talu_bs_oe;\noutput wire\talu_op1_sel_bus;\noutput wire\talu_op1_sel_low;\noutput wire\talu_op1_sel_zero;\noutput wire\talu_op2_sel_zero;\noutput wire\talu_op2_sel_bus;\noutput wire\talu_op2_sel_lq;\noutput wire\talu_sel_op2_neg;\noutput wire\talu_sel_op2_high;\noutput wire\talu_core_R;\noutput wire\talu_core_V;\noutput wire\talu_core_S;\n\n\nassign\talu_oe = ctl_alu_oe;\nassign\talu_shift_oe = ctl_alu_shift_oe;\nassign\talu_op2_oe = ctl_alu_op2_oe;\nassign\talu_res_oe = ctl_alu_res_oe;\nassign\talu_op1_oe = ctl_alu_op1_oe;\nassign\talu_bs_oe = ctl_alu_bs_oe;\nassign\talu_op1_sel_bus = ctl_alu_op1_sel_bus;\nassign\talu_op1_sel_low = ctl_alu_op1_sel_low;\nassign\talu_op1_sel_zero = ctl_alu_op1_sel_zero;\nassign\talu_op2_sel_zero = ctl_alu_op2_sel_zero;\nassign\talu_op2_sel_bus = ctl_alu_op2_sel_bus;\nassign\talu_op2_sel_lq = ctl_alu_op2_sel_lq;\nassign\talu_sel_op2_neg = ctl_alu_sel_op2_neg;\nassign\talu_sel_op2_high = ctl_alu_sel_op2_high;\nassign\talu_core_R = ctl_alu_core_R;\nassign\talu_core_V = ctl_alu_core_V;\nassign\talu_core_S = ctl_alu_core_S;\n\n\n\n\nendmodule\n"
  },
  {
    "path": "cpu/alu/alu_shifter_core.bdf",
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  },
  {
    "path": "cpu/alu/alu_shifter_core.bsf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"symbol\" (version \"1.2\"))\n(symbol\n\t(rect 16 16 200 144)\n\t(text \"alu_shifter_core\" (rect 5 0 98 14)(font \"Arial\" (font_size 8)))\n\t(text \"inst\" (rect 8 112 25 124)(font \"Arial\" ))\n\t(port\n\t\t(pt 0 32)\n\t\t(input)\n\t\t(text \"db[7..0]\" (rect 0 0 42 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"db[7..0]\" (rect 21 27 63 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 32)(pt 16 32)(line_width 3))\n\t)\n\t(port\n\t\t(pt 0 48)\n\t\t(input)\n\t\t(text \"shift_in\" (rect 0 0 41 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"shift_in\" (rect 21 43 62 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 48)(pt 16 48))\n\t)\n\t(port\n\t\t(pt 0 64)\n\t\t(input)\n\t\t(text \"shift_left\" (rect 0 0 49 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"shift_left\" (rect 21 59 70 73)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 64)(pt 16 64))\n\t)\n\t(port\n\t\t(pt 0 80)\n\t\t(input)\n\t\t(text \"shift_right\" (rect 0 0 56 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"shift_right\" (rect 21 75 77 89)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 80)(pt 16 80))\n\t)\n\t(port\n\t\t(pt 184 32)\n\t\t(output)\n\t\t(text \"shift_db0\" (rect 0 0 53 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"shift_db0\" (rect 110 27 163 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 184 32)(pt 168 32))\n\t)\n\t(port\n\t\t(pt 184 48)\n\t\t(output)\n\t\t(text \"shift_db7\" (rect 0 0 53 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"shift_db7\" (rect 110 43 163 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 184 48)(pt 168 48))\n\t)\n\t(port\n\t\t(pt 184 64)\n\t\t(output)\n\t\t(text \"out_low[3..0]\" (rect 0 0 74 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"out_low[3..0]\" (rect 89 59 163 73)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 184 64)(pt 168 64)(line_width 3))\n\t)\n\t(port\n\t\t(pt 184 80)\n\t\t(output)\n\t\t(text \"out_high[3..0]\" (rect 0 0 76 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"out_high[3..0]\" (rect 87 75 163 89)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 184 80)(pt 168 80)(line_width 3))\n\t)\n\t(drawing\n\t\t(rectangle (rect 16 16 168 112))\n\t)\n\t(fill (color 217 255 255))\n)\n"
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    "path": "cpu/alu/alu_shifter_core.v",
    "content": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and other software and tools, and its AMPP partner logic \n// functions, and any output files from any of the foregoing \n// (including device programming or simulation files), and any \n// associated documentation or information are expressly subject \n// to the terms and conditions of the Altera Program License \n// Subscription Agreement, Altera MegaCore Function License \n// Agreement, or other applicable license agreement, including, \n// without limitation, that your use is for the sole purpose of \n// programming logic devices manufactured by Altera and sold by \n// Altera or its authorized distributors.  Please refer to the \n// applicable agreement for further details.\n\n// PROGRAM\t\t\"Quartus II 64-Bit\"\n// VERSION\t\t\"Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\"\n// CREATED\t\t\"Mon Oct 13 11:55:31 2014\"\n\nmodule alu_shifter_core(\n\tshift_in,\n\tshift_right,\n\tshift_left,\n\tdb,\n\tshift_db0,\n\tshift_db7,\n\tout_high,\n\tout_low\n);\n\n\ninput wire\tshift_in;\ninput wire\tshift_right;\ninput wire\tshift_left;\ninput wire\t[7:0] db;\noutput wire\tshift_db0;\noutput wire\tshift_db7;\noutput wire\t[3:0] out_high;\noutput wire\t[3:0] out_low;\n\nwire\t[3:0] out_high_ALTERA_SYNTHESIZED;\nwire\t[3:0] out_low_ALTERA_SYNTHESIZED;\nwire\tSYNTHESIZED_WIRE_32;\nwire\tSYNTHESIZED_WIRE_8;\nwire\tSYNTHESIZED_WIRE_9;\nwire\tSYNTHESIZED_WIRE_10;\nwire\tSYNTHESIZED_WIRE_11;\nwire\tSYNTHESIZED_WIRE_12;\nwire\tSYNTHESIZED_WIRE_13;\nwire\tSYNTHESIZED_WIRE_14;\nwire\tSYNTHESIZED_WIRE_15;\nwire\tSYNTHESIZED_WIRE_16;\nwire\tSYNTHESIZED_WIRE_17;\nwire\tSYNTHESIZED_WIRE_18;\nwire\tSYNTHESIZED_WIRE_19;\nwire\tSYNTHESIZED_WIRE_20;\nwire\tSYNTHESIZED_WIRE_21;\nwire\tSYNTHESIZED_WIRE_22;\nwire\tSYNTHESIZED_WIRE_23;\nwire\tSYNTHESIZED_WIRE_24;\nwire\tSYNTHESIZED_WIRE_25;\nwire\tSYNTHESIZED_WIRE_26;\nwire\tSYNTHESIZED_WIRE_27;\nwire\tSYNTHESIZED_WIRE_28;\nwire\tSYNTHESIZED_WIRE_29;\nwire\tSYNTHESIZED_WIRE_30;\nwire\tSYNTHESIZED_WIRE_31;\n\nassign\tshift_db0 = db[0];\nassign\tshift_db7 = db[7];\n\n\n\nassign\tSYNTHESIZED_WIRE_9 = shift_in & shift_left;\n\nassign\tSYNTHESIZED_WIRE_8 = db[0] & SYNTHESIZED_WIRE_32;\n\nassign\tSYNTHESIZED_WIRE_10 = db[1] & shift_right;\n\nassign\tSYNTHESIZED_WIRE_12 = db[0] & shift_left;\n\nassign\tSYNTHESIZED_WIRE_11 = db[1] & SYNTHESIZED_WIRE_32;\n\nassign\tSYNTHESIZED_WIRE_13 = db[2] & shift_right;\n\nassign\tSYNTHESIZED_WIRE_15 = db[1] & shift_left;\n\nassign\tSYNTHESIZED_WIRE_14 = db[2] & SYNTHESIZED_WIRE_32;\n\nassign\tSYNTHESIZED_WIRE_16 = db[3] & shift_right;\n\nassign\tSYNTHESIZED_WIRE_18 = db[2] & shift_left;\n\nassign\tSYNTHESIZED_WIRE_17 = db[3] & SYNTHESIZED_WIRE_32;\n\nassign\tSYNTHESIZED_WIRE_19 = db[4] & shift_right;\n\nassign\tSYNTHESIZED_WIRE_21 = db[3] & shift_left;\n\nassign\tSYNTHESIZED_WIRE_20 = db[4] & SYNTHESIZED_WIRE_32;\n\nassign\tSYNTHESIZED_WIRE_22 = db[5] & shift_right;\n\nassign\tSYNTHESIZED_WIRE_24 = db[4] & shift_left;\n\nassign\tSYNTHESIZED_WIRE_23 = db[5] & SYNTHESIZED_WIRE_32;\n\nassign\tSYNTHESIZED_WIRE_25 = db[6] & shift_right;\n\nassign\tSYNTHESIZED_WIRE_27 = db[5] & shift_left;\n\nassign\tSYNTHESIZED_WIRE_26 = db[6] & SYNTHESIZED_WIRE_32;\n\nassign\tSYNTHESIZED_WIRE_28 = db[7] & shift_right;\n\nassign\tSYNTHESIZED_WIRE_30 = db[6] & shift_left;\n\nassign\tSYNTHESIZED_WIRE_29 = db[7] & SYNTHESIZED_WIRE_32;\n\nassign\tSYNTHESIZED_WIRE_31 = shift_in & shift_right;\n\nassign\tSYNTHESIZED_WIRE_32 = ~(shift_right | shift_left);\n\nassign\tout_low_ALTERA_SYNTHESIZED[0] = SYNTHESIZED_WIRE_8 | SYNTHESIZED_WIRE_9 | SYNTHESIZED_WIRE_10;\n\nassign\tout_low_ALTERA_SYNTHESIZED[1] = SYNTHESIZED_WIRE_11 | SYNTHESIZED_WIRE_12 | SYNTHESIZED_WIRE_13;\n\nassign\tout_low_ALTERA_SYNTHESIZED[2] = SYNTHESIZED_WIRE_14 | SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16;\n\nassign\tout_low_ALTERA_SYNTHESIZED[3] = SYNTHESIZED_WIRE_17 | SYNTHESIZED_WIRE_18 | SYNTHESIZED_WIRE_19;\n\nassign\tout_high_ALTERA_SYNTHESIZED[0] = SYNTHESIZED_WIRE_20 | SYNTHESIZED_WIRE_21 | SYNTHESIZED_WIRE_22;\n\nassign\tout_high_ALTERA_SYNTHESIZED[1] = SYNTHESIZED_WIRE_23 | SYNTHESIZED_WIRE_24 | SYNTHESIZED_WIRE_25;\n\nassign\tout_high_ALTERA_SYNTHESIZED[2] = SYNTHESIZED_WIRE_26 | SYNTHESIZED_WIRE_27 | SYNTHESIZED_WIRE_28;\n\nassign\tout_high_ALTERA_SYNTHESIZED[3] = SYNTHESIZED_WIRE_29 | SYNTHESIZED_WIRE_30 | SYNTHESIZED_WIRE_31;\n\nassign\tout_high = out_high_ALTERA_SYNTHESIZED;\nassign\tout_low = out_low_ALTERA_SYNTHESIZED;\n\nendmodule\n"
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    "path": "cpu/alu/alu_slice.bdf",
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  },
  {
    "path": "cpu/alu/alu_slice.bsf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"symbol\" (version \"1.2\"))\n(symbol\n\t(rect 16 16 136 176)\n\t(text \"alu_slice\" (rect 5 0 54 14)(font \"Arial\" (font_size 8)))\n\t(text \"inst\" (rect 8 144 25 156)(font \"Arial\" ))\n\t(port\n\t\t(pt 0 32)\n\t\t(input)\n\t\t(text \"cy_in\" (rect 0 0 30 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"cy_in\" (rect 21 27 51 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 32)(pt 16 32))\n\t)\n\t(port\n\t\t(pt 0 48)\n\t\t(input)\n\t\t(text \"op1\" (rect 0 0 21 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"op1\" (rect 21 43 42 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 48)(pt 16 48))\n\t)\n\t(port\n\t\t(pt 0 64)\n\t\t(input)\n\t\t(text \"op2\" (rect 0 0 21 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"op2\" (rect 21 59 42 73)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 64)(pt 16 64))\n\t)\n\t(port\n\t\t(pt 0 80)\n\t\t(input)\n\t\t(text \"S\" (rect 0 0 8 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"S\" (rect 21 75 29 89)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 80)(pt 16 80))\n\t)\n\t(port\n\t\t(pt 0 96)\n\t\t(input)\n\t\t(text \"V\" (rect 0 0 9 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"V\" (rect 21 91 30 105)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 96)(pt 16 96))\n\t)\n\t(port\n\t\t(pt 0 112)\n\t\t(input)\n\t\t(text \"R\" (rect 0 0 8 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"R\" (rect 21 107 29 121)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 112)(pt 16 112))\n\t)\n\t(port\n\t\t(pt 120 32)\n\t\t(output)\n\t\t(text \"result\" (rect 0 0 31 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"result\" (rect 68 27 99 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 120 32)(pt 104 32))\n\t)\n\t(port\n\t\t(pt 120 48)\n\t\t(output)\n\t\t(text \"cy_out\" (rect 0 0 38 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"cy_out\" (rect 61 43 99 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 120 48)(pt 104 48))\n\t)\n\t(drawing\n\t\t(rectangle (rect 16 16 104 144))\n\t)\n)\n"
  },
  {
    "path": "cpu/alu/alu_slice.v",
    "content": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and other software and tools, and its AMPP partner logic \n// functions, and any output files from any of the foregoing \n// (including device programming or simulation files), and any \n// associated documentation or information are expressly subject \n// to the terms and conditions of the Altera Program License \n// Subscription Agreement, Altera MegaCore Function License \n// Agreement, or other applicable license agreement, including, \n// without limitation, that your use is for the sole purpose of \n// programming logic devices manufactured by Altera and sold by \n// Altera or its authorized distributors.  Please refer to the \n// applicable agreement for further details.\n\n// PROGRAM\t\t\"Quartus II 64-Bit\"\n// VERSION\t\t\"Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\"\n// CREATED\t\t\"Mon Oct 13 11:51:12 2014\"\n\nmodule alu_slice(\n\top2,\n\top1,\n\tcy_in,\n\tR,\n\tS,\n\tV,\n\tcy_out,\n\tresult\n);\n\n\ninput wire\top2;\ninput wire\top1;\ninput wire\tcy_in;\ninput wire\tR;\ninput wire\tS;\ninput wire\tV;\noutput wire\tcy_out;\noutput wire\tresult;\n\nwire\tSYNTHESIZED_WIRE_0;\nwire\tSYNTHESIZED_WIRE_1;\nwire\tSYNTHESIZED_WIRE_2;\nwire\tSYNTHESIZED_WIRE_3;\nwire\tSYNTHESIZED_WIRE_4;\nwire\tSYNTHESIZED_WIRE_5;\nwire\tSYNTHESIZED_WIRE_10;\nwire\tSYNTHESIZED_WIRE_7;\nwire\tSYNTHESIZED_WIRE_8;\n\n\n\n\nassign\tSYNTHESIZED_WIRE_0 = op2 | cy_in | op1;\n\nassign\tSYNTHESIZED_WIRE_3 = SYNTHESIZED_WIRE_0 & SYNTHESIZED_WIRE_1;\n\nassign\tSYNTHESIZED_WIRE_4 = cy_in & op2 & op1;\n\nassign\tresult =  ~SYNTHESIZED_WIRE_2;\n\nassign\tSYNTHESIZED_WIRE_2 = ~(SYNTHESIZED_WIRE_3 | SYNTHESIZED_WIRE_4);\n\nassign\tSYNTHESIZED_WIRE_5 = op2 | op1;\n\nassign\tSYNTHESIZED_WIRE_7 = cy_in & SYNTHESIZED_WIRE_5;\n\nassign\tSYNTHESIZED_WIRE_8 = op1 & op2;\n\nassign\tcy_out = ~(R | SYNTHESIZED_WIRE_10);\n\nassign\tSYNTHESIZED_WIRE_10 = ~(SYNTHESIZED_WIRE_7 | SYNTHESIZED_WIRE_8 | S);\n\nassign\tSYNTHESIZED_WIRE_1 = V | SYNTHESIZED_WIRE_10;\n\n\nendmodule\n"
  },
  {
    "path": "cpu/alu/simulation/modelsim/r",
    "content": "restart -f ; run -all\n"
  },
  {
    "path": "cpu/alu/simulation/modelsim/test_alu.mpf",
    "content": "; Copyright 1991-2009 Mentor Graphics Corporation\n;\n; All Rights Reserved.\n;\n; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF\n; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.\n;\n\n[Library]\nstd = $MODEL_TECH/../std\nieee = $MODEL_TECH/../ieee\nverilog = $MODEL_TECH/../verilog\nvital2000 = $MODEL_TECH/../vital2000\nstd_developerskit = $MODEL_TECH/../std_developerskit\nsynopsys = $MODEL_TECH/../synopsys\nmodelsim_lib = $MODEL_TECH/../modelsim_lib\nsv_std = $MODEL_TECH/../sv_std\n\n; Altera Primitive libraries\n;\n; VHDL Section\n;\naltera_mf = $MODEL_TECH/../altera/vhdl/altera_mf\naltera = $MODEL_TECH/../altera/vhdl/altera\naltera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim\nlpm = $MODEL_TECH/../altera/vhdl/220model\n220model = $MODEL_TECH/../altera/vhdl/220model\nmax = $MODEL_TECH/../altera/vhdl/max\nmaxii = $MODEL_TECH/../altera/vhdl/maxii\nmaxv = $MODEL_TECH/../altera/vhdl/maxv\nstratix = $MODEL_TECH/../altera/vhdl/stratix\nstratixii = $MODEL_TECH/../altera/vhdl/stratixii\nstratixiigx = $MODEL_TECH/../altera/vhdl/stratixiigx\nhardcopyii = $MODEL_TECH/../altera/vhdl/hardcopyii\nhardcopyiii = $MODEL_TECH/../altera/vhdl/hardcopyiii\nhardcopyiv = $MODEL_TECH/../altera/vhdl/hardcopyiv\ncyclone = $MODEL_TECH/../altera/vhdl/cyclone\ncycloneii = $MODEL_TECH/../altera/vhdl/cycloneii\ncycloneiii = $MODEL_TECH/../altera/vhdl/cycloneiii\ncycloneiiils = $MODEL_TECH/../altera/vhdl/cycloneiiils\nsgate = $MODEL_TECH/../altera/vhdl/sgate\nstratixgx = $MODEL_TECH/../altera/vhdl/stratixgx\naltgxb = $MODEL_TECH/../altera/vhdl/altgxb\nstratixgx_gxb = $MODEL_TECH/../altera/vhdl/stratixgx_gxb\nstratixiigx_hssi = $MODEL_TECH/../altera/vhdl/stratixiigx_hssi\narriagx_hssi = $MODEL_TECH/../altera/vhdl/arriagx_hssi\narriaii = $MODEL_TECH/../altera/vhdl/arriaii\narriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi\narriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip\narriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz\narriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi\narriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip\narriagx = $MODEL_TECH/../altera/vhdl/arriagx\naltgxb_lib = $MODEL_TECH/../altera/vhdl/altgxb\nstratixiv = $MODEL_TECH/../altera/vhdl/stratixiv\nstratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi\nstratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip\ncycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv\ncycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi\ncycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip\ncycloneive = $MODEL_TECH/../altera/vhdl/cycloneive\nhardcopyiv_hssi = $MODEL_TECH/../altera/vhdl/hardcopyiv_hssi\nhardcopyiv_pcie_hip = $MODEL_TECH/../altera/vhdl/hardcopyiv_pcie_hip\nstratixv = $MODEL_TECH/../altera/vhdl/stratixv\nstratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi\nstratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip\narriavgz = $MODEL_TECH/../altera/vhdl/arriavgz\narriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi\narriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip\narriav = $MODEL_TECH/../altera/vhdl/arriav\ncyclonev = $MODEL_TECH/../altera/vhdl/cyclonev\n;\n; Verilog Section\n;\naltera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf\naltera_ver = $MODEL_TECH/../altera/verilog/altera\naltera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim\nlpm_ver = $MODEL_TECH/../altera/verilog/220model\n220model_ver = $MODEL_TECH/../altera/verilog/220model\nmax_ver = $MODEL_TECH/../altera/verilog/max\nmaxii_ver = $MODEL_TECH/../altera/verilog/maxii\nmaxv_ver = $MODEL_TECH/../altera/verilog/maxv\nstratix_ver = $MODEL_TECH/../altera/verilog/stratix\nstratixii_ver = $MODEL_TECH/../altera/verilog/stratixii\nstratixiigx_ver = $MODEL_TECH/../altera/verilog/stratixiigx\narriagx_ver = $MODEL_TECH/../altera/verilog/arriagx\nhardcopyii_ver = $MODEL_TECH/../altera/verilog/hardcopyii\nhardcopyiii_ver = $MODEL_TECH/../altera/verilog/hardcopyiii\nhardcopyiv_ver = $MODEL_TECH/../altera/verilog/hardcopyiv\ncyclone_ver = $MODEL_TECH/../altera/verilog/cyclone\ncycloneii_ver = $MODEL_TECH/../altera/verilog/cycloneii\ncycloneiii_ver = $MODEL_TECH/../altera/verilog/cycloneiii\ncycloneiiils_ver = $MODEL_TECH/../altera/verilog/cycloneiiils\nsgate_ver = $MODEL_TECH/../altera/verilog/sgate\nstratixgx_ver = $MODEL_TECH/../altera/verilog/stratixgx\naltgxb_ver = $MODEL_TECH/../altera/verilog/altgxb\nstratixgx_gxb_ver = $MODEL_TECH/../altera/verilog/stratixgx_gxb\nstratixiigx_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiigx_hssi\narriagx_hssi_ver = $MODEL_TECH/../altera/verilog/arriagx_hssi\narriaii_ver = $MODEL_TECH/../altera/verilog/arriaii\narriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi\narriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip\narriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz\narriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi\narriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip\nstratixiii_ver = $MODEL_TECH/../altera/verilog/stratixiii\nstratixiii = $MODEL_TECH/../altera/vhdl/stratixiii\nstratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv\nstratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi\nstratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip\nstratixv_ver = $MODEL_TECH/../altera/verilog/stratixv\nstratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi\nstratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip\narriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz\narriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi\narriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip\narriav_ver = $MODEL_TECH/../altera/verilog/arriav\narriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi\narriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip\ncyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev\ncyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi\ncyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip\ncycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv\ncycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi\ncycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip\ncycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive\nhardcopyiv_hssi_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_hssi\nhardcopyiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_pcie_hip\n\nwork = work\n[vcom]\n; VHDL93 variable selects language version as the default.\n; Default is VHDL-2002.\n; Value of 0 or 1987 for VHDL-1987.\n; Value of 1 or 1993 for VHDL-1993.\n; Default or value of 2 or 2002 for VHDL-2002.\n; Default or value of 3 or 2008 for VHDL-2008.\nVHDL93 = 2002\n\n; Show source line containing error. Default is off.\n; Show_source = 1\n\n; Turn off unbound-component warnings. Default is on.\n; Show_Warning1 = 0\n\n; Turn off process-without-a-wait-statement warnings. Default is on.\n; Show_Warning2 = 0\n\n; Turn off null-range warnings. Default is on.\n; Show_Warning3 = 0\n\n; Turn off no-space-in-time-literal warnings. Default is on.\n; Show_Warning4 = 0\n\n; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.\n; Show_Warning5 = 0\n\n; Turn off optimization for IEEE std_logic_1164 package. Default is on.\n; Optimize_1164 = 0\n\n; Turn on resolving of ambiguous function overloading in favor of the\n; \"explicit\" function declaration (not the one automatically created by\n; the compiler for each type declaration). Default is off.\n; The .ini file has Explicit enabled so that std_logic_signed/unsigned\n; will match the behavior of synthesis tools.\nExplicit = 1\n\n; Turn off acceleration of the VITAL packages. Default is to accelerate.\n; NoVital = 1\n\n; Turn off VITAL compliance checking. Default is checking on.\n; NoVitalCheck = 1\n\n; Ignore VITAL compliance checking errors. Default is to not ignore.\n; IgnoreVitalErrors = 1\n\n; Turn off VITAL compliance checking warnings. Default is to show warnings.\n; Show_VitalChecksWarnings = 0\n\n; Keep silent about case statement static warnings.\n; Default is to give a warning.\n; NoCaseStaticError = 1\n\n; Keep silent about warnings caused by aggregates that are not locally static.\n; Default is to give a warning.\n; NoOthersStaticError = 1\n\n; Turn off inclusion of debugging info within design units.\n; Default is to include debugging info.\n; NoDebug = 1\n\n; Turn off \"Loading...\" messages. Default is messages on.\n; Quiet = 1\n\n; Turn on some limited synthesis rule compliance checking. Checks only:\n;    -- signals used (read) by a process must be in the sensitivity list\n; CheckSynthesis = 1\n\n; Activate optimizations on expressions that do not involve signals,\n; waits, or function/procedure/task invocations. Default is off.\n; ScalarOpts = 1\n\n; Require the user to specify a configuration for all bindings,\n; and do not generate a compile time default binding for the\n; component. This will result in an elaboration error of\n; 'component not bound' if the user fails to do so. Avoids the rare\n; issue of a false dependency upon the unused default binding.\n; RequireConfigForAllDefaultBinding = 1\n\n; Inhibit range checking on subscripts of arrays. Range checking on\n; scalars defined with subtypes is inhibited by default.\n; NoIndexCheck = 1\n\n; Inhibit range checks on all (implicit and explicit) assignments to\n; scalar objects defined with subtypes.\n; NoRangeCheck = 1\n\n[vlog]\n\n; Turn off inclusion of debugging info within design units.\n; Default is to include debugging info.\n; NoDebug = 1\n\n; Turn off \"loading...\" messages. Default is messages on.\n; Quiet = 1\n\n; Turn on Verilog hazard checking (order-dependent accessing of global vars).\n; Default is off.\n; Hazard = 1\n\n; Turn on converting regular Verilog identifiers to uppercase. Allows case\n; insensitivity for module names. Default is no conversion.\n; UpCase = 1\n\n; Turn on incremental compilation of modules. Default is off.\n; Incremental = 1\n\n; Turns on lint-style checking.\n; Show_Lint = 1\n\n[vsim]\n; Simulator resolution\n; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.\nResolution = ps\n\n; User time unit for run commands\n; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the\n; unit specified for Resolution. For example, if Resolution is 100ps,\n; then UserTimeUnit defaults to ps.\n; Should generally be set to default.\nUserTimeUnit = default\n\n; Default run length\nRunLength = 0 ns\n\n; Maximum iterations that can be run without advancing simulation time\nIterationLimit = 5000\n\n; Directive to license manager:\n; vhdl          Immediately reserve a VHDL license\n; vlog          Immediately reserve a Verilog license\n; plus          Immediately reserve a VHDL and Verilog license\n; nomgc         Do not look for Mentor Graphics Licenses\n; nomti         Do not look for Model Technology Licenses\n; noqueue       Do not wait in the license queue when a license isn't available\n; viewsim\tTry for viewer license but accept simulator license(s) instead\n;\t\tof queuing for viewer license\n; License = plus\n\n; Stop the simulator after a VHDL/Verilog assertion message\n; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal\nBreakOnAssertion = 3\n\n; Assertion Message Format\n; %S - Severity Level\n; %R - Report Message\n; %T - Time of assertion\n; %D - Delta\n; %I - Instance or Region pathname (if available)\n; %% - print '%' character\n; AssertionFormat = \"** %S: %R\\n   Time: %T  Iteration: %D%I\\n\"\n\n; Assertion File - alternate file for storing VHDL/Verilog assertion messages\n; AssertFile = assert.log\n\n; Default radix for all windows and commands...\n; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned\nDefaultRadix = symbolic\n\n; VSIM Startup command\n; Startup = do startup.do\n\n; File for saving command transcript\nTranscriptFile = transcript\n\n; File for saving command history\n; CommandHistory = cmdhist.log\n\n; Specify whether paths in simulator commands should be described\n; in VHDL or Verilog format.\n; For VHDL, PathSeparator = /\n; For Verilog, PathSeparator = .\n; Must not be the same character as DatasetSeparator.\nPathSeparator = /\n\n; Specify the dataset separator for fully rooted contexts.\n; The default is ':'. For example, sim:/top\n; Must not be the same character as PathSeparator.\nDatasetSeparator = :\n\n; Disable VHDL assertion messages\n; IgnoreNote = 1\n; IgnoreWarning = 1\n; IgnoreError = 1\n; IgnoreFailure = 1\n\n; Default force kind. May be freeze, drive, deposit, or default\n; or in other terms, fixed, wired, or charged.\n; A value of \"default\" will use the signal kind to determine the\n; force kind, drive for resolved signals, freeze for unresolved signals\n; DefaultForceKind = freeze\n\n; If zero, open files when elaborated; otherwise, open files on\n; first read or write.  Default is 0.\n; DelayFileOpen = 1\n\n; Control VHDL files opened for write.\n;   0 = Buffered, 1 = Unbuffered\nUnbufferedOutput = 0\n\n; Control the number of VHDL files open concurrently.\n; This number should always be less than the current ulimit\n; setting for max file descriptors.\n;   0 = unlimited\nConcurrentFileLimit = 40\n\n; Control the number of hierarchical regions displayed as\n; part of a signal name shown in the Wave window.\n; A value of zero tells VSIM to display the full name.\n; The default is 0.\n; WaveSignalNameWidth = 0\n\n; Turn off warnings from the std_logic_arith, std_logic_unsigned\n; and std_logic_signed packages.\n; StdArithNoWarnings = 1\n\n; Turn off warnings from the IEEE numeric_std and numeric_bit packages.\n; NumericStdNoWarnings = 1\n\n; Control the format of the (VHDL) FOR generate statement label\n; for each iteration.  Do not quote it.\n; The format string here must contain the conversion codes %s and %d,\n; in that order, and no other conversion codes.  The %s represents\n; the generate_label; the %d represents the generate parameter value\n; at a particular generate iteration (this is the position number if\n; the generate parameter is of an enumeration type).  Embedded whitespace\n; is allowed (but discouraged); leading and trailing whitespace is ignored.\n; Application of the format must result in a unique scope name over all\n; such names in the design so that name lookup can function properly.\n; GenerateFormat = %s__%d\n\n; Specify whether checkpoint files should be compressed.\n; The default is 1 (compressed).\n; CheckpointCompressMode = 0\n\n; List of dynamically loaded objects for Verilog PLI applications\n; Veriuser = veriuser.sl\n\n; Specify default options for the restart command. Options can be one\n; or more of: -force -nobreakpoint -nolist -nolog -nowave\n; DefaultRestartOptions = -force\n\n; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs\n; (> 500 megabyte memory footprint). Default is disabled.\n; Specify number of megabytes to lock.\n; LockedMemory = 1000\n\n; Turn on (1) or off (0) WLF file compression.\n; The default is 1 (compress WLF file).\n; WLFCompress = 0\n\n; Specify whether to save all design hierarchy (1) in the WLF file\n; or only regions containing logged signals (0).\n; The default is 0 (save only regions with logged signals).\n; WLFSaveAllRegions = 1\n\n; WLF file time limit.  Limit WLF file by time, as closely as possible,\n; to the specified amount of simulation time.  When the limit is exceeded\n; the earliest times get truncated from the file.\n; If both time and size limits are specified the most restrictive is used.\n; UserTimeUnits are used if time units are not specified.\n; The default is 0 (no limit).  Example: WLFTimeLimit = {100 ms}\n; WLFTimeLimit = 0\n\n; WLF file size limit.  Limit WLF file size, as closely as possible,\n; to the specified number of megabytes.  If both time and size limits\n; are specified then the most restrictive is used.\n; The default is 0 (no limit).\n; WLFSizeLimit = 1000\n\n; Specify whether or not a WLF file should be deleted when the\n; simulation ends.  A value of 1 will cause the WLF file to be deleted.\n; The default is 0 (do not delete WLF file when simulation ends).\n; WLFDeleteOnQuit = 1\n\n; Automatic SDF compilation\n; Disables automatic compilation of SDF files in flows that support it.\n; Default is on, uncomment to turn off.\n; NoAutoSDFCompile = 1\n\n[lmc]\n\n[msg_system]\n; Change a message severity or suppress a message.\n; The format is: <msg directive> = <msg number>[,<msg number>...]\n; Examples:\n;   note = 3009\n;   warning = 3033\n;   error = 3010,3016\n;   fatal = 3016,3033\n;   suppress = 3009,3016,3043\n; The command verror <msg number> can be used to get the complete\n; description of a message.\n\n; Control transcripting of elaboration/runtime messages.\n; The default is to have messages appear in the transcript and\n; recorded in the wlf file (messages that are recorded in the\n; wlf file can be viewed in the MsgViewer).  The other settings\n; are to send messages only to the transcript or only to the\n; wlf file.  The valid values are\n;    both  {default}\n;    tran  {transcript only}\n;    wlf   {wlf file only}\n; msgmode = both\n[Project]\n; Warning -- Do not edit the project properties directly.\n;            Property names are dynamic in nature and property\n;            values have special syntax.  Changing property data directly\n;            can result in a corrupt MPF file.  All project properties\n;            can be modified through project window dialogs.\nProject_Version = 6\nProject_DefaultLib = work\nProject_SortMethod = unused\nProject_Files_Count = 14\nProject_File_0 = $ROOT/cpu/alu/alu.v\nProject_File_P_0 = compile_order 11 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {ALU Complete} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_1 = $ROOT/cpu/alu/alu_bit_select.v\nProject_File_P_1 = compile_order 12 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {ALU Complete} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_2 = $ROOT/cpu/alu/alu_core.v\nProject_File_P_2 = compile_order 2 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_3 = $ROOT/cpu/alu/alu_mux_2z.v\nProject_File_P_3 = compile_order 13 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {ALU Complete} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_4 = $ROOT/cpu/alu/alu_mux_3z.v\nProject_File_P_4 = compile_order 7 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder misc group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_5 = $ROOT/cpu/alu/alu_prep_daa.v\nProject_File_P_5 = compile_order 8 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder misc group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_6 = $ROOT/cpu/alu/alu_shifter_core.v\nProject_File_P_6 = compile_order 4 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder shifter group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_7 = $ROOT/cpu/alu/alu_slice.v\nProject_File_P_7 = compile_order 0 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_8 = $ROOT/cpu/alu/test_alu.sv\nProject_File_P_8 = compile_order 10 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder {ALU Complete} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 1 vlog_enable0In 0 vlog_hazard 1 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_9 = $ROOT/cpu/alu/test_core.sv\nProject_File_P_9 = compile_order 3 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_10 = $ROOT/cpu/alu/test_mux_3z.sv\nProject_File_P_10 = compile_order 6 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder misc group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_11 = $ROOT/cpu/alu/test_prep_daa.sv\nProject_File_P_11 = compile_order 9 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder misc group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_12 = $ROOT/cpu/alu/test_shifter_core.sv\nProject_File_P_12 = compile_order 5 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder shifter group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_13 = $ROOT/cpu/alu/test_slice.sv\nProject_File_P_13 = compile_order 1 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_Sim_Count = 6\nProject_Sim_0 = Test slice\nProject_Sim_P_0 = timing default -t default -sdfnoerror 0 -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder alu +pulse_e {} additional_dus work.test_slice -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {}\nProject_Sim_1 = Test core\nProject_Sim_P_1 = timing default -sdfnoerror 0 -t default -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder alu +pulse_e {} additional_dus work.test_core -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {}\nProject_Sim_2 = Test prep daa\nProject_Sim_P_2 = timing default cover_exttoggle 0 vlog_nodebug 0 last_compile 1418395911 -t default -sdfnoerror 0 compile_to work -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} file_type systemverilog +notimingchecks 0 cover_cond 0 ok 1 folder misc vlog_noload 0 cover_fsm 0 cover_excludedefault 0 +pulse_e {} cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 compile_order 3 additional_dus work.test_prep_daa -assertfile {} cover_toggle 0 vlog_protect 0 -std_output {} -L {} -nopsl 0 -nosva 0 -absentisempty 0 +pulse_r {} -assertcover 0 vlog_disableopt 0 OtherArgs {} -multisource_delay {} -vital2.2b 0 voptflow 1 ood 0 -memprof 0 is_vopt_flow 0 vlog_upper 0 -noglitch 0 -0in_options {} selected_du {} cover_nofec 0 group_id 0 -hazards 0 -sdf {} vlog_1995compat SV -0in 0 cover_branch 0 vlog_enable0In 0 cover_covercells 0 +plusarg {} -coverage 0 vopt_env 1 toggle - vlog_0InOptions {} cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 -wlf {} -assertdebug 0 cover_stmt 0 -std_input {} -sdfnowarn 0\nProject_Sim_3 = Test ALU\nProject_Sim_P_3 = timing default -sdfnoerror 0 -t default -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder {ALU Complete} +pulse_e {} additional_dus work.test_alu -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {}\nProject_Sim_4 = Test shifter core\nProject_Sim_P_4 = timing default -t default -sdfnoerror 0 -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder shifter +pulse_e {} additional_dus work.test_shifter_core -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {}\nProject_Sim_5 = Test mux 3z\nProject_Sim_P_5 = timing default cover_exttoggle 0 vlog_nodebug 0 last_compile 1418395911 -t default -sdfnoerror 0 compile_to work -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} file_type systemverilog +notimingchecks 0 cover_cond 0 ok 1 folder misc vlog_noload 0 cover_fsm 0 cover_excludedefault 0 +pulse_e {} cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 compile_order 3 additional_dus work.test_mux_3z -assertfile {} cover_toggle 0 vlog_protect 0 -std_output {} -L {} -nopsl 0 -nosva 0 -absentisempty 0 +pulse_r {} -assertcover 0 vlog_disableopt 0 OtherArgs {} -multisource_delay {} -vital2.2b 0 voptflow 1 ood 0 -memprof 0 is_vopt_flow 0 vlog_upper 0 -noglitch 0 -0in_options {} selected_du {} cover_nofec 0 group_id 0 -hazards 0 -sdf {} vlog_1995compat SV -0in 0 cover_branch 0 vlog_enable0In 0 cover_covercells 0 +plusarg {} -coverage 0 vopt_env 1 toggle - vlog_0InOptions {} cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 -wlf {} -assertdebug 0 cover_stmt 0 -std_input {} -sdfnowarn 0\nProject_Folder_Count = 4\nProject_Folder_0 = misc\nProject_Folder_P_0 = folder {Top Level}\nProject_Folder_1 = shifter\nProject_Folder_P_1 = folder {Top Level}\nProject_Folder_2 = alu\nProject_Folder_P_2 = folder {Top Level}\nProject_Folder_3 = ALU Complete\nProject_Folder_P_3 = folder {Top Level}\nEcho_Compile_Output = 0\nSave_Compile_Report = 1\nProject_Opt_Count = 0\nForceSoftPaths = 1\nProjectStatusDelay = 5000\nVERILOG_DoubleClick = Edit\nVERILOG_CustomDoubleClick =\nSYSTEMVERILOG_DoubleClick = Edit\nSYSTEMVERILOG_CustomDoubleClick =\nVHDL_DoubleClick = Edit\nVHDL_CustomDoubleClick =\nPSL_DoubleClick = Edit\nPSL_CustomDoubleClick =\nTEXT_DoubleClick = Edit\nTEXT_CustomDoubleClick =\nSYSTEMC_DoubleClick = Edit\nSYSTEMC_CustomDoubleClick =\nTCL_DoubleClick = Edit\nTCL_CustomDoubleClick =\nMACRO_DoubleClick = Edit\nMACRO_CustomDoubleClick =\nVCD_DoubleClick = Edit\nVCD_CustomDoubleClick =\nSDF_DoubleClick = Edit\nSDF_CustomDoubleClick =\nXML_DoubleClick = Edit\nXML_CustomDoubleClick =\nLOGFILE_DoubleClick = Edit\nLOGFILE_CustomDoubleClick =\nUCDB_DoubleClick = Edit\nUCDB_CustomDoubleClick =\nUPF_DoubleClick = Edit\nUPF_CustomDoubleClick =\nPCF_DoubleClick = Edit\nPCF_CustomDoubleClick =\nPROJECT_DoubleClick = Edit\nPROJECT_CustomDoubleClick =\nVRM_DoubleClick = Edit\nVRM_CustomDoubleClick =\nDEBUGDATABASE_DoubleClick = Edit\nDEBUGDATABASE_CustomDoubleClick =\nDEBUGARCHIVE_DoubleClick = Edit\nDEBUGARCHIVE_CustomDoubleClick =\nProject_Major_Version = 10\nProject_Minor_Version = 1\n"
  },
  {
    "path": "cpu/alu/simulation/modelsim/wave_alu.do",
    "content": "onerror {resume}\nquietly virtual signal -install /test_alu { (context /test_alu )&{test_db_low ,test_db_high }} test_bus\nquietly virtual signal -install /test_alu { (context /test_alu )&{test_db_high ,test_db_low }} test_bus001\nquietly virtual function -install /test_alu/alu_inst -env /test_alu { &{/test_alu/alu_inst/op1_high, /test_alu/alu_inst/op1_low }} OP1\nquietly virtual function -install /test_alu/alu_inst -env /test_alu { &{/test_alu/alu_inst/op2_high, /test_alu/alu_inst/op2_low }} OP2\nquietly virtual function -install /test_alu/alu_inst -env /test_alu { &{/test_alu/alu_inst/result_hi, /test_alu/alu_inst/result_lo }} RESULT\nquietly WaveActivateNextPane {} 0\nadd wave -noupdate -color Gold -itemcolor Gold -radix hexadecimal -childformat {{{/test_alu/db_w[7]} -radix hexadecimal} {{/test_alu/db_w[6]} -radix hexadecimal} {{/test_alu/db_w[5]} -radix hexadecimal} {{/test_alu/db_w[4]} -radix hexadecimal} {{/test_alu/db_w[3]} -radix hexadecimal} {{/test_alu/db_w[2]} -radix hexadecimal} {{/test_alu/db_w[1]} -radix hexadecimal} {{/test_alu/db_w[0]} -radix hexadecimal}} -subitemconfig {{/test_alu/db_w[7]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal} {/test_alu/db_w[6]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal} {/test_alu/db_w[5]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal} {/test_alu/db_w[4]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal} {/test_alu/db_w[3]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal} {/test_alu/db_w[2]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal} {/test_alu/db_w[1]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal} {/test_alu/db_w[0]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal}} /test_alu/db_w\nadd wave -noupdate -color Gold -itemcolor Gold -radix hexadecimal -childformat {{{/test_alu/db[7]} -radix hexadecimal} {{/test_alu/db[6]} -radix hexadecimal} {{/test_alu/db[5]} -radix hexadecimal} {{/test_alu/db[4]} -radix hexadecimal} {{/test_alu/db[3]} -radix hexadecimal} {{/test_alu/db[2]} -radix hexadecimal} {{/test_alu/db[1]} -radix hexadecimal} {{/test_alu/db[0]} -radix hexadecimal}} -subitemconfig {{/test_alu/db[7]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal} {/test_alu/db[6]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal} {/test_alu/db[5]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal} {/test_alu/db[4]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal} {/test_alu/db[3]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal} {/test_alu/db[2]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal} {/test_alu/db[1]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal} {/test_alu/db[0]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal}} /test_alu/db\nadd wave -noupdate -color {Medium Orchid} -itemcolor Gold -label test_bus -radix hexadecimal -childformat {{{/test_alu/test_bus001[7]} -radix hexadecimal} {{/test_alu/test_bus001[6]} -radix hexadecimal} {{/test_alu/test_bus001[5]} -radix hexadecimal} {{/test_alu/test_bus001[4]} -radix hexadecimal} {{/test_alu/test_bus001[3]} -radix hexadecimal} {{/test_alu/test_bus001[2]} -radix hexadecimal} {{/test_alu/test_bus001[1]} -radix hexadecimal} {{/test_alu/test_bus001[0]} -radix hexadecimal}} -subitemconfig {{/test_alu/test_db_high[3]} {-color {Medium Orchid} -itemcolor Gold -radix hexadecimal} {/test_alu/test_db_high[2]} {-color {Medium Orchid} -itemcolor Gold -radix hexadecimal} {/test_alu/test_db_high[1]} {-color {Medium Orchid} -itemcolor Gold -radix hexadecimal} {/test_alu/test_db_high[0]} {-color {Medium Orchid} -itemcolor Gold -radix hexadecimal} {/test_alu/test_db_low[3]} {-color {Medium Orchid} -itemcolor Gold -radix hexadecimal} {/test_alu/test_db_low[2]} {-color {Medium Orchid} -itemcolor Gold -radix hexadecimal} {/test_alu/test_db_low[1]} {-color {Medium Orchid} -itemcolor Gold -radix hexadecimal} {/test_alu/test_db_low[0]} {-color {Medium Orchid} -itemcolor Gold -radix hexadecimal}} /test_alu/test_bus001\nadd wave -noupdate /test_alu/clk\nadd wave -noupdate -expand -group Registers -color Pink -radix hexadecimal /test_alu/alu_inst/alu_op1\nadd wave -noupdate -expand -group Registers -color Pink -radix hexadecimal /test_alu/alu_inst/alu_op2\nadd wave -noupdate -expand -group Registers -radix hexadecimal -childformat {{(7) -radix hexadecimal} {(6) -radix hexadecimal} {(5) -radix hexadecimal} {(4) -radix hexadecimal} {(3) -radix hexadecimal} {(2) -radix hexadecimal} {(1) -radix hexadecimal} {(0) -radix hexadecimal}} -subitemconfig {{/test_alu/alu_inst/op1_high[3]} {-radix hexadecimal} {/test_alu/alu_inst/op1_high[2]} {-radix hexadecimal} {/test_alu/alu_inst/op1_high[1]} {-radix hexadecimal} {/test_alu/alu_inst/op1_high[0]} {-radix hexadecimal} {/test_alu/alu_inst/op1_low[3]} {-radix hexadecimal} {/test_alu/alu_inst/op1_low[2]} {-radix hexadecimal} {/test_alu/alu_inst/op1_low[1]} {-radix hexadecimal} {/test_alu/alu_inst/op1_low[0]} {-radix hexadecimal}} /test_alu/alu_inst/OP1\nadd wave -noupdate -expand -group Registers -radix hexadecimal /test_alu/alu_inst/OP2\nadd wave -noupdate -radix hexadecimal /test_alu/alu_inst/result_hi\nadd wave -noupdate -radix hexadecimal /test_alu/alu_inst/result_lo\nadd wave -noupdate -expand -group {Bus control} /test_alu/alu_oe\nadd wave -noupdate -expand -group {Bus control} /test_alu/alu_op1_oe\nadd wave -noupdate -expand -group {Bus control} /test_alu/alu_op2_oe\nadd wave -noupdate -expand -group {Bus control} /test_alu/alu_res_oe\nadd wave -noupdate -expand -group {Bus control} /test_alu/alu_shift_oe\nadd wave -noupdate -expand -group {Bus control} /test_alu/alu_bs_oe\nadd wave -noupdate -expand -group {Input shifter} /test_alu/alu_shift_db0\nadd wave -noupdate -expand -group {Input shifter} /test_alu/alu_shift_db7\nadd wave -noupdate -expand -group {Input shifter} /test_alu/alu_shift_in\nadd wave -noupdate -expand -group {Input shifter} /test_alu/alu_shift_right\nadd wave -noupdate -expand -group {Input shifter} /test_alu/alu_shift_left\nadd wave -noupdate /test_alu/bsel\nadd wave -noupdate -expand -group {Operand selectors} /test_alu/alu_op1_sel_bus\nadd wave -noupdate -expand -group {Operand selectors} /test_alu/alu_op1_sel_low\nadd wave -noupdate -expand -group {Operand selectors} /test_alu/alu_op1_sel_zero\nadd wave -noupdate -expand -group {Operand selectors} /test_alu/alu_op2_sel_bus\nadd wave -noupdate -expand -group {Operand selectors} /test_alu/alu_op2_sel_lq\nadd wave -noupdate -expand -group {Operand selectors} /test_alu/alu_op2_sel_zero\nadd wave -noupdate -expand -group {ALU core} /test_alu/alu_core_R\nadd wave -noupdate -expand -group {ALU core} /test_alu/alu_core_S\nadd wave -noupdate -expand -group {ALU core} /test_alu/alu_core_V\nadd wave -noupdate -expand -group {ALU core} /test_alu/alu_sel_op2_neg\nadd wave -noupdate -expand -group {ALU core} /test_alu/alu_sel_op2_high\nadd wave -noupdate -expand -group {ALU core} /test_alu/alu_op_low\nadd wave -noupdate -expand -group Flags /test_alu/alu_core_cf_in\nadd wave -noupdate -expand -group Flags /test_alu/alu_core_cf_out\nadd wave -noupdate -expand -group Flags /test_alu/alu_parity_in\nadd wave -noupdate -expand -group Flags /test_alu/alu_parity_out\nadd wave -noupdate -expand -group Flags /test_alu/alu_zero\nadd wave -noupdate -expand -group Flags /test_alu/alu_vf_out\nadd wave -noupdate -expand -group Flags /test_alu/alu_sf_out\nadd wave -noupdate -expand -group Flags /test_alu/alu_xf_out\nadd wave -noupdate -expand -group Flags /test_alu/alu_yf_out\nadd wave -noupdate -expand -group Flags /test_alu/alu_low_gt_9\nadd wave -noupdate -expand -group Flags /test_alu/alu_high_gt_9\nadd wave -noupdate -expand -group Flags /test_alu/alu_high_eq_9\nadd wave -noupdate /test_alu/cf\nadd wave -noupdate /test_alu/pf\nadd wave -noupdate /test_alu/hf\nTreeUpdate [SetDefaultTree]\nWaveRestoreCursors {{Cursor 1} {1800 ns} 0}\nquietly wave cursor active 1\nconfigure wave -namecolwidth 180\nconfigure wave -valuecolwidth 58\nconfigure wave -justifyvalue right\nconfigure wave -signalnamewidth 1\nconfigure wave -snapdistance 10\nconfigure wave -datasetprefix 0\nconfigure wave -rowmargin 4\nconfigure wave -childrowmargin 2\nconfigure wave -gridoffset 0\nconfigure wave -gridperiod 1\nconfigure wave -griddelta 40\nconfigure wave -timeline 1\nconfigure wave -timelineunits us\nupdate\nWaveRestoreZoom {0 ns} {4800 ns}\n"
  },
  {
    "path": "cpu/alu/simulation/modelsim/wave_core.do",
    "content": "onerror {resume}\nquietly WaveActivateNextPane {} 0\nadd wave -noupdate -radix hexadecimal /test_core/op1_sig\nadd wave -noupdate -radix hexadecimal /test_core/op2_sig\nadd wave -noupdate /test_core/cy_in_sig\nadd wave -noupdate -color Gold -itemcolor Gold -radix hexadecimal /test_core/result_sig\nadd wave -noupdate -color Gold -format Literal -itemcolor Gold /test_core/cy_out_sig\nadd wave -noupdate -color Gray75 -itemcolor Gray75 /test_core/vf_out_sig\nadd wave -noupdate /test_core/R_sig\nadd wave -noupdate /test_core/S_sig\nadd wave -noupdate /test_core/V_sig\nTreeUpdate [SetDefaultTree]\nWaveRestoreCursors {{Cursor 1} {2000 ns} 0}\nquietly wave cursor active 1\nconfigure wave -namecolwidth 140\nconfigure wave -valuecolwidth 53\nconfigure wave -justifyvalue right\nconfigure wave -signalnamewidth 1\nconfigure wave -snapdistance 10\nconfigure wave -datasetprefix 0\nconfigure wave -rowmargin 4\nconfigure wave -childrowmargin 2\nconfigure wave -gridoffset 0\nconfigure wave -gridperiod 1\nconfigure wave -griddelta 40\nconfigure wave -timeline 1\nconfigure wave -timelineunits us\nupdate\nWaveRestoreZoom {0 ns} {4400 ns}\n"
  },
  {
    "path": "cpu/alu/simulation/modelsim/wave_mux_3z.do",
    "content": "onerror {resume}\nquietly WaveActivateNextPane {} 0\nadd wave -noupdate -radix hexadecimal /test_mux_3z/a_sig\nadd wave -noupdate -radix hexadecimal /test_mux_3z/b_sig\nadd wave -noupdate -color Gold -itemcolor Gold -radix hexadecimal /test_mux_3z/Q_sig\nadd wave -noupdate /test_mux_3z/sel_a_sig\nadd wave -noupdate /test_mux_3z/sel_b_sig\nadd wave -noupdate /test_mux_3z/sel_zero_sig\nadd wave -noupdate /test_mux_3z/ena_out_sig\nTreeUpdate [SetDefaultTree]\nWaveRestoreCursors {{Cursor 1} {600 ns} 0}\nquietly wave cursor active 1\nconfigure wave -namecolwidth 118\nconfigure wave -valuecolwidth 59\nconfigure wave -justifyvalue right\nconfigure wave -signalnamewidth 1\nconfigure wave -snapdistance 10\nconfigure wave -datasetprefix 0\nconfigure wave -rowmargin 4\nconfigure wave -childrowmargin 2\nconfigure wave -gridoffset 0\nconfigure wave -gridperiod 1\nconfigure wave -griddelta 40\nconfigure wave -timeline 1\nconfigure wave -timelineunits us\nupdate\nWaveRestoreZoom {0 ns} {3800 ns}\n"
  },
  {
    "path": "cpu/alu/simulation/modelsim/wave_prep_daa.do",
    "content": "onerror {resume}\nquietly WaveActivateNextPane {} 0\nadd wave -noupdate -color Gold -itemcolor Gold -radix hexadecimal /test_prep_daa/low_sig\nadd wave -noupdate -color Gold -itemcolor Gold -radix hexadecimal /test_prep_daa/high_sig\nadd wave -noupdate /test_prep_daa/low_gt_9_sig\nadd wave -noupdate /test_prep_daa/high_gt_9_sig\nadd wave -noupdate /test_prep_daa/high_eq_9_sig\nTreeUpdate [SetDefaultTree]\nWaveRestoreCursors {{Cursor 1} {1400 ns} 0}\nquietly wave cursor active 1\nconfigure wave -namecolwidth 138\nconfigure wave -valuecolwidth 60\nconfigure wave -justifyvalue right\nconfigure wave -signalnamewidth 1\nconfigure wave -snapdistance 10\nconfigure wave -datasetprefix 0\nconfigure wave -rowmargin 4\nconfigure wave -childrowmargin 2\nconfigure wave -gridoffset 0\nconfigure wave -gridperiod 1\nconfigure wave -griddelta 40\nconfigure wave -timeline 1\nconfigure wave -timelineunits us\nupdate\nWaveRestoreZoom {0 ns} {4100 ns}\n"
  },
  {
    "path": "cpu/alu/simulation/modelsim/wave_shifter_core.do",
    "content": "onerror {resume}\nquietly virtual signal -install /test_shifter_core { (context /test_shifter_core )&{out_high ,out_low }} db_out\nquietly WaveActivateNextPane {} 0\nadd wave -noupdate -radix binary -childformat {{{/test_shifter_core/db[7]} -radix binary} {{/test_shifter_core/db[6]} -radix binary} {{/test_shifter_core/db[5]} -radix binary} {{/test_shifter_core/db[4]} -radix binary} {{/test_shifter_core/db[3]} -radix binary} {{/test_shifter_core/db[2]} -radix binary} {{/test_shifter_core/db[1]} -radix binary} {{/test_shifter_core/db[0]} -radix binary}} -subitemconfig {{/test_shifter_core/db[7]} {-height 15 -radix binary} {/test_shifter_core/db[6]} {-height 15 -radix binary} {/test_shifter_core/db[5]} {-height 15 -radix binary} {/test_shifter_core/db[4]} {-height 15 -radix binary} {/test_shifter_core/db[3]} {-height 15 -radix binary} {/test_shifter_core/db[2]} {-height 15 -radix binary} {/test_shifter_core/db[1]} {-height 15 -radix binary} {/test_shifter_core/db[0]} {-height 15 -radix binary}} /test_shifter_core/db\nadd wave -noupdate -color Gold -itemcolor Gold /test_shifter_core/db_out\nadd wave -noupdate -color {Medium Aquamarine} -itemcolor {Medium Aquamarine} /test_shifter_core/shift_db0\nadd wave -noupdate -color Cyan -itemcolor Cyan /test_shifter_core/shift_db7\nadd wave -noupdate /test_shifter_core/shift_in\nadd wave -noupdate /test_shifter_core/shift_left\nadd wave -noupdate /test_shifter_core/shift_right\nadd wave -noupdate /test_shifter_core/out_high\nadd wave -noupdate /test_shifter_core/out_low\nTreeUpdate [SetDefaultTree]\nWaveRestoreCursors {{Cursor 1} {5100 ns} 0}\nquietly wave cursor active 1\nconfigure wave -namecolwidth 143\nconfigure wave -valuecolwidth 64\nconfigure wave -justifyvalue right\nconfigure wave -signalnamewidth 1\nconfigure wave -snapdistance 10\nconfigure wave -datasetprefix 0\nconfigure wave -rowmargin 4\nconfigure wave -childrowmargin 2\nconfigure wave -gridoffset 0\nconfigure wave -gridperiod 1\nconfigure wave -griddelta 40\nconfigure wave -timeline 1\nconfigure wave -timelineunits us\nupdate\nWaveRestoreZoom {0 ns} {9500 ns}\n"
  },
  {
    "path": "cpu/alu/simulation/modelsim/wave_slice.do",
    "content": "onerror {resume}\nquietly WaveActivateNextPane {} 0\nadd wave -noupdate -radix hexadecimal /test_slice/op1_sig\nadd wave -noupdate -radix hexadecimal /test_slice/op2_sig\nadd wave -noupdate /test_slice/cy_in_sig\nadd wave -noupdate -color Gold -itemcolor Gold -radix hexadecimal /test_slice/result_sig\nadd wave -noupdate -color Gold -format Literal -itemcolor Gold /test_slice/cy_out_sig\nadd wave -noupdate /test_slice/R_sig\nadd wave -noupdate /test_slice/S_sig\nadd wave -noupdate /test_slice/V_sig\nadd wave -noupdate /test_slice/cy_out_D_sig\nadd wave -noupdate /test_slice/cy_out_C_sig\nadd wave -noupdate /test_slice/cy_out_B_sig\nTreeUpdate [SetDefaultTree]\nWaveRestoreCursors {{Cursor 1} {2000 ns} 0}\nquietly wave cursor active 1\nconfigure wave -namecolwidth 132\nconfigure wave -valuecolwidth 57\nconfigure wave -justifyvalue right\nconfigure wave -signalnamewidth 1\nconfigure wave -snapdistance 10\nconfigure wave -datasetprefix 0\nconfigure wave -rowmargin 4\nconfigure wave -childrowmargin 2\nconfigure wave -gridoffset 0\nconfigure wave -gridperiod 1\nconfigure wave -griddelta 40\nconfigure wave -timeline 1\nconfigure wave -timelineunits us\nupdate\nWaveRestoreZoom {0 ns} {4100 ns}\n"
  },
  {
    "path": "cpu/alu/test_alu.qpf",
    "content": "# -------------------------------------------------------------------------- #\n#\n# Copyright (C) 1991-2013 Altera Corporation\n# Your use of Altera Corporation's design tools, logic functions \n# and other software and tools, and its AMPP partner logic \n# functions, and any output files from any of the foregoing \n# (including device programming or simulation files), and any \n# associated documentation or information are expressly subject \n# to the terms and conditions of the Altera Program License \n# Subscription Agreement, Altera MegaCore Function License \n# Agreement, or other applicable license agreement, including, \n# without limitation, that your use is for the sole purpose of \n# programming logic devices manufactured by Altera and sold by \n# Altera or its authorized distributors.  Please refer to the \n# applicable agreement for further details.\n#\n# -------------------------------------------------------------------------- #\n#\n# Quartus II 64-Bit\n# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\n# Date created = 09:01:54  October 13, 2014\n#\n# -------------------------------------------------------------------------- #\n\nQUARTUS_VERSION = \"13.0\"\nDATE = \"09:01:54  October 13, 2014\"\n\n# Revisions\n\nPROJECT_REVISION = \"test_alu\"\n"
  },
  {
    "path": "cpu/alu/test_alu.qsf",
    "content": "# -------------------------------------------------------------------------- #\n#\n# Copyright (C) 1991-2013 Altera Corporation\n# Your use of Altera Corporation's design tools, logic functions \n# and other software and tools, and its AMPP partner logic \n# functions, and any output files from any of the foregoing \n# (including device programming or simulation files), and any \n# associated documentation or information are expressly subject \n# to the terms and conditions of the Altera Program License \n# Subscription Agreement, Altera MegaCore Function License \n# Agreement, or other applicable license agreement, including, \n# without limitation, that your use is for the sole purpose of \n# programming logic devices manufactured by Altera and sold by \n# Altera or its authorized distributors.  Please refer to the \n# applicable agreement for further details.\n#\n# -------------------------------------------------------------------------- #\n#\n# Quartus II 64-Bit\n# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\n# Date created = 09:01:54  October 13, 2014\n#\n# -------------------------------------------------------------------------- #\n#\n# Notes:\n#\n# 1) The default values for assignments are stored in the file:\n#\t\ttest_alu_assignment_defaults.qdf\n#    If this file doesn't exist, see file:\n#\t\tassignment_defaults.qdf\n#\n# 2) Altera recommends that you do not modify this file. This\n#    file is updated automatically by the Quartus II software\n#    and any changes you make may be lost or overwritten.\n#\n# -------------------------------------------------------------------------- #\n\n\nset_global_assignment -name FAMILY \"Cyclone II\"\nset_global_assignment -name DEVICE EP2C20F484C7\nset_global_assignment -name TOP_LEVEL_ENTITY alu_control\nset_global_assignment -name ORIGINAL_QUARTUS_VERSION \"13.0 SP1\"\nset_global_assignment -name PROJECT_CREATION_TIME_DATE \"09:01:54  OCTOBER 13, 2014\"\nset_global_assignment -name LAST_QUARTUS_VERSION \"13.0 SP1\"\nset_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files\nset_global_assignment -name MIN_CORE_JUNCTION_TEMP 0\nset_global_assignment -name MAX_CORE_JUNCTION_TEMP 85\nset_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1\nset_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top\nset_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top\nset_global_assignment -name PARTITION_COLOR 16764057 -section_id Top\nset_global_assignment -name BDF_FILE alu_slice.bdf\nset_global_assignment -name BDF_FILE alu_shifter_core.bdf\nset_global_assignment -name BDF_FILE alu_select.bdf\nset_global_assignment -name BDF_FILE alu_prep_daa.bdf\nset_global_assignment -name BDF_FILE alu_mux_8.bdf\nset_global_assignment -name BDF_FILE alu_mux_4.bdf\nset_global_assignment -name BDF_FILE alu_mux_3z.bdf\nset_global_assignment -name BDF_FILE alu_mux_2z.bdf\nset_global_assignment -name BDF_FILE alu_mux_2.bdf\nset_global_assignment -name BDF_FILE alu_flags.bdf\nset_global_assignment -name BDF_FILE alu_core.bdf\nset_global_assignment -name BDF_FILE alu_control.bdf\nset_global_assignment -name BDF_FILE alu_bit_select.bdf\nset_global_assignment -name BDF_FILE alu.bdf\nset_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top"
  },
  {
    "path": "cpu/alu/test_alu.sv",
    "content": "//==============================================================\n// Test complete ALU block\n//==============================================================\n`timescale 100 ns/ 100 ns\n\nmodule test_alu;\n\n// ----------------- CLOCKS AND RESET -----------------\n// Define one full T-clock cycle delay\n`define T #2\nbit clk = 1;\ninitial repeat (24) #1 clk = ~clk;\n\n// ------------------------ BUS LOGIC ------------------------\n// Bus control\nlogic alu_oe;               // ALU unit output enable to the outside bus\n\n// Write to the ALU internal data buses\nlogic alu_op1_oe;           // Enable writing by the OP1 latch\nlogic alu_op2_oe;           // Enable writing by the OP2 latch\nlogic alu_res_oe;           // Enable writing by the ALU result latch\nlogic alu_shift_oe;         // Enable writing by the input shifter\nlogic alu_bs_oe;            // Enable writing by the input bit selector\n// Our own test internal mux to select ALU bus writers\nlogic [2:0] bus_sel;        // Select internal bus writer:\n\ntypedef enum logic[2:0] {\n    BUS_HIGHZ, BUS_OP1, BUS_OP2, BUS_RES, BUS_SHIFT, BUS_BS\n} bus_t;\n\n// Mux to select only one block to drive internal ALU bus\nalways_comb\nbegin\n    alu_op1_oe = 0;\n    alu_op2_oe = 0;\n    alu_res_oe = 0;\n    alu_shift_oe = 0;\n    alu_bs_oe = 0;\n    case (bus_sel)\n        BUS_OP1     : alu_op1_oe = 1;\n        BUS_OP2     : alu_op2_oe = 1;\n        BUS_RES     : alu_res_oe = 1;\n        BUS_SHIFT   : alu_shift_oe = 1;\n        BUS_BS      : alu_bs_oe = 1;\n    endcase\nend\n\n// ------------------------ INPUT ------------------------\n// Input shifter control wires and output from the shifter\nlogic alu_shift_in;         // Carry-in into the shifter\nlogic alu_shift_right;      // Shift right\nlogic alu_shift_left;       // Shift left\nwire alu_shift_db0;         // Output db[0] from the shifter for the shift logic\nwire alu_shift_db7;         // Output db[7] from the shifter for the shift logic\n\n// Input bit selector control wires\nlogic [2:0] bsel;           // Selects a bit to generate\n\n// Operator latch 1 mux select\nlogic alu_op1_sel_bus;      // OP1 is read from the internal bus\nlogic alu_op1_sel_low;      // OP1 is read from the low nibble\nlogic alu_op1_sel_zero;     // OP1 is loaded with zero\n\n// Operator 2 latch mux select\nlogic alu_op2_sel_bus;      // OP2 is read from the internal bus\nlogic alu_op2_sel_lq;       // OP2 is read from the L-Q gates (see schematic)\nlogic alu_op2_sel_zero;     // OP2 is loaded with zero\n\n// ALU operator mux select\nlogic alu_sel_op2_neg;      // Selects complemented OP2\nlogic alu_sel_op2_high;     // Selects high OP2 nibble as opposed to low\n\n// ALU Core operations\nlogic alu_core_cf_in;       // Carry input into the ALU core\nlogic alu_core_R;           // Operation control \"R\"\nlogic alu_core_S;           // Operation control \"S\"\nlogic alu_core_V;           // Operation control \"V\"\nlogic alu_op_low;           // Signal to compute and store the low nibble (see schematic)\nwire alu_core_cf_out;       // Output carry bit from the ALU core\nwire alu_vf_out;            // Output overflow flag from the ALU\n\n// Zero-detect, parity calculation, flag preparation and DAA-preparation logic\nlogic alu_parity_in;        // Input parity bit from a previous nibble\nwire alu_parity_out;        // Output parity on the result and a previous nibble\nwire alu_zero;              // Output signal that the result is zero\nwire alu_sf_out;            // Output signal containing the result sign bit\nwire alu_yf_out;            // Output signal containing the result[5] bit which is YF\nwire alu_xf_out;            // Output signal containing the result[3] bit which is XF\nwire alu_low_gt_9;          // Output signal that the low nibble result > 9\nwire alu_high_gt_9;         // Output signal that the high nibble result > 9\nwire alu_high_eq_9;         // Output signal that the high nibble result == 9\n\n// ------------------------ BUSSES ------------------------\n// Bidirectional data bus, interface to the outside world\nlogic  [7:0] db_w;          // Drive it using this bus\nwire [7:0] db;              // Read it using this bus\n\nwire [3:0] test_db_low;     // Test point to probe internal low nibble bus\nwire [3:0] test_db_high;    // Test point to probe internal high nibble bus\n\n// ------------------------ FLAGS  ------------------------\nreg cf;                     // Carry flag\nreg pf;                     // Parity flag\nreg hf;                     // Half-carry flag\n\n// ----------------- TEST -------------------\ninitial begin\n    // Init / reset\n    db_w = 8'h00;\n    bus_sel = BUS_HIGHZ;\n\n    alu_shift_in = 0;\n    alu_shift_right = 0;\n    alu_shift_left = 0;\n\n    bsel = 2'h0;\n\n    alu_op1_sel_bus = 0;\n    alu_op1_sel_low = 0;\n    alu_op1_sel_zero = 0;\n\n    alu_op2_sel_bus = 0;\n    alu_op2_sel_lq = 0;\n    alu_op2_sel_zero = 0;\n\n    alu_sel_op2_neg = 0;\n    alu_sel_op2_high = 0;\n\n    alu_parity_in = 0;\n    alu_core_cf_in = 0;\n    alu_core_R = 0;\n    alu_core_S = 0;\n    alu_core_V = 0;\n    alu_op_low = 0;\n\n    cf = 0;\n    hf = 0;\n    pf = 0;\n\n    //------------------------------------------------------------\n    // Test loading to internal bus from the input shifter through the OP1 latch\n    `T  db_w = 8'h24;                   // High: 0010  Low: 0100\n        bus_sel = BUS_SHIFT;\n        alu_shift_right = 1;            // Enable shift and shift *right*\n        alu_shift_in = 1;               // shift in <- 1\n        alu_op1_sel_bus = 1;            // Write into the OP1 latch\n\n    `T  db_w = 'z;\n        alu_op1_sel_bus = 0;\n        alu_shift_in = 0;\n        bus_sel = BUS_OP1;              // Read back OP1 latch\n        alu_shift_right = 0;\n        // Expected output on the external ALU bus : 1001 0010, 0x92\n    `T  assert(db==8'h92);\n        // Reset\n        bus_sel = BUS_HIGHZ;\n\n    //------------------------------------------------------------\n    // Test loading to internal bus from the input bit selector through the OP2 latch\n    `T  db_w = 'z;                      // Not using external bus to load, but the bit-select\n        bsel = 2'h3;                    // Bit 3:  0000 1000\n        bus_sel = BUS_BS;\n        alu_op2_sel_bus = 1;            // Write into the OP2 latch\n\n    `T  db_w = 'z;\n        alu_op2_sel_bus = 0;\n        alu_shift_in = 0;\n        bus_sel = BUS_OP2;\n        bsel = 2'h0;\n        // Expected output on the external ALU bus : 0000 1000, 0x08\n    `T  assert(db==8'h08);\n        // Reset\n    `T  bus_sel = BUS_HIGHZ;\n\n    //------------------------------------------------------------\n    // Test the full adding function, ADD\n    `T  db_w = 8'h8C;                   // Operand 1:  8C\n        bus_sel = BUS_SHIFT;            // Shifter writes to internal bus\n        alu_op1_sel_bus = 1;            // Write into the OP1 latch\n\n    `T  db_w = 8'h68;                   // Operand 1:  68\n        alu_op_low = 1;                 // Perform the low nibble calculation\n        alu_op1_sel_bus = 0;\n        bus_sel = BUS_SHIFT;            // Shifter writes to internal bus\n        alu_op2_sel_bus = 1;            // Write into the OP2 latch\n        // Do a low nibble addition in this cycle\n        alu_sel_op2_high = 0;           // ALU select low OP nibble\n        alu_parity_in = 0;              // Reset parity of the nibble\n        alu_core_cf_in = 0;             // CF in 0\n        alu_core_R = 0;\n        alu_core_S = 0;\n        alu_core_V = 0;\n        hf = alu_core_cf_out;           // Load the HF with the half-carry out\n        pf = alu_parity_out;            // Load the PF with the parity of the nibble result\n\n    `T  db_w = 'z;\n        alu_op_low = 0;                 // Perform the high nibble calculation\n        alu_op2_sel_bus = 0;\n        alu_sel_op2_high = 1;           // ALU select high OP2 nibble\n        alu_core_cf_in = 0;\n        alu_core_cf_in = hf;            // Carry in the half-carry\n        alu_parity_in = pf;             // Parity in the parity of the low result nibble\n        bus_sel = BUS_RES;              // ALU result latch writes to the bus\n        // Expected output on the external ALU bus : 8C + 68 = F4\n    `T  assert(db==8'hF4);\n        // Reset\n        bus_sel = BUS_HIGHZ;\n\n    `T  $display(\"End of test\");\nend\n\n//--------------------------------------------------------------\n// External bus logic\nassign db = db_w;           // Drive 3-state bidirectional bus\nalways_comb                 // Output internal ALU bus only when our\nbegin                       // test is not driving it\n    if (db_w==='z)\n        alu_oe = 1;\n    else\n        alu_oe = 0;\nend\n\n//--------------------------------------------------------------\n// Instantiate ALU block and assign identical nets and variables\n//--------------------------------------------------------------\n\nalu alu_inst( .* );\n\nendmodule\n"
  },
  {
    "path": "cpu/alu/test_core.sv",
    "content": "//==============================================================\n// Test ALU core\n//==============================================================\n`timescale 100 ns/ 100 ns\n\nmodule test_core;\n\n// ----------------- INPUT -----------------\nreg [3:0] op1_sig;          // Operand 1\nreg [3:0] op2_sig;          // Operand 2\nreg cy_in_sig;              // Carry in (to slice D)\nreg R_sig;                  // Operation control \"R\"\nreg S_sig;                  // Operation control \"S\"\nreg V_sig;                  // Operation control \"V\"\n\n// ----------------- OUTPUT -----------------\nwire cy_out_sig;            // Carry out (from slice A)\nwire vf_out_sig;            // Overflow out\nwire [3:0] result_sig;      // Result bits\n\n// ----------------- TEST -------------------\n`define CHECK(arg) \\\n   assert(result_sig==arg);\n\ninitial begin\n    //------------------------------------------------------------\n    // Test ADD/ADC:    R=0  S=0  V=0    Cin for ADC operation\n    R_sig = 0;\n    S_sig = 0;\n    V_sig = 0;\n        op1_sig = 4'h0;     // 0 + 0 + 0 = 0\n        op2_sig = 4'h0;\n        cy_in_sig = 0;\n    #1 `CHECK(4'h0);\n        cy_in_sig = 1;      // 0 + 0 + 1 = 1\n    #1 `CHECK(4'h1);\n        op1_sig = 4'h2;     // 2 + 8 + 0 = A\n        op2_sig = 4'h8;\n        cy_in_sig = 0;\n    #1 `CHECK(4'hA);\n        cy_in_sig = 1;      // 2 + 8 + 1 = B\n    #1 `CHECK(4'hB);\n        op1_sig = 4'hB;     // B + 4 + 0 = F\n        op2_sig = 4'h4;\n        cy_in_sig = 0;\n    #1 `CHECK(4'hF);\n        cy_in_sig = 1;      // B + 4 + 1 = 0 + CY\n    #1 `CHECK(4'h0);\n        op1_sig = 4'hD;     // D + 6 + 0 = 3 + CY\n        op2_sig = 4'h6;\n        cy_in_sig = 0;\n    #1 `CHECK(4'h3);\n        cy_in_sig = 1;      // D + 6 + 1 = 4 + CY\n    #1 `CHECK(4'h4);\n\n    //------------------------------------------------------------\n    // Test XOR:        R=1  S=0  V=0  Cin=0\n    #1\n    R_sig = 1;\n    S_sig = 0;\n    V_sig = 0;\n    cy_in_sig = 0;\n        op1_sig = 4'h0;     // 0 ^ 0 = 0\n        op2_sig = 4'h0;\n    #1 `CHECK(4'h0);\n        op1_sig = 4'h3;     // 3 ^ C = F\n        op2_sig = 4'hC;\n    #1 `CHECK(4'hF);\n        op1_sig = 4'h6;     // 6 ^ 3 = 5\n        op2_sig = 4'h3;\n    #1 `CHECK(4'h5);\n        op1_sig = 4'hF;     // F ^ F = 0\n        op2_sig = 4'hF;\n    #1 `CHECK(4'h0);\n\n    //------------------------------------------------------------\n    // Test AND:        R=0  S=1  V=0  Cin=1\n    #1\n    R_sig = 0;\n    S_sig = 1;\n    V_sig = 0;\n    cy_in_sig = 1;\n        op1_sig = 4'h0;     // 0 & 0 = 0\n        op2_sig = 4'h0;\n    #1 `CHECK(4'h0);\n        op1_sig = 4'h3;     // 3 & C = 0\n        op2_sig = 4'hC;\n    #1 `CHECK(4'h0);\n        op1_sig = 4'h6;     // 6 & 3 = 2\n        op2_sig = 4'h3;\n    #1 `CHECK(4'h2);\n        op1_sig = 4'hF;     // F & F = F\n        op2_sig = 4'hF;\n    #1 `CHECK(4'hF);\n\n    //------------------------------------------------------------\n    // Test OR:         R=1  S=1  V=1  Cin=0\n    #1\n    R_sig = 1;\n    S_sig = 1;\n    V_sig = 1;\n    cy_in_sig = 0;\n        op1_sig = 4'h0;     // 0 | 0 = 0\n        op2_sig = 4'h0;\n    #1 `CHECK(4'h0);\n        op1_sig = 4'h3;     // 3 | C = F\n        op2_sig = 4'hC;\n    #1 `CHECK(4'hF);\n        op1_sig = 4'h6;     // 6 | 3 = 7\n        op2_sig = 4'h3;\n    #1 `CHECK(4'h7);\n        op1_sig = 4'hF;     // F | F = F\n        op2_sig = 4'hF;\n    #1 `CHECK(4'hf);\n\n    #1 $display(\"End of test\");\nend\n\n//--------------------------------------------------------------\n// Instantiate ALU core block\n//--------------------------------------------------------------\nalu_core alu_core_inst\n(\n    .cy_in(cy_in_sig) ,         // input  cy_in_sig\n    .op1(op1_sig[3:0]) ,        // input [3:0] op1_sig\n    .op2(op2_sig[3:0]) ,        // input [3:0] op2_sig\n    .S(S_sig) ,                 // input  S_sig\n    .V(V_sig) ,                 // input  V_sig\n    .R(R_sig) ,                 // input  R_sig\n    .cy_out(cy_out_sig) ,       // output  cy_out_sig\n    .vf_out(vf_out_sig) ,       // output  vf_out_sig\n    .result(result_sig[3:0])    // output [3:0] result_sig\n);\n\nendmodule\n"
  },
  {
    "path": "cpu/alu/test_mux_3z.sv",
    "content": "//==============================================================\n// Test ALU op1 MUX which is a bit more complicated\n//==============================================================\n`timescale 100 ns/ 100 ns\n\nmodule test_mux_3z;\n\n// ----------------- INPUT -----------------\nreg sel_a_sig;\nreg sel_b_sig;\nreg sel_zero_sig;\nreg [3:0] a_sig;\nreg [3:0] b_sig;\n\n// ----------------- OUTPUT -----------------\nwire [3:0] Q_sig;           // Output of a mux\nwire ena_out_sig;           // Write enable to the latch\n\n// ----------------- TEST -------------------\n`define CHECK(arg) \\\n   assert(Q_sig==arg);\n\ninitial begin\n    sel_a_sig = 0;\n    sel_b_sig = 0;\n    sel_zero_sig = 0;\n    a_sig = 4'hA;\n    b_sig = 4'h5;\n    #1  `CHECK(0);\n\n    sel_zero_sig = 0;\n    sel_a_sig = 0;\n    sel_b_sig = 0;\n    #1  `CHECK(0);\n\n    sel_zero_sig = 1;\n    sel_a_sig = 0;\n    sel_b_sig = 0;\n    #1  `CHECK(0);\n\n    sel_zero_sig = 0;\n    sel_a_sig = 1;\n    sel_b_sig = 0;\n    #1  `CHECK(a_sig);\n\n    sel_zero_sig = 0;\n    sel_a_sig = 0;\n    sel_b_sig = 1;\n    #1  `CHECK(b_sig);\n\n    sel_zero_sig = 1;\n    sel_a_sig = 1;\n    sel_b_sig = 1;\n    #1  `CHECK(0);\n\n    #1 $display(\"End of test\");\nend\n\n//--------------------------------------------------------------\n// Instantiate a mux\n//--------------------------------------------------------------\nalu_mux_3z alu_mux_3z_inst\n(\n    .sel_zero(sel_zero_sig) ,   // input  sel_zero_sig\n    .sel_a(sel_a_sig) ,         // input  sel_a_sig\n    .b(b_sig) ,                 // input [3:0] b_sig\n    .sel_b(sel_b_sig) ,         // input  sel_b_sig\n    .a(a_sig) ,                 // input [3:0] a_sig\n    .Q(Q_sig) ,                 // output [3:0] Q_sig\n    .ena(ena_out_sig)           // output  ena_out_sig\n);\n\nendmodule\n"
  },
  {
    "path": "cpu/alu/test_prep_daa.sv",
    "content": "//==============================================================\n// Test ALU state preparation for DAA instruction\n//==============================================================\n`timescale 100 ns/ 100 ns\n\nmodule test_prep_daa;\n\n// ----------------- INPUT -----------------\nreg [3:0] low_sig;          // Input data bus A (independent)\nreg [3:0] high_sig;         // Input data bus B (independent)\n\n// ----------------- OUTPUT -----------------\nwire low_gt_9_sig;          // low bus > 9\nwire high_gt_9_sig;         // high bus > 9\nwire high_eq_9_sig;         // high bus == 9\n\n// ----------------- TEST -------------------\n`define CHECK \\\n   assert(low_gt_9_sig==low_sig>9 && high_gt_9_sig==high_sig>9 && high_eq_9_sig==(high_sig==9));\n\ninitial begin\n    low_sig  = 4'h0;\n    high_sig = 4'h0;\n    #1 `CHECK\n    low_sig  = 4'h1;\n    high_sig = 4'h1;\n    #1 `CHECK\n    low_sig  = 4'h2;\n    high_sig = 4'h2;\n    #1 `CHECK\n    low_sig  = 4'h3;\n    high_sig = 4'h3;\n    #1 `CHECK\n    low_sig  = 4'h4;\n    high_sig = 4'h4;\n    #1 `CHECK\n    low_sig  = 4'h5;\n    high_sig = 4'h5;\n    #1 `CHECK\n    low_sig  = 4'h6;\n    high_sig = 4'h6;\n    #1 `CHECK\n    low_sig  = 4'h7;\n    high_sig = 4'h7;\n    #1 `CHECK\n    low_sig  = 4'h8;\n    high_sig = 4'h8;\n    #1 `CHECK\n    low_sig  = 4'h9;\n    high_sig = 4'h9;\n    #1 `CHECK\n    low_sig  = 4'hA;\n    high_sig = 4'hA;\n    #1 `CHECK\n    low_sig  = 4'hB;\n    high_sig = 4'hB;\n    #1 `CHECK\n    low_sig  = 4'hC;\n    high_sig = 4'hC;\n    #1 `CHECK\n    low_sig  = 4'hD;\n    high_sig = 4'hD;\n    #1 `CHECK\n    low_sig  = 4'hE;\n    high_sig = 4'hE;\n    #1 `CHECK\n    low_sig  = 4'hF;\n    high_sig = 4'hF;\n    #1 `CHECK\n\n    #1 $display(\"End of test\");\nend\n\n//--------------------------------------------------------------\n// Instantiate prep-DAA block\n//--------------------------------------------------------------\nalu_prep_daa alu_prep_daa_inst\n(\n    .low(low_sig) ,             // input [3:0] low_sig\n    .high(high_sig) ,           // input [3:0] high_sig\n    .low_gt_9(low_gt_9_sig) ,   // output  low_gt_9_sig\n    .high_eq_9(high_eq_9_sig) , // output  high_eq_9_sig\n    .high_gt_9(high_gt_9_sig)   // output  high_gt_9_sig\n);\n\nendmodule\n"
  },
  {
    "path": "cpu/alu/test_shifter_core.sv",
    "content": "//==============================================================\n// Test ALU shifter core block\n//==============================================================\n`timescale 100 ns/ 100 ns\n\nmodule test_shifter_core;\n\n// ----------------- INPUT -----------------\nlogic [7:0] db;                 // Input data bus\nlogic shift_in;                 // Input bit to be shifted in\nlogic shift_left;               // Input control to left-shift\nlogic shift_right;              // Input control to right-shift\n\n// ----------------- OUTPUT -----------------\nwire shift_db0;                 // db[0] for shift logic\nwire shift_db7;                 // db[7] for shift logic\nwire [3:0] out_high;            // To internal ALU bus, high nibble\nwire [3:0] out_low;             // ..low nibble\n\n// ----------------- TEST -------------------\n`define CHECK(arg) \\\n   assert({out_high,out_low}==arg);\n\ninitial begin\n    db = 8'h00;\n    shift_left = 0;\n    shift_right = 0;\n    shift_in = 0;\n\n    //------------------------------------------------------------\n    // Test load without shifting\n        db = 8'hAA;\n    #1 `CHECK(8'hAA);\n        db = 8'h55;\n    #1 `CHECK(8'h55);\n\n    //------------------------------------------------------------\n    // Test right shift, no carry-in\n    #1  db =  8'b00000001;\n        shift_right = 1;\n        shift_in = 0;\n    #1 `CHECK(8'b00000000);\n        db =  8'b00000010;\n    #1 `CHECK(8'b00000001);\n        db =  8'b00000100;\n    #1 `CHECK(8'b00000010);\n        db =  8'b00001000;\n    #1 `CHECK(8'b00000100);\n        db =  8'b00010000;\n    #1 `CHECK(8'b00001000);\n        db =  8'b00100000;\n    #1 `CHECK(8'b00010000);\n        db =  8'b01000000;\n    #1 `CHECK(8'b00100000);\n        db =  8'b10000000;\n    #1 `CHECK(8'b01000000);\n\n    // With carry-in\n    #1  db =  8'b00000001;\n        shift_in = 1;\n    #1 `CHECK(8'b10000000);\n        db =  8'b00000010;\n    #1 `CHECK(8'b10000001);\n        db =  8'b00000100;\n    #1 `CHECK(8'b10000010);\n        db =  8'b00001000;\n    #1 `CHECK(8'b10000100);\n        db =  8'b00010000;\n    #1 `CHECK(8'b10001000);\n        db =  8'b00100000;\n    #1 `CHECK(8'b10010000);\n        db =  8'b01000000;\n    #1 `CHECK(8'b10100000);\n        db =  8'b10000000;\n    #1 `CHECK(8'b11000000);\n\n    //------------------------------------------------------------\n    // Test left shift, no carry-in\n    #1  db =  8'b00000001;\n        shift_right = 0;\n        shift_left = 1;\n        shift_in = 0;\n    #1 `CHECK(8'b00000010);\n        db =  8'b00000010;\n    #1 `CHECK(8'b00000100);\n        db =  8'b00000100;\n    #1 `CHECK(8'b00001000);\n        db =  8'b00001000;\n    #1 `CHECK(8'b00010000);\n        db =  8'b00010000;\n    #1 `CHECK(8'b00100000);\n        db =  8'b00100000;\n    #1 `CHECK(8'b01000000);\n        db =  8'b01000000;\n    #1 `CHECK(8'b10000000);\n        db =  8'b10000000;\n    #1 `CHECK(8'b00000000);\n\n    // With carry-in\n    #1  db =  8'b00000001;\n        shift_in = 1;\n    #1 `CHECK(8'b00000011);\n        db =  8'b00000010;\n    #1 `CHECK(8'b00000101);\n        db =  8'b00000100;\n    #1 `CHECK(8'b00001001);\n        db =  8'b00001000;\n    #1 `CHECK(8'b00010001);\n        db =  8'b00010000;\n    #1 `CHECK(8'b00100001);\n        db =  8'b00100000;\n    #1 `CHECK(8'b01000001);\n        db =  8'b01000000;\n    #1 `CHECK(8'b10000001);\n        db =  8'b10000000;\n    #1 `CHECK(8'b00000001);\n\n    //------------------------------------------------------------\n    // Test right shift, no carry-in - special SRA instruction\n    // This instruction simply duplicates bit [7] instead of using CY\n    #1  db =  8'b00000001;\n        shift_right = 1;\n        shift_left = 0;\n        shift_in = shift_db7;\n    #1 `CHECK(8'b10000000);\n        db =  8'b00000010;\n    #1 `CHECK(8'b10000001);\n        db =  8'b00000100;\n    #1 `CHECK(8'b10000010);\n        db =  8'b00001000;\n    #1 `CHECK(8'b10000100);\n        db =  8'b00010000;\n    #1 `CHECK(8'b10001000);\n        db =  8'b00100000;\n    #1 `CHECK(8'b10010000);\n        db =  8'b01000000;\n    #1 `CHECK(8'b10100000);\n        db =  8'b10000000;\n    #1 `CHECK(8'b11000000);\n\n    // With carry-in\n    #1  db =  8'b00000001;\n        shift_in = 1;\n    #1 `CHECK(8'b10000000);\n        db =  8'b00000010;\n    #1 `CHECK(8'b10000001);\n        db =  8'b00000100;\n    #1 `CHECK(8'b10000010);\n        db =  8'b00001000;\n    #1 `CHECK(8'b10000100);\n        db =  8'b00010000;\n    #1 `CHECK(8'b10001000);\n        db =  8'b00100000;\n    #1 `CHECK(8'b10010000);\n        db =  8'b01000000;\n    #1 `CHECK(8'b10100000);\n        db =  8'b10000000;\n    #1 `CHECK(8'b11000000);\n\n    #1 $display(\"End of test\");\nend\n\n//--------------------------------------------------------------\n// Instantiate shifter core block and assign identical nets and variables\n//--------------------------------------------------------------\n\nalu_shifter_core alu_shifter_core_inst( .* );\n\nendmodule\n"
  },
  {
    "path": "cpu/alu/test_slice.sv",
    "content": "//==============================================================\n// Test ALU slice\n//==============================================================\n`timescale 100 ns/ 100 ns\n\nmodule test_slice;\n\n// ----------------- INPUT -----------------\nreg [3:0] op1_sig;          // Operand 1\nreg [3:0] op2_sig;          // Operand 2\nreg cy_in_sig;              // Carry in (to slice D)\nreg R_sig;                  // Operation control \"R\"\nreg S_sig;                  // Operation control \"S\"\nreg V_sig;                  // Operation control \"V\"\n\n// ----------------- OUTPUT -----------------\nwire cy_out_sig;            // Carry out (from slice A)\nwire [3:0] result_sig;      // Result bits\n\n// ----------------- CONNECTIONS -----------------\nwire cy_out_D_sig;          // Carry out from slice D into slice C\nwire cy_out_C_sig;          // Carry out from slice C into slice B\nwire cy_out_B_sig;          // Carry out from slice B into slice A\n\n// ----------------- TEST -------------------\n`define CHECK(arg) \\\n   assert(result_sig==arg);\n\ninitial begin\n    op1_sig = '0;\n    op2_sig = '0;\n    cy_in_sig = 0;\n    R_sig = 0;\n    S_sig = 0;\n    V_sig = 0;\n\n    //------------------------------------------------------------\n    // Test ADD/ADC:    R=0  S=0  V=0    Cin for ADC operation\n    R_sig = 0;\n    S_sig = 0;\n    V_sig = 0;\n        op1_sig = 4'h0;     // 0 + 0 + 0 = 0\n        op2_sig = 4'h0;\n        cy_in_sig = 0;\n    #1 `CHECK(0);\n        cy_in_sig = 1;      // 0 + 0 + 1 = 1\n    #1 `CHECK(1);\n        op1_sig = 4'h2;     // 2 + 8 + 0 = A\n        op2_sig = 4'h8;\n        cy_in_sig = 0;\n    #1 `CHECK(4'hA);\n        cy_in_sig = 1;      // 2 + 8 + 1 = B\n    #1 `CHECK(4'hB);\n        op1_sig = 4'hB;     // B + 4 + 0 = F\n        op2_sig = 4'h4;\n        cy_in_sig = 0;\n    #1 `CHECK(4'hF);\n        cy_in_sig = 1;      // B + 4 + 1 = 0 + CY\n    #1 `CHECK(4'h0);\n        op1_sig = 4'hD;     // D + 6 + 0 = 3 + CY\n        op2_sig = 4'h6;\n        cy_in_sig = 0;\n    #1 `CHECK(4'h3);\n        cy_in_sig = 1;      // D + 6 + 1 = 4 + CY\n    #1 `CHECK(4'h4);\n\n    //------------------------------------------------------------\n    // Test XOR:        R=1  S=0  V=0  Cin=0\n    #1\n    R_sig = 1;\n    S_sig = 0;\n    V_sig = 0;\n    cy_in_sig = 0;\n        op1_sig = 4'h0;     // 0 ^ 0 = 0\n        op2_sig = 4'h0;\n    #1 `CHECK(4'h0);\n        op1_sig = 4'h3;     // 3 ^ C = F\n        op2_sig = 4'hC;\n    #1 `CHECK(4'hF);\n        op1_sig = 4'h6;     // 6 ^ 3 = 5\n        op2_sig = 4'h3;\n    #1 `CHECK(4'h5);\n        op1_sig = 4'hF;     // F ^ F = 0\n        op2_sig = 4'hF;\n    #1 `CHECK(4'h0);\n\n    //------------------------------------------------------------\n    // Test AND:        R=0  S=1  V=0  Cin=1\n    #1\n    R_sig = 0;\n    S_sig = 1;\n    V_sig = 0;\n    cy_in_sig = 1;\n        op1_sig = 4'h0;     // 0 & 0 = 0\n        op2_sig = 4'h0;\n    #1 `CHECK(4'h0);\n        op1_sig = 4'h3;     // 3 & C = 0\n        op2_sig = 4'hC;\n    #1 `CHECK(4'h0);\n        op1_sig = 4'h6;     // 6 & 3 = 2\n        op2_sig = 4'h3;\n    #1 `CHECK(4'h2);\n        op1_sig = 4'hF;     // F & F = F\n        op2_sig = 4'hF;\n    #1 `CHECK(4'hF);\n\n    //------------------------------------------------------------\n    // Test OR:         R=1  S=1  V=1  Cin=0\n    #1\n    R_sig = 1;\n    S_sig = 1;\n    V_sig = 1;\n    cy_in_sig = 0;\n        op1_sig = 4'h0;     // 0 | 0 = 0\n        op2_sig = 4'h0;\n    #1 `CHECK(4'h0);\n        op1_sig = 4'h3;     // 3 | C = F\n        op2_sig = 4'hC;\n    #1 `CHECK(4'hF);\n        op1_sig = 4'h6;     // 6 | 3 = 7\n        op2_sig = 4'h3;\n    #1 `CHECK(4'h7);\n        op1_sig = 4'hF;     // F | F = F\n        op2_sig = 4'hF;\n    #1 `CHECK(4'hF);\n\n    #1 $display(\"End of test\");\nend\n\n//--------------------------------------------------------------\n// Instantiate 4 ALU slice units, daisy-chained; MSB is slice A\n//\n//            slice_A slice_B slice_C slice_D\n//  cy_out <=   [3]     [2]     [1]     [0]  <= cy_in\n//--------------------------------------------------------------\nalu_slice slice_A\n(\n    .op1(op1_sig[3]) ,          // input  op1_sig\n    .op2(op2_sig[3]) ,          // input  op2_sig\n    .cy_in(cy_out_B_sig) ,      // input  cy_in_sig\n    .R(R_sig) ,                 // input  R_sig\n    .S(S_sig) ,                 // input  S_sig\n    .V(V_sig) ,                 // input  V_sig\n    .cy_out(cy_out_sig) ,       // output  cy_out_sig\n    .result(result_sig[3])      // output  result_sig\n);\n\nalu_slice slice_B\n(\n    .op1(op1_sig[2]) ,          // input  op1_sig\n    .op2(op2_sig[2]) ,          // input  op2_sig\n    .cy_in(cy_out_C_sig) ,      // input  cy_in_sig\n    .R(R_sig) ,                 // input  R_sig\n    .S(S_sig) ,                 // input  S_sig\n    .V(V_sig) ,                 // input  V_sig\n    .cy_out(cy_out_B_sig) ,     // output  cy_out_sig\n    .result(result_sig[2])      // output  result_sig\n);\n\nalu_slice slice_C\n(\n    .op1(op1_sig[1]) ,          // input  op1_sig\n    .op2(op2_sig[1]) ,          // input  op2_sig\n    .cy_in(cy_out_D_sig) ,      // input  cy_in_sig\n    .R(R_sig) ,                 // input  R_sig\n    .S(S_sig) ,                 // input  S_sig\n    .V(V_sig) ,                 // input  V_sig\n    .cy_out(cy_out_C_sig) ,     // output  cy_out_sig\n    .result(result_sig[1])      // output  result_sig\n);\n\nalu_slice slice_D\n(\n    .op1(op1_sig[0]) ,          // input  op1_sig\n    .op2(op2_sig[0]) ,          // input  op2_sig\n    .cy_in(cy_in_sig) ,         // input  cy_in_sig\n    .R(R_sig) ,                 // input  R_sig\n    .S(S_sig) ,                 // input  S_sig\n    .V(V_sig) ,                 // input  V_sig\n    .cy_out(cy_out_D_sig) ,     // output  cy_out_sig\n    .result(result_sig[0])      // output  result_sig\n);\n\nendmodule\n"
  },
  {
    "path": "cpu/bus/address_latch.bdf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  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    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"symbol\" (version \"1.2\"))\n(symbol\n\t(rect 16 16 240 240)\n\t(text \"address_latch\" (rect 5 0 86 14)(font \"Arial\" (font_size 8)))\n\t(text \"inst\" (rect 8 208 25 220)(font \"Arial\" ))\n\t(port\n\t\t(pt 0 32)\n\t\t(input)\n\t\t(text \"clrpc\" (rect 0 0 28 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"clrpc\" (rect 21 27 49 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 32)(pt 16 32))\n\t)\n\t(port\n\t\t(pt 0 48)\n\t\t(input)\n\t\t(text \"ctl_bus_inc_oe\" (rect 0 0 86 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"ctl_bus_inc_oe\" (rect 21 43 107 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 48)(pt 16 48))\n\t)\n\t(port\n\t\t(pt 0 64)\n\t\t(input)\n\t\t(text \"ctl_inc_limit6\" (rect 0 0 70 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"ctl_inc_limit6\" (rect 21 59 91 73)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 64)(pt 16 64))\n\t)\n\t(port\n\t\t(pt 0 80)\n\t\t(input)\n\t\t(text \"ctl_inc_dec\" (rect 0 0 64 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"ctl_inc_dec\" (rect 21 75 85 89)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 80)(pt 16 80))\n\t)\n\t(port\n\t\t(pt 0 96)\n\t\t(input)\n\t\t(text \"ctl_inc_cy\" (rect 0 0 57 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"ctl_inc_cy\" (rect 21 91 78 105)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 96)(pt 16 96))\n\t)\n\t(port\n\t\t(pt 0 112)\n\t\t(input)\n\t\t(text \"clk\" (rect 0 0 15 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"clk\" (rect 21 107 36 121)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 112)(pt 16 112))\n\t)\n\t(port\n\t\t(pt 0 128)\n\t\t(input)\n\t\t(text \"ctl_al_we\" (rect 0 0 55 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"ctl_al_we\" (rect 21 123 76 137)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 128)(pt 16 128))\n\t)\n\t(port\n\t\t(pt 0 144)\n\t\t(input)\n\t\t(text \"nreset\" (rect 0 0 36 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"nreset\" (rect 21 139 57 153)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 144)(pt 16 144))\n\t)\n\t(port\n\t\t(pt 0 160)\n\t\t(input)\n\t\t(text \"ctl_apin_mux2\" (rect 0 0 81 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"ctl_apin_mux2\" (rect 21 155 102 169)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 160)(pt 16 160))\n\t)\n\t(port\n\t\t(pt 0 176)\n\t\t(input)\n\t\t(text \"ctl_apin_mux\" (rect 0 0 74 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"ctl_apin_mux\" (rect 21 171 95 185)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 176)(pt 16 176))\n\t)\n\t(port\n\t\t(pt 224 48)\n\t\t(output)\n\t\t(text \"address_is_1\" (rect 0 0 77 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"address_is_1\" (rect 126 43 203 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 224 48)(pt 208 48))\n\t)\n\t(port\n\t\t(pt 224 64)\n\t\t(output)\n\t\t(text \"address[15..0]\" (rect 0 0 82 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"address[15..0]\" (rect 121 59 203 73)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 224 64)(pt 208 64)(line_width 3))\n\t)\n\t(port\n\t\t(pt 224 32)\n\t\t(bidir)\n\t\t(text \"abus[15..0]\" (rect 0 0 63 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"abus[15..0]\" (rect 140 27 203 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 224 32)(pt 208 32)(line_width 3))\n\t)\n\t(drawing\n\t\t(rectangle (rect 16 16 208 208))\n\t)\n)\n"
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  {
    "path": "cpu/bus/address_latch.v",
    "content": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and other software and tools, and its AMPP partner logic \n// functions, and any output files from any of the foregoing \n// (including device programming or simulation files), and any \n// associated documentation or information are expressly subject \n// to the terms and conditions of the Altera Program License \n// Subscription Agreement, Altera MegaCore Function License \n// Agreement, or other applicable license agreement, including, \n// without limitation, that your use is for the sole purpose of \n// programming logic devices manufactured by Altera and sold by \n// Altera or its authorized distributors.  Please refer to the \n// applicable agreement for further details.\n\n// PROGRAM\t\t\"Quartus II 64-Bit\"\n// VERSION\t\t\"Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\"\n// CREATED\t\t\"Sat Feb 27 08:13:14 2016\"\n\nmodule address_latch(\n\tctl_inc_cy,\n\tctl_inc_dec,\n\tctl_al_we,\n\tctl_inc_limit6,\n\tctl_bus_inc_oe,\n\tclk,\n\tctl_apin_mux,\n\tctl_apin_mux2,\n\tclrpc,\n\tnreset,\n\taddress_is_1,\n\tabus,\n\taddress\n);\n\n\ninput wire\tctl_inc_cy;\ninput wire\tctl_inc_dec;\ninput wire\tctl_al_we;\ninput wire\tctl_inc_limit6;\ninput wire\tctl_bus_inc_oe;\ninput wire\tclk;\ninput wire\tctl_apin_mux;\ninput wire\tctl_apin_mux2;\ninput wire\tclrpc;\ninput wire\tnreset;\noutput wire\taddress_is_1;\ninout wire\t[15:0] abus;\noutput wire\t[15:0] address;\n\nwire\t[15:0] abusz;\nreg\t[15:0] Q;\nwire\tSYNTHESIZED_WIRE_0;\nwire\tSYNTHESIZED_WIRE_1;\nwire\tSYNTHESIZED_WIRE_2;\nwire\t[15:0] SYNTHESIZED_WIRE_7;\nwire\tSYNTHESIZED_WIRE_4;\nwire\t[15:0] SYNTHESIZED_WIRE_5;\n\n\n\n\n\nalways@(posedge clk or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tQ[15:0] <= 16'b0000000000000000;\n\tend\nelse\nif (ctl_al_we)\n\tbegin\n\tQ[15:0] <= abusz[15:0];\n\tend\nend\n\nassign\taddress_is_1 = ~(SYNTHESIZED_WIRE_0 | SYNTHESIZED_WIRE_1);\n\nassign\tabusz = {SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2} & abus;\n\nassign\tabus[15] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[15] : 1'bz;\nassign\tabus[14] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[14] : 1'bz;\nassign\tabus[13] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[13] : 1'bz;\nassign\tabus[12] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[12] : 1'bz;\nassign\tabus[11] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[11] : 1'bz;\nassign\tabus[10] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[10] : 1'bz;\nassign\tabus[9] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[9] : 1'bz;\nassign\tabus[8] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[8] : 1'bz;\nassign\tabus[7] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[7] : 1'bz;\nassign\tabus[6] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[6] : 1'bz;\nassign\tabus[5] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[5] : 1'bz;\nassign\tabus[4] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[4] : 1'bz;\nassign\tabus[3] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[3] : 1'bz;\nassign\tabus[2] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[2] : 1'bz;\nassign\tabus[1] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[1] : 1'bz;\nassign\tabus[0] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[0] : 1'bz;\n\nassign\tSYNTHESIZED_WIRE_0 = Q[7] | Q[5] | Q[6] | Q[4] | Q[2] | Q[3] | Q[1] | SYNTHESIZED_WIRE_4;\n\nassign\tSYNTHESIZED_WIRE_1 = Q[15] | Q[13] | Q[14] | Q[12] | Q[10] | Q[11] | Q[9] | Q[8];\n\n\naddress_mux\tb2v_inst7(\n\t.select(ctl_apin_mux2),\n\t.in0(SYNTHESIZED_WIRE_5),\n\t.in1(Q),\n\t.out(address));\n\nassign\tSYNTHESIZED_WIRE_2 =  ~clrpc;\n\n\ninc_dec\tb2v_inst_inc_dec(\n\t.limit6(ctl_inc_limit6),\n\t.decrement(ctl_inc_dec),\n\t.carry_in(ctl_inc_cy),\n\t.d(Q),\n\t.address(SYNTHESIZED_WIRE_7));\n\n\naddress_mux\tb2v_mux(\n\t.select(ctl_apin_mux),\n\t.in0(abusz),\n\t.in1(SYNTHESIZED_WIRE_7),\n\t.out(SYNTHESIZED_WIRE_5));\n\nassign\tSYNTHESIZED_WIRE_4 =  ~Q[0];\n\n\nendmodule\n"
  },
  {
    "path": "cpu/bus/address_mux.bdf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"graphic\" (version \"1.4\"))\n(pin\n\t(input)\n\t(rect 32 168 208 184)\n\t(text \"INPUT\" (rect 133 0 161 10)(font \"Arial\" (font_size 6)))\n\t(text \"select\" (rect 9 0 38 12)(font \"Arial\" ))\n\t(pt 176 8)\n\t(drawing\n\t\t(line (pt 92 12)(pt 117 12))\n\t\t(line (pt 92 4)(pt 117 4))\n\t\t(line (pt 121 8)(pt 176 8))\n\t\t(line (pt 92 12)(pt 92 4))\n\t\t(line (pt 117 4)(pt 121 8))\n\t\t(line (pt 117 12)(pt 121 8))\n\t)\n\t(text \"VCC\" (rect 136 7 156 17)(font \"Arial\" (font_size 6)))\n)\n(pin\n\t(input)\n\t(rect 32 48 208 64)\n\t(text \"INPUT\" (rect 133 0 161 10)(font \"Arial\" (font_size 6)))\n\t(text \"in1[15..0]\" (rect 9 0 55 12)(font \"Arial\" ))\n\t(pt 176 8)\n\t(drawing\n\t\t(line (pt 92 12)(pt 117 12))\n\t\t(line (pt 92 4)(pt 117 4))\n\t\t(line (pt 121 8)(pt 176 8))\n\t\t(line (pt 92 12)(pt 92 4))\n\t\t(line (pt 117 4)(pt 121 8))\n\t\t(line (pt 117 12)(pt 121 8))\n\t)\n\t(text \"VCC\" (rect 136 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  },
  {
    "path": "cpu/bus/address_mux.bsf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"symbol\" (version \"1.2\"))\n(symbol\n\t(rect 64 64 152 208)\n\t(text \"address_mux\" (rect 5 0 82 14)(font \"Arial\" (font_size 8)))\n\t(text \"inst\" (rect 0 128 17 140)(font \"Arial\" ))\n\t(port\n\t\t(pt 0 32)\n\t\t(input)\n\t\t(text \"in1[15..0]\" (rect 0 0 51 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"in1[15..0]\" (rect 21 27 72 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 32)(pt 16 32)(line_width 3))\n\t)\n\t(port\n\t\t(pt 0 72)\n\t\t(input)\n\t\t(text \"in0[15..0]\" (rect 0 0 51 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"in0[15..0]\" (rect 21 67 72 81)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 72)(pt 16 72)(line_width 3))\n\t)\n\t(port\n\t\t(pt 0 120)\n\t\t(input)\n\t\t(text \"select\" (rect 0 0 34 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"select\" (rect 5 99 39 113)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 120)(pt 16 120))\n\t)\n\t(port\n\t\t(pt 88 56)\n\t\t(output)\n\t\t(text \"out[15..0]\" (rect -72 0 -19 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"out[15..0]\" (rect 24 48 77 62)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 88 56)(pt 72 56)(line_width 3))\n\t)\n\t(drawing\n\t\t(line (pt 8 16)(pt 80 40))\n\t\t(line (pt 8 120)(pt 48 120))\n\t\t(line (pt 80 40)(pt 80 72))\n\t\t(line (pt 8 16)(pt 8 96))\n\t\t(line (pt 80 72)(pt 8 96))\n\t\t(line (pt 48 120)(pt 48 80))\n\t)\n)\n"
  },
  {
    "path": "cpu/bus/address_mux.v",
    "content": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and other software and tools, and its AMPP partner logic \n// functions, and any output files from any of the foregoing \n// (including device programming or simulation files), and any \n// associated documentation or information are expressly subject \n// to the terms and conditions of the Altera Program License \n// Subscription Agreement, Altera MegaCore Function License \n// Agreement, or other applicable license agreement, including, \n// without limitation, that your use is for the sole purpose of \n// programming logic devices manufactured by Altera and sold by \n// Altera or its authorized distributors.  Please refer to the \n// applicable agreement for further details.\n\n// PROGRAM\t\t\"Quartus II 64-Bit\"\n// VERSION\t\t\"Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\"\n// CREATED\t\t\"Sat Nov 08 09:37:58 2014\"\n\nmodule address_mux(\n\tselect,\n\tin0,\n\tin1,\n\tout\n);\n\n\ninput wire\tselect;\ninput wire\t[15:0] in0;\ninput wire\t[15:0] in1;\noutput wire\t[15:0] out;\n\nwire\tSYNTHESIZED_WIRE_0;\nwire\t[15:0] SYNTHESIZED_WIRE_1;\nwire\t[15:0] SYNTHESIZED_WIRE_2;\n\n\n\n\nassign\tSYNTHESIZED_WIRE_1 = in0 & {SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0};\n\nassign\tSYNTHESIZED_WIRE_2 = in1 & {select,select,select,select,select,select,select,select,select,select,select,select,select,select,select,select};\n\nassign\tSYNTHESIZED_WIRE_0 =  ~select;\n\nassign\tout = SYNTHESIZED_WIRE_1 | SYNTHESIZED_WIRE_2;\n\n\nendmodule\n"
  },
  {
    "path": "cpu/bus/address_pins.bdf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"graphic\" (version \"1.4\"))\n(pin\n\t(input)\n\t(rect 40 80 216 96)\n\t(text \"INPUT\" (rect 133 0 161 10)(font \"Arial\" (font_size 6)))\n\t(text \"address[15..0]\" (rect 9 0 79 12)(font \"Arial\" ))\n\t(pt 176 8)\n\t(drawing\n\t\t(line (pt 92 12)(pt 117 12))\n\t\t(line (pt 92 4)(pt 117 4))\n\t\t(line (pt 121 8)(pt 176 8))\n\t\t(line (pt 92 12)(pt 92 4))\n\t\t(line (pt 117 4)(pt 121 8))\n\t\t(line (pt 117 12)(pt 121 8))\n\t)\n\t(text \"VCC\" (rect 136 7 156 17)(font \"Arial\" (font_size 6)))\n)\n(pin\n\t(input)\n\t(rect 40 96 216 112)\n\t(text \"INPUT\" (rect 133 0 161 10)(font \"Arial\" (font_size 6)))\n\t(text \"clk\" (rect 9 0 23 12)(font \"Arial\" ))\n\t(pt 176 8)\n\t(drawing\n\t\t(line (pt 92 12)(pt 117 12))\n\t\t(line (pt 92 4)(pt 117 4))\n\t\t(line (pt 121 8)(pt 176 8))\n\t\t(line (pt 92 12)(pt 92 4))\n\t\t(line (pt 117 4)(pt 121 8))\n\t\t(line (pt 117 12)(pt 121 8))\n\t)\n\t(text \"VCC\" (rect 136 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  },
  {
    "path": "cpu/bus/address_pins.bsf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"symbol\" (version \"1.2\"))\n(symbol\n\t(rect 16 16 224 144)\n\t(text \"address_pins\" (rect 5 0 82 14)(font \"Arial\" (font_size 8)))\n\t(text \"inst\" (rect 8 112 25 124)(font \"Arial\" ))\n\t(port\n\t\t(pt 0 32)\n\t\t(input)\n\t\t(text \"pin_control_oe\" (rect 0 0 83 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"pin_control_oe\" (rect 21 27 104 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 32)(pt 16 32))\n\t)\n\t(port\n\t\t(pt 0 48)\n\t\t(input)\n\t\t(text \"address[15..0]\" (rect 0 0 82 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"address[15..0]\" (rect 21 43 103 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 48)(pt 16 48)(line_width 3))\n\t)\n\t(port\n\t\t(pt 0 64)\n\t\t(input)\n\t\t(text \"clk\" (rect 0 0 15 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"clk\" (rect 21 59 36 73)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 64)(pt 16 64))\n\t)\n\t(port\n\t\t(pt 0 80)\n\t\t(input)\n\t\t(text \"bus_ab_pin_we\" (rect 0 0 92 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"bus_ab_pin_we\" (rect 21 75 113 89)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 80)(pt 16 80))\n\t)\n\t(port\n\t\t(pt 208 32)\n\t\t(output)\n\t\t(text \"abus[15..0]\" (rect 0 0 63 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"abus[15..0]\" (rect 124 27 187 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 208 32)(pt 192 32)(line_width 3))\n\t)\n\t(drawing\n\t\t(rectangle (rect 16 16 192 112))\n\t)\n)\n"
  },
  {
    "path": "cpu/bus/address_pins.v",
    "content": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and other software and tools, and its AMPP partner logic \n// functions, and any output files from any of the foregoing \n// (including device programming or simulation files), and any \n// associated documentation or information are expressly subject \n// to the terms and conditions of the Altera Program License \n// Subscription Agreement, Altera MegaCore Function License \n// Agreement, or other applicable license agreement, including, \n// without limitation, that your use is for the sole purpose of \n// programming logic devices manufactured by Altera and sold by \n// Altera or its authorized distributors.  Please refer to the \n// applicable agreement for further details.\n\n// PROGRAM\t\t\"Quartus II 64-Bit\"\n// VERSION\t\t\"Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\"\n// CREATED\t\t\"Sun Nov 16 16:56:05 2014\"\n\nmodule address_pins(\n\tclk,\n\tbus_ab_pin_we,\n\tpin_control_oe,\n\taddress,\n\tabus\n);\n\n\ninput wire\tclk;\ninput wire\tbus_ab_pin_we;\ninput wire\tpin_control_oe;\ninput wire\t[15:0] address;\noutput wire\t[15:0] abus;\n\nwire\tSYNTHESIZED_WIRE_0;\nreg\t[15:0] DFFE_apin_latch;\n\n\n\n\n\nalways@(posedge SYNTHESIZED_WIRE_0)\nbegin\nif (bus_ab_pin_we)\n\tbegin\n\tDFFE_apin_latch[15:0] <= address[15:0];\n\tend\nend\n\nassign\tabus[15] = pin_control_oe ? DFFE_apin_latch[15] : 1'bz;\nassign\tabus[14] = pin_control_oe ? DFFE_apin_latch[14] : 1'bz;\nassign\tabus[13] = pin_control_oe ? DFFE_apin_latch[13] : 1'bz;\nassign\tabus[12] = pin_control_oe ? DFFE_apin_latch[12] : 1'bz;\nassign\tabus[11] = pin_control_oe ? DFFE_apin_latch[11] : 1'bz;\nassign\tabus[10] = pin_control_oe ? DFFE_apin_latch[10] : 1'bz;\nassign\tabus[9] = pin_control_oe ? DFFE_apin_latch[9] : 1'bz;\nassign\tabus[8] = pin_control_oe ? DFFE_apin_latch[8] : 1'bz;\nassign\tabus[7] = pin_control_oe ? DFFE_apin_latch[7] : 1'bz;\nassign\tabus[6] = pin_control_oe ? DFFE_apin_latch[6] : 1'bz;\nassign\tabus[5] = pin_control_oe ? DFFE_apin_latch[5] : 1'bz;\nassign\tabus[4] = pin_control_oe ? DFFE_apin_latch[4] : 1'bz;\nassign\tabus[3] = pin_control_oe ? DFFE_apin_latch[3] : 1'bz;\nassign\tabus[2] = pin_control_oe ? DFFE_apin_latch[2] : 1'bz;\nassign\tabus[1] = pin_control_oe ? DFFE_apin_latch[1] : 1'bz;\nassign\tabus[0] = pin_control_oe ? DFFE_apin_latch[0] : 1'bz;\n\nassign\tSYNTHESIZED_WIRE_0 =  ~clk;\n\n\nendmodule\n"
  },
  {
    "path": "cpu/bus/bus_control.bdf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"graphic\" (version \"1.4\"))\n(pin\n\t(input)\n\t(rect 32 64 208 80)\n\t(text \"INPUT\" (rect 133 0 161 10)(font \"Arial\" (font_size 6)))\n\t(text \"ctl_bus_ff_oe\" (rect 9 0 77 12)(font \"Arial\" ))\n\t(pt 176 8)\n\t(drawing\n\t\t(line (pt 92 12)(pt 117 12))\n\t\t(line (pt 92 4)(pt 117 4))\n\t\t(line (pt 121 8)(pt 176 8))\n\t\t(line (pt 92 12)(pt 92 4))\n\t\t(line (pt 117 4)(pt 121 8))\n\t\t(line (pt 117 12)(pt 121 8))\n\t)\n\t(text \"VCC\" (rect 136 7 156 17)(font \"Arial\" (font_size 6)))\n)\n(pin\n\t(input)\n\t(rect 32 48 208 64)\n\t(text \"INPUT\" (rect 133 0 161 10)(font \"Arial\" (font_size 6)))\n\t(text \"ctl_bus_zero_oe\" (rect 9 0 88 12)(font \"Arial\" ))\n\t(pt 176 8)\n\t(drawing\n\t\t(line (pt 92 12)(pt 117 12))\n\t\t(line (pt 92 4)(pt 117 4))\n\t\t(line (pt 121 8)(pt 176 8))\n\t\t(line (pt 92 12)(pt 92 4))\n\t\t(line (pt 117 4)(pt 121 8))\n\t\t(line (pt 117 12)(pt 121 8))\n\t)\n\t(text \"VCC\" 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    "path": "cpu/bus/bus_control.bsf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"symbol\" (version \"1.2\"))\n(symbol\n\t(rect 16 16 208 112)\n\t(text \"bus_control\" (rect 5 0 72 14)(font \"Arial\" (font_size 8)))\n\t(text \"inst\" (rect 8 80 25 92)(font \"Arial\" ))\n\t(port\n\t\t(pt 0 32)\n\t\t(input)\n\t\t(text \"ctl_bus_zero_oe\" (rect 0 0 95 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"ctl_bus_zero_oe\" (rect 21 27 116 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 32)(pt 16 32))\n\t)\n\t(port\n\t\t(pt 0 48)\n\t\t(input)\n\t\t(text \"ctl_bus_ff_oe\" (rect 0 0 79 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"ctl_bus_ff_oe\" (rect 21 43 100 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 48)(pt 16 48))\n\t)\n\t(port\n\t\t(pt 192 32)\n\t\t(bidir)\n\t\t(text \"db[7..0]\" (rect 0 0 42 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"db[7..0]\" (rect 129 27 171 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 192 32)(pt 176 32)(line_width 3))\n\t)\n\t(drawing\n\t\t(rectangle (rect 16 16 176 80))\n\t)\n)\n"
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  {
    "path": "cpu/bus/bus_control.v",
    "content": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and other software and tools, and its AMPP partner logic \n// functions, and any output files from any of the foregoing \n// (including device programming or simulation files), and any \n// associated documentation or information are expressly subject \n// to the terms and conditions of the Altera Program License \n// Subscription Agreement, Altera MegaCore Function License \n// Agreement, or other applicable license agreement, including, \n// without limitation, that your use is for the sole purpose of \n// programming logic devices manufactured by Altera and sold by \n// Altera or its authorized distributors.  Please refer to the \n// applicable agreement for further details.\n\n// PROGRAM\t\t\"Quartus II 64-Bit\"\n// VERSION\t\t\"Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\"\n// CREATED\t\t\"Fri Feb 26 22:25:37 2016\"\n\nmodule bus_control(\n\tctl_bus_ff_oe,\n\tctl_bus_zero_oe,\n\tdb\n);\n\n\ninput wire\tctl_bus_ff_oe;\ninput wire\tctl_bus_zero_oe;\ninout wire\t[7:0] db;\n\nwire\t[7:0] bus;\nwire\t[7:0] vcc;\nwire\tSYNTHESIZED_WIRE_0;\n\n\n\n\nassign\tdb[7] = SYNTHESIZED_WIRE_0 ? bus[7] : 1'bz;\nassign\tdb[6] = SYNTHESIZED_WIRE_0 ? bus[6] : 1'bz;\nassign\tdb[5] = SYNTHESIZED_WIRE_0 ? bus[5] : 1'bz;\nassign\tdb[4] = SYNTHESIZED_WIRE_0 ? bus[4] : 1'bz;\nassign\tdb[3] = SYNTHESIZED_WIRE_0 ? bus[3] : 1'bz;\nassign\tdb[2] = SYNTHESIZED_WIRE_0 ? bus[2] : 1'bz;\nassign\tdb[1] = SYNTHESIZED_WIRE_0 ? bus[1] : 1'bz;\nassign\tdb[0] = SYNTHESIZED_WIRE_0 ? bus[0] : 1'bz;\n\n\nassign\tbus = {ctl_bus_ff_oe,ctl_bus_ff_oe,ctl_bus_ff_oe,ctl_bus_ff_oe,ctl_bus_ff_oe,ctl_bus_ff_oe,ctl_bus_ff_oe,ctl_bus_ff_oe} & vcc;\n\nassign\tSYNTHESIZED_WIRE_0 = ctl_bus_ff_oe | ctl_bus_zero_oe;\n\nassign\tvcc = 8'b11111111;\n\nendmodule\n"
  },
  {
    "path": "cpu/bus/bus_switch.bsf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"symbol\" (version \"1.1\"))\n(symbol\n\t(rect 16 16 288 160)\n\t(text \"bus_switch\" (rect 5 0 48 12)(font \"Arial\" ))\n\t(text \"inst\" (rect 8 128 20 140)(font \"Arial\" ))\n\t(port\n\t\t(pt 0 32)\n\t\t(input)\n\t\t(text \"ctl_sw_1u\" (rect 0 0 38 12)(font \"Arial\" ))\n\t\t(text \"ctl_sw_1u\" (rect 21 27 59 39)(font \"Arial\" ))\n\t\t(line (pt 0 32)(pt 16 32)(line_width 1))\n\t)\n\t(port\n\t\t(pt 0 48)\n\t\t(input)\n\t\t(text \"ctl_sw_1d\" (rect 0 0 38 12)(font \"Arial\" ))\n\t\t(text \"ctl_sw_1d\" (rect 21 43 59 55)(font \"Arial\" ))\n\t\t(line (pt 0 48)(pt 16 48)(line_width 1))\n\t)\n\t(port\n\t\t(pt 0 64)\n\t\t(input)\n\t\t(text \"ctl_sw_2u\" (rect 0 0 40 12)(font \"Arial\" ))\n\t\t(text \"ctl_sw_2u\" (rect 21 59 61 71)(font \"Arial\" ))\n\t\t(line (pt 0 64)(pt 16 64)(line_width 1))\n\t)\n\t(port\n\t\t(pt 0 80)\n\t\t(input)\n\t\t(text \"ctl_sw_2d\" (rect 0 0 40 12)(font \"Arial\" ))\n\t\t(text \"ctl_sw_2d\" (rect 21 75 61 87)(font \"Arial\" ))\n\t\t(line (pt 0 80)(pt 16 80)(line_width 1))\n\t)\n\t(port\n\t\t(pt 0 96)\n\t\t(input)\n\t\t(text \"ctl_sw_mask543_en\" (rect 0 0 83 12)(font \"Arial\" ))\n\t\t(text \"ctl_sw_mask543_en\" (rect 21 91 104 103)(font \"Arial\" ))\n\t\t(line (pt 0 96)(pt 16 96)(line_width 1))\n\t)\n\t(port\n\t\t(pt 272 32)\n\t\t(output)\n\t\t(text \"bus_sw_1u\" (rect 0 0 44 12)(font \"Arial\" ))\n\t\t(text \"bus_sw_1u\" (rect 207 27 251 39)(font \"Arial\" ))\n\t\t(line (pt 272 32)(pt 256 32)(line_width 1))\n\t)\n\t(port\n\t\t(pt 272 48)\n\t\t(output)\n\t\t(text \"bus_sw_1d\" (rect 0 0 44 12)(font \"Arial\" ))\n\t\t(text \"bus_sw_1d\" (rect 207 43 251 55)(font \"Arial\" ))\n\t\t(line (pt 272 48)(pt 256 48)(line_width 1))\n\t)\n\t(port\n\t\t(pt 272 64)\n\t\t(output)\n\t\t(text \"bus_sw_2u\" (rect 0 0 46 12)(font \"Arial\" ))\n\t\t(text \"bus_sw_2u\" (rect 205 59 251 71)(font \"Arial\" ))\n\t\t(line (pt 272 64)(pt 256 64)(line_width 1))\n\t)\n\t(port\n\t\t(pt 272 80)\n\t\t(output)\n\t\t(text \"bus_sw_2d\" (rect 0 0 46 12)(font \"Arial\" ))\n\t\t(text \"bus_sw_2d\" (rect 205 75 251 87)(font \"Arial\" ))\n\t\t(line (pt 272 80)(pt 256 80)(line_width 1))\n\t)\n\t(port\n\t\t(pt 272 96)\n\t\t(output)\n\t\t(text \"bus_sw_mask543_en\" (rect 0 0 89 12)(font \"Arial\" ))\n\t\t(text \"bus_sw_mask543_en\" (rect 162 91 251 103)(font \"Arial\" ))\n\t\t(line (pt 272 96)(pt 256 96)(line_width 1))\n\t)\n\t(drawing\n\t\t(rectangle (rect 16 16 256 128)(line_width 1))\n\t)\n)\n"
  },
  {
    "path": "cpu/bus/bus_switch.v",
    "content": "//============================================================================\n// Bus switch in bus A-Z80 CPU\n//\n// Copyright 2014, 2016 Goran Devic\n//\n// This module provides control data bus switch signals. The sole purpose of\n// having these wires defined in this module is to get all control signals\n// (which are processed by genglobals.py) to appear in the list of global\n// control signals (\"globals.vh\") for consistency.\n//============================================================================\n\nmodule bus_switch\n(\n    input wire ctl_sw_1u,               // Control input for the SW1 upstream\n    input wire ctl_sw_1d,               // Control input for the SW1 downstream\n\n    input wire ctl_sw_2u,               // Control input for the SW2 upstream\n    input wire ctl_sw_2d,               // Control input for the SW2 downstream\n\n    input wire ctl_sw_mask543_en,       // Enables masking [5:3] on the data bus switch 1\n\n    //--------------------------------------------------------------------\n\n    output wire bus_sw_1u,              // SW1 upstream\n    output wire bus_sw_1d,              // SW1 downstream\n\n    output wire bus_sw_2u,              // SW2 upstream\n    output wire bus_sw_2d,              // SW2 downstream\n\n    output wire bus_sw_mask543_en       // Affects SW1 downstream\n);\n\nassign bus_sw_1u = ctl_sw_1u;\nassign bus_sw_1d = ctl_sw_1d;\n\nassign bus_sw_2u = ctl_sw_2u;\nassign bus_sw_2d = ctl_sw_2d;\n\nassign bus_sw_mask543_en = ctl_sw_mask543_en;\n\nendmodule\n"
  },
  {
    "path": "cpu/bus/control_pins_n.bdf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  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  },
  {
    "path": "cpu/bus/control_pins_n.bsf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"symbol\" (version \"1.2\"))\n(symbol\n\t(rect 16 16 232 304)\n\t(text \"control_pins_n\" (rect 5 0 88 14)(font \"Arial\" (font_size 8)))\n\t(text \"inst\" (rect 8 272 25 284)(font \"Arial\" ))\n\t(port\n\t\t(pt 0 32)\n\t\t(input)\n\t\t(text \"nM1_out\" (rect 0 0 48 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"nM1_out\" (rect 21 27 69 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 32)(pt 16 32))\n\t)\n\t(port\n\t\t(pt 0 48)\n\t\t(input)\n\t\t(text \"pin_control_oe\" (rect 0 0 83 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"pin_control_oe\" (rect 21 43 104 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 48)(pt 16 48))\n\t)\n\t(port\n\t\t(pt 0 64)\n\t\t(input)\n\t\t(text \"nMREQ_out\" (rect 0 0 66 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"nMREQ_out\" (rect 21 59 87 73)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 64)(pt 16 64))\n\t)\n\t(port\n\t\t(pt 0 80)\n\t\t(input)\n\t\t(text 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  },
  {
    "path": "cpu/bus/control_pins_n.v",
    "content": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and other software and tools, and its AMPP partner logic \n// functions, and any output files from any of the foregoing \n// (including device programming or simulation files), and any \n// associated documentation or information are expressly subject \n// to the terms and conditions of the Altera Program License \n// Subscription Agreement, Altera MegaCore Function License \n// Agreement, or other applicable license agreement, including, \n// without limitation, that your use is for the sole purpose of \n// programming logic devices manufactured by Altera and sold by \n// Altera or its authorized distributors.  Please refer to the \n// applicable agreement for further details.\n\n// PROGRAM\t\t\"Quartus II 64-Bit\"\n// VERSION\t\t\"Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\"\n// CREATED\t\t\"Sun Nov 16 23:06:14 2014\"\n\nmodule control_pins_n(\n\tbusack,\n\tCPUCLK,\n\tpin_control_oe,\n\tin_halt,\n\tpin_nWAIT,\n\tpin_nBUSRQ,\n\tpin_nINT,\n\tpin_nNMI,\n\tpin_nRESET,\n\tnM1_out,\n\tnRFSH_out,\n\tnRD_out,\n\tnWR_out,\n\tnIORQ_out,\n\tnMREQ_out,\n\tnmi,\n\tbusrq,\n\tclk,\n\tintr,\n\tmwait,\n\treset_in,\n\tpin_nM1,\n\tpin_nMREQ,\n\tpin_nIORQ,\n\tpin_nRD,\n\tpin_nWR,\n\tpin_nRFSH,\n\tpin_nHALT,\n\tpin_nBUSACK\n);\n\n\ninput wire\tbusack;\ninput wire\tCPUCLK;\ninput wire\tpin_control_oe;\ninput wire\tin_halt;\ninput wire\tpin_nWAIT;\ninput wire\tpin_nBUSRQ;\ninput wire\tpin_nINT;\ninput wire\tpin_nNMI;\ninput wire\tpin_nRESET;\ninput wire\tnM1_out;\ninput wire\tnRFSH_out;\ninput wire\tnRD_out;\ninput wire\tnWR_out;\ninput wire\tnIORQ_out;\ninput wire\tnMREQ_out;\noutput wire\tnmi;\noutput wire\tbusrq;\noutput wire\tclk;\noutput wire\tintr;\noutput wire\tmwait;\noutput wire\treset_in;\noutput wire\tpin_nM1;\noutput wire\tpin_nMREQ;\noutput wire\tpin_nIORQ;\noutput wire\tpin_nRD;\noutput wire\tpin_nWR;\noutput wire\tpin_nRFSH;\noutput wire\tpin_nHALT;\noutput wire\tpin_nBUSACK;\n\n\nassign\tclk = CPUCLK;\nassign\tpin_nM1 = nM1_out;\nassign\tpin_nRFSH = nRFSH_out;\n\n\n\nassign\tpin_nMREQ = pin_control_oe ? nMREQ_out : 1'bz;\n\nassign\tpin_nIORQ = pin_control_oe ? nIORQ_out : 1'bz;\n\nassign\tpin_nRD = pin_control_oe ? nRD_out : 1'bz;\n\nassign\tpin_nWR = pin_control_oe ? nWR_out : 1'bz;\n\nassign\tbusrq =  ~pin_nBUSRQ;\n\nassign\tpin_nHALT =  ~in_halt;\n\nassign\tmwait =  ~pin_nWAIT;\n\nassign\tpin_nBUSACK =  ~busack;\n\nassign\tintr =  ~pin_nINT;\n\nassign\tnmi =  ~pin_nNMI;\n\nassign\treset_in =  ~pin_nRESET;\n\n\nendmodule\n"
  },
  {
    "path": "cpu/bus/data_pins.bdf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  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  {
    "path": "cpu/bus/data_pins.bsf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"symbol\" (version \"1.2\"))\n(symbol\n\t(rect 16 16 200 144)\n\t(text \"data_pins\" (rect 5 0 60 14)(font \"Arial\" (font_size 8)))\n\t(text \"inst\" (rect 8 112 25 124)(font \"Arial\" ))\n\t(port\n\t\t(pt 0 32)\n\t\t(input)\n\t\t(text \"bus_db_pin_oe\" (rect 0 0 87 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"bus_db_pin_oe\" (rect 21 27 108 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 32)(pt 16 32))\n\t)\n\t(port\n\t\t(pt 0 48)\n\t\t(input)\n\t\t(text \"clk\" (rect 0 0 15 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"clk\" (rect 21 43 36 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 48)(pt 16 48))\n\t)\n\t(port\n\t\t(pt 0 64)\n\t\t(input)\n\t\t(text \"bus_db_pin_re\" (rect 0 0 84 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"bus_db_pin_re\" (rect 21 59 105 73)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 64)(pt 16 64))\n\t)\n\t(port\n\t\t(pt 0 80)\n\t\t(input)\n\t\t(text \"ctl_bus_db_we\" (rect 0 0 88 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"ctl_bus_db_we\" (rect 21 75 109 89)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 80)(pt 16 80))\n\t)\n\t(port\n\t\t(pt 0 96)\n\t\t(input)\n\t\t(text \"ctl_bus_db_oe\" (rect 0 0 83 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"ctl_bus_db_oe\" (rect 21 91 104 105)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 96)(pt 16 96))\n\t)\n\t(port\n\t\t(pt 184 32)\n\t\t(bidir)\n\t\t(text \"D[7..0]\" (rect 0 0 36 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"D[7..0]\" (rect 127 27 163 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 184 32)(pt 168 32)(line_width 3))\n\t)\n\t(port\n\t\t(pt 184 48)\n\t\t(bidir)\n\t\t(text \"db[7..0]\" (rect 0 0 42 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"db[7..0]\" (rect 121 43 163 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 184 48)(pt 168 48)(line_width 3))\n\t)\n\t(drawing\n\t\t(rectangle (rect 16 16 168 112))\n\t)\n)\n"
  },
  {
    "path": "cpu/bus/data_pins.v",
    "content": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and other software and tools, and its AMPP partner logic \n// functions, and any output files from any of the foregoing \n// (including device programming or simulation files), and any \n// associated documentation or information are expressly subject \n// to the terms and conditions of the Altera Program License \n// Subscription Agreement, Altera MegaCore Function License \n// Agreement, or other applicable license agreement, including, \n// without limitation, that your use is for the sole purpose of \n// programming logic devices manufactured by Altera and sold by \n// Altera or its authorized distributors.  Please refer to the \n// applicable agreement for further details.\n\n// PROGRAM\t\t\"Quartus II 64-Bit\"\n// VERSION\t\t\"Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\"\n// CREATED\t\t\"Thu Nov 06 23:28:26 2014\"\n\nmodule data_pins(\n\tbus_db_pin_oe,\n\tbus_db_pin_re,\n\tctl_bus_db_we,\n\tclk,\n\tctl_bus_db_oe,\n\tD,\n\tdb\n);\n\n\ninput wire\tbus_db_pin_oe;\ninput wire\tbus_db_pin_re;\ninput wire\tctl_bus_db_we;\ninput wire\tclk;\ninput wire\tctl_bus_db_oe;\ninout wire\t[7:0] D;\ninout wire\t[7:0] db;\n\nreg\t[7:0] dout;\nwire\t[7:0] SYNTHESIZED_WIRE_0;\nwire\tSYNTHESIZED_WIRE_1;\nwire\tSYNTHESIZED_WIRE_2;\nwire\t[7:0] SYNTHESIZED_WIRE_3;\nwire\t[7:0] SYNTHESIZED_WIRE_4;\n\n\n\n\n\nalways@(posedge SYNTHESIZED_WIRE_1)\nbegin\nif (SYNTHESIZED_WIRE_2)\n\tbegin\n\tdout[7:0] <= SYNTHESIZED_WIRE_0[7:0];\n\tend\nend\n\nassign\tSYNTHESIZED_WIRE_4 = {ctl_bus_db_we,ctl_bus_db_we,ctl_bus_db_we,ctl_bus_db_we,ctl_bus_db_we,ctl_bus_db_we,ctl_bus_db_we,ctl_bus_db_we} & db;\n\nassign\tSYNTHESIZED_WIRE_3 = {bus_db_pin_re,bus_db_pin_re,bus_db_pin_re,bus_db_pin_re,bus_db_pin_re,bus_db_pin_re,bus_db_pin_re,bus_db_pin_re} & D;\n\nassign\tSYNTHESIZED_WIRE_0 = SYNTHESIZED_WIRE_3 | SYNTHESIZED_WIRE_4;\n\nassign\tSYNTHESIZED_WIRE_2 = ctl_bus_db_we | bus_db_pin_re;\n\nassign\tdb[7] = ctl_bus_db_oe ? dout[7] : 1'bz;\nassign\tdb[6] = ctl_bus_db_oe ? dout[6] : 1'bz;\nassign\tdb[5] = ctl_bus_db_oe ? dout[5] : 1'bz;\nassign\tdb[4] = ctl_bus_db_oe ? dout[4] : 1'bz;\nassign\tdb[3] = ctl_bus_db_oe ? dout[3] : 1'bz;\nassign\tdb[2] = ctl_bus_db_oe ? dout[2] : 1'bz;\nassign\tdb[1] = ctl_bus_db_oe ? dout[1] : 1'bz;\nassign\tdb[0] = ctl_bus_db_oe ? dout[0] : 1'bz;\n\nassign\tD[7] = bus_db_pin_oe ? dout[7] : 1'bz;\nassign\tD[6] = bus_db_pin_oe ? dout[6] : 1'bz;\nassign\tD[5] = bus_db_pin_oe ? dout[5] : 1'bz;\nassign\tD[4] = bus_db_pin_oe ? dout[4] : 1'bz;\nassign\tD[3] = bus_db_pin_oe ? dout[3] : 1'bz;\nassign\tD[2] = bus_db_pin_oe ? dout[2] : 1'bz;\nassign\tD[1] = bus_db_pin_oe ? dout[1] : 1'bz;\nassign\tD[0] = bus_db_pin_oe ? dout[0] : 1'bz;\n\nassign\tSYNTHESIZED_WIRE_1 =  ~clk;\n\n\nendmodule\n"
  },
  {
    "path": "cpu/bus/data_pins_lattice.v",
    "content": "// Use this file with Lattice toolset instead of data_pins.v\n//\n// This file is provided courtesy by JuanS\n\nmodule data_pins(\n    bus_db_pin_oe,\n    bus_db_pin_re,\n    ctl_bus_db_we,\n    clk,\n    ctl_bus_db_oe,\n    D,\n    db\n);\n\ninput wire bus_db_pin_oe;\ninput wire bus_db_pin_re;\ninput wire ctl_bus_db_we;\ninput wire clk;\ninput wire ctl_bus_db_oe;\ninout wire [7:0] D;\ninout wire [7:0] db;\n\nreg [7:0] dout;\n\nalways@(negedge clk)\nbegin\n    if (ctl_bus_db_we | bus_db_pin_re)\n    begin\n        if (bus_db_pin_re)\n        dout <= D;\n    else if (ctl_bus_db_we)\n        dout <= db;\n    end\nend\n\nassign db = ctl_bus_db_oe ? dout : 8'hZ;\nassign D = bus_db_pin_oe ? dout : 8'hZ;\n\nendmodule\n"
  },
  {
    "path": "cpu/bus/data_switch.bdf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"graphic\" (version \"1.4\"))\n(pin\n\t(input)\n\t(rect 32 32 208 48)\n\t(text \"INPUT\" (rect 133 0 161 10)(font \"Arial\" (font_size 6)))\n\t(text \"sw_up_en\" (rect 9 0 57 12)(font \"Arial\" ))\n\t(pt 176 8)\n\t(drawing\n\t\t(line (pt 92 12)(pt 117 12))\n\t\t(line (pt 92 4)(pt 117 4))\n\t\t(line (pt 121 8)(pt 176 8))\n\t\t(line (pt 92 12)(pt 92 4))\n\t\t(line (pt 117 4)(pt 121 8))\n\t\t(line (pt 117 12)(pt 121 8))\n\t)\n\t(text \"VCC\" (rect 136 7 156 17)(font \"Arial\" (font_size 6)))\n)\n(pin\n\t(input)\n\t(rect 32 128 208 144)\n\t(text \"INPUT\" (rect 133 0 161 10)(font \"Arial\" (font_size 6)))\n\t(text \"sw_down_en\" (rect 9 0 70 12)(font \"Arial\" ))\n\t(pt 176 8)\n\t(drawing\n\t\t(line (pt 92 12)(pt 117 12))\n\t\t(line (pt 92 4)(pt 117 4))\n\t\t(line (pt 121 8)(pt 176 8))\n\t\t(line (pt 92 12)(pt 92 4))\n\t\t(line (pt 117 4)(pt 121 8))\n\t\t(line (pt 117 12)(pt 121 8))\n\t)\n\t(text \"VCC\" (rect 136 7 156 17)(font \"Arial\" (font_size 6)))\n)\n(pin\n\t(bidir)\n\t(rect 32 80 208 96)\n\t(text \"BIDIR\" (rect 151 0 175 10)(font \"Arial\" (font_size 6)))\n\t(text \"db_down[7..0]\" (rect 18 0 86 12)(font \"Arial\" ))\n\t(pt 176 8)\n\t(drawing\n\t\t(line (pt 120 4)(pt 98 4))\n\t\t(line (pt 176 8)(pt 124 8))\n\t\t(line (pt 120 12)(pt 98 12))\n\t\t(line (pt 98 4)(pt 94 8))\n\t\t(line (pt 98 12)(pt 94 8))\n\t\t(line (pt 120 4)(pt 124 8))\n\t\t(line (pt 124 8)(pt 120 12))\n\t)\n\t(flipy)\n\t(text \"VCC\" (rect 152 7 172 17)(font \"Arial\" (font_size 6)))\n)\n(pin\n\t(bidir)\n\t(rect 352 80 528 96)\n\t(text \"BIDIR\" (rect 1 0 25 10)(font \"Arial\" (font_size 6)))\n\t(text \"db_up[7..0]\" (rect 90 0 145 12)(font \"Arial\" ))\n\t(pt 0 8)\n\t(drawing\n\t\t(line (pt 56 4)(pt 78 4))\n\t\t(line (pt 0 8)(pt 52 8))\n\t\t(line (pt 56 12)(pt 78 12))\n\t\t(line (pt 78 4)(pt 82 8))\n\t\t(line (pt 78 12)(pt 82 8))\n\t\t(line (pt 56 4)(pt 52 8))\n\t\t(line (pt 52 8)(pt 56 12))\n\t)\n\t(text \"VCC\" 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17)(font \"Arial\" (font_size 8)))(border))\n\t(section (rect 0 18 256 34)(text \"DESIGNER\" (rect 2 0 59 12)(font \"Arial\" ))(text \"Goran Devic\" (rect 56 2 135 17)(font \"Arial\" (font_size 9)))(border))\n\t(section (rect 104 0 256 17)(text \"MODULE\" (rect 2 1 48 13)(font \"Arial\" ))(text \"data_switch\" (rect 43 2 125 17)(font \"Arial\" (font_size 9)(bold)))(border))\n\t(section (rect 0 0 256 17)(text \"PROJECT\" (rect 2 0 52 12)(font \"Arial\" ))(text \"A-Z80\" (rect 56 2 94 17)(font \"Arial\" (font_size 9)(bold)))(border))\n\t(section (rect 192 35 256 51)(text \"REV\" (rect 2 1 25 13)(font \"Arial\" ))(text \"1.0\" (rect 43 3 60 17)(font \"Arial\" (font_size 8)))(border))\n\t(drawing\n\t)\n)\n"
  },
  {
    "path": "cpu/bus/data_switch.bsf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"symbol\" (version \"1.2\"))\n(symbol\n\t(rect 16 16 232 112)\n\t(text \"data_switch\" (rect 5 0 75 14)(font \"Arial\" (font_size 8)))\n\t(text \"inst\" (rect 8 80 25 92)(font \"Arial\" ))\n\t(port\n\t\t(pt 0 32)\n\t\t(input)\n\t\t(text \"sw_up_en\" (rect 0 0 61 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"sw_up_en\" (rect 21 27 82 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 32)(pt 16 32))\n\t)\n\t(port\n\t\t(pt 0 48)\n\t\t(input)\n\t\t(text \"sw_down_en\" (rect 0 0 80 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"sw_down_en\" (rect 21 43 101 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 48)(pt 16 48))\n\t)\n\t(port\n\t\t(pt 216 32)\n\t\t(bidir)\n\t\t(text \"db_down[7..0]\" (rect 0 0 82 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"db_down[7..0]\" (rect 113 27 195 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 216 32)(pt 200 32)(line_width 3))\n\t)\n\t(port\n\t\t(pt 216 48)\n\t\t(bidir)\n\t\t(text \"db_up[7..0]\" (rect 0 0 63 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"db_up[7..0]\" (rect 132 43 195 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 216 48)(pt 200 48)(line_width 3))\n\t)\n\t(drawing\n\t\t(rectangle (rect 16 16 200 80))\n\t)\n)\n"
  },
  {
    "path": "cpu/bus/data_switch.v",
    "content": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and other software and tools, and its AMPP partner logic \n// functions, and any output files from any of the foregoing \n// (including device programming or simulation files), and any \n// associated documentation or information are expressly subject \n// to the terms and conditions of the Altera Program License \n// Subscription Agreement, Altera MegaCore Function License \n// Agreement, or other applicable license agreement, including, \n// without limitation, that your use is for the sole purpose of \n// programming logic devices manufactured by Altera and sold by \n// Altera or its authorized distributors.  Please refer to the \n// applicable agreement for further details.\n\n// PROGRAM\t\t\"Quartus II 64-Bit\"\n// VERSION\t\t\"Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\"\n// CREATED\t\t\"Mon Oct 13 12:33:19 2014\"\n\nmodule data_switch(\n\tsw_up_en,\n\tsw_down_en,\n\tdb_down,\n\tdb_up\n);\n\n\ninput wire\tsw_up_en;\ninput wire\tsw_down_en;\ninout wire\t[7:0] db_down;\ninout wire\t[7:0] db_up;\n\n\n\n\n\nassign\tdb_up[7] = sw_up_en ? db_down[7] : 1'bz;\nassign\tdb_up[6] = sw_up_en ? db_down[6] : 1'bz;\nassign\tdb_up[5] = sw_up_en ? db_down[5] : 1'bz;\nassign\tdb_up[4] = sw_up_en ? db_down[4] : 1'bz;\nassign\tdb_up[3] = sw_up_en ? db_down[3] : 1'bz;\nassign\tdb_up[2] = sw_up_en ? db_down[2] : 1'bz;\nassign\tdb_up[1] = sw_up_en ? db_down[1] : 1'bz;\nassign\tdb_up[0] = sw_up_en ? db_down[0] : 1'bz;\n\nassign\tdb_down[7] = sw_down_en ? db_up[7] : 1'bz;\nassign\tdb_down[6] = sw_down_en ? db_up[6] : 1'bz;\nassign\tdb_down[5] = sw_down_en ? db_up[5] : 1'bz;\nassign\tdb_down[4] = sw_down_en ? db_up[4] : 1'bz;\nassign\tdb_down[3] = sw_down_en ? db_up[3] : 1'bz;\nassign\tdb_down[2] = sw_down_en ? db_up[2] : 1'bz;\nassign\tdb_down[1] = sw_down_en ? db_up[1] : 1'bz;\nassign\tdb_down[0] = sw_down_en ? db_up[0] : 1'bz;\n\n\nendmodule\n"
  },
  {
    "path": "cpu/bus/data_switch_mask.bdf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"graphic\" (version \"1.4\"))\n(pin\n\t(input)\n\t(rect 32 32 208 48)\n\t(text \"INPUT\" (rect 133 0 161 10)(font \"Arial\" (font_size 6)))\n\t(text \"sw_up_en\" (rect 9 0 57 12)(font \"Arial\" ))\n\t(pt 176 8)\n\t(drawing\n\t\t(line (pt 92 12)(pt 117 12))\n\t\t(line (pt 92 4)(pt 117 4))\n\t\t(line (pt 121 8)(pt 176 8))\n\t\t(line (pt 92 12)(pt 92 4))\n\t\t(line (pt 117 4)(pt 121 8))\n\t\t(line (pt 117 12)(pt 121 8))\n\t)\n\t(text \"VCC\" (rect 136 7 156 17)(font \"Arial\" (font_size 6)))\n)\n(pin\n\t(input)\n\t(rect 32 304 208 320)\n\t(text \"INPUT\" (rect 133 0 161 10)(font \"Arial\" (font_size 6)))\n\t(text \"sw_down_en\" (rect 9 0 70 12)(font \"Arial\" ))\n\t(pt 176 8)\n\t(drawing\n\t\t(line (pt 92 12)(pt 117 12))\n\t\t(line (pt 92 4)(pt 117 4))\n\t\t(line (pt 121 8)(pt 176 8))\n\t\t(line (pt 92 12)(pt 92 4))\n\t\t(line (pt 117 4)(pt 121 8))\n\t\t(line (pt 117 12)(pt 121 8))\n\t)\n\t(text \"VCC\" (rect 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  },
  {
    "path": "cpu/bus/data_switch_mask.bsf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"symbol\" (version \"1.2\"))\n(symbol\n\t(rect 16 16 248 112)\n\t(text \"data_switch_mask\" (rect 5 0 112 14)(font \"Arial\" (font_size 8)))\n\t(text \"inst\" (rect 8 80 25 92)(font \"Arial\" ))\n\t(port\n\t\t(pt 0 32)\n\t\t(input)\n\t\t(text \"sw_up_en\" (rect 0 0 61 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"sw_up_en\" (rect 21 27 82 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 32)(pt 16 32))\n\t)\n\t(port\n\t\t(pt 0 48)\n\t\t(input)\n\t\t(text \"sw_down_en\" (rect 0 0 80 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"sw_down_en\" (rect 21 43 101 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 48)(pt 16 48))\n\t)\n\t(port\n\t\t(pt 0 64)\n\t\t(input)\n\t\t(text \"sw_mask543_en\" (rect 0 0 97 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"sw_mask543_en\" (rect 21 59 118 73)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 64)(pt 16 64))\n\t)\n\t(port\n\t\t(pt 232 32)\n\t\t(bidir)\n\t\t(text \"db_down[7..0]\" (rect 0 0 82 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"db_down[7..0]\" (rect 129 27 211 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 232 32)(pt 216 32)(line_width 3))\n\t)\n\t(port\n\t\t(pt 232 48)\n\t\t(bidir)\n\t\t(text \"db_up[7..0]\" (rect 0 0 63 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"db_up[7..0]\" (rect 148 43 211 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 232 48)(pt 216 48)(line_width 3))\n\t)\n\t(drawing\n\t\t(rectangle (rect 16 16 216 80))\n\t)\n)\n"
  },
  {
    "path": "cpu/bus/data_switch_mask.v",
    "content": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and other software and tools, and its AMPP partner logic \n// functions, and any output files from any of the foregoing \n// (including device programming or simulation files), and any \n// associated documentation or information are expressly subject \n// to the terms and conditions of the Altera Program License \n// Subscription Agreement, Altera MegaCore Function License \n// Agreement, or other applicable license agreement, including, \n// without limitation, that your use is for the sole purpose of \n// programming logic devices manufactured by Altera and sold by \n// Altera or its authorized distributors.  Please refer to the \n// applicable agreement for further details.\n\n// PROGRAM\t\t\"Quartus II 64-Bit\"\n// VERSION\t\t\"Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\"\n// CREATED\t\t\"Mon Oct 13 12:32:03 2014\"\n\nmodule data_switch_mask(\n\tsw_up_en,\n\tsw_down_en,\n\tsw_mask543_en,\n\tdb_down,\n\tdb_up\n);\n\n\ninput wire\tsw_up_en;\ninput wire\tsw_down_en;\ninput wire\tsw_mask543_en;\ninout wire\t[7:0] db_down;\ninout wire\t[7:0] db_up;\n\nwire\tSYNTHESIZED_WIRE_4;\nwire\t[1:0] SYNTHESIZED_WIRE_1;\nwire\t[2:0] SYNTHESIZED_WIRE_2;\n\n\n\n\nassign\tSYNTHESIZED_WIRE_4 =  ~sw_mask543_en;\n\nassign\tSYNTHESIZED_WIRE_1 = db_up[7:6] & {SYNTHESIZED_WIRE_4,SYNTHESIZED_WIRE_4};\n\nassign\tdb_down[7] = sw_down_en ? SYNTHESIZED_WIRE_1[1] : 1'bz;\nassign\tdb_down[6] = sw_down_en ? SYNTHESIZED_WIRE_1[0] : 1'bz;\n\nassign\tdb_down[2] = sw_down_en ? SYNTHESIZED_WIRE_2[2] : 1'bz;\nassign\tdb_down[1] = sw_down_en ? SYNTHESIZED_WIRE_2[1] : 1'bz;\nassign\tdb_down[0] = sw_down_en ? SYNTHESIZED_WIRE_2[0] : 1'bz;\n\nassign\tSYNTHESIZED_WIRE_2 = db_up[2:0] & {SYNTHESIZED_WIRE_4,SYNTHESIZED_WIRE_4,SYNTHESIZED_WIRE_4};\n\nassign\tdb_up[7] = sw_up_en ? db_down[7] : 1'bz;\nassign\tdb_up[6] = sw_up_en ? db_down[6] : 1'bz;\nassign\tdb_up[5] = sw_up_en ? db_down[5] : 1'bz;\nassign\tdb_up[4] = sw_up_en ? db_down[4] : 1'bz;\nassign\tdb_up[3] = sw_up_en ? db_down[3] : 1'bz;\nassign\tdb_up[2] = sw_up_en ? db_down[2] : 1'bz;\nassign\tdb_up[1] = sw_up_en ? db_down[1] : 1'bz;\nassign\tdb_up[0] = sw_up_en ? db_down[0] : 1'bz;\n\nassign\tdb_down[5] = sw_down_en ? db_up[5] : 1'bz;\nassign\tdb_down[4] = sw_down_en ? db_up[4] : 1'bz;\nassign\tdb_down[3] = sw_down_en ? db_up[3] : 1'bz;\n\n\nendmodule\n"
  },
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    "path": "cpu/bus/inc_dec.bdf",
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264)\n)\n(connector\n\t(pt 672 248)\n\t(pt 1080 248)\n)\n(connector\n\t(pt 672 216)\n\t(pt 888 216)\n)\n(connector\n\t(pt 672 200)\n\t(pt 824 200)\n)\n(connector\n\t(pt 672 184)\n\t(pt 696 184)\n)\n(connector\n\t(pt 336 232)\n\t(pt 600 232)\n)\n(connector\n\t(pt 336 216)\n\t(pt 552 216)\n)\n(connector\n\t(pt 336 200)\n\t(pt 488 200)\n)\n(connector\n\t(pt 336 184)\n\t(pt 360 184)\n)\n(connector\n\t(pt 192 32)\n\t(pt 1136 32)\n)\n(connector\n\t(text \"address[6]\" (rect 1288 576 1300 627)(font \"Arial\" )(vertical))\n\t(pt 1304 568)\n\t(pt 1304 632)\n)\n(connector\n\t(pt 1136 216)\n\t(pt 1136 248)\n)\n(connector\n\t(text \"address[11]\" (rect 720 571 732 628)(font \"Arial\" )(vertical))\n\t(pt 736 568)\n\t(pt 736 632)\n)\n(connector\n\t(text \"address[14]\" (rect 384 571 396 628)(font \"Arial\" )(vertical))\n\t(pt 400 568)\n\t(pt 400 632)\n)\n(connector\n\t(text \"address[15]\" (rect 232 571 244 628)(font \"Arial\" )(vertical))\n\t(pt 248 568)\n\t(pt 248 632)\n)\n(connector\n\t(pt 1784 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632))\n(junction (pt 1472 632))\n(junction (pt 1640 632))\n(junction (pt 1664 632))\n(junction (pt 1832 632))\n(text \"Fast increment / decrement circuit with carry-skip and carry-lookahead\" (rect 664 664 1351 686)(font \"Arial\" (font_size 14)))\n(title_block\n\t(rect 24 656 345 717)\n\t(name \"title-custom-medium\")\n\t(section (rect 0 41 240 60)(text \"DATE\" (rect 2 0 30 12)(font \"Arial\" ))(text \"May 3, 2014\" (rect 56 3 140 19)(font \"Arial\" (font_size 10)))(border))\n\t(section (rect 0 21 320 40)(text \"DESIGNER\" (rect 2 0 59 12)(font \"Arial\" ))(text \"Goran Devic\" (rect 56 2 151 19)(font \"Arial\" (font_size 11)))(border))\n\t(section (rect 130 0 320 20)(text \"MODULE\" (rect 2 1 48 13)(font \"Arial\" ))(text \"inc_dec\" (rect 43 2 113 21)(font \"Arial\" (font_size 12)(bold)))(border))\n\t(section (rect 0 0 320 20)(text \"PROJECT\" (rect 2 0 52 12)(font \"Arial\" ))(text \"A-Z80\" (rect 56 2 106 21)(font \"Arial\" (font_size 12)(bold)))(border))\n\t(section (rect 241 41 320 60)(text \"REV\" (rect 2 1 25 13)(font \"Arial\" ))(text \"1.0\" (rect 43 3 64 19)(font \"Arial\" (font_size 10)))(border))\n\t(drawing\n\t)\n)\n"
  },
  {
    "path": "cpu/bus/inc_dec.bsf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"symbol\" (version \"1.2\"))\n(symbol\n\t(rect 16 16 216 144)\n\t(text \"inc_dec\" (rect 5 0 49 14)(font \"Arial\" (font_size 8)))\n\t(text \"inst\" (rect 8 112 25 124)(font \"Arial\" ))\n\t(port\n\t\t(pt 0 32)\n\t\t(input)\n\t\t(text \"limit6\" (rect 0 0 27 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"limit6\" (rect 21 27 48 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 32)(pt 16 32))\n\t)\n\t(port\n\t\t(pt 0 48)\n\t\t(input)\n\t\t(text \"decrement\" (rect 0 0 60 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"decrement\" (rect 21 43 81 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 48)(pt 16 48))\n\t)\n\t(port\n\t\t(pt 0 64)\n\t\t(input)\n\t\t(text \"d[15..0]\" (rect 0 0 42 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"d[15..0]\" (rect 21 59 63 73)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 64)(pt 16 64)(line_width 3))\n\t)\n\t(port\n\t\t(pt 0 80)\n\t\t(input)\n\t\t(text \"carry_in\" (rect 0 0 47 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"carry_in\" (rect 21 75 68 89)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 80)(pt 16 80))\n\t)\n\t(port\n\t\t(pt 200 32)\n\t\t(output)\n\t\t(text \"address[15..0]\" (rect 0 0 82 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"address[15..0]\" (rect 97 27 179 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 200 32)(pt 184 32)(line_width 3))\n\t)\n\t(drawing\n\t\t(rectangle (rect 16 16 184 112))\n\t)\n)\n"
  },
  {
    "path": "cpu/bus/inc_dec.v",
    "content": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and other software and tools, and its AMPP partner logic \n// functions, and any output files from any of the foregoing \n// (including device programming or simulation files), and any \n// associated documentation or information are expressly subject \n// to the terms and conditions of the Altera Program License \n// Subscription Agreement, Altera MegaCore Function License \n// Agreement, or other applicable license agreement, including, \n// without limitation, that your use is for the sole purpose of \n// programming logic devices manufactured by Altera and sold by \n// Altera or its authorized distributors.  Please refer to the \n// applicable agreement for further details.\n\n// PROGRAM\t\t\"Quartus II 64-Bit\"\n// VERSION\t\t\"Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\"\n// CREATED\t\t\"Mon Oct 13 12:30:20 2014\"\n\nmodule inc_dec(\n\tcarry_in,\n\tlimit6,\n\tdecrement,\n\td,\n\taddress\n);\n\n\ninput wire\tcarry_in;\ninput wire\tlimit6;\ninput wire\tdecrement;\ninput wire\t[15:0] d;\noutput wire\t[15:0] address;\n\nwire\t[15:0] address_ALTERA_SYNTHESIZED;\nwire\tSYNTHESIZED_WIRE_40;\nwire\tSYNTHESIZED_WIRE_41;\nwire\tSYNTHESIZED_WIRE_42;\nwire\tSYNTHESIZED_WIRE_43;\nwire\tSYNTHESIZED_WIRE_44;\nwire\tSYNTHESIZED_WIRE_5;\nwire\tSYNTHESIZED_WIRE_45;\nwire\tSYNTHESIZED_WIRE_46;\nwire\tSYNTHESIZED_WIRE_47;\nwire\tSYNTHESIZED_WIRE_48;\nwire\tSYNTHESIZED_WIRE_49;\nwire\tSYNTHESIZED_WIRE_50;\nwire\tSYNTHESIZED_WIRE_12;\nwire\tSYNTHESIZED_WIRE_51;\nwire\tSYNTHESIZED_WIRE_52;\nwire\tSYNTHESIZED_WIRE_53;\nwire\tSYNTHESIZED_WIRE_16;\nwire\tSYNTHESIZED_WIRE_22;\nwire\tSYNTHESIZED_WIRE_25;\nwire\tSYNTHESIZED_WIRE_31;\nwire\tSYNTHESIZED_WIRE_34;\nwire\tSYNTHESIZED_WIRE_35;\nwire\tSYNTHESIZED_WIRE_36;\nwire\tSYNTHESIZED_WIRE_37;\nwire\tSYNTHESIZED_WIRE_38;\nwire\tSYNTHESIZED_WIRE_39;\n\n\n\n\nassign\tSYNTHESIZED_WIRE_34 = carry_in & SYNTHESIZED_WIRE_40 & SYNTHESIZED_WIRE_41 & SYNTHESIZED_WIRE_42 & SYNTHESIZED_WIRE_43 & SYNTHESIZED_WIRE_44 & SYNTHESIZED_WIRE_5 & SYNTHESIZED_WIRE_45;\n\nassign\tSYNTHESIZED_WIRE_51 = SYNTHESIZED_WIRE_46 & SYNTHESIZED_WIRE_47 & SYNTHESIZED_WIRE_48 & SYNTHESIZED_WIRE_49 & SYNTHESIZED_WIRE_50 & SYNTHESIZED_WIRE_12;\n\nassign\tSYNTHESIZED_WIRE_38 = SYNTHESIZED_WIRE_51 & SYNTHESIZED_WIRE_52 & SYNTHESIZED_WIRE_53 & SYNTHESIZED_WIRE_16;\n\n\ninc_dec_2bit\tb2v_dual_adder_0(\n\t.carry_borrow_in(carry_in),\n\t.d1_in(d[1]),\n\t.d0_in(d[0]),\n\t.dec1_in(SYNTHESIZED_WIRE_40),\n\t.dec0_in(SYNTHESIZED_WIRE_41),\n\t.carry_borrow_out(SYNTHESIZED_WIRE_22),\n\t.d1_out(address_ALTERA_SYNTHESIZED[1]),\n\t.d0_out(address_ALTERA_SYNTHESIZED[0]));\n\n\ninc_dec_2bit\tb2v_dual_adder_10(\n\t.carry_borrow_in(SYNTHESIZED_WIRE_51),\n\t.d1_in(d[13]),\n\t.d0_in(d[12]),\n\t.dec1_in(SYNTHESIZED_WIRE_53),\n\t.dec0_in(SYNTHESIZED_WIRE_52),\n\t.carry_borrow_out(SYNTHESIZED_WIRE_37),\n\t.d1_out(address_ALTERA_SYNTHESIZED[13]),\n\t.d0_out(address_ALTERA_SYNTHESIZED[12]));\n\n\ninc_dec_2bit\tb2v_dual_adder_2(\n\t.carry_borrow_in(SYNTHESIZED_WIRE_22),\n\t.d1_in(d[3]),\n\t.d0_in(d[2]),\n\t.dec1_in(SYNTHESIZED_WIRE_45),\n\t.dec0_in(SYNTHESIZED_WIRE_42),\n\t.carry_borrow_out(SYNTHESIZED_WIRE_25),\n\t.d1_out(address_ALTERA_SYNTHESIZED[3]),\n\t.d0_out(address_ALTERA_SYNTHESIZED[2]));\n\n\ninc_dec_2bit\tb2v_dual_adder_4(\n\t.carry_borrow_in(SYNTHESIZED_WIRE_25),\n\t.d1_in(d[5]),\n\t.d0_in(d[4]),\n\t.dec1_in(SYNTHESIZED_WIRE_43),\n\t.dec0_in(SYNTHESIZED_WIRE_44),\n\t.carry_borrow_out(SYNTHESIZED_WIRE_39),\n\t.d1_out(address_ALTERA_SYNTHESIZED[5]),\n\t.d0_out(address_ALTERA_SYNTHESIZED[4]));\n\n\ninc_dec_2bit\tb2v_dual_adder_7(\n\t.carry_borrow_in(SYNTHESIZED_WIRE_47),\n\t.d1_in(d[8]),\n\t.d0_in(d[7]),\n\t.dec1_in(SYNTHESIZED_WIRE_46),\n\t.dec0_in(SYNTHESIZED_WIRE_48),\n\t.carry_borrow_out(SYNTHESIZED_WIRE_31),\n\t.d1_out(address_ALTERA_SYNTHESIZED[8]),\n\t.d0_out(address_ALTERA_SYNTHESIZED[7]));\n\n\ninc_dec_2bit\tb2v_dual_adder_9(\n\t.carry_borrow_in(SYNTHESIZED_WIRE_31),\n\t.d1_in(d[10]),\n\t.d0_in(d[9]),\n\t.dec1_in(SYNTHESIZED_WIRE_50),\n\t.dec0_in(SYNTHESIZED_WIRE_49),\n\t.carry_borrow_out(SYNTHESIZED_WIRE_36),\n\t.d1_out(address_ALTERA_SYNTHESIZED[10]),\n\t.d0_out(address_ALTERA_SYNTHESIZED[9]));\n\nassign\tSYNTHESIZED_WIRE_47 = SYNTHESIZED_WIRE_34 & SYNTHESIZED_WIRE_35;\n\nassign\tSYNTHESIZED_WIRE_35 =  ~limit6;\n\nassign\tSYNTHESIZED_WIRE_41 = d[0] ^ decrement;\n\nassign\tSYNTHESIZED_WIRE_40 = d[1] ^ decrement;\n\nassign\tSYNTHESIZED_WIRE_50 = d[10] ^ decrement;\n\nassign\tSYNTHESIZED_WIRE_12 = d[11] ^ decrement;\n\nassign\taddress_ALTERA_SYNTHESIZED[11] = SYNTHESIZED_WIRE_36 ^ d[11];\n\nassign\tSYNTHESIZED_WIRE_52 = d[12] ^ decrement;\n\nassign\tSYNTHESIZED_WIRE_53 = d[13] ^ decrement;\n\nassign\tSYNTHESIZED_WIRE_16 = d[14] ^ decrement;\n\nassign\taddress_ALTERA_SYNTHESIZED[14] = SYNTHESIZED_WIRE_37 ^ d[14];\n\nassign\taddress_ALTERA_SYNTHESIZED[15] = SYNTHESIZED_WIRE_38 ^ d[15];\n\nassign\tSYNTHESIZED_WIRE_42 = d[2] ^ decrement;\n\nassign\tSYNTHESIZED_WIRE_45 = d[3] ^ decrement;\n\nassign\tSYNTHESIZED_WIRE_44 = d[4] ^ decrement;\n\nassign\tSYNTHESIZED_WIRE_43 = d[5] ^ decrement;\n\nassign\tSYNTHESIZED_WIRE_5 = d[6] ^ decrement;\n\nassign\taddress_ALTERA_SYNTHESIZED[6] = SYNTHESIZED_WIRE_39 ^ d[6];\n\nassign\tSYNTHESIZED_WIRE_48 = d[7] ^ decrement;\n\nassign\tSYNTHESIZED_WIRE_46 = d[8] ^ decrement;\n\nassign\tSYNTHESIZED_WIRE_49 = d[9] ^ decrement;\n\nassign\taddress = address_ALTERA_SYNTHESIZED;\n\nendmodule\n"
  },
  {
    "path": "cpu/bus/inc_dec_2bit.bdf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"graphic\" (version \"1.4\"))\n(pin\n\t(input)\n\t(rect 24 80 200 96)\n\t(text \"INPUT\" (rect 133 0 161 10)(font \"Arial\" (font_size 6)))\n\t(text \"carry_borrow_in\" (rect 9 0 86 12)(font \"Arial\" ))\n\t(pt 176 8)\n\t(drawing\n\t\t(line (pt 92 12)(pt 117 12))\n\t\t(line (pt 92 4)(pt 117 4))\n\t\t(line (pt 121 8)(pt 176 8))\n\t\t(line (pt 92 12)(pt 92 4))\n\t\t(line (pt 117 4)(pt 121 8))\n\t\t(line (pt 117 12)(pt 121 8))\n\t)\n\t(text \"VCC\" (rect 136 7 156 17)(font \"Arial\" (font_size 6)))\n)\n(pin\n\t(input)\n\t(rect 24 32 200 48)\n\t(text \"INPUT\" (rect 133 0 161 10)(font \"Arial\" (font_size 6)))\n\t(text \"d1_in\" (rect 9 0 34 12)(font \"Arial\" ))\n\t(pt 176 8)\n\t(drawing\n\t\t(line (pt 92 12)(pt 117 12))\n\t\t(line (pt 92 4)(pt 117 4))\n\t\t(line (pt 121 8)(pt 176 8))\n\t\t(line (pt 92 12)(pt 92 4))\n\t\t(line (pt 117 4)(pt 121 8))\n\t\t(line (pt 117 12)(pt 121 8))\n\t)\n\t(text \"VCC\" (rect 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9)(bold)))(border))\n\t(section (rect 192 35 256 51)(text \"REV\" (rect 2 1 25 13)(font \"Arial\" ))(text \"1.0\" (rect 43 3 60 17)(font \"Arial\" (font_size 8)))(border))\n\t(drawing\n\t)\n)\n"
  },
  {
    "path": "cpu/bus/inc_dec_2bit.bsf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2011 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"symbol\" (version \"1.2\"))\n(symbol\n\t(rect 64 64 312 224)\n\t(text \"inc_dec_2bit\" (rect 16 0 87 14)(font \"Arial\" (font_size 8)))\n\t(text \"inst\" (rect 112 72 129 84)(font \"Arial\" ))\n\t(port\n\t\t(pt 0 24)\n\t\t(input)\n\t\t(text \"carry_borrow_in\" (rect 0 0 96 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"carry_borrow_in\" (rect 21 19 117 33)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 24)(pt 16 24))\n\t)\n\t(port\n\t\t(pt 0 104)\n\t\t(input)\n\t\t(text \"d1_in\" (rect 0 0 30 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"d1_in\" (rect 21 99 51 113)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 104)(pt 16 104))\n\t)\n\t(port\n\t\t(pt 0 40)\n\t\t(input)\n\t\t(text \"d0_in\" (rect 0 0 30 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"d0_in\" (rect 21 35 51 49)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 40)(pt 16 40))\n\t)\n\t(port\n\t\t(pt 0 136)\n\t\t(input)\n\t\t(text \"dec1_in\" (rect 0 0 44 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"dec1_in\" (rect 21 131 65 145)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 136)(pt 16 136))\n\t)\n\t(port\n\t\t(pt 0 72)\n\t\t(input)\n\t\t(text \"dec0_in\" (rect 0 0 44 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"dec0_in\" (rect 21 67 65 81)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 72)(pt 16 72))\n\t)\n\t(port\n\t\t(pt 248 128)\n\t\t(output)\n\t\t(text \"carry_borrow_out\" (rect -8 0 97 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"carry_borrow_out\" (rect 122 123 227 137)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 248 128)(pt 232 128))\n\t)\n\t(port\n\t\t(pt 248 80)\n\t\t(output)\n\t\t(text \"d1_out\" (rect -8 0 30 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"d1_out\" (rect 189 75 227 89)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 248 80)(pt 232 80))\n\t)\n\t(port\n\t\t(pt 248 56)\n\t\t(output)\n\t\t(text \"d0_out\" (rect -8 0 30 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"d0_out\" (rect 189 51 227 65)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 248 56)(pt 232 56))\n\t)\n\t(drawing\n\t\t(rectangle (rect 16 16 240 152))\n\t)\n\t(fill (color 253 211 206))\n)\n"
  },
  {
    "path": "cpu/bus/inc_dec_2bit.v",
    "content": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and other software and tools, and its AMPP partner logic \n// functions, and any output files from any of the foregoing \n// (including device programming or simulation files), and any \n// associated documentation or information are expressly subject \n// to the terms and conditions of the Altera Program License \n// Subscription Agreement, Altera MegaCore Function License \n// Agreement, or other applicable license agreement, including, \n// without limitation, that your use is for the sole purpose of \n// programming logic devices manufactured by Altera and sold by \n// Altera or its authorized distributors.  Please refer to the \n// applicable agreement for further details.\n\n// PROGRAM\t\t\"Quartus II 64-Bit\"\n// VERSION\t\t\"Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\"\n// CREATED\t\t\"Mon Oct 13 12:26:57 2014\"\n\nmodule inc_dec_2bit(\n\tcarry_borrow_in,\n\td1_in,\n\td0_in,\n\tdec1_in,\n\tdec0_in,\n\tcarry_borrow_out,\n\td1_out,\n\td0_out\n);\n\n\ninput wire\tcarry_borrow_in;\ninput wire\td1_in;\ninput wire\td0_in;\ninput wire\tdec1_in;\ninput wire\tdec0_in;\noutput wire\tcarry_borrow_out;\noutput wire\td1_out;\noutput wire\td0_out;\n\nwire\tSYNTHESIZED_WIRE_0;\n\n\n\n\nassign\tSYNTHESIZED_WIRE_0 = dec0_in & carry_borrow_in;\n\nassign\tcarry_borrow_out = dec0_in & dec1_in & carry_borrow_in;\n\nassign\td1_out = d1_in ^ SYNTHESIZED_WIRE_0;\n\nassign\td0_out = carry_borrow_in ^ d0_in;\n\n\nendmodule\n"
  },
  {
    "path": "cpu/bus/simulation/modelsim/r",
    "content": "restart -f ; run -all\n"
  },
  {
    "path": "cpu/bus/simulation/modelsim/test_bus.mpf",
    "content": "; Copyright 1991-2009 Mentor Graphics Corporation\n;\n; All Rights Reserved.\n;\n; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF\n; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.\n;\n\n[Library]\nstd = $MODEL_TECH/../std\nieee = $MODEL_TECH/../ieee\nverilog = $MODEL_TECH/../verilog\nvital2000 = $MODEL_TECH/../vital2000\nstd_developerskit = $MODEL_TECH/../std_developerskit\nsynopsys = $MODEL_TECH/../synopsys\nmodelsim_lib = $MODEL_TECH/../modelsim_lib\nsv_std = $MODEL_TECH/../sv_std\n\n; Altera Primitive libraries\n;\n; VHDL Section\n;\naltera_mf = $MODEL_TECH/../altera/vhdl/altera_mf\naltera = $MODEL_TECH/../altera/vhdl/altera\naltera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim\nlpm = $MODEL_TECH/../altera/vhdl/220model\n220model = $MODEL_TECH/../altera/vhdl/220model\nmax = $MODEL_TECH/../altera/vhdl/max\nmaxii = $MODEL_TECH/../altera/vhdl/maxii\nmaxv = $MODEL_TECH/../altera/vhdl/maxv\nstratix = $MODEL_TECH/../altera/vhdl/stratix\nstratixii = $MODEL_TECH/../altera/vhdl/stratixii\nstratixiigx = $MODEL_TECH/../altera/vhdl/stratixiigx\nhardcopyii = $MODEL_TECH/../altera/vhdl/hardcopyii\nhardcopyiii = $MODEL_TECH/../altera/vhdl/hardcopyiii\nhardcopyiv = $MODEL_TECH/../altera/vhdl/hardcopyiv\ncyclone = $MODEL_TECH/../altera/vhdl/cyclone\ncycloneii = $MODEL_TECH/../altera/vhdl/cycloneii\ncycloneiii = $MODEL_TECH/../altera/vhdl/cycloneiii\ncycloneiiils = $MODEL_TECH/../altera/vhdl/cycloneiiils\nsgate = $MODEL_TECH/../altera/vhdl/sgate\nstratixgx = $MODEL_TECH/../altera/vhdl/stratixgx\naltgxb = $MODEL_TECH/../altera/vhdl/altgxb\nstratixgx_gxb = $MODEL_TECH/../altera/vhdl/stratixgx_gxb\nstratixiigx_hssi = $MODEL_TECH/../altera/vhdl/stratixiigx_hssi\narriagx_hssi = $MODEL_TECH/../altera/vhdl/arriagx_hssi\narriaii = $MODEL_TECH/../altera/vhdl/arriaii\narriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi\narriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip\narriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz\narriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi\narriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip\narriagx = $MODEL_TECH/../altera/vhdl/arriagx\naltgxb_lib = $MODEL_TECH/../altera/vhdl/altgxb\nstratixiv = $MODEL_TECH/../altera/vhdl/stratixiv\nstratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi\nstratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip\ncycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv\ncycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi\ncycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip\ncycloneive = $MODEL_TECH/../altera/vhdl/cycloneive\nhardcopyiv_hssi = $MODEL_TECH/../altera/vhdl/hardcopyiv_hssi\nhardcopyiv_pcie_hip = $MODEL_TECH/../altera/vhdl/hardcopyiv_pcie_hip\nstratixv = $MODEL_TECH/../altera/vhdl/stratixv\nstratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi\nstratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip\narriavgz = $MODEL_TECH/../altera/vhdl/arriavgz\narriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi\narriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip\narriav = $MODEL_TECH/../altera/vhdl/arriav\ncyclonev = $MODEL_TECH/../altera/vhdl/cyclonev\n;\n; Verilog Section\n;\naltera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf\naltera_ver = $MODEL_TECH/../altera/verilog/altera\naltera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim\nlpm_ver = $MODEL_TECH/../altera/verilog/220model\n220model_ver = $MODEL_TECH/../altera/verilog/220model\nmax_ver = $MODEL_TECH/../altera/verilog/max\nmaxii_ver = $MODEL_TECH/../altera/verilog/maxii\nmaxv_ver = $MODEL_TECH/../altera/verilog/maxv\nstratix_ver = $MODEL_TECH/../altera/verilog/stratix\nstratixii_ver = $MODEL_TECH/../altera/verilog/stratixii\nstratixiigx_ver = $MODEL_TECH/../altera/verilog/stratixiigx\narriagx_ver = $MODEL_TECH/../altera/verilog/arriagx\nhardcopyii_ver = $MODEL_TECH/../altera/verilog/hardcopyii\nhardcopyiii_ver = $MODEL_TECH/../altera/verilog/hardcopyiii\nhardcopyiv_ver = $MODEL_TECH/../altera/verilog/hardcopyiv\ncyclone_ver = $MODEL_TECH/../altera/verilog/cyclone\ncycloneii_ver = $MODEL_TECH/../altera/verilog/cycloneii\ncycloneiii_ver = $MODEL_TECH/../altera/verilog/cycloneiii\ncycloneiiils_ver = $MODEL_TECH/../altera/verilog/cycloneiiils\nsgate_ver = $MODEL_TECH/../altera/verilog/sgate\nstratixgx_ver = $MODEL_TECH/../altera/verilog/stratixgx\naltgxb_ver = $MODEL_TECH/../altera/verilog/altgxb\nstratixgx_gxb_ver = $MODEL_TECH/../altera/verilog/stratixgx_gxb\nstratixiigx_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiigx_hssi\narriagx_hssi_ver = $MODEL_TECH/../altera/verilog/arriagx_hssi\narriaii_ver = $MODEL_TECH/../altera/verilog/arriaii\narriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi\narriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip\narriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz\narriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi\narriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip\nstratixiii_ver = $MODEL_TECH/../altera/verilog/stratixiii\nstratixiii = $MODEL_TECH/../altera/vhdl/stratixiii\nstratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv\nstratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi\nstratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip\nstratixv_ver = $MODEL_TECH/../altera/verilog/stratixv\nstratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi\nstratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip\narriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz\narriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi\narriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip\narriav_ver = $MODEL_TECH/../altera/verilog/arriav\narriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi\narriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip\ncyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev\ncyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi\ncyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip\ncycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv\ncycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi\ncycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip\ncycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive\nhardcopyiv_hssi_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_hssi\nhardcopyiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_pcie_hip\n\nwork = work\n[vcom]\n; VHDL93 variable selects language version as the default.\n; Default is VHDL-2002.\n; Value of 0 or 1987 for VHDL-1987.\n; Value of 1 or 1993 for VHDL-1993.\n; Default or value of 2 or 2002 for VHDL-2002.\n; Default or value of 3 or 2008 for VHDL-2008.\nVHDL93 = 2002\n\n; Show source line containing error. Default is off.\n; Show_source = 1\n\n; Turn off unbound-component warnings. Default is on.\n; Show_Warning1 = 0\n\n; Turn off process-without-a-wait-statement warnings. Default is on.\n; Show_Warning2 = 0\n\n; Turn off null-range warnings. Default is on.\n; Show_Warning3 = 0\n\n; Turn off no-space-in-time-literal warnings. Default is on.\n; Show_Warning4 = 0\n\n; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.\n; Show_Warning5 = 0\n\n; Turn off optimization for IEEE std_logic_1164 package. Default is on.\n; Optimize_1164 = 0\n\n; Turn on resolving of ambiguous function overloading in favor of the\n; \"explicit\" function declaration (not the one automatically created by\n; the compiler for each type declaration). Default is off.\n; The .ini file has Explicit enabled so that std_logic_signed/unsigned\n; will match the behavior of synthesis tools.\nExplicit = 1\n\n; Turn off acceleration of the VITAL packages. Default is to accelerate.\n; NoVital = 1\n\n; Turn off VITAL compliance checking. Default is checking on.\n; NoVitalCheck = 1\n\n; Ignore VITAL compliance checking errors. Default is to not ignore.\n; IgnoreVitalErrors = 1\n\n; Turn off VITAL compliance checking warnings. Default is to show warnings.\n; Show_VitalChecksWarnings = 0\n\n; Keep silent about case statement static warnings.\n; Default is to give a warning.\n; NoCaseStaticError = 1\n\n; Keep silent about warnings caused by aggregates that are not locally static.\n; Default is to give a warning.\n; NoOthersStaticError = 1\n\n; Turn off inclusion of debugging info within design units.\n; Default is to include debugging info.\n; NoDebug = 1\n\n; Turn off \"Loading...\" messages. Default is messages on.\n; Quiet = 1\n\n; Turn on some limited synthesis rule compliance checking. Checks only:\n;    -- signals used (read) by a process must be in the sensitivity list\n; CheckSynthesis = 1\n\n; Activate optimizations on expressions that do not involve signals,\n; waits, or function/procedure/task invocations. Default is off.\n; ScalarOpts = 1\n\n; Require the user to specify a configuration for all bindings,\n; and do not generate a compile time default binding for the\n; component. This will result in an elaboration error of\n; 'component not bound' if the user fails to do so. Avoids the rare\n; issue of a false dependency upon the unused default binding.\n; RequireConfigForAllDefaultBinding = 1\n\n; Inhibit range checking on subscripts of arrays. Range checking on\n; scalars defined with subtypes is inhibited by default.\n; NoIndexCheck = 1\n\n; Inhibit range checks on all (implicit and explicit) assignments to\n; scalar objects defined with subtypes.\n; NoRangeCheck = 1\n\n[vlog]\n\n; Turn off inclusion of debugging info within design units.\n; Default is to include debugging info.\n; NoDebug = 1\n\n; Turn off \"loading...\" messages. Default is messages on.\n; Quiet = 1\n\n; Turn on Verilog hazard checking (order-dependent accessing of global vars).\n; Default is off.\n; Hazard = 1\n\n; Turn on converting regular Verilog identifiers to uppercase. Allows case\n; insensitivity for module names. Default is no conversion.\n; UpCase = 1\n\n; Turn on incremental compilation of modules. Default is off.\n; Incremental = 1\n\n; Turns on lint-style checking.\n; Show_Lint = 1\n\n[vsim]\n; Simulator resolution\n; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.\nResolution = ps\n\n; User time unit for run commands\n; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the\n; unit specified for Resolution. For example, if Resolution is 100ps,\n; then UserTimeUnit defaults to ps.\n; Should generally be set to default.\nUserTimeUnit = default\n\n; Default run length\nRunLength = 1 us\n\n; Maximum iterations that can be run without advancing simulation time\nIterationLimit = 5000\n\n; Directive to license manager:\n; vhdl          Immediately reserve a VHDL license\n; vlog          Immediately reserve a Verilog license\n; plus          Immediately reserve a VHDL and Verilog license\n; nomgc         Do not look for Mentor Graphics Licenses\n; nomti         Do not look for Model Technology Licenses\n; noqueue       Do not wait in the license queue when a license isn't available\n; viewsim\tTry for viewer license but accept simulator license(s) instead\n;\t\tof queuing for viewer license\n; License = plus\n\n; Stop the simulator after a VHDL/Verilog assertion message\n; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal\nBreakOnAssertion = 3\n\n; Assertion Message Format\n; %S - Severity Level\n; %R - Report Message\n; %T - Time of assertion\n; %D - Delta\n; %I - Instance or Region pathname (if available)\n; %% - print '%' character\n; AssertionFormat = \"** %S: %R\\n   Time: %T  Iteration: %D%I\\n\"\n\n; Assertion File - alternate file for storing VHDL/Verilog assertion messages\n; AssertFile = assert.log\n\n; Default radix for all windows and commands...\n; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned\nDefaultRadix = hexadecimal\n\n; VSIM Startup command\n; Startup = do startup.do\n\n; File for saving command transcript\nTranscriptFile = transcript\n\n; File for saving command history\n; CommandHistory = cmdhist.log\n\n; Specify whether paths in simulator commands should be described\n; in VHDL or Verilog format.\n; For VHDL, PathSeparator = /\n; For Verilog, PathSeparator = .\n; Must not be the same character as DatasetSeparator.\nPathSeparator = /\n\n; Specify the dataset separator for fully rooted contexts.\n; The default is ':'. For example, sim:/top\n; Must not be the same character as PathSeparator.\nDatasetSeparator = :\n\n; Disable VHDL assertion messages\n; IgnoreNote = 1\n; IgnoreWarning = 1\n; IgnoreError = 1\n; IgnoreFailure = 1\n\n; Default force kind. May be freeze, drive, deposit, or default\n; or in other terms, fixed, wired, or charged.\n; A value of \"default\" will use the signal kind to determine the\n; force kind, drive for resolved signals, freeze for unresolved signals\n; DefaultForceKind = freeze\n\n; If zero, open files when elaborated; otherwise, open files on\n; first read or write.  Default is 0.\n; DelayFileOpen = 1\n\n; Control VHDL files opened for write.\n;   0 = Buffered, 1 = Unbuffered\nUnbufferedOutput = 0\n\n; Control the number of VHDL files open concurrently.\n; This number should always be less than the current ulimit\n; setting for max file descriptors.\n;   0 = unlimited\nConcurrentFileLimit = 40\n\n; Control the number of hierarchical regions displayed as\n; part of a signal name shown in the Wave window.\n; A value of zero tells VSIM to display the full name.\n; The default is 0.\n; WaveSignalNameWidth = 0\n\n; Turn off warnings from the std_logic_arith, std_logic_unsigned\n; and std_logic_signed packages.\n; StdArithNoWarnings = 1\n\n; Turn off warnings from the IEEE numeric_std and numeric_bit packages.\n; NumericStdNoWarnings = 1\n\n; Control the format of the (VHDL) FOR generate statement label\n; for each iteration.  Do not quote it.\n; The format string here must contain the conversion codes %s and %d,\n; in that order, and no other conversion codes.  The %s represents\n; the generate_label; the %d represents the generate parameter value\n; at a particular generate iteration (this is the position number if\n; the generate parameter is of an enumeration type).  Embedded whitespace\n; is allowed (but discouraged); leading and trailing whitespace is ignored.\n; Application of the format must result in a unique scope name over all\n; such names in the design so that name lookup can function properly.\n; GenerateFormat = %s__%d\n\n; Specify whether checkpoint files should be compressed.\n; The default is 1 (compressed).\n; CheckpointCompressMode = 0\n\n; List of dynamically loaded objects for Verilog PLI applications\n; Veriuser = veriuser.sl\n\n; Specify default options for the restart command. Options can be one\n; or more of: -force -nobreakpoint -nolist -nolog -nowave\n; DefaultRestartOptions = -force\n\n; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs\n; (> 500 megabyte memory footprint). Default is disabled.\n; Specify number of megabytes to lock.\n; LockedMemory = 1000\n\n; Turn on (1) or off (0) WLF file compression.\n; The default is 1 (compress WLF file).\n; WLFCompress = 0\n\n; Specify whether to save all design hierarchy (1) in the WLF file\n; or only regions containing logged signals (0).\n; The default is 0 (save only regions with logged signals).\n; WLFSaveAllRegions = 1\n\n; WLF file time limit.  Limit WLF file by time, as closely as possible,\n; to the specified amount of simulation time.  When the limit is exceeded\n; the earliest times get truncated from the file.\n; If both time and size limits are specified the most restrictive is used.\n; UserTimeUnits are used if time units are not specified.\n; The default is 0 (no limit).  Example: WLFTimeLimit = {100 ms}\n; WLFTimeLimit = 0\n\n; WLF file size limit.  Limit WLF file size, as closely as possible,\n; to the specified number of megabytes.  If both time and size limits\n; are specified then the most restrictive is used.\n; The default is 0 (no limit).\n; WLFSizeLimit = 1000\n\n; Specify whether or not a WLF file should be deleted when the\n; simulation ends.  A value of 1 will cause the WLF file to be deleted.\n; The default is 0 (do not delete WLF file when simulation ends).\n; WLFDeleteOnQuit = 1\n\n; Automatic SDF compilation\n; Disables automatic compilation of SDF files in flows that support it.\n; Default is on, uncomment to turn off.\n; NoAutoSDFCompile = 1\n\n[lmc]\n\n[msg_system]\n; Change a message severity or suppress a message.\n; The format is: <msg directive> = <msg number>[,<msg number>...]\n; Examples:\n;   note = 3009\n;   warning = 3033\n;   error = 3010,3016\n;   fatal = 3016,3033\n;   suppress = 3009,3016,3043\n; The command verror <msg number> can be used to get the complete\n; description of a message.\n\n; Control transcripting of elaboration/runtime messages.\n; The default is to have messages appear in the transcript and\n; recorded in the wlf file (messages that are recorded in the\n; wlf file can be viewed in the MsgViewer).  The other settings\n; are to send messages only to the transcript or only to the\n; wlf file.  The valid values are\n;    both  {default}\n;    tran  {transcript only}\n;    wlf   {wlf file only}\n; msgmode = both\n[Project]\n; Warning -- Do not edit the project properties directly.\n;            Property names are dynamic in nature and property\n;            values have special syntax.  Changing property data directly\n;            can result in a corrupt MPF file.  All project properties\n;            can be modified through project window dialogs.\nProject_Version = 6\nProject_DefaultLib = work\nProject_SortMethod = unused\nProject_Files_Count = 8\nProject_File_0 = $ROOT/cpu/bus/address_latch.v\nProject_File_P_0 = compile_order 0 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_1 = $ROOT/cpu/bus/address_mux.v\nProject_File_P_1 = compile_order 7 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_2 = $ROOT/cpu/bus/address_pins.v\nProject_File_P_2 = compile_order 5 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_3 = $ROOT/cpu/bus/data_pins.v\nProject_File_P_3 = compile_order 6 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_4 = $ROOT/cpu/bus/inc_dec.v\nProject_File_P_4 = compile_order 1 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_5 = $ROOT/cpu/bus/inc_dec_2bit.v\nProject_File_P_5 = compile_order 3 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_6 = $ROOT/cpu/bus/test_bus.sv\nProject_File_P_6 = compile_order 2 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_7 = $ROOT/cpu/bus/test_pins.sv\nProject_File_P_7 = compile_order 4 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_Sim_Count = 2\nProject_Sim_0 = Test pins\nProject_Sim_P_0 = timing default -t default -sdfnoerror 0 -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder {Top Level} +pulse_e {} additional_dus work.test_pins -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {}\nProject_Sim_1 = Test bus\nProject_Sim_P_1 = timing default -t default -sdfnoerror 0 -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder {Top Level} +pulse_e {} additional_dus work.test_bus -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {}\nProject_Folder_Count = 0\nEcho_Compile_Output = 0\nSave_Compile_Report = 1\nProject_Opt_Count = 0\nForceSoftPaths = 1\nProjectStatusDelay = 5000\nVERILOG_DoubleClick = Edit\nVERILOG_CustomDoubleClick =\nSYSTEMVERILOG_DoubleClick = Edit\nSYSTEMVERILOG_CustomDoubleClick =\nVHDL_DoubleClick = Edit\nVHDL_CustomDoubleClick =\nPSL_DoubleClick = Edit\nPSL_CustomDoubleClick =\nTEXT_DoubleClick = Edit\nTEXT_CustomDoubleClick =\nSYSTEMC_DoubleClick = Edit\nSYSTEMC_CustomDoubleClick =\nTCL_DoubleClick = Edit\nTCL_CustomDoubleClick =\nMACRO_DoubleClick = Edit\nMACRO_CustomDoubleClick =\nVCD_DoubleClick = Edit\nVCD_CustomDoubleClick =\nSDF_DoubleClick = Edit\nSDF_CustomDoubleClick =\nXML_DoubleClick = Edit\nXML_CustomDoubleClick =\nLOGFILE_DoubleClick = Edit\nLOGFILE_CustomDoubleClick =\nUCDB_DoubleClick = Edit\nUCDB_CustomDoubleClick =\nUPF_DoubleClick = Edit\nUPF_CustomDoubleClick =\nPCF_DoubleClick = Edit\nPCF_CustomDoubleClick =\nPROJECT_DoubleClick = Edit\nPROJECT_CustomDoubleClick =\nVRM_DoubleClick = Edit\nVRM_CustomDoubleClick =\nDEBUGDATABASE_DoubleClick = Edit\nDEBUGDATABASE_CustomDoubleClick =\nDEBUGARCHIVE_DoubleClick = Edit\nDEBUGARCHIVE_CustomDoubleClick =\nProject_Major_Version = 10\nProject_Minor_Version = 1\n"
  },
  {
    "path": "cpu/bus/simulation/modelsim/wave_bus.do",
    "content": "onerror {resume}\nquietly WaveActivateNextPane {} 0\nadd wave -noupdate /test_bus/nreset\nadd wave -noupdate /test_bus/clk\nadd wave -noupdate /test_bus/abusw\nadd wave -noupdate /test_bus/abus\nadd wave -noupdate -color Gold /test_bus/address\nadd wave -noupdate /test_bus/ctl_al_we\nadd wave -noupdate /test_bus/ctl_bus_inc_oe\nadd wave -noupdate /test_bus/ctl_inc_dec\nadd wave -noupdate /test_bus/ctl_inc_limit6\nadd wave -noupdate /test_bus/ctl_inc_cy\nadd wave -noupdate /test_bus/clrpc\nadd wave -noupdate /test_bus/address_is_1\nadd wave -noupdate /test_bus/address_latch_/ctl_apin_mux\nadd wave -noupdate /test_bus/address_latch_/ctl_apin_mux2\nTreeUpdate [SetDefaultTree]\nWaveRestoreCursors {{Cursor 1} {5500 ns} 0}\nquietly wave cursor active 1\nconfigure wave -namecolwidth 141\nconfigure wave -valuecolwidth 62\nconfigure wave -justifyvalue left\nconfigure wave -signalnamewidth 1\nconfigure wave -snapdistance 10\nconfigure wave -datasetprefix 0\nconfigure wave -rowmargin 4\nconfigure wave -childrowmargin 2\nconfigure wave -gridoffset 0\nconfigure wave -gridperiod 1\nconfigure wave -griddelta 40\nconfigure wave -timeline 1\nconfigure wave -timelineunits ps\nupdate\nWaveRestoreZoom {0 ns} {39500 ns}\n"
  },
  {
    "path": "cpu/bus/simulation/modelsim/wave_pins.do",
    "content": "onerror {resume}\nquietly WaveActivateNextPane {} 0\nadd wave -noupdate /test_pins/clk\nadd wave -noupdate -divider apins\nadd wave -noupdate -color Gold -radix hexadecimal /test_pins/apin\nadd wave -noupdate -radix hexadecimal /test_pins/ab\nadd wave -noupdate /test_pins/ctl_ab_we\nadd wave -noupdate -divider dpins\nadd wave -noupdate -radix hexadecimal /test_pins/dpin\nadd wave -noupdate -color Gold -radix hexadecimal /test_pins/db\nadd wave -noupdate /test_pins/ctl_db_we\nadd wave -noupdate /test_pins/ctl_db_pin_re\nadd wave -noupdate /test_pins/ctl_db_pin_oe\nadd wave -noupdate /test_pins/ctl_db_oe\nadd wave -noupdate -radix hexadecimal /test_pins/db_w\nadd wave -noupdate -radix hexadecimal /test_pins/dpin_w\nTreeUpdate [SetDefaultTree]\nWaveRestoreCursors {{Cursor 1} {19000 ns} 0}\nquietly wave cursor active 1\nconfigure wave -namecolwidth 138\nconfigure wave -valuecolwidth 54\nconfigure wave -justifyvalue right\nconfigure wave -signalnamewidth 1\nconfigure wave -snapdistance 10\nconfigure wave -datasetprefix 0\nconfigure wave -rowmargin 4\nconfigure wave -childrowmargin 2\nconfigure wave -gridoffset 0\nconfigure wave -gridperiod 1\nconfigure wave -griddelta 40\nconfigure wave -timeline 1\nconfigure wave -timelineunits us\nupdate\nWaveRestoreZoom {0 ns} {57700 ns}\n"
  },
  {
    "path": "cpu/bus/test_bus.qpf",
    "content": "# -------------------------------------------------------------------------- #\n#\n# Copyright (C) 1991-2013 Altera Corporation\n# Your use of Altera Corporation's design tools, logic functions \n# and other software and tools, and its AMPP partner logic \n# functions, and any output files from any of the foregoing \n# (including device programming or simulation files), and any \n# associated documentation or information are expressly subject \n# to the terms and conditions of the Altera Program License \n# Subscription Agreement, Altera MegaCore Function License \n# Agreement, or other applicable license agreement, including, \n# without limitation, that your use is for the sole purpose of \n# programming logic devices manufactured by Altera and sold by \n# Altera or its authorized distributors.  Please refer to the \n# applicable agreement for further details.\n#\n# -------------------------------------------------------------------------- #\n#\n# Quartus II 64-Bit\n# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\n# Date created = 09:15:26  October 13, 2014\n#\n# -------------------------------------------------------------------------- #\n\nQUARTUS_VERSION = \"13.0\"\nDATE = \"09:15:26  October 13, 2014\"\n\n# Revisions\n\nPROJECT_REVISION = \"test_bus\"\n"
  },
  {
    "path": "cpu/bus/test_bus.qsf",
    "content": "# -------------------------------------------------------------------------- #\n#\n# Copyright (C) 1991-2013 Altera Corporation\n# Your use of Altera Corporation's design tools, logic functions\n# and other software and tools, and its AMPP partner logic\n# functions, and any output files from any of the foregoing\n# (including device programming or simulation files), and any\n# associated documentation or information are expressly subject\n# to the terms and conditions of the Altera Program License\n# Subscription Agreement, Altera MegaCore Function License\n# Agreement, or other applicable license agreement, including,\n# without limitation, that your use is for the sole purpose of\n# programming logic devices manufactured by Altera and sold by\n# Altera or its authorized distributors.  Please refer to the\n# applicable agreement for further details.\n#\n# -------------------------------------------------------------------------- #\n#\n# Quartus II 64-Bit\n# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\n# Date created = 09:15:26  October 13, 2014\n#\n# -------------------------------------------------------------------------- #\n#\n# Notes:\n#\n# 1) The default values for assignments are stored in the file:\n#\t\ttest_bus_assignment_defaults.qdf\n#    If this file doesn't exist, see file:\n#\t\tassignment_defaults.qdf\n#\n# 2) Altera recommends that you do not modify this file. This\n#    file is updated automatically by the Quartus II software\n#    and any changes you make may be lost or overwritten.\n#\n# -------------------------------------------------------------------------- #\n\n\nset_global_assignment -name FAMILY \"Cyclone II\"\nset_global_assignment -name DEVICE EP2C20F484C7\nset_global_assignment -name TOP_LEVEL_ENTITY control_pins_n\nset_global_assignment -name ORIGINAL_QUARTUS_VERSION \"13.0 SP1\"\nset_global_assignment -name PROJECT_CREATION_TIME_DATE \"09:15:26  OCTOBER 13, 2014\"\nset_global_assignment -name LAST_QUARTUS_VERSION \"13.0 SP1\"\nset_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files\nset_global_assignment -name MIN_CORE_JUNCTION_TEMP 0\nset_global_assignment -name MAX_CORE_JUNCTION_TEMP 85\nset_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1\nset_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top\nset_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top\nset_global_assignment -name PARTITION_COLOR 16764057 -section_id Top\nset_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON\nset_global_assignment -name SMART_RECOMPILE ON\nset_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON\nset_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS OFF\nset_global_assignment -name POWER_PRESET_COOLING_SOLUTION \"23 MM HEAT SINK WITH 200 LFPM AIRFLOW\"\nset_global_assignment -name POWER_BOARD_THERMAL_MODEL \"NONE (CONSERVATIVE)\"\nset_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005\nset_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF\nset_global_assignment -name USE_CONFIGURATION_DEVICE ON\nset_global_assignment -name RESERVE_ALL_UNUSED_PINS \"AS INPUT TRI-STATED WITH WEAK PULL-UP\"\nset_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON\nset_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON\nset_global_assignment -name BSF_FILE address_mux.bsf\nset_global_assignment -name BSF_FILE inc_dec_2bit.bsf\nset_global_assignment -name BDF_FILE inc_dec_2bit.bdf\nset_global_assignment -name BDF_FILE inc_dec.bdf\nset_global_assignment -name BDF_FILE data_switch_mask.bdf\nset_global_assignment -name BDF_FILE data_switch.bdf\nset_global_assignment -name BDF_FILE data_pins.bdf\nset_global_assignment -name BDF_FILE control_pins_n.bdf\nset_global_assignment -name BDF_FILE bus_control.bdf\nset_global_assignment -name BDF_FILE address_pins.bdf\nset_global_assignment -name BDF_FILE address_latch.bdf\nset_global_assignment -name BDF_FILE address_mux.bdf\nset_global_assignment -name VERILOG_FILE bus_switch.v\nset_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top"
  },
  {
    "path": "cpu/bus/test_bus.sv",
    "content": "//==============================================================\n// Test address latch and increment block\n//==============================================================\n`timescale 1us/ 100 ns\n\nmodule test_bus;\n\n// ----------------- CLOCKS AND RESET -----------------\n// Define one full T-clock cycle delay\n`define T #2\nbit clk = 1;\ninitial repeat (26) #1 clk = ~clk;\nreg nreset;\n\n// ----------------------------------------------------\n// Bi-directional bus that can also be tri-stated\nreg  [15:0] abusw;          // Drive it using this bus\nwire [15:0] abus;           // Read it using this bus\nwire [15:0] address;        // Final address ouput\n\n// ----------------- INPUT CONTROL -----------------\nreg ctl_al_we;              // Write enable to address latch\nreg ctl_bus_inc_oe;         // Write incrementer onto the internal data bus\nreg ctl_apin_mux;           // Selects mux1\nreg ctl_apin_mux2;          // Selects mux2\n\n// ----------------- INC/DEC -----------------\nreg ctl_inc_dec;            // Perform decrement (1) or increment (0)\nreg ctl_inc_limit6;         // Limit increment to 6 bits (for incrementing IR)\nreg ctl_inc_cy;             // Address increment, carry in value (+/-1 or 0)\nreg clrpc;                  // Force zero (to clear PC/IR)\n\n// ----------------- OUTPUT/STATUS -----------------\nwire address_is_1;          // Signals when the final address is 1\n\n// ----------------- TEST -------------------\n`define CHECK(arg) \\\n   assert(address==arg);\n\ninitial begin\n    nreset = 0;\n    abusw = 'z;\n    ctl_al_we = 0;\n    ctl_bus_inc_oe = 0;\n    ctl_inc_dec = 0;\n    ctl_inc_limit6 = 0;\n    ctl_inc_cy = 0;\n    clrpc = 0;\n    ctl_apin_mux = 0;\n    ctl_apin_mux2 = 0;\n\n    //------------------------------------------------------------\n    `T  nreset = 1;\n\n    //------------------------------------------------------------\n    // Perform a simple increment and decrement\n    `T  abusw = 16'h1234;\n        ctl_al_we = 1;          // Write value to the latch\n        ctl_apin_mux = 1;       // Output incrementer to the address bus\n        ctl_inc_cy = 1;         // +1  show \"1235\"\n    `T `CHECK(16'h1235);\n        ctl_inc_dec = 1;        // -1  show \"1233\"\n    `T `CHECK(16'h1233);\n    // ...through overflow\n        abusw = 16'hffff;\n        ctl_inc_dec = 0;\n        ctl_inc_cy = 1;         // +1  show \"0\"\n    `T `CHECK(16'h0000);\n        ctl_inc_dec = 1;        // -1  show \"FFFE\"\n    `T `CHECK(16'hFFFE);\n        abusw = 16'h0;\n        ctl_inc_dec = 0;\n        ctl_inc_cy = 1;         // +1  show \"1\"\n    `T `CHECK(16'h0001);\n        ctl_inc_dec = 1;        // -1  show \"FFFF\"\n    `T `CHECK(16'hFFFF);\n        ctl_inc_cy = 0;         // show \"0000\"\n    `T `CHECK(16'h0000);\n        ctl_inc_dec = 0;        // show \"0000\"\n\n    //------------------------------------------------------------\n    // Test the address latch and the mux\n    `T  abusw = 16'hAA50;\n        ctl_al_we = 1;          // Write AA55 to the latch\n        ctl_inc_cy = 1;\n    `T  ctl_al_we = 0;          // show \"AA51\"\n    `T `CHECK(16'hAA51);\n        ctl_apin_mux = 0;\n        ctl_apin_mux2 = 1;\n\n    //------------------------------------------------------------\n    // Test the tri-state db\n    `T  abusw = 'z;\n        ctl_bus_inc_oe = 1;     // Output latched value (AA50)\n    `T `CHECK(16'hAA50);\n\n    `T  $display(\"End of test\");\nend\n\n// Drive 3-state bidirectional bus with these statements\nassign abus = abusw;\n\n//--------------------------------------------------------------\n// Instantiate address latch block\n//--------------------------------------------------------------\n\naddress_latch address_latch_( .* );\n\nendmodule\n"
  },
  {
    "path": "cpu/bus/test_pins.sv",
    "content": "//==============================================================\n// Test address and data pins blocks\n//==============================================================\n`timescale 1us/ 100 ns\n\nmodule test_pins;\n\n// ----------------- CLOCKS AND RESET -----------------\n// Define one full T-clock cycle delay\n`define T #2\nbit clk = 1;\ninitial repeat (24) #1 clk = ~clk;\n\n// ------------------------ ADDRESS PINS ---------------------\nlogic [15:0] ab;            // Internal address bus\nlogic ctl_ab_we;            // Write enable to address pin latch\nlogic pin_control_oe;        // Output enable to address pins; otherwise tri-stated\nwire [15:0] apin;           // Output address bus to address pins\n\n// ------------------------ DATA PINS ------------------------\nlogic ctl_db_we;            // Write enable to data pin output latch\nlogic ctl_db_oe;            // Output enable to internal data bus\nlogic ctl_db_pin_re;        // Read from the data pin into the latch\nlogic ctl_db_pin_oe;        // Output enable to data pins; otherwise tri-stated\nlogic ctl_pin_oe;\n\n// ----------------------------------------------------\n// Bidirectional internal data bus\nlogic  [7:0] db_w;          // Drive it using this bus\nwire [7:0] db;              // Read it using this bus\nassign db = db_w;           // Drive 3-state bidirectional bus\nalways_comb                 // Output to pin bus only when our\nbegin                       // test is not driving it\n    if (db_w==='z)\n        ctl_db_oe = 1;\n    else\n        ctl_db_oe = 0;\nend\n\n// ----------------------------------------------------\n// Bidirectional external data pins\nlogic  [7:0] dpin_w;        // Drive it using this bus\nwire [7:0] dpin;            // Read it using this bus\nassign dpin = dpin_w;       // Drive 3-state bidirectional\nalways_comb                 // Output to pin bus only when our\nbegin                       // test is not driving it\n    if (dpin_w==='z)\n        ctl_db_pin_oe = 1;\n    else\n        ctl_db_pin_oe = 0;\nend\n\n// ----------------- TEST -------------------\n`define CHECKA(arg) \\\n   assert(apin===arg);\n\n`define CHECKD(arg) \\\n   assert(dpin===arg);\n\ninitial begin\n    ab = 16'h0;\n    ctl_ab_we = 0;\n    pin_control_oe = 0;\n    db_w = 'z;\n    dpin_w = 'z;\n    ctl_db_we = 0;\n\n    //------------------------------------------------------------\n    // Test the address pin logic\n    `T  ab = 16'hAA55;      // Latch a value and output it\n        ctl_ab_we = 1;\n        pin_control_oe = 1;\n    `T  ctl_ab_we = 0;\n    `T `CHECKA(16'hAA55);\n        pin_control_oe = 0;\n        ab = 16'h1234;      // Should not affect\n    `T  pin_control_oe = 1;  // Toggle output on and off\n    `T `CHECKA(16'hAA55);\n        pin_control_oe = 0;\n    `T `CHECKA(16'hz);\n\n    //------------------------------------------------------------\n    // Test the data pin logic\n    `T  dpin_w = 8'hAA;     // Load and latch a value\n        ctl_db_pin_re = 1;  // Read into the latch\n\n    `T  dpin_w = 'z;\n        db_w = 8'h55;\n        ctl_db_pin_re = 0;\n        ctl_db_we = 1;\n       `CHECKD(8'hAA);\n    `T  db_w = 'z;\n\n    `T $display(\"End of test\");\nend\n\n//--------------------------------------------------------------\n// Instantiate bus block and assign identical nets and variables\n//--------------------------------------------------------------\n\naddress_pins address_pins_inst( .*, .bus_ab_pin_we(ctl_ab_we), .address(ab[15:0]), .abus(apin[15:0]) );\n\ndata_pins data_pins_inst( .*, .ctl_bus_db_oe(ctl_db_pin_oe), .ctl_bus_db_we(ctl_db_we), .bus_db_pin_oe(ctl_db_pin_oe), .bus_db_pin_re(ctl_db_pin_re), .D(dpin[7:0]) );\n\nendmodule\n"
  },
  {
    "path": "cpu/control/Timings.csv",
    "content": "A-Z80 Timing Table\tM_\tT_\tFunction\tvalid\tnextM\tsetM1\tA:reg rd\tA:reg wr\tinc/dec\tA:latch\tD:reg rd\tD:reg wr\tReg gate\tSW2\tSW1\tDB pads\tFLAGT\tALU\tALU bus\top2 latch\top1 latch\tnibble\toperation\t\tSZ\tXY\tHF\tPF\tNF\tCF\tCF2\t\tSpecial\tComments\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n// 8-bit Load Group\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"#if pla[17] & ~pla[50] : ld r,n\"\t\t\t\"4,3\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\tr8\t<\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#002H T2  AB:000 DB:46  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T5  AB:001 DB:--\t2\t1\tfMRead\t\t\t\tPC\t\t \tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T6  AB:001 DB:01          MREQ RD\t2\t2\tfMRead\t\t\t\t\tPC\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T7  AB:001 DB:01          MREQ RD\t2\t3\tfMRead\t\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"#if pla[61] & ~pla[58] & ~pla[59] : ld r,r'\"\t\t\t4\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\tr8\t<\tu\t\t\t\t<\top1\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#002H T2  AB:000 DB:05  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\t\tY\t\t\t\t\tr8\t\t>r8\t-\t\t\t\t>s0\t\t\tbus\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"#if use_ixiy & pla[58] : ld r,(ix+d)\"\t\t\t\"4,3,5,3\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T1  AB:001 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\tr8\t<\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T2  AB:001 DB:4E  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T3  AB:001 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#008H T4  AB:001 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#009H T5  AB:002 DB:--\t2\t1\tfMRead\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#010H T6  AB:002 DB:01          MREQ RD\t2\t2\tfMRead\t\t\t\t\tPC\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#011H T7  AB:002 DB:01          MREQ RD\t2\t3\tfMRead\t \tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#012H T8  AB:002 DB:--\t3\t1\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tWZ=IX+d\t\n#013H T9  AB:002 DB:--\t3\t2\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tWZ=IX+d\t\n#014H T10 AB:002 DB:--\t3\t3\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tWZ=IX+d\t\n#015H T11 AB:002 DB:--\t3\t4\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tWZ=IX+d\t\n#016H T12 AB:002 DB:--\t3\t5\t\t\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tWZ=IX+d\tClears the IX/IY and ...\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"#if ~use_ixiy & pla[58] : ld r,(hl)\"\t\t\t\"4,3\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\tr8\t<\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#002H T2  AB:000 DB:46  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T5  AB:003 DB:--\t2\t1\tfMRead\t\t\t\tHL\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T6  AB:003 DB:03          MREQ RD\t2\t2\tfMRead\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T7  AB:003 DB:03          MREQ RD\t2\t3\tfMRead\t\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#017H T13 AB:001 DB:--\t4\t1\tfMRead\t\t\t\t\t\t\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t...continues here\n#018H T14 AB:001 DB:4E          MREQ RD\t4\t2\tfMRead\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#019H T15 AB:001 DB:4E          MREQ RD\t4\t3\tfMRead\t\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"#if use_ixiy & pla[59] : ld (ix+d),r\"\t\t\t\"4,3,5,3\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T1  AB:001 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T2  AB:001 DB:70  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T3  AB:001 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#008H T4  AB:001 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#009H T5  AB:002 DB:--\t2\t1\tfMRead\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#010H T6  AB:002 DB:01          MREQ RD\t2\t2\tfMRead\t\t\t\t\tPC\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#011H T7  AB:002 DB:01          MREQ RD\t2\t3\tfMRead\t \tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#012H T8  AB:002 DB:--\t3\t1\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tWZ=IX+d\t\n#013H T9  AB:002 DB:--\t3\t2\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tWZ=IX+d\t\n#014H T10 AB:002 DB:--\t3\t3\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tWZ=IX+d\t\n#015H T11 AB:002 DB:--\t3\t4\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tWZ=IX+d\t\n#016H T12 AB:002 DB:--\t3\t5\t\t\tmw\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tWZ=IX+d\tClears the IX/IY and ...\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"#if ~use_ixiy & pla[59] : ld (hl),r\"\t\t\t\"4,3\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#002H T2  AB:000 DB:70  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tmw\t\t\t\t\t\tr8\t\t>r8\t-\t>\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T5  AB:001 DB:--\t2\t1\tfMWrite\t\t\t\tHL\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T6  AB:001 DB:01          MREQ\t2\t2\tfMWrite\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T7  AB:001 DB:01          MREQ    WR\t2\t3\tfMWrite\t\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#017H T13 AB:000 DB:--\t4\t1\tfMWrite\t\t\t\t\t\t\tR\tr8\t\t>r8\t-\t>\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t...continues here\n#018H T14 AB:000 DB:46          MREQ\t4\t2\tfMWrite\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#019H T15 AB:000 DB:46          MREQ    WR\t4\t3\tfMWrite\t\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"#if pla[40] : ld (ix+d),n\"\t\t\t\"4,3,5,3\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T1  AB:001 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T2  AB:001 DB:36  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T3  AB:001 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#008H T4  AB:001 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#009H T5  AB:002 DB:--\t2\t1\tfMRead\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#010H T6  AB:002 DB:01          MREQ RD\t2\t2\tfMRead\t\t\t\t\tPC\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#011H T7  AB:002 DB:01          MREQ RD\t2\t3\tfMRead\t \tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#012H T8  AB:003 DB:--\t3\t1\tfMRead\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tWZ=IX+d\t\n#013H T9  AB:003 DB:02          MREQ RD\t3\t2\tfMRead\t\t\t\t\tPC\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tWZ=IX+d\t\n#014H T10 AB:003 DB:02          MREQ RD\t3\t3\tfMRead\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tWZ=IX+d\t\"Reads \"\"n\"\" at the same time\"\n#015H T11 AB:003 DB:--\t3\t4\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tWZ=IX+d\t\n#016H T12 AB:003 DB:--\t3\t5\t\t\tmw\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tWZ=IX+d\tClears the IX/IY and ...\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"#if pla[50] & ~pla[40] : ld (hl),n\"\t\t\t\"4,3,3\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#002H T2  AB:000 DB:36  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T5  AB:001 DB:--\t2\t1\tfMRead\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T6  AB:001 DB:01          MREQ RD\t2\t2\tfMRead\t\t\t\t\tPC\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T7  AB:001 DB:01          MREQ RD\t2\t3\tfMRead\t \tmw\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#008H T8  AB:001 DB:--\t3\t1\tfMWrite\t\t\t\tHL\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#009H T9  AB:001 DB:01          MREQ\t3\t2\tfMWrite\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#010H T10 AB:001 DB:01          MREQ    WR\t3\t3\tfMWrite\t\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#017H T13 AB:002 DB:--\t4\t1\tfMWrite\t\t\t\t\t\t\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t...continues here\n#018H T14 AB:002 DB:02          MREQ\t4\t2\tfMWrite\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#019H T15 AB:002 DB:02          MREQ    WR\t4\t3\tfMWrite\t\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"#if pla[8] & pla[13] : ld (rr),a\"\t\t\t\"4,3\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#002H T2  AB:000 DB:02  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tmw\t\t\t\t\t\tA\t\t>h\tu\t>\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T5  AB:001 DB:--\t2\t1\tfMWrite\t\t\t\tr16\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T6  AB:001 DB:FF          MREQ\t2\t2\tfMWrite\t\t\t\t\tWZ\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T7  AB:001 DB:FF          MREQ    WR\t2\t3\tfMWrite\t\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"#if pla[8] & ~pla[13] : ld a,(rr)\"\t\t\t\"4,3\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\tA\t<\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#002H T2  AB:000 DB:0A  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T5  AB:002 DB:--\t2\t1\tfMRead\t\t\t\tr16\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T6  AB:002 DB:02          MREQ RD\t2\t2\tfMRead\t\t\t\t\tWZ\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T7  AB:002 DB:02          MREQ RD\t2\t3\tfMRead\t\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"#if pla[38] & pla[13] : ld (nn),a\"\t\t\t\"4,3,3,3\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#002H T2  AB:000 DB:32  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T5  AB:001 DB:--\t2\t1\tfMRead\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T6  AB:001 DB:01          MREQ RD\t2\t2\tfMRead\t\t\t\t\tPC\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T7  AB:001 DB:01          MREQ RD\t2\t3\tfMRead\t\tmr\t\t\t\t\t\t\tZ\t<l\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#008H T8  AB:002 DB:--\t3\t1\tfMRead\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#009H T9  AB:002 DB:02          MREQ RD\t3\t2\tfMRead\t\t\t\t\tPC\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#010H T10 AB:002 DB:02          MREQ RD\t3\t3\tfMRead\t\tmw\t\tWZ\t\t\tW\t\tW\t<h\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#011H T11 AB:001 DB:--\t4\t1\tfMWrite\t\t\t\t\t\t\tR\tA\t\t>h\tu\t>\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#012H T12 AB:001 DB:FE          MREQ\t4\t2\tfMWrite\t\t\t\t\tWZ\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#013H T13 AB:001 DB:FE          MREQ    WR\t4\t3\tfMWrite\t\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"#if pla[38] & ~pla[13] : ld a,(nn)\"\t\t\t\"4,3,3,3\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\tA\t<\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#002H T2  AB:000 DB:3A  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T5  AB:001 DB:--\t2\t1\tfMRead\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T6  AB:001 DB:01          MREQ RD\t2\t2\tfMRead\t\t\t\t\tPC\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T7  AB:001 DB:01          MREQ RD\t2\t3\tfMRead\t\tmr\t\t\t\t\t\t\tZ\t<l\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#008H T8  AB:002 DB:--\t3\t1\tfMRead\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#009H T9  AB:002 DB:02          MREQ RD\t3\t2\tfMRead\t\t\t\t\tPC\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#010H T10 AB:002 DB:02          MREQ RD\t3\t3\tfMRead\t\tmr\t\t\t\t\t\t\tW\t<h\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#011H T11 AB:001 DB:--\t4\t1\tfMRead\t\t\t\tWZ\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#012H T12 AB:001 DB:01          MREQ RD\t4\t2\tfMRead\t\t\t\t\tWZ\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#013H T13 AB:001 DB:01          MREQ RD\t4\t3\tfMRead\t\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"#if pla[83] : ld a,i/a,r\"\t\t\t5\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T1  AB:001 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\tA\t<\t\t\t\talu\t<\tres\t\t\tH\tOR\t\t*\t*\t*\tiff2\t0\t\t\t\t\t\n#006H T2  AB:001 DB:57  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\tF\t<\t\t\t\t<\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T3  AB:001 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\tAF\t\t>\t\t\t\t>\t>s0\t\tbus\tbus\t\t\t\t*\t*\t*\t*\t*\t*\t\t\t\t\n#008H T4  AB:001 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\t\t\t\t\t\t\tI/R\t\t>r8'\t-\t\t\talu\t>s0\t\tbus\tbus\tL\tOR\t\t*\t*\t*\t\t0\t\t\t\t\t\n#009H T5  AB:001 DB:--\t1\t5\t\t\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"#if pla[57] : ld i,a/r,a\"\t\t\t5\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T1  AB:001 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T2  AB:001 DB:47  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T3  AB:001 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\tAF\t\t>\t\t\t\t>\t>s0\t\tbus\tbus\t\t\t\t*\t*\t*\t*\t*\t*\t\t\t\t\n#008H T4  AB:001 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\t\t\t\t\t\t\t\tI/R\t<\tu\t\t\t\t<\top1\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#009H T5  AB:001 DB:--\t1\t5\t\t\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n// 16-bit Load Group\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"#if pla[7] : ld rr,nn\"\t\t\t\"4,3,3\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\trh\t<\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tUSE_SP\t\n#002H T2  AB:000 DB:01  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T5  AB:001 DB:--\t2\t1\tfMRead\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T6  AB:001 DB:01          MREQ RD\t2\t2\tfMRead\t\t\t\t\tPC\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T7  AB:001 DB:01          MREQ RD\t2\t3\tfMRead\t\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#008H T8  AB:002 DB:--\t3\t1\tfMRead\t\t\t\tPC\t\t\tW\t\trl\t<\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tUSE_SP\t\n#009H T9  AB:002 DB:02          MREQ RD\t3\t2\tfMRead\t\t\t\t\tPC\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#010H T10 AB:002 DB:02          MREQ RD\t3\t3\tfMRead\t\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"#if pla[30] & pla[13] : ld (nn),hl\"\t\t\t\"4,3,3,3,3\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#002H T2  AB:000 DB:22  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T5  AB:001 DB:--\t2\t1\tfMRead\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T6  AB:001 DB:01          MREQ RD\t2\t2\tfMRead\t\t\t\t\tPC\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T7  AB:001 DB:01          MREQ RD\t2\t3\tfMRead\t\tmr\t\t\t\t\t\t\tZ\t<l\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#008H T8  AB:002 DB:--\t3\t1\tfMRead\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#009H T9  AB:002 DB:02          MREQ RD\t3\t2\tfMRead\t\t\t\t\tPC\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#010H T10 AB:002 DB:02          MREQ RD\t3\t3\tfMRead\t\tmw\t\tWZ\t\t\tW\t\tW\t<h\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#011H T11 AB:001 DB:--\t4\t1\tfMWrite\t\t\t\t\t\t\tR\trl\t\t>l\t\t>\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#012H T12 AB:001 DB:01          MREQ\t4\t2\tfMWrite\t\t\t\t\tWZ\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#013H T13 AB:001 DB:01          MREQ    WR\t4\t3\tfMWrite\t\tmw\t\tWZ\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#014H T14 AB:002 DB:--\t5\t1\tfMWrite\t\t\t\t\t\t\tR\trh\t\t>h\tu\t>\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#015H T15 AB:002 DB:02          MREQ\t5\t2\tfMWrite\t\t\t\t\tWZ\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#016H T16 AB:002 DB:02          MREQ    WR\t5\t3\tfMWrite\t\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"#if pla[30] & ~pla[13] : ld hl,(nn)\"\t\t\t\"4,3,3,3,3\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#002H T2  AB:000 DB:2A  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T5  AB:001 DB:--\t2\t1\tfMRead\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T6  AB:001 DB:01          MREQ RD\t2\t2\tfMRead\t\t\t\t\tPC\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T7  AB:001 DB:01          MREQ RD\t2\t3\tfMRead\t\tmr\t\t\t\t\t\t\tZ\t<l\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#008H T8  AB:002 DB:--\t3\t1\tfMRead\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#009H T9  AB:002 DB:02          MREQ RD\t3\t2\tfMRead\t\t\t\t\tPC\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#010H T10 AB:002 DB:02          MREQ RD\t3\t3\tfMRead\t\tmr\t\t\t\t\t\t\tW\t<h\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#011H T11 AB:001 DB:--\t4\t1\tfMRead\t\t\t\tWZ\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#012H T12 AB:001 DB:01          MREQ RD\t4\t2\tfMRead\t\t\t\t\tWZ\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#013H T13 AB:001 DB:01          MREQ RD\t4\t3\tfMRead\t\tmr\t\t\t\t\t\t\trl\t<\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#014H T14 AB:002 DB:--\t5\t1\tfMRead\t\t\t\tWZ\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#015H T15 AB:002 DB:02          MREQ RD\t5\t2\tfMRead\t\t\t\t\tWZ\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#016H T16 AB:002 DB:02          MREQ RD\t5\t3\tfMRead\t\t\tY\t\t\t\t\t\trh\t<\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"#if pla[31] & pla[33] : ld (nn),rr\"\t\t\t\"4,3,3,3,3\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T1  AB:001 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T2  AB:001 DB:43  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T3  AB:001 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#008H T4  AB:001 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#009H T5  AB:002 DB:--\t2\t1\tfMRead\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#010H T6  AB:002 DB:01          MREQ RD\t2\t2\tfMRead\t\t\t\t\tPC\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#011H T7  AB:002 DB:01          MREQ RD\t2\t3\tfMRead\t\tmr\t\t\t\t\t\t\tZ\t<l\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#012H T8  AB:003 DB:--\t3\t1\tfMRead\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#013H T9  AB:003 DB:02          MREQ RD\t3\t2\tfMRead\t\t\t\t\tPC\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#014H T10 AB:003 DB:02          MREQ RD\t3\t3\tfMRead\t\tmw\t\tWZ\t\t\tW\t\tW\t<h\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#015H T11 AB:001 DB:--\t4\t1\tfMWrite\t\t\t\t\t\t\tR\trl\t\t>l\t\t>\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tUSE_SP\t\n#016H T12 AB:001 DB:FF          MREQ\t4\t2\tfMWrite\t\t\t\t\tWZ\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#017H T13 AB:001 DB:FF          MREQ    WR\t4\t3\tfMWrite\t\tmw\t\tWZ\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#018H T14 AB:002 DB:--\t5\t1\tfMWrite\t\t\t\t\t\t\tR\trh\t\t>h\tu\t>\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tUSE_SP\t\n#019H T15 AB:002 DB:C3          MREQ\t5\t2\tfMWrite\t\t\t\t\tWZ\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#020H T16 AB:002 DB:C3          MREQ    WR\t5\t3\tfMWrite\t\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"#if pla[31] & ~pla[33] : ld rr,(nn)\"\t\t\t\"4,3,3,3,3\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T1  AB:001 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T2  AB:001 DB:43  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T3  AB:001 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#008H T4  AB:001 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#009H T5  AB:002 DB:--\t2\t1\tfMRead\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#010H T6  AB:002 DB:01          MREQ RD\t2\t2\tfMRead\t\t\t\t\tPC\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#011H T7  AB:002 DB:01          MREQ RD\t2\t3\tfMRead\t\tmr\t\t\t\t\t\t\tZ\t<l\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#012H T8  AB:003 DB:--\t3\t1\tfMRead\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#013H T9  AB:003 DB:02          MREQ RD\t3\t2\tfMRead\t\t\t\t\tPC\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#014H T10 AB:003 DB:02          MREQ RD\t3\t3\tfMRead\t\tmr\t\t\t\t\t\t\tW\t<h\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#015H T11 AB:001 DB:--\t4\t1\tfMRead\t\t\t\tWZ\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#016H T12 AB:001 DB:FF          MREQ RD\t4\t2\tfMRead\t\t\t\t\tWZ\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#017H T13 AB:001 DB:FF          MREQ RD\t4\t3\tfMRead\t\tmr\t\t\t\t\t\t\trl\t<\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tUSE_SP\t\n#018H T14 AB:002 DB:--\t5\t1\tfMRead\t\t\t\tWZ\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#019H T15 AB:002 DB:C3          MREQ RD\t5\t2\tfMRead\t\t\t\t\tWZ\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#020H T16 AB:002 DB:C3          MREQ RD\t5\t3\tfMRead\t\t\tY\t\t\t\t\t\trh\t<\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tUSE_SP\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"#if pla[5] : ld sp,hl\"\t\t\t6\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#002H T2  AB:000 DB:F9  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\t\t\tHL\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T5  AB:000 DB:--\t1\t5\t\t\t\t\t\tSP\t\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T6  AB:000 DB:--\t1\t6\t\t\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[23] & pla[16] : push qq\t\t\t\"5,3,3\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#002H T2  AB:000 DB:C5  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T5  AB:000 DB:--\t1\t5\t\t\tmw\t\tSP\t\t-\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T6  AB:002 DB:--\t2\t1\tfMWrite\t\t\t\t\t\t-\tP\trh\t\t>h\tu\t>\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T7  AB:002 DB:02          MREQ\t2\t2\tfMWrite\t\t\t\t\tSP\t-\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#008H T8  AB:002 DB:02          MREQ    WR\t2\t3\tfMWrite\t\tmw\t\tSP\t\t-\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#009H T9  AB:001 DB:--\t3\t1\tfMWrite\t\t\t\t\t\t-\tP\trl\t\t>l\t\t>\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#010H T10 AB:001 DB:01          MREQ\t3\t2\tfMWrite\t\t\t\t\tSP\t-\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#011H T11 AB:001 DB:01          MREQ    WR\t3\t3\tfMWrite\t\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[23] & ~pla[16] : pop qq\t\t\t\"4,3,3\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#002H T2  AB:000 DB:C1  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T5  AB:001 DB:--\t2\t1\tfMRead\t\t\t\tSP\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T6  AB:001 DB:01          MREQ RD\t2\t2\tfMRead\t\t\t\t\tSP\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T7  AB:001 DB:01          MREQ RD\t2\t3\tfMRead\t\tmr\t\t\t\t\t\t\trl\t<\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#008H T8  AB:002 DB:--\t3\t1\tfMRead\t\t\t\tSP\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#009H T9  AB:002 DB:02          MREQ RD\t3\t2\tfMRead\t\t\t\t\tSP\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#010H T10 AB:002 DB:02          MREQ RD\t3\t3\tfMRead\t\t\tY\t\t\t\t\t\trh\t<\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"// Exchange, Block Transfer and Search Groups\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"#if pla[2] : ex de,hl\"\t\t\t4\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#002H T2  AB:000 DB:EB  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tEx_DE_HL\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"#if pla[39] : ex af,af'\"\t\t\t4\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#002H T2  AB:000 DB:08  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tEx_AF_AF'\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[1] : exx\t\t\t4\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#002H T2  AB:000 DB:D9  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tEXX\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"#if pla[10] : ex (sp),hl\"\t\t\t\"4,3,4,3,5\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#002H T2  AB:000 DB:E3  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T5  AB:0FD DB:--\t2\t1\tfMRead\t\t\t\tSP\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T6  AB:0FD DB:03          MREQ RD\t2\t2\tfMRead\t\t\t\t\tSP\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T7  AB:0FD DB:03          MREQ RD\t2\t3\tfMRead\t\tmr\t\t\t\t\t\t\tZ\t<l\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#008H T8  AB:0FE DB:--\t3\t1\tfMRead\t\t\t\tSP\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#009H T9  AB:0FE DB:D1          MREQ RD\t3\t2\tfMRead\t\t\t\t\tSP\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#010H T10 AB:0FE DB:D1          MREQ RD\t3\t3\tfMRead\t\t\t\t\t\t\t\t\tW\t<h\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#011H T11 AB:0FE DB:-- \t3\t4\t\t\tmw\t\tSP\t\t-\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#012H T12 AB:0FE DB:--\t4\t1\tfMWrite\t\t\t\t\t\t-\tP\trh\t\t>h\tu\t>\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#013H T13 AB:0FE DB:00          MREQ\t4\t2\tfMWrite\t\t\t\t\tSP\t-\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#014H T14 AB:0FE DB:00          MREQ    WR\t4\t3\tfMWrite\t\tmw\t\tSP\t\t-\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#015H T15 AB:0FD DB:--\t5\t1\tfMWrite\t\t\t\t\t\t-\tP\trl\t\t>l\t\t>\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#016H T16 AB:0FD DB:01          MREQ\t5\t2\tfMWrite\t\t\t\t\tSP\t-\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#017H T17 AB:0FD DB:01          MREQ    WR \t5\t3\tfMWrite\t\t\t\tWZ\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#018H T18 AB:0FD DB:01\t5\t4\t\t\t\t\t\tHL\t\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#019H T19 AB:0FD DB:01\t5\t5\t\t\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[0] : Non-repeating version of a block instruction\t\t\t\"4,3,5,(5)\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#always\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tNonRep\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[12] : ldi/ldir/ldd/lddr\t\t\t\"4,3,5,(5)\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#035H T1  AB:00A DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\talu\t\tres\t\t\tH\tOR\t\t\t*\t*\tREP\t0\t\tR\t\t\t\n#036H T2  AB:00A DB:B0  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\tF\t<\t\t\t\t<\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#037H T3  AB:004 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\tAF\t\t>\t\t\t\t>\t>s0\t\tbus\tbus\t\t\t\t*\t*\t*\t*\t*\t*\t\t\t\t\n#038H T4  AB:004 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#039H T5  AB:000 DB:--\t2\t1\tfMRead\t\t\t\tHL\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#040H T6  AB:000 DB:21          MREQ RD\t2\t2\tfMRead\t\t\t\t\tHL\top3\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#041H T7  AB:000 DB:21          MREQ RD\t2\t3\tfMRead\t\tmw\t\t\t\t\t\t\t\t\td\t<\tR\talu\t>s0\t\tbus\t\tL\tADD\t\t\t\t*\t\t\t\tW\t\t\t\n#042H T8  AB:000 DB:--\t3\t1\tfMWrite\t\t\t\tDE\t\t\tW\t\t\t\t\t\t\talu\t<\tres\t\t\tH\tADD\t\t\t\t\t\t\t\tR\t\t\t\n#043H T9  AB:000 DB:21          MREQ\t3\t2\tfMWrite\t\t\t\t\tDE\top3\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#044H T10 AB:000 DB:21          MREQ    WR\t3\t3\tfMWrite\t\t\t\tBC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#045H T11 AB:000 DB:21\t3\t4\t\t\t\t\t\tBC\t-\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tWriteBC=1\tUpdate repeat flag latch\n#046H T12 AB:000 DB:21\t3\t5\t\t\tY\tBR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#047H T13 AB:000 DB:--\t4\t1\t\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#048H T14 AB:000 DB:--\t4\t2\t\t\t\t\t\tPC\t-\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#049H T15 AB:000 DB:--\t4\t3\t\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#050H T16 AB:000 DB:--\t4\t4\t\t\t\t\t\tPC\t-\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#051H T17 AB:000 DB:--\t4\t5\t\t\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[11] : cpi/cpir/cpd/cpdr\t\t\t\"4,3,5,(5)\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#035H T1  AB:00A DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\talu\t<\tres\t\t0\tH\tSUB\t\t\t*\t\tREP\t1\t\tR\t\t\t\n#036H T2  AB:00A DB:B1  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\tF\t<\t\t\t\t<\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t?NF_HF\t\n#037H T3  AB:004 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\tAF\t\t>\t\t\t\t>\t>s0\t\tbus\tbus\t\t\t\t*\t*\t*\t*\t*\t*\t\t\t\t\n#038H T4  AB:004 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#039H T5  AB:000 DB:--\t2\t1\tfMRead\t\t\t\tHL\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#040H T6  AB:000 DB:21          MREQ RD\t2\t2\tfMRead\t\t\t\t\tHL\top3\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#041H T7  AB:000 DB:21          MREQ RD\t2\t3\tfMRead\t\tY\t\t\t\t\t\t\t\t\td\t<\tR\talu\t>s0\t\tbus\t\tL\tSUB\t\t\t\t*\t\t\t\tW\t\t\t\n#042H T8  AB:000 DB:--\t3\t1\t\t\t\t\t\t\t\t\t\t\t\t\t\t\talu\t<\tres\t\t\tH\tSUB\t\t*\t\t\t\t\t\tR\t\t\t\n#043H T9  AB:000 DB:--\t3\t2\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#044H T10 AB:000 DB:--\t3\t3\t\t\t\t\tBC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#045H T11 AB:000 DB:--\t3\t4\t\t\t\t\t\tBC\t-\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tWriteBC=1\tUpdate repeat flag latch\n#046H T12 AB:000 DB:--\t3\t5\t\t\tY\tBRZ\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#047H T13 AB:000 DB:--\t4\t1\t\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#048H T14 AB:000 DB:--\t4\t2\t\t\t\t\t\tPC\t-\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#049H T15 AB:000 DB:--\t4\t3\t\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#050H T16 AB:000 DB:--\t4\t4\t\t\t\t\t\tPC\t-\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#051H T17 AB:000 DB:--\t4\t5\t\t\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n// 8-bit Arithmetic and Logic Group\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"#if pla[65] & ~pla[52] : add/sub/and/or/xor/cmp a,r\"\t\t\t4\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t?\t<\tu\t\t\talu\t<\tres\t\t\tH\tPLA\t\t*\t?\t\t?\t?\t*\t\t\t\tA is stored in each ALU PLA below\n#002H T2  AB:000 DB:80  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\tF\t<\t\t\t\t<\t\t\t\t\t\tPLA\t\t\t\t\t\t\t\t\t\t?NF_HF_CF\t\"If (NF), complement HF, CF\"\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\tAF\t\t>\t\t\t\t>\t>s0\t\tbus\tbus\t\t\t\t*\t*\t*\t*\t*\t*\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\t\tY\t\t\t\t\tr8\t\t>r8\t-\t\t\talu\t>s0\t\tbus\t\tL\tPLA\t\t*\t*\t*\t\t?\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"#if pla[64] : add/sub/and/or/xor/cmp a,n\"\t\t\t\"4,3\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t?\t<\tu\t\t\talu\t<\tres\t\t\tH\tPLA\t\t*\t?\t\t?\t?\t*\t\t\t\tA is stored in each ALU PLA below\n#002H T2  AB:000 DB:C6  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\tF\t<\t\t\t\t<\t\t\t\t\t\tPLA\t\t\t\t\t\t\t\t\t\t?NF_HF_CF\t\"If (NF), complement HF, CF\"\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\tAF\t\t>\t\t\t\t>\t>s0\t\tbus\tbus\t\t\t\t*\t*\t*\t*\t*\t*\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tmr\t\t\t\t\t\tr8\t\t>r8\t-\t\t\talu\t>s0\t\tbus\t\tL\tPLA\t\t*\t*\t*\t\t?\t\t\t\t\t\n#005H T5  AB:001 DB:--\t2\t1\tfMRead\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\tPLA\t\t\t\t\t\t\t\t\t\t\t\n#006H T6  AB:001 DB:01          MREQ RD\t2\t2\tfMRead\t\t\t\t\tPC\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T7  AB:001 DB:01          MREQ RD\t2\t3\tfMRead\t\t\tY\t\t\t\t\t\t\t\td\t<\tR\talu\t>s0\t\tbus\t\tL\tPLA\t\t*\t*\t*\t\t?\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if use_ixiy & pla[52] : add/sub/and/or/xor/cp (ix+d)\t\t\t\"4,3,5,3\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T1  AB:001 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T2  AB:001 DB:86  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T3  AB:001 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\tAF\t\t>\t\t\t\t>\t>s0\t\tbus\tbus\t\t\t\t*\t*\t*\t*\t*\t*\t\t\t\t\n#008H T4  AB:001 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#009H T5  AB:002 DB:--\t2\t1\tfMRead\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#010H T6  AB:002 DB:01          MREQ RD\t2\t2\tfMRead\t\t\t\t\tPC\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#011H T7  AB:002 DB:01          MREQ RD\t2\t3\tfMRead\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#012H T8  AB:002 DB:--\t3\t1\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tWZ=IX+d\t\n#013H T9  AB:002 DB:--\t3\t2\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tWZ=IX+d\t\n#014H T10 AB:002 DB:--\t3\t3\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tWZ=IX+d\t\"Reads \"\"n\"\" at the same time\"\n#015H T11 AB:002 DB:--\t3\t4\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tWZ=IX+d\t\n#016H T12 AB:002 DB:--\t3\t5\t\t\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tWZ=IX+d\tClears the IX/IY and ...\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if ~use_ixiy & pla[52] : add/sub/and/or/xor/cp (hl)\t\t\t\"4,3\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t?\t<\tu\t\t\talu\t<\tres\t\t\tH\tPLA\t\t*\t?\t\t?\t?\t*\t\t\t\tA is stored in each ALU PLA below\n#002H T2  AB:000 DB:86  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\tF\t<\t\t\t\t<\t\t\t\t\t\tPLA\t\t\t\t\t\t\t\t\t\t?NF_HF_CF\t\"If (NF), complement HF, CF\"\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\tAF\t\t>\t\t\t\t>\t>s0\t\tbus\tbus\t\t\t\t*\t*\t*\t*\t*\t*\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T5  AB:001 DB:--\t2\t1\tfMRead\t\t\t\tHL\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T6  AB:001 DB:01          MREQ RD\t2\t2\tfMRead\t\t\t\t\tWZ\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T7  AB:001 DB:01          MREQ RD\t2\t3\tfMRead\t\t\tY\t\t\t\t\t\t\t\td\t<\tR\talu\t>s0\t\tbus\t\tL\tPLA\t\t*\t*\t*\t\t?\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#017H T13 AB:000 DB:--\t4\t1\tfMRead\t\t\t\t\t\t\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t...continues here\n#018H T14 AB:000 DB:DD          MREQ RD\t4\t2\tfMRead\t\t\t\t\t\t\t\tAF\t\t>\t\t\t\t>\t>s0\t\tbus\tbus\t\t\t\t*\t*\t*\t\t*\t*\t\t\t\tReloads AF since (IX+d) used ALU core\n#019H T15 AB:000 DB:DD          MREQ RD\t4\t3\tfMRead\t\t\tY\t\t\t\t\t\t\t\td\t<\tR\talu\t>s0\t\tbus\t\tL\tPLA\t\t*\t*\t*\t\t?\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[66] & ~pla[53] : inc/dec r\t\t\t4\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\tr8\t<\tu\t\t\talu\t<\tres\t\t\tH\tADC\t\t*\t*\t\tV\t\t\tR\t\t\t\n#002H T2  AB:000 DB:05  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\tF\t<\t\t\t\t<\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t?NF_HF\t\"If (NF), complement HF\"\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\tAF\t\t>\t\t\t\t>\t>s0\t\tbus\tbus\t\t\t\t*\t*\t*\t*\t*\t*\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\t\tY\t\t\t\t\tr8'\t\t>r8'\t-\t\t\talu\t>s0\t\t0\tbus\tL\tADC\t\t*\t*\t*\t\t0\t1\tW\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[75] : dec\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t1\t0\t\t\tNEG_OP2\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t1\t0\t\t\tNEG_OP2\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if (M2 | M4) & pla[75] : dec\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#always\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t1\t0\t\t\tNEG_OP2\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if use_ixiy & pla[53] : inc/dec (ix+d)\t\t\t\"4,3,5,4,3\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T1  AB:001 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T2  AB:001 DB:34  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T3  AB:001 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\tAF\t\t>\t\t\t\t>\t>s0\t\tbus\tbus\t\t\t\t*\t*\t*\t*\t*\t*\t\t\t\t\n#008H T4  AB:001 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#009H T5  AB:002 DB:--\t2\t1\tfMRead\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#010H T6  AB:002 DB:01          MREQ RD\t2\t2\tfMRead\t\t\t\t\tPC\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#011H T7  AB:002 DB:01          MREQ RD\t2\t3\tfMRead\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#012H T8  AB:002 DB:--\t3\t1\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tWZ=IX+d\t\n#013H T9  AB:002 DB:--\t3\t2\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tWZ=IX+d\t\n#014H T10 AB:002 DB:--\t3\t3\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tWZ=IX+d\t\n#015H T11 AB:002 DB:--\t3\t4\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tWZ=IX+d\t\n#016H T12 AB:002 DB:--\t3\t5\t\t\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tWZ=IX+d\tClears the IX/IY and ...\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if ~use_ixiy & pla[53] : inc/dec (hl)\t\t\t\"4,4,3\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#002H T2  AB:000 DB:34  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\tF\t<\t\t\t\t<\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t?NF_HF\t\"If (NF), complement HF\"\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\tAF\t\t>\t\t\t\t>\t>s0\t\tbus\tbus\t\t\t\t*\t*\t*\t*\t*\t*\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T5  AB:001 DB:--\t2\t1\tfMRead\t\t\t\tHL\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T6  AB:001 DB:01          MREQ RD\t2\t2\tfMRead\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T7  AB:001 DB:01          MREQ RD\t2\t3\tfMRead\t\t\t\t\t\t\t\t\t\t\td\t<\tR\talu\t>s0\t\t0\tbus\tL\tADC\t\t\t\t*\t\t0\t1\tW\t\t\t\n#008H T8  AB:001 DB:--\t2\t4\t\t\tmw\t\t\t\t\t\t\t\t\tu\t>\tW\talu\t<\tres\t\t\tH\tADC\t\t*\t*\t\tV\t\t\tR\t\t\t\n#009H T9  AB:001 DB:--\t3\t1\tfMWrite\t\t\t\t\t\t\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#010H T10 AB:001 DB:02          MREQ\t3\t2\tfMWrite\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#011H T11 AB:001 DB:02          MREQ    WR\t3\t3\tfMWrite\t\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#017H T13 AB:002 DB:--\t4\t1\tfMRead\t\t\t\t\t\t\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t...continues here\n#018H T14 AB:002 DB:01          MREQ RD\t4\t2\tfMRead\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#019H T15 AB:002 DB:01          MREQ RD\t4\t3\tfMRead\t\t\t\t\t\t\t\t\t\t\td\t<\tR\talu\t>s0\t\t0\tbus\tL\tADC\t\t\t\t*\t\t0\t1\tW\t\t\t\n#020H T16 AB:002 DB:--\t4\t4\t\t\tmw\t\t\t\t\t\t\t\t\tu\t>\tW\talu\t<\tres\t\t\tH\tADC\t\t*\t*\t\tV\t\t\tR\t\t\t\n#021H T17 AB:002 DB:--\t5\t1\tfMWrite\t\t\t\t\t\t\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#022H T18 AB:002 DB:02          MREQ\t5\t2\tfMWrite\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#023H T19 AB:002 DB:02          MREQ    WR\t5\t3\tfMWrite\t\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n// 16-bit Arithmetic Group\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"#if pla[69] : add hl,ss\"\t\t\t\"4,4,3\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#002H T2  AB:000 DB:09  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\tF\t<\t\t\t\t<\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\tAF\t\t>\t\t\t\t>\t>s0\t\tbus\tbus\t\t\t\t*\t*\t*\t*\t0\t*\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tY\t\t\t\t\t\tL\t\t>l\td\t\t\t\t>s0\t\t\tbus\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T5  AB:000 DB:--\t2\t1\t\t\t\t\t\t\t\t\trl\t\t>l\td\t\t\talu\t>s0\t\tbus\t\tL\tADD\t\t\t\t*\t\t\t\t\t\tUSE_SP\t\n#006H T6  AB:000 DB:--\t2\t2\t\t\t\t\t\t\t\t\t\tZ\t<l\tu\t\t\talu\t<\tres\t\t\tH\tADC\t\t\t*\t\t\t\t*\t\t\t\t\n#007H T7  AB:000 DB:--\t2\t3\t\t\t\t\t\t\t\t\tH\t\t>\t\t\t\t\t>s0\t\t\tbus\t\t\t\t\t\t\t\t\t\t\t\t\t\n#008H T8  AB:000 DB:--\t2\t4\t\t\tY\t\t\t\t\t\trh\t\t>\t\t\t\talu\t>s0\t\tbus\t\tL\tADC\t\t\t\t*\t\t\t\t\t\tUSE_SP\t\n#009H T9  AB:000 DB:--\t3\t1\t\t\t\t\tWZ\t\t\tW\t\tW\t<h\tu\t\t\talu\t<\tres\t\t\tH\tADC\t\t\t*\t\t\t\t*\t\t\t\t\n#010H T10 AB:000 DB:--\t3\t2\t\t\t\t\t\tHL\t\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#011H T11 AB:000 DB:--\t3\t3\t\t\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"#if op3 & pla[68] : adc hl,ss\"\t\t\t\"4,4,3\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T1  AB:001 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T2  AB:001 DB:42  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\tF\t<\t\t\t\t<\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T3  AB:001 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\tAF\t\t>\t\t\t\t>\t>s0\t\tbus\tbus\t\t\t\t*\t*\t*\t*\t0\t*\t\t\t\t\n#008H T4  AB:001 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tY\t\t\t\t\t\tL\t\t>l\td\t\t\t\t>s0\t\t\tbus\t\t\t\t\t\t\t\t\t\t\t\t\t\n#009H T5  AB:001 DB:--\t2\t1\t\t\t\t\t\t\t\t\trl\t\t>l\td\t\t\talu\t>s0\t\tbus\t\tL\tADC\t\t\t\t*\t\t\t\t\t\tUSE_SP\t\n#010H T6  AB:001 DB:--\t2\t2\t\t\t\t\t\t\t\t\t\tZ\t<l\tu\t\t\talu\t<\tres\t\t\tH\tADC\t\t*\t*\t\t\t\t*\t\t\t\t\n#011H T7  AB:001 DB:--\t2\t3\t\t\t\t\t\t\t\t\tH\t\t>\t\t\t\t\t>s0\t\t\tbus\t\t\t\t\t\t\t\t\t\t\t\t\t\n#012H T8  AB:001 DB:--\t2\t4\t\t\tY\t\t\t\t\t\trh\t\t>\t\t\t\talu\t>s0\t\tbus\t\tL\tADC\t\t\t\t*\t\t\t\t\t\tUSE_SP\t\n#013H T9  AB:001 DB:--\t3\t1\t\t\t\t\tWZ\t\t\tW\t\tW\t<h\tu\t\t\talu\t<\tres\t\t\tH\tADC\t\t*\t*\t\tV\t\t*\t\t\tZERO_16BIT\t\n#014H T10 AB:001 DB:--\t3\t2\t\t\t\t\t\tHL\t\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#015H T11 AB:001 DB:--\t3\t3\t\t\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"#if ~op3 & pla[68] : sbc hl,ss\"\t\t\t\"4,4,3\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T1  AB:001 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T2  AB:001 DB:42  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\tF\t<\t\t\t\t<\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t?NF_HF_CF\t\n#007H T3  AB:001 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\tAF\t\t>\t\t\t\t>\t>s0\t\tbus\tbus\t\t\t\t*\t*\t*\t*\t1\t*\t\t\t\t\n#008H T4  AB:001 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tY\t\t\t\t\t\tL\t\t>l\td\t\t\t\t>s0\t\t\tbus\t\t\t\t\t\t\t\t\t\t\t\t\t\n#009H T5  AB:001 DB:--\t2\t1\t\t\t\t\t\t\t\t\trl\t\t>l\td\t\t\talu\t>s0\t\tbus\t\tL\tSBC\t\t\t\t*\t\t\t\t\t\tUSE_SP\t\n#010H T6  AB:001 DB:--\t2\t2\t\t\t\t\t\t\t\t\t\tZ\t<l\tu\t\t\talu\t<\tres\t\t\tH\tSBC\t\t*\t*\t\t\t\t*\t\t\t\t\n#011H T7  AB:001 DB:--\t2\t3\t\t\t\t\t\t\t\t\tH\t\t>\t\t\t\t\t>s0\t\t\tbus\t\t\t\t\t\t\t\t\t\t\t\t\t\n#012H T8  AB:001 DB:--\t2\t4\t\t\tY\t\t\t\t\t\trh\t\t>\t\t\t\talu\t>s0\t\tbus\t\tL\tSBCh\t\t\t\t*\t\t\t\t\t\tUSE_SP\t\n#013H T9  AB:001 DB:--\t3\t1\t\t\t\t\tWZ\t\t\tW\t\tW\t<h\tu\t\t\talu\t<\tres\t\t\tH\tSBC\t\t*\t*\t\tV\t\t*\t\t\tZERO_16BIT\t\n#014H T10 AB:001 DB:--\t3\t2\t\t\t\t\t\tHL\t\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#015H T11 AB:001 DB:--\t3\t3\t\t\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[9] : inc/dec ss\t\t\t6\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#002H T2  AB:000 DB:03  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\t\t\tr16\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tUSE_SP\t\n#005H T5  AB:000 DB:--\t1\t5\t\t\t\t\t\tr16\top3\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tUSE_SP\t\n#006H T6  AB:000 DB:--\t1\t6\t\t\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n// General Purpose Arithmetic and CPU Control Groups\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[77] : daa\t\t\t4\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\tA\t<\t\t\t\talu\t<\tres\t\t\tH\tADC\t\t*\t*\t\tP\t\t*\t\t\t?NF_SUB\t\n#002H T2  AB:000 DB:27  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\tF\t<\t\t\t\t<\t\t\t\t\t\t\t\t\t\t\t\t\t\tR\t\t?NF_HF\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\tAF\t\t>\t\t\t\t>\t>s0\t\tbus\tbus\t\t\t\t*\t*\tW2\t*\t*\t*\t\t\t\t\"Only for DAA, write HF2 flag\"\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\t\tY\t\t\t\t\t\t\t\td\t\t\talu\t>s0\t\tbus\t\tL\tADC\t\t*\t*\t*\t\t\t1\tW.daa\t\t\"DAA,?NF_SUB\"\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[81] : cpl\t\t\t4\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\tA\t<\t\t\t\talu\t<\tres\t\t\tH\tOR\t\t\t*\t\t\t1\t\t\t\tNEG_OP2\t\n#002H T2  AB:000 DB:2F  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\tF\t<\t\t\t\t<\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t?NF_HF\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\tAF\t\t>\t\t\t\t>\t>s0\t\tbus\tbus\t\t\t\t*\t*\t*\t*\t*\t*\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\t\tY\t\t\t\t\t\t\t\t\t\t\talu\t\t\t\t0\tL\tOR\t\t\t*\t*\t\t1\t\t\t\tNEG_OP2\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[82] : neg\t\t\t4\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T1  AB:001 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\tA\t<\t\t\t\talu\t<\tres\t\t\tH\tSUB\t\t*\t*\t\tV\t1\t*\t\t\t\t\n#006H T2  AB:001 DB:44  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\tF\t<\t\t\t\t<\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t?NF_HF_CF\t\n#007H T3  AB:001 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\tAF\t\t>\t\t\t\t>\t>s0\t\tbus\tbus\t\t\t\t*\t*\t*\t*\t*\t*\t\t\t\t\n#008H T4  AB:001 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\t\tY\t\t\t\t\t\t\t\t\t\t\talu\t\t\t\t0\tL\tSUB\t\t*\t*\t*\t\t1\t*\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[89] : ccf\t\t\t4\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\talu\t<\tres\t\t\tH\tOR\t\t\t*\t\t\t0\t\t\t\t\t\n#002H T2  AB:000 DB:3F  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\tF\t<\t\t\t\t<\t\t\t\t\t\t\t\t\t\t\t\t\t^\t\t\t?~CF_HF\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\tAF\t\t>\t\t\t\t>\t>s0\t\tbus\tbus\t\t\t\t*\t*\t*\t*\t*\t*\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\t\tY\t\t\t\t\t\t\t\t\t\t\talu\t\t\t\t\tL\tOR\t\t\t*\t*\t\t0\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[92] : scf\t\t\t4\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\talu\t<\tres\t\t\tH\tOR\t\t\t*\t\t\t0\t\t\t\t\t\n#002H T2  AB:000 DB:37  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\tF\t<\t\t\t\t<\t\t\t\t\t\t\t\t\t\t\t\t\t1\t\t\t\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\tAF\t\t>\t\t\t\t>\t>s0\t\tbus\tbus\t\t\t\t*\t*\t*\t*\t*\t*\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\t\tY\t\t\t\t\t\t\t\t\t\t\talu\t\t\t\t\tL\tOR\t\t\t*\t*\t\t0\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[95] : halt\t\t\t4\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#002H T2  AB:000 DB:76  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tHALT\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[97] : di/ei\t\t\t4\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#002H T2  AB:000 DB:F3  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tDI_EI\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tNO_INTS\t\"At last M/T, inhibit interrupts\"\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[96] : im n\t\t\t4\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T1  AB:001 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T2  AB:001 DB:46  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T3  AB:001 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tIM\tM1/T3 reads in mode # from opcode[4:3]\n#008H T4  AB:001 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n// Rotate and Shift Group\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[25] : rlca/rla/rrca/rra\t\t\t4\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\tA\t<\t\t\t\talu\t<\tres\t\t\tH\tOR\t\t\t*\t*\t\t0\t*\t\t\t\t\n#002H T2  AB:000 DB:07  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\tF\t<\t\t\t\t<\t\t\t\t\t\t\t\t\t\t\t\t\t\tR\t\t\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\tAF\t\t>\t\t\t\t>\t>s0\t\tbus\tbus\t\t\t\t*\t*\t*\t*\t*\t*\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\t\tY\t\t\t\t\tA\t\t>\t\t\t\talu\t>s1\t\tbus\tbus\tL\tOR\t\t\t*\t*\t\t0\t\tW.sh\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if ~use_ixiy & pla[70] & ~pla[55] : rlc r\t\t\t4\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T1  AB:001 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\tr8'\t<\tu\t\t\talu\t<\tres\t\t\tH\tOR\t\t*\t*\t*\tP\t0\t*\t\t\t\t\n#006H T2  AB:001 DB:00  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\tF\t<\t\t\t\t<\t\t\t\t\t\t\t\t\t\t\t\t\t\tR\t\t\t\n#007H T3  AB:001 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\tAF\t\t>\t\t\t\t>\t>s0\t\tbus\tbus\t\t\t\t*\t*\t*\t*\t*\t*\t\t\t\t\n#008H T4  AB:001 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\t\tY\t\t\t\t\tr8\t\t>r8\t-\t\t\talu\t>s1\t\tbus\tbus\tL\tOR\t\t*\t*\t*\t\t0\t\tW.sh\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#017H T13 AB:000 DB:--\t4\t1\tfMRead\t\t\t\tWZ\t\t\tW\t\t\t\t\t\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tOpcodeToIR\t...continues here from the (ix+d) addressing mode\n#018H T14 AB:000 DB:DD          MREQ RD\t4\t2\tfMRead\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#019H T15 AB:000 DB:DD          MREQ RD\t4\t3\tfMRead\t\tmw\t\t\t\t\t\t\t\t\td\t<\tR\talu\t>s1\t\tbus\tbus\tL\tOR\t\t\t\t\t\t0\t\tW.sh\t\t\t\n#029H T17 AB:002 DB:--\t5\t1\tfMWrite\t\t\t\t\t\t\tR\t\t\t\tu\t>\tW\talu\t<\tres\t\t\tH\tOR\t\t*\t*\t*\tP\t0\t*\t\t\t\t\n#030H T18 AB:002 DB:BB          MREQ\t5\t2\tfMWrite\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#031H T19 AB:002 DB:BB          MREQ    WR\t5\t3\tfMWrite\t\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if ~use_ixiy & pla[70] & pla[55] : rlc (hl)\t\t\t\"4,4,3\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T1  AB:001 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T2  AB:001 DB:00  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\tF\t<\t\t\t\t<\t\t\t\t\t\t\t\t\t\t\t\t\t\tR\t\t\t\n#007H T3  AB:001 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\tAF\t\t>\t\t\t\t>\t>s0\t\tbus\tbus\t\t\t\t*\t*\t*\t*\t*\t*\t\t\t\t\n#008H T4  AB:001 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#009H T5  AB:006 DB:--\t2\t1\tfMRead\t\t\t\tHL\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#010H T6  AB:006 DB:05          MREQ RD\t2\t2\tfMRead\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#011H T7  AB:006 DB:05          MREQ RD\t2\t3\tfMRead\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#012H T8  AB:006 DB:--\t2\t4\t\t\tmw\t\t\t\t\t\t\t\t\td\t<\tR\talu\t>s1\t\tbus\tbus\tL\tOR\t\t\t\t\t\t0\t\tW.sh\t\t\t\n#013H T9  AB:006 DB:--\t3\t1\tfMWrite\t\t\t\t\t\t\tR\t\t\t\tu\t>\tW\talu\t<\tres\t\t\tH\tOR\t\t*\t*\t*\tP\t0\t*\t\t\t\t\n#014H T10 AB:006 DB:0A          MREQ\t3\t2\tfMWrite\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#015H T11 AB:006 DB:0A          MREQ    WR\t3\t3\tfMWrite\t\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#017H T13 AB:000 DB:--\t4\t1\tfMRead\t\t\t\tWZ\t\t\tW\t\t\t\t\t\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tOpcodeToIR\t...continues here from the (ix+d) addressing mode\n#018H T14 AB:000 DB:DD          MREQ RD\t4\t2\tfMRead\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#019H T15 AB:000 DB:DD          MREQ RD\t4\t3\tfMRead\t\tmw\t\t\t\t\t\t\t\t\td\t<\tR\talu\t>s1\t\tbus\tbus\tL\tOR\t\t\t\t\t\t0\t\tW.sh\t\t\t\n#029H T17 AB:002 DB:--\t5\t1\tfMWrite\t\t\t\t\t\t\tR\t\t\t\tu\t>\tW\talu\t<\tres\t\t\tH\tOR\t\t*\t*\t*\tP\t0\t*\t\t\t\t\n#030H T18 AB:002 DB:BB          MREQ\t5\t2\tfMWrite\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#031H T19 AB:002 DB:BB          MREQ    WR\t5\t3\tfMWrite\t\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[15] & op3 : rld\t\t\t\"4,3,4,3\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T1  AB:001 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\tA\t<\t\t\t\talu\t<\tres\t\t\tH\tOR\t\t*\t*\t\tP\t0\t\t\t\t\t\n#006H T2  AB:001 DB:67  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\tF\t<\t\t\t\t<\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T3  AB:001 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\tAF\t\t>\t\t\t\t>\t>s0\t\tbus\tbus\t\t\t\t*\t*\t*\t*\t*\t*\t\t\t\t\n#008H T4  AB:001 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#009H T5  AB:000 DB:--\t2\t1\tfMRead\t\t\t\tHL\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#010H T6  AB:000 DB:ED          MREQ RD\t2\t2\tfMRead\t\t\t\t\tWZ\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#011H T7  AB:000 DB:ED          MREQ RD\t2\t3\tfMRead\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#012H T8  AB:000 DB:--\t3\t1\t\t\t\t\t\t\t\t\t\t\t\td\t<\tR\t\t>s0\t\tlq\t\tL\t\t\t\t\t\t\t\t\t\t\t\t\n#013H T9  AB:000 DB:--\t3\t2\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#014H T10 AB:000 DB:--\t3\t3\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#015H T11 AB:000 DB:--\t3\t4\t\t\tmw\t\t\t\t\t\t\t\t\td\t<\tR\t\t>s0\t\t\tlow\tH\t\t\t\t\t\t\t\t\t\t\t\t\n#016H T12 AB:000 DB:--\t4\t1\tfMWrite\t\t\t\t\t\t\tR\t\t\t\tu\t>\tW\t\t<\top2\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#017H T13 AB:000 DB:EE          MREQ\t4\t2\tfMWrite\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\top1\tbus\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#018H T14 AB:000 DB:EE          MREQ    WR\t4\t3\tfMWrite\t\t\tY\t\t\t\t\t\t\t\t\t\t\talu\t\t\t\t\tL\tOR\t\t*\t*\t*\t\t0\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[15] & ~op3 : rrd\t\t\t\"4,3,4,3\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T1  AB:001 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\tA\t<\t\t\t\talu\t<\tres\t\t\tH\tOR\t\t*\t*\t\tP\t0\t\t\t\t\t\n#006H T2  AB:001 DB:67  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\tF\t<\t\t\t\t<\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T3  AB:001 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\tAF\t\t>\t\t\t\t>\t>s0\t\tbus\tbus\t\t\t\t*\t*\t*\t*\t*\t*\t\t\t\t\n#008H T4  AB:001 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#009H T5  AB:000 DB:--\t2\t1\tfMRead\t\t\t\tHL\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#010H T6  AB:000 DB:ED          MREQ RD\t2\t2\tfMRead\t\t\t\t\tWZ\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#011H T7  AB:000 DB:ED          MREQ RD\t2\t3\tfMRead\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#012H T8  AB:000 DB:--\t3\t1\t\t\t\t\t\t\t\t\t\t\t\td\t<\tR\t\t>s0\t\tlq\tlow\tL\t\t\t\t\t\t\t\t\t\t\t\t\n#013H T9  AB:000 DB:--\t3\t2\t\t\t\t\t\t\t\t\t\t\t\tu\t>\tW\t\t<\top2\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#014H T10 AB:000 DB:--\t3\t3\t\t\t\t\t\t\t\t\tA\t\t>\t\t\t\t\t>s0\t\tlq\t\tL\t\t\t\t\t\t\t\t\t\t\t\t\n#015H T11 AB:000 DB:--\t3\t4\t\t\tmw\t\t\t\t\t\t\t\t\td\t<\tR\t\t>s0\t\t\tlow\tH\t\t\t\t\t\t\t\t\t\t\t\t\n#016H T12 AB:000 DB:--\t4\t1\tfMWrite\t\t\t\t\t\t\tR\t\t\t\tu\t>\tW\t\t<\top2\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#017H T13 AB:000 DB:EE          MREQ\t4\t2\tfMWrite\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\top1\tbus\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#018H T14 AB:000 DB:EE          MREQ    WR\t4\t3\tfMWrite\t\t\tY\t\t\t\t\t\t\t\t\t\t\talu\t\t\t\t\tL\tOR\t\t*\t*\t*\t\t0\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n// Bit Manipulation Group\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"#if ~use_ixiy & pla[72] & ~pla[55] : bit b,r\"\t\t\t4\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T1  AB:001 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\talu\t<\tres\t\t\tH\tAND\t\t*\t\t*\tP\t0\t\t\t\t\t\n#006H T2  AB:001 DB:40  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\tF\t<\t\t\t\t<\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T3  AB:001 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\tAF\t\t>\t\t\tR\t>\t>bs\t\tbus\tbus\t\t\t\t*\t*\t*\t*\t*\t*\t\t\t\tOverride M1/T3 load with a bit select\n#008H T4  AB:001 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\t\tY\t\t\t\t\tr8\t\t>r8\t-\t\t\talu\t>s0\t\t\tbus\tL\tAND\t\t*\t*\t*\t\t0\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#017H T13 AB:000 DB:--\t4\t1\tfMRead\t\t\t\t\t\t\tR\t\t\t\t\t\tR\t\t>bs\t\tbus\tbus\t\t\t\t\t\t\t\t\t\t\t\tOpcodeToIR\t...continues here from the (ix+d) addressing mode\n#018H T14 AB:000 DB:DD          MREQ RD\t4\t2\tfMRead\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#019H T15 AB:000 DB:DD          MREQ RD\t4\t3\tfMRead\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#020H T16 AB:000 DB:--\t4\t4\t\t\t\tY\t\t\t\t\t\t\t\td\t<\tR\talu\t>s0\t\t\tbus\tL\tAND\t\t*\t\t*\t\t0\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"#if ~use_ixiy & pla[72] & pla[55] : bit b,(hl)\"\t\t\t\"4,4\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T1  AB:001 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\talu\t<\tres\t\t\tH\tAND\t\t*\t\t*\tP\t0\t\t\t\t\t\n#006H T2  AB:001 DB:06  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\tF\t<\t\t\t\t<\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T3  AB:001 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\tAF\t\t>\t\t\tR\t>\t>bs\t\tbus\tbus\t\t\t\t*\t*\t*\t*\t*\t*\t\t\t\tOverride M1/T3 load with a bit select\n#008H T4  AB:001 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#009H T5  AB:006 DB:--\t2\t1\tfMRead\t\t\t\tHL\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#010H T6  AB:006 DB:05          MREQ RD\t2\t2\tfMRead\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#011H T7  AB:006 DB:05          MREQ RD\t2\t3\tfMRead\t\t\t\t\t\t\t\tWZ\t\t>\t\t\t\t>\t\t\t\t\t\t\t\t\t*\t\t\t\t\t\t\t\t\"BIT n,(HL) saves WZ in X,Y (\"\"MEMPTR\"\")\"\n#012H T8  AB:006 DB:--\t2\t4\t\t\t\tY\t\t\t\t\t\t\t\td\t<\tR\talu\t>s0\t\t\tbus\tL\tAND\t\t*\t\t*\t\t0\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#017H T13 AB:000 DB:--\t4\t1\tfMRead\t\t\t\tWZ\t\t\tW\t\t\t\t\t\tR\t\t>bs\t\tbus\tbus\t\t\t\t\t\t\t\t\t\t\t\tOpcodeToIR\t...continues here from the (ix+d) addressing mode\n#018H T14 AB:000 DB:DD          MREQ RD\t4\t2\tfMRead\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#019H T15 AB:000 DB:DD          MREQ RD\t4\t3\tfMRead\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#020H T16 AB:000 DB:--\t4\t4\t\t\t\tY\t\t\t\t\t\t\t\td\t<\tR\talu\t>s0\t\t\tbus\tL\tAND\t\t*\t\t*\t\t0\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"#if ~use_ixiy & pla[74] & ~pla[55] : set b,r\"\t\t\t4\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T1  AB:001 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\tr8'\t<\tu\t\t\t\t<\tres\t\t\tH\tOR\t\t\t\t\t\t\t\t\t\t\t\n#006H T2  AB:001 DB:40  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T3  AB:001 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\tAF\t\t>\t\t\tR\t>\t>bs\t\tbus\tbus\t\t\t\t*\t*\t*\t*\t*\t*\t\t\t\tOverride M1/T3 load with a bit select\n#008H T4  AB:001 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\t\tY\t\t\t\t\tr8\t\t>r8\t-\t\t\t\t>s0\t\t\tbus\tL\tOR\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#017H T13 AB:000 DB:--\t4\t1\tfMRead\t\t\t\tWZ\t\t\tW\t\t\t\t\t\tR\t\t>bs\t\tbus\tbus\t\t\t\t\t\t\t\t\t\t\t\tOpcodeToIR\t...continues here from the (ix+d) addressing mode\n#018H T14 AB:000 DB:DD          MREQ RD\t4\t2\tfMRead\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#019H T15 AB:000 DB:DD          MREQ RD\t4\t3\tfMRead\t\tmw\t\t\t\t\t\t\t\t\td\t<\tR\talu\t>s0\t\t\tbus\tL\tOR\t\t\t\t\t\t\t\t\t\t\t\n#029H T17 AB:002 DB:--\t5\t1\tfMWrite\t\t\t\t\t\t\tR\t\t\t\tu\t>\tW\t\t<\tres\t\t\tH\tOR\t\t\t\t\t\t\t\t\t\t\t\n#030H T18 AB:002 DB:BB          MREQ\t5\t2\tfMWrite\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#031H T19 AB:002 DB:BB          MREQ    WR\t5\t3\tfMWrite\t\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"#if ~use_ixiy & pla[74] & pla[55] : set b,(hl)\"\t\t\t\"4,4,3\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T1  AB:001 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T2  AB:001 DB:06  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T3  AB:001 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\tAF\t\t>\t\t\tR\t>\t>bs\t\tbus\tbus\t\t\t\t*\t*\t*\t*\t*\t*\t\t\t\tOverride M1/T3 load with a bit select\n#008H T4  AB:001 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#009H T5  AB:006 DB:--\t2\t1\tfMRead\t\t\t\tHL\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#010H T6  AB:006 DB:05          MREQ RD\t2\t2\tfMRead\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#011H T7  AB:006 DB:05          MREQ RD\t2\t3\tfMRead\t\t\t\t\t\t\t\t\t\t\td\t<\tR\t\t>s0\t\t\tbus\tL\tOR\t\t\t\t\t\t\t\t\t\t\t\n#012H T8  AB:006 DB:--\t2\t4\t\t\tmw\t\t\t\t\t\t\t\t\tu\t>\tW\t\t<\tres\t\t\tH\tOR\t\t\t\t\t\t\t\t\t\t\t\n#013H T9  AB:006 DB:--\t3\t1\tfMWrite\t\t\t\t\t\t\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#014H T10 AB:006 DB:0A          MREQ\t3\t2\tfMWrite\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#015H T11 AB:006 DB:0A          MREQ    WR\t3\t3\tfMWrite\t\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#017H T13 AB:000 DB:--\t4\t1\tfMRead\t\t\t\tWZ\t\t\tW\t\t\t\t\t\tR\t\t>bs\t\tbus\tbus\t\t\t\t\t\t\t\t\t\t\t\tOpcodeToIR\t...continues here from the (ix+d) addressing mode\n#018H T14 AB:000 DB:DD          MREQ RD\t4\t2\tfMRead\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#019H T15 AB:000 DB:DD          MREQ RD\t4\t3\tfMRead\t\tmw\t\t\t\t\t\t\t\t\td\t<\tR\talu\t>s0\t\t\tbus\tL\tOR\t\t\t\t\t\t\t\t\t\t\t\n#029H T17 AB:002 DB:--\t5\t1\tfMWrite\t\t\t\t\t\t\tR\t\t\t\tu\t>\tW\t\t<\tres\t\t\tH\tOR\t\t\t\t\t\t\t\t\t\t\t\n#030H T18 AB:002 DB:BB          MREQ\t5\t2\tfMWrite\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#031H T19 AB:002 DB:BB          MREQ    WR\t5\t3\tfMWrite\t\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"#if ~use_ixiy & pla[73] & ~pla[55] : res b,r\"\t\t\t4\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T1  AB:001 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\tr8'\t<\tu\t\t\t\t<\tres\t\t\tH\tNAND\t\t\t\t\t\t\t\t\t\t\t\n#006H T2  AB:001 DB:40  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T3  AB:001 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\tAF\t\t>\t\t\tR\t>\t>bs\t\tbus\tbus\t\t\t\t*\t*\t*\t*\t*\t*\t\t\t\tOverride M1/T3 load with a bit select\n#008H T4  AB:001 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\t\tY\t\t\t\t\tr8\t\t>r8\t-\t\t\t\t>s0\t\t\tbus\tL\tNAND\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#017H T13 AB:000 DB:--\t4\t1\tfMRead\t\t\t\tWZ\t\t\tW\t\t\t\t\t\tR\t\t>bs\t\tbus\tbus\t\t\t\t\t\t\t\t\t\t\t\tOpcodeToIR\t...continues here from the (ix+d) addressing mode\n#018H T14 AB:000 DB:DD          MREQ RD\t4\t2\tfMRead\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#019H T15 AB:000 DB:DD          MREQ RD\t4\t3\tfMRead\t\tmw\t\t\t\t\t\t\t\t\td\t<\tR\talu\t>s0\t\t\tbus\tL\tNAND\t\t\t\t\t\t\t\t\t\t\t\n#029H T17 AB:002 DB:--\t5\t1\tfMWrite\t\t\t\t\t\t\tR\t\t\t\tu\t>\tW\t\t<\tres\t\t\tH\tNAND\t\t\t\t\t\t\t\t\t\t\t\n#030H T18 AB:002 DB:BB          MREQ\t5\t2\tfMWrite\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#031H T19 AB:002 DB:BB          MREQ    WR\t5\t3\tfMWrite\t\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"#if ~use_ixiy & pla[73] & pla[55] : res b,(hl)\"\t\t\t\"4,4,3\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T1  AB:001 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T2  AB:001 DB:06  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T3  AB:001 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\tAF\t\t>\t\t\tR\t>\t>bs\t\tbus\tbus\t\t\t\t*\t*\t*\t*\t*\t*\t\t\t\tOverride M1/T3 load with a bit select\n#008H T4  AB:001 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#009H T5  AB:006 DB:--\t2\t1\tfMRead\t\t\t\tHL\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#010H T6  AB:006 DB:05          MREQ RD\t2\t2\tfMRead\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#011H T7  AB:006 DB:05          MREQ RD\t2\t3\tfMRead\t\t\t\t\t\t\t\t\t\t\td\t<\tR\t\t>s0\t\t\tbus\tL\tNAND\t\t\t\t\t\t\t\t\t\t\t\n#012H T8  AB:006 DB:--\t2\t4\t\t\tmw\t\t\t\t\t\t\t\t\tu\t>\tW\t\t<\tres\t\t\tH\tNAND\t\t\t\t\t\t\t\t\t\t\t\n#013H T9  AB:006 DB:--\t3\t1\tfMWrite\t\t\t\t\t\t\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#014H T10 AB:006 DB:0A          MREQ\t3\t2\tfMWrite\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#015H T11 AB:006 DB:0A          MREQ    WR\t3\t3\tfMWrite\t\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#017H T13 AB:000 DB:--\t4\t1\tfMRead\t\t\t\tWZ\t\t\tW\t\t\t\t\t\tR\t\t>bs\t\tbus\tbus\t\t\t\t\t\t\t\t\t\t\t\tOpcodeToIR\t...continues here from the (ix+d) addressing mode\n#018H T14 AB:000 DB:DD          MREQ RD\t4\t2\tfMRead\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#019H T15 AB:000 DB:DD          MREQ RD\t4\t3\tfMRead\t\tmw\t\t\t\t\t\t\t\t\td\t<\tR\talu\t>s0\t\t\tbus\tL\tNAND\t\t\t\t\t\t\t\t\t\t\t\n#029H T17 AB:002 DB:--\t5\t1\tfMWrite\t\t\t\t\t\t\tR\t\t\t\tu\t>\tW\t\t<\tres\t\t\tH\tNAND\t\t\t\t\t\t\t\t\t\t\t\n#030H T18 AB:002 DB:BB          MREQ\t5\t2\tfMWrite\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#031H T19 AB:002 DB:BB          MREQ    WR\t5\t3\tfMWrite\t\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n// Input and Output Groups\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"#if pla[37] & ~pla[28] : in a,(n)\"\t\t\t\"4,3,4\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\tA\t<\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#002H T2  AB:000 DB:DB  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T5  AB:001 DB:--\t2\t1\tfMRead\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T6  AB:001 DB:01          MREQ RD\t2\t2\tfMRead\t\t\t\t\tPC\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T7  AB:001 DB:01          MREQ RD\t2\t3\tfMRead\t\tior\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#008H T8  AB:001 DB:--\t3\t1\tfIORead\t\t\t\tA\t\t\tW\t\t?\t<\t\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#009H T9  AB:001 DB:--               RD    IORQ\t3\t2\tfIORead\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#010H T10 AB:001 DB:--               RD    IORQ\t3\t3\tfIORead\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#011H T11 AB:001 DB:--               RD    IORQ\t3\t4\tfIORead\t\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"#if pla[27] & ~pla[34] : in r,(c)\"\t\t\t\"4,4\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T1  AB:001 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\tr8\t<\td\t<\tR\talu\t\tres\t\t\tH\tOR\t\t*\t*\t\tP\t0\t\t\t\t\t\n#006H T2  AB:001 DB:40  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\tF\t<\t\t\t\t<\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T3  AB:001 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\tAF\t\t>\t\t\t\t>\t>s0\t\tbus\tbus\t\t\t\t*\t*\t*\t*\t*\t*\t\t\t\t\n#008H T4  AB:001 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tior\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#009H T5  AB:0FF DB:--\t2\t1\tfIORead\t\t\t\tBC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#010H T6  AB:0FF DB:--               RD    IORQ\t2\t2\tfIORead\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#011H T7  AB:0FF DB:--               RD    IORQ\t2\t3\tfIORead\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#012H T8  AB:0FF DB:--               RD    IORQ\t2\t4\tfIORead\t\t\tY\t\t\t\t\t\t\t\td\t<\tR\talu\t>s0\t\tbus\tbus\tL\tOR\t\t*\t*\t*\t\t0\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"#if pla[37] & pla[28] : out (n),a\"\t\t\t\"4,3,4\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#002H T2  AB:000 DB:D3  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T5  AB:001 DB:--\t2\t1\tfMRead\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T6  AB:001 DB:01          MREQ RD\t2\t2\tfMRead\t\t\t\t\tPC\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T7  AB:001 DB:01          MREQ RD\t2\t3\tfMRead\t\tiow\t\tA\t\t\tW\t\t\t<l\t\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#008H T8  AB:001 DB:--\t3\t1\tfIOWrite\t\t\t\t\t\t\tR\tA\t\t>h\tu\t>\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#009H T9  AB:001 DB:03                  WR IORQ\t3\t2\tfIOWrite\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#010H T10 AB:001 DB:03                  WR IORQ\t3\t3\tfIOWrite\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#011H T11 AB:001 DB:03                  WR IORQ\t3\t4\tfIOWrite\t\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"#if pla[27] & pla[34] : out (c),r\"\t\t\t\"4,4\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T1  AB:001 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T2  AB:001 DB:41  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T3  AB:001 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#008H T4  AB:001 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tiow\t\t\t\t\t\tr8'\t\t>r8'\t-\t>\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#009H T5  AB:0FF DB:--\t2\t1\tfIOWrite\t\t\t\tBC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#010H T6  AB:0FF DB:C3                  WR IORQ\t2\t2\tfIOWrite\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#011H T7  AB:0FF DB:C3                  WR IORQ\t2\t3\tfIOWrite\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#012H T8  AB:0FF DB:C3                  WR IORQ\t2\t4\tfIOWrite\t\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[91] & pla[21] : ini/inir/ind/indr\t\t\t\"5,4,3,(5)\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#035H T1  AB:00A DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\tres\t\t\tH\tXOR\t\t\t\t\tP\t\t\t\t\t\t\n#036H T2  AB:00A DB:B2  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\tF\t<\t\t\t\t<\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#037H T3  AB:004 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\tAF\t\t>\t\t\t\t>\t>s0\t\tbus\tbus\t\t\t\t*\t*\t*\t*\t*\t*\t\t\t\t\n#038H T4  AB:004 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#039H T5  AB:004 DB:--\t1\t5\t\t\tior\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#040H T6  AB:000 DB:--\t2\t1\tfIORead\t\t\t\tBC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#041H T7  AB:000 DB:--               RD    IORQ\t2\t2\tfIORead\t\t\t\t\t\t\t\tB\t\t>\t\t\t\talu\t>s0\t\t0\tbus\tL\tADD\t\t\t\t*\t\t\t\t\t\tNEG_OP2\t\n#042H T8  AB:000 DB:--               RD    IORQ\t2\t3\tfIORead\t\t\t\t\t\t\t\t\tB\t<\t\t\t\talu\t<\tres\t\t\tH\tADD\t\t*\t*\t\t\t\t*\t\t\tNEG_OP2\t\n#043H T9  AB:000 DB:--               RD    IORQ\t2\t4\tfIORead\t\tmw\t\t\t\t\t\t\t\t\td\t<\tR\talu\t>s0\t\t\tbus\t\t\t\t\t\t\t\tS\t\t\t\tNEG_OP2\t\n#044H T10 AB:000 DB:--\t3\t1\tfMWrite\t\t\t\tHL\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#045H T11 AB:000 DB:B1          MREQ\t3\t2\tfMWrite\t\t\t\t\tHL\top3\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#046H T12 AB:000 DB:B1          MREQ    WR\t3\t3\tfMWrite\t\tY\tBZ\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#047H T13 AB:000 DB:--\t4\t1\t\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#048H T14 AB:000 DB:--\t4\t2\t\t\t\t\t\tPC\t-\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#049H T15 AB:000 DB:--\t4\t3\t\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#050H T16 AB:000 DB:--\t4\t4\t\t\t\t\t\tPC\t-\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#051H T17 AB:000 DB:--\t4\t5\t\t\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[91] & pla[20] : outi/outir/outd/outdr\t\t\t\"5,4,3,(5)\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#035H T1  AB:00A DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\talu\t<\tres\t\t\tH\tXOR\t\t\t\t\tP\t\t\t\t\t\t\n#036H T2  AB:00A DB:B3  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\tF\t<\t\t\t\t<\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#037H T3  AB:004 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\tAF\t\t>\t\t\t\t>\t>s0\t\tbus\tbus\t\t\t\t*\t*\t*\t*\t*\t*\t\t\t\t\n#038H T4  AB:004 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\t\t\t\t\t\t\tB\t\t>\t\t\t\talu\t>s0\t\t0\tbus\tL\tADD\t\t\t\t*\t\t\t\t\t\tNEG_OP2\t\n#039H T5  AB:004 DB:--\t1\t5\t\t\tmr\t\t\t\t\t\t\tB\t<\t\t\t\talu\t<\tres\t\t\tH\tADD\t\t*\t*\t\t\t\t\t\t\tNEG_OP2\t\n#040H T6  AB:000 DB:--\t2\t1\tfMRead\t\t\t\tHL\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#041H T7  AB:000 DB:21          MREQ RD\t2\t2\tfMRead\t\t\t\t\tHL\top3\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#042H T8  AB:000 DB:21          MREQ RD\t2\t3\tfMRead\t\tiow\t\t\t\t\t\tL\t\t>l\td\t\t\t\t>s0\t\t\tbus\t\t\t\t\t\t\t\t\t\t\t\t\t\n#043H T9  AB:000 DB:--\t3\t1\tfIOWrite\t\t\t\tBC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#044H T10 AB:000 DB:21                  WR IORQ\t3\t2\tfIOWrite\t\t\t\t\t\t\t\t\t\t\td\t<\tR\talu\t>s0\t\tbus\t\tL\tADD\t\t\t\t*\t\tS\t\t\t\t\t\n#045H T11 AB:000 DB:21                  WR IORQ\t3\t3\tfIOWrite\t\t\t\t\t\t\t\t\t\t\t\t\t\talu\t<\tres\t\t\tH\tADD\t\t\t\t\t\t\t*\t\t\t\t\n#046H T12 AB:000 DB:21                  WR IORQ\t3\t4\tfIOWrite\t\tY\tBZ\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#047H T13 AB:000 DB:--\t4\t1\t\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#048H T14 AB:000 DB:--\t4\t2\t\t\t\t\t\tPC\t-\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#049H T15 AB:000 DB:--\t4\t3\t\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#050H T16 AB:000 DB:--\t4\t4\t\t\t\t\t\tPC\t-\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#051H T17 AB:000 DB:--\t4\t5\t\t\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n// Jump Group\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[29] : jp nn\t\t\t\"4,3,3\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#002H T2  AB:000 DB:C3  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T5  AB:001 DB:--\t2\t1\tfMRead\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T6  AB:001 DB:01          MREQ RD\t2\t2\tfMRead\t\t\t\t\tPC\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T7  AB:001 DB:01          MREQ RD\t2\t3\tfMRead\t\tmr\t\t\t\t\t\t\tZ\t<l\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#008H T8  AB:002 DB:--\t3\t1\tfMRead\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#009H T9  AB:002 DB:02          MREQ RD\t3\t2\tfMRead\t\t\t\t\tPC\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#010H T10 AB:002 DB:02          MREQ RD\t3\t3\tfMRead\t\t\tY\tWZ\t\t\tW\t\tW\t<h\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tNOT_PC!\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"#if pla[43] : jp cc,nn\"\t\t\t\"4,3,3\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#002H T2  AB:000 DB:C2  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\tAF\t\t>\t\t\t\t>\t>s0\t\tbus\tbus\t\t\t\t*\t*\t*\t*\t*\t*\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T5  AB:001 DB:--\t2\t1\tfMRead\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T6  AB:001 DB:01          MREQ RD\t2\t2\tfMRead\t\t\t\t\tPC\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T7  AB:001 DB:01          MREQ RD\t2\t3\tfMRead\t\tmr\t\t\t\t\t\t\tZ\t<l\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#008H T8  AB:002 DB:--\t3\t1\tfMRead\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#009H T9  AB:002 DB:02          MREQ RD\t3\t2\tfMRead\t\t\t\t\tPC\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#010H T10 AB:002 DB:02          MREQ RD\t3\t3\tfMRead\t\t\tY\tWZ?\t\t\tW\t\tW?\t<h\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tSelect WZ if condition is true\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[47] : jr e\t\t\t\"4,3,5\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#002H T2  AB:000 DB:18  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\tAF\t\t>\t\t\t\t>\t>s0\t\tbus\tbus\t\t\t\t*\t*\t*\t*\t*\t*\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T5  AB:001 DB:--\t2\t1\tfMRead\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T6  AB:001 DB:01          MREQ RD\t2\t2\tfMRead\t\t\t\t\tPC\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T7  AB:001 DB:01          MREQ RD\t2\t3\tfMRead\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#008H T8  AB:001 DB:--\t3\t1\t\t\t\t\t\t\t\t\t\t\t\td\t<\tR\talu\t>s0\t\tbus\t\t\t\t\t*\t\t\t\t\t\t\t\t\t\"Reads \"\"e\"\" from the data latch\"\n#009H T9  AB:001 DB:--\t3\t2\t\t\t\t\t\t\t\t\tPCl\t\t>l\td\t\t\talu\t>s0\t\t\tbus\tL\tADD\t\t\t\t*\t\t\t\t\t\t\t\n#010H T10 AB:001 DB:--\t3\t3\t\t\t\t\t\t\t\t\t\tZ\t<l\tu\t\t\talu\t<\tres\t\t\tH\tADD\t\t\t\t\t\t\t*\t\t\t\t\n#011H T11 AB:001 DB:--\t3\t4\t\t\t\t\t\t\t\t\tPCh\t\t>\t\t\t\talu\t>s0\t\t0\tbus\tL\tADC\t\t\t\t*\t\t\t\t\t\t?SF_NEG\t\n#012H T12 AB:001 DB:--\t3\t5\t\t\t\tY\tWZ\t\t\tW\t\tW\t<h\t\t\t\talu\t<\tres\t\t\tH\tADC\t\t\t\t\t\t\t\t\t\t\"?SF_NEG, NOT_PC!\"\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"#if pla[48] : jr ss,e\"\t\t\t\"4,3,(5)\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#002H T2  AB:000 DB:20  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\tAF\t\t>\t\t\t\t>\t>s0\t\tbus\tbus\t\t\t\t*\t*\t*\t*\t*\t*\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tCondShort\tM1/T4 evaluates a condition: force short\n#005H T5  AB:001 DB:--\t2\t1\tfMRead\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T6  AB:001 DB:01          MREQ RD\t2\t2\tfMRead\t\t\t\t\tPC\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T7  AB:001 DB:01          MREQ RD\t2\t3\tfMRead\t\tY\tSS\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#008H T8  AB:001 DB:--\t3\t1\t\t\t\t\t\t\t\t\t\t\t\td\t<\tR\talu\t>s0\t\tbus\t\t\t\t\t*\t\t\t\t\t\t\t\t\t\"Reads \"\"e\"\" from the data latch\"\n#009H T9  AB:001 DB:--\t3\t2\t\t\t\t\t\t\t\t\tPCl\t\t>l\td\t\t\talu\t>s0\t\t\tbus\tL\tADD\t\t\t\t*\t\t\t\t\t\t\t\n#010H T10 AB:001 DB:--\t3\t3\t\t\t\t\t\t\t\t\t\tZ\t<l\tu\t\t\talu\t<\tres\t\t\tH\tADD\t\t\t\t\t\t\t*\t\t\t\t\n#011H T11 AB:001 DB:--\t3\t4\t\t\t\t\t\t\t\t\tPCh\t\t>\t\t\t\talu\t>s0\t\t0\tbus\tL\tADC\t\t\t\t*\t\t\t\t\t\t?SF_NEG\t\n#012H T12 AB:001 DB:--\t3\t5\t\t\t\tY\tWZ\t\t\tW\t\tW\t<h\t\t\t\talu\t<\tres\t\t\tH\tADC\t\t\t\t\t\t\t\t\t\t\"?SF_NEG, NOT_PC!\"\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[6] : jp hl\t\t\t4\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#002H T2  AB:000 DB:E9  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\t\tY\tHL\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tNOT_PC!\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[26] : djnz e\t\t\t\"5,3,(5)\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#002H T2  AB:000 DB:10  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\tAF\t\t>\t\t\t\t>\t>s0\t\tbus\tbus\t\t\t\t*\t*\t*\t*\t*\t*\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\t\t\t\t\t\t\tB\t\t>h\t\t\t\talu\t>s0\t\t0\tbus\tL\tADD\t\t\t\t*\t\t\t\t\t\tNEG_OP2\tB=B-1\n#005H T5  AB:000 DB:--\t1\t5\t\t\tmr\t\t\t\t\t\t\tB\t<\t\t\t\talu\t<\tres\t\t\tH\tADD\t\t*\t\t\t\t\t\t\t\tNEG_OP2\t\n#006H T6  AB:001 DB:--\t2\t1\tfMRead\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T7  AB:001 DB:01          MREQ RD\t2\t2\tfMRead\t\t\t\t\tPC\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#008H T8  AB:001 DB:01          MREQ RD\t2\t3\tfMRead\t\tY\tZF\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#009H T9  AB:001 DB:--\t3\t1\t\t\t\t\t\t\t\t\t\t\t\td\t<\tR\talu\t>s0\t\tbus\t\t\t\t\t*\t\t\t\t\t\t\t\t\t\"Reads \"\"e\"\" from the data latch\"\n#010H T10 AB:001 DB:--\t3\t2\t\t\t\t\t\t\t\t\tPCl\t\t>l\td\t\t\talu\t>s0\t\t\tbus\tL\tADD\t\t\t\t*\t\t\t\t\t\t\t\n#011H T11 AB:001 DB:--\t3\t3\t\t\t\t\t\t\t\t\t\tZ\t<l\tu\t\t\talu\t<\tres\t\t\tH\tADD\t\t\t\t\t\t\t*\t\t\t\t\n#012H T12 AB:001 DB:--\t3\t4\t\t\t\t\t\t\t\t\tPCh\t\t>h\t\t\t\talu\t>s0\t\t0\tbus\tL\tADC\t\t\t\t*\t\t\t\t\t\t?SF_NEG\t\n#013H T13 AB:001 DB:--\t3\t5\t\t\t\tY\tWZ\t\t\tW\t\tW\t<h\t\t\t\talu\t<\tres\t\t\tH\tADC\t\t\t\t\t\t\t\t\t\t\"?SF_NEG, NOT_PC!\"\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n// Call and Return Group\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[24] : call nn\t\t\t\"4,3,4,3,3\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#002H T2  AB:000 DB:CD  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T5  AB:001 DB:--\t2\t1\tfMRead\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T6  AB:001 DB:01          MREQ RD\t2\t2\tfMRead\t\t\t\t\tPC\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T7  AB:001 DB:01          MREQ RD\t2\t3\tfMRead\t\tmr\t\t\t\t\t\t\tZ\t<l\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#008H T8  AB:002 DB:--\t3\t1\tfMRead\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#009H T9  AB:002 DB:02          MREQ RD\t3\t2\tfMRead\t\t\t\t\tPC\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#010H T10 AB:002 DB:02          MREQ RD\t3\t3\tfMRead\t\t\t\t\t\t\t\t\tW\t<h\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#011H T11 AB:002 DB:--\t3\t4\t\t\tmw\t\tSP\t\t-\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#012H T12 AB:000 DB:--\t4\t1\tfMWrite\t\t\t\t\t\t-\tP\tPCh\t\t>h\tu\t>\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#013H T13 AB:000 DB:00          MREQ\t4\t2\tfMWrite\t\t\t\t\tSP\t-\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#014H T14 AB:000 DB:00          MREQ    WR\t4\t3\tfMWrite\t\tmw\t\tSP\t\t-\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#015H T15 AB:0FF DB:--\t5\t1\tfMWrite\t\t\t\t\t\t-\tP\tPCl\t\t>l\t\t>\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#016H T16 AB:0FF DB:03          MREQ\t5\t2\tfMWrite\t\t\t\t\tSP\t-\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#017H T17 AB:0FF DB:03          MREQ    WR\t5\t3\tfMWrite\t\t\tY\tWZ\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tNOT_PC!\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"#if pla[42] : call cc,nn\"\t\t\t\"4,3,3/(4,3,4,3,3)\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#002H T2  AB:000 DB:C4  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\tAF\t\t>\t\t\t\t>\t>s0\t\tbus\tbus\t\t\t\t*\t*\t*\t*\t*\t*\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T5  AB:001 DB:--\t2\t1\tfMRead\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T6  AB:001 DB:01          MREQ RD\t2\t2\tfMRead\t\t\t\t\tPC\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T7  AB:001 DB:01          MREQ RD\t2\t3\tfMRead\t\tmr\t\t\t\t\t\t\tZ\t<l\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#008H T8  AB:002 DB:--\t3\t1\tfMRead\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#009H T9  AB:002 DB:02          MREQ RD\t3\t2\tfMRead\t\t\t\t\tPC\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#010H T10 AB:002 DB:02          MREQ RD\t3\t3\tfMRead\t\tCC\tCC\t\t\t\t\t\tW?\t<h\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tLoad W only if condition is true\n#011H T11 AB:002 DB:--\t3\t4\t\t\tmw\t\tSP\t\t-\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#012H T12 AB:000 DB:--\t4\t1\tfMWrite\t\t\t\t\t\t-\tP\tPCh\t\t>h\tu\t>\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#013H T13 AB:000 DB:00          MREQ\t4\t2\tfMWrite\t\t\t\t\tSP\t-\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#014H T14 AB:000 DB:00          MREQ    WR\t4\t3\tfMWrite\t\tmw\t\tSP\t\t-\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#015H T15 AB:0FF DB:--\t5\t1\tfMWrite\t\t\t\t\t\t-\tP\tPCl\t\t>l\t\t>\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#016H T16 AB:0FF DB:03          MREQ\t5\t2\tfMWrite\t\t\t\t\tSP\t-\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#017H T17 AB:0FF DB:03          MREQ    WR\t5\t3\tfMWrite\t\t\tY\tWZ\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tNOT_PC!\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[35] : ret\t\t\t\"4,3,3\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#002H T2  AB:000 DB:C9  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T5  AB:0FF DB:--\t2\t1\tfMRead\t\t\t\tSP\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T6  AB:0FF DB:01          MREQ RD\t2\t2\tfMRead\t\t\t\t\tSP\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T7  AB:0FF DB:01          MREQ RD\t2\t3\tfMRead\t\tmr\t\t\t\t\t\t\tZ\t<l\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#008H T8  AB:000 DB:--\t3\t1\tfMRead\t\t\t\tSP\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#009H T9  AB:000 DB:C9          MREQ RD\t3\t2\tfMRead\t\t\t\t\tSP\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#010H T10 AB:000 DB:C9          MREQ RD\t3\t3\tfMRead\t\t\tY\tWZ\t\t\tW\t\tW\t<h\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tNOT_PC!\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[45] : ret cc\t\t\t\"5/(5,3,3)\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#002H T2  AB:000 DB:C0  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\tAF\t\t>\t\t\t\t>\t>s0\t\tbus\tbus\t\t\t\t*\t*\t*\t*\t*\t*\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T5  AB:000 DB:--\t1\t5\t\t\tmr\tCC\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T6  AB:001 DB:--\t2\t1\tfMRead\t\t\t\tSP\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T7  AB:001 DB:01          MREQ RD\t2\t2\tfMRead\t\t\t\t\tSP\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#008H T8  AB:001 DB:01          MREQ RD\t2\t3\tfMRead\t\tmr\t\t\t\t\t\t\tZ\t<l\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#009H T9  AB:002 DB:--\t3\t1\tfMRead\t\t\t\tSP\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#010H T10 AB:002 DB:02          MREQ RD\t3\t2\tfMRead\t\t\t\t\tSP\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#011H T11 AB:002 DB:02          MREQ RD\t3\t3\tfMRead\t\t\tY\tWZ\t\t\tW\t\tW\t<h\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tNOT_PC!\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[46] : reti/retn\t\t\t\"4,3,3\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T1  AB:001 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T2  AB:001 DB:45  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T3  AB:001 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#008H T4  AB:001 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tRETN\tIFF1<=IFF2\n#009H T5  AB:001 DB:--\t2\t1\tfMRead\t\t\t\tSP\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#010H T6  AB:001 DB:45          MREQ RD\t2\t2\tfMRead\t\t\t\t\tSP\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#011H T7  AB:001 DB:45          MREQ RD\t2\t3\tfMRead\t\tmr\t\t\t\t\t\t\tZ\t<l\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#012H T8  AB:002 DB:--\t3\t1\tfMRead\t\t\t\tSP\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#013H T9  AB:002 DB:01          MREQ RD\t3\t2\tfMRead\t\t\t\t\tSP\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#014H T10 AB:002 DB:01          MREQ RD\t3\t3\tfMRead\t\t\tY\tWZ\t\t\tW\t\tW\t<h\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tNOT_PC!\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[56] : rst p\t\t\t\"5,3,3\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#002H T2  AB:000 DB:C7  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\t\tWZ\t<\t\t\tR\t\t<\top1\t\t0\t\t\t\t\t\t\t\t\t\t\t\t\"MASK_543, RST_NMI, RST_INT\"\tRST instruction also executes on NMI and INT\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T5  AB:000 DB:--\t1\t5\t\t\tmw\t\tSP\t\t-\tW\t\t\t\td\t<\tR\t\t>s0\t\t\tbus\t\t\t\t\t\t\t\t\t\t\t\t\tStore im2 vector into the ALU op1\n#006H T6  AB:000 DB:--\t2\t1\tfMWrite\t\t\t\t\t\t-\tP\tPCh\t\t>h\tu\t>\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T7  AB:000 DB:00          MREQ\t2\t2\tfMWrite\t\t\t\t\tSP\t-\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#008H T8  AB:000 DB:00          MREQ    WR\t2\t3\tfMWrite\t\tmw\t\tSP\t\t-\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#009H T9  AB:0FF DB:--\t3\t1\tfMWrite\t\t\t\t\t\t-\tP\tPCl\t\t>l\t\t>\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#010H T10 AB:0FF DB:01          MREQ\t3\t2\tfMWrite\t\t\t\t\tSP\t-\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#011H T11 AB:0FF DB:01          MREQ    WR\t3\t3\tfMWrite\t\tINT\tINT\tWZ\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tNOT_PC!\tValue on the bus into ALU OP\n// INTR IM2 continues here...\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tExtension for IM2 interrupt mode\n#012H T12 AB:001 DB:--\t4\t1\tfMRead\t\t\t\tI*\t\t\tW\t\t\t<l\tu\t\t\t\t<\top1\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#013H T13 AB:001 DB:01          MREQ RD\t4\t2\tfMRead\t\t\t\t\t>\t+\tR\t\t\t>l\td\t\t\t\t>s0\t\t\tbus\t\t\t\t\t\t\t\t\t\t\t\t\t\n#014H T14 AB:001 DB:01          MREQ RD\t4\t3\tfMRead\t\tmr\t\t\t\t\t\t\tZ\t<l\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#015H T15 AB:002 DB:--\t5\t1\tfMRead\t\t\t\tI*\t\t\tW\t\t\t<l\tu\t\t\t\t<\top1\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#016H T16 AB:002 DB:02          MREQ RD\t5\t2\tfMRead\t\t\t\t\t\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#017H T17 AB:002 DB:02          MREQ RD\t5\t3\tfMRead\t\t\tY\tWZ\t\t\tW\t\tW\t<h\td\t<\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tNOT_PC!\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n// CB-Table opcodes\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[49] : Every CB with IX/IY\t\t\t\"4,3,5,+\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#005H T1  AB:001 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#006H T2  AB:001 DB:CB  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#007H T3  AB:001 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\tAF\t\t>\t\t\t\t>\t>s0\t\tbus\tbus\t\t\t\t*\t*\t*\t*\t*\t*\t\t\tCB\t\n#008H T4  AB:001 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#009H T5  AB:002 DB:--\t2\t1\tfMRead\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#010H T6  AB:002 DB:01          MREQ RD\t2\t2\tfMRead\t\t\t\t\tPC\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#011H T7  AB:002 DB:01          MREQ RD\t2\t3\tfMRead\t\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#012H T8  AB:003 DB:--\t3\t1\tfMRead\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tWZ=IX+d\t\n#013H T9  AB:003 DB:00          MREQ RD\t3\t2\tfMRead\t\t\t\t\tPC\t+\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tWZ=IX+d\t\n#014H T10 AB:003 DB:00          MREQ RD\t3\t3\tfMRead\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tWZ=IX+d\tLoads the opcode byte in parallel\n#015H T11 AB:003 DB:--\t3\t4\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tWZ=IX+d\t\n#016H T12 AB:003 DB:--\t3\t5\t\t\tmr\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tWZ=IX+d\t\n#017H T13 AB:000 DB:--\t4\t1\t\t\t\t\t\t\t\t\t\t\t\t\t\tR\t\t>bs\t\tbus\tbus\t\t\t\t\t\t\t\t\t\t\t\tOpcodeToIR\tLoads instruction register; starts the execute cycle\n// Loading a new instruction immediately changes PLA wires and continues into the new effective instructions' M4/T1 cycle\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n// Special Purposes PLA Entries\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[3] : IX/IY\t\t\t4\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#002H T2  AB:000 DB:DD  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tIX_IY\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tNO_INTS\t\"At last M/T, inhibit interrupts\"\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[44] : CB prefix\t\t\t4\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#002H T2  AB:000 DB:CB  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tCB\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tNO_INTS\t\"At last M/T, inhibit interrupts\"\n\"#end Only set CB ff and clear ED, XX ff\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[51] : ED prefix\t\t\t4\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#002H T2  AB:000 DB:ED  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tED\t\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\tY\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tNO_INTS\t\"At last M/T, inhibit interrupts\"\n\"#end Only set ED ff and clear CB, XX ff\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[76] : ALU CP\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#always\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tCP\t\t\t\t\t\t1\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tV\t\t\t\t\t\tUpdate P/V once on a high nibble phase\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tDoes not store the result!\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[78] : ALU SUB\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#always\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tSUB\t\t\t\t\t\t1\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\tA\t<\t\t\t\t\t\t\t\t\t\t\t\t\t*\t\tV\t\t\t\t\t\tUpdate P/V and store result to A\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[79] : ALU SBC\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#always\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tSBC\t\t\t\t\t\t1\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\tA\t<\t\t\t\t\t\t\t\t\t\t\t\t\t*\t\tV\t\t\t\t\t\tUpdate P/V and store result to A\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[80] : ALU ADC\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#always\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tADC\t\t\t\t\t\t0\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\tA\t<\t\t\t\t\t\t\t\t\t\t\t\t\t*\t\tV\t\t\t\t\t\tUpdate P/V and store result to A\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[84] : ALU ADD\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#always\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tADD\t\t\t\t\t\t0\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\tA\t<\t\t\t\t\t\t\t\t\t\t\t\t\t*\t\tV\t\t\t\t\t\tUpdate P/V and store result to A\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[85] : ALU AND\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#always\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tAND\t\t\t\t\t\t0\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\tA\t<\t\t\t\t\t\t\t\t\t\t\t\t\t*\t\tP\t\t\t\t\t\tUpdate P/V and store result to A\n#002H T2  AB:000 DB:A0  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t0\t\t\t\tAND clears CF\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[86] : ALU OR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#always\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tOR\t\t\t\t\t\t0\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\tA\t<\t\t\t\t\t\t\t\t\t\t\t\t\t*\t\tP\t\t\t\t\t\tUpdate P/V and store result to A\n#002H T2  AB:000 DB:B0  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t0\t\t\t\tOR clears CF\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if pla[88] : ALU XOR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#always\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tXOR\t\t\t\t\t\t0\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\t\t\t\t\tA\t<\t\t\t\t\t\t\t\t\t\t\t\t\t*\t\tP\t\t\t\t\t\tUpdate P/V and store result to A\n#002H T2  AB:000 DB:A8  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t0\t\t\t\tXOR clears CF\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n// State machine to compute (IX+d)\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if ixy_d : Compute WZ=IX+d\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1 any M-cycle\t?\t1\t\t\t\t\t\t\t\t\t\t\t\td\t<\tR\talu\t>s0\t\tbus\t\t\t\t\t*\t\t\t\t\t\t\t\t\t\"Reads \"\"d\"\" from the data latch\"\n#002H T2\t?\t2\t\t\t\t\t\t\t\t\tL\t\t>l\td\t\t\talu\t>s0\t\t\tbus\tL\tADD\t\t\t\t*\t\t\t\t\t\t\t\n#003H T3\t?\t3\t\t\t\t\t\t\t\t\t\tZ\t<l\tu\t\t\talu\t<\tres\t\t\tH\tADC\t\t\t\t\t\t\t\tW\t\t\t\n#004H T4\t?\t4\t\t\t\t\t\t\t\t\tH\t\t>\t\t\t\talu\t>s0\t\t0\tbus\tL\tADC\t\t\t\t*\t\t\t\tR\t\t?SF_NEG\tStores result into WZ\n#005H T5\t?\t5\t\t\t\t\tWZ\t\t\tW\t\tW\t<h\t\t\t\talu\t<\tres\t\t\tH\tADC\t\t\t*\t\t\t\t\t\t\t\"?SF_NEG, CLR_IX_IY\"\tand disables any further use of IX/IY\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n// Default instruction fetch (M1) state machine\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if 1 :\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H T1  AB:000 DB:--  M1\t1\t1\tfMFetch\t\t\t\t\tPC\t+\tRL\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tFetch/execute overlap\n#002H T2  AB:000 DB:CB  M1      MREQ RD\t1\t2\tfMFetch\t\t\t\tIR\t\t\tW\t\t\t\t\t\tR\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\"CLR_IX_IY, CLR_CB_ED, OpcodeToIR, OverrideIR\"\tPrepares for the next execution cycle\n#003H T3  AB:000 DB:--     RFSH\t1\t3\tfMFetch\t\t\t\t\tIR\t+\tRL\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tLimit6\t\"Fetch opcode, evaluate flags\"\n#004H T4  AB:000 DB:--     RFSH MREQ\t1\t4\tfMFetch\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tEvalCond\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\"// For all undecoded instructions, at M1/T4 advance a byte to the next opcode\"\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if ~validPLA : A catch-all case\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#001H\t1\t4\t\t\t\tY\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n// The last cycle of an instruction is also the first cycle of the next one\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#if setM1 :\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n#always\t\t\t\t\t\t\tPC\t\t\tW\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tFetch/execute overlap\n#end\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n"
  },
  {
    "path": "cpu/control/clk_delay.bdf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  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  {
    "path": "cpu/control/clk_delay.bsf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"symbol\" (version \"1.2\"))\n(symbol\n\t(rect 16 16 216 208)\n\t(text \"clk_delay\" (rect 5 0 58 14)(font \"Arial\" (font_size 8)))\n\t(text \"inst\" (rect 8 176 25 188)(font \"Arial\" ))\n\t(port\n\t\t(pt 0 32)\n\t\t(input)\n\t\t(text \"in_intr\" (rect 0 0 34 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"in_intr\" (rect 21 27 55 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 32)(pt 16 32))\n\t)\n\t(port\n\t\t(pt 0 48)\n\t\t(input)\n\t\t(text \"M1\" (rect 0 0 16 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"M1\" (rect 21 43 37 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 48)(pt 16 48))\n\t)\n\t(port\n\t\t(pt 0 64)\n\t\t(input)\n\t\t(text \"T1\" (rect 0 0 14 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"T1\" (rect 21 59 35 73)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 64)(pt 16 64))\n\t)\n\t(port\n\t\t(pt 0 80)\n\t\t(input)\n\t\t(text \"clk\" (rect 0 0 15 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"clk\" (rect 21 75 36 89)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 80)(pt 16 80))\n\t)\n\t(port\n\t\t(pt 0 96)\n\t\t(input)\n\t\t(text \"mwait\" (rect 0 0 34 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"mwait\" (rect 21 91 55 105)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 96)(pt 16 96))\n\t)\n\t(port\n\t\t(pt 0 112)\n\t\t(input)\n\t\t(text \"latch_wait\" (rect 0 0 59 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"latch_wait\" (rect 21 107 80 121)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 112)(pt 16 112))\n\t)\n\t(port\n\t\t(pt 0 128)\n\t\t(input)\n\t\t(text \"busrq\" (rect 0 0 33 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"busrq\" (rect 21 123 54 137)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 128)(pt 16 128))\n\t)\n\t(port\n\t\t(pt 0 144)\n\t\t(input)\n\t\t(text \"nreset\" (rect 0 0 36 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"nreset\" (rect 21 139 57 153)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 144)(pt 16 144))\n\t)\n\t(port\n\t\t(pt 0 160)\n\t\t(input)\n\t\t(text \"setM1\" (rect 0 0 34 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"setM1\" (rect 21 155 55 169)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 160)(pt 16 160))\n\t)\n\t(port\n\t\t(pt 200 32)\n\t\t(output)\n\t\t(text \"hold_clk_iorq\" (rect 0 0 74 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"hold_clk_iorq\" (rect 105 27 179 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 200 32)(pt 184 32))\n\t)\n\t(port\n\t\t(pt 200 48)\n\t\t(output)\n\t\t(text \"iorq_Tw\" (rect 0 0 47 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"iorq_Tw\" (rect 132 43 179 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 200 48)(pt 184 48))\n\t)\n\t(port\n\t\t(pt 200 64)\n\t\t(output)\n\t\t(text \"nhold_clk_wait\" (rect 0 0 84 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"nhold_clk_wait\" (rect 95 59 179 73)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 200 64)(pt 184 64))\n\t)\n\t(port\n\t\t(pt 200 80)\n\t\t(output)\n\t\t(text \"hold_clk_wait\" (rect 0 0 77 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"hold_clk_wait\" (rect 102 75 179 89)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 200 80)(pt 184 80))\n\t)\n\t(port\n\t\t(pt 200 96)\n\t\t(output)\n\t\t(text \"busack\" (rect 0 0 41 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"busack\" (rect 138 91 179 105)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 200 96)(pt 184 96))\n\t)\n\t(port\n\t\t(pt 200 112)\n\t\t(output)\n\t\t(text \"hold_clk_busrq\" (rect 0 0 86 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"hold_clk_busrq\" (rect 93 107 179 121)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 200 112)(pt 184 112))\n\t)\n\t(port\n\t\t(pt 200 128)\n\t\t(output)\n\t\t(text \"pin_control_oe\" (rect 0 0 83 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"pin_control_oe\" (rect 96 123 179 137)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 200 128)(pt 184 128))\n\t)\n\t(drawing\n\t\t(rectangle (rect 16 16 184 176))\n\t)\n)\n"
  },
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    "path": "cpu/control/clk_delay.v",
    "content": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and other software and tools, and its AMPP partner logic \n// functions, and any output files from any of the foregoing \n// (including device programming or simulation files), and any \n// associated documentation or information are expressly subject \n// to the terms and conditions of the Altera Program License \n// Subscription Agreement, Altera MegaCore Function License \n// Agreement, or other applicable license agreement, including, \n// without limitation, that your use is for the sole purpose of \n// programming logic devices manufactured by Altera and sold by \n// Altera or its authorized distributors.  Please refer to the \n// applicable agreement for further details.\n\n// PROGRAM\t\t\"Quartus II 64-Bit\"\n// VERSION\t\t\"Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\"\n// CREATED\t\t\"Sat Dec 10 08:59:31 2016\"\n\nmodule clk_delay(\n\tclk,\n\tin_intr,\n\tnreset,\n\tT1,\n\tlatch_wait,\n\tmwait,\n\tM1,\n\tbusrq,\n\tsetM1,\n\thold_clk_iorq,\n\thold_clk_wait,\n\tiorq_Tw,\n\tbusack,\n\tpin_control_oe,\n\thold_clk_busrq,\n\tnhold_clk_wait\n);\n\n\ninput wire\tclk;\ninput wire\tin_intr;\ninput wire\tnreset;\ninput wire\tT1;\ninput wire\tlatch_wait;\ninput wire\tmwait;\ninput wire\tM1;\ninput wire\tbusrq;\ninput wire\tsetM1;\noutput wire\thold_clk_iorq;\noutput wire\thold_clk_wait;\noutput wire\tiorq_Tw;\noutput wire\tbusack;\noutput wire\tpin_control_oe;\noutput wire\thold_clk_busrq;\noutput wire\tnhold_clk_wait;\n\nreg\thold_clk_busrq_ALTERA_SYNTHESIZED;\nwire\tSYNTHESIZED_WIRE_6;\nwire\tSYNTHESIZED_WIRE_1;\nreg\tDFF_inst5;\nreg\tSYNTHESIZED_WIRE_7;\nreg\tSYNTHESIZED_WIRE_8;\nwire\tSYNTHESIZED_WIRE_3;\nwire\tSYNTHESIZED_WIRE_4;\nwire\tSYNTHESIZED_WIRE_5;\nreg\tSYNTHESIZED_WIRE_9;\n\nassign\thold_clk_wait = SYNTHESIZED_WIRE_9;\nassign\tiorq_Tw = DFF_inst5;\n\n\n\n\nalways@(posedge SYNTHESIZED_WIRE_6 or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tSYNTHESIZED_WIRE_9 <= 0;\n\tend\nelse\nif (SYNTHESIZED_WIRE_1)\n\tbegin\n\tSYNTHESIZED_WIRE_9 <= mwait;\n\tend\nend\n\n\nalways@(posedge SYNTHESIZED_WIRE_6 or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tSYNTHESIZED_WIRE_8 <= 0;\n\tend\nelse\n\tbegin\n\tSYNTHESIZED_WIRE_8 <= busrq;\n\tend\nend\n\nassign\thold_clk_iorq = DFF_inst5 | SYNTHESIZED_WIRE_7;\n\nassign\tbusack = SYNTHESIZED_WIRE_8 & hold_clk_busrq_ALTERA_SYNTHESIZED;\n\nassign\tpin_control_oe = SYNTHESIZED_WIRE_3 & nreset;\n\nassign\tSYNTHESIZED_WIRE_5 = hold_clk_busrq_ALTERA_SYNTHESIZED | setM1;\n\nassign\tSYNTHESIZED_WIRE_3 =  ~hold_clk_busrq_ALTERA_SYNTHESIZED;\n\n\nalways@(posedge clk or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tSYNTHESIZED_WIRE_7 <= 0;\n\tend\nelse\n\tbegin\n\tSYNTHESIZED_WIRE_7 <= SYNTHESIZED_WIRE_4;\n\tend\nend\n\n\nalways@(posedge clk or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\thold_clk_busrq_ALTERA_SYNTHESIZED <= 0;\n\tend\nelse\nif (SYNTHESIZED_WIRE_5)\n\tbegin\n\thold_clk_busrq_ALTERA_SYNTHESIZED <= SYNTHESIZED_WIRE_8;\n\tend\nend\n\n\nalways@(posedge clk or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tDFF_inst5 <= 0;\n\tend\nelse\n\tbegin\n\tDFF_inst5 <= SYNTHESIZED_WIRE_7;\n\tend\nend\n\nassign\tSYNTHESIZED_WIRE_4 = in_intr & M1 & T1;\n\nassign\tSYNTHESIZED_WIRE_1 = latch_wait | SYNTHESIZED_WIRE_9;\n\nassign\tnhold_clk_wait =  ~SYNTHESIZED_WIRE_9;\n\nassign\tSYNTHESIZED_WIRE_6 =  ~clk;\n\nassign\thold_clk_busrq = hold_clk_busrq_ALTERA_SYNTHESIZED;\n\nendmodule\n"
  },
  {
    "path": "cpu/control/decode_state.bdf",
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    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  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  {
    "path": "cpu/control/decode_state.v",
    "content": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and other software and tools, and its AMPP partner logic \n// functions, and any output files from any of the foregoing \n// (including device programming or simulation files), and any \n// associated documentation or information are expressly subject \n// to the terms and conditions of the Altera Program License \n// Subscription Agreement, Altera MegaCore Function License \n// Agreement, or other applicable license agreement, including, \n// without limitation, that your use is for the sole purpose of \n// programming logic devices manufactured by Altera and sold by \n// Altera or its authorized distributors.  Please refer to the \n// applicable agreement for further details.\n\n// PROGRAM\t\t\"Quartus II 64-Bit\"\n// VERSION\t\t\"Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\"\n// CREATED\t\t\"Sat Dec 10 08:55:35 2016\"\n\nmodule decode_state(\n\tctl_state_iy_set,\n\tctl_state_ixiy_clr,\n\tctl_state_ixiy_we,\n\tctl_state_halt_set,\n\tctl_state_tbl_ed_set,\n\tctl_state_tbl_cb_set,\n\tctl_state_alu,\n\tclk,\n\taddress_is_1,\n\tctl_repeat_we,\n\tin_intr,\n\tin_nmi,\n\tnreset,\n\tctl_state_tbl_we,\n\tnhold_clk_wait,\n\tin_halt,\n\ttable_cb,\n\ttable_ed,\n\ttable_xx,\n\tuse_ix,\n\tuse_ixiy,\n\tin_alu,\n\trepeat_en\n);\n\n\ninput wire\tctl_state_iy_set;\ninput wire\tctl_state_ixiy_clr;\ninput wire\tctl_state_ixiy_we;\ninput wire\tctl_state_halt_set;\ninput wire\tctl_state_tbl_ed_set;\ninput wire\tctl_state_tbl_cb_set;\ninput wire\tctl_state_alu;\ninput wire\tclk;\ninput wire\taddress_is_1;\ninput wire\tctl_repeat_we;\ninput wire\tin_intr;\ninput wire\tin_nmi;\ninput wire\tnreset;\ninput wire\tctl_state_tbl_we;\ninput wire\tnhold_clk_wait;\noutput reg\tin_halt;\noutput wire\ttable_cb;\noutput wire\ttable_ed;\noutput wire\ttable_xx;\noutput wire\tuse_ix;\noutput wire\tuse_ixiy;\noutput wire\tin_alu;\noutput wire\trepeat_en;\n\nreg\tDFFE_instNonRep;\nreg\tDFFE_instIY1;\nreg\tDFFE_inst4;\nreg\tDFFE_instED;\nreg\tDFFE_instCB;\nwire\tSYNTHESIZED_WIRE_0;\nwire\tSYNTHESIZED_WIRE_4;\nwire\tSYNTHESIZED_WIRE_3;\n\nassign\tin_alu = ctl_state_alu;\nassign\ttable_cb = DFFE_instCB;\nassign\ttable_ed = DFFE_instED;\nassign\tuse_ix = DFFE_inst4;\n\n\n\nassign\trepeat_en =  ~DFFE_instNonRep;\n\nassign\tuse_ixiy = DFFE_instIY1 | DFFE_inst4;\n\nassign\ttable_xx = ~(DFFE_instED | DFFE_instCB);\n\n\nalways@(posedge clk or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tDFFE_inst4 <= 0;\n\tend\nelse\nif (ctl_state_ixiy_we)\n\tbegin\n\tDFFE_inst4 <= SYNTHESIZED_WIRE_0;\n\tend\nend\n\nassign\tSYNTHESIZED_WIRE_0 = ~(ctl_state_iy_set | ctl_state_ixiy_clr);\n\nassign\tSYNTHESIZED_WIRE_4 = ctl_state_tbl_we & nhold_clk_wait;\n\nassign\tSYNTHESIZED_WIRE_3 = in_nmi | in_intr;\n\n\nalways@(posedge clk or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tDFFE_instCB <= 0;\n\tend\nelse\nif (SYNTHESIZED_WIRE_4)\n\tbegin\n\tDFFE_instCB <= ctl_state_tbl_cb_set;\n\tend\nend\n\n\nalways@(posedge clk or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tDFFE_instED <= 0;\n\tend\nelse\nif (SYNTHESIZED_WIRE_4)\n\tbegin\n\tDFFE_instED <= ctl_state_tbl_ed_set;\n\tend\nend\n\n\nalways@(posedge clk or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tin_halt <= 0;\n\tend\nelse\n\tbegin\n\tin_halt <= ~in_halt & ctl_state_halt_set | in_halt & ~SYNTHESIZED_WIRE_3;\n\tend\nend\n\n\nalways@(posedge clk or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tDFFE_instIY1 <= 0;\n\tend\nelse\nif (ctl_state_ixiy_we)\n\tbegin\n\tDFFE_instIY1 <= ctl_state_iy_set;\n\tend\nend\n\n\nalways@(posedge clk or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tDFFE_instNonRep <= 0;\n\tend\nelse\nif (ctl_repeat_we)\n\tbegin\n\tDFFE_instNonRep <= address_is_1;\n\tend\nend\n\n\nendmodule\n"
  },
  {
    "path": "cpu/control/exec_matrix.vh",
    "content": "// Automatically generated by genmatrix.py\n\n// 8-bit Load Group\nif (pla[17] & ~pla[50]) begin\n    if (M1 & T1) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; /* Write 8-bit GP register */\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M2 & T3) begin fMRead=1; setM1=1; end\nend\n\nif (pla[61] & ~pla[58] & ~pla[59]) begin\n    if (M1 & T1) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; /* Write 8-bit GP register */\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_sw_2u=1;\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_op1_oe=1; /* OP1 latch */ end\n    if (M1 & T4) begin validPLA=1; setM1=1;\n                    ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */\n                    ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; /* Enable register gate based on the rsel0 */ /* Controlled by register gate */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */ end\nend\n\nif (use_ixiy & pla[58]) begin\n    if (M1 & T1) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; /* Write 8-bit GP register */\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M2 & T3) begin fMRead=1; nextM=1; end\n    if (M3 & T1) begin ixy_d=1; /* Compute WZ=IX+d */ end\n    if (M3 & T2) begin ixy_d=1; /* Compute WZ=IX+d */ end\n    if (M3 & T3) begin ixy_d=1; /* Compute WZ=IX+d */ end\n    if (M3 & T4) begin ixy_d=1; /* Compute WZ=IX+d */ end\n    if (M3 & T5) begin nextM=1; ctl_mRead=1; ixy_d=1; /* Compute WZ=IX+d */ end\nend\n\nif (~use_ixiy & pla[58]) begin\n    if (M1 & T1) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; /* Write 8-bit GP register */\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMRead=1; end\n    if (M2 & T3) begin fMRead=1; setM1=1; end\n    if (M4 & T1) begin fMRead=1;\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M4 & T2) begin fMRead=1; end\n    if (M4 & T3) begin fMRead=1; setM1=1; end\nend\n\nif (use_ixiy & pla[59]) begin\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M2 & T3) begin fMRead=1; nextM=1; end\n    if (M3 & T1) begin ixy_d=1; /* Compute WZ=IX+d */ end\n    if (M3 & T2) begin ixy_d=1; /* Compute WZ=IX+d */ end\n    if (M3 & T3) begin ixy_d=1; /* Compute WZ=IX+d */ end\n    if (M3 & T4) begin ixy_d=1; /* Compute WZ=IX+d */ end\n    if (M3 & T5) begin nextM=1; ctl_mWrite=1; ixy_d=1; /* Compute WZ=IX+d */ end\nend\n\nif (~use_ixiy & pla[59]) begin\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mWrite=1;\n                    ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */\n                    ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; /* Enable register gate based on the rsel0 */ /* Controlled by register gate */\n                    ctl_sw_1u=1;\n                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end\n    if (M2 & T1) begin fMWrite=1;\n                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMWrite=1; end\n    if (M2 & T3) begin fMWrite=1; setM1=1; end\n    if (M4 & T1) begin fMWrite=1;\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */\n                    ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */\n                    ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; /* Enable register gate based on the rsel0 */ /* Controlled by register gate */\n                    ctl_sw_1u=1;\n                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end\n    if (M4 & T2) begin fMWrite=1; end\n    if (M4 & T3) begin fMWrite=1; setM1=1; end\nend\n\nif (pla[40]) begin\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1; end\n    if (M3 & T1) begin fMRead=1;\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ ixy_d=1; /* Compute WZ=IX+d */ end\n    if (M3 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ ixy_d=1; /* Compute WZ=IX+d */ end\n    if (M3 & T3) begin fMRead=1; ixy_d=1; /* Compute WZ=IX+d */ end\n    if (M3 & T4) begin ixy_d=1; /* Compute WZ=IX+d */ end\n    if (M3 & T5) begin nextM=1; ctl_mWrite=1; ixy_d=1; /* Compute WZ=IX+d */ end\nend\n\nif (pla[50] & ~pla[40]) begin\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1; end\n    if (M3 & T1) begin fMWrite=1;\n                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M3 & T2) begin fMWrite=1; end\n    if (M3 & T3) begin fMWrite=1; setM1=1; end\n    if (M4 & T1) begin fMWrite=1;\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M4 & T2) begin fMWrite=1; end\n    if (M4 & T3) begin fMWrite=1; setM1=1; end\nend\n\nif (pla[8] & pla[13]) begin\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mWrite=1;\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;\n                    ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */\n                    ctl_sw_2u=1;\n                    ctl_sw_1u=1;\n                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end\n    if (M2 & T1) begin fMWrite=1;\n                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit general purpose register, enable SW4 downstream */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMWrite=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M2 & T3) begin fMWrite=1; setM1=1; end\nend\n\nif (pla[8] & ~pla[13]) begin\n    if (M1 & T1) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit general purpose register, enable SW4 downstream */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M2 & T3) begin fMRead=1; setM1=1; end\nend\n\nif (pla[38] & pla[13]) begin\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;\n                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */\n                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end\n    if (M3 & T1) begin fMRead=1;\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M3 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M3 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1;\n                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */\n                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */\n                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end\n    if (M4 & T1) begin fMWrite=1;\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;\n                    ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */\n                    ctl_sw_2u=1;\n                    ctl_sw_1u=1;\n                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end\n    if (M4 & T2) begin fMWrite=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M4 & T3) begin fMWrite=1; setM1=1; end\nend\n\nif (pla[38] & ~pla[13]) begin\n    if (M1 & T1) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;\n                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */\n                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end\n    if (M3 & T1) begin fMRead=1;\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M3 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M3 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;\n                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */\n                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end\n    if (M4 & T1) begin fMRead=1;\n                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M4 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M4 & T3) begin fMRead=1; setM1=1; end\nend\n\nif (pla[83]) begin\n    if (M1 & T1) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_IFF2;\n                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end\n    if (M1 & T2) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end\n    if (M1 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_bus=1; /* Load FLAGT from the data bus */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1;\n                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */\n                    ctl_flags_cf_we=1; end\n    if (M1 & T4) begin validPLA=1;\n                    ctl_reg_sel_ir=1; ctl_reg_sys_hilo={~op3,op3}; ctl_sw_4u=1; /* Read either I or R based on op3 (0 or 1) */\n                    ctl_reg_out_hi=~rsel3; ctl_reg_out_lo=rsel3; ctl_sw_2u=~rsel3; ctl_sw_2d=rsel3; /* Enable register gate based on the rsel3 */ /* Controlled by register gate */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end\n    if (M1 & T5) begin setM1=1; end\nend\n\nif (pla[57]) begin\n    if (M1 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_bus=1; /* Load FLAGT from the data bus */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1;\n                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */\n                    ctl_flags_cf_we=1; end\n    if (M1 & T4) begin validPLA=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_ir=1; ctl_reg_sys_hilo={~op3,op3}; ctl_sw_4d=1; /* Write either I or R based on op3 (0 or 1) */\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_sw_2u=1;\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_op1_oe=1; /* OP1 latch */ end\n    if (M1 & T5) begin setM1=1; end\nend\n\n// 16-bit Load Group\nif (pla[7]) begin\n    if (M1 & T1) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Write 8-bit GP register high byte */\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1; end\n    if (M3 & T1) begin fMRead=1;\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Write 8-bit GP register low byte */\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end\n    if (M3 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M3 & T3) begin fMRead=1; setM1=1; end\nend\n\nif (pla[30] & pla[13]) begin\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;\n                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */\n                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end\n    if (M3 & T1) begin fMRead=1;\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M3 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M3 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1;\n                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */\n                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */\n                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end\n    if (M4 & T1) begin fMWrite=1;\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */\n                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */\n                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */\n                    ctl_sw_1u=1;\n                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end\n    if (M4 & T2) begin fMWrite=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M4 & T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;\n                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M5 & T1) begin fMWrite=1;\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */\n                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */\n                    ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */\n                    ctl_sw_2u=1;\n                    ctl_sw_1u=1;\n                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end\n    if (M5 & T2) begin fMWrite=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M5 & T3) begin fMWrite=1; setM1=1; end\nend\n\nif (pla[30] & ~pla[13]) begin\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;\n                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */\n                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end\n    if (M3 & T1) begin fMRead=1;\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M3 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M3 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;\n                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */\n                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end\n    if (M4 & T1) begin fMRead=1;\n                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M4 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M4 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Write 8-bit GP register low byte */\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end\n    if (M5 & T1) begin fMRead=1;\n                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M5 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M5 & T3) begin fMRead=1; setM1=1;\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Write 8-bit GP register high byte */\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end\nend\n\nif (pla[31] & pla[33]) begin\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;\n                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */\n                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end\n    if (M3 & T1) begin fMRead=1;\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M3 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M3 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1;\n                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */\n                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */\n                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end\n    if (M4 & T1) begin fMWrite=1;\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */\n                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */\n                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */\n                    ctl_sw_1u=1;\n                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */\n                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end\n    if (M4 & T2) begin fMWrite=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M4 & T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;\n                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M5 & T1) begin fMWrite=1;\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */\n                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */\n                    ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */\n                    ctl_sw_2u=1;\n                    ctl_sw_1u=1;\n                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */\n                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end\n    if (M5 & T2) begin fMWrite=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M5 & T3) begin fMWrite=1; setM1=1; end\nend\n\nif (pla[31] & ~pla[33]) begin\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;\n                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */\n                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end\n    if (M3 & T1) begin fMRead=1;\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M3 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M3 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;\n                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */\n                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end\n    if (M4 & T1) begin fMRead=1;\n                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M4 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M4 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Write 8-bit GP register low byte */\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end\n    if (M5 & T1) begin fMRead=1;\n                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M5 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M5 & T3) begin fMRead=1; setM1=1;\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Write 8-bit GP register high byte */\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end\nend\n\nif (pla[5]) begin\n    if (M1 & T4) begin validPLA=1;\n                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M1 & T5) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M1 & T6) begin setM1=1; end\nend\n\nif (pla[23] & pla[16]) begin\n    if (M1 & T4) begin validPLA=1; end\n    if (M1 & T5) begin nextM=1; ctl_mWrite=1;\n                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T1) begin fMWrite=1;\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */\n                    ctl_apin_mux=1; /* Apin sourced from incrementer */\n                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */\n                    ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */\n                    ctl_sw_2u=1;\n                    ctl_sw_1u=1;\n                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end\n    if (M2 & T2) begin fMWrite=1;\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M2 & T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;\n                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M3 & T1) begin fMWrite=1;\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */\n                    ctl_apin_mux=1; /* Apin sourced from incrementer */\n                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */\n                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */\n                    ctl_sw_1u=1;\n                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end\n    if (M3 & T2) begin fMWrite=1;\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M3 & T3) begin fMWrite=1; setM1=1; end\nend\n\nif (pla[23] & ~pla[16]) begin\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMRead=1;\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Write 8-bit GP register low byte */\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end\n    if (M3 & T1) begin fMRead=1;\n                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M3 & T2) begin fMRead=1;\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M3 & T3) begin fMRead=1; setM1=1;\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Write 8-bit GP register high byte */\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end\nend\n\n// Exchange, Block Transfer and Search Groups\nif (pla[2]) begin\n    if (M1 & T2) begin\n                    ctl_reg_ex_de_hl=1; /* EX DE,HL */ end\n    if (M1 & T4) begin validPLA=1; setM1=1; end\nend\n\nif (pla[39]) begin\n    if (M1 & T2) begin\n                    ctl_reg_ex_af=1; /* EX AF,AF' */ end\n    if (M1 & T4) begin validPLA=1; setM1=1; end\nend\n\nif (pla[1]) begin\n    if (M1 & T2) begin\n                    ctl_reg_exx=1; /* EXX */ end\n    if (M1 & T4) begin validPLA=1; setM1=1; end\nend\n\nif (pla[10]) begin\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMRead=1;\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;\n                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */\n                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end\n    if (M3 & T1) begin fMRead=1;\n                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M3 & T2) begin fMRead=1;\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M3 & T3) begin fMRead=1;\n                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */\n                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end\n    if (M3 & T4) begin nextM=1; ctl_mWrite=1;\n                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M4 & T1) begin fMWrite=1;\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */\n                    ctl_apin_mux=1; /* Apin sourced from incrementer */\n                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */\n                    ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */\n                    ctl_sw_2u=1;\n                    ctl_sw_1u=1;\n                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end\n    if (M4 & T2) begin fMWrite=1;\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M4 & T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;\n                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M5 & T1) begin fMWrite=1;\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */\n                    ctl_apin_mux=1; /* Apin sourced from incrementer */\n                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */\n                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */\n                    ctl_sw_1u=1;\n                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end\n    if (M5 & T2) begin fMWrite=1;\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M5 & T3) begin fMWrite=1;\n                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M5 & T4) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M5 & T5) begin setM1=1; end\nend\n\nif (pla[0]) begin\n    begin nonRep=1; /* Non-repeating block instruction */ end\nend\n\nif (pla[12]) begin\n    if (M1 & T1) begin\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_REP;\n                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;\n                    ctl_flags_use_cf2=1; end\n    if (M1 & T2) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end\n    if (M1 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_bus=1; /* Load FLAGT from the data bus */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1;\n                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */\n                    ctl_flags_cf_we=1; end\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMRead=1;\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1;\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_cf2_we=1; end\n    if (M3 & T1) begin fMWrite=1;\n                    ctl_reg_gp_sel=`GP_REG_DE; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit DE, enable SW4 downstream */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_use_cf2=1; end\n    if (M3 & T2) begin fMWrite=1;\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_DE; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit BC, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M3 & T3) begin fMWrite=1;\n                    ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M3 & T4) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit BC, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */\n                    ctl_repeat_we=1; /* Update repeating flag latch with BC=1 status */ end\n    if (M3 & T5) begin nextM=1; setM1=nonRep | ~repeat_en; end\n    if (M4 & T1) begin\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M4 & T2) begin\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M4 & T3) begin\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M4 & T4) begin\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M4 & T5) begin setM1=1; end\nend\n\nif (pla[11]) begin\n    if (M1 & T1) begin\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_op1_sel_zero=1; /* Zero */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_sel_op2_neg=1; ctl_flags_cf_set|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_REP;\n                    ctl_flags_nf_we=1; ctl_flags_nf_set=1;\n                    ctl_flags_use_cf2=1; end\n    if (M1 & T2) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */\n                    ctl_flags_hf_cpl=flags_nf; end\n    if (M1 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_bus=1; /* Load FLAGT from the data bus */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1;\n                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */\n                    ctl_flags_cf_we=1; end\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMRead=1;\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M2 & T3) begin fMRead=1; nextM=1;\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_alu_sel_op2_neg=1; ctl_flags_cf_set|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_cf2_we=1; end\n    if (M3 & T1) begin\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_sel_op2_neg=1; ctl_flags_cf_set|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_sz_we=1;\n                    ctl_flags_use_cf2=1; end\n    if (M3 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M3 & T4) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit BC, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */\n                    ctl_repeat_we=1; /* Update repeating flag latch with BC=1 status */ end\n    if (M3 & T5) begin nextM=1; setM1=nonRep | ~repeat_en | flags_zf; end\n    if (M4 & T1) begin\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M4 & T2) begin\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M4 & T3) begin\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M4 & T4) begin\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M4 & T5) begin setM1=1; end\nend\n\n// 8-bit Arithmetic and Logic Group\nif (pla[65] & ~pla[52]) begin\n    if (M1 & T1) begin /* Which register to be written is decided elsewhere */\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_sw_2u=1;\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_cf_we=1; end\n    if (M1 & T2) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */\n                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */\n                    ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end\n    if (M1 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_bus=1; /* Load FLAGT from the data bus */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1;\n                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */\n                    ctl_flags_cf_we=1; end\n    if (M1 & T4) begin validPLA=1; setM1=1;\n                    ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */\n                    ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; /* Enable register gate based on the rsel0 */ /* Controlled by register gate */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1; end\nend\n\nif (pla[64]) begin\n    if (M1 & T1) begin /* Which register to be written is decided elsewhere */\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_sw_2u=1;\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_cf_we=1; end\n    if (M1 & T2) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */\n                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */\n                    ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end\n    if (M1 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_bus=1; /* Load FLAGT from the data bus */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1;\n                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */\n                    ctl_flags_cf_we=1; end\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1;\n                    ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */\n                    ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; /* Enable register gate based on the rsel0 */ /* Controlled by register gate */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1; end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */\n                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */ end\n    if (M2 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M2 & T3) begin fMRead=1; setM1=1;\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1; end\nend\n\nif (use_ixiy & pla[52]) begin\n    if (M1 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_bus=1; /* Load FLAGT from the data bus */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1;\n                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */\n                    ctl_flags_cf_we=1; end\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M2 & T3) begin fMRead=1; nextM=1; end\n    if (M3 & T1) begin ixy_d=1; /* Compute WZ=IX+d */ end\n    if (M3 & T2) begin ixy_d=1; /* Compute WZ=IX+d */ end\n    if (M3 & T3) begin ixy_d=1; /* Compute WZ=IX+d */ end\n    if (M3 & T4) begin ixy_d=1; /* Compute WZ=IX+d */ end\n    if (M3 & T5) begin nextM=1; ctl_mRead=1; ixy_d=1; /* Compute WZ=IX+d */ end\nend\n\nif (~use_ixiy & pla[52]) begin\n    if (M1 & T1) begin /* Which register to be written is decided elsewhere */\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_sw_2u=1;\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_cf_we=1; end\n    if (M1 & T2) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */\n                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */\n                    ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end\n    if (M1 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_bus=1; /* Load FLAGT from the data bus */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1;\n                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */\n                    ctl_flags_cf_we=1; end\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M2 & T3) begin fMRead=1; setM1=1;\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1; end\n    if (M4 & T1) begin fMRead=1;\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M4 & T2) begin fMRead=1;\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_bus=1; /* Load FLAGT from the data bus */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */\n                    ctl_flags_cf_we=1; end\n    if (M4 & T3) begin fMRead=1; setM1=1;\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1; end\nend\n\nif (pla[66] & ~pla[53]) begin\n    if (M1 & T1) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; /* Write 8-bit GP register */\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_sw_2u=1;\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V;\n                    ctl_flags_use_cf2=1; end\n    if (M1 & T2) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */\n                    ctl_flags_hf_cpl=flags_nf; end\n    if (M1 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_bus=1; /* Load FLAGT from the data bus */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1;\n                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */\n                    ctl_flags_cf_we=1; end\n    if (M1 & T4) begin validPLA=1; setM1=1;\n        if (op4 & op5 & ~op3) begin ctl_bus_zero_oe=1; end  /* Trying to read flags? Put 0 on the bus instead. */\n        if (~(op4 & op5 & ~op3)) begin ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; end /* Read 8-bit GP register */\n                    ctl_reg_out_hi=~rsel3; ctl_reg_out_lo=rsel3; ctl_sw_2u=~rsel3; ctl_sw_2d=rsel3; /* Enable register gate based on the rsel3 */ /* Controlled by register gate */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_zero=1; /* Zero */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;\n                    ctl_flags_cf_set=1; /* Set CF going into the ALU core */\n                    ctl_flags_cf2_we=1; end\nend\n\nif (pla[75]) begin\n    if (M1 & T1) begin\n                    ctl_flags_nf_we=1; ctl_flags_nf_set=1;\n                    ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */\n                    ctl_alu_sel_op2_neg=1; end\n    if (M1 & T4) begin\n                    ctl_flags_nf_we=1; ctl_flags_nf_set=1;\n                    ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */\n                    ctl_alu_sel_op2_neg=1; end\nend\n\nif ((M2 | M4) & pla[75]) begin\n    begin\n                    ctl_flags_nf_we=1; ctl_flags_nf_set=1;\n                    ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */\n                    ctl_alu_sel_op2_neg=1; end\nend\n\nif (use_ixiy & pla[53]) begin\n    if (M1 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_bus=1; /* Load FLAGT from the data bus */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1;\n                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */\n                    ctl_flags_cf_we=1; end\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M2 & T3) begin fMRead=1; nextM=1; end\n    if (M3 & T1) begin ixy_d=1; /* Compute WZ=IX+d */ end\n    if (M3 & T2) begin ixy_d=1; /* Compute WZ=IX+d */ end\n    if (M3 & T3) begin ixy_d=1; /* Compute WZ=IX+d */ end\n    if (M3 & T4) begin ixy_d=1; /* Compute WZ=IX+d */ end\n    if (M3 & T5) begin nextM=1; ctl_mRead=1; ixy_d=1; /* Compute WZ=IX+d */ end\nend\n\nif (~use_ixiy & pla[53]) begin\n    if (M1 & T2) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */\n                    ctl_flags_hf_cpl=flags_nf; end\n    if (M1 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_bus=1; /* Load FLAGT from the data bus */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1;\n                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */\n                    ctl_flags_cf_we=1; end\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMRead=1; end\n    if (M2 & T3) begin fMRead=1;\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_zero=1; /* Zero */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;\n                    ctl_flags_cf_set=1; /* Set CF going into the ALU core */\n                    ctl_flags_cf2_we=1; end\n    if (M2 & T4) begin nextM=1; ctl_mWrite=1;\n                    ctl_sw_2u=1;\n                    ctl_sw_1u=1;\n                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V;\n                    ctl_flags_use_cf2=1; end\n    if (M3 & T1) begin fMWrite=1;\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M3 & T2) begin fMWrite=1; end\n    if (M3 & T3) begin fMWrite=1; setM1=1; end\n    if (M4 & T1) begin fMRead=1;\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M4 & T2) begin fMRead=1; end\n    if (M4 & T3) begin fMRead=1;\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_zero=1; /* Zero */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;\n                    ctl_flags_cf_set=1; /* Set CF going into the ALU core */\n                    ctl_flags_cf2_we=1; end\n    if (M4 & T4) begin nextM=1; ctl_mWrite=1;\n                    ctl_sw_2u=1;\n                    ctl_sw_1u=1;\n                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V;\n                    ctl_flags_use_cf2=1; end\n    if (M5 & T1) begin fMWrite=1;\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M5 & T2) begin fMWrite=1; end\n    if (M5 & T3) begin fMWrite=1; setM1=1; end\nend\n\n// 16-bit Arithmetic Group\nif (pla[69]) begin\n    if (M1 & T2) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end\n    if (M1 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_bus=1; /* Load FLAGT from the data bus */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1;\n                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;\n                    ctl_flags_cf_we=1; end\n    if (M1 & T4) begin validPLA=1; nextM=1;\n                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b01;\n                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */\n                    ctl_sw_2d=1;\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */ end\n    if (M2 & T1) begin\n                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */\n                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */\n                    ctl_sw_2d=1;\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_hf_we=1;\n                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end\n    if (M2 & T2) begin\n                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */\n                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */\n                    ctl_sw_2u=1;\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_cf_we=1; end\n    if (M2 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b10;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */ end\n    if (M2 & T4) begin nextM=1;\n                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_hf_we=1;\n                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end\n    if (M3 & T1) begin\n                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */\n                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */\n                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */\n                    ctl_sw_2u=1;\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_cf_we=1; end\n    if (M3 & T2) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M3 & T3) begin setM1=1; end\nend\n\nif (op3 & pla[68]) begin\n    if (M1 & T2) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end\n    if (M1 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_bus=1; /* Load FLAGT from the data bus */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1;\n                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;\n                    ctl_flags_cf_we=1; end\n    if (M1 & T4) begin validPLA=1; nextM=1;\n                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b01;\n                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */\n                    ctl_sw_2d=1;\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */ end\n    if (M2 & T1) begin\n                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */\n                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */\n                    ctl_sw_2d=1;\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_hf_we=1;\n                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end\n    if (M2 & T2) begin\n                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */\n                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */\n                    ctl_sw_2u=1;\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_cf_we=1; end\n    if (M2 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b10;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */ end\n    if (M2 & T4) begin nextM=1;\n                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_hf_we=1;\n                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end\n    if (M3 & T1) begin\n                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */\n                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */\n                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */\n                    ctl_sw_2u=1;\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V;\n                    ctl_flags_cf_we=1;\n                    ctl_alu_zero_16bit=1; /* 16-bit arithmetic operation uses ZF calculated over 2 bytes */ end\n    if (M3 & T2) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M3 & T3) begin setM1=1; end\nend\n\nif (~op3 & pla[68]) begin\n    if (M1 & T2) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */\n                    ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end\n    if (M1 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_bus=1; /* Load FLAGT from the data bus */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1;\n                    ctl_flags_nf_we=1; ctl_flags_nf_set=1;\n                    ctl_flags_cf_we=1; end\n    if (M1 & T4) begin validPLA=1; nextM=1;\n                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b01;\n                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */\n                    ctl_sw_2d=1;\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */ end\n    if (M2 & T1) begin\n                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */\n                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */\n                    ctl_sw_2d=1;\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_alu_sel_op2_neg=1; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_hf_we=1;\n                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end\n    if (M2 & T2) begin\n                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */\n                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */\n                    ctl_sw_2u=1;\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_sel_op2_neg=1; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_cf_we=1; end\n    if (M2 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b10;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */ end\n    if (M2 & T4) begin nextM=1;\n                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_alu_sel_op2_neg=1; ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_hf_we=1;\n                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end\n    if (M3 & T1) begin\n                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */\n                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */\n                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */\n                    ctl_sw_2u=1;\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_sel_op2_neg=1; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V;\n                    ctl_flags_cf_we=1;\n                    ctl_alu_zero_16bit=1; /* 16-bit arithmetic operation uses ZF calculated over 2 bytes */ end\n    if (M3 & T2) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M3 & T3) begin setM1=1; end\nend\n\nif (pla[9]) begin\n    if (M1 & T4) begin validPLA=1;\n                    ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit general purpose register, enable SW4 downstream */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */\n                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end\n    if (M1 & T5) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit general purpose register, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */\n                    ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end\n    if (M1 & T6) begin setM1=1; end\nend\n\n// General Purpose Arithmetic and CPU Control Groups\nif (pla[77]) begin\n    if (M1 & T1) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;\n                    ctl_flags_cf_we=1;\n                    ctl_alu_sel_op2_neg=flags_nf; ctl_flags_cf_cpl=~flags_nf; end\n    if (M1 & T2) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */\n                    ctl_flags_use_cf2=1;\n                    ctl_flags_hf_cpl=flags_nf; end\n    if (M1 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_bus=1; /* Load FLAGT from the data bus */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf2_we=1; /* Write HF2 flag (DAA only) */\n                    ctl_flags_pf_we=1;\n                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */\n                    ctl_flags_cf_we=1; end\n    if (M1 & T4) begin validPLA=1; setM1=1;\n                    ctl_sw_2d=1;\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_cf_set=1; /* Set CF going into the ALU core */\n                    ctl_flags_cf2_we=1; ctl_flags_cf2_sel_daa=1;\n                    ctl_daa_oe=1; /* Write DAA correction factor to the bus */\n                    ctl_alu_sel_op2_neg=flags_nf; ctl_flags_cf_cpl=~flags_nf; end\nend\n\nif (pla[81]) begin\n    if (M1 & T1) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_nf_we=1; ctl_flags_nf_set=1;\n                    ctl_alu_sel_op2_neg=1; end\n    if (M1 & T2) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */\n                    ctl_flags_hf_cpl=flags_nf; end\n    if (M1 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_bus=1; /* Load FLAGT from the data bus */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1;\n                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */\n                    ctl_flags_cf_we=1; end\n    if (M1 & T4) begin validPLA=1; setM1=1;\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_op1_sel_zero=1; /* Zero */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_nf_we=1; ctl_flags_nf_set=1;\n                    ctl_alu_sel_op2_neg=1; end\nend\n\nif (pla[82]) begin\n    if (M1 & T1) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_sel_op2_neg=1; ctl_flags_cf_set|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V;\n                    ctl_flags_nf_we=1; ctl_flags_nf_set=1;\n                    ctl_flags_cf_we=1; end\n    if (M1 & T2) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */\n                    ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end\n    if (M1 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_bus=1; /* Load FLAGT from the data bus */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1;\n                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */\n                    ctl_flags_cf_we=1; end\n    if (M1 & T4) begin validPLA=1; setM1=1;\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_op1_sel_zero=1; /* Zero */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_alu_sel_op2_neg=1; ctl_flags_cf_set|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_nf_we=1; ctl_flags_nf_set=1;\n                    ctl_flags_cf_we=1; end\nend\n\nif (pla[89]) begin\n    if (M1 & T1) begin\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end\n    if (M1 & T2) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */\n                    ctl_flags_cf_we=1; ctl_flags_cf_cpl=1; /* CCF */\n                    ctl_flags_hf_cpl=~flags_cf; /* Used for CCF */ end\n    if (M1 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_bus=1; /* Load FLAGT from the data bus */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1;\n                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */\n                    ctl_flags_cf_we=1; end\n    if (M1 & T4) begin validPLA=1; setM1=1;\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end\nend\n\nif (pla[92]) begin\n    if (M1 & T1) begin\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end\n    if (M1 & T2) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */\n                    ctl_flags_cf_set=1; /* Set CF going into the ALU core */ end\n    if (M1 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_bus=1; /* Load FLAGT from the data bus */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1;\n                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */\n                    ctl_flags_cf_we=1; end\n    if (M1 & T4) begin validPLA=1; setM1=1;\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end\nend\n\nif (pla[95]) begin\n    if (M1 & T3) begin\n                    ctl_state_halt_set=1; /* Enter HALT state */ end\n    if (M1 & T4) begin validPLA=1; setM1=1; end\nend\n\nif (pla[97]) begin\n    if (M1 & T3) begin\n                    ctl_iffx_bit=op3; ctl_iffx_we=1; /* DI/EI */ end\n    if (M1 & T4) begin validPLA=1; setM1=1;\n                    ctl_no_ints=1; /* Disable interrupt generation for this opcode (DI/EI/CB/ED/DD/FD) */ end\nend\n\nif (pla[96]) begin\n    if (M1 & T3) begin\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_im_we=1; /* IM n ('n' is read by opcode[4:3]) */ end\n    if (M1 & T4) begin validPLA=1; setM1=1; end\nend\n\n// Rotate and Shift Group\nif (pla[25]) begin\n    if (M1 & T1) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;\n                    ctl_flags_cf_we=1; end\n    if (M1 & T2) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */\n                    ctl_flags_use_cf2=1; end\n    if (M1 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_bus=1; /* Load FLAGT from the data bus */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1;\n                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */\n                    ctl_flags_cf_we=1; end\n    if (M1 & T4) begin validPLA=1; setM1=1;\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=1; ctl_shift_en=1; /* Shifter unit AND shift enable! */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;\n                    ctl_flags_cf2_we=1; ctl_flags_cf2_sel_shift=1; end\nend\n\nif (~use_ixiy & pla[70] & ~pla[55]) begin\n    if (M1 & T1) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0}; /* Write 8-bit GP register selected by op[2:0] */\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_sw_2u=1;\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;\n                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;\n                    ctl_flags_cf_we=1; end\n    if (M1 & T2) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */\n                    ctl_flags_use_cf2=1; end\n    if (M1 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_bus=1; /* Load FLAGT from the data bus */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1;\n                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */\n                    ctl_flags_cf_we=1; end\n    if (M1 & T4) begin validPLA=1; setM1=1;\n                    ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */\n                    ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; /* Enable register gate based on the rsel0 */ /* Controlled by register gate */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=1; ctl_shift_en=1; /* Shifter unit AND shift enable! */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;\n                    ctl_flags_cf2_we=1; ctl_flags_cf2_sel_shift=1; end\n    if (M4 & T1) begin fMRead=1;\n                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_ir_we=1; end\n    if (M4 & T2) begin fMRead=1; end\n    if (M4 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1;\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=1; ctl_shift_en=1; /* Shifter unit AND shift enable! */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;\n                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;\n                    ctl_flags_cf2_we=1; ctl_flags_cf2_sel_shift=1; end\n    if (M5 & T1) begin fMWrite=1;\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */\n                    ctl_sw_2u=1;\n                    ctl_sw_1u=1;\n                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;\n                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;\n                    ctl_flags_cf_we=1; end\n    if (M5 & T2) begin fMWrite=1; end\n    if (M5 & T3) begin fMWrite=1; setM1=1; end\nend\n\nif (~use_ixiy & pla[70] & pla[55]) begin\n    if (M1 & T2) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */\n                    ctl_flags_use_cf2=1; end\n    if (M1 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_bus=1; /* Load FLAGT from the data bus */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1;\n                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */\n                    ctl_flags_cf_we=1; end\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMRead=1; end\n    if (M2 & T3) begin fMRead=1; end\n    if (M2 & T4) begin nextM=1; ctl_mWrite=1;\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=1; ctl_shift_en=1; /* Shifter unit AND shift enable! */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;\n                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;\n                    ctl_flags_cf2_we=1; ctl_flags_cf2_sel_shift=1; end\n    if (M3 & T1) begin fMWrite=1;\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */\n                    ctl_sw_2u=1;\n                    ctl_sw_1u=1;\n                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;\n                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;\n                    ctl_flags_cf_we=1; end\n    if (M3 & T2) begin fMWrite=1; end\n    if (M3 & T3) begin fMWrite=1; setM1=1; end\n    if (M4 & T1) begin fMRead=1;\n                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_ir_we=1; end\n    if (M4 & T2) begin fMRead=1; end\n    if (M4 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1;\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=1; ctl_shift_en=1; /* Shifter unit AND shift enable! */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;\n                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;\n                    ctl_flags_cf2_we=1; ctl_flags_cf2_sel_shift=1; end\n    if (M5 & T1) begin fMWrite=1;\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */\n                    ctl_sw_2u=1;\n                    ctl_sw_1u=1;\n                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;\n                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1;\n                    ctl_flags_cf_we=1; end\n    if (M5 & T2) begin fMWrite=1; end\n    if (M5 & T3) begin fMWrite=1; setM1=1; end\nend\n\nif (pla[15] & op3) begin\n    if (M1 & T1) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;\n                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end\n    if (M1 & T2) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end\n    if (M1 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_bus=1; /* Load FLAGT from the data bus */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1;\n                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */\n                    ctl_flags_cf_we=1; end\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M2 & T3) begin fMRead=1; nextM=1; end\n    if (M3 & T1) begin\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_lq=1; /* Cross-bus wire (see schematic) */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ end\n    if (M3 & T4) begin nextM=1; ctl_mWrite=1;\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op1_sel_low=1; /* Write low nibble with a high nibble */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ end\n    if (M4 & T1) begin fMWrite=1;\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */\n                    ctl_sw_2u=1;\n                    ctl_sw_1u=1;\n                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_op2_oe=1; /* OP2 latch */ end\n    if (M4 & T2) begin fMWrite=1;\n                    ctl_alu_op1_oe=1; /* OP1 latch */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */ end\n    if (M4 & T3) begin fMWrite=1; setM1=1;\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end\nend\n\nif (pla[15] & ~op3) begin\n    if (M1 & T1) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;\n                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end\n    if (M1 & T2) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end\n    if (M1 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_bus=1; /* Load FLAGT from the data bus */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1;\n                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */\n                    ctl_flags_cf_we=1; end\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M2 & T3) begin fMRead=1; nextM=1; end\n    if (M3 & T1) begin\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_lq=1; /* Cross-bus wire (see schematic) */\n                    ctl_alu_op1_sel_low=1; /* Write low nibble with a high nibble */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ end\n    if (M3 & T2) begin\n                    ctl_sw_2u=1;\n                    ctl_sw_1u=1;\n                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_op2_oe=1; /* OP2 latch */ end\n    if (M3 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_lq=1; /* Cross-bus wire (see schematic) */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ end\n    if (M3 & T4) begin nextM=1; ctl_mWrite=1;\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op1_sel_low=1; /* Write low nibble with a high nibble */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ end\n    if (M4 & T1) begin fMWrite=1;\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */\n                    ctl_sw_2u=1;\n                    ctl_sw_1u=1;\n                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_op2_oe=1; /* OP2 latch */ end\n    if (M4 & T2) begin fMWrite=1;\n                    ctl_alu_op1_oe=1; /* OP1 latch */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */ end\n    if (M4 & T3) begin fMWrite=1; setM1=1;\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end\nend\n\n// Bit Manipulation Group\nif (~use_ixiy & pla[72] & ~pla[55]) begin\n    if (M1 & T1) begin\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_core_S=1; ctl_flags_cf_set=1;\n                    ctl_flags_sz_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;\n                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end\n    if (M1 & T2) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end\n    if (M1 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_flags_bus=1; /* Load FLAGT from the data bus */\n                    ctl_alu_bs_oe=1; /* Bit-selector unit */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1;\n                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */\n                    ctl_flags_cf_we=1; end\n    if (M1 & T4) begin validPLA=1; setM1=1;\n                    ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */\n                    ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; /* Enable register gate based on the rsel0 */ /* Controlled by register gate */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_alu_core_S=1; ctl_flags_cf_set=1;\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end\n    if (M4 & T1) begin fMRead=1;\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_alu_bs_oe=1; /* Bit-selector unit */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_ir_we=1; end\n    if (M4 & T2) begin fMRead=1; end\n    if (M4 & T3) begin fMRead=1; end\n    if (M4 & T4) begin setM1=1;\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_alu_core_S=1; ctl_flags_cf_set=1;\n                    ctl_flags_sz_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end\nend\n\nif (~use_ixiy & pla[72] & pla[55]) begin\n    if (M1 & T1) begin\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_core_S=1; ctl_flags_cf_set=1;\n                    ctl_flags_sz_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;\n                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end\n    if (M1 & T2) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end\n    if (M1 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_flags_bus=1; /* Load FLAGT from the data bus */\n                    ctl_alu_bs_oe=1; /* Bit-selector unit */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1;\n                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */\n                    ctl_flags_cf_we=1; end\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMRead=1; end\n    if (M2 & T3) begin fMRead=1;\n                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_bus=1; /* Load FLAGT from the data bus */\n                    ctl_flags_xy_we=1; end\n    if (M2 & T4) begin setM1=1;\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_alu_core_S=1; ctl_flags_cf_set=1;\n                    ctl_flags_sz_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end\n    if (M4 & T1) begin fMRead=1;\n                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_alu_bs_oe=1; /* Bit-selector unit */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_ir_we=1; end\n    if (M4 & T2) begin fMRead=1; end\n    if (M4 & T3) begin fMRead=1; end\n    if (M4 & T4) begin setM1=1;\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_alu_core_S=1; ctl_flags_cf_set=1;\n                    ctl_flags_sz_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end\nend\n\nif (~use_ixiy & pla[74] & ~pla[55]) begin\n    if (M1 & T1) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0}; /* Write 8-bit GP register selected by op[2:0] */\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_sw_2u=1;\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end\n    if (M1 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_flags_bus=1; /* Load FLAGT from the data bus */\n                    ctl_alu_bs_oe=1; /* Bit-selector unit */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1;\n                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */\n                    ctl_flags_cf_we=1; end\n    if (M1 & T4) begin validPLA=1; setM1=1;\n                    ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */\n                    ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; /* Enable register gate based on the rsel0 */ /* Controlled by register gate */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end\n    if (M4 & T1) begin fMRead=1;\n                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_alu_bs_oe=1; /* Bit-selector unit */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_ir_we=1; end\n    if (M4 & T2) begin fMRead=1; end\n    if (M4 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1;\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end\n    if (M5 & T1) begin fMWrite=1;\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */\n                    ctl_sw_2u=1;\n                    ctl_sw_1u=1;\n                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end\n    if (M5 & T2) begin fMWrite=1; end\n    if (M5 & T3) begin fMWrite=1; setM1=1; end\nend\n\nif (~use_ixiy & pla[74] & pla[55]) begin\n    if (M1 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_flags_bus=1; /* Load FLAGT from the data bus */\n                    ctl_alu_bs_oe=1; /* Bit-selector unit */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1;\n                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */\n                    ctl_flags_cf_we=1; end\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMRead=1; end\n    if (M2 & T3) begin fMRead=1;\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end\n    if (M2 & T4) begin nextM=1; ctl_mWrite=1;\n                    ctl_sw_2u=1;\n                    ctl_sw_1u=1;\n                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end\n    if (M3 & T1) begin fMWrite=1;\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M3 & T2) begin fMWrite=1; end\n    if (M3 & T3) begin fMWrite=1; setM1=1; end\n    if (M4 & T1) begin fMRead=1;\n                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_alu_bs_oe=1; /* Bit-selector unit */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_ir_we=1; end\n    if (M4 & T2) begin fMRead=1; end\n    if (M4 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1;\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end\n    if (M5 & T1) begin fMWrite=1;\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */\n                    ctl_sw_2u=1;\n                    ctl_sw_1u=1;\n                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end\n    if (M5 & T2) begin fMWrite=1; end\n    if (M5 & T3) begin fMWrite=1; setM1=1; end\nend\n\nif (~use_ixiy & pla[73] & ~pla[55]) begin\n    if (M1 & T1) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0}; /* Write 8-bit GP register selected by op[2:0] */\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_sw_2u=1;\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end\n    if (M1 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_flags_bus=1; /* Load FLAGT from the data bus */\n                    ctl_alu_bs_oe=1; /* Bit-selector unit */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1;\n                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */\n                    ctl_flags_cf_we=1; end\n    if (M1 & T4) begin validPLA=1; setM1=1;\n                    ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */\n                    ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; /* Enable register gate based on the rsel0 */ /* Controlled by register gate */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end\n    if (M4 & T1) begin fMRead=1;\n                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_alu_bs_oe=1; /* Bit-selector unit */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_ir_we=1; end\n    if (M4 & T2) begin fMRead=1; end\n    if (M4 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1;\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end\n    if (M5 & T1) begin fMWrite=1;\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */\n                    ctl_sw_2u=1;\n                    ctl_sw_1u=1;\n                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end\n    if (M5 & T2) begin fMWrite=1; end\n    if (M5 & T3) begin fMWrite=1; setM1=1; end\nend\n\nif (~use_ixiy & pla[73] & pla[55]) begin\n    if (M1 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_flags_bus=1; /* Load FLAGT from the data bus */\n                    ctl_alu_bs_oe=1; /* Bit-selector unit */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1;\n                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */\n                    ctl_flags_cf_we=1; end\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMRead=1; end\n    if (M2 & T3) begin fMRead=1;\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end\n    if (M2 & T4) begin nextM=1; ctl_mWrite=1;\n                    ctl_sw_2u=1;\n                    ctl_sw_1u=1;\n                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end\n    if (M3 & T1) begin fMWrite=1;\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M3 & T2) begin fMWrite=1; end\n    if (M3 & T3) begin fMWrite=1; setM1=1; end\n    if (M4 & T1) begin fMRead=1;\n                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_alu_bs_oe=1; /* Bit-selector unit */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_ir_we=1; end\n    if (M4 & T2) begin fMRead=1; end\n    if (M4 & T3) begin fMRead=1; nextM=1; ctl_mWrite=1;\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end\n    if (M5 & T1) begin fMWrite=1;\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */\n                    ctl_sw_2u=1;\n                    ctl_sw_1u=1;\n                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end\n    if (M5 & T2) begin fMWrite=1; end\n    if (M5 & T3) begin fMWrite=1; setM1=1; end\nend\n\n// Input and Output Groups\nif (pla[37] & ~pla[28]) begin\n    if (M1 & T1) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M2 & T3) begin fMRead=1; nextM=1; ctl_iorw=1; end\n    if (M3 & T1) begin fIORead=1;\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; ctl_sw_4d=1; /* Read 8-bit general purpose A register, enable SW4 downstream */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ /* Which register to be written is decided elsewhere */\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end\n    if (M3 & T2) begin fIORead=1; end\n    if (M3 & T3) begin fIORead=1; end\n    if (M3 & T4) begin fIORead=1; setM1=1; end\nend\n\nif (pla[27] & ~pla[34]) begin\n    if (M1 & T1) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; /* Write 8-bit GP register */\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;\n                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end\n    if (M1 & T2) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end\n    if (M1 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_bus=1; /* Load FLAGT from the data bus */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1;\n                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */\n                    ctl_flags_cf_we=1; end\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_iorw=1; end\n    if (M2 & T1) begin fIORead=1;\n                    ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fIORead=1; end\n    if (M2 & T3) begin fIORead=1; end\n    if (M2 & T4) begin fIORead=1; setM1=1;\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end\nend\n\nif (pla[37] & pla[28]) begin\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M2 & T3) begin fMRead=1; nextM=1; ctl_iorw=1;\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; ctl_sw_4d=1; /* Read 8-bit general purpose A register, enable SW4 downstream */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */\n                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end\n    if (M3 & T1) begin fIOWrite=1;\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;\n                    ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */\n                    ctl_sw_2u=1;\n                    ctl_sw_1u=1;\n                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end\n    if (M3 & T2) begin fIOWrite=1; end\n    if (M3 & T3) begin fIOWrite=1; end\n    if (M3 & T4) begin fIOWrite=1; setM1=1; end\nend\n\nif (pla[27] & pla[34]) begin\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_iorw=1;\n        if (op4 & op5 & ~op3) begin ctl_bus_zero_oe=1; end  /* Trying to read flags? Put 0 on the bus instead. */\n        if (~(op4 & op5 & ~op3)) begin ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; end /* Read 8-bit GP register */\n                    ctl_reg_out_hi=~rsel3; ctl_reg_out_lo=rsel3; ctl_sw_2u=~rsel3; ctl_sw_2d=rsel3; /* Enable register gate based on the rsel3 */ /* Controlled by register gate */\n                    ctl_sw_1u=1;\n                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end\n    if (M2 & T1) begin fIOWrite=1;\n                    ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fIOWrite=1; end\n    if (M2 & T3) begin fIOWrite=1; end\n    if (M2 & T4) begin fIOWrite=1; setM1=1; end\nend\n\nif (pla[91] & pla[21]) begin\n    if (M1 & T1) begin\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_core_R=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;\n                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; end\n    if (M1 & T2) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end\n    if (M1 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_bus=1; /* Load FLAGT from the data bus */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1;\n                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */\n                    ctl_flags_cf_we=1; end\n    if (M1 & T4) begin validPLA=1; end\n    if (M1 & T5) begin nextM=1; ctl_iorw=1; end\n    if (M2 & T1) begin fIORead=1;\n                    ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fIORead=1;\n                    ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_zero=1; /* Zero */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_hf_we=1;\n                    ctl_alu_sel_op2_neg=1; end\n    if (M2 & T3) begin fIORead=1;\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_cf_we=1;\n                    ctl_alu_sel_op2_neg=1; end\n    if (M2 & T4) begin fIORead=1; nextM=1; ctl_mWrite=1;\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_flags_nf_we=1; /* Sign bit, to be used with FLAGT source set to \"alu\" */\n                    ctl_alu_sel_op2_neg=1; end\n    if (M3 & T1) begin fMWrite=1;\n                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M3 & T2) begin fMWrite=1;\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M3 & T3) begin fMWrite=1; nextM=1; setM1=nonRep | flags_zf; end\n    if (M4 & T1) begin\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M4 & T2) begin\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M4 & T3) begin\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M4 & T4) begin\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M4 & T5) begin setM1=1; end\nend\n\nif (pla[91] & pla[20]) begin\n    if (M1 & T1) begin\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_core_R=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;\n                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; end\n    if (M1 & T2) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end\n    if (M1 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_bus=1; /* Load FLAGT from the data bus */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1;\n                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */\n                    ctl_flags_cf_we=1; end\n    if (M1 & T4) begin validPLA=1;\n                    ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_zero=1; /* Zero */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_hf_we=1;\n                    ctl_alu_sel_op2_neg=1; end\n    if (M1 & T5) begin nextM=1; ctl_mRead=1;\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_alu_sel_op2_neg=1; end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMRead=1;\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M2 & T3) begin fMRead=1; nextM=1; ctl_iorw=1;\n                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b01;\n                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */\n                    ctl_sw_2d=1;\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */ end\n    if (M3 & T1) begin fIOWrite=1;\n                    ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M3 & T2) begin fIOWrite=1;\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_nf_we=1; /* Sign bit, to be used with FLAGT source set to \"alu\" */ end\n    if (M3 & T3) begin fIOWrite=1;\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_cf_we=1; end\n    if (M3 & T4) begin fIOWrite=1; nextM=1; setM1=nonRep | flags_zf; end\n    if (M4 & T1) begin\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M4 & T2) begin\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M4 & T3) begin\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M4 & T4) begin\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M4 & T5) begin setM1=1; end\nend\n\n// Jump Group\nif (pla[29]) begin\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;\n                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */\n                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end\n    if (M3 & T1) begin fMRead=1;\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M3 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M3 & T3) begin fMRead=1; setM1=1;\n                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */\n                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */\n                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end\nend\n\nif (pla[43]) begin\n    if (M1 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_bus=1; /* Load FLAGT from the data bus */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1;\n                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */\n                    ctl_flags_cf_we=1; end\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;\n                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */\n                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end\n    if (M3 & T1) begin fMRead=1;\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M3 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M3 & T3) begin fMRead=1; setM1=1;\n                    ctl_reg_not_pc|=flags_cond_true; ctl_reg_sel_wz|=flags_cond_true; ctl_reg_sys_hilo|={flags_cond_true,flags_cond_true}; ctl_sw_4d|=flags_cond_true;\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */\n                    ctl_reg_sys_we_hi=flags_cond_true; ctl_reg_sel_wz=flags_cond_true; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Conditionally selecting only W */\n                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end\nend\n\nif (pla[47]) begin\n    if (M1 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_bus=1; /* Load FLAGT from the data bus */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1;\n                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */\n                    ctl_flags_cf_we=1; end\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M2 & T3) begin fMRead=1; nextM=1; end\n    if (M3 & T1) begin\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1; end\n    if (M3 & T2) begin\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1;\n                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */\n                    ctl_sw_2d=1;\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_hf_we=1; end\n    if (M3 & T3) begin\n                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */\n                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */\n                    ctl_sw_2u=1;\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_cf_we=1; end\n    if (M3 & T4) begin\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4u=1;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_zero=1; /* Zero */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_hf_we=1;\n                    ctl_alu_sel_op2_neg=flags_sf; end\n    if (M3 & T5) begin setM1=1;\n                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */\n                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */\n                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_alu_sel_op2_neg=flags_sf;\n                    ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end\nend\n\nif (pla[48]) begin\n    if (M1 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_bus=1; /* Load FLAGT from the data bus */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1;\n                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */\n                    ctl_flags_cf_we=1; end\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1;\n                    ctl_cond_short=1; /* M1/T3 only: force a short flags condition (SS) */ end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M2 & T3) begin fMRead=1; nextM=1; setM1=~flags_cond_true; end\n    if (M3 & T1) begin\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1; end\n    if (M3 & T2) begin\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1;\n                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */\n                    ctl_sw_2d=1;\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_hf_we=1; end\n    if (M3 & T3) begin\n                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */\n                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */\n                    ctl_sw_2u=1;\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_cf_we=1; end\n    if (M3 & T4) begin\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4u=1;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_zero=1; /* Zero */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_hf_we=1;\n                    ctl_alu_sel_op2_neg=flags_sf; end\n    if (M3 & T5) begin setM1=1;\n                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */\n                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */\n                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_alu_sel_op2_neg=flags_sf;\n                    ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end\nend\n\nif (pla[6]) begin\n    if (M1 & T4) begin validPLA=1; setM1=1;\n                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */\n                    ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end\nend\n\nif (pla[26]) begin\n    if (M1 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_bus=1; /* Load FLAGT from the data bus */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1;\n                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */\n                    ctl_flags_cf_we=1; end\n    if (M1 & T4) begin validPLA=1;\n                    ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10;\n                    ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_zero=1; /* Zero */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_hf_we=1;\n                    ctl_alu_sel_op2_neg=1; end\n    if (M1 & T5) begin nextM=1; ctl_mRead=1;\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_sz_we=1;\n                    ctl_alu_sel_op2_neg=1; end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M2 & T3) begin fMRead=1; nextM=1; setM1=flags_zf; /* Used in DJNZ */ end\n    if (M3 & T1) begin\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1; end\n    if (M3 & T2) begin\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1;\n                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */\n                    ctl_sw_2d=1;\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_hf_we=1; end\n    if (M3 & T3) begin\n                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */\n                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */\n                    ctl_sw_2u=1;\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_cf_we=1; end\n    if (M3 & T4) begin\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4u=1;\n                    ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_zero=1; /* Zero */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_hf_we=1;\n                    ctl_alu_sel_op2_neg=flags_sf; end\n    if (M3 & T5) begin setM1=1;\n                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */\n                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */\n                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_alu_sel_op2_neg=flags_sf;\n                    ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end\nend\n\n// Call and Return Group\nif (pla[24]) begin\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;\n                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */\n                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end\n    if (M3 & T1) begin fMRead=1;\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M3 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M3 & T3) begin fMRead=1;\n                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */\n                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end\n    if (M3 & T4) begin nextM=1; ctl_mWrite=1;\n                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M4 & T1) begin fMWrite=1;\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */\n                    ctl_apin_mux=1; /* Apin sourced from incrementer */\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4u=1;\n                    ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */\n                    ctl_sw_2u=1;\n                    ctl_sw_1u=1;\n                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end\n    if (M4 & T2) begin fMWrite=1;\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M4 & T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;\n                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M5 & T1) begin fMWrite=1;\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */\n                    ctl_apin_mux=1; /* Apin sourced from incrementer */\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1;\n                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */\n                    ctl_sw_1u=1;\n                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end\n    if (M5 & T2) begin fMWrite=1;\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M5 & T3) begin fMWrite=1; setM1=1;\n                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */\n                    ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end\nend\n\nif (pla[42]) begin\n    if (M1 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_bus=1; /* Load FLAGT from the data bus */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1;\n                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */\n                    ctl_flags_cf_we=1; end\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;\n                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */\n                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end\n    if (M3 & T1) begin fMRead=1;\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M3 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M3 & T3) begin fMRead=1; nextM=~flags_cond_true; setM1=~flags_cond_true;\n                    ctl_reg_sys_we_hi=flags_cond_true; ctl_reg_sel_wz=flags_cond_true; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Conditionally selecting only W */\n                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end\n    if (M3 & T4) begin nextM=1; ctl_mWrite=1;\n                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M4 & T1) begin fMWrite=1;\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */\n                    ctl_apin_mux=1; /* Apin sourced from incrementer */\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4u=1;\n                    ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */\n                    ctl_sw_2u=1;\n                    ctl_sw_1u=1;\n                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end\n    if (M4 & T2) begin fMWrite=1;\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M4 & T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;\n                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M5 & T1) begin fMWrite=1;\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */\n                    ctl_apin_mux=1; /* Apin sourced from incrementer */\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1;\n                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */\n                    ctl_sw_1u=1;\n                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end\n    if (M5 & T2) begin fMWrite=1;\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M5 & T3) begin fMWrite=1; setM1=1;\n                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */\n                    ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end\nend\n\nif (pla[35]) begin\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMRead=1;\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;\n                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */\n                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end\n    if (M3 & T1) begin fMRead=1;\n                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M3 & T2) begin fMRead=1;\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M3 & T3) begin fMRead=1; setM1=1;\n                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */\n                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */\n                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end\nend\n\nif (pla[45]) begin\n    if (M1 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_bus=1; /* Load FLAGT from the data bus */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1;\n                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */\n                    ctl_flags_cf_we=1; end\n    if (M1 & T4) begin validPLA=1; end\n    if (M1 & T5) begin nextM=1; ctl_mRead=1; setM1=~flags_cond_true; end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMRead=1;\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;\n                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */\n                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end\n    if (M3 & T1) begin fMRead=1;\n                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M3 & T2) begin fMRead=1;\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M3 & T3) begin fMRead=1; setM1=1;\n                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */\n                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */\n                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end\nend\n\nif (pla[46]) begin\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1;\n                    ctl_iff1_iff2=1; /* RETN copies IFF2 into IFF1 */ end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMRead=1;\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;\n                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */\n                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end\n    if (M3 & T1) begin fMRead=1;\n                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M3 & T2) begin fMRead=1;\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M3 & T3) begin fMRead=1; setM1=1;\n                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */\n                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */\n                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end\nend\n\nif (pla[56]) begin\n    if (M1 & T3) begin\n                    ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_op1_oe=1; /* OP1 latch */\n                    ctl_alu_op1_sel_zero=1; /* Zero */\n                    ctl_sw_mask543_en=~((in_intr & im2) | in_nmi);\n                    ctl_sw_1d=~in_nmi; ctl_66_oe=in_nmi;\n                    ctl_bus_ff_oe=in_intr & im1; end\n    if (M1 & T4) begin validPLA=1; end\n    if (M1 & T5) begin nextM=1; ctl_mWrite=1;\n                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */ end\n    if (M2 & T1) begin fMWrite=1;\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */\n                    ctl_apin_mux=1; /* Apin sourced from incrementer */\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4u=1;\n                    ctl_reg_out_hi=1; /* From the register file onto the db2 (sw2 + ALU) */\n                    ctl_sw_2u=1;\n                    ctl_sw_1u=1;\n                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end\n    if (M2 & T2) begin fMWrite=1;\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M2 & T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;\n                    ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M3 & T1) begin fMWrite=1;\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */\n                    ctl_apin_mux=1; /* Apin sourced from incrementer */\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1;\n                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */\n                    ctl_sw_1u=1;\n                    ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end\n    if (M3 & T2) begin fMWrite=1;\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */\n                    ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; /* Decrement */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M3 & T3) begin fMWrite=1; nextM=1; ctl_mRead=in_intr & im2; /* RST38 interrupt extension */ setM1=~(in_intr & im2); /* RST38 interrupt extension */\n                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */\n                    ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end\n// INTR IM2 continues here...\n    if (M4 & T1) begin fMRead=1;\n                    ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4d=1; /* Select 8-bit I register */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */\n                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */\n                    ctl_sw_2u=1;\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_op1_oe=1; /* OP1 latch */ end\n    if (M4 & T2) begin fMRead=1;\n                    ctl_sw_4u=1;\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */\n                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */\n                    ctl_sw_2d=1;\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */ end\n    if (M4 & T3) begin fMRead=1; nextM=1; ctl_mRead=1;\n                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */\n                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end\n    if (M5 & T1) begin fMRead=1;\n                    ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4d=1; /* Select 8-bit I register */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */\n                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */\n                    ctl_sw_2u=1;\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_op1_oe=1; /* OP1 latch */ end\n    if (M5 & T2) begin fMRead=1;\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M5 & T3) begin fMRead=1; setM1=1;\n                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */\n                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */\n                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end\nend\n\n// CB-Table opcodes\nif (pla[49]) begin\n    if (M1 & T3) begin\n                    ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_bus=1; /* Load FLAGT from the data bus */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1;\n                    ctl_flags_xy_we=1;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_pf_we=1;\n                    ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */\n                    ctl_flags_cf_we=1;\n                    ctl_state_tbl_we=1; ctl_state_tbl_cb_set=1; /* CB-table prefix */ end\n    if (M1 & T4) begin validPLA=1; nextM=1; ctl_mRead=1; end\n    if (M2 & T1) begin fMRead=1;\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\n    if (M2 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end\n    if (M2 & T3) begin fMRead=1; nextM=1; ctl_mRead=1; end\n    if (M3 & T1) begin fMRead=1;\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ ixy_d=1; /* Compute WZ=IX+d */ end\n    if (M3 & T2) begin fMRead=1;\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ ixy_d=1; /* Compute WZ=IX+d */ end\n    if (M3 & T3) begin fMRead=1; ixy_d=1; /* Compute WZ=IX+d */ end\n    if (M3 & T4) begin ixy_d=1; /* Compute WZ=IX+d */ end\n    if (M3 & T5) begin nextM=1; ctl_mRead=1; ixy_d=1; /* Compute WZ=IX+d */ end\n    if (M4 & T1) begin\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_alu_bs_oe=1; /* Bit-selector unit */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_ir_we=1; end\n// Loading a new instruction immediately changes PLA wires and continues into the new effective instructions' M4/T1 cycle\nend\n\n// Special Purposes PLA Entries\nif (pla[3]) begin\n    if (M1 & T2) begin\n                    ctl_state_ixiy_we=1; ctl_state_iy_set=op5; setIXIY=1; /* IX/IY prefix */ end\n    if (M1 & T4) begin validPLA=1; setM1=1;\n                    ctl_no_ints=1; /* Disable interrupt generation for this opcode (DI/EI/CB/ED/DD/FD) */ end\nend\n\nif (pla[44]) begin\n    if (M1 & T2) begin\n                    ctl_state_tbl_we=1; ctl_state_tbl_cb_set=1; /* CB-table prefix */ end\n    if (M1 & T4) begin validPLA=1; setM1=1;\n                    ctl_no_ints=1; /* Disable interrupt generation for this opcode (DI/EI/CB/ED/DD/FD) */ end\nend\n\nif (pla[51]) begin\n    if (M1 & T2) begin\n                    ctl_state_tbl_we=1; ctl_state_tbl_ed_set=1; /* ED-table prefix */ end\n    if (M1 & T4) begin validPLA=1; setM1=1;\n                    ctl_no_ints=1; /* Disable interrupt generation for this opcode (DI/EI/CB/ED/DD/FD) */ end\nend\n\nif (pla[76]) begin\n    begin\n                    ctl_alu_sel_op2_neg=1; ctl_flags_cf_set|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_nf_we=1; ctl_flags_nf_set=1; end\n    if (M1 & T1) begin\n                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V; end\nend\n\nif (pla[78]) begin\n    begin\n                    ctl_alu_sel_op2_neg=1; ctl_flags_cf_set|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_nf_we=1; ctl_flags_nf_set=1; end\n    if (M1 & T1) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_xy_we=1;\n                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V; end\nend\n\nif (pla[79]) begin\n    begin\n                    ctl_alu_sel_op2_neg=1; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_nf_we=1; ctl_flags_nf_set=1; end\n    if (M1 & T1) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_xy_we=1;\n                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V; end\nend\n\nif (pla[80]) begin\n    begin\n                    ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end\n    if (M1 & T1) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_xy_we=1;\n                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V; end\nend\n\nif (pla[84]) begin\n    begin\n                    ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end\n    if (M1 & T1) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_xy_we=1;\n                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V; end\nend\n\nif (pla[85]) begin\n    begin\n                    ctl_alu_core_S=1; ctl_flags_cf_set=1;\n                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end\n    if (M1 & T1) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_xy_we=1;\n                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; end\n    if (M1 & T2) begin\n                    ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */ end\nend\n\nif (pla[86]) begin\n    begin\n                    ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;\n                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end\n    if (M1 & T1) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_xy_we=1;\n                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; end\n    if (M1 & T2) begin\n                    ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */ end\nend\n\nif (pla[88]) begin\n    begin\n                    ctl_alu_core_R=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;\n                    ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end\n    if (M1 & T1) begin\n                    ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;\n                    ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */\n                    ctl_flags_xy_we=1;\n                    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; end\n    if (M1 & T2) begin\n                    ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */ end\nend\n\n// State machine to compute (IX+d)\nif (ixy_d) begin\n    if (T1) begin\n                    ctl_sw_2d=1;\n                    ctl_sw_1d=1;\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_bus=1; /* Internal bus */\n                    ctl_flags_sz_we=1; end\n    if (T2) begin\n                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b01;\n                    ctl_reg_out_lo=1; /* From the register file onto the db1 (sw2 + FLAGT + sw1) */\n                    ctl_sw_2d=1;\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_hf_we=1; end\n    if (T3) begin\n                    ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; /* Selecting only Z */\n                    ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */\n                    ctl_sw_2u=1;\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_cf2_we=1; end\n    if (T4) begin\n                    ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b10;\n                    ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the FLAGT and ALU */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_shift_oe=~ctl_alu_bs_oe; /* Shifter unit without shift-enable */\n                    ctl_alu_op2_sel_zero=1; /* Zero */\n                    ctl_alu_op1_sel_bus=1; /* Internal bus */\n                    ctl_alu_op_low=1; /* Activate ALU operation on low nibble */\n                    ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_hf_we=1;\n                    ctl_flags_use_cf2=1;\n                    ctl_alu_sel_op2_neg=flags_sf; end\n    if (T5) begin\n                    ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */\n                    ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; /* Selecting only W */\n                    ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */\n                    ctl_flags_alu=1; /* Load FLAGT from the ALU */\n                    ctl_alu_oe=1; /* Enable ALU onto the data bus */\n                    ctl_alu_res_oe=1; /* Result latch */\n                    ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */\n                    ctl_alu_core_hf|=~ctl_alu_op_low;\n                    ctl_flags_xy_we=1;\n                    ctl_alu_sel_op2_neg=flags_sf;\n                    ctl_state_ixiy_we=1; ctl_state_ixiy_clr=~setIXIY; /* Clear IX/IY flag if not explicitly set */ end\nend\n\n// Default instruction fetch (M1) state machine\nif (1) begin\n    if (M1 & T1) begin\n                    ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; ctl_apin_mux2=1; /* Apin sourced from AL */ end\n    if (M1 & T2) begin\n                    ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit IR */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */\n                    ctl_bus_db_oe=1; /* Read DB pads to internal data bus */\n                    ctl_state_ixiy_we=1; ctl_state_ixiy_clr=~setIXIY; /* Clear IX/IY flag if not explicitly set */\n                    ctl_state_tbl_we=1; /* Clear CB/ED prefix if not explicitly set */\n                    ctl_ir_we=1;\n                    ctl_bus_zero_oe=in_halt; ctl_bus_ff_oe=(in_intr & (im1 | im2)) | in_nmi; end\n    if (M1 & T3) begin\n                    ctl_reg_sys_we=1; ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b11; /* Write 16-bit IR */\n                    ctl_inc_cy=~pc_inc_hold; /* Increment */\n                    ctl_bus_inc_oe=1; ctl_apin_mux2=1; /* Apin sourced from AL */\n                    ctl_inc_limit6=1; /* Limit the incrementer to 6 bits */ end\n    if (M1 & T4) begin\n                    ctl_eval_cond=1; /* Evaluate flags condition based on the opcode[5:3] */ end\nend\n\n// For all undecoded instructions, at M1/T4 advance a byte to the next opcode\nif (~validPLA) begin\n    if (M1 & T4) begin setM1=1; end\nend\n\n// The last cycle of an instruction is also the first cycle of the next one\nif (setM1) begin\n    begin\n                    ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */\n                    ctl_al_we=1; /* Write a value from the register bus to the address latch */ end\nend\n\n"
  },
  {
    "path": "cpu/control/exec_matrix_compiled.vh",
    "content": "// Automatically generated by gencompile.py\n\nctl_reg_gp_we = ctl_reg_gp_we | (pla[17]&~pla[50])&(M1&T1);\nctl_reg_gp_sel_pla17npla50M1T1_2 = (pla[17]&~pla[50])&(M1&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla17npla50M1T1_2,ctl_reg_gp_sel_pla17npla50M1T1_2})&(op54);\nctl_reg_gp_hilo_pla17npla50M1T1_3 = (pla[17]&~pla[50])&(M1&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla17npla50M1T1_3,ctl_reg_gp_hilo_pla17npla50M1T1_3})&({~rsel3,rsel3});\nctl_reg_in_hi = ctl_reg_in_hi | (pla[17]&~pla[50])&(M1&T1);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[17]&~pla[50])&(M1&T1);\nctl_sw_2d = ctl_sw_2d | (pla[17]&~pla[50])&(M1&T1);\nctl_sw_1d = ctl_sw_1d | (pla[17]&~pla[50])&(M1&T1);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[17]&~pla[50])&(M1&T1);\nvalidPLA = validPLA | (pla[17]&~pla[50])&(M1&T4);\nnextM = nextM | (pla[17]&~pla[50])&(M1&T4);\nctl_mRead = ctl_mRead | (pla[17]&~pla[50])&(M1&T4);\nfMRead = fMRead | (pla[17]&~pla[50])&(M2&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[17]&~pla[50])&(M2&T1);\nctl_reg_sys_hilo_pla17npla50M2T1_3 = (pla[17]&~pla[50])&(M2&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla17npla50M2T1_3,ctl_reg_sys_hilo_pla17npla50M2T1_3})&(2'b11);\nctl_al_we = ctl_al_we | (pla[17]&~pla[50])&(M2&T1);\nfMRead = fMRead | (pla[17]&~pla[50])&(M2&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[17]&~pla[50])&(M2&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[17]&~pla[50])&(M2&T2);\nctl_reg_sys_hilo_pla17npla50M2T2_4 = (pla[17]&~pla[50])&(M2&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla17npla50M2T2_4,ctl_reg_sys_hilo_pla17npla50M2T2_4})&(2'b11);\npc_inc_hold = pc_inc_hold | (pla[17]&~pla[50])&(M2&T2)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (pla[17]&~pla[50])&(M2&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[17]&~pla[50])&(M2&T2);\nfMRead = fMRead | (pla[17]&~pla[50])&(M2&T3);\nsetM1 = setM1 | (pla[17]&~pla[50])&(M2&T3);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[61]&~pla[58]&~pla[59])&(M1&T1);\nctl_reg_gp_sel_pla61npla58npla59M1T1_2 = (pla[61]&~pla[58]&~pla[59])&(M1&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla61npla58npla59M1T1_2,ctl_reg_gp_sel_pla61npla58npla59M1T1_2})&(op54);\nctl_reg_gp_hilo_pla61npla58npla59M1T1_3 = (pla[61]&~pla[58]&~pla[59])&(M1&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla61npla58npla59M1T1_3,ctl_reg_gp_hilo_pla61npla58npla59M1T1_3})&({~rsel3,rsel3});\nctl_reg_in_hi = ctl_reg_in_hi | (pla[61]&~pla[58]&~pla[59])&(M1&T1);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[61]&~pla[58]&~pla[59])&(M1&T1);\nctl_sw_2u = ctl_sw_2u | (pla[61]&~pla[58]&~pla[59])&(M1&T1);\nctl_alu_oe = ctl_alu_oe | (pla[61]&~pla[58]&~pla[59])&(M1&T1);\nctl_alu_op1_oe = ctl_alu_op1_oe | (pla[61]&~pla[58]&~pla[59])&(M1&T1);\nvalidPLA = validPLA | (pla[61]&~pla[58]&~pla[59])&(M1&T4);\nsetM1 = setM1 | (pla[61]&~pla[58]&~pla[59])&(M1&T4);\nctl_reg_gp_sel_pla61npla58npla59M1T4_3 = (pla[61]&~pla[58]&~pla[59])&(M1&T4);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla61npla58npla59M1T4_3,ctl_reg_gp_sel_pla61npla58npla59M1T4_3})&(op21);\nctl_reg_gp_hilo_pla61npla58npla59M1T4_4 = (pla[61]&~pla[58]&~pla[59])&(M1&T4);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla61npla58npla59M1T4_4,ctl_reg_gp_hilo_pla61npla58npla59M1T4_4})&({~rsel0,rsel0});\nctl_reg_out_hi = ctl_reg_out_hi | (pla[61]&~pla[58]&~pla[59])&(M1&T4)&(~rsel0);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[61]&~pla[58]&~pla[59])&(M1&T4)&(rsel0);\nctl_sw_2u = ctl_sw_2u | (pla[61]&~pla[58]&~pla[59])&(M1&T4)&(~rsel0);\nctl_sw_2d = ctl_sw_2d | (pla[61]&~pla[58]&~pla[59])&(M1&T4)&(rsel0);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[61]&~pla[58]&~pla[59])&(M1&T4)&(~ctl_alu_bs_oe);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[61]&~pla[58]&~pla[59])&(M1&T4);\nctl_reg_gp_we = ctl_reg_gp_we | (use_ixiy&pla[58])&(M1&T1);\nctl_reg_gp_sel_use_ixiypla58M1T1_2 = (use_ixiy&pla[58])&(M1&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_use_ixiypla58M1T1_2,ctl_reg_gp_sel_use_ixiypla58M1T1_2})&(op54);\nctl_reg_gp_hilo_use_ixiypla58M1T1_3 = (use_ixiy&pla[58])&(M1&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_use_ixiypla58M1T1_3,ctl_reg_gp_hilo_use_ixiypla58M1T1_3})&({~rsel3,rsel3});\nctl_reg_in_hi = ctl_reg_in_hi | (use_ixiy&pla[58])&(M1&T1);\nctl_reg_in_lo = ctl_reg_in_lo | (use_ixiy&pla[58])&(M1&T1);\nctl_sw_2d = ctl_sw_2d | (use_ixiy&pla[58])&(M1&T1);\nctl_sw_1d = ctl_sw_1d | (use_ixiy&pla[58])&(M1&T1);\nctl_bus_db_oe = ctl_bus_db_oe | (use_ixiy&pla[58])&(M1&T1);\nvalidPLA = validPLA | (use_ixiy&pla[58])&(M1&T4);\nnextM = nextM | (use_ixiy&pla[58])&(M1&T4);\nctl_mRead = ctl_mRead | (use_ixiy&pla[58])&(M1&T4);\nfMRead = fMRead | (use_ixiy&pla[58])&(M2&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (use_ixiy&pla[58])&(M2&T1);\nctl_reg_sys_hilo_use_ixiypla58M2T1_3 = (use_ixiy&pla[58])&(M2&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_use_ixiypla58M2T1_3,ctl_reg_sys_hilo_use_ixiypla58M2T1_3})&(2'b11);\nctl_al_we = ctl_al_we | (use_ixiy&pla[58])&(M2&T1);\nfMRead = fMRead | (use_ixiy&pla[58])&(M2&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (use_ixiy&pla[58])&(M2&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (use_ixiy&pla[58])&(M2&T2);\nctl_reg_sys_hilo_use_ixiypla58M2T2_4 = (use_ixiy&pla[58])&(M2&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_use_ixiypla58M2T2_4,ctl_reg_sys_hilo_use_ixiypla58M2T2_4})&(2'b11);\npc_inc_hold = pc_inc_hold | (use_ixiy&pla[58])&(M2&T2)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (use_ixiy&pla[58])&(M2&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (use_ixiy&pla[58])&(M2&T2);\nfMRead = fMRead | (use_ixiy&pla[58])&(M2&T3);\nnextM = nextM | (use_ixiy&pla[58])&(M2&T3);\nixy_d = ixy_d | (use_ixiy&pla[58])&(M3&T1);\nixy_d = ixy_d | (use_ixiy&pla[58])&(M3&T2);\nixy_d = ixy_d | (use_ixiy&pla[58])&(M3&T3);\nixy_d = ixy_d | (use_ixiy&pla[58])&(M3&T4);\nnextM = nextM | (use_ixiy&pla[58])&(M3&T5);\nctl_mRead = ctl_mRead | (use_ixiy&pla[58])&(M3&T5);\nixy_d = ixy_d | (use_ixiy&pla[58])&(M3&T5);\nctl_reg_gp_we = ctl_reg_gp_we | (~use_ixiy&pla[58])&(M1&T1);\nctl_reg_gp_sel_nuse_ixiypla58M1T1_2 = (~use_ixiy&pla[58])&(M1&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla58M1T1_2,ctl_reg_gp_sel_nuse_ixiypla58M1T1_2})&(op54);\nctl_reg_gp_hilo_nuse_ixiypla58M1T1_3 = (~use_ixiy&pla[58])&(M1&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla58M1T1_3,ctl_reg_gp_hilo_nuse_ixiypla58M1T1_3})&({~rsel3,rsel3});\nctl_reg_in_hi = ctl_reg_in_hi | (~use_ixiy&pla[58])&(M1&T1);\nctl_reg_in_lo = ctl_reg_in_lo | (~use_ixiy&pla[58])&(M1&T1);\nctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[58])&(M1&T1);\nctl_sw_1d = ctl_sw_1d | (~use_ixiy&pla[58])&(M1&T1);\nctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[58])&(M1&T1);\nvalidPLA = validPLA | (~use_ixiy&pla[58])&(M1&T4);\nnextM = nextM | (~use_ixiy&pla[58])&(M1&T4);\nctl_mRead = ctl_mRead | (~use_ixiy&pla[58])&(M1&T4);\nfMRead = fMRead | (~use_ixiy&pla[58])&(M2&T1);\nctl_reg_gp_sel_nuse_ixiypla58M2T1_2 = (~use_ixiy&pla[58])&(M2&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla58M2T1_2,ctl_reg_gp_sel_nuse_ixiypla58M2T1_2})&(`GP_REG_HL);\nctl_reg_gp_hilo_nuse_ixiypla58M2T1_3 = (~use_ixiy&pla[58])&(M2&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla58M2T1_3,ctl_reg_gp_hilo_nuse_ixiypla58M2T1_3})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (~use_ixiy&pla[58])&(M2&T1);\nctl_al_we = ctl_al_we | (~use_ixiy&pla[58])&(M2&T1);\nfMRead = fMRead | (~use_ixiy&pla[58])&(M2&T2);\nfMRead = fMRead | (~use_ixiy&pla[58])&(M2&T3);\nsetM1 = setM1 | (~use_ixiy&pla[58])&(M2&T3);\nfMRead = fMRead | (~use_ixiy&pla[58])&(M4&T1);\nctl_bus_inc_oe = ctl_bus_inc_oe | (~use_ixiy&pla[58])&(M4&T1);\nfMRead = fMRead | (~use_ixiy&pla[58])&(M4&T2);\nfMRead = fMRead | (~use_ixiy&pla[58])&(M4&T3);\nsetM1 = setM1 | (~use_ixiy&pla[58])&(M4&T3);\nvalidPLA = validPLA | (use_ixiy&pla[59])&(M1&T4);\nnextM = nextM | (use_ixiy&pla[59])&(M1&T4);\nctl_mRead = ctl_mRead | (use_ixiy&pla[59])&(M1&T4);\nfMRead = fMRead | (use_ixiy&pla[59])&(M2&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (use_ixiy&pla[59])&(M2&T1);\nctl_reg_sys_hilo_use_ixiypla59M2T1_3 = (use_ixiy&pla[59])&(M2&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_use_ixiypla59M2T1_3,ctl_reg_sys_hilo_use_ixiypla59M2T1_3})&(2'b11);\nctl_al_we = ctl_al_we | (use_ixiy&pla[59])&(M2&T1);\nfMRead = fMRead | (use_ixiy&pla[59])&(M2&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (use_ixiy&pla[59])&(M2&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (use_ixiy&pla[59])&(M2&T2);\nctl_reg_sys_hilo_use_ixiypla59M2T2_4 = (use_ixiy&pla[59])&(M2&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_use_ixiypla59M2T2_4,ctl_reg_sys_hilo_use_ixiypla59M2T2_4})&(2'b11);\npc_inc_hold = pc_inc_hold | (use_ixiy&pla[59])&(M2&T2)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (use_ixiy&pla[59])&(M2&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (use_ixiy&pla[59])&(M2&T2);\nfMRead = fMRead | (use_ixiy&pla[59])&(M2&T3);\nnextM = nextM | (use_ixiy&pla[59])&(M2&T3);\nixy_d = ixy_d | (use_ixiy&pla[59])&(M3&T1);\nixy_d = ixy_d | (use_ixiy&pla[59])&(M3&T2);\nixy_d = ixy_d | (use_ixiy&pla[59])&(M3&T3);\nixy_d = ixy_d | (use_ixiy&pla[59])&(M3&T4);\nnextM = nextM | (use_ixiy&pla[59])&(M3&T5);\nctl_mWrite = ctl_mWrite | (use_ixiy&pla[59])&(M3&T5);\nixy_d = ixy_d | (use_ixiy&pla[59])&(M3&T5);\nvalidPLA = validPLA | (~use_ixiy&pla[59])&(M1&T4);\nnextM = nextM | (~use_ixiy&pla[59])&(M1&T4);\nctl_mWrite = ctl_mWrite | (~use_ixiy&pla[59])&(M1&T4);\nctl_reg_gp_sel_nuse_ixiypla59M1T4_4 = (~use_ixiy&pla[59])&(M1&T4);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla59M1T4_4,ctl_reg_gp_sel_nuse_ixiypla59M1T4_4})&(op21);\nctl_reg_gp_hilo_nuse_ixiypla59M1T4_5 = (~use_ixiy&pla[59])&(M1&T4);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla59M1T4_5,ctl_reg_gp_hilo_nuse_ixiypla59M1T4_5})&({~rsel0,rsel0});\nctl_reg_out_hi = ctl_reg_out_hi | (~use_ixiy&pla[59])&(M1&T4)&(~rsel0);\nctl_reg_out_lo = ctl_reg_out_lo | (~use_ixiy&pla[59])&(M1&T4)&(rsel0);\nctl_sw_2u = ctl_sw_2u | (~use_ixiy&pla[59])&(M1&T4)&(~rsel0);\nctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[59])&(M1&T4)&(rsel0);\nctl_sw_1u = ctl_sw_1u | (~use_ixiy&pla[59])&(M1&T4);\nctl_bus_db_we = ctl_bus_db_we | (~use_ixiy&pla[59])&(M1&T4);\nfMWrite = fMWrite | (~use_ixiy&pla[59])&(M2&T1);\nctl_reg_gp_sel_nuse_ixiypla59M2T1_2 = (~use_ixiy&pla[59])&(M2&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla59M2T1_2,ctl_reg_gp_sel_nuse_ixiypla59M2T1_2})&(`GP_REG_HL);\nctl_reg_gp_hilo_nuse_ixiypla59M2T1_3 = (~use_ixiy&pla[59])&(M2&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla59M2T1_3,ctl_reg_gp_hilo_nuse_ixiypla59M2T1_3})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (~use_ixiy&pla[59])&(M2&T1);\nctl_al_we = ctl_al_we | (~use_ixiy&pla[59])&(M2&T1);\nfMWrite = fMWrite | (~use_ixiy&pla[59])&(M2&T2);\nfMWrite = fMWrite | (~use_ixiy&pla[59])&(M2&T3);\nsetM1 = setM1 | (~use_ixiy&pla[59])&(M2&T3);\nfMWrite = fMWrite | (~use_ixiy&pla[59])&(M4&T1);\nctl_bus_inc_oe = ctl_bus_inc_oe | (~use_ixiy&pla[59])&(M4&T1);\nctl_reg_gp_sel_nuse_ixiypla59M4T1_3 = (~use_ixiy&pla[59])&(M4&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla59M4T1_3,ctl_reg_gp_sel_nuse_ixiypla59M4T1_3})&(op21);\nctl_reg_gp_hilo_nuse_ixiypla59M4T1_4 = (~use_ixiy&pla[59])&(M4&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla59M4T1_4,ctl_reg_gp_hilo_nuse_ixiypla59M4T1_4})&({~rsel0,rsel0});\nctl_reg_out_hi = ctl_reg_out_hi | (~use_ixiy&pla[59])&(M4&T1)&(~rsel0);\nctl_reg_out_lo = ctl_reg_out_lo | (~use_ixiy&pla[59])&(M4&T1)&(rsel0);\nctl_sw_2u = ctl_sw_2u | (~use_ixiy&pla[59])&(M4&T1)&(~rsel0);\nctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[59])&(M4&T1)&(rsel0);\nctl_sw_1u = ctl_sw_1u | (~use_ixiy&pla[59])&(M4&T1);\nctl_bus_db_we = ctl_bus_db_we | (~use_ixiy&pla[59])&(M4&T1);\nfMWrite = fMWrite | (~use_ixiy&pla[59])&(M4&T2);\nfMWrite = fMWrite | (~use_ixiy&pla[59])&(M4&T3);\nsetM1 = setM1 | (~use_ixiy&pla[59])&(M4&T3);\nvalidPLA = validPLA | (pla[40])&(M1&T4);\nnextM = nextM | (pla[40])&(M1&T4);\nctl_mRead = ctl_mRead | (pla[40])&(M1&T4);\nfMRead = fMRead | (pla[40])&(M2&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[40])&(M2&T1);\nctl_reg_sys_hilo_pla40M2T1_3 = (pla[40])&(M2&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla40M2T1_3,ctl_reg_sys_hilo_pla40M2T1_3})&(2'b11);\nctl_al_we = ctl_al_we | (pla[40])&(M2&T1);\nfMRead = fMRead | (pla[40])&(M2&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[40])&(M2&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[40])&(M2&T2);\nctl_reg_sys_hilo_pla40M2T2_4 = (pla[40])&(M2&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla40M2T2_4,ctl_reg_sys_hilo_pla40M2T2_4})&(2'b11);\npc_inc_hold = pc_inc_hold | (pla[40])&(M2&T2)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (pla[40])&(M2&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[40])&(M2&T2);\nfMRead = fMRead | (pla[40])&(M2&T3);\nnextM = nextM | (pla[40])&(M2&T3);\nctl_mRead = ctl_mRead | (pla[40])&(M2&T3);\nfMRead = fMRead | (pla[40])&(M3&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[40])&(M3&T1);\nctl_reg_sys_hilo_pla40M3T1_3 = (pla[40])&(M3&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla40M3T1_3,ctl_reg_sys_hilo_pla40M3T1_3})&(2'b11);\nctl_al_we = ctl_al_we | (pla[40])&(M3&T1);\nixy_d = ixy_d | (pla[40])&(M3&T1);\nfMRead = fMRead | (pla[40])&(M3&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[40])&(M3&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[40])&(M3&T2);\nctl_reg_sys_hilo_pla40M3T2_4 = (pla[40])&(M3&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla40M3T2_4,ctl_reg_sys_hilo_pla40M3T2_4})&(2'b11);\npc_inc_hold = pc_inc_hold | (pla[40])&(M3&T2)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (pla[40])&(M3&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[40])&(M3&T2);\nixy_d = ixy_d | (pla[40])&(M3&T2);\nfMRead = fMRead | (pla[40])&(M3&T3);\nixy_d = ixy_d | (pla[40])&(M3&T3);\nixy_d = ixy_d | (pla[40])&(M3&T4);\nnextM = nextM | (pla[40])&(M3&T5);\nctl_mWrite = ctl_mWrite | (pla[40])&(M3&T5);\nixy_d = ixy_d | (pla[40])&(M3&T5);\nvalidPLA = validPLA | (pla[50]&~pla[40])&(M1&T4);\nnextM = nextM | (pla[50]&~pla[40])&(M1&T4);\nctl_mRead = ctl_mRead | (pla[50]&~pla[40])&(M1&T4);\nfMRead = fMRead | (pla[50]&~pla[40])&(M2&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[50]&~pla[40])&(M2&T1);\nctl_reg_sys_hilo_pla50npla40M2T1_3 = (pla[50]&~pla[40])&(M2&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla50npla40M2T1_3,ctl_reg_sys_hilo_pla50npla40M2T1_3})&(2'b11);\nctl_al_we = ctl_al_we | (pla[50]&~pla[40])&(M2&T1);\nfMRead = fMRead | (pla[50]&~pla[40])&(M2&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[50]&~pla[40])&(M2&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[50]&~pla[40])&(M2&T2);\nctl_reg_sys_hilo_pla50npla40M2T2_4 = (pla[50]&~pla[40])&(M2&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla50npla40M2T2_4,ctl_reg_sys_hilo_pla50npla40M2T2_4})&(2'b11);\npc_inc_hold = pc_inc_hold | (pla[50]&~pla[40])&(M2&T2)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (pla[50]&~pla[40])&(M2&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[50]&~pla[40])&(M2&T2);\nfMRead = fMRead | (pla[50]&~pla[40])&(M2&T3);\nnextM = nextM | (pla[50]&~pla[40])&(M2&T3);\nctl_mWrite = ctl_mWrite | (pla[50]&~pla[40])&(M2&T3);\nfMWrite = fMWrite | (pla[50]&~pla[40])&(M3&T1);\nctl_reg_gp_sel_pla50npla40M3T1_2 = (pla[50]&~pla[40])&(M3&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla50npla40M3T1_2,ctl_reg_gp_sel_pla50npla40M3T1_2})&(`GP_REG_HL);\nctl_reg_gp_hilo_pla50npla40M3T1_3 = (pla[50]&~pla[40])&(M3&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla50npla40M3T1_3,ctl_reg_gp_hilo_pla50npla40M3T1_3})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[50]&~pla[40])&(M3&T1);\nctl_al_we = ctl_al_we | (pla[50]&~pla[40])&(M3&T1);\nfMWrite = fMWrite | (pla[50]&~pla[40])&(M3&T2);\nfMWrite = fMWrite | (pla[50]&~pla[40])&(M3&T3);\nsetM1 = setM1 | (pla[50]&~pla[40])&(M3&T3);\nfMWrite = fMWrite | (pla[50]&~pla[40])&(M4&T1);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[50]&~pla[40])&(M4&T1);\nfMWrite = fMWrite | (pla[50]&~pla[40])&(M4&T2);\nfMWrite = fMWrite | (pla[50]&~pla[40])&(M4&T3);\nsetM1 = setM1 | (pla[50]&~pla[40])&(M4&T3);\nvalidPLA = validPLA | (pla[8]&pla[13])&(M1&T4);\nnextM = nextM | (pla[8]&pla[13])&(M1&T4);\nctl_mWrite = ctl_mWrite | (pla[8]&pla[13])&(M1&T4);\nctl_reg_gp_sel_pla8pla13M1T4_4 = (pla[8]&pla[13])&(M1&T4);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla8pla13M1T4_4,ctl_reg_gp_sel_pla8pla13M1T4_4})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla8pla13M1T4_5 = (pla[8]&pla[13])&(M1&T4);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla8pla13M1T4_5,ctl_reg_gp_hilo_pla8pla13M1T4_5})&(2'b10);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[8]&pla[13])&(M1&T4);\nctl_sw_2u = ctl_sw_2u | (pla[8]&pla[13])&(M1&T4);\nctl_sw_1u = ctl_sw_1u | (pla[8]&pla[13])&(M1&T4);\nctl_bus_db_we = ctl_bus_db_we | (pla[8]&pla[13])&(M1&T4);\nfMWrite = fMWrite | (pla[8]&pla[13])&(M2&T1);\nctl_reg_gp_sel_pla8pla13M2T1_2 = (pla[8]&pla[13])&(M2&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla8pla13M2T1_2,ctl_reg_gp_sel_pla8pla13M2T1_2})&(op54);\nctl_reg_gp_hilo_pla8pla13M2T1_3 = (pla[8]&pla[13])&(M2&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla8pla13M2T1_3,ctl_reg_gp_hilo_pla8pla13M2T1_3})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[8]&pla[13])&(M2&T1);\nctl_al_we = ctl_al_we | (pla[8]&pla[13])&(M2&T1);\nfMWrite = fMWrite | (pla[8]&pla[13])&(M2&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[8]&pla[13])&(M2&T2);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[8]&pla[13])&(M2&T2);\nctl_reg_sys_hilo_pla8pla13M2T2_4 = (pla[8]&pla[13])&(M2&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla8pla13M2T2_4,ctl_reg_sys_hilo_pla8pla13M2T2_4})&(2'b11);\nctl_sw_4u = ctl_sw_4u | (pla[8]&pla[13])&(M2&T2);\nctl_inc_cy = ctl_inc_cy | (pla[8]&pla[13])&(M2&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[8]&pla[13])&(M2&T2);\nfMWrite = fMWrite | (pla[8]&pla[13])&(M2&T3);\nsetM1 = setM1 | (pla[8]&pla[13])&(M2&T3);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[8]&~pla[13])&(M1&T1);\nctl_reg_gp_sel_pla8npla13M1T1_2 = (pla[8]&~pla[13])&(M1&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla8npla13M1T1_2,ctl_reg_gp_sel_pla8npla13M1T1_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla8npla13M1T1_3 = (pla[8]&~pla[13])&(M1&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla8npla13M1T1_3,ctl_reg_gp_hilo_pla8npla13M1T1_3})&(2'b10);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[8]&~pla[13])&(M1&T1);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[8]&~pla[13])&(M1&T1);\nctl_sw_2d = ctl_sw_2d | (pla[8]&~pla[13])&(M1&T1);\nctl_sw_1d = ctl_sw_1d | (pla[8]&~pla[13])&(M1&T1);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[8]&~pla[13])&(M1&T1);\nvalidPLA = validPLA | (pla[8]&~pla[13])&(M1&T4);\nnextM = nextM | (pla[8]&~pla[13])&(M1&T4);\nctl_mRead = ctl_mRead | (pla[8]&~pla[13])&(M1&T4);\nfMRead = fMRead | (pla[8]&~pla[13])&(M2&T1);\nctl_reg_gp_sel_pla8npla13M2T1_2 = (pla[8]&~pla[13])&(M2&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla8npla13M2T1_2,ctl_reg_gp_sel_pla8npla13M2T1_2})&(op54);\nctl_reg_gp_hilo_pla8npla13M2T1_3 = (pla[8]&~pla[13])&(M2&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla8npla13M2T1_3,ctl_reg_gp_hilo_pla8npla13M2T1_3})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[8]&~pla[13])&(M2&T1);\nctl_al_we = ctl_al_we | (pla[8]&~pla[13])&(M2&T1);\nfMRead = fMRead | (pla[8]&~pla[13])&(M2&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[8]&~pla[13])&(M2&T2);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[8]&~pla[13])&(M2&T2);\nctl_reg_sys_hilo_pla8npla13M2T2_4 = (pla[8]&~pla[13])&(M2&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla8npla13M2T2_4,ctl_reg_sys_hilo_pla8npla13M2T2_4})&(2'b11);\nctl_sw_4u = ctl_sw_4u | (pla[8]&~pla[13])&(M2&T2);\nctl_inc_cy = ctl_inc_cy | (pla[8]&~pla[13])&(M2&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[8]&~pla[13])&(M2&T2);\nfMRead = fMRead | (pla[8]&~pla[13])&(M2&T3);\nsetM1 = setM1 | (pla[8]&~pla[13])&(M2&T3);\nvalidPLA = validPLA | (pla[38]&pla[13])&(M1&T4);\nnextM = nextM | (pla[38]&pla[13])&(M1&T4);\nctl_mRead = ctl_mRead | (pla[38]&pla[13])&(M1&T4);\nfMRead = fMRead | (pla[38]&pla[13])&(M2&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[38]&pla[13])&(M2&T1);\nctl_reg_sys_hilo_pla38pla13M2T1_3 = (pla[38]&pla[13])&(M2&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla38pla13M2T1_3,ctl_reg_sys_hilo_pla38pla13M2T1_3})&(2'b11);\nctl_al_we = ctl_al_we | (pla[38]&pla[13])&(M2&T1);\nfMRead = fMRead | (pla[38]&pla[13])&(M2&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[38]&pla[13])&(M2&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[38]&pla[13])&(M2&T2);\nctl_reg_sys_hilo_pla38pla13M2T2_4 = (pla[38]&pla[13])&(M2&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla38pla13M2T2_4,ctl_reg_sys_hilo_pla38pla13M2T2_4})&(2'b11);\npc_inc_hold = pc_inc_hold | (pla[38]&pla[13])&(M2&T2)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (pla[38]&pla[13])&(M2&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[38]&pla[13])&(M2&T2);\nfMRead = fMRead | (pla[38]&pla[13])&(M2&T3);\nnextM = nextM | (pla[38]&pla[13])&(M2&T3);\nctl_mRead = ctl_mRead | (pla[38]&pla[13])&(M2&T3);\nctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (pla[38]&pla[13])&(M2&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[38]&pla[13])&(M2&T3);\nctl_reg_sys_hilo_pla38pla13M2T3_6 = (pla[38]&pla[13])&(M2&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla38pla13M2T3_6,ctl_reg_sys_hilo_pla38pla13M2T3_6})&({ctl_reg_sys_hilo[1],1'b1});\nctl_reg_in_lo = ctl_reg_in_lo | (pla[38]&pla[13])&(M2&T3);\nctl_sw_2d = ctl_sw_2d | (pla[38]&pla[13])&(M2&T3);\nctl_sw_1d = ctl_sw_1d | (pla[38]&pla[13])&(M2&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[38]&pla[13])&(M2&T3);\nfMRead = fMRead | (pla[38]&pla[13])&(M3&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[38]&pla[13])&(M3&T1);\nctl_reg_sys_hilo_pla38pla13M3T1_3 = (pla[38]&pla[13])&(M3&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla38pla13M3T1_3,ctl_reg_sys_hilo_pla38pla13M3T1_3})&(2'b11);\nctl_al_we = ctl_al_we | (pla[38]&pla[13])&(M3&T1);\nfMRead = fMRead | (pla[38]&pla[13])&(M3&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[38]&pla[13])&(M3&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[38]&pla[13])&(M3&T2);\nctl_reg_sys_hilo_pla38pla13M3T2_4 = (pla[38]&pla[13])&(M3&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla38pla13M3T2_4,ctl_reg_sys_hilo_pla38pla13M3T2_4})&(2'b11);\npc_inc_hold = pc_inc_hold | (pla[38]&pla[13])&(M3&T2)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (pla[38]&pla[13])&(M3&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[38]&pla[13])&(M3&T2);\nfMRead = fMRead | (pla[38]&pla[13])&(M3&T3);\nnextM = nextM | (pla[38]&pla[13])&(M3&T3);\nctl_mWrite = ctl_mWrite | (pla[38]&pla[13])&(M3&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[38]&pla[13])&(M3&T3);\nctl_reg_sys_hilo_pla38pla13M3T3_5 = (pla[38]&pla[13])&(M3&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla38pla13M3T3_5,ctl_reg_sys_hilo_pla38pla13M3T3_5})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[38]&pla[13])&(M3&T3);\nctl_al_we = ctl_al_we | (pla[38]&pla[13])&(M3&T3);\nctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (pla[38]&pla[13])&(M3&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[38]&pla[13])&(M3&T3);\nctl_reg_sys_hilo_pla38pla13M3T3_10 = (pla[38]&pla[13])&(M3&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla38pla13M3T3_10,ctl_reg_sys_hilo_pla38pla13M3T3_10})&({1'b1,ctl_reg_sys_hilo[0]});\nctl_reg_in_hi = ctl_reg_in_hi | (pla[38]&pla[13])&(M3&T3);\nctl_sw_2d = ctl_sw_2d | (pla[38]&pla[13])&(M3&T3);\nctl_sw_1d = ctl_sw_1d | (pla[38]&pla[13])&(M3&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[38]&pla[13])&(M3&T3);\nfMWrite = fMWrite | (pla[38]&pla[13])&(M4&T1);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[38]&pla[13])&(M4&T1);\nctl_reg_gp_sel_pla38pla13M4T1_3 = (pla[38]&pla[13])&(M4&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla38pla13M4T1_3,ctl_reg_gp_sel_pla38pla13M4T1_3})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla38pla13M4T1_4 = (pla[38]&pla[13])&(M4&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla38pla13M4T1_4,ctl_reg_gp_hilo_pla38pla13M4T1_4})&(2'b10);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[38]&pla[13])&(M4&T1);\nctl_sw_2u = ctl_sw_2u | (pla[38]&pla[13])&(M4&T1);\nctl_sw_1u = ctl_sw_1u | (pla[38]&pla[13])&(M4&T1);\nctl_bus_db_we = ctl_bus_db_we | (pla[38]&pla[13])&(M4&T1);\nfMWrite = fMWrite | (pla[38]&pla[13])&(M4&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[38]&pla[13])&(M4&T2);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[38]&pla[13])&(M4&T2);\nctl_reg_sys_hilo_pla38pla13M4T2_4 = (pla[38]&pla[13])&(M4&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla38pla13M4T2_4,ctl_reg_sys_hilo_pla38pla13M4T2_4})&(2'b11);\nctl_sw_4u = ctl_sw_4u | (pla[38]&pla[13])&(M4&T2);\nctl_inc_cy = ctl_inc_cy | (pla[38]&pla[13])&(M4&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[38]&pla[13])&(M4&T2);\nfMWrite = fMWrite | (pla[38]&pla[13])&(M4&T3);\nsetM1 = setM1 | (pla[38]&pla[13])&(M4&T3);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[38]&~pla[13])&(M1&T1);\nctl_reg_gp_sel_pla38npla13M1T1_2 = (pla[38]&~pla[13])&(M1&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla38npla13M1T1_2,ctl_reg_gp_sel_pla38npla13M1T1_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla38npla13M1T1_3 = (pla[38]&~pla[13])&(M1&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla38npla13M1T1_3,ctl_reg_gp_hilo_pla38npla13M1T1_3})&(2'b10);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[38]&~pla[13])&(M1&T1);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[38]&~pla[13])&(M1&T1);\nctl_sw_2d = ctl_sw_2d | (pla[38]&~pla[13])&(M1&T1);\nctl_sw_1d = ctl_sw_1d | (pla[38]&~pla[13])&(M1&T1);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[38]&~pla[13])&(M1&T1);\nvalidPLA = validPLA | (pla[38]&~pla[13])&(M1&T4);\nnextM = nextM | (pla[38]&~pla[13])&(M1&T4);\nctl_mRead = ctl_mRead | (pla[38]&~pla[13])&(M1&T4);\nfMRead = fMRead | (pla[38]&~pla[13])&(M2&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[38]&~pla[13])&(M2&T1);\nctl_reg_sys_hilo_pla38npla13M2T1_3 = (pla[38]&~pla[13])&(M2&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla38npla13M2T1_3,ctl_reg_sys_hilo_pla38npla13M2T1_3})&(2'b11);\nctl_al_we = ctl_al_we | (pla[38]&~pla[13])&(M2&T1);\nfMRead = fMRead | (pla[38]&~pla[13])&(M2&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[38]&~pla[13])&(M2&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[38]&~pla[13])&(M2&T2);\nctl_reg_sys_hilo_pla38npla13M2T2_4 = (pla[38]&~pla[13])&(M2&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla38npla13M2T2_4,ctl_reg_sys_hilo_pla38npla13M2T2_4})&(2'b11);\npc_inc_hold = pc_inc_hold | (pla[38]&~pla[13])&(M2&T2)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (pla[38]&~pla[13])&(M2&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[38]&~pla[13])&(M2&T2);\nfMRead = fMRead | (pla[38]&~pla[13])&(M2&T3);\nnextM = nextM | (pla[38]&~pla[13])&(M2&T3);\nctl_mRead = ctl_mRead | (pla[38]&~pla[13])&(M2&T3);\nctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (pla[38]&~pla[13])&(M2&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[38]&~pla[13])&(M2&T3);\nctl_reg_sys_hilo_pla38npla13M2T3_6 = (pla[38]&~pla[13])&(M2&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla38npla13M2T3_6,ctl_reg_sys_hilo_pla38npla13M2T3_6})&({ctl_reg_sys_hilo[1],1'b1});\nctl_reg_in_lo = ctl_reg_in_lo | (pla[38]&~pla[13])&(M2&T3);\nctl_sw_2d = ctl_sw_2d | (pla[38]&~pla[13])&(M2&T3);\nctl_sw_1d = ctl_sw_1d | (pla[38]&~pla[13])&(M2&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[38]&~pla[13])&(M2&T3);\nfMRead = fMRead | (pla[38]&~pla[13])&(M3&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[38]&~pla[13])&(M3&T1);\nctl_reg_sys_hilo_pla38npla13M3T1_3 = (pla[38]&~pla[13])&(M3&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla38npla13M3T1_3,ctl_reg_sys_hilo_pla38npla13M3T1_3})&(2'b11);\nctl_al_we = ctl_al_we | (pla[38]&~pla[13])&(M3&T1);\nfMRead = fMRead | (pla[38]&~pla[13])&(M3&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[38]&~pla[13])&(M3&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[38]&~pla[13])&(M3&T2);\nctl_reg_sys_hilo_pla38npla13M3T2_4 = (pla[38]&~pla[13])&(M3&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla38npla13M3T2_4,ctl_reg_sys_hilo_pla38npla13M3T2_4})&(2'b11);\npc_inc_hold = pc_inc_hold | (pla[38]&~pla[13])&(M3&T2)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (pla[38]&~pla[13])&(M3&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[38]&~pla[13])&(M3&T2);\nfMRead = fMRead | (pla[38]&~pla[13])&(M3&T3);\nnextM = nextM | (pla[38]&~pla[13])&(M3&T3);\nctl_mRead = ctl_mRead | (pla[38]&~pla[13])&(M3&T3);\nctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (pla[38]&~pla[13])&(M3&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[38]&~pla[13])&(M3&T3);\nctl_reg_sys_hilo_pla38npla13M3T3_6 = (pla[38]&~pla[13])&(M3&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla38npla13M3T3_6,ctl_reg_sys_hilo_pla38npla13M3T3_6})&({1'b1,ctl_reg_sys_hilo[0]});\nctl_reg_in_hi = ctl_reg_in_hi | (pla[38]&~pla[13])&(M3&T3);\nctl_sw_2d = ctl_sw_2d | (pla[38]&~pla[13])&(M3&T3);\nctl_sw_1d = ctl_sw_1d | (pla[38]&~pla[13])&(M3&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[38]&~pla[13])&(M3&T3);\nfMRead = fMRead | (pla[38]&~pla[13])&(M4&T1);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[38]&~pla[13])&(M4&T1);\nctl_reg_sys_hilo_pla38npla13M4T1_3 = (pla[38]&~pla[13])&(M4&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla38npla13M4T1_3,ctl_reg_sys_hilo_pla38npla13M4T1_3})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[38]&~pla[13])&(M4&T1);\nctl_al_we = ctl_al_we | (pla[38]&~pla[13])&(M4&T1);\nfMRead = fMRead | (pla[38]&~pla[13])&(M4&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[38]&~pla[13])&(M4&T2);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[38]&~pla[13])&(M4&T2);\nctl_reg_sys_hilo_pla38npla13M4T2_4 = (pla[38]&~pla[13])&(M4&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla38npla13M4T2_4,ctl_reg_sys_hilo_pla38npla13M4T2_4})&(2'b11);\nctl_sw_4u = ctl_sw_4u | (pla[38]&~pla[13])&(M4&T2);\nctl_inc_cy = ctl_inc_cy | (pla[38]&~pla[13])&(M4&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[38]&~pla[13])&(M4&T2);\nfMRead = fMRead | (pla[38]&~pla[13])&(M4&T3);\nsetM1 = setM1 | (pla[38]&~pla[13])&(M4&T3);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[83])&(M1&T1);\nctl_reg_gp_sel_pla83M1T1_2 = (pla[83])&(M1&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla83M1T1_2,ctl_reg_gp_sel_pla83M1T1_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla83M1T1_3 = (pla[83])&(M1&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla83M1T1_3,ctl_reg_gp_hilo_pla83M1T1_3})&(2'b10);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[83])&(M1&T1);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[83])&(M1&T1);\nctl_flags_alu = ctl_flags_alu | (pla[83])&(M1&T1);\nctl_alu_oe = ctl_alu_oe | (pla[83])&(M1&T1);\nctl_alu_res_oe = ctl_alu_res_oe | (pla[83])&(M1&T1);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[83])&(M1&T1);\nctl_alu_core_R = ctl_alu_core_R | (pla[83])&(M1&T1);\nctl_alu_core_V = ctl_alu_core_V | (pla[83])&(M1&T1);\nctl_alu_core_S = ctl_alu_core_S | (pla[83])&(M1&T1);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[83])&(M1&T1);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[83])&(M1&T1);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[83])&(M1&T1);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[83])&(M1&T1);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[83])&(M1&T1);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[83])&(M1&T1);\nctl_pf_sel_pla83M1T1_19 = (pla[83])&(M1&T1);\nctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_pla83M1T1_19,ctl_pf_sel_pla83M1T1_19})&(`PFSEL_IFF2);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[83])&(M1&T1);\nctl_flags_nf_clr = ctl_flags_nf_clr | (pla[83])&(M1&T1);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[83])&(M1&T2);\nctl_reg_gp_sel_pla83M1T2_2 = (pla[83])&(M1&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla83M1T2_2,ctl_reg_gp_sel_pla83M1T2_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla83M1T2_3 = (pla[83])&(M1&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla83M1T2_3,ctl_reg_gp_hilo_pla83M1T2_3})&(2'b01);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[83])&(M1&T2);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[83])&(M1&T2);\nctl_flags_oe = ctl_flags_oe | (pla[83])&(M1&T2);\nctl_reg_gp_sel_pla83M1T3_1 = (pla[83])&(M1&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla83M1T3_1,ctl_reg_gp_sel_pla83M1T3_1})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla83M1T3_2 = (pla[83])&(M1&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla83M1T3_2,ctl_reg_gp_hilo_pla83M1T3_2})&(2'b11);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[83])&(M1&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[83])&(M1&T3);\nctl_flags_bus = ctl_flags_bus | (pla[83])&(M1&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[83])&(M1&T3)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[83])&(M1&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[83])&(M1&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[83])&(M1&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[83])&(M1&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[83])&(M1&T3);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[83])&(M1&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[83])&(M1&T3);\nctl_flags_cf_we = ctl_flags_cf_we | (pla[83])&(M1&T3);\nvalidPLA = validPLA | (pla[83])&(M1&T4);\nctl_reg_sel_ir = ctl_reg_sel_ir | (pla[83])&(M1&T4);\nctl_reg_sys_hilo_pla83M1T4_3 = (pla[83])&(M1&T4);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla83M1T4_3,ctl_reg_sys_hilo_pla83M1T4_3})&({~op3,op3});\nctl_sw_4u = ctl_sw_4u | (pla[83])&(M1&T4);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[83])&(M1&T4)&(~rsel3);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[83])&(M1&T4)&(rsel3);\nctl_sw_2u = ctl_sw_2u | (pla[83])&(M1&T4)&(~rsel3);\nctl_sw_2d = ctl_sw_2d | (pla[83])&(M1&T4)&(rsel3);\nctl_flags_alu = ctl_flags_alu | (pla[83])&(M1&T4);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[83])&(M1&T4)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[83])&(M1&T4);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[83])&(M1&T4);\nctl_alu_op_low = ctl_alu_op_low | (pla[83])&(M1&T4);\nctl_alu_core_R = ctl_alu_core_R | (pla[83])&(M1&T4);\nctl_alu_core_V = ctl_alu_core_V | (pla[83])&(M1&T4);\nctl_alu_core_S = ctl_alu_core_S | (pla[83])&(M1&T4);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[83])&(M1&T4);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[83])&(M1&T4);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[83])&(M1&T4);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[83])&(M1&T4);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[83])&(M1&T4);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[83])&(M1&T4);\nctl_flags_nf_clr = ctl_flags_nf_clr | (pla[83])&(M1&T4);\nsetM1 = setM1 | (pla[83])&(M1&T5);\nctl_reg_gp_sel_pla57M1T3_1 = (pla[57])&(M1&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla57M1T3_1,ctl_reg_gp_sel_pla57M1T3_1})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla57M1T3_2 = (pla[57])&(M1&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla57M1T3_2,ctl_reg_gp_hilo_pla57M1T3_2})&(2'b11);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[57])&(M1&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[57])&(M1&T3);\nctl_flags_bus = ctl_flags_bus | (pla[57])&(M1&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[57])&(M1&T3)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[57])&(M1&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[57])&(M1&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[57])&(M1&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[57])&(M1&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[57])&(M1&T3);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[57])&(M1&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[57])&(M1&T3);\nctl_flags_cf_we = ctl_flags_cf_we | (pla[57])&(M1&T3);\nvalidPLA = validPLA | (pla[57])&(M1&T4);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[57])&(M1&T4);\nctl_reg_sel_ir = ctl_reg_sel_ir | (pla[57])&(M1&T4);\nctl_reg_sys_hilo_pla57M1T4_4 = (pla[57])&(M1&T4);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla57M1T4_4,ctl_reg_sys_hilo_pla57M1T4_4})&({~op3,op3});\nctl_sw_4d = ctl_sw_4d | (pla[57])&(M1&T4);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[57])&(M1&T4);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[57])&(M1&T4);\nctl_sw_2u = ctl_sw_2u | (pla[57])&(M1&T4);\nctl_alu_oe = ctl_alu_oe | (pla[57])&(M1&T4);\nctl_alu_op1_oe = ctl_alu_op1_oe | (pla[57])&(M1&T4);\nsetM1 = setM1 | (pla[57])&(M1&T5);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[7])&(M1&T1);\nctl_reg_gp_sel_pla7M1T1_2 = (pla[7])&(M1&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla7M1T1_2,ctl_reg_gp_sel_pla7M1T1_2})&(op54);\nctl_reg_gp_hilo_pla7M1T1_3 = (pla[7])&(M1&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla7M1T1_3,ctl_reg_gp_hilo_pla7M1T1_3})&(2'b10);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[7])&(M1&T1);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[7])&(M1&T1);\nctl_sw_2d = ctl_sw_2d | (pla[7])&(M1&T1);\nctl_sw_1d = ctl_sw_1d | (pla[7])&(M1&T1);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[7])&(M1&T1);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[7])&(M1&T1);\nvalidPLA = validPLA | (pla[7])&(M1&T4);\nnextM = nextM | (pla[7])&(M1&T4);\nctl_mRead = ctl_mRead | (pla[7])&(M1&T4);\nfMRead = fMRead | (pla[7])&(M2&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[7])&(M2&T1);\nctl_reg_sys_hilo_pla7M2T1_3 = (pla[7])&(M2&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla7M2T1_3,ctl_reg_sys_hilo_pla7M2T1_3})&(2'b11);\nctl_al_we = ctl_al_we | (pla[7])&(M2&T1);\nfMRead = fMRead | (pla[7])&(M2&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[7])&(M2&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[7])&(M2&T2);\nctl_reg_sys_hilo_pla7M2T2_4 = (pla[7])&(M2&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla7M2T2_4,ctl_reg_sys_hilo_pla7M2T2_4})&(2'b11);\npc_inc_hold = pc_inc_hold | (pla[7])&(M2&T2)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (pla[7])&(M2&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[7])&(M2&T2);\nfMRead = fMRead | (pla[7])&(M2&T3);\nnextM = nextM | (pla[7])&(M2&T3);\nctl_mRead = ctl_mRead | (pla[7])&(M2&T3);\nfMRead = fMRead | (pla[7])&(M3&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[7])&(M3&T1);\nctl_reg_sys_hilo_pla7M3T1_3 = (pla[7])&(M3&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla7M3T1_3,ctl_reg_sys_hilo_pla7M3T1_3})&(2'b11);\nctl_al_we = ctl_al_we | (pla[7])&(M3&T1);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[7])&(M3&T1);\nctl_reg_gp_sel_pla7M3T1_6 = (pla[7])&(M3&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla7M3T1_6,ctl_reg_gp_sel_pla7M3T1_6})&(op54);\nctl_reg_gp_hilo_pla7M3T1_7 = (pla[7])&(M3&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla7M3T1_7,ctl_reg_gp_hilo_pla7M3T1_7})&(2'b01);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[7])&(M3&T1);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[7])&(M3&T1);\nctl_sw_2d = ctl_sw_2d | (pla[7])&(M3&T1);\nctl_sw_1d = ctl_sw_1d | (pla[7])&(M3&T1);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[7])&(M3&T1);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[7])&(M3&T1);\nfMRead = fMRead | (pla[7])&(M3&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[7])&(M3&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[7])&(M3&T2);\nctl_reg_sys_hilo_pla7M3T2_4 = (pla[7])&(M3&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla7M3T2_4,ctl_reg_sys_hilo_pla7M3T2_4})&(2'b11);\npc_inc_hold = pc_inc_hold | (pla[7])&(M3&T2)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (pla[7])&(M3&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[7])&(M3&T2);\nfMRead = fMRead | (pla[7])&(M3&T3);\nsetM1 = setM1 | (pla[7])&(M3&T3);\nvalidPLA = validPLA | (pla[30]&pla[13])&(M1&T4);\nnextM = nextM | (pla[30]&pla[13])&(M1&T4);\nctl_mRead = ctl_mRead | (pla[30]&pla[13])&(M1&T4);\nfMRead = fMRead | (pla[30]&pla[13])&(M2&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[30]&pla[13])&(M2&T1);\nctl_reg_sys_hilo_pla30pla13M2T1_3 = (pla[30]&pla[13])&(M2&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla30pla13M2T1_3,ctl_reg_sys_hilo_pla30pla13M2T1_3})&(2'b11);\nctl_al_we = ctl_al_we | (pla[30]&pla[13])&(M2&T1);\nfMRead = fMRead | (pla[30]&pla[13])&(M2&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[30]&pla[13])&(M2&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[30]&pla[13])&(M2&T2);\nctl_reg_sys_hilo_pla30pla13M2T2_4 = (pla[30]&pla[13])&(M2&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla30pla13M2T2_4,ctl_reg_sys_hilo_pla30pla13M2T2_4})&(2'b11);\npc_inc_hold = pc_inc_hold | (pla[30]&pla[13])&(M2&T2)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (pla[30]&pla[13])&(M2&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[30]&pla[13])&(M2&T2);\nfMRead = fMRead | (pla[30]&pla[13])&(M2&T3);\nnextM = nextM | (pla[30]&pla[13])&(M2&T3);\nctl_mRead = ctl_mRead | (pla[30]&pla[13])&(M2&T3);\nctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (pla[30]&pla[13])&(M2&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[30]&pla[13])&(M2&T3);\nctl_reg_sys_hilo_pla30pla13M2T3_6 = (pla[30]&pla[13])&(M2&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla30pla13M2T3_6,ctl_reg_sys_hilo_pla30pla13M2T3_6})&({ctl_reg_sys_hilo[1],1'b1});\nctl_reg_in_lo = ctl_reg_in_lo | (pla[30]&pla[13])&(M2&T3);\nctl_sw_2d = ctl_sw_2d | (pla[30]&pla[13])&(M2&T3);\nctl_sw_1d = ctl_sw_1d | (pla[30]&pla[13])&(M2&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[30]&pla[13])&(M2&T3);\nfMRead = fMRead | (pla[30]&pla[13])&(M3&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[30]&pla[13])&(M3&T1);\nctl_reg_sys_hilo_pla30pla13M3T1_3 = (pla[30]&pla[13])&(M3&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla30pla13M3T1_3,ctl_reg_sys_hilo_pla30pla13M3T1_3})&(2'b11);\nctl_al_we = ctl_al_we | (pla[30]&pla[13])&(M3&T1);\nfMRead = fMRead | (pla[30]&pla[13])&(M3&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[30]&pla[13])&(M3&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[30]&pla[13])&(M3&T2);\nctl_reg_sys_hilo_pla30pla13M3T2_4 = (pla[30]&pla[13])&(M3&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla30pla13M3T2_4,ctl_reg_sys_hilo_pla30pla13M3T2_4})&(2'b11);\npc_inc_hold = pc_inc_hold | (pla[30]&pla[13])&(M3&T2)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (pla[30]&pla[13])&(M3&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[30]&pla[13])&(M3&T2);\nfMRead = fMRead | (pla[30]&pla[13])&(M3&T3);\nnextM = nextM | (pla[30]&pla[13])&(M3&T3);\nctl_mWrite = ctl_mWrite | (pla[30]&pla[13])&(M3&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[30]&pla[13])&(M3&T3);\nctl_reg_sys_hilo_pla30pla13M3T3_5 = (pla[30]&pla[13])&(M3&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla30pla13M3T3_5,ctl_reg_sys_hilo_pla30pla13M3T3_5})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[30]&pla[13])&(M3&T3);\nctl_al_we = ctl_al_we | (pla[30]&pla[13])&(M3&T3);\nctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (pla[30]&pla[13])&(M3&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[30]&pla[13])&(M3&T3);\nctl_reg_sys_hilo_pla30pla13M3T3_10 = (pla[30]&pla[13])&(M3&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla30pla13M3T3_10,ctl_reg_sys_hilo_pla30pla13M3T3_10})&({1'b1,ctl_reg_sys_hilo[0]});\nctl_reg_in_hi = ctl_reg_in_hi | (pla[30]&pla[13])&(M3&T3);\nctl_sw_2d = ctl_sw_2d | (pla[30]&pla[13])&(M3&T3);\nctl_sw_1d = ctl_sw_1d | (pla[30]&pla[13])&(M3&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[30]&pla[13])&(M3&T3);\nfMWrite = fMWrite | (pla[30]&pla[13])&(M4&T1);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[30]&pla[13])&(M4&T1);\nctl_reg_gp_sel_pla30pla13M4T1_3 = (pla[30]&pla[13])&(M4&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla30pla13M4T1_3,ctl_reg_gp_sel_pla30pla13M4T1_3})&(op54);\nctl_reg_gp_hilo_pla30pla13M4T1_4 = (pla[30]&pla[13])&(M4&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla30pla13M4T1_4,ctl_reg_gp_hilo_pla30pla13M4T1_4})&(2'b01);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[30]&pla[13])&(M4&T1);\nctl_sw_1u = ctl_sw_1u | (pla[30]&pla[13])&(M4&T1);\nctl_bus_db_we = ctl_bus_db_we | (pla[30]&pla[13])&(M4&T1);\nfMWrite = fMWrite | (pla[30]&pla[13])&(M4&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[30]&pla[13])&(M4&T2);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[30]&pla[13])&(M4&T2);\nctl_reg_sys_hilo_pla30pla13M4T2_4 = (pla[30]&pla[13])&(M4&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla30pla13M4T2_4,ctl_reg_sys_hilo_pla30pla13M4T2_4})&(2'b11);\nctl_sw_4u = ctl_sw_4u | (pla[30]&pla[13])&(M4&T2);\nctl_inc_cy = ctl_inc_cy | (pla[30]&pla[13])&(M4&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[30]&pla[13])&(M4&T2);\nfMWrite = fMWrite | (pla[30]&pla[13])&(M4&T3);\nnextM = nextM | (pla[30]&pla[13])&(M4&T3);\nctl_mWrite = ctl_mWrite | (pla[30]&pla[13])&(M4&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[30]&pla[13])&(M4&T3);\nctl_reg_sys_hilo_pla30pla13M4T3_5 = (pla[30]&pla[13])&(M4&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla30pla13M4T3_5,ctl_reg_sys_hilo_pla30pla13M4T3_5})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[30]&pla[13])&(M4&T3);\nctl_al_we = ctl_al_we | (pla[30]&pla[13])&(M4&T3);\nfMWrite = fMWrite | (pla[30]&pla[13])&(M5&T1);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[30]&pla[13])&(M5&T1);\nctl_reg_gp_sel_pla30pla13M5T1_3 = (pla[30]&pla[13])&(M5&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla30pla13M5T1_3,ctl_reg_gp_sel_pla30pla13M5T1_3})&(op54);\nctl_reg_gp_hilo_pla30pla13M5T1_4 = (pla[30]&pla[13])&(M5&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla30pla13M5T1_4,ctl_reg_gp_hilo_pla30pla13M5T1_4})&(2'b10);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[30]&pla[13])&(M5&T1);\nctl_sw_2u = ctl_sw_2u | (pla[30]&pla[13])&(M5&T1);\nctl_sw_1u = ctl_sw_1u | (pla[30]&pla[13])&(M5&T1);\nctl_bus_db_we = ctl_bus_db_we | (pla[30]&pla[13])&(M5&T1);\nfMWrite = fMWrite | (pla[30]&pla[13])&(M5&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[30]&pla[13])&(M5&T2);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[30]&pla[13])&(M5&T2);\nctl_reg_sys_hilo_pla30pla13M5T2_4 = (pla[30]&pla[13])&(M5&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla30pla13M5T2_4,ctl_reg_sys_hilo_pla30pla13M5T2_4})&(2'b11);\nctl_sw_4u = ctl_sw_4u | (pla[30]&pla[13])&(M5&T2);\nctl_inc_cy = ctl_inc_cy | (pla[30]&pla[13])&(M5&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[30]&pla[13])&(M5&T2);\nfMWrite = fMWrite | (pla[30]&pla[13])&(M5&T3);\nsetM1 = setM1 | (pla[30]&pla[13])&(M5&T3);\nvalidPLA = validPLA | (pla[30]&~pla[13])&(M1&T4);\nnextM = nextM | (pla[30]&~pla[13])&(M1&T4);\nctl_mRead = ctl_mRead | (pla[30]&~pla[13])&(M1&T4);\nfMRead = fMRead | (pla[30]&~pla[13])&(M2&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[30]&~pla[13])&(M2&T1);\nctl_reg_sys_hilo_pla30npla13M2T1_3 = (pla[30]&~pla[13])&(M2&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla30npla13M2T1_3,ctl_reg_sys_hilo_pla30npla13M2T1_3})&(2'b11);\nctl_al_we = ctl_al_we | (pla[30]&~pla[13])&(M2&T1);\nfMRead = fMRead | (pla[30]&~pla[13])&(M2&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[30]&~pla[13])&(M2&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[30]&~pla[13])&(M2&T2);\nctl_reg_sys_hilo_pla30npla13M2T2_4 = (pla[30]&~pla[13])&(M2&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla30npla13M2T2_4,ctl_reg_sys_hilo_pla30npla13M2T2_4})&(2'b11);\npc_inc_hold = pc_inc_hold | (pla[30]&~pla[13])&(M2&T2)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (pla[30]&~pla[13])&(M2&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[30]&~pla[13])&(M2&T2);\nfMRead = fMRead | (pla[30]&~pla[13])&(M2&T3);\nnextM = nextM | (pla[30]&~pla[13])&(M2&T3);\nctl_mRead = ctl_mRead | (pla[30]&~pla[13])&(M2&T3);\nctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (pla[30]&~pla[13])&(M2&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[30]&~pla[13])&(M2&T3);\nctl_reg_sys_hilo_pla30npla13M2T3_6 = (pla[30]&~pla[13])&(M2&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla30npla13M2T3_6,ctl_reg_sys_hilo_pla30npla13M2T3_6})&({ctl_reg_sys_hilo[1],1'b1});\nctl_reg_in_lo = ctl_reg_in_lo | (pla[30]&~pla[13])&(M2&T3);\nctl_sw_2d = ctl_sw_2d | (pla[30]&~pla[13])&(M2&T3);\nctl_sw_1d = ctl_sw_1d | (pla[30]&~pla[13])&(M2&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[30]&~pla[13])&(M2&T3);\nfMRead = fMRead | (pla[30]&~pla[13])&(M3&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[30]&~pla[13])&(M3&T1);\nctl_reg_sys_hilo_pla30npla13M3T1_3 = (pla[30]&~pla[13])&(M3&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla30npla13M3T1_3,ctl_reg_sys_hilo_pla30npla13M3T1_3})&(2'b11);\nctl_al_we = ctl_al_we | (pla[30]&~pla[13])&(M3&T1);\nfMRead = fMRead | (pla[30]&~pla[13])&(M3&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[30]&~pla[13])&(M3&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[30]&~pla[13])&(M3&T2);\nctl_reg_sys_hilo_pla30npla13M3T2_4 = (pla[30]&~pla[13])&(M3&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla30npla13M3T2_4,ctl_reg_sys_hilo_pla30npla13M3T2_4})&(2'b11);\npc_inc_hold = pc_inc_hold | (pla[30]&~pla[13])&(M3&T2)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (pla[30]&~pla[13])&(M3&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[30]&~pla[13])&(M3&T2);\nfMRead = fMRead | (pla[30]&~pla[13])&(M3&T3);\nnextM = nextM | (pla[30]&~pla[13])&(M3&T3);\nctl_mRead = ctl_mRead | (pla[30]&~pla[13])&(M3&T3);\nctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (pla[30]&~pla[13])&(M3&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[30]&~pla[13])&(M3&T3);\nctl_reg_sys_hilo_pla30npla13M3T3_6 = (pla[30]&~pla[13])&(M3&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla30npla13M3T3_6,ctl_reg_sys_hilo_pla30npla13M3T3_6})&({1'b1,ctl_reg_sys_hilo[0]});\nctl_reg_in_hi = ctl_reg_in_hi | (pla[30]&~pla[13])&(M3&T3);\nctl_sw_2d = ctl_sw_2d | (pla[30]&~pla[13])&(M3&T3);\nctl_sw_1d = ctl_sw_1d | (pla[30]&~pla[13])&(M3&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[30]&~pla[13])&(M3&T3);\nfMRead = fMRead | (pla[30]&~pla[13])&(M4&T1);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[30]&~pla[13])&(M4&T1);\nctl_reg_sys_hilo_pla30npla13M4T1_3 = (pla[30]&~pla[13])&(M4&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla30npla13M4T1_3,ctl_reg_sys_hilo_pla30npla13M4T1_3})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[30]&~pla[13])&(M4&T1);\nctl_al_we = ctl_al_we | (pla[30]&~pla[13])&(M4&T1);\nfMRead = fMRead | (pla[30]&~pla[13])&(M4&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[30]&~pla[13])&(M4&T2);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[30]&~pla[13])&(M4&T2);\nctl_reg_sys_hilo_pla30npla13M4T2_4 = (pla[30]&~pla[13])&(M4&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla30npla13M4T2_4,ctl_reg_sys_hilo_pla30npla13M4T2_4})&(2'b11);\nctl_sw_4u = ctl_sw_4u | (pla[30]&~pla[13])&(M4&T2);\nctl_inc_cy = ctl_inc_cy | (pla[30]&~pla[13])&(M4&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[30]&~pla[13])&(M4&T2);\nfMRead = fMRead | (pla[30]&~pla[13])&(M4&T3);\nnextM = nextM | (pla[30]&~pla[13])&(M4&T3);\nctl_mRead = ctl_mRead | (pla[30]&~pla[13])&(M4&T3);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[30]&~pla[13])&(M4&T3);\nctl_reg_gp_sel_pla30npla13M4T3_5 = (pla[30]&~pla[13])&(M4&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla30npla13M4T3_5,ctl_reg_gp_sel_pla30npla13M4T3_5})&(op54);\nctl_reg_gp_hilo_pla30npla13M4T3_6 = (pla[30]&~pla[13])&(M4&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla30npla13M4T3_6,ctl_reg_gp_hilo_pla30npla13M4T3_6})&(2'b01);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[30]&~pla[13])&(M4&T3);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[30]&~pla[13])&(M4&T3);\nctl_sw_2d = ctl_sw_2d | (pla[30]&~pla[13])&(M4&T3);\nctl_sw_1d = ctl_sw_1d | (pla[30]&~pla[13])&(M4&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[30]&~pla[13])&(M4&T3);\nfMRead = fMRead | (pla[30]&~pla[13])&(M5&T1);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[30]&~pla[13])&(M5&T1);\nctl_reg_sys_hilo_pla30npla13M5T1_3 = (pla[30]&~pla[13])&(M5&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla30npla13M5T1_3,ctl_reg_sys_hilo_pla30npla13M5T1_3})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[30]&~pla[13])&(M5&T1);\nctl_al_we = ctl_al_we | (pla[30]&~pla[13])&(M5&T1);\nfMRead = fMRead | (pla[30]&~pla[13])&(M5&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[30]&~pla[13])&(M5&T2);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[30]&~pla[13])&(M5&T2);\nctl_reg_sys_hilo_pla30npla13M5T2_4 = (pla[30]&~pla[13])&(M5&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla30npla13M5T2_4,ctl_reg_sys_hilo_pla30npla13M5T2_4})&(2'b11);\nctl_sw_4u = ctl_sw_4u | (pla[30]&~pla[13])&(M5&T2);\nctl_inc_cy = ctl_inc_cy | (pla[30]&~pla[13])&(M5&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[30]&~pla[13])&(M5&T2);\nfMRead = fMRead | (pla[30]&~pla[13])&(M5&T3);\nsetM1 = setM1 | (pla[30]&~pla[13])&(M5&T3);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[30]&~pla[13])&(M5&T3);\nctl_reg_gp_sel_pla30npla13M5T3_4 = (pla[30]&~pla[13])&(M5&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla30npla13M5T3_4,ctl_reg_gp_sel_pla30npla13M5T3_4})&(op54);\nctl_reg_gp_hilo_pla30npla13M5T3_5 = (pla[30]&~pla[13])&(M5&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla30npla13M5T3_5,ctl_reg_gp_hilo_pla30npla13M5T3_5})&(2'b10);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[30]&~pla[13])&(M5&T3);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[30]&~pla[13])&(M5&T3);\nctl_sw_2d = ctl_sw_2d | (pla[30]&~pla[13])&(M5&T3);\nctl_sw_1d = ctl_sw_1d | (pla[30]&~pla[13])&(M5&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[30]&~pla[13])&(M5&T3);\nvalidPLA = validPLA | (pla[31]&pla[33])&(M1&T4);\nnextM = nextM | (pla[31]&pla[33])&(M1&T4);\nctl_mRead = ctl_mRead | (pla[31]&pla[33])&(M1&T4);\nfMRead = fMRead | (pla[31]&pla[33])&(M2&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[31]&pla[33])&(M2&T1);\nctl_reg_sys_hilo_pla31pla33M2T1_3 = (pla[31]&pla[33])&(M2&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla31pla33M2T1_3,ctl_reg_sys_hilo_pla31pla33M2T1_3})&(2'b11);\nctl_al_we = ctl_al_we | (pla[31]&pla[33])&(M2&T1);\nfMRead = fMRead | (pla[31]&pla[33])&(M2&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[31]&pla[33])&(M2&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[31]&pla[33])&(M2&T2);\nctl_reg_sys_hilo_pla31pla33M2T2_4 = (pla[31]&pla[33])&(M2&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla31pla33M2T2_4,ctl_reg_sys_hilo_pla31pla33M2T2_4})&(2'b11);\npc_inc_hold = pc_inc_hold | (pla[31]&pla[33])&(M2&T2)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (pla[31]&pla[33])&(M2&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[31]&pla[33])&(M2&T2);\nfMRead = fMRead | (pla[31]&pla[33])&(M2&T3);\nnextM = nextM | (pla[31]&pla[33])&(M2&T3);\nctl_mRead = ctl_mRead | (pla[31]&pla[33])&(M2&T3);\nctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (pla[31]&pla[33])&(M2&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[31]&pla[33])&(M2&T3);\nctl_reg_sys_hilo_pla31pla33M2T3_6 = (pla[31]&pla[33])&(M2&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla31pla33M2T3_6,ctl_reg_sys_hilo_pla31pla33M2T3_6})&({ctl_reg_sys_hilo[1],1'b1});\nctl_reg_in_lo = ctl_reg_in_lo | (pla[31]&pla[33])&(M2&T3);\nctl_sw_2d = ctl_sw_2d | (pla[31]&pla[33])&(M2&T3);\nctl_sw_1d = ctl_sw_1d | (pla[31]&pla[33])&(M2&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[31]&pla[33])&(M2&T3);\nfMRead = fMRead | (pla[31]&pla[33])&(M3&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[31]&pla[33])&(M3&T1);\nctl_reg_sys_hilo_pla31pla33M3T1_3 = (pla[31]&pla[33])&(M3&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla31pla33M3T1_3,ctl_reg_sys_hilo_pla31pla33M3T1_3})&(2'b11);\nctl_al_we = ctl_al_we | (pla[31]&pla[33])&(M3&T1);\nfMRead = fMRead | (pla[31]&pla[33])&(M3&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[31]&pla[33])&(M3&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[31]&pla[33])&(M3&T2);\nctl_reg_sys_hilo_pla31pla33M3T2_4 = (pla[31]&pla[33])&(M3&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla31pla33M3T2_4,ctl_reg_sys_hilo_pla31pla33M3T2_4})&(2'b11);\npc_inc_hold = pc_inc_hold | (pla[31]&pla[33])&(M3&T2)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (pla[31]&pla[33])&(M3&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[31]&pla[33])&(M3&T2);\nfMRead = fMRead | (pla[31]&pla[33])&(M3&T3);\nnextM = nextM | (pla[31]&pla[33])&(M3&T3);\nctl_mWrite = ctl_mWrite | (pla[31]&pla[33])&(M3&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[31]&pla[33])&(M3&T3);\nctl_reg_sys_hilo_pla31pla33M3T3_5 = (pla[31]&pla[33])&(M3&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla31pla33M3T3_5,ctl_reg_sys_hilo_pla31pla33M3T3_5})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[31]&pla[33])&(M3&T3);\nctl_al_we = ctl_al_we | (pla[31]&pla[33])&(M3&T3);\nctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (pla[31]&pla[33])&(M3&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[31]&pla[33])&(M3&T3);\nctl_reg_sys_hilo_pla31pla33M3T3_10 = (pla[31]&pla[33])&(M3&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla31pla33M3T3_10,ctl_reg_sys_hilo_pla31pla33M3T3_10})&({1'b1,ctl_reg_sys_hilo[0]});\nctl_reg_in_hi = ctl_reg_in_hi | (pla[31]&pla[33])&(M3&T3);\nctl_sw_2d = ctl_sw_2d | (pla[31]&pla[33])&(M3&T3);\nctl_sw_1d = ctl_sw_1d | (pla[31]&pla[33])&(M3&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[31]&pla[33])&(M3&T3);\nfMWrite = fMWrite | (pla[31]&pla[33])&(M4&T1);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[31]&pla[33])&(M4&T1);\nctl_reg_gp_sel_pla31pla33M4T1_3 = (pla[31]&pla[33])&(M4&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla31pla33M4T1_3,ctl_reg_gp_sel_pla31pla33M4T1_3})&(op54);\nctl_reg_gp_hilo_pla31pla33M4T1_4 = (pla[31]&pla[33])&(M4&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla31pla33M4T1_4,ctl_reg_gp_hilo_pla31pla33M4T1_4})&(2'b01);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[31]&pla[33])&(M4&T1);\nctl_sw_1u = ctl_sw_1u | (pla[31]&pla[33])&(M4&T1);\nctl_bus_db_we = ctl_bus_db_we | (pla[31]&pla[33])&(M4&T1);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[31]&pla[33])&(M4&T1);\nfMWrite = fMWrite | (pla[31]&pla[33])&(M4&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[31]&pla[33])&(M4&T2);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[31]&pla[33])&(M4&T2);\nctl_reg_sys_hilo_pla31pla33M4T2_4 = (pla[31]&pla[33])&(M4&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla31pla33M4T2_4,ctl_reg_sys_hilo_pla31pla33M4T2_4})&(2'b11);\nctl_sw_4u = ctl_sw_4u | (pla[31]&pla[33])&(M4&T2);\nctl_inc_cy = ctl_inc_cy | (pla[31]&pla[33])&(M4&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[31]&pla[33])&(M4&T2);\nfMWrite = fMWrite | (pla[31]&pla[33])&(M4&T3);\nnextM = nextM | (pla[31]&pla[33])&(M4&T3);\nctl_mWrite = ctl_mWrite | (pla[31]&pla[33])&(M4&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[31]&pla[33])&(M4&T3);\nctl_reg_sys_hilo_pla31pla33M4T3_5 = (pla[31]&pla[33])&(M4&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla31pla33M4T3_5,ctl_reg_sys_hilo_pla31pla33M4T3_5})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[31]&pla[33])&(M4&T3);\nctl_al_we = ctl_al_we | (pla[31]&pla[33])&(M4&T3);\nfMWrite = fMWrite | (pla[31]&pla[33])&(M5&T1);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[31]&pla[33])&(M5&T1);\nctl_reg_gp_sel_pla31pla33M5T1_3 = (pla[31]&pla[33])&(M5&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla31pla33M5T1_3,ctl_reg_gp_sel_pla31pla33M5T1_3})&(op54);\nctl_reg_gp_hilo_pla31pla33M5T1_4 = (pla[31]&pla[33])&(M5&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla31pla33M5T1_4,ctl_reg_gp_hilo_pla31pla33M5T1_4})&(2'b10);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[31]&pla[33])&(M5&T1);\nctl_sw_2u = ctl_sw_2u | (pla[31]&pla[33])&(M5&T1);\nctl_sw_1u = ctl_sw_1u | (pla[31]&pla[33])&(M5&T1);\nctl_bus_db_we = ctl_bus_db_we | (pla[31]&pla[33])&(M5&T1);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[31]&pla[33])&(M5&T1);\nfMWrite = fMWrite | (pla[31]&pla[33])&(M5&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[31]&pla[33])&(M5&T2);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[31]&pla[33])&(M5&T2);\nctl_reg_sys_hilo_pla31pla33M5T2_4 = (pla[31]&pla[33])&(M5&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla31pla33M5T2_4,ctl_reg_sys_hilo_pla31pla33M5T2_4})&(2'b11);\nctl_sw_4u = ctl_sw_4u | (pla[31]&pla[33])&(M5&T2);\nctl_inc_cy = ctl_inc_cy | (pla[31]&pla[33])&(M5&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[31]&pla[33])&(M5&T2);\nfMWrite = fMWrite | (pla[31]&pla[33])&(M5&T3);\nsetM1 = setM1 | (pla[31]&pla[33])&(M5&T3);\nvalidPLA = validPLA | (pla[31]&~pla[33])&(M1&T4);\nnextM = nextM | (pla[31]&~pla[33])&(M1&T4);\nctl_mRead = ctl_mRead | (pla[31]&~pla[33])&(M1&T4);\nfMRead = fMRead | (pla[31]&~pla[33])&(M2&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[31]&~pla[33])&(M2&T1);\nctl_reg_sys_hilo_pla31npla33M2T1_3 = (pla[31]&~pla[33])&(M2&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla31npla33M2T1_3,ctl_reg_sys_hilo_pla31npla33M2T1_3})&(2'b11);\nctl_al_we = ctl_al_we | (pla[31]&~pla[33])&(M2&T1);\nfMRead = fMRead | (pla[31]&~pla[33])&(M2&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[31]&~pla[33])&(M2&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[31]&~pla[33])&(M2&T2);\nctl_reg_sys_hilo_pla31npla33M2T2_4 = (pla[31]&~pla[33])&(M2&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla31npla33M2T2_4,ctl_reg_sys_hilo_pla31npla33M2T2_4})&(2'b11);\npc_inc_hold = pc_inc_hold | (pla[31]&~pla[33])&(M2&T2)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (pla[31]&~pla[33])&(M2&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[31]&~pla[33])&(M2&T2);\nfMRead = fMRead | (pla[31]&~pla[33])&(M2&T3);\nnextM = nextM | (pla[31]&~pla[33])&(M2&T3);\nctl_mRead = ctl_mRead | (pla[31]&~pla[33])&(M2&T3);\nctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (pla[31]&~pla[33])&(M2&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[31]&~pla[33])&(M2&T3);\nctl_reg_sys_hilo_pla31npla33M2T3_6 = (pla[31]&~pla[33])&(M2&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla31npla33M2T3_6,ctl_reg_sys_hilo_pla31npla33M2T3_6})&({ctl_reg_sys_hilo[1],1'b1});\nctl_reg_in_lo = ctl_reg_in_lo | (pla[31]&~pla[33])&(M2&T3);\nctl_sw_2d = ctl_sw_2d | (pla[31]&~pla[33])&(M2&T3);\nctl_sw_1d = ctl_sw_1d | (pla[31]&~pla[33])&(M2&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[31]&~pla[33])&(M2&T3);\nfMRead = fMRead | (pla[31]&~pla[33])&(M3&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[31]&~pla[33])&(M3&T1);\nctl_reg_sys_hilo_pla31npla33M3T1_3 = (pla[31]&~pla[33])&(M3&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla31npla33M3T1_3,ctl_reg_sys_hilo_pla31npla33M3T1_3})&(2'b11);\nctl_al_we = ctl_al_we | (pla[31]&~pla[33])&(M3&T1);\nfMRead = fMRead | (pla[31]&~pla[33])&(M3&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[31]&~pla[33])&(M3&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[31]&~pla[33])&(M3&T2);\nctl_reg_sys_hilo_pla31npla33M3T2_4 = (pla[31]&~pla[33])&(M3&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla31npla33M3T2_4,ctl_reg_sys_hilo_pla31npla33M3T2_4})&(2'b11);\npc_inc_hold = pc_inc_hold | (pla[31]&~pla[33])&(M3&T2)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (pla[31]&~pla[33])&(M3&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[31]&~pla[33])&(M3&T2);\nfMRead = fMRead | (pla[31]&~pla[33])&(M3&T3);\nnextM = nextM | (pla[31]&~pla[33])&(M3&T3);\nctl_mRead = ctl_mRead | (pla[31]&~pla[33])&(M3&T3);\nctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (pla[31]&~pla[33])&(M3&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[31]&~pla[33])&(M3&T3);\nctl_reg_sys_hilo_pla31npla33M3T3_6 = (pla[31]&~pla[33])&(M3&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla31npla33M3T3_6,ctl_reg_sys_hilo_pla31npla33M3T3_6})&({1'b1,ctl_reg_sys_hilo[0]});\nctl_reg_in_hi = ctl_reg_in_hi | (pla[31]&~pla[33])&(M3&T3);\nctl_sw_2d = ctl_sw_2d | (pla[31]&~pla[33])&(M3&T3);\nctl_sw_1d = ctl_sw_1d | (pla[31]&~pla[33])&(M3&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[31]&~pla[33])&(M3&T3);\nfMRead = fMRead | (pla[31]&~pla[33])&(M4&T1);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[31]&~pla[33])&(M4&T1);\nctl_reg_sys_hilo_pla31npla33M4T1_3 = (pla[31]&~pla[33])&(M4&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla31npla33M4T1_3,ctl_reg_sys_hilo_pla31npla33M4T1_3})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[31]&~pla[33])&(M4&T1);\nctl_al_we = ctl_al_we | (pla[31]&~pla[33])&(M4&T1);\nfMRead = fMRead | (pla[31]&~pla[33])&(M4&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[31]&~pla[33])&(M4&T2);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[31]&~pla[33])&(M4&T2);\nctl_reg_sys_hilo_pla31npla33M4T2_4 = (pla[31]&~pla[33])&(M4&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla31npla33M4T2_4,ctl_reg_sys_hilo_pla31npla33M4T2_4})&(2'b11);\nctl_sw_4u = ctl_sw_4u | (pla[31]&~pla[33])&(M4&T2);\nctl_inc_cy = ctl_inc_cy | (pla[31]&~pla[33])&(M4&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[31]&~pla[33])&(M4&T2);\nfMRead = fMRead | (pla[31]&~pla[33])&(M4&T3);\nnextM = nextM | (pla[31]&~pla[33])&(M4&T3);\nctl_mRead = ctl_mRead | (pla[31]&~pla[33])&(M4&T3);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[31]&~pla[33])&(M4&T3);\nctl_reg_gp_sel_pla31npla33M4T3_5 = (pla[31]&~pla[33])&(M4&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla31npla33M4T3_5,ctl_reg_gp_sel_pla31npla33M4T3_5})&(op54);\nctl_reg_gp_hilo_pla31npla33M4T3_6 = (pla[31]&~pla[33])&(M4&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla31npla33M4T3_6,ctl_reg_gp_hilo_pla31npla33M4T3_6})&(2'b01);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[31]&~pla[33])&(M4&T3);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[31]&~pla[33])&(M4&T3);\nctl_sw_2d = ctl_sw_2d | (pla[31]&~pla[33])&(M4&T3);\nctl_sw_1d = ctl_sw_1d | (pla[31]&~pla[33])&(M4&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[31]&~pla[33])&(M4&T3);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[31]&~pla[33])&(M4&T3);\nfMRead = fMRead | (pla[31]&~pla[33])&(M5&T1);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[31]&~pla[33])&(M5&T1);\nctl_reg_sys_hilo_pla31npla33M5T1_3 = (pla[31]&~pla[33])&(M5&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla31npla33M5T1_3,ctl_reg_sys_hilo_pla31npla33M5T1_3})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[31]&~pla[33])&(M5&T1);\nctl_al_we = ctl_al_we | (pla[31]&~pla[33])&(M5&T1);\nfMRead = fMRead | (pla[31]&~pla[33])&(M5&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[31]&~pla[33])&(M5&T2);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[31]&~pla[33])&(M5&T2);\nctl_reg_sys_hilo_pla31npla33M5T2_4 = (pla[31]&~pla[33])&(M5&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla31npla33M5T2_4,ctl_reg_sys_hilo_pla31npla33M5T2_4})&(2'b11);\nctl_sw_4u = ctl_sw_4u | (pla[31]&~pla[33])&(M5&T2);\nctl_inc_cy = ctl_inc_cy | (pla[31]&~pla[33])&(M5&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[31]&~pla[33])&(M5&T2);\nfMRead = fMRead | (pla[31]&~pla[33])&(M5&T3);\nsetM1 = setM1 | (pla[31]&~pla[33])&(M5&T3);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[31]&~pla[33])&(M5&T3);\nctl_reg_gp_sel_pla31npla33M5T3_4 = (pla[31]&~pla[33])&(M5&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla31npla33M5T3_4,ctl_reg_gp_sel_pla31npla33M5T3_4})&(op54);\nctl_reg_gp_hilo_pla31npla33M5T3_5 = (pla[31]&~pla[33])&(M5&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla31npla33M5T3_5,ctl_reg_gp_hilo_pla31npla33M5T3_5})&(2'b10);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[31]&~pla[33])&(M5&T3);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[31]&~pla[33])&(M5&T3);\nctl_sw_2d = ctl_sw_2d | (pla[31]&~pla[33])&(M5&T3);\nctl_sw_1d = ctl_sw_1d | (pla[31]&~pla[33])&(M5&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[31]&~pla[33])&(M5&T3);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[31]&~pla[33])&(M5&T3);\nvalidPLA = validPLA | (pla[5])&(M1&T4);\nctl_reg_gp_sel_pla5M1T4_2 = (pla[5])&(M1&T4);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla5M1T4_2,ctl_reg_gp_sel_pla5M1T4_2})&(`GP_REG_HL);\nctl_reg_gp_hilo_pla5M1T4_3 = (pla[5])&(M1&T4);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla5M1T4_3,ctl_reg_gp_hilo_pla5M1T4_3})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[5])&(M1&T4);\nctl_al_we = ctl_al_we | (pla[5])&(M1&T4);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[5])&(M1&T5);\nctl_reg_gp_sel_pla5M1T5_2 = (pla[5])&(M1&T5);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla5M1T5_2,ctl_reg_gp_sel_pla5M1T5_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla5M1T5_3 = (pla[5])&(M1&T5);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla5M1T5_3,ctl_reg_gp_hilo_pla5M1T5_3})&(2'b11);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[5])&(M1&T5);\nctl_sw_4u = ctl_sw_4u | (pla[5])&(M1&T5);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[5])&(M1&T5);\nsetM1 = setM1 | (pla[5])&(M1&T6);\nvalidPLA = validPLA | (pla[23]&pla[16])&(M1&T4);\nnextM = nextM | (pla[23]&pla[16])&(M1&T5);\nctl_mWrite = ctl_mWrite | (pla[23]&pla[16])&(M1&T5);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[23]&pla[16])&(M1&T5);\nctl_reg_gp_sel_pla23pla16M1T5_4 = (pla[23]&pla[16])&(M1&T5);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla23pla16M1T5_4,ctl_reg_gp_sel_pla23pla16M1T5_4})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla23pla16M1T5_5 = (pla[23]&pla[16])&(M1&T5);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla23pla16M1T5_5,ctl_reg_gp_hilo_pla23pla16M1T5_5})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[23]&pla[16])&(M1&T5);\nctl_inc_cy = ctl_inc_cy | (pla[23]&pla[16])&(M1&T5)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[23]&pla[16])&(M1&T5);\nctl_al_we = ctl_al_we | (pla[23]&pla[16])&(M1&T5);\nfMWrite = fMWrite | (pla[23]&pla[16])&(M2&T1);\nctl_inc_cy = ctl_inc_cy | (pla[23]&pla[16])&(M2&T1)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[23]&pla[16])&(M2&T1);\nctl_apin_mux = ctl_apin_mux | (pla[23]&pla[16])&(M2&T1);\nctl_reg_gp_sel_pla23pla16M2T1_5 = (pla[23]&pla[16])&(M2&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla23pla16M2T1_5,ctl_reg_gp_sel_pla23pla16M2T1_5})&(op54);\nctl_reg_gp_hilo_pla23pla16M2T1_6 = (pla[23]&pla[16])&(M2&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla23pla16M2T1_6,ctl_reg_gp_hilo_pla23pla16M2T1_6})&(2'b10);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[23]&pla[16])&(M2&T1);\nctl_sw_2u = ctl_sw_2u | (pla[23]&pla[16])&(M2&T1);\nctl_sw_1u = ctl_sw_1u | (pla[23]&pla[16])&(M2&T1);\nctl_bus_db_we = ctl_bus_db_we | (pla[23]&pla[16])&(M2&T1);\nfMWrite = fMWrite | (pla[23]&pla[16])&(M2&T2);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[23]&pla[16])&(M2&T2);\nctl_reg_gp_sel_pla23pla16M2T2_3 = (pla[23]&pla[16])&(M2&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla23pla16M2T2_3,ctl_reg_gp_sel_pla23pla16M2T2_3})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla23pla16M2T2_4 = (pla[23]&pla[16])&(M2&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla23pla16M2T2_4,ctl_reg_gp_hilo_pla23pla16M2T2_4})&(2'b11);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[23]&pla[16])&(M2&T2);\nctl_sw_4u = ctl_sw_4u | (pla[23]&pla[16])&(M2&T2);\nctl_inc_cy = ctl_inc_cy | (pla[23]&pla[16])&(M2&T2)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[23]&pla[16])&(M2&T2);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[23]&pla[16])&(M2&T2);\nfMWrite = fMWrite | (pla[23]&pla[16])&(M2&T3);\nnextM = nextM | (pla[23]&pla[16])&(M2&T3);\nctl_mWrite = ctl_mWrite | (pla[23]&pla[16])&(M2&T3);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[23]&pla[16])&(M2&T3);\nctl_reg_gp_sel_pla23pla16M2T3_5 = (pla[23]&pla[16])&(M2&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla23pla16M2T3_5,ctl_reg_gp_sel_pla23pla16M2T3_5})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla23pla16M2T3_6 = (pla[23]&pla[16])&(M2&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla23pla16M2T3_6,ctl_reg_gp_hilo_pla23pla16M2T3_6})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[23]&pla[16])&(M2&T3);\nctl_inc_cy = ctl_inc_cy | (pla[23]&pla[16])&(M2&T3)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[23]&pla[16])&(M2&T3);\nctl_al_we = ctl_al_we | (pla[23]&pla[16])&(M2&T3);\nfMWrite = fMWrite | (pla[23]&pla[16])&(M3&T1);\nctl_inc_cy = ctl_inc_cy | (pla[23]&pla[16])&(M3&T1)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[23]&pla[16])&(M3&T1);\nctl_apin_mux = ctl_apin_mux | (pla[23]&pla[16])&(M3&T1);\nctl_reg_gp_sel_pla23pla16M3T1_5 = (pla[23]&pla[16])&(M3&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla23pla16M3T1_5,ctl_reg_gp_sel_pla23pla16M3T1_5})&(op54);\nctl_reg_gp_hilo_pla23pla16M3T1_6 = (pla[23]&pla[16])&(M3&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla23pla16M3T1_6,ctl_reg_gp_hilo_pla23pla16M3T1_6})&(2'b01);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[23]&pla[16])&(M3&T1);\nctl_sw_1u = ctl_sw_1u | (pla[23]&pla[16])&(M3&T1);\nctl_bus_db_we = ctl_bus_db_we | (pla[23]&pla[16])&(M3&T1);\nfMWrite = fMWrite | (pla[23]&pla[16])&(M3&T2);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[23]&pla[16])&(M3&T2);\nctl_reg_gp_sel_pla23pla16M3T2_3 = (pla[23]&pla[16])&(M3&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla23pla16M3T2_3,ctl_reg_gp_sel_pla23pla16M3T2_3})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla23pla16M3T2_4 = (pla[23]&pla[16])&(M3&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla23pla16M3T2_4,ctl_reg_gp_hilo_pla23pla16M3T2_4})&(2'b11);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[23]&pla[16])&(M3&T2);\nctl_sw_4u = ctl_sw_4u | (pla[23]&pla[16])&(M3&T2);\nctl_inc_cy = ctl_inc_cy | (pla[23]&pla[16])&(M3&T2)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[23]&pla[16])&(M3&T2);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[23]&pla[16])&(M3&T2);\nfMWrite = fMWrite | (pla[23]&pla[16])&(M3&T3);\nsetM1 = setM1 | (pla[23]&pla[16])&(M3&T3);\nvalidPLA = validPLA | (pla[23]&~pla[16])&(M1&T4);\nnextM = nextM | (pla[23]&~pla[16])&(M1&T4);\nctl_mRead = ctl_mRead | (pla[23]&~pla[16])&(M1&T4);\nfMRead = fMRead | (pla[23]&~pla[16])&(M2&T1);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[23]&~pla[16])&(M2&T1);\nctl_reg_gp_sel_pla23npla16M2T1_3 = (pla[23]&~pla[16])&(M2&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla23npla16M2T1_3,ctl_reg_gp_sel_pla23npla16M2T1_3})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla23npla16M2T1_4 = (pla[23]&~pla[16])&(M2&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla23npla16M2T1_4,ctl_reg_gp_hilo_pla23npla16M2T1_4})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[23]&~pla[16])&(M2&T1);\nctl_al_we = ctl_al_we | (pla[23]&~pla[16])&(M2&T1);\nfMRead = fMRead | (pla[23]&~pla[16])&(M2&T2);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[23]&~pla[16])&(M2&T2);\nctl_reg_gp_sel_pla23npla16M2T2_3 = (pla[23]&~pla[16])&(M2&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla23npla16M2T2_3,ctl_reg_gp_sel_pla23npla16M2T2_3})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla23npla16M2T2_4 = (pla[23]&~pla[16])&(M2&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla23npla16M2T2_4,ctl_reg_gp_hilo_pla23npla16M2T2_4})&(2'b11);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[23]&~pla[16])&(M2&T2);\nctl_sw_4u = ctl_sw_4u | (pla[23]&~pla[16])&(M2&T2);\nctl_inc_cy = ctl_inc_cy | (pla[23]&~pla[16])&(M2&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[23]&~pla[16])&(M2&T2);\nfMRead = fMRead | (pla[23]&~pla[16])&(M2&T3);\nnextM = nextM | (pla[23]&~pla[16])&(M2&T3);\nctl_mRead = ctl_mRead | (pla[23]&~pla[16])&(M2&T3);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[23]&~pla[16])&(M2&T3);\nctl_reg_gp_sel_pla23npla16M2T3_5 = (pla[23]&~pla[16])&(M2&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla23npla16M2T3_5,ctl_reg_gp_sel_pla23npla16M2T3_5})&(op54);\nctl_reg_gp_hilo_pla23npla16M2T3_6 = (pla[23]&~pla[16])&(M2&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla23npla16M2T3_6,ctl_reg_gp_hilo_pla23npla16M2T3_6})&(2'b01);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[23]&~pla[16])&(M2&T3);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[23]&~pla[16])&(M2&T3);\nctl_sw_2d = ctl_sw_2d | (pla[23]&~pla[16])&(M2&T3);\nctl_sw_1d = ctl_sw_1d | (pla[23]&~pla[16])&(M2&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[23]&~pla[16])&(M2&T3);\nfMRead = fMRead | (pla[23]&~pla[16])&(M3&T1);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[23]&~pla[16])&(M3&T1);\nctl_reg_gp_sel_pla23npla16M3T1_3 = (pla[23]&~pla[16])&(M3&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla23npla16M3T1_3,ctl_reg_gp_sel_pla23npla16M3T1_3})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla23npla16M3T1_4 = (pla[23]&~pla[16])&(M3&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla23npla16M3T1_4,ctl_reg_gp_hilo_pla23npla16M3T1_4})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[23]&~pla[16])&(M3&T1);\nctl_al_we = ctl_al_we | (pla[23]&~pla[16])&(M3&T1);\nfMRead = fMRead | (pla[23]&~pla[16])&(M3&T2);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[23]&~pla[16])&(M3&T2);\nctl_reg_gp_sel_pla23npla16M3T2_3 = (pla[23]&~pla[16])&(M3&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla23npla16M3T2_3,ctl_reg_gp_sel_pla23npla16M3T2_3})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla23npla16M3T2_4 = (pla[23]&~pla[16])&(M3&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla23npla16M3T2_4,ctl_reg_gp_hilo_pla23npla16M3T2_4})&(2'b11);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[23]&~pla[16])&(M3&T2);\nctl_sw_4u = ctl_sw_4u | (pla[23]&~pla[16])&(M3&T2);\nctl_inc_cy = ctl_inc_cy | (pla[23]&~pla[16])&(M3&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[23]&~pla[16])&(M3&T2);\nfMRead = fMRead | (pla[23]&~pla[16])&(M3&T3);\nsetM1 = setM1 | (pla[23]&~pla[16])&(M3&T3);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[23]&~pla[16])&(M3&T3);\nctl_reg_gp_sel_pla23npla16M3T3_4 = (pla[23]&~pla[16])&(M3&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla23npla16M3T3_4,ctl_reg_gp_sel_pla23npla16M3T3_4})&(op54);\nctl_reg_gp_hilo_pla23npla16M3T3_5 = (pla[23]&~pla[16])&(M3&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla23npla16M3T3_5,ctl_reg_gp_hilo_pla23npla16M3T3_5})&(2'b10);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[23]&~pla[16])&(M3&T3);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[23]&~pla[16])&(M3&T3);\nctl_sw_2d = ctl_sw_2d | (pla[23]&~pla[16])&(M3&T3);\nctl_sw_1d = ctl_sw_1d | (pla[23]&~pla[16])&(M3&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[23]&~pla[16])&(M3&T3);\nctl_reg_ex_de_hl = ctl_reg_ex_de_hl | (pla[2])&(M1&T2);\nvalidPLA = validPLA | (pla[2])&(M1&T4);\nsetM1 = setM1 | (pla[2])&(M1&T4);\nctl_reg_ex_af = ctl_reg_ex_af | (pla[39])&(M1&T2);\nvalidPLA = validPLA | (pla[39])&(M1&T4);\nsetM1 = setM1 | (pla[39])&(M1&T4);\nctl_reg_exx = ctl_reg_exx | (pla[1])&(M1&T2);\nvalidPLA = validPLA | (pla[1])&(M1&T4);\nsetM1 = setM1 | (pla[1])&(M1&T4);\nvalidPLA = validPLA | (pla[10])&(M1&T4);\nnextM = nextM | (pla[10])&(M1&T4);\nctl_mRead = ctl_mRead | (pla[10])&(M1&T4);\nfMRead = fMRead | (pla[10])&(M2&T1);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[10])&(M2&T1);\nctl_reg_gp_sel_pla10M2T1_3 = (pla[10])&(M2&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla10M2T1_3,ctl_reg_gp_sel_pla10M2T1_3})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla10M2T1_4 = (pla[10])&(M2&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla10M2T1_4,ctl_reg_gp_hilo_pla10M2T1_4})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[10])&(M2&T1);\nctl_al_we = ctl_al_we | (pla[10])&(M2&T1);\nfMRead = fMRead | (pla[10])&(M2&T2);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[10])&(M2&T2);\nctl_reg_gp_sel_pla10M2T2_3 = (pla[10])&(M2&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla10M2T2_3,ctl_reg_gp_sel_pla10M2T2_3})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla10M2T2_4 = (pla[10])&(M2&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla10M2T2_4,ctl_reg_gp_hilo_pla10M2T2_4})&(2'b11);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[10])&(M2&T2);\nctl_sw_4u = ctl_sw_4u | (pla[10])&(M2&T2);\nctl_inc_cy = ctl_inc_cy | (pla[10])&(M2&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[10])&(M2&T2);\nfMRead = fMRead | (pla[10])&(M2&T3);\nnextM = nextM | (pla[10])&(M2&T3);\nctl_mRead = ctl_mRead | (pla[10])&(M2&T3);\nctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (pla[10])&(M2&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[10])&(M2&T3);\nctl_reg_sys_hilo_pla10M2T3_6 = (pla[10])&(M2&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla10M2T3_6,ctl_reg_sys_hilo_pla10M2T3_6})&({ctl_reg_sys_hilo[1],1'b1});\nctl_reg_in_lo = ctl_reg_in_lo | (pla[10])&(M2&T3);\nctl_sw_2d = ctl_sw_2d | (pla[10])&(M2&T3);\nctl_sw_1d = ctl_sw_1d | (pla[10])&(M2&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[10])&(M2&T3);\nfMRead = fMRead | (pla[10])&(M3&T1);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[10])&(M3&T1);\nctl_reg_gp_sel_pla10M3T1_3 = (pla[10])&(M3&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla10M3T1_3,ctl_reg_gp_sel_pla10M3T1_3})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla10M3T1_4 = (pla[10])&(M3&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla10M3T1_4,ctl_reg_gp_hilo_pla10M3T1_4})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[10])&(M3&T1);\nctl_al_we = ctl_al_we | (pla[10])&(M3&T1);\nfMRead = fMRead | (pla[10])&(M3&T2);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[10])&(M3&T2);\nctl_reg_gp_sel_pla10M3T2_3 = (pla[10])&(M3&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla10M3T2_3,ctl_reg_gp_sel_pla10M3T2_3})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla10M3T2_4 = (pla[10])&(M3&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla10M3T2_4,ctl_reg_gp_hilo_pla10M3T2_4})&(2'b11);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[10])&(M3&T2);\nctl_sw_4u = ctl_sw_4u | (pla[10])&(M3&T2);\nctl_inc_cy = ctl_inc_cy | (pla[10])&(M3&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[10])&(M3&T2);\nfMRead = fMRead | (pla[10])&(M3&T3);\nctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (pla[10])&(M3&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[10])&(M3&T3);\nctl_reg_sys_hilo_pla10M3T3_4 = (pla[10])&(M3&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla10M3T3_4,ctl_reg_sys_hilo_pla10M3T3_4})&({1'b1,ctl_reg_sys_hilo[0]});\nctl_reg_in_hi = ctl_reg_in_hi | (pla[10])&(M3&T3);\nctl_sw_2d = ctl_sw_2d | (pla[10])&(M3&T3);\nctl_sw_1d = ctl_sw_1d | (pla[10])&(M3&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[10])&(M3&T3);\nnextM = nextM | (pla[10])&(M3&T4);\nctl_mWrite = ctl_mWrite | (pla[10])&(M3&T4);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[10])&(M3&T4);\nctl_reg_gp_sel_pla10M3T4_4 = (pla[10])&(M3&T4);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla10M3T4_4,ctl_reg_gp_sel_pla10M3T4_4})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla10M3T4_5 = (pla[10])&(M3&T4);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla10M3T4_5,ctl_reg_gp_hilo_pla10M3T4_5})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[10])&(M3&T4);\nctl_inc_cy = ctl_inc_cy | (pla[10])&(M3&T4)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[10])&(M3&T4);\nctl_al_we = ctl_al_we | (pla[10])&(M3&T4);\nfMWrite = fMWrite | (pla[10])&(M4&T1);\nctl_inc_cy = ctl_inc_cy | (pla[10])&(M4&T1)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[10])&(M4&T1);\nctl_apin_mux = ctl_apin_mux | (pla[10])&(M4&T1);\nctl_reg_gp_sel_pla10M4T1_5 = (pla[10])&(M4&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla10M4T1_5,ctl_reg_gp_sel_pla10M4T1_5})&(op54);\nctl_reg_gp_hilo_pla10M4T1_6 = (pla[10])&(M4&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla10M4T1_6,ctl_reg_gp_hilo_pla10M4T1_6})&(2'b10);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[10])&(M4&T1);\nctl_sw_2u = ctl_sw_2u | (pla[10])&(M4&T1);\nctl_sw_1u = ctl_sw_1u | (pla[10])&(M4&T1);\nctl_bus_db_we = ctl_bus_db_we | (pla[10])&(M4&T1);\nfMWrite = fMWrite | (pla[10])&(M4&T2);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[10])&(M4&T2);\nctl_reg_gp_sel_pla10M4T2_3 = (pla[10])&(M4&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla10M4T2_3,ctl_reg_gp_sel_pla10M4T2_3})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla10M4T2_4 = (pla[10])&(M4&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla10M4T2_4,ctl_reg_gp_hilo_pla10M4T2_4})&(2'b11);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[10])&(M4&T2);\nctl_sw_4u = ctl_sw_4u | (pla[10])&(M4&T2);\nctl_inc_cy = ctl_inc_cy | (pla[10])&(M4&T2)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[10])&(M4&T2);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[10])&(M4&T2);\nfMWrite = fMWrite | (pla[10])&(M4&T3);\nnextM = nextM | (pla[10])&(M4&T3);\nctl_mWrite = ctl_mWrite | (pla[10])&(M4&T3);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[10])&(M4&T3);\nctl_reg_gp_sel_pla10M4T3_5 = (pla[10])&(M4&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla10M4T3_5,ctl_reg_gp_sel_pla10M4T3_5})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla10M4T3_6 = (pla[10])&(M4&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla10M4T3_6,ctl_reg_gp_hilo_pla10M4T3_6})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[10])&(M4&T3);\nctl_inc_cy = ctl_inc_cy | (pla[10])&(M4&T3)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[10])&(M4&T3);\nctl_al_we = ctl_al_we | (pla[10])&(M4&T3);\nfMWrite = fMWrite | (pla[10])&(M5&T1);\nctl_inc_cy = ctl_inc_cy | (pla[10])&(M5&T1)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[10])&(M5&T1);\nctl_apin_mux = ctl_apin_mux | (pla[10])&(M5&T1);\nctl_reg_gp_sel_pla10M5T1_5 = (pla[10])&(M5&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla10M5T1_5,ctl_reg_gp_sel_pla10M5T1_5})&(op54);\nctl_reg_gp_hilo_pla10M5T1_6 = (pla[10])&(M5&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla10M5T1_6,ctl_reg_gp_hilo_pla10M5T1_6})&(2'b01);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[10])&(M5&T1);\nctl_sw_1u = ctl_sw_1u | (pla[10])&(M5&T1);\nctl_bus_db_we = ctl_bus_db_we | (pla[10])&(M5&T1);\nfMWrite = fMWrite | (pla[10])&(M5&T2);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[10])&(M5&T2);\nctl_reg_gp_sel_pla10M5T2_3 = (pla[10])&(M5&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla10M5T2_3,ctl_reg_gp_sel_pla10M5T2_3})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla10M5T2_4 = (pla[10])&(M5&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla10M5T2_4,ctl_reg_gp_hilo_pla10M5T2_4})&(2'b11);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[10])&(M5&T2);\nctl_sw_4u = ctl_sw_4u | (pla[10])&(M5&T2);\nctl_inc_cy = ctl_inc_cy | (pla[10])&(M5&T2)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[10])&(M5&T2);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[10])&(M5&T2);\nfMWrite = fMWrite | (pla[10])&(M5&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[10])&(M5&T3);\nctl_reg_sys_hilo_pla10M5T3_3 = (pla[10])&(M5&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla10M5T3_3,ctl_reg_sys_hilo_pla10M5T3_3})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[10])&(M5&T3);\nctl_al_we = ctl_al_we | (pla[10])&(M5&T3);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[10])&(M5&T4);\nctl_reg_gp_sel_pla10M5T4_2 = (pla[10])&(M5&T4);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla10M5T4_2,ctl_reg_gp_sel_pla10M5T4_2})&(`GP_REG_HL);\nctl_reg_gp_hilo_pla10M5T4_3 = (pla[10])&(M5&T4);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla10M5T4_3,ctl_reg_gp_hilo_pla10M5T4_3})&(2'b11);\nctl_sw_4u = ctl_sw_4u | (pla[10])&(M5&T4);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[10])&(M5&T4);\nsetM1 = setM1 | (pla[10])&(M5&T5);\nnonRep = nonRep | (pla[0]);\nctl_flags_alu = ctl_flags_alu | (pla[12])&(M1&T1);\nctl_alu_res_oe = ctl_alu_res_oe | (pla[12])&(M1&T1);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[12])&(M1&T1);\nctl_alu_core_R = ctl_alu_core_R | (pla[12])&(M1&T1);\nctl_alu_core_V = ctl_alu_core_V | (pla[12])&(M1&T1);\nctl_alu_core_S = ctl_alu_core_S | (pla[12])&(M1&T1);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[12])&(M1&T1);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[12])&(M1&T1);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[12])&(M1&T1);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[12])&(M1&T1);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[12])&(M1&T1);\nctl_pf_sel_pla12M1T1_12 = (pla[12])&(M1&T1);\nctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_pla12M1T1_12,ctl_pf_sel_pla12M1T1_12})&(`PFSEL_REP);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[12])&(M1&T1);\nctl_flags_nf_clr = ctl_flags_nf_clr | (pla[12])&(M1&T1);\nctl_flags_use_cf2 = ctl_flags_use_cf2 | (pla[12])&(M1&T1);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[12])&(M1&T2);\nctl_reg_gp_sel_pla12M1T2_2 = (pla[12])&(M1&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla12M1T2_2,ctl_reg_gp_sel_pla12M1T2_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla12M1T2_3 = (pla[12])&(M1&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla12M1T2_3,ctl_reg_gp_hilo_pla12M1T2_3})&(2'b01);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[12])&(M1&T2);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[12])&(M1&T2);\nctl_flags_oe = ctl_flags_oe | (pla[12])&(M1&T2);\nctl_reg_gp_sel_pla12M1T3_1 = (pla[12])&(M1&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla12M1T3_1,ctl_reg_gp_sel_pla12M1T3_1})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla12M1T3_2 = (pla[12])&(M1&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla12M1T3_2,ctl_reg_gp_hilo_pla12M1T3_2})&(2'b11);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[12])&(M1&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[12])&(M1&T3);\nctl_flags_bus = ctl_flags_bus | (pla[12])&(M1&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[12])&(M1&T3)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[12])&(M1&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[12])&(M1&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[12])&(M1&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[12])&(M1&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[12])&(M1&T3);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[12])&(M1&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[12])&(M1&T3);\nctl_flags_cf_we = ctl_flags_cf_we | (pla[12])&(M1&T3);\nvalidPLA = validPLA | (pla[12])&(M1&T4);\nnextM = nextM | (pla[12])&(M1&T4);\nctl_mRead = ctl_mRead | (pla[12])&(M1&T4);\nfMRead = fMRead | (pla[12])&(M2&T1);\nctl_reg_gp_sel_pla12M2T1_2 = (pla[12])&(M2&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla12M2T1_2,ctl_reg_gp_sel_pla12M2T1_2})&(`GP_REG_HL);\nctl_reg_gp_hilo_pla12M2T1_3 = (pla[12])&(M2&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla12M2T1_3,ctl_reg_gp_hilo_pla12M2T1_3})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[12])&(M2&T1);\nctl_al_we = ctl_al_we | (pla[12])&(M2&T1);\nfMRead = fMRead | (pla[12])&(M2&T2);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[12])&(M2&T2);\nctl_reg_gp_sel_pla12M2T2_3 = (pla[12])&(M2&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla12M2T2_3,ctl_reg_gp_sel_pla12M2T2_3})&(`GP_REG_HL);\nctl_reg_gp_hilo_pla12M2T2_4 = (pla[12])&(M2&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla12M2T2_4,ctl_reg_gp_hilo_pla12M2T2_4})&(2'b11);\nctl_sw_4u = ctl_sw_4u | (pla[12])&(M2&T2);\nctl_inc_cy = ctl_inc_cy | (pla[12])&(M2&T2)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[12])&(M2&T2)&(op3);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[12])&(M2&T2);\nfMRead = fMRead | (pla[12])&(M2&T3);\nnextM = nextM | (pla[12])&(M2&T3);\nctl_mWrite = ctl_mWrite | (pla[12])&(M2&T3);\nctl_sw_2d = ctl_sw_2d | (pla[12])&(M2&T3);\nctl_sw_1d = ctl_sw_1d | (pla[12])&(M2&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[12])&(M2&T3);\nctl_flags_alu = ctl_flags_alu | (pla[12])&(M2&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[12])&(M2&T3)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[12])&(M2&T3);\nctl_alu_op_low = ctl_alu_op_low | (pla[12])&(M2&T3);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[12])&(M2&T3)&(ctl_alu_op_low);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[12])&(M2&T3)&(ctl_alu_op_low);\nctl_alu_core_hf = ctl_alu_core_hf | (pla[12])&(M2&T3)&(~ctl_alu_op_low);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[12])&(M2&T3);\nctl_flags_cf2_we = ctl_flags_cf2_we | (pla[12])&(M2&T3);\nfMWrite = fMWrite | (pla[12])&(M3&T1);\nctl_reg_gp_sel_pla12M3T1_2 = (pla[12])&(M3&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla12M3T1_2,ctl_reg_gp_sel_pla12M3T1_2})&(`GP_REG_DE);\nctl_reg_gp_hilo_pla12M3T1_3 = (pla[12])&(M3&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla12M3T1_3,ctl_reg_gp_hilo_pla12M3T1_3})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[12])&(M3&T1);\nctl_al_we = ctl_al_we | (pla[12])&(M3&T1);\nctl_flags_alu = ctl_flags_alu | (pla[12])&(M3&T1);\nctl_alu_oe = ctl_alu_oe | (pla[12])&(M3&T1);\nctl_alu_res_oe = ctl_alu_res_oe | (pla[12])&(M3&T1);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[12])&(M3&T1);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[12])&(M3&T1)&(ctl_alu_op_low);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[12])&(M3&T1)&(ctl_alu_op_low);\nctl_alu_core_hf = ctl_alu_core_hf | (pla[12])&(M3&T1)&(~ctl_alu_op_low);\nctl_flags_use_cf2 = ctl_flags_use_cf2 | (pla[12])&(M3&T1);\nfMWrite = fMWrite | (pla[12])&(M3&T2);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[12])&(M3&T2);\nctl_reg_gp_sel_pla12M3T2_3 = (pla[12])&(M3&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla12M3T2_3,ctl_reg_gp_sel_pla12M3T2_3})&(`GP_REG_DE);\nctl_reg_gp_hilo_pla12M3T2_4 = (pla[12])&(M3&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla12M3T2_4,ctl_reg_gp_hilo_pla12M3T2_4})&(2'b11);\nctl_sw_4u = ctl_sw_4u | (pla[12])&(M3&T2);\nctl_inc_cy = ctl_inc_cy | (pla[12])&(M3&T2)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[12])&(M3&T2)&(op3);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[12])&(M3&T2);\nfMWrite = fMWrite | (pla[12])&(M3&T3);\nctl_reg_gp_sel_pla12M3T3_2 = (pla[12])&(M3&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla12M3T3_2,ctl_reg_gp_sel_pla12M3T3_2})&(`GP_REG_BC);\nctl_reg_gp_hilo_pla12M3T3_3 = (pla[12])&(M3&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla12M3T3_3,ctl_reg_gp_hilo_pla12M3T3_3})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[12])&(M3&T3);\nctl_al_we = ctl_al_we | (pla[12])&(M3&T3);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[12])&(M3&T4);\nctl_reg_gp_sel_pla12M3T4_2 = (pla[12])&(M3&T4);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla12M3T4_2,ctl_reg_gp_sel_pla12M3T4_2})&(`GP_REG_BC);\nctl_reg_gp_hilo_pla12M3T4_3 = (pla[12])&(M3&T4);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla12M3T4_3,ctl_reg_gp_hilo_pla12M3T4_3})&(2'b11);\nctl_sw_4u = ctl_sw_4u | (pla[12])&(M3&T4);\nctl_inc_cy = ctl_inc_cy | (pla[12])&(M3&T4)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[12])&(M3&T4);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[12])&(M3&T4);\nctl_repeat_we = ctl_repeat_we | (pla[12])&(M3&T4);\nnextM = nextM | (pla[12])&(M3&T5);\nsetM1 = setM1 | (pla[12])&(M3&T5)&(nonRep|~repeat_en);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[12])&(M4&T1);\nctl_reg_sys_hilo_pla12M4T1_2 = (pla[12])&(M4&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla12M4T1_2,ctl_reg_sys_hilo_pla12M4T1_2})&(2'b11);\nctl_al_we = ctl_al_we | (pla[12])&(M4&T1);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[12])&(M4&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[12])&(M4&T2);\nctl_reg_sys_hilo_pla12M4T2_3 = (pla[12])&(M4&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla12M4T2_3,ctl_reg_sys_hilo_pla12M4T2_3})&(2'b11);\npc_inc_hold = pc_inc_hold | (pla[12])&(M4&T2)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (pla[12])&(M4&T2)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[12])&(M4&T2);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[12])&(M4&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[12])&(M4&T3);\nctl_reg_sys_hilo_pla12M4T3_2 = (pla[12])&(M4&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla12M4T3_2,ctl_reg_sys_hilo_pla12M4T3_2})&(2'b11);\nctl_al_we = ctl_al_we | (pla[12])&(M4&T3);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[12])&(M4&T4);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[12])&(M4&T4);\nctl_reg_sys_hilo_pla12M4T4_3 = (pla[12])&(M4&T4);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla12M4T4_3,ctl_reg_sys_hilo_pla12M4T4_3})&(2'b11);\npc_inc_hold = pc_inc_hold | (pla[12])&(M4&T4)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (pla[12])&(M4&T4)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[12])&(M4&T4);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[12])&(M4&T4);\nsetM1 = setM1 | (pla[12])&(M4&T5);\nctl_flags_alu = ctl_flags_alu | (pla[11])&(M1&T1);\nctl_alu_oe = ctl_alu_oe | (pla[11])&(M1&T1);\nctl_alu_res_oe = ctl_alu_res_oe | (pla[11])&(M1&T1);\nctl_alu_op1_sel_zero = ctl_alu_op1_sel_zero | (pla[11])&(M1&T1);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[11])&(M1&T1);\nctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[11])&(M1&T1);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[11])&(M1&T1)&(ctl_alu_op_low);\nctl_alu_core_hf = ctl_alu_core_hf | (pla[11])&(M1&T1)&(~ctl_alu_op_low);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[11])&(M1&T1);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[11])&(M1&T1);\nctl_pf_sel_pla11M1T1_11 = (pla[11])&(M1&T1);\nctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_pla11M1T1_11,ctl_pf_sel_pla11M1T1_11})&(`PFSEL_REP);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[11])&(M1&T1);\nctl_flags_nf_set = ctl_flags_nf_set | (pla[11])&(M1&T1);\nctl_flags_use_cf2 = ctl_flags_use_cf2 | (pla[11])&(M1&T1);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[11])&(M1&T2);\nctl_reg_gp_sel_pla11M1T2_2 = (pla[11])&(M1&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla11M1T2_2,ctl_reg_gp_sel_pla11M1T2_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla11M1T2_3 = (pla[11])&(M1&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla11M1T2_3,ctl_reg_gp_hilo_pla11M1T2_3})&(2'b01);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[11])&(M1&T2);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[11])&(M1&T2);\nctl_flags_oe = ctl_flags_oe | (pla[11])&(M1&T2);\nctl_flags_hf_cpl = ctl_flags_hf_cpl | (pla[11])&(M1&T2)&(flags_nf);\nctl_reg_gp_sel_pla11M1T3_1 = (pla[11])&(M1&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla11M1T3_1,ctl_reg_gp_sel_pla11M1T3_1})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla11M1T3_2 = (pla[11])&(M1&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla11M1T3_2,ctl_reg_gp_hilo_pla11M1T3_2})&(2'b11);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[11])&(M1&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[11])&(M1&T3);\nctl_flags_bus = ctl_flags_bus | (pla[11])&(M1&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[11])&(M1&T3)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[11])&(M1&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[11])&(M1&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[11])&(M1&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[11])&(M1&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[11])&(M1&T3);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[11])&(M1&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[11])&(M1&T3);\nctl_flags_cf_we = ctl_flags_cf_we | (pla[11])&(M1&T3);\nvalidPLA = validPLA | (pla[11])&(M1&T4);\nnextM = nextM | (pla[11])&(M1&T4);\nctl_mRead = ctl_mRead | (pla[11])&(M1&T4);\nfMRead = fMRead | (pla[11])&(M2&T1);\nctl_reg_gp_sel_pla11M2T1_2 = (pla[11])&(M2&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla11M2T1_2,ctl_reg_gp_sel_pla11M2T1_2})&(`GP_REG_HL);\nctl_reg_gp_hilo_pla11M2T1_3 = (pla[11])&(M2&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla11M2T1_3,ctl_reg_gp_hilo_pla11M2T1_3})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[11])&(M2&T1);\nctl_al_we = ctl_al_we | (pla[11])&(M2&T1);\nfMRead = fMRead | (pla[11])&(M2&T2);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[11])&(M2&T2);\nctl_reg_gp_sel_pla11M2T2_3 = (pla[11])&(M2&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla11M2T2_3,ctl_reg_gp_sel_pla11M2T2_3})&(`GP_REG_HL);\nctl_reg_gp_hilo_pla11M2T2_4 = (pla[11])&(M2&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla11M2T2_4,ctl_reg_gp_hilo_pla11M2T2_4})&(2'b11);\nctl_sw_4u = ctl_sw_4u | (pla[11])&(M2&T2);\nctl_inc_cy = ctl_inc_cy | (pla[11])&(M2&T2)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[11])&(M2&T2)&(op3);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[11])&(M2&T2);\nfMRead = fMRead | (pla[11])&(M2&T3);\nnextM = nextM | (pla[11])&(M2&T3);\nctl_sw_2d = ctl_sw_2d | (pla[11])&(M2&T3);\nctl_sw_1d = ctl_sw_1d | (pla[11])&(M2&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[11])&(M2&T3);\nctl_flags_alu = ctl_flags_alu | (pla[11])&(M2&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[11])&(M2&T3)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[11])&(M2&T3);\nctl_alu_op_low = ctl_alu_op_low | (pla[11])&(M2&T3);\nctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[11])&(M2&T3);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[11])&(M2&T3)&(ctl_alu_op_low);\nctl_alu_core_hf = ctl_alu_core_hf | (pla[11])&(M2&T3)&(~ctl_alu_op_low);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[11])&(M2&T3);\nctl_flags_cf2_we = ctl_flags_cf2_we | (pla[11])&(M2&T3);\nctl_flags_alu = ctl_flags_alu | (pla[11])&(M3&T1);\nctl_alu_oe = ctl_alu_oe | (pla[11])&(M3&T1);\nctl_alu_res_oe = ctl_alu_res_oe | (pla[11])&(M3&T1);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[11])&(M3&T1);\nctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[11])&(M3&T1);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[11])&(M3&T1)&(ctl_alu_op_low);\nctl_alu_core_hf = ctl_alu_core_hf | (pla[11])&(M3&T1)&(~ctl_alu_op_low);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[11])&(M3&T1);\nctl_flags_use_cf2 = ctl_flags_use_cf2 | (pla[11])&(M3&T1);\nctl_reg_gp_sel_pla11M3T3_1 = (pla[11])&(M3&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla11M3T3_1,ctl_reg_gp_sel_pla11M3T3_1})&(`GP_REG_BC);\nctl_reg_gp_hilo_pla11M3T3_2 = (pla[11])&(M3&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla11M3T3_2,ctl_reg_gp_hilo_pla11M3T3_2})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[11])&(M3&T3);\nctl_al_we = ctl_al_we | (pla[11])&(M3&T3);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[11])&(M3&T4);\nctl_reg_gp_sel_pla11M3T4_2 = (pla[11])&(M3&T4);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla11M3T4_2,ctl_reg_gp_sel_pla11M3T4_2})&(`GP_REG_BC);\nctl_reg_gp_hilo_pla11M3T4_3 = (pla[11])&(M3&T4);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla11M3T4_3,ctl_reg_gp_hilo_pla11M3T4_3})&(2'b11);\nctl_sw_4u = ctl_sw_4u | (pla[11])&(M3&T4);\nctl_inc_cy = ctl_inc_cy | (pla[11])&(M3&T4)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[11])&(M3&T4);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[11])&(M3&T4);\nctl_repeat_we = ctl_repeat_we | (pla[11])&(M3&T4);\nnextM = nextM | (pla[11])&(M3&T5);\nsetM1 = setM1 | (pla[11])&(M3&T5)&(nonRep|~repeat_en|flags_zf);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[11])&(M4&T1);\nctl_reg_sys_hilo_pla11M4T1_2 = (pla[11])&(M4&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla11M4T1_2,ctl_reg_sys_hilo_pla11M4T1_2})&(2'b11);\nctl_al_we = ctl_al_we | (pla[11])&(M4&T1);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[11])&(M4&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[11])&(M4&T2);\nctl_reg_sys_hilo_pla11M4T2_3 = (pla[11])&(M4&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla11M4T2_3,ctl_reg_sys_hilo_pla11M4T2_3})&(2'b11);\npc_inc_hold = pc_inc_hold | (pla[11])&(M4&T2)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (pla[11])&(M4&T2)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[11])&(M4&T2);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[11])&(M4&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[11])&(M4&T3);\nctl_reg_sys_hilo_pla11M4T3_2 = (pla[11])&(M4&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla11M4T3_2,ctl_reg_sys_hilo_pla11M4T3_2})&(2'b11);\nctl_al_we = ctl_al_we | (pla[11])&(M4&T3);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[11])&(M4&T4);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[11])&(M4&T4);\nctl_reg_sys_hilo_pla11M4T4_3 = (pla[11])&(M4&T4);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla11M4T4_3,ctl_reg_sys_hilo_pla11M4T4_3})&(2'b11);\npc_inc_hold = pc_inc_hold | (pla[11])&(M4&T4)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (pla[11])&(M4&T4)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[11])&(M4&T4);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[11])&(M4&T4);\nsetM1 = setM1 | (pla[11])&(M4&T5);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[65]&~pla[52])&(M1&T1);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[65]&~pla[52])&(M1&T1);\nctl_sw_2u = ctl_sw_2u | (pla[65]&~pla[52])&(M1&T1);\nctl_flags_alu = ctl_flags_alu | (pla[65]&~pla[52])&(M1&T1);\nctl_alu_oe = ctl_alu_oe | (pla[65]&~pla[52])&(M1&T1);\nctl_alu_res_oe = ctl_alu_res_oe | (pla[65]&~pla[52])&(M1&T1);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[65]&~pla[52])&(M1&T1);\nctl_state_alu = ctl_state_alu | (pla[65]&~pla[52])&(M1&T1);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[65]&~pla[52])&(M1&T1);\nctl_flags_cf_we = ctl_flags_cf_we | (pla[65]&~pla[52])&(M1&T1);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[65]&~pla[52])&(M1&T2);\nctl_reg_gp_sel_pla65npla52M1T2_2 = (pla[65]&~pla[52])&(M1&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla65npla52M1T2_2,ctl_reg_gp_sel_pla65npla52M1T2_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla65npla52M1T2_3 = (pla[65]&~pla[52])&(M1&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla65npla52M1T2_3,ctl_reg_gp_hilo_pla65npla52M1T2_3})&(2'b01);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[65]&~pla[52])&(M1&T2);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[65]&~pla[52])&(M1&T2);\nctl_flags_oe = ctl_flags_oe | (pla[65]&~pla[52])&(M1&T2);\nctl_state_alu = ctl_state_alu | (pla[65]&~pla[52])&(M1&T2);\nctl_flags_hf_cpl = ctl_flags_hf_cpl | (pla[65]&~pla[52])&(M1&T2)&(flags_nf);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[65]&~pla[52])&(M1&T2)&(flags_nf);\nctl_reg_gp_sel_pla65npla52M1T3_1 = (pla[65]&~pla[52])&(M1&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla65npla52M1T3_1,ctl_reg_gp_sel_pla65npla52M1T3_1})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla65npla52M1T3_2 = (pla[65]&~pla[52])&(M1&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla65npla52M1T3_2,ctl_reg_gp_hilo_pla65npla52M1T3_2})&(2'b11);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[65]&~pla[52])&(M1&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[65]&~pla[52])&(M1&T3);\nctl_flags_bus = ctl_flags_bus | (pla[65]&~pla[52])&(M1&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[65]&~pla[52])&(M1&T3)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[65]&~pla[52])&(M1&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[65]&~pla[52])&(M1&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[65]&~pla[52])&(M1&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[65]&~pla[52])&(M1&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[65]&~pla[52])&(M1&T3);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[65]&~pla[52])&(M1&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[65]&~pla[52])&(M1&T3);\nctl_flags_cf_we = ctl_flags_cf_we | (pla[65]&~pla[52])&(M1&T3);\nvalidPLA = validPLA | (pla[65]&~pla[52])&(M1&T4);\nsetM1 = setM1 | (pla[65]&~pla[52])&(M1&T4);\nctl_reg_gp_sel_pla65npla52M1T4_3 = (pla[65]&~pla[52])&(M1&T4);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla65npla52M1T4_3,ctl_reg_gp_sel_pla65npla52M1T4_3})&(op21);\nctl_reg_gp_hilo_pla65npla52M1T4_4 = (pla[65]&~pla[52])&(M1&T4);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla65npla52M1T4_4,ctl_reg_gp_hilo_pla65npla52M1T4_4})&({~rsel0,rsel0});\nctl_reg_out_hi = ctl_reg_out_hi | (pla[65]&~pla[52])&(M1&T4)&(~rsel0);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[65]&~pla[52])&(M1&T4)&(rsel0);\nctl_sw_2u = ctl_sw_2u | (pla[65]&~pla[52])&(M1&T4)&(~rsel0);\nctl_sw_2d = ctl_sw_2d | (pla[65]&~pla[52])&(M1&T4)&(rsel0);\nctl_flags_alu = ctl_flags_alu | (pla[65]&~pla[52])&(M1&T4);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[65]&~pla[52])&(M1&T4)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[65]&~pla[52])&(M1&T4);\nctl_alu_op_low = ctl_alu_op_low | (pla[65]&~pla[52])&(M1&T4);\nctl_state_alu = ctl_state_alu | (pla[65]&~pla[52])&(M1&T4);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[65]&~pla[52])&(M1&T4);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[65]&~pla[52])&(M1&T4);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[65]&~pla[52])&(M1&T4);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[64])&(M1&T1);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[64])&(M1&T1);\nctl_sw_2u = ctl_sw_2u | (pla[64])&(M1&T1);\nctl_flags_alu = ctl_flags_alu | (pla[64])&(M1&T1);\nctl_alu_oe = ctl_alu_oe | (pla[64])&(M1&T1);\nctl_alu_res_oe = ctl_alu_res_oe | (pla[64])&(M1&T1);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[64])&(M1&T1);\nctl_state_alu = ctl_state_alu | (pla[64])&(M1&T1);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[64])&(M1&T1);\nctl_flags_cf_we = ctl_flags_cf_we | (pla[64])&(M1&T1);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[64])&(M1&T2);\nctl_reg_gp_sel_pla64M1T2_2 = (pla[64])&(M1&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla64M1T2_2,ctl_reg_gp_sel_pla64M1T2_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla64M1T2_3 = (pla[64])&(M1&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla64M1T2_3,ctl_reg_gp_hilo_pla64M1T2_3})&(2'b01);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[64])&(M1&T2);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[64])&(M1&T2);\nctl_flags_oe = ctl_flags_oe | (pla[64])&(M1&T2);\nctl_state_alu = ctl_state_alu | (pla[64])&(M1&T2);\nctl_flags_hf_cpl = ctl_flags_hf_cpl | (pla[64])&(M1&T2)&(flags_nf);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[64])&(M1&T2)&(flags_nf);\nctl_reg_gp_sel_pla64M1T3_1 = (pla[64])&(M1&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla64M1T3_1,ctl_reg_gp_sel_pla64M1T3_1})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla64M1T3_2 = (pla[64])&(M1&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla64M1T3_2,ctl_reg_gp_hilo_pla64M1T3_2})&(2'b11);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[64])&(M1&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[64])&(M1&T3);\nctl_flags_bus = ctl_flags_bus | (pla[64])&(M1&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[64])&(M1&T3)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[64])&(M1&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[64])&(M1&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[64])&(M1&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[64])&(M1&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[64])&(M1&T3);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[64])&(M1&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[64])&(M1&T3);\nctl_flags_cf_we = ctl_flags_cf_we | (pla[64])&(M1&T3);\nvalidPLA = validPLA | (pla[64])&(M1&T4);\nnextM = nextM | (pla[64])&(M1&T4);\nctl_mRead = ctl_mRead | (pla[64])&(M1&T4);\nctl_reg_gp_sel_pla64M1T4_4 = (pla[64])&(M1&T4);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla64M1T4_4,ctl_reg_gp_sel_pla64M1T4_4})&(op21);\nctl_reg_gp_hilo_pla64M1T4_5 = (pla[64])&(M1&T4);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla64M1T4_5,ctl_reg_gp_hilo_pla64M1T4_5})&({~rsel0,rsel0});\nctl_reg_out_hi = ctl_reg_out_hi | (pla[64])&(M1&T4)&(~rsel0);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[64])&(M1&T4)&(rsel0);\nctl_sw_2u = ctl_sw_2u | (pla[64])&(M1&T4)&(~rsel0);\nctl_sw_2d = ctl_sw_2d | (pla[64])&(M1&T4)&(rsel0);\nctl_flags_alu = ctl_flags_alu | (pla[64])&(M1&T4);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[64])&(M1&T4)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[64])&(M1&T4);\nctl_alu_op_low = ctl_alu_op_low | (pla[64])&(M1&T4);\nctl_state_alu = ctl_state_alu | (pla[64])&(M1&T4);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[64])&(M1&T4);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[64])&(M1&T4);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[64])&(M1&T4);\nfMRead = fMRead | (pla[64])&(M2&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[64])&(M2&T1);\nctl_reg_sys_hilo_pla64M2T1_3 = (pla[64])&(M2&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla64M2T1_3,ctl_reg_sys_hilo_pla64M2T1_3})&(2'b11);\nctl_al_we = ctl_al_we | (pla[64])&(M2&T1);\nctl_state_alu = ctl_state_alu | (pla[64])&(M2&T1);\nfMRead = fMRead | (pla[64])&(M2&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[64])&(M2&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[64])&(M2&T2);\nctl_reg_sys_hilo_pla64M2T2_4 = (pla[64])&(M2&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla64M2T2_4,ctl_reg_sys_hilo_pla64M2T2_4})&(2'b11);\npc_inc_hold = pc_inc_hold | (pla[64])&(M2&T2)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (pla[64])&(M2&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[64])&(M2&T2);\nfMRead = fMRead | (pla[64])&(M2&T3);\nsetM1 = setM1 | (pla[64])&(M2&T3);\nctl_sw_2d = ctl_sw_2d | (pla[64])&(M2&T3);\nctl_sw_1d = ctl_sw_1d | (pla[64])&(M2&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[64])&(M2&T3);\nctl_flags_alu = ctl_flags_alu | (pla[64])&(M2&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[64])&(M2&T3)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[64])&(M2&T3);\nctl_alu_op_low = ctl_alu_op_low | (pla[64])&(M2&T3);\nctl_state_alu = ctl_state_alu | (pla[64])&(M2&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[64])&(M2&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[64])&(M2&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[64])&(M2&T3);\nctl_reg_gp_sel_use_ixiypla52M1T3_1 = (use_ixiy&pla[52])&(M1&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_use_ixiypla52M1T3_1,ctl_reg_gp_sel_use_ixiypla52M1T3_1})&(`GP_REG_AF);\nctl_reg_gp_hilo_use_ixiypla52M1T3_2 = (use_ixiy&pla[52])&(M1&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_use_ixiypla52M1T3_2,ctl_reg_gp_hilo_use_ixiypla52M1T3_2})&(2'b11);\nctl_reg_out_hi = ctl_reg_out_hi | (use_ixiy&pla[52])&(M1&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (use_ixiy&pla[52])&(M1&T3);\nctl_flags_bus = ctl_flags_bus | (use_ixiy&pla[52])&(M1&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (use_ixiy&pla[52])&(M1&T3)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (use_ixiy&pla[52])&(M1&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (use_ixiy&pla[52])&(M1&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (use_ixiy&pla[52])&(M1&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (use_ixiy&pla[52])&(M1&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (use_ixiy&pla[52])&(M1&T3);\nctl_flags_pf_we = ctl_flags_pf_we | (use_ixiy&pla[52])&(M1&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (use_ixiy&pla[52])&(M1&T3);\nctl_flags_cf_we = ctl_flags_cf_we | (use_ixiy&pla[52])&(M1&T3);\nvalidPLA = validPLA | (use_ixiy&pla[52])&(M1&T4);\nnextM = nextM | (use_ixiy&pla[52])&(M1&T4);\nctl_mRead = ctl_mRead | (use_ixiy&pla[52])&(M1&T4);\nfMRead = fMRead | (use_ixiy&pla[52])&(M2&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (use_ixiy&pla[52])&(M2&T1);\nctl_reg_sys_hilo_use_ixiypla52M2T1_3 = (use_ixiy&pla[52])&(M2&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_use_ixiypla52M2T1_3,ctl_reg_sys_hilo_use_ixiypla52M2T1_3})&(2'b11);\nctl_al_we = ctl_al_we | (use_ixiy&pla[52])&(M2&T1);\nfMRead = fMRead | (use_ixiy&pla[52])&(M2&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (use_ixiy&pla[52])&(M2&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (use_ixiy&pla[52])&(M2&T2);\nctl_reg_sys_hilo_use_ixiypla52M2T2_4 = (use_ixiy&pla[52])&(M2&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_use_ixiypla52M2T2_4,ctl_reg_sys_hilo_use_ixiypla52M2T2_4})&(2'b11);\npc_inc_hold = pc_inc_hold | (use_ixiy&pla[52])&(M2&T2)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (use_ixiy&pla[52])&(M2&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (use_ixiy&pla[52])&(M2&T2);\nfMRead = fMRead | (use_ixiy&pla[52])&(M2&T3);\nnextM = nextM | (use_ixiy&pla[52])&(M2&T3);\nixy_d = ixy_d | (use_ixiy&pla[52])&(M3&T1);\nixy_d = ixy_d | (use_ixiy&pla[52])&(M3&T2);\nixy_d = ixy_d | (use_ixiy&pla[52])&(M3&T3);\nixy_d = ixy_d | (use_ixiy&pla[52])&(M3&T4);\nnextM = nextM | (use_ixiy&pla[52])&(M3&T5);\nctl_mRead = ctl_mRead | (use_ixiy&pla[52])&(M3&T5);\nixy_d = ixy_d | (use_ixiy&pla[52])&(M3&T5);\nctl_reg_in_hi = ctl_reg_in_hi | (~use_ixiy&pla[52])&(M1&T1);\nctl_reg_in_lo = ctl_reg_in_lo | (~use_ixiy&pla[52])&(M1&T1);\nctl_sw_2u = ctl_sw_2u | (~use_ixiy&pla[52])&(M1&T1);\nctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[52])&(M1&T1);\nctl_alu_oe = ctl_alu_oe | (~use_ixiy&pla[52])&(M1&T1);\nctl_alu_res_oe = ctl_alu_res_oe | (~use_ixiy&pla[52])&(M1&T1);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (~use_ixiy&pla[52])&(M1&T1);\nctl_state_alu = ctl_state_alu | (~use_ixiy&pla[52])&(M1&T1);\nctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[52])&(M1&T1);\nctl_flags_cf_we = ctl_flags_cf_we | (~use_ixiy&pla[52])&(M1&T1);\nctl_reg_gp_we = ctl_reg_gp_we | (~use_ixiy&pla[52])&(M1&T2);\nctl_reg_gp_sel_nuse_ixiypla52M1T2_2 = (~use_ixiy&pla[52])&(M1&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla52M1T2_2,ctl_reg_gp_sel_nuse_ixiypla52M1T2_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_nuse_ixiypla52M1T2_3 = (~use_ixiy&pla[52])&(M1&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla52M1T2_3,ctl_reg_gp_hilo_nuse_ixiypla52M1T2_3})&(2'b01);\nctl_reg_in_hi = ctl_reg_in_hi | (~use_ixiy&pla[52])&(M1&T2);\nctl_reg_in_lo = ctl_reg_in_lo | (~use_ixiy&pla[52])&(M1&T2);\nctl_flags_oe = ctl_flags_oe | (~use_ixiy&pla[52])&(M1&T2);\nctl_state_alu = ctl_state_alu | (~use_ixiy&pla[52])&(M1&T2);\nctl_flags_hf_cpl = ctl_flags_hf_cpl | (~use_ixiy&pla[52])&(M1&T2)&(flags_nf);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (~use_ixiy&pla[52])&(M1&T2)&(flags_nf);\nctl_reg_gp_sel_nuse_ixiypla52M1T3_1 = (~use_ixiy&pla[52])&(M1&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla52M1T3_1,ctl_reg_gp_sel_nuse_ixiypla52M1T3_1})&(`GP_REG_AF);\nctl_reg_gp_hilo_nuse_ixiypla52M1T3_2 = (~use_ixiy&pla[52])&(M1&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla52M1T3_2,ctl_reg_gp_hilo_nuse_ixiypla52M1T3_2})&(2'b11);\nctl_reg_out_hi = ctl_reg_out_hi | (~use_ixiy&pla[52])&(M1&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (~use_ixiy&pla[52])&(M1&T3);\nctl_flags_bus = ctl_flags_bus | (~use_ixiy&pla[52])&(M1&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[52])&(M1&T3)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[52])&(M1&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[52])&(M1&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[52])&(M1&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[52])&(M1&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[52])&(M1&T3);\nctl_flags_pf_we = ctl_flags_pf_we | (~use_ixiy&pla[52])&(M1&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[52])&(M1&T3);\nctl_flags_cf_we = ctl_flags_cf_we | (~use_ixiy&pla[52])&(M1&T3);\nvalidPLA = validPLA | (~use_ixiy&pla[52])&(M1&T4);\nnextM = nextM | (~use_ixiy&pla[52])&(M1&T4);\nctl_mRead = ctl_mRead | (~use_ixiy&pla[52])&(M1&T4);\nfMRead = fMRead | (~use_ixiy&pla[52])&(M2&T1);\nctl_reg_gp_sel_nuse_ixiypla52M2T1_2 = (~use_ixiy&pla[52])&(M2&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla52M2T1_2,ctl_reg_gp_sel_nuse_ixiypla52M2T1_2})&(`GP_REG_HL);\nctl_reg_gp_hilo_nuse_ixiypla52M2T1_3 = (~use_ixiy&pla[52])&(M2&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla52M2T1_3,ctl_reg_gp_hilo_nuse_ixiypla52M2T1_3})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (~use_ixiy&pla[52])&(M2&T1);\nctl_al_we = ctl_al_we | (~use_ixiy&pla[52])&(M2&T1);\nfMRead = fMRead | (~use_ixiy&pla[52])&(M2&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (~use_ixiy&pla[52])&(M2&T2);\nctl_reg_sel_wz = ctl_reg_sel_wz | (~use_ixiy&pla[52])&(M2&T2);\nctl_reg_sys_hilo_nuse_ixiypla52M2T2_4 = (~use_ixiy&pla[52])&(M2&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4,ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4})&(2'b11);\nctl_sw_4u = ctl_sw_4u | (~use_ixiy&pla[52])&(M2&T2);\nctl_inc_cy = ctl_inc_cy | (~use_ixiy&pla[52])&(M2&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (~use_ixiy&pla[52])&(M2&T2);\nfMRead = fMRead | (~use_ixiy&pla[52])&(M2&T3);\nsetM1 = setM1 | (~use_ixiy&pla[52])&(M2&T3);\nctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[52])&(M2&T3);\nctl_sw_1d = ctl_sw_1d | (~use_ixiy&pla[52])&(M2&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[52])&(M2&T3);\nctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[52])&(M2&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[52])&(M2&T3)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[52])&(M2&T3);\nctl_alu_op_low = ctl_alu_op_low | (~use_ixiy&pla[52])&(M2&T3);\nctl_state_alu = ctl_state_alu | (~use_ixiy&pla[52])&(M2&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[52])&(M2&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[52])&(M2&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[52])&(M2&T3);\nfMRead = fMRead | (~use_ixiy&pla[52])&(M4&T1);\nctl_bus_inc_oe = ctl_bus_inc_oe | (~use_ixiy&pla[52])&(M4&T1);\nfMRead = fMRead | (~use_ixiy&pla[52])&(M4&T2);\nctl_reg_gp_sel_nuse_ixiypla52M4T2_2 = (~use_ixiy&pla[52])&(M4&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla52M4T2_2,ctl_reg_gp_sel_nuse_ixiypla52M4T2_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_nuse_ixiypla52M4T2_3 = (~use_ixiy&pla[52])&(M4&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla52M4T2_3,ctl_reg_gp_hilo_nuse_ixiypla52M4T2_3})&(2'b11);\nctl_reg_out_hi = ctl_reg_out_hi | (~use_ixiy&pla[52])&(M4&T2);\nctl_reg_out_lo = ctl_reg_out_lo | (~use_ixiy&pla[52])&(M4&T2);\nctl_flags_bus = ctl_flags_bus | (~use_ixiy&pla[52])&(M4&T2);\nctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[52])&(M4&T2)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[52])&(M4&T2);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[52])&(M4&T2);\nctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[52])&(M4&T2);\nctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[52])&(M4&T2);\nctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[52])&(M4&T2);\nctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[52])&(M4&T2);\nctl_flags_cf_we = ctl_flags_cf_we | (~use_ixiy&pla[52])&(M4&T2);\nfMRead = fMRead | (~use_ixiy&pla[52])&(M4&T3);\nsetM1 = setM1 | (~use_ixiy&pla[52])&(M4&T3);\nctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[52])&(M4&T3);\nctl_sw_1d = ctl_sw_1d | (~use_ixiy&pla[52])&(M4&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[52])&(M4&T3);\nctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[52])&(M4&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[52])&(M4&T3)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[52])&(M4&T3);\nctl_alu_op_low = ctl_alu_op_low | (~use_ixiy&pla[52])&(M4&T3);\nctl_state_alu = ctl_state_alu | (~use_ixiy&pla[52])&(M4&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[52])&(M4&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[52])&(M4&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[52])&(M4&T3);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[66]&~pla[53])&(M1&T1);\nctl_reg_gp_sel_pla66npla53M1T1_2 = (pla[66]&~pla[53])&(M1&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla66npla53M1T1_2,ctl_reg_gp_sel_pla66npla53M1T1_2})&(op54);\nctl_reg_gp_hilo_pla66npla53M1T1_3 = (pla[66]&~pla[53])&(M1&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla66npla53M1T1_3,ctl_reg_gp_hilo_pla66npla53M1T1_3})&({~rsel3,rsel3});\nctl_reg_in_hi = ctl_reg_in_hi | (pla[66]&~pla[53])&(M1&T1);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[66]&~pla[53])&(M1&T1);\nctl_sw_2u = ctl_sw_2u | (pla[66]&~pla[53])&(M1&T1);\nctl_flags_alu = ctl_flags_alu | (pla[66]&~pla[53])&(M1&T1);\nctl_alu_oe = ctl_alu_oe | (pla[66]&~pla[53])&(M1&T1);\nctl_alu_res_oe = ctl_alu_res_oe | (pla[66]&~pla[53])&(M1&T1);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[66]&~pla[53])&(M1&T1);\nctl_alu_core_hf = ctl_alu_core_hf | (pla[66]&~pla[53])&(M1&T1)&(~ctl_alu_op_low);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[66]&~pla[53])&(M1&T1);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[66]&~pla[53])&(M1&T1);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[66]&~pla[53])&(M1&T1);\nctl_pf_sel_pla66npla53M1T1_15 = (pla[66]&~pla[53])&(M1&T1);\nctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_pla66npla53M1T1_15,ctl_pf_sel_pla66npla53M1T1_15})&(`PFSEL_V);\nctl_flags_use_cf2 = ctl_flags_use_cf2 | (pla[66]&~pla[53])&(M1&T1);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[66]&~pla[53])&(M1&T2);\nctl_reg_gp_sel_pla66npla53M1T2_2 = (pla[66]&~pla[53])&(M1&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla66npla53M1T2_2,ctl_reg_gp_sel_pla66npla53M1T2_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla66npla53M1T2_3 = (pla[66]&~pla[53])&(M1&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla66npla53M1T2_3,ctl_reg_gp_hilo_pla66npla53M1T2_3})&(2'b01);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[66]&~pla[53])&(M1&T2);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[66]&~pla[53])&(M1&T2);\nctl_flags_oe = ctl_flags_oe | (pla[66]&~pla[53])&(M1&T2);\nctl_flags_hf_cpl = ctl_flags_hf_cpl | (pla[66]&~pla[53])&(M1&T2)&(flags_nf);\nctl_reg_gp_sel_pla66npla53M1T3_1 = (pla[66]&~pla[53])&(M1&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla66npla53M1T3_1,ctl_reg_gp_sel_pla66npla53M1T3_1})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla66npla53M1T3_2 = (pla[66]&~pla[53])&(M1&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla66npla53M1T3_2,ctl_reg_gp_hilo_pla66npla53M1T3_2})&(2'b11);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[66]&~pla[53])&(M1&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[66]&~pla[53])&(M1&T3);\nctl_flags_bus = ctl_flags_bus | (pla[66]&~pla[53])&(M1&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[66]&~pla[53])&(M1&T3)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[66]&~pla[53])&(M1&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[66]&~pla[53])&(M1&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[66]&~pla[53])&(M1&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[66]&~pla[53])&(M1&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[66]&~pla[53])&(M1&T3);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[66]&~pla[53])&(M1&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[66]&~pla[53])&(M1&T3);\nctl_flags_cf_we = ctl_flags_cf_we | (pla[66]&~pla[53])&(M1&T3);\nvalidPLA = validPLA | (pla[66]&~pla[53])&(M1&T4);\nsetM1 = setM1 | (pla[66]&~pla[53])&(M1&T4);\nctl_bus_zero_oe = ctl_bus_zero_oe | (pla[66]&~pla[53])&(M1&T4)&(op4&op5&~op3);\nctl_reg_gp_sel_pla66npla53M1T4nop4op5nop3_1 = (pla[66]&~pla[53])&(M1&T4)&(~(op4&op5&~op3));\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla66npla53M1T4nop4op5nop3_1,ctl_reg_gp_sel_pla66npla53M1T4nop4op5nop3_1})&(op54);\nctl_reg_gp_hilo_pla66npla53M1T4nop4op5nop3_2 = (pla[66]&~pla[53])&(M1&T4)&(~(op4&op5&~op3));\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla66npla53M1T4nop4op5nop3_2,ctl_reg_gp_hilo_pla66npla53M1T4nop4op5nop3_2})&({~rsel3,rsel3});\nctl_reg_out_hi = ctl_reg_out_hi | (pla[66]&~pla[53])&(M1&T4)&(~rsel3);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[66]&~pla[53])&(M1&T4)&(rsel3);\nctl_sw_2u = ctl_sw_2u | (pla[66]&~pla[53])&(M1&T4)&(~rsel3);\nctl_sw_2d = ctl_sw_2d | (pla[66]&~pla[53])&(M1&T4)&(rsel3);\nctl_flags_alu = ctl_flags_alu | (pla[66]&~pla[53])&(M1&T4);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[66]&~pla[53])&(M1&T4)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_zero = ctl_alu_op2_sel_zero | (pla[66]&~pla[53])&(M1&T4);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[66]&~pla[53])&(M1&T4);\nctl_alu_op_low = ctl_alu_op_low | (pla[66]&~pla[53])&(M1&T4);\nctl_alu_core_hf = ctl_alu_core_hf | (pla[66]&~pla[53])&(M1&T4)&(~ctl_alu_op_low);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[66]&~pla[53])&(M1&T4);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[66]&~pla[53])&(M1&T4);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[66]&~pla[53])&(M1&T4);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[66]&~pla[53])&(M1&T4);\nctl_flags_nf_clr = ctl_flags_nf_clr | (pla[66]&~pla[53])&(M1&T4);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[66]&~pla[53])&(M1&T4);\nctl_flags_cf2_we = ctl_flags_cf2_we | (pla[66]&~pla[53])&(M1&T4);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[75])&(M1&T1);\nctl_flags_nf_set = ctl_flags_nf_set | (pla[75])&(M1&T1);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[75])&(M1&T1);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[75])&(M1&T1);\nctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[75])&(M1&T1);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[75])&(M1&T4);\nctl_flags_nf_set = ctl_flags_nf_set | (pla[75])&(M1&T4);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[75])&(M1&T4);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[75])&(M1&T4);\nctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[75])&(M1&T4);\nctl_flags_nf_we = ctl_flags_nf_we | ((M2|M4)&pla[75]);\nctl_flags_nf_set = ctl_flags_nf_set | ((M2|M4)&pla[75]);\nctl_flags_cf_set = ctl_flags_cf_set | ((M2|M4)&pla[75]);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | ((M2|M4)&pla[75]);\nctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | ((M2|M4)&pla[75]);\nctl_reg_gp_sel_use_ixiypla53M1T3_1 = (use_ixiy&pla[53])&(M1&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_use_ixiypla53M1T3_1,ctl_reg_gp_sel_use_ixiypla53M1T3_1})&(`GP_REG_AF);\nctl_reg_gp_hilo_use_ixiypla53M1T3_2 = (use_ixiy&pla[53])&(M1&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_use_ixiypla53M1T3_2,ctl_reg_gp_hilo_use_ixiypla53M1T3_2})&(2'b11);\nctl_reg_out_hi = ctl_reg_out_hi | (use_ixiy&pla[53])&(M1&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (use_ixiy&pla[53])&(M1&T3);\nctl_flags_bus = ctl_flags_bus | (use_ixiy&pla[53])&(M1&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (use_ixiy&pla[53])&(M1&T3)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (use_ixiy&pla[53])&(M1&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (use_ixiy&pla[53])&(M1&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (use_ixiy&pla[53])&(M1&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (use_ixiy&pla[53])&(M1&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (use_ixiy&pla[53])&(M1&T3);\nctl_flags_pf_we = ctl_flags_pf_we | (use_ixiy&pla[53])&(M1&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (use_ixiy&pla[53])&(M1&T3);\nctl_flags_cf_we = ctl_flags_cf_we | (use_ixiy&pla[53])&(M1&T3);\nvalidPLA = validPLA | (use_ixiy&pla[53])&(M1&T4);\nnextM = nextM | (use_ixiy&pla[53])&(M1&T4);\nctl_mRead = ctl_mRead | (use_ixiy&pla[53])&(M1&T4);\nfMRead = fMRead | (use_ixiy&pla[53])&(M2&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (use_ixiy&pla[53])&(M2&T1);\nctl_reg_sys_hilo_use_ixiypla53M2T1_3 = (use_ixiy&pla[53])&(M2&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_use_ixiypla53M2T1_3,ctl_reg_sys_hilo_use_ixiypla53M2T1_3})&(2'b11);\nctl_al_we = ctl_al_we | (use_ixiy&pla[53])&(M2&T1);\nfMRead = fMRead | (use_ixiy&pla[53])&(M2&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (use_ixiy&pla[53])&(M2&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (use_ixiy&pla[53])&(M2&T2);\nctl_reg_sys_hilo_use_ixiypla53M2T2_4 = (use_ixiy&pla[53])&(M2&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_use_ixiypla53M2T2_4,ctl_reg_sys_hilo_use_ixiypla53M2T2_4})&(2'b11);\npc_inc_hold = pc_inc_hold | (use_ixiy&pla[53])&(M2&T2)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (use_ixiy&pla[53])&(M2&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (use_ixiy&pla[53])&(M2&T2);\nfMRead = fMRead | (use_ixiy&pla[53])&(M2&T3);\nnextM = nextM | (use_ixiy&pla[53])&(M2&T3);\nixy_d = ixy_d | (use_ixiy&pla[53])&(M3&T1);\nixy_d = ixy_d | (use_ixiy&pla[53])&(M3&T2);\nixy_d = ixy_d | (use_ixiy&pla[53])&(M3&T3);\nixy_d = ixy_d | (use_ixiy&pla[53])&(M3&T4);\nnextM = nextM | (use_ixiy&pla[53])&(M3&T5);\nctl_mRead = ctl_mRead | (use_ixiy&pla[53])&(M3&T5);\nixy_d = ixy_d | (use_ixiy&pla[53])&(M3&T5);\nctl_reg_gp_we = ctl_reg_gp_we | (~use_ixiy&pla[53])&(M1&T2);\nctl_reg_gp_sel_nuse_ixiypla53M1T2_2 = (~use_ixiy&pla[53])&(M1&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla53M1T2_2,ctl_reg_gp_sel_nuse_ixiypla53M1T2_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_nuse_ixiypla53M1T2_3 = (~use_ixiy&pla[53])&(M1&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla53M1T2_3,ctl_reg_gp_hilo_nuse_ixiypla53M1T2_3})&(2'b01);\nctl_reg_in_hi = ctl_reg_in_hi | (~use_ixiy&pla[53])&(M1&T2);\nctl_reg_in_lo = ctl_reg_in_lo | (~use_ixiy&pla[53])&(M1&T2);\nctl_flags_oe = ctl_flags_oe | (~use_ixiy&pla[53])&(M1&T2);\nctl_flags_hf_cpl = ctl_flags_hf_cpl | (~use_ixiy&pla[53])&(M1&T2)&(flags_nf);\nctl_reg_gp_sel_nuse_ixiypla53M1T3_1 = (~use_ixiy&pla[53])&(M1&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla53M1T3_1,ctl_reg_gp_sel_nuse_ixiypla53M1T3_1})&(`GP_REG_AF);\nctl_reg_gp_hilo_nuse_ixiypla53M1T3_2 = (~use_ixiy&pla[53])&(M1&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla53M1T3_2,ctl_reg_gp_hilo_nuse_ixiypla53M1T3_2})&(2'b11);\nctl_reg_out_hi = ctl_reg_out_hi | (~use_ixiy&pla[53])&(M1&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (~use_ixiy&pla[53])&(M1&T3);\nctl_flags_bus = ctl_flags_bus | (~use_ixiy&pla[53])&(M1&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[53])&(M1&T3)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[53])&(M1&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[53])&(M1&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[53])&(M1&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[53])&(M1&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[53])&(M1&T3);\nctl_flags_pf_we = ctl_flags_pf_we | (~use_ixiy&pla[53])&(M1&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[53])&(M1&T3);\nctl_flags_cf_we = ctl_flags_cf_we | (~use_ixiy&pla[53])&(M1&T3);\nvalidPLA = validPLA | (~use_ixiy&pla[53])&(M1&T4);\nnextM = nextM | (~use_ixiy&pla[53])&(M1&T4);\nctl_mRead = ctl_mRead | (~use_ixiy&pla[53])&(M1&T4);\nfMRead = fMRead | (~use_ixiy&pla[53])&(M2&T1);\nctl_reg_gp_sel_nuse_ixiypla53M2T1_2 = (~use_ixiy&pla[53])&(M2&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla53M2T1_2,ctl_reg_gp_sel_nuse_ixiypla53M2T1_2})&(`GP_REG_HL);\nctl_reg_gp_hilo_nuse_ixiypla53M2T1_3 = (~use_ixiy&pla[53])&(M2&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla53M2T1_3,ctl_reg_gp_hilo_nuse_ixiypla53M2T1_3})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (~use_ixiy&pla[53])&(M2&T1);\nctl_al_we = ctl_al_we | (~use_ixiy&pla[53])&(M2&T1);\nfMRead = fMRead | (~use_ixiy&pla[53])&(M2&T2);\nfMRead = fMRead | (~use_ixiy&pla[53])&(M2&T3);\nctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[53])&(M2&T3);\nctl_sw_1d = ctl_sw_1d | (~use_ixiy&pla[53])&(M2&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[53])&(M2&T3);\nctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[53])&(M2&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[53])&(M2&T3)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_zero = ctl_alu_op2_sel_zero | (~use_ixiy&pla[53])&(M2&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[53])&(M2&T3);\nctl_alu_op_low = ctl_alu_op_low | (~use_ixiy&pla[53])&(M2&T3);\nctl_alu_core_hf = ctl_alu_core_hf | (~use_ixiy&pla[53])&(M2&T3)&(~ctl_alu_op_low);\nctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[53])&(M2&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[53])&(M2&T3);\nctl_flags_nf_clr = ctl_flags_nf_clr | (~use_ixiy&pla[53])&(M2&T3);\nctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[53])&(M2&T3);\nctl_flags_cf2_we = ctl_flags_cf2_we | (~use_ixiy&pla[53])&(M2&T3);\nnextM = nextM | (~use_ixiy&pla[53])&(M2&T4);\nctl_mWrite = ctl_mWrite | (~use_ixiy&pla[53])&(M2&T4);\nctl_sw_2u = ctl_sw_2u | (~use_ixiy&pla[53])&(M2&T4);\nctl_sw_1u = ctl_sw_1u | (~use_ixiy&pla[53])&(M2&T4);\nctl_bus_db_we = ctl_bus_db_we | (~use_ixiy&pla[53])&(M2&T4);\nctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[53])&(M2&T4);\nctl_alu_oe = ctl_alu_oe | (~use_ixiy&pla[53])&(M2&T4);\nctl_alu_res_oe = ctl_alu_res_oe | (~use_ixiy&pla[53])&(M2&T4);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (~use_ixiy&pla[53])&(M2&T4);\nctl_alu_core_hf = ctl_alu_core_hf | (~use_ixiy&pla[53])&(M2&T4)&(~ctl_alu_op_low);\nctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[53])&(M2&T4);\nctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[53])&(M2&T4);\nctl_flags_pf_we = ctl_flags_pf_we | (~use_ixiy&pla[53])&(M2&T4);\nctl_pf_sel_nuse_ixiypla53M2T4_14 = (~use_ixiy&pla[53])&(M2&T4);\nctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_nuse_ixiypla53M2T4_14,ctl_pf_sel_nuse_ixiypla53M2T4_14})&(`PFSEL_V);\nctl_flags_use_cf2 = ctl_flags_use_cf2 | (~use_ixiy&pla[53])&(M2&T4);\nfMWrite = fMWrite | (~use_ixiy&pla[53])&(M3&T1);\nctl_bus_inc_oe = ctl_bus_inc_oe | (~use_ixiy&pla[53])&(M3&T1);\nfMWrite = fMWrite | (~use_ixiy&pla[53])&(M3&T2);\nfMWrite = fMWrite | (~use_ixiy&pla[53])&(M3&T3);\nsetM1 = setM1 | (~use_ixiy&pla[53])&(M3&T3);\nfMRead = fMRead | (~use_ixiy&pla[53])&(M4&T1);\nctl_bus_inc_oe = ctl_bus_inc_oe | (~use_ixiy&pla[53])&(M4&T1);\nfMRead = fMRead | (~use_ixiy&pla[53])&(M4&T2);\nfMRead = fMRead | (~use_ixiy&pla[53])&(M4&T3);\nctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[53])&(M4&T3);\nctl_sw_1d = ctl_sw_1d | (~use_ixiy&pla[53])&(M4&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[53])&(M4&T3);\nctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[53])&(M4&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[53])&(M4&T3)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_zero = ctl_alu_op2_sel_zero | (~use_ixiy&pla[53])&(M4&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[53])&(M4&T3);\nctl_alu_op_low = ctl_alu_op_low | (~use_ixiy&pla[53])&(M4&T3);\nctl_alu_core_hf = ctl_alu_core_hf | (~use_ixiy&pla[53])&(M4&T3)&(~ctl_alu_op_low);\nctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[53])&(M4&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[53])&(M4&T3);\nctl_flags_nf_clr = ctl_flags_nf_clr | (~use_ixiy&pla[53])&(M4&T3);\nctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[53])&(M4&T3);\nctl_flags_cf2_we = ctl_flags_cf2_we | (~use_ixiy&pla[53])&(M4&T3);\nnextM = nextM | (~use_ixiy&pla[53])&(M4&T4);\nctl_mWrite = ctl_mWrite | (~use_ixiy&pla[53])&(M4&T4);\nctl_sw_2u = ctl_sw_2u | (~use_ixiy&pla[53])&(M4&T4);\nctl_sw_1u = ctl_sw_1u | (~use_ixiy&pla[53])&(M4&T4);\nctl_bus_db_we = ctl_bus_db_we | (~use_ixiy&pla[53])&(M4&T4);\nctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[53])&(M4&T4);\nctl_alu_oe = ctl_alu_oe | (~use_ixiy&pla[53])&(M4&T4);\nctl_alu_res_oe = ctl_alu_res_oe | (~use_ixiy&pla[53])&(M4&T4);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (~use_ixiy&pla[53])&(M4&T4);\nctl_alu_core_hf = ctl_alu_core_hf | (~use_ixiy&pla[53])&(M4&T4)&(~ctl_alu_op_low);\nctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[53])&(M4&T4);\nctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[53])&(M4&T4);\nctl_flags_pf_we = ctl_flags_pf_we | (~use_ixiy&pla[53])&(M4&T4);\nctl_pf_sel_nuse_ixiypla53M4T4_14 = (~use_ixiy&pla[53])&(M4&T4);\nctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_nuse_ixiypla53M4T4_14,ctl_pf_sel_nuse_ixiypla53M4T4_14})&(`PFSEL_V);\nctl_flags_use_cf2 = ctl_flags_use_cf2 | (~use_ixiy&pla[53])&(M4&T4);\nfMWrite = fMWrite | (~use_ixiy&pla[53])&(M5&T1);\nctl_bus_inc_oe = ctl_bus_inc_oe | (~use_ixiy&pla[53])&(M5&T1);\nfMWrite = fMWrite | (~use_ixiy&pla[53])&(M5&T2);\nfMWrite = fMWrite | (~use_ixiy&pla[53])&(M5&T3);\nsetM1 = setM1 | (~use_ixiy&pla[53])&(M5&T3);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[69])&(M1&T2);\nctl_reg_gp_sel_pla69M1T2_2 = (pla[69])&(M1&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla69M1T2_2,ctl_reg_gp_sel_pla69M1T2_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla69M1T2_3 = (pla[69])&(M1&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla69M1T2_3,ctl_reg_gp_hilo_pla69M1T2_3})&(2'b01);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[69])&(M1&T2);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[69])&(M1&T2);\nctl_flags_oe = ctl_flags_oe | (pla[69])&(M1&T2);\nctl_reg_gp_sel_pla69M1T3_1 = (pla[69])&(M1&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla69M1T3_1,ctl_reg_gp_sel_pla69M1T3_1})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla69M1T3_2 = (pla[69])&(M1&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla69M1T3_2,ctl_reg_gp_hilo_pla69M1T3_2})&(2'b11);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[69])&(M1&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[69])&(M1&T3);\nctl_flags_bus = ctl_flags_bus | (pla[69])&(M1&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[69])&(M1&T3)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[69])&(M1&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[69])&(M1&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[69])&(M1&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[69])&(M1&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[69])&(M1&T3);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[69])&(M1&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[69])&(M1&T3);\nctl_flags_nf_clr = ctl_flags_nf_clr | (pla[69])&(M1&T3);\nctl_flags_cf_we = ctl_flags_cf_we | (pla[69])&(M1&T3);\nvalidPLA = validPLA | (pla[69])&(M1&T4);\nnextM = nextM | (pla[69])&(M1&T4);\nctl_reg_gp_sel_pla69M1T4_3 = (pla[69])&(M1&T4);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla69M1T4_3,ctl_reg_gp_sel_pla69M1T4_3})&(`GP_REG_HL);\nctl_reg_gp_hilo_pla69M1T4_4 = (pla[69])&(M1&T4);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla69M1T4_4,ctl_reg_gp_hilo_pla69M1T4_4})&(2'b01);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[69])&(M1&T4);\nctl_sw_2d = ctl_sw_2d | (pla[69])&(M1&T4);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[69])&(M1&T4)&(~ctl_alu_bs_oe);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[69])&(M1&T4);\nctl_reg_gp_sel_pla69M2T1_1 = (pla[69])&(M2&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla69M2T1_1,ctl_reg_gp_sel_pla69M2T1_1})&(op54);\nctl_reg_gp_hilo_pla69M2T1_2 = (pla[69])&(M2&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla69M2T1_2,ctl_reg_gp_hilo_pla69M2T1_2})&(2'b01);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[69])&(M2&T1);\nctl_sw_2d = ctl_sw_2d | (pla[69])&(M2&T1);\nctl_flags_alu = ctl_flags_alu | (pla[69])&(M2&T1);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[69])&(M2&T1)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[69])&(M2&T1);\nctl_alu_op_low = ctl_alu_op_low | (pla[69])&(M2&T1);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[69])&(M2&T1)&(ctl_alu_op_low);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[69])&(M2&T1)&(ctl_alu_op_low);\nctl_alu_core_hf = ctl_alu_core_hf | (pla[69])&(M2&T1)&(~ctl_alu_op_low);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[69])&(M2&T1);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[69])&(M2&T1);\nctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (pla[69])&(M2&T2);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[69])&(M2&T2);\nctl_reg_sys_hilo_pla69M2T2_3 = (pla[69])&(M2&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla69M2T2_3,ctl_reg_sys_hilo_pla69M2T2_3})&({ctl_reg_sys_hilo[1],1'b1});\nctl_reg_in_lo = ctl_reg_in_lo | (pla[69])&(M2&T2);\nctl_sw_2u = ctl_sw_2u | (pla[69])&(M2&T2);\nctl_flags_alu = ctl_flags_alu | (pla[69])&(M2&T2);\nctl_alu_oe = ctl_alu_oe | (pla[69])&(M2&T2);\nctl_alu_res_oe = ctl_alu_res_oe | (pla[69])&(M2&T2);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[69])&(M2&T2);\nctl_alu_core_hf = ctl_alu_core_hf | (pla[69])&(M2&T2)&(~ctl_alu_op_low);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[69])&(M2&T2);\nctl_flags_cf_we = ctl_flags_cf_we | (pla[69])&(M2&T2);\nctl_reg_gp_sel_pla69M2T3_1 = (pla[69])&(M2&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla69M2T3_1,ctl_reg_gp_sel_pla69M2T3_1})&(`GP_REG_HL);\nctl_reg_gp_hilo_pla69M2T3_2 = (pla[69])&(M2&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla69M2T3_2,ctl_reg_gp_hilo_pla69M2T3_2})&(2'b10);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[69])&(M2&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[69])&(M2&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[69])&(M2&T3)&(~ctl_alu_bs_oe);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[69])&(M2&T3);\nnextM = nextM | (pla[69])&(M2&T4);\nctl_reg_gp_sel_pla69M2T4_2 = (pla[69])&(M2&T4);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla69M2T4_2,ctl_reg_gp_sel_pla69M2T4_2})&(op54);\nctl_reg_gp_hilo_pla69M2T4_3 = (pla[69])&(M2&T4);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla69M2T4_3,ctl_reg_gp_hilo_pla69M2T4_3})&(2'b10);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[69])&(M2&T4);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[69])&(M2&T4);\nctl_flags_alu = ctl_flags_alu | (pla[69])&(M2&T4);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[69])&(M2&T4)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[69])&(M2&T4);\nctl_alu_op_low = ctl_alu_op_low | (pla[69])&(M2&T4);\nctl_alu_core_hf = ctl_alu_core_hf | (pla[69])&(M2&T4)&(~ctl_alu_op_low);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[69])&(M2&T4);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[69])&(M2&T4);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[69])&(M3&T1);\nctl_reg_sys_hilo_pla69M3T1_2 = (pla[69])&(M3&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla69M3T1_2,ctl_reg_sys_hilo_pla69M3T1_2})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[69])&(M3&T1);\nctl_al_we = ctl_al_we | (pla[69])&(M3&T1);\nctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (pla[69])&(M3&T1);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[69])&(M3&T1);\nctl_reg_sys_hilo_pla69M3T1_7 = (pla[69])&(M3&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla69M3T1_7,ctl_reg_sys_hilo_pla69M3T1_7})&({1'b1,ctl_reg_sys_hilo[0]});\nctl_reg_in_hi = ctl_reg_in_hi | (pla[69])&(M3&T1);\nctl_sw_2u = ctl_sw_2u | (pla[69])&(M3&T1);\nctl_flags_alu = ctl_flags_alu | (pla[69])&(M3&T1);\nctl_alu_oe = ctl_alu_oe | (pla[69])&(M3&T1);\nctl_alu_res_oe = ctl_alu_res_oe | (pla[69])&(M3&T1);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[69])&(M3&T1);\nctl_alu_core_hf = ctl_alu_core_hf | (pla[69])&(M3&T1)&(~ctl_alu_op_low);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[69])&(M3&T1);\nctl_flags_cf_we = ctl_flags_cf_we | (pla[69])&(M3&T1);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[69])&(M3&T2);\nctl_reg_gp_sel_pla69M3T2_2 = (pla[69])&(M3&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla69M3T2_2,ctl_reg_gp_sel_pla69M3T2_2})&(`GP_REG_HL);\nctl_reg_gp_hilo_pla69M3T2_3 = (pla[69])&(M3&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla69M3T2_3,ctl_reg_gp_hilo_pla69M3T2_3})&(2'b11);\nctl_sw_4u = ctl_sw_4u | (pla[69])&(M3&T2);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[69])&(M3&T2);\nsetM1 = setM1 | (pla[69])&(M3&T3);\nctl_reg_gp_we = ctl_reg_gp_we | (op3&pla[68])&(M1&T2);\nctl_reg_gp_sel_op3pla68M1T2_2 = (op3&pla[68])&(M1&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_op3pla68M1T2_2,ctl_reg_gp_sel_op3pla68M1T2_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_op3pla68M1T2_3 = (op3&pla[68])&(M1&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_op3pla68M1T2_3,ctl_reg_gp_hilo_op3pla68M1T2_3})&(2'b01);\nctl_reg_in_hi = ctl_reg_in_hi | (op3&pla[68])&(M1&T2);\nctl_reg_in_lo = ctl_reg_in_lo | (op3&pla[68])&(M1&T2);\nctl_flags_oe = ctl_flags_oe | (op3&pla[68])&(M1&T2);\nctl_reg_gp_sel_op3pla68M1T3_1 = (op3&pla[68])&(M1&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_op3pla68M1T3_1,ctl_reg_gp_sel_op3pla68M1T3_1})&(`GP_REG_AF);\nctl_reg_gp_hilo_op3pla68M1T3_2 = (op3&pla[68])&(M1&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_op3pla68M1T3_2,ctl_reg_gp_hilo_op3pla68M1T3_2})&(2'b11);\nctl_reg_out_hi = ctl_reg_out_hi | (op3&pla[68])&(M1&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (op3&pla[68])&(M1&T3);\nctl_flags_bus = ctl_flags_bus | (op3&pla[68])&(M1&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (op3&pla[68])&(M1&T3)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (op3&pla[68])&(M1&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (op3&pla[68])&(M1&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (op3&pla[68])&(M1&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (op3&pla[68])&(M1&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (op3&pla[68])&(M1&T3);\nctl_flags_pf_we = ctl_flags_pf_we | (op3&pla[68])&(M1&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (op3&pla[68])&(M1&T3);\nctl_flags_nf_clr = ctl_flags_nf_clr | (op3&pla[68])&(M1&T3);\nctl_flags_cf_we = ctl_flags_cf_we | (op3&pla[68])&(M1&T3);\nvalidPLA = validPLA | (op3&pla[68])&(M1&T4);\nnextM = nextM | (op3&pla[68])&(M1&T4);\nctl_reg_gp_sel_op3pla68M1T4_3 = (op3&pla[68])&(M1&T4);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_op3pla68M1T4_3,ctl_reg_gp_sel_op3pla68M1T4_3})&(`GP_REG_HL);\nctl_reg_gp_hilo_op3pla68M1T4_4 = (op3&pla[68])&(M1&T4);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_op3pla68M1T4_4,ctl_reg_gp_hilo_op3pla68M1T4_4})&(2'b01);\nctl_reg_out_lo = ctl_reg_out_lo | (op3&pla[68])&(M1&T4);\nctl_sw_2d = ctl_sw_2d | (op3&pla[68])&(M1&T4);\nctl_alu_shift_oe = ctl_alu_shift_oe | (op3&pla[68])&(M1&T4)&(~ctl_alu_bs_oe);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (op3&pla[68])&(M1&T4);\nctl_reg_gp_sel_op3pla68M2T1_1 = (op3&pla[68])&(M2&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_op3pla68M2T1_1,ctl_reg_gp_sel_op3pla68M2T1_1})&(op54);\nctl_reg_gp_hilo_op3pla68M2T1_2 = (op3&pla[68])&(M2&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_op3pla68M2T1_2,ctl_reg_gp_hilo_op3pla68M2T1_2})&(2'b01);\nctl_reg_out_lo = ctl_reg_out_lo | (op3&pla[68])&(M2&T1);\nctl_sw_2d = ctl_sw_2d | (op3&pla[68])&(M2&T1);\nctl_flags_alu = ctl_flags_alu | (op3&pla[68])&(M2&T1);\nctl_alu_shift_oe = ctl_alu_shift_oe | (op3&pla[68])&(M2&T1)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (op3&pla[68])&(M2&T1);\nctl_alu_op_low = ctl_alu_op_low | (op3&pla[68])&(M2&T1);\nctl_alu_core_hf = ctl_alu_core_hf | (op3&pla[68])&(M2&T1)&(~ctl_alu_op_low);\nctl_flags_hf_we = ctl_flags_hf_we | (op3&pla[68])&(M2&T1);\nctl_reg_use_sp = ctl_reg_use_sp | (op3&pla[68])&(M2&T1);\nctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (op3&pla[68])&(M2&T2);\nctl_reg_sel_wz = ctl_reg_sel_wz | (op3&pla[68])&(M2&T2);\nctl_reg_sys_hilo_op3pla68M2T2_3 = (op3&pla[68])&(M2&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_op3pla68M2T2_3,ctl_reg_sys_hilo_op3pla68M2T2_3})&({ctl_reg_sys_hilo[1],1'b1});\nctl_reg_in_lo = ctl_reg_in_lo | (op3&pla[68])&(M2&T2);\nctl_sw_2u = ctl_sw_2u | (op3&pla[68])&(M2&T2);\nctl_flags_alu = ctl_flags_alu | (op3&pla[68])&(M2&T2);\nctl_alu_oe = ctl_alu_oe | (op3&pla[68])&(M2&T2);\nctl_alu_res_oe = ctl_alu_res_oe | (op3&pla[68])&(M2&T2);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (op3&pla[68])&(M2&T2);\nctl_alu_core_hf = ctl_alu_core_hf | (op3&pla[68])&(M2&T2)&(~ctl_alu_op_low);\nctl_flags_sz_we = ctl_flags_sz_we | (op3&pla[68])&(M2&T2);\nctl_flags_xy_we = ctl_flags_xy_we | (op3&pla[68])&(M2&T2);\nctl_flags_cf_we = ctl_flags_cf_we | (op3&pla[68])&(M2&T2);\nctl_reg_gp_sel_op3pla68M2T3_1 = (op3&pla[68])&(M2&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_op3pla68M2T3_1,ctl_reg_gp_sel_op3pla68M2T3_1})&(`GP_REG_HL);\nctl_reg_gp_hilo_op3pla68M2T3_2 = (op3&pla[68])&(M2&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_op3pla68M2T3_2,ctl_reg_gp_hilo_op3pla68M2T3_2})&(2'b10);\nctl_reg_out_hi = ctl_reg_out_hi | (op3&pla[68])&(M2&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (op3&pla[68])&(M2&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (op3&pla[68])&(M2&T3)&(~ctl_alu_bs_oe);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (op3&pla[68])&(M2&T3);\nnextM = nextM | (op3&pla[68])&(M2&T4);\nctl_reg_gp_sel_op3pla68M2T4_2 = (op3&pla[68])&(M2&T4);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_op3pla68M2T4_2,ctl_reg_gp_sel_op3pla68M2T4_2})&(op54);\nctl_reg_gp_hilo_op3pla68M2T4_3 = (op3&pla[68])&(M2&T4);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_op3pla68M2T4_3,ctl_reg_gp_hilo_op3pla68M2T4_3})&(2'b10);\nctl_reg_out_hi = ctl_reg_out_hi | (op3&pla[68])&(M2&T4);\nctl_reg_out_lo = ctl_reg_out_lo | (op3&pla[68])&(M2&T4);\nctl_flags_alu = ctl_flags_alu | (op3&pla[68])&(M2&T4);\nctl_alu_shift_oe = ctl_alu_shift_oe | (op3&pla[68])&(M2&T4)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (op3&pla[68])&(M2&T4);\nctl_alu_op_low = ctl_alu_op_low | (op3&pla[68])&(M2&T4);\nctl_alu_core_hf = ctl_alu_core_hf | (op3&pla[68])&(M2&T4)&(~ctl_alu_op_low);\nctl_flags_hf_we = ctl_flags_hf_we | (op3&pla[68])&(M2&T4);\nctl_reg_use_sp = ctl_reg_use_sp | (op3&pla[68])&(M2&T4);\nctl_reg_sel_wz = ctl_reg_sel_wz | (op3&pla[68])&(M3&T1);\nctl_reg_sys_hilo_op3pla68M3T1_2 = (op3&pla[68])&(M3&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_op3pla68M3T1_2,ctl_reg_sys_hilo_op3pla68M3T1_2})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (op3&pla[68])&(M3&T1);\nctl_al_we = ctl_al_we | (op3&pla[68])&(M3&T1);\nctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (op3&pla[68])&(M3&T1);\nctl_reg_sel_wz = ctl_reg_sel_wz | (op3&pla[68])&(M3&T1);\nctl_reg_sys_hilo_op3pla68M3T1_7 = (op3&pla[68])&(M3&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_op3pla68M3T1_7,ctl_reg_sys_hilo_op3pla68M3T1_7})&({1'b1,ctl_reg_sys_hilo[0]});\nctl_reg_in_hi = ctl_reg_in_hi | (op3&pla[68])&(M3&T1);\nctl_sw_2u = ctl_sw_2u | (op3&pla[68])&(M3&T1);\nctl_flags_alu = ctl_flags_alu | (op3&pla[68])&(M3&T1);\nctl_alu_oe = ctl_alu_oe | (op3&pla[68])&(M3&T1);\nctl_alu_res_oe = ctl_alu_res_oe | (op3&pla[68])&(M3&T1);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (op3&pla[68])&(M3&T1);\nctl_alu_core_hf = ctl_alu_core_hf | (op3&pla[68])&(M3&T1)&(~ctl_alu_op_low);\nctl_flags_sz_we = ctl_flags_sz_we | (op3&pla[68])&(M3&T1);\nctl_flags_xy_we = ctl_flags_xy_we | (op3&pla[68])&(M3&T1);\nctl_flags_pf_we = ctl_flags_pf_we | (op3&pla[68])&(M3&T1);\nctl_pf_sel_op3pla68M3T1_18 = (op3&pla[68])&(M3&T1);\nctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_op3pla68M3T1_18,ctl_pf_sel_op3pla68M3T1_18})&(`PFSEL_V);\nctl_flags_cf_we = ctl_flags_cf_we | (op3&pla[68])&(M3&T1);\nctl_alu_zero_16bit = ctl_alu_zero_16bit | (op3&pla[68])&(M3&T1);\nctl_reg_gp_we = ctl_reg_gp_we | (op3&pla[68])&(M3&T2);\nctl_reg_gp_sel_op3pla68M3T2_2 = (op3&pla[68])&(M3&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_op3pla68M3T2_2,ctl_reg_gp_sel_op3pla68M3T2_2})&(`GP_REG_HL);\nctl_reg_gp_hilo_op3pla68M3T2_3 = (op3&pla[68])&(M3&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_op3pla68M3T2_3,ctl_reg_gp_hilo_op3pla68M3T2_3})&(2'b11);\nctl_sw_4u = ctl_sw_4u | (op3&pla[68])&(M3&T2);\nctl_bus_inc_oe = ctl_bus_inc_oe | (op3&pla[68])&(M3&T2);\nsetM1 = setM1 | (op3&pla[68])&(M3&T3);\nctl_reg_gp_we = ctl_reg_gp_we | (~op3&pla[68])&(M1&T2);\nctl_reg_gp_sel_nop3pla68M1T2_2 = (~op3&pla[68])&(M1&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nop3pla68M1T2_2,ctl_reg_gp_sel_nop3pla68M1T2_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_nop3pla68M1T2_3 = (~op3&pla[68])&(M1&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nop3pla68M1T2_3,ctl_reg_gp_hilo_nop3pla68M1T2_3})&(2'b01);\nctl_reg_in_hi = ctl_reg_in_hi | (~op3&pla[68])&(M1&T2);\nctl_reg_in_lo = ctl_reg_in_lo | (~op3&pla[68])&(M1&T2);\nctl_flags_oe = ctl_flags_oe | (~op3&pla[68])&(M1&T2);\nctl_flags_hf_cpl = ctl_flags_hf_cpl | (~op3&pla[68])&(M1&T2)&(flags_nf);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (~op3&pla[68])&(M1&T2)&(flags_nf);\nctl_reg_gp_sel_nop3pla68M1T3_1 = (~op3&pla[68])&(M1&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nop3pla68M1T3_1,ctl_reg_gp_sel_nop3pla68M1T3_1})&(`GP_REG_AF);\nctl_reg_gp_hilo_nop3pla68M1T3_2 = (~op3&pla[68])&(M1&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nop3pla68M1T3_2,ctl_reg_gp_hilo_nop3pla68M1T3_2})&(2'b11);\nctl_reg_out_hi = ctl_reg_out_hi | (~op3&pla[68])&(M1&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (~op3&pla[68])&(M1&T3);\nctl_flags_bus = ctl_flags_bus | (~op3&pla[68])&(M1&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (~op3&pla[68])&(M1&T3)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~op3&pla[68])&(M1&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~op3&pla[68])&(M1&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (~op3&pla[68])&(M1&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (~op3&pla[68])&(M1&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (~op3&pla[68])&(M1&T3);\nctl_flags_pf_we = ctl_flags_pf_we | (~op3&pla[68])&(M1&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (~op3&pla[68])&(M1&T3);\nctl_flags_nf_set = ctl_flags_nf_set | (~op3&pla[68])&(M1&T3);\nctl_flags_cf_we = ctl_flags_cf_we | (~op3&pla[68])&(M1&T3);\nvalidPLA = validPLA | (~op3&pla[68])&(M1&T4);\nnextM = nextM | (~op3&pla[68])&(M1&T4);\nctl_reg_gp_sel_nop3pla68M1T4_3 = (~op3&pla[68])&(M1&T4);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nop3pla68M1T4_3,ctl_reg_gp_sel_nop3pla68M1T4_3})&(`GP_REG_HL);\nctl_reg_gp_hilo_nop3pla68M1T4_4 = (~op3&pla[68])&(M1&T4);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nop3pla68M1T4_4,ctl_reg_gp_hilo_nop3pla68M1T4_4})&(2'b01);\nctl_reg_out_lo = ctl_reg_out_lo | (~op3&pla[68])&(M1&T4);\nctl_sw_2d = ctl_sw_2d | (~op3&pla[68])&(M1&T4);\nctl_alu_shift_oe = ctl_alu_shift_oe | (~op3&pla[68])&(M1&T4)&(~ctl_alu_bs_oe);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~op3&pla[68])&(M1&T4);\nctl_reg_gp_sel_nop3pla68M2T1_1 = (~op3&pla[68])&(M2&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nop3pla68M2T1_1,ctl_reg_gp_sel_nop3pla68M2T1_1})&(op54);\nctl_reg_gp_hilo_nop3pla68M2T1_2 = (~op3&pla[68])&(M2&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nop3pla68M2T1_2,ctl_reg_gp_hilo_nop3pla68M2T1_2})&(2'b01);\nctl_reg_out_lo = ctl_reg_out_lo | (~op3&pla[68])&(M2&T1);\nctl_sw_2d = ctl_sw_2d | (~op3&pla[68])&(M2&T1);\nctl_flags_alu = ctl_flags_alu | (~op3&pla[68])&(M2&T1);\nctl_alu_shift_oe = ctl_alu_shift_oe | (~op3&pla[68])&(M2&T1)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~op3&pla[68])&(M2&T1);\nctl_alu_op_low = ctl_alu_op_low | (~op3&pla[68])&(M2&T1);\nctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (~op3&pla[68])&(M2&T1);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (~op3&pla[68])&(M2&T1)&(ctl_alu_op_low);\nctl_alu_core_hf = ctl_alu_core_hf | (~op3&pla[68])&(M2&T1)&(~ctl_alu_op_low);\nctl_flags_hf_we = ctl_flags_hf_we | (~op3&pla[68])&(M2&T1);\nctl_reg_use_sp = ctl_reg_use_sp | (~op3&pla[68])&(M2&T1);\nctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (~op3&pla[68])&(M2&T2);\nctl_reg_sel_wz = ctl_reg_sel_wz | (~op3&pla[68])&(M2&T2);\nctl_reg_sys_hilo_nop3pla68M2T2_3 = (~op3&pla[68])&(M2&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_nop3pla68M2T2_3,ctl_reg_sys_hilo_nop3pla68M2T2_3})&({ctl_reg_sys_hilo[1],1'b1});\nctl_reg_in_lo = ctl_reg_in_lo | (~op3&pla[68])&(M2&T2);\nctl_sw_2u = ctl_sw_2u | (~op3&pla[68])&(M2&T2);\nctl_flags_alu = ctl_flags_alu | (~op3&pla[68])&(M2&T2);\nctl_alu_oe = ctl_alu_oe | (~op3&pla[68])&(M2&T2);\nctl_alu_res_oe = ctl_alu_res_oe | (~op3&pla[68])&(M2&T2);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (~op3&pla[68])&(M2&T2);\nctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (~op3&pla[68])&(M2&T2);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (~op3&pla[68])&(M2&T2)&(ctl_alu_op_low);\nctl_alu_core_hf = ctl_alu_core_hf | (~op3&pla[68])&(M2&T2)&(~ctl_alu_op_low);\nctl_flags_sz_we = ctl_flags_sz_we | (~op3&pla[68])&(M2&T2);\nctl_flags_xy_we = ctl_flags_xy_we | (~op3&pla[68])&(M2&T2);\nctl_flags_cf_we = ctl_flags_cf_we | (~op3&pla[68])&(M2&T2);\nctl_reg_gp_sel_nop3pla68M2T3_1 = (~op3&pla[68])&(M2&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nop3pla68M2T3_1,ctl_reg_gp_sel_nop3pla68M2T3_1})&(`GP_REG_HL);\nctl_reg_gp_hilo_nop3pla68M2T3_2 = (~op3&pla[68])&(M2&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nop3pla68M2T3_2,ctl_reg_gp_hilo_nop3pla68M2T3_2})&(2'b10);\nctl_reg_out_hi = ctl_reg_out_hi | (~op3&pla[68])&(M2&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (~op3&pla[68])&(M2&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (~op3&pla[68])&(M2&T3)&(~ctl_alu_bs_oe);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~op3&pla[68])&(M2&T3);\nnextM = nextM | (~op3&pla[68])&(M2&T4);\nctl_reg_gp_sel_nop3pla68M2T4_2 = (~op3&pla[68])&(M2&T4);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nop3pla68M2T4_2,ctl_reg_gp_sel_nop3pla68M2T4_2})&(op54);\nctl_reg_gp_hilo_nop3pla68M2T4_3 = (~op3&pla[68])&(M2&T4);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nop3pla68M2T4_3,ctl_reg_gp_hilo_nop3pla68M2T4_3})&(2'b10);\nctl_reg_out_hi = ctl_reg_out_hi | (~op3&pla[68])&(M2&T4);\nctl_reg_out_lo = ctl_reg_out_lo | (~op3&pla[68])&(M2&T4);\nctl_flags_alu = ctl_flags_alu | (~op3&pla[68])&(M2&T4);\nctl_alu_shift_oe = ctl_alu_shift_oe | (~op3&pla[68])&(M2&T4)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~op3&pla[68])&(M2&T4);\nctl_alu_op_low = ctl_alu_op_low | (~op3&pla[68])&(M2&T4);\nctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (~op3&pla[68])&(M2&T4);\nctl_alu_core_hf = ctl_alu_core_hf | (~op3&pla[68])&(M2&T4)&(~ctl_alu_op_low);\nctl_flags_hf_we = ctl_flags_hf_we | (~op3&pla[68])&(M2&T4);\nctl_reg_use_sp = ctl_reg_use_sp | (~op3&pla[68])&(M2&T4);\nctl_reg_sel_wz = ctl_reg_sel_wz | (~op3&pla[68])&(M3&T1);\nctl_reg_sys_hilo_nop3pla68M3T1_2 = (~op3&pla[68])&(M3&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_nop3pla68M3T1_2,ctl_reg_sys_hilo_nop3pla68M3T1_2})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (~op3&pla[68])&(M3&T1);\nctl_al_we = ctl_al_we | (~op3&pla[68])&(M3&T1);\nctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (~op3&pla[68])&(M3&T1);\nctl_reg_sel_wz = ctl_reg_sel_wz | (~op3&pla[68])&(M3&T1);\nctl_reg_sys_hilo_nop3pla68M3T1_7 = (~op3&pla[68])&(M3&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_nop3pla68M3T1_7,ctl_reg_sys_hilo_nop3pla68M3T1_7})&({1'b1,ctl_reg_sys_hilo[0]});\nctl_reg_in_hi = ctl_reg_in_hi | (~op3&pla[68])&(M3&T1);\nctl_sw_2u = ctl_sw_2u | (~op3&pla[68])&(M3&T1);\nctl_flags_alu = ctl_flags_alu | (~op3&pla[68])&(M3&T1);\nctl_alu_oe = ctl_alu_oe | (~op3&pla[68])&(M3&T1);\nctl_alu_res_oe = ctl_alu_res_oe | (~op3&pla[68])&(M3&T1);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (~op3&pla[68])&(M3&T1);\nctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (~op3&pla[68])&(M3&T1);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (~op3&pla[68])&(M3&T1)&(ctl_alu_op_low);\nctl_alu_core_hf = ctl_alu_core_hf | (~op3&pla[68])&(M3&T1)&(~ctl_alu_op_low);\nctl_flags_sz_we = ctl_flags_sz_we | (~op3&pla[68])&(M3&T1);\nctl_flags_xy_we = ctl_flags_xy_we | (~op3&pla[68])&(M3&T1);\nctl_flags_pf_we = ctl_flags_pf_we | (~op3&pla[68])&(M3&T1);\nctl_pf_sel_nop3pla68M3T1_20 = (~op3&pla[68])&(M3&T1);\nctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_nop3pla68M3T1_20,ctl_pf_sel_nop3pla68M3T1_20})&(`PFSEL_V);\nctl_flags_cf_we = ctl_flags_cf_we | (~op3&pla[68])&(M3&T1);\nctl_alu_zero_16bit = ctl_alu_zero_16bit | (~op3&pla[68])&(M3&T1);\nctl_reg_gp_we = ctl_reg_gp_we | (~op3&pla[68])&(M3&T2);\nctl_reg_gp_sel_nop3pla68M3T2_2 = (~op3&pla[68])&(M3&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nop3pla68M3T2_2,ctl_reg_gp_sel_nop3pla68M3T2_2})&(`GP_REG_HL);\nctl_reg_gp_hilo_nop3pla68M3T2_3 = (~op3&pla[68])&(M3&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nop3pla68M3T2_3,ctl_reg_gp_hilo_nop3pla68M3T2_3})&(2'b11);\nctl_sw_4u = ctl_sw_4u | (~op3&pla[68])&(M3&T2);\nctl_bus_inc_oe = ctl_bus_inc_oe | (~op3&pla[68])&(M3&T2);\nsetM1 = setM1 | (~op3&pla[68])&(M3&T3);\nvalidPLA = validPLA | (pla[9])&(M1&T4);\nctl_reg_gp_sel_pla9M1T4_2 = (pla[9])&(M1&T4);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla9M1T4_2,ctl_reg_gp_sel_pla9M1T4_2})&(op54);\nctl_reg_gp_hilo_pla9M1T4_3 = (pla[9])&(M1&T4);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla9M1T4_3,ctl_reg_gp_hilo_pla9M1T4_3})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[9])&(M1&T4);\nctl_al_we = ctl_al_we | (pla[9])&(M1&T4);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[9])&(M1&T4);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[9])&(M1&T5);\nctl_reg_gp_sel_pla9M1T5_2 = (pla[9])&(M1&T5);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla9M1T5_2,ctl_reg_gp_sel_pla9M1T5_2})&(op54);\nctl_reg_gp_hilo_pla9M1T5_3 = (pla[9])&(M1&T5);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla9M1T5_3,ctl_reg_gp_hilo_pla9M1T5_3})&(2'b11);\nctl_sw_4u = ctl_sw_4u | (pla[9])&(M1&T5);\nctl_inc_cy = ctl_inc_cy | (pla[9])&(M1&T5)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[9])&(M1&T5)&(op3);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[9])&(M1&T5);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[9])&(M1&T5);\nsetM1 = setM1 | (pla[9])&(M1&T6);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[77])&(M1&T1);\nctl_reg_gp_sel_pla77M1T1_2 = (pla[77])&(M1&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla77M1T1_2,ctl_reg_gp_sel_pla77M1T1_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla77M1T1_3 = (pla[77])&(M1&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla77M1T1_3,ctl_reg_gp_hilo_pla77M1T1_3})&(2'b10);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[77])&(M1&T1);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[77])&(M1&T1);\nctl_flags_alu = ctl_flags_alu | (pla[77])&(M1&T1);\nctl_alu_oe = ctl_alu_oe | (pla[77])&(M1&T1);\nctl_alu_res_oe = ctl_alu_res_oe | (pla[77])&(M1&T1);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[77])&(M1&T1);\nctl_alu_core_hf = ctl_alu_core_hf | (pla[77])&(M1&T1)&(~ctl_alu_op_low);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[77])&(M1&T1);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[77])&(M1&T1);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[77])&(M1&T1);\nctl_pf_sel_pla77M1T1_14 = (pla[77])&(M1&T1);\nctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_pla77M1T1_14,ctl_pf_sel_pla77M1T1_14})&(`PFSEL_P);\nctl_flags_cf_we = ctl_flags_cf_we | (pla[77])&(M1&T1);\nctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[77])&(M1&T1)&(flags_nf);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[77])&(M1&T1)&(~flags_nf);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[77])&(M1&T2);\nctl_reg_gp_sel_pla77M1T2_2 = (pla[77])&(M1&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla77M1T2_2,ctl_reg_gp_sel_pla77M1T2_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla77M1T2_3 = (pla[77])&(M1&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla77M1T2_3,ctl_reg_gp_hilo_pla77M1T2_3})&(2'b01);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[77])&(M1&T2);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[77])&(M1&T2);\nctl_flags_oe = ctl_flags_oe | (pla[77])&(M1&T2);\nctl_flags_use_cf2 = ctl_flags_use_cf2 | (pla[77])&(M1&T2);\nctl_flags_hf_cpl = ctl_flags_hf_cpl | (pla[77])&(M1&T2)&(flags_nf);\nctl_reg_gp_sel_pla77M1T3_1 = (pla[77])&(M1&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla77M1T3_1,ctl_reg_gp_sel_pla77M1T3_1})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla77M1T3_2 = (pla[77])&(M1&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla77M1T3_2,ctl_reg_gp_hilo_pla77M1T3_2})&(2'b11);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[77])&(M1&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[77])&(M1&T3);\nctl_flags_bus = ctl_flags_bus | (pla[77])&(M1&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[77])&(M1&T3)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[77])&(M1&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[77])&(M1&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[77])&(M1&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[77])&(M1&T3);\nctl_flags_hf2_we = ctl_flags_hf2_we | (pla[77])&(M1&T3);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[77])&(M1&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[77])&(M1&T3);\nctl_flags_cf_we = ctl_flags_cf_we | (pla[77])&(M1&T3);\nvalidPLA = validPLA | (pla[77])&(M1&T4);\nsetM1 = setM1 | (pla[77])&(M1&T4);\nctl_sw_2d = ctl_sw_2d | (pla[77])&(M1&T4);\nctl_flags_alu = ctl_flags_alu | (pla[77])&(M1&T4);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[77])&(M1&T4)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[77])&(M1&T4);\nctl_alu_op_low = ctl_alu_op_low | (pla[77])&(M1&T4);\nctl_alu_core_hf = ctl_alu_core_hf | (pla[77])&(M1&T4)&(~ctl_alu_op_low);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[77])&(M1&T4);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[77])&(M1&T4);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[77])&(M1&T4);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[77])&(M1&T4);\nctl_flags_cf2_we = ctl_flags_cf2_we | (pla[77])&(M1&T4);\nctl_flags_cf2_sel_daa = ctl_flags_cf2_sel_daa | (pla[77])&(M1&T4);\nctl_daa_oe = ctl_daa_oe | (pla[77])&(M1&T4);\nctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[77])&(M1&T4)&(flags_nf);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[77])&(M1&T4)&(~flags_nf);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[81])&(M1&T1);\nctl_reg_gp_sel_pla81M1T1_2 = (pla[81])&(M1&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla81M1T1_2,ctl_reg_gp_sel_pla81M1T1_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla81M1T1_3 = (pla[81])&(M1&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla81M1T1_3,ctl_reg_gp_hilo_pla81M1T1_3})&(2'b10);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[81])&(M1&T1);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[81])&(M1&T1);\nctl_flags_alu = ctl_flags_alu | (pla[81])&(M1&T1);\nctl_alu_oe = ctl_alu_oe | (pla[81])&(M1&T1);\nctl_alu_res_oe = ctl_alu_res_oe | (pla[81])&(M1&T1);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[81])&(M1&T1);\nctl_alu_core_R = ctl_alu_core_R | (pla[81])&(M1&T1);\nctl_alu_core_V = ctl_alu_core_V | (pla[81])&(M1&T1);\nctl_alu_core_S = ctl_alu_core_S | (pla[81])&(M1&T1);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[81])&(M1&T1);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[81])&(M1&T1);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[81])&(M1&T1);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[81])&(M1&T1);\nctl_flags_nf_set = ctl_flags_nf_set | (pla[81])&(M1&T1);\nctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[81])&(M1&T1);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[81])&(M1&T2);\nctl_reg_gp_sel_pla81M1T2_2 = (pla[81])&(M1&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla81M1T2_2,ctl_reg_gp_sel_pla81M1T2_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla81M1T2_3 = (pla[81])&(M1&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla81M1T2_3,ctl_reg_gp_hilo_pla81M1T2_3})&(2'b01);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[81])&(M1&T2);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[81])&(M1&T2);\nctl_flags_oe = ctl_flags_oe | (pla[81])&(M1&T2);\nctl_flags_hf_cpl = ctl_flags_hf_cpl | (pla[81])&(M1&T2)&(flags_nf);\nctl_reg_gp_sel_pla81M1T3_1 = (pla[81])&(M1&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla81M1T3_1,ctl_reg_gp_sel_pla81M1T3_1})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla81M1T3_2 = (pla[81])&(M1&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla81M1T3_2,ctl_reg_gp_hilo_pla81M1T3_2})&(2'b11);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[81])&(M1&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[81])&(M1&T3);\nctl_flags_bus = ctl_flags_bus | (pla[81])&(M1&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[81])&(M1&T3)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[81])&(M1&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[81])&(M1&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[81])&(M1&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[81])&(M1&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[81])&(M1&T3);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[81])&(M1&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[81])&(M1&T3);\nctl_flags_cf_we = ctl_flags_cf_we | (pla[81])&(M1&T3);\nvalidPLA = validPLA | (pla[81])&(M1&T4);\nsetM1 = setM1 | (pla[81])&(M1&T4);\nctl_flags_alu = ctl_flags_alu | (pla[81])&(M1&T4);\nctl_alu_op1_sel_zero = ctl_alu_op1_sel_zero | (pla[81])&(M1&T4);\nctl_alu_op_low = ctl_alu_op_low | (pla[81])&(M1&T4);\nctl_alu_core_R = ctl_alu_core_R | (pla[81])&(M1&T4);\nctl_alu_core_V = ctl_alu_core_V | (pla[81])&(M1&T4);\nctl_alu_core_S = ctl_alu_core_S | (pla[81])&(M1&T4);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[81])&(M1&T4);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[81])&(M1&T4);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[81])&(M1&T4);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[81])&(M1&T4);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[81])&(M1&T4);\nctl_flags_nf_set = ctl_flags_nf_set | (pla[81])&(M1&T4);\nctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[81])&(M1&T4);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[82])&(M1&T1);\nctl_reg_gp_sel_pla82M1T1_2 = (pla[82])&(M1&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla82M1T1_2,ctl_reg_gp_sel_pla82M1T1_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla82M1T1_3 = (pla[82])&(M1&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla82M1T1_3,ctl_reg_gp_hilo_pla82M1T1_3})&(2'b10);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[82])&(M1&T1);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[82])&(M1&T1);\nctl_flags_alu = ctl_flags_alu | (pla[82])&(M1&T1);\nctl_alu_oe = ctl_alu_oe | (pla[82])&(M1&T1);\nctl_alu_res_oe = ctl_alu_res_oe | (pla[82])&(M1&T1);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[82])&(M1&T1);\nctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[82])&(M1&T1);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[82])&(M1&T1)&(ctl_alu_op_low);\nctl_alu_core_hf = ctl_alu_core_hf | (pla[82])&(M1&T1)&(~ctl_alu_op_low);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[82])&(M1&T1);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[82])&(M1&T1);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[82])&(M1&T1);\nctl_pf_sel_pla82M1T1_16 = (pla[82])&(M1&T1);\nctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_pla82M1T1_16,ctl_pf_sel_pla82M1T1_16})&(`PFSEL_V);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[82])&(M1&T1);\nctl_flags_nf_set = ctl_flags_nf_set | (pla[82])&(M1&T1);\nctl_flags_cf_we = ctl_flags_cf_we | (pla[82])&(M1&T1);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[82])&(M1&T2);\nctl_reg_gp_sel_pla82M1T2_2 = (pla[82])&(M1&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla82M1T2_2,ctl_reg_gp_sel_pla82M1T2_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla82M1T2_3 = (pla[82])&(M1&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla82M1T2_3,ctl_reg_gp_hilo_pla82M1T2_3})&(2'b01);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[82])&(M1&T2);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[82])&(M1&T2);\nctl_flags_oe = ctl_flags_oe | (pla[82])&(M1&T2);\nctl_flags_hf_cpl = ctl_flags_hf_cpl | (pla[82])&(M1&T2)&(flags_nf);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[82])&(M1&T2)&(flags_nf);\nctl_reg_gp_sel_pla82M1T3_1 = (pla[82])&(M1&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla82M1T3_1,ctl_reg_gp_sel_pla82M1T3_1})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla82M1T3_2 = (pla[82])&(M1&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla82M1T3_2,ctl_reg_gp_hilo_pla82M1T3_2})&(2'b11);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[82])&(M1&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[82])&(M1&T3);\nctl_flags_bus = ctl_flags_bus | (pla[82])&(M1&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[82])&(M1&T3)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[82])&(M1&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[82])&(M1&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[82])&(M1&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[82])&(M1&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[82])&(M1&T3);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[82])&(M1&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[82])&(M1&T3);\nctl_flags_cf_we = ctl_flags_cf_we | (pla[82])&(M1&T3);\nvalidPLA = validPLA | (pla[82])&(M1&T4);\nsetM1 = setM1 | (pla[82])&(M1&T4);\nctl_flags_alu = ctl_flags_alu | (pla[82])&(M1&T4);\nctl_alu_op1_sel_zero = ctl_alu_op1_sel_zero | (pla[82])&(M1&T4);\nctl_alu_op_low = ctl_alu_op_low | (pla[82])&(M1&T4);\nctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[82])&(M1&T4);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[82])&(M1&T4)&(ctl_alu_op_low);\nctl_alu_core_hf = ctl_alu_core_hf | (pla[82])&(M1&T4)&(~ctl_alu_op_low);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[82])&(M1&T4);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[82])&(M1&T4);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[82])&(M1&T4);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[82])&(M1&T4);\nctl_flags_nf_set = ctl_flags_nf_set | (pla[82])&(M1&T4);\nctl_flags_cf_we = ctl_flags_cf_we | (pla[82])&(M1&T4);\nctl_flags_alu = ctl_flags_alu | (pla[89])&(M1&T1);\nctl_alu_oe = ctl_alu_oe | (pla[89])&(M1&T1);\nctl_alu_res_oe = ctl_alu_res_oe | (pla[89])&(M1&T1);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[89])&(M1&T1);\nctl_alu_core_R = ctl_alu_core_R | (pla[89])&(M1&T1);\nctl_alu_core_V = ctl_alu_core_V | (pla[89])&(M1&T1);\nctl_alu_core_S = ctl_alu_core_S | (pla[89])&(M1&T1);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[89])&(M1&T1);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[89])&(M1&T1);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[89])&(M1&T1);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[89])&(M1&T1);\nctl_flags_nf_clr = ctl_flags_nf_clr | (pla[89])&(M1&T1);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[89])&(M1&T2);\nctl_reg_gp_sel_pla89M1T2_2 = (pla[89])&(M1&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla89M1T2_2,ctl_reg_gp_sel_pla89M1T2_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla89M1T2_3 = (pla[89])&(M1&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla89M1T2_3,ctl_reg_gp_hilo_pla89M1T2_3})&(2'b01);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[89])&(M1&T2);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[89])&(M1&T2);\nctl_flags_oe = ctl_flags_oe | (pla[89])&(M1&T2);\nctl_flags_cf_we = ctl_flags_cf_we | (pla[89])&(M1&T2);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[89])&(M1&T2);\nctl_flags_hf_cpl = ctl_flags_hf_cpl | (pla[89])&(M1&T2)&(~flags_cf);\nctl_reg_gp_sel_pla89M1T3_1 = (pla[89])&(M1&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla89M1T3_1,ctl_reg_gp_sel_pla89M1T3_1})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla89M1T3_2 = (pla[89])&(M1&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla89M1T3_2,ctl_reg_gp_hilo_pla89M1T3_2})&(2'b11);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[89])&(M1&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[89])&(M1&T3);\nctl_flags_bus = ctl_flags_bus | (pla[89])&(M1&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[89])&(M1&T3)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[89])&(M1&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[89])&(M1&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[89])&(M1&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[89])&(M1&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[89])&(M1&T3);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[89])&(M1&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[89])&(M1&T3);\nctl_flags_cf_we = ctl_flags_cf_we | (pla[89])&(M1&T3);\nvalidPLA = validPLA | (pla[89])&(M1&T4);\nsetM1 = setM1 | (pla[89])&(M1&T4);\nctl_flags_alu = ctl_flags_alu | (pla[89])&(M1&T4);\nctl_alu_op_low = ctl_alu_op_low | (pla[89])&(M1&T4);\nctl_alu_core_R = ctl_alu_core_R | (pla[89])&(M1&T4);\nctl_alu_core_V = ctl_alu_core_V | (pla[89])&(M1&T4);\nctl_alu_core_S = ctl_alu_core_S | (pla[89])&(M1&T4);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[89])&(M1&T4);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[89])&(M1&T4);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[89])&(M1&T4);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[89])&(M1&T4);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[89])&(M1&T4);\nctl_flags_nf_clr = ctl_flags_nf_clr | (pla[89])&(M1&T4);\nctl_flags_alu = ctl_flags_alu | (pla[92])&(M1&T1);\nctl_alu_oe = ctl_alu_oe | (pla[92])&(M1&T1);\nctl_alu_res_oe = ctl_alu_res_oe | (pla[92])&(M1&T1);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[92])&(M1&T1);\nctl_alu_core_R = ctl_alu_core_R | (pla[92])&(M1&T1);\nctl_alu_core_V = ctl_alu_core_V | (pla[92])&(M1&T1);\nctl_alu_core_S = ctl_alu_core_S | (pla[92])&(M1&T1);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[92])&(M1&T1);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[92])&(M1&T1);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[92])&(M1&T1);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[92])&(M1&T1);\nctl_flags_nf_clr = ctl_flags_nf_clr | (pla[92])&(M1&T1);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[92])&(M1&T2);\nctl_reg_gp_sel_pla92M1T2_2 = (pla[92])&(M1&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla92M1T2_2,ctl_reg_gp_sel_pla92M1T2_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla92M1T2_3 = (pla[92])&(M1&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla92M1T2_3,ctl_reg_gp_hilo_pla92M1T2_3})&(2'b01);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[92])&(M1&T2);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[92])&(M1&T2);\nctl_flags_oe = ctl_flags_oe | (pla[92])&(M1&T2);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[92])&(M1&T2);\nctl_reg_gp_sel_pla92M1T3_1 = (pla[92])&(M1&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla92M1T3_1,ctl_reg_gp_sel_pla92M1T3_1})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla92M1T3_2 = (pla[92])&(M1&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla92M1T3_2,ctl_reg_gp_hilo_pla92M1T3_2})&(2'b11);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[92])&(M1&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[92])&(M1&T3);\nctl_flags_bus = ctl_flags_bus | (pla[92])&(M1&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[92])&(M1&T3)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[92])&(M1&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[92])&(M1&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[92])&(M1&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[92])&(M1&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[92])&(M1&T3);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[92])&(M1&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[92])&(M1&T3);\nctl_flags_cf_we = ctl_flags_cf_we | (pla[92])&(M1&T3);\nvalidPLA = validPLA | (pla[92])&(M1&T4);\nsetM1 = setM1 | (pla[92])&(M1&T4);\nctl_flags_alu = ctl_flags_alu | (pla[92])&(M1&T4);\nctl_alu_op_low = ctl_alu_op_low | (pla[92])&(M1&T4);\nctl_alu_core_R = ctl_alu_core_R | (pla[92])&(M1&T4);\nctl_alu_core_V = ctl_alu_core_V | (pla[92])&(M1&T4);\nctl_alu_core_S = ctl_alu_core_S | (pla[92])&(M1&T4);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[92])&(M1&T4);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[92])&(M1&T4);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[92])&(M1&T4);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[92])&(M1&T4);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[92])&(M1&T4);\nctl_flags_nf_clr = ctl_flags_nf_clr | (pla[92])&(M1&T4);\nctl_state_halt_set = ctl_state_halt_set | (pla[95])&(M1&T3);\nvalidPLA = validPLA | (pla[95])&(M1&T4);\nsetM1 = setM1 | (pla[95])&(M1&T4);\nctl_iffx_bit = ctl_iffx_bit | (pla[97])&(M1&T3)&(op3);\nctl_iffx_we = ctl_iffx_we | (pla[97])&(M1&T3);\nvalidPLA = validPLA | (pla[97])&(M1&T4);\nsetM1 = setM1 | (pla[97])&(M1&T4);\nctl_no_ints = ctl_no_ints | (pla[97])&(M1&T4);\nctl_sw_1d = ctl_sw_1d | (pla[96])&(M1&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[96])&(M1&T3);\nctl_im_we = ctl_im_we | (pla[96])&(M1&T3);\nvalidPLA = validPLA | (pla[96])&(M1&T4);\nsetM1 = setM1 | (pla[96])&(M1&T4);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[25])&(M1&T1);\nctl_reg_gp_sel_pla25M1T1_2 = (pla[25])&(M1&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla25M1T1_2,ctl_reg_gp_sel_pla25M1T1_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla25M1T1_3 = (pla[25])&(M1&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla25M1T1_3,ctl_reg_gp_hilo_pla25M1T1_3})&(2'b10);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[25])&(M1&T1);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[25])&(M1&T1);\nctl_flags_alu = ctl_flags_alu | (pla[25])&(M1&T1);\nctl_alu_oe = ctl_alu_oe | (pla[25])&(M1&T1);\nctl_alu_res_oe = ctl_alu_res_oe | (pla[25])&(M1&T1);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[25])&(M1&T1);\nctl_alu_core_R = ctl_alu_core_R | (pla[25])&(M1&T1);\nctl_alu_core_V = ctl_alu_core_V | (pla[25])&(M1&T1);\nctl_alu_core_S = ctl_alu_core_S | (pla[25])&(M1&T1);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[25])&(M1&T1);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[25])&(M1&T1);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[25])&(M1&T1);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[25])&(M1&T1);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[25])&(M1&T1);\nctl_flags_nf_clr = ctl_flags_nf_clr | (pla[25])&(M1&T1);\nctl_flags_cf_we = ctl_flags_cf_we | (pla[25])&(M1&T1);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[25])&(M1&T2);\nctl_reg_gp_sel_pla25M1T2_2 = (pla[25])&(M1&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla25M1T2_2,ctl_reg_gp_sel_pla25M1T2_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla25M1T2_3 = (pla[25])&(M1&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla25M1T2_3,ctl_reg_gp_hilo_pla25M1T2_3})&(2'b01);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[25])&(M1&T2);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[25])&(M1&T2);\nctl_flags_oe = ctl_flags_oe | (pla[25])&(M1&T2);\nctl_flags_use_cf2 = ctl_flags_use_cf2 | (pla[25])&(M1&T2);\nctl_reg_gp_sel_pla25M1T3_1 = (pla[25])&(M1&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla25M1T3_1,ctl_reg_gp_sel_pla25M1T3_1})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla25M1T3_2 = (pla[25])&(M1&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla25M1T3_2,ctl_reg_gp_hilo_pla25M1T3_2})&(2'b11);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[25])&(M1&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[25])&(M1&T3);\nctl_flags_bus = ctl_flags_bus | (pla[25])&(M1&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[25])&(M1&T3)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[25])&(M1&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[25])&(M1&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[25])&(M1&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[25])&(M1&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[25])&(M1&T3);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[25])&(M1&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[25])&(M1&T3);\nctl_flags_cf_we = ctl_flags_cf_we | (pla[25])&(M1&T3);\nvalidPLA = validPLA | (pla[25])&(M1&T4);\nsetM1 = setM1 | (pla[25])&(M1&T4);\nctl_reg_gp_sel_pla25M1T4_3 = (pla[25])&(M1&T4);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla25M1T4_3,ctl_reg_gp_sel_pla25M1T4_3})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla25M1T4_4 = (pla[25])&(M1&T4);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla25M1T4_4,ctl_reg_gp_hilo_pla25M1T4_4})&(2'b10);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[25])&(M1&T4);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[25])&(M1&T4);\nctl_flags_alu = ctl_flags_alu | (pla[25])&(M1&T4);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[25])&(M1&T4);\nctl_shift_en = ctl_shift_en | (pla[25])&(M1&T4);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[25])&(M1&T4);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[25])&(M1&T4);\nctl_alu_op_low = ctl_alu_op_low | (pla[25])&(M1&T4);\nctl_alu_core_R = ctl_alu_core_R | (pla[25])&(M1&T4);\nctl_alu_core_V = ctl_alu_core_V | (pla[25])&(M1&T4);\nctl_alu_core_S = ctl_alu_core_S | (pla[25])&(M1&T4);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[25])&(M1&T4);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[25])&(M1&T4);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[25])&(M1&T4);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[25])&(M1&T4);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[25])&(M1&T4);\nctl_flags_nf_clr = ctl_flags_nf_clr | (pla[25])&(M1&T4);\nctl_flags_cf2_we = ctl_flags_cf2_we | (pla[25])&(M1&T4);\nctl_flags_cf2_sel_shift = ctl_flags_cf2_sel_shift | (pla[25])&(M1&T4);\nctl_reg_gp_we = ctl_reg_gp_we | (~use_ixiy&pla[70]&~pla[55])&(M1&T1);\nctl_reg_gp_sel_nuse_ixiypla70npla55M1T1_2 = (~use_ixiy&pla[70]&~pla[55])&(M1&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla70npla55M1T1_2,ctl_reg_gp_sel_nuse_ixiypla70npla55M1T1_2})&(op21);\nctl_reg_gp_hilo_nuse_ixiypla70npla55M1T1_3 = (~use_ixiy&pla[70]&~pla[55])&(M1&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla70npla55M1T1_3,ctl_reg_gp_hilo_nuse_ixiypla70npla55M1T1_3})&({~rsel0,rsel0});\nctl_reg_in_hi = ctl_reg_in_hi | (~use_ixiy&pla[70]&~pla[55])&(M1&T1);\nctl_reg_in_lo = ctl_reg_in_lo | (~use_ixiy&pla[70]&~pla[55])&(M1&T1);\nctl_sw_2u = ctl_sw_2u | (~use_ixiy&pla[70]&~pla[55])&(M1&T1);\nctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[70]&~pla[55])&(M1&T1);\nctl_alu_oe = ctl_alu_oe | (~use_ixiy&pla[70]&~pla[55])&(M1&T1);\nctl_alu_res_oe = ctl_alu_res_oe | (~use_ixiy&pla[70]&~pla[55])&(M1&T1);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (~use_ixiy&pla[70]&~pla[55])&(M1&T1);\nctl_alu_core_R = ctl_alu_core_R | (~use_ixiy&pla[70]&~pla[55])&(M1&T1);\nctl_alu_core_V = ctl_alu_core_V | (~use_ixiy&pla[70]&~pla[55])&(M1&T1);\nctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[70]&~pla[55])&(M1&T1);\nctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[70]&~pla[55])&(M1&T1);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (~use_ixiy&pla[70]&~pla[55])&(M1&T1);\nctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[70]&~pla[55])&(M1&T1);\nctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[70]&~pla[55])&(M1&T1);\nctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[70]&~pla[55])&(M1&T1);\nctl_flags_pf_we = ctl_flags_pf_we | (~use_ixiy&pla[70]&~pla[55])&(M1&T1);\nctl_pf_sel_nuse_ixiypla70npla55M1T1_20 = (~use_ixiy&pla[70]&~pla[55])&(M1&T1);\nctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_nuse_ixiypla70npla55M1T1_20,ctl_pf_sel_nuse_ixiypla70npla55M1T1_20})&(`PFSEL_P);\nctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[70]&~pla[55])&(M1&T1);\nctl_flags_nf_clr = ctl_flags_nf_clr | (~use_ixiy&pla[70]&~pla[55])&(M1&T1);\nctl_flags_cf_we = ctl_flags_cf_we | (~use_ixiy&pla[70]&~pla[55])&(M1&T1);\nctl_reg_gp_we = ctl_reg_gp_we | (~use_ixiy&pla[70]&~pla[55])&(M1&T2);\nctl_reg_gp_sel_nuse_ixiypla70npla55M1T2_2 = (~use_ixiy&pla[70]&~pla[55])&(M1&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla70npla55M1T2_2,ctl_reg_gp_sel_nuse_ixiypla70npla55M1T2_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_nuse_ixiypla70npla55M1T2_3 = (~use_ixiy&pla[70]&~pla[55])&(M1&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla70npla55M1T2_3,ctl_reg_gp_hilo_nuse_ixiypla70npla55M1T2_3})&(2'b01);\nctl_reg_in_hi = ctl_reg_in_hi | (~use_ixiy&pla[70]&~pla[55])&(M1&T2);\nctl_reg_in_lo = ctl_reg_in_lo | (~use_ixiy&pla[70]&~pla[55])&(M1&T2);\nctl_flags_oe = ctl_flags_oe | (~use_ixiy&pla[70]&~pla[55])&(M1&T2);\nctl_flags_use_cf2 = ctl_flags_use_cf2 | (~use_ixiy&pla[70]&~pla[55])&(M1&T2);\nctl_reg_gp_sel_nuse_ixiypla70npla55M1T3_1 = (~use_ixiy&pla[70]&~pla[55])&(M1&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla70npla55M1T3_1,ctl_reg_gp_sel_nuse_ixiypla70npla55M1T3_1})&(`GP_REG_AF);\nctl_reg_gp_hilo_nuse_ixiypla70npla55M1T3_2 = (~use_ixiy&pla[70]&~pla[55])&(M1&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla70npla55M1T3_2,ctl_reg_gp_hilo_nuse_ixiypla70npla55M1T3_2})&(2'b11);\nctl_reg_out_hi = ctl_reg_out_hi | (~use_ixiy&pla[70]&~pla[55])&(M1&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (~use_ixiy&pla[70]&~pla[55])&(M1&T3);\nctl_flags_bus = ctl_flags_bus | (~use_ixiy&pla[70]&~pla[55])&(M1&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[70]&~pla[55])&(M1&T3)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[70]&~pla[55])&(M1&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[70]&~pla[55])&(M1&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[70]&~pla[55])&(M1&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[70]&~pla[55])&(M1&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[70]&~pla[55])&(M1&T3);\nctl_flags_pf_we = ctl_flags_pf_we | (~use_ixiy&pla[70]&~pla[55])&(M1&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[70]&~pla[55])&(M1&T3);\nctl_flags_cf_we = ctl_flags_cf_we | (~use_ixiy&pla[70]&~pla[55])&(M1&T3);\nvalidPLA = validPLA | (~use_ixiy&pla[70]&~pla[55])&(M1&T4);\nsetM1 = setM1 | (~use_ixiy&pla[70]&~pla[55])&(M1&T4);\nctl_reg_gp_sel_nuse_ixiypla70npla55M1T4_3 = (~use_ixiy&pla[70]&~pla[55])&(M1&T4);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla70npla55M1T4_3,ctl_reg_gp_sel_nuse_ixiypla70npla55M1T4_3})&(op21);\nctl_reg_gp_hilo_nuse_ixiypla70npla55M1T4_4 = (~use_ixiy&pla[70]&~pla[55])&(M1&T4);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla70npla55M1T4_4,ctl_reg_gp_hilo_nuse_ixiypla70npla55M1T4_4})&({~rsel0,rsel0});\nctl_reg_out_hi = ctl_reg_out_hi | (~use_ixiy&pla[70]&~pla[55])&(M1&T4)&(~rsel0);\nctl_reg_out_lo = ctl_reg_out_lo | (~use_ixiy&pla[70]&~pla[55])&(M1&T4)&(rsel0);\nctl_sw_2u = ctl_sw_2u | (~use_ixiy&pla[70]&~pla[55])&(M1&T4)&(~rsel0);\nctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[70]&~pla[55])&(M1&T4)&(rsel0);\nctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[70]&~pla[55])&(M1&T4);\nctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[70]&~pla[55])&(M1&T4);\nctl_shift_en = ctl_shift_en | (~use_ixiy&pla[70]&~pla[55])&(M1&T4);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[70]&~pla[55])&(M1&T4);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[70]&~pla[55])&(M1&T4);\nctl_alu_op_low = ctl_alu_op_low | (~use_ixiy&pla[70]&~pla[55])&(M1&T4);\nctl_alu_core_R = ctl_alu_core_R | (~use_ixiy&pla[70]&~pla[55])&(M1&T4);\nctl_alu_core_V = ctl_alu_core_V | (~use_ixiy&pla[70]&~pla[55])&(M1&T4);\nctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[70]&~pla[55])&(M1&T4);\nctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[70]&~pla[55])&(M1&T4);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (~use_ixiy&pla[70]&~pla[55])&(M1&T4);\nctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[70]&~pla[55])&(M1&T4);\nctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[70]&~pla[55])&(M1&T4);\nctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[70]&~pla[55])&(M1&T4);\nctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[70]&~pla[55])&(M1&T4);\nctl_flags_nf_clr = ctl_flags_nf_clr | (~use_ixiy&pla[70]&~pla[55])&(M1&T4);\nctl_flags_cf2_we = ctl_flags_cf2_we | (~use_ixiy&pla[70]&~pla[55])&(M1&T4);\nctl_flags_cf2_sel_shift = ctl_flags_cf2_sel_shift | (~use_ixiy&pla[70]&~pla[55])&(M1&T4);\nfMRead = fMRead | (~use_ixiy&pla[70]&~pla[55])&(M4&T1);\nctl_reg_sel_wz = ctl_reg_sel_wz | (~use_ixiy&pla[70]&~pla[55])&(M4&T1);\nctl_reg_sys_hilo_nuse_ixiypla70npla55M4T1_3 = (~use_ixiy&pla[70]&~pla[55])&(M4&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_nuse_ixiypla70npla55M4T1_3,ctl_reg_sys_hilo_nuse_ixiypla70npla55M4T1_3})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (~use_ixiy&pla[70]&~pla[55])&(M4&T1);\nctl_al_we = ctl_al_we | (~use_ixiy&pla[70]&~pla[55])&(M4&T1);\nctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[70]&~pla[55])&(M4&T1);\nctl_ir_we = ctl_ir_we | (~use_ixiy&pla[70]&~pla[55])&(M4&T1);\nfMRead = fMRead | (~use_ixiy&pla[70]&~pla[55])&(M4&T2);\nfMRead = fMRead | (~use_ixiy&pla[70]&~pla[55])&(M4&T3);\nnextM = nextM | (~use_ixiy&pla[70]&~pla[55])&(M4&T3);\nctl_mWrite = ctl_mWrite | (~use_ixiy&pla[70]&~pla[55])&(M4&T3);\nctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[70]&~pla[55])&(M4&T3);\nctl_sw_1d = ctl_sw_1d | (~use_ixiy&pla[70]&~pla[55])&(M4&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[70]&~pla[55])&(M4&T3);\nctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[70]&~pla[55])&(M4&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[70]&~pla[55])&(M4&T3);\nctl_shift_en = ctl_shift_en | (~use_ixiy&pla[70]&~pla[55])&(M4&T3);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[70]&~pla[55])&(M4&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[70]&~pla[55])&(M4&T3);\nctl_alu_op_low = ctl_alu_op_low | (~use_ixiy&pla[70]&~pla[55])&(M4&T3);\nctl_alu_core_R = ctl_alu_core_R | (~use_ixiy&pla[70]&~pla[55])&(M4&T3);\nctl_alu_core_V = ctl_alu_core_V | (~use_ixiy&pla[70]&~pla[55])&(M4&T3);\nctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[70]&~pla[55])&(M4&T3);\nctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[70]&~pla[55])&(M4&T3);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (~use_ixiy&pla[70]&~pla[55])&(M4&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[70]&~pla[55])&(M4&T3);\nctl_flags_nf_clr = ctl_flags_nf_clr | (~use_ixiy&pla[70]&~pla[55])&(M4&T3);\nctl_flags_cf2_we = ctl_flags_cf2_we | (~use_ixiy&pla[70]&~pla[55])&(M4&T3);\nctl_flags_cf2_sel_shift = ctl_flags_cf2_sel_shift | (~use_ixiy&pla[70]&~pla[55])&(M4&T3);\nfMWrite = fMWrite | (~use_ixiy&pla[70]&~pla[55])&(M5&T1);\nctl_bus_inc_oe = ctl_bus_inc_oe | (~use_ixiy&pla[70]&~pla[55])&(M5&T1);\nctl_sw_2u = ctl_sw_2u | (~use_ixiy&pla[70]&~pla[55])&(M5&T1);\nctl_sw_1u = ctl_sw_1u | (~use_ixiy&pla[70]&~pla[55])&(M5&T1);\nctl_bus_db_we = ctl_bus_db_we | (~use_ixiy&pla[70]&~pla[55])&(M5&T1);\nctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[70]&~pla[55])&(M5&T1);\nctl_alu_oe = ctl_alu_oe | (~use_ixiy&pla[70]&~pla[55])&(M5&T1);\nctl_alu_res_oe = ctl_alu_res_oe | (~use_ixiy&pla[70]&~pla[55])&(M5&T1);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (~use_ixiy&pla[70]&~pla[55])&(M5&T1);\nctl_alu_core_R = ctl_alu_core_R | (~use_ixiy&pla[70]&~pla[55])&(M5&T1);\nctl_alu_core_V = ctl_alu_core_V | (~use_ixiy&pla[70]&~pla[55])&(M5&T1);\nctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[70]&~pla[55])&(M5&T1);\nctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[70]&~pla[55])&(M5&T1);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (~use_ixiy&pla[70]&~pla[55])&(M5&T1);\nctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[70]&~pla[55])&(M5&T1);\nctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[70]&~pla[55])&(M5&T1);\nctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[70]&~pla[55])&(M5&T1);\nctl_flags_pf_we = ctl_flags_pf_we | (~use_ixiy&pla[70]&~pla[55])&(M5&T1);\nctl_pf_sel_nuse_ixiypla70npla55M5T1_19 = (~use_ixiy&pla[70]&~pla[55])&(M5&T1);\nctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_nuse_ixiypla70npla55M5T1_19,ctl_pf_sel_nuse_ixiypla70npla55M5T1_19})&(`PFSEL_P);\nctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[70]&~pla[55])&(M5&T1);\nctl_flags_nf_clr = ctl_flags_nf_clr | (~use_ixiy&pla[70]&~pla[55])&(M5&T1);\nctl_flags_cf_we = ctl_flags_cf_we | (~use_ixiy&pla[70]&~pla[55])&(M5&T1);\nfMWrite = fMWrite | (~use_ixiy&pla[70]&~pla[55])&(M5&T2);\nfMWrite = fMWrite | (~use_ixiy&pla[70]&~pla[55])&(M5&T3);\nsetM1 = setM1 | (~use_ixiy&pla[70]&~pla[55])&(M5&T3);\nctl_reg_gp_we = ctl_reg_gp_we | (~use_ixiy&pla[70]&pla[55])&(M1&T2);\nctl_reg_gp_sel_nuse_ixiypla70pla55M1T2_2 = (~use_ixiy&pla[70]&pla[55])&(M1&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla70pla55M1T2_2,ctl_reg_gp_sel_nuse_ixiypla70pla55M1T2_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_nuse_ixiypla70pla55M1T2_3 = (~use_ixiy&pla[70]&pla[55])&(M1&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla70pla55M1T2_3,ctl_reg_gp_hilo_nuse_ixiypla70pla55M1T2_3})&(2'b01);\nctl_reg_in_hi = ctl_reg_in_hi | (~use_ixiy&pla[70]&pla[55])&(M1&T2);\nctl_reg_in_lo = ctl_reg_in_lo | (~use_ixiy&pla[70]&pla[55])&(M1&T2);\nctl_flags_oe = ctl_flags_oe | (~use_ixiy&pla[70]&pla[55])&(M1&T2);\nctl_flags_use_cf2 = ctl_flags_use_cf2 | (~use_ixiy&pla[70]&pla[55])&(M1&T2);\nctl_reg_gp_sel_nuse_ixiypla70pla55M1T3_1 = (~use_ixiy&pla[70]&pla[55])&(M1&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla70pla55M1T3_1,ctl_reg_gp_sel_nuse_ixiypla70pla55M1T3_1})&(`GP_REG_AF);\nctl_reg_gp_hilo_nuse_ixiypla70pla55M1T3_2 = (~use_ixiy&pla[70]&pla[55])&(M1&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla70pla55M1T3_2,ctl_reg_gp_hilo_nuse_ixiypla70pla55M1T3_2})&(2'b11);\nctl_reg_out_hi = ctl_reg_out_hi | (~use_ixiy&pla[70]&pla[55])&(M1&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (~use_ixiy&pla[70]&pla[55])&(M1&T3);\nctl_flags_bus = ctl_flags_bus | (~use_ixiy&pla[70]&pla[55])&(M1&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[70]&pla[55])&(M1&T3)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[70]&pla[55])&(M1&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[70]&pla[55])&(M1&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[70]&pla[55])&(M1&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[70]&pla[55])&(M1&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[70]&pla[55])&(M1&T3);\nctl_flags_pf_we = ctl_flags_pf_we | (~use_ixiy&pla[70]&pla[55])&(M1&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[70]&pla[55])&(M1&T3);\nctl_flags_cf_we = ctl_flags_cf_we | (~use_ixiy&pla[70]&pla[55])&(M1&T3);\nvalidPLA = validPLA | (~use_ixiy&pla[70]&pla[55])&(M1&T4);\nnextM = nextM | (~use_ixiy&pla[70]&pla[55])&(M1&T4);\nctl_mRead = ctl_mRead | (~use_ixiy&pla[70]&pla[55])&(M1&T4);\nfMRead = fMRead | (~use_ixiy&pla[70]&pla[55])&(M2&T1);\nctl_reg_gp_sel_nuse_ixiypla70pla55M2T1_2 = (~use_ixiy&pla[70]&pla[55])&(M2&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla70pla55M2T1_2,ctl_reg_gp_sel_nuse_ixiypla70pla55M2T1_2})&(`GP_REG_HL);\nctl_reg_gp_hilo_nuse_ixiypla70pla55M2T1_3 = (~use_ixiy&pla[70]&pla[55])&(M2&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla70pla55M2T1_3,ctl_reg_gp_hilo_nuse_ixiypla70pla55M2T1_3})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (~use_ixiy&pla[70]&pla[55])&(M2&T1);\nctl_al_we = ctl_al_we | (~use_ixiy&pla[70]&pla[55])&(M2&T1);\nfMRead = fMRead | (~use_ixiy&pla[70]&pla[55])&(M2&T2);\nfMRead = fMRead | (~use_ixiy&pla[70]&pla[55])&(M2&T3);\nnextM = nextM | (~use_ixiy&pla[70]&pla[55])&(M2&T4);\nctl_mWrite = ctl_mWrite | (~use_ixiy&pla[70]&pla[55])&(M2&T4);\nctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[70]&pla[55])&(M2&T4);\nctl_sw_1d = ctl_sw_1d | (~use_ixiy&pla[70]&pla[55])&(M2&T4);\nctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[70]&pla[55])&(M2&T4);\nctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[70]&pla[55])&(M2&T4);\nctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[70]&pla[55])&(M2&T4);\nctl_shift_en = ctl_shift_en | (~use_ixiy&pla[70]&pla[55])&(M2&T4);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[70]&pla[55])&(M2&T4);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[70]&pla[55])&(M2&T4);\nctl_alu_op_low = ctl_alu_op_low | (~use_ixiy&pla[70]&pla[55])&(M2&T4);\nctl_alu_core_R = ctl_alu_core_R | (~use_ixiy&pla[70]&pla[55])&(M2&T4);\nctl_alu_core_V = ctl_alu_core_V | (~use_ixiy&pla[70]&pla[55])&(M2&T4);\nctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[70]&pla[55])&(M2&T4);\nctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[70]&pla[55])&(M2&T4);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (~use_ixiy&pla[70]&pla[55])&(M2&T4);\nctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[70]&pla[55])&(M2&T4);\nctl_flags_nf_clr = ctl_flags_nf_clr | (~use_ixiy&pla[70]&pla[55])&(M2&T4);\nctl_flags_cf2_we = ctl_flags_cf2_we | (~use_ixiy&pla[70]&pla[55])&(M2&T4);\nctl_flags_cf2_sel_shift = ctl_flags_cf2_sel_shift | (~use_ixiy&pla[70]&pla[55])&(M2&T4);\nfMWrite = fMWrite | (~use_ixiy&pla[70]&pla[55])&(M3&T1);\nctl_bus_inc_oe = ctl_bus_inc_oe | (~use_ixiy&pla[70]&pla[55])&(M3&T1);\nctl_sw_2u = ctl_sw_2u | (~use_ixiy&pla[70]&pla[55])&(M3&T1);\nctl_sw_1u = ctl_sw_1u | (~use_ixiy&pla[70]&pla[55])&(M3&T1);\nctl_bus_db_we = ctl_bus_db_we | (~use_ixiy&pla[70]&pla[55])&(M3&T1);\nctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[70]&pla[55])&(M3&T1);\nctl_alu_oe = ctl_alu_oe | (~use_ixiy&pla[70]&pla[55])&(M3&T1);\nctl_alu_res_oe = ctl_alu_res_oe | (~use_ixiy&pla[70]&pla[55])&(M3&T1);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (~use_ixiy&pla[70]&pla[55])&(M3&T1);\nctl_alu_core_R = ctl_alu_core_R | (~use_ixiy&pla[70]&pla[55])&(M3&T1);\nctl_alu_core_V = ctl_alu_core_V | (~use_ixiy&pla[70]&pla[55])&(M3&T1);\nctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[70]&pla[55])&(M3&T1);\nctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[70]&pla[55])&(M3&T1);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (~use_ixiy&pla[70]&pla[55])&(M3&T1);\nctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[70]&pla[55])&(M3&T1);\nctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[70]&pla[55])&(M3&T1);\nctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[70]&pla[55])&(M3&T1);\nctl_flags_pf_we = ctl_flags_pf_we | (~use_ixiy&pla[70]&pla[55])&(M3&T1);\nctl_pf_sel_nuse_ixiypla70pla55M3T1_19 = (~use_ixiy&pla[70]&pla[55])&(M3&T1);\nctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_nuse_ixiypla70pla55M3T1_19,ctl_pf_sel_nuse_ixiypla70pla55M3T1_19})&(`PFSEL_P);\nctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[70]&pla[55])&(M3&T1);\nctl_flags_nf_clr = ctl_flags_nf_clr | (~use_ixiy&pla[70]&pla[55])&(M3&T1);\nctl_flags_cf_we = ctl_flags_cf_we | (~use_ixiy&pla[70]&pla[55])&(M3&T1);\nfMWrite = fMWrite | (~use_ixiy&pla[70]&pla[55])&(M3&T2);\nfMWrite = fMWrite | (~use_ixiy&pla[70]&pla[55])&(M3&T3);\nsetM1 = setM1 | (~use_ixiy&pla[70]&pla[55])&(M3&T3);\nfMRead = fMRead | (~use_ixiy&pla[70]&pla[55])&(M4&T1);\nctl_reg_sel_wz = ctl_reg_sel_wz | (~use_ixiy&pla[70]&pla[55])&(M4&T1);\nctl_reg_sys_hilo_nuse_ixiypla70pla55M4T1_3 = (~use_ixiy&pla[70]&pla[55])&(M4&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_nuse_ixiypla70pla55M4T1_3,ctl_reg_sys_hilo_nuse_ixiypla70pla55M4T1_3})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (~use_ixiy&pla[70]&pla[55])&(M4&T1);\nctl_al_we = ctl_al_we | (~use_ixiy&pla[70]&pla[55])&(M4&T1);\nctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[70]&pla[55])&(M4&T1);\nctl_ir_we = ctl_ir_we | (~use_ixiy&pla[70]&pla[55])&(M4&T1);\nfMRead = fMRead | (~use_ixiy&pla[70]&pla[55])&(M4&T2);\nfMRead = fMRead | (~use_ixiy&pla[70]&pla[55])&(M4&T3);\nnextM = nextM | (~use_ixiy&pla[70]&pla[55])&(M4&T3);\nctl_mWrite = ctl_mWrite | (~use_ixiy&pla[70]&pla[55])&(M4&T3);\nctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[70]&pla[55])&(M4&T3);\nctl_sw_1d = ctl_sw_1d | (~use_ixiy&pla[70]&pla[55])&(M4&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[70]&pla[55])&(M4&T3);\nctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[70]&pla[55])&(M4&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[70]&pla[55])&(M4&T3);\nctl_shift_en = ctl_shift_en | (~use_ixiy&pla[70]&pla[55])&(M4&T3);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[70]&pla[55])&(M4&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[70]&pla[55])&(M4&T3);\nctl_alu_op_low = ctl_alu_op_low | (~use_ixiy&pla[70]&pla[55])&(M4&T3);\nctl_alu_core_R = ctl_alu_core_R | (~use_ixiy&pla[70]&pla[55])&(M4&T3);\nctl_alu_core_V = ctl_alu_core_V | (~use_ixiy&pla[70]&pla[55])&(M4&T3);\nctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[70]&pla[55])&(M4&T3);\nctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[70]&pla[55])&(M4&T3);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (~use_ixiy&pla[70]&pla[55])&(M4&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[70]&pla[55])&(M4&T3);\nctl_flags_nf_clr = ctl_flags_nf_clr | (~use_ixiy&pla[70]&pla[55])&(M4&T3);\nctl_flags_cf2_we = ctl_flags_cf2_we | (~use_ixiy&pla[70]&pla[55])&(M4&T3);\nctl_flags_cf2_sel_shift = ctl_flags_cf2_sel_shift | (~use_ixiy&pla[70]&pla[55])&(M4&T3);\nfMWrite = fMWrite | (~use_ixiy&pla[70]&pla[55])&(M5&T1);\nctl_bus_inc_oe = ctl_bus_inc_oe | (~use_ixiy&pla[70]&pla[55])&(M5&T1);\nctl_sw_2u = ctl_sw_2u | (~use_ixiy&pla[70]&pla[55])&(M5&T1);\nctl_sw_1u = ctl_sw_1u | (~use_ixiy&pla[70]&pla[55])&(M5&T1);\nctl_bus_db_we = ctl_bus_db_we | (~use_ixiy&pla[70]&pla[55])&(M5&T1);\nctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[70]&pla[55])&(M5&T1);\nctl_alu_oe = ctl_alu_oe | (~use_ixiy&pla[70]&pla[55])&(M5&T1);\nctl_alu_res_oe = ctl_alu_res_oe | (~use_ixiy&pla[70]&pla[55])&(M5&T1);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (~use_ixiy&pla[70]&pla[55])&(M5&T1);\nctl_alu_core_R = ctl_alu_core_R | (~use_ixiy&pla[70]&pla[55])&(M5&T1);\nctl_alu_core_V = ctl_alu_core_V | (~use_ixiy&pla[70]&pla[55])&(M5&T1);\nctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[70]&pla[55])&(M5&T1);\nctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[70]&pla[55])&(M5&T1);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (~use_ixiy&pla[70]&pla[55])&(M5&T1);\nctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[70]&pla[55])&(M5&T1);\nctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[70]&pla[55])&(M5&T1);\nctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[70]&pla[55])&(M5&T1);\nctl_flags_pf_we = ctl_flags_pf_we | (~use_ixiy&pla[70]&pla[55])&(M5&T1);\nctl_pf_sel_nuse_ixiypla70pla55M5T1_19 = (~use_ixiy&pla[70]&pla[55])&(M5&T1);\nctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_nuse_ixiypla70pla55M5T1_19,ctl_pf_sel_nuse_ixiypla70pla55M5T1_19})&(`PFSEL_P);\nctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[70]&pla[55])&(M5&T1);\nctl_flags_nf_clr = ctl_flags_nf_clr | (~use_ixiy&pla[70]&pla[55])&(M5&T1);\nctl_flags_cf_we = ctl_flags_cf_we | (~use_ixiy&pla[70]&pla[55])&(M5&T1);\nfMWrite = fMWrite | (~use_ixiy&pla[70]&pla[55])&(M5&T2);\nfMWrite = fMWrite | (~use_ixiy&pla[70]&pla[55])&(M5&T3);\nsetM1 = setM1 | (~use_ixiy&pla[70]&pla[55])&(M5&T3);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[15]&op3)&(M1&T1);\nctl_reg_gp_sel_pla15op3M1T1_2 = (pla[15]&op3)&(M1&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla15op3M1T1_2,ctl_reg_gp_sel_pla15op3M1T1_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla15op3M1T1_3 = (pla[15]&op3)&(M1&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla15op3M1T1_3,ctl_reg_gp_hilo_pla15op3M1T1_3})&(2'b10);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[15]&op3)&(M1&T1);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[15]&op3)&(M1&T1);\nctl_flags_alu = ctl_flags_alu | (pla[15]&op3)&(M1&T1);\nctl_alu_oe = ctl_alu_oe | (pla[15]&op3)&(M1&T1);\nctl_alu_res_oe = ctl_alu_res_oe | (pla[15]&op3)&(M1&T1);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[15]&op3)&(M1&T1);\nctl_alu_core_R = ctl_alu_core_R | (pla[15]&op3)&(M1&T1);\nctl_alu_core_V = ctl_alu_core_V | (pla[15]&op3)&(M1&T1);\nctl_alu_core_S = ctl_alu_core_S | (pla[15]&op3)&(M1&T1);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[15]&op3)&(M1&T1);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[15]&op3)&(M1&T1);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[15]&op3)&(M1&T1);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[15]&op3)&(M1&T1);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[15]&op3)&(M1&T1);\nctl_pf_sel_pla15op3M1T1_18 = (pla[15]&op3)&(M1&T1);\nctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_pla15op3M1T1_18,ctl_pf_sel_pla15op3M1T1_18})&(`PFSEL_P);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[15]&op3)&(M1&T1);\nctl_flags_nf_clr = ctl_flags_nf_clr | (pla[15]&op3)&(M1&T1);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[15]&op3)&(M1&T2);\nctl_reg_gp_sel_pla15op3M1T2_2 = (pla[15]&op3)&(M1&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla15op3M1T2_2,ctl_reg_gp_sel_pla15op3M1T2_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla15op3M1T2_3 = (pla[15]&op3)&(M1&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla15op3M1T2_3,ctl_reg_gp_hilo_pla15op3M1T2_3})&(2'b01);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[15]&op3)&(M1&T2);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[15]&op3)&(M1&T2);\nctl_flags_oe = ctl_flags_oe | (pla[15]&op3)&(M1&T2);\nctl_reg_gp_sel_pla15op3M1T3_1 = (pla[15]&op3)&(M1&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla15op3M1T3_1,ctl_reg_gp_sel_pla15op3M1T3_1})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla15op3M1T3_2 = (pla[15]&op3)&(M1&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla15op3M1T3_2,ctl_reg_gp_hilo_pla15op3M1T3_2})&(2'b11);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[15]&op3)&(M1&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[15]&op3)&(M1&T3);\nctl_flags_bus = ctl_flags_bus | (pla[15]&op3)&(M1&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[15]&op3)&(M1&T3)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[15]&op3)&(M1&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[15]&op3)&(M1&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[15]&op3)&(M1&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[15]&op3)&(M1&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[15]&op3)&(M1&T3);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[15]&op3)&(M1&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[15]&op3)&(M1&T3);\nctl_flags_cf_we = ctl_flags_cf_we | (pla[15]&op3)&(M1&T3);\nvalidPLA = validPLA | (pla[15]&op3)&(M1&T4);\nnextM = nextM | (pla[15]&op3)&(M1&T4);\nctl_mRead = ctl_mRead | (pla[15]&op3)&(M1&T4);\nfMRead = fMRead | (pla[15]&op3)&(M2&T1);\nctl_reg_gp_sel_pla15op3M2T1_2 = (pla[15]&op3)&(M2&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla15op3M2T1_2,ctl_reg_gp_sel_pla15op3M2T1_2})&(`GP_REG_HL);\nctl_reg_gp_hilo_pla15op3M2T1_3 = (pla[15]&op3)&(M2&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla15op3M2T1_3,ctl_reg_gp_hilo_pla15op3M2T1_3})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[15]&op3)&(M2&T1);\nctl_al_we = ctl_al_we | (pla[15]&op3)&(M2&T1);\nfMRead = fMRead | (pla[15]&op3)&(M2&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[15]&op3)&(M2&T2);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[15]&op3)&(M2&T2);\nctl_reg_sys_hilo_pla15op3M2T2_4 = (pla[15]&op3)&(M2&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla15op3M2T2_4,ctl_reg_sys_hilo_pla15op3M2T2_4})&(2'b11);\nctl_sw_4u = ctl_sw_4u | (pla[15]&op3)&(M2&T2);\nctl_inc_cy = ctl_inc_cy | (pla[15]&op3)&(M2&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[15]&op3)&(M2&T2);\nfMRead = fMRead | (pla[15]&op3)&(M2&T3);\nnextM = nextM | (pla[15]&op3)&(M2&T3);\nctl_sw_2d = ctl_sw_2d | (pla[15]&op3)&(M3&T1);\nctl_sw_1d = ctl_sw_1d | (pla[15]&op3)&(M3&T1);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[15]&op3)&(M3&T1);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[15]&op3)&(M3&T1)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_lq = ctl_alu_op2_sel_lq | (pla[15]&op3)&(M3&T1);\nctl_alu_op_low = ctl_alu_op_low | (pla[15]&op3)&(M3&T1);\nnextM = nextM | (pla[15]&op3)&(M3&T4);\nctl_mWrite = ctl_mWrite | (pla[15]&op3)&(M3&T4);\nctl_sw_2d = ctl_sw_2d | (pla[15]&op3)&(M3&T4);\nctl_sw_1d = ctl_sw_1d | (pla[15]&op3)&(M3&T4);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[15]&op3)&(M3&T4);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[15]&op3)&(M3&T4)&(~ctl_alu_bs_oe);\nctl_alu_op1_sel_low = ctl_alu_op1_sel_low | (pla[15]&op3)&(M3&T4);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[15]&op3)&(M3&T4);\nfMWrite = fMWrite | (pla[15]&op3)&(M4&T1);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[15]&op3)&(M4&T1);\nctl_sw_2u = ctl_sw_2u | (pla[15]&op3)&(M4&T1);\nctl_sw_1u = ctl_sw_1u | (pla[15]&op3)&(M4&T1);\nctl_bus_db_we = ctl_bus_db_we | (pla[15]&op3)&(M4&T1);\nctl_alu_oe = ctl_alu_oe | (pla[15]&op3)&(M4&T1);\nctl_alu_op2_oe = ctl_alu_op2_oe | (pla[15]&op3)&(M4&T1);\nfMWrite = fMWrite | (pla[15]&op3)&(M4&T2);\nctl_alu_op1_oe = ctl_alu_op1_oe | (pla[15]&op3)&(M4&T2);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[15]&op3)&(M4&T2);\nfMWrite = fMWrite | (pla[15]&op3)&(M4&T3);\nsetM1 = setM1 | (pla[15]&op3)&(M4&T3);\nctl_flags_alu = ctl_flags_alu | (pla[15]&op3)&(M4&T3);\nctl_alu_op_low = ctl_alu_op_low | (pla[15]&op3)&(M4&T3);\nctl_alu_core_R = ctl_alu_core_R | (pla[15]&op3)&(M4&T3);\nctl_alu_core_V = ctl_alu_core_V | (pla[15]&op3)&(M4&T3);\nctl_alu_core_S = ctl_alu_core_S | (pla[15]&op3)&(M4&T3);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[15]&op3)&(M4&T3);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[15]&op3)&(M4&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[15]&op3)&(M4&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[15]&op3)&(M4&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[15]&op3)&(M4&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[15]&op3)&(M4&T3);\nctl_flags_nf_clr = ctl_flags_nf_clr | (pla[15]&op3)&(M4&T3);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[15]&~op3)&(M1&T1);\nctl_reg_gp_sel_pla15nop3M1T1_2 = (pla[15]&~op3)&(M1&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla15nop3M1T1_2,ctl_reg_gp_sel_pla15nop3M1T1_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla15nop3M1T1_3 = (pla[15]&~op3)&(M1&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla15nop3M1T1_3,ctl_reg_gp_hilo_pla15nop3M1T1_3})&(2'b10);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[15]&~op3)&(M1&T1);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[15]&~op3)&(M1&T1);\nctl_flags_alu = ctl_flags_alu | (pla[15]&~op3)&(M1&T1);\nctl_alu_oe = ctl_alu_oe | (pla[15]&~op3)&(M1&T1);\nctl_alu_res_oe = ctl_alu_res_oe | (pla[15]&~op3)&(M1&T1);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[15]&~op3)&(M1&T1);\nctl_alu_core_R = ctl_alu_core_R | (pla[15]&~op3)&(M1&T1);\nctl_alu_core_V = ctl_alu_core_V | (pla[15]&~op3)&(M1&T1);\nctl_alu_core_S = ctl_alu_core_S | (pla[15]&~op3)&(M1&T1);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[15]&~op3)&(M1&T1);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[15]&~op3)&(M1&T1);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[15]&~op3)&(M1&T1);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[15]&~op3)&(M1&T1);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[15]&~op3)&(M1&T1);\nctl_pf_sel_pla15nop3M1T1_18 = (pla[15]&~op3)&(M1&T1);\nctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_pla15nop3M1T1_18,ctl_pf_sel_pla15nop3M1T1_18})&(`PFSEL_P);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[15]&~op3)&(M1&T1);\nctl_flags_nf_clr = ctl_flags_nf_clr | (pla[15]&~op3)&(M1&T1);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[15]&~op3)&(M1&T2);\nctl_reg_gp_sel_pla15nop3M1T2_2 = (pla[15]&~op3)&(M1&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla15nop3M1T2_2,ctl_reg_gp_sel_pla15nop3M1T2_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla15nop3M1T2_3 = (pla[15]&~op3)&(M1&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla15nop3M1T2_3,ctl_reg_gp_hilo_pla15nop3M1T2_3})&(2'b01);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[15]&~op3)&(M1&T2);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[15]&~op3)&(M1&T2);\nctl_flags_oe = ctl_flags_oe | (pla[15]&~op3)&(M1&T2);\nctl_reg_gp_sel_pla15nop3M1T3_1 = (pla[15]&~op3)&(M1&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla15nop3M1T3_1,ctl_reg_gp_sel_pla15nop3M1T3_1})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla15nop3M1T3_2 = (pla[15]&~op3)&(M1&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla15nop3M1T3_2,ctl_reg_gp_hilo_pla15nop3M1T3_2})&(2'b11);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[15]&~op3)&(M1&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[15]&~op3)&(M1&T3);\nctl_flags_bus = ctl_flags_bus | (pla[15]&~op3)&(M1&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[15]&~op3)&(M1&T3)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[15]&~op3)&(M1&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[15]&~op3)&(M1&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[15]&~op3)&(M1&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[15]&~op3)&(M1&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[15]&~op3)&(M1&T3);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[15]&~op3)&(M1&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[15]&~op3)&(M1&T3);\nctl_flags_cf_we = ctl_flags_cf_we | (pla[15]&~op3)&(M1&T3);\nvalidPLA = validPLA | (pla[15]&~op3)&(M1&T4);\nnextM = nextM | (pla[15]&~op3)&(M1&T4);\nctl_mRead = ctl_mRead | (pla[15]&~op3)&(M1&T4);\nfMRead = fMRead | (pla[15]&~op3)&(M2&T1);\nctl_reg_gp_sel_pla15nop3M2T1_2 = (pla[15]&~op3)&(M2&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla15nop3M2T1_2,ctl_reg_gp_sel_pla15nop3M2T1_2})&(`GP_REG_HL);\nctl_reg_gp_hilo_pla15nop3M2T1_3 = (pla[15]&~op3)&(M2&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla15nop3M2T1_3,ctl_reg_gp_hilo_pla15nop3M2T1_3})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[15]&~op3)&(M2&T1);\nctl_al_we = ctl_al_we | (pla[15]&~op3)&(M2&T1);\nfMRead = fMRead | (pla[15]&~op3)&(M2&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[15]&~op3)&(M2&T2);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[15]&~op3)&(M2&T2);\nctl_reg_sys_hilo_pla15nop3M2T2_4 = (pla[15]&~op3)&(M2&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla15nop3M2T2_4,ctl_reg_sys_hilo_pla15nop3M2T2_4})&(2'b11);\nctl_sw_4u = ctl_sw_4u | (pla[15]&~op3)&(M2&T2);\nctl_inc_cy = ctl_inc_cy | (pla[15]&~op3)&(M2&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[15]&~op3)&(M2&T2);\nfMRead = fMRead | (pla[15]&~op3)&(M2&T3);\nnextM = nextM | (pla[15]&~op3)&(M2&T3);\nctl_sw_2d = ctl_sw_2d | (pla[15]&~op3)&(M3&T1);\nctl_sw_1d = ctl_sw_1d | (pla[15]&~op3)&(M3&T1);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[15]&~op3)&(M3&T1);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[15]&~op3)&(M3&T1)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_lq = ctl_alu_op2_sel_lq | (pla[15]&~op3)&(M3&T1);\nctl_alu_op1_sel_low = ctl_alu_op1_sel_low | (pla[15]&~op3)&(M3&T1);\nctl_alu_op_low = ctl_alu_op_low | (pla[15]&~op3)&(M3&T1);\nctl_sw_2u = ctl_sw_2u | (pla[15]&~op3)&(M3&T2);\nctl_sw_1u = ctl_sw_1u | (pla[15]&~op3)&(M3&T2);\nctl_bus_db_we = ctl_bus_db_we | (pla[15]&~op3)&(M3&T2);\nctl_alu_oe = ctl_alu_oe | (pla[15]&~op3)&(M3&T2);\nctl_alu_op2_oe = ctl_alu_op2_oe | (pla[15]&~op3)&(M3&T2);\nctl_reg_gp_sel_pla15nop3M3T3_1 = (pla[15]&~op3)&(M3&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla15nop3M3T3_1,ctl_reg_gp_sel_pla15nop3M3T3_1})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla15nop3M3T3_2 = (pla[15]&~op3)&(M3&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla15nop3M3T3_2,ctl_reg_gp_hilo_pla15nop3M3T3_2})&(2'b10);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[15]&~op3)&(M3&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[15]&~op3)&(M3&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[15]&~op3)&(M3&T3)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_lq = ctl_alu_op2_sel_lq | (pla[15]&~op3)&(M3&T3);\nctl_alu_op_low = ctl_alu_op_low | (pla[15]&~op3)&(M3&T3);\nnextM = nextM | (pla[15]&~op3)&(M3&T4);\nctl_mWrite = ctl_mWrite | (pla[15]&~op3)&(M3&T4);\nctl_sw_2d = ctl_sw_2d | (pla[15]&~op3)&(M3&T4);\nctl_sw_1d = ctl_sw_1d | (pla[15]&~op3)&(M3&T4);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[15]&~op3)&(M3&T4);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[15]&~op3)&(M3&T4)&(~ctl_alu_bs_oe);\nctl_alu_op1_sel_low = ctl_alu_op1_sel_low | (pla[15]&~op3)&(M3&T4);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[15]&~op3)&(M3&T4);\nfMWrite = fMWrite | (pla[15]&~op3)&(M4&T1);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[15]&~op3)&(M4&T1);\nctl_sw_2u = ctl_sw_2u | (pla[15]&~op3)&(M4&T1);\nctl_sw_1u = ctl_sw_1u | (pla[15]&~op3)&(M4&T1);\nctl_bus_db_we = ctl_bus_db_we | (pla[15]&~op3)&(M4&T1);\nctl_alu_oe = ctl_alu_oe | (pla[15]&~op3)&(M4&T1);\nctl_alu_op2_oe = ctl_alu_op2_oe | (pla[15]&~op3)&(M4&T1);\nfMWrite = fMWrite | (pla[15]&~op3)&(M4&T2);\nctl_alu_op1_oe = ctl_alu_op1_oe | (pla[15]&~op3)&(M4&T2);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[15]&~op3)&(M4&T2);\nfMWrite = fMWrite | (pla[15]&~op3)&(M4&T3);\nsetM1 = setM1 | (pla[15]&~op3)&(M4&T3);\nctl_flags_alu = ctl_flags_alu | (pla[15]&~op3)&(M4&T3);\nctl_alu_op_low = ctl_alu_op_low | (pla[15]&~op3)&(M4&T3);\nctl_alu_core_R = ctl_alu_core_R | (pla[15]&~op3)&(M4&T3);\nctl_alu_core_V = ctl_alu_core_V | (pla[15]&~op3)&(M4&T3);\nctl_alu_core_S = ctl_alu_core_S | (pla[15]&~op3)&(M4&T3);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[15]&~op3)&(M4&T3);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[15]&~op3)&(M4&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[15]&~op3)&(M4&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[15]&~op3)&(M4&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[15]&~op3)&(M4&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[15]&~op3)&(M4&T3);\nctl_flags_nf_clr = ctl_flags_nf_clr | (pla[15]&~op3)&(M4&T3);\nctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[72]&~pla[55])&(M1&T1);\nctl_alu_oe = ctl_alu_oe | (~use_ixiy&pla[72]&~pla[55])&(M1&T1);\nctl_alu_res_oe = ctl_alu_res_oe | (~use_ixiy&pla[72]&~pla[55])&(M1&T1);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (~use_ixiy&pla[72]&~pla[55])&(M1&T1);\nctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[72]&~pla[55])&(M1&T1);\nctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[72]&~pla[55])&(M1&T1);\nctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[72]&~pla[55])&(M1&T1);\nctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[72]&~pla[55])&(M1&T1);\nctl_flags_pf_we = ctl_flags_pf_we | (~use_ixiy&pla[72]&~pla[55])&(M1&T1);\nctl_pf_sel_nuse_ixiypla72npla55M1T1_10 = (~use_ixiy&pla[72]&~pla[55])&(M1&T1);\nctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_nuse_ixiypla72npla55M1T1_10,ctl_pf_sel_nuse_ixiypla72npla55M1T1_10})&(`PFSEL_P);\nctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[72]&~pla[55])&(M1&T1);\nctl_flags_nf_clr = ctl_flags_nf_clr | (~use_ixiy&pla[72]&~pla[55])&(M1&T1);\nctl_reg_gp_we = ctl_reg_gp_we | (~use_ixiy&pla[72]&~pla[55])&(M1&T2);\nctl_reg_gp_sel_nuse_ixiypla72npla55M1T2_2 = (~use_ixiy&pla[72]&~pla[55])&(M1&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla72npla55M1T2_2,ctl_reg_gp_sel_nuse_ixiypla72npla55M1T2_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_nuse_ixiypla72npla55M1T2_3 = (~use_ixiy&pla[72]&~pla[55])&(M1&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T2_3,ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T2_3})&(2'b01);\nctl_reg_in_hi = ctl_reg_in_hi | (~use_ixiy&pla[72]&~pla[55])&(M1&T2);\nctl_reg_in_lo = ctl_reg_in_lo | (~use_ixiy&pla[72]&~pla[55])&(M1&T2);\nctl_flags_oe = ctl_flags_oe | (~use_ixiy&pla[72]&~pla[55])&(M1&T2);\nctl_reg_gp_sel_nuse_ixiypla72npla55M1T3_1 = (~use_ixiy&pla[72]&~pla[55])&(M1&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla72npla55M1T3_1,ctl_reg_gp_sel_nuse_ixiypla72npla55M1T3_1})&(`GP_REG_AF);\nctl_reg_gp_hilo_nuse_ixiypla72npla55M1T3_2 = (~use_ixiy&pla[72]&~pla[55])&(M1&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T3_2,ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T3_2})&(2'b11);\nctl_reg_out_hi = ctl_reg_out_hi | (~use_ixiy&pla[72]&~pla[55])&(M1&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (~use_ixiy&pla[72]&~pla[55])&(M1&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[72]&~pla[55])&(M1&T3);\nctl_flags_bus = ctl_flags_bus | (~use_ixiy&pla[72]&~pla[55])&(M1&T3);\nctl_alu_bs_oe = ctl_alu_bs_oe | (~use_ixiy&pla[72]&~pla[55])&(M1&T3);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[72]&~pla[55])&(M1&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[72]&~pla[55])&(M1&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[72]&~pla[55])&(M1&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[72]&~pla[55])&(M1&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[72]&~pla[55])&(M1&T3);\nctl_flags_pf_we = ctl_flags_pf_we | (~use_ixiy&pla[72]&~pla[55])&(M1&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[72]&~pla[55])&(M1&T3);\nctl_flags_cf_we = ctl_flags_cf_we | (~use_ixiy&pla[72]&~pla[55])&(M1&T3);\nvalidPLA = validPLA | (~use_ixiy&pla[72]&~pla[55])&(M1&T4);\nsetM1 = setM1 | (~use_ixiy&pla[72]&~pla[55])&(M1&T4);\nctl_reg_gp_sel_nuse_ixiypla72npla55M1T4_3 = (~use_ixiy&pla[72]&~pla[55])&(M1&T4);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla72npla55M1T4_3,ctl_reg_gp_sel_nuse_ixiypla72npla55M1T4_3})&(op21);\nctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 = (~use_ixiy&pla[72]&~pla[55])&(M1&T4);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4,ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4})&({~rsel0,rsel0});\nctl_reg_out_hi = ctl_reg_out_hi | (~use_ixiy&pla[72]&~pla[55])&(M1&T4)&(~rsel0);\nctl_reg_out_lo = ctl_reg_out_lo | (~use_ixiy&pla[72]&~pla[55])&(M1&T4)&(rsel0);\nctl_sw_2u = ctl_sw_2u | (~use_ixiy&pla[72]&~pla[55])&(M1&T4)&(~rsel0);\nctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[72]&~pla[55])&(M1&T4)&(rsel0);\nctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[72]&~pla[55])&(M1&T4);\nctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[72]&~pla[55])&(M1&T4)&(~ctl_alu_bs_oe);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[72]&~pla[55])&(M1&T4);\nctl_alu_op_low = ctl_alu_op_low | (~use_ixiy&pla[72]&~pla[55])&(M1&T4);\nctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[72]&~pla[55])&(M1&T4);\nctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[72]&~pla[55])&(M1&T4);\nctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[72]&~pla[55])&(M1&T4);\nctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[72]&~pla[55])&(M1&T4);\nctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[72]&~pla[55])&(M1&T4);\nctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[72]&~pla[55])&(M1&T4);\nctl_flags_nf_clr = ctl_flags_nf_clr | (~use_ixiy&pla[72]&~pla[55])&(M1&T4);\nfMRead = fMRead | (~use_ixiy&pla[72]&~pla[55])&(M4&T1);\nctl_bus_inc_oe = ctl_bus_inc_oe | (~use_ixiy&pla[72]&~pla[55])&(M4&T1);\nctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[72]&~pla[55])&(M4&T1);\nctl_alu_bs_oe = ctl_alu_bs_oe | (~use_ixiy&pla[72]&~pla[55])&(M4&T1);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[72]&~pla[55])&(M4&T1);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[72]&~pla[55])&(M4&T1);\nctl_ir_we = ctl_ir_we | (~use_ixiy&pla[72]&~pla[55])&(M4&T1);\nfMRead = fMRead | (~use_ixiy&pla[72]&~pla[55])&(M4&T2);\nfMRead = fMRead | (~use_ixiy&pla[72]&~pla[55])&(M4&T3);\nsetM1 = setM1 | (~use_ixiy&pla[72]&~pla[55])&(M4&T4);\nctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[72]&~pla[55])&(M4&T4);\nctl_sw_1d = ctl_sw_1d | (~use_ixiy&pla[72]&~pla[55])&(M4&T4);\nctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[72]&~pla[55])&(M4&T4);\nctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[72]&~pla[55])&(M4&T4);\nctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[72]&~pla[55])&(M4&T4)&(~ctl_alu_bs_oe);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[72]&~pla[55])&(M4&T4);\nctl_alu_op_low = ctl_alu_op_low | (~use_ixiy&pla[72]&~pla[55])&(M4&T4);\nctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[72]&~pla[55])&(M4&T4);\nctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[72]&~pla[55])&(M4&T4);\nctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[72]&~pla[55])&(M4&T4);\nctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[72]&~pla[55])&(M4&T4);\nctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[72]&~pla[55])&(M4&T4);\nctl_flags_nf_clr = ctl_flags_nf_clr | (~use_ixiy&pla[72]&~pla[55])&(M4&T4);\nctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[72]&pla[55])&(M1&T1);\nctl_alu_oe = ctl_alu_oe | (~use_ixiy&pla[72]&pla[55])&(M1&T1);\nctl_alu_res_oe = ctl_alu_res_oe | (~use_ixiy&pla[72]&pla[55])&(M1&T1);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (~use_ixiy&pla[72]&pla[55])&(M1&T1);\nctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[72]&pla[55])&(M1&T1);\nctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[72]&pla[55])&(M1&T1);\nctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[72]&pla[55])&(M1&T1);\nctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[72]&pla[55])&(M1&T1);\nctl_flags_pf_we = ctl_flags_pf_we | (~use_ixiy&pla[72]&pla[55])&(M1&T1);\nctl_pf_sel_nuse_ixiypla72pla55M1T1_10 = (~use_ixiy&pla[72]&pla[55])&(M1&T1);\nctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_nuse_ixiypla72pla55M1T1_10,ctl_pf_sel_nuse_ixiypla72pla55M1T1_10})&(`PFSEL_P);\nctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[72]&pla[55])&(M1&T1);\nctl_flags_nf_clr = ctl_flags_nf_clr | (~use_ixiy&pla[72]&pla[55])&(M1&T1);\nctl_reg_gp_we = ctl_reg_gp_we | (~use_ixiy&pla[72]&pla[55])&(M1&T2);\nctl_reg_gp_sel_nuse_ixiypla72pla55M1T2_2 = (~use_ixiy&pla[72]&pla[55])&(M1&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla72pla55M1T2_2,ctl_reg_gp_sel_nuse_ixiypla72pla55M1T2_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_nuse_ixiypla72pla55M1T2_3 = (~use_ixiy&pla[72]&pla[55])&(M1&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla72pla55M1T2_3,ctl_reg_gp_hilo_nuse_ixiypla72pla55M1T2_3})&(2'b01);\nctl_reg_in_hi = ctl_reg_in_hi | (~use_ixiy&pla[72]&pla[55])&(M1&T2);\nctl_reg_in_lo = ctl_reg_in_lo | (~use_ixiy&pla[72]&pla[55])&(M1&T2);\nctl_flags_oe = ctl_flags_oe | (~use_ixiy&pla[72]&pla[55])&(M1&T2);\nctl_reg_gp_sel_nuse_ixiypla72pla55M1T3_1 = (~use_ixiy&pla[72]&pla[55])&(M1&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla72pla55M1T3_1,ctl_reg_gp_sel_nuse_ixiypla72pla55M1T3_1})&(`GP_REG_AF);\nctl_reg_gp_hilo_nuse_ixiypla72pla55M1T3_2 = (~use_ixiy&pla[72]&pla[55])&(M1&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla72pla55M1T3_2,ctl_reg_gp_hilo_nuse_ixiypla72pla55M1T3_2})&(2'b11);\nctl_reg_out_hi = ctl_reg_out_hi | (~use_ixiy&pla[72]&pla[55])&(M1&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (~use_ixiy&pla[72]&pla[55])&(M1&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[72]&pla[55])&(M1&T3);\nctl_flags_bus = ctl_flags_bus | (~use_ixiy&pla[72]&pla[55])&(M1&T3);\nctl_alu_bs_oe = ctl_alu_bs_oe | (~use_ixiy&pla[72]&pla[55])&(M1&T3);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[72]&pla[55])&(M1&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[72]&pla[55])&(M1&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[72]&pla[55])&(M1&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[72]&pla[55])&(M1&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[72]&pla[55])&(M1&T3);\nctl_flags_pf_we = ctl_flags_pf_we | (~use_ixiy&pla[72]&pla[55])&(M1&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[72]&pla[55])&(M1&T3);\nctl_flags_cf_we = ctl_flags_cf_we | (~use_ixiy&pla[72]&pla[55])&(M1&T3);\nvalidPLA = validPLA | (~use_ixiy&pla[72]&pla[55])&(M1&T4);\nnextM = nextM | (~use_ixiy&pla[72]&pla[55])&(M1&T4);\nctl_mRead = ctl_mRead | (~use_ixiy&pla[72]&pla[55])&(M1&T4);\nfMRead = fMRead | (~use_ixiy&pla[72]&pla[55])&(M2&T1);\nctl_reg_gp_sel_nuse_ixiypla72pla55M2T1_2 = (~use_ixiy&pla[72]&pla[55])&(M2&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla72pla55M2T1_2,ctl_reg_gp_sel_nuse_ixiypla72pla55M2T1_2})&(`GP_REG_HL);\nctl_reg_gp_hilo_nuse_ixiypla72pla55M2T1_3 = (~use_ixiy&pla[72]&pla[55])&(M2&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla72pla55M2T1_3,ctl_reg_gp_hilo_nuse_ixiypla72pla55M2T1_3})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (~use_ixiy&pla[72]&pla[55])&(M2&T1);\nctl_al_we = ctl_al_we | (~use_ixiy&pla[72]&pla[55])&(M2&T1);\nfMRead = fMRead | (~use_ixiy&pla[72]&pla[55])&(M2&T2);\nfMRead = fMRead | (~use_ixiy&pla[72]&pla[55])&(M2&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (~use_ixiy&pla[72]&pla[55])&(M2&T3);\nctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 = (~use_ixiy&pla[72]&pla[55])&(M2&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3,ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3})&(2'b11);\nctl_sw_4u = ctl_sw_4u | (~use_ixiy&pla[72]&pla[55])&(M2&T3);\nctl_reg_out_hi = ctl_reg_out_hi | (~use_ixiy&pla[72]&pla[55])&(M2&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (~use_ixiy&pla[72]&pla[55])&(M2&T3);\nctl_flags_bus = ctl_flags_bus | (~use_ixiy&pla[72]&pla[55])&(M2&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[72]&pla[55])&(M2&T3);\nsetM1 = setM1 | (~use_ixiy&pla[72]&pla[55])&(M2&T4);\nctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[72]&pla[55])&(M2&T4);\nctl_sw_1d = ctl_sw_1d | (~use_ixiy&pla[72]&pla[55])&(M2&T4);\nctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[72]&pla[55])&(M2&T4);\nctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[72]&pla[55])&(M2&T4);\nctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[72]&pla[55])&(M2&T4)&(~ctl_alu_bs_oe);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[72]&pla[55])&(M2&T4);\nctl_alu_op_low = ctl_alu_op_low | (~use_ixiy&pla[72]&pla[55])&(M2&T4);\nctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[72]&pla[55])&(M2&T4);\nctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[72]&pla[55])&(M2&T4);\nctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[72]&pla[55])&(M2&T4);\nctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[72]&pla[55])&(M2&T4);\nctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[72]&pla[55])&(M2&T4);\nctl_flags_nf_clr = ctl_flags_nf_clr | (~use_ixiy&pla[72]&pla[55])&(M2&T4);\nfMRead = fMRead | (~use_ixiy&pla[72]&pla[55])&(M4&T1);\nctl_reg_sel_wz = ctl_reg_sel_wz | (~use_ixiy&pla[72]&pla[55])&(M4&T1);\nctl_reg_sys_hilo_nuse_ixiypla72pla55M4T1_3 = (~use_ixiy&pla[72]&pla[55])&(M4&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_nuse_ixiypla72pla55M4T1_3,ctl_reg_sys_hilo_nuse_ixiypla72pla55M4T1_3})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (~use_ixiy&pla[72]&pla[55])&(M4&T1);\nctl_al_we = ctl_al_we | (~use_ixiy&pla[72]&pla[55])&(M4&T1);\nctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[72]&pla[55])&(M4&T1);\nctl_alu_bs_oe = ctl_alu_bs_oe | (~use_ixiy&pla[72]&pla[55])&(M4&T1);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[72]&pla[55])&(M4&T1);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[72]&pla[55])&(M4&T1);\nctl_ir_we = ctl_ir_we | (~use_ixiy&pla[72]&pla[55])&(M4&T1);\nfMRead = fMRead | (~use_ixiy&pla[72]&pla[55])&(M4&T2);\nfMRead = fMRead | (~use_ixiy&pla[72]&pla[55])&(M4&T3);\nsetM1 = setM1 | (~use_ixiy&pla[72]&pla[55])&(M4&T4);\nctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[72]&pla[55])&(M4&T4);\nctl_sw_1d = ctl_sw_1d | (~use_ixiy&pla[72]&pla[55])&(M4&T4);\nctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[72]&pla[55])&(M4&T4);\nctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[72]&pla[55])&(M4&T4);\nctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[72]&pla[55])&(M4&T4)&(~ctl_alu_bs_oe);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[72]&pla[55])&(M4&T4);\nctl_alu_op_low = ctl_alu_op_low | (~use_ixiy&pla[72]&pla[55])&(M4&T4);\nctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[72]&pla[55])&(M4&T4);\nctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[72]&pla[55])&(M4&T4);\nctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[72]&pla[55])&(M4&T4);\nctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[72]&pla[55])&(M4&T4);\nctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[72]&pla[55])&(M4&T4);\nctl_flags_nf_clr = ctl_flags_nf_clr | (~use_ixiy&pla[72]&pla[55])&(M4&T4);\nctl_reg_gp_we = ctl_reg_gp_we | (~use_ixiy&pla[74]&~pla[55])&(M1&T1);\nctl_reg_gp_sel_nuse_ixiypla74npla55M1T1_2 = (~use_ixiy&pla[74]&~pla[55])&(M1&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla74npla55M1T1_2,ctl_reg_gp_sel_nuse_ixiypla74npla55M1T1_2})&(op21);\nctl_reg_gp_hilo_nuse_ixiypla74npla55M1T1_3 = (~use_ixiy&pla[74]&~pla[55])&(M1&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla74npla55M1T1_3,ctl_reg_gp_hilo_nuse_ixiypla74npla55M1T1_3})&({~rsel0,rsel0});\nctl_reg_in_hi = ctl_reg_in_hi | (~use_ixiy&pla[74]&~pla[55])&(M1&T1);\nctl_reg_in_lo = ctl_reg_in_lo | (~use_ixiy&pla[74]&~pla[55])&(M1&T1);\nctl_sw_2u = ctl_sw_2u | (~use_ixiy&pla[74]&~pla[55])&(M1&T1);\nctl_alu_oe = ctl_alu_oe | (~use_ixiy&pla[74]&~pla[55])&(M1&T1);\nctl_alu_res_oe = ctl_alu_res_oe | (~use_ixiy&pla[74]&~pla[55])&(M1&T1);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (~use_ixiy&pla[74]&~pla[55])&(M1&T1);\nctl_alu_core_R = ctl_alu_core_R | (~use_ixiy&pla[74]&~pla[55])&(M1&T1);\nctl_alu_core_V = ctl_alu_core_V | (~use_ixiy&pla[74]&~pla[55])&(M1&T1);\nctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[74]&~pla[55])&(M1&T1);\nctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[74]&~pla[55])&(M1&T1);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (~use_ixiy&pla[74]&~pla[55])&(M1&T1);\nctl_reg_gp_sel_nuse_ixiypla74npla55M1T3_1 = (~use_ixiy&pla[74]&~pla[55])&(M1&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla74npla55M1T3_1,ctl_reg_gp_sel_nuse_ixiypla74npla55M1T3_1})&(`GP_REG_AF);\nctl_reg_gp_hilo_nuse_ixiypla74npla55M1T3_2 = (~use_ixiy&pla[74]&~pla[55])&(M1&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla74npla55M1T3_2,ctl_reg_gp_hilo_nuse_ixiypla74npla55M1T3_2})&(2'b11);\nctl_reg_out_hi = ctl_reg_out_hi | (~use_ixiy&pla[74]&~pla[55])&(M1&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (~use_ixiy&pla[74]&~pla[55])&(M1&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[74]&~pla[55])&(M1&T3);\nctl_flags_bus = ctl_flags_bus | (~use_ixiy&pla[74]&~pla[55])&(M1&T3);\nctl_alu_bs_oe = ctl_alu_bs_oe | (~use_ixiy&pla[74]&~pla[55])&(M1&T3);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[74]&~pla[55])&(M1&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[74]&~pla[55])&(M1&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[74]&~pla[55])&(M1&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[74]&~pla[55])&(M1&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[74]&~pla[55])&(M1&T3);\nctl_flags_pf_we = ctl_flags_pf_we | (~use_ixiy&pla[74]&~pla[55])&(M1&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[74]&~pla[55])&(M1&T3);\nctl_flags_cf_we = ctl_flags_cf_we | (~use_ixiy&pla[74]&~pla[55])&(M1&T3);\nvalidPLA = validPLA | (~use_ixiy&pla[74]&~pla[55])&(M1&T4);\nsetM1 = setM1 | (~use_ixiy&pla[74]&~pla[55])&(M1&T4);\nctl_reg_gp_sel_nuse_ixiypla74npla55M1T4_3 = (~use_ixiy&pla[74]&~pla[55])&(M1&T4);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla74npla55M1T4_3,ctl_reg_gp_sel_nuse_ixiypla74npla55M1T4_3})&(op21);\nctl_reg_gp_hilo_nuse_ixiypla74npla55M1T4_4 = (~use_ixiy&pla[74]&~pla[55])&(M1&T4);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla74npla55M1T4_4,ctl_reg_gp_hilo_nuse_ixiypla74npla55M1T4_4})&({~rsel0,rsel0});\nctl_reg_out_hi = ctl_reg_out_hi | (~use_ixiy&pla[74]&~pla[55])&(M1&T4)&(~rsel0);\nctl_reg_out_lo = ctl_reg_out_lo | (~use_ixiy&pla[74]&~pla[55])&(M1&T4)&(rsel0);\nctl_sw_2u = ctl_sw_2u | (~use_ixiy&pla[74]&~pla[55])&(M1&T4)&(~rsel0);\nctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[74]&~pla[55])&(M1&T4)&(rsel0);\nctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[74]&~pla[55])&(M1&T4)&(~ctl_alu_bs_oe);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[74]&~pla[55])&(M1&T4);\nctl_alu_op_low = ctl_alu_op_low | (~use_ixiy&pla[74]&~pla[55])&(M1&T4);\nctl_alu_core_R = ctl_alu_core_R | (~use_ixiy&pla[74]&~pla[55])&(M1&T4);\nctl_alu_core_V = ctl_alu_core_V | (~use_ixiy&pla[74]&~pla[55])&(M1&T4);\nctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[74]&~pla[55])&(M1&T4);\nctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[74]&~pla[55])&(M1&T4);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (~use_ixiy&pla[74]&~pla[55])&(M1&T4);\nfMRead = fMRead | (~use_ixiy&pla[74]&~pla[55])&(M4&T1);\nctl_reg_sel_wz = ctl_reg_sel_wz | (~use_ixiy&pla[74]&~pla[55])&(M4&T1);\nctl_reg_sys_hilo_nuse_ixiypla74npla55M4T1_3 = (~use_ixiy&pla[74]&~pla[55])&(M4&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_nuse_ixiypla74npla55M4T1_3,ctl_reg_sys_hilo_nuse_ixiypla74npla55M4T1_3})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (~use_ixiy&pla[74]&~pla[55])&(M4&T1);\nctl_al_we = ctl_al_we | (~use_ixiy&pla[74]&~pla[55])&(M4&T1);\nctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[74]&~pla[55])&(M4&T1);\nctl_alu_bs_oe = ctl_alu_bs_oe | (~use_ixiy&pla[74]&~pla[55])&(M4&T1);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[74]&~pla[55])&(M4&T1);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[74]&~pla[55])&(M4&T1);\nctl_ir_we = ctl_ir_we | (~use_ixiy&pla[74]&~pla[55])&(M4&T1);\nfMRead = fMRead | (~use_ixiy&pla[74]&~pla[55])&(M4&T2);\nfMRead = fMRead | (~use_ixiy&pla[74]&~pla[55])&(M4&T3);\nnextM = nextM | (~use_ixiy&pla[74]&~pla[55])&(M4&T3);\nctl_mWrite = ctl_mWrite | (~use_ixiy&pla[74]&~pla[55])&(M4&T3);\nctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[74]&~pla[55])&(M4&T3);\nctl_sw_1d = ctl_sw_1d | (~use_ixiy&pla[74]&~pla[55])&(M4&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[74]&~pla[55])&(M4&T3);\nctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[74]&~pla[55])&(M4&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[74]&~pla[55])&(M4&T3)&(~ctl_alu_bs_oe);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[74]&~pla[55])&(M4&T3);\nctl_alu_op_low = ctl_alu_op_low | (~use_ixiy&pla[74]&~pla[55])&(M4&T3);\nctl_alu_core_R = ctl_alu_core_R | (~use_ixiy&pla[74]&~pla[55])&(M4&T3);\nctl_alu_core_V = ctl_alu_core_V | (~use_ixiy&pla[74]&~pla[55])&(M4&T3);\nctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[74]&~pla[55])&(M4&T3);\nctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[74]&~pla[55])&(M4&T3);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (~use_ixiy&pla[74]&~pla[55])&(M4&T3);\nfMWrite = fMWrite | (~use_ixiy&pla[74]&~pla[55])&(M5&T1);\nctl_bus_inc_oe = ctl_bus_inc_oe | (~use_ixiy&pla[74]&~pla[55])&(M5&T1);\nctl_sw_2u = ctl_sw_2u | (~use_ixiy&pla[74]&~pla[55])&(M5&T1);\nctl_sw_1u = ctl_sw_1u | (~use_ixiy&pla[74]&~pla[55])&(M5&T1);\nctl_bus_db_we = ctl_bus_db_we | (~use_ixiy&pla[74]&~pla[55])&(M5&T1);\nctl_alu_oe = ctl_alu_oe | (~use_ixiy&pla[74]&~pla[55])&(M5&T1);\nctl_alu_res_oe = ctl_alu_res_oe | (~use_ixiy&pla[74]&~pla[55])&(M5&T1);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (~use_ixiy&pla[74]&~pla[55])&(M5&T1);\nctl_alu_core_R = ctl_alu_core_R | (~use_ixiy&pla[74]&~pla[55])&(M5&T1);\nctl_alu_core_V = ctl_alu_core_V | (~use_ixiy&pla[74]&~pla[55])&(M5&T1);\nctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[74]&~pla[55])&(M5&T1);\nctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[74]&~pla[55])&(M5&T1);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (~use_ixiy&pla[74]&~pla[55])&(M5&T1);\nfMWrite = fMWrite | (~use_ixiy&pla[74]&~pla[55])&(M5&T2);\nfMWrite = fMWrite | (~use_ixiy&pla[74]&~pla[55])&(M5&T3);\nsetM1 = setM1 | (~use_ixiy&pla[74]&~pla[55])&(M5&T3);\nctl_reg_gp_sel_nuse_ixiypla74pla55M1T3_1 = (~use_ixiy&pla[74]&pla[55])&(M1&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla74pla55M1T3_1,ctl_reg_gp_sel_nuse_ixiypla74pla55M1T3_1})&(`GP_REG_AF);\nctl_reg_gp_hilo_nuse_ixiypla74pla55M1T3_2 = (~use_ixiy&pla[74]&pla[55])&(M1&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla74pla55M1T3_2,ctl_reg_gp_hilo_nuse_ixiypla74pla55M1T3_2})&(2'b11);\nctl_reg_out_hi = ctl_reg_out_hi | (~use_ixiy&pla[74]&pla[55])&(M1&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (~use_ixiy&pla[74]&pla[55])&(M1&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[74]&pla[55])&(M1&T3);\nctl_flags_bus = ctl_flags_bus | (~use_ixiy&pla[74]&pla[55])&(M1&T3);\nctl_alu_bs_oe = ctl_alu_bs_oe | (~use_ixiy&pla[74]&pla[55])&(M1&T3);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[74]&pla[55])&(M1&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[74]&pla[55])&(M1&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[74]&pla[55])&(M1&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[74]&pla[55])&(M1&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[74]&pla[55])&(M1&T3);\nctl_flags_pf_we = ctl_flags_pf_we | (~use_ixiy&pla[74]&pla[55])&(M1&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[74]&pla[55])&(M1&T3);\nctl_flags_cf_we = ctl_flags_cf_we | (~use_ixiy&pla[74]&pla[55])&(M1&T3);\nvalidPLA = validPLA | (~use_ixiy&pla[74]&pla[55])&(M1&T4);\nnextM = nextM | (~use_ixiy&pla[74]&pla[55])&(M1&T4);\nctl_mRead = ctl_mRead | (~use_ixiy&pla[74]&pla[55])&(M1&T4);\nfMRead = fMRead | (~use_ixiy&pla[74]&pla[55])&(M2&T1);\nctl_reg_gp_sel_nuse_ixiypla74pla55M2T1_2 = (~use_ixiy&pla[74]&pla[55])&(M2&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla74pla55M2T1_2,ctl_reg_gp_sel_nuse_ixiypla74pla55M2T1_2})&(`GP_REG_HL);\nctl_reg_gp_hilo_nuse_ixiypla74pla55M2T1_3 = (~use_ixiy&pla[74]&pla[55])&(M2&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla74pla55M2T1_3,ctl_reg_gp_hilo_nuse_ixiypla74pla55M2T1_3})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (~use_ixiy&pla[74]&pla[55])&(M2&T1);\nctl_al_we = ctl_al_we | (~use_ixiy&pla[74]&pla[55])&(M2&T1);\nfMRead = fMRead | (~use_ixiy&pla[74]&pla[55])&(M2&T2);\nfMRead = fMRead | (~use_ixiy&pla[74]&pla[55])&(M2&T3);\nctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[74]&pla[55])&(M2&T3);\nctl_sw_1d = ctl_sw_1d | (~use_ixiy&pla[74]&pla[55])&(M2&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[74]&pla[55])&(M2&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[74]&pla[55])&(M2&T3)&(~ctl_alu_bs_oe);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[74]&pla[55])&(M2&T3);\nctl_alu_op_low = ctl_alu_op_low | (~use_ixiy&pla[74]&pla[55])&(M2&T3);\nctl_alu_core_R = ctl_alu_core_R | (~use_ixiy&pla[74]&pla[55])&(M2&T3);\nctl_alu_core_V = ctl_alu_core_V | (~use_ixiy&pla[74]&pla[55])&(M2&T3);\nctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[74]&pla[55])&(M2&T3);\nctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[74]&pla[55])&(M2&T3);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (~use_ixiy&pla[74]&pla[55])&(M2&T3);\nnextM = nextM | (~use_ixiy&pla[74]&pla[55])&(M2&T4);\nctl_mWrite = ctl_mWrite | (~use_ixiy&pla[74]&pla[55])&(M2&T4);\nctl_sw_2u = ctl_sw_2u | (~use_ixiy&pla[74]&pla[55])&(M2&T4);\nctl_sw_1u = ctl_sw_1u | (~use_ixiy&pla[74]&pla[55])&(M2&T4);\nctl_bus_db_we = ctl_bus_db_we | (~use_ixiy&pla[74]&pla[55])&(M2&T4);\nctl_alu_oe = ctl_alu_oe | (~use_ixiy&pla[74]&pla[55])&(M2&T4);\nctl_alu_res_oe = ctl_alu_res_oe | (~use_ixiy&pla[74]&pla[55])&(M2&T4);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (~use_ixiy&pla[74]&pla[55])&(M2&T4);\nctl_alu_core_R = ctl_alu_core_R | (~use_ixiy&pla[74]&pla[55])&(M2&T4);\nctl_alu_core_V = ctl_alu_core_V | (~use_ixiy&pla[74]&pla[55])&(M2&T4);\nctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[74]&pla[55])&(M2&T4);\nctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[74]&pla[55])&(M2&T4);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (~use_ixiy&pla[74]&pla[55])&(M2&T4);\nfMWrite = fMWrite | (~use_ixiy&pla[74]&pla[55])&(M3&T1);\nctl_bus_inc_oe = ctl_bus_inc_oe | (~use_ixiy&pla[74]&pla[55])&(M3&T1);\nfMWrite = fMWrite | (~use_ixiy&pla[74]&pla[55])&(M3&T2);\nfMWrite = fMWrite | (~use_ixiy&pla[74]&pla[55])&(M3&T3);\nsetM1 = setM1 | (~use_ixiy&pla[74]&pla[55])&(M3&T3);\nfMRead = fMRead | (~use_ixiy&pla[74]&pla[55])&(M4&T1);\nctl_reg_sel_wz = ctl_reg_sel_wz | (~use_ixiy&pla[74]&pla[55])&(M4&T1);\nctl_reg_sys_hilo_nuse_ixiypla74pla55M4T1_3 = (~use_ixiy&pla[74]&pla[55])&(M4&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_nuse_ixiypla74pla55M4T1_3,ctl_reg_sys_hilo_nuse_ixiypla74pla55M4T1_3})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (~use_ixiy&pla[74]&pla[55])&(M4&T1);\nctl_al_we = ctl_al_we | (~use_ixiy&pla[74]&pla[55])&(M4&T1);\nctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[74]&pla[55])&(M4&T1);\nctl_alu_bs_oe = ctl_alu_bs_oe | (~use_ixiy&pla[74]&pla[55])&(M4&T1);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[74]&pla[55])&(M4&T1);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[74]&pla[55])&(M4&T1);\nctl_ir_we = ctl_ir_we | (~use_ixiy&pla[74]&pla[55])&(M4&T1);\nfMRead = fMRead | (~use_ixiy&pla[74]&pla[55])&(M4&T2);\nfMRead = fMRead | (~use_ixiy&pla[74]&pla[55])&(M4&T3);\nnextM = nextM | (~use_ixiy&pla[74]&pla[55])&(M4&T3);\nctl_mWrite = ctl_mWrite | (~use_ixiy&pla[74]&pla[55])&(M4&T3);\nctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[74]&pla[55])&(M4&T3);\nctl_sw_1d = ctl_sw_1d | (~use_ixiy&pla[74]&pla[55])&(M4&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[74]&pla[55])&(M4&T3);\nctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[74]&pla[55])&(M4&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[74]&pla[55])&(M4&T3)&(~ctl_alu_bs_oe);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[74]&pla[55])&(M4&T3);\nctl_alu_op_low = ctl_alu_op_low | (~use_ixiy&pla[74]&pla[55])&(M4&T3);\nctl_alu_core_R = ctl_alu_core_R | (~use_ixiy&pla[74]&pla[55])&(M4&T3);\nctl_alu_core_V = ctl_alu_core_V | (~use_ixiy&pla[74]&pla[55])&(M4&T3);\nctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[74]&pla[55])&(M4&T3);\nctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[74]&pla[55])&(M4&T3);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (~use_ixiy&pla[74]&pla[55])&(M4&T3);\nfMWrite = fMWrite | (~use_ixiy&pla[74]&pla[55])&(M5&T1);\nctl_bus_inc_oe = ctl_bus_inc_oe | (~use_ixiy&pla[74]&pla[55])&(M5&T1);\nctl_sw_2u = ctl_sw_2u | (~use_ixiy&pla[74]&pla[55])&(M5&T1);\nctl_sw_1u = ctl_sw_1u | (~use_ixiy&pla[74]&pla[55])&(M5&T1);\nctl_bus_db_we = ctl_bus_db_we | (~use_ixiy&pla[74]&pla[55])&(M5&T1);\nctl_alu_oe = ctl_alu_oe | (~use_ixiy&pla[74]&pla[55])&(M5&T1);\nctl_alu_res_oe = ctl_alu_res_oe | (~use_ixiy&pla[74]&pla[55])&(M5&T1);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (~use_ixiy&pla[74]&pla[55])&(M5&T1);\nctl_alu_core_R = ctl_alu_core_R | (~use_ixiy&pla[74]&pla[55])&(M5&T1);\nctl_alu_core_V = ctl_alu_core_V | (~use_ixiy&pla[74]&pla[55])&(M5&T1);\nctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[74]&pla[55])&(M5&T1);\nctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[74]&pla[55])&(M5&T1);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (~use_ixiy&pla[74]&pla[55])&(M5&T1);\nfMWrite = fMWrite | (~use_ixiy&pla[74]&pla[55])&(M5&T2);\nfMWrite = fMWrite | (~use_ixiy&pla[74]&pla[55])&(M5&T3);\nsetM1 = setM1 | (~use_ixiy&pla[74]&pla[55])&(M5&T3);\nctl_reg_gp_we = ctl_reg_gp_we | (~use_ixiy&pla[73]&~pla[55])&(M1&T1);\nctl_reg_gp_sel_nuse_ixiypla73npla55M1T1_2 = (~use_ixiy&pla[73]&~pla[55])&(M1&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla73npla55M1T1_2,ctl_reg_gp_sel_nuse_ixiypla73npla55M1T1_2})&(op21);\nctl_reg_gp_hilo_nuse_ixiypla73npla55M1T1_3 = (~use_ixiy&pla[73]&~pla[55])&(M1&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla73npla55M1T1_3,ctl_reg_gp_hilo_nuse_ixiypla73npla55M1T1_3})&({~rsel0,rsel0});\nctl_reg_in_hi = ctl_reg_in_hi | (~use_ixiy&pla[73]&~pla[55])&(M1&T1);\nctl_reg_in_lo = ctl_reg_in_lo | (~use_ixiy&pla[73]&~pla[55])&(M1&T1);\nctl_sw_2u = ctl_sw_2u | (~use_ixiy&pla[73]&~pla[55])&(M1&T1);\nctl_alu_oe = ctl_alu_oe | (~use_ixiy&pla[73]&~pla[55])&(M1&T1);\nctl_alu_res_oe = ctl_alu_res_oe | (~use_ixiy&pla[73]&~pla[55])&(M1&T1);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (~use_ixiy&pla[73]&~pla[55])&(M1&T1);\nctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[73]&~pla[55])&(M1&T1);\nctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[73]&~pla[55])&(M1&T1);\nctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (~use_ixiy&pla[73]&~pla[55])&(M1&T1);\nctl_reg_gp_sel_nuse_ixiypla73npla55M1T3_1 = (~use_ixiy&pla[73]&~pla[55])&(M1&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla73npla55M1T3_1,ctl_reg_gp_sel_nuse_ixiypla73npla55M1T3_1})&(`GP_REG_AF);\nctl_reg_gp_hilo_nuse_ixiypla73npla55M1T3_2 = (~use_ixiy&pla[73]&~pla[55])&(M1&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla73npla55M1T3_2,ctl_reg_gp_hilo_nuse_ixiypla73npla55M1T3_2})&(2'b11);\nctl_reg_out_hi = ctl_reg_out_hi | (~use_ixiy&pla[73]&~pla[55])&(M1&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (~use_ixiy&pla[73]&~pla[55])&(M1&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[73]&~pla[55])&(M1&T3);\nctl_flags_bus = ctl_flags_bus | (~use_ixiy&pla[73]&~pla[55])&(M1&T3);\nctl_alu_bs_oe = ctl_alu_bs_oe | (~use_ixiy&pla[73]&~pla[55])&(M1&T3);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[73]&~pla[55])&(M1&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[73]&~pla[55])&(M1&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[73]&~pla[55])&(M1&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[73]&~pla[55])&(M1&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[73]&~pla[55])&(M1&T3);\nctl_flags_pf_we = ctl_flags_pf_we | (~use_ixiy&pla[73]&~pla[55])&(M1&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[73]&~pla[55])&(M1&T3);\nctl_flags_cf_we = ctl_flags_cf_we | (~use_ixiy&pla[73]&~pla[55])&(M1&T3);\nvalidPLA = validPLA | (~use_ixiy&pla[73]&~pla[55])&(M1&T4);\nsetM1 = setM1 | (~use_ixiy&pla[73]&~pla[55])&(M1&T4);\nctl_reg_gp_sel_nuse_ixiypla73npla55M1T4_3 = (~use_ixiy&pla[73]&~pla[55])&(M1&T4);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla73npla55M1T4_3,ctl_reg_gp_sel_nuse_ixiypla73npla55M1T4_3})&(op21);\nctl_reg_gp_hilo_nuse_ixiypla73npla55M1T4_4 = (~use_ixiy&pla[73]&~pla[55])&(M1&T4);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla73npla55M1T4_4,ctl_reg_gp_hilo_nuse_ixiypla73npla55M1T4_4})&({~rsel0,rsel0});\nctl_reg_out_hi = ctl_reg_out_hi | (~use_ixiy&pla[73]&~pla[55])&(M1&T4)&(~rsel0);\nctl_reg_out_lo = ctl_reg_out_lo | (~use_ixiy&pla[73]&~pla[55])&(M1&T4)&(rsel0);\nctl_sw_2u = ctl_sw_2u | (~use_ixiy&pla[73]&~pla[55])&(M1&T4)&(~rsel0);\nctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[73]&~pla[55])&(M1&T4)&(rsel0);\nctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[73]&~pla[55])&(M1&T4)&(~ctl_alu_bs_oe);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[73]&~pla[55])&(M1&T4);\nctl_alu_op_low = ctl_alu_op_low | (~use_ixiy&pla[73]&~pla[55])&(M1&T4);\nctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[73]&~pla[55])&(M1&T4);\nctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[73]&~pla[55])&(M1&T4);\nctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (~use_ixiy&pla[73]&~pla[55])&(M1&T4);\nfMRead = fMRead | (~use_ixiy&pla[73]&~pla[55])&(M4&T1);\nctl_reg_sel_wz = ctl_reg_sel_wz | (~use_ixiy&pla[73]&~pla[55])&(M4&T1);\nctl_reg_sys_hilo_nuse_ixiypla73npla55M4T1_3 = (~use_ixiy&pla[73]&~pla[55])&(M4&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_nuse_ixiypla73npla55M4T1_3,ctl_reg_sys_hilo_nuse_ixiypla73npla55M4T1_3})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (~use_ixiy&pla[73]&~pla[55])&(M4&T1);\nctl_al_we = ctl_al_we | (~use_ixiy&pla[73]&~pla[55])&(M4&T1);\nctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[73]&~pla[55])&(M4&T1);\nctl_alu_bs_oe = ctl_alu_bs_oe | (~use_ixiy&pla[73]&~pla[55])&(M4&T1);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[73]&~pla[55])&(M4&T1);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[73]&~pla[55])&(M4&T1);\nctl_ir_we = ctl_ir_we | (~use_ixiy&pla[73]&~pla[55])&(M4&T1);\nfMRead = fMRead | (~use_ixiy&pla[73]&~pla[55])&(M4&T2);\nfMRead = fMRead | (~use_ixiy&pla[73]&~pla[55])&(M4&T3);\nnextM = nextM | (~use_ixiy&pla[73]&~pla[55])&(M4&T3);\nctl_mWrite = ctl_mWrite | (~use_ixiy&pla[73]&~pla[55])&(M4&T3);\nctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[73]&~pla[55])&(M4&T3);\nctl_sw_1d = ctl_sw_1d | (~use_ixiy&pla[73]&~pla[55])&(M4&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[73]&~pla[55])&(M4&T3);\nctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[73]&~pla[55])&(M4&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[73]&~pla[55])&(M4&T3)&(~ctl_alu_bs_oe);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[73]&~pla[55])&(M4&T3);\nctl_alu_op_low = ctl_alu_op_low | (~use_ixiy&pla[73]&~pla[55])&(M4&T3);\nctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[73]&~pla[55])&(M4&T3);\nctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[73]&~pla[55])&(M4&T3);\nctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (~use_ixiy&pla[73]&~pla[55])&(M4&T3);\nfMWrite = fMWrite | (~use_ixiy&pla[73]&~pla[55])&(M5&T1);\nctl_bus_inc_oe = ctl_bus_inc_oe | (~use_ixiy&pla[73]&~pla[55])&(M5&T1);\nctl_sw_2u = ctl_sw_2u | (~use_ixiy&pla[73]&~pla[55])&(M5&T1);\nctl_sw_1u = ctl_sw_1u | (~use_ixiy&pla[73]&~pla[55])&(M5&T1);\nctl_bus_db_we = ctl_bus_db_we | (~use_ixiy&pla[73]&~pla[55])&(M5&T1);\nctl_alu_oe = ctl_alu_oe | (~use_ixiy&pla[73]&~pla[55])&(M5&T1);\nctl_alu_res_oe = ctl_alu_res_oe | (~use_ixiy&pla[73]&~pla[55])&(M5&T1);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (~use_ixiy&pla[73]&~pla[55])&(M5&T1);\nctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[73]&~pla[55])&(M5&T1);\nctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[73]&~pla[55])&(M5&T1);\nctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (~use_ixiy&pla[73]&~pla[55])&(M5&T1);\nfMWrite = fMWrite | (~use_ixiy&pla[73]&~pla[55])&(M5&T2);\nfMWrite = fMWrite | (~use_ixiy&pla[73]&~pla[55])&(M5&T3);\nsetM1 = setM1 | (~use_ixiy&pla[73]&~pla[55])&(M5&T3);\nctl_reg_gp_sel_nuse_ixiypla73pla55M1T3_1 = (~use_ixiy&pla[73]&pla[55])&(M1&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla73pla55M1T3_1,ctl_reg_gp_sel_nuse_ixiypla73pla55M1T3_1})&(`GP_REG_AF);\nctl_reg_gp_hilo_nuse_ixiypla73pla55M1T3_2 = (~use_ixiy&pla[73]&pla[55])&(M1&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla73pla55M1T3_2,ctl_reg_gp_hilo_nuse_ixiypla73pla55M1T3_2})&(2'b11);\nctl_reg_out_hi = ctl_reg_out_hi | (~use_ixiy&pla[73]&pla[55])&(M1&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (~use_ixiy&pla[73]&pla[55])&(M1&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[73]&pla[55])&(M1&T3);\nctl_flags_bus = ctl_flags_bus | (~use_ixiy&pla[73]&pla[55])&(M1&T3);\nctl_alu_bs_oe = ctl_alu_bs_oe | (~use_ixiy&pla[73]&pla[55])&(M1&T3);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[73]&pla[55])&(M1&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[73]&pla[55])&(M1&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (~use_ixiy&pla[73]&pla[55])&(M1&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (~use_ixiy&pla[73]&pla[55])&(M1&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (~use_ixiy&pla[73]&pla[55])&(M1&T3);\nctl_flags_pf_we = ctl_flags_pf_we | (~use_ixiy&pla[73]&pla[55])&(M1&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (~use_ixiy&pla[73]&pla[55])&(M1&T3);\nctl_flags_cf_we = ctl_flags_cf_we | (~use_ixiy&pla[73]&pla[55])&(M1&T3);\nvalidPLA = validPLA | (~use_ixiy&pla[73]&pla[55])&(M1&T4);\nnextM = nextM | (~use_ixiy&pla[73]&pla[55])&(M1&T4);\nctl_mRead = ctl_mRead | (~use_ixiy&pla[73]&pla[55])&(M1&T4);\nfMRead = fMRead | (~use_ixiy&pla[73]&pla[55])&(M2&T1);\nctl_reg_gp_sel_nuse_ixiypla73pla55M2T1_2 = (~use_ixiy&pla[73]&pla[55])&(M2&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_nuse_ixiypla73pla55M2T1_2,ctl_reg_gp_sel_nuse_ixiypla73pla55M2T1_2})&(`GP_REG_HL);\nctl_reg_gp_hilo_nuse_ixiypla73pla55M2T1_3 = (~use_ixiy&pla[73]&pla[55])&(M2&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_nuse_ixiypla73pla55M2T1_3,ctl_reg_gp_hilo_nuse_ixiypla73pla55M2T1_3})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (~use_ixiy&pla[73]&pla[55])&(M2&T1);\nctl_al_we = ctl_al_we | (~use_ixiy&pla[73]&pla[55])&(M2&T1);\nfMRead = fMRead | (~use_ixiy&pla[73]&pla[55])&(M2&T2);\nfMRead = fMRead | (~use_ixiy&pla[73]&pla[55])&(M2&T3);\nctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[73]&pla[55])&(M2&T3);\nctl_sw_1d = ctl_sw_1d | (~use_ixiy&pla[73]&pla[55])&(M2&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[73]&pla[55])&(M2&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[73]&pla[55])&(M2&T3)&(~ctl_alu_bs_oe);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[73]&pla[55])&(M2&T3);\nctl_alu_op_low = ctl_alu_op_low | (~use_ixiy&pla[73]&pla[55])&(M2&T3);\nctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[73]&pla[55])&(M2&T3);\nctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[73]&pla[55])&(M2&T3);\nctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (~use_ixiy&pla[73]&pla[55])&(M2&T3);\nnextM = nextM | (~use_ixiy&pla[73]&pla[55])&(M2&T4);\nctl_mWrite = ctl_mWrite | (~use_ixiy&pla[73]&pla[55])&(M2&T4);\nctl_sw_2u = ctl_sw_2u | (~use_ixiy&pla[73]&pla[55])&(M2&T4);\nctl_sw_1u = ctl_sw_1u | (~use_ixiy&pla[73]&pla[55])&(M2&T4);\nctl_bus_db_we = ctl_bus_db_we | (~use_ixiy&pla[73]&pla[55])&(M2&T4);\nctl_alu_oe = ctl_alu_oe | (~use_ixiy&pla[73]&pla[55])&(M2&T4);\nctl_alu_res_oe = ctl_alu_res_oe | (~use_ixiy&pla[73]&pla[55])&(M2&T4);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (~use_ixiy&pla[73]&pla[55])&(M2&T4);\nctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[73]&pla[55])&(M2&T4);\nctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[73]&pla[55])&(M2&T4);\nctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (~use_ixiy&pla[73]&pla[55])&(M2&T4);\nfMWrite = fMWrite | (~use_ixiy&pla[73]&pla[55])&(M3&T1);\nctl_bus_inc_oe = ctl_bus_inc_oe | (~use_ixiy&pla[73]&pla[55])&(M3&T1);\nfMWrite = fMWrite | (~use_ixiy&pla[73]&pla[55])&(M3&T2);\nfMWrite = fMWrite | (~use_ixiy&pla[73]&pla[55])&(M3&T3);\nsetM1 = setM1 | (~use_ixiy&pla[73]&pla[55])&(M3&T3);\nfMRead = fMRead | (~use_ixiy&pla[73]&pla[55])&(M4&T1);\nctl_reg_sel_wz = ctl_reg_sel_wz | (~use_ixiy&pla[73]&pla[55])&(M4&T1);\nctl_reg_sys_hilo_nuse_ixiypla73pla55M4T1_3 = (~use_ixiy&pla[73]&pla[55])&(M4&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_nuse_ixiypla73pla55M4T1_3,ctl_reg_sys_hilo_nuse_ixiypla73pla55M4T1_3})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (~use_ixiy&pla[73]&pla[55])&(M4&T1);\nctl_al_we = ctl_al_we | (~use_ixiy&pla[73]&pla[55])&(M4&T1);\nctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[73]&pla[55])&(M4&T1);\nctl_alu_bs_oe = ctl_alu_bs_oe | (~use_ixiy&pla[73]&pla[55])&(M4&T1);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (~use_ixiy&pla[73]&pla[55])&(M4&T1);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[73]&pla[55])&(M4&T1);\nctl_ir_we = ctl_ir_we | (~use_ixiy&pla[73]&pla[55])&(M4&T1);\nfMRead = fMRead | (~use_ixiy&pla[73]&pla[55])&(M4&T2);\nfMRead = fMRead | (~use_ixiy&pla[73]&pla[55])&(M4&T3);\nnextM = nextM | (~use_ixiy&pla[73]&pla[55])&(M4&T3);\nctl_mWrite = ctl_mWrite | (~use_ixiy&pla[73]&pla[55])&(M4&T3);\nctl_sw_2d = ctl_sw_2d | (~use_ixiy&pla[73]&pla[55])&(M4&T3);\nctl_sw_1d = ctl_sw_1d | (~use_ixiy&pla[73]&pla[55])&(M4&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (~use_ixiy&pla[73]&pla[55])&(M4&T3);\nctl_flags_alu = ctl_flags_alu | (~use_ixiy&pla[73]&pla[55])&(M4&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (~use_ixiy&pla[73]&pla[55])&(M4&T3)&(~ctl_alu_bs_oe);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (~use_ixiy&pla[73]&pla[55])&(M4&T3);\nctl_alu_op_low = ctl_alu_op_low | (~use_ixiy&pla[73]&pla[55])&(M4&T3);\nctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[73]&pla[55])&(M4&T3);\nctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[73]&pla[55])&(M4&T3);\nctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (~use_ixiy&pla[73]&pla[55])&(M4&T3);\nfMWrite = fMWrite | (~use_ixiy&pla[73]&pla[55])&(M5&T1);\nctl_bus_inc_oe = ctl_bus_inc_oe | (~use_ixiy&pla[73]&pla[55])&(M5&T1);\nctl_sw_2u = ctl_sw_2u | (~use_ixiy&pla[73]&pla[55])&(M5&T1);\nctl_sw_1u = ctl_sw_1u | (~use_ixiy&pla[73]&pla[55])&(M5&T1);\nctl_bus_db_we = ctl_bus_db_we | (~use_ixiy&pla[73]&pla[55])&(M5&T1);\nctl_alu_oe = ctl_alu_oe | (~use_ixiy&pla[73]&pla[55])&(M5&T1);\nctl_alu_res_oe = ctl_alu_res_oe | (~use_ixiy&pla[73]&pla[55])&(M5&T1);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (~use_ixiy&pla[73]&pla[55])&(M5&T1);\nctl_alu_core_S = ctl_alu_core_S | (~use_ixiy&pla[73]&pla[55])&(M5&T1);\nctl_flags_cf_set = ctl_flags_cf_set | (~use_ixiy&pla[73]&pla[55])&(M5&T1);\nctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (~use_ixiy&pla[73]&pla[55])&(M5&T1);\nfMWrite = fMWrite | (~use_ixiy&pla[73]&pla[55])&(M5&T2);\nfMWrite = fMWrite | (~use_ixiy&pla[73]&pla[55])&(M5&T3);\nsetM1 = setM1 | (~use_ixiy&pla[73]&pla[55])&(M5&T3);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[37]&~pla[28])&(M1&T1);\nctl_reg_gp_sel_pla37npla28M1T1_2 = (pla[37]&~pla[28])&(M1&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla37npla28M1T1_2,ctl_reg_gp_sel_pla37npla28M1T1_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla37npla28M1T1_3 = (pla[37]&~pla[28])&(M1&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla37npla28M1T1_3,ctl_reg_gp_hilo_pla37npla28M1T1_3})&(2'b10);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[37]&~pla[28])&(M1&T1);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[37]&~pla[28])&(M1&T1);\nctl_sw_2d = ctl_sw_2d | (pla[37]&~pla[28])&(M1&T1);\nctl_sw_1d = ctl_sw_1d | (pla[37]&~pla[28])&(M1&T1);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[37]&~pla[28])&(M1&T1);\nvalidPLA = validPLA | (pla[37]&~pla[28])&(M1&T4);\nnextM = nextM | (pla[37]&~pla[28])&(M1&T4);\nctl_mRead = ctl_mRead | (pla[37]&~pla[28])&(M1&T4);\nfMRead = fMRead | (pla[37]&~pla[28])&(M2&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[37]&~pla[28])&(M2&T1);\nctl_reg_sys_hilo_pla37npla28M2T1_3 = (pla[37]&~pla[28])&(M2&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla37npla28M2T1_3,ctl_reg_sys_hilo_pla37npla28M2T1_3})&(2'b11);\nctl_al_we = ctl_al_we | (pla[37]&~pla[28])&(M2&T1);\nfMRead = fMRead | (pla[37]&~pla[28])&(M2&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[37]&~pla[28])&(M2&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[37]&~pla[28])&(M2&T2);\nctl_reg_sys_hilo_pla37npla28M2T2_4 = (pla[37]&~pla[28])&(M2&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla37npla28M2T2_4,ctl_reg_sys_hilo_pla37npla28M2T2_4})&(2'b11);\npc_inc_hold = pc_inc_hold | (pla[37]&~pla[28])&(M2&T2)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (pla[37]&~pla[28])&(M2&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[37]&~pla[28])&(M2&T2);\nfMRead = fMRead | (pla[37]&~pla[28])&(M2&T3);\nnextM = nextM | (pla[37]&~pla[28])&(M2&T3);\nctl_iorw = ctl_iorw | (pla[37]&~pla[28])&(M2&T3);\nfIORead = fIORead | (pla[37]&~pla[28])&(M3&T1);\nctl_reg_gp_sel_pla37npla28M3T1_2 = (pla[37]&~pla[28])&(M3&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla37npla28M3T1_2,ctl_reg_gp_sel_pla37npla28M3T1_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla37npla28M3T1_3 = (pla[37]&~pla[28])&(M3&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla37npla28M3T1_3,ctl_reg_gp_hilo_pla37npla28M3T1_3})&(2'b10);\nctl_sw_4d = ctl_sw_4d | (pla[37]&~pla[28])&(M3&T1);\nctl_al_we = ctl_al_we | (pla[37]&~pla[28])&(M3&T1);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[37]&~pla[28])&(M3&T1);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[37]&~pla[28])&(M3&T1);\nctl_sw_1d = ctl_sw_1d | (pla[37]&~pla[28])&(M3&T1);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[37]&~pla[28])&(M3&T1);\nfIORead = fIORead | (pla[37]&~pla[28])&(M3&T2);\nfIORead = fIORead | (pla[37]&~pla[28])&(M3&T3);\nfIORead = fIORead | (pla[37]&~pla[28])&(M3&T4);\nsetM1 = setM1 | (pla[37]&~pla[28])&(M3&T4);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[27]&~pla[34])&(M1&T1);\nctl_reg_gp_sel_pla27npla34M1T1_2 = (pla[27]&~pla[34])&(M1&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla27npla34M1T1_2,ctl_reg_gp_sel_pla27npla34M1T1_2})&(op54);\nctl_reg_gp_hilo_pla27npla34M1T1_3 = (pla[27]&~pla[34])&(M1&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla27npla34M1T1_3,ctl_reg_gp_hilo_pla27npla34M1T1_3})&({~rsel3,rsel3});\nctl_reg_in_hi = ctl_reg_in_hi | (pla[27]&~pla[34])&(M1&T1);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[27]&~pla[34])&(M1&T1);\nctl_sw_2d = ctl_sw_2d | (pla[27]&~pla[34])&(M1&T1);\nctl_sw_1d = ctl_sw_1d | (pla[27]&~pla[34])&(M1&T1);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[27]&~pla[34])&(M1&T1);\nctl_flags_alu = ctl_flags_alu | (pla[27]&~pla[34])&(M1&T1);\nctl_alu_res_oe = ctl_alu_res_oe | (pla[27]&~pla[34])&(M1&T1);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[27]&~pla[34])&(M1&T1);\nctl_alu_core_R = ctl_alu_core_R | (pla[27]&~pla[34])&(M1&T1);\nctl_alu_core_V = ctl_alu_core_V | (pla[27]&~pla[34])&(M1&T1);\nctl_alu_core_S = ctl_alu_core_S | (pla[27]&~pla[34])&(M1&T1);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[27]&~pla[34])&(M1&T1);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[27]&~pla[34])&(M1&T1);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[27]&~pla[34])&(M1&T1);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[27]&~pla[34])&(M1&T1);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[27]&~pla[34])&(M1&T1);\nctl_pf_sel_pla27npla34M1T1_20 = (pla[27]&~pla[34])&(M1&T1);\nctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_pla27npla34M1T1_20,ctl_pf_sel_pla27npla34M1T1_20})&(`PFSEL_P);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[27]&~pla[34])&(M1&T1);\nctl_flags_nf_clr = ctl_flags_nf_clr | (pla[27]&~pla[34])&(M1&T1);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[27]&~pla[34])&(M1&T2);\nctl_reg_gp_sel_pla27npla34M1T2_2 = (pla[27]&~pla[34])&(M1&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla27npla34M1T2_2,ctl_reg_gp_sel_pla27npla34M1T2_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla27npla34M1T2_3 = (pla[27]&~pla[34])&(M1&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla27npla34M1T2_3,ctl_reg_gp_hilo_pla27npla34M1T2_3})&(2'b01);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[27]&~pla[34])&(M1&T2);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[27]&~pla[34])&(M1&T2);\nctl_flags_oe = ctl_flags_oe | (pla[27]&~pla[34])&(M1&T2);\nctl_reg_gp_sel_pla27npla34M1T3_1 = (pla[27]&~pla[34])&(M1&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla27npla34M1T3_1,ctl_reg_gp_sel_pla27npla34M1T3_1})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla27npla34M1T3_2 = (pla[27]&~pla[34])&(M1&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla27npla34M1T3_2,ctl_reg_gp_hilo_pla27npla34M1T3_2})&(2'b11);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[27]&~pla[34])&(M1&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[27]&~pla[34])&(M1&T3);\nctl_flags_bus = ctl_flags_bus | (pla[27]&~pla[34])&(M1&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[27]&~pla[34])&(M1&T3)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[27]&~pla[34])&(M1&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[27]&~pla[34])&(M1&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[27]&~pla[34])&(M1&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[27]&~pla[34])&(M1&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[27]&~pla[34])&(M1&T3);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[27]&~pla[34])&(M1&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[27]&~pla[34])&(M1&T3);\nctl_flags_cf_we = ctl_flags_cf_we | (pla[27]&~pla[34])&(M1&T3);\nvalidPLA = validPLA | (pla[27]&~pla[34])&(M1&T4);\nnextM = nextM | (pla[27]&~pla[34])&(M1&T4);\nctl_iorw = ctl_iorw | (pla[27]&~pla[34])&(M1&T4);\nfIORead = fIORead | (pla[27]&~pla[34])&(M2&T1);\nctl_reg_gp_sel_pla27npla34M2T1_2 = (pla[27]&~pla[34])&(M2&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla27npla34M2T1_2,ctl_reg_gp_sel_pla27npla34M2T1_2})&(`GP_REG_BC);\nctl_reg_gp_hilo_pla27npla34M2T1_3 = (pla[27]&~pla[34])&(M2&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla27npla34M2T1_3,ctl_reg_gp_hilo_pla27npla34M2T1_3})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[27]&~pla[34])&(M2&T1);\nctl_al_we = ctl_al_we | (pla[27]&~pla[34])&(M2&T1);\nfIORead = fIORead | (pla[27]&~pla[34])&(M2&T2);\nfIORead = fIORead | (pla[27]&~pla[34])&(M2&T3);\nfIORead = fIORead | (pla[27]&~pla[34])&(M2&T4);\nsetM1 = setM1 | (pla[27]&~pla[34])&(M2&T4);\nctl_sw_2d = ctl_sw_2d | (pla[27]&~pla[34])&(M2&T4);\nctl_sw_1d = ctl_sw_1d | (pla[27]&~pla[34])&(M2&T4);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[27]&~pla[34])&(M2&T4);\nctl_flags_alu = ctl_flags_alu | (pla[27]&~pla[34])&(M2&T4);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[27]&~pla[34])&(M2&T4)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[27]&~pla[34])&(M2&T4);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[27]&~pla[34])&(M2&T4);\nctl_alu_op_low = ctl_alu_op_low | (pla[27]&~pla[34])&(M2&T4);\nctl_alu_core_R = ctl_alu_core_R | (pla[27]&~pla[34])&(M2&T4);\nctl_alu_core_V = ctl_alu_core_V | (pla[27]&~pla[34])&(M2&T4);\nctl_alu_core_S = ctl_alu_core_S | (pla[27]&~pla[34])&(M2&T4);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[27]&~pla[34])&(M2&T4);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[27]&~pla[34])&(M2&T4);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[27]&~pla[34])&(M2&T4);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[27]&~pla[34])&(M2&T4);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[27]&~pla[34])&(M2&T4);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[27]&~pla[34])&(M2&T4);\nctl_flags_nf_clr = ctl_flags_nf_clr | (pla[27]&~pla[34])&(M2&T4);\nvalidPLA = validPLA | (pla[37]&pla[28])&(M1&T4);\nnextM = nextM | (pla[37]&pla[28])&(M1&T4);\nctl_mRead = ctl_mRead | (pla[37]&pla[28])&(M1&T4);\nfMRead = fMRead | (pla[37]&pla[28])&(M2&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[37]&pla[28])&(M2&T1);\nctl_reg_sys_hilo_pla37pla28M2T1_3 = (pla[37]&pla[28])&(M2&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla37pla28M2T1_3,ctl_reg_sys_hilo_pla37pla28M2T1_3})&(2'b11);\nctl_al_we = ctl_al_we | (pla[37]&pla[28])&(M2&T1);\nfMRead = fMRead | (pla[37]&pla[28])&(M2&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[37]&pla[28])&(M2&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[37]&pla[28])&(M2&T2);\nctl_reg_sys_hilo_pla37pla28M2T2_4 = (pla[37]&pla[28])&(M2&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla37pla28M2T2_4,ctl_reg_sys_hilo_pla37pla28M2T2_4})&(2'b11);\npc_inc_hold = pc_inc_hold | (pla[37]&pla[28])&(M2&T2)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (pla[37]&pla[28])&(M2&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[37]&pla[28])&(M2&T2);\nfMRead = fMRead | (pla[37]&pla[28])&(M2&T3);\nnextM = nextM | (pla[37]&pla[28])&(M2&T3);\nctl_iorw = ctl_iorw | (pla[37]&pla[28])&(M2&T3);\nctl_reg_gp_sel_pla37pla28M2T3_4 = (pla[37]&pla[28])&(M2&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla37pla28M2T3_4,ctl_reg_gp_sel_pla37pla28M2T3_4})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla37pla28M2T3_5 = (pla[37]&pla[28])&(M2&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla37pla28M2T3_5,ctl_reg_gp_hilo_pla37pla28M2T3_5})&(2'b10);\nctl_sw_4d = ctl_sw_4d | (pla[37]&pla[28])&(M2&T3);\nctl_al_we = ctl_al_we | (pla[37]&pla[28])&(M2&T3);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[37]&pla[28])&(M2&T3);\nctl_sw_1d = ctl_sw_1d | (pla[37]&pla[28])&(M2&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[37]&pla[28])&(M2&T3);\nfIOWrite = fIOWrite | (pla[37]&pla[28])&(M3&T1);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[37]&pla[28])&(M3&T1);\nctl_reg_gp_sel_pla37pla28M3T1_3 = (pla[37]&pla[28])&(M3&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla37pla28M3T1_3,ctl_reg_gp_sel_pla37pla28M3T1_3})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla37pla28M3T1_4 = (pla[37]&pla[28])&(M3&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla37pla28M3T1_4,ctl_reg_gp_hilo_pla37pla28M3T1_4})&(2'b10);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[37]&pla[28])&(M3&T1);\nctl_sw_2u = ctl_sw_2u | (pla[37]&pla[28])&(M3&T1);\nctl_sw_1u = ctl_sw_1u | (pla[37]&pla[28])&(M3&T1);\nctl_bus_db_we = ctl_bus_db_we | (pla[37]&pla[28])&(M3&T1);\nfIOWrite = fIOWrite | (pla[37]&pla[28])&(M3&T2);\nfIOWrite = fIOWrite | (pla[37]&pla[28])&(M3&T3);\nfIOWrite = fIOWrite | (pla[37]&pla[28])&(M3&T4);\nsetM1 = setM1 | (pla[37]&pla[28])&(M3&T4);\nvalidPLA = validPLA | (pla[27]&pla[34])&(M1&T4);\nnextM = nextM | (pla[27]&pla[34])&(M1&T4);\nctl_iorw = ctl_iorw | (pla[27]&pla[34])&(M1&T4);\nctl_bus_zero_oe = ctl_bus_zero_oe | (pla[27]&pla[34])&(M1&T4)&(op4&op5&~op3);\nctl_reg_gp_sel_pla27pla34M1T4nop4op5nop3_1 = (pla[27]&pla[34])&(M1&T4)&(~(op4&op5&~op3));\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla27pla34M1T4nop4op5nop3_1,ctl_reg_gp_sel_pla27pla34M1T4nop4op5nop3_1})&(op54);\nctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2 = (pla[27]&pla[34])&(M1&T4)&(~(op4&op5&~op3));\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2,ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2})&({~rsel3,rsel3});\nctl_reg_out_hi = ctl_reg_out_hi | (pla[27]&pla[34])&(M1&T4)&(~rsel3);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[27]&pla[34])&(M1&T4)&(rsel3);\nctl_sw_2u = ctl_sw_2u | (pla[27]&pla[34])&(M1&T4)&(~rsel3);\nctl_sw_2d = ctl_sw_2d | (pla[27]&pla[34])&(M1&T4)&(rsel3);\nctl_sw_1u = ctl_sw_1u | (pla[27]&pla[34])&(M1&T4);\nctl_bus_db_we = ctl_bus_db_we | (pla[27]&pla[34])&(M1&T4);\nfIOWrite = fIOWrite | (pla[27]&pla[34])&(M2&T1);\nctl_reg_gp_sel_pla27pla34M2T1_2 = (pla[27]&pla[34])&(M2&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla27pla34M2T1_2,ctl_reg_gp_sel_pla27pla34M2T1_2})&(`GP_REG_BC);\nctl_reg_gp_hilo_pla27pla34M2T1_3 = (pla[27]&pla[34])&(M2&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla27pla34M2T1_3,ctl_reg_gp_hilo_pla27pla34M2T1_3})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[27]&pla[34])&(M2&T1);\nctl_al_we = ctl_al_we | (pla[27]&pla[34])&(M2&T1);\nfIOWrite = fIOWrite | (pla[27]&pla[34])&(M2&T2);\nfIOWrite = fIOWrite | (pla[27]&pla[34])&(M2&T3);\nfIOWrite = fIOWrite | (pla[27]&pla[34])&(M2&T4);\nsetM1 = setM1 | (pla[27]&pla[34])&(M2&T4);\nctl_alu_oe = ctl_alu_oe | (pla[91]&pla[21])&(M1&T1);\nctl_alu_res_oe = ctl_alu_res_oe | (pla[91]&pla[21])&(M1&T1);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[91]&pla[21])&(M1&T1);\nctl_alu_core_R = ctl_alu_core_R | (pla[91]&pla[21])&(M1&T1);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[91]&pla[21])&(M1&T1);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[91]&pla[21])&(M1&T1);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[91]&pla[21])&(M1&T1);\nctl_pf_sel_pla91pla21M1T1_8 = (pla[91]&pla[21])&(M1&T1);\nctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_pla91pla21M1T1_8,ctl_pf_sel_pla91pla21M1T1_8})&(`PFSEL_P);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[91]&pla[21])&(M1&T2);\nctl_reg_gp_sel_pla91pla21M1T2_2 = (pla[91]&pla[21])&(M1&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla91pla21M1T2_2,ctl_reg_gp_sel_pla91pla21M1T2_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla91pla21M1T2_3 = (pla[91]&pla[21])&(M1&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla91pla21M1T2_3,ctl_reg_gp_hilo_pla91pla21M1T2_3})&(2'b01);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[91]&pla[21])&(M1&T2);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[91]&pla[21])&(M1&T2);\nctl_flags_oe = ctl_flags_oe | (pla[91]&pla[21])&(M1&T2);\nctl_reg_gp_sel_pla91pla21M1T3_1 = (pla[91]&pla[21])&(M1&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla91pla21M1T3_1,ctl_reg_gp_sel_pla91pla21M1T3_1})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla91pla21M1T3_2 = (pla[91]&pla[21])&(M1&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla91pla21M1T3_2,ctl_reg_gp_hilo_pla91pla21M1T3_2})&(2'b11);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[91]&pla[21])&(M1&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[91]&pla[21])&(M1&T3);\nctl_flags_bus = ctl_flags_bus | (pla[91]&pla[21])&(M1&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[91]&pla[21])&(M1&T3)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[91]&pla[21])&(M1&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[91]&pla[21])&(M1&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[91]&pla[21])&(M1&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[91]&pla[21])&(M1&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[91]&pla[21])&(M1&T3);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[91]&pla[21])&(M1&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[91]&pla[21])&(M1&T3);\nctl_flags_cf_we = ctl_flags_cf_we | (pla[91]&pla[21])&(M1&T3);\nvalidPLA = validPLA | (pla[91]&pla[21])&(M1&T4);\nnextM = nextM | (pla[91]&pla[21])&(M1&T5);\nctl_iorw = ctl_iorw | (pla[91]&pla[21])&(M1&T5);\nfIORead = fIORead | (pla[91]&pla[21])&(M2&T1);\nctl_reg_gp_sel_pla91pla21M2T1_2 = (pla[91]&pla[21])&(M2&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla91pla21M2T1_2,ctl_reg_gp_sel_pla91pla21M2T1_2})&(`GP_REG_BC);\nctl_reg_gp_hilo_pla91pla21M2T1_3 = (pla[91]&pla[21])&(M2&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla91pla21M2T1_3,ctl_reg_gp_hilo_pla91pla21M2T1_3})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[91]&pla[21])&(M2&T1);\nctl_al_we = ctl_al_we | (pla[91]&pla[21])&(M2&T1);\nfIORead = fIORead | (pla[91]&pla[21])&(M2&T2);\nctl_reg_gp_sel_pla91pla21M2T2_2 = (pla[91]&pla[21])&(M2&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla91pla21M2T2_2,ctl_reg_gp_sel_pla91pla21M2T2_2})&(`GP_REG_BC);\nctl_reg_gp_hilo_pla91pla21M2T2_3 = (pla[91]&pla[21])&(M2&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla91pla21M2T2_3,ctl_reg_gp_hilo_pla91pla21M2T2_3})&(2'b10);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[91]&pla[21])&(M2&T2);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[91]&pla[21])&(M2&T2);\nctl_flags_alu = ctl_flags_alu | (pla[91]&pla[21])&(M2&T2);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[91]&pla[21])&(M2&T2)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_zero = ctl_alu_op2_sel_zero | (pla[91]&pla[21])&(M2&T2);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[91]&pla[21])&(M2&T2);\nctl_alu_op_low = ctl_alu_op_low | (pla[91]&pla[21])&(M2&T2);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[91]&pla[21])&(M2&T2)&(ctl_alu_op_low);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[91]&pla[21])&(M2&T2)&(ctl_alu_op_low);\nctl_alu_core_hf = ctl_alu_core_hf | (pla[91]&pla[21])&(M2&T2)&(~ctl_alu_op_low);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[91]&pla[21])&(M2&T2);\nctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[91]&pla[21])&(M2&T2);\nfIORead = fIORead | (pla[91]&pla[21])&(M2&T3);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[91]&pla[21])&(M2&T3);\nctl_reg_gp_sel_pla91pla21M2T3_3 = (pla[91]&pla[21])&(M2&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla91pla21M2T3_3,ctl_reg_gp_sel_pla91pla21M2T3_3})&(`GP_REG_BC);\nctl_reg_gp_hilo_pla91pla21M2T3_4 = (pla[91]&pla[21])&(M2&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla91pla21M2T3_4,ctl_reg_gp_hilo_pla91pla21M2T3_4})&(2'b10);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[91]&pla[21])&(M2&T3);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[91]&pla[21])&(M2&T3);\nctl_flags_alu = ctl_flags_alu | (pla[91]&pla[21])&(M2&T3);\nctl_alu_oe = ctl_alu_oe | (pla[91]&pla[21])&(M2&T3);\nctl_alu_res_oe = ctl_alu_res_oe | (pla[91]&pla[21])&(M2&T3);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[91]&pla[21])&(M2&T3);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[91]&pla[21])&(M2&T3)&(ctl_alu_op_low);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[91]&pla[21])&(M2&T3)&(ctl_alu_op_low);\nctl_alu_core_hf = ctl_alu_core_hf | (pla[91]&pla[21])&(M2&T3)&(~ctl_alu_op_low);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[91]&pla[21])&(M2&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[91]&pla[21])&(M2&T3);\nctl_flags_cf_we = ctl_flags_cf_we | (pla[91]&pla[21])&(M2&T3);\nctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[91]&pla[21])&(M2&T3);\nfIORead = fIORead | (pla[91]&pla[21])&(M2&T4);\nnextM = nextM | (pla[91]&pla[21])&(M2&T4);\nctl_mWrite = ctl_mWrite | (pla[91]&pla[21])&(M2&T4);\nctl_sw_2d = ctl_sw_2d | (pla[91]&pla[21])&(M2&T4);\nctl_sw_1d = ctl_sw_1d | (pla[91]&pla[21])&(M2&T4);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[91]&pla[21])&(M2&T4);\nctl_flags_alu = ctl_flags_alu | (pla[91]&pla[21])&(M2&T4);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[91]&pla[21])&(M2&T4)&(~ctl_alu_bs_oe);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[91]&pla[21])&(M2&T4);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[91]&pla[21])&(M2&T4);\nctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[91]&pla[21])&(M2&T4);\nfMWrite = fMWrite | (pla[91]&pla[21])&(M3&T1);\nctl_reg_gp_sel_pla91pla21M3T1_2 = (pla[91]&pla[21])&(M3&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla91pla21M3T1_2,ctl_reg_gp_sel_pla91pla21M3T1_2})&(`GP_REG_HL);\nctl_reg_gp_hilo_pla91pla21M3T1_3 = (pla[91]&pla[21])&(M3&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla91pla21M3T1_3,ctl_reg_gp_hilo_pla91pla21M3T1_3})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[91]&pla[21])&(M3&T1);\nctl_al_we = ctl_al_we | (pla[91]&pla[21])&(M3&T1);\nfMWrite = fMWrite | (pla[91]&pla[21])&(M3&T2);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[91]&pla[21])&(M3&T2);\nctl_reg_gp_sel_pla91pla21M3T2_3 = (pla[91]&pla[21])&(M3&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla91pla21M3T2_3,ctl_reg_gp_sel_pla91pla21M3T2_3})&(`GP_REG_HL);\nctl_reg_gp_hilo_pla91pla21M3T2_4 = (pla[91]&pla[21])&(M3&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla91pla21M3T2_4,ctl_reg_gp_hilo_pla91pla21M3T2_4})&(2'b11);\nctl_sw_4u = ctl_sw_4u | (pla[91]&pla[21])&(M3&T2);\nctl_inc_cy = ctl_inc_cy | (pla[91]&pla[21])&(M3&T2)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[91]&pla[21])&(M3&T2)&(op3);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[91]&pla[21])&(M3&T2);\nfMWrite = fMWrite | (pla[91]&pla[21])&(M3&T3);\nnextM = nextM | (pla[91]&pla[21])&(M3&T3);\nsetM1 = setM1 | (pla[91]&pla[21])&(M3&T3)&(nonRep|flags_zf);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[91]&pla[21])&(M4&T1);\nctl_reg_sys_hilo_pla91pla21M4T1_2 = (pla[91]&pla[21])&(M4&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla91pla21M4T1_2,ctl_reg_sys_hilo_pla91pla21M4T1_2})&(2'b11);\nctl_al_we = ctl_al_we | (pla[91]&pla[21])&(M4&T1);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[91]&pla[21])&(M4&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[91]&pla[21])&(M4&T2);\nctl_reg_sys_hilo_pla91pla21M4T2_3 = (pla[91]&pla[21])&(M4&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla91pla21M4T2_3,ctl_reg_sys_hilo_pla91pla21M4T2_3})&(2'b11);\npc_inc_hold = pc_inc_hold | (pla[91]&pla[21])&(M4&T2)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (pla[91]&pla[21])&(M4&T2)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[91]&pla[21])&(M4&T2);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[91]&pla[21])&(M4&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[91]&pla[21])&(M4&T3);\nctl_reg_sys_hilo_pla91pla21M4T3_2 = (pla[91]&pla[21])&(M4&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla91pla21M4T3_2,ctl_reg_sys_hilo_pla91pla21M4T3_2})&(2'b11);\nctl_al_we = ctl_al_we | (pla[91]&pla[21])&(M4&T3);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[91]&pla[21])&(M4&T4);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[91]&pla[21])&(M4&T4);\nctl_reg_sys_hilo_pla91pla21M4T4_3 = (pla[91]&pla[21])&(M4&T4);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla91pla21M4T4_3,ctl_reg_sys_hilo_pla91pla21M4T4_3})&(2'b11);\npc_inc_hold = pc_inc_hold | (pla[91]&pla[21])&(M4&T4)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (pla[91]&pla[21])&(M4&T4)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[91]&pla[21])&(M4&T4);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[91]&pla[21])&(M4&T4);\nsetM1 = setM1 | (pla[91]&pla[21])&(M4&T5);\nctl_flags_alu = ctl_flags_alu | (pla[91]&pla[20])&(M1&T1);\nctl_alu_oe = ctl_alu_oe | (pla[91]&pla[20])&(M1&T1);\nctl_alu_res_oe = ctl_alu_res_oe | (pla[91]&pla[20])&(M1&T1);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[91]&pla[20])&(M1&T1);\nctl_alu_core_R = ctl_alu_core_R | (pla[91]&pla[20])&(M1&T1);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[91]&pla[20])&(M1&T1);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[91]&pla[20])&(M1&T1);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[91]&pla[20])&(M1&T1);\nctl_pf_sel_pla91pla20M1T1_9 = (pla[91]&pla[20])&(M1&T1);\nctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_pla91pla20M1T1_9,ctl_pf_sel_pla91pla20M1T1_9})&(`PFSEL_P);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[91]&pla[20])&(M1&T2);\nctl_reg_gp_sel_pla91pla20M1T2_2 = (pla[91]&pla[20])&(M1&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla91pla20M1T2_2,ctl_reg_gp_sel_pla91pla20M1T2_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla91pla20M1T2_3 = (pla[91]&pla[20])&(M1&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla91pla20M1T2_3,ctl_reg_gp_hilo_pla91pla20M1T2_3})&(2'b01);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[91]&pla[20])&(M1&T2);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[91]&pla[20])&(M1&T2);\nctl_flags_oe = ctl_flags_oe | (pla[91]&pla[20])&(M1&T2);\nctl_reg_gp_sel_pla91pla20M1T3_1 = (pla[91]&pla[20])&(M1&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla91pla20M1T3_1,ctl_reg_gp_sel_pla91pla20M1T3_1})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla91pla20M1T3_2 = (pla[91]&pla[20])&(M1&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla91pla20M1T3_2,ctl_reg_gp_hilo_pla91pla20M1T3_2})&(2'b11);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[91]&pla[20])&(M1&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[91]&pla[20])&(M1&T3);\nctl_flags_bus = ctl_flags_bus | (pla[91]&pla[20])&(M1&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[91]&pla[20])&(M1&T3)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[91]&pla[20])&(M1&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[91]&pla[20])&(M1&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[91]&pla[20])&(M1&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[91]&pla[20])&(M1&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[91]&pla[20])&(M1&T3);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[91]&pla[20])&(M1&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[91]&pla[20])&(M1&T3);\nctl_flags_cf_we = ctl_flags_cf_we | (pla[91]&pla[20])&(M1&T3);\nvalidPLA = validPLA | (pla[91]&pla[20])&(M1&T4);\nctl_reg_gp_sel_pla91pla20M1T4_2 = (pla[91]&pla[20])&(M1&T4);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla91pla20M1T4_2,ctl_reg_gp_sel_pla91pla20M1T4_2})&(`GP_REG_BC);\nctl_reg_gp_hilo_pla91pla20M1T4_3 = (pla[91]&pla[20])&(M1&T4);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla91pla20M1T4_3,ctl_reg_gp_hilo_pla91pla20M1T4_3})&(2'b10);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[91]&pla[20])&(M1&T4);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[91]&pla[20])&(M1&T4);\nctl_flags_alu = ctl_flags_alu | (pla[91]&pla[20])&(M1&T4);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[91]&pla[20])&(M1&T4)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_zero = ctl_alu_op2_sel_zero | (pla[91]&pla[20])&(M1&T4);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[91]&pla[20])&(M1&T4);\nctl_alu_op_low = ctl_alu_op_low | (pla[91]&pla[20])&(M1&T4);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[91]&pla[20])&(M1&T4)&(ctl_alu_op_low);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[91]&pla[20])&(M1&T4)&(ctl_alu_op_low);\nctl_alu_core_hf = ctl_alu_core_hf | (pla[91]&pla[20])&(M1&T4)&(~ctl_alu_op_low);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[91]&pla[20])&(M1&T4);\nctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[91]&pla[20])&(M1&T4);\nnextM = nextM | (pla[91]&pla[20])&(M1&T5);\nctl_mRead = ctl_mRead | (pla[91]&pla[20])&(M1&T5);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[91]&pla[20])&(M1&T5);\nctl_reg_gp_sel_pla91pla20M1T5_4 = (pla[91]&pla[20])&(M1&T5);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla91pla20M1T5_4,ctl_reg_gp_sel_pla91pla20M1T5_4})&(`GP_REG_BC);\nctl_reg_gp_hilo_pla91pla20M1T5_5 = (pla[91]&pla[20])&(M1&T5);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla91pla20M1T5_5,ctl_reg_gp_hilo_pla91pla20M1T5_5})&(2'b10);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[91]&pla[20])&(M1&T5);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[91]&pla[20])&(M1&T5);\nctl_flags_alu = ctl_flags_alu | (pla[91]&pla[20])&(M1&T5);\nctl_alu_oe = ctl_alu_oe | (pla[91]&pla[20])&(M1&T5);\nctl_alu_res_oe = ctl_alu_res_oe | (pla[91]&pla[20])&(M1&T5);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[91]&pla[20])&(M1&T5);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[91]&pla[20])&(M1&T5)&(ctl_alu_op_low);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[91]&pla[20])&(M1&T5)&(ctl_alu_op_low);\nctl_alu_core_hf = ctl_alu_core_hf | (pla[91]&pla[20])&(M1&T5)&(~ctl_alu_op_low);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[91]&pla[20])&(M1&T5);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[91]&pla[20])&(M1&T5);\nctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[91]&pla[20])&(M1&T5);\nfMRead = fMRead | (pla[91]&pla[20])&(M2&T1);\nctl_reg_gp_sel_pla91pla20M2T1_2 = (pla[91]&pla[20])&(M2&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla91pla20M2T1_2,ctl_reg_gp_sel_pla91pla20M2T1_2})&(`GP_REG_HL);\nctl_reg_gp_hilo_pla91pla20M2T1_3 = (pla[91]&pla[20])&(M2&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla91pla20M2T1_3,ctl_reg_gp_hilo_pla91pla20M2T1_3})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[91]&pla[20])&(M2&T1);\nctl_al_we = ctl_al_we | (pla[91]&pla[20])&(M2&T1);\nfMRead = fMRead | (pla[91]&pla[20])&(M2&T2);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[91]&pla[20])&(M2&T2);\nctl_reg_gp_sel_pla91pla20M2T2_3 = (pla[91]&pla[20])&(M2&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla91pla20M2T2_3,ctl_reg_gp_sel_pla91pla20M2T2_3})&(`GP_REG_HL);\nctl_reg_gp_hilo_pla91pla20M2T2_4 = (pla[91]&pla[20])&(M2&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla91pla20M2T2_4,ctl_reg_gp_hilo_pla91pla20M2T2_4})&(2'b11);\nctl_sw_4u = ctl_sw_4u | (pla[91]&pla[20])&(M2&T2);\nctl_inc_cy = ctl_inc_cy | (pla[91]&pla[20])&(M2&T2)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[91]&pla[20])&(M2&T2)&(op3);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[91]&pla[20])&(M2&T2);\nfMRead = fMRead | (pla[91]&pla[20])&(M2&T3);\nnextM = nextM | (pla[91]&pla[20])&(M2&T3);\nctl_iorw = ctl_iorw | (pla[91]&pla[20])&(M2&T3);\nctl_reg_gp_sel_pla91pla20M2T3_4 = (pla[91]&pla[20])&(M2&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla91pla20M2T3_4,ctl_reg_gp_sel_pla91pla20M2T3_4})&(`GP_REG_HL);\nctl_reg_gp_hilo_pla91pla20M2T3_5 = (pla[91]&pla[20])&(M2&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla91pla20M2T3_5,ctl_reg_gp_hilo_pla91pla20M2T3_5})&(2'b01);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[91]&pla[20])&(M2&T3);\nctl_sw_2d = ctl_sw_2d | (pla[91]&pla[20])&(M2&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[91]&pla[20])&(M2&T3)&(~ctl_alu_bs_oe);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[91]&pla[20])&(M2&T3);\nfIOWrite = fIOWrite | (pla[91]&pla[20])&(M3&T1);\nctl_reg_gp_sel_pla91pla20M3T1_2 = (pla[91]&pla[20])&(M3&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla91pla20M3T1_2,ctl_reg_gp_sel_pla91pla20M3T1_2})&(`GP_REG_BC);\nctl_reg_gp_hilo_pla91pla20M3T1_3 = (pla[91]&pla[20])&(M3&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla91pla20M3T1_3,ctl_reg_gp_hilo_pla91pla20M3T1_3})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[91]&pla[20])&(M3&T1);\nctl_al_we = ctl_al_we | (pla[91]&pla[20])&(M3&T1);\nfIOWrite = fIOWrite | (pla[91]&pla[20])&(M3&T2);\nctl_sw_2d = ctl_sw_2d | (pla[91]&pla[20])&(M3&T2);\nctl_sw_1d = ctl_sw_1d | (pla[91]&pla[20])&(M3&T2);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[91]&pla[20])&(M3&T2);\nctl_flags_alu = ctl_flags_alu | (pla[91]&pla[20])&(M3&T2);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[91]&pla[20])&(M3&T2)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[91]&pla[20])&(M3&T2);\nctl_alu_op_low = ctl_alu_op_low | (pla[91]&pla[20])&(M3&T2);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[91]&pla[20])&(M3&T2)&(ctl_alu_op_low);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[91]&pla[20])&(M3&T2)&(ctl_alu_op_low);\nctl_alu_core_hf = ctl_alu_core_hf | (pla[91]&pla[20])&(M3&T2)&(~ctl_alu_op_low);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[91]&pla[20])&(M3&T2);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[91]&pla[20])&(M3&T2);\nfIOWrite = fIOWrite | (pla[91]&pla[20])&(M3&T3);\nctl_flags_alu = ctl_flags_alu | (pla[91]&pla[20])&(M3&T3);\nctl_alu_oe = ctl_alu_oe | (pla[91]&pla[20])&(M3&T3);\nctl_alu_res_oe = ctl_alu_res_oe | (pla[91]&pla[20])&(M3&T3);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[91]&pla[20])&(M3&T3);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[91]&pla[20])&(M3&T3)&(ctl_alu_op_low);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[91]&pla[20])&(M3&T3)&(ctl_alu_op_low);\nctl_alu_core_hf = ctl_alu_core_hf | (pla[91]&pla[20])&(M3&T3)&(~ctl_alu_op_low);\nctl_flags_cf_we = ctl_flags_cf_we | (pla[91]&pla[20])&(M3&T3);\nfIOWrite = fIOWrite | (pla[91]&pla[20])&(M3&T4);\nnextM = nextM | (pla[91]&pla[20])&(M3&T4);\nsetM1 = setM1 | (pla[91]&pla[20])&(M3&T4)&(nonRep|flags_zf);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[91]&pla[20])&(M4&T1);\nctl_reg_sys_hilo_pla91pla20M4T1_2 = (pla[91]&pla[20])&(M4&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla91pla20M4T1_2,ctl_reg_sys_hilo_pla91pla20M4T1_2})&(2'b11);\nctl_al_we = ctl_al_we | (pla[91]&pla[20])&(M4&T1);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[91]&pla[20])&(M4&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[91]&pla[20])&(M4&T2);\nctl_reg_sys_hilo_pla91pla20M4T2_3 = (pla[91]&pla[20])&(M4&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla91pla20M4T2_3,ctl_reg_sys_hilo_pla91pla20M4T2_3})&(2'b11);\npc_inc_hold = pc_inc_hold | (pla[91]&pla[20])&(M4&T2)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (pla[91]&pla[20])&(M4&T2)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[91]&pla[20])&(M4&T2);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[91]&pla[20])&(M4&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[91]&pla[20])&(M4&T3);\nctl_reg_sys_hilo_pla91pla20M4T3_2 = (pla[91]&pla[20])&(M4&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla91pla20M4T3_2,ctl_reg_sys_hilo_pla91pla20M4T3_2})&(2'b11);\nctl_al_we = ctl_al_we | (pla[91]&pla[20])&(M4&T3);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[91]&pla[20])&(M4&T4);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[91]&pla[20])&(M4&T4);\nctl_reg_sys_hilo_pla91pla20M4T4_3 = (pla[91]&pla[20])&(M4&T4);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla91pla20M4T4_3,ctl_reg_sys_hilo_pla91pla20M4T4_3})&(2'b11);\npc_inc_hold = pc_inc_hold | (pla[91]&pla[20])&(M4&T4)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (pla[91]&pla[20])&(M4&T4)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[91]&pla[20])&(M4&T4);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[91]&pla[20])&(M4&T4);\nsetM1 = setM1 | (pla[91]&pla[20])&(M4&T5);\nvalidPLA = validPLA | (pla[29])&(M1&T4);\nnextM = nextM | (pla[29])&(M1&T4);\nctl_mRead = ctl_mRead | (pla[29])&(M1&T4);\nfMRead = fMRead | (pla[29])&(M2&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[29])&(M2&T1);\nctl_reg_sys_hilo_pla29M2T1_3 = (pla[29])&(M2&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla29M2T1_3,ctl_reg_sys_hilo_pla29M2T1_3})&(2'b11);\nctl_al_we = ctl_al_we | (pla[29])&(M2&T1);\nfMRead = fMRead | (pla[29])&(M2&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[29])&(M2&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[29])&(M2&T2);\nctl_reg_sys_hilo_pla29M2T2_4 = (pla[29])&(M2&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla29M2T2_4,ctl_reg_sys_hilo_pla29M2T2_4})&(2'b11);\npc_inc_hold = pc_inc_hold | (pla[29])&(M2&T2)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (pla[29])&(M2&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[29])&(M2&T2);\nfMRead = fMRead | (pla[29])&(M2&T3);\nnextM = nextM | (pla[29])&(M2&T3);\nctl_mRead = ctl_mRead | (pla[29])&(M2&T3);\nctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (pla[29])&(M2&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[29])&(M2&T3);\nctl_reg_sys_hilo_pla29M2T3_6 = (pla[29])&(M2&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla29M2T3_6,ctl_reg_sys_hilo_pla29M2T3_6})&({ctl_reg_sys_hilo[1],1'b1});\nctl_reg_in_lo = ctl_reg_in_lo | (pla[29])&(M2&T3);\nctl_sw_2d = ctl_sw_2d | (pla[29])&(M2&T3);\nctl_sw_1d = ctl_sw_1d | (pla[29])&(M2&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[29])&(M2&T3);\nfMRead = fMRead | (pla[29])&(M3&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[29])&(M3&T1);\nctl_reg_sys_hilo_pla29M3T1_3 = (pla[29])&(M3&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla29M3T1_3,ctl_reg_sys_hilo_pla29M3T1_3})&(2'b11);\nctl_al_we = ctl_al_we | (pla[29])&(M3&T1);\nfMRead = fMRead | (pla[29])&(M3&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[29])&(M3&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[29])&(M3&T2);\nctl_reg_sys_hilo_pla29M3T2_4 = (pla[29])&(M3&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla29M3T2_4,ctl_reg_sys_hilo_pla29M3T2_4})&(2'b11);\npc_inc_hold = pc_inc_hold | (pla[29])&(M3&T2)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (pla[29])&(M3&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[29])&(M3&T2);\nfMRead = fMRead | (pla[29])&(M3&T3);\nsetM1 = setM1 | (pla[29])&(M3&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[29])&(M3&T3);\nctl_reg_sys_hilo_pla29M3T3_4 = (pla[29])&(M3&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla29M3T3_4,ctl_reg_sys_hilo_pla29M3T3_4})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[29])&(M3&T3);\nctl_al_we = ctl_al_we | (pla[29])&(M3&T3);\nctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (pla[29])&(M3&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[29])&(M3&T3);\nctl_reg_sys_hilo_pla29M3T3_9 = (pla[29])&(M3&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla29M3T3_9,ctl_reg_sys_hilo_pla29M3T3_9})&({1'b1,ctl_reg_sys_hilo[0]});\nctl_reg_in_hi = ctl_reg_in_hi | (pla[29])&(M3&T3);\nctl_sw_2d = ctl_sw_2d | (pla[29])&(M3&T3);\nctl_sw_1d = ctl_sw_1d | (pla[29])&(M3&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[29])&(M3&T3);\nctl_reg_not_pc = ctl_reg_not_pc | (pla[29])&(M3&T3);\nctl_reg_gp_sel_pla43M1T3_1 = (pla[43])&(M1&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla43M1T3_1,ctl_reg_gp_sel_pla43M1T3_1})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla43M1T3_2 = (pla[43])&(M1&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla43M1T3_2,ctl_reg_gp_hilo_pla43M1T3_2})&(2'b11);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[43])&(M1&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[43])&(M1&T3);\nctl_flags_bus = ctl_flags_bus | (pla[43])&(M1&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[43])&(M1&T3)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[43])&(M1&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[43])&(M1&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[43])&(M1&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[43])&(M1&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[43])&(M1&T3);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[43])&(M1&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[43])&(M1&T3);\nctl_flags_cf_we = ctl_flags_cf_we | (pla[43])&(M1&T3);\nvalidPLA = validPLA | (pla[43])&(M1&T4);\nnextM = nextM | (pla[43])&(M1&T4);\nctl_mRead = ctl_mRead | (pla[43])&(M1&T4);\nfMRead = fMRead | (pla[43])&(M2&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[43])&(M2&T1);\nctl_reg_sys_hilo_pla43M2T1_3 = (pla[43])&(M2&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla43M2T1_3,ctl_reg_sys_hilo_pla43M2T1_3})&(2'b11);\nctl_al_we = ctl_al_we | (pla[43])&(M2&T1);\nfMRead = fMRead | (pla[43])&(M2&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[43])&(M2&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[43])&(M2&T2);\nctl_reg_sys_hilo_pla43M2T2_4 = (pla[43])&(M2&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla43M2T2_4,ctl_reg_sys_hilo_pla43M2T2_4})&(2'b11);\npc_inc_hold = pc_inc_hold | (pla[43])&(M2&T2)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (pla[43])&(M2&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[43])&(M2&T2);\nfMRead = fMRead | (pla[43])&(M2&T3);\nnextM = nextM | (pla[43])&(M2&T3);\nctl_mRead = ctl_mRead | (pla[43])&(M2&T3);\nctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (pla[43])&(M2&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[43])&(M2&T3);\nctl_reg_sys_hilo_pla43M2T3_6 = (pla[43])&(M2&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla43M2T3_6,ctl_reg_sys_hilo_pla43M2T3_6})&({ctl_reg_sys_hilo[1],1'b1});\nctl_reg_in_lo = ctl_reg_in_lo | (pla[43])&(M2&T3);\nctl_sw_2d = ctl_sw_2d | (pla[43])&(M2&T3);\nctl_sw_1d = ctl_sw_1d | (pla[43])&(M2&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[43])&(M2&T3);\nfMRead = fMRead | (pla[43])&(M3&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[43])&(M3&T1);\nctl_reg_sys_hilo_pla43M3T1_3 = (pla[43])&(M3&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla43M3T1_3,ctl_reg_sys_hilo_pla43M3T1_3})&(2'b11);\nctl_al_we = ctl_al_we | (pla[43])&(M3&T1);\nfMRead = fMRead | (pla[43])&(M3&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[43])&(M3&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[43])&(M3&T2);\nctl_reg_sys_hilo_pla43M3T2_4 = (pla[43])&(M3&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla43M3T2_4,ctl_reg_sys_hilo_pla43M3T2_4})&(2'b11);\npc_inc_hold = pc_inc_hold | (pla[43])&(M3&T2)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (pla[43])&(M3&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[43])&(M3&T2);\nfMRead = fMRead | (pla[43])&(M3&T3);\nsetM1 = setM1 | (pla[43])&(M3&T3);\nctl_reg_not_pc = ctl_reg_not_pc | (pla[43])&(M3&T3)&(flags_cond_true);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[43])&(M3&T3)&(flags_cond_true);\nctl_reg_sys_hilo_pla43M3T3_5 = (pla[43])&(M3&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla43M3T3_5,ctl_reg_sys_hilo_pla43M3T3_5})&({flags_cond_true,flags_cond_true});\nctl_sw_4d = ctl_sw_4d | (pla[43])&(M3&T3)&(flags_cond_true);\nctl_al_we = ctl_al_we | (pla[43])&(M3&T3);\nctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (pla[43])&(M3&T3)&(flags_cond_true);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[43])&(M3&T3)&(flags_cond_true);\nctl_reg_sys_hilo_pla43M3T3_10 = (pla[43])&(M3&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla43M3T3_10,ctl_reg_sys_hilo_pla43M3T3_10})&({1'b1,ctl_reg_sys_hilo[0]});\nctl_reg_in_hi = ctl_reg_in_hi | (pla[43])&(M3&T3);\nctl_sw_2d = ctl_sw_2d | (pla[43])&(M3&T3);\nctl_sw_1d = ctl_sw_1d | (pla[43])&(M3&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[43])&(M3&T3);\nctl_reg_gp_sel_pla47M1T3_1 = (pla[47])&(M1&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla47M1T3_1,ctl_reg_gp_sel_pla47M1T3_1})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla47M1T3_2 = (pla[47])&(M1&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla47M1T3_2,ctl_reg_gp_hilo_pla47M1T3_2})&(2'b11);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[47])&(M1&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[47])&(M1&T3);\nctl_flags_bus = ctl_flags_bus | (pla[47])&(M1&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[47])&(M1&T3)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[47])&(M1&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[47])&(M1&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[47])&(M1&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[47])&(M1&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[47])&(M1&T3);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[47])&(M1&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[47])&(M1&T3);\nctl_flags_cf_we = ctl_flags_cf_we | (pla[47])&(M1&T3);\nvalidPLA = validPLA | (pla[47])&(M1&T4);\nnextM = nextM | (pla[47])&(M1&T4);\nctl_mRead = ctl_mRead | (pla[47])&(M1&T4);\nfMRead = fMRead | (pla[47])&(M2&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[47])&(M2&T1);\nctl_reg_sys_hilo_pla47M2T1_3 = (pla[47])&(M2&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla47M2T1_3,ctl_reg_sys_hilo_pla47M2T1_3})&(2'b11);\nctl_al_we = ctl_al_we | (pla[47])&(M2&T1);\nfMRead = fMRead | (pla[47])&(M2&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[47])&(M2&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[47])&(M2&T2);\nctl_reg_sys_hilo_pla47M2T2_4 = (pla[47])&(M2&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla47M2T2_4,ctl_reg_sys_hilo_pla47M2T2_4})&(2'b11);\npc_inc_hold = pc_inc_hold | (pla[47])&(M2&T2)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (pla[47])&(M2&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[47])&(M2&T2);\nfMRead = fMRead | (pla[47])&(M2&T3);\nnextM = nextM | (pla[47])&(M2&T3);\nctl_sw_2d = ctl_sw_2d | (pla[47])&(M3&T1);\nctl_sw_1d = ctl_sw_1d | (pla[47])&(M3&T1);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[47])&(M3&T1);\nctl_flags_alu = ctl_flags_alu | (pla[47])&(M3&T1);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[47])&(M3&T1)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[47])&(M3&T1);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[47])&(M3&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[47])&(M3&T2);\nctl_reg_sys_hilo_pla47M3T2_2 = (pla[47])&(M3&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla47M3T2_2,ctl_reg_sys_hilo_pla47M3T2_2})&(2'b01);\nctl_sw_4u = ctl_sw_4u | (pla[47])&(M3&T2);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[47])&(M3&T2);\nctl_sw_2d = ctl_sw_2d | (pla[47])&(M3&T2);\nctl_flags_alu = ctl_flags_alu | (pla[47])&(M3&T2);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[47])&(M3&T2)&(~ctl_alu_bs_oe);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[47])&(M3&T2);\nctl_alu_op_low = ctl_alu_op_low | (pla[47])&(M3&T2);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[47])&(M3&T2)&(ctl_alu_op_low);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[47])&(M3&T2)&(ctl_alu_op_low);\nctl_alu_core_hf = ctl_alu_core_hf | (pla[47])&(M3&T2)&(~ctl_alu_op_low);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[47])&(M3&T2);\nctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (pla[47])&(M3&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[47])&(M3&T3);\nctl_reg_sys_hilo_pla47M3T3_3 = (pla[47])&(M3&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla47M3T3_3,ctl_reg_sys_hilo_pla47M3T3_3})&({ctl_reg_sys_hilo[1],1'b1});\nctl_reg_in_lo = ctl_reg_in_lo | (pla[47])&(M3&T3);\nctl_sw_2u = ctl_sw_2u | (pla[47])&(M3&T3);\nctl_flags_alu = ctl_flags_alu | (pla[47])&(M3&T3);\nctl_alu_oe = ctl_alu_oe | (pla[47])&(M3&T3);\nctl_alu_res_oe = ctl_alu_res_oe | (pla[47])&(M3&T3);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[47])&(M3&T3);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[47])&(M3&T3)&(ctl_alu_op_low);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[47])&(M3&T3)&(ctl_alu_op_low);\nctl_alu_core_hf = ctl_alu_core_hf | (pla[47])&(M3&T3)&(~ctl_alu_op_low);\nctl_flags_cf_we = ctl_flags_cf_we | (pla[47])&(M3&T3);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[47])&(M3&T4);\nctl_reg_sys_hilo_pla47M3T4_2 = (pla[47])&(M3&T4);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla47M3T4_2,ctl_reg_sys_hilo_pla47M3T4_2})&(2'b10);\nctl_sw_4u = ctl_sw_4u | (pla[47])&(M3&T4);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[47])&(M3&T4);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[47])&(M3&T4);\nctl_flags_alu = ctl_flags_alu | (pla[47])&(M3&T4);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[47])&(M3&T4)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_zero = ctl_alu_op2_sel_zero | (pla[47])&(M3&T4);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[47])&(M3&T4);\nctl_alu_op_low = ctl_alu_op_low | (pla[47])&(M3&T4);\nctl_alu_core_hf = ctl_alu_core_hf | (pla[47])&(M3&T4)&(~ctl_alu_op_low);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[47])&(M3&T4);\nctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[47])&(M3&T4)&(flags_sf);\nsetM1 = setM1 | (pla[47])&(M3&T5);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[47])&(M3&T5);\nctl_reg_sys_hilo_pla47M3T5_3 = (pla[47])&(M3&T5);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla47M3T5_3,ctl_reg_sys_hilo_pla47M3T5_3})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[47])&(M3&T5);\nctl_al_we = ctl_al_we | (pla[47])&(M3&T5);\nctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (pla[47])&(M3&T5);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[47])&(M3&T5);\nctl_reg_sys_hilo_pla47M3T5_8 = (pla[47])&(M3&T5);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla47M3T5_8,ctl_reg_sys_hilo_pla47M3T5_8})&({1'b1,ctl_reg_sys_hilo[0]});\nctl_reg_in_hi = ctl_reg_in_hi | (pla[47])&(M3&T5);\nctl_flags_alu = ctl_flags_alu | (pla[47])&(M3&T5);\nctl_alu_oe = ctl_alu_oe | (pla[47])&(M3&T5);\nctl_alu_res_oe = ctl_alu_res_oe | (pla[47])&(M3&T5);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[47])&(M3&T5);\nctl_alu_core_hf = ctl_alu_core_hf | (pla[47])&(M3&T5)&(~ctl_alu_op_low);\nctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[47])&(M3&T5)&(flags_sf);\nctl_reg_not_pc = ctl_reg_not_pc | (pla[47])&(M3&T5);\nctl_reg_gp_sel_pla48M1T3_1 = (pla[48])&(M1&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla48M1T3_1,ctl_reg_gp_sel_pla48M1T3_1})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla48M1T3_2 = (pla[48])&(M1&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla48M1T3_2,ctl_reg_gp_hilo_pla48M1T3_2})&(2'b11);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[48])&(M1&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[48])&(M1&T3);\nctl_flags_bus = ctl_flags_bus | (pla[48])&(M1&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[48])&(M1&T3)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[48])&(M1&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[48])&(M1&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[48])&(M1&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[48])&(M1&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[48])&(M1&T3);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[48])&(M1&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[48])&(M1&T3);\nctl_flags_cf_we = ctl_flags_cf_we | (pla[48])&(M1&T3);\nvalidPLA = validPLA | (pla[48])&(M1&T4);\nnextM = nextM | (pla[48])&(M1&T4);\nctl_mRead = ctl_mRead | (pla[48])&(M1&T4);\nctl_cond_short = ctl_cond_short | (pla[48])&(M1&T4);\nfMRead = fMRead | (pla[48])&(M2&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[48])&(M2&T1);\nctl_reg_sys_hilo_pla48M2T1_3 = (pla[48])&(M2&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla48M2T1_3,ctl_reg_sys_hilo_pla48M2T1_3})&(2'b11);\nctl_al_we = ctl_al_we | (pla[48])&(M2&T1);\nfMRead = fMRead | (pla[48])&(M2&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[48])&(M2&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[48])&(M2&T2);\nctl_reg_sys_hilo_pla48M2T2_4 = (pla[48])&(M2&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla48M2T2_4,ctl_reg_sys_hilo_pla48M2T2_4})&(2'b11);\npc_inc_hold = pc_inc_hold | (pla[48])&(M2&T2)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (pla[48])&(M2&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[48])&(M2&T2);\nfMRead = fMRead | (pla[48])&(M2&T3);\nnextM = nextM | (pla[48])&(M2&T3);\nsetM1 = setM1 | (pla[48])&(M2&T3)&(~flags_cond_true);\nctl_sw_2d = ctl_sw_2d | (pla[48])&(M3&T1);\nctl_sw_1d = ctl_sw_1d | (pla[48])&(M3&T1);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[48])&(M3&T1);\nctl_flags_alu = ctl_flags_alu | (pla[48])&(M3&T1);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[48])&(M3&T1)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[48])&(M3&T1);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[48])&(M3&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[48])&(M3&T2);\nctl_reg_sys_hilo_pla48M3T2_2 = (pla[48])&(M3&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla48M3T2_2,ctl_reg_sys_hilo_pla48M3T2_2})&(2'b01);\nctl_sw_4u = ctl_sw_4u | (pla[48])&(M3&T2);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[48])&(M3&T2);\nctl_sw_2d = ctl_sw_2d | (pla[48])&(M3&T2);\nctl_flags_alu = ctl_flags_alu | (pla[48])&(M3&T2);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[48])&(M3&T2)&(~ctl_alu_bs_oe);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[48])&(M3&T2);\nctl_alu_op_low = ctl_alu_op_low | (pla[48])&(M3&T2);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[48])&(M3&T2)&(ctl_alu_op_low);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[48])&(M3&T2)&(ctl_alu_op_low);\nctl_alu_core_hf = ctl_alu_core_hf | (pla[48])&(M3&T2)&(~ctl_alu_op_low);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[48])&(M3&T2);\nctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (pla[48])&(M3&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[48])&(M3&T3);\nctl_reg_sys_hilo_pla48M3T3_3 = (pla[48])&(M3&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla48M3T3_3,ctl_reg_sys_hilo_pla48M3T3_3})&({ctl_reg_sys_hilo[1],1'b1});\nctl_reg_in_lo = ctl_reg_in_lo | (pla[48])&(M3&T3);\nctl_sw_2u = ctl_sw_2u | (pla[48])&(M3&T3);\nctl_flags_alu = ctl_flags_alu | (pla[48])&(M3&T3);\nctl_alu_oe = ctl_alu_oe | (pla[48])&(M3&T3);\nctl_alu_res_oe = ctl_alu_res_oe | (pla[48])&(M3&T3);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[48])&(M3&T3);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[48])&(M3&T3)&(ctl_alu_op_low);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[48])&(M3&T3)&(ctl_alu_op_low);\nctl_alu_core_hf = ctl_alu_core_hf | (pla[48])&(M3&T3)&(~ctl_alu_op_low);\nctl_flags_cf_we = ctl_flags_cf_we | (pla[48])&(M3&T3);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[48])&(M3&T4);\nctl_reg_sys_hilo_pla48M3T4_2 = (pla[48])&(M3&T4);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla48M3T4_2,ctl_reg_sys_hilo_pla48M3T4_2})&(2'b10);\nctl_sw_4u = ctl_sw_4u | (pla[48])&(M3&T4);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[48])&(M3&T4);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[48])&(M3&T4);\nctl_flags_alu = ctl_flags_alu | (pla[48])&(M3&T4);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[48])&(M3&T4)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_zero = ctl_alu_op2_sel_zero | (pla[48])&(M3&T4);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[48])&(M3&T4);\nctl_alu_op_low = ctl_alu_op_low | (pla[48])&(M3&T4);\nctl_alu_core_hf = ctl_alu_core_hf | (pla[48])&(M3&T4)&(~ctl_alu_op_low);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[48])&(M3&T4);\nctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[48])&(M3&T4)&(flags_sf);\nsetM1 = setM1 | (pla[48])&(M3&T5);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[48])&(M3&T5);\nctl_reg_sys_hilo_pla48M3T5_3 = (pla[48])&(M3&T5);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla48M3T5_3,ctl_reg_sys_hilo_pla48M3T5_3})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[48])&(M3&T5);\nctl_al_we = ctl_al_we | (pla[48])&(M3&T5);\nctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (pla[48])&(M3&T5);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[48])&(M3&T5);\nctl_reg_sys_hilo_pla48M3T5_8 = (pla[48])&(M3&T5);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla48M3T5_8,ctl_reg_sys_hilo_pla48M3T5_8})&({1'b1,ctl_reg_sys_hilo[0]});\nctl_reg_in_hi = ctl_reg_in_hi | (pla[48])&(M3&T5);\nctl_flags_alu = ctl_flags_alu | (pla[48])&(M3&T5);\nctl_alu_oe = ctl_alu_oe | (pla[48])&(M3&T5);\nctl_alu_res_oe = ctl_alu_res_oe | (pla[48])&(M3&T5);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[48])&(M3&T5);\nctl_alu_core_hf = ctl_alu_core_hf | (pla[48])&(M3&T5)&(~ctl_alu_op_low);\nctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[48])&(M3&T5)&(flags_sf);\nctl_reg_not_pc = ctl_reg_not_pc | (pla[48])&(M3&T5);\nvalidPLA = validPLA | (pla[6])&(M1&T4);\nsetM1 = setM1 | (pla[6])&(M1&T4);\nctl_reg_gp_sel_pla6M1T4_3 = (pla[6])&(M1&T4);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla6M1T4_3,ctl_reg_gp_sel_pla6M1T4_3})&(`GP_REG_HL);\nctl_reg_gp_hilo_pla6M1T4_4 = (pla[6])&(M1&T4);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla6M1T4_4,ctl_reg_gp_hilo_pla6M1T4_4})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[6])&(M1&T4);\nctl_al_we = ctl_al_we | (pla[6])&(M1&T4);\nctl_reg_not_pc = ctl_reg_not_pc | (pla[6])&(M1&T4);\nctl_reg_gp_sel_pla26M1T3_1 = (pla[26])&(M1&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla26M1T3_1,ctl_reg_gp_sel_pla26M1T3_1})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla26M1T3_2 = (pla[26])&(M1&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla26M1T3_2,ctl_reg_gp_hilo_pla26M1T3_2})&(2'b11);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[26])&(M1&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[26])&(M1&T3);\nctl_flags_bus = ctl_flags_bus | (pla[26])&(M1&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[26])&(M1&T3)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[26])&(M1&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[26])&(M1&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[26])&(M1&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[26])&(M1&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[26])&(M1&T3);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[26])&(M1&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[26])&(M1&T3);\nctl_flags_cf_we = ctl_flags_cf_we | (pla[26])&(M1&T3);\nvalidPLA = validPLA | (pla[26])&(M1&T4);\nctl_reg_gp_sel_pla26M1T4_2 = (pla[26])&(M1&T4);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla26M1T4_2,ctl_reg_gp_sel_pla26M1T4_2})&(`GP_REG_BC);\nctl_reg_gp_hilo_pla26M1T4_3 = (pla[26])&(M1&T4);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla26M1T4_3,ctl_reg_gp_hilo_pla26M1T4_3})&(2'b10);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[26])&(M1&T4);\nctl_flags_alu = ctl_flags_alu | (pla[26])&(M1&T4);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[26])&(M1&T4)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_zero = ctl_alu_op2_sel_zero | (pla[26])&(M1&T4);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[26])&(M1&T4);\nctl_alu_op_low = ctl_alu_op_low | (pla[26])&(M1&T4);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[26])&(M1&T4)&(ctl_alu_op_low);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[26])&(M1&T4)&(ctl_alu_op_low);\nctl_alu_core_hf = ctl_alu_core_hf | (pla[26])&(M1&T4)&(~ctl_alu_op_low);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[26])&(M1&T4);\nctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[26])&(M1&T4);\nnextM = nextM | (pla[26])&(M1&T5);\nctl_mRead = ctl_mRead | (pla[26])&(M1&T5);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[26])&(M1&T5);\nctl_reg_gp_sel_pla26M1T5_4 = (pla[26])&(M1&T5);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla26M1T5_4,ctl_reg_gp_sel_pla26M1T5_4})&(`GP_REG_BC);\nctl_reg_gp_hilo_pla26M1T5_5 = (pla[26])&(M1&T5);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla26M1T5_5,ctl_reg_gp_hilo_pla26M1T5_5})&(2'b10);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[26])&(M1&T5);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[26])&(M1&T5);\nctl_flags_alu = ctl_flags_alu | (pla[26])&(M1&T5);\nctl_alu_oe = ctl_alu_oe | (pla[26])&(M1&T5);\nctl_alu_res_oe = ctl_alu_res_oe | (pla[26])&(M1&T5);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[26])&(M1&T5);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[26])&(M1&T5)&(ctl_alu_op_low);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[26])&(M1&T5)&(ctl_alu_op_low);\nctl_alu_core_hf = ctl_alu_core_hf | (pla[26])&(M1&T5)&(~ctl_alu_op_low);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[26])&(M1&T5);\nctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[26])&(M1&T5);\nfMRead = fMRead | (pla[26])&(M2&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[26])&(M2&T1);\nctl_reg_sys_hilo_pla26M2T1_3 = (pla[26])&(M2&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla26M2T1_3,ctl_reg_sys_hilo_pla26M2T1_3})&(2'b11);\nctl_al_we = ctl_al_we | (pla[26])&(M2&T1);\nfMRead = fMRead | (pla[26])&(M2&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[26])&(M2&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[26])&(M2&T2);\nctl_reg_sys_hilo_pla26M2T2_4 = (pla[26])&(M2&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla26M2T2_4,ctl_reg_sys_hilo_pla26M2T2_4})&(2'b11);\npc_inc_hold = pc_inc_hold | (pla[26])&(M2&T2)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (pla[26])&(M2&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[26])&(M2&T2);\nfMRead = fMRead | (pla[26])&(M2&T3);\nnextM = nextM | (pla[26])&(M2&T3);\nsetM1 = setM1 | (pla[26])&(M2&T3)&(flags_zf);\nctl_sw_2d = ctl_sw_2d | (pla[26])&(M3&T1);\nctl_sw_1d = ctl_sw_1d | (pla[26])&(M3&T1);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[26])&(M3&T1);\nctl_flags_alu = ctl_flags_alu | (pla[26])&(M3&T1);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[26])&(M3&T1)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[26])&(M3&T1);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[26])&(M3&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[26])&(M3&T2);\nctl_reg_sys_hilo_pla26M3T2_2 = (pla[26])&(M3&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla26M3T2_2,ctl_reg_sys_hilo_pla26M3T2_2})&(2'b01);\nctl_sw_4u = ctl_sw_4u | (pla[26])&(M3&T2);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[26])&(M3&T2);\nctl_sw_2d = ctl_sw_2d | (pla[26])&(M3&T2);\nctl_flags_alu = ctl_flags_alu | (pla[26])&(M3&T2);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[26])&(M3&T2)&(~ctl_alu_bs_oe);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[26])&(M3&T2);\nctl_alu_op_low = ctl_alu_op_low | (pla[26])&(M3&T2);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[26])&(M3&T2)&(ctl_alu_op_low);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[26])&(M3&T2)&(ctl_alu_op_low);\nctl_alu_core_hf = ctl_alu_core_hf | (pla[26])&(M3&T2)&(~ctl_alu_op_low);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[26])&(M3&T2);\nctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (pla[26])&(M3&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[26])&(M3&T3);\nctl_reg_sys_hilo_pla26M3T3_3 = (pla[26])&(M3&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla26M3T3_3,ctl_reg_sys_hilo_pla26M3T3_3})&({ctl_reg_sys_hilo[1],1'b1});\nctl_reg_in_lo = ctl_reg_in_lo | (pla[26])&(M3&T3);\nctl_sw_2u = ctl_sw_2u | (pla[26])&(M3&T3);\nctl_flags_alu = ctl_flags_alu | (pla[26])&(M3&T3);\nctl_alu_oe = ctl_alu_oe | (pla[26])&(M3&T3);\nctl_alu_res_oe = ctl_alu_res_oe | (pla[26])&(M3&T3);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[26])&(M3&T3);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[26])&(M3&T3)&(ctl_alu_op_low);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[26])&(M3&T3)&(ctl_alu_op_low);\nctl_alu_core_hf = ctl_alu_core_hf | (pla[26])&(M3&T3)&(~ctl_alu_op_low);\nctl_flags_cf_we = ctl_flags_cf_we | (pla[26])&(M3&T3);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[26])&(M3&T4);\nctl_reg_sys_hilo_pla26M3T4_2 = (pla[26])&(M3&T4);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla26M3T4_2,ctl_reg_sys_hilo_pla26M3T4_2})&(2'b10);\nctl_sw_4u = ctl_sw_4u | (pla[26])&(M3&T4);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[26])&(M3&T4);\nctl_flags_alu = ctl_flags_alu | (pla[26])&(M3&T4);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[26])&(M3&T4)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_zero = ctl_alu_op2_sel_zero | (pla[26])&(M3&T4);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[26])&(M3&T4);\nctl_alu_op_low = ctl_alu_op_low | (pla[26])&(M3&T4);\nctl_alu_core_hf = ctl_alu_core_hf | (pla[26])&(M3&T4)&(~ctl_alu_op_low);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[26])&(M3&T4);\nctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[26])&(M3&T4)&(flags_sf);\nsetM1 = setM1 | (pla[26])&(M3&T5);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[26])&(M3&T5);\nctl_reg_sys_hilo_pla26M3T5_3 = (pla[26])&(M3&T5);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla26M3T5_3,ctl_reg_sys_hilo_pla26M3T5_3})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[26])&(M3&T5);\nctl_al_we = ctl_al_we | (pla[26])&(M3&T5);\nctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (pla[26])&(M3&T5);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[26])&(M3&T5);\nctl_reg_sys_hilo_pla26M3T5_8 = (pla[26])&(M3&T5);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla26M3T5_8,ctl_reg_sys_hilo_pla26M3T5_8})&({1'b1,ctl_reg_sys_hilo[0]});\nctl_reg_in_hi = ctl_reg_in_hi | (pla[26])&(M3&T5);\nctl_flags_alu = ctl_flags_alu | (pla[26])&(M3&T5);\nctl_alu_oe = ctl_alu_oe | (pla[26])&(M3&T5);\nctl_alu_res_oe = ctl_alu_res_oe | (pla[26])&(M3&T5);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (pla[26])&(M3&T5);\nctl_alu_core_hf = ctl_alu_core_hf | (pla[26])&(M3&T5)&(~ctl_alu_op_low);\nctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[26])&(M3&T5)&(flags_sf);\nctl_reg_not_pc = ctl_reg_not_pc | (pla[26])&(M3&T5);\nvalidPLA = validPLA | (pla[24])&(M1&T4);\nnextM = nextM | (pla[24])&(M1&T4);\nctl_mRead = ctl_mRead | (pla[24])&(M1&T4);\nfMRead = fMRead | (pla[24])&(M2&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[24])&(M2&T1);\nctl_reg_sys_hilo_pla24M2T1_3 = (pla[24])&(M2&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla24M2T1_3,ctl_reg_sys_hilo_pla24M2T1_3})&(2'b11);\nctl_al_we = ctl_al_we | (pla[24])&(M2&T1);\nfMRead = fMRead | (pla[24])&(M2&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[24])&(M2&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[24])&(M2&T2);\nctl_reg_sys_hilo_pla24M2T2_4 = (pla[24])&(M2&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla24M2T2_4,ctl_reg_sys_hilo_pla24M2T2_4})&(2'b11);\npc_inc_hold = pc_inc_hold | (pla[24])&(M2&T2)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (pla[24])&(M2&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[24])&(M2&T2);\nfMRead = fMRead | (pla[24])&(M2&T3);\nnextM = nextM | (pla[24])&(M2&T3);\nctl_mRead = ctl_mRead | (pla[24])&(M2&T3);\nctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (pla[24])&(M2&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[24])&(M2&T3);\nctl_reg_sys_hilo_pla24M2T3_6 = (pla[24])&(M2&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla24M2T3_6,ctl_reg_sys_hilo_pla24M2T3_6})&({ctl_reg_sys_hilo[1],1'b1});\nctl_reg_in_lo = ctl_reg_in_lo | (pla[24])&(M2&T3);\nctl_sw_2d = ctl_sw_2d | (pla[24])&(M2&T3);\nctl_sw_1d = ctl_sw_1d | (pla[24])&(M2&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[24])&(M2&T3);\nfMRead = fMRead | (pla[24])&(M3&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[24])&(M3&T1);\nctl_reg_sys_hilo_pla24M3T1_3 = (pla[24])&(M3&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla24M3T1_3,ctl_reg_sys_hilo_pla24M3T1_3})&(2'b11);\nctl_al_we = ctl_al_we | (pla[24])&(M3&T1);\nfMRead = fMRead | (pla[24])&(M3&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[24])&(M3&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[24])&(M3&T2);\nctl_reg_sys_hilo_pla24M3T2_4 = (pla[24])&(M3&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla24M3T2_4,ctl_reg_sys_hilo_pla24M3T2_4})&(2'b11);\npc_inc_hold = pc_inc_hold | (pla[24])&(M3&T2)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (pla[24])&(M3&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[24])&(M3&T2);\nfMRead = fMRead | (pla[24])&(M3&T3);\nctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (pla[24])&(M3&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[24])&(M3&T3);\nctl_reg_sys_hilo_pla24M3T3_4 = (pla[24])&(M3&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla24M3T3_4,ctl_reg_sys_hilo_pla24M3T3_4})&({1'b1,ctl_reg_sys_hilo[0]});\nctl_reg_in_hi = ctl_reg_in_hi | (pla[24])&(M3&T3);\nctl_sw_2d = ctl_sw_2d | (pla[24])&(M3&T3);\nctl_sw_1d = ctl_sw_1d | (pla[24])&(M3&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[24])&(M3&T3);\nnextM = nextM | (pla[24])&(M3&T4);\nctl_mWrite = ctl_mWrite | (pla[24])&(M3&T4);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[24])&(M3&T4);\nctl_reg_gp_sel_pla24M3T4_4 = (pla[24])&(M3&T4);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla24M3T4_4,ctl_reg_gp_sel_pla24M3T4_4})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla24M3T4_5 = (pla[24])&(M3&T4);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla24M3T4_5,ctl_reg_gp_hilo_pla24M3T4_5})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[24])&(M3&T4);\nctl_inc_cy = ctl_inc_cy | (pla[24])&(M3&T4)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[24])&(M3&T4);\nctl_al_we = ctl_al_we | (pla[24])&(M3&T4);\nfMWrite = fMWrite | (pla[24])&(M4&T1);\nctl_inc_cy = ctl_inc_cy | (pla[24])&(M4&T1)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[24])&(M4&T1);\nctl_apin_mux = ctl_apin_mux | (pla[24])&(M4&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[24])&(M4&T1);\nctl_reg_sys_hilo_pla24M4T1_6 = (pla[24])&(M4&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla24M4T1_6,ctl_reg_sys_hilo_pla24M4T1_6})&(2'b10);\nctl_sw_4u = ctl_sw_4u | (pla[24])&(M4&T1);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[24])&(M4&T1);\nctl_sw_2u = ctl_sw_2u | (pla[24])&(M4&T1);\nctl_sw_1u = ctl_sw_1u | (pla[24])&(M4&T1);\nctl_bus_db_we = ctl_bus_db_we | (pla[24])&(M4&T1);\nfMWrite = fMWrite | (pla[24])&(M4&T2);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[24])&(M4&T2);\nctl_reg_gp_sel_pla24M4T2_3 = (pla[24])&(M4&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla24M4T2_3,ctl_reg_gp_sel_pla24M4T2_3})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla24M4T2_4 = (pla[24])&(M4&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla24M4T2_4,ctl_reg_gp_hilo_pla24M4T2_4})&(2'b11);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[24])&(M4&T2);\nctl_sw_4u = ctl_sw_4u | (pla[24])&(M4&T2);\nctl_inc_cy = ctl_inc_cy | (pla[24])&(M4&T2)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[24])&(M4&T2);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[24])&(M4&T2);\nfMWrite = fMWrite | (pla[24])&(M4&T3);\nnextM = nextM | (pla[24])&(M4&T3);\nctl_mWrite = ctl_mWrite | (pla[24])&(M4&T3);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[24])&(M4&T3);\nctl_reg_gp_sel_pla24M4T3_5 = (pla[24])&(M4&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla24M4T3_5,ctl_reg_gp_sel_pla24M4T3_5})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla24M4T3_6 = (pla[24])&(M4&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla24M4T3_6,ctl_reg_gp_hilo_pla24M4T3_6})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[24])&(M4&T3);\nctl_inc_cy = ctl_inc_cy | (pla[24])&(M4&T3)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[24])&(M4&T3);\nctl_al_we = ctl_al_we | (pla[24])&(M4&T3);\nfMWrite = fMWrite | (pla[24])&(M5&T1);\nctl_inc_cy = ctl_inc_cy | (pla[24])&(M5&T1)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[24])&(M5&T1);\nctl_apin_mux = ctl_apin_mux | (pla[24])&(M5&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[24])&(M5&T1);\nctl_reg_sys_hilo_pla24M5T1_6 = (pla[24])&(M5&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla24M5T1_6,ctl_reg_sys_hilo_pla24M5T1_6})&(2'b01);\nctl_sw_4u = ctl_sw_4u | (pla[24])&(M5&T1);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[24])&(M5&T1);\nctl_sw_1u = ctl_sw_1u | (pla[24])&(M5&T1);\nctl_bus_db_we = ctl_bus_db_we | (pla[24])&(M5&T1);\nfMWrite = fMWrite | (pla[24])&(M5&T2);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[24])&(M5&T2);\nctl_reg_gp_sel_pla24M5T2_3 = (pla[24])&(M5&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla24M5T2_3,ctl_reg_gp_sel_pla24M5T2_3})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla24M5T2_4 = (pla[24])&(M5&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla24M5T2_4,ctl_reg_gp_hilo_pla24M5T2_4})&(2'b11);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[24])&(M5&T2);\nctl_sw_4u = ctl_sw_4u | (pla[24])&(M5&T2);\nctl_inc_cy = ctl_inc_cy | (pla[24])&(M5&T2)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[24])&(M5&T2);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[24])&(M5&T2);\nfMWrite = fMWrite | (pla[24])&(M5&T3);\nsetM1 = setM1 | (pla[24])&(M5&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[24])&(M5&T3);\nctl_reg_sys_hilo_pla24M5T3_4 = (pla[24])&(M5&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla24M5T3_4,ctl_reg_sys_hilo_pla24M5T3_4})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[24])&(M5&T3);\nctl_al_we = ctl_al_we | (pla[24])&(M5&T3);\nctl_reg_not_pc = ctl_reg_not_pc | (pla[24])&(M5&T3);\nctl_reg_gp_sel_pla42M1T3_1 = (pla[42])&(M1&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla42M1T3_1,ctl_reg_gp_sel_pla42M1T3_1})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla42M1T3_2 = (pla[42])&(M1&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla42M1T3_2,ctl_reg_gp_hilo_pla42M1T3_2})&(2'b11);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[42])&(M1&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[42])&(M1&T3);\nctl_flags_bus = ctl_flags_bus | (pla[42])&(M1&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[42])&(M1&T3)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[42])&(M1&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[42])&(M1&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[42])&(M1&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[42])&(M1&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[42])&(M1&T3);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[42])&(M1&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[42])&(M1&T3);\nctl_flags_cf_we = ctl_flags_cf_we | (pla[42])&(M1&T3);\nvalidPLA = validPLA | (pla[42])&(M1&T4);\nnextM = nextM | (pla[42])&(M1&T4);\nctl_mRead = ctl_mRead | (pla[42])&(M1&T4);\nfMRead = fMRead | (pla[42])&(M2&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[42])&(M2&T1);\nctl_reg_sys_hilo_pla42M2T1_3 = (pla[42])&(M2&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla42M2T1_3,ctl_reg_sys_hilo_pla42M2T1_3})&(2'b11);\nctl_al_we = ctl_al_we | (pla[42])&(M2&T1);\nfMRead = fMRead | (pla[42])&(M2&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[42])&(M2&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[42])&(M2&T2);\nctl_reg_sys_hilo_pla42M2T2_4 = (pla[42])&(M2&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla42M2T2_4,ctl_reg_sys_hilo_pla42M2T2_4})&(2'b11);\npc_inc_hold = pc_inc_hold | (pla[42])&(M2&T2)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (pla[42])&(M2&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[42])&(M2&T2);\nfMRead = fMRead | (pla[42])&(M2&T3);\nnextM = nextM | (pla[42])&(M2&T3);\nctl_mRead = ctl_mRead | (pla[42])&(M2&T3);\nctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (pla[42])&(M2&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[42])&(M2&T3);\nctl_reg_sys_hilo_pla42M2T3_6 = (pla[42])&(M2&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla42M2T3_6,ctl_reg_sys_hilo_pla42M2T3_6})&({ctl_reg_sys_hilo[1],1'b1});\nctl_reg_in_lo = ctl_reg_in_lo | (pla[42])&(M2&T3);\nctl_sw_2d = ctl_sw_2d | (pla[42])&(M2&T3);\nctl_sw_1d = ctl_sw_1d | (pla[42])&(M2&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[42])&(M2&T3);\nfMRead = fMRead | (pla[42])&(M3&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[42])&(M3&T1);\nctl_reg_sys_hilo_pla42M3T1_3 = (pla[42])&(M3&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla42M3T1_3,ctl_reg_sys_hilo_pla42M3T1_3})&(2'b11);\nctl_al_we = ctl_al_we | (pla[42])&(M3&T1);\nfMRead = fMRead | (pla[42])&(M3&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[42])&(M3&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[42])&(M3&T2);\nctl_reg_sys_hilo_pla42M3T2_4 = (pla[42])&(M3&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla42M3T2_4,ctl_reg_sys_hilo_pla42M3T2_4})&(2'b11);\npc_inc_hold = pc_inc_hold | (pla[42])&(M3&T2)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (pla[42])&(M3&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[42])&(M3&T2);\nfMRead = fMRead | (pla[42])&(M3&T3);\nnextM = nextM | (pla[42])&(M3&T3)&(~flags_cond_true);\nsetM1 = setM1 | (pla[42])&(M3&T3)&(~flags_cond_true);\nctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (pla[42])&(M3&T3)&(flags_cond_true);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[42])&(M3&T3)&(flags_cond_true);\nctl_reg_sys_hilo_pla42M3T3_6 = (pla[42])&(M3&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla42M3T3_6,ctl_reg_sys_hilo_pla42M3T3_6})&({1'b1,ctl_reg_sys_hilo[0]});\nctl_reg_in_hi = ctl_reg_in_hi | (pla[42])&(M3&T3);\nctl_sw_2d = ctl_sw_2d | (pla[42])&(M3&T3);\nctl_sw_1d = ctl_sw_1d | (pla[42])&(M3&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[42])&(M3&T3);\nnextM = nextM | (pla[42])&(M3&T4);\nctl_mWrite = ctl_mWrite | (pla[42])&(M3&T4);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[42])&(M3&T4);\nctl_reg_gp_sel_pla42M3T4_4 = (pla[42])&(M3&T4);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla42M3T4_4,ctl_reg_gp_sel_pla42M3T4_4})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla42M3T4_5 = (pla[42])&(M3&T4);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla42M3T4_5,ctl_reg_gp_hilo_pla42M3T4_5})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[42])&(M3&T4);\nctl_inc_cy = ctl_inc_cy | (pla[42])&(M3&T4)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[42])&(M3&T4);\nctl_al_we = ctl_al_we | (pla[42])&(M3&T4);\nfMWrite = fMWrite | (pla[42])&(M4&T1);\nctl_inc_cy = ctl_inc_cy | (pla[42])&(M4&T1)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[42])&(M4&T1);\nctl_apin_mux = ctl_apin_mux | (pla[42])&(M4&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[42])&(M4&T1);\nctl_reg_sys_hilo_pla42M4T1_6 = (pla[42])&(M4&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla42M4T1_6,ctl_reg_sys_hilo_pla42M4T1_6})&(2'b10);\nctl_sw_4u = ctl_sw_4u | (pla[42])&(M4&T1);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[42])&(M4&T1);\nctl_sw_2u = ctl_sw_2u | (pla[42])&(M4&T1);\nctl_sw_1u = ctl_sw_1u | (pla[42])&(M4&T1);\nctl_bus_db_we = ctl_bus_db_we | (pla[42])&(M4&T1);\nfMWrite = fMWrite | (pla[42])&(M4&T2);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[42])&(M4&T2);\nctl_reg_gp_sel_pla42M4T2_3 = (pla[42])&(M4&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla42M4T2_3,ctl_reg_gp_sel_pla42M4T2_3})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla42M4T2_4 = (pla[42])&(M4&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla42M4T2_4,ctl_reg_gp_hilo_pla42M4T2_4})&(2'b11);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[42])&(M4&T2);\nctl_sw_4u = ctl_sw_4u | (pla[42])&(M4&T2);\nctl_inc_cy = ctl_inc_cy | (pla[42])&(M4&T2)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[42])&(M4&T2);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[42])&(M4&T2);\nfMWrite = fMWrite | (pla[42])&(M4&T3);\nnextM = nextM | (pla[42])&(M4&T3);\nctl_mWrite = ctl_mWrite | (pla[42])&(M4&T3);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[42])&(M4&T3);\nctl_reg_gp_sel_pla42M4T3_5 = (pla[42])&(M4&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla42M4T3_5,ctl_reg_gp_sel_pla42M4T3_5})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla42M4T3_6 = (pla[42])&(M4&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla42M4T3_6,ctl_reg_gp_hilo_pla42M4T3_6})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[42])&(M4&T3);\nctl_inc_cy = ctl_inc_cy | (pla[42])&(M4&T3)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[42])&(M4&T3);\nctl_al_we = ctl_al_we | (pla[42])&(M4&T3);\nfMWrite = fMWrite | (pla[42])&(M5&T1);\nctl_inc_cy = ctl_inc_cy | (pla[42])&(M5&T1)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[42])&(M5&T1);\nctl_apin_mux = ctl_apin_mux | (pla[42])&(M5&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[42])&(M5&T1);\nctl_reg_sys_hilo_pla42M5T1_6 = (pla[42])&(M5&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla42M5T1_6,ctl_reg_sys_hilo_pla42M5T1_6})&(2'b01);\nctl_sw_4u = ctl_sw_4u | (pla[42])&(M5&T1);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[42])&(M5&T1);\nctl_sw_1u = ctl_sw_1u | (pla[42])&(M5&T1);\nctl_bus_db_we = ctl_bus_db_we | (pla[42])&(M5&T1);\nfMWrite = fMWrite | (pla[42])&(M5&T2);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[42])&(M5&T2);\nctl_reg_gp_sel_pla42M5T2_3 = (pla[42])&(M5&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla42M5T2_3,ctl_reg_gp_sel_pla42M5T2_3})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla42M5T2_4 = (pla[42])&(M5&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla42M5T2_4,ctl_reg_gp_hilo_pla42M5T2_4})&(2'b11);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[42])&(M5&T2);\nctl_sw_4u = ctl_sw_4u | (pla[42])&(M5&T2);\nctl_inc_cy = ctl_inc_cy | (pla[42])&(M5&T2)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[42])&(M5&T2);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[42])&(M5&T2);\nfMWrite = fMWrite | (pla[42])&(M5&T3);\nsetM1 = setM1 | (pla[42])&(M5&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[42])&(M5&T3);\nctl_reg_sys_hilo_pla42M5T3_4 = (pla[42])&(M5&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla42M5T3_4,ctl_reg_sys_hilo_pla42M5T3_4})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[42])&(M5&T3);\nctl_al_we = ctl_al_we | (pla[42])&(M5&T3);\nctl_reg_not_pc = ctl_reg_not_pc | (pla[42])&(M5&T3);\nvalidPLA = validPLA | (pla[35])&(M1&T4);\nnextM = nextM | (pla[35])&(M1&T4);\nctl_mRead = ctl_mRead | (pla[35])&(M1&T4);\nfMRead = fMRead | (pla[35])&(M2&T1);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[35])&(M2&T1);\nctl_reg_gp_sel_pla35M2T1_3 = (pla[35])&(M2&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla35M2T1_3,ctl_reg_gp_sel_pla35M2T1_3})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla35M2T1_4 = (pla[35])&(M2&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla35M2T1_4,ctl_reg_gp_hilo_pla35M2T1_4})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[35])&(M2&T1);\nctl_al_we = ctl_al_we | (pla[35])&(M2&T1);\nfMRead = fMRead | (pla[35])&(M2&T2);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[35])&(M2&T2);\nctl_reg_gp_sel_pla35M2T2_3 = (pla[35])&(M2&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla35M2T2_3,ctl_reg_gp_sel_pla35M2T2_3})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla35M2T2_4 = (pla[35])&(M2&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla35M2T2_4,ctl_reg_gp_hilo_pla35M2T2_4})&(2'b11);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[35])&(M2&T2);\nctl_sw_4u = ctl_sw_4u | (pla[35])&(M2&T2);\nctl_inc_cy = ctl_inc_cy | (pla[35])&(M2&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[35])&(M2&T2);\nfMRead = fMRead | (pla[35])&(M2&T3);\nnextM = nextM | (pla[35])&(M2&T3);\nctl_mRead = ctl_mRead | (pla[35])&(M2&T3);\nctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (pla[35])&(M2&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[35])&(M2&T3);\nctl_reg_sys_hilo_pla35M2T3_6 = (pla[35])&(M2&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla35M2T3_6,ctl_reg_sys_hilo_pla35M2T3_6})&({ctl_reg_sys_hilo[1],1'b1});\nctl_reg_in_lo = ctl_reg_in_lo | (pla[35])&(M2&T3);\nctl_sw_2d = ctl_sw_2d | (pla[35])&(M2&T3);\nctl_sw_1d = ctl_sw_1d | (pla[35])&(M2&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[35])&(M2&T3);\nfMRead = fMRead | (pla[35])&(M3&T1);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[35])&(M3&T1);\nctl_reg_gp_sel_pla35M3T1_3 = (pla[35])&(M3&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla35M3T1_3,ctl_reg_gp_sel_pla35M3T1_3})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla35M3T1_4 = (pla[35])&(M3&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla35M3T1_4,ctl_reg_gp_hilo_pla35M3T1_4})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[35])&(M3&T1);\nctl_al_we = ctl_al_we | (pla[35])&(M3&T1);\nfMRead = fMRead | (pla[35])&(M3&T2);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[35])&(M3&T2);\nctl_reg_gp_sel_pla35M3T2_3 = (pla[35])&(M3&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla35M3T2_3,ctl_reg_gp_sel_pla35M3T2_3})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla35M3T2_4 = (pla[35])&(M3&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla35M3T2_4,ctl_reg_gp_hilo_pla35M3T2_4})&(2'b11);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[35])&(M3&T2);\nctl_sw_4u = ctl_sw_4u | (pla[35])&(M3&T2);\nctl_inc_cy = ctl_inc_cy | (pla[35])&(M3&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[35])&(M3&T2);\nfMRead = fMRead | (pla[35])&(M3&T3);\nsetM1 = setM1 | (pla[35])&(M3&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[35])&(M3&T3);\nctl_reg_sys_hilo_pla35M3T3_4 = (pla[35])&(M3&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla35M3T3_4,ctl_reg_sys_hilo_pla35M3T3_4})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[35])&(M3&T3);\nctl_al_we = ctl_al_we | (pla[35])&(M3&T3);\nctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (pla[35])&(M3&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[35])&(M3&T3);\nctl_reg_sys_hilo_pla35M3T3_9 = (pla[35])&(M3&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla35M3T3_9,ctl_reg_sys_hilo_pla35M3T3_9})&({1'b1,ctl_reg_sys_hilo[0]});\nctl_reg_in_hi = ctl_reg_in_hi | (pla[35])&(M3&T3);\nctl_sw_2d = ctl_sw_2d | (pla[35])&(M3&T3);\nctl_sw_1d = ctl_sw_1d | (pla[35])&(M3&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[35])&(M3&T3);\nctl_reg_not_pc = ctl_reg_not_pc | (pla[35])&(M3&T3);\nctl_reg_gp_sel_pla45M1T3_1 = (pla[45])&(M1&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla45M1T3_1,ctl_reg_gp_sel_pla45M1T3_1})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla45M1T3_2 = (pla[45])&(M1&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla45M1T3_2,ctl_reg_gp_hilo_pla45M1T3_2})&(2'b11);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[45])&(M1&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[45])&(M1&T3);\nctl_flags_bus = ctl_flags_bus | (pla[45])&(M1&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[45])&(M1&T3)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[45])&(M1&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[45])&(M1&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[45])&(M1&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[45])&(M1&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[45])&(M1&T3);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[45])&(M1&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[45])&(M1&T3);\nctl_flags_cf_we = ctl_flags_cf_we | (pla[45])&(M1&T3);\nvalidPLA = validPLA | (pla[45])&(M1&T4);\nnextM = nextM | (pla[45])&(M1&T5);\nctl_mRead = ctl_mRead | (pla[45])&(M1&T5);\nsetM1 = setM1 | (pla[45])&(M1&T5)&(~flags_cond_true);\nfMRead = fMRead | (pla[45])&(M2&T1);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[45])&(M2&T1);\nctl_reg_gp_sel_pla45M2T1_3 = (pla[45])&(M2&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla45M2T1_3,ctl_reg_gp_sel_pla45M2T1_3})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla45M2T1_4 = (pla[45])&(M2&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla45M2T1_4,ctl_reg_gp_hilo_pla45M2T1_4})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[45])&(M2&T1);\nctl_al_we = ctl_al_we | (pla[45])&(M2&T1);\nfMRead = fMRead | (pla[45])&(M2&T2);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[45])&(M2&T2);\nctl_reg_gp_sel_pla45M2T2_3 = (pla[45])&(M2&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla45M2T2_3,ctl_reg_gp_sel_pla45M2T2_3})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla45M2T2_4 = (pla[45])&(M2&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla45M2T2_4,ctl_reg_gp_hilo_pla45M2T2_4})&(2'b11);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[45])&(M2&T2);\nctl_sw_4u = ctl_sw_4u | (pla[45])&(M2&T2);\nctl_inc_cy = ctl_inc_cy | (pla[45])&(M2&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[45])&(M2&T2);\nfMRead = fMRead | (pla[45])&(M2&T3);\nnextM = nextM | (pla[45])&(M2&T3);\nctl_mRead = ctl_mRead | (pla[45])&(M2&T3);\nctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (pla[45])&(M2&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[45])&(M2&T3);\nctl_reg_sys_hilo_pla45M2T3_6 = (pla[45])&(M2&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla45M2T3_6,ctl_reg_sys_hilo_pla45M2T3_6})&({ctl_reg_sys_hilo[1],1'b1});\nctl_reg_in_lo = ctl_reg_in_lo | (pla[45])&(M2&T3);\nctl_sw_2d = ctl_sw_2d | (pla[45])&(M2&T3);\nctl_sw_1d = ctl_sw_1d | (pla[45])&(M2&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[45])&(M2&T3);\nfMRead = fMRead | (pla[45])&(M3&T1);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[45])&(M3&T1);\nctl_reg_gp_sel_pla45M3T1_3 = (pla[45])&(M3&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla45M3T1_3,ctl_reg_gp_sel_pla45M3T1_3})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla45M3T1_4 = (pla[45])&(M3&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla45M3T1_4,ctl_reg_gp_hilo_pla45M3T1_4})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[45])&(M3&T1);\nctl_al_we = ctl_al_we | (pla[45])&(M3&T1);\nfMRead = fMRead | (pla[45])&(M3&T2);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[45])&(M3&T2);\nctl_reg_gp_sel_pla45M3T2_3 = (pla[45])&(M3&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla45M3T2_3,ctl_reg_gp_sel_pla45M3T2_3})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla45M3T2_4 = (pla[45])&(M3&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla45M3T2_4,ctl_reg_gp_hilo_pla45M3T2_4})&(2'b11);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[45])&(M3&T2);\nctl_sw_4u = ctl_sw_4u | (pla[45])&(M3&T2);\nctl_inc_cy = ctl_inc_cy | (pla[45])&(M3&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[45])&(M3&T2);\nfMRead = fMRead | (pla[45])&(M3&T3);\nsetM1 = setM1 | (pla[45])&(M3&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[45])&(M3&T3);\nctl_reg_sys_hilo_pla45M3T3_4 = (pla[45])&(M3&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla45M3T3_4,ctl_reg_sys_hilo_pla45M3T3_4})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[45])&(M3&T3);\nctl_al_we = ctl_al_we | (pla[45])&(M3&T3);\nctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (pla[45])&(M3&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[45])&(M3&T3);\nctl_reg_sys_hilo_pla45M3T3_9 = (pla[45])&(M3&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla45M3T3_9,ctl_reg_sys_hilo_pla45M3T3_9})&({1'b1,ctl_reg_sys_hilo[0]});\nctl_reg_in_hi = ctl_reg_in_hi | (pla[45])&(M3&T3);\nctl_sw_2d = ctl_sw_2d | (pla[45])&(M3&T3);\nctl_sw_1d = ctl_sw_1d | (pla[45])&(M3&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[45])&(M3&T3);\nctl_reg_not_pc = ctl_reg_not_pc | (pla[45])&(M3&T3);\nvalidPLA = validPLA | (pla[46])&(M1&T4);\nnextM = nextM | (pla[46])&(M1&T4);\nctl_mRead = ctl_mRead | (pla[46])&(M1&T4);\nctl_iff1_iff2 = ctl_iff1_iff2 | (pla[46])&(M1&T4);\nfMRead = fMRead | (pla[46])&(M2&T1);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[46])&(M2&T1);\nctl_reg_gp_sel_pla46M2T1_3 = (pla[46])&(M2&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla46M2T1_3,ctl_reg_gp_sel_pla46M2T1_3})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla46M2T1_4 = (pla[46])&(M2&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla46M2T1_4,ctl_reg_gp_hilo_pla46M2T1_4})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[46])&(M2&T1);\nctl_al_we = ctl_al_we | (pla[46])&(M2&T1);\nfMRead = fMRead | (pla[46])&(M2&T2);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[46])&(M2&T2);\nctl_reg_gp_sel_pla46M2T2_3 = (pla[46])&(M2&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla46M2T2_3,ctl_reg_gp_sel_pla46M2T2_3})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla46M2T2_4 = (pla[46])&(M2&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla46M2T2_4,ctl_reg_gp_hilo_pla46M2T2_4})&(2'b11);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[46])&(M2&T2);\nctl_sw_4u = ctl_sw_4u | (pla[46])&(M2&T2);\nctl_inc_cy = ctl_inc_cy | (pla[46])&(M2&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[46])&(M2&T2);\nfMRead = fMRead | (pla[46])&(M2&T3);\nnextM = nextM | (pla[46])&(M2&T3);\nctl_mRead = ctl_mRead | (pla[46])&(M2&T3);\nctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (pla[46])&(M2&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[46])&(M2&T3);\nctl_reg_sys_hilo_pla46M2T3_6 = (pla[46])&(M2&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla46M2T3_6,ctl_reg_sys_hilo_pla46M2T3_6})&({ctl_reg_sys_hilo[1],1'b1});\nctl_reg_in_lo = ctl_reg_in_lo | (pla[46])&(M2&T3);\nctl_sw_2d = ctl_sw_2d | (pla[46])&(M2&T3);\nctl_sw_1d = ctl_sw_1d | (pla[46])&(M2&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[46])&(M2&T3);\nfMRead = fMRead | (pla[46])&(M3&T1);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[46])&(M3&T1);\nctl_reg_gp_sel_pla46M3T1_3 = (pla[46])&(M3&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla46M3T1_3,ctl_reg_gp_sel_pla46M3T1_3})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla46M3T1_4 = (pla[46])&(M3&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla46M3T1_4,ctl_reg_gp_hilo_pla46M3T1_4})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[46])&(M3&T1);\nctl_al_we = ctl_al_we | (pla[46])&(M3&T1);\nfMRead = fMRead | (pla[46])&(M3&T2);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[46])&(M3&T2);\nctl_reg_gp_sel_pla46M3T2_3 = (pla[46])&(M3&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla46M3T2_3,ctl_reg_gp_sel_pla46M3T2_3})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla46M3T2_4 = (pla[46])&(M3&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla46M3T2_4,ctl_reg_gp_hilo_pla46M3T2_4})&(2'b11);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[46])&(M3&T2);\nctl_sw_4u = ctl_sw_4u | (pla[46])&(M3&T2);\nctl_inc_cy = ctl_inc_cy | (pla[46])&(M3&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[46])&(M3&T2);\nfMRead = fMRead | (pla[46])&(M3&T3);\nsetM1 = setM1 | (pla[46])&(M3&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[46])&(M3&T3);\nctl_reg_sys_hilo_pla46M3T3_4 = (pla[46])&(M3&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla46M3T3_4,ctl_reg_sys_hilo_pla46M3T3_4})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[46])&(M3&T3);\nctl_al_we = ctl_al_we | (pla[46])&(M3&T3);\nctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (pla[46])&(M3&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[46])&(M3&T3);\nctl_reg_sys_hilo_pla46M3T3_9 = (pla[46])&(M3&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla46M3T3_9,ctl_reg_sys_hilo_pla46M3T3_9})&({1'b1,ctl_reg_sys_hilo[0]});\nctl_reg_in_hi = ctl_reg_in_hi | (pla[46])&(M3&T3);\nctl_sw_2d = ctl_sw_2d | (pla[46])&(M3&T3);\nctl_sw_1d = ctl_sw_1d | (pla[46])&(M3&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[46])&(M3&T3);\nctl_reg_not_pc = ctl_reg_not_pc | (pla[46])&(M3&T3);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[56])&(M1&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[56])&(M1&T3);\nctl_reg_sys_hilo_pla56M1T3_3 = (pla[56])&(M1&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla56M1T3_3,ctl_reg_sys_hilo_pla56M1T3_3})&(2'b11);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[56])&(M1&T3);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[56])&(M1&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[56])&(M1&T3);\nctl_alu_oe = ctl_alu_oe | (pla[56])&(M1&T3);\nctl_alu_op1_oe = ctl_alu_op1_oe | (pla[56])&(M1&T3);\nctl_alu_op1_sel_zero = ctl_alu_op1_sel_zero | (pla[56])&(M1&T3);\nctl_sw_mask543_en = ctl_sw_mask543_en | (pla[56])&(M1&T3)&(~((in_intr&im2)|in_nmi));\nctl_sw_1d = ctl_sw_1d | (pla[56])&(M1&T3)&(~in_nmi);\nctl_66_oe = ctl_66_oe | (pla[56])&(M1&T3)&(in_nmi);\nctl_bus_ff_oe = ctl_bus_ff_oe | (pla[56])&(M1&T3)&(in_intr&im1);\nvalidPLA = validPLA | (pla[56])&(M1&T4);\nnextM = nextM | (pla[56])&(M1&T5);\nctl_mWrite = ctl_mWrite | (pla[56])&(M1&T5);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[56])&(M1&T5);\nctl_reg_gp_sel_pla56M1T5_4 = (pla[56])&(M1&T5);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla56M1T5_4,ctl_reg_gp_sel_pla56M1T5_4})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla56M1T5_5 = (pla[56])&(M1&T5);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla56M1T5_5,ctl_reg_gp_hilo_pla56M1T5_5})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[56])&(M1&T5);\nctl_inc_cy = ctl_inc_cy | (pla[56])&(M1&T5)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[56])&(M1&T5);\nctl_al_we = ctl_al_we | (pla[56])&(M1&T5);\nctl_sw_2d = ctl_sw_2d | (pla[56])&(M1&T5);\nctl_sw_1d = ctl_sw_1d | (pla[56])&(M1&T5);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[56])&(M1&T5);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[56])&(M1&T5)&(~ctl_alu_bs_oe);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[56])&(M1&T5);\nfMWrite = fMWrite | (pla[56])&(M2&T1);\nctl_inc_cy = ctl_inc_cy | (pla[56])&(M2&T1)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[56])&(M2&T1);\nctl_apin_mux = ctl_apin_mux | (pla[56])&(M2&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[56])&(M2&T1);\nctl_reg_sys_hilo_pla56M2T1_6 = (pla[56])&(M2&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla56M2T1_6,ctl_reg_sys_hilo_pla56M2T1_6})&(2'b10);\nctl_sw_4u = ctl_sw_4u | (pla[56])&(M2&T1);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[56])&(M2&T1);\nctl_sw_2u = ctl_sw_2u | (pla[56])&(M2&T1);\nctl_sw_1u = ctl_sw_1u | (pla[56])&(M2&T1);\nctl_bus_db_we = ctl_bus_db_we | (pla[56])&(M2&T1);\nfMWrite = fMWrite | (pla[56])&(M2&T2);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[56])&(M2&T2);\nctl_reg_gp_sel_pla56M2T2_3 = (pla[56])&(M2&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla56M2T2_3,ctl_reg_gp_sel_pla56M2T2_3})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla56M2T2_4 = (pla[56])&(M2&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla56M2T2_4,ctl_reg_gp_hilo_pla56M2T2_4})&(2'b11);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[56])&(M2&T2);\nctl_sw_4u = ctl_sw_4u | (pla[56])&(M2&T2);\nctl_inc_cy = ctl_inc_cy | (pla[56])&(M2&T2)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[56])&(M2&T2);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[56])&(M2&T2);\nfMWrite = fMWrite | (pla[56])&(M2&T3);\nnextM = nextM | (pla[56])&(M2&T3);\nctl_mWrite = ctl_mWrite | (pla[56])&(M2&T3);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[56])&(M2&T3);\nctl_reg_gp_sel_pla56M2T3_5 = (pla[56])&(M2&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla56M2T3_5,ctl_reg_gp_sel_pla56M2T3_5})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla56M2T3_6 = (pla[56])&(M2&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla56M2T3_6,ctl_reg_gp_hilo_pla56M2T3_6})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[56])&(M2&T3);\nctl_inc_cy = ctl_inc_cy | (pla[56])&(M2&T3)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[56])&(M2&T3);\nctl_al_we = ctl_al_we | (pla[56])&(M2&T3);\nfMWrite = fMWrite | (pla[56])&(M3&T1);\nctl_inc_cy = ctl_inc_cy | (pla[56])&(M3&T1)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[56])&(M3&T1);\nctl_apin_mux = ctl_apin_mux | (pla[56])&(M3&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[56])&(M3&T1);\nctl_reg_sys_hilo_pla56M3T1_6 = (pla[56])&(M3&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla56M3T1_6,ctl_reg_sys_hilo_pla56M3T1_6})&(2'b01);\nctl_sw_4u = ctl_sw_4u | (pla[56])&(M3&T1);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[56])&(M3&T1);\nctl_sw_1u = ctl_sw_1u | (pla[56])&(M3&T1);\nctl_bus_db_we = ctl_bus_db_we | (pla[56])&(M3&T1);\nfMWrite = fMWrite | (pla[56])&(M3&T2);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[56])&(M3&T2);\nctl_reg_gp_sel_pla56M3T2_3 = (pla[56])&(M3&T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla56M3T2_3,ctl_reg_gp_sel_pla56M3T2_3})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla56M3T2_4 = (pla[56])&(M3&T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla56M3T2_4,ctl_reg_gp_hilo_pla56M3T2_4})&(2'b11);\nctl_reg_use_sp = ctl_reg_use_sp | (pla[56])&(M3&T2);\nctl_sw_4u = ctl_sw_4u | (pla[56])&(M3&T2);\nctl_inc_cy = ctl_inc_cy | (pla[56])&(M3&T2)&(~pc_inc_hold);\nctl_inc_dec = ctl_inc_dec | (pla[56])&(M3&T2);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[56])&(M3&T2);\nfMWrite = fMWrite | (pla[56])&(M3&T3);\nnextM = nextM | (pla[56])&(M3&T3);\nctl_mRead = ctl_mRead | (pla[56])&(M3&T3)&(in_intr&im2);\nsetM1 = setM1 | (pla[56])&(M3&T3)&(~(in_intr&im2));\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[56])&(M3&T3);\nctl_reg_sys_hilo_pla56M3T3_6 = (pla[56])&(M3&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla56M3T3_6,ctl_reg_sys_hilo_pla56M3T3_6})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[56])&(M3&T3);\nctl_al_we = ctl_al_we | (pla[56])&(M3&T3);\nctl_reg_not_pc = ctl_reg_not_pc | (pla[56])&(M3&T3);\nfMRead = fMRead | (pla[56])&(M4&T1);\nctl_reg_sel_ir = ctl_reg_sel_ir | (pla[56])&(M4&T1);\nctl_reg_sys_hilo_pla56M4T1_3 = (pla[56])&(M4&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla56M4T1_3,ctl_reg_sys_hilo_pla56M4T1_3})&(2'b10);\nctl_sw_4d = ctl_sw_4d | (pla[56])&(M4&T1);\nctl_al_we = ctl_al_we | (pla[56])&(M4&T1);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[56])&(M4&T1);\nctl_sw_2u = ctl_sw_2u | (pla[56])&(M4&T1);\nctl_alu_oe = ctl_alu_oe | (pla[56])&(M4&T1);\nctl_alu_op1_oe = ctl_alu_op1_oe | (pla[56])&(M4&T1);\nfMRead = fMRead | (pla[56])&(M4&T2);\nctl_sw_4u = ctl_sw_4u | (pla[56])&(M4&T2);\nctl_inc_cy = ctl_inc_cy | (pla[56])&(M4&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[56])&(M4&T2);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[56])&(M4&T2);\nctl_sw_2d = ctl_sw_2d | (pla[56])&(M4&T2);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[56])&(M4&T2)&(~ctl_alu_bs_oe);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[56])&(M4&T2);\nfMRead = fMRead | (pla[56])&(M4&T3);\nnextM = nextM | (pla[56])&(M4&T3);\nctl_mRead = ctl_mRead | (pla[56])&(M4&T3);\nctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (pla[56])&(M4&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[56])&(M4&T3);\nctl_reg_sys_hilo_pla56M4T3_6 = (pla[56])&(M4&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla56M4T3_6,ctl_reg_sys_hilo_pla56M4T3_6})&({ctl_reg_sys_hilo[1],1'b1});\nctl_reg_in_lo = ctl_reg_in_lo | (pla[56])&(M4&T3);\nctl_sw_2d = ctl_sw_2d | (pla[56])&(M4&T3);\nctl_sw_1d = ctl_sw_1d | (pla[56])&(M4&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[56])&(M4&T3);\nfMRead = fMRead | (pla[56])&(M5&T1);\nctl_reg_sel_ir = ctl_reg_sel_ir | (pla[56])&(M5&T1);\nctl_reg_sys_hilo_pla56M5T1_3 = (pla[56])&(M5&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla56M5T1_3,ctl_reg_sys_hilo_pla56M5T1_3})&(2'b10);\nctl_sw_4d = ctl_sw_4d | (pla[56])&(M5&T1);\nctl_al_we = ctl_al_we | (pla[56])&(M5&T1);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[56])&(M5&T1);\nctl_sw_2u = ctl_sw_2u | (pla[56])&(M5&T1);\nctl_alu_oe = ctl_alu_oe | (pla[56])&(M5&T1);\nctl_alu_op1_oe = ctl_alu_op1_oe | (pla[56])&(M5&T1);\nfMRead = fMRead | (pla[56])&(M5&T2);\nctl_inc_cy = ctl_inc_cy | (pla[56])&(M5&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[56])&(M5&T2);\nfMRead = fMRead | (pla[56])&(M5&T3);\nsetM1 = setM1 | (pla[56])&(M5&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[56])&(M5&T3);\nctl_reg_sys_hilo_pla56M5T3_4 = (pla[56])&(M5&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla56M5T3_4,ctl_reg_sys_hilo_pla56M5T3_4})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (pla[56])&(M5&T3);\nctl_al_we = ctl_al_we | (pla[56])&(M5&T3);\nctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (pla[56])&(M5&T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (pla[56])&(M5&T3);\nctl_reg_sys_hilo_pla56M5T3_9 = (pla[56])&(M5&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla56M5T3_9,ctl_reg_sys_hilo_pla56M5T3_9})&({1'b1,ctl_reg_sys_hilo[0]});\nctl_reg_in_hi = ctl_reg_in_hi | (pla[56])&(M5&T3);\nctl_sw_2d = ctl_sw_2d | (pla[56])&(M5&T3);\nctl_sw_1d = ctl_sw_1d | (pla[56])&(M5&T3);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[56])&(M5&T3);\nctl_reg_not_pc = ctl_reg_not_pc | (pla[56])&(M5&T3);\nctl_reg_gp_sel_pla49M1T3_1 = (pla[49])&(M1&T3);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla49M1T3_1,ctl_reg_gp_sel_pla49M1T3_1})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla49M1T3_2 = (pla[49])&(M1&T3);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla49M1T3_2,ctl_reg_gp_hilo_pla49M1T3_2})&(2'b11);\nctl_reg_out_hi = ctl_reg_out_hi | (pla[49])&(M1&T3);\nctl_reg_out_lo = ctl_reg_out_lo | (pla[49])&(M1&T3);\nctl_flags_bus = ctl_flags_bus | (pla[49])&(M1&T3);\nctl_alu_shift_oe = ctl_alu_shift_oe | (pla[49])&(M1&T3)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[49])&(M1&T3);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[49])&(M1&T3);\nctl_flags_sz_we = ctl_flags_sz_we | (pla[49])&(M1&T3);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[49])&(M1&T3);\nctl_flags_hf_we = ctl_flags_hf_we | (pla[49])&(M1&T3);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[49])&(M1&T3);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[49])&(M1&T3);\nctl_flags_cf_we = ctl_flags_cf_we | (pla[49])&(M1&T3);\nctl_state_tbl_we = ctl_state_tbl_we | (pla[49])&(M1&T3);\nctl_state_tbl_cb_set = ctl_state_tbl_cb_set | (pla[49])&(M1&T3);\nvalidPLA = validPLA | (pla[49])&(M1&T4);\nnextM = nextM | (pla[49])&(M1&T4);\nctl_mRead = ctl_mRead | (pla[49])&(M1&T4);\nfMRead = fMRead | (pla[49])&(M2&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[49])&(M2&T1);\nctl_reg_sys_hilo_pla49M2T1_3 = (pla[49])&(M2&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla49M2T1_3,ctl_reg_sys_hilo_pla49M2T1_3})&(2'b11);\nctl_al_we = ctl_al_we | (pla[49])&(M2&T1);\nfMRead = fMRead | (pla[49])&(M2&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[49])&(M2&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[49])&(M2&T2);\nctl_reg_sys_hilo_pla49M2T2_4 = (pla[49])&(M2&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla49M2T2_4,ctl_reg_sys_hilo_pla49M2T2_4})&(2'b11);\npc_inc_hold = pc_inc_hold | (pla[49])&(M2&T2)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (pla[49])&(M2&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[49])&(M2&T2);\nfMRead = fMRead | (pla[49])&(M2&T3);\nnextM = nextM | (pla[49])&(M2&T3);\nctl_mRead = ctl_mRead | (pla[49])&(M2&T3);\nfMRead = fMRead | (pla[49])&(M3&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[49])&(M3&T1);\nctl_reg_sys_hilo_pla49M3T1_3 = (pla[49])&(M3&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla49M3T1_3,ctl_reg_sys_hilo_pla49M3T1_3})&(2'b11);\nctl_al_we = ctl_al_we | (pla[49])&(M3&T1);\nixy_d = ixy_d | (pla[49])&(M3&T1);\nfMRead = fMRead | (pla[49])&(M3&T2);\nctl_reg_sys_we = ctl_reg_sys_we | (pla[49])&(M3&T2);\nctl_reg_sel_pc = ctl_reg_sel_pc | (pla[49])&(M3&T2);\nctl_reg_sys_hilo_pla49M3T2_4 = (pla[49])&(M3&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_pla49M3T2_4,ctl_reg_sys_hilo_pla49M3T2_4})&(2'b11);\npc_inc_hold = pc_inc_hold | (pla[49])&(M3&T2)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (pla[49])&(M3&T2)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (pla[49])&(M3&T2);\nixy_d = ixy_d | (pla[49])&(M3&T2);\nfMRead = fMRead | (pla[49])&(M3&T3);\nixy_d = ixy_d | (pla[49])&(M3&T3);\nixy_d = ixy_d | (pla[49])&(M3&T4);\nnextM = nextM | (pla[49])&(M3&T5);\nctl_mRead = ctl_mRead | (pla[49])&(M3&T5);\nixy_d = ixy_d | (pla[49])&(M3&T5);\nctl_bus_db_oe = ctl_bus_db_oe | (pla[49])&(M4&T1);\nctl_alu_bs_oe = ctl_alu_bs_oe | (pla[49])&(M4&T1);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (pla[49])&(M4&T1);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (pla[49])&(M4&T1);\nctl_ir_we = ctl_ir_we | (pla[49])&(M4&T1);\nctl_state_ixiy_we = ctl_state_ixiy_we | (pla[3])&(M1&T2);\nctl_state_iy_set = ctl_state_iy_set | (pla[3])&(M1&T2)&(op5);\nsetIXIY = setIXIY | (pla[3])&(M1&T2);\nvalidPLA = validPLA | (pla[3])&(M1&T4);\nsetM1 = setM1 | (pla[3])&(M1&T4);\nctl_no_ints = ctl_no_ints | (pla[3])&(M1&T4);\nctl_state_tbl_we = ctl_state_tbl_we | (pla[44])&(M1&T2);\nctl_state_tbl_cb_set = ctl_state_tbl_cb_set | (pla[44])&(M1&T2);\nvalidPLA = validPLA | (pla[44])&(M1&T4);\nsetM1 = setM1 | (pla[44])&(M1&T4);\nctl_no_ints = ctl_no_ints | (pla[44])&(M1&T4);\nctl_state_tbl_we = ctl_state_tbl_we | (pla[51])&(M1&T2);\nctl_state_tbl_ed_set = ctl_state_tbl_ed_set | (pla[51])&(M1&T2);\nvalidPLA = validPLA | (pla[51])&(M1&T4);\nsetM1 = setM1 | (pla[51])&(M1&T4);\nctl_no_ints = ctl_no_ints | (pla[51])&(M1&T4);\nctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[76]);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[76])&(ctl_alu_op_low);\nctl_alu_core_hf = ctl_alu_core_hf | (pla[76])&(~ctl_alu_op_low);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[76]);\nctl_flags_nf_set = ctl_flags_nf_set | (pla[76]);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[76])&(M1&T1);\nctl_pf_sel_pla76M1T1_2 = (pla[76])&(M1&T1);\nctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_pla76M1T1_2,ctl_pf_sel_pla76M1T1_2})&(`PFSEL_V);\nctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[78]);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[78])&(ctl_alu_op_low);\nctl_alu_core_hf = ctl_alu_core_hf | (pla[78])&(~ctl_alu_op_low);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[78]);\nctl_flags_nf_set = ctl_flags_nf_set | (pla[78]);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[78])&(M1&T1);\nctl_reg_gp_sel_pla78M1T1_2 = (pla[78])&(M1&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla78M1T1_2,ctl_reg_gp_sel_pla78M1T1_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla78M1T1_3 = (pla[78])&(M1&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla78M1T1_3,ctl_reg_gp_hilo_pla78M1T1_3})&(2'b10);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[78])&(M1&T1);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[78])&(M1&T1);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[78])&(M1&T1);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[78])&(M1&T1);\nctl_pf_sel_pla78M1T1_8 = (pla[78])&(M1&T1);\nctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_pla78M1T1_8,ctl_pf_sel_pla78M1T1_8})&(`PFSEL_V);\nctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (pla[79]);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[79])&(ctl_alu_op_low);\nctl_alu_core_hf = ctl_alu_core_hf | (pla[79])&(~ctl_alu_op_low);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[79]);\nctl_flags_nf_set = ctl_flags_nf_set | (pla[79]);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[79])&(M1&T1);\nctl_reg_gp_sel_pla79M1T1_2 = (pla[79])&(M1&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla79M1T1_2,ctl_reg_gp_sel_pla79M1T1_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla79M1T1_3 = (pla[79])&(M1&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla79M1T1_3,ctl_reg_gp_hilo_pla79M1T1_3})&(2'b10);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[79])&(M1&T1);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[79])&(M1&T1);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[79])&(M1&T1);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[79])&(M1&T1);\nctl_pf_sel_pla79M1T1_8 = (pla[79])&(M1&T1);\nctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_pla79M1T1_8,ctl_pf_sel_pla79M1T1_8})&(`PFSEL_V);\nctl_alu_core_hf = ctl_alu_core_hf | (pla[80])&(~ctl_alu_op_low);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[80]);\nctl_flags_nf_clr = ctl_flags_nf_clr | (pla[80]);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[80])&(M1&T1);\nctl_reg_gp_sel_pla80M1T1_2 = (pla[80])&(M1&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla80M1T1_2,ctl_reg_gp_sel_pla80M1T1_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla80M1T1_3 = (pla[80])&(M1&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla80M1T1_3,ctl_reg_gp_hilo_pla80M1T1_3})&(2'b10);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[80])&(M1&T1);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[80])&(M1&T1);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[80])&(M1&T1);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[80])&(M1&T1);\nctl_pf_sel_pla80M1T1_8 = (pla[80])&(M1&T1);\nctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_pla80M1T1_8,ctl_pf_sel_pla80M1T1_8})&(`PFSEL_V);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[84])&(ctl_alu_op_low);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[84])&(ctl_alu_op_low);\nctl_alu_core_hf = ctl_alu_core_hf | (pla[84])&(~ctl_alu_op_low);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[84]);\nctl_flags_nf_clr = ctl_flags_nf_clr | (pla[84]);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[84])&(M1&T1);\nctl_reg_gp_sel_pla84M1T1_2 = (pla[84])&(M1&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla84M1T1_2,ctl_reg_gp_sel_pla84M1T1_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla84M1T1_3 = (pla[84])&(M1&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla84M1T1_3,ctl_reg_gp_hilo_pla84M1T1_3})&(2'b10);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[84])&(M1&T1);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[84])&(M1&T1);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[84])&(M1&T1);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[84])&(M1&T1);\nctl_pf_sel_pla84M1T1_8 = (pla[84])&(M1&T1);\nctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_pla84M1T1_8,ctl_pf_sel_pla84M1T1_8})&(`PFSEL_V);\nctl_alu_core_S = ctl_alu_core_S | (pla[85]);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[85]);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[85]);\nctl_flags_nf_clr = ctl_flags_nf_clr | (pla[85]);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[85])&(M1&T1);\nctl_reg_gp_sel_pla85M1T1_2 = (pla[85])&(M1&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla85M1T1_2,ctl_reg_gp_sel_pla85M1T1_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla85M1T1_3 = (pla[85])&(M1&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla85M1T1_3,ctl_reg_gp_hilo_pla85M1T1_3})&(2'b10);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[85])&(M1&T1);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[85])&(M1&T1);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[85])&(M1&T1);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[85])&(M1&T1);\nctl_pf_sel_pla85M1T1_8 = (pla[85])&(M1&T1);\nctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_pla85M1T1_8,ctl_pf_sel_pla85M1T1_8})&(`PFSEL_P);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[85])&(M1&T2);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[85])&(M1&T2);\nctl_alu_core_R = ctl_alu_core_R | (pla[86]);\nctl_alu_core_V = ctl_alu_core_V | (pla[86]);\nctl_alu_core_S = ctl_alu_core_S | (pla[86]);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[86]);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[86]);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[86]);\nctl_flags_nf_clr = ctl_flags_nf_clr | (pla[86]);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[86])&(M1&T1);\nctl_reg_gp_sel_pla86M1T1_2 = (pla[86])&(M1&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla86M1T1_2,ctl_reg_gp_sel_pla86M1T1_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla86M1T1_3 = (pla[86])&(M1&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla86M1T1_3,ctl_reg_gp_hilo_pla86M1T1_3})&(2'b10);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[86])&(M1&T1);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[86])&(M1&T1);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[86])&(M1&T1);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[86])&(M1&T1);\nctl_pf_sel_pla86M1T1_8 = (pla[86])&(M1&T1);\nctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_pla86M1T1_8,ctl_pf_sel_pla86M1T1_8})&(`PFSEL_P);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[86])&(M1&T2);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[86])&(M1&T2);\nctl_alu_core_R = ctl_alu_core_R | (pla[88]);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[88]);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[88]);\nctl_flags_nf_we = ctl_flags_nf_we | (pla[88]);\nctl_flags_nf_clr = ctl_flags_nf_clr | (pla[88]);\nctl_reg_gp_we = ctl_reg_gp_we | (pla[88])&(M1&T1);\nctl_reg_gp_sel_pla88M1T1_2 = (pla[88])&(M1&T1);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_pla88M1T1_2,ctl_reg_gp_sel_pla88M1T1_2})&(`GP_REG_AF);\nctl_reg_gp_hilo_pla88M1T1_3 = (pla[88])&(M1&T1);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_pla88M1T1_3,ctl_reg_gp_hilo_pla88M1T1_3})&(2'b10);\nctl_reg_in_hi = ctl_reg_in_hi | (pla[88])&(M1&T1);\nctl_reg_in_lo = ctl_reg_in_lo | (pla[88])&(M1&T1);\nctl_flags_xy_we = ctl_flags_xy_we | (pla[88])&(M1&T1);\nctl_flags_pf_we = ctl_flags_pf_we | (pla[88])&(M1&T1);\nctl_pf_sel_pla88M1T1_8 = (pla[88])&(M1&T1);\nctl_pf_sel = ctl_pf_sel | ({ctl_pf_sel_pla88M1T1_8,ctl_pf_sel_pla88M1T1_8})&(`PFSEL_P);\nctl_flags_cf_set = ctl_flags_cf_set | (pla[88])&(M1&T2);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (pla[88])&(M1&T2);\nctl_sw_2d = ctl_sw_2d | (ixy_d)&(T1);\nctl_sw_1d = ctl_sw_1d | (ixy_d)&(T1);\nctl_bus_db_oe = ctl_bus_db_oe | (ixy_d)&(T1);\nctl_flags_alu = ctl_flags_alu | (ixy_d)&(T1);\nctl_alu_shift_oe = ctl_alu_shift_oe | (ixy_d)&(T1)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_bus = ctl_alu_op2_sel_bus | (ixy_d)&(T1);\nctl_flags_sz_we = ctl_flags_sz_we | (ixy_d)&(T1);\nctl_reg_gp_sel_ixy_dT2_1 = (ixy_d)&(T2);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_ixy_dT2_1,ctl_reg_gp_sel_ixy_dT2_1})&(`GP_REG_HL);\nctl_reg_gp_hilo_ixy_dT2_2 = (ixy_d)&(T2);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_ixy_dT2_2,ctl_reg_gp_hilo_ixy_dT2_2})&(2'b01);\nctl_reg_out_lo = ctl_reg_out_lo | (ixy_d)&(T2);\nctl_sw_2d = ctl_sw_2d | (ixy_d)&(T2);\nctl_flags_alu = ctl_flags_alu | (ixy_d)&(T2);\nctl_alu_shift_oe = ctl_alu_shift_oe | (ixy_d)&(T2)&(~ctl_alu_bs_oe);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (ixy_d)&(T2);\nctl_alu_op_low = ctl_alu_op_low | (ixy_d)&(T2);\nctl_flags_cf_set = ctl_flags_cf_set | (ixy_d)&(T2)&(ctl_alu_op_low);\nctl_flags_cf_cpl = ctl_flags_cf_cpl | (ixy_d)&(T2)&(ctl_alu_op_low);\nctl_alu_core_hf = ctl_alu_core_hf | (ixy_d)&(T2)&(~ctl_alu_op_low);\nctl_flags_hf_we = ctl_flags_hf_we | (ixy_d)&(T2);\nctl_reg_sys_we_lo = ctl_reg_sys_we_lo | (ixy_d)&(T3);\nctl_reg_sel_wz = ctl_reg_sel_wz | (ixy_d)&(T3);\nctl_reg_sys_hilo_ixy_dT3_3 = (ixy_d)&(T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_ixy_dT3_3,ctl_reg_sys_hilo_ixy_dT3_3})&({ctl_reg_sys_hilo[1],1'b1});\nctl_reg_in_lo = ctl_reg_in_lo | (ixy_d)&(T3);\nctl_sw_2u = ctl_sw_2u | (ixy_d)&(T3);\nctl_flags_alu = ctl_flags_alu | (ixy_d)&(T3);\nctl_alu_oe = ctl_alu_oe | (ixy_d)&(T3);\nctl_alu_res_oe = ctl_alu_res_oe | (ixy_d)&(T3);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (ixy_d)&(T3);\nctl_alu_core_hf = ctl_alu_core_hf | (ixy_d)&(T3)&(~ctl_alu_op_low);\nctl_flags_cf2_we = ctl_flags_cf2_we | (ixy_d)&(T3);\nctl_reg_gp_sel_ixy_dT4_1 = (ixy_d)&(T4);\nctl_reg_gp_sel = ctl_reg_gp_sel | ({ctl_reg_gp_sel_ixy_dT4_1,ctl_reg_gp_sel_ixy_dT4_1})&(`GP_REG_HL);\nctl_reg_gp_hilo_ixy_dT4_2 = (ixy_d)&(T4);\nctl_reg_gp_hilo = ctl_reg_gp_hilo | ({ctl_reg_gp_hilo_ixy_dT4_2,ctl_reg_gp_hilo_ixy_dT4_2})&(2'b10);\nctl_reg_out_hi = ctl_reg_out_hi | (ixy_d)&(T4);\nctl_reg_out_lo = ctl_reg_out_lo | (ixy_d)&(T4);\nctl_flags_alu = ctl_flags_alu | (ixy_d)&(T4);\nctl_alu_shift_oe = ctl_alu_shift_oe | (ixy_d)&(T4)&(~ctl_alu_bs_oe);\nctl_alu_op2_sel_zero = ctl_alu_op2_sel_zero | (ixy_d)&(T4);\nctl_alu_op1_sel_bus = ctl_alu_op1_sel_bus | (ixy_d)&(T4);\nctl_alu_op_low = ctl_alu_op_low | (ixy_d)&(T4);\nctl_alu_core_hf = ctl_alu_core_hf | (ixy_d)&(T4)&(~ctl_alu_op_low);\nctl_flags_hf_we = ctl_flags_hf_we | (ixy_d)&(T4);\nctl_flags_use_cf2 = ctl_flags_use_cf2 | (ixy_d)&(T4);\nctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (ixy_d)&(T4)&(flags_sf);\nctl_reg_sel_wz = ctl_reg_sel_wz | (ixy_d)&(T5);\nctl_reg_sys_hilo_ixy_dT5_2 = (ixy_d)&(T5);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_ixy_dT5_2,ctl_reg_sys_hilo_ixy_dT5_2})&(2'b11);\nctl_sw_4d = ctl_sw_4d | (ixy_d)&(T5);\nctl_al_we = ctl_al_we | (ixy_d)&(T5);\nctl_reg_sys_we_hi = ctl_reg_sys_we_hi | (ixy_d)&(T5);\nctl_reg_sel_wz = ctl_reg_sel_wz | (ixy_d)&(T5);\nctl_reg_sys_hilo_ixy_dT5_7 = (ixy_d)&(T5);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_ixy_dT5_7,ctl_reg_sys_hilo_ixy_dT5_7})&({1'b1,ctl_reg_sys_hilo[0]});\nctl_reg_in_hi = ctl_reg_in_hi | (ixy_d)&(T5);\nctl_flags_alu = ctl_flags_alu | (ixy_d)&(T5);\nctl_alu_oe = ctl_alu_oe | (ixy_d)&(T5);\nctl_alu_res_oe = ctl_alu_res_oe | (ixy_d)&(T5);\nctl_alu_sel_op2_high = ctl_alu_sel_op2_high | (ixy_d)&(T5);\nctl_alu_core_hf = ctl_alu_core_hf | (ixy_d)&(T5)&(~ctl_alu_op_low);\nctl_flags_xy_we = ctl_flags_xy_we | (ixy_d)&(T5);\nctl_alu_sel_op2_neg = ctl_alu_sel_op2_neg | (ixy_d)&(T5)&(flags_sf);\nctl_state_ixiy_we = ctl_state_ixiy_we | (ixy_d)&(T5);\nctl_state_ixiy_clr = ctl_state_ixiy_clr | (ixy_d)&(T5)&(~setIXIY);\nctl_reg_sys_we = ctl_reg_sys_we | (M1&T1);\nctl_reg_sel_pc = ctl_reg_sel_pc | (M1&T1);\nctl_reg_sys_hilo_1M1T1_3 = (M1&T1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_1M1T1_3,ctl_reg_sys_hilo_1M1T1_3})&(2'b11);\npc_inc_hold = pc_inc_hold | (M1&T1)&((in_halt|in_intr|in_nmi));\nctl_inc_cy = ctl_inc_cy | (M1&T1)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (M1&T1);\nctl_apin_mux2 = ctl_apin_mux2 | (M1&T1);\nctl_reg_sel_ir = ctl_reg_sel_ir | (M1&T2);\nctl_reg_sys_hilo_1M1T2_2 = (M1&T2);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_1M1T2_2,ctl_reg_sys_hilo_1M1T2_2})&(2'b11);\nctl_al_we = ctl_al_we | (M1&T2);\nctl_bus_db_oe = ctl_bus_db_oe | (M1&T2);\nctl_state_ixiy_we = ctl_state_ixiy_we | (M1&T2);\nctl_state_ixiy_clr = ctl_state_ixiy_clr | (M1&T2)&(~setIXIY);\nctl_state_tbl_we = ctl_state_tbl_we | (M1&T2);\nctl_ir_we = ctl_ir_we | (M1&T2);\nctl_bus_zero_oe = ctl_bus_zero_oe | (M1&T2)&(in_halt);\nctl_bus_ff_oe = ctl_bus_ff_oe | (M1&T2)&((in_intr&(im1|im2))|in_nmi);\nctl_reg_sys_we = ctl_reg_sys_we | (M1&T3);\nctl_reg_sel_ir = ctl_reg_sel_ir | (M1&T3);\nctl_reg_sys_hilo_1M1T3_3 = (M1&T3);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_1M1T3_3,ctl_reg_sys_hilo_1M1T3_3})&(2'b11);\nctl_inc_cy = ctl_inc_cy | (M1&T3)&(~pc_inc_hold);\nctl_bus_inc_oe = ctl_bus_inc_oe | (M1&T3);\nctl_apin_mux2 = ctl_apin_mux2 | (M1&T3);\nctl_inc_limit6 = ctl_inc_limit6 | (M1&T3);\nctl_eval_cond = ctl_eval_cond | (M1&T4);\nsetM1 = setM1 | (~validPLA)&(M1&T4);\nctl_reg_sel_pc = ctl_reg_sel_pc | (setM1);\nctl_reg_sys_hilo_setM1_2 = (setM1);\nctl_reg_sys_hilo = ctl_reg_sys_hilo | ({ctl_reg_sys_hilo_setM1_2,ctl_reg_sys_hilo_setM1_2})&(2'b11);\nctl_al_we = ctl_al_we | (setM1);\n"
  },
  {
    "path": "cpu/control/exec_module.vh",
    "content": "// Automatically generated by genref.py\n\n// Module: control/decode_state.v\noutput reg ctl_state_iy_set,\noutput reg ctl_state_ixiy_clr,\noutput reg ctl_state_ixiy_we,\noutput reg ctl_state_halt_set,\noutput reg ctl_state_tbl_ed_set,\noutput reg ctl_state_tbl_cb_set,\noutput reg ctl_state_alu,\noutput reg ctl_repeat_we,\noutput reg ctl_state_tbl_we,\n\n// Module: control/interrupts.v\noutput reg ctl_iff1_iff2,\noutput reg ctl_iffx_we,\noutput reg ctl_iffx_bit,\noutput reg ctl_im_we,\noutput reg ctl_no_ints,\n\n// Module: control/ir.v\noutput reg ctl_ir_we,\n\n// Module: control/memory_ifc.v\noutput reg ctl_mRead,\noutput reg ctl_mWrite,\noutput reg ctl_iorw,\n\n// Module: alu/alu_control.v\noutput reg ctl_shift_en,\noutput reg ctl_daa_oe,\noutput reg ctl_alu_op_low,\noutput reg ctl_cond_short,\noutput reg ctl_alu_core_hf,\noutput reg ctl_eval_cond,\noutput reg ctl_66_oe,\noutput reg [1:0] ctl_pf_sel,\n\n// Module: alu/alu_select.v\noutput reg ctl_alu_oe,\noutput reg ctl_alu_shift_oe,\noutput reg ctl_alu_op2_oe,\noutput reg ctl_alu_res_oe,\noutput reg ctl_alu_op1_oe,\noutput reg ctl_alu_bs_oe,\noutput reg ctl_alu_op1_sel_bus,\noutput reg ctl_alu_op1_sel_low,\noutput reg ctl_alu_op1_sel_zero,\noutput reg ctl_alu_op2_sel_zero,\noutput reg ctl_alu_op2_sel_bus,\noutput reg ctl_alu_op2_sel_lq,\noutput reg ctl_alu_sel_op2_neg,\noutput reg ctl_alu_sel_op2_high,\noutput reg ctl_alu_core_R,\noutput reg ctl_alu_core_V,\noutput reg ctl_alu_core_S,\n\n// Module: alu/alu_flags.v\noutput reg ctl_flags_oe,\noutput reg ctl_flags_bus,\noutput reg ctl_flags_alu,\noutput reg ctl_flags_nf_set,\noutput reg ctl_flags_cf_set,\noutput reg ctl_flags_cf_cpl,\noutput reg ctl_flags_cf_we,\noutput reg ctl_flags_sz_we,\noutput reg ctl_flags_xy_we,\noutput reg ctl_flags_hf_we,\noutput reg ctl_flags_pf_we,\noutput reg ctl_flags_nf_we,\noutput reg ctl_flags_cf2_we,\noutput reg ctl_flags_hf_cpl,\noutput reg ctl_flags_use_cf2,\noutput reg ctl_flags_hf2_we,\noutput reg ctl_flags_nf_clr,\noutput reg ctl_alu_zero_16bit,\noutput reg ctl_flags_cf2_sel_shift,\noutput reg ctl_flags_cf2_sel_daa,\n\n// Module: registers/reg_file.v\noutput reg ctl_sw_4u,\noutput reg ctl_reg_in_hi,\noutput reg ctl_reg_in_lo,\noutput reg ctl_reg_out_lo,\noutput reg ctl_reg_out_hi,\n\n// Module: registers/reg_control.v\noutput reg ctl_reg_exx,\noutput reg ctl_reg_ex_af,\noutput reg ctl_reg_ex_de_hl,\noutput reg ctl_reg_use_sp,\noutput reg ctl_reg_sel_pc,\noutput reg ctl_reg_sel_ir,\noutput reg ctl_reg_sel_wz,\noutput reg ctl_reg_gp_we,\noutput reg ctl_reg_not_pc,\noutput reg ctl_reg_sys_we_lo,\noutput reg ctl_reg_sys_we_hi,\noutput reg ctl_reg_sys_we,\noutput reg ctl_sw_4d,\noutput reg [1:0] ctl_reg_gp_hilo,\noutput reg [1:0] ctl_reg_gp_sel,\noutput reg [1:0] ctl_reg_sys_hilo,\n\n// Module: bus/address_latch.v\noutput reg ctl_inc_cy,\noutput reg ctl_inc_dec,\noutput reg ctl_al_we,\noutput reg ctl_inc_limit6,\noutput reg ctl_bus_inc_oe,\noutput reg ctl_apin_mux,\noutput reg ctl_apin_mux2,\n\n// Module: bus/bus_control.v\noutput reg ctl_bus_ff_oe,\noutput reg ctl_bus_zero_oe,\n\n// Module: bus/bus_switch.v\noutput reg ctl_sw_1u,\noutput reg ctl_sw_1d,\noutput reg ctl_sw_2u,\noutput reg ctl_sw_2d,\noutput reg ctl_sw_mask543_en,\n\n// Module: bus/data_pins.v\noutput reg ctl_bus_db_we,\noutput reg ctl_bus_db_oe,\n"
  },
  {
    "path": "cpu/control/exec_zero.vh",
    "content": "// Automatically generated by genref.py\n\n// Module: control/decode_state.v\nctl_state_iy_set = 0;\nctl_state_ixiy_clr = 0;\nctl_state_ixiy_we = 0;\nctl_state_halt_set = 0;\nctl_state_tbl_ed_set = 0;\nctl_state_tbl_cb_set = 0;\nctl_state_alu = 0;\nctl_repeat_we = 0;\nctl_state_tbl_we = 0;\n\n// Module: control/interrupts.v\nctl_iff1_iff2 = 0;\nctl_iffx_we = 0;\nctl_iffx_bit = 0;\nctl_im_we = 0;\nctl_no_ints = 0;\n\n// Module: control/ir.v\nctl_ir_we = 0;\n\n// Module: control/memory_ifc.v\nctl_mRead = 0;\nctl_mWrite = 0;\nctl_iorw = 0;\n\n// Module: alu/alu_control.v\nctl_shift_en = 0;\nctl_daa_oe = 0;\nctl_alu_op_low = 0;\nctl_cond_short = 0;\nctl_alu_core_hf = 0;\nctl_eval_cond = 0;\nctl_66_oe = 0;\nctl_pf_sel = 0;\n\n// Module: alu/alu_select.v\nctl_alu_oe = 0;\nctl_alu_shift_oe = 0;\nctl_alu_op2_oe = 0;\nctl_alu_res_oe = 0;\nctl_alu_op1_oe = 0;\nctl_alu_bs_oe = 0;\nctl_alu_op1_sel_bus = 0;\nctl_alu_op1_sel_low = 0;\nctl_alu_op1_sel_zero = 0;\nctl_alu_op2_sel_zero = 0;\nctl_alu_op2_sel_bus = 0;\nctl_alu_op2_sel_lq = 0;\nctl_alu_sel_op2_neg = 0;\nctl_alu_sel_op2_high = 0;\nctl_alu_core_R = 0;\nctl_alu_core_V = 0;\nctl_alu_core_S = 0;\n\n// Module: alu/alu_flags.v\nctl_flags_oe = 0;\nctl_flags_bus = 0;\nctl_flags_alu = 0;\nctl_flags_nf_set = 0;\nctl_flags_cf_set = 0;\nctl_flags_cf_cpl = 0;\nctl_flags_cf_we = 0;\nctl_flags_sz_we = 0;\nctl_flags_xy_we = 0;\nctl_flags_hf_we = 0;\nctl_flags_pf_we = 0;\nctl_flags_nf_we = 0;\nctl_flags_cf2_we = 0;\nctl_flags_hf_cpl = 0;\nctl_flags_use_cf2 = 0;\nctl_flags_hf2_we = 0;\nctl_flags_nf_clr = 0;\nctl_alu_zero_16bit = 0;\nctl_flags_cf2_sel_shift = 0;\nctl_flags_cf2_sel_daa = 0;\n\n// Module: registers/reg_file.v\nctl_sw_4u = 0;\nctl_reg_in_hi = 0;\nctl_reg_in_lo = 0;\nctl_reg_out_lo = 0;\nctl_reg_out_hi = 0;\n\n// Module: registers/reg_control.v\nctl_reg_exx = 0;\nctl_reg_ex_af = 0;\nctl_reg_ex_de_hl = 0;\nctl_reg_use_sp = 0;\nctl_reg_sel_pc = 0;\nctl_reg_sel_ir = 0;\nctl_reg_sel_wz = 0;\nctl_reg_gp_we = 0;\nctl_reg_not_pc = 0;\nctl_reg_sys_we_lo = 0;\nctl_reg_sys_we_hi = 0;\nctl_reg_sys_we = 0;\nctl_sw_4d = 0;\nctl_reg_gp_hilo = 0;\nctl_reg_gp_sel = 0;\nctl_reg_sys_hilo = 0;\n\n// Module: bus/address_latch.v\nctl_inc_cy = 0;\nctl_inc_dec = 0;\nctl_al_we = 0;\nctl_inc_limit6 = 0;\nctl_bus_inc_oe = 0;\nctl_apin_mux = 0;\nctl_apin_mux2 = 0;\n\n// Module: bus/bus_control.v\nctl_bus_ff_oe = 0;\nctl_bus_zero_oe = 0;\n\n// Module: bus/bus_switch.v\nctl_sw_1u = 0;\nctl_sw_1d = 0;\nctl_sw_2u = 0;\nctl_sw_2d = 0;\nctl_sw_mask543_en = 0;\n\n// Module: bus/data_pins.v\nctl_bus_db_we = 0;\nctl_bus_db_oe = 0;\n"
  },
  {
    "path": "cpu/control/execute.bsf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  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12)(font \"Arial\" ))\n\t\t(text \"nextM\" (rect 211 1627 235 1639)(font \"Arial\" ))\n\t\t(line (pt 256 1632)(pt 240 1632)(line_width 1))\n\t)\n\t(port\n\t\t(pt 256 1648)\n\t\t(output)\n\t\t(text \"setM1\" (rect 0 0 23 12)(font \"Arial\" ))\n\t\t(text \"setM1\" (rect 212 1643 235 1655)(font \"Arial\" ))\n\t\t(line (pt 256 1648)(pt 240 1648)(line_width 1))\n\t)\n\t(port\n\t\t(pt 256 1664)\n\t\t(output)\n\t\t(text \"fFetch\" (rect 0 0 25 12)(font \"Arial\" ))\n\t\t(text \"fFetch\" (rect 210 1659 235 1671)(font \"Arial\" ))\n\t\t(line (pt 256 1664)(pt 240 1664)(line_width 1))\n\t)\n\t(port\n\t\t(pt 256 1680)\n\t\t(output)\n\t\t(text \"fMRead\" (rect 0 0 34 12)(font \"Arial\" ))\n\t\t(text \"fMRead\" (rect 201 1675 235 1687)(font \"Arial\" ))\n\t\t(line (pt 256 1680)(pt 240 1680)(line_width 1))\n\t)\n\t(port\n\t\t(pt 256 1696)\n\t\t(output)\n\t\t(text \"fMWrite\" (rect 0 0 34 12)(font \"Arial\" ))\n\t\t(text \"fMWrite\" (rect 201 1691 235 1703)(font \"Arial\" ))\n\t\t(line (pt 256 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  },
  {
    "path": "cpu/control/execute.v",
    "content": "//=============================================================================\n// This module implements the instruction execute state logic.\n//\n//  Copyright (C) 2014-2016  Goran Devic\n//\n//  This program is free software; you can redistribute it and/or modify it\n//  under the terms of the GNU General Public License as published by the Free\n//  Software Foundation; either version 2 of the License, or (at your option)\n//  any later version.\n//\n//  This program is distributed in the hope that it will be useful, but WITHOUT\n//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n//  more details.\n//\n//  You should have received a copy of the GNU General Public License along\n//  with this program; if not, write to the Free Software Foundation, Inc.,\n//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n//=============================================================================\n// Using a compiled format will include files generated by \"gencompile.py\" script\n// These files are a processed version of \"exec_matrix_compiled.vh\"\n// You would define this on Xilinx and undefine (comment out) on Altera\n`define USE_COMPILED_FORMAT\n\nmodule execute\n(\n    //----------------------------------------------------------\n    // Control signals generated by the instruction execution\n    //----------------------------------------------------------\n    `include \"exec_module.vh\"\n\n    output reg nextM,                   // Last M cycle of any instruction\n    output reg setM1,                   // Last T clock of any instruction\n    output reg fFetch,                  // Function: opcode fetch cycle (\"M1\")\n    output reg fMRead,                  // Function: memory read cycle\n    output reg fMWrite,                 // Function: memory write cycle\n    output reg fIORead,                 // Function: IO Read cycle\n    output reg fIOWrite,                // Function: IO Write cycle\n\n    //----------------------------------------------------------\n    // Inputs from the instruction decode PLA\n    //----------------------------------------------------------\n    input wire [104:0] pla,             // Statically decoded instructions\n\n    //----------------------------------------------------------\n    // Inputs from various blocks\n    //----------------------------------------------------------\n    input wire in_intr,                 // Servicing maskable interrupt\n    input wire in_nmi,                  // Servicing non-maskable interrupt\n    input wire in_halt,                 // Currently in HALT mode\n    input wire im1,                     // Interrupt Mode 1\n    input wire im2,                     // Interrupt Mode 2\n    input wire use_ixiy,                // Special decode signal\n    input wire flags_cond_true,         // Flags condition is true\n    input wire repeat_en,               // Enable repeat of a block instruction\n    input wire flags_zf,                // ZF to test a condition\n    input wire flags_nf,                // NF to test for subtraction\n    input wire flags_sf,                // SF to test for 8-bit sign of a value\n    input wire flags_cf,                // CF to set HF for CCF\n\n    //----------------------------------------------------------\n    // Machine and clock cycles\n    //----------------------------------------------------------\n    input wire M1,                      // Machine cycle #1\n    input wire M2,                      // Machine cycle #2\n    input wire M3,                      // Machine cycle #3\n    input wire M4,                      // Machine cycle #4\n    input wire M5,                      // Machine cycle #5\n    input wire T1,                      // T-cycle #1\n    input wire T2,                      // T-cycle #2\n    input wire T3,                      // T-cycle #3\n    input wire T4,                      // T-cycle #4\n    input wire T5,                      // T-cycle #5\n    input wire T6                       // T-cycle #6\n);\n\n// Detects unknown instructions by signalling the known ones\nreg validPLA;                           // Valid PLA asserts this reg\n// Activates a state machine to compute WZ=IX+d; takes 5T cycles\nreg ixy_d;                              // Compute WX=IX+d\n// Signals the setting of IX/IY prefix flags; inhibits clearing them\nreg setIXIY;                            // Set IX/IY flag at the next T cycle\n// Holds asserted by non-repeating versions of block instructions (LDI/CPI,...)\nreg nonRep;                             // Non-repeating block instruction\n// Suspends incrementing PC through address latch unless in HALT or interrupt mode\nreg pc_inc_hold;                        // Normally 0 unless in one of those modes\n\n//--------------------------------------------------------------\n// Define various shortcuts to field naming\n//--------------------------------------------------------------\n`define GP_REG_BC       2'h0\n`define GP_REG_DE       2'h1\n`define GP_REG_HL       2'h2\n`define GP_REG_AF       2'h3\n\n`define PFSEL_P         2'h0\n`define PFSEL_V         2'h1\n`define PFSEL_IFF2      2'h2\n`define PFSEL_REP       2'h3\n\n//--------------------------------------------------------------\n// Make available different bits and sections of the opcode byte\n//--------------------------------------------------------------\nwire op0 = pla[99];\nwire op1 = pla[100];\nwire op2 = pla[101];\nwire op3 = pla[102];\nwire op4 = pla[103];\nwire op5 = pla[104];\n\nwire [1:0] op21 = { pla[101], pla[100] };\nwire [1:0] op54 = { pla[104], pla[103] };\n\n//--------------------------------------------------------------\n// 8-bit register selections needs to swizzle mux for A and F\n//--------------------------------------------------------------\nwire rsel0 = op0 ^ (op1 & op2);\nwire rsel3 = op3 ^ (op4 & op5);\n\n`ifdef USE_COMPILED_FORMAT\n`include \"temp_wires.vh\"                // Define all temp wires used with compiled equations\n`endif\n\nalways @(*) // always_comb\nbegin\n    //-----------------------------------------------------------------------------\n    // Default assignment of all control outputs to 0 to prevent generating latches\n    //-----------------------------------------------------------------------------\n    `include \"exec_zero.vh\"             // Initial assignment to all ctl wires to zero\n\n    // Reset internal control regs\n    validPLA = 0;                       // Will be set by every *valid* PLA entry\n    nextM = 0;                          // Will be set to advance to the next M cycle\n    setM1 = 0;                          // Will be set on a last M/T cycle of an instruction\n\n    // Reset global machine cycle functions\n    fFetch = M1;                        // Fetch is aliased to M1\n    fMRead = 0; fMWrite = 0; fIORead = 0; fIOWrite = 0;\n    ixy_d = 0;\n    setIXIY = 0;\n    nonRep = 0;\n    pc_inc_hold = 0;\n\n    //-------------------------------------------------------------------------\n    // State-based signal assignment; code generated from Timings spreadsheet\n    //-------------------------------------------------------------------------\n`ifdef USE_COMPILED_FORMAT\n    `include \"exec_matrix_compiled.vh\"  // Compiled execution equations\n`else\n    `include \"exec_matrix.vh\"           // Execution statements in the original nested-if format\n`endif\n\n    // Needed by data bus 0 override logic, make only one bus writer active at any time\n    ctl_bus_db_oe = ctl_bus_db_oe & ~(ctl_bus_zero_oe | ctl_bus_ff_oe);\n\nend\n\nendmodule\n"
  },
  {
    "path": "cpu/control/gencompile.py",
    "content": "#!/usr/bin/env python3\n#\n# This script reads 'exec_matrix.vh' file and compiles it into an alternate format\n# that can be used with Xilinx toolchain.\n#\n# Xilinx synthesis tool is effectively not capable of processing that file.\n# Altera Quartus has no problems compiling it.\n#\n#-------------------------------------------------------------------------------\n#  Copyright (C) 2016  Goran Devic\n#\n#  This program is free software; you can redistribute it and/or modify it\n#  under the terms of the GNU General Public License as published by the Free\n#  Software Foundation; either version 2 of the License, or (at your option)\n#  any later version.\n#\n#  This program is distributed in the hope that it will be useful, but WITHOUT\n#  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n#  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n#  more details.\n#-------------------------------------------------------------------------------\nimport os\nimport io\nimport copy\nimport tokenize\nfrom io import BytesIO\nfrom tokenize import NAME, INDENT, DEDENT, ENCODING\n\n# Input file to process\nfname = \"exec_matrix.vh\"\n\n# Output file to contain compiled version of the input\noname = \"exec_matrix_compiled.vh\"\n\n# Output file to contain a list of temporary wires used by the compiled Verilog file\ntname = \"temp_wires.vh\"\n\n# Define a list of control signals that are 2-bits wide\nctls_wide = ['ctl_reg_gp_sel', 'ctl_reg_gp_hilo', 'ctl_reg_sys_hilo', 'ctl_pf_sel']\n\n# Help recognizing control signal names\ndef is_ctl(name):\n    return name.startswith('ctl_') or name=='validPLA' or name=='nextM' or name=='setM1' \\\n        or name=='fFetch' or name=='fMRead' or name=='fMWrite' or name=='fIORead' or name=='fIOWrite' \\\n        or name=='ixy_d' or name=='setIXIY' or name=='nonRep' or name=='pc_inc_hold'\n\ndef str2tok(s):\n    t = io.BytesIO(bytes(s.encode()))\n    return list(tokenize.tokenize(t.readline))[1:-1]\n\ndef tok2str(tokens):\n    line = [ tokens[n][m].string for n in range(len(tokens)) for m in range(len(tokens[n])) ]\n    return ''.join(line)\n\ndef get_rval(tokens, i):\n    assert (tokens[i+1].string=='=' or tokens[i+1].string=='|=')\n    paren = list(str2tok('()'))\n    rval = paren[:1]\n    while (tokens[i+2].string!=';'):\n        rval.append(tokens[i+2])\n        i += 1\n    rval.extend(paren[1:2])\n    return [rval]\n\ndef decomment(s):\n    i = s.find('//') # Remove trailing comments from a line\n    if i>=0:\n        return s[:i]\n    i = s.find('/*') # Remove comments within a line\n    j = s.find('*/')\n    if i>=0 and j>=0:\n        return decomment(s[:i] + s[j+2:])\n    return s\n\n#--------------------------------------------------------------------------------\n# Generate a sequential-or form for all control wires\n#--------------------------------------------------------------------------------\ndef sequential_or(f, t, tokens):\n    incond = False              # Inside an \"if\" condition state\n    cond = []                   # Condition nested lists\n    ccond = []                  # Currently scanned condition list\n    ctls = {}                   # Dictionary of control wires and their equations\n    ccwires = []                # List of wires at the current condition list level\n    i = 0                       # Current index into the tokens list\n    while i < len(tokens):\n        tok = tokens[i]\n        (toknum, tokval, _, _, _) = tok\n        if incond and not (toknum==NAME and tokval=='begin'):\n            if toknum != DEDENT and toknum != INDENT:\n                ccond.append(tok)\n        if toknum==NAME:\n            if tokval=='if':\n                incond = True\n            if tokval=='begin': # Push a condition list\n                incond = False\n                cond.append(copy.deepcopy(ccond))\n                ccond.clear()\n                ccwires.clear()\n            if tokval=='end': # Pop a condition list\n                cond.pop()\n            if is_ctl(tokval) and not incond:\n                rval = get_rval(tokens, i)\n                linesub = tok2str(cond)\n                rhs = tok2str(rval)\n                line = \"{0} = {0} | \".format(tokval)\n                if tokval in ccwires: # Check for duplicate assignments\n                    hint = [ cond[n][m].string for n in range(len(cond)) for m in range(len(cond[n])) ]\n                    print (\"WARNING: {0}: Multiple assignment of {1}\".format(''.join(hint), tokval))\n                ccwires.append(tokval) # Track this wire as assigned at this condition level\n                if tokval in ctls_wide:\n                    tr = linesub.translate(str.maketrans(dict.fromkeys('~','n'))) # Make temporary name\n                    tmpname = \"{0}_{1}_{2}\".format(tokval, tr.translate(str.maketrans(dict.fromkeys('[]()&',None))), len(ccwires))\n                    t.write(\"reg {0};\\n\".format(tmpname))\n                    line = \"{0} = {1};\\n\".format(tmpname, linesub) + line\n                    line += \"({{{0},{0}}}){1}\".format(tmpname, rhs)\n                else:\n                    line += linesub + rhs\n                line = line.replace(')(', ')&(')\n                line = line.replace('&&', '&')\n                line = line.replace('(1)&', '')\n                line = line.replace('&(1)', '')\n                i += len(rval[0])\n                f.write ('{0};\\n'.format(line))\n        i += 1\n\n#--------------------------------------------------------------------------------\ntokens = []\n# Input file which we are processing\nwith open(fname) as f:\n    lines = f.readlines()\n\nfor line in lines:\n    src = decomment(line)\n    src = bytes(src.encode())\n    src = io.BytesIO(src)\n    toklist = list(tokenize.tokenize(src.readline))\n    tokens.extend(toklist)\n\nwith open(oname, 'w') as f:\n    with open(tname, 'w') as t:\n        f.write(\"// Automatically generated by gencompile.py\\n\\n\")\n        t.write(\"// Automatically generated by gencompile.py\\n\\n\")\n        sequential_or(f, t, tokens)\n\n# Touch a file that includes 'exec_matrix_compiled.vh' to ensure it will recompile correctly\nos.utime(\"execute.v\", None)\n"
  },
  {
    "path": "cpu/control/genmatrix.py",
    "content": "#!/usr/bin/env python3\n#\n# This script reads A-Z80 instruction timing data from a spreadsheet text file\n# 'Timings.csv' (which is a TAB-delimited text file exported from 'Timings.xlsm')\n# and generates a Verilog include file defining the control block execution matrix.\n# Token keywords in the timing spreadsheet are substituted using a list of keys\n# defined in 'timing_macros.i'.\n#\n#-------------------------------------------------------------------------------\n#  Copyright (C) 2014,2016  Goran Devic\n#\n#  This program is free software; you can redistribute it and/or modify it\n#  under the terms of the GNU General Public License as published by the Free\n#  Software Foundation; either version 2 of the License, or (at your option)\n#  any later version.\n#\n#  This program is distributed in the hope that it will be useful, but WITHOUT\n#  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n#  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n#  more details.\n#-------------------------------------------------------------------------------\nimport string\nimport sys\nimport csv\nimport os\n\n# Input file (exported from 'Timings.xlsm'):\nfname = \"Timings.csv\"\n\n# Input file containing macro substitution keys\nkname = \"timing_macros.i\"\n\n# Set this to 1 if you want abbreviated matrix (no-action lines removed)\nabbr = 1\n\n# Set this to 0 if you want to strip all comments from the resulting file\ncomment = 1\n\n# Set this to 1 if you want debug $display() printout on each PLA line\ndebug = 0\n\n# Print this string in front of every line that starts with \"ctl_\". This helps\n# formatting the output to be more readable.\nctl_prefix = \"\\n\"+\" \"*19\n\n# Read in the content of the macro substitution file\nmacros = []\nwith open(kname, 'r') as f:\n    for line in f:\n        if len(line.strip())>0 and line[0]!='/':\n            # Wrap up non-starting //-style comments into /* ... */ so the\n            # line can be concatenated while preserving comments\n            i = line.find(\"//\")\n            if i>0:\n                if comment==1:\n                    macros.append( line.rstrip().replace(\"//\", \"/*\", 1) + \" */\" )\n                else:\n                    macros.append( line.rstrip()[0:i] )\n            else:\n                macros.append(line.rstrip())\n\n# List of errors / keys and macros that did not match. We stash them as we go\n# and then print at the end so it is easier to find them\nerrors = []\n\n# Returns a substitution string given the section name (key) and the macro token\n# This is done by simply traversing macro substitution list of lines, finding a\n# section that starts with a :key and copying the substitution lines verbatim.\ndef getSubst(key, token):\n    subst = []\n    multiline = False\n    validset = False\n    if key==\"Comments\":                 # Special case: ignore \"Comments\" column!\n        return \"\"\n    for l in macros:\n        if multiline==True:\n            # Multiline copies lines until a char at [0] is not a space\n            if len(l.strip())==0 or l[0]!=' ':\n                return '\\n' + \"\\n\".join(subst).rstrip()\n            else:\n                subst.append(l.rstrip())\n        lx = l.split(' ')               # Split the string and then ignore (duplicate)\n        lx = list(filter(None, lx))     # spaces in the list left by the split()\n        if l.startswith(\":\"):           # Find and recognize a matching set (key) section\n            if validset:                # Error if there is a new section going from the macthing one\n                break                   # meaning we did not find our macro in there\n            if l[1:]==key:\n                validset = True\n        elif validset and lx[0]==token:\n            if len(lx)==1:\n                return \"\"\n            if lx[1]=='\\\\':             # Multi-line macro state starts with '\\' character\n                multiline = True\n                continue\n            lx.pop(0)\n            s = \" \".join(lx)\n            return ' ' + s.strip()\n    err = \"{0} not in {1}\".format(token, key)\n    if err not in errors:\n        errors.append(err)\n    return \" --- {0} ?? {1} --- \".format(token, key)\n\n# Read the content of a file and using the csv reader and remove any quotes from the input fields\ncontent = []                            # Content of the spreadsheet timing file\nwith open(fname, 'r') as csvFile:\n    reader = csv.reader(csvFile, delimiter='\\t', quotechar='\"')\n    for row in reader:\n        content.append('\\t'.join(row))\n\n# The first line is special: it contains names of sets for our macro substitutions\ntkeys = {}                              # Spreadsheet table column keys\ntokens = content.pop(0).split('\\t')\nfor col in range(len(tokens)):\n    if len(tokens[col])==0:\n        continue\n    tkeys[col] = tokens[col]\n\n# Process each line separately (stateless processor)\nimatrix = []    # Verilog execution matrix code\nfor line in content:\n    col = line.split('\\t')              # Split the string into a list of columns\n    col_clean = list(filter(None, col)) # Removed all empty fields (between the separators)\n    if len(col_clean)==0:               # Ignore completely empty lines\n        continue\n\n    if col_clean[0].startswith('//') and comment==1:\n        imatrix.append(col_clean[0])    # Optionally print comment lines\n\n    if col_clean[0].startswith(\"#end\"): # Print the end of a condition\n        imatrix.append(\"end\\n\")\n\n    if col_clean[0].startswith('#if'):  # Print the start of a condition\n        s = col_clean[0]\n        tag = s.find(\":\")\n        condition = s[4:tag]\n        imatrix.append(\"if ({0}) begin\".format(condition.strip()))\n        if debug and len(s[tag:])>1:    # Print only in debug and there is something to print\n            imatrix.append(\"    $display(\\\"{0}\\\");\".format(s[4:]))\n\n    # We recognize 2 kinds of timing statements based on the starting characters:\n    # \"#0\"..        common timings using M and T cycles (M being optional)\n    # \"#always\"     timing that does not depend on M and T cycles (ex. ALU operations)\n    if col_clean[0].startswith('#0') or col_clean[0].startswith('#always'):\n        # M and T states are hard-coded in the table at the index 1 and 2\n        if col_clean[0].startswith('#0'):\n            if col[1]=='?':     # M is optional, use '?' to skip it\n                state = \"    if (T{0}) begin\".format(col[2])\n            else:\n                state = \"    if (M{0} & T{1}) begin\".format(col[1], col[2])\n        else:\n            state = \"    begin\"\n\n        # Loop over all other columns and perform verbatim substitution\n        action = \"\"\n        for i in range(3,len(col)):\n            # There may be multiple tokens separated by commas\n            tokList = col[i].strip().split(',')\n            tokList = list(filter(None, tokList)) # Filter out empty lines\n            for token in tokList:\n                token = token.strip()\n                if i in tkeys and len(token)>0:\n                    macro = getSubst(tkeys[i], token)\n                    if macro.strip().startswith(\"ctl_\"):\n                        action += ctl_prefix\n                    action += macro\n                    if state.find(\"ERROR\")>=0:\n                        print (\"{0} {1}\".format(state, action))\n                        break\n\n        # Complete and write out a line\n        if abbr and len(action)==0:\n            continue\n        imatrix.append(\"{0}{1} end\".format(state, action))\n\n# Create a file containing the logic matrix code\nwith open('exec_matrix.vh', 'w') as file:\n    if comment==1:\n        file.write(\"// Automatically generated by genmatrix.py\\n\\n\")\n    # If there were errors, print them first (and output to the console)\n    if len(errors)>0:\n        for error in errors:\n            print (error)\n            file.write(error + \"\\n\")\n        file.write(\"-\" * 80 + \"\\n\")\n    for item in imatrix:\n        file.write(\"{}\\n\".format(item))\n\n# Touch a file that includes 'exec_matrix.vh' to ensure it will recompile correctly\nos.utime(\"execute.v\", None)\n"
  },
  {
    "path": "cpu/control/genref.py",
    "content": "#!/usr/bin/env python3\n#\n# This script reads and parses selected Verilog and SystemVerilog modules\n# and generates a set of Verilog include files for the control block.\n#\n#-------------------------------------------------------------------------------\n#  Copyright (C) 2014  Goran Devic\n#\n#  This program is free software; you can redistribute it and/or modify it\n#  under the terms of the GNU General Public License as published by the Free\n#  Software Foundation; either version 2 of the License, or (at your option)\n#  any later version.\n#\n#  This program is distributed in the hope that it will be useful, but WITHOUT\n#  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n#  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n#  more details.\n#-------------------------------------------------------------------------------\nimport glob\nimport os\n\nwith open('../top-level-files.txt') as f:\n    files = f.read().splitlines()\n\n# Create 2 files that should be included by the execution engine:\n# 1. A file listing all control signals\n# 2. A file containing statements initializing control signals to zero\nwith open('exec_module.vh', 'w') as file1, open('exec_zero.vh', 'w') as file0:\n    file1.write(\"// Automatically generated by genref.py\\n\")\n    file0.write(\"// Automatically generated by genref.py\\n\")\n\n# Read and parse each file from the list of input files\nfor infile in files:\n    wires = []\n    if not os.path.isfile('../' + infile):\n        continue\n    with open('../' + infile, \"r\") as f:\n        for line in f:\n            info = line.split()\n            # input wire register case\n            if len(info)>2 and info[0]==\"input\" and info[1]==\"wire\" and info[2].startswith(\"ctl_\"):\n                wires.append(info[2].strip(';,'))\n            # input wire bus case (ex. \"[1:0]\")\n            if len(info)>3 and info[0]==\"input\" and info[1]==\"wire\" and info[2].startswith(\"[\") and info[3].startswith(\"ctl_\"):\n                wires.append(info[2] + \" \" + info[3].strip(';,'))\n\n    if len(wires)>0:\n        with open('exec_module.vh', 'a') as file1, open('exec_zero.vh', 'a') as file0:\n            print (\"MODULE:\", infile)\n            file0.write(\"\\n// Module: \" + infile + \"\\n\")\n            file1.write(\"\\n// Module: \" + infile + \"\\n\")\n            for wire in wires:\n                print (\"  \", wire)\n                file1.write(\"output reg \" + wire + \",\\n\")\n                if \"[\" in wire:\n                    file0.write(wire.split()[1] + \" = 0;\\n\")\n                else:\n                    file0.write(wire + \" = 0;\\n\")\n\n# Touch a file that includes 'exec_module.vh' and 'exec_zero.vh' to ensure it will recompile correctly\nos.utime(\"execute.v\", None)\n"
  },
  {
    "path": "cpu/control/interrupts.bdf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  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  },
  {
    "path": "cpu/control/interrupts.bsf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"symbol\" (version \"1.2\"))\n(symbol\n\t(rect 64 64 216 288)\n\t(text \"interrupts\" (rect 5 0 59 14)(font \"Arial\" (font_size 8)))\n\t(text \"inst\" (rect 8 208 25 220)(font \"Arial\" ))\n\t(port\n\t\t(pt 0 32)\n\t\t(input)\n\t\t(text \"ctl_iff1_iff2\" (rect 0 0 64 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"ctl_iff1_iff2\" (rect 21 27 85 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 32)(pt 16 32))\n\t)\n\t(port\n\t\t(pt 0 48)\n\t\t(input)\n\t\t(text \"ctl_iffx_we\" (rect 0 0 64 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"ctl_iffx_we\" (rect 21 43 85 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 48)(pt 16 48))\n\t)\n\t(port\n\t\t(pt 0 64)\n\t\t(input)\n\t\t(text \"ctl_iffx_bit\" (rect 0 0 59 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"ctl_iffx_bit\" (rect 21 59 80 73)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 64)(pt 16 64))\n\t)\n\t(port\n\t\t(pt 0 80)\n\t\t(input)\n\t\t(text \"nmi\" (rect 0 0 18 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"nmi\" (rect 21 75 39 89)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 80)(pt 16 80))\n\t)\n\t(port\n\t\t(pt 0 96)\n\t\t(input)\n\t\t(text \"intr\" (rect 0 0 17 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"intr\" (rect 21 91 38 105)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 96)(pt 16 96))\n\t)\n\t(port\n\t\t(pt 0 112)\n\t\t(input)\n\t\t(text \"setM1\" (rect 0 0 34 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"setM1\" (rect 21 107 55 121)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 112)(pt 16 112))\n\t)\n\t(port\n\t\t(pt 0 128)\n\t\t(input)\n\t\t(text \"ctl_no_ints\" (rect 0 0 61 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"ctl_no_ints\" (rect 21 123 82 137)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 128)(pt 16 128))\n\t)\n\t(port\n\t\t(pt 0 144)\n\t\t(input)\n\t\t(text \"db[1..0]\" (rect 0 0 42 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"db[1..0]\" (rect 21 139 63 153)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 144)(pt 16 144)(line_width 3))\n\t)\n\t(port\n\t\t(pt 0 160)\n\t\t(input)\n\t\t(text \"clk\" (rect 0 0 15 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"clk\" (rect 21 155 36 169)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 160)(pt 16 160))\n\t)\n\t(port\n\t\t(pt 0 176)\n\t\t(input)\n\t\t(text \"ctl_im_we\" (rect 0 0 57 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"ctl_im_we\" (rect 21 171 78 185)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 176)(pt 16 176))\n\t)\n\t(port\n\t\t(pt 0 192)\n\t\t(input)\n\t\t(text \"nreset\" (rect 0 0 36 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"nreset\" (rect 21 187 57 201)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 192)(pt 16 192))\n\t)\n\t(port\n\t\t(pt 152 32)\n\t\t(output)\n\t\t(text \"iff2\" (rect 0 0 18 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"iff2\" (rect 113 27 131 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 152 32)(pt 136 32))\n\t)\n\t(port\n\t\t(pt 152 48)\n\t\t(output)\n\t\t(text \"in_nmi\" (rect 0 0 35 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"in_nmi\" (rect 96 43 131 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 152 48)(pt 136 48))\n\t)\n\t(port\n\t\t(pt 152 64)\n\t\t(output)\n\t\t(text \"in_intr\" (rect 0 0 34 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"in_intr\" (rect 97 59 131 73)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 152 64)(pt 136 64))\n\t)\n\t(port\n\t\t(pt 152 80)\n\t\t(output)\n\t\t(text \"im1\" (rect 0 0 18 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"im1\" (rect 113 75 131 89)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 152 80)(pt 136 80))\n\t)\n\t(port\n\t\t(pt 152 96)\n\t\t(output)\n\t\t(text \"im2\" (rect 0 0 18 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"im2\" (rect 113 91 131 105)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 152 96)(pt 136 96))\n\t)\n\t(drawing\n\t\t(rectangle (rect 16 16 136 208))\n\t)\n)\n"
  },
  {
    "path": "cpu/control/interrupts.v",
    "content": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and other software and tools, and its AMPP partner logic \n// functions, and any output files from any of the foregoing \n// (including device programming or simulation files), and any \n// associated documentation or information are expressly subject \n// to the terms and conditions of the Altera Program License \n// Subscription Agreement, Altera MegaCore Function License \n// Agreement, or other applicable license agreement, including, \n// without limitation, that your use is for the sole purpose of \n// programming logic devices manufactured by Altera and sold by \n// Altera or its authorized distributors.  Please refer to the \n// applicable agreement for further details.\n\n// PROGRAM\t\t\"Quartus II 64-Bit\"\n// VERSION\t\t\"Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\"\n// CREATED\t\t\"Sat Feb 13 19:23:03 2016\"\n\nmodule interrupts(\n\tctl_iff1_iff2,\n\tnmi,\n\tsetM1,\n\tintr,\n\tctl_iffx_we,\n\tctl_iffx_bit,\n\tctl_im_we,\n\tclk,\n\tctl_no_ints,\n\tnreset,\n\tdb,\n\tiff2,\n\tim1,\n\tim2,\n\tin_nmi,\n\tin_intr\n);\n\n\ninput wire\tctl_iff1_iff2;\ninput wire\tnmi;\ninput wire\tsetM1;\ninput wire\tintr;\ninput wire\tctl_iffx_we;\ninput wire\tctl_iffx_bit;\ninput wire\tctl_im_we;\ninput wire\tclk;\ninput wire\tctl_no_ints;\ninput wire\tnreset;\ninput wire\t[1:0] db;\noutput wire\tiff2;\noutput reg\tim1;\noutput reg\tim2;\noutput wire\tin_nmi;\noutput wire\tin_intr;\n\nreg\tiff1;\nwire\tin_intr_ALTERA_SYNTHESIZED;\nreg\tin_nmi_ALTERA_SYNTHESIZED;\nreg\tint_armed;\nreg\tnmi_armed;\nwire\ttest1;\nwire\tSYNTHESIZED_WIRE_0;\nreg\tDFFE_instIFF2;\nwire\tSYNTHESIZED_WIRE_1;\nwire\tSYNTHESIZED_WIRE_2;\nwire\tSYNTHESIZED_WIRE_3;\nwire\tSYNTHESIZED_WIRE_4;\nwire\tSYNTHESIZED_WIRE_5;\nreg\tDFFE_inst44;\nwire\tSYNTHESIZED_WIRE_21;\nwire\tSYNTHESIZED_WIRE_7;\nwire\tSYNTHESIZED_WIRE_8;\nwire\tSYNTHESIZED_WIRE_9;\nwire\tSYNTHESIZED_WIRE_10;\nwire\tSYNTHESIZED_WIRE_11;\nwire\tSYNTHESIZED_WIRE_12;\nwire\tSYNTHESIZED_WIRE_13;\nwire\tSYNTHESIZED_WIRE_14;\nwire\tSYNTHESIZED_WIRE_15;\nwire\tSYNTHESIZED_WIRE_16;\nwire\tSYNTHESIZED_WIRE_17;\nwire\tSYNTHESIZED_WIRE_19;\nwire\tSYNTHESIZED_WIRE_20;\n\nassign\tiff2 = DFFE_instIFF2;\nassign\tSYNTHESIZED_WIRE_10 = 1;\n\n\n\nassign\tSYNTHESIZED_WIRE_2 = ctl_iffx_bit & SYNTHESIZED_WIRE_0;\n\nassign\tSYNTHESIZED_WIRE_1 = ctl_iff1_iff2 & DFFE_instIFF2;\n\nassign\tSYNTHESIZED_WIRE_16 = SYNTHESIZED_WIRE_1 | SYNTHESIZED_WIRE_2;\n\nassign\tSYNTHESIZED_WIRE_17 = ctl_iffx_we | ctl_iff1_iff2;\n\nassign\tSYNTHESIZED_WIRE_21 = SYNTHESIZED_WIRE_3 & nreset;\n\nassign\tSYNTHESIZED_WIRE_0 =  ~ctl_iff1_iff2;\n\nassign\tSYNTHESIZED_WIRE_4 =  ~db[0];\n\nassign\tSYNTHESIZED_WIRE_5 =  ~in_nmi_ALTERA_SYNTHESIZED;\n\nassign\tSYNTHESIZED_WIRE_20 = db[1] & db[0];\n\nassign\tSYNTHESIZED_WIRE_19 = db[1] & SYNTHESIZED_WIRE_4;\n\n\nassign\tin_intr_ALTERA_SYNTHESIZED = SYNTHESIZED_WIRE_5 & DFFE_inst44;\n\nassign\tSYNTHESIZED_WIRE_15 = SYNTHESIZED_WIRE_21 & SYNTHESIZED_WIRE_7;\n\nassign\tSYNTHESIZED_WIRE_13 = iff1 & intr;\n\nassign\ttest1 = setM1 & SYNTHESIZED_WIRE_8;\n\n\nalways@(posedge nmi or negedge SYNTHESIZED_WIRE_9)\nbegin\nif (!SYNTHESIZED_WIRE_9)\n\tbegin\n\tnmi_armed <= 0;\n\tend\nelse\n\tbegin\n\tnmi_armed <= SYNTHESIZED_WIRE_10;\n\tend\nend\n\nassign\tSYNTHESIZED_WIRE_12 = SYNTHESIZED_WIRE_11 & nreset;\n\n\nalways@(posedge clk or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tin_nmi_ALTERA_SYNTHESIZED <= 0;\n\tend\nelse\nif (test1)\n\tbegin\n\tin_nmi_ALTERA_SYNTHESIZED <= nmi_armed;\n\tend\nend\n\n\nalways@(posedge clk or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tDFFE_inst44 <= 0;\n\tend\nelse\nif (test1)\n\tbegin\n\tDFFE_inst44 <= int_armed;\n\tend\nend\n\n\nalways@(posedge clk or negedge SYNTHESIZED_WIRE_12)\nbegin\nif (!SYNTHESIZED_WIRE_12)\n\tbegin\n\tint_armed <= 0;\n\tend\nelse\n\tbegin\n\tint_armed <= SYNTHESIZED_WIRE_13;\n\tend\nend\n\nassign\tSYNTHESIZED_WIRE_9 = SYNTHESIZED_WIRE_14 & nreset;\n\nassign\tSYNTHESIZED_WIRE_8 =  ~ctl_no_ints;\n\n\nalways@(posedge clk or negedge SYNTHESIZED_WIRE_15)\nbegin\nif (!SYNTHESIZED_WIRE_15)\n\tbegin\n\tiff1 <= 0;\n\tend\nelse\nif (SYNTHESIZED_WIRE_17)\n\tbegin\n\tiff1 <= SYNTHESIZED_WIRE_16;\n\tend\nend\n\n\nalways@(posedge clk or negedge SYNTHESIZED_WIRE_21)\nbegin\nif (!SYNTHESIZED_WIRE_21)\n\tbegin\n\tDFFE_instIFF2 <= 0;\n\tend\nelse\nif (ctl_iffx_we)\n\tbegin\n\tDFFE_instIFF2 <= ctl_iffx_bit;\n\tend\nend\n\n\nalways@(posedge clk or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tim1 <= 0;\n\tend\nelse\nif (ctl_im_we)\n\tbegin\n\tim1 <= SYNTHESIZED_WIRE_19;\n\tend\nend\n\n\nalways@(posedge clk or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tim2 <= 0;\n\tend\nelse\nif (ctl_im_we)\n\tbegin\n\tim2 <= SYNTHESIZED_WIRE_20;\n\tend\nend\n\nassign\tSYNTHESIZED_WIRE_3 =  ~in_intr_ALTERA_SYNTHESIZED;\n\nassign\tSYNTHESIZED_WIRE_11 =  ~in_intr_ALTERA_SYNTHESIZED;\n\nassign\tSYNTHESIZED_WIRE_7 =  ~in_nmi_ALTERA_SYNTHESIZED;\n\nassign\tSYNTHESIZED_WIRE_14 =  ~in_nmi_ALTERA_SYNTHESIZED;\n\nassign\tin_nmi = in_nmi_ALTERA_SYNTHESIZED;\nassign\tin_intr = in_intr_ALTERA_SYNTHESIZED;\n\nendmodule\n"
  },
  {
    "path": "cpu/control/ir.bdf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"graphic\" (version \"1.4\"))\n(pin\n\t(input)\n\t(rect 40 96 216 112)\n\t(text \"INPUT\" (rect 133 0 161 10)(font \"Arial\" (font_size 6)))\n\t(text \"ctl_ir_we\" (rect 9 0 51 12)(font \"Arial\" ))\n\t(pt 176 8)\n\t(drawing\n\t\t(line (pt 92 12)(pt 117 12))\n\t\t(line (pt 92 4)(pt 117 4))\n\t\t(line (pt 121 8)(pt 176 8))\n\t\t(line (pt 92 12)(pt 92 4))\n\t\t(line (pt 117 4)(pt 121 8))\n\t\t(line (pt 117 12)(pt 121 8))\n\t)\n\t(text \"VCC\" (rect 136 7 156 17)(font \"Arial\" (font_size 6)))\n)\n(pin\n\t(input)\n\t(rect 40 48 216 64)\n\t(text \"INPUT\" (rect 133 0 161 10)(font \"Arial\" (font_size 6)))\n\t(text \"db[7..0]\" (rect 9 0 46 12)(font \"Arial\" ))\n\t(pt 176 8)\n\t(drawing\n\t\t(line (pt 92 12)(pt 117 12))\n\t\t(line (pt 92 4)(pt 117 4))\n\t\t(line (pt 121 8)(pt 176 8))\n\t\t(line (pt 92 12)(pt 92 4))\n\t\t(line (pt 117 4)(pt 121 8))\n\t\t(line (pt 117 12)(pt 121 8))\n\t)\n\t(text \"VCC\" (rect 136 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  },
  {
    "path": "cpu/control/ir.bsf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"symbol\" (version \"1.2\"))\n(symbol\n\t(rect 16 16 224 144)\n\t(text \"ir\" (rect 5 0 12 14)(font \"Arial\" (font_size 8)))\n\t(text \"inst\" (rect 8 112 25 124)(font \"Arial\" ))\n\t(port\n\t\t(pt 0 32)\n\t\t(input)\n\t\t(text \"db[7..0]\" (rect 0 0 42 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"db[7..0]\" (rect 21 27 63 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 32)(pt 16 32)(line_width 3))\n\t)\n\t(port\n\t\t(pt 0 48)\n\t\t(input)\n\t\t(text \"clk\" (rect 0 0 15 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"clk\" (rect 21 43 36 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 48)(pt 16 48))\n\t)\n\t(port\n\t\t(pt 0 64)\n\t\t(input)\n\t\t(text \"ctl_ir_we\" (rect 0 0 53 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"ctl_ir_we\" (rect 21 59 74 73)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 64)(pt 16 64))\n\t)\n\t(port\n\t\t(pt 0 80)\n\t\t(input)\n\t\t(text \"nhold_clk_wait\" (rect 0 0 84 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"nhold_clk_wait\" (rect 21 75 105 89)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 80)(pt 16 80))\n\t)\n\t(port\n\t\t(pt 0 96)\n\t\t(input)\n\t\t(text \"nreset\" (rect 0 0 36 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"nreset\" (rect 21 91 57 105)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 96)(pt 16 96))\n\t)\n\t(port\n\t\t(pt 208 32)\n\t\t(output)\n\t\t(text \"opcode[7..0]\" (rect 0 0 70 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"opcode[7..0]\" (rect 117 27 187 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 208 32)(pt 192 32)(line_width 3))\n\t)\n\t(drawing\n\t\t(rectangle (rect 16 16 192 112))\n\t)\n)\n"
  },
  {
    "path": "cpu/control/ir.v",
    "content": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and other software and tools, and its AMPP partner logic \n// functions, and any output files from any of the foregoing \n// (including device programming or simulation files), and any \n// associated documentation or information are expressly subject \n// to the terms and conditions of the Altera Program License \n// Subscription Agreement, Altera MegaCore Function License \n// Agreement, or other applicable license agreement, including, \n// without limitation, that your use is for the sole purpose of \n// programming logic devices manufactured by Altera and sold by \n// Altera or its authorized distributors.  Please refer to the \n// applicable agreement for further details.\n\n// PROGRAM\t\t\"Quartus II 64-Bit\"\n// VERSION\t\t\"Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\"\n// CREATED\t\t\"Sat Dec 10 08:56:46 2016\"\n\nmodule ir(\n\tctl_ir_we,\n\tclk,\n\tnreset,\n\tnhold_clk_wait,\n\tdb,\n\topcode\n);\n\n\ninput wire\tctl_ir_we;\ninput wire\tclk;\ninput wire\tnreset;\ninput wire\tnhold_clk_wait;\ninput wire\t[7:0] db;\noutput reg\t[7:0] opcode;\n\nwire\tSYNTHESIZED_WIRE_0;\n\n\n\n\nassign\tSYNTHESIZED_WIRE_0 = ctl_ir_we & nhold_clk_wait;\n\n\nalways@(posedge clk or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\topcode[7:0] <= 8'b00000000;\n\tend\nelse\nif (SYNTHESIZED_WIRE_0)\n\tbegin\n\topcode[7:0] <= db[7:0];\n\tend\nend\n\n\nendmodule\n"
  },
  {
    "path": "cpu/control/memory_ifc.bdf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  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  },
  {
    "path": "cpu/control/memory_ifc.bsf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"symbol\" (version \"1.2\"))\n(symbol\n\t(rect 16 16 224 272)\n\t(text \"memory_ifc\" (rect 5 0 71 14)(font \"Arial\" (font_size 8)))\n\t(text \"inst\" (rect 8 240 25 252)(font \"Arial\" ))\n\t(port\n\t\t(pt 0 32)\n\t\t(input)\n\t\t(text \"nM1_int\" (rect 0 0 43 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"nM1_int\" (rect 21 27 64 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 32)(pt 16 32))\n\t)\n\t(port\n\t\t(pt 0 48)\n\t\t(input)\n\t\t(text \"clk\" (rect 0 0 15 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"clk\" (rect 21 43 36 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 48)(pt 16 48))\n\t)\n\t(port\n\t\t(pt 0 64)\n\t\t(input)\n\t\t(text \"nreset\" (rect 0 0 36 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"nreset\" (rect 21 59 57 73)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 64)(pt 16 64))\n\t)\n\t(port\n\t\t(pt 0 80)\n\t\t(input)\n\t\t(text \"setM1\" (rect 0 0 34 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"setM1\" (rect 21 75 55 89)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 80)(pt 16 80))\n\t)\n\t(port\n\t\t(pt 0 96)\n\t\t(input)\n\t\t(text \"timings_en\" (rect 0 0 60 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"timings_en\" (rect 21 91 81 105)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 96)(pt 16 96))\n\t)\n\t(port\n\t\t(pt 0 112)\n\t\t(input)\n\t\t(text \"in_intr\" (rect 0 0 34 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"in_intr\" (rect 21 107 55 121)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 112)(pt 16 112))\n\t)\n\t(port\n\t\t(pt 0 128)\n\t\t(input)\n\t\t(text \"ctl_mRead\" (rect 0 0 59 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"ctl_mRead\" (rect 21 123 80 137)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 128)(pt 16 128))\n\t)\n\t(port\n\t\t(pt 0 144)\n\t\t(input)\n\t\t(text \"ctl_mWrite\" (rect 0 0 59 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"ctl_mWrite\" (rect 21 139 80 153)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 144)(pt 16 144))\n\t)\n\t(port\n\t\t(pt 0 160)\n\t\t(input)\n\t\t(text \"ctl_iorw\" (rect 0 0 46 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"ctl_iorw\" (rect 21 155 67 169)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 160)(pt 16 160))\n\t)\n\t(port\n\t\t(pt 0 176)\n\t\t(input)\n\t\t(text \"fIORead\" (rect 0 0 46 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"fIORead\" (rect 21 171 67 185)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 176)(pt 16 176))\n\t)\n\t(port\n\t\t(pt 0 192)\n\t\t(input)\n\t\t(text \"fIOWrite\" (rect 0 0 46 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"fIOWrite\" (rect 21 187 67 201)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 192)(pt 16 192))\n\t)\n\t(port\n\t\t(pt 0 208)\n\t\t(input)\n\t\t(text \"iorq_Tw\" (rect 0 0 47 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"iorq_Tw\" (rect 21 203 68 217)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 208)(pt 16 208))\n\t)\n\t(port\n\t\t(pt 0 224)\n\t\t(input)\n\t\t(text \"nhold_clk_wait\" (rect 0 0 84 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"nhold_clk_wait\" (rect 21 219 105 233)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 224)(pt 16 224))\n\t)\n\t(port\n\t\t(pt 208 32)\n\t\t(output)\n\t\t(text \"nRFSH_out\" (rect 0 0 63 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"nRFSH_out\" (rect 124 27 187 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 208 32)(pt 192 32))\n\t)\n\t(port\n\t\t(pt 208 48)\n\t\t(output)\n\t\t(text \"nM1_out\" (rect 0 0 48 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"nM1_out\" (rect 139 43 187 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 208 48)(pt 192 48))\n\t)\n\t(port\n\t\t(pt 208 64)\n\t\t(output)\n\t\t(text \"nMREQ_out\" (rect 0 0 66 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"nMREQ_out\" (rect 121 59 187 73)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 208 64)(pt 192 64))\n\t)\n\t(port\n\t\t(pt 208 80)\n\t\t(output)\n\t\t(text \"wait_m1\" (rect 0 0 48 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"wait_m1\" (rect 139 75 187 89)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 208 80)(pt 192 80))\n\t)\n\t(port\n\t\t(pt 208 96)\n\t\t(output)\n\t\t(text \"nRD_out\" (rect 0 0 48 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"nRD_out\" (rect 139 91 187 105)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 208 96)(pt 192 96))\n\t)\n\t(port\n\t\t(pt 208 112)\n\t\t(output)\n\t\t(text \"nWR_out\" (rect 0 0 51 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"nWR_out\" (rect 136 107 187 121)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 208 112)(pt 192 112))\n\t)\n\t(port\n\t\t(pt 208 128)\n\t\t(output)\n\t\t(text \"nIORQ_out\" (rect 0 0 61 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"nIORQ_out\" (rect 126 123 187 137)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 208 128)(pt 192 128))\n\t)\n\t(port\n\t\t(pt 208 144)\n\t\t(output)\n\t\t(text \"latch_wait\" (rect 0 0 59 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"latch_wait\" (rect 128 139 187 153)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 208 144)(pt 192 144))\n\t)\n\t(drawing\n\t\t(rectangle (rect 16 16 192 240))\n\t)\n)\n"
  },
  {
    "path": "cpu/control/memory_ifc.v",
    "content": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and other software and tools, and its AMPP partner logic \n// functions, and any output files from any of the foregoing \n// (including device programming or simulation files), and any \n// associated documentation or information are expressly subject \n// to the terms and conditions of the Altera Program License \n// Subscription Agreement, Altera MegaCore Function License \n// Agreement, or other applicable license agreement, including, \n// without limitation, that your use is for the sole purpose of \n// programming logic devices manufactured by Altera and sold by \n// Altera or its authorized distributors.  Please refer to the \n// applicable agreement for further details.\n\n// PROGRAM\t\t\"Quartus II 64-Bit\"\n// VERSION\t\t\"Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\"\n// CREATED\t\t\"Sun Dec 09 19:14:29 2018\"\n\nmodule memory_ifc(\n\tclk,\n\tnM1_int,\n\tctl_mRead,\n\tctl_mWrite,\n\tin_intr,\n\tnreset,\n\tfIORead,\n\tfIOWrite,\n\tsetM1,\n\tctl_iorw,\n\ttimings_en,\n\tiorq_Tw,\n\tnhold_clk_wait,\n\tnM1_out,\n\tnRFSH_out,\n\tnMREQ_out,\n\tnRD_out,\n\tnWR_out,\n\tnIORQ_out,\n\tlatch_wait,\n\twait_m1\n);\n\n\ninput wire\tclk;\ninput wire\tnM1_int;\ninput wire\tctl_mRead;\ninput wire\tctl_mWrite;\ninput wire\tin_intr;\ninput wire\tnreset;\ninput wire\tfIORead;\ninput wire\tfIOWrite;\ninput wire\tsetM1;\ninput wire\tctl_iorw;\ninput wire\ttimings_en;\ninput wire\tiorq_Tw;\ninput wire\tnhold_clk_wait;\noutput wire\tnM1_out;\noutput wire\tnRFSH_out;\noutput wire\tnMREQ_out;\noutput wire\tnRD_out;\noutput wire\tnWR_out;\noutput wire\tnIORQ_out;\noutput wire\tlatch_wait;\noutput wire\twait_m1;\n\nwire\tintr_iorq;\nwire\tioRead;\nwire\tiorq;\nwire\tioWrite;\nwire\tm1_mreq;\nwire\tmrd_mreq;\nwire\tmwr_mreq;\nreg\tmwr_wr;\nwire\tnMEMRQ_int;\nwire\tnq2;\nreg\tq1;\nreg\tq2;\nwire\twait_io;\nreg\twait_iorq;\nreg\twait_iorqinta;\nreg\twait_m_ALTERA_SYNTHESIZED1;\nreg\twait_mrd;\nreg\twait_mwr;\nwire\tSYNTHESIZED_WIRE_0;\nreg\tDFFE_m1_ff3;\nwire\tSYNTHESIZED_WIRE_1;\nreg\tDFFE_iorq_ff4;\nreg\tSYNTHESIZED_WIRE_15;\nreg\tDFFE_mrd_ff3;\nreg\tDFFE_intr_ff3;\nwire\tSYNTHESIZED_WIRE_2;\nreg\tSYNTHESIZED_WIRE_16;\nwire\tSYNTHESIZED_WIRE_3;\nreg\tSYNTHESIZED_WIRE_17;\nwire\tSYNTHESIZED_WIRE_18;\nreg\tDFFE_iorq_ff1;\nreg\tDFFE_m1_ff1;\nreg\tDFFE_mrd_ff1;\nreg\tDFFE_mwr_ff1;\nreg\tDFFE_mreq_ff2;\n\n\n\n\nassign\tnMREQ_out = SYNTHESIZED_WIRE_0 & nMEMRQ_int;\n\nassign\tioRead = iorq & fIORead;\n\nassign\tSYNTHESIZED_WIRE_1 = ~(DFFE_m1_ff3 | wait_m_ALTERA_SYNTHESIZED1);\n\nassign\tm1_mreq = ~(in_intr | SYNTHESIZED_WIRE_1);\n\nassign\tiorq = wait_iorq | DFFE_iorq_ff4 | SYNTHESIZED_WIRE_15;\n\nassign\tioWrite = iorq & fIOWrite;\n\nassign\tlatch_wait = wait_mrd | wait_io | wait_m_ALTERA_SYNTHESIZED1 | wait_mwr;\n\nassign\tnMEMRQ_int = ~(m1_mreq | mrd_mreq | mwr_mreq);\n\nassign\tnRD_out = ~(m1_mreq | mrd_mreq | ioRead);\n\nassign\tmrd_mreq = DFFE_mrd_ff3 | wait_mrd;\n\nassign\tnWR_out = ~(ioWrite | mwr_wr);\n\nassign\tmwr_mreq = mwr_wr | wait_mwr;\n\nassign\tnIORQ_out = ~(intr_iorq | iorq);\n\nassign\twait_io = wait_iorqinta | wait_iorq;\n\nassign\tintr_iorq = DFFE_intr_ff3 | wait_iorqinta;\n\nassign\tnM1_out = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_16;\n\nassign\tSYNTHESIZED_WIRE_0 = ~(SYNTHESIZED_WIRE_3 & SYNTHESIZED_WIRE_17);\n\nassign\tnRFSH_out = ~(nq2 & SYNTHESIZED_WIRE_16);\n\n\nalways@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\twait_iorqinta <= 0;\n\tend\nelse\n\tbegin\n\twait_iorqinta <= iorq_Tw;\n\tend\nend\n\n\nalways@(posedge clk or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tDFFE_intr_ff3 <= 0;\n\tend\nelse\nif (nhold_clk_wait)\n\tbegin\n\tDFFE_intr_ff3 <= wait_iorqinta;\n\tend\nend\n\n\nalways@(posedge clk or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tDFFE_iorq_ff1 <= 0;\n\tend\nelse\nif (timings_en)\n\tbegin\n\tDFFE_iorq_ff1 <= ctl_iorw;\n\tend\nend\n\n\nalways@(posedge clk or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tSYNTHESIZED_WIRE_15 <= 0;\n\tend\nelse\nif (timings_en)\n\tbegin\n\tSYNTHESIZED_WIRE_15 <= DFFE_iorq_ff1;\n\tend\nend\n\n\nalways@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\twait_iorq <= 0;\n\tend\nelse\nif (timings_en)\n\tbegin\n\twait_iorq <= SYNTHESIZED_WIRE_15;\n\tend\nend\n\n\nalways@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tDFFE_iorq_ff4 <= 0;\n\tend\nelse\nif (timings_en)\n\tbegin\n\tDFFE_iorq_ff4 <= wait_iorq;\n\tend\nend\n\n\nalways@(posedge clk or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tSYNTHESIZED_WIRE_16 <= 0;\n\tend\nelse\nif (timings_en)\n\tbegin\n\tSYNTHESIZED_WIRE_16 <= nM1_int;\n\tend\nend\n\n\nalways@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tDFFE_m1_ff1 <= 1;\n\tend\nelse\nif (timings_en)\n\tbegin\n\tDFFE_m1_ff1 <= setM1;\n\tend\nend\n\n\nalways@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\twait_m_ALTERA_SYNTHESIZED1 <= 0;\n\tend\nelse\nif (timings_en)\n\tbegin\n\twait_m_ALTERA_SYNTHESIZED1 <= DFFE_m1_ff1;\n\tend\nend\n\n\nalways@(posedge clk or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tDFFE_m1_ff3 <= 0;\n\tend\nelse\nif (timings_en)\n\tbegin\n\tDFFE_m1_ff3 <= wait_m_ALTERA_SYNTHESIZED1;\n\tend\nend\n\n\nalways@(posedge clk or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tDFFE_mrd_ff1 <= 0;\n\tend\nelse\nif (timings_en)\n\tbegin\n\tDFFE_mrd_ff1 <= ctl_mRead;\n\tend\nend\n\n\nalways@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\twait_mrd <= 0;\n\tend\nelse\nif (timings_en)\n\tbegin\n\twait_mrd <= DFFE_mrd_ff1;\n\tend\nend\n\n\nalways@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tDFFE_mrd_ff3 <= 0;\n\tend\nelse\nif (timings_en)\n\tbegin\n\tDFFE_mrd_ff3 <= wait_mrd;\n\tend\nend\n\n\nalways@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tSYNTHESIZED_WIRE_17 <= 0;\n\tend\nelse\nif (timings_en)\n\tbegin\n\tSYNTHESIZED_WIRE_17 <= SYNTHESIZED_WIRE_16;\n\tend\nend\n\n\nalways@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tDFFE_mreq_ff2 <= 0;\n\tend\nelse\nif (timings_en)\n\tbegin\n\tDFFE_mreq_ff2 <= SYNTHESIZED_WIRE_17;\n\tend\nend\n\n\nalways@(posedge clk or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tDFFE_mwr_ff1 <= 0;\n\tend\nelse\nif (timings_en)\n\tbegin\n\tDFFE_mwr_ff1 <= ctl_mWrite;\n\tend\nend\n\n\nalways@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\twait_mwr <= 0;\n\tend\nelse\nif (timings_en)\n\tbegin\n\twait_mwr <= DFFE_mwr_ff1;\n\tend\nend\n\n\nalways@(posedge SYNTHESIZED_WIRE_18 or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tmwr_wr <= 0;\n\tend\nelse\nif (timings_en)\n\tbegin\n\tmwr_wr <= wait_mwr;\n\tend\nend\n\nassign\tSYNTHESIZED_WIRE_18 =  ~clk;\n\nassign\tnq2 =  ~q2;\n\nassign\tSYNTHESIZED_WIRE_2 =  ~nreset;\n\nassign\tSYNTHESIZED_WIRE_3 =  ~DFFE_mreq_ff2;\n\n\nalways@(posedge clk or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tq1 <= 0;\n\tend\nelse\nif (timings_en)\n\tbegin\n\tq1 <= SYNTHESIZED_WIRE_16;\n\tend\nend\n\n\nalways@(posedge clk or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tq2 <= 0;\n\tend\nelse\nif (timings_en)\n\tbegin\n\tq2 <= q1;\n\tend\nend\n\nassign\twait_m1 = wait_m_ALTERA_SYNTHESIZED1;\n\nendmodule\n"
  },
  {
    "path": "cpu/control/pin_control.bdf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"graphic\" (version \"1.4\"))\n(pin\n\t(input)\n\t(rect 32 112 208 128)\n\t(text \"INPUT\" (rect 133 0 161 10)(font \"Arial\" (font_size 6)))\n\t(text \"fFetch\" (rect 9 0 42 12)(font \"Arial\" ))\n\t(pt 176 8)\n\t(drawing\n\t\t(line (pt 92 12)(pt 117 12))\n\t\t(line (pt 92 4)(pt 117 4))\n\t\t(line (pt 121 8)(pt 176 8))\n\t\t(line (pt 92 12)(pt 92 4))\n\t\t(line (pt 117 4)(pt 121 8))\n\t\t(line (pt 117 12)(pt 121 8))\n\t)\n\t(text \"VCC\" (rect 136 7 156 17)(font \"Arial\" (font_size 6)))\n)\n(pin\n\t(input)\n\t(rect 32 128 208 144)\n\t(text \"INPUT\" (rect 133 0 161 10)(font \"Arial\" (font_size 6)))\n\t(text \"fMRead\" (rect 9 0 47 12)(font \"Arial\" ))\n\t(pt 176 8)\n\t(drawing\n\t\t(line (pt 92 12)(pt 117 12))\n\t\t(line (pt 92 4)(pt 117 4))\n\t\t(line (pt 121 8)(pt 176 8))\n\t\t(line (pt 92 12)(pt 92 4))\n\t\t(line (pt 117 4)(pt 121 8))\n\t\t(line (pt 117 12)(pt 121 8))\n\t)\n\t(text \"VCC\" (rect 136 7 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40)\n)\n(connector\n\t(pt 208 56)\n\t(pt 328 56)\n)\n(connector\n\t(pt 328 56)\n\t(pt 600 56)\n)\n(connector\n\t(pt 208 72)\n\t(pt 344 72)\n)\n(connector\n\t(pt 344 72)\n\t(pt 384 72)\n)\n(connector\n\t(pt 208 88)\n\t(pt 360 88)\n)\n(connector\n\t(pt 360 88)\n\t(pt 600 88)\n)\n(junction (pt 384 328))\n(junction (pt 264 296))\n(junction (pt 264 400))\n(junction (pt 296 328))\n(junction (pt 296 512))\n(junction (pt 248 280))\n(junction (pt 248 632))\n(junction (pt 280 312))\n(junction (pt 280 680))\n(junction (pt 232 224))\n(junction (pt 232 264))\n(junction (pt 232 584))\n(junction (pt 384 72))\n(junction (pt 344 440))\n(junction (pt 328 424))\n(junction (pt 328 568))\n(junction (pt 328 480))\n(junction (pt 344 488))\n(junction (pt 360 88))\n(junction (pt 480 40))\n(junction (pt 344 72))\n(junction (pt 328 56))\n(text \"bus_ab_pin_we = (fFetch   & (T1 | T3)) |\\n                (fMRead   & (T1)) |\\n                (fMWrite  & (T1)) |\\n                (fIORead  & (T1)) |\\n             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13)(font \"Arial\" ))(text \"pin_control\" (rect 43 2 118 17)(font \"Arial\" (font_size 9)(bold)))(border))\n\t(section (rect 0 18 256 34)(text \"DESIGNER\" (rect 2 0 59 12)(font \"Arial\" ))(text \"Goran Devic\" (rect 56 2 135 17)(font \"Arial\" (font_size 9)))(border))\n\t(section (rect 0 35 256 51)(text \"DATE\" (rect 2 0 30 12)(font \"Arial\" ))(text \"November 16, 2014\" (rect 56 3 166 17)(font \"Arial\" (font_size 8)))(border))\n\t(section (rect 192 35 256 51)(text \"REV\" (rect 2 1 25 13)(font \"Arial\" ))(text \"1.0\" (rect 43 3 60 17)(font \"Arial\" (font_size 8)))(border))\n\t(drawing\n\t)\n)\n"
  },
  {
    "path": "cpu/control/pin_control.bsf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"symbol\" (version \"1.2\"))\n(symbol\n\t(rect 16 16 208 208)\n\t(text \"pin_control\" (rect 5 0 67 14)(font \"Arial\" (font_size 8)))\n\t(text \"inst\" (rect 8 176 25 188)(font \"Arial\" ))\n\t(port\n\t\t(pt 0 32)\n\t\t(input)\n\t\t(text \"T1\" (rect 0 0 14 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"T1\" (rect 21 27 35 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 32)(pt 16 32))\n\t)\n\t(port\n\t\t(pt 0 48)\n\t\t(input)\n\t\t(text \"T2\" (rect 0 0 14 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"T2\" (rect 21 43 35 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 48)(pt 16 48))\n\t)\n\t(port\n\t\t(pt 0 64)\n\t\t(input)\n\t\t(text \"T3\" (rect 0 0 14 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"T3\" (rect 21 59 35 73)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 64)(pt 16 64))\n\t)\n\t(port\n\t\t(pt 0 80)\n\t\t(input)\n\t\t(text \"T4\" (rect 0 0 14 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"T4\" (rect 21 75 35 89)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 80)(pt 16 80))\n\t)\n\t(port\n\t\t(pt 0 96)\n\t\t(input)\n\t\t(text \"fFetch\" (rect 0 0 36 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"fFetch\" (rect 21 91 57 105)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 96)(pt 16 96))\n\t)\n\t(port\n\t\t(pt 0 112)\n\t\t(input)\n\t\t(text \"fMRead\" (rect 0 0 43 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"fMRead\" (rect 21 107 64 121)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 112)(pt 16 112))\n\t)\n\t(port\n\t\t(pt 0 128)\n\t\t(input)\n\t\t(text \"fMWrite\" (rect 0 0 43 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"fMWrite\" (rect 21 123 64 137)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 128)(pt 16 128))\n\t)\n\t(port\n\t\t(pt 0 144)\n\t\t(input)\n\t\t(text \"fIORead\" (rect 0 0 46 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"fIORead\" (rect 21 139 67 153)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 144)(pt 16 144))\n\t)\n\t(port\n\t\t(pt 0 160)\n\t\t(input)\n\t\t(text \"fIOWrite\" (rect 0 0 46 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"fIOWrite\" (rect 21 155 67 169)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 160)(pt 16 160))\n\t)\n\t(port\n\t\t(pt 192 32)\n\t\t(output)\n\t\t(text \"bus_ab_pin_we\" (rect 0 0 92 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"bus_ab_pin_we\" (rect 79 27 171 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 192 32)(pt 176 32))\n\t)\n\t(port\n\t\t(pt 192 48)\n\t\t(output)\n\t\t(text \"bus_db_pin_oe\" (rect 0 0 87 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"bus_db_pin_oe\" (rect 84 43 171 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 192 48)(pt 176 48))\n\t)\n\t(port\n\t\t(pt 192 64)\n\t\t(output)\n\t\t(text \"bus_db_pin_re\" (rect 0 0 84 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"bus_db_pin_re\" (rect 87 59 171 73)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 192 64)(pt 176 64))\n\t)\n\t(drawing\n\t\t(rectangle (rect 16 16 176 176))\n\t)\n)\n"
  },
  {
    "path": "cpu/control/pin_control.v",
    "content": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and other software and tools, and its AMPP partner logic \n// functions, and any output files from any of the foregoing \n// (including device programming or simulation files), and any \n// associated documentation or information are expressly subject \n// to the terms and conditions of the Altera Program License \n// Subscription Agreement, Altera MegaCore Function License \n// Agreement, or other applicable license agreement, including, \n// without limitation, that your use is for the sole purpose of \n// programming logic devices manufactured by Altera and sold by \n// Altera or its authorized distributors.  Please refer to the \n// applicable agreement for further details.\n\n// PROGRAM\t\t\"Quartus II 64-Bit\"\n// VERSION\t\t\"Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\"\n// CREATED\t\t\"Sun Nov 16 21:18:37 2014\"\n\nmodule pin_control(\n\tfFetch,\n\tfMRead,\n\tfMWrite,\n\tfIORead,\n\tfIOWrite,\n\tT1,\n\tT2,\n\tT3,\n\tT4,\n\tbus_ab_pin_we,\n\tbus_db_pin_oe,\n\tbus_db_pin_re\n);\n\n\ninput wire\tfFetch;\ninput wire\tfMRead;\ninput wire\tfMWrite;\ninput wire\tfIORead;\ninput wire\tfIOWrite;\ninput wire\tT1;\ninput wire\tT2;\ninput wire\tT3;\ninput wire\tT4;\noutput wire\tbus_ab_pin_we;\noutput wire\tbus_db_pin_oe;\noutput wire\tbus_db_pin_re;\n\nwire\tSYNTHESIZED_WIRE_0;\nwire\tSYNTHESIZED_WIRE_1;\nwire\tSYNTHESIZED_WIRE_2;\nwire\tSYNTHESIZED_WIRE_3;\nwire\tSYNTHESIZED_WIRE_4;\nwire\tSYNTHESIZED_WIRE_5;\nwire\tSYNTHESIZED_WIRE_6;\nwire\tSYNTHESIZED_WIRE_7;\nwire\tSYNTHESIZED_WIRE_8;\nwire\tSYNTHESIZED_WIRE_9;\n\n\n\n\nassign\tSYNTHESIZED_WIRE_9 = fFetch | fMWrite | fMRead | fIORead | fIOWrite | fIOWrite;\n\nassign\tSYNTHESIZED_WIRE_7 = T3 | T2;\n\nassign\tbus_db_pin_oe = SYNTHESIZED_WIRE_0 | SYNTHESIZED_WIRE_1;\n\nassign\tSYNTHESIZED_WIRE_3 = T3 & fIORead;\n\nassign\tbus_db_pin_re = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_3 | SYNTHESIZED_WIRE_4;\n\nassign\tbus_ab_pin_we = SYNTHESIZED_WIRE_5 | SYNTHESIZED_WIRE_6;\n\nassign\tSYNTHESIZED_WIRE_8 = T2 | T3 | T4;\n\nassign\tSYNTHESIZED_WIRE_1 = fMWrite & SYNTHESIZED_WIRE_7;\n\nassign\tSYNTHESIZED_WIRE_0 = SYNTHESIZED_WIRE_8 & fIOWrite;\n\nassign\tSYNTHESIZED_WIRE_4 = T2 & fFetch;\n\nassign\tSYNTHESIZED_WIRE_2 = T2 & fMRead;\n\nassign\tSYNTHESIZED_WIRE_6 = T3 & fFetch;\n\nassign\tSYNTHESIZED_WIRE_5 = T1 & SYNTHESIZED_WIRE_9;\n\n\nendmodule\n"
  },
  {
    "path": "cpu/control/pla_decode.bsf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"symbol\" (version \"1.1\"))\n(symbol\n\t(rect 16 16 208 96)\n\t(text \"pla_decode\" (rect 5 0 49 12)(font \"Arial\" ))\n\t(text \"inst\" (rect 8 64 20 76)(font \"Arial\" ))\n\t(port\n\t\t(pt 0 32)\n\t\t(input)\n\t\t(text \"opcode[7..0]\" (rect 0 0 48 12)(font \"Arial\" ))\n\t\t(text \"opcode[7..0]\" (rect 21 27 69 39)(font \"Arial\" ))\n\t\t(line (pt 0 32)(pt 16 32)(line_width 3))\n\t)\n\t(port\n\t\t(pt 0 48)\n\t\t(input)\n\t\t(text \"prefix[6..0]\" (rect 0 0 42 12)(font \"Arial\" ))\n\t\t(text \"prefix[6..0]\" (rect 21 43 63 55)(font \"Arial\" ))\n\t\t(line (pt 0 48)(pt 16 48)(line_width 3))\n\t)\n\t(port\n\t\t(pt 192 32)\n\t\t(output)\n\t\t(text \"pla[104..0]\" (rect 0 0 40 12)(font \"Arial\" ))\n\t\t(text \"pla[104..0]\" (rect 131 27 171 39)(font \"Arial\" ))\n\t\t(line (pt 192 32)(pt 176 32)(line_width 3))\n\t)\n\t(drawing\n\t\t(rectangle (rect 16 16 176 64)(line_width 1))\n\t)\n)\n"
  },
  {
    "path": "cpu/control/pla_decode.v",
    "content": "//=====================================================================================\n// This file is automatically generated by the z80_pla_checker tool. Do not edit!\n//=====================================================================================\nmodule pla_decode\n(\n    input wire [6:0] prefix,\n    input wire [7:0] opcode,\n    output wire [104:0] pla\n);\n\nassign pla[  0] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11110100) == 15'b0000001_10100000) ? 1'b1 : 1'b0;   // ldx/cpx/inx/outx brk\nassign pla[  1] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11011001) ? 1'b1 : 1'b0;   // exx\nassign pla[  2] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11101011) ? 1'b1 : 1'b0;   // ex de,hl\nassign pla[  3] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11011111) == 15'b0000100_11011101) ? 1'b1 : 1'b0;   // IX/IY prefix\nassign pla[  5] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11111001) ? 1'b1 : 1'b0;   // ld sp,hl\nassign pla[  6] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11101001) ? 1'b1 : 1'b0;   // jp hl\nassign pla[  7] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11001111) == 15'b0000100_00000001) ? 1'b1 : 1'b0;   // ld rr,nn\nassign pla[  8] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11100111) == 15'b0000100_00000010) ? 1'b1 : 1'b0;   // ld (rr),a/a,(rr)\nassign pla[  9] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_00000011) ? 1'b1 : 1'b0;   // inc/dec rr\nassign pla[ 10] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11100011) ? 1'b1 : 1'b0;   // ex (sp),hl\nassign pla[ 11] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11100111) == 15'b0000001_10100001) ? 1'b1 : 1'b0;   // cpi/cpir/cpd/cpdr\nassign pla[ 12] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11100111) == 15'b0000001_10100000) ? 1'b1 : 1'b0;   // ldi/ldir/ldd/lddr\nassign pla[ 13] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11001111) == 15'b0000100_00000010) ? 1'b1 : 1'b0;   // ld direction\nassign pla[ 15] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11110111) == 15'b0000001_01100111) ? 1'b1 : 1'b0;   // rrd/rld\nassign pla[ 16] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11001111) == 15'b0000100_11000101) ? 1'b1 : 1'b0;   // push rr\nassign pla[ 17] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_00000110) ? 1'b1 : 1'b0;   // ld r,n\nassign pla[ 20] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11100111) == 15'b0000001_10100011) ? 1'b1 : 1'b0;   // outx/otxr\nassign pla[ 21] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11100111) == 15'b0000001_10100010) ? 1'b1 : 1'b0;   // inx/inxr\nassign pla[ 23] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11001011) == 15'b0000100_11000001) ? 1'b1 : 1'b0;   // push/pop\nassign pla[ 24] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11001101) ? 1'b1 : 1'b0;   // call nn\nassign pla[ 25] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11100111) == 15'b0000100_00000111) ? 1'b1 : 1'b0;   // rlca/rla/rrca/rra\nassign pla[ 26] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00010000) ? 1'b1 : 1'b0;   // djnz e\nassign pla[ 27] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11000110) == 15'b0000001_01000000) ? 1'b1 : 1'b0;   // in/out r,(c)\nassign pla[ 28] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11010011) ? 1'b1 : 1'b0;   // out (n),a\nassign pla[ 29] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11000011) ? 1'b1 : 1'b0;   // jp nn\nassign pla[ 30] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11110111) == 15'b0000100_00100010) ? 1'b1 : 1'b0;   // ld hl,(nn)/(nn),hl\nassign pla[ 31] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11000111) == 15'b0000001_01000011) ? 1'b1 : 1'b0;   // ld rr,(nn)/(nn),rr\nassign pla[ 33] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11001111) == 15'b0000001_01000011) ? 1'b1 : 1'b0;   // ld direction\nassign pla[ 34] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11000111) == 15'b0000001_01000001) ? 1'b1 : 1'b0;   // out (c),r\nassign pla[ 35] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11001001) ? 1'b1 : 1'b0;   // ret\nassign pla[ 37] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11110111) == 15'b0000100_11010011) ? 1'b1 : 1'b0;   // out (n),a/a,(n)\nassign pla[ 38] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11110111) == 15'b0000100_00110010) ? 1'b1 : 1'b0;   // ld (nn),a/a,(nn)\nassign pla[ 39] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00001000) ? 1'b1 : 1'b0;   // ex af,af'\nassign pla[ 40] = (({prefix[6:0], opcode[7:0]} & 15'b0100100_11111111) == 15'b0100100_00110110) ? 1'b1 : 1'b0;   // ld (ix+d),n\nassign pla[ 42] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_11000100) ? 1'b1 : 1'b0;   // call cc,nn\nassign pla[ 43] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_11000010) ? 1'b1 : 1'b0;   // jp cc,nn\nassign pla[ 44] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11001011) ? 1'b1 : 1'b0;   // CB prefix\nassign pla[ 45] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_11000000) ? 1'b1 : 1'b0;   // ret cc\nassign pla[ 46] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11000111) == 15'b0000001_01000101) ? 1'b1 : 1'b0;   // reti/retn\nassign pla[ 47] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00011000) ? 1'b1 : 1'b0;   // jr e\nassign pla[ 48] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11100111) == 15'b0000100_00100000) ? 1'b1 : 1'b0;   // jr ss,e\nassign pla[ 49] = (({prefix[6:0], opcode[7:0]} & 15'b0100000_11111111) == 15'b0100000_11001011) ? 1'b1 : 1'b0;   // CB prefix with IX/IY\nassign pla[ 50] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00110110) ? 1'b1 : 1'b0;   // ld (hl),n\nassign pla[ 51] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11101101) ? 1'b1 : 1'b0;   // ED prefix\nassign pla[ 52] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_10000110) ? 1'b1 : 1'b0;   // add/sub/and/or/xor/cp (hl)\nassign pla[ 53] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111110) == 15'b0000100_00110100) ? 1'b1 : 1'b0;   // inc/dec (hl)\nassign pla[ 55] = (({prefix[6:0], opcode[7:0]} & 15'b0000010_00000111) == 15'b0000010_00000110) ? 1'b1 : 1'b0;   // Every CB op (hl)\nassign pla[ 56] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_11000111) ? 1'b1 : 1'b0;   // rst p\nassign pla[ 57] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11110111) == 15'b0000001_01000111) ? 1'b1 : 1'b0;   // ld i,a/r,a\nassign pla[ 58] = (({prefix[6:0], opcode[7:0]} & 15'b0010100_11000111) == 15'b0010100_01000110) ? 1'b1 : 1'b0;   // ld r,(hl)\nassign pla[ 59] = (({prefix[6:0], opcode[7:0]} & 15'b0010100_11111000) == 15'b0010100_01110000) ? 1'b1 : 1'b0;   // ld (hl),r\nassign pla[ 61] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000000) == 15'b0000100_01000000) ? 1'b1 : 1'b0;   // ld r,r'\nassign pla[ 64] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_11000110) ? 1'b1 : 1'b0;   // add/sub/and/or/xor/cmp a,imm\nassign pla[ 65] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000000) == 15'b0000100_10000000) ? 1'b1 : 1'b0;   // add/sub/and/or/xor/cmp a,r\nassign pla[ 66] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000110) == 15'b0000100_00000100) ? 1'b1 : 1'b0;   // inc/dec r\nassign pla[ 68] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11000111) == 15'b0000001_01000010) ? 1'b1 : 1'b0;   // adc/sbc hl,rr\nassign pla[ 69] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11001111) == 15'b0000100_00001001) ? 1'b1 : 1'b0;   // add hl,rr\nassign pla[ 70] = (({prefix[6:0], opcode[7:0]} & 15'b0000010_11000000) == 15'b0000010_00000000) ? 1'b1 : 1'b0;   // rlc r\nassign pla[ 72] = (({prefix[6:0], opcode[7:0]} & 15'b0000010_11000000) == 15'b0000010_01000000) ? 1'b1 : 1'b0;   // bit b,r\nassign pla[ 73] = (({prefix[6:0], opcode[7:0]} & 15'b0000010_11000000) == 15'b0000010_10000000) ? 1'b1 : 1'b0;   // res b,r\nassign pla[ 74] = (({prefix[6:0], opcode[7:0]} & 15'b0000010_11000000) == 15'b0000010_11000000) ? 1'b1 : 1'b0;   // set b,r\nassign pla[ 75] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_00000101) ? 1'b1 : 1'b0;   // dec r\nassign pla[ 76] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00111000) ? 1'b1 : 1'b0;   // 111 (CP)\nassign pla[ 77] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00100111) ? 1'b1 : 1'b0;   // daa\nassign pla[ 78] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00010000) ? 1'b1 : 1'b0;   // 010 (SUB)\nassign pla[ 79] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00011000) ? 1'b1 : 1'b0;   // 011 (SBC)\nassign pla[ 80] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00001000) ? 1'b1 : 1'b0;   // 001 (ADC)\nassign pla[ 81] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00101111) ? 1'b1 : 1'b0;   // cpl\nassign pla[ 82] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11000111) == 15'b0000001_01000100) ? 1'b1 : 1'b0;   // neg\nassign pla[ 83] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11110111) == 15'b0000001_01010111) ? 1'b1 : 1'b0;   // ld a,i/a,r\nassign pla[ 84] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00000000) ? 1'b1 : 1'b0;   // 000 (ADD)\nassign pla[ 85] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00100000) ? 1'b1 : 1'b0;   // 100 (AND)\nassign pla[ 86] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00110000) ? 1'b1 : 1'b0;   // 110 (OR)\nassign pla[ 88] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00101000) ? 1'b1 : 1'b0;   // 101 (XOR)\nassign pla[ 89] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00111111) ? 1'b1 : 1'b0;   // ccf\nassign pla[ 91] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11100110) == 15'b0000001_10100010) ? 1'b1 : 1'b0;   // inx/outx/inxr/otxr\nassign pla[ 92] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00110111) ? 1'b1 : 1'b0;   // scf\nassign pla[ 95] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_01110110) ? 1'b1 : 1'b0;   // halt\nassign pla[ 96] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11000111) == 15'b0000001_01000110) ? 1'b1 : 1'b0;   // im n\nassign pla[ 97] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11110111) == 15'b0000100_11110011) ? 1'b1 : 1'b0;   // di/ei\nassign pla[ 99] = (({prefix[6:0], opcode[7:0]} & 15'b0000000_00000001) == 15'b0000000_00000001) ? 1'b1 : 1'b0;   // opcode[0]\nassign pla[100] = (({prefix[6:0], opcode[7:0]} & 15'b0000000_00000010) == 15'b0000000_00000010) ? 1'b1 : 1'b0;   // opcode[1]\nassign pla[101] = (({prefix[6:0], opcode[7:0]} & 15'b0000000_00000100) == 15'b0000000_00000100) ? 1'b1 : 1'b0;   // opcode[2]\nassign pla[102] = (({prefix[6:0], opcode[7:0]} & 15'b0000000_00001000) == 15'b0000000_00001000) ? 1'b1 : 1'b0;   // opcode[3]\nassign pla[103] = (({prefix[6:0], opcode[7:0]} & 15'b0000000_00010000) == 15'b0000000_00010000) ? 1'b1 : 1'b0;   // opcode[4]\nassign pla[104] = (({prefix[6:0], opcode[7:0]} & 15'b0000000_00100000) == 15'b0000000_00100000) ? 1'b1 : 1'b0;   // opcode[5]\n\n// Entries not used by our timing matrix\nassign pla[ 67] = 1'b0;   // in\nassign pla[ 62] = 1'b0;   // For all CB opcodes\nassign pla[ 54] = 1'b0;   // Every CB with IX/IY\nassign pla[ 22] = 1'b0;   // CB prefix w/o IX/IY\nassign pla[ 14] = 1'b0;   // dec rr\nassign pla[  4] = 1'b0;   // ld x,a/a,x\n\n// Duplicate entries\nassign pla[ 18] = 1'b0;   // ldi/ldir/ldd/lddr\nassign pla[ 19] = 1'b0;   // cpi/cpir/cpd/cpdr\nassign pla[ 32] = 1'b0;   // ld i,a/a,i/r,a/a,r\nassign pla[ 36] = 1'b0;   // ld(rr),a/a,(rr)\nassign pla[ 41] = 1'b0;   // IX/IY\nassign pla[ 60] = 1'b0;   // rrd/rld\nassign pla[ 63] = 1'b0;   // ld r,*\nassign pla[ 71] = 1'b0;   // rlca/rla/rrca/rra\nassign pla[ 87] = 1'b0;   // ld a,i / ld a,r\nassign pla[ 90] = 1'b0;   // djnz *\nassign pla[ 93] = 1'b0;   // cpi/cpir/cpd/cpdr\nassign pla[ 94] = 1'b0;   // ldi/ldir/ldd/lddr\nassign pla[ 98] = 1'b0;   // out (*),a/in a,(*)\n\nendmodule\n"
  },
  {
    "path": "cpu/control/resets.bdf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  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    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"symbol\" (version \"1.2\"))\n(symbol\n\t(rect 16 16 192 176)\n\t(text \"resets\" (rect 5 0 41 14)(font \"Arial\" (font_size 8)))\n\t(text \"inst\" (rect 8 144 25 156)(font \"Arial\" ))\n\t(port\n\t\t(pt 0 32)\n\t\t(input)\n\t\t(text \"fpga_reset\" (rect 0 0 62 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"fpga_reset\" (rect 21 27 83 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 32)(pt 16 32))\n\t)\n\t(port\n\t\t(pt 0 48)\n\t\t(input)\n\t\t(text \"reset_in\" (rect 0 0 46 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"reset_in\" (rect 21 43 67 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 48)(pt 16 48))\n\t)\n\t(port\n\t\t(pt 0 64)\n\t\t(input)\n\t\t(text \"M1\" (rect 0 0 16 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"M1\" (rect 21 59 37 73)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 64)(pt 16 64))\n\t)\n\t(port\n\t\t(pt 0 80)\n\t\t(input)\n\t\t(text \"T2\" (rect 0 0 14 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"T2\" (rect 21 75 35 89)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 80)(pt 16 80))\n\t)\n\t(port\n\t\t(pt 0 96)\n\t\t(input)\n\t\t(text \"clk\" (rect 0 0 15 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"clk\" (rect 21 91 36 105)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 96)(pt 16 96))\n\t)\n\t(port\n\t\t(pt 0 112)\n\t\t(input)\n\t\t(text \"nhold_clk_wait\" (rect 0 0 84 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"nhold_clk_wait\" (rect 21 107 105 121)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 112)(pt 16 112))\n\t)\n\t(port\n\t\t(pt 176 32)\n\t\t(output)\n\t\t(text \"nreset\" (rect 0 0 36 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"nreset\" (rect 119 27 155 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 176 32)(pt 160 32))\n\t)\n\t(port\n\t\t(pt 176 48)\n\t\t(output)\n\t\t(text \"clrpc\" (rect 0 0 28 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"clrpc\" (rect 127 43 155 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 176 48)(pt 160 48))\n\t)\n\t(drawing\n\t\t(rectangle (rect 16 16 160 144))\n\t)\n)\n"
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    "path": "cpu/control/resets.v",
    "content": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and other software and tools, and its AMPP partner logic \n// functions, and any output files from any of the foregoing \n// (including device programming or simulation files), and any \n// associated documentation or information are expressly subject \n// to the terms and conditions of the Altera Program License \n// Subscription Agreement, Altera MegaCore Function License \n// Agreement, or other applicable license agreement, including, \n// without limitation, that your use is for the sole purpose of \n// programming logic devices manufactured by Altera and sold by \n// Altera or its authorized distributors.  Please refer to the \n// applicable agreement for further details.\n\n// PROGRAM\t\t\"Quartus II 64-Bit\"\n// VERSION\t\t\"Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\"\n// CREATED\t\t\"Sat Dec 10 08:57:54 2016\"\n\nmodule resets(\n\treset_in,\n\tclk,\n\tM1,\n\tT2,\n\tfpga_reset,\n\tnhold_clk_wait,\n\tclrpc,\n\tnreset\n);\n\n\ninput wire\treset_in;\ninput wire\tclk;\ninput wire\tM1;\ninput wire\tT2;\ninput wire\tfpga_reset;\ninput wire\tnhold_clk_wait;\noutput wire\tclrpc;\noutput wire\tnreset;\n\nreg\tclrpc_int;\nwire\tnclk;\nreg\tx1;\nwire\tx2;\nwire\tx3;\nwire\tSYNTHESIZED_WIRE_8;\nwire\tSYNTHESIZED_WIRE_1;\nreg\tSYNTHESIZED_WIRE_9;\nreg\tDFFE_intr_ff3;\nreg\tSYNTHESIZED_WIRE_10;\nwire\tSYNTHESIZED_WIRE_11;\nwire\tSYNTHESIZED_WIRE_3;\nreg\tSYNTHESIZED_WIRE_12;\nwire\tSYNTHESIZED_WIRE_6;\n\nassign\tnreset = SYNTHESIZED_WIRE_6;\n\n\n\n\nalways@(posedge nclk or negedge SYNTHESIZED_WIRE_8)\nbegin\nif (!SYNTHESIZED_WIRE_8)\n\tbegin\n\tx1 <= 1;\n\tend\nelse\n\tbegin\n\tx1 <= ~x1 & reset_in | x1 & ~SYNTHESIZED_WIRE_1;\n\tend\nend\n\nassign\tclrpc = clrpc_int | SYNTHESIZED_WIRE_9 | DFFE_intr_ff3 | SYNTHESIZED_WIRE_10;\n\nassign\tSYNTHESIZED_WIRE_1 =  ~reset_in;\n\nassign\tx2 = x1 & SYNTHESIZED_WIRE_11;\n\nassign\tSYNTHESIZED_WIRE_11 = M1 & T2;\n\nassign\tx3 = x1 & SYNTHESIZED_WIRE_3;\n\nassign\tSYNTHESIZED_WIRE_6 =  ~SYNTHESIZED_WIRE_12;\n\nassign\tSYNTHESIZED_WIRE_3 =  ~SYNTHESIZED_WIRE_11;\n\nassign\tnclk =  ~clk;\n\nassign\tSYNTHESIZED_WIRE_8 =  ~fpga_reset;\n\n\nalways@(posedge nclk)\nbegin\nif (nhold_clk_wait)\n\tbegin\n\tDFFE_intr_ff3 <= SYNTHESIZED_WIRE_9;\n\tend\nend\n\n\nalways@(posedge nclk)\nbegin\nif (nhold_clk_wait)\n\tbegin\n\tSYNTHESIZED_WIRE_10 <= SYNTHESIZED_WIRE_12;\n\tend\nend\n\n\nalways@(posedge nclk)\nbegin\nif (nhold_clk_wait)\n\tbegin\n\tSYNTHESIZED_WIRE_9 <= SYNTHESIZED_WIRE_10;\n\tend\nend\n\n\nalways@(posedge clk or negedge SYNTHESIZED_WIRE_8)\nbegin\nif (!SYNTHESIZED_WIRE_8)\n\tbegin\n\tSYNTHESIZED_WIRE_12 <= 1;\n\tend\nelse\n\tbegin\n\tSYNTHESIZED_WIRE_12 <= x3;\n\tend\nend\n\n\nalways@(posedge nclk or negedge SYNTHESIZED_WIRE_6)\nbegin\nif (!SYNTHESIZED_WIRE_6)\n\tbegin\n\tclrpc_int <= 0;\n\tend\nelse\n\tbegin\n\tclrpc_int <= ~clrpc_int & x2 | clrpc_int & ~SYNTHESIZED_WIRE_11;\n\tend\nend\n\n\nendmodule\n"
  },
  {
    "path": "cpu/control/sequencer.bdf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  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13)(font \"Arial\" ))(text \"sequencer\" (rect 43 2 138 21)(font \"Arial\" (font_size 12)(bold)))(border))\n\t(section (rect 0 0 320 20)(text \"PROJECT\" (rect 2 0 52 12)(font \"Arial\" ))(text \"A-Z80\" (rect 56 2 106 21)(font \"Arial\" (font_size 12)(bold)))(border))\n\t(section (rect 241 41 320 60)(text \"REV\" (rect 2 1 25 13)(font \"Arial\" ))(text \"1.4\" (rect 43 3 64 19)(font \"Arial\" (font_size 10)))(border))\n\t(drawing\n\t)\n)\n"
  },
  {
    "path": "cpu/control/sequencer.bsf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"symbol\" (version \"1.2\"))\n(symbol\n\t(rect 16 16 216 272)\n\t(text \"sequencer\" (rect 5 0 66 14)(font \"Arial\" (font_size 8)))\n\t(text \"inst\" (rect 8 240 25 252)(font \"Arial\" ))\n\t(port\n\t\t(pt 0 32)\n\t\t(input)\n\t\t(text \"setM1\" (rect 0 0 34 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"setM1\" (rect 21 27 55 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 32)(pt 16 32))\n\t)\n\t(port\n\t\t(pt 0 48)\n\t\t(input)\n\t\t(text \"clk\" (rect 0 0 15 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"clk\" (rect 21 43 36 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 48)(pt 16 48))\n\t)\n\t(port\n\t\t(pt 0 64)\n\t\t(input)\n\t\t(text \"nreset\" (rect 0 0 36 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"nreset\" (rect 21 59 57 73)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 64)(pt 16 64))\n\t)\n\t(port\n\t\t(pt 0 80)\n\t\t(input)\n\t\t(text \"nextM\" (rect 0 0 34 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"nextM\" (rect 21 75 55 89)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 80)(pt 16 80))\n\t)\n\t(port\n\t\t(pt 0 96)\n\t\t(input)\n\t\t(text \"hold_clk_iorq\" (rect 0 0 74 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"hold_clk_iorq\" (rect 21 91 95 105)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 96)(pt 16 96))\n\t)\n\t(port\n\t\t(pt 0 112)\n\t\t(input)\n\t\t(text \"hold_clk_wait\" (rect 0 0 77 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"hold_clk_wait\" (rect 21 107 98 121)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 112)(pt 16 112))\n\t)\n\t(port\n\t\t(pt 0 128)\n\t\t(input)\n\t\t(text \"hold_clk_busrq\" (rect 0 0 86 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"hold_clk_busrq\" (rect 21 123 107 137)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 128)(pt 16 128))\n\t)\n\t(port\n\t\t(pt 200 32)\n\t\t(output)\n\t\t(text \"M1\" (rect 0 0 16 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"M1\" (rect 163 27 179 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 200 32)(pt 184 32))\n\t)\n\t(port\n\t\t(pt 200 48)\n\t\t(output)\n\t\t(text \"M2\" (rect 0 0 16 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"M2\" (rect 163 43 179 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 200 48)(pt 184 48))\n\t)\n\t(port\n\t\t(pt 200 64)\n\t\t(output)\n\t\t(text \"M3\" (rect 0 0 16 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"M3\" (rect 163 59 179 73)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 200 64)(pt 184 64))\n\t)\n\t(port\n\t\t(pt 200 80)\n\t\t(output)\n\t\t(text \"M4\" (rect 0 0 16 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"M4\" (rect 163 75 179 89)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 200 80)(pt 184 80))\n\t)\n\t(port\n\t\t(pt 200 96)\n\t\t(output)\n\t\t(text \"M5\" (rect 0 0 16 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"M5\" (rect 163 91 179 105)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 200 96)(pt 184 96))\n\t)\n\t(port\n\t\t(pt 200 128)\n\t\t(output)\n\t\t(text \"T1\" (rect 0 0 14 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"T1\" (rect 165 123 179 137)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 200 128)(pt 184 128))\n\t)\n\t(port\n\t\t(pt 200 144)\n\t\t(output)\n\t\t(text \"T2\" (rect 0 0 14 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"T2\" (rect 165 139 179 153)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 200 144)(pt 184 144))\n\t)\n\t(port\n\t\t(pt 200 160)\n\t\t(output)\n\t\t(text \"T3\" (rect 0 0 14 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"T3\" (rect 165 155 179 169)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 200 160)(pt 184 160))\n\t)\n\t(port\n\t\t(pt 200 176)\n\t\t(output)\n\t\t(text \"T4\" (rect 0 0 14 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"T4\" (rect 165 171 179 185)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 200 176)(pt 184 176))\n\t)\n\t(port\n\t\t(pt 200 192)\n\t\t(output)\n\t\t(text \"T5\" (rect 0 0 14 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"T5\" (rect 165 187 179 201)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 200 192)(pt 184 192))\n\t)\n\t(port\n\t\t(pt 200 208)\n\t\t(output)\n\t\t(text \"T6\" (rect 0 0 14 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"T6\" (rect 165 203 179 217)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 200 208)(pt 184 208))\n\t)\n\t(port\n\t\t(pt 200 224)\n\t\t(output)\n\t\t(text \"timings_en\" (rect 0 0 60 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"timings_en\" (rect 119 219 179 233)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 200 224)(pt 184 224))\n\t)\n\t(drawing\n\t\t(rectangle (rect 16 16 184 240))\n\t)\n)\n"
  },
  {
    "path": "cpu/control/sequencer.v",
    "content": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and other software and tools, and its AMPP partner logic \n// functions, and any output files from any of the foregoing \n// (including device programming or simulation files), and any \n// associated documentation or information are expressly subject \n// to the terms and conditions of the Altera Program License \n// Subscription Agreement, Altera MegaCore Function License \n// Agreement, or other applicable license agreement, including, \n// without limitation, that your use is for the sole purpose of \n// programming logic devices manufactured by Altera and sold by \n// Altera or its authorized distributors.  Please refer to the \n// applicable agreement for further details.\n\n// PROGRAM\t\t\"Quartus II 64-Bit\"\n// VERSION\t\t\"Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\"\n// CREATED\t\t\"Sat Feb 13 17:56:57 2016\"\n\nmodule sequencer(\n\tclk,\n\tnextM,\n\tsetM1,\n\tnreset,\n\thold_clk_iorq,\n\thold_clk_wait,\n\thold_clk_busrq,\n\tM1,\n\tM2,\n\tM3,\n\tM4,\n\tM5,\n\tT1,\n\tT2,\n\tT3,\n\tT4,\n\tT5,\n\tT6,\n\ttimings_en\n);\n\n\ninput wire\tclk;\ninput wire\tnextM;\ninput wire\tsetM1;\ninput wire\tnreset;\ninput wire\thold_clk_iorq;\ninput wire\thold_clk_wait;\ninput wire\thold_clk_busrq;\noutput wire\tM1;\noutput wire\tM2;\noutput wire\tM3;\noutput wire\tM4;\noutput reg\tM5;\noutput wire\tT1;\noutput wire\tT2;\noutput wire\tT3;\noutput wire\tT4;\noutput wire\tT5;\noutput reg\tT6;\noutput wire\ttimings_en;\n\nwire\tena_M;\nwire\tena_T;\nreg\tDFFE_M4_ff;\nwire\tSYNTHESIZED_WIRE_18;\nreg\tDFFE_T1_ff;\nwire\tSYNTHESIZED_WIRE_19;\nreg\tDFFE_T2_ff;\nreg\tDFFE_T3_ff;\nreg\tDFFE_T4_ff;\nreg\tDFFE_T5_ff;\nreg\tDFFE_M1_ff;\nreg\tDFFE_M2_ff;\nreg\tDFFE_M3_ff;\nwire\tSYNTHESIZED_WIRE_9;\nwire\tSYNTHESIZED_WIRE_10;\nwire\tSYNTHESIZED_WIRE_11;\nwire\tSYNTHESIZED_WIRE_12;\nwire\tSYNTHESIZED_WIRE_13;\nwire\tSYNTHESIZED_WIRE_14;\nwire\tSYNTHESIZED_WIRE_15;\nwire\tSYNTHESIZED_WIRE_16;\nwire\tSYNTHESIZED_WIRE_17;\n\nassign\tM1 = DFFE_M1_ff;\nassign\tM2 = DFFE_M2_ff;\nassign\tM3 = DFFE_M3_ff;\nassign\tM4 = DFFE_M4_ff;\nassign\tT1 = DFFE_T1_ff;\nassign\tT2 = DFFE_T2_ff;\nassign\tT3 = DFFE_T3_ff;\nassign\tT4 = DFFE_T4_ff;\nassign\tT5 = DFFE_T5_ff;\n\n\n\nassign\tena_M = nextM | setM1;\n\nassign\tSYNTHESIZED_WIRE_12 = DFFE_M4_ff & SYNTHESIZED_WIRE_18;\n\nassign\tSYNTHESIZED_WIRE_13 = DFFE_T1_ff & SYNTHESIZED_WIRE_19;\n\nassign\tSYNTHESIZED_WIRE_14 = DFFE_T2_ff & SYNTHESIZED_WIRE_19;\n\nassign\tSYNTHESIZED_WIRE_15 = DFFE_T3_ff & SYNTHESIZED_WIRE_19;\n\nassign\tSYNTHESIZED_WIRE_16 = DFFE_T4_ff & SYNTHESIZED_WIRE_19;\n\nassign\tSYNTHESIZED_WIRE_17 = DFFE_T5_ff & SYNTHESIZED_WIRE_19;\n\nassign\tSYNTHESIZED_WIRE_9 = DFFE_M1_ff & SYNTHESIZED_WIRE_18;\n\nassign\tSYNTHESIZED_WIRE_10 = DFFE_M2_ff & SYNTHESIZED_WIRE_18;\n\nassign\tSYNTHESIZED_WIRE_11 = DFFE_M3_ff & SYNTHESIZED_WIRE_18;\n\nassign\tena_T = ~(hold_clk_iorq | hold_clk_wait | hold_clk_busrq);\n\n\nalways@(posedge clk or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tDFFE_M1_ff <= 1;\n\tend\nelse\nif (ena_M)\n\tbegin\n\tDFFE_M1_ff <= setM1;\n\tend\nend\n\n\nalways@(posedge clk or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tDFFE_M2_ff <= 0;\n\tend\nelse\nif (ena_M)\n\tbegin\n\tDFFE_M2_ff <= SYNTHESIZED_WIRE_9;\n\tend\nend\n\n\nalways@(posedge clk or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tDFFE_M3_ff <= 0;\n\tend\nelse\nif (ena_M)\n\tbegin\n\tDFFE_M3_ff <= SYNTHESIZED_WIRE_10;\n\tend\nend\n\n\nalways@(posedge clk or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tDFFE_M4_ff <= 0;\n\tend\nelse\nif (ena_M)\n\tbegin\n\tDFFE_M4_ff <= SYNTHESIZED_WIRE_11;\n\tend\nend\n\n\nalways@(posedge clk or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tM5 <= 0;\n\tend\nelse\nif (ena_M)\n\tbegin\n\tM5 <= SYNTHESIZED_WIRE_12;\n\tend\nend\n\nassign\tSYNTHESIZED_WIRE_19 =  ~ena_M;\n\nassign\tSYNTHESIZED_WIRE_18 =  ~setM1;\n\n\nalways@(posedge clk or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tDFFE_T1_ff <= 1;\n\tend\nelse\nif (ena_T)\n\tbegin\n\tDFFE_T1_ff <= ena_M;\n\tend\nend\n\n\nalways@(posedge clk or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tDFFE_T2_ff <= 0;\n\tend\nelse\nif (ena_T)\n\tbegin\n\tDFFE_T2_ff <= SYNTHESIZED_WIRE_13;\n\tend\nend\n\n\nalways@(posedge clk or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tDFFE_T3_ff <= 0;\n\tend\nelse\nif (ena_T)\n\tbegin\n\tDFFE_T3_ff <= SYNTHESIZED_WIRE_14;\n\tend\nend\n\n\nalways@(posedge clk or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tDFFE_T4_ff <= 0;\n\tend\nelse\nif (ena_T)\n\tbegin\n\tDFFE_T4_ff <= SYNTHESIZED_WIRE_15;\n\tend\nend\n\n\nalways@(posedge clk or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tDFFE_T5_ff <= 0;\n\tend\nelse\nif (ena_T)\n\tbegin\n\tDFFE_T5_ff <= SYNTHESIZED_WIRE_16;\n\tend\nend\n\n\nalways@(posedge clk or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tT6 <= 0;\n\tend\nelse\nif (ena_T)\n\tbegin\n\tT6 <= SYNTHESIZED_WIRE_17;\n\tend\nend\n\nassign\ttimings_en = ena_T;\n\nendmodule\n"
  },
  {
    "path": "cpu/control/simulation/modelsim/r",
    "content": "restart -f ; run -all\n"
  },
  {
    "path": "cpu/control/simulation/modelsim/test_control.mpf",
    "content": "; Copyright 1991-2009 Mentor Graphics Corporation\n;\n; All Rights Reserved.\n;\n; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF\n; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.\n;\n\n[Library]\nstd = $MODEL_TECH/../std\nieee = $MODEL_TECH/../ieee\nverilog = $MODEL_TECH/../verilog\nvital2000 = $MODEL_TECH/../vital2000\nstd_developerskit = $MODEL_TECH/../std_developerskit\nsynopsys = $MODEL_TECH/../synopsys\nmodelsim_lib = $MODEL_TECH/../modelsim_lib\nsv_std = $MODEL_TECH/../sv_std\n\n; Altera Primitive libraries\n;\n; VHDL Section\n;\naltera_mf = $MODEL_TECH/../altera/vhdl/altera_mf\naltera = $MODEL_TECH/../altera/vhdl/altera\naltera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim\nlpm = $MODEL_TECH/../altera/vhdl/220model\n220model = $MODEL_TECH/../altera/vhdl/220model\nmax = $MODEL_TECH/../altera/vhdl/max\nmaxii = $MODEL_TECH/../altera/vhdl/maxii\nmaxv = $MODEL_TECH/../altera/vhdl/maxv\nstratix = $MODEL_TECH/../altera/vhdl/stratix\nstratixii = $MODEL_TECH/../altera/vhdl/stratixii\nstratixiigx = $MODEL_TECH/../altera/vhdl/stratixiigx\nhardcopyii = $MODEL_TECH/../altera/vhdl/hardcopyii\nhardcopyiii = $MODEL_TECH/../altera/vhdl/hardcopyiii\nhardcopyiv = $MODEL_TECH/../altera/vhdl/hardcopyiv\ncyclone = $MODEL_TECH/../altera/vhdl/cyclone\ncycloneii = $MODEL_TECH/../altera/vhdl/cycloneii\ncycloneiii = $MODEL_TECH/../altera/vhdl/cycloneiii\ncycloneiiils = $MODEL_TECH/../altera/vhdl/cycloneiiils\nsgate = $MODEL_TECH/../altera/vhdl/sgate\nstratixgx = $MODEL_TECH/../altera/vhdl/stratixgx\naltgxb = $MODEL_TECH/../altera/vhdl/altgxb\nstratixgx_gxb = $MODEL_TECH/../altera/vhdl/stratixgx_gxb\nstratixiigx_hssi = $MODEL_TECH/../altera/vhdl/stratixiigx_hssi\narriagx_hssi = $MODEL_TECH/../altera/vhdl/arriagx_hssi\narriaii = $MODEL_TECH/../altera/vhdl/arriaii\narriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi\narriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip\narriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz\narriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi\narriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip\narriagx = $MODEL_TECH/../altera/vhdl/arriagx\naltgxb_lib = $MODEL_TECH/../altera/vhdl/altgxb\nstratixiv = $MODEL_TECH/../altera/vhdl/stratixiv\nstratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi\nstratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip\ncycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv\ncycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi\ncycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip\ncycloneive = $MODEL_TECH/../altera/vhdl/cycloneive\nhardcopyiv_hssi = $MODEL_TECH/../altera/vhdl/hardcopyiv_hssi\nhardcopyiv_pcie_hip = $MODEL_TECH/../altera/vhdl/hardcopyiv_pcie_hip\nstratixv = $MODEL_TECH/../altera/vhdl/stratixv\nstratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi\nstratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip\narriavgz = $MODEL_TECH/../altera/vhdl/arriavgz\narriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi\narriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip\narriav = $MODEL_TECH/../altera/vhdl/arriav\ncyclonev = $MODEL_TECH/../altera/vhdl/cyclonev\n;\n; Verilog Section\n;\naltera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf\naltera_ver = $MODEL_TECH/../altera/verilog/altera\naltera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim\nlpm_ver = $MODEL_TECH/../altera/verilog/220model\n220model_ver = $MODEL_TECH/../altera/verilog/220model\nmax_ver = $MODEL_TECH/../altera/verilog/max\nmaxii_ver = $MODEL_TECH/../altera/verilog/maxii\nmaxv_ver = $MODEL_TECH/../altera/verilog/maxv\nstratix_ver = $MODEL_TECH/../altera/verilog/stratix\nstratixii_ver = $MODEL_TECH/../altera/verilog/stratixii\nstratixiigx_ver = $MODEL_TECH/../altera/verilog/stratixiigx\narriagx_ver = $MODEL_TECH/../altera/verilog/arriagx\nhardcopyii_ver = $MODEL_TECH/../altera/verilog/hardcopyii\nhardcopyiii_ver = $MODEL_TECH/../altera/verilog/hardcopyiii\nhardcopyiv_ver = $MODEL_TECH/../altera/verilog/hardcopyiv\ncyclone_ver = $MODEL_TECH/../altera/verilog/cyclone\ncycloneii_ver = $MODEL_TECH/../altera/verilog/cycloneii\ncycloneiii_ver = $MODEL_TECH/../altera/verilog/cycloneiii\ncycloneiiils_ver = $MODEL_TECH/../altera/verilog/cycloneiiils\nsgate_ver = $MODEL_TECH/../altera/verilog/sgate\nstratixgx_ver = $MODEL_TECH/../altera/verilog/stratixgx\naltgxb_ver = $MODEL_TECH/../altera/verilog/altgxb\nstratixgx_gxb_ver = $MODEL_TECH/../altera/verilog/stratixgx_gxb\nstratixiigx_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiigx_hssi\narriagx_hssi_ver = $MODEL_TECH/../altera/verilog/arriagx_hssi\narriaii_ver = $MODEL_TECH/../altera/verilog/arriaii\narriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi\narriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip\narriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz\narriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi\narriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip\nstratixiii_ver = $MODEL_TECH/../altera/verilog/stratixiii\nstratixiii = $MODEL_TECH/../altera/vhdl/stratixiii\nstratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv\nstratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi\nstratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip\nstratixv_ver = $MODEL_TECH/../altera/verilog/stratixv\nstratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi\nstratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip\narriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz\narriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi\narriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip\narriav_ver = $MODEL_TECH/../altera/verilog/arriav\narriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi\narriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip\ncyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev\ncyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi\ncyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip\ncycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv\ncycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi\ncycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip\ncycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive\nhardcopyiv_hssi_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_hssi\nhardcopyiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_pcie_hip\n\nwork = work\n[vcom]\n; VHDL93 variable selects language version as the default.\n; Default is VHDL-2002.\n; Value of 0 or 1987 for VHDL-1987.\n; Value of 1 or 1993 for VHDL-1993.\n; Default or value of 2 or 2002 for VHDL-2002.\n; Default or value of 3 or 2008 for VHDL-2008.\nVHDL93 = 2002\n\n; Show source line containing error. Default is off.\n; Show_source = 1\n\n; Turn off unbound-component warnings. Default is on.\n; Show_Warning1 = 0\n\n; Turn off process-without-a-wait-statement warnings. Default is on.\n; Show_Warning2 = 0\n\n; Turn off null-range warnings. Default is on.\n; Show_Warning3 = 0\n\n; Turn off no-space-in-time-literal warnings. Default is on.\n; Show_Warning4 = 0\n\n; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.\n; Show_Warning5 = 0\n\n; Turn off optimization for IEEE std_logic_1164 package. Default is on.\n; Optimize_1164 = 0\n\n; Turn on resolving of ambiguous function overloading in favor of the\n; \"explicit\" function declaration (not the one automatically created by\n; the compiler for each type declaration). Default is off.\n; The .ini file has Explicit enabled so that std_logic_signed/unsigned\n; will match the behavior of synthesis tools.\nExplicit = 1\n\n; Turn off acceleration of the VITAL packages. Default is to accelerate.\n; NoVital = 1\n\n; Turn off VITAL compliance checking. Default is checking on.\n; NoVitalCheck = 1\n\n; Ignore VITAL compliance checking errors. Default is to not ignore.\n; IgnoreVitalErrors = 1\n\n; Turn off VITAL compliance checking warnings. Default is to show warnings.\n; Show_VitalChecksWarnings = 0\n\n; Keep silent about case statement static warnings.\n; Default is to give a warning.\n; NoCaseStaticError = 1\n\n; Keep silent about warnings caused by aggregates that are not locally static.\n; Default is to give a warning.\n; NoOthersStaticError = 1\n\n; Turn off inclusion of debugging info within design units.\n; Default is to include debugging info.\n; NoDebug = 1\n\n; Turn off \"Loading...\" messages. Default is messages on.\n; Quiet = 1\n\n; Turn on some limited synthesis rule compliance checking. Checks only:\n;    -- signals used (read) by a process must be in the sensitivity list\n; CheckSynthesis = 1\n\n; Activate optimizations on expressions that do not involve signals,\n; waits, or function/procedure/task invocations. Default is off.\n; ScalarOpts = 1\n\n; Require the user to specify a configuration for all bindings,\n; and do not generate a compile time default binding for the\n; component. This will result in an elaboration error of\n; 'component not bound' if the user fails to do so. Avoids the rare\n; issue of a false dependency upon the unused default binding.\n; RequireConfigForAllDefaultBinding = 1\n\n; Inhibit range checking on subscripts of arrays. Range checking on\n; scalars defined with subtypes is inhibited by default.\n; NoIndexCheck = 1\n\n; Inhibit range checks on all (implicit and explicit) assignments to\n; scalar objects defined with subtypes.\n; NoRangeCheck = 1\n\n[vlog]\n\n; Turn off inclusion of debugging info within design units.\n; Default is to include debugging info.\n; NoDebug = 1\n\n; Turn off \"loading...\" messages. Default is messages on.\n; Quiet = 1\n\n; Turn on Verilog hazard checking (order-dependent accessing of global vars).\n; Default is off.\n; Hazard = 1\n\n; Turn on converting regular Verilog identifiers to uppercase. Allows case\n; insensitivity for module names. Default is no conversion.\n; UpCase = 1\n\n; Turn on incremental compilation of modules. Default is off.\n; Incremental = 1\n\n; Turns on lint-style checking.\n; Show_Lint = 1\n\n[vsim]\n; Simulator resolution\n; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.\nResolution = ps\n\n; User time unit for run commands\n; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the\n; unit specified for Resolution. For example, if Resolution is 100ps,\n; then UserTimeUnit defaults to ps.\n; Should generally be set to default.\nUserTimeUnit = default\n\n; Default run length\nRunLength = 0 ns\n\n; Maximum iterations that can be run without advancing simulation time\nIterationLimit = 5000\n\n; Directive to license manager:\n; vhdl          Immediately reserve a VHDL license\n; vlog          Immediately reserve a Verilog license\n; plus          Immediately reserve a VHDL and Verilog license\n; nomgc         Do not look for Mentor Graphics Licenses\n; nomti         Do not look for Model Technology Licenses\n; noqueue       Do not wait in the license queue when a license isn't available\n; viewsim\tTry for viewer license but accept simulator license(s) instead\n;\t\tof queuing for viewer license\n; License = plus\n\n; Stop the simulator after a VHDL/Verilog assertion message\n; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal\nBreakOnAssertion = 4\n\n; Assertion Message Format\n; %S - Severity Level\n; %R - Report Message\n; %T - Time of assertion\n; %D - Delta\n; %I - Instance or Region pathname (if available)\n; %% - print '%' character\n; AssertionFormat = \"** %S: %R\\n   Time: %T  Iteration: %D%I\\n\"\n\n; Assertion File - alternate file for storing VHDL/Verilog assertion messages\n; AssertFile = assert.log\n\n; Default radix for all windows and commands...\n; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned\nDefaultRadix = symbolic\n\n; VSIM Startup command\n; Startup = do startup.do\n\n; File for saving command transcript\nTranscriptFile = transcript\n\n; File for saving command history\n; CommandHistory = cmdhist.log\n\n; Specify whether paths in simulator commands should be described\n; in VHDL or Verilog format.\n; For VHDL, PathSeparator = /\n; For Verilog, PathSeparator = .\n; Must not be the same character as DatasetSeparator.\nPathSeparator = /\n\n; Specify the dataset separator for fully rooted contexts.\n; The default is ':'. For example, sim:/top\n; Must not be the same character as PathSeparator.\nDatasetSeparator = :\n\n; Disable VHDL assertion messages\n; IgnoreNote = 1\n; IgnoreWarning = 1\n; IgnoreError = 1\n; IgnoreFailure = 1\n\n; Default force kind. May be freeze, drive, deposit, or default\n; or in other terms, fixed, wired, or charged.\n; A value of \"default\" will use the signal kind to determine the\n; force kind, drive for resolved signals, freeze for unresolved signals\n; DefaultForceKind = freeze\n\n; If zero, open files when elaborated; otherwise, open files on\n; first read or write.  Default is 0.\n; DelayFileOpen = 1\n\n; Control VHDL files opened for write.\n;   0 = Buffered, 1 = Unbuffered\nUnbufferedOutput = 0\n\n; Control the number of VHDL files open concurrently.\n; This number should always be less than the current ulimit\n; setting for max file descriptors.\n;   0 = unlimited\nConcurrentFileLimit = 40\n\n; Control the number of hierarchical regions displayed as\n; part of a signal name shown in the Wave window.\n; A value of zero tells VSIM to display the full name.\n; The default is 0.\n; WaveSignalNameWidth = 0\n\n; Turn off warnings from the std_logic_arith, std_logic_unsigned\n; and std_logic_signed packages.\n; StdArithNoWarnings = 1\n\n; Turn off warnings from the IEEE numeric_std and numeric_bit packages.\n; NumericStdNoWarnings = 1\n\n; Control the format of the (VHDL) FOR generate statement label\n; for each iteration.  Do not quote it.\n; The format string here must contain the conversion codes %s and %d,\n; in that order, and no other conversion codes.  The %s represents\n; the generate_label; the %d represents the generate parameter value\n; at a particular generate iteration (this is the position number if\n; the generate parameter is of an enumeration type).  Embedded whitespace\n; is allowed (but discouraged); leading and trailing whitespace is ignored.\n; Application of the format must result in a unique scope name over all\n; such names in the design so that name lookup can function properly.\n; GenerateFormat = %s__%d\n\n; Specify whether checkpoint files should be compressed.\n; The default is 1 (compressed).\n; CheckpointCompressMode = 0\n\n; List of dynamically loaded objects for Verilog PLI applications\n; Veriuser = veriuser.sl\n\n; Specify default options for the restart command. Options can be one\n; or more of: -force -nobreakpoint -nolist -nolog -nowave\n; DefaultRestartOptions = -force\n\n; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs\n; (> 500 megabyte memory footprint). Default is disabled.\n; Specify number of megabytes to lock.\n; LockedMemory = 1000\n\n; Turn on (1) or off (0) WLF file compression.\n; The default is 1 (compress WLF file).\n; WLFCompress = 0\n\n; Specify whether to save all design hierarchy (1) in the WLF file\n; or only regions containing logged signals (0).\n; The default is 0 (save only regions with logged signals).\n; WLFSaveAllRegions = 1\n\n; WLF file time limit.  Limit WLF file by time, as closely as possible,\n; to the specified amount of simulation time.  When the limit is exceeded\n; the earliest times get truncated from the file.\n; If both time and size limits are specified the most restrictive is used.\n; UserTimeUnits are used if time units are not specified.\n; The default is 0 (no limit).  Example: WLFTimeLimit = {100 ms}\n; WLFTimeLimit = 0\n\n; WLF file size limit.  Limit WLF file size, as closely as possible,\n; to the specified number of megabytes.  If both time and size limits\n; are specified then the most restrictive is used.\n; The default is 0 (no limit).\n; WLFSizeLimit = 1000\n\n; Specify whether or not a WLF file should be deleted when the\n; simulation ends.  A value of 1 will cause the WLF file to be deleted.\n; The default is 0 (do not delete WLF file when simulation ends).\n; WLFDeleteOnQuit = 1\n\n; Automatic SDF compilation\n; Disables automatic compilation of SDF files in flows that support it.\n; Default is on, uncomment to turn off.\n; NoAutoSDFCompile = 1\n\nDelayFileOpen = 1\n[lmc]\n\n[msg_system]\n; Change a message severity or suppress a message.\n; The format is: <msg directive> = <msg number>[,<msg number>...]\n; Examples:\n;   note = 3009\n;   warning = 3033\n;   error = 3010,3016\n;   fatal = 3016,3033\n;   suppress = 3009,3016,3043\n; The command verror <msg number> can be used to get the complete\n; description of a message.\n\n; Control transcripting of elaboration/runtime messages.\n; The default is to have messages appear in the transcript and\n; recorded in the wlf file (messages that are recorded in the\n; wlf file can be viewed in the MsgViewer).  The other settings\n; are to send messages only to the transcript or only to the\n; wlf file.  The valid values are\n;    both  {default}\n;    tran  {transcript only}\n;    wlf   {wlf file only}\n; msgmode = both\n[Project]\n; Warning -- Do not edit the project properties directly.\n;            Property names are dynamic in nature and property\n;            values have special syntax.  Changing property data directly\n;            can result in a corrupt MPF file.  All project properties\n;            can be modified through project window dialogs.\nProject_Version = 6\nProject_DefaultLib = work\nProject_SortMethod = unused\nProject_Files_Count = 8\nProject_File_0 = $ROOT/cpu/control/interrupts.v\nProject_File_P_0 = compile_order 1 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder interrupts group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_1 = $ROOT/cpu/control/pin_control.v\nProject_File_P_1 = compile_order 6 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {pin control} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_2 = $ROOT/cpu/control/resets.v\nProject_File_P_2 = compile_order 4 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder reset group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_3 = $ROOT/cpu/control/sequencer.v\nProject_File_P_3 = compile_order 7 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder sequencer group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_4 = $ROOT/cpu/control/test_interrupts.sv\nProject_File_P_4 = compile_order 2 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder interrupts group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_5 = $ROOT/cpu/control/test_pin_control.sv\nProject_File_P_5 = compile_order 0 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder {pin control} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_6 = $ROOT/cpu/control/test_reset.sv\nProject_File_P_6 = compile_order 3 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder reset group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_7 = $ROOT/cpu/control/test_sequencer.sv\nProject_File_P_7 = compile_order 5 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder sequencer group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_Sim_Count = 4\nProject_Sim_0 = Test pin control\nProject_Sim_P_0 = timing default -sdfnoerror 0 -t default -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder {pin control} +pulse_e {} additional_dus work.test_pin_control -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {}\nProject_Sim_1 = Test interrupts\nProject_Sim_P_1 = timing default -sdfnoerror 0 -t default -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder interrupts +pulse_e {} additional_dus work.test_interrupts -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {}\nProject_Sim_2 = Test reset\nProject_Sim_P_2 = timing default -sdfnoerror 0 -t default -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder reset +pulse_e {} additional_dus work.test_reset -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {}\nProject_Sim_3 = Test sequencer\nProject_Sim_P_3 = timing default -t default -sdfnoerror 0 -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder sequencer +pulse_e {} additional_dus work.test_sequencer -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {}\nProject_Folder_Count = 4\nProject_Folder_0 = interrupts\nProject_Folder_P_0 = folder {Top Level}\nProject_Folder_1 = pin control\nProject_Folder_P_1 = folder {Top Level}\nProject_Folder_2 = reset\nProject_Folder_P_2 = folder {Top Level}\nProject_Folder_3 = sequencer\nProject_Folder_P_3 = folder {Top Level}\nEcho_Compile_Output = 0\nSave_Compile_Report = 1\nProject_Opt_Count = 0\nForceSoftPaths = 1\nProjectStatusDelay = 5000\nVERILOG_DoubleClick = Edit\nVERILOG_CustomDoubleClick =\nSYSTEMVERILOG_DoubleClick = Edit\nSYSTEMVERILOG_CustomDoubleClick =\nVHDL_DoubleClick = Edit\nVHDL_CustomDoubleClick =\nPSL_DoubleClick = Edit\nPSL_CustomDoubleClick =\nTEXT_DoubleClick = Edit\nTEXT_CustomDoubleClick =\nSYSTEMC_DoubleClick = Edit\nSYSTEMC_CustomDoubleClick =\nTCL_DoubleClick = Edit\nTCL_CustomDoubleClick =\nMACRO_DoubleClick = Edit\nMACRO_CustomDoubleClick =\nVCD_DoubleClick = Edit\nVCD_CustomDoubleClick =\nSDF_DoubleClick = Edit\nSDF_CustomDoubleClick =\nXML_DoubleClick = Edit\nXML_CustomDoubleClick =\nLOGFILE_DoubleClick = Edit\nLOGFILE_CustomDoubleClick =\nUCDB_DoubleClick = Edit\nUCDB_CustomDoubleClick =\nUPF_DoubleClick = Edit\nUPF_CustomDoubleClick =\nPCF_DoubleClick = Edit\nPCF_CustomDoubleClick =\nPROJECT_DoubleClick = Edit\nPROJECT_CustomDoubleClick =\nVRM_DoubleClick = Edit\nVRM_CustomDoubleClick =\nDEBUGDATABASE_DoubleClick = Edit\nDEBUGDATABASE_CustomDoubleClick =\nDEBUGARCHIVE_DoubleClick = Edit\nDEBUGARCHIVE_CustomDoubleClick =\nProject_Major_Version = 10\nProject_Minor_Version = 1\n"
  },
  {
    "path": "cpu/control/simulation/modelsim/wave_interrupts.do",
    "content": "onerror {resume}\nquietly WaveActivateNextPane {} 0\nadd wave -noupdate /test_interrupts/clk\nadd wave -noupdate /test_interrupts/nreset\nadd wave -noupdate /test_interrupts/ctl_iff1_iff2_sig\nadd wave -noupdate /test_interrupts/nmi_sig\nadd wave -noupdate /test_interrupts/setM1_sig\nadd wave -noupdate /test_interrupts/intr_sig\nadd wave -noupdate /test_interrupts/ctl_iffx_we_sig\nadd wave -noupdate /test_interrupts/ctl_iffx_bit_sig\nadd wave -noupdate /test_interrupts/ctl_im_we_sig\nadd wave -noupdate /test_interrupts/db_sig\nadd wave -noupdate /test_interrupts/ctl_no_ints_sig\nadd wave -noupdate -divider STATE\nadd wave -noupdate -color Aquamarine /test_interrupts/iff1_sig\nadd wave -noupdate -color Aquamarine /test_interrupts/iff2_sig\nadd wave -noupdate -color Pink /test_interrupts/im1_sig\nadd wave -noupdate -color Pink /test_interrupts/im2_sig\nadd wave -noupdate /test_interrupts/in_nmi_sig\nadd wave -noupdate /test_interrupts/in_intr_sig\nTreeUpdate [SetDefaultTree]\nWaveRestoreCursors {{Cursor 1} {1800 ns} 0}\nquietly wave cursor active 1\nconfigure wave -namecolwidth 202\nconfigure wave -valuecolwidth 66\nconfigure wave -justifyvalue left\nconfigure wave -signalnamewidth 0\nconfigure wave -snapdistance 10\nconfigure wave -datasetprefix 0\nconfigure wave -rowmargin 4\nconfigure wave -childrowmargin 2\nconfigure wave -gridoffset 0\nconfigure wave -gridperiod 1\nconfigure wave -griddelta 40\nconfigure wave -timeline 1\nconfigure wave -timelineunits ps\nupdate\nWaveRestoreZoom {0 ns} {25800 ns}\n"
  },
  {
    "path": "cpu/control/simulation/modelsim/wave_pin_control.do",
    "content": "onerror {resume}\nquietly WaveActivateNextPane {} 0\nadd wave -noupdate /test_pin_control/fFetch_sig\nadd wave -noupdate /test_pin_control/fMRead_sig\nadd wave -noupdate /test_pin_control/fMWrite_sig\nadd wave -noupdate /test_pin_control/fIORead_sig\nadd wave -noupdate /test_pin_control/fIOWrite_sig\nadd wave -noupdate /test_pin_control/T1_sig\nadd wave -noupdate /test_pin_control/T2_sig\nadd wave -noupdate /test_pin_control/T3_sig\nadd wave -noupdate /test_pin_control/T4_sig\nadd wave -noupdate -divider STATE\nadd wave -noupdate -color Pink /test_pin_control/bus_ab_pin_we_sig\nadd wave -noupdate -color Pink /test_pin_control/bus_db_pin_oe_sig\nadd wave -noupdate -color Pink /test_pin_control/bus_db_pin_re_sig\nTreeUpdate [SetDefaultTree]\nWaveRestoreCursors {{Cursor 1} {1400 ns} 0}\nquietly wave cursor active 1\nconfigure wave -namecolwidth 240\nconfigure wave -valuecolwidth 54\nconfigure wave -justifyvalue left\nconfigure wave -signalnamewidth 2\nconfigure wave -snapdistance 10\nconfigure wave -datasetprefix 0\nconfigure wave -rowmargin 4\nconfigure wave -childrowmargin 2\nconfigure wave -gridoffset 0\nconfigure wave -gridperiod 1\nconfigure wave -griddelta 40\nconfigure wave -timeline 1\nconfigure wave -timelineunits us\nupdate\nWaveRestoreZoom {0 ns} {4600 ns}\n"
  },
  {
    "path": "cpu/control/simulation/modelsim/wave_reset.do",
    "content": "onerror {resume}\nquietly WaveActivateNextPane {} 0\nadd wave -noupdate /test_reset/clk\nadd wave -noupdate /test_reset/reset_in\nadd wave -noupdate /test_reset/fpga_reset\nadd wave -noupdate /test_reset/M1\nadd wave -noupdate /test_reset/T2\nadd wave -noupdate -color Gold /test_reset/clrpc\nadd wave -noupdate /test_reset/reset_block/nhold_clk_wait\nadd wave -noupdate /test_reset/nreset\nadd wave -noupdate -color {Cadet Blue} /test_reset/reset_block/x1\nadd wave -noupdate -color {Cadet Blue} /test_reset/reset_block/x2\nadd wave -noupdate -color {Cadet Blue} /test_reset/reset_block/x3\nTreeUpdate [SetDefaultTree]\nWaveRestoreCursors {{Cursor 1} {2800 ns} 0}\nquietly wave cursor active 1\nconfigure wave -namecolwidth 112\nconfigure wave -valuecolwidth 73\nconfigure wave -justifyvalue right\nconfigure wave -signalnamewidth 1\nconfigure wave -snapdistance 10\nconfigure wave -datasetprefix 0\nconfigure wave -rowmargin 4\nconfigure wave -childrowmargin 2\nconfigure wave -gridoffset 0\nconfigure wave -gridperiod 1\nconfigure wave -griddelta 40\nconfigure wave -timeline 1\nconfigure wave -timelineunits us\nupdate\nWaveRestoreZoom {0 ns} {13700 ns}\n"
  },
  {
    "path": "cpu/control/simulation/modelsim/wave_sequencer.do",
    "content": "onerror {resume}\nquietly WaveActivateNextPane {} 0\nadd wave -noupdate /test_sequencer/clk\nadd wave -noupdate /test_sequencer/nreset\nadd wave -noupdate /test_sequencer/nextM_sig\nadd wave -noupdate /test_sequencer/setM1_sig\nadd wave -noupdate /test_sequencer/hold_clk_iorq_sig\nadd wave -noupdate /test_sequencer/hold_clk_wait_sig\nadd wave -noupdate /test_sequencer/hold_clk_busrq_sig\nadd wave -noupdate -divider M-STATE\nadd wave -noupdate -color Aquamarine /test_sequencer/M1_sig\nadd wave -noupdate -color Aquamarine /test_sequencer/M2_sig\nadd wave -noupdate -color Aquamarine /test_sequencer/M3_sig\nadd wave -noupdate -color Aquamarine /test_sequencer/M4_sig\nadd wave -noupdate -color Aquamarine /test_sequencer/M5_sig\nadd wave -noupdate -divider T-STATE\nadd wave -noupdate -color Pink /test_sequencer/T1_sig\nadd wave -noupdate -color Pink /test_sequencer/T2_sig\nadd wave -noupdate -color Pink /test_sequencer/T3_sig\nadd wave -noupdate -color Pink /test_sequencer/T4_sig\nadd wave -noupdate -color Pink /test_sequencer/T5_sig\nadd wave -noupdate -color Pink /test_sequencer/T6_sig\nTreeUpdate [SetDefaultTree]\nWaveRestoreCursors {{Cursor 1} {6800 ns} 0}\nquietly wave cursor active 1\nconfigure wave -namecolwidth 226\nconfigure wave -valuecolwidth 78\nconfigure wave -justifyvalue left\nconfigure wave -signalnamewidth 2\nconfigure wave -snapdistance 10\nconfigure wave -datasetprefix 0\nconfigure wave -rowmargin 4\nconfigure wave -childrowmargin 2\nconfigure wave -gridoffset 0\nconfigure wave -gridperiod 1\nconfigure wave -griddelta 40\nconfigure wave -timeline 1\nconfigure wave -timelineunits us\nupdate\nWaveRestoreZoom {0 ns} {25 us}\n"
  },
  {
    "path": "cpu/control/temp_wires.vh",
    "content": "// Automatically generated by gencompile.py\n\nreg ctl_reg_gp_sel_pla17npla50M1T1_2;\nreg ctl_reg_gp_hilo_pla17npla50M1T1_3;\nreg ctl_reg_sys_hilo_pla17npla50M2T1_3;\nreg ctl_reg_sys_hilo_pla17npla50M2T2_4;\nreg ctl_reg_gp_sel_pla61npla58npla59M1T1_2;\nreg ctl_reg_gp_hilo_pla61npla58npla59M1T1_3;\nreg ctl_reg_gp_sel_pla61npla58npla59M1T4_3;\nreg ctl_reg_gp_hilo_pla61npla58npla59M1T4_4;\nreg ctl_reg_gp_sel_use_ixiypla58M1T1_2;\nreg ctl_reg_gp_hilo_use_ixiypla58M1T1_3;\nreg ctl_reg_sys_hilo_use_ixiypla58M2T1_3;\nreg ctl_reg_sys_hilo_use_ixiypla58M2T2_4;\nreg ctl_reg_gp_sel_nuse_ixiypla58M1T1_2;\nreg ctl_reg_gp_hilo_nuse_ixiypla58M1T1_3;\nreg ctl_reg_gp_sel_nuse_ixiypla58M2T1_2;\nreg ctl_reg_gp_hilo_nuse_ixiypla58M2T1_3;\nreg ctl_reg_sys_hilo_use_ixiypla59M2T1_3;\nreg ctl_reg_sys_hilo_use_ixiypla59M2T2_4;\nreg ctl_reg_gp_sel_nuse_ixiypla59M1T4_4;\nreg ctl_reg_gp_hilo_nuse_ixiypla59M1T4_5;\nreg ctl_reg_gp_sel_nuse_ixiypla59M2T1_2;\nreg ctl_reg_gp_hilo_nuse_ixiypla59M2T1_3;\nreg ctl_reg_gp_sel_nuse_ixiypla59M4T1_3;\nreg ctl_reg_gp_hilo_nuse_ixiypla59M4T1_4;\nreg ctl_reg_sys_hilo_pla40M2T1_3;\nreg ctl_reg_sys_hilo_pla40M2T2_4;\nreg ctl_reg_sys_hilo_pla40M3T1_3;\nreg ctl_reg_sys_hilo_pla40M3T2_4;\nreg ctl_reg_sys_hilo_pla50npla40M2T1_3;\nreg ctl_reg_sys_hilo_pla50npla40M2T2_4;\nreg ctl_reg_gp_sel_pla50npla40M3T1_2;\nreg ctl_reg_gp_hilo_pla50npla40M3T1_3;\nreg ctl_reg_gp_sel_pla8pla13M1T4_4;\nreg ctl_reg_gp_hilo_pla8pla13M1T4_5;\nreg ctl_reg_gp_sel_pla8pla13M2T1_2;\nreg ctl_reg_gp_hilo_pla8pla13M2T1_3;\nreg ctl_reg_sys_hilo_pla8pla13M2T2_4;\nreg ctl_reg_gp_sel_pla8npla13M1T1_2;\nreg ctl_reg_gp_hilo_pla8npla13M1T1_3;\nreg ctl_reg_gp_sel_pla8npla13M2T1_2;\nreg ctl_reg_gp_hilo_pla8npla13M2T1_3;\nreg ctl_reg_sys_hilo_pla8npla13M2T2_4;\nreg ctl_reg_sys_hilo_pla38pla13M2T1_3;\nreg ctl_reg_sys_hilo_pla38pla13M2T2_4;\nreg ctl_reg_sys_hilo_pla38pla13M2T3_6;\nreg ctl_reg_sys_hilo_pla38pla13M3T1_3;\nreg ctl_reg_sys_hilo_pla38pla13M3T2_4;\nreg ctl_reg_sys_hilo_pla38pla13M3T3_5;\nreg ctl_reg_sys_hilo_pla38pla13M3T3_10;\nreg ctl_reg_gp_sel_pla38pla13M4T1_3;\nreg ctl_reg_gp_hilo_pla38pla13M4T1_4;\nreg ctl_reg_sys_hilo_pla38pla13M4T2_4;\nreg ctl_reg_gp_sel_pla38npla13M1T1_2;\nreg ctl_reg_gp_hilo_pla38npla13M1T1_3;\nreg ctl_reg_sys_hilo_pla38npla13M2T1_3;\nreg ctl_reg_sys_hilo_pla38npla13M2T2_4;\nreg ctl_reg_sys_hilo_pla38npla13M2T3_6;\nreg ctl_reg_sys_hilo_pla38npla13M3T1_3;\nreg ctl_reg_sys_hilo_pla38npla13M3T2_4;\nreg ctl_reg_sys_hilo_pla38npla13M3T3_6;\nreg ctl_reg_sys_hilo_pla38npla13M4T1_3;\nreg ctl_reg_sys_hilo_pla38npla13M4T2_4;\nreg ctl_reg_gp_sel_pla83M1T1_2;\nreg ctl_reg_gp_hilo_pla83M1T1_3;\nreg ctl_pf_sel_pla83M1T1_19;\nreg ctl_reg_gp_sel_pla83M1T2_2;\nreg ctl_reg_gp_hilo_pla83M1T2_3;\nreg ctl_reg_gp_sel_pla83M1T3_1;\nreg ctl_reg_gp_hilo_pla83M1T3_2;\nreg ctl_reg_sys_hilo_pla83M1T4_3;\nreg ctl_reg_gp_sel_pla57M1T3_1;\nreg ctl_reg_gp_hilo_pla57M1T3_2;\nreg ctl_reg_sys_hilo_pla57M1T4_4;\nreg ctl_reg_gp_sel_pla7M1T1_2;\nreg ctl_reg_gp_hilo_pla7M1T1_3;\nreg ctl_reg_sys_hilo_pla7M2T1_3;\nreg ctl_reg_sys_hilo_pla7M2T2_4;\nreg ctl_reg_sys_hilo_pla7M3T1_3;\nreg ctl_reg_gp_sel_pla7M3T1_6;\nreg ctl_reg_gp_hilo_pla7M3T1_7;\nreg ctl_reg_sys_hilo_pla7M3T2_4;\nreg ctl_reg_sys_hilo_pla30pla13M2T1_3;\nreg ctl_reg_sys_hilo_pla30pla13M2T2_4;\nreg ctl_reg_sys_hilo_pla30pla13M2T3_6;\nreg ctl_reg_sys_hilo_pla30pla13M3T1_3;\nreg ctl_reg_sys_hilo_pla30pla13M3T2_4;\nreg ctl_reg_sys_hilo_pla30pla13M3T3_5;\nreg ctl_reg_sys_hilo_pla30pla13M3T3_10;\nreg ctl_reg_gp_sel_pla30pla13M4T1_3;\nreg ctl_reg_gp_hilo_pla30pla13M4T1_4;\nreg ctl_reg_sys_hilo_pla30pla13M4T2_4;\nreg ctl_reg_sys_hilo_pla30pla13M4T3_5;\nreg ctl_reg_gp_sel_pla30pla13M5T1_3;\nreg ctl_reg_gp_hilo_pla30pla13M5T1_4;\nreg ctl_reg_sys_hilo_pla30pla13M5T2_4;\nreg ctl_reg_sys_hilo_pla30npla13M2T1_3;\nreg ctl_reg_sys_hilo_pla30npla13M2T2_4;\nreg ctl_reg_sys_hilo_pla30npla13M2T3_6;\nreg ctl_reg_sys_hilo_pla30npla13M3T1_3;\nreg ctl_reg_sys_hilo_pla30npla13M3T2_4;\nreg ctl_reg_sys_hilo_pla30npla13M3T3_6;\nreg ctl_reg_sys_hilo_pla30npla13M4T1_3;\nreg ctl_reg_sys_hilo_pla30npla13M4T2_4;\nreg ctl_reg_gp_sel_pla30npla13M4T3_5;\nreg ctl_reg_gp_hilo_pla30npla13M4T3_6;\nreg ctl_reg_sys_hilo_pla30npla13M5T1_3;\nreg ctl_reg_sys_hilo_pla30npla13M5T2_4;\nreg ctl_reg_gp_sel_pla30npla13M5T3_4;\nreg ctl_reg_gp_hilo_pla30npla13M5T3_5;\nreg ctl_reg_sys_hilo_pla31pla33M2T1_3;\nreg ctl_reg_sys_hilo_pla31pla33M2T2_4;\nreg ctl_reg_sys_hilo_pla31pla33M2T3_6;\nreg ctl_reg_sys_hilo_pla31pla33M3T1_3;\nreg ctl_reg_sys_hilo_pla31pla33M3T2_4;\nreg ctl_reg_sys_hilo_pla31pla33M3T3_5;\nreg ctl_reg_sys_hilo_pla31pla33M3T3_10;\nreg ctl_reg_gp_sel_pla31pla33M4T1_3;\nreg ctl_reg_gp_hilo_pla31pla33M4T1_4;\nreg ctl_reg_sys_hilo_pla31pla33M4T2_4;\nreg ctl_reg_sys_hilo_pla31pla33M4T3_5;\nreg ctl_reg_gp_sel_pla31pla33M5T1_3;\nreg ctl_reg_gp_hilo_pla31pla33M5T1_4;\nreg ctl_reg_sys_hilo_pla31pla33M5T2_4;\nreg ctl_reg_sys_hilo_pla31npla33M2T1_3;\nreg ctl_reg_sys_hilo_pla31npla33M2T2_4;\nreg ctl_reg_sys_hilo_pla31npla33M2T3_6;\nreg ctl_reg_sys_hilo_pla31npla33M3T1_3;\nreg ctl_reg_sys_hilo_pla31npla33M3T2_4;\nreg ctl_reg_sys_hilo_pla31npla33M3T3_6;\nreg ctl_reg_sys_hilo_pla31npla33M4T1_3;\nreg ctl_reg_sys_hilo_pla31npla33M4T2_4;\nreg ctl_reg_gp_sel_pla31npla33M4T3_5;\nreg ctl_reg_gp_hilo_pla31npla33M4T3_6;\nreg ctl_reg_sys_hilo_pla31npla33M5T1_3;\nreg ctl_reg_sys_hilo_pla31npla33M5T2_4;\nreg ctl_reg_gp_sel_pla31npla33M5T3_4;\nreg ctl_reg_gp_hilo_pla31npla33M5T3_5;\nreg ctl_reg_gp_sel_pla5M1T4_2;\nreg ctl_reg_gp_hilo_pla5M1T4_3;\nreg ctl_reg_gp_sel_pla5M1T5_2;\nreg ctl_reg_gp_hilo_pla5M1T5_3;\nreg ctl_reg_gp_sel_pla23pla16M1T5_4;\nreg ctl_reg_gp_hilo_pla23pla16M1T5_5;\nreg ctl_reg_gp_sel_pla23pla16M2T1_5;\nreg ctl_reg_gp_hilo_pla23pla16M2T1_6;\nreg ctl_reg_gp_sel_pla23pla16M2T2_3;\nreg ctl_reg_gp_hilo_pla23pla16M2T2_4;\nreg ctl_reg_gp_sel_pla23pla16M2T3_5;\nreg ctl_reg_gp_hilo_pla23pla16M2T3_6;\nreg ctl_reg_gp_sel_pla23pla16M3T1_5;\nreg ctl_reg_gp_hilo_pla23pla16M3T1_6;\nreg ctl_reg_gp_sel_pla23pla16M3T2_3;\nreg ctl_reg_gp_hilo_pla23pla16M3T2_4;\nreg ctl_reg_gp_sel_pla23npla16M2T1_3;\nreg ctl_reg_gp_hilo_pla23npla16M2T1_4;\nreg ctl_reg_gp_sel_pla23npla16M2T2_3;\nreg ctl_reg_gp_hilo_pla23npla16M2T2_4;\nreg ctl_reg_gp_sel_pla23npla16M2T3_5;\nreg ctl_reg_gp_hilo_pla23npla16M2T3_6;\nreg ctl_reg_gp_sel_pla23npla16M3T1_3;\nreg ctl_reg_gp_hilo_pla23npla16M3T1_4;\nreg ctl_reg_gp_sel_pla23npla16M3T2_3;\nreg ctl_reg_gp_hilo_pla23npla16M3T2_4;\nreg ctl_reg_gp_sel_pla23npla16M3T3_4;\nreg ctl_reg_gp_hilo_pla23npla16M3T3_5;\nreg ctl_reg_gp_sel_pla10M2T1_3;\nreg ctl_reg_gp_hilo_pla10M2T1_4;\nreg ctl_reg_gp_sel_pla10M2T2_3;\nreg ctl_reg_gp_hilo_pla10M2T2_4;\nreg ctl_reg_sys_hilo_pla10M2T3_6;\nreg ctl_reg_gp_sel_pla10M3T1_3;\nreg ctl_reg_gp_hilo_pla10M3T1_4;\nreg ctl_reg_gp_sel_pla10M3T2_3;\nreg ctl_reg_gp_hilo_pla10M3T2_4;\nreg ctl_reg_sys_hilo_pla10M3T3_4;\nreg ctl_reg_gp_sel_pla10M3T4_4;\nreg ctl_reg_gp_hilo_pla10M3T4_5;\nreg ctl_reg_gp_sel_pla10M4T1_5;\nreg ctl_reg_gp_hilo_pla10M4T1_6;\nreg ctl_reg_gp_sel_pla10M4T2_3;\nreg ctl_reg_gp_hilo_pla10M4T2_4;\nreg ctl_reg_gp_sel_pla10M4T3_5;\nreg ctl_reg_gp_hilo_pla10M4T3_6;\nreg ctl_reg_gp_sel_pla10M5T1_5;\nreg ctl_reg_gp_hilo_pla10M5T1_6;\nreg ctl_reg_gp_sel_pla10M5T2_3;\nreg ctl_reg_gp_hilo_pla10M5T2_4;\nreg ctl_reg_sys_hilo_pla10M5T3_3;\nreg ctl_reg_gp_sel_pla10M5T4_2;\nreg ctl_reg_gp_hilo_pla10M5T4_3;\nreg ctl_pf_sel_pla12M1T1_12;\nreg ctl_reg_gp_sel_pla12M1T2_2;\nreg ctl_reg_gp_hilo_pla12M1T2_3;\nreg ctl_reg_gp_sel_pla12M1T3_1;\nreg ctl_reg_gp_hilo_pla12M1T3_2;\nreg ctl_reg_gp_sel_pla12M2T1_2;\nreg ctl_reg_gp_hilo_pla12M2T1_3;\nreg ctl_reg_gp_sel_pla12M2T2_3;\nreg ctl_reg_gp_hilo_pla12M2T2_4;\nreg ctl_reg_gp_sel_pla12M3T1_2;\nreg ctl_reg_gp_hilo_pla12M3T1_3;\nreg ctl_reg_gp_sel_pla12M3T2_3;\nreg ctl_reg_gp_hilo_pla12M3T2_4;\nreg ctl_reg_gp_sel_pla12M3T3_2;\nreg ctl_reg_gp_hilo_pla12M3T3_3;\nreg ctl_reg_gp_sel_pla12M3T4_2;\nreg ctl_reg_gp_hilo_pla12M3T4_3;\nreg ctl_reg_sys_hilo_pla12M4T1_2;\nreg ctl_reg_sys_hilo_pla12M4T2_3;\nreg ctl_reg_sys_hilo_pla12M4T3_2;\nreg ctl_reg_sys_hilo_pla12M4T4_3;\nreg ctl_pf_sel_pla11M1T1_11;\nreg ctl_reg_gp_sel_pla11M1T2_2;\nreg ctl_reg_gp_hilo_pla11M1T2_3;\nreg ctl_reg_gp_sel_pla11M1T3_1;\nreg ctl_reg_gp_hilo_pla11M1T3_2;\nreg ctl_reg_gp_sel_pla11M2T1_2;\nreg ctl_reg_gp_hilo_pla11M2T1_3;\nreg ctl_reg_gp_sel_pla11M2T2_3;\nreg ctl_reg_gp_hilo_pla11M2T2_4;\nreg ctl_reg_gp_sel_pla11M3T3_1;\nreg ctl_reg_gp_hilo_pla11M3T3_2;\nreg ctl_reg_gp_sel_pla11M3T4_2;\nreg ctl_reg_gp_hilo_pla11M3T4_3;\nreg ctl_reg_sys_hilo_pla11M4T1_2;\nreg ctl_reg_sys_hilo_pla11M4T2_3;\nreg ctl_reg_sys_hilo_pla11M4T3_2;\nreg ctl_reg_sys_hilo_pla11M4T4_3;\nreg ctl_reg_gp_sel_pla65npla52M1T2_2;\nreg ctl_reg_gp_hilo_pla65npla52M1T2_3;\nreg ctl_reg_gp_sel_pla65npla52M1T3_1;\nreg ctl_reg_gp_hilo_pla65npla52M1T3_2;\nreg ctl_reg_gp_sel_pla65npla52M1T4_3;\nreg ctl_reg_gp_hilo_pla65npla52M1T4_4;\nreg ctl_reg_gp_sel_pla64M1T2_2;\nreg ctl_reg_gp_hilo_pla64M1T2_3;\nreg ctl_reg_gp_sel_pla64M1T3_1;\nreg ctl_reg_gp_hilo_pla64M1T3_2;\nreg ctl_reg_gp_sel_pla64M1T4_4;\nreg ctl_reg_gp_hilo_pla64M1T4_5;\nreg ctl_reg_sys_hilo_pla64M2T1_3;\nreg ctl_reg_sys_hilo_pla64M2T2_4;\nreg ctl_reg_gp_sel_use_ixiypla52M1T3_1;\nreg ctl_reg_gp_hilo_use_ixiypla52M1T3_2;\nreg ctl_reg_sys_hilo_use_ixiypla52M2T1_3;\nreg ctl_reg_sys_hilo_use_ixiypla52M2T2_4;\nreg ctl_reg_gp_sel_nuse_ixiypla52M1T2_2;\nreg ctl_reg_gp_hilo_nuse_ixiypla52M1T2_3;\nreg ctl_reg_gp_sel_nuse_ixiypla52M1T3_1;\nreg ctl_reg_gp_hilo_nuse_ixiypla52M1T3_2;\nreg ctl_reg_gp_sel_nuse_ixiypla52M2T1_2;\nreg ctl_reg_gp_hilo_nuse_ixiypla52M2T1_3;\nreg ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4;\nreg ctl_reg_gp_sel_nuse_ixiypla52M4T2_2;\nreg ctl_reg_gp_hilo_nuse_ixiypla52M4T2_3;\nreg ctl_reg_gp_sel_pla66npla53M1T1_2;\nreg ctl_reg_gp_hilo_pla66npla53M1T1_3;\nreg ctl_pf_sel_pla66npla53M1T1_15;\nreg ctl_reg_gp_sel_pla66npla53M1T2_2;\nreg ctl_reg_gp_hilo_pla66npla53M1T2_3;\nreg ctl_reg_gp_sel_pla66npla53M1T3_1;\nreg ctl_reg_gp_hilo_pla66npla53M1T3_2;\nreg ctl_reg_gp_sel_pla66npla53M1T4nop4op5nop3_1;\nreg ctl_reg_gp_hilo_pla66npla53M1T4nop4op5nop3_2;\nreg ctl_reg_gp_sel_use_ixiypla53M1T3_1;\nreg ctl_reg_gp_hilo_use_ixiypla53M1T3_2;\nreg ctl_reg_sys_hilo_use_ixiypla53M2T1_3;\nreg ctl_reg_sys_hilo_use_ixiypla53M2T2_4;\nreg ctl_reg_gp_sel_nuse_ixiypla53M1T2_2;\nreg ctl_reg_gp_hilo_nuse_ixiypla53M1T2_3;\nreg ctl_reg_gp_sel_nuse_ixiypla53M1T3_1;\nreg ctl_reg_gp_hilo_nuse_ixiypla53M1T3_2;\nreg ctl_reg_gp_sel_nuse_ixiypla53M2T1_2;\nreg ctl_reg_gp_hilo_nuse_ixiypla53M2T1_3;\nreg ctl_pf_sel_nuse_ixiypla53M2T4_14;\nreg ctl_pf_sel_nuse_ixiypla53M4T4_14;\nreg ctl_reg_gp_sel_pla69M1T2_2;\nreg ctl_reg_gp_hilo_pla69M1T2_3;\nreg ctl_reg_gp_sel_pla69M1T3_1;\nreg ctl_reg_gp_hilo_pla69M1T3_2;\nreg ctl_reg_gp_sel_pla69M1T4_3;\nreg ctl_reg_gp_hilo_pla69M1T4_4;\nreg ctl_reg_gp_sel_pla69M2T1_1;\nreg ctl_reg_gp_hilo_pla69M2T1_2;\nreg ctl_reg_sys_hilo_pla69M2T2_3;\nreg ctl_reg_gp_sel_pla69M2T3_1;\nreg ctl_reg_gp_hilo_pla69M2T3_2;\nreg ctl_reg_gp_sel_pla69M2T4_2;\nreg ctl_reg_gp_hilo_pla69M2T4_3;\nreg ctl_reg_sys_hilo_pla69M3T1_2;\nreg ctl_reg_sys_hilo_pla69M3T1_7;\nreg ctl_reg_gp_sel_pla69M3T2_2;\nreg ctl_reg_gp_hilo_pla69M3T2_3;\nreg ctl_reg_gp_sel_op3pla68M1T2_2;\nreg ctl_reg_gp_hilo_op3pla68M1T2_3;\nreg ctl_reg_gp_sel_op3pla68M1T3_1;\nreg ctl_reg_gp_hilo_op3pla68M1T3_2;\nreg ctl_reg_gp_sel_op3pla68M1T4_3;\nreg ctl_reg_gp_hilo_op3pla68M1T4_4;\nreg ctl_reg_gp_sel_op3pla68M2T1_1;\nreg ctl_reg_gp_hilo_op3pla68M2T1_2;\nreg ctl_reg_sys_hilo_op3pla68M2T2_3;\nreg ctl_reg_gp_sel_op3pla68M2T3_1;\nreg ctl_reg_gp_hilo_op3pla68M2T3_2;\nreg ctl_reg_gp_sel_op3pla68M2T4_2;\nreg ctl_reg_gp_hilo_op3pla68M2T4_3;\nreg ctl_reg_sys_hilo_op3pla68M3T1_2;\nreg ctl_reg_sys_hilo_op3pla68M3T1_7;\nreg ctl_pf_sel_op3pla68M3T1_18;\nreg ctl_reg_gp_sel_op3pla68M3T2_2;\nreg ctl_reg_gp_hilo_op3pla68M3T2_3;\nreg ctl_reg_gp_sel_nop3pla68M1T2_2;\nreg ctl_reg_gp_hilo_nop3pla68M1T2_3;\nreg ctl_reg_gp_sel_nop3pla68M1T3_1;\nreg ctl_reg_gp_hilo_nop3pla68M1T3_2;\nreg ctl_reg_gp_sel_nop3pla68M1T4_3;\nreg ctl_reg_gp_hilo_nop3pla68M1T4_4;\nreg ctl_reg_gp_sel_nop3pla68M2T1_1;\nreg ctl_reg_gp_hilo_nop3pla68M2T1_2;\nreg ctl_reg_sys_hilo_nop3pla68M2T2_3;\nreg ctl_reg_gp_sel_nop3pla68M2T3_1;\nreg ctl_reg_gp_hilo_nop3pla68M2T3_2;\nreg ctl_reg_gp_sel_nop3pla68M2T4_2;\nreg ctl_reg_gp_hilo_nop3pla68M2T4_3;\nreg ctl_reg_sys_hilo_nop3pla68M3T1_2;\nreg ctl_reg_sys_hilo_nop3pla68M3T1_7;\nreg ctl_pf_sel_nop3pla68M3T1_20;\nreg ctl_reg_gp_sel_nop3pla68M3T2_2;\nreg ctl_reg_gp_hilo_nop3pla68M3T2_3;\nreg ctl_reg_gp_sel_pla9M1T4_2;\nreg ctl_reg_gp_hilo_pla9M1T4_3;\nreg ctl_reg_gp_sel_pla9M1T5_2;\nreg ctl_reg_gp_hilo_pla9M1T5_3;\nreg ctl_reg_gp_sel_pla77M1T1_2;\nreg ctl_reg_gp_hilo_pla77M1T1_3;\nreg ctl_pf_sel_pla77M1T1_14;\nreg ctl_reg_gp_sel_pla77M1T2_2;\nreg ctl_reg_gp_hilo_pla77M1T2_3;\nreg ctl_reg_gp_sel_pla77M1T3_1;\nreg ctl_reg_gp_hilo_pla77M1T3_2;\nreg ctl_reg_gp_sel_pla81M1T1_2;\nreg ctl_reg_gp_hilo_pla81M1T1_3;\nreg ctl_reg_gp_sel_pla81M1T2_2;\nreg ctl_reg_gp_hilo_pla81M1T2_3;\nreg ctl_reg_gp_sel_pla81M1T3_1;\nreg ctl_reg_gp_hilo_pla81M1T3_2;\nreg ctl_reg_gp_sel_pla82M1T1_2;\nreg ctl_reg_gp_hilo_pla82M1T1_3;\nreg ctl_pf_sel_pla82M1T1_16;\nreg ctl_reg_gp_sel_pla82M1T2_2;\nreg ctl_reg_gp_hilo_pla82M1T2_3;\nreg ctl_reg_gp_sel_pla82M1T3_1;\nreg ctl_reg_gp_hilo_pla82M1T3_2;\nreg ctl_reg_gp_sel_pla89M1T2_2;\nreg ctl_reg_gp_hilo_pla89M1T2_3;\nreg ctl_reg_gp_sel_pla89M1T3_1;\nreg ctl_reg_gp_hilo_pla89M1T3_2;\nreg ctl_reg_gp_sel_pla92M1T2_2;\nreg ctl_reg_gp_hilo_pla92M1T2_3;\nreg ctl_reg_gp_sel_pla92M1T3_1;\nreg ctl_reg_gp_hilo_pla92M1T3_2;\nreg ctl_reg_gp_sel_pla25M1T1_2;\nreg ctl_reg_gp_hilo_pla25M1T1_3;\nreg ctl_reg_gp_sel_pla25M1T2_2;\nreg ctl_reg_gp_hilo_pla25M1T2_3;\nreg ctl_reg_gp_sel_pla25M1T3_1;\nreg ctl_reg_gp_hilo_pla25M1T3_2;\nreg ctl_reg_gp_sel_pla25M1T4_3;\nreg ctl_reg_gp_hilo_pla25M1T4_4;\nreg ctl_reg_gp_sel_nuse_ixiypla70npla55M1T1_2;\nreg ctl_reg_gp_hilo_nuse_ixiypla70npla55M1T1_3;\nreg ctl_pf_sel_nuse_ixiypla70npla55M1T1_20;\nreg ctl_reg_gp_sel_nuse_ixiypla70npla55M1T2_2;\nreg ctl_reg_gp_hilo_nuse_ixiypla70npla55M1T2_3;\nreg ctl_reg_gp_sel_nuse_ixiypla70npla55M1T3_1;\nreg ctl_reg_gp_hilo_nuse_ixiypla70npla55M1T3_2;\nreg ctl_reg_gp_sel_nuse_ixiypla70npla55M1T4_3;\nreg ctl_reg_gp_hilo_nuse_ixiypla70npla55M1T4_4;\nreg ctl_reg_sys_hilo_nuse_ixiypla70npla55M4T1_3;\nreg ctl_pf_sel_nuse_ixiypla70npla55M5T1_19;\nreg ctl_reg_gp_sel_nuse_ixiypla70pla55M1T2_2;\nreg ctl_reg_gp_hilo_nuse_ixiypla70pla55M1T2_3;\nreg ctl_reg_gp_sel_nuse_ixiypla70pla55M1T3_1;\nreg ctl_reg_gp_hilo_nuse_ixiypla70pla55M1T3_2;\nreg ctl_reg_gp_sel_nuse_ixiypla70pla55M2T1_2;\nreg ctl_reg_gp_hilo_nuse_ixiypla70pla55M2T1_3;\nreg ctl_pf_sel_nuse_ixiypla70pla55M3T1_19;\nreg ctl_reg_sys_hilo_nuse_ixiypla70pla55M4T1_3;\nreg ctl_pf_sel_nuse_ixiypla70pla55M5T1_19;\nreg ctl_reg_gp_sel_pla15op3M1T1_2;\nreg ctl_reg_gp_hilo_pla15op3M1T1_3;\nreg ctl_pf_sel_pla15op3M1T1_18;\nreg ctl_reg_gp_sel_pla15op3M1T2_2;\nreg ctl_reg_gp_hilo_pla15op3M1T2_3;\nreg ctl_reg_gp_sel_pla15op3M1T3_1;\nreg ctl_reg_gp_hilo_pla15op3M1T3_2;\nreg ctl_reg_gp_sel_pla15op3M2T1_2;\nreg ctl_reg_gp_hilo_pla15op3M2T1_3;\nreg ctl_reg_sys_hilo_pla15op3M2T2_4;\nreg ctl_reg_gp_sel_pla15nop3M1T1_2;\nreg ctl_reg_gp_hilo_pla15nop3M1T1_3;\nreg ctl_pf_sel_pla15nop3M1T1_18;\nreg ctl_reg_gp_sel_pla15nop3M1T2_2;\nreg ctl_reg_gp_hilo_pla15nop3M1T2_3;\nreg ctl_reg_gp_sel_pla15nop3M1T3_1;\nreg ctl_reg_gp_hilo_pla15nop3M1T3_2;\nreg ctl_reg_gp_sel_pla15nop3M2T1_2;\nreg ctl_reg_gp_hilo_pla15nop3M2T1_3;\nreg ctl_reg_sys_hilo_pla15nop3M2T2_4;\nreg ctl_reg_gp_sel_pla15nop3M3T3_1;\nreg ctl_reg_gp_hilo_pla15nop3M3T3_2;\nreg ctl_pf_sel_nuse_ixiypla72npla55M1T1_10;\nreg ctl_reg_gp_sel_nuse_ixiypla72npla55M1T2_2;\nreg ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T2_3;\nreg ctl_reg_gp_sel_nuse_ixiypla72npla55M1T3_1;\nreg ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T3_2;\nreg ctl_reg_gp_sel_nuse_ixiypla72npla55M1T4_3;\nreg ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4;\nreg ctl_pf_sel_nuse_ixiypla72pla55M1T1_10;\nreg ctl_reg_gp_sel_nuse_ixiypla72pla55M1T2_2;\nreg ctl_reg_gp_hilo_nuse_ixiypla72pla55M1T2_3;\nreg ctl_reg_gp_sel_nuse_ixiypla72pla55M1T3_1;\nreg ctl_reg_gp_hilo_nuse_ixiypla72pla55M1T3_2;\nreg ctl_reg_gp_sel_nuse_ixiypla72pla55M2T1_2;\nreg ctl_reg_gp_hilo_nuse_ixiypla72pla55M2T1_3;\nreg ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3;\nreg ctl_reg_sys_hilo_nuse_ixiypla72pla55M4T1_3;\nreg ctl_reg_gp_sel_nuse_ixiypla74npla55M1T1_2;\nreg ctl_reg_gp_hilo_nuse_ixiypla74npla55M1T1_3;\nreg ctl_reg_gp_sel_nuse_ixiypla74npla55M1T3_1;\nreg ctl_reg_gp_hilo_nuse_ixiypla74npla55M1T3_2;\nreg ctl_reg_gp_sel_nuse_ixiypla74npla55M1T4_3;\nreg ctl_reg_gp_hilo_nuse_ixiypla74npla55M1T4_4;\nreg ctl_reg_sys_hilo_nuse_ixiypla74npla55M4T1_3;\nreg ctl_reg_gp_sel_nuse_ixiypla74pla55M1T3_1;\nreg ctl_reg_gp_hilo_nuse_ixiypla74pla55M1T3_2;\nreg ctl_reg_gp_sel_nuse_ixiypla74pla55M2T1_2;\nreg ctl_reg_gp_hilo_nuse_ixiypla74pla55M2T1_3;\nreg ctl_reg_sys_hilo_nuse_ixiypla74pla55M4T1_3;\nreg ctl_reg_gp_sel_nuse_ixiypla73npla55M1T1_2;\nreg ctl_reg_gp_hilo_nuse_ixiypla73npla55M1T1_3;\nreg ctl_reg_gp_sel_nuse_ixiypla73npla55M1T3_1;\nreg ctl_reg_gp_hilo_nuse_ixiypla73npla55M1T3_2;\nreg ctl_reg_gp_sel_nuse_ixiypla73npla55M1T4_3;\nreg ctl_reg_gp_hilo_nuse_ixiypla73npla55M1T4_4;\nreg ctl_reg_sys_hilo_nuse_ixiypla73npla55M4T1_3;\nreg ctl_reg_gp_sel_nuse_ixiypla73pla55M1T3_1;\nreg ctl_reg_gp_hilo_nuse_ixiypla73pla55M1T3_2;\nreg ctl_reg_gp_sel_nuse_ixiypla73pla55M2T1_2;\nreg ctl_reg_gp_hilo_nuse_ixiypla73pla55M2T1_3;\nreg ctl_reg_sys_hilo_nuse_ixiypla73pla55M4T1_3;\nreg ctl_reg_gp_sel_pla37npla28M1T1_2;\nreg ctl_reg_gp_hilo_pla37npla28M1T1_3;\nreg ctl_reg_sys_hilo_pla37npla28M2T1_3;\nreg ctl_reg_sys_hilo_pla37npla28M2T2_4;\nreg ctl_reg_gp_sel_pla37npla28M3T1_2;\nreg ctl_reg_gp_hilo_pla37npla28M3T1_3;\nreg ctl_reg_gp_sel_pla27npla34M1T1_2;\nreg ctl_reg_gp_hilo_pla27npla34M1T1_3;\nreg ctl_pf_sel_pla27npla34M1T1_20;\nreg ctl_reg_gp_sel_pla27npla34M1T2_2;\nreg ctl_reg_gp_hilo_pla27npla34M1T2_3;\nreg ctl_reg_gp_sel_pla27npla34M1T3_1;\nreg ctl_reg_gp_hilo_pla27npla34M1T3_2;\nreg ctl_reg_gp_sel_pla27npla34M2T1_2;\nreg ctl_reg_gp_hilo_pla27npla34M2T1_3;\nreg ctl_reg_sys_hilo_pla37pla28M2T1_3;\nreg ctl_reg_sys_hilo_pla37pla28M2T2_4;\nreg ctl_reg_gp_sel_pla37pla28M2T3_4;\nreg ctl_reg_gp_hilo_pla37pla28M2T3_5;\nreg ctl_reg_gp_sel_pla37pla28M3T1_3;\nreg ctl_reg_gp_hilo_pla37pla28M3T1_4;\nreg ctl_reg_gp_sel_pla27pla34M1T4nop4op5nop3_1;\nreg ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2;\nreg ctl_reg_gp_sel_pla27pla34M2T1_2;\nreg ctl_reg_gp_hilo_pla27pla34M2T1_3;\nreg ctl_pf_sel_pla91pla21M1T1_8;\nreg ctl_reg_gp_sel_pla91pla21M1T2_2;\nreg ctl_reg_gp_hilo_pla91pla21M1T2_3;\nreg ctl_reg_gp_sel_pla91pla21M1T3_1;\nreg ctl_reg_gp_hilo_pla91pla21M1T3_2;\nreg ctl_reg_gp_sel_pla91pla21M2T1_2;\nreg ctl_reg_gp_hilo_pla91pla21M2T1_3;\nreg ctl_reg_gp_sel_pla91pla21M2T2_2;\nreg ctl_reg_gp_hilo_pla91pla21M2T2_3;\nreg ctl_reg_gp_sel_pla91pla21M2T3_3;\nreg ctl_reg_gp_hilo_pla91pla21M2T3_4;\nreg ctl_reg_gp_sel_pla91pla21M3T1_2;\nreg ctl_reg_gp_hilo_pla91pla21M3T1_3;\nreg ctl_reg_gp_sel_pla91pla21M3T2_3;\nreg ctl_reg_gp_hilo_pla91pla21M3T2_4;\nreg ctl_reg_sys_hilo_pla91pla21M4T1_2;\nreg ctl_reg_sys_hilo_pla91pla21M4T2_3;\nreg ctl_reg_sys_hilo_pla91pla21M4T3_2;\nreg ctl_reg_sys_hilo_pla91pla21M4T4_3;\nreg ctl_pf_sel_pla91pla20M1T1_9;\nreg ctl_reg_gp_sel_pla91pla20M1T2_2;\nreg ctl_reg_gp_hilo_pla91pla20M1T2_3;\nreg ctl_reg_gp_sel_pla91pla20M1T3_1;\nreg ctl_reg_gp_hilo_pla91pla20M1T3_2;\nreg ctl_reg_gp_sel_pla91pla20M1T4_2;\nreg ctl_reg_gp_hilo_pla91pla20M1T4_3;\nreg ctl_reg_gp_sel_pla91pla20M1T5_4;\nreg ctl_reg_gp_hilo_pla91pla20M1T5_5;\nreg ctl_reg_gp_sel_pla91pla20M2T1_2;\nreg ctl_reg_gp_hilo_pla91pla20M2T1_3;\nreg ctl_reg_gp_sel_pla91pla20M2T2_3;\nreg ctl_reg_gp_hilo_pla91pla20M2T2_4;\nreg ctl_reg_gp_sel_pla91pla20M2T3_4;\nreg ctl_reg_gp_hilo_pla91pla20M2T3_5;\nreg ctl_reg_gp_sel_pla91pla20M3T1_2;\nreg ctl_reg_gp_hilo_pla91pla20M3T1_3;\nreg ctl_reg_sys_hilo_pla91pla20M4T1_2;\nreg ctl_reg_sys_hilo_pla91pla20M4T2_3;\nreg ctl_reg_sys_hilo_pla91pla20M4T3_2;\nreg ctl_reg_sys_hilo_pla91pla20M4T4_3;\nreg ctl_reg_sys_hilo_pla29M2T1_3;\nreg ctl_reg_sys_hilo_pla29M2T2_4;\nreg ctl_reg_sys_hilo_pla29M2T3_6;\nreg ctl_reg_sys_hilo_pla29M3T1_3;\nreg ctl_reg_sys_hilo_pla29M3T2_4;\nreg ctl_reg_sys_hilo_pla29M3T3_4;\nreg ctl_reg_sys_hilo_pla29M3T3_9;\nreg ctl_reg_gp_sel_pla43M1T3_1;\nreg ctl_reg_gp_hilo_pla43M1T3_2;\nreg ctl_reg_sys_hilo_pla43M2T1_3;\nreg ctl_reg_sys_hilo_pla43M2T2_4;\nreg ctl_reg_sys_hilo_pla43M2T3_6;\nreg ctl_reg_sys_hilo_pla43M3T1_3;\nreg ctl_reg_sys_hilo_pla43M3T2_4;\nreg ctl_reg_sys_hilo_pla43M3T3_5;\nreg ctl_reg_sys_hilo_pla43M3T3_10;\nreg ctl_reg_gp_sel_pla47M1T3_1;\nreg ctl_reg_gp_hilo_pla47M1T3_2;\nreg ctl_reg_sys_hilo_pla47M2T1_3;\nreg ctl_reg_sys_hilo_pla47M2T2_4;\nreg ctl_reg_sys_hilo_pla47M3T2_2;\nreg ctl_reg_sys_hilo_pla47M3T3_3;\nreg ctl_reg_sys_hilo_pla47M3T4_2;\nreg ctl_reg_sys_hilo_pla47M3T5_3;\nreg ctl_reg_sys_hilo_pla47M3T5_8;\nreg ctl_reg_gp_sel_pla48M1T3_1;\nreg ctl_reg_gp_hilo_pla48M1T3_2;\nreg ctl_reg_sys_hilo_pla48M2T1_3;\nreg ctl_reg_sys_hilo_pla48M2T2_4;\nreg ctl_reg_sys_hilo_pla48M3T2_2;\nreg ctl_reg_sys_hilo_pla48M3T3_3;\nreg ctl_reg_sys_hilo_pla48M3T4_2;\nreg ctl_reg_sys_hilo_pla48M3T5_3;\nreg ctl_reg_sys_hilo_pla48M3T5_8;\nreg ctl_reg_gp_sel_pla6M1T4_3;\nreg ctl_reg_gp_hilo_pla6M1T4_4;\nreg ctl_reg_gp_sel_pla26M1T3_1;\nreg ctl_reg_gp_hilo_pla26M1T3_2;\nreg ctl_reg_gp_sel_pla26M1T4_2;\nreg ctl_reg_gp_hilo_pla26M1T4_3;\nreg ctl_reg_gp_sel_pla26M1T5_4;\nreg ctl_reg_gp_hilo_pla26M1T5_5;\nreg ctl_reg_sys_hilo_pla26M2T1_3;\nreg ctl_reg_sys_hilo_pla26M2T2_4;\nreg ctl_reg_sys_hilo_pla26M3T2_2;\nreg ctl_reg_sys_hilo_pla26M3T3_3;\nreg ctl_reg_sys_hilo_pla26M3T4_2;\nreg ctl_reg_sys_hilo_pla26M3T5_3;\nreg ctl_reg_sys_hilo_pla26M3T5_8;\nreg ctl_reg_sys_hilo_pla24M2T1_3;\nreg ctl_reg_sys_hilo_pla24M2T2_4;\nreg ctl_reg_sys_hilo_pla24M2T3_6;\nreg ctl_reg_sys_hilo_pla24M3T1_3;\nreg ctl_reg_sys_hilo_pla24M3T2_4;\nreg ctl_reg_sys_hilo_pla24M3T3_4;\nreg ctl_reg_gp_sel_pla24M3T4_4;\nreg ctl_reg_gp_hilo_pla24M3T4_5;\nreg ctl_reg_sys_hilo_pla24M4T1_6;\nreg ctl_reg_gp_sel_pla24M4T2_3;\nreg ctl_reg_gp_hilo_pla24M4T2_4;\nreg ctl_reg_gp_sel_pla24M4T3_5;\nreg ctl_reg_gp_hilo_pla24M4T3_6;\nreg ctl_reg_sys_hilo_pla24M5T1_6;\nreg ctl_reg_gp_sel_pla24M5T2_3;\nreg ctl_reg_gp_hilo_pla24M5T2_4;\nreg ctl_reg_sys_hilo_pla24M5T3_4;\nreg ctl_reg_gp_sel_pla42M1T3_1;\nreg ctl_reg_gp_hilo_pla42M1T3_2;\nreg ctl_reg_sys_hilo_pla42M2T1_3;\nreg ctl_reg_sys_hilo_pla42M2T2_4;\nreg ctl_reg_sys_hilo_pla42M2T3_6;\nreg ctl_reg_sys_hilo_pla42M3T1_3;\nreg ctl_reg_sys_hilo_pla42M3T2_4;\nreg ctl_reg_sys_hilo_pla42M3T3_6;\nreg ctl_reg_gp_sel_pla42M3T4_4;\nreg ctl_reg_gp_hilo_pla42M3T4_5;\nreg ctl_reg_sys_hilo_pla42M4T1_6;\nreg ctl_reg_gp_sel_pla42M4T2_3;\nreg ctl_reg_gp_hilo_pla42M4T2_4;\nreg ctl_reg_gp_sel_pla42M4T3_5;\nreg ctl_reg_gp_hilo_pla42M4T3_6;\nreg ctl_reg_sys_hilo_pla42M5T1_6;\nreg ctl_reg_gp_sel_pla42M5T2_3;\nreg ctl_reg_gp_hilo_pla42M5T2_4;\nreg ctl_reg_sys_hilo_pla42M5T3_4;\nreg ctl_reg_gp_sel_pla35M2T1_3;\nreg ctl_reg_gp_hilo_pla35M2T1_4;\nreg ctl_reg_gp_sel_pla35M2T2_3;\nreg ctl_reg_gp_hilo_pla35M2T2_4;\nreg ctl_reg_sys_hilo_pla35M2T3_6;\nreg ctl_reg_gp_sel_pla35M3T1_3;\nreg ctl_reg_gp_hilo_pla35M3T1_4;\nreg ctl_reg_gp_sel_pla35M3T2_3;\nreg ctl_reg_gp_hilo_pla35M3T2_4;\nreg ctl_reg_sys_hilo_pla35M3T3_4;\nreg ctl_reg_sys_hilo_pla35M3T3_9;\nreg ctl_reg_gp_sel_pla45M1T3_1;\nreg ctl_reg_gp_hilo_pla45M1T3_2;\nreg ctl_reg_gp_sel_pla45M2T1_3;\nreg ctl_reg_gp_hilo_pla45M2T1_4;\nreg ctl_reg_gp_sel_pla45M2T2_3;\nreg ctl_reg_gp_hilo_pla45M2T2_4;\nreg ctl_reg_sys_hilo_pla45M2T3_6;\nreg ctl_reg_gp_sel_pla45M3T1_3;\nreg ctl_reg_gp_hilo_pla45M3T1_4;\nreg ctl_reg_gp_sel_pla45M3T2_3;\nreg ctl_reg_gp_hilo_pla45M3T2_4;\nreg ctl_reg_sys_hilo_pla45M3T3_4;\nreg ctl_reg_sys_hilo_pla45M3T3_9;\nreg ctl_reg_gp_sel_pla46M2T1_3;\nreg ctl_reg_gp_hilo_pla46M2T1_4;\nreg ctl_reg_gp_sel_pla46M2T2_3;\nreg ctl_reg_gp_hilo_pla46M2T2_4;\nreg ctl_reg_sys_hilo_pla46M2T3_6;\nreg ctl_reg_gp_sel_pla46M3T1_3;\nreg ctl_reg_gp_hilo_pla46M3T1_4;\nreg ctl_reg_gp_sel_pla46M3T2_3;\nreg ctl_reg_gp_hilo_pla46M3T2_4;\nreg ctl_reg_sys_hilo_pla46M3T3_4;\nreg ctl_reg_sys_hilo_pla46M3T3_9;\nreg ctl_reg_sys_hilo_pla56M1T3_3;\nreg ctl_reg_gp_sel_pla56M1T5_4;\nreg ctl_reg_gp_hilo_pla56M1T5_5;\nreg ctl_reg_sys_hilo_pla56M2T1_6;\nreg ctl_reg_gp_sel_pla56M2T2_3;\nreg ctl_reg_gp_hilo_pla56M2T2_4;\nreg ctl_reg_gp_sel_pla56M2T3_5;\nreg ctl_reg_gp_hilo_pla56M2T3_6;\nreg ctl_reg_sys_hilo_pla56M3T1_6;\nreg ctl_reg_gp_sel_pla56M3T2_3;\nreg ctl_reg_gp_hilo_pla56M3T2_4;\nreg ctl_reg_sys_hilo_pla56M3T3_6;\nreg ctl_reg_sys_hilo_pla56M4T1_3;\nreg ctl_reg_sys_hilo_pla56M4T3_6;\nreg ctl_reg_sys_hilo_pla56M5T1_3;\nreg ctl_reg_sys_hilo_pla56M5T3_4;\nreg ctl_reg_sys_hilo_pla56M5T3_9;\nreg ctl_reg_gp_sel_pla49M1T3_1;\nreg ctl_reg_gp_hilo_pla49M1T3_2;\nreg ctl_reg_sys_hilo_pla49M2T1_3;\nreg ctl_reg_sys_hilo_pla49M2T2_4;\nreg ctl_reg_sys_hilo_pla49M3T1_3;\nreg ctl_reg_sys_hilo_pla49M3T2_4;\nreg ctl_pf_sel_pla76M1T1_2;\nreg ctl_reg_gp_sel_pla78M1T1_2;\nreg ctl_reg_gp_hilo_pla78M1T1_3;\nreg ctl_pf_sel_pla78M1T1_8;\nreg ctl_reg_gp_sel_pla79M1T1_2;\nreg ctl_reg_gp_hilo_pla79M1T1_3;\nreg ctl_pf_sel_pla79M1T1_8;\nreg ctl_reg_gp_sel_pla80M1T1_2;\nreg ctl_reg_gp_hilo_pla80M1T1_3;\nreg ctl_pf_sel_pla80M1T1_8;\nreg ctl_reg_gp_sel_pla84M1T1_2;\nreg ctl_reg_gp_hilo_pla84M1T1_3;\nreg ctl_pf_sel_pla84M1T1_8;\nreg ctl_reg_gp_sel_pla85M1T1_2;\nreg ctl_reg_gp_hilo_pla85M1T1_3;\nreg ctl_pf_sel_pla85M1T1_8;\nreg ctl_reg_gp_sel_pla86M1T1_2;\nreg ctl_reg_gp_hilo_pla86M1T1_3;\nreg ctl_pf_sel_pla86M1T1_8;\nreg ctl_reg_gp_sel_pla88M1T1_2;\nreg ctl_reg_gp_hilo_pla88M1T1_3;\nreg ctl_pf_sel_pla88M1T1_8;\nreg ctl_reg_gp_sel_ixy_dT2_1;\nreg ctl_reg_gp_hilo_ixy_dT2_2;\nreg ctl_reg_sys_hilo_ixy_dT3_3;\nreg ctl_reg_gp_sel_ixy_dT4_1;\nreg ctl_reg_gp_hilo_ixy_dT4_2;\nreg ctl_reg_sys_hilo_ixy_dT5_2;\nreg ctl_reg_sys_hilo_ixy_dT5_7;\nreg ctl_reg_sys_hilo_1M1T1_3;\nreg ctl_reg_sys_hilo_1M1T2_2;\nreg ctl_reg_sys_hilo_1M1T3_3;\nreg ctl_reg_sys_hilo_setM1_2;\n"
  },
  {
    "path": "cpu/control/test_control.qpf",
    "content": "# -------------------------------------------------------------------------- #\n#\n# Copyright (C) 1991-2013 Altera Corporation\n# Your use of Altera Corporation's design tools, logic functions \n# and other software and tools, and its AMPP partner logic \n# functions, and any output files from any of the foregoing \n# (including device programming or simulation files), and any \n# associated documentation or information are expressly subject \n# to the terms and conditions of the Altera Program License \n# Subscription Agreement, Altera MegaCore Function License \n# Agreement, or other applicable license agreement, including, \n# without limitation, that your use is for the sole purpose of \n# programming logic devices manufactured by Altera and sold by \n# Altera or its authorized distributors.  Please refer to the \n# applicable agreement for further details.\n#\n# -------------------------------------------------------------------------- #\n#\n# Quartus II 64-Bit\n# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\n# Date created = 09:22:29  October 13, 2014\n#\n# -------------------------------------------------------------------------- #\n\nQUARTUS_VERSION = \"13.0\"\nDATE = \"09:22:29  October 13, 2014\"\n\n# Revisions\n\nPROJECT_REVISION = \"test_control\"\n"
  },
  {
    "path": "cpu/control/test_control.qsf",
    "content": "# -------------------------------------------------------------------------- #\n#\n# Copyright (C) 1991-2013 Altera Corporation\n# Your use of Altera Corporation's design tools, logic functions\n# and other software and tools, and its AMPP partner logic\n# functions, and any output files from any of the foregoing\n# (including device programming or simulation files), and any\n# associated documentation or information are expressly subject\n# to the terms and conditions of the Altera Program License\n# Subscription Agreement, Altera MegaCore Function License\n# Agreement, or other applicable license agreement, including,\n# without limitation, that your use is for the sole purpose of\n# programming logic devices manufactured by Altera and sold by\n# Altera or its authorized distributors.  Please refer to the\n# applicable agreement for further details.\n#\n# -------------------------------------------------------------------------- #\n#\n# Quartus II 64-Bit\n# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\n# Date created = 09:22:29  October 13, 2014\n#\n# -------------------------------------------------------------------------- #\n#\n# Notes:\n#\n# 1) The default values for assignments are stored in the file:\n#\t\ttest_control_assignment_defaults.qdf\n#    If this file doesn't exist, see file:\n#\t\tassignment_defaults.qdf\n#\n# 2) Altera recommends that you do not modify this file. This\n#    file is updated automatically by the Quartus II software\n#    and any changes you make may be lost or overwritten.\n#\n# -------------------------------------------------------------------------- #\n\n\nset_global_assignment -name FAMILY \"Cyclone II\"\nset_global_assignment -name DEVICE EP2C20F484C7\nset_global_assignment -name TOP_LEVEL_ENTITY execute\nset_global_assignment -name ORIGINAL_QUARTUS_VERSION \"13.0 SP1\"\nset_global_assignment -name PROJECT_CREATION_TIME_DATE \"09:22:29  OCTOBER 13, 2014\"\nset_global_assignment -name LAST_QUARTUS_VERSION \"13.0 SP1\"\nset_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files\nset_global_assignment -name MIN_CORE_JUNCTION_TEMP 0\nset_global_assignment -name MAX_CORE_JUNCTION_TEMP 85\nset_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1\nset_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top\nset_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top\nset_global_assignment -name PARTITION_COLOR 16764057 -section_id Top\nset_global_assignment -name POWER_PRESET_COOLING_SOLUTION \"23 MM HEAT SINK WITH 200 LFPM AIRFLOW\"\nset_global_assignment -name POWER_BOARD_THERMAL_MODEL \"NONE (CONSERVATIVE)\"\nset_global_assignment -name USE_CONFIGURATION_DEVICE ON\nset_global_assignment -name RESERVE_ALL_UNUSED_PINS \"AS INPUT TRI-STATED WITH WEAK PULL-UP\"\nset_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON\nset_global_assignment -name SMART_RECOMPILE ON\nset_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON\nset_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS OFF\nset_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005\nset_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF\nset_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON\nset_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON\nset_global_assignment -name VERILOG_FILE pla_decode.v\nset_global_assignment -name VERILOG_FILE execute.v\nset_global_assignment -name BDF_FILE sequencer.bdf\nset_global_assignment -name BDF_FILE resets.bdf\nset_global_assignment -name BDF_FILE memory_ifc.bdf\nset_global_assignment -name BDF_FILE ir.bdf\nset_global_assignment -name BDF_FILE interrupts.bdf\nset_global_assignment -name BDF_FILE decode_state.bdf\nset_global_assignment -name BDF_FILE clk_delay.bdf\nset_global_assignment -name BDF_FILE pin_control.bdf\nset_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top"
  },
  {
    "path": "cpu/control/test_decode.sv",
    "content": "//==============================================================\n// Test PLA decode and combinatorial static execute\n//==============================================================\n`timescale 100 ns/ 100 ns\n\nmodule test_decode;\n\nreg [7:0] ir_sig;\nreg [4:0] prefix_sig;\nwire [107:0] pla_sig;\n\n// ----------------- TEST -------------------\ninitial begin\n    integer opcode;\n\n    // Test every opcode in the first table\n\n    //================================================\n    // Regular instructions with no prefix\n    //================================================\n    $display(\"START IXY0:XX\");\n    opcode = 0;\n    while(opcode<256) begin\n        #1 $display(\"OPCODE: 0x%2H\", opcode);\n           prefix_sig[4:0] = 5'b10100;\n           ir_sig[7:0] = opcode;\n        #1 // Reset the IR into NOP so we get the trigger signal again\n           prefix_sig[4:0] = 5'b01100;\n           ir_sig[7:0] = 0;\n           opcode++;\n    end\n    #1 $display(\"END\");\n\n    //================================================\n    // Regular instructions with IX/IY prefix\n    //================================================\n    $display(\"START IXY1:XX\");\n    opcode = 0;\n    while(opcode<256) begin\n        #1 $display(\"OPCODE: 0x%2H\", opcode);\n           prefix_sig[4:0] = 5'b01100;\n           ir_sig[7:0] = opcode;\n        #1 // Reset the IR into NOP so we get the trigger signal again\n           prefix_sig[4:0] = 5'b01100;\n           ir_sig[7:0] = 0;\n           opcode++;\n    end\n    #1 $display(\"END\");\n\n    //================================================\n    // CD instructions with no prefix\n    //================================================\n    $display(\"START IXY0:CB\");\n    opcode = 0;\n    while(opcode<256) begin\n        #1 $display(\"OPCODE: 0x%2H\", opcode);\n           prefix_sig[4:0] = 5'b10010;\n           ir_sig[7:0] = opcode;\n        #1 // Reset the IR into NOP so we get the trigger signal again\n           prefix_sig[4:0] = 5'b01100;\n           ir_sig[7:0] = 0;\n           opcode++;\n    end\n    #1 $display(\"END\");\n\n    //================================================\n    // CB instructions with IX/IY prefix\n    //================================================\n    $display(\"START IXY1:CB\");\n    opcode = 0;\n    while(opcode<256) begin\n        #1 $display(\"OPCODE: 0x%2H\", opcode);\n           prefix_sig[4:0] = 5'b01010;\n           ir_sig[7:0] = opcode;\n        #1 // Reset the IR into NOP so we get the trigger signal again\n           prefix_sig[4:0] = 5'b01100;\n           ir_sig[7:0] = 0;\n           opcode++;\n    end\n    #1 $display(\"END\");\n\n    //================================================\n    // ED instructions with no prefix\n    //================================================\n    $display(\"START IXY0:ED\");\n    opcode = 0;\n    while(opcode<256) begin\n        #1 $display(\"OPCODE: 0x%2H\", opcode);\n           prefix_sig[4:0] = 5'b10001;\n           ir_sig[7:0] = opcode;\n        #1 // Reset the IR into NOP so we get the trigger signal again\n           prefix_sig[4:0] = 5'b01100;\n           ir_sig[7:0] = 0;\n           opcode++;\n    end\n    #1 $display(\"END\");\n\n    //================================================\n    // ED instructions with IX/IY prefix\n    //================================================\n    $display(\"START IXY1:ED\");\n    opcode = 0;\n    while(opcode<256) begin\n        #1 $display(\"OPCODE: 0x%2H\", opcode);\n           prefix_sig[4:0] = 5'b01001;\n           ir_sig[7:0] = opcode;\n        #1 // Reset the IR into NOP so we get the trigger signal again\n           prefix_sig[4:0] = 5'b01001;\n           ir_sig[7:0] = 0;\n           opcode++;\n    end\n    #1 $display(\"END\");\n\nend\n\n//--------------------------------------------------------------\n// Instantiate decode blocks\n//--------------------------------------------------------------\n\npla_decode pla_decode_inst\n(\n    .prefix(prefix_sig) ,       // input [6:0] prefix_sig\n    .opcode(ir_sig) ,           // input [7:0] opcode\n    .pla(pla_sig)               // output [104:0] pla_sig\n);\n\nexecute execute_inst\n(\n    .pla(pla_sig) ,             // input [107:0] pla_sig\n    .M1(M1_sig) ,               // input  M1_sig\n    .M2(M2_sig) ,               // input  M2_sig\n    .M3(M3_sig) ,               // input  M3_sig\n    .M4(M4_sig) ,               // input  M4_sig\n    .M5(M5_sig) ,               // input  M5_sig\n    .T1(T1_sig) ,               // input  T1_sig\n    .T2(T2_sig) ,               // input  T2_sig\n    .T3(T3_sig) ,               // input  T3_sig\n    .T4(T4_sig) ,               // input  T4_sig\n    .T5(T5_sig) ,               // input  T5_sig\n    .T6(T6_sig) ,               // input  T6_sig\n    .nextM(nextM_sig) ,         // output  nextM_sig\n    .setM1(setM1_sig) ,         // output  setM1_sig\n    .setM1ss(setM1ss_sig) ,     // output  setM1ss_sig\n    .setM1cc(setM1cc_sig) ,     // output  setM1cc_sig\n    .setM1bz(setM1bz_sig) ,     // output  setM1bz_sig\n    .fFetch(fFetch_sig) ,       // output  fFetch_sig\n    .fMRead(fMRead_sig) ,       // output  fMRead_sig\n    .fMWrite(fMWrite_sig) ,     // output  fMWrite_sig\n    .fIORead(fIORead_sig) ,     // output  fIORead_sig\n    .fIOWrite(fIOWrite_sig) ,   // output  fIOWrite_sig\n    .FIntr(FIntr_sig) ,         // output  FIntr_sig\n    .ctl_bus_sw1(ctl_bus_sw1_sig) ,         // output  ctl_bus_sw1_sig\n    .ctl_bus_sw2(ctl_bus_sw2_sig) ,         // output  ctl_bus_sw2_sig\n    .ctl_bus_sw4(ctl_bus_sw4_sig) ,         // output  ctl_bus_sw4_sig\n    .ctl_al_we(ctl_al_we_sig) ,             // output  ctl_al_we_sig\n    .ctl_inc_dec(ctl_inc_dec_sig) ,         // output  ctl_inc_dec_sig\n    .ctl_inc_limit6(ctl_inc_limit6_sig) ,   // output  ctl_inc_limit6_sig\n    .ctl_inc_cy(ctl_inc_cy_sig) ,           // output  ctl_inc_cy_sig\n    .ctl_ab_mux_inc(ctl_ab_mux_inc_sig) ,   // output  ctl_ab_mux_inc_sig\n    .explode(explode_sig)                   // output  explode_sig\n);\n\nendmodule\n"
  },
  {
    "path": "cpu/control/test_interrupts.sv",
    "content": "//==============================================================\n// Test interrupts unit\n//==============================================================\n`timescale 100 ns/ 100 ns\n\nmodule test_interrupts;\n\n// ----------------- CLOCKS AND RESET -----------------\n// Define one full T-clock cycle delay\n`define T #2\nbit clk = 1;\ninitial repeat (20) #1 clk = ~clk;\n\nlogic nreset = 0;\n\n// ----------------- CONTROL ----------------\nlogic ctl_iff1_iff2_sig=0;\nlogic ctl_iffx_we_sig=0;\nlogic ctl_iffx_bit_sig=0;\nlogic nmi_sig=0;\nlogic setM1_sig=0;\nlogic intr_sig=0;\nlogic ctl_im_we_sig=0;\nlogic [1:0] db_sig=0;\nlogic clk_sig=0;\nlogic ctl_no_ints_sig=0;\n\n// ----------------- STATES ----------------\nwire iff1_sig;\nassign iff1_sig = interrupts_inst.iff1;\nwire iff2_sig;\nwire im1_sig;\nwire im2_sig;\nwire in_nmi_sig;\nwire in_intr_sig;\n\n// ----------------- TEST -------------------\ninitial begin\n    // Init / reset\n    `T  nreset = 1;\n        // Test interrupt modes\n        db_sig = 2'b10;             // IM1\n        ctl_im_we_sig = 1;\n    `T  assert(im1_sig==1 && im2_sig==0);\n        db_sig = 2'b11;             // IM2\n    `T  assert(im1_sig==0 && im2_sig==1);\n        db_sig = 2'b00;             // IM0\n    `T  assert(im1_sig==0 && im2_sig==0);\n\n        // Test IFF state flags\n        assert(iff1_sig==0 && iff2_sig==0);\n        ctl_iff1_iff2_sig = 1;\n        ctl_iffx_we_sig = 1;\n        ctl_iffx_bit_sig = 1;\n    `T  assert(iff1_sig==0 && iff2_sig==1);\n    `T  assert(iff1_sig==1 && iff2_sig==1);\n        ctl_iff1_iff2_sig = 0;\n        ctl_iffx_we_sig = 0;\n        ctl_iffx_bit_sig = 0;\n\n        // Simulate NMI triggering\n        nmi_sig = 1;\n    `T  setM1_sig = 1;\n    `T  assert(iff1_sig==0 && iff2_sig==1);\n\n    `T  $display(\"End of test\");\nend\n\n//--------------------------------------------------------------\n// Instantiate interrupts\n//--------------------------------------------------------------\n\ninterrupts interrupts_inst\n(\n    .ctl_iff1_iff2(ctl_iff1_iff2_sig) , // input  ctl_iff1_iff2_sig\n    .nmi(nmi_sig) ,                     // input  nmi_sig\n    .setM1(setM1_sig) ,                 // input  setM1_sig\n    .intr(intr_sig) ,                   // input  intr_sig\n    .ctl_iffx_we(ctl_iffx_we_sig) ,     // input  ctl_iffx_we_sig\n    .ctl_iffx_bit(ctl_iffx_bit_sig) ,   // input  ctl_iffx_bit_sig\n    .ctl_im_we(ctl_im_we_sig) ,         // input  ctl_im_we_sig\n    .db(db_sig) ,                       // input [1:0] db_sig\n    .clk(clk) ,                         // input  clk\n    .ctl_no_ints(ctl_no_ints_sig) ,     // input  ctl_no_ints_sig\n    .nreset(nreset) ,                   // input  nreset\n    .iff2(iff2_sig) ,                   // output  iff2_sig\n    .im1(im1_sig) ,                     // output  im1_sig\n    .im2(im2_sig) ,                     // output  im2_sig\n    .in_nmi(in_nmi_sig) ,               // output  in_nmi_sig\n    .in_intr(in_intr_sig)               // output  in_intr_sig\n);\n\nendmodule\n"
  },
  {
    "path": "cpu/control/test_pin_control.sv",
    "content": "//==============================================================\n// Test pin control unit\n//==============================================================\n`timescale 100 ns/ 100 ns\n\nmodule test_pin_control;\n\n// ----------------- CONTROL ----------------\nlogic fFetch_sig=0;\nlogic fMRead_sig=0;\nlogic fMWrite_sig=0;\nlogic fIORead_sig=0;\nlogic fIOWrite_sig=0;\nlogic T1_sig=0;\nlogic T2_sig=0;\nlogic T3_sig=0;\nlogic T4_sig=0;\n\n// ----------------- STATES ----------------\nwire bus_ab_pin_we_sig;\nwire bus_db_pin_oe_sig;\nwire bus_db_pin_re_sig;\n\n// ----------------- TEST -------------------\ninitial begin\n    // Initial condition\n    #1  assert(bus_ab_pin_we_sig==0 && bus_db_pin_oe_sig==0 && bus_db_pin_re_sig==0);\n\n        // Activate formula for each signal\n        fFetch_sig = 1;\n        T1_sig = 1;\n    #1  assert(bus_ab_pin_we_sig==1 && bus_db_pin_oe_sig==0 && bus_db_pin_re_sig==0);\n        T1_sig = 0;\n        T3_sig = 1;\n    #1  assert(bus_ab_pin_we_sig==1 && bus_db_pin_oe_sig==0 && bus_db_pin_re_sig==0);\n        fFetch_sig = 0;\n        T1_sig = 0;\n        T3_sig = 0;\n    #1  assert(bus_ab_pin_we_sig==0 && bus_db_pin_oe_sig==0 && bus_db_pin_re_sig==0);\n        // Read phase\n        fMRead_sig = 1;\n    #1  assert(bus_ab_pin_we_sig==0 && bus_db_pin_oe_sig==0 && bus_db_pin_re_sig==0);\n        T1_sig = 1;\n    #1  assert(bus_ab_pin_we_sig==1 && bus_db_pin_oe_sig==0 && bus_db_pin_re_sig==0);\n        // Write phase\n        fMRead_sig = 0;\n        fMWrite_sig = 1;\n        fIORead_sig = 0;\n        fIOWrite_sig = 0;\n    #1  assert(bus_ab_pin_we_sig==1 && bus_db_pin_oe_sig==0 && bus_db_pin_re_sig==0);\n        // IO Read phase\n        fMRead_sig = 0;\n        fMWrite_sig = 0;\n        fIORead_sig = 1;\n        fIOWrite_sig = 0;\n    #1  assert(bus_ab_pin_we_sig==1 && bus_db_pin_oe_sig==0 && bus_db_pin_re_sig==0);\n        // IO Write phase\n        fMRead_sig = 0;\n        fMWrite_sig = 0;\n        fIORead_sig = 0;\n        fIOWrite_sig = 1;\n    #1  assert(bus_ab_pin_we_sig==1 && bus_db_pin_oe_sig==0 && bus_db_pin_re_sig==0);\n        fIOWrite_sig = 0;\n    #1  assert(bus_ab_pin_we_sig==0 && bus_db_pin_oe_sig==0 && bus_db_pin_re_sig==0);\n\n        // Test bus pin control\n        T2_sig = 1;\n        fMWrite_sig = 1;\n    #1  assert(bus_ab_pin_we_sig==1 && bus_db_pin_oe_sig==1 && bus_db_pin_re_sig==0);\n        fMWrite_sig = 0;\n        fIORead_sig = 1;\n    #1  assert(bus_ab_pin_we_sig==1 && bus_db_pin_oe_sig==0 && bus_db_pin_re_sig==0);\n        T3_sig = 1;\n    #1  assert(bus_ab_pin_we_sig==1 && bus_db_pin_oe_sig==0 && bus_db_pin_re_sig==1);\n\n    #1  $display(\"End of test\");\nend\n\n//--------------------------------------------------------------\n// Instantiate pin control\n//--------------------------------------------------------------\n\npin_control pin_control_inst\n(\n    .fFetch(fFetch_sig) ,               // input  fFetch_sig\n    .fMRead(fMRead_sig) ,               // input  fMRead_sig\n    .fMWrite(fMWrite_sig) ,             // input  fMWrite_sig\n    .fIORead(fIORead_sig) ,             // input  fIORead_sig\n    .fIOWrite(fIOWrite_sig) ,           // input  fIOWrite_sig\n    .T1(T1_sig) ,                       // input  T1_sig\n    .T2(T2_sig) ,                       // input  T2_sig\n    .T3(T3_sig) ,                       // input  T3_sig\n    .T4(T4_sig) ,                       // input  T4_sig\n    .bus_ab_pin_we(bus_ab_pin_we_sig) , // output  bus_ab_pin_we_sig\n    .bus_db_pin_oe(bus_db_pin_oe_sig) , // output  bus_db_pin_oe_sig\n    .bus_db_pin_re(bus_db_pin_re_sig)   // output  bus_db_pin_re_sig\n);\n\nendmodule\n"
  },
  {
    "path": "cpu/control/test_reset.sv",
    "content": "//==============================================================\n// Test reset circuit\n//==============================================================\n`timescale 100 ns/ 100 ns\n\nmodule test_reset;\n\n// ----------------- CLOCKS AND RESET -----------------\n`define T #2\nbit clk = 1;\ninitial repeat (40) #1 clk = ~clk;\n\n// Specific to FPGA, some modules in the schematic need to be pre-initialized\nreg fpga_reset = 1;\nalways_latch\n    if (clk) fpga_reset <= 0;\n\n//----------------------------------------------------------\n// Input reset from the pin; state from the sequencer\n//----------------------------------------------------------\nlogic reset_in = 0;\nlogic M1 = 0;\nlogic T2 = 0;\n\nwire clrpc;            // Load 0 to PC\nwire nhold_clk_wait;   // Hold clrpc\nwire nreset;           // Internal inverted reset signal\n\nassign nhold_clk_wait = 1; // Will not test this case\n\n// ----------------- TEST -------------------\ninitial begin\n    // Test normal reset sequence - 3 clocks long\n    `T reset_in = 1;\n    `T `T `T reset_in = 0;\n    `T assert(nreset==0);\n    // Out of the reset for several more cycles\n    // Check that the clrpc is set for the next 2 1/2 cycles (see waveform)\n    `T assert(nreset==1 && clrpc==1);\n    `T assert(nreset==1 && clrpc==1);\n    `T assert(nreset==1 && clrpc==0);\n    `T assert(nreset==1 && clrpc==0);\n    `T assert(nreset==1 && clrpc==0);\n\n    // Test special reset sequence: a reset pin is briefly\n    // asserted at M1/T1 and CLRPC should hold until the next\n    // M1/T2\n    `T reset_in = 1; M1=1;\n    `T reset_in = 0; M1=1; T2=1;\n    `T               M1=1; T2=0;\n    `T `T\n    `T assert(nreset==1 && clrpc==1);\n    `T               M1=1; T2=1;\n    `T               M1=1; T2=0;\n    `T assert(nreset==1 && clrpc==0);\n\n    `T $display(\"End of test\");\nend\n\n//--------------------------------------------------------------\n// Instantiate DUT\n//--------------------------------------------------------------\n\nresets reset_block ( .* );\n\nendmodule\n\n"
  },
  {
    "path": "cpu/control/test_sequencer.sv",
    "content": "//==============================================================\n// Test sequencer\n//==============================================================\n`timescale 100 ns/ 100 ns\n\nmodule test_sequencer;\n\n// ----------------- CLOCKS AND RESET -----------------\n// Define one full T-clock cycle delay\n`define T #2\nbit clk = 1;\ninitial repeat (100) #1 clk = ~clk;\n\nlogic nreset = 0;\n\n// ----------------- CONTROL ----------------\nlogic nextM_sig;\nlogic setM1_sig;\nlogic hold_clk_iorq_sig=0;\nlogic hold_clk_wait_sig=0;\nlogic hold_clk_busrq_sig=0;\n\nwire T6_sig;\nwire M5_sig;\nassign nextM_sig = T6_sig;              // Restart when reaching T6\nassign setM1_sig = M5_sig & T6_sig;     // Restart when reaching M5/T6\n\n// ----------------- TEST -------------------\ninitial begin\n    // Init / reset\n    `T  nreset = 1;\n    repeat (100) @(posedge clk); nreset <= 1;\n\n    // This test does not use assert() -- we just check visually\n\n    `T  $display(\"End of test\");\nend\n\n//--------------------------------------------------------------\n// Instantiate sequencer\n//--------------------------------------------------------------\n\nsequencer sequencer_inst\n(\n    .clk(clk) ,                         // input  clk\n    .nextM(nextM_sig) ,                 // input  nextM_sig\n    .setM1(setM1_sig) ,                 // input  setM1_sig\n    .nreset(nreset) ,                   // input  nreset\n    .hold_clk_iorq(hold_clk_iorq_sig) , // input  hold_clk_iorq_sig\n    .hold_clk_wait(hold_clk_wait_sig) , // input  hold_clk_wait_sig\n    .hold_clk_busrq(hold_clk_busrq_sig),// input  hold_clk_busrq_sig\n    .M1(M1_sig) ,                       // output  M1_sig\n    .M2(M2_sig) ,                       // output  M2_sig\n    .M3(M3_sig) ,                       // output  M3_sig\n    .M4(M4_sig) ,                       // output  M4_sig\n    .M5(M5_sig) ,                       // output  M5_sig\n    .T1(T1_sig) ,                       // output  T1_sig\n    .T2(T2_sig) ,                       // output  T2_sig\n    .T3(T3_sig) ,                       // output  T3_sig\n    .T4(T4_sig) ,                       // output  T4_sig\n    .T5(T5_sig) ,                       // output  T5_sig\n    .T6(T6_sig) ,                       // output  T6_sig\n    .timings_en(timings_en_sig)         // output  timings_en_sig\n);\n\nendmodule\n"
  },
  {
    "path": "cpu/control/timing_macros.i",
    "content": "//=========================================================================================\n// This file contains substitute strings for macro expansions. Macros are defined in an\n// Excel timing spreadsheet 'Timings.xlsm' and exported to a .csv file which is then read\n// and processed by genmatrix.py script to generate exec_matrix.vh include file.\n//\n// Macro format:\n//\n// * Each key is prefixed by ':' and corresponds to a spreadsheet *column* name.\n// * A key may contain several different macros, one per line.\n// * A macro may span multiple lines; use the '\\' character to continue on the next line.\n// * Multi-line macros end when a line does not start with a space character.\n// //-style comments are wrapped within /* ... */ if they don't start a line.\n//=========================================================================================\n\n//-----------------------------------------------------------------------------------------\n// CPU machine state\n//-----------------------------------------------------------------------------------------\n:Function\n//Fetch is M1\nfMFetch\nfMRead          fMRead=1;\nfMWrite         fMWrite=1;\nfIORead         fIORead=1;\nfIOWrite        fIOWrite=1;\n\n//-----------------------------------------------------------------------------------------\n// Basic timing control\n//-----------------------------------------------------------------------------------------\n:valid\nY               validPLA=1;\n:nextM\nY               nextM=1;\nmr              nextM=1; ctl_mRead=1;\nmw              nextM=1; ctl_mWrite=1;\nior             nextM=1; ctl_iorw=1;\niow             nextM=1; ctl_iorw=1;\nCC              nextM=~flags_cond_true;\nINT             nextM=1; ctl_mRead=in_intr & im2;   // RST38 interrupt extension\n:setM1\nY               setM1=1;\nSS              setM1=~flags_cond_true;\nCC              setM1=~flags_cond_true;\nZF              setM1=flags_zf;                     // Used in DJNZ\nBR              setM1=nonRep | ~repeat_en;\nBRZ             setM1=nonRep | ~repeat_en | flags_zf;\nBZ              setM1=nonRep | flags_zf;\nINT             setM1=~(in_intr & im2);             // RST38 interrupt extension\n\n//-----------------------------------------------------------------------------------------\n// Register file, address (downstream) endpoint\n//-----------------------------------------------------------------------------------------\n:A:reg rd\n// General purpose registers\nA       ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; ctl_sw_4d=1;  // Read 8-bit general purpose A register, enable SW4 downstream\nr16     ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;        // Read 16-bit general purpose register, enable SW4 downstream\nBC      ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;  // Read 16-bit BC, enable SW4 downstream\nDE      ctl_reg_gp_sel=`GP_REG_DE; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;  // Read 16-bit DE, enable SW4 downstream\nHL      ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;  // Read 16-bit HL, enable SW4 downstream\nSP      ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;// Read 16-bit SP, enable SW4 downstream\n\n// System registers\nWZ      ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1;          // Select 16-bit WZ\nIR      ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b11;                       // Select 16-bit IR\nI*      ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4d=1;          // Select 8-bit I register\nPC      ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11;                       // Select 16-bit PC\n\n// Conditional assertions of WZ, HL instead of PC\nWZ?     ctl_reg_not_pc|=flags_cond_true; ctl_reg_sel_wz|=flags_cond_true; ctl_reg_sys_hilo|={flags_cond_true,flags_cond_true}; ctl_sw_4d|=flags_cond_true;\n// Alternate format:\n//    if (flags_cond_true) begin // If cc is true, use WZ instead of PC (for jumps)\n//        ctl_reg_not_pc=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1;\n//    end\n\n:A:reg wr\n// General purpose registers\nr16     ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; // Write 16-bit general purpose register, enable SW4 upstream\nBC      ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; // Write 16-bit BC, enable SW4 upstream\nDE      ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_DE; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; // Write 16-bit BC, enable SW4 upstream\nHL      ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; // Write 16-bit HL, enable SW4 upstream\nSP      ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; // Write 16-bit SP, enable SW4 upstream\n// System registers\nWZ      ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; // Write 16-bit WZ, enable SW4 upstream\nIR      ctl_reg_sys_we=1; ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b11; // Write 16-bit IR\n// PC will not be incremented if we are in HALT, INTR or NMI state\nPC      ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); // Write 16-bit PC and control incrementer\n>       ctl_sw_4u=1;\n\n//-----------------------------------------------------------------------------------------\n// Controls the address latch incrementer, the address latch and the address pin mux\n//-----------------------------------------------------------------------------------------\n:inc/dec\n+       ctl_inc_cy=~pc_inc_hold;                      // Increment\n-       ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1;       // Decrement\nop3     ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=op3;     // Decrement if op3 is set; increment otherwise\n\n:A:latch\nW       ctl_al_we=1;                            // Write a value from the register bus to the address latch\nR       ctl_bus_inc_oe=1;                       // Output enable incrementer to the register bus\nP       ctl_apin_mux=1;                         // Apin sourced from incrementer\nRL      ctl_bus_inc_oe=1; ctl_apin_mux2=1;      // Apin sourced from AL\n\n//-----------------------------------------------------------------------------------------\n// Register file, data (upstream) endpoint\n//-----------------------------------------------------------------------------------------\n:D:reg rd\n//----- General purpose registers -----\nA       ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;\nAF      ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;\nB       ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10;\nH       ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b10;\nL       ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b01;\nr8      ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};// Read 8-bit GP register selected by op[2:0]\nr8' \\   // r8 addressing does not allow reading F register (indices of A and F are also swapped) (ex. in OUT (c),r)\n        if (op4 & op5 & ~op3) begin ctl_bus_zero_oe=1; end  // Trying to read flags? Put 0 on the bus instead.\n        if (~(op4 & op5 & ~op3)) begin ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; end // Read 8-bit GP register\nrh      ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10;         // Read 8-bit GP register high byte\nrl      ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01;         // Read 8-bit GP register low byte\n//----- System registers -----\nWZ      ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1;\nZ       ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1; // Selecting strictly Z\nI/R     ctl_reg_sel_ir=1; ctl_reg_sys_hilo={~op3,op3}; ctl_sw_4u=1; // Read either I or R based on op3 (0 or 1)\nPCh     ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4u=1;\nPCl     ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1;\n\n:D:reg wr\n?       // Which register to be written is decided elsewhere\n//----- General purpose registers -----\nA       ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;\nF       ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;\nB       ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10;\nr8      ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; // Write 8-bit GP register\nr8'     ctl_reg_gp_we=1; ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0}; // Write 8-bit GP register selected by op[2:0]\nrh      ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; // Write 8-bit GP register high byte\nrl      ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; // Write 8-bit GP register low byte\n//----- System registers -----\nI/R     ctl_reg_sys_we=1; ctl_reg_sel_ir=1; ctl_reg_sys_hilo={~op3,op3}; ctl_sw_4d=1; // Write either I or R based on op3 (0 or 1)\nWZ      ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11;\nW       ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; // Selecting only W\nW?      ctl_reg_sys_we_hi=flags_cond_true; ctl_reg_sel_wz=flags_cond_true; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; // Conditionally selecting only W\nZ       ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; // Selecting only Z\n\n//-----------------------------------------------------------------------------------------\n// Controls the register file gate connecting it with the ALU and data bus\n//-----------------------------------------------------------------------------------------\n:Reg gate\n<       ctl_reg_in_hi=1; ctl_reg_in_lo=1;       // From the ALU side into the register file\n<l      ctl_reg_in_lo=1;                        // From the ALU side into the register file low byte only\n<h      ctl_reg_in_hi=1;                        // From the ALU side into the register file high byte only\n\n>       ctl_reg_out_hi=1; ctl_reg_out_lo=1;     // From the register file into the FLAGT and ALU\n\n// Enables a register gate (high/low) corresponding to the selected 8-bit register\n>r8     ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; // Enable register gate based on the rsel0\n>r8'    ctl_reg_out_hi=~rsel3; ctl_reg_out_lo=rsel3; ctl_sw_2u=~rsel3; ctl_sw_2d=rsel3; // Enable register gate based on the rsel3\n\n>l      ctl_reg_out_lo=1;                       // From the register file onto the db1 (sw2 + FLAGT + sw1)\n>h      ctl_reg_out_hi=1;                       // From the register file onto the db2 (sw2 + ALU)\n\n//-----------------------------------------------------------------------------------------\n// Switches on the data bus for each direction (upstream, downstream)\n//-----------------------------------------------------------------------------------------\n:SW2\nd       ctl_sw_2d=1;\nu       ctl_sw_2u=1;\n-       // Controlled by register gate\n\n:SW1\n<       ctl_sw_1d=1;\n>       ctl_sw_1u=1;\n\n//-----------------------------------------------------------------------------------------\n// Data bus latches and pads control\n//-----------------------------------------------------------------------------------------\n:DB pads\nR       ctl_bus_db_oe=1;                        // Read DB pads to internal data bus\nW       ctl_bus_db_we=1;                        // Write DB pads with internal data bus value\n00      ctl_bus_zero_oe=1;                      // Force 0x00 on the data bus\nFF      ctl_bus_ff_oe=1;                        // Force 0xFF on the data bus\n\n//-----------------------------------------------------------------------------------------\n// ALU\n//-----------------------------------------------------------------------------------------\n:ALU\n// Controls the master ALU output enable and the ALU input, only one can be active at a time\n// >bs if set, will override >s0 which is used by bit instructions to override default M1/T3 load\n<       ctl_alu_oe=1;                           // Enable ALU onto the data bus\n>s0     ctl_alu_shift_oe=~ctl_alu_bs_oe;        // Shifter unit without shift-enable\n>s1     ctl_alu_shift_oe=1; ctl_shift_en=1;     // Shifter unit AND shift enable!\n>bs     ctl_alu_bs_oe=1;                        // Bit-selector unit\n\n:ALU bus\n// Controls the writer to the internal ALU bus\nop1     ctl_alu_op1_oe=1;                       // OP1 latch\nop2     ctl_alu_op2_oe=1;                       // OP2 latch\nres     ctl_alu_res_oe=1;                       // Result latch\n\n:op2 latch\n// Controls a MUX to select the input to the OP2 latch\nbus     ctl_alu_op2_sel_bus=1;                  // Internal bus\nlq      ctl_alu_op2_sel_lq=1;                   // Cross-bus wire (see schematic)\n0       ctl_alu_op2_sel_zero=1;                 // Zero\n\n:op1 latch\n// Controls a MUX to select the input to the OP1 latch\nbus     ctl_alu_op1_sel_bus=1;                  // Internal bus\nlow     ctl_alu_op1_sel_low=1;                  // Write low nibble with a high nibble\n0       ctl_alu_op1_sel_zero=1;                 // Zero\n\n:operation\n// Defines the ALU core compute operation\n// The listing is also showing their alternate formats (using if/then)\n//-----------------------------------------------------------------------------------------\nCP      ctl_alu_sel_op2_neg=1; ctl_flags_cf_set|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;\n//    ctl_alu_sel_op2_neg=1;\n//    if (ctl_alu_op_low) begin\n//        ctl_flags_cf_set=1;\n//    end else begin\n//        ctl_alu_core_hf=1;\n//    end\n//-----------------------------------------------------------------------------------------\nSUB     ctl_alu_sel_op2_neg=1; ctl_flags_cf_set|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;\n//    ctl_alu_sel_op2_neg=1;\n//    if (ctl_alu_op_low) begin\n//        ctl_flags_cf_set=1;\n//    end else begin\n//        ctl_alu_core_hf=1;\n//    end\n//-----------------------------------------------------------------------------------------\nSBC     ctl_alu_sel_op2_neg=1; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;\n//    ctl_alu_sel_op2_neg=1;\n//    if (ctl_alu_op_low) begin\n//        ctl_flags_cf_cpl=1;\n//    end else begin\n//        ctl_alu_core_hf=1;\n//    end\n//-----------------------------------------------------------------------------------------\nSBCh    ctl_alu_sel_op2_neg=1; ctl_alu_core_hf|=~ctl_alu_op_low;\n//    ctl_alu_sel_op2_neg=1;\n//    if (~ctl_alu_op_low) begin\n//        ctl_alu_core_hf=1;\n//    end\n//-----------------------------------------------------------------------------------------\nADC     ctl_alu_core_hf|=~ctl_alu_op_low;\n//    if (~ctl_alu_op_low) begin\n//        ctl_alu_core_hf=1;\n//    end\n//-----------------------------------------------------------------------------------------\nADD     ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low;\n//    if (ctl_alu_op_low) begin\n//        ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;\n//    end else begin\n//        ctl_alu_core_hf=1;\n//    end\n//-----------------------------------------------------------------------------------------\nAND     ctl_alu_core_S=1; ctl_flags_cf_set=1;\nOR      ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;\nXOR     ctl_alu_core_R=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;\nNAND    ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1;\nNOR     ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; ctl_alu_sel_op2_neg=1;\n//-----------------------------------------------------------------------------------------\n\nPLA     ctl_state_alu=1;                        // Assert the ALU PLA modifier to determine operation\n\n:nibble\n// ALU compute phase: working on low nibble or high nibble\nL       ctl_alu_op_low=1;                       // Activate ALU operation on low nibble\nH       ctl_alu_sel_op2_high=1;                 // Activate ALU operation on high nibble\n\n//-----------------------------------------------------------------------------------------\n// FLAGT\n//-----------------------------------------------------------------------------------------\n:FLAGT\n<       ctl_flags_oe=1;                         // Enable FLAGT onto the data bus\n>       ctl_flags_bus=1;                        // Load FLAGT from the data bus\nalu     ctl_flags_alu=1;                        // Load FLAGT from the ALU\n\n// Write enables for various flag bits and segments\n:SZ\n*       ctl_flags_sz_we=1;\n:XY\n*       ctl_flags_xy_we=1;\n?\n:HF\n*       ctl_flags_hf_we=1;\nW2      ctl_flags_hf2_we=1;                     // Write HF2 flag (DAA only)\n:PF\n*       ctl_flags_pf_we=1;\nP       ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;\nV       ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V;\niff2    ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_IFF2;\nREP     ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_REP;\n?\n:NF\n*       ctl_flags_nf_we=1;                      // Previous NF, to be used when loading FLAGT\n0       ctl_flags_nf_we=1; ctl_flags_nf_clr=1;\n1       ctl_flags_nf_we=1; ctl_flags_nf_set=1;\nS       ctl_flags_nf_we=1;                      // Sign bit, to be used with FLAGT source set to \"alu\"\n?\n:CF\n*       ctl_flags_cf_we=1;\n0       ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; // Clear CF going into the ALU core\n1       ctl_flags_cf_set=1;                     // Set CF going into the ALU core\n^       ctl_flags_cf_we=1;  ctl_flags_cf_cpl=1; // CCF\n:CF2\nR       ctl_flags_use_cf2=1;\nW       ctl_flags_cf2_we=1;\nW.sh    ctl_flags_cf2_we=1; ctl_flags_cf2_sel_shift=1;\nW.daa   ctl_flags_cf2_we=1; ctl_flags_cf2_sel_daa=1;\n\n//------------------------------------------------------------------------------------------\n// Macros for some special cases; also simplifies control logic for a number of instructions\n//------------------------------------------------------------------------------------------\n:Special\nUSE_SP          ctl_reg_use_sp=1;                           // For 16-bit loads: use SP instead of AF\n\n// A few more specific states and instructions:\nEx_DE_HL        ctl_reg_ex_de_hl=1;                         // EX DE,HL\nEx_AF_AF'       ctl_reg_ex_af=1;                            // EX AF,AF'\nEXX             ctl_reg_exx=1;                              // EXX\nHALT            ctl_state_halt_set=1;                       // Enter HALT state\nDI_EI           ctl_iffx_bit=op3; ctl_iffx_we=1;            // DI/EI\nIM              ctl_im_we=1;                                // IM n ('n' is read by opcode[4:3])\n\nWZ=IX+d         ixy_d=1;                                    // Compute WZ=IX+d\nIX_IY           ctl_state_ixiy_we=1; ctl_state_iy_set=op5; setIXIY=1;   // IX/IY prefix\nCLR_IX_IY       ctl_state_ixiy_we=1; ctl_state_ixiy_clr=~setIXIY;       // Clear IX/IY flag if not explicitly set\n\nCB              ctl_state_tbl_we=1; ctl_state_tbl_cb_set=1; // CB-table prefix\nED              ctl_state_tbl_we=1; ctl_state_tbl_ed_set=1; // ED-table prefix\nCLR_CB_ED       ctl_state_tbl_we=1;                         // Clear CB/ED prefix if not explicitly set\n\n// If the NF is set, complement HF and CF on the way out to the bus\n// This is used to correctly set those flags after subtraction operations\n?NF_HF_CF       ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf;\n?NF_HF          ctl_flags_hf_cpl=flags_nf;\n?~CF_HF         ctl_flags_hf_cpl=~flags_cf;  // Used for CCF\n?SF_NEG         ctl_alu_sel_op2_neg=flags_sf;\nNEG_OP2         ctl_alu_sel_op2_neg=1;\n?NF_SUB         ctl_alu_sel_op2_neg=flags_nf; ctl_flags_cf_cpl=~flags_nf;\n\n// M1 opcode read cycle and the refresh register increment cycle\n// Write opcode into the instruction register through internal db0 bus:\nOpcodeToIR      ctl_ir_we=1;\n\n// At the common instruction load M1/T3, override opcode byte when servicing interrupts:\n// 1. We are in HALT mode: push NOP (0x00) instead\n// 2. We are in INTR mode (IM1 or IM2): push RST38 (0xFF) instead\n// 3. We are in NMI mode: push RST38 (0xFF) instead\nOverrideIR      ctl_bus_zero_oe=in_halt; ctl_bus_ff_oe=(in_intr & (im1 | im2)) | in_nmi;\n\n// RST instruction uses opcode[5:3] to specify a vector and this macro passes those 3 bits through\nMASK_543        ctl_sw_mask543_en=~((in_intr & im2) | in_nmi);\n// Based on the in_nmi state:\n// 1. Disable SW1 so the opcode will not get onto db1 bus\n// 2. Generate 0x66 on the db1 bus which will be used as the target vector address\n// 3. Clear IFF1 (done by the nmi logic on posedge of in_nmi)\nRST_NMI         ctl_sw_1d=~in_nmi; ctl_66_oe=in_nmi;\n// Based on the in_intr state:\n// 1. IM1 mode, force 0xFF on the db0 bus\n// 2. Clear IFF1 and IFF2 (done by the intr logic on posedge of in_intr)\nRST_INT         ctl_bus_ff_oe=in_intr & im1;\nRETN            ctl_iff1_iff2=1;                // RETN copies IFF2 into IFF1\nNO_INTS         ctl_no_ints=1;                  // Disable interrupt generation for this opcode (DI/EI/CB/ED/DD/FD)\n\nEvalCond        ctl_eval_cond=1;                // Evaluate flags condition based on the opcode[5:3]\nCondShort       ctl_cond_short=1;               // M1/T3 only: force a short flags condition (SS)\nLimit6          ctl_inc_limit6=1;               // Limit the incrementer to 6 bits\nDAA             ctl_daa_oe=1;                   // Write DAA correction factor to the bus\nZERO_16BIT      ctl_alu_zero_16bit=1;           // 16-bit arithmetic operation uses ZF calculated over 2 bytes\nNonRep          nonRep=1;                       // Non-repeating block instruction\nWriteBC=1       ctl_repeat_we=1;                // Update repeating flag latch with BC=1 status\nNOT_PC!         ctl_reg_not_pc=1;               // For M1/T1 load from a register other than PC\n"
  },
  {
    "path": "cpu/copyleft.txt",
    "content": "//----------------------------------------------------------------------------\n//  A-Z80 CPU Copyright (C) 2014,2017  Goran Devic, www.baltazarstudios.com\n//\n//  This program is free software; you can redistribute it and/or modify it\n//  under the terms of the GNU General Public License as published by the Free\n//  Software Foundation; either version 2 of the License, or (at your option)\n//  any later version.\n//\n//  This program is distributed in the hope that it will be useful, but WITHOUT\n//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n//  more details.\n//----------------------------------------------------------------------------\n"
  },
  {
    "path": "cpu/export.py",
    "content": "#!/usr/bin/env python3\n#\n# Run this script to export necessary CPU files away and into your project.\n#\n#-------------------------------------------------------------------------------\n#  Copyright (C) 2014,2018  Goran Devic, www.baltazarstudios.com\n#\n#  This program is free software; you can redistribute it and/or modify it\n#  under the terms of the GNU General Public License as published by the Free\n#  Software Foundation; either version 2 of the License, or (at your option)\n#  any later version.\n#\n#  This program is distributed in the hope that it will be useful, but WITHOUT\n#  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n#  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n#  more details.\n#-------------------------------------------------------------------------------\nimport sys\nimport os\nfrom shutil import copyfile\n\nif len(sys.argv) != 2:\n    print (\"\\nUsage: export.py <destination-folder>\\n\")\n    print (\"Exports all necessary A-Z80 Verilog files to a project folder of your choice.\")\n    exit(-1)\n\ndest = sys.argv[1]\ntotal = 0\n\nif not os.path.exists(dest):\n    print (\"ERROR: Destination folder does not exist!\")\n    exit(-1)\n\nif not os.path.isdir(dest):\n    print (\"ERROR: Destination is not a directory!\")\n    exit(-1)\n\nwith open('top-level-files.txt') as f:\n    files = f.read().splitlines()\n\nwith open('copyleft.txt') as f:\n    copyleft = f.read()\n\n# Read and copy each file from the list of input files\nfor infile in files:\n    if infile.startswith('+'):\n        infile = infile[2:]\n    if infile.startswith('Files='):\n        files = int(infile[6:])\n        if total != files:\n            print (\"ERROR: Incorrect number of files copied!\")\n            exit(-1)\n        else:\n            print (\"\\nDone copying {0} files.\\n\".format(files))\n    if not os.path.isfile(infile):\n        continue\n    name = os.path.basename(infile)\n    print ('Copying', infile)\n    with open(dest + '/' + name, 'wt') as f:\n        f.write(copyleft)\n        with open(infile) as g:\n            f.write(g.read())\n    total += 1\n\nprint (\"All necessary A-Z80 CPU files are copied to\", dest)\nprint (\"Add all Verilog files (*.v) to your project and ensure that Verilog include\")\nprint (\"files (*.vh) are on the include path.\\n\")\nprint (\"Use z80_top_direct_n.v as your top-level interface file.\\n\")\nprint (\"Note for the users of Lattice FPGA toolset: instead of data_pins.v, manually\")\nprint (\"copy and use data_pins_lattice.v file instead.\")\n"
  },
  {
    "path": "cpu/readme.txt",
    "content": "A-Z80 Logic Design\n==================\nEach functional block contains a Quartus project file:\n./<block>/test_<block>.qpf\n\nQuartus projects are only used as containers for files within individual\nmodules; complete and working top-level solutions that use A-Z80 are in the\n\"host\" folder.\n\nMajority of sub-modules are designed in the Quartus schematic editor and then\nexported to Verilog for simulation and top-level integration.\n\nSimulation\n==========\nBefore you can load and simulate any module through Modelsim, you need to set up\nthe environment by running 'modelsim_setup.py'. The script creates relative file\npath mapping to source files in all module project folders.\n\nEach functional block, including the top level, contains a Modelsim simulation\nprofile: ./<block>/simulation/modelsim/test_<block>.mpf\n\nAfter opening a Modelsim session, create a library and compile sources:\nModelSim> vlib work\nCompile->Compile All\nRun a simulation through one of the defined configurations.\n\nIf you get a message \"Unable to compile\", you likely forgot to run 'modelsim_setup.py'.\nExit ModelSim, revert changes to \".mpf\" file, delete \"work\" folder and run\n'modelsim_setup.py'.\n\nEach project contains a set of predefined waveform scripts which you can\nload before running a simulation:\n./<block>/simulation/modelsim/wave_<test>.do\n"
  },
  {
    "path": "cpu/registers/reg_control.bdf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  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281)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 264 272)(pt 248 272))\n\t)\n\t(port\n\t\t(pt 264 288)\n\t\t(output)\n\t\t(text \"reg_sel_sys_lo\" (rect 0 0 87 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"reg_sel_sys_lo\" (rect 156 283 243 297)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 264 288)(pt 248 288))\n\t)\n\t(port\n\t\t(pt 264 304)\n\t\t(output)\n\t\t(text \"reg_sel_sys_hi\" (rect 0 0 87 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"reg_sel_sys_hi\" (rect 156 299 243 313)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 264 304)(pt 248 304))\n\t)\n\t(port\n\t\t(pt 264 320)\n\t\t(output)\n\t\t(text \"reg_sw_4d_lo\" (rect 0 0 82 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"reg_sw_4d_lo\" (rect 161 315 243 329)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 264 320)(pt 248 320))\n\t)\n\t(port\n\t\t(pt 264 336)\n\t\t(output)\n\t\t(text \"reg_sw_4d_hi\" (rect 0 0 82 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"reg_sw_4d_hi\" (rect 161 331 243 345)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 264 336)(pt 248 336))\n\t)\n\t(port\n\t\t(pt 264 352)\n\t\t(output)\n\t\t(text \"reg_sel_ir\" (rect 0 0 56 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"reg_sel_ir\" (rect 187 347 243 361)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 264 352)(pt 248 352))\n\t)\n\t(port\n\t\t(pt 264 368)\n\t\t(output)\n\t\t(text \"reg_sel_pc\" (rect 0 0 63 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"reg_sel_pc\" (rect 180 363 243 377)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 264 368)(pt 248 368))\n\t)\n\t(port\n\t\t(pt 264 384)\n\t\t(output)\n\t\t(text \"reg_sel_wz\" (rect 0 0 68 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"reg_sel_wz\" (rect 175 379 243 393)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 264 384)(pt 248 384))\n\t)\n\t(drawing\n\t\t(rectangle (rect 16 16 248 400))\n\t)\n)\n"
  },
  {
    "path": "cpu/registers/reg_control.v",
    "content": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and other software and tools, and its AMPP partner logic \n// functions, and any output files from any of the foregoing \n// (including device programming or simulation files), and any \n// associated documentation or information are expressly subject \n// to the terms and conditions of the Altera Program License \n// Subscription Agreement, Altera MegaCore Function License \n// Agreement, or other applicable license agreement, including, \n// without limitation, that your use is for the sole purpose of \n// programming logic devices manufactured by Altera and sold by \n// Altera or its authorized distributors.  Please refer to the \n// applicable agreement for further details.\n\n// PROGRAM\t\t\"Quartus II 64-Bit\"\n// VERSION\t\t\"Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\"\n// CREATED\t\t\"Sat Dec 10 09:05:10 2016\"\n\nmodule reg_control(\n\tctl_reg_exx,\n\tctl_reg_ex_af,\n\tctl_reg_ex_de_hl,\n\tctl_reg_use_sp,\n\tnreset,\n\tctl_reg_sel_pc,\n\tctl_reg_sel_ir,\n\tctl_reg_sel_wz,\n\tctl_reg_gp_we,\n\tctl_reg_not_pc,\n\tuse_ixiy,\n\tuse_ix,\n\tctl_reg_sys_we_lo,\n\tctl_reg_sys_we_hi,\n\tctl_reg_sys_we,\n\tclk,\n\tctl_sw_4d,\n\tnhold_clk_wait,\n\tctl_reg_gp_hilo,\n\tctl_reg_gp_sel,\n\tctl_reg_sys_hilo,\n\treg_sel_bc,\n\treg_sel_bc2,\n\treg_sel_ix,\n\treg_sel_iy,\n\treg_sel_de,\n\treg_sel_hl,\n\treg_sel_de2,\n\treg_sel_hl2,\n\treg_sel_af,\n\treg_sel_af2,\n\treg_sel_wz,\n\treg_sel_pc,\n\treg_sel_ir,\n\treg_sel_sp,\n\treg_sel_gp_hi,\n\treg_sel_gp_lo,\n\treg_sel_sys_lo,\n\treg_sel_sys_hi,\n\treg_gp_we,\n\treg_sys_we_lo,\n\treg_sys_we_hi,\n\treg_sw_4d_lo,\n\treg_sw_4d_hi\n);\n\n\ninput wire\tctl_reg_exx;\ninput wire\tctl_reg_ex_af;\ninput wire\tctl_reg_ex_de_hl;\ninput wire\tctl_reg_use_sp;\ninput wire\tnreset;\ninput wire\tctl_reg_sel_pc;\ninput wire\tctl_reg_sel_ir;\ninput wire\tctl_reg_sel_wz;\ninput wire\tctl_reg_gp_we;\ninput wire\tctl_reg_not_pc;\ninput wire\tuse_ixiy;\ninput wire\tuse_ix;\ninput wire\tctl_reg_sys_we_lo;\ninput wire\tctl_reg_sys_we_hi;\ninput wire\tctl_reg_sys_we;\ninput wire\tclk;\ninput wire\tctl_sw_4d;\ninput wire\tnhold_clk_wait;\ninput wire\t[1:0] ctl_reg_gp_hilo;\ninput wire\t[1:0] ctl_reg_gp_sel;\ninput wire\t[1:0] ctl_reg_sys_hilo;\noutput wire\treg_sel_bc;\noutput wire\treg_sel_bc2;\noutput wire\treg_sel_ix;\noutput wire\treg_sel_iy;\noutput wire\treg_sel_de;\noutput wire\treg_sel_hl;\noutput wire\treg_sel_de2;\noutput wire\treg_sel_hl2;\noutput wire\treg_sel_af;\noutput wire\treg_sel_af2;\noutput wire\treg_sel_wz;\noutput wire\treg_sel_pc;\noutput wire\treg_sel_ir;\noutput wire\treg_sel_sp;\noutput wire\treg_sel_gp_hi;\noutput wire\treg_sel_gp_lo;\noutput wire\treg_sel_sys_lo;\noutput wire\treg_sel_sys_hi;\noutput wire\treg_gp_we;\noutput wire\treg_sys_we_lo;\noutput wire\treg_sys_we_hi;\noutput wire\treg_sw_4d_lo;\noutput wire\treg_sw_4d_hi;\n\nreg\tbank_af;\nreg\tbank_exx;\nreg\tbank_hl_de1;\nreg\tbank_hl_de2;\nwire\treg_sys_we_lo_ALTERA_SYNTHESIZED;\nwire\tSYNTHESIZED_WIRE_52;\nwire\tSYNTHESIZED_WIRE_53;\nwire\tSYNTHESIZED_WIRE_2;\nwire\tSYNTHESIZED_WIRE_54;\nwire\tSYNTHESIZED_WIRE_55;\nwire\tSYNTHESIZED_WIRE_5;\nwire\tSYNTHESIZED_WIRE_56;\nwire\tSYNTHESIZED_WIRE_10;\nwire\tSYNTHESIZED_WIRE_57;\nwire\tSYNTHESIZED_WIRE_58;\nwire\tSYNTHESIZED_WIRE_59;\nwire\tSYNTHESIZED_WIRE_60;\nwire\tSYNTHESIZED_WIRE_21;\nwire\tSYNTHESIZED_WIRE_23;\nwire\tSYNTHESIZED_WIRE_24;\nwire\tSYNTHESIZED_WIRE_25;\nwire\tSYNTHESIZED_WIRE_30;\nwire\tSYNTHESIZED_WIRE_31;\nwire\tSYNTHESIZED_WIRE_32;\nwire\tSYNTHESIZED_WIRE_61;\nwire\tSYNTHESIZED_WIRE_34;\nwire\tSYNTHESIZED_WIRE_36;\nwire\tSYNTHESIZED_WIRE_37;\nwire\tSYNTHESIZED_WIRE_38;\nwire\tSYNTHESIZED_WIRE_39;\nwire\tSYNTHESIZED_WIRE_40;\nwire\tSYNTHESIZED_WIRE_41;\nwire\tSYNTHESIZED_WIRE_42;\nwire\tSYNTHESIZED_WIRE_43;\nwire\tSYNTHESIZED_WIRE_44;\nwire\tSYNTHESIZED_WIRE_45;\nwire\tSYNTHESIZED_WIRE_46;\nwire\tSYNTHESIZED_WIRE_47;\nwire\tSYNTHESIZED_WIRE_48;\nwire\tSYNTHESIZED_WIRE_49;\nwire\tSYNTHESIZED_WIRE_50;\n\nassign\treg_sel_wz = ctl_reg_sel_wz;\nassign\treg_sel_ir = ctl_reg_sel_ir;\nassign\treg_sel_gp_hi = ctl_reg_gp_hilo[1];\nassign\treg_sel_gp_lo = ctl_reg_gp_hilo[0];\nassign\treg_sel_sys_lo = ctl_reg_sys_hilo[0];\nassign\treg_sel_sys_hi = ctl_reg_sys_hilo[1];\nassign\treg_gp_we = ctl_reg_gp_we;\nassign\treg_sw_4d_lo = ctl_sw_4d;\n\n\n\nassign\treg_sel_bc = SYNTHESIZED_WIRE_52 & SYNTHESIZED_WIRE_53;\n\nassign\treg_sel_af = SYNTHESIZED_WIRE_2 & SYNTHESIZED_WIRE_54;\n\nassign\tSYNTHESIZED_WIRE_54 = SYNTHESIZED_WIRE_55 & SYNTHESIZED_WIRE_5;\n\nassign\treg_sel_sp = SYNTHESIZED_WIRE_55 & ctl_reg_use_sp;\n\nassign\tSYNTHESIZED_WIRE_5 =  ~ctl_reg_use_sp;\n\nassign\treg_sel_ix = SYNTHESIZED_WIRE_56 & use_ix;\n\nassign\tSYNTHESIZED_WIRE_50 = ctl_reg_ex_de_hl & SYNTHESIZED_WIRE_53;\n\nassign\treg_sel_iy = SYNTHESIZED_WIRE_56 & SYNTHESIZED_WIRE_10;\n\nassign\treg_sel_af2 = bank_af & SYNTHESIZED_WIRE_54;\n\nassign\tSYNTHESIZED_WIRE_2 =  ~bank_af;\n\nassign\tSYNTHESIZED_WIRE_47 = SYNTHESIZED_WIRE_57 & SYNTHESIZED_WIRE_58;\n\nassign\tSYNTHESIZED_WIRE_46 = bank_hl_de2 & SYNTHESIZED_WIRE_59;\n\nassign\tSYNTHESIZED_WIRE_39 = SYNTHESIZED_WIRE_60 & SYNTHESIZED_WIRE_58;\n\nassign\tSYNTHESIZED_WIRE_49 = bank_hl_de2 & SYNTHESIZED_WIRE_58;\n\nassign\tSYNTHESIZED_WIRE_48 = SYNTHESIZED_WIRE_57 & SYNTHESIZED_WIRE_59;\n\nassign\treg_sel_de = SYNTHESIZED_WIRE_53 & SYNTHESIZED_WIRE_21;\n\nassign\treg_sel_hl = SYNTHESIZED_WIRE_53 & SYNTHESIZED_WIRE_23;\n\nassign\treg_sel_de2 = bank_exx & SYNTHESIZED_WIRE_24;\n\nassign\treg_sel_hl2 = bank_exx & SYNTHESIZED_WIRE_25;\n\nassign\tSYNTHESIZED_WIRE_38 = bank_hl_de1 & SYNTHESIZED_WIRE_59;\n\nassign\tSYNTHESIZED_WIRE_53 =  ~bank_exx;\n\nassign\tSYNTHESIZED_WIRE_45 = bank_hl_de1 & SYNTHESIZED_WIRE_58;\n\nassign\tSYNTHESIZED_WIRE_44 = SYNTHESIZED_WIRE_60 & SYNTHESIZED_WIRE_59;\n\nassign\tSYNTHESIZED_WIRE_52 = SYNTHESIZED_WIRE_30 & SYNTHESIZED_WIRE_31;\n\nassign\tSYNTHESIZED_WIRE_60 =  ~bank_hl_de1;\n\nassign\treg_sys_we_hi = ctl_reg_sys_we | ctl_reg_sys_we_hi;\n\nassign\treg_sel_pc = ctl_reg_sel_pc & SYNTHESIZED_WIRE_32;\n\nassign\tSYNTHESIZED_WIRE_58 = SYNTHESIZED_WIRE_61 & SYNTHESIZED_WIRE_34;\n\nassign\tSYNTHESIZED_WIRE_32 =  ~ctl_reg_not_pc;\n\nassign\tSYNTHESIZED_WIRE_36 =  ~ctl_reg_gp_sel[1];\n\nassign\treg_sys_we_lo_ALTERA_SYNTHESIZED = ctl_reg_sys_we_lo | ctl_reg_sys_we;\n\nassign\tSYNTHESIZED_WIRE_56 = SYNTHESIZED_WIRE_61 & use_ixiy;\n\nassign\tSYNTHESIZED_WIRE_42 =  ~ctl_reg_gp_sel[0];\n\nassign\tSYNTHESIZED_WIRE_43 = ctl_reg_ex_de_hl & bank_exx;\n\nassign\tSYNTHESIZED_WIRE_34 =  ~use_ixiy;\n\nassign\tSYNTHESIZED_WIRE_59 = ctl_reg_gp_sel[0] & SYNTHESIZED_WIRE_36;\n\n\nalways@(posedge clk or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tbank_af <= 0;\n\tend\nelse\nif (nhold_clk_wait)\n\tbegin\n\tbank_af <= bank_af ^ ctl_reg_ex_af;\n\tend\nend\n\nassign\tSYNTHESIZED_WIRE_10 =  ~use_ix;\n\nassign\tSYNTHESIZED_WIRE_57 =  ~bank_hl_de2;\n\nassign\tSYNTHESIZED_WIRE_41 =  ~reg_sys_we_lo_ALTERA_SYNTHESIZED;\n\nassign\tSYNTHESIZED_WIRE_40 =  ~SYNTHESIZED_WIRE_37;\n\nassign\tSYNTHESIZED_WIRE_23 = SYNTHESIZED_WIRE_38 | SYNTHESIZED_WIRE_39;\n\nassign\treg_sw_4d_hi = ctl_sw_4d & SYNTHESIZED_WIRE_40;\n\nassign\tSYNTHESIZED_WIRE_37 = ctl_reg_sys_hilo[1] & SYNTHESIZED_WIRE_41 & ctl_reg_sel_ir;\n\nassign\tSYNTHESIZED_WIRE_61 = SYNTHESIZED_WIRE_42 & ctl_reg_gp_sel[1];\n\n\nalways@(posedge clk or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tbank_hl_de2 <= 0;\n\tend\nelse\nif (nhold_clk_wait)\n\tbegin\n\tbank_hl_de2 <= bank_hl_de2 ^ SYNTHESIZED_WIRE_43;\n\tend\nend\n\nassign\tSYNTHESIZED_WIRE_21 = SYNTHESIZED_WIRE_44 | SYNTHESIZED_WIRE_45;\n\nassign\tSYNTHESIZED_WIRE_25 = SYNTHESIZED_WIRE_46 | SYNTHESIZED_WIRE_47;\n\nassign\tSYNTHESIZED_WIRE_24 = SYNTHESIZED_WIRE_48 | SYNTHESIZED_WIRE_49;\n\n\nalways@(posedge clk or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tbank_hl_de1 <= 0;\n\tend\nelse\nif (nhold_clk_wait)\n\tbegin\n\tbank_hl_de1 <= bank_hl_de1 ^ SYNTHESIZED_WIRE_50;\n\tend\nend\n\n\nalways@(posedge clk or negedge nreset)\nbegin\nif (!nreset)\n\tbegin\n\tbank_exx <= 0;\n\tend\nelse\nif (nhold_clk_wait)\n\tbegin\n\tbank_exx <= bank_exx ^ ctl_reg_exx;\n\tend\nend\n\nassign\tSYNTHESIZED_WIRE_55 = ctl_reg_gp_sel[0] & ctl_reg_gp_sel[1];\n\nassign\tSYNTHESIZED_WIRE_30 =  ~ctl_reg_gp_sel[0];\n\nassign\tSYNTHESIZED_WIRE_31 =  ~ctl_reg_gp_sel[1];\n\nassign\treg_sel_bc2 = SYNTHESIZED_WIRE_52 & bank_exx;\n\nassign\treg_sys_we_lo = reg_sys_we_lo_ALTERA_SYNTHESIZED;\n\nendmodule\n"
  },
  {
    "path": "cpu/registers/reg_file.bdf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"graphic\" (version \"1.4\"))\n(pin\n\t(input)\n\t(rect 32 256 208 272)\n\t(text \"INPUT\" (rect 133 0 161 10)(font \"Arial\" (font_size 6)))\n\t(text \"reg_sel_sys_lo\" (rect 9 0 83 12)(font \"Arial\" ))\n\t(pt 176 8)\n\t(drawing\n\t\t(line (pt 92 12)(pt 117 12))\n\t\t(line (pt 92 4)(pt 117 4))\n\t\t(line (pt 121 8)(pt 176 8))\n\t\t(line (pt 92 12)(pt 92 4))\n\t\t(line (pt 117 4)(pt 121 8))\n\t\t(line (pt 117 12)(pt 121 8))\n\t)\n\t(text \"VCC\" (rect 136 7 156 17)(font \"Arial\" (font_size 6)))\n)\n(pin\n\t(input)\n\t(rect 2688 256 2864 272)\n\t(text \"INPUT\" (rect 15 6 43 16)(font \"Arial\" (font_size 6)))\n\t(text \"reg_sel_gp_lo\" (rect 100 4 167 16)(font \"Arial\" ))\n\t(pt 0 8)\n\t(drawing\n\t\t(line (pt 84 4)(pt 59 4))\n\t\t(line (pt 84 12)(pt 59 12))\n\t\t(line (pt 55 8)(pt 0 8))\n\t\t(line (pt 84 4)(pt 84 12))\n\t\t(line (pt 59 12)(pt 55 8))\n\t\t(line (pt 59 4)(pt 55 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  {
    "path": "cpu/registers/reg_file.bsf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"symbol\" (version \"1.2\"))\n(symbol\n\t(rect 16 16 240 528)\n\t(text \"reg_file\" (rect 5 0 47 14)(font \"Arial\" (font_size 8)))\n\t(text \"inst\" (rect 8 496 25 508)(font \"Arial\" ))\n\t(port\n\t\t(pt 0 32)\n\t\t(input)\n\t\t(text \"reg_sel_ir\" (rect 0 0 56 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"reg_sel_ir\" (rect 21 27 77 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 32)(pt 16 32))\n\t)\n\t(port\n\t\t(pt 0 48)\n\t\t(input)\n\t\t(text \"reg_sel_pc\" (rect 0 0 63 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"reg_sel_pc\" (rect 21 43 84 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 48)(pt 16 48))\n\t)\n\t(port\n\t\t(pt 0 64)\n\t\t(input)\n\t\t(text \"ctl_sw_4u\" (rect 0 0 60 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"ctl_sw_4u\" (rect 21 59 81 73)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 64)(pt 16 64))\n\t)\n\t(port\n\t\t(pt 0 80)\n\t\t(input)\n\t\t(text \"reg_sel_wz\" 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  {
    "path": "cpu/registers/reg_file.v",
    "content": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and other software and tools, and its AMPP partner logic \n// functions, and any output files from any of the foregoing \n// (including device programming or simulation files), and any \n// associated documentation or information are expressly subject \n// to the terms and conditions of the Altera Program License \n// Subscription Agreement, Altera MegaCore Function License \n// Agreement, or other applicable license agreement, including, \n// without limitation, that your use is for the sole purpose of \n// programming logic devices manufactured by Altera and sold by \n// Altera or its authorized distributors.  Please refer to the \n// applicable agreement for further details.\n\n// PROGRAM\t\t\"Quartus II 64-Bit\"\n// VERSION\t\t\"Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\"\n// CREATED\t\t\"Tue Mar 08 06:12:46 2016\"\n\nmodule reg_file(\n\treg_sel_sys_lo,\n\treg_sel_gp_lo,\n\treg_sel_sys_hi,\n\treg_sel_gp_hi,\n\treg_sel_ir,\n\treg_sel_pc,\n\tctl_sw_4u,\n\treg_sel_wz,\n\treg_sel_sp,\n\treg_sel_iy,\n\treg_sel_ix,\n\treg_sel_hl2,\n\treg_sel_hl,\n\treg_sel_de2,\n\treg_sel_de,\n\treg_sel_bc2,\n\treg_sel_bc,\n\treg_sel_af2,\n\treg_sel_af,\n\treg_gp_we,\n\treg_sys_we_lo,\n\treg_sys_we_hi,\n\tctl_reg_in_hi,\n\tctl_reg_in_lo,\n\tctl_reg_out_lo,\n\tctl_reg_out_hi,\n\tclk,\n\treg_sw_4d_lo,\n\treg_sw_4d_hi,\n\tdb_hi_as,\n\tdb_hi_ds,\n\tdb_lo_as,\n\tdb_lo_ds\n);\n\n\ninput wire\treg_sel_sys_lo;\ninput wire\treg_sel_gp_lo;\ninput wire\treg_sel_sys_hi;\ninput wire\treg_sel_gp_hi;\ninput wire\treg_sel_ir;\ninput wire\treg_sel_pc;\ninput wire\tctl_sw_4u;\ninput wire\treg_sel_wz;\ninput wire\treg_sel_sp;\ninput wire\treg_sel_iy;\ninput wire\treg_sel_ix;\ninput wire\treg_sel_hl2;\ninput wire\treg_sel_hl;\ninput wire\treg_sel_de2;\ninput wire\treg_sel_de;\ninput wire\treg_sel_bc2;\ninput wire\treg_sel_bc;\ninput wire\treg_sel_af2;\ninput wire\treg_sel_af;\ninput wire\treg_gp_we;\ninput wire\treg_sys_we_lo;\ninput wire\treg_sys_we_hi;\ninput wire\tctl_reg_in_hi;\ninput wire\tctl_reg_in_lo;\ninput wire\tctl_reg_out_lo;\ninput wire\tctl_reg_out_hi;\ninput wire\tclk;\ninput wire\treg_sw_4d_lo;\ninput wire\treg_sw_4d_hi;\ninout wire\t[7:0] db_hi_as;\ninout wire\t[7:0] db_hi_ds;\ninout wire\t[7:0] db_lo_as;\ninout wire\t[7:0] db_lo_ds;\n\nwire\t[7:0] gdfx_temp0;\nwire\t[7:0] gdfx_temp1;\nwire\tSYNTHESIZED_WIRE_84;\nwire\tSYNTHESIZED_WIRE_85;\nwire\tSYNTHESIZED_WIRE_86;\nwire\tSYNTHESIZED_WIRE_28;\nwire\tSYNTHESIZED_WIRE_29;\nwire\tSYNTHESIZED_WIRE_30;\nwire\tSYNTHESIZED_WIRE_31;\nwire\tSYNTHESIZED_WIRE_32;\nwire\tSYNTHESIZED_WIRE_33;\nwire\tSYNTHESIZED_WIRE_34;\nwire\tSYNTHESIZED_WIRE_35;\nwire\tSYNTHESIZED_WIRE_36;\nwire\tSYNTHESIZED_WIRE_37;\nwire\tSYNTHESIZED_WIRE_38;\nwire\tSYNTHESIZED_WIRE_39;\nwire\tSYNTHESIZED_WIRE_40;\nwire\tSYNTHESIZED_WIRE_41;\nwire\tSYNTHESIZED_WIRE_42;\nwire\tSYNTHESIZED_WIRE_43;\nwire\tSYNTHESIZED_WIRE_44;\nwire\tSYNTHESIZED_WIRE_45;\nwire\tSYNTHESIZED_WIRE_46;\nwire\tSYNTHESIZED_WIRE_47;\nwire\tSYNTHESIZED_WIRE_48;\nwire\tSYNTHESIZED_WIRE_49;\nwire\tSYNTHESIZED_WIRE_50;\nwire\tSYNTHESIZED_WIRE_51;\nwire\tSYNTHESIZED_WIRE_52;\nwire\tSYNTHESIZED_WIRE_53;\nwire\tSYNTHESIZED_WIRE_54;\nwire\tSYNTHESIZED_WIRE_55;\nwire\tSYNTHESIZED_WIRE_56;\nwire\tSYNTHESIZED_WIRE_57;\nwire\tSYNTHESIZED_WIRE_58;\nwire\tSYNTHESIZED_WIRE_59;\nwire\tSYNTHESIZED_WIRE_60;\nwire\tSYNTHESIZED_WIRE_61;\nwire\tSYNTHESIZED_WIRE_62;\nwire\tSYNTHESIZED_WIRE_63;\nwire\tSYNTHESIZED_WIRE_64;\nwire\tSYNTHESIZED_WIRE_65;\nwire\tSYNTHESIZED_WIRE_66;\nwire\tSYNTHESIZED_WIRE_67;\nwire\tSYNTHESIZED_WIRE_68;\nwire\tSYNTHESIZED_WIRE_69;\nwire\tSYNTHESIZED_WIRE_70;\nwire\tSYNTHESIZED_WIRE_71;\nwire\tSYNTHESIZED_WIRE_72;\nwire\tSYNTHESIZED_WIRE_73;\nwire\tSYNTHESIZED_WIRE_74;\nwire\tSYNTHESIZED_WIRE_75;\nwire\tSYNTHESIZED_WIRE_76;\nwire\tSYNTHESIZED_WIRE_77;\nwire\tSYNTHESIZED_WIRE_78;\nwire\tSYNTHESIZED_WIRE_79;\nwire\tSYNTHESIZED_WIRE_80;\nwire\tSYNTHESIZED_WIRE_81;\nwire\tSYNTHESIZED_WIRE_82;\nwire\tSYNTHESIZED_WIRE_83;\n\n\n\n\nassign\tSYNTHESIZED_WIRE_82 = SYNTHESIZED_WIRE_84 & reg_sel_sys_lo & reg_sel_wz;\n\nassign\tSYNTHESIZED_WIRE_80 = reg_sel_wz & reg_sel_sys_hi & SYNTHESIZED_WIRE_85;\n\nassign\tSYNTHESIZED_WIRE_78 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_sp;\n\nassign\tSYNTHESIZED_WIRE_76 = reg_sel_sp & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;\n\nassign\tSYNTHESIZED_WIRE_84 =  ~reg_sys_we_lo;\n\nassign\tSYNTHESIZED_WIRE_71 = reg_sel_gp_lo & reg_gp_we & reg_sel_iy;\n\nassign\tSYNTHESIZED_WIRE_85 =  ~reg_sys_we_hi;\n\nassign\tSYNTHESIZED_WIRE_74 = SYNTHESIZED_WIRE_84 & reg_sel_sys_lo & reg_sel_pc;\n\nassign\tSYNTHESIZED_WIRE_67 = reg_sel_gp_lo & reg_gp_we & reg_sel_ix;\n\nassign\tSYNTHESIZED_WIRE_55 = reg_sel_gp_lo & reg_gp_we & reg_sel_hl2;\n\nassign\tSYNTHESIZED_WIRE_72 = reg_sel_pc & reg_sel_sys_hi & SYNTHESIZED_WIRE_85;\n\nassign\tSYNTHESIZED_WIRE_59 = reg_sel_gp_lo & reg_gp_we & reg_sel_hl;\n\nassign\tSYNTHESIZED_WIRE_47 = reg_sel_gp_lo & reg_gp_we & reg_sel_de2;\n\nassign\tSYNTHESIZED_WIRE_51 = reg_sel_gp_lo & reg_gp_we & reg_sel_de;\n\nassign\tSYNTHESIZED_WIRE_81 = reg_sel_wz & reg_sys_we_hi & reg_sel_sys_hi;\n\nassign\tSYNTHESIZED_WIRE_86 =  ~reg_gp_we;\n\nassign\tSYNTHESIZED_WIRE_70 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_iy;\n\nassign\tSYNTHESIZED_WIRE_68 = reg_sel_iy & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;\n\nassign\tSYNTHESIZED_WIRE_39 = reg_sel_gp_lo & reg_gp_we & reg_sel_bc2;\n\nassign\tSYNTHESIZED_WIRE_43 = reg_sel_gp_lo & reg_gp_we & reg_sel_bc;\n\nassign\tSYNTHESIZED_WIRE_31 = reg_sel_gp_lo & reg_gp_we & reg_sel_af2;\n\nassign\tSYNTHESIZED_WIRE_77 = reg_sel_sp & reg_gp_we & reg_sel_gp_hi;\n\nassign\tSYNTHESIZED_WIRE_66 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_ix;\n\nassign\tSYNTHESIZED_WIRE_64 = reg_sel_ix & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;\n\nassign\tSYNTHESIZED_WIRE_35 = reg_sel_gp_lo & reg_gp_we & reg_sel_af;\n\nassign\tSYNTHESIZED_WIRE_69 = reg_sel_iy & reg_gp_we & reg_sel_gp_hi;\n\nassign\tSYNTHESIZED_WIRE_63 = reg_sel_sys_lo & reg_sys_we_lo & reg_sel_ir;\n\nassign\tSYNTHESIZED_WIRE_65 = reg_sel_ix & reg_gp_we & reg_sel_gp_hi;\n\nassign\tSYNTHESIZED_WIRE_53 = reg_sel_hl2 & reg_gp_we & reg_sel_gp_hi;\n\nassign\tSYNTHESIZED_WIRE_54 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_hl2;\n\nassign\tSYNTHESIZED_WIRE_52 = reg_sel_hl2 & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;\n\nassign\tSYNTHESIZED_WIRE_57 = reg_sel_hl & reg_gp_we & reg_sel_gp_hi;\n\nassign\tSYNTHESIZED_WIRE_45 = reg_sel_de2 & reg_gp_we & reg_sel_gp_hi;\n\nassign\tSYNTHESIZED_WIRE_49 = reg_sel_de & reg_gp_we & reg_sel_gp_hi;\n\nassign\tSYNTHESIZED_WIRE_37 = reg_sel_bc2 & reg_gp_we & reg_sel_gp_hi;\n\nassign\tSYNTHESIZED_WIRE_58 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_hl;\n\nassign\tSYNTHESIZED_WIRE_56 = reg_sel_hl & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;\n\nassign\tSYNTHESIZED_WIRE_75 = reg_sel_sys_lo & reg_sys_we_lo & reg_sel_pc;\n\nassign\tSYNTHESIZED_WIRE_41 = reg_sel_bc & reg_gp_we & reg_sel_gp_hi;\n\nassign\tSYNTHESIZED_WIRE_29 = reg_sel_af2 & reg_gp_we & reg_sel_gp_hi;\n\nassign\tSYNTHESIZED_WIRE_33 = reg_sel_af & reg_gp_we & reg_sel_gp_hi;\n\nassign\tSYNTHESIZED_WIRE_61 = reg_sel_ir & reg_sys_we_hi & reg_sel_sys_hi;\n\nassign\tSYNTHESIZED_WIRE_46 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_de2;\n\nassign\tSYNTHESIZED_WIRE_44 = reg_sel_de2 & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;\n\nassign\tSYNTHESIZED_WIRE_73 = reg_sel_pc & reg_sys_we_hi & reg_sel_sys_hi;\n\nassign\tSYNTHESIZED_WIRE_83 = reg_sel_sys_lo & reg_sys_we_lo & reg_sel_wz;\n\nassign\tSYNTHESIZED_WIRE_50 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_de;\n\nassign\tSYNTHESIZED_WIRE_48 = reg_sel_de & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;\n\nassign\tSYNTHESIZED_WIRE_38 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_bc2;\n\nassign\tSYNTHESIZED_WIRE_36 = reg_sel_bc2 & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;\n\nassign\tSYNTHESIZED_WIRE_42 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_bc;\n\nassign\tSYNTHESIZED_WIRE_40 = reg_sel_bc & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;\n\nassign\tSYNTHESIZED_WIRE_30 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_af2;\n\nassign\tSYNTHESIZED_WIRE_28 = reg_sel_af2 & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;\n\nassign\tSYNTHESIZED_WIRE_62 = SYNTHESIZED_WIRE_84 & reg_sel_sys_lo & reg_sel_ir;\n\nassign\tSYNTHESIZED_WIRE_34 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_af;\n\nassign\tSYNTHESIZED_WIRE_32 = reg_sel_af & reg_sel_gp_hi & SYNTHESIZED_WIRE_86;\n\nassign\tSYNTHESIZED_WIRE_60 = reg_sel_ir & reg_sel_sys_hi & SYNTHESIZED_WIRE_85;\n\nassign\tSYNTHESIZED_WIRE_79 = reg_sel_gp_lo & reg_gp_we & reg_sel_sp;\n\n\nreg_latch\tb2v_latch_af2_hi(\n\t.oe(SYNTHESIZED_WIRE_28),\n\t.we(SYNTHESIZED_WIRE_29),\n\t.clk(clk),\n\t.db(gdfx_temp1)\n\t);\n\n\nreg_latch\tb2v_latch_af2_lo(\n\t.oe(SYNTHESIZED_WIRE_30),\n\t.we(SYNTHESIZED_WIRE_31),\n\t.clk(clk),\n\t.db(gdfx_temp0)\n\t);\n\n\nreg_latch\tb2v_latch_af_hi(\n\t.oe(SYNTHESIZED_WIRE_32),\n\t.we(SYNTHESIZED_WIRE_33),\n\t.clk(clk),\n\t.db(gdfx_temp1)\n\t);\n\n\nreg_latch\tb2v_latch_af_lo(\n\t.oe(SYNTHESIZED_WIRE_34),\n\t.we(SYNTHESIZED_WIRE_35),\n\t.clk(clk),\n\t.db(gdfx_temp0)\n\t);\n\n\nreg_latch\tb2v_latch_bc2_hi(\n\t.oe(SYNTHESIZED_WIRE_36),\n\t.we(SYNTHESIZED_WIRE_37),\n\t.clk(clk),\n\t.db(gdfx_temp1)\n\t);\n\n\nreg_latch\tb2v_latch_bc2_lo(\n\t.oe(SYNTHESIZED_WIRE_38),\n\t.we(SYNTHESIZED_WIRE_39),\n\t.clk(clk),\n\t.db(gdfx_temp0)\n\t);\n\n\nreg_latch\tb2v_latch_bc_hi(\n\t.oe(SYNTHESIZED_WIRE_40),\n\t.we(SYNTHESIZED_WIRE_41),\n\t.clk(clk),\n\t.db(gdfx_temp1)\n\t);\n\n\nreg_latch\tb2v_latch_bc_lo(\n\t.oe(SYNTHESIZED_WIRE_42),\n\t.we(SYNTHESIZED_WIRE_43),\n\t.clk(clk),\n\t.db(gdfx_temp0)\n\t);\n\n\nreg_latch\tb2v_latch_de2_hi(\n\t.oe(SYNTHESIZED_WIRE_44),\n\t.we(SYNTHESIZED_WIRE_45),\n\t.clk(clk),\n\t.db(gdfx_temp1)\n\t);\n\n\nreg_latch\tb2v_latch_de2_lo(\n\t.oe(SYNTHESIZED_WIRE_46),\n\t.we(SYNTHESIZED_WIRE_47),\n\t.clk(clk),\n\t.db(gdfx_temp0)\n\t);\n\n\nreg_latch\tb2v_latch_de_hi(\n\t.oe(SYNTHESIZED_WIRE_48),\n\t.we(SYNTHESIZED_WIRE_49),\n\t.clk(clk),\n\t.db(gdfx_temp1)\n\t);\n\n\nreg_latch\tb2v_latch_de_lo(\n\t.oe(SYNTHESIZED_WIRE_50),\n\t.we(SYNTHESIZED_WIRE_51),\n\t.clk(clk),\n\t.db(gdfx_temp0)\n\t);\n\n\nreg_latch\tb2v_latch_hl2_hi(\n\t.oe(SYNTHESIZED_WIRE_52),\n\t.we(SYNTHESIZED_WIRE_53),\n\t.clk(clk),\n\t.db(gdfx_temp1)\n\t);\n\n\nreg_latch\tb2v_latch_hl2_lo(\n\t.oe(SYNTHESIZED_WIRE_54),\n\t.we(SYNTHESIZED_WIRE_55),\n\t.clk(clk),\n\t.db(gdfx_temp0)\n\t);\n\n\nreg_latch\tb2v_latch_hl_hi(\n\t.oe(SYNTHESIZED_WIRE_56),\n\t.we(SYNTHESIZED_WIRE_57),\n\t.clk(clk),\n\t.db(gdfx_temp1)\n\t);\n\n\nreg_latch\tb2v_latch_hl_lo(\n\t.oe(SYNTHESIZED_WIRE_58),\n\t.we(SYNTHESIZED_WIRE_59),\n\t.clk(clk),\n\t.db(gdfx_temp0)\n\t);\n\n\nreg_latch\tb2v_latch_ir_hi(\n\t.oe(SYNTHESIZED_WIRE_60),\n\t.we(SYNTHESIZED_WIRE_61),\n\t.clk(clk),\n\t.db(db_hi_as)\n\t);\n\n\nreg_latch\tb2v_latch_ir_lo(\n\t.oe(SYNTHESIZED_WIRE_62),\n\t.we(SYNTHESIZED_WIRE_63),\n\t.clk(clk),\n\t.db(db_lo_as)\n\t);\n\n\nreg_latch\tb2v_latch_ix_hi(\n\t.oe(SYNTHESIZED_WIRE_64),\n\t.we(SYNTHESIZED_WIRE_65),\n\t.clk(clk),\n\t.db(gdfx_temp1)\n\t);\n\n\nreg_latch\tb2v_latch_ix_lo(\n\t.oe(SYNTHESIZED_WIRE_66),\n\t.we(SYNTHESIZED_WIRE_67),\n\t.clk(clk),\n\t.db(gdfx_temp0)\n\t);\n\n\nreg_latch\tb2v_latch_iy_hi(\n\t.oe(SYNTHESIZED_WIRE_68),\n\t.we(SYNTHESIZED_WIRE_69),\n\t.clk(clk),\n\t.db(gdfx_temp1)\n\t);\n\n\nreg_latch\tb2v_latch_iy_lo(\n\t.oe(SYNTHESIZED_WIRE_70),\n\t.we(SYNTHESIZED_WIRE_71),\n\t.clk(clk),\n\t.db(gdfx_temp0)\n\t);\n\n\nreg_latch\tb2v_latch_pc_hi(\n\t.oe(SYNTHESIZED_WIRE_72),\n\t.we(SYNTHESIZED_WIRE_73),\n\t.clk(clk),\n\t.db(db_hi_as)\n\t);\n\n\nreg_latch\tb2v_latch_pc_lo(\n\t.oe(SYNTHESIZED_WIRE_74),\n\t.we(SYNTHESIZED_WIRE_75),\n\t.clk(clk),\n\t.db(db_lo_as)\n\t);\n\n\nreg_latch\tb2v_latch_sp_hi(\n\t.oe(SYNTHESIZED_WIRE_76),\n\t.we(SYNTHESIZED_WIRE_77),\n\t.clk(clk),\n\t.db(gdfx_temp1)\n\t);\n\n\nreg_latch\tb2v_latch_sp_lo(\n\t.oe(SYNTHESIZED_WIRE_78),\n\t.we(SYNTHESIZED_WIRE_79),\n\t.clk(clk),\n\t.db(gdfx_temp0)\n\t);\n\n\nreg_latch\tb2v_latch_wz_hi(\n\t.oe(SYNTHESIZED_WIRE_80),\n\t.we(SYNTHESIZED_WIRE_81),\n\t.clk(clk),\n\t.db(gdfx_temp1)\n\t);\n\n\nreg_latch\tb2v_latch_wz_lo(\n\t.oe(SYNTHESIZED_WIRE_82),\n\t.we(SYNTHESIZED_WIRE_83),\n\t.clk(clk),\n\t.db(gdfx_temp0)\n\t);\n\nassign\tgdfx_temp0[7] = ctl_sw_4u ? db_lo_as[7] : 1'bz;\nassign\tgdfx_temp0[6] = ctl_sw_4u ? db_lo_as[6] : 1'bz;\nassign\tgdfx_temp0[5] = ctl_sw_4u ? db_lo_as[5] : 1'bz;\nassign\tgdfx_temp0[4] = ctl_sw_4u ? db_lo_as[4] : 1'bz;\nassign\tgdfx_temp0[3] = ctl_sw_4u ? db_lo_as[3] : 1'bz;\nassign\tgdfx_temp0[2] = ctl_sw_4u ? db_lo_as[2] : 1'bz;\nassign\tgdfx_temp0[1] = ctl_sw_4u ? db_lo_as[1] : 1'bz;\nassign\tgdfx_temp0[0] = ctl_sw_4u ? db_lo_as[0] : 1'bz;\n\nassign\tdb_lo_as[7] = reg_sw_4d_lo ? gdfx_temp0[7] : 1'bz;\nassign\tdb_lo_as[6] = reg_sw_4d_lo ? gdfx_temp0[6] : 1'bz;\nassign\tdb_lo_as[5] = reg_sw_4d_lo ? gdfx_temp0[5] : 1'bz;\nassign\tdb_lo_as[4] = reg_sw_4d_lo ? gdfx_temp0[4] : 1'bz;\nassign\tdb_lo_as[3] = reg_sw_4d_lo ? gdfx_temp0[3] : 1'bz;\nassign\tdb_lo_as[2] = reg_sw_4d_lo ? gdfx_temp0[2] : 1'bz;\nassign\tdb_lo_as[1] = reg_sw_4d_lo ? gdfx_temp0[1] : 1'bz;\nassign\tdb_lo_as[0] = reg_sw_4d_lo ? gdfx_temp0[0] : 1'bz;\n\nassign\tgdfx_temp1[7] = ctl_sw_4u ? db_hi_as[7] : 1'bz;\nassign\tgdfx_temp1[6] = ctl_sw_4u ? db_hi_as[6] : 1'bz;\nassign\tgdfx_temp1[5] = ctl_sw_4u ? db_hi_as[5] : 1'bz;\nassign\tgdfx_temp1[4] = ctl_sw_4u ? db_hi_as[4] : 1'bz;\nassign\tgdfx_temp1[3] = ctl_sw_4u ? db_hi_as[3] : 1'bz;\nassign\tgdfx_temp1[2] = ctl_sw_4u ? db_hi_as[2] : 1'bz;\nassign\tgdfx_temp1[1] = ctl_sw_4u ? db_hi_as[1] : 1'bz;\nassign\tgdfx_temp1[0] = ctl_sw_4u ? db_hi_as[0] : 1'bz;\n\nassign\tdb_hi_as[7] = reg_sw_4d_hi ? gdfx_temp1[7] : 1'bz;\nassign\tdb_hi_as[6] = reg_sw_4d_hi ? gdfx_temp1[6] : 1'bz;\nassign\tdb_hi_as[5] = reg_sw_4d_hi ? gdfx_temp1[5] : 1'bz;\nassign\tdb_hi_as[4] = reg_sw_4d_hi ? gdfx_temp1[4] : 1'bz;\nassign\tdb_hi_as[3] = reg_sw_4d_hi ? gdfx_temp1[3] : 1'bz;\nassign\tdb_hi_as[2] = reg_sw_4d_hi ? gdfx_temp1[2] : 1'bz;\nassign\tdb_hi_as[1] = reg_sw_4d_hi ? gdfx_temp1[1] : 1'bz;\nassign\tdb_hi_as[0] = reg_sw_4d_hi ? gdfx_temp1[0] : 1'bz;\n\nassign\tdb_lo_ds[7] = ctl_reg_out_lo ? gdfx_temp0[7] : 1'bz;\nassign\tdb_lo_ds[6] = ctl_reg_out_lo ? gdfx_temp0[6] : 1'bz;\nassign\tdb_lo_ds[5] = ctl_reg_out_lo ? gdfx_temp0[5] : 1'bz;\nassign\tdb_lo_ds[4] = ctl_reg_out_lo ? gdfx_temp0[4] : 1'bz;\nassign\tdb_lo_ds[3] = ctl_reg_out_lo ? gdfx_temp0[3] : 1'bz;\nassign\tdb_lo_ds[2] = ctl_reg_out_lo ? gdfx_temp0[2] : 1'bz;\nassign\tdb_lo_ds[1] = ctl_reg_out_lo ? gdfx_temp0[1] : 1'bz;\nassign\tdb_lo_ds[0] = ctl_reg_out_lo ? gdfx_temp0[0] : 1'bz;\n\nassign\tgdfx_temp0[7] = ctl_reg_in_lo ? db_lo_ds[7] : 1'bz;\nassign\tgdfx_temp0[6] = ctl_reg_in_lo ? db_lo_ds[6] : 1'bz;\nassign\tgdfx_temp0[5] = ctl_reg_in_lo ? db_lo_ds[5] : 1'bz;\nassign\tgdfx_temp0[4] = ctl_reg_in_lo ? db_lo_ds[4] : 1'bz;\nassign\tgdfx_temp0[3] = ctl_reg_in_lo ? db_lo_ds[3] : 1'bz;\nassign\tgdfx_temp0[2] = ctl_reg_in_lo ? db_lo_ds[2] : 1'bz;\nassign\tgdfx_temp0[1] = ctl_reg_in_lo ? db_lo_ds[1] : 1'bz;\nassign\tgdfx_temp0[0] = ctl_reg_in_lo ? db_lo_ds[0] : 1'bz;\n\nassign\tdb_hi_ds[7] = ctl_reg_out_hi ? gdfx_temp1[7] : 1'bz;\nassign\tdb_hi_ds[6] = ctl_reg_out_hi ? gdfx_temp1[6] : 1'bz;\nassign\tdb_hi_ds[5] = ctl_reg_out_hi ? gdfx_temp1[5] : 1'bz;\nassign\tdb_hi_ds[4] = ctl_reg_out_hi ? gdfx_temp1[4] : 1'bz;\nassign\tdb_hi_ds[3] = ctl_reg_out_hi ? gdfx_temp1[3] : 1'bz;\nassign\tdb_hi_ds[2] = ctl_reg_out_hi ? gdfx_temp1[2] : 1'bz;\nassign\tdb_hi_ds[1] = ctl_reg_out_hi ? gdfx_temp1[1] : 1'bz;\nassign\tdb_hi_ds[0] = ctl_reg_out_hi ? gdfx_temp1[0] : 1'bz;\n\nassign\tgdfx_temp1[7] = ctl_reg_in_hi ? db_hi_ds[7] : 1'bz;\nassign\tgdfx_temp1[6] = ctl_reg_in_hi ? db_hi_ds[6] : 1'bz;\nassign\tgdfx_temp1[5] = ctl_reg_in_hi ? db_hi_ds[5] : 1'bz;\nassign\tgdfx_temp1[4] = ctl_reg_in_hi ? db_hi_ds[4] : 1'bz;\nassign\tgdfx_temp1[3] = ctl_reg_in_hi ? db_hi_ds[3] : 1'bz;\nassign\tgdfx_temp1[2] = ctl_reg_in_hi ? db_hi_ds[2] : 1'bz;\nassign\tgdfx_temp1[1] = ctl_reg_in_hi ? db_hi_ds[1] : 1'bz;\nassign\tgdfx_temp1[0] = ctl_reg_in_hi ? db_hi_ds[0] : 1'bz;\n\n\nendmodule\n"
  },
  {
    "path": "cpu/registers/reg_latch.bdf",
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  },
  {
    "path": "cpu/registers/reg_latch.bsf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"symbol\" (version \"1.2\"))\n(symbol\n\t(rect 64 64 184 160)\n\t(text \"reg_latch\" (rect 5 0 58 14)(font \"Arial\" (font_size 8)))\n\t(text \"inst\" (rect 8 80 25 92)(font \"Arial\" ))\n\t(port\n\t\t(pt 0 32)\n\t\t(input)\n\t\t(text \"oe\" (rect 0 0 14 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"oe\" (rect 21 27 35 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 32)(pt 16 32))\n\t)\n\t(port\n\t\t(pt 0 48)\n\t\t(input)\n\t\t(text \"we\" (rect 0 0 18 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"we\" (rect 21 43 39 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 48)(pt 16 48))\n\t)\n\t(port\n\t\t(pt 120 64)\n\t\t(input)\n\t\t(text \"clk\" (rect 0 0 15 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"clk\" (rect 73 56 88 70)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 104 64)(pt 120 64))\n\t)\n\t(port\n\t\t(pt 120 32)\n\t\t(bidir)\n\t\t(text \"db[7..0]\" (rect 0 0 42 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"db[7..0]\" (rect 57 27 99 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 120 32)(pt 104 32)(line_width 3))\n\t)\n\t(drawing\n\t\t(rectangle (rect 16 16 104 80))\n\t)\n\t(fill (color 85 255 127))\n)\n"
  },
  {
    "path": "cpu/registers/reg_latch.v",
    "content": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and other software and tools, and its AMPP partner logic \n// functions, and any output files from any of the foregoing \n// (including device programming or simulation files), and any \n// associated documentation or information are expressly subject \n// to the terms and conditions of the Altera Program License \n// Subscription Agreement, Altera MegaCore Function License \n// Agreement, or other applicable license agreement, including, \n// without limitation, that your use is for the sole purpose of \n// programming logic devices manufactured by Altera and sold by \n// Altera or its authorized distributors.  Please refer to the \n// applicable agreement for further details.\n\n// PROGRAM\t\t\"Quartus II 64-Bit\"\n// VERSION\t\t\"Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\"\n// CREATED\t\t\"Fri Nov 07 10:28:37 2014\"\n\nmodule reg_latch(\n\twe,\n\toe,\n\tclk,\n\tdb\n);\n\n\ninput wire\twe;\ninput wire\toe;\ninput wire\tclk;\ninout wire\t[7:0] db;\n\nreg\t[7:0] latch;\n\n\n\n\nassign\tdb[7] = oe ? latch[7] : 1'bz;\nassign\tdb[6] = oe ? latch[6] : 1'bz;\nassign\tdb[5] = oe ? latch[5] : 1'bz;\nassign\tdb[4] = oe ? latch[4] : 1'bz;\nassign\tdb[3] = oe ? latch[3] : 1'bz;\nassign\tdb[2] = oe ? latch[2] : 1'bz;\nassign\tdb[1] = oe ? latch[1] : 1'bz;\nassign\tdb[0] = oe ? latch[0] : 1'bz;\n\n\nalways@(posedge clk)\nbegin\nif (we)\n\tbegin\n\tlatch[7:0] <= db[7:0];\n\tend\nend\n\n\nendmodule\n"
  },
  {
    "path": "cpu/registers/simulation/modelsim/r",
    "content": "restart -f ; run -all\n"
  },
  {
    "path": "cpu/registers/simulation/modelsim/test_registers.mpf",
    "content": "; Copyright 1991-2009 Mentor Graphics Corporation\n;\n; All Rights Reserved.\n;\n; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF\n; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.\n;\n\n[Library]\nstd = $MODEL_TECH/../std\nieee = $MODEL_TECH/../ieee\nverilog = $MODEL_TECH/../verilog\nvital2000 = $MODEL_TECH/../vital2000\nstd_developerskit = $MODEL_TECH/../std_developerskit\nsynopsys = $MODEL_TECH/../synopsys\nmodelsim_lib = $MODEL_TECH/../modelsim_lib\nsv_std = $MODEL_TECH/../sv_std\n\n; Altera Primitive libraries\n;\n; VHDL Section\n;\naltera_mf = $MODEL_TECH/../altera/vhdl/altera_mf\naltera = $MODEL_TECH/../altera/vhdl/altera\naltera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim\nlpm = $MODEL_TECH/../altera/vhdl/220model\n220model = $MODEL_TECH/../altera/vhdl/220model\nmax = $MODEL_TECH/../altera/vhdl/max\nmaxii = $MODEL_TECH/../altera/vhdl/maxii\nmaxv = $MODEL_TECH/../altera/vhdl/maxv\nstratix = $MODEL_TECH/../altera/vhdl/stratix\nstratixii = $MODEL_TECH/../altera/vhdl/stratixii\nstratixiigx = $MODEL_TECH/../altera/vhdl/stratixiigx\nhardcopyii = $MODEL_TECH/../altera/vhdl/hardcopyii\nhardcopyiii = $MODEL_TECH/../altera/vhdl/hardcopyiii\nhardcopyiv = $MODEL_TECH/../altera/vhdl/hardcopyiv\ncyclone = $MODEL_TECH/../altera/vhdl/cyclone\ncycloneii = $MODEL_TECH/../altera/vhdl/cycloneii\ncycloneiii = $MODEL_TECH/../altera/vhdl/cycloneiii\ncycloneiiils = $MODEL_TECH/../altera/vhdl/cycloneiiils\nsgate = $MODEL_TECH/../altera/vhdl/sgate\nstratixgx = $MODEL_TECH/../altera/vhdl/stratixgx\naltgxb = $MODEL_TECH/../altera/vhdl/altgxb\nstratixgx_gxb = $MODEL_TECH/../altera/vhdl/stratixgx_gxb\nstratixiigx_hssi = $MODEL_TECH/../altera/vhdl/stratixiigx_hssi\narriagx_hssi = $MODEL_TECH/../altera/vhdl/arriagx_hssi\narriaii = $MODEL_TECH/../altera/vhdl/arriaii\narriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi\narriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip\narriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz\narriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi\narriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip\narriagx = $MODEL_TECH/../altera/vhdl/arriagx\naltgxb_lib = $MODEL_TECH/../altera/vhdl/altgxb\nstratixiv = $MODEL_TECH/../altera/vhdl/stratixiv\nstratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi\nstratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip\ncycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv\ncycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi\ncycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip\ncycloneive = $MODEL_TECH/../altera/vhdl/cycloneive\nhardcopyiv_hssi = $MODEL_TECH/../altera/vhdl/hardcopyiv_hssi\nhardcopyiv_pcie_hip = $MODEL_TECH/../altera/vhdl/hardcopyiv_pcie_hip\nstratixv = $MODEL_TECH/../altera/vhdl/stratixv\nstratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi\nstratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip\narriavgz = $MODEL_TECH/../altera/vhdl/arriavgz\narriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi\narriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip\narriav = $MODEL_TECH/../altera/vhdl/arriav\ncyclonev = $MODEL_TECH/../altera/vhdl/cyclonev\n;\n; Verilog Section\n;\naltera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf\naltera_ver = $MODEL_TECH/../altera/verilog/altera\naltera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim\nlpm_ver = $MODEL_TECH/../altera/verilog/220model\n220model_ver = $MODEL_TECH/../altera/verilog/220model\nmax_ver = $MODEL_TECH/../altera/verilog/max\nmaxii_ver = $MODEL_TECH/../altera/verilog/maxii\nmaxv_ver = $MODEL_TECH/../altera/verilog/maxv\nstratix_ver = $MODEL_TECH/../altera/verilog/stratix\nstratixii_ver = $MODEL_TECH/../altera/verilog/stratixii\nstratixiigx_ver = $MODEL_TECH/../altera/verilog/stratixiigx\narriagx_ver = $MODEL_TECH/../altera/verilog/arriagx\nhardcopyii_ver = $MODEL_TECH/../altera/verilog/hardcopyii\nhardcopyiii_ver = $MODEL_TECH/../altera/verilog/hardcopyiii\nhardcopyiv_ver = $MODEL_TECH/../altera/verilog/hardcopyiv\ncyclone_ver = $MODEL_TECH/../altera/verilog/cyclone\ncycloneii_ver = $MODEL_TECH/../altera/verilog/cycloneii\ncycloneiii_ver = $MODEL_TECH/../altera/verilog/cycloneiii\ncycloneiiils_ver = $MODEL_TECH/../altera/verilog/cycloneiiils\nsgate_ver = $MODEL_TECH/../altera/verilog/sgate\nstratixgx_ver = $MODEL_TECH/../altera/verilog/stratixgx\naltgxb_ver = $MODEL_TECH/../altera/verilog/altgxb\nstratixgx_gxb_ver = $MODEL_TECH/../altera/verilog/stratixgx_gxb\nstratixiigx_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiigx_hssi\narriagx_hssi_ver = $MODEL_TECH/../altera/verilog/arriagx_hssi\narriaii_ver = $MODEL_TECH/../altera/verilog/arriaii\narriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi\narriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip\narriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz\narriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi\narriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip\nstratixiii_ver = $MODEL_TECH/../altera/verilog/stratixiii\nstratixiii = $MODEL_TECH/../altera/vhdl/stratixiii\nstratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv\nstratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi\nstratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip\nstratixv_ver = $MODEL_TECH/../altera/verilog/stratixv\nstratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi\nstratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip\narriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz\narriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi\narriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip\narriav_ver = $MODEL_TECH/../altera/verilog/arriav\narriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi\narriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip\ncyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev\ncyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi\ncyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip\ncycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv\ncycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi\ncycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip\ncycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive\nhardcopyiv_hssi_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_hssi\nhardcopyiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_pcie_hip\n\nwork = work\n[vcom]\n; VHDL93 variable selects language version as the default.\n; Default is VHDL-2002.\n; Value of 0 or 1987 for VHDL-1987.\n; Value of 1 or 1993 for VHDL-1993.\n; Default or value of 2 or 2002 for VHDL-2002.\n; Default or value of 3 or 2008 for VHDL-2008.\nVHDL93 = 2002\n\n; Show source line containing error. Default is off.\n; Show_source = 1\n\n; Turn off unbound-component warnings. Default is on.\n; Show_Warning1 = 0\n\n; Turn off process-without-a-wait-statement warnings. Default is on.\n; Show_Warning2 = 0\n\n; Turn off null-range warnings. Default is on.\n; Show_Warning3 = 0\n\n; Turn off no-space-in-time-literal warnings. Default is on.\n; Show_Warning4 = 0\n\n; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.\n; Show_Warning5 = 0\n\n; Turn off optimization for IEEE std_logic_1164 package. Default is on.\n; Optimize_1164 = 0\n\n; Turn on resolving of ambiguous function overloading in favor of the\n; \"explicit\" function declaration (not the one automatically created by\n; the compiler for each type declaration). Default is off.\n; The .ini file has Explicit enabled so that std_logic_signed/unsigned\n; will match the behavior of synthesis tools.\nExplicit = 1\n\n; Turn off acceleration of the VITAL packages. Default is to accelerate.\n; NoVital = 1\n\n; Turn off VITAL compliance checking. Default is checking on.\n; NoVitalCheck = 1\n\n; Ignore VITAL compliance checking errors. Default is to not ignore.\n; IgnoreVitalErrors = 1\n\n; Turn off VITAL compliance checking warnings. Default is to show warnings.\n; Show_VitalChecksWarnings = 0\n\n; Keep silent about case statement static warnings.\n; Default is to give a warning.\n; NoCaseStaticError = 1\n\n; Keep silent about warnings caused by aggregates that are not locally static.\n; Default is to give a warning.\n; NoOthersStaticError = 1\n\n; Turn off inclusion of debugging info within design units.\n; Default is to include debugging info.\n; NoDebug = 1\n\n; Turn off \"Loading...\" messages. Default is messages on.\n; Quiet = 1\n\n; Turn on some limited synthesis rule compliance checking. Checks only:\n;    -- signals used (read) by a process must be in the sensitivity list\n; CheckSynthesis = 1\n\n; Activate optimizations on expressions that do not involve signals,\n; waits, or function/procedure/task invocations. Default is off.\n; ScalarOpts = 1\n\n; Require the user to specify a configuration for all bindings,\n; and do not generate a compile time default binding for the\n; component. This will result in an elaboration error of\n; 'component not bound' if the user fails to do so. Avoids the rare\n; issue of a false dependency upon the unused default binding.\n; RequireConfigForAllDefaultBinding = 1\n\n; Inhibit range checking on subscripts of arrays. Range checking on\n; scalars defined with subtypes is inhibited by default.\n; NoIndexCheck = 1\n\n; Inhibit range checks on all (implicit and explicit) assignments to\n; scalar objects defined with subtypes.\n; NoRangeCheck = 1\n\n[vlog]\n\n; Turn off inclusion of debugging info within design units.\n; Default is to include debugging info.\n; NoDebug = 1\n\n; Turn off \"loading...\" messages. Default is messages on.\n; Quiet = 1\n\n; Turn on Verilog hazard checking (order-dependent accessing of global vars).\n; Default is off.\n; Hazard = 1\n\n; Turn on converting regular Verilog identifiers to uppercase. Allows case\n; insensitivity for module names. Default is no conversion.\n; UpCase = 1\n\n; Turn on incremental compilation of modules. Default is off.\n; Incremental = 1\n\n; Turns on lint-style checking.\n; Show_Lint = 1\n\n[vsim]\n; Simulator resolution\n; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.\nResolution = ps\n\n; User time unit for run commands\n; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the\n; unit specified for Resolution. For example, if Resolution is 100ps,\n; then UserTimeUnit defaults to ps.\n; Should generally be set to default.\nUserTimeUnit = default\n\n; Default run length\nRunLength = 100 ns\n\n; Maximum iterations that can be run without advancing simulation time\nIterationLimit = 5000\n\n; Directive to license manager:\n; vhdl          Immediately reserve a VHDL license\n; vlog          Immediately reserve a Verilog license\n; plus          Immediately reserve a VHDL and Verilog license\n; nomgc         Do not look for Mentor Graphics Licenses\n; nomti         Do not look for Model Technology Licenses\n; noqueue       Do not wait in the license queue when a license isn't available\n; viewsim\tTry for viewer license but accept simulator license(s) instead\n;\t\tof queuing for viewer license\n; License = plus\n\n; Stop the simulator after a VHDL/Verilog assertion message\n; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal\nBreakOnAssertion = 4\n\n; Assertion Message Format\n; %S - Severity Level\n; %R - Report Message\n; %T - Time of assertion\n; %D - Delta\n; %I - Instance or Region pathname (if available)\n; %% - print '%' character\n; AssertionFormat = \"** %S: %R\\n   Time: %T  Iteration: %D%I\\n\"\n\n; Assertion File - alternate file for storing VHDL/Verilog assertion messages\n; AssertFile = assert.log\n\n; Default radix for all windows and commands...\n; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned\nDefaultRadix = symbolic\n\n; VSIM Startup command\n; Startup = do startup.do\n\n; File for saving command transcript\nTranscriptFile = transcript\n\n; File for saving command history\n; CommandHistory = cmdhist.log\n\n; Specify whether paths in simulator commands should be described\n; in VHDL or Verilog format.\n; For VHDL, PathSeparator = /\n; For Verilog, PathSeparator = .\n; Must not be the same character as DatasetSeparator.\nPathSeparator = /\n\n; Specify the dataset separator for fully rooted contexts.\n; The default is ':'. For example, sim:/top\n; Must not be the same character as PathSeparator.\nDatasetSeparator = :\n\n; Disable VHDL assertion messages\n; IgnoreNote = 1\n; IgnoreWarning = 1\n; IgnoreError = 1\n; IgnoreFailure = 1\n\n; Default force kind. May be freeze, drive, deposit, or default\n; or in other terms, fixed, wired, or charged.\n; A value of \"default\" will use the signal kind to determine the\n; force kind, drive for resolved signals, freeze for unresolved signals\n; DefaultForceKind = freeze\n\n; If zero, open files when elaborated; otherwise, open files on\n; first read or write.  Default is 0.\n; DelayFileOpen = 1\n\n; Control VHDL files opened for write.\n;   0 = Buffered, 1 = Unbuffered\nUnbufferedOutput = 0\n\n; Control the number of VHDL files open concurrently.\n; This number should always be less than the current ulimit\n; setting for max file descriptors.\n;   0 = unlimited\nConcurrentFileLimit = 40\n\n; Control the number of hierarchical regions displayed as\n; part of a signal name shown in the Wave window.\n; A value of zero tells VSIM to display the full name.\n; The default is 0.\n; WaveSignalNameWidth = 0\n\n; Turn off warnings from the std_logic_arith, std_logic_unsigned\n; and std_logic_signed packages.\n; StdArithNoWarnings = 1\n\n; Turn off warnings from the IEEE numeric_std and numeric_bit packages.\n; NumericStdNoWarnings = 1\n\n; Control the format of the (VHDL) FOR generate statement label\n; for each iteration.  Do not quote it.\n; The format string here must contain the conversion codes %s and %d,\n; in that order, and no other conversion codes.  The %s represents\n; the generate_label; the %d represents the generate parameter value\n; at a particular generate iteration (this is the position number if\n; the generate parameter is of an enumeration type).  Embedded whitespace\n; is allowed (but discouraged); leading and trailing whitespace is ignored.\n; Application of the format must result in a unique scope name over all\n; such names in the design so that name lookup can function properly.\n; GenerateFormat = %s__%d\n\n; Specify whether checkpoint files should be compressed.\n; The default is 1 (compressed).\n; CheckpointCompressMode = 0\n\n; List of dynamically loaded objects for Verilog PLI applications\n; Veriuser = veriuser.sl\n\n; Specify default options for the restart command. Options can be one\n; or more of: -force -nobreakpoint -nolist -nolog -nowave\n; DefaultRestartOptions = -force\n\n; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs\n; (> 500 megabyte memory footprint). Default is disabled.\n; Specify number of megabytes to lock.\n; LockedMemory = 1000\n\n; Turn on (1) or off (0) WLF file compression.\n; The default is 1 (compress WLF file).\n; WLFCompress = 0\n\n; Specify whether to save all design hierarchy (1) in the WLF file\n; or only regions containing logged signals (0).\n; The default is 0 (save only regions with logged signals).\n; WLFSaveAllRegions = 1\n\n; WLF file time limit.  Limit WLF file by time, as closely as possible,\n; to the specified amount of simulation time.  When the limit is exceeded\n; the earliest times get truncated from the file.\n; If both time and size limits are specified the most restrictive is used.\n; UserTimeUnits are used if time units are not specified.\n; The default is 0 (no limit).  Example: WLFTimeLimit = {100 ms}\n; WLFTimeLimit = 0\n\n; WLF file size limit.  Limit WLF file size, as closely as possible,\n; to the specified number of megabytes.  If both time and size limits\n; are specified then the most restrictive is used.\n; The default is 0 (no limit).\n; WLFSizeLimit = 1000\n\n; Specify whether or not a WLF file should be deleted when the\n; simulation ends.  A value of 1 will cause the WLF file to be deleted.\n; The default is 0 (do not delete WLF file when simulation ends).\n; WLFDeleteOnQuit = 1\n\n; Automatic SDF compilation\n; Disables automatic compilation of SDF files in flows that support it.\n; Default is on, uncomment to turn off.\n; NoAutoSDFCompile = 1\n\nDelayFileOpen = 1\n[lmc]\n\n[msg_system]\n; Change a message severity or suppress a message.\n; The format is: <msg directive> = <msg number>[,<msg number>...]\n; Examples:\n;   note = 3009\n;   warning = 3033\n;   error = 3010,3016\n;   fatal = 3016,3033\n;   suppress = 3009,3016,3043\n; The command verror <msg number> can be used to get the complete\n; description of a message.\n\n; Control transcripting of elaboration/runtime messages.\n; The default is to have messages appear in the transcript and\n; recorded in the wlf file (messages that are recorded in the\n; wlf file can be viewed in the MsgViewer).  The other settings\n; are to send messages only to the transcript or only to the\n; wlf file.  The valid values are\n;    both  {default}\n;    tran  {transcript only}\n;    wlf   {wlf file only}\n; msgmode = both\n[Project]\n; Warning -- Do not edit the project properties directly.\n;            Property names are dynamic in nature and property\n;            values have special syntax.  Changing property data directly\n;            can result in a corrupt MPF file.  All project properties\n;            can be modified through project window dialogs.\nProject_Version = 6\nProject_DefaultLib = work\nProject_SortMethod = unused\nProject_Files_Count = 6\nProject_File_0 = $ROOT/cpu/registers/reg_control.v\nProject_File_P_0 = compile_order 0 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_1 = $ROOT/cpu/registers/reg_file.v\nProject_File_P_1 = compile_order 1 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_2 = $ROOT/cpu/registers/reg_latch.v\nProject_File_P_2 = compile_order 2 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_3 = $ROOT/cpu/registers/test_latch.sv\nProject_File_P_3 = compile_order 4 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_4 = $ROOT/cpu/registers/test_regfile.sv\nProject_File_P_4 = compile_order 5 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_5 = $ROOT/cpu/registers/test_registers.sv\nProject_File_P_5 = compile_order 3 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_Sim_Count = 3\nProject_Sim_0 = Test registers\nProject_Sim_P_0 = timing default -sdfnoerror 0 -t default -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder {Top Level} +pulse_e {} additional_dus work.test_registers -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {}\nProject_Sim_1 = Test latch\nProject_Sim_P_1 = timing default -t default -sdfnoerror 0 -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder {Top Level} +pulse_e {} additional_dus work.test_latch -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {}\nProject_Sim_2 = Test regfile\nProject_Sim_P_2 = timing default -t default -sdfnoerror 0 -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder {Top Level} +pulse_e {} additional_dus work.test_regfile -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 0 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {}\nProject_Folder_Count = 0\nEcho_Compile_Output = 0\nSave_Compile_Report = 1\nProject_Opt_Count = 0\nForceSoftPaths = 1\nProjectStatusDelay = 5000\nVERILOG_DoubleClick = Edit\nVERILOG_CustomDoubleClick =\nSYSTEMVERILOG_DoubleClick = Edit\nSYSTEMVERILOG_CustomDoubleClick =\nVHDL_DoubleClick = Edit\nVHDL_CustomDoubleClick =\nPSL_DoubleClick = Edit\nPSL_CustomDoubleClick =\nTEXT_DoubleClick = Edit\nTEXT_CustomDoubleClick =\nSYSTEMC_DoubleClick = Edit\nSYSTEMC_CustomDoubleClick =\nTCL_DoubleClick = Edit\nTCL_CustomDoubleClick =\nMACRO_DoubleClick = Edit\nMACRO_CustomDoubleClick =\nVCD_DoubleClick = Edit\nVCD_CustomDoubleClick =\nSDF_DoubleClick = Edit\nSDF_CustomDoubleClick =\nXML_DoubleClick = Edit\nXML_CustomDoubleClick =\nLOGFILE_DoubleClick = Edit\nLOGFILE_CustomDoubleClick =\nUCDB_DoubleClick = Edit\nUCDB_CustomDoubleClick =\nUPF_DoubleClick = Edit\nUPF_CustomDoubleClick =\nPCF_DoubleClick = Edit\nPCF_CustomDoubleClick =\nPROJECT_DoubleClick = Edit\nPROJECT_CustomDoubleClick =\nVRM_DoubleClick = Edit\nVRM_CustomDoubleClick =\nDEBUGDATABASE_DoubleClick = Edit\nDEBUGDATABASE_CustomDoubleClick =\nDEBUGARCHIVE_DoubleClick = Edit\nDEBUGARCHIVE_CustomDoubleClick =\nProject_Major_Version = 10\nProject_Minor_Version = 1\n"
  },
  {
    "path": "cpu/registers/simulation/modelsim/wave_latch.do",
    "content": "onerror {resume}\nquietly WaveActivateNextPane {} 0\nadd wave -noupdate /test_latch/clk\nadd wave -noupdate -radix hexadecimal /test_latch/db\nadd wave -noupdate -radix hexadecimal /test_latch/db_sig\nadd wave -noupdate /test_latch/oe_sig\nadd wave -noupdate /test_latch/we_sig\nadd wave -noupdate -radix hexadecimal /test_latch/reg_latch_inst/latch\nTreeUpdate [SetDefaultTree]\nWaveRestoreCursors {{Cursor 1} {2000 ns} 0}\nquietly wave cursor active 1\nconfigure wave -namecolwidth 123\nconfigure wave -valuecolwidth 72\nconfigure wave -justifyvalue right\nconfigure wave -signalnamewidth 1\nconfigure wave -snapdistance 10\nconfigure wave -datasetprefix 0\nconfigure wave -rowmargin 4\nconfigure wave -childrowmargin 2\nconfigure wave -gridoffset 0\nconfigure wave -gridperiod 1\nconfigure wave -griddelta 40\nconfigure wave -timeline 1\nconfigure wave -timelineunits us\nupdate\nWaveRestoreZoom {0 ns} {12600 ns}\n"
  },
  {
    "path": "cpu/registers/simulation/modelsim/wave_regfile.do",
    "content": "onerror {resume}\nquietly WaveActivateNextPane {} 0\nadd wave -noupdate /test_regfile/clk\nadd wave -noupdate -radix hexadecimal /test_regfile/db_lo_ds\nadd wave -noupdate -radix hexadecimal /test_regfile/db_lo_ds_sig\nadd wave -noupdate -radix hexadecimal /test_regfile/db_hi_ds\nadd wave -noupdate -radix hexadecimal /test_regfile/db_hi_ds_sig\nadd wave -noupdate /test_regfile/reg_sel_af_sig\nadd wave -noupdate /test_regfile/reg_sel_af2_sig\nadd wave -noupdate /test_regfile/reg_sel_bc_sig\nadd wave -noupdate /test_regfile/reg_sel_bc2_sig\nadd wave -noupdate /test_regfile/reg_sel_de_sig\nadd wave -noupdate /test_regfile/reg_sel_de2_sig\nadd wave -noupdate /test_regfile/reg_sel_hl_sig\nadd wave -noupdate /test_regfile/reg_sel_hl2_sig\nadd wave -noupdate /test_regfile/reg_sel_ix_sig\nadd wave -noupdate /test_regfile/reg_sel_iy_sig\nadd wave -noupdate /test_regfile/reg_sel_wz_sig\nadd wave -noupdate /test_regfile/reg_sel_sp_sig\nadd wave -noupdate /test_regfile/reg_sel_gp_hi_sig\nadd wave -noupdate /test_regfile/reg_sel_gp_lo_sig\nadd wave -noupdate /test_regfile/reg_gp_oe_sig\nadd wave -noupdate /test_regfile/reg_sel_pc_sig\nadd wave -noupdate /test_regfile/reg_sel_ir_sig\nadd wave -noupdate /test_regfile/reg_sel_sys_hi_sig\nadd wave -noupdate /test_regfile/reg_sel_sys_lo_sig\nadd wave -noupdate /test_regfile/reg_sys_oe_sig\nadd wave -noupdate -divider Bus\nadd wave -noupdate -radix hexadecimal /test_regfile/reg_file_inst/db_hi_as\nadd wave -noupdate -radix hexadecimal /test_regfile/reg_file_inst/db_hi_ds\nadd wave -noupdate -radix hexadecimal /test_regfile/reg_file_inst/db_lo_as\nadd wave -noupdate -radix hexadecimal /test_regfile/reg_file_inst/db_lo_ds\nTreeUpdate [SetDefaultTree]\nWaveRestoreCursors {{Cursor 1} {0 ns} 0}\nquietly wave cursor active 0\nconfigure wave -namecolwidth 215\nconfigure wave -valuecolwidth 100\nconfigure wave -justifyvalue left\nconfigure wave -signalnamewidth 0\nconfigure wave -snapdistance 10\nconfigure wave -datasetprefix 0\nconfigure wave -rowmargin 4\nconfigure wave -childrowmargin 2\nconfigure wave -gridoffset 0\nconfigure wave -gridperiod 1\nconfigure wave -griddelta 40\nconfigure wave -timeline 1\nconfigure wave -timelineunits ps\nupdate\nWaveRestoreZoom {0 ns} {10400 ns}\n"
  },
  {
    "path": "cpu/registers/simulation/modelsim/wave_registers.do",
    "content": "onerror {resume}\nquietly WaveActivateNextPane {} 0\nadd wave -noupdate /test_registers/clk\nadd wave -noupdate -expand -group {Address Side} -itemcolor Black -radix hexadecimal -childformat {{{/test_registers/db_lo_as[7]} -radix hexadecimal} {{/test_registers/db_lo_as[6]} -radix hexadecimal} {{/test_registers/db_lo_as[5]} -radix hexadecimal} {{/test_registers/db_lo_as[4]} -radix hexadecimal} {{/test_registers/db_lo_as[3]} -radix hexadecimal} {{/test_registers/db_lo_as[2]} -radix hexadecimal} {{/test_registers/db_lo_as[1]} -radix hexadecimal} {{/test_registers/db_lo_as[0]} -radix hexadecimal}} -subitemconfig {{/test_registers/db_lo_as[7]} {-height 15 -itemcolor Black -radix hexadecimal} {/test_registers/db_lo_as[6]} {-height 15 -itemcolor Black -radix hexadecimal} {/test_registers/db_lo_as[5]} {-height 15 -itemcolor Black -radix hexadecimal} {/test_registers/db_lo_as[4]} {-height 15 -itemcolor Black -radix hexadecimal} {/test_registers/db_lo_as[3]} {-height 15 -itemcolor Black -radix hexadecimal} {/test_registers/db_lo_as[2]} {-height 15 -itemcolor Black -radix hexadecimal} {/test_registers/db_lo_as[1]} {-height 15 -itemcolor Black -radix hexadecimal} {/test_registers/db_lo_as[0]} {-height 15 -itemcolor Black -radix hexadecimal}} /test_registers/db_lo_as\nadd wave -noupdate -expand -group {Address Side} -itemcolor Black -radix hexadecimal /test_registers/db_lo_as_sig\nadd wave -noupdate -expand -group {Address Side} -itemcolor Black -radix hexadecimal /test_registers/db_hi_as\nadd wave -noupdate -expand -group {Address Side} -itemcolor Black -radix hexadecimal /test_registers/db_hi_as_sig\nadd wave -noupdate -expand -group {Data Side} -itemcolor Black -radix hexadecimal /test_registers/db_lo_ds\nadd wave -noupdate -expand -group {Data Side} -itemcolor Black -radix hexadecimal /test_registers/db_lo_ds_sig\nadd wave -noupdate -expand -group {Data Side} -itemcolor Black -radix hexadecimal /test_registers/db_hi_ds\nadd wave -noupdate -expand -group {Data Side} -itemcolor Black -radix hexadecimal /test_registers/db_hi_ds_sig\nadd wave -noupdate -divider Control\nadd wave -noupdate -itemcolor Violet /test_registers/ctl_sw_4u_sig\nadd wave -noupdate -itemcolor Violet /test_registers/ctl_sw_4d_sig\nadd wave -noupdate -itemcolor Violet /test_registers/reg_file_inst/reg_sw_4d_lo\nadd wave -noupdate -itemcolor Violet /test_registers/reg_file_inst/reg_sw_4d_hi\nadd wave -noupdate /test_registers/ctl_reg_in_hi_sig\nadd wave -noupdate /test_registers/ctl_reg_in_lo_sig\nadd wave -noupdate /test_registers/ctl_reg_out_hi_sig\nadd wave -noupdate /test_registers/ctl_reg_out_lo_sig\nadd wave -noupdate /test_registers/ctl_reg_exx_sig\nadd wave -noupdate /test_registers/ctl_reg_ex_af_sig\nadd wave -noupdate /test_registers/ctl_reg_ex_de_hl_sig\nadd wave -noupdate /test_registers/ctl_reg_use_sp_sig\nadd wave -noupdate /test_registers/ctl_reg_sel_wz_sig\nadd wave -noupdate /test_registers/ctl_reg_sel_pc_sig\nadd wave -noupdate /test_registers/ctl_reg_sel_ir_sig\nadd wave -noupdate -color Coral -itemcolor Gold /test_registers/reg_sel_bc_sig\nadd wave -noupdate -color Coral -itemcolor Gold /test_registers/reg_sel_bc2_sig\nadd wave -noupdate -color Coral -itemcolor Gold /test_registers/reg_sel_de_sig\nadd wave -noupdate -color Coral -itemcolor Gold /test_registers/reg_sel_de2_sig\nadd wave -noupdate -color Coral -itemcolor Gold /test_registers/reg_sel_hl_sig\nadd wave -noupdate -color Coral -itemcolor Gold /test_registers/reg_sel_hl2_sig\nadd wave -noupdate -color Coral -itemcolor Gold /test_registers/reg_sel_af_sig\nadd wave -noupdate -color Coral -itemcolor Gold /test_registers/reg_sel_af2_sig\nadd wave -noupdate -color Coral -itemcolor Gold /test_registers/reg_sel_ix_sig\nadd wave -noupdate -color Coral -itemcolor Gold /test_registers/reg_sel_iy_sig\nadd wave -noupdate -color Coral -itemcolor Gold /test_registers/reg_sel_wz_sig\nadd wave -noupdate -color Coral -itemcolor Gold /test_registers/reg_sel_pc_sig\nadd wave -noupdate -color Coral -itemcolor Gold /test_registers/reg_sel_ir_sig\nadd wave -noupdate -color Coral -itemcolor Gold /test_registers/reg_sel_gp_hi_sig\nadd wave -noupdate -color Coral -itemcolor Gold /test_registers/reg_sel_gp_lo_sig\nadd wave -noupdate -color Coral -itemcolor Gold /test_registers/reg_sel_sys_hi_sig\nadd wave -noupdate -color Coral -itemcolor Gold /test_registers/reg_sel_sys_lo_sig\nTreeUpdate [SetDefaultTree]\nWaveRestoreCursors {{Cursor 1} {1200 ns} 0}\nquietly wave cursor active 1\nconfigure wave -namecolwidth 260\nconfigure wave -valuecolwidth 39\nconfigure wave -justifyvalue left\nconfigure wave -signalnamewidth 0\nconfigure wave -snapdistance 10\nconfigure wave -datasetprefix 0\nconfigure wave -rowmargin 4\nconfigure wave -childrowmargin 2\nconfigure wave -gridoffset 0\nconfigure wave -gridperiod 1\nconfigure wave -griddelta 40\nconfigure wave -timeline 1\nconfigure wave -timelineunits ps\nupdate\nWaveRestoreZoom {0 ns} {7800 ns}\n"
  },
  {
    "path": "cpu/registers/test_latch.sv",
    "content": "//==============================================================\n// Test 8-bit latch block\n//==============================================================\n`timescale 100 ns/ 100 ns\n\nmodule test_latch;\n\n// ----------------- CLOCKS AND RESET -----------------\n// Define one full T-clock cycle delay\n`define T #2\nbit clk = 1;\ninitial repeat (30) #1 clk = ~clk;\n\n// ----------------------------------------------------\n// Bi-directional bus with 3-state\nreg  [7:0] db;              // Drive it using these wires\nwire [7:0] db_sig;          // Read it using these wires\n\nreg oe_sig;\nreg we_sig;\n\n// ----------------- TEST -------------------\n`define CHECK(arg) \\\n   assert(db_sig===arg);\n\ninitial begin\n    oe_sig = 0;\n    we_sig = 0;\n\n    // Test bidirectional data bus and leave it at Z\n    `T  db = 8'hAA;\n    `T  db = 'z;\n    `T `CHECK(8'hz);\n\n    // Write a byte into the latch\n    `T  db = 8'h55;\n    `T  we_sig = 1;\n    `T  we_sig = 0;\n    `T  db = 'z;\n\n    // Read latch\n    `T  db = 'z;\n    `T  oe_sig = 1;\n    `T `CHECK(8'h55);\n    `T  oe_sig = 0;\n\n    `T  $display(\"End of test\");\nend\n\n// Drive a 3-state bidirectional bus with this statement\nassign db_sig = db;\n\n//--------------------------------------------------------------\n// Instantiate register latch\n//--------------------------------------------------------------\n\nreg_latch reg_latch_inst\n(\n    .clk(clk),\n    .oe(oe_sig) ,               // input  oe_sig\n    .we(we_sig) ,               // input  we_sig\n    .db(db_sig[7:0])            // inout [7:0] db_sig\n);\n\nendmodule\n"
  },
  {
    "path": "cpu/registers/test_regfile.sv",
    "content": "//==============================================================\n// Test register file block (without reg. control unit)\n//==============================================================\n`timescale 100 ns/ 100 ns\n\nmodule test_regfile;\n\n// ----------------- CLOCKS AND RESET -----------------\n// Define one full T-clock cycle delay\n`define T #2\nbit clk = 1;\ninitial repeat (10) #1 clk = ~clk;\n\n// ----------------- BUSES -----------------\n// We have 4 Bi-directional buses that can also be 3-stated:\n// On the address-side, there are high and low 8-bit buses\nreg  [7:0] db_lo_as;        // Drive it using this bus\nwire [7:0] db_lo_as_sig;    // Read it using this bus\n\nreg  [7:0] db_hi_as;        // Drive it using this bus\nwire [7:0] db_hi_as_sig;    // Read it using this bus\n\n// ----------------- BUSES -----------------\n// On the data-side, there are high and low 8-bit buses\nreg  [7:0] db_lo_ds;        // Drive it using this bus\nwire [7:0] db_lo_ds_sig;    // Read it using this bus\n\nreg  [7:0] db_hi_ds;        // Drive it using this bus\nwire [7:0] db_hi_ds_sig;    // Read it using this bus\n\n// ----------------- CONTROL -----------------\nreg ctl_sw_4u_sig;          // Bus switch #4 upstream gate\nreg reg_sw_4d_lo_sig;       // Bus switch #4 downstream gate low byte lane\nreg reg_sw_4d_hi_sig;       // Bus switch #4 downstream gate high byte lane\n\n// ----------------- GP REGS -----------------\nreg reg_sel_af_sig;         // Select AF register\nreg reg_sel_af2_sig;        // ...\nreg reg_sel_bc_sig;\nreg reg_sel_bc2_sig;\nreg reg_sel_de_sig;\nreg reg_sel_de2_sig;\nreg reg_sel_hl_sig;\nreg reg_sel_hl2_sig;\nreg reg_sel_ix_sig;\nreg reg_sel_iy_sig;\nreg reg_sel_wz_sig;\nreg reg_sel_sp_sig;\n\nreg reg_sel_gp_hi_sig;      // Select high byte of a GP register\nreg reg_sel_gp_lo_sig;      // Select low byte of a GP register\nreg reg_gp_oe_sig;          // Write selected GP register to the data bus\n\n// ----------------- SYSTEM REGS -----------------\nreg reg_sel_pc_sig;         // Select PC register\nreg reg_sel_ir_sig;         // Select IR register\n\nreg reg_sel_sys_hi_sig;     // Select high byte of a system register\nreg reg_sel_sys_lo_sig;     // Select low byte of a system register\nreg reg_sys_oe_sig;         // Write selected system register to the data bus\n\n// ----------------- TEST -------------------\n`define CHECK(arg) \\\n   assert(db_sig===arg);\n\ninitial begin\n    reg_sw_4d_lo_sig = 0;\n    reg_sw_4d_hi_sig = 0;\n    ctl_sw_4u_sig = 0;\n\n    reg_sel_af_sig = 0;         // Select AF register\n    reg_sel_af2_sig = 0;        // ...\n    reg_sel_bc_sig = 0;\n    reg_sel_bc2_sig = 0;\n    reg_sel_de_sig = 0;\n    reg_sel_de2_sig = 0;\n    reg_sel_hl_sig = 0;\n    reg_sel_hl2_sig = 0;\n    reg_sel_ix_sig = 0;\n    reg_sel_iy_sig = 0;\n    reg_sel_wz_sig = 0;\n    reg_sel_sp_sig = 0;\n\n    reg_sel_gp_hi_sig = 0;      // Select high byte of a GP register\n    reg_sel_gp_lo_sig = 0;      // Select low byte of a GP register\n    reg_gp_oe_sig = 0;          // Write selected GP register to the data bus\n\n    reg_sel_pc_sig = 0;         // Select PC register\n    reg_sel_ir_sig = 0;         // Select IR register\n\n    reg_sel_sys_hi_sig = 0;     // Select high byte of a system register\n    reg_sel_sys_lo_sig = 0;     // Select low byte of a system register\n    reg_sys_oe_sig = 0;         // Write selected system register to the data bus\n\n    // Test bidirectional data buses and leave them at Z\n    `T  db_lo_as = 8'hAA;\n        db_hi_as = 8'h55;\n        db_lo_ds   = 8'hCA;\n        db_hi_ds   = 8'hFE;\n\n    `T  db_lo_as = 'z;\n        db_hi_as = 'z;\n        db_lo_ds   = 'z;\n        db_hi_ds   = 'z;\n\n    // Store a value in a GP register and read it back\n    `T  db_lo_ds = 8'h12;\n        db_hi_ds = 8'h34;\n        reg_sel_gp_hi_sig = 1;\n        reg_sel_gp_lo_sig = 1;\n        reg_sel_af_sig = 1;\n    `T  db_lo_ds = 'z;\n        db_hi_ds = 'z;\n        reg_sel_af_sig = 0;\n    `T\n    `T  reg_sel_gp_hi_sig = 1;\n        reg_sel_gp_lo_sig = 1;\n        reg_sel_af_sig = 1;\n        reg_gp_oe_sig = 1;\n    `T\n\n    `T  $display(\"End of test\");\nend\n\n// Drive 3-state bidirectional buses with these statements\nassign db_lo_as_sig = db_lo_as;\nassign db_hi_as_sig = db_hi_as;\n\nassign db_lo_ds_sig = db_lo_ds;\nassign db_hi_ds_sig = db_hi_ds;\n\n//--------------------------------------------------------------\n// Instantiate register file block\n//--------------------------------------------------------------\n\nreg_file reg_file_inst\n(\n    .reg_sel_sys_lo(reg_sel_sys_lo_sig) ,   // input  reg_sel_sys_lo_sig\n    .reg_sel_gp_lo(reg_sel_gp_lo_sig) ,     // input  reg_sel_gp_lo_sig\n    .reg_sel_sys_hi(reg_sel_sys_hi_sig) ,   // input  reg_sel_sys_hi_sig\n    .reg_sel_gp_hi(reg_sel_gp_hi_sig) ,     // input  reg_sel_gp_hi_sig\n    .reg_sel_ir(reg_sel_ir_sig) ,           // input  reg_sel_ir_sig\n    .reg_sel_pc(reg_sel_pc_sig) ,           // input  reg_sel_pc_sig\n    .reg_sw_4d_lo(reg_sw_4d_lo_sig) ,       // input  reg_sw_4d_lo_sig\n    .reg_sw_4d_hi(reg_sw_4d_hi_sig) ,       // input  reg_sw_4d_hi_sig\n    .ctl_sw_4u(ctl_sw_4u_sig) ,             // input  ctl_sw_4u_sig\n    .reg_sel_wz(reg_sel_wz_sig) ,           // input  reg_sel_wz_sig\n    .reg_sel_sp(reg_sel_sp_sig) ,           // input  reg_sel_sp_sig\n    .reg_sel_iy(reg_sel_iy_sig) ,           // input  reg_sel_iy_sig\n    .reg_sel_ix(reg_sel_ix_sig) ,           // input  reg_sel_ix_sig\n    .reg_sel_hl2(reg_sel_hl2_sig) ,         // input  reg_sel_hl2_sig\n    .reg_sel_hl(reg_sel_hl_sig) ,           // input  reg_sel_hl_sig\n    .reg_sel_de2(reg_sel_de2_sig) ,         // input  reg_sel_de2_sig\n    .reg_sel_de(reg_sel_de_sig) ,           // input  reg_sel_de_sig\n    .reg_sel_bc2(reg_sel_bc2_sig) ,         // input  reg_sel_bc2_sig\n    .reg_sel_bc(reg_sel_bc_sig) ,           // input  reg_sel_bc_sig\n    .reg_sel_af2(reg_sel_af2_sig) ,         // input  reg_sel_af2_sig\n    .reg_sel_af(reg_sel_af_sig) ,           // input  reg_sel_af_sig\n    .reg_gp_we(reg_gp_we_sig) ,             // input  reg_gp_we_sig\n    .reg_sys_we_lo(reg_sys_we_lo_sig) ,     // input  reg_sys_we_lo_sig\n    .reg_sys_we_hi(reg_sys_we_hi_sig) ,     // input  reg_sys_we_hi_sig\n    .ctl_reg_in_hi(ctl_reg_in_hi_sig) ,     // input  ctl_reg_in_hi_sig\n    .ctl_reg_in_lo(ctl_reg_in_lo_sig) ,     // input  ctl_reg_in_lo_sig\n    .ctl_reg_out_lo(ctl_reg_out_lo_sig) ,   // input  ctl_reg_out_lo_sig\n    .ctl_reg_out_hi(ctl_reg_out_hi_sig) ,   // input  ctl_reg_out_hi_sig\n    .clk(clk) ,                             // input  clk_sig\n    .db_lo_ds(db_lo_ds_sig) ,               // inout [7:0] db_lo_ds_sig\n    .db_hi_ds(db_hi_ds_sig) ,               // inout [7:0] db_hi_ds_sig\n    .db_lo_as(db_lo_as_sig) ,               // inout [7:0] db_lo_as_sig\n    .db_hi_as(db_hi_as_sig)                 // inout [7:0] db_hi_as_sig\n);\n\nendmodule\n"
  },
  {
    "path": "cpu/registers/test_registers.qpf",
    "content": "# -------------------------------------------------------------------------- #\n#\n# Copyright (C) 1991-2013 Altera Corporation\n# Your use of Altera Corporation's design tools, logic functions \n# and other software and tools, and its AMPP partner logic \n# functions, and any output files from any of the foregoing \n# (including device programming or simulation files), and any \n# associated documentation or information are expressly subject \n# to the terms and conditions of the Altera Program License \n# Subscription Agreement, Altera MegaCore Function License \n# Agreement, or other applicable license agreement, including, \n# without limitation, that your use is for the sole purpose of \n# programming logic devices manufactured by Altera and sold by \n# Altera or its authorized distributors.  Please refer to the \n# applicable agreement for further details.\n#\n# -------------------------------------------------------------------------- #\n#\n# Quartus II 64-Bit\n# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\n# Date created = 09:26:31  October 13, 2014\n#\n# -------------------------------------------------------------------------- #\n\nQUARTUS_VERSION = \"13.0\"\nDATE = \"09:26:31  October 13, 2014\"\n\n# Revisions\n\nPROJECT_REVISION = \"test_registers\"\n"
  },
  {
    "path": "cpu/registers/test_registers.qsf",
    "content": "# -------------------------------------------------------------------------- #\n#\n# Copyright (C) 1991-2013 Altera Corporation\n# Your use of Altera Corporation's design tools, logic functions \n# and other software and tools, and its AMPP partner logic \n# functions, and any output files from any of the foregoing \n# (including device programming or simulation files), and any \n# associated documentation or information are expressly subject \n# to the terms and conditions of the Altera Program License \n# Subscription Agreement, Altera MegaCore Function License \n# Agreement, or other applicable license agreement, including, \n# without limitation, that your use is for the sole purpose of \n# programming logic devices manufactured by Altera and sold by \n# Altera or its authorized distributors.  Please refer to the \n# applicable agreement for further details.\n#\n# -------------------------------------------------------------------------- #\n#\n# Quartus II 64-Bit\n# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\n# Date created = 09:26:31  October 13, 2014\n#\n# -------------------------------------------------------------------------- #\n#\n# Notes:\n#\n# 1) The default values for assignments are stored in the file:\n#\t\ttest_registers_assignment_defaults.qdf\n#    If this file doesn't exist, see file:\n#\t\tassignment_defaults.qdf\n#\n# 2) Altera recommends that you do not modify this file. This\n#    file is updated automatically by the Quartus II software\n#    and any changes you make may be lost or overwritten.\n#\n# -------------------------------------------------------------------------- #\n\n\nset_global_assignment -name FAMILY \"Cyclone II\"\nset_global_assignment -name DEVICE EP2C20F484C7\nset_global_assignment -name TOP_LEVEL_ENTITY reg_control\nset_global_assignment -name ORIGINAL_QUARTUS_VERSION \"13.0 SP1\"\nset_global_assignment -name PROJECT_CREATION_TIME_DATE \"09:26:31  OCTOBER 13, 2014\"\nset_global_assignment -name LAST_QUARTUS_VERSION \"13.0 SP1\"\nset_global_assignment -name BSF_FILE reg_latch.bsf\nset_global_assignment -name BDF_FILE reg_latch.bdf\nset_global_assignment -name BDF_FILE reg_file.bdf\nset_global_assignment -name BDF_FILE reg_control.bdf\nset_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files\nset_global_assignment -name MIN_CORE_JUNCTION_TEMP 0\nset_global_assignment -name MAX_CORE_JUNCTION_TEMP 85\nset_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1\nset_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top\nset_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top\nset_global_assignment -name PARTITION_COLOR 16764057 -section_id Top\nset_global_assignment -name USE_CONFIGURATION_DEVICE ON\nset_global_assignment -name RESERVE_ALL_UNUSED_PINS \"AS INPUT TRI-STATED WITH WEAK PULL-UP\"\nset_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON\nset_global_assignment -name SMART_RECOMPILE ON\nset_global_assignment -name POWER_PRESET_COOLING_SOLUTION \"23 MM HEAT SINK WITH 200 LFPM AIRFLOW\"\nset_global_assignment -name POWER_BOARD_THERMAL_MODEL \"NONE (CONSERVATIVE)\"\nset_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON\nset_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS OFF\nset_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005\nset_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF\nset_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON\nset_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON\nset_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top"
  },
  {
    "path": "cpu/registers/test_registers.sv",
    "content": "//==============================================================\n// Test register control and register file blocks\n//==============================================================\n`timescale 100 ns/ 100 ns\n\nmodule test_registers;\n\n// ----------------- CLOCKS AND RESET -----------------\n// Define one full T-clock cycle delay\n`define T #2\nbit clk = 1;\ninitial repeat (36) #1 clk = ~clk;\n\nlogic nreset = 0;\n\n// ----------------- BUSES -----------------\n// We have 4 Bi-directional buses that can also be 3-stated:\n\n// On the address-side, there are high and low 8-bit buses\nreg  [7:0] db_lo_as=8'hz;           // Drive it using this bus\nwire [7:0] db_lo_as_sig;            // Read it using this bus\n\nreg  [7:0] db_hi_as=8'hz;           // Drive it using this bus\nwire [7:0] db_hi_as_sig;            // Read it using this bus\n\n// On the data-side, there are high and low 8-bit buses\nreg  [7:0] db_lo_ds=8'hz;           // Drive it using this bus\nwire [7:0] db_lo_ds_sig;            // Read it using this bus\n\nreg  [7:0] db_hi_ds=8'hz;           // Drive it using this bus\nwire [7:0] db_hi_ds_sig;            // Read it using this bus\n\n// ----------------- BUS SWITCHES ------------\nlogic ctl_sw_4u_sig=0;              // Bus switch #4 upstream gate\nlogic ctl_sw_4d_sig=0;              // Bus switch #4 downstream gate\n\nlogic ctl_reg_in_hi_sig=0;          // Input to the register file high\nlogic ctl_reg_in_lo_sig=0;          // Input to the register file low\nlogic ctl_reg_out_hi_sig=0;         // Output from the register file high\nlogic ctl_reg_out_lo_sig=0;         // Output from the register file low\n\n// ----------------- CONTROL -----------------\nlogic [1:0] ctl_reg_gp_sel_sig=0;   // Selection of a general purpose register\nlogic [1:0] ctl_reg_gp_hilo_sig=0;  // Hi/Lo selector for GP registers\nlogic ctl_reg_gp_we_sig=0;          // Write to a general purpose register\nlogic [1:0] ctl_reg_sys_hilo_sig=0; // Hi/Lo selector for system registers\nlogic ctl_reg_sys_we_lo_sig=0;      // Write to low byte of a system register\nlogic ctl_reg_sys_we_hi_sig=0;      // Write to high byte of a system register\nlogic ctl_reg_sys_we_sig=0;         // Write to system register\nlogic use_ixiy_sig=0;               // Use IX or IY\nlogic use_ix_sig=0;                 // Use IX and not IY\nlogic nhold_clk_wait_sig=1;         // Enable transitions due to nWAIT\n\nlogic ctl_reg_exx_sig=0;            // Exchange register banks\nlogic ctl_reg_ex_af_sig=0;          // Exchange AF banks\nlogic ctl_reg_ex_de_hl_sig=0;       // Exchange HL/DE banks\nlogic ctl_reg_use_sp_sig=0;         // Use SP register\nlogic ctl_reg_sel_pc_sig=0;         // Select PC\nlogic ctl_reg_sel_ir_sig=0;         // Select IR\nlogic ctl_reg_sel_wz_sig=0;         // Select WZ\nlogic ctl_reg_not_pc_sig=0;         // Do not select PC\n\n// ----------------- TEST -------------------\n`define CHECK(arg) \\\n   assert({db_hi_ds_sig,db_lo_ds_sig}===arg);\n\ninitial begin\n    `T  nreset = 1;\n\n    //------------------------------------------------------------\n    // Identify each 16-bit system register and check access to it\n    `T  ctl_sw_4d_sig = 1;          // Use unified bus: downstream\n        ctl_sw_4u_sig = 0;\n        ctl_reg_in_hi_sig = 1;\n        ctl_reg_in_lo_sig = 1;\n        db_hi_ds = 8'h81;\n        db_lo_ds = 8'h41;\n        ctl_reg_sys_hilo_sig = 2'b11;\n        ctl_reg_sys_we_hi_sig = 1;  // 16-bit access\n        ctl_reg_sys_we_lo_sig = 1;  // 16-bit access\n        ctl_reg_sel_wz_sig = 1;     // WZ\n    `T  db_hi_ds = 8'h82;\n        db_lo_ds = 8'h42;\n        ctl_reg_sel_wz_sig = 0;     // WZ off\n        ctl_reg_sel_pc_sig = 1;     // PC\n    `T  db_hi_ds = 8'h83;\n        db_lo_ds = 8'h43;\n        ctl_reg_sel_pc_sig = 0;     // PC off\n        ctl_reg_sel_ir_sig = 1;     // IR\n    `T  db_hi_ds = 'z;\n        db_lo_ds = 'z;\n        ctl_reg_sel_ir_sig = 0;     // IR off\n    // Read back\n        ctl_sw_4d_sig = 0;\n        ctl_sw_4u_sig = 0;          // Upstream\n        ctl_reg_in_hi_sig = 0;\n        ctl_reg_in_lo_sig = 0;\n        ctl_reg_out_hi_sig = 1;\n        ctl_reg_out_lo_sig = 1;\n        ctl_reg_sys_we_hi_sig = 0;\n        ctl_reg_sys_we_lo_sig = 0;\n        ctl_reg_sel_wz_sig = 1;     // WZ\n    `T `CHECK(16'h8141);\n        ctl_reg_sel_wz_sig = 0;     // WZ off\n        ctl_sw_4u_sig = 1;          // Upstream\n        ctl_reg_sel_pc_sig = 1;     // PC\n    `T `CHECK(16'h8242);\n        ctl_reg_sel_pc_sig = 0;     // PC off\n        ctl_reg_sel_ir_sig = 1;     // IR\n    `T `CHECK(16'h8343);\n        ctl_reg_sel_ir_sig = 0;     // IR off\n        ctl_sw_4d_sig = 0;\n        ctl_sw_4u_sig = 0;\n        ctl_reg_sys_hilo_sig = 2'b00;\n\n    //------------------------------------------------------------\n    // Identify a 16-bit system register and check access to it\n    `T  ctl_reg_in_hi_sig = 1;\n        ctl_reg_in_lo_sig = 1;\n        ctl_reg_out_hi_sig = 0;\n        ctl_reg_out_lo_sig = 0;\n        ctl_reg_gp_we_sig = 1;      // Write to a GP register\n        ctl_reg_gp_hilo_sig = 2'b11;// 16-bit write\n        db_hi_ds = 8'hAA;\n        db_lo_ds = 8'h55;\n        ctl_reg_gp_sel_sig = 2'b00; // AF\n    `T  db_hi_ds = 8'hAB;\n        db_lo_ds = 8'h56;\n        ctl_reg_gp_sel_sig = 2'b01; // BC\n    `T  db_hi_ds = 8'hAC;\n        db_lo_ds = 8'h57;\n        ctl_reg_gp_sel_sig = 2'b10; // DE\n    `T  db_hi_ds = 8'hAD;\n        db_lo_ds = 8'h58;\n        ctl_reg_gp_sel_sig = 2'b11; // HL\n    `T  db_hi_ds = 'z;\n        db_lo_ds = 'z;\n    // Read back\n        ctl_reg_in_hi_sig = 0;\n        ctl_reg_in_lo_sig = 0;\n        ctl_reg_out_hi_sig = 1;\n        ctl_reg_out_lo_sig = 1;\n        ctl_reg_gp_we_sig = 0;\n        ctl_reg_gp_sel_sig = 2'b00; // Check AF\n    `T `CHECK(16'hAA55);\n        ctl_reg_gp_sel_sig = 2'b01; // Check BC\n    `T `CHECK(16'hAB56);\n        ctl_reg_gp_sel_sig = 2'b10; // Check DE\n    `T `CHECK(16'hAC57);\n        ctl_reg_gp_sel_sig = 2'b11; // Check HL\n    `T `CHECK(16'hAD58);\n\n    `T  $display(\"End of test\");\nend\n\n// Drive 3-state bidirectional buses with these statements\nassign db_lo_as_sig = db_lo_as;\nassign db_hi_as_sig = db_hi_as;\n\nassign db_lo_ds_sig = db_lo_ds;\nassign db_hi_ds_sig = db_hi_ds;\n\n// Instantiate register control block\nreg_control reg_control_inst\n(\n    .ctl_reg_gp_sel(ctl_reg_gp_sel_sig) ,   // input [1:0] ctl_reg_gp_sel_sig\n    .ctl_reg_sys_hilo(ctl_reg_sys_hilo_sig),// input [1:0] ctl_reg_sys_hilo_sig\n    .ctl_reg_exx(ctl_reg_exx_sig) ,         // input  ctl_reg_exx_sig\n    .ctl_reg_ex_af(ctl_reg_ex_af_sig) ,     // input  ctl_reg_ex_af_sig\n    .ctl_reg_ex_de_hl(ctl_reg_ex_de_hl_sig),// input  ctl_reg_ex_de_hl_sig\n    .ctl_reg_use_sp(ctl_reg_use_sp_sig) ,   // input  ctl_reg_use_sp_sig\n    .ctl_reg_gp_hilo(ctl_reg_gp_hilo_sig) , // input [1:0] ctl_reg_gp_hilo_sig\n    .nreset(nreset) ,                       // input  nreset\n    .ctl_reg_sel_pc(ctl_reg_sel_pc_sig) ,   // input  ctl_reg_sel_pc_sig\n    .ctl_reg_sel_ir(ctl_reg_sel_ir_sig) ,   // input  ctl_reg_sel_ir_sig\n    .ctl_reg_sel_wz(ctl_reg_sel_wz_sig) ,   // input  ctl_reg_sel_wz_sig\n    .ctl_reg_gp_we(ctl_reg_gp_we_sig) ,     // input  ctl_reg_gp_we_sig\n    .ctl_reg_not_pc(ctl_reg_not_pc_sig) ,   // input  ctl_reg_not_pc_sig\n    .use_ixiy(use_ixiy_sig) ,               // input  use_ixiy_sig\n    .use_ix(use_ix_sig) ,                   // input  use_ix_sig\n    .ctl_reg_sys_we_lo(ctl_reg_sys_we_lo_sig),// input  ctl_reg_sys_we_lo_sig\n    .ctl_reg_sys_we_hi(ctl_reg_sys_we_hi_sig),// input  ctl_reg_sys_we_hi_sig\n    .ctl_reg_sys_we(ctl_reg_sys_we_sig) ,   // input  ctl_reg_sys_we_sig\n    .clk(clk) ,                             // input  clk\n    .ctl_sw_4d (ctl_sw_4d_sig) ,            // input  ctl_sw_4d\n    .nhold_clk_wait(nhold_clk_wait_sig) ,   // input  nhold_clk_wait_sig\n    .reg_sel_bc(reg_sel_bc_sig) ,           // output  reg_sel_bc_sig\n    .reg_sel_bc2(reg_sel_bc2_sig) ,         // output  reg_sel_bc2_sig\n    .reg_sel_ix(reg_sel_ix_sig) ,           // output  reg_sel_ix_sig\n    .reg_sel_iy(reg_sel_iy_sig) ,           // output  reg_sel_iy_sig\n    .reg_sel_de(reg_sel_de_sig) ,           // output  reg_sel_de_sig\n    .reg_sel_hl(reg_sel_hl_sig) ,           // output  reg_sel_hl_sig\n    .reg_sel_de2(reg_sel_de2_sig) ,         // output  reg_sel_de2_sig\n    .reg_sel_hl2(reg_sel_hl2_sig) ,         // output  reg_sel_hl2_sig\n    .reg_sel_af(reg_sel_af_sig) ,           // output  reg_sel_af_sig\n    .reg_sel_af2(reg_sel_af2_sig) ,         // output  reg_sel_af2_sig\n    .reg_sel_wz(reg_sel_wz_sig) ,           // output  reg_sel_wz_sig\n    .reg_sel_pc(reg_sel_pc_sig) ,           // output  reg_sel_pc_sig\n    .reg_sel_ir(reg_sel_ir_sig) ,           // output  reg_sel_ir_sig\n    .reg_sel_sp(reg_sel_sp_sig) ,           // output  reg_sel_sp_sig\n    .reg_sel_gp_hi(reg_sel_gp_hi_sig) ,     // output  reg_sel_gp_hi_sig\n    .reg_sel_gp_lo(reg_sel_gp_lo_sig) ,     // output  reg_sel_gp_lo_sig\n    .reg_sel_sys_lo(reg_sel_sys_lo_sig) ,   // output  reg_sel_sys_lo_sig\n    .reg_sel_sys_hi(reg_sel_sys_hi_sig) ,   // output  reg_sel_sys_hi_sig\n    .reg_gp_we(reg_gp_we_sig) ,             // output  reg_gp_we_sig\n    .reg_sys_we_lo(reg_sys_we_lo_sig) ,     // output  reg_sys_we_lo_sig\n    .reg_sys_we_hi(reg_sys_we_hi_sig) ,     // output  reg_sys_we_hi_sig\n    .reg_sw_4d_lo (reg_sw_4d_lo_sig) ,      // output  reg_sw_4d_lo_sig\n    .reg_sw_4d_hi (reg_sw_4d_hi_sig)        // output  reg_sw_4d_hi_sig\n);\n\n// Instantiate register file block\nreg_file reg_file_inst\n(\n    .reg_sel_sys_lo(reg_sel_sys_lo_sig) ,   // input  reg_sel_sys_lo_sig\n    .reg_sel_gp_lo(reg_sel_gp_lo_sig) ,     // input  reg_sel_gp_lo_sig\n    .reg_sel_sys_hi(reg_sel_sys_hi_sig) ,   // input  reg_sel_sys_hi_sig\n    .reg_sel_gp_hi(reg_sel_gp_hi_sig) ,     // input  reg_sel_gp_hi_sig\n    .reg_sel_ir(reg_sel_ir_sig) ,           // input  reg_sel_ir_sig\n    .reg_sel_pc(reg_sel_pc_sig) ,           // input  reg_sel_pc_sig\n    .reg_sw_4d_lo(reg_sw_4d_lo_sig) ,       // input  reg_sw_4d_lo_sig\n    .reg_sw_4d_hi(reg_sw_4d_hi_sig) ,       // input  reg_sw_4d_hi_sig\n    .ctl_sw_4u(ctl_sw_4u_sig) ,             // input  ctl_sw_4u_sig\n    .reg_sel_wz(reg_sel_wz_sig) ,           // input  reg_sel_wz_sig\n    .reg_sel_sp(reg_sel_sp_sig) ,           // input  reg_sel_sp_sig\n    .reg_sel_iy(reg_sel_iy_sig) ,           // input  reg_sel_iy_sig\n    .reg_sel_ix(reg_sel_ix_sig) ,           // input  reg_sel_ix_sig\n    .reg_sel_hl2(reg_sel_hl2_sig) ,         // input  reg_sel_hl2_sig\n    .reg_sel_hl(reg_sel_hl_sig) ,           // input  reg_sel_hl_sig\n    .reg_sel_de2(reg_sel_de2_sig) ,         // input  reg_sel_de2_sig\n    .reg_sel_de(reg_sel_de_sig) ,           // input  reg_sel_de_sig\n    .reg_sel_bc2(reg_sel_bc2_sig) ,         // input  reg_sel_bc2_sig\n    .reg_sel_bc(reg_sel_bc_sig) ,           // input  reg_sel_bc_sig\n    .reg_sel_af2(reg_sel_af2_sig) ,         // input  reg_sel_af2_sig\n    .reg_sel_af(reg_sel_af_sig) ,           // input  reg_sel_af_sig\n    .reg_gp_we(reg_gp_we_sig) ,             // input  reg_gp_we_sig\n    .reg_sys_we_lo(reg_sys_we_lo_sig) ,     // input  reg_sys_we_lo_sig\n    .reg_sys_we_hi(reg_sys_we_hi_sig) ,     // input  reg_sys_we_hi_sig\n    .ctl_reg_in_hi(ctl_reg_in_hi_sig) ,     // input  ctl_reg_in_hi_sig\n    .ctl_reg_in_lo(ctl_reg_in_lo_sig) ,     // input  ctl_reg_in_lo_sig\n    .ctl_reg_out_lo(ctl_reg_out_lo_sig) ,   // input  ctl_reg_out_lo_sig\n    .ctl_reg_out_hi(ctl_reg_out_hi_sig) ,   // input  ctl_reg_out_hi_sig\n    .clk(clk) ,                             // input  clk\n    .db_lo_ds(db_lo_ds_sig) ,               // inout [7:0] db_lo_ds_sig\n    .db_hi_ds(db_hi_ds_sig) ,               // inout [7:0] db_hi_ds_sig\n    .db_lo_as(db_lo_as_sig) ,               // inout [7:0] db_lo_as_sig\n    .db_hi_as(db_hi_as_sig)                 // inout [7:0] db_hi_as_sig\n);\n\nendmodule\n"
  },
  {
    "path": "cpu/top-level-files.txt",
    "content": "# This is a list of A-Z80 files and their dependencies. It is used by several scripts.\n# To copy A-Z80 files into your project, run \"export.py\" script.\n\n------ Control block -------\ncontrol/clk_delay.v\ncontrol/decode_state.v\ncontrol/exec_module.vh\ncontrol/execute.v\n+ control/exec_matrix.vh\n+ control/exec_matrix_compiled.vh\n+ control/exec_module.vh\n+ control/exec_zero.vh\n+ control/temp_wires.vh\ncontrol/interrupts.v\ncontrol/ir.v\ncontrol/pin_control.v\ncontrol/pla_decode.v\ncontrol/resets.v\ncontrol/memory_ifc.v\ncontrol/sequencer.v\n\n---------- ALU -------------\nalu/alu_control.v\n+ alu/alu_mux_4.v\n+ alu/alu_mux_8.v\nalu/alu_select.v\nalu/alu_flags.v\n+ alu/alu_mux_2.v\n+ alu/alu_mux_4.v\nalu/alu.v\n+ alu/alu_core.v\n+ alu/alu_slice.v\n+ alu/alu_bit_select.v\n+ alu/alu_shifter_core.v\n+ alu/alu_mux_2z.v\n+ alu/alu_mux_3z.v\n+ alu/alu_prep_daa.v\n\n------ Register file -------\nregisters/reg_file.v\n+ registers/reg_latch.v\nregisters/reg_control.v\n\n------ Address latch -------\nbus/address_latch.v\n+ bus/address_mux.v\n+ bus/inc_dec.v\n+ bus/inc_dec_2bit.v\nbus/address_pins.v\n\n--------- Misc bus ---------\nbus/bus_control.v\nbus/bus_switch.v\n+ bus/data_switch.v\n+ bus/data_switch_mask.v\n\n------ I/O pin control -----\nbus/data_pins.v\nbus/control_pins_n.v\n\n--------- Top level --------\n+ toplevel/z80_top_direct_n.v\n+ toplevel/core.vh\n+ toplevel/coremodules.vh\n+ toplevel/globals.vh\n\nFiles=49\n"
  },
  {
    "path": "cpu/toplevel/core.vh",
    "content": "//============================================================================\n// A-Z80 core, instantiates and connects all internal blocks.\n//\n// This file is included by the \"z80_top_ifc_n\" and \"z80_top_direct\" providing\n// interface binding and direct (no interface) binding.\n//============================================================================\n\n// Include a list of top-level signal wires\n`include \"globals.vh\"\n\n// Specific to simulation, some modules in the schematics need to be pre-initialized\n// to avoid starting simulations with unknown values in selected flip flops.\nreg fpga_reset = 1;\nalways @(posedge clk)\nbegin\n    fpga_reset <= 0;\nend\n\n// Define internal data bus partitions segmented by data bus switches\nwire [7:0] db0;         // Segment connecting data pins and IR\nwire [7:0] db1;         // Segment leading to the ALU\nwire [7:0] db2;         // Segment with msb part of the register address-side interface\n\nwire [7:0] db_hi_as;    // Register file data bus segment high byte\nwire [7:0] db_lo_as;    // Register file data bus segment low byte\n\nwire [6:0] prefix;      // Instruction decode PLA prefix bitfield\nassign prefix = { ~use_ixiy, use_ixiy, ~in_halt, in_alu, table_xx, table_cb, table_ed };\n\nwire nM1_int;           // External pins timing control\nassign nM1_int = !(setM1 | (fFetch & T1));\n\n`include \"coremodules.vh\"\n\n// Data path within the CPU in various forms, ending with data pins\ndata_switch sw2_( .sw_up_en(bus_sw_2u), .sw_down_en(bus_sw_2d), .db_up(db1[7:0]), .db_down(db2[7:0]) );\n\n// Data switch SW1 with the data mask\ndata_switch_mask sw1_( .sw_mask543_en(bus_sw_mask543_en), .sw_up_en(bus_sw_1u), .sw_down_en(bus_sw_1d), .db_up(db0[7:0]), .db_down(db1[7:0]) );\n\n/* This SystemVerilog-style code is kept for future reference\n// Control block\nclk_delay   clk_delay_( .* );\ndecode_state decode_state_( .* );\nexecute     execute_( .* );\ninterrupts  interrupts_( .*, .db(db0[4:3]) );\nir          ir_( .*, .db(db0[7:0]) );\npin_control pin_control_( .* );\npla_decode  pla_decode_( .* );\nresets      resets_( .* );\nsequencer   sequencer_( .* );\n\n// ALU and ALU control, including the flags\nalu_control alu_control_( .*, .db(db1[7:0]), .op543({pla[104],pla[103],pla[102]}) );\nalu_select  alu_select_( .* );\nalu_flags   alu_flags_( .*, .db(db1[7:0]) );\nalu         alu_( .*, .db(db2[7:0]), .bsel(db0[5:3]) );\n\n// Register file and register control\nreg_file    reg_file_( .*, .db_hi_ds(db2[7:0]), .db_lo_ds(db1[7:0]), .db_hi_as(db_hi_as[7:0]), .db_lo_as(db_lo_as[7:0]) );\nreg_control reg_control_( .* );\n\n// Address latch and the incrementer\naddress_latch address_latch_( .*, .abus({db_hi_as[7:0], db_lo_as[7:0]}) );\n\n// Misc bus\nbus_control bus_control_( .*, .db(db0[7:0]) );\nbus_switch bus_switch_( .* );\n\n// Timing control of the external pins\nmemory_ifc memory_ifc_( .* );\n*/\n"
  },
  {
    "path": "cpu/toplevel/coremodules.vh",
    "content": "// Automatically generated by gencoremodules.py\n\nclk_delay clk_delay_(\n    .clk (clk),\n    .in_intr (in_intr),\n    .nreset (nreset),\n    .T1 (T1),\n    .latch_wait (latch_wait),\n    .mwait (mwait),\n    .M1 (M1),\n    .busrq (busrq),\n    .setM1 (setM1),\n    .hold_clk_iorq (hold_clk_iorq),\n    .hold_clk_wait (hold_clk_wait),\n    .iorq_Tw (iorq_Tw),\n    .busack (busack),\n    .pin_control_oe (pin_control_oe),\n    .hold_clk_busrq (hold_clk_busrq),\n    .nhold_clk_wait (nhold_clk_wait)\n);\n\ndecode_state decode_state_(\n    .ctl_state_iy_set (ctl_state_iy_set),\n    .ctl_state_ixiy_clr (ctl_state_ixiy_clr),\n    .ctl_state_ixiy_we (ctl_state_ixiy_we),\n    .ctl_state_halt_set (ctl_state_halt_set),\n    .ctl_state_tbl_ed_set (ctl_state_tbl_ed_set),\n    .ctl_state_tbl_cb_set (ctl_state_tbl_cb_set),\n    .ctl_state_alu (ctl_state_alu),\n    .clk (clk),\n    .address_is_1 (address_is_1),\n    .ctl_repeat_we (ctl_repeat_we),\n    .in_intr (in_intr),\n    .in_nmi (in_nmi),\n    .nreset (nreset),\n    .ctl_state_tbl_we (ctl_state_tbl_we),\n    .nhold_clk_wait (nhold_clk_wait),\n    .in_halt (in_halt),\n    .table_cb (table_cb),\n    .table_ed (table_ed),\n    .table_xx (table_xx),\n    .use_ix (use_ix),\n    .use_ixiy (use_ixiy),\n    .in_alu (in_alu),\n    .repeat_en (repeat_en)\n);\n\nexecute execute_(\n    .ctl_state_iy_set (ctl_state_iy_set),\n    .ctl_state_ixiy_clr (ctl_state_ixiy_clr),\n    .ctl_state_ixiy_we (ctl_state_ixiy_we),\n    .ctl_state_halt_set (ctl_state_halt_set),\n    .ctl_state_tbl_ed_set (ctl_state_tbl_ed_set),\n    .ctl_state_tbl_cb_set (ctl_state_tbl_cb_set),\n    .ctl_state_alu (ctl_state_alu),\n    .ctl_repeat_we (ctl_repeat_we),\n    .ctl_state_tbl_we (ctl_state_tbl_we),\n    .ctl_iff1_iff2 (ctl_iff1_iff2),\n    .ctl_iffx_we (ctl_iffx_we),\n    .ctl_iffx_bit (ctl_iffx_bit),\n    .ctl_im_we (ctl_im_we),\n    .ctl_no_ints (ctl_no_ints),\n    .ctl_ir_we (ctl_ir_we),\n    .ctl_mRead (ctl_mRead),\n    .ctl_mWrite (ctl_mWrite),\n    .ctl_iorw (ctl_iorw),\n    .ctl_shift_en (ctl_shift_en),\n    .ctl_daa_oe (ctl_daa_oe),\n    .ctl_alu_op_low (ctl_alu_op_low),\n    .ctl_cond_short (ctl_cond_short),\n    .ctl_alu_core_hf (ctl_alu_core_hf),\n    .ctl_eval_cond (ctl_eval_cond),\n    .ctl_66_oe (ctl_66_oe),\n    .ctl_pf_sel (ctl_pf_sel),\n    .ctl_alu_oe (ctl_alu_oe),\n    .ctl_alu_shift_oe (ctl_alu_shift_oe),\n    .ctl_alu_op2_oe (ctl_alu_op2_oe),\n    .ctl_alu_res_oe (ctl_alu_res_oe),\n    .ctl_alu_op1_oe (ctl_alu_op1_oe),\n    .ctl_alu_bs_oe (ctl_alu_bs_oe),\n    .ctl_alu_op1_sel_bus (ctl_alu_op1_sel_bus),\n    .ctl_alu_op1_sel_low (ctl_alu_op1_sel_low),\n    .ctl_alu_op1_sel_zero (ctl_alu_op1_sel_zero),\n    .ctl_alu_op2_sel_zero (ctl_alu_op2_sel_zero),\n    .ctl_alu_op2_sel_bus (ctl_alu_op2_sel_bus),\n    .ctl_alu_op2_sel_lq (ctl_alu_op2_sel_lq),\n    .ctl_alu_sel_op2_neg (ctl_alu_sel_op2_neg),\n    .ctl_alu_sel_op2_high (ctl_alu_sel_op2_high),\n    .ctl_alu_core_R (ctl_alu_core_R),\n    .ctl_alu_core_V (ctl_alu_core_V),\n    .ctl_alu_core_S (ctl_alu_core_S),\n    .ctl_flags_oe (ctl_flags_oe),\n    .ctl_flags_bus (ctl_flags_bus),\n    .ctl_flags_alu (ctl_flags_alu),\n    .ctl_flags_nf_set (ctl_flags_nf_set),\n    .ctl_flags_cf_set (ctl_flags_cf_set),\n    .ctl_flags_cf_cpl (ctl_flags_cf_cpl),\n    .ctl_flags_cf_we (ctl_flags_cf_we),\n    .ctl_flags_sz_we (ctl_flags_sz_we),\n    .ctl_flags_xy_we (ctl_flags_xy_we),\n    .ctl_flags_hf_we (ctl_flags_hf_we),\n    .ctl_flags_pf_we (ctl_flags_pf_we),\n    .ctl_flags_nf_we (ctl_flags_nf_we),\n    .ctl_flags_cf2_we (ctl_flags_cf2_we),\n    .ctl_flags_hf_cpl (ctl_flags_hf_cpl),\n    .ctl_flags_use_cf2 (ctl_flags_use_cf2),\n    .ctl_flags_hf2_we (ctl_flags_hf2_we),\n    .ctl_flags_nf_clr (ctl_flags_nf_clr),\n    .ctl_alu_zero_16bit (ctl_alu_zero_16bit),\n    .ctl_flags_cf2_sel_shift (ctl_flags_cf2_sel_shift),\n    .ctl_flags_cf2_sel_daa (ctl_flags_cf2_sel_daa),\n    .ctl_sw_4u (ctl_sw_4u),\n    .ctl_reg_in_hi (ctl_reg_in_hi),\n    .ctl_reg_in_lo (ctl_reg_in_lo),\n    .ctl_reg_out_lo (ctl_reg_out_lo),\n    .ctl_reg_out_hi (ctl_reg_out_hi),\n    .ctl_reg_exx (ctl_reg_exx),\n    .ctl_reg_ex_af (ctl_reg_ex_af),\n    .ctl_reg_ex_de_hl (ctl_reg_ex_de_hl),\n    .ctl_reg_use_sp (ctl_reg_use_sp),\n    .ctl_reg_sel_pc (ctl_reg_sel_pc),\n    .ctl_reg_sel_ir (ctl_reg_sel_ir),\n    .ctl_reg_sel_wz (ctl_reg_sel_wz),\n    .ctl_reg_gp_we (ctl_reg_gp_we),\n    .ctl_reg_not_pc (ctl_reg_not_pc),\n    .ctl_reg_sys_we_lo (ctl_reg_sys_we_lo),\n    .ctl_reg_sys_we_hi (ctl_reg_sys_we_hi),\n    .ctl_reg_sys_we (ctl_reg_sys_we),\n    .ctl_sw_4d (ctl_sw_4d),\n    .ctl_reg_gp_hilo (ctl_reg_gp_hilo),\n    .ctl_reg_gp_sel (ctl_reg_gp_sel),\n    .ctl_reg_sys_hilo (ctl_reg_sys_hilo),\n    .ctl_inc_cy (ctl_inc_cy),\n    .ctl_inc_dec (ctl_inc_dec),\n    .ctl_al_we (ctl_al_we),\n    .ctl_inc_limit6 (ctl_inc_limit6),\n    .ctl_bus_inc_oe (ctl_bus_inc_oe),\n    .ctl_apin_mux (ctl_apin_mux),\n    .ctl_apin_mux2 (ctl_apin_mux2),\n    .ctl_bus_ff_oe (ctl_bus_ff_oe),\n    .ctl_bus_zero_oe (ctl_bus_zero_oe),\n    .ctl_sw_1u (ctl_sw_1u),\n    .ctl_sw_1d (ctl_sw_1d),\n    .ctl_sw_2u (ctl_sw_2u),\n    .ctl_sw_2d (ctl_sw_2d),\n    .ctl_sw_mask543_en (ctl_sw_mask543_en),\n    .ctl_bus_db_we (ctl_bus_db_we),\n    .ctl_bus_db_oe (ctl_bus_db_oe),\n    .nextM (nextM),\n    .setM1 (setM1),\n    .fFetch (fFetch),\n    .fMRead (fMRead),\n    .fMWrite (fMWrite),\n    .fIORead (fIORead),\n    .fIOWrite (fIOWrite),\n    .pla (pla),\n    .in_intr (in_intr),\n    .in_nmi (in_nmi),\n    .in_halt (in_halt),\n    .im1 (im1),\n    .im2 (im2),\n    .use_ixiy (use_ixiy),\n    .flags_cond_true (flags_cond_true),\n    .repeat_en (repeat_en),\n    .flags_zf (flags_zf),\n    .flags_nf (flags_nf),\n    .flags_sf (flags_sf),\n    .flags_cf (flags_cf),\n    .M1 (M1),\n    .M2 (M2),\n    .M3 (M3),\n    .M4 (M4),\n    .M5 (M5),\n    .T1 (T1),\n    .T2 (T2),\n    .T3 (T3),\n    .T4 (T4),\n    .T5 (T5),\n    .T6 (T6)\n);\n\ninterrupts interrupts_(\n    .ctl_iff1_iff2 (ctl_iff1_iff2),\n    .nmi (nmi),\n    .setM1 (setM1),\n    .intr (intr),\n    .ctl_iffx_we (ctl_iffx_we),\n    .ctl_iffx_bit (ctl_iffx_bit),\n    .ctl_im_we (ctl_im_we),\n    .clk (clk),\n    .ctl_no_ints (ctl_no_ints),\n    .nreset (nreset),\n    .db (db0[4:3]),\n    .iff2 (iff2),\n    .im1 (im1),\n    .im2 (im2),\n    .in_nmi (in_nmi),\n    .in_intr (in_intr)\n);\n\nir ir_(\n    .ctl_ir_we (ctl_ir_we),\n    .clk (clk),\n    .nreset (nreset),\n    .nhold_clk_wait (nhold_clk_wait),\n    .db (db0[7:0]),\n    .opcode (opcode)\n);\n\npin_control pin_control_(\n    .fFetch (fFetch),\n    .fMRead (fMRead),\n    .fMWrite (fMWrite),\n    .fIORead (fIORead),\n    .fIOWrite (fIOWrite),\n    .T1 (T1),\n    .T2 (T2),\n    .T3 (T3),\n    .T4 (T4),\n    .bus_ab_pin_we (bus_ab_pin_we),\n    .bus_db_pin_oe (bus_db_pin_oe),\n    .bus_db_pin_re (bus_db_pin_re)\n);\n\npla_decode pla_decode_(\n    .prefix (prefix),\n    .opcode (opcode),\n    .pla (pla)\n);\n\nresets resets_(\n    .reset_in (reset_in),\n    .clk (clk),\n    .M1 (M1),\n    .T2 (T2),\n    .fpga_reset (fpga_reset),\n    .nhold_clk_wait (nhold_clk_wait),\n    .clrpc (clrpc),\n    .nreset (nreset)\n);\n\nmemory_ifc memory_ifc_(\n    .clk (clk),\n    .nM1_int (nM1_int),\n    .ctl_mRead (ctl_mRead),\n    .ctl_mWrite (ctl_mWrite),\n    .in_intr (in_intr),\n    .nreset (nreset),\n    .fIORead (fIORead),\n    .fIOWrite (fIOWrite),\n    .setM1 (setM1),\n    .ctl_iorw (ctl_iorw),\n    .timings_en (timings_en),\n    .iorq_Tw (iorq_Tw),\n    .nhold_clk_wait (nhold_clk_wait),\n    .nM1_out (nM1_out),\n    .nRFSH_out (nRFSH_out),\n    .nMREQ_out (nMREQ_out),\n    .nRD_out (nRD_out),\n    .nWR_out (nWR_out),\n    .nIORQ_out (nIORQ_out),\n    .latch_wait (latch_wait),\n    .wait_m1 (wait_m1)\n);\n\nsequencer sequencer_(\n    .clk (clk),\n    .nextM (nextM),\n    .setM1 (setM1),\n    .nreset (nreset),\n    .hold_clk_iorq (hold_clk_iorq),\n    .hold_clk_wait (hold_clk_wait),\n    .hold_clk_busrq (hold_clk_busrq),\n    .M1 (M1),\n    .M2 (M2),\n    .M3 (M3),\n    .M4 (M4),\n    .M5 (M5),\n    .T1 (T1),\n    .T2 (T2),\n    .T3 (T3),\n    .T4 (T4),\n    .T5 (T5),\n    .T6 (T6),\n    .timings_en (timings_en)\n);\n\nalu_control alu_control_(\n    .alu_shift_db0 (alu_shift_db0),\n    .alu_shift_db7 (alu_shift_db7),\n    .ctl_shift_en (ctl_shift_en),\n    .alu_low_gt_9 (alu_low_gt_9),\n    .alu_high_gt_9 (alu_high_gt_9),\n    .alu_high_eq_9 (alu_high_eq_9),\n    .ctl_daa_oe (ctl_daa_oe),\n    .ctl_alu_op_low (ctl_alu_op_low),\n    .alu_parity_out (alu_parity_out),\n    .flags_cf (flags_cf),\n    .flags_zf (flags_zf),\n    .flags_pf (flags_pf),\n    .flags_sf (flags_sf),\n    .ctl_cond_short (ctl_cond_short),\n    .alu_vf_out (alu_vf_out),\n    .iff2 (iff2),\n    .ctl_alu_core_hf (ctl_alu_core_hf),\n    .ctl_eval_cond (ctl_eval_cond),\n    .repeat_en (repeat_en),\n    .flags_cf_latch (flags_cf_latch),\n    .flags_hf2 (flags_hf2),\n    .flags_hf (flags_hf),\n    .ctl_66_oe (ctl_66_oe),\n    .clk (clk),\n    .ctl_pf_sel (ctl_pf_sel),\n    .op543 ({pla[104],pla[103],pla[102]}),\n    .alu_shift_in (alu_shift_in),\n    .alu_shift_right (alu_shift_right),\n    .alu_shift_left (alu_shift_left),\n    .shift_cf_out (shift_cf_out),\n    .alu_parity_in (alu_parity_in),\n    .flags_cond_true (flags_cond_true),\n    .daa_cf_out (daa_cf_out),\n    .pf_sel (pf_sel),\n    .alu_op_low (alu_op_low),\n    .alu_core_cf_in (alu_core_cf_in),\n    .db (db1[7:0])\n);\n\nalu_select alu_select_(\n    .ctl_alu_oe (ctl_alu_oe),\n    .ctl_alu_shift_oe (ctl_alu_shift_oe),\n    .ctl_alu_op2_oe (ctl_alu_op2_oe),\n    .ctl_alu_res_oe (ctl_alu_res_oe),\n    .ctl_alu_op1_oe (ctl_alu_op1_oe),\n    .ctl_alu_bs_oe (ctl_alu_bs_oe),\n    .ctl_alu_op1_sel_bus (ctl_alu_op1_sel_bus),\n    .ctl_alu_op1_sel_low (ctl_alu_op1_sel_low),\n    .ctl_alu_op1_sel_zero (ctl_alu_op1_sel_zero),\n    .ctl_alu_op2_sel_zero (ctl_alu_op2_sel_zero),\n    .ctl_alu_op2_sel_bus (ctl_alu_op2_sel_bus),\n    .ctl_alu_op2_sel_lq (ctl_alu_op2_sel_lq),\n    .ctl_alu_sel_op2_neg (ctl_alu_sel_op2_neg),\n    .ctl_alu_sel_op2_high (ctl_alu_sel_op2_high),\n    .ctl_alu_core_R (ctl_alu_core_R),\n    .ctl_alu_core_V (ctl_alu_core_V),\n    .ctl_alu_core_S (ctl_alu_core_S),\n    .alu_oe (alu_oe),\n    .alu_shift_oe (alu_shift_oe),\n    .alu_op2_oe (alu_op2_oe),\n    .alu_res_oe (alu_res_oe),\n    .alu_op1_oe (alu_op1_oe),\n    .alu_bs_oe (alu_bs_oe),\n    .alu_op1_sel_bus (alu_op1_sel_bus),\n    .alu_op1_sel_low (alu_op1_sel_low),\n    .alu_op1_sel_zero (alu_op1_sel_zero),\n    .alu_op2_sel_zero (alu_op2_sel_zero),\n    .alu_op2_sel_bus (alu_op2_sel_bus),\n    .alu_op2_sel_lq (alu_op2_sel_lq),\n    .alu_sel_op2_neg (alu_sel_op2_neg),\n    .alu_sel_op2_high (alu_sel_op2_high),\n    .alu_core_R (alu_core_R),\n    .alu_core_V (alu_core_V),\n    .alu_core_S (alu_core_S)\n);\n\nalu_flags alu_flags_(\n    .ctl_flags_oe (ctl_flags_oe),\n    .ctl_flags_bus (ctl_flags_bus),\n    .ctl_flags_alu (ctl_flags_alu),\n    .alu_sf_out (alu_sf_out),\n    .alu_yf_out (alu_yf_out),\n    .alu_xf_out (alu_xf_out),\n    .ctl_flags_nf_set (ctl_flags_nf_set),\n    .alu_zero (alu_zero),\n    .shift_cf_out (shift_cf_out),\n    .alu_core_cf_out (alu_core_cf_out),\n    .daa_cf_out (daa_cf_out),\n    .ctl_flags_cf_set (ctl_flags_cf_set),\n    .ctl_flags_cf_cpl (ctl_flags_cf_cpl),\n    .pf_sel (pf_sel),\n    .ctl_flags_cf_we (ctl_flags_cf_we),\n    .ctl_flags_sz_we (ctl_flags_sz_we),\n    .ctl_flags_xy_we (ctl_flags_xy_we),\n    .ctl_flags_hf_we (ctl_flags_hf_we),\n    .ctl_flags_pf_we (ctl_flags_pf_we),\n    .ctl_flags_nf_we (ctl_flags_nf_we),\n    .ctl_flags_cf2_we (ctl_flags_cf2_we),\n    .ctl_flags_hf_cpl (ctl_flags_hf_cpl),\n    .ctl_flags_use_cf2 (ctl_flags_use_cf2),\n    .ctl_flags_hf2_we (ctl_flags_hf2_we),\n    .ctl_flags_nf_clr (ctl_flags_nf_clr),\n    .ctl_alu_zero_16bit (ctl_alu_zero_16bit),\n    .clk (clk),\n    .ctl_flags_cf2_sel_shift (ctl_flags_cf2_sel_shift),\n    .ctl_flags_cf2_sel_daa (ctl_flags_cf2_sel_daa),\n    .nhold_clk_wait (nhold_clk_wait),\n    .flags_sf (flags_sf),\n    .flags_zf (flags_zf),\n    .flags_hf (flags_hf),\n    .flags_pf (flags_pf),\n    .flags_cf (flags_cf),\n    .flags_nf (flags_nf),\n    .flags_cf_latch (flags_cf_latch),\n    .flags_hf2 (flags_hf2),\n    .db (db1[7:0])\n);\n\nalu alu_(\n    .alu_core_R (alu_core_R),\n    .alu_core_V (alu_core_V),\n    .alu_core_S (alu_core_S),\n    .alu_bs_oe (alu_bs_oe),\n    .alu_parity_in (alu_parity_in),\n    .alu_oe (alu_oe),\n    .alu_shift_oe (alu_shift_oe),\n    .alu_core_cf_in (alu_core_cf_in),\n    .alu_op2_oe (alu_op2_oe),\n    .alu_op1_oe (alu_op1_oe),\n    .alu_res_oe (alu_res_oe),\n    .alu_op1_sel_low (alu_op1_sel_low),\n    .alu_op1_sel_zero (alu_op1_sel_zero),\n    .alu_op1_sel_bus (alu_op1_sel_bus),\n    .alu_op2_sel_zero (alu_op2_sel_zero),\n    .alu_op2_sel_bus (alu_op2_sel_bus),\n    .alu_op2_sel_lq (alu_op2_sel_lq),\n    .alu_op_low (alu_op_low),\n    .alu_shift_in (alu_shift_in),\n    .alu_sel_op2_neg (alu_sel_op2_neg),\n    .alu_sel_op2_high (alu_sel_op2_high),\n    .alu_shift_left (alu_shift_left),\n    .alu_shift_right (alu_shift_right),\n    .clk (clk),\n    .bsel (db0[5:3]),\n    .alu_zero (alu_zero),\n    .alu_parity_out (alu_parity_out),\n    .alu_high_eq_9 (alu_high_eq_9),\n    .alu_high_gt_9 (alu_high_gt_9),\n    .alu_low_gt_9 (alu_low_gt_9),\n    .alu_shift_db0 (alu_shift_db0),\n    .alu_shift_db7 (alu_shift_db7),\n    .alu_core_cf_out (alu_core_cf_out),\n    .alu_sf_out (alu_sf_out),\n    .alu_yf_out (alu_yf_out),\n    .alu_xf_out (alu_xf_out),\n    .alu_vf_out (alu_vf_out),\n    .db (db2[7:0]),\n    .test_db_high (test_db_high),\n    .test_db_low (test_db_low)\n);\n\nreg_file reg_file_(\n    .reg_sel_sys_lo (reg_sel_sys_lo),\n    .reg_sel_gp_lo (reg_sel_gp_lo),\n    .reg_sel_sys_hi (reg_sel_sys_hi),\n    .reg_sel_gp_hi (reg_sel_gp_hi),\n    .reg_sel_ir (reg_sel_ir),\n    .reg_sel_pc (reg_sel_pc),\n    .ctl_sw_4u (ctl_sw_4u),\n    .reg_sel_wz (reg_sel_wz),\n    .reg_sel_sp (reg_sel_sp),\n    .reg_sel_iy (reg_sel_iy),\n    .reg_sel_ix (reg_sel_ix),\n    .reg_sel_hl2 (reg_sel_hl2),\n    .reg_sel_hl (reg_sel_hl),\n    .reg_sel_de2 (reg_sel_de2),\n    .reg_sel_de (reg_sel_de),\n    .reg_sel_bc2 (reg_sel_bc2),\n    .reg_sel_bc (reg_sel_bc),\n    .reg_sel_af2 (reg_sel_af2),\n    .reg_sel_af (reg_sel_af),\n    .reg_gp_we (reg_gp_we),\n    .reg_sys_we_lo (reg_sys_we_lo),\n    .reg_sys_we_hi (reg_sys_we_hi),\n    .ctl_reg_in_hi (ctl_reg_in_hi),\n    .ctl_reg_in_lo (ctl_reg_in_lo),\n    .ctl_reg_out_lo (ctl_reg_out_lo),\n    .ctl_reg_out_hi (ctl_reg_out_hi),\n    .clk (clk),\n    .reg_sw_4d_lo (reg_sw_4d_lo),\n    .reg_sw_4d_hi (reg_sw_4d_hi),\n    .db_hi_as (db_hi_as[7:0]),\n    .db_hi_ds (db2[7:0]),\n    .db_lo_as (db_lo_as[7:0]),\n    .db_lo_ds (db1[7:0])\n);\n\nreg_control reg_control_(\n    .ctl_reg_exx (ctl_reg_exx),\n    .ctl_reg_ex_af (ctl_reg_ex_af),\n    .ctl_reg_ex_de_hl (ctl_reg_ex_de_hl),\n    .ctl_reg_use_sp (ctl_reg_use_sp),\n    .nreset (nreset),\n    .ctl_reg_sel_pc (ctl_reg_sel_pc),\n    .ctl_reg_sel_ir (ctl_reg_sel_ir),\n    .ctl_reg_sel_wz (ctl_reg_sel_wz),\n    .ctl_reg_gp_we (ctl_reg_gp_we),\n    .ctl_reg_not_pc (ctl_reg_not_pc),\n    .use_ixiy (use_ixiy),\n    .use_ix (use_ix),\n    .ctl_reg_sys_we_lo (ctl_reg_sys_we_lo),\n    .ctl_reg_sys_we_hi (ctl_reg_sys_we_hi),\n    .ctl_reg_sys_we (ctl_reg_sys_we),\n    .clk (clk),\n    .ctl_sw_4d (ctl_sw_4d),\n    .nhold_clk_wait (nhold_clk_wait),\n    .ctl_reg_gp_hilo (ctl_reg_gp_hilo),\n    .ctl_reg_gp_sel (ctl_reg_gp_sel),\n    .ctl_reg_sys_hilo (ctl_reg_sys_hilo),\n    .reg_sel_bc (reg_sel_bc),\n    .reg_sel_bc2 (reg_sel_bc2),\n    .reg_sel_ix (reg_sel_ix),\n    .reg_sel_iy (reg_sel_iy),\n    .reg_sel_de (reg_sel_de),\n    .reg_sel_hl (reg_sel_hl),\n    .reg_sel_de2 (reg_sel_de2),\n    .reg_sel_hl2 (reg_sel_hl2),\n    .reg_sel_af (reg_sel_af),\n    .reg_sel_af2 (reg_sel_af2),\n    .reg_sel_wz (reg_sel_wz),\n    .reg_sel_pc (reg_sel_pc),\n    .reg_sel_ir (reg_sel_ir),\n    .reg_sel_sp (reg_sel_sp),\n    .reg_sel_gp_hi (reg_sel_gp_hi),\n    .reg_sel_gp_lo (reg_sel_gp_lo),\n    .reg_sel_sys_lo (reg_sel_sys_lo),\n    .reg_sel_sys_hi (reg_sel_sys_hi),\n    .reg_gp_we (reg_gp_we),\n    .reg_sys_we_lo (reg_sys_we_lo),\n    .reg_sys_we_hi (reg_sys_we_hi),\n    .reg_sw_4d_lo (reg_sw_4d_lo),\n    .reg_sw_4d_hi (reg_sw_4d_hi)\n);\n\naddress_latch address_latch_(\n    .ctl_inc_cy (ctl_inc_cy),\n    .ctl_inc_dec (ctl_inc_dec),\n    .ctl_al_we (ctl_al_we),\n    .ctl_inc_limit6 (ctl_inc_limit6),\n    .ctl_bus_inc_oe (ctl_bus_inc_oe),\n    .clk (clk),\n    .ctl_apin_mux (ctl_apin_mux),\n    .ctl_apin_mux2 (ctl_apin_mux2),\n    .clrpc (clrpc),\n    .nreset (nreset),\n    .address_is_1 (address_is_1),\n    .abus ({db_hi_as[7:0], db_lo_as[7:0]}),\n    .address (address)\n);\n\nbus_control bus_control_(\n    .ctl_bus_ff_oe (ctl_bus_ff_oe),\n    .ctl_bus_zero_oe (ctl_bus_zero_oe),\n    .db (db0[7:0])\n);\n\nbus_switch bus_switch_(\n    .ctl_sw_1u (ctl_sw_1u),\n    .ctl_sw_1d (ctl_sw_1d),\n    .ctl_sw_2u (ctl_sw_2u),\n    .ctl_sw_2d (ctl_sw_2d),\n    .ctl_sw_mask543_en (ctl_sw_mask543_en),\n    .bus_sw_1u (bus_sw_1u),\n    .bus_sw_1d (bus_sw_1d),\n    .bus_sw_2u (bus_sw_2u),\n    .bus_sw_2d (bus_sw_2d),\n    .bus_sw_mask543_en (bus_sw_mask543_en)\n);\n"
  },
  {
    "path": "cpu/toplevel/fuse/README",
    "content": "These files are part of the Fuse emulator Z80 test vectors:\nhttp://fuse-emulator.sourceforge.net/\n\nFile formats\n============\n\ntests.in\n--------\n\nEach test has the format:\n\n<arbitrary test description>\nAF BC DE HL AF' BC' DE' HL' IX IY SP PC\nI R IFF1 IFF2 IM <halted> <tstates>\n\n<halted> specifies whether the Z80 is halted.\n<tstates> specifies the number of tstates to run the test for, in\n  decimal; the number actually executed may be higher, as the final\n  instruction is allowed to complete.\n\nThen followed by lines specifying the initial memory setup. Each has\nthe format:\n\n<start address> <byte1> <byte2> ... -1\n\neg\n\n1234 56 78 9a -1\n\nsays to put 0x56 at 0x1234, 0x78 at 0x1235 and 0x9a at 0x1236.\n\nFinally, -1 to end the test. Blank lines may follow before the next test.\n\ntests.expected\n--------------\n\nEach test output starts with the test description, followed by a list\nof 'events': each has the format\n\n<time> <type> <address> <data>\n\n<time> is simply the time at which the event occurs.\n<type> is one of MR (memory read), MW (memory write), MC (memory\n       contend), PR (port read), PW (port write) or PC (port contend).\n<address> is the address (or IO port) affected.\n<data> is the byte written or read. Missing for contentions.\n\nAfter that, lines specifying AF, BC etc as for .in files. <tstates>\nnow specifies the final time.\n\nAfter that, lines specifying which bits of memory have changed since\nthe initial setup. Same format as for .in files.\n\nWhy some specific tests are here\n================================\n\n37_{1,2,3}: check the behaviour of SCF with respect to bits 3 and 5\n\t    (bug fixed on 20040225).\n\ncb{4,5,6,7}{7,f}_1: designed to check that bits 3 and 5 are copied to\n\t\t    F only for BIT 3,<arg> and BIT 5,<arg> respectively\n\t\t    (bug fixed on 20040225).\n\n\t\t    However, later research has revealed the bits 3\n\t\t    and 5 are copied on all BIT instructions, so these\n\t\t    tests are now essentially redundant.\n\nd{3,b}_{1,2,3}: check for correct port contention on IO in the four\n\t        relevant states (port high byte in 0x40 to 0x7f or not,\n\t\tport low bit set or reset).\n\ndd00.in, ddfd00.in: test timings of \"extended NOP\" opcodes DD 00 and\n\t\t    DD FD 00; the extra 00 at the end is to check the\n\t\t    next opcode executes at the right time (bug fixed\n\t\t    on 20060722).\n\n"
  },
  {
    "path": "cpu/toplevel/fuse/regress.expected",
    "content": "00      NOP\n    0 MC 0000\n    4 MR 0000 00\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\ned67    RRD\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 67\n    8 MC b9de\n   11 MR b9de 93\n   11 MC b9de\n   12 MC b9de\n   13 MC b9de\n   14 MC b9de\n   15 MC b9de\n   18 MW b9de 69\n3324 b16a a4db b9de 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 18\nb9de 69 -1\n\ned6f    RLD\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 6f\n    8 MC 403c\n   11 MR 403c c4\n   11 MC 403c\n   12 MC 403c\n   13 MC 403c\n   14 MC 403c\n   15 MC 403c\n   18 MW 403c 45\n6c2d 7a7a ecf0 403c 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 18\n403c 45 -1\n\n81      ADD A,C\n    0 MC 0000\n    4 MR 0000 81\n3031 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\ncb41    BIT 0,C\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 41\n9e10 1b43 954e 7be9 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb93    RES 2,E\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 93\nc200 4e05 b3f8 2234 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbe5    SET 4,L\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 e5\nca00 df0d d588 b49f 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\n8c      ADC A,H\n    0 MC 0000\n    4 MR 0000 8c\nd191 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n92      SUB D\n    0 MC 0000\n    4 MR 0000 92\nd582 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n9d      SBC A,L\n    0 MC 0000\n    4 MR 0000 9d\n4f1a 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\na3      AND E\n    0 MC 0000\n    4 MR 0000 a3\n0514 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\nae      XOR (HL)\n    0 MC 0000\n    4 MR 0000 ae\n    4 MC dca6\n    7 MR dca6 49\nbca8 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 7\n\nb4      OR H\n    0 MC 0000\n    4 MR 0000 b4\nfda8 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\nbf      CP A\n    0 MC 0000\n    4 MR 0000 bf\nf562 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n43      LD B,E\n    0 MC 0000\n    4 MR 0000 43\n0200 d898 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n6e      LD L,(HL)\n    0 MC 0000\n    4 MR 0000 6e\n    4 MC a169\n    7 MR a169 50\n0200 cf98 90d8 a150 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 7\n\ne3      EX (SP),HL\n    0 MC 0000\n    4 MR 0000 e3\n    4 MC 0373\n    7 MR 0373 8e\n    7 MC 0374\n   10 MR 0374 e1\n   10 MC 0374\n   11 MC 0374\n   14 MW 0374 4d\n   14 MC 0373\n   17 MW 0373 22\n   17 MC 0373\n   18 MC 0373\n0000 0000 0000 e18e 0000 0000 0000 0000 0000 0000 0373 0001\n00 01 0 0 0 0 19\n0373 22 4d -1\n\n03      INC BC\n    0 MC 0000\n    4 MR 0000 03\n    4 MC 0001\n    5 MC 0001\n0000 789b 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 6\n\n3b      DEC SP\n    0 MC 0000\n    4 MR 0000 3b\n    4 MC 0001\n    5 MC 0001\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 9d35 0001\n00 01 0 0 0 0 6\n\n07      RLCA\n    0 MC 0000\n    4 MR 0000 07\n1101 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n1f      RRA\n    0 MC 0000\n    4 MR 0000 1f\n00c5 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\ncb09    RRC C\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 09\n182c 122e dd97 59c6 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb11    RL C\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 11\n65ac e2b8 4b8a ed42 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb36    SLL (HL)*\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 36\n    8 MC 6d38\n   11 MR 6d38 f1\n   11 MC 6d38\n   12 MC 6d38\n   15 MW 6d38 e3\n8aa1 1185 1dde 6d38 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 15\n6d38 e3 -1\n\ncb52    BIT 2,D\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 52\n8b74 ff7a b0ff ac44 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb93    RES 2,E\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 93\nc200 4e05 b3f8 2234 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbc4    SET 0,H\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 c4\n7e00 545a 6ecf 5976 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ndd75    LD (IX+d),L\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 75\n    8 MC 0002\n   11 MR 0002 30\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC ae7c\n   19 MW ae7c 4f\n5772 e833 b63e 734f 0000 0000 0000 0000 ae4c e8c2 0000 0003\n00 02 0 0 0 0 19\nae7c 4f -1\n\ndd4e    LD C,(IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 4e\n    8 MC 0002\n   11 MR 0002 2e\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC d979\n   19 MR d979 76\n7bf7 6676 8d55 def2 0000 0000 0000 0000 d94b 17fb 0000 0003\n00 02 0 0 0 0 19\n\n"
  },
  {
    "path": "cpu/toplevel/fuse/regress.in",
    "content": "00      NOP\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 00 -1\n-1\n\ned67    RRD\n3624 b16a a4db b9de 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed 67 -1\nb9de 93 -1\n-1\n\ned6f    RLD\n658b 7a7a ecf0 403c 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed 6f -1\n403c c4 -1\n-1\n\n81      ADD A,C\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 81 -1\ndca6 49 -1\n-1\n\ncb41    BIT 0,C\n9e00 1b43 954e 7be9 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 41 -1\n7be9 f7 -1\n-1\n\ncb93    RES 2,E\nc200 4e05 b3f8 2234 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 93 -1\n2234 a0 -1\n-1\n\ncbe5    SET 4,L\nca00 df0d d588 b48f 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb e5 -1\nb48f cf -1\n-1\n\n8c      ADC A,H\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 8c -1\ndca6 49 -1\n-1\n\n92      SUB D\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 92 -1\ndca6 49 -1\n-1\n\n9d      SBC A,L\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 9d -1\ndca6 49 -1\n-1\n\na3      AND E\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 a3 -1\ndca6 49 -1\n-1\n\nae      XOR (HL)\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ae -1\ndca6 49 -1\n-1\n\nb4      OR H\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 b4 -1\ndca6 49 -1\n-1\n\nbf      CP A\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 bf -1\ndca6 49 -1\n-1\n\n43      LD B,E\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 43 -1\na169 50 -1\n-1\n\n6e      LD L,(HL)\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 6e -1\na169 50 -1\n-1\n\ne3      EX (SP),HL\n0000 0000 0000 4d22 0000 0000 0000 0000 0000 0000 0373 0000\n00 00 0 0 0 0     1\n0000 e3 -1\n0373 8e e1 -1\n-1\n\n03      INC BC\n0000 789a 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 03 -1\n-1\n\n3b      DEC SP\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 9d36 0000\n00 00 0 0 0 0     1\n0000 3b -1\n-1\n\n07      RLCA\n8800 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 07 -1\n-1\n\n1f      RRA\n01c4 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 1f -1\n-1\n\ncb09    RRC C\n1800 125c dd97 59c6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 09 -1\n59c6 9e -1\n-1\n\ncb11    RL C\n6500 e25c 4b8a ed42 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 11 -1\ned42 b7 -1\n-1\n\ncb36    SLL (HL)*\n8a00 1185 1dde 6d38 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 36 -1\n6d38 f1 -1\n-1\n\ncb52    BIT 2,D\n8b00 ff7a b0ff ac44 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 52 -1\nac44 00 -1\n-1\n\ncb93    RES 2,E\nc200 4e05 b3f8 2234 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 93 -1\n2234 a0 -1\n-1\n\ncbc4    SET 0,H\n7e00 545a 6ecf 5876 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb c4 -1\n5876 9d -1\n-1\n\ndd75    LD (IX+d),L\n5772 e833 b63e 734f 0000 0000 0000 0000 ae4c e8c2 0000 0000\n00 00 0 0 0 0     1\n0000 dd 75 30 -1\n-1\n\ndd4e    LD C,(IX+d)\n7bf7 6605 8d55 def2 0000 0000 0000 0000 d94b 17fb 0000 0000\n00 00 0 0 0 0     1\n0000 dd 4e 2e -1\nd979 76 -1\n-1\n\n"
  },
  {
    "path": "cpu/toplevel/fuse/tests.expected",
    "content": "00      NOP\n    0 MC 0000\n    4 MR 0000 00\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n01      LD BC,nn\n    0 MC 0000\n    4 MR 0000 01\n    4 MC 0001\n    7 MR 0001 12\n    7 MC 0002\n   10 MR 0002 34\n0000 3412 0000 0000 0000 0000 0000 0000 0000 0000 0000 0003\n00 01 0 0 0 0 10\n\n02      LD (BC),A\n    0 MC 0000\n    4 MR 0000 02\n    4 MC 0001\n    7 MW 0001 56\n5600 0001 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 7\n0001 56 -1\n\n03      INC BC\n    0 MC 0000\n    4 MR 0000 03\n    4 MC 0001\n    5 MC 0001\n0000 789b 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 6\n\n04      INC B\n    0 MC 0000\n    4 MR 0000 04\n0050 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n05      DEC B\n    0 MC 0000\n    4 MR 0000 05\n00ba ff00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n06      LD B,n\n    0 MC 0000\n    4 MR 0000 06\n    4 MC 0001\n    7 MR 0001 bc\n0000 bc00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0002\n00 01 0 0 0 0 7\n\n07      RLCA\n    0 MC 0000\n    4 MR 0000 07\n1101 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n08      EX AF,AF'\n    0 MC 0000\n    4 MR 0000 08\n1234 0000 0000 0000 def0 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n09      ADD HL,BC\n    0 MC 0000\n    4 MR 0000 09\n    4 MC 0001\n    5 MC 0001\n    6 MC 0001\n    7 MC 0001\n    8 MC 0001\n    9 MC 0001\n   10 MC 0001\n0030 5678 0000 f134 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 11\n\n0a      LD A,(BC)\n    0 MC 0000\n    4 MR 0000 0a\n    4 MC 0001\n    7 MR 0001 de\nde00 0001 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 7\n\n0b      DEC BC\n    0 MC 0000\n    4 MR 0000 0b\n    4 MC 0001\n    5 MC 0001\n0000 ffff 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 6\n\n0c      INC C\n    0 MC 0000\n    4 MR 0000 0c\n0094 0080 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n0d      DEC C\n    0 MC 0000\n    4 MR 0000 0d\n003e 007f 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n0e      LD C,n\n    0 MC 0000\n    4 MR 0000 0e\n    4 MC 0001\n    7 MR 0001 f0\n0000 00f0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0002\n00 01 0 0 0 0 7\n\n0f      RRCA\n    0 MC 0000\n    4 MR 0000 0f\na021 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n10      DJNZ (PC+e)\n    0 MC 0000\n    4 MR 0000 00\n    4 MC 0001\n    8 MR 0001 10\n    8 MC 0002\n    9 MC 0002\n   12 MR 0002 fd\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC 0002\n   17 MC 0000\n   21 MR 0000 00\n   21 MC 0001\n   25 MR 0001 10\n   25 MC 0004\n   26 MC 0002\n   29 MR 0002 fd\n   29 MC 0002\n   30 MC 0002\n   31 MC 0002\n   32 MC 0002\n   33 MC 0002\n   34 MC 0000\n   38 MR 0000 00\n   38 MC 0001\n   42 MR 0001 10\n   42 MC 0006\n   43 MC 0002\n   46 MR 0002 fd\n   46 MC 0002\n   47 MC 0002\n   48 MC 0002\n   49 MC 0002\n   50 MC 0002\n   51 MC 0000\n   55 MR 0000 00\n   55 MC 0001\n   59 MR 0001 10\n   59 MC 0008\n   60 MC 0002\n   63 MR 0002 fd\n   63 MC 0002\n   64 MC 0002\n   65 MC 0002\n   66 MC 0002\n   67 MC 0002\n   68 MC 0000\n   72 MR 0000 00\n   72 MC 0001\n   76 MR 0001 10\n   76 MC 000a\n   77 MC 0002\n   80 MR 0002 fd\n   80 MC 0002\n   81 MC 0002\n   82 MC 0002\n   83 MC 0002\n   84 MC 0002\n   85 MC 0000\n   89 MR 0000 00\n   89 MC 0001\n   93 MR 0001 10\n   93 MC 000c\n   94 MC 0002\n   97 MR 0002 fd\n   97 MC 0002\n   98 MC 0002\n   99 MC 0002\n  100 MC 0002\n  101 MC 0002\n  102 MC 0000\n  106 MR 0000 00\n  106 MC 0001\n  110 MR 0001 10\n  110 MC 000e\n  111 MC 0002\n  114 MR 0002 fd\n  114 MC 0002\n  115 MC 0002\n  116 MC 0002\n  117 MC 0002\n  118 MC 0002\n  119 MC 0000\n  123 MR 0000 00\n  123 MC 0001\n  127 MR 0001 10\n  127 MC 0010\n  128 MC 0002\n  131 MC 0003\n  135 MR 0003 0c\n0000 0001 0000 0000 0000 0000 0000 0000 0000 0000 0000 0004\n00 11 0 0 0 0 135\n\n11      LD DE,nn\n    0 MC 0000\n    4 MR 0000 11\n    4 MC 0001\n    7 MR 0001 9a\n    7 MC 0002\n   10 MR 0002 bc\n0000 0000 bc9a 0000 0000 0000 0000 0000 0000 0000 0000 0003\n00 01 0 0 0 0 10\n\n12      LD (DE),A\n    0 MC 0000\n    4 MR 0000 12\n    4 MC 8000\n    7 MW 8000 56\n5600 0000 8000 0000 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 7\n8000 56 -1\n\n13      INC DE\n    0 MC 0000\n    4 MR 0000 13\n    4 MC 0001\n    5 MC 0001\n0000 0000 def1 0000 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 6\n\n14      INC D\n    0 MC 0000\n    4 MR 0000 14\n0028 0000 2800 0000 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n15      DEC D\n    0 MC 0000\n    4 MR 0000 15\n001a 0000 0f00 0000 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n16      LD D,n\n    0 MC 0000\n    4 MR 0000 16\n    4 MC 0001\n    7 MR 0001 12\n0000 0000 1200 0000 0000 0000 0000 0000 0000 0000 0000 0002\n00 01 0 0 0 0 7\n\n17      RLA\n    0 MC 0000\n    4 MR 0000 17\n1100 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n18      JR e\n    0 MC 0000\n    4 MR 0000 18\n    4 MC 0001\n    7 MR 0001 40\n    7 MC 0001\n    8 MC 0001\n    9 MC 0001\n   10 MC 0001\n   11 MC 0001\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0042\n00 01 0 0 0 0 12\n\n19      ADD HL,DE\n    0 MC 0000\n    4 MR 0000 19\n    4 MC 0001\n    5 MC 0001\n    6 MC 0001\n    7 MC 0001\n    8 MC 0001\n    9 MC 0001\n   10 MC 0001\n0028 0000 3456 acf0 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 11\n\n1a      LD A,(DE)\n    0 MC 0000\n    4 MR 0000 1a\n    4 MC 8000\n    7 MR 8000 13\n1300 0000 8000 0000 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 7\n\n1b      DEC DE\n    0 MC 0000\n    4 MR 0000 1b\n    4 MC 0001\n    5 MC 0001\n0000 0000 e5d3 0000 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 6\n\n1c      INC E\n    0 MC 0000\n    4 MR 0000 1c\n00a8 0000 00ab 0000 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n1d      DEC E\n    0 MC 0000\n    4 MR 0000 1d\n00aa 0000 00a9 0000 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n1e      LD E,n\n    0 MC 0000\n    4 MR 0000 1e\n    4 MC 0001\n    7 MR 0001 ef\n0000 0000 00ef 0000 0000 0000 0000 0000 0000 0000 0000 0002\n00 01 0 0 0 0 7\n\n1f      RRA\n    0 MC 0000\n    4 MR 0000 1f\n00c5 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n20_1    JR NZ,e\n    0 MC 0000\n    4 MR 0000 20\n    4 MC 0001\n    7 MR 0001 40\n    7 MC 0001\n    8 MC 0001\n    9 MC 0001\n   10 MC 0001\n   11 MC 0001\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0042\n00 01 0 0 0 0 12\n\n20_2    JR NZ,e\n    0 MC 0000\n    4 MR 0000 20\n    4 MC 0001\n0040 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0002\n00 01 0 0 0 0 7\n\n21      LD HL,nn\n    0 MC 0000\n    4 MR 0000 21\n    4 MC 0001\n    7 MR 0001 28\n    7 MC 0002\n   10 MR 0002 ed\n0000 0000 0000 ed28 0000 0000 0000 0000 0000 0000 0000 0003\n00 01 0 0 0 0 10\n\n22      LD (nn),HL\n    0 MC 0000\n    4 MR 0000 22\n    4 MC 0001\n    7 MR 0001 b0\n    7 MC 0002\n   10 MR 0002 c3\n   10 MC c3b0\n   13 MW c3b0 4c\n   13 MC c3b1\n   16 MW c3b1 c6\n0000 0000 0000 c64c 0000 0000 0000 0000 0000 0000 0000 0003\n00 01 0 0 0 0 16\nc3b0 4c c6 -1\n\n23      INC HL\n    0 MC 0000\n    4 MR 0000 23\n    4 MC 0001\n    5 MC 0001\n0000 0000 0000 9c4f 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 6\n\n24      INC H\n    0 MC 0000\n    4 MR 0000 24\n0020 0000 0000 7300 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n25      DEC H\n    0 MC 0000\n    4 MR 0000 25\n00a2 0000 0000 a400 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n26      LD H,n\n    0 MC 0000\n    4 MR 0000 26\n    4 MC 0001\n    7 MR 0001 3a\n0000 0000 0000 3a00 0000 0000 0000 0000 0000 0000 0000 0002\n00 01 0 0 0 0 7\n\n27_1    DAA\n    0 MC 0000\n    4 MR 0000 27\n3423 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n27      DAA\n    0 MC 0000\n    4 MR 0000 27\n2530 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n28_1    JR Z,e\n    0 MC 0000\n    4 MR 0000 28\n    4 MC 0001\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0002\n00 01 0 0 0 0 7\n\n28_2    JR Z,e\n    0 MC 0000\n    4 MR 0000 28\n    4 MC 0001\n    7 MR 0001 8e\n    7 MC 0001\n    8 MC 0001\n    9 MC 0001\n   10 MC 0001\n   11 MC 0001\n0040 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ff90\n00 01 0 0 0 0 12\n\n29      ADD HL,HL\n    0 MC 0000\n    4 MR 0000 29\n    4 MC 0001\n    5 MC 0001\n    6 MC 0001\n    7 MC 0001\n    8 MC 0001\n    9 MC 0001\n   10 MC 0001\n0019 0000 0000 9bf4 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 11\n\n2a      LD HL,(nn)\n    0 MC 0000\n    4 MR 0000 2a\n    4 MC 0001\n    7 MR 0001 45\n    7 MC 0002\n   10 MR 0002 ac\n   10 MC ac45\n   13 MR ac45 c4\n   13 MC ac46\n   16 MR ac46 de\n0000 0000 0000 dec4 0000 0000 0000 0000 0000 0000 0000 0003\n00 01 0 0 0 0 16\n\n2b      DEC HL\n    0 MC 0000\n    4 MR 0000 2b\n    4 MC 0001\n    5 MC 0001\n0000 0000 0000 9e65 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 6\n\n2c      INC L\n    0 MC 0000\n    4 MR 0000 2c\n0020 0000 0000 0027 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n2d      DEC L\n    0 MC 0000\n    4 MR 0000 2d\n0022 0000 0000 0031 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n2e      LD L,n\n    0 MC 0000\n    4 MR 0000 2e\n    4 MC 0001\n    7 MR 0001 18\n0000 0000 0000 0018 0000 0000 0000 0000 0000 0000 0000 0002\n00 01 0 0 0 0 7\n\n2f      CPL\n    0 MC 0000\n    4 MR 0000 2f\n7632 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n30_1    JR NC,e\n    0 MC 0000\n    4 MR 0000 30\n    4 MC 0001\n    7 MR 0001 50\n    7 MC 0001\n    8 MC 0001\n    9 MC 0001\n   10 MC 0001\n   11 MC 0001\n0036 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0052\n00 01 0 0 0 0 12\n\n30_2    JR NC,e\n    0 MC 0000\n    4 MR 0000 30\n    4 MC 0001\n0037 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0002\n00 01 0 0 0 0 7\n\n31      LD SP,nn\n    0 MC 0000\n    4 MR 0000 31\n    4 MC 0001\n    7 MR 0001 d4\n    7 MC 0002\n   10 MR 0002 61\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 61d4 0003\n00 01 0 0 0 0 10\n\n32      LD (nn),A\n    0 MC 0000\n    4 MR 0000 32\n    4 MC 0001\n    7 MR 0001 ac\n    7 MC 0002\n   10 MR 0002 ad\n   10 MC adac\n   13 MW adac 0e\n0e00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0003\n00 01 0 0 0 0 13\nadac 0e -1\n\n33      INC SP\n    0 MC 0000\n    4 MR 0000 33\n    4 MC 0001\n    5 MC 0001\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 a55b 0001\n00 01 0 0 0 0 6\n\n34      INC (HL)\n    0 MC 0000\n    4 MR 0000 34\n    4 MC fe1d\n    7 MR fe1d fd\n    7 MC fe1d\n    8 MC fe1d\n   11 MW fe1d fe\n00a8 0000 0000 fe1d 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 11\nfe1d fe -1\n\n35      DEC (HL)\n    0 MC 0000\n    4 MR 0000 35\n    4 MC 470c\n    7 MR 470c 82\n    7 MC 470c\n    8 MC 470c\n   11 MW 470c 81\n0082 0000 0000 470c 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 11\n470c 81 -1\n\n36      LD (HL),n\n    0 MC 0000\n    4 MR 0000 36\n    4 MC 0001\n    7 MR 0001 7c\n    7 MC 7d29\n   10 MW 7d29 7c\n0000 0000 0000 7d29 0000 0000 0000 0000 0000 0000 0000 0002\n00 01 0 0 0 0 10\n7d29 7c -1\n\n37_1    SCF\n    0 MC 0000\n    4 MR 0000 37\n00c5 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n37_2    SCF\n    0 MC 0000\n    4 MR 0000 37\nff29 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n37_3    SCF\n    0 MC 0000\n    4 MR 0000 37\nffed 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n37      SCF\n    0 MC 0000\n    4 MR 0000 37\n0001 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n38_1    JR C,e\n    0 MC 0000\n    4 MR 0000 38\n    4 MC 0001\n00b2 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0002\n00 01 0 0 0 0 7\n\n38_2    JR C,e\n    0 MC 0000\n    4 MR 0000 38\n    4 MC 0001\n    7 MR 0001 66\n    7 MC 0001\n    8 MC 0001\n    9 MC 0001\n   10 MC 0001\n   11 MC 0001\n00b3 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0068\n00 01 0 0 0 0 12\n\n39      ADD HL,SP\n    0 MC 0000\n    4 MR 0000 29\n    4 MC 0001\n    5 MC 0001\n    6 MC 0001\n    7 MC 0001\n    8 MC 0001\n    9 MC 0001\n   10 MC 0001\n0030 0000 0000 35de 0000 0000 0000 0000 0000 0000 c534 0001\n00 01 0 0 0 0 11\n\n3a      LD A,(nn)\n    0 MC 0000\n    4 MR 0000 3a\n    4 MC 0001\n    7 MR 0001 52\n    7 MC 0002\n   10 MR 0002 99\n   10 MC 9952\n   13 MR 9952 28\n2800 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0003\n00 01 0 0 0 0 13\n\n3b      DEC SP\n    0 MC 0000\n    4 MR 0000 3b\n    4 MC 0001\n    5 MC 0001\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 9d35 0001\n00 01 0 0 0 0 6\n\n3c      INC A\n    0 MC 0000\n    4 MR 0000 3c\nd090 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n3d      DEC A\n    0 MC 0000\n    4 MR 0000 3d\ne9aa 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n3e      LD A,n\n    0 MC 0000\n    4 MR 0000 3e\n    4 MC 0001\n    7 MR 0001 d6\nd600 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0002\n00 01 0 0 0 0 7\n\n3f      CCF\n    0 MC 0000\n    4 MR 0000 3f\n0050 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n3f_1    CCF\n    0 MC 0000\n    4 MR 0000 3f\n0041 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n40      LD B,B\n    0 MC 0000\n    4 MR 0000 40\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n41      LD B,C\n    0 MC 0000\n    4 MR 0000 41\n0200 9898 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n42      LD B,D\n    0 MC 0000\n    4 MR 0000 42\n0200 9098 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n43      LD B,E\n    0 MC 0000\n    4 MR 0000 43\n0200 d898 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n44      LD B,H\n    0 MC 0000\n    4 MR 0000 44\n0200 a198 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n45      LD B,L\n    0 MC 0000\n    4 MR 0000 45\n0200 6998 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n46      LD B,(HL)\n    0 MC 0000\n    4 MR 0000 46\n    4 MC a169\n    7 MR a169 50\n0200 5098 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 7\n\n47      LD B,A\n    0 MC 0000\n    4 MR 0000 47\n0200 0298 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n48      LD C,B\n    0 MC 0000\n    4 MR 0000 48\n0200 cfcf 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n49      LD C,C\n    0 MC 0000\n    4 MR 0000 49\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n4a      LD C,D\n    0 MC 0000\n    4 MR 0000 4a\n0200 cf90 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n4b      LD C,E\n    0 MC 0000\n    4 MR 0000 4b\n0200 cfd8 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n4c      LD C,H\n    0 MC 0000\n    4 MR 0000 4c\n0200 cfa1 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n4d      LD C,L\n    0 MC 0000\n    4 MR 0000 4d\n0200 cf69 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n4e      LD C,(HL)\n    0 MC 0000\n    4 MR 0000 4e\n    4 MC a169\n    7 MR a169 50\n0200 cf50 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 7\n\n4f      LD C,A\n    0 MC 0000\n    4 MR 0000 4f\n0200 cf02 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n50      LD D,B\n    0 MC 0000\n    4 MR 0000 50\n0200 cf98 cfd8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n51      LD D,C\n    0 MC 0000\n    4 MR 0000 51\n0200 cf98 98d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n52      LD D,D\n    0 MC 0000\n    4 MR 0000 52\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n53      LD D,E\n    0 MC 0000\n    4 MR 0000 53\n0200 cf98 d8d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n54      LD D,H\n    0 MC 0000\n    4 MR 0000 54\n0200 cf98 a1d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n55      LD D,L\n    0 MC 0000\n    4 MR 0000 55\n0200 cf98 69d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n56      LD D,(HL)\n    0 MC 0000\n    4 MR 0000 56\n    4 MC a169\n    7 MR a169 50\n0200 cf98 50d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 7\n\n57      LD D,A\n    0 MC 0000\n    4 MR 0000 57\n0200 cf98 02d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n58      LD E,B\n    0 MC 0000\n    4 MR 0000 58\n0200 cf98 90cf a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n59      LD E,C\n    0 MC 0000\n    4 MR 0000 59\n0200 cf98 9098 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n5a      LD E,D\n    0 MC 0000\n    4 MR 0000 5a\n0200 cf98 9090 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n5b      LD E,E\n    0 MC 0000\n    4 MR 0000 5b\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n5c      LD E,H\n    0 MC 0000\n    4 MR 0000 5c\n0200 cf98 90a1 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n5d      LD E,L\n    0 MC 0000\n    4 MR 0000 5d\n0200 cf98 9069 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n5e      LD E,(HL)\n    0 MC 0000\n    4 MR 0000 5e\n    4 MC a169\n    7 MR a169 50\n0200 cf98 9050 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 7\n\n5f      LD E,A\n    0 MC 0000\n    4 MR 0000 5f\n0200 cf98 9002 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n60      LD H,B\n    0 MC 0000\n    4 MR 0000 60\n0200 cf98 90d8 cf69 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n61      LD H,C\n    0 MC 0000\n    4 MR 0000 61\n0200 cf98 90d8 9869 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n62      LD H,D\n    0 MC 0000\n    4 MR 0000 62\n0200 cf98 90d8 9069 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n63      LD H,E\n    0 MC 0000\n    4 MR 0000 63\n0200 cf98 90d8 d869 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n64      LD H,H\n    0 MC 0000\n    4 MR 0000 64\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n65      LD H,L\n    0 MC 0000\n    4 MR 0000 65\n0200 cf98 90d8 6969 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n66      LD H,(HL)\n    0 MC 0000\n    4 MR 0000 66\n    4 MC a169\n    7 MR a169 50\n0200 cf98 90d8 5069 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 7\n\n67      LD H,A\n    0 MC 0000\n    4 MR 0000 67\n0200 cf98 90d8 0269 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n68      LD L,B\n    0 MC 0000\n    4 MR 0000 68\n0200 cf98 90d8 a1cf 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n69      LD L,C\n    0 MC 0000\n    4 MR 0000 69\n0200 cf98 90d8 a198 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n6a      LD L,D\n    0 MC 0000\n    4 MR 0000 6a\n0200 cf98 90d8 a190 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n6b      LD L,E\n    0 MC 0000\n    4 MR 0000 6b\n0200 cf98 90d8 a1d8 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n6c      LD L,H\n    0 MC 0000\n    4 MR 0000 6c\n0200 cf98 90d8 a1a1 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n6d      LD L,L\n    0 MC 0000\n    4 MR 0000 6d\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n6e      LD L,(HL)\n    0 MC 0000\n    4 MR 0000 6e\n    4 MC a169\n    7 MR a169 50\n0200 cf98 90d8 a150 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 7\n\n6f      LD L,A\n    0 MC 0000\n    4 MR 0000 6f\n0200 cf98 90d8 a102 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n70      LD (HL),B\n    0 MC 0000\n    4 MR 0000 70\n    4 MC a169\n    7 MW a169 cf\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 7\na169 cf -1\n\n71      LD (HL),C\n    0 MC 0000\n    4 MR 0000 71\n    4 MC a169\n    7 MW a169 98\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 7\na169 98 -1\n\n72      LD (HL),D\n    0 MC 0000\n    4 MR 0000 72\n    4 MC a169\n    7 MW a169 90\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 7\na169 90 -1\n\n73      LD (HL),E\n    0 MC 0000\n    4 MR 0000 73\n    4 MC a169\n    7 MW a169 d8\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 7\na169 d8 -1\n\n74      LD (HL),H\n    0 MC 0000\n    4 MR 0000 74\n    4 MC a169\n    7 MW a169 a1\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 7\na169 a1 -1\n\n75      LD (HL),L\n    0 MC 0000\n    4 MR 0000 75\n    4 MC a169\n    7 MW a169 69\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 7\na169 69 -1\n\n76      HALT\n    0 MC 0000\n    4 MR 0000 76\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 1 4\n\n77      LD (HL),A\n    0 MC 0000\n    4 MR 0000 77\n    4 MC a169\n    7 MW a169 02\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 7\na169 02 -1\n\n78      LD A,B\n    0 MC 0000\n    4 MR 0000 78\ncf00 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n79      LD A,C\n    0 MC 0000\n    4 MR 0000 79\n9800 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n7a      LD A,D\n    0 MC 0000\n    4 MR 0000 7a\n9000 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n7b      LD A,E\n    0 MC 0000\n    4 MR 0000 7b\nd800 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n7c      LD A,H\n    0 MC 0000\n    4 MR 0000 7c\na100 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n7d      LD A,L\n    0 MC 0000\n    4 MR 0000 7d\n6900 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n7e      LD A,(HL)\n    0 MC 0000\n    4 MR 0000 7e\n    4 MC a169\n    7 MR a169 50\n5000 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 7\n\n7f      LD A,A\n    0 MC 0000\n    4 MR 0000 7f\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n80      ADD A,B\n    0 MC 0000\n    4 MR 0000 80\n0411 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n81      ADD A,C\n    0 MC 0000\n    4 MR 0000 81\n3031 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n82      ADD A,D\n    0 MC 0000\n    4 MR 0000 82\n1501 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n83      ADD A,E\n    0 MC 0000\n    4 MR 0000 83\n0211 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n84      ADD A,H\n    0 MC 0000\n    4 MR 0000 84\nd191 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n85      ADD A,L\n    0 MC 0000\n    4 MR 0000 85\n9b89 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n86      ADD A,(HL)\n    0 MC 0000\n    4 MR 0000 86\n    4 MC dca6\n    7 MR dca6 49\n3e29 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 7\n\n87      ADD A,A\n    0 MC 0000\n    4 MR 0000 87\neaa9 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n88      ADC A,B\n    0 MC 0000\n    4 MR 0000 88\n0411 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n89      ADC A,C\n    0 MC 0000\n    4 MR 0000 89\n3031 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n8a      ADC A,D\n    0 MC 0000\n    4 MR 0000 8a\n1501 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n8b      ADC A,E\n    0 MC 0000\n    4 MR 0000 8b\n0211 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n8c      ADC A,H\n    0 MC 0000\n    4 MR 0000 8c\nd191 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n8d      ADC A,L\n    0 MC 0000\n    4 MR 0000 8d\n9b89 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n8e      ADC A,(HL)\n    0 MC 0000\n    4 MR 0000 8e\n    4 MC dca6\n    7 MR dca6 49\n3e29 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 7\n\n8f      ADC A,A\n    0 MC 0000\n    4 MR 0000 8f\neaa9 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n90      SUB B\n    0 MC 0000\n    4 MR 0000 90\ne6b2 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n91      SUB C\n    0 MC 0000\n    4 MR 0000 91\nbaba 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n92      SUB D\n    0 MC 0000\n    4 MR 0000 92\nd582 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n93      SUB E\n    0 MC 0000\n    4 MR 0000 93\ne8ba 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n94      SUB H\n    0 MC 0000\n    4 MR 0000 94\n191a 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n95      SUB L\n    0 MC 0000\n    4 MR 0000 95\n4f1a 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n96      SUB (HL)\n    0 MC 0000\n    4 MR 0000 96\n    4 MC dca6\n    7 MR dca6 49\nacba 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 7\n\n97      SUB A\n    0 MC 0000\n    4 MR 0000 97\n0042 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n98      SBC A,B\n    0 MC 0000\n    4 MR 0000 98\ne6b2 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n99      SBC A,C\n    0 MC 0000\n    4 MR 0000 99\nbaba 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n9a      SBC A,D\n    0 MC 0000\n    4 MR 0000 9a\nd582 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n9b      SBC A,E\n    0 MC 0000\n    4 MR 0000 9b\ne8ba 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n9c      SBC A,H\n    0 MC 0000\n    4 MR 0000 9c\n191a 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n9d      SBC A,L\n    0 MC 0000\n    4 MR 0000 9d\n4f1a 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n9e      SBC A,(HL)\n    0 MC 0000\n    4 MR 0000 9e\n    4 MC dca6\n    7 MR dca6 49\nacba 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 7\n\n9f      SBC A,A\n    0 MC 0000\n    4 MR 0000 9f\n0042 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\na0      AND B\n    0 MC 0000\n    4 MR 0000 a0\n0514 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\na1      AND C\n    0 MC 0000\n    4 MR 0000 a1\n3130 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\na2      AND D\n    0 MC 0000\n    4 MR 0000 a2\n2030 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\na3      AND E\n    0 MC 0000\n    4 MR 0000 a3\n0514 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\na4      AND H\n    0 MC 0000\n    4 MR 0000 a4\nd494 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\na5      AND L\n    0 MC 0000\n    4 MR 0000 a5\na4b0 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\na6      AND (HL)\n    0 MC 0000\n    4 MR 0000 a6\n    4 MC dca6\n    7 MR dca6 49\n4114 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 7\n\na7      AND A\n    0 MC 0000\n    4 MR 0000 a7\nf5b4 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\na8      XOR B\n    0 MC 0000\n    4 MR 0000 a8\nfaac 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\na9      XOR C\n    0 MC 0000\n    4 MR 0000 a9\nce88 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\naa      XOR D\n    0 MC 0000\n    4 MR 0000 aa\nd580 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\nab      XOR E\n    0 MC 0000\n    4 MR 0000 ab\nf8a8 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\nac      XOR H\n    0 MC 0000\n    4 MR 0000 ac\n2928 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\nad      XOR L\n    0 MC 0000\n    4 MR 0000 ad\n5304 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\nae      XOR (HL)\n    0 MC 0000\n    4 MR 0000 ae\n    4 MC dca6\n    7 MR dca6 49\nbca8 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 7\n\naf      XOR A\n    0 MC 0000\n    4 MR 0000 af\n0044 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\nb0      OR B\n    0 MC 0000\n    4 MR 0000 b0\nffac 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\nb1      OR C\n    0 MC 0000\n    4 MR 0000 b1\nffac 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\nb2      OR D\n    0 MC 0000\n    4 MR 0000 b2\nf5a4 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\nb3      OR E\n    0 MC 0000\n    4 MR 0000 b3\nfda8 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\nb4      OR H\n    0 MC 0000\n    4 MR 0000 b4\nfda8 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\nb5      OR L\n    0 MC 0000\n    4 MR 0000 b5\nf7a0 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\nb6      OR (HL)\n    0 MC 0000\n    4 MR 0000 b6\n    4 MC dca6\n    7 MR dca6 49\nfda8 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 7\n\nb7      OR A\n    0 MC 0000\n    4 MR 0000 b7\nf5a4 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\nb8      CP B\n    0 MC 0000\n    4 MR 0000 b8\nf59a 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\nb9      CP C\n    0 MC 0000\n    4 MR 0000 b9\nf5ba 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\nba      CP D\n    0 MC 0000\n    4 MR 0000 ba\nf5a2 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\nbb      CP E\n    0 MC 0000\n    4 MR 0000 bb\nf59a 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\nbc      CP H\n    0 MC 0000\n    4 MR 0000 bc\nf51a 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\nbd      CP L\n    0 MC 0000\n    4 MR 0000 bd\nf532 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\nbe      CP (HL)\n    0 MC 0000\n    4 MR 0000 be\n    4 MC dca6\n    7 MR dca6 49\nf59a 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 7\n\nbf      CP A\n    0 MC 0000\n    4 MR 0000 bf\nf562 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\nc0_1    RET NZ\n    0 MC 0000\n    4 MR 0000 c0\n    4 MC 0001\n    5 MC 43f7\n    8 MR 43f7 e9\n    8 MC 43f8\n   11 MR 43f8 af\n0098 0000 0000 0000 0000 0000 0000 0000 0000 0000 43f9 afe9\n00 01 0 0 0 0 11\n\nc0_2    RET NZ\n    0 MC 0000\n    4 MR 0000 c0\n    4 MC 0001\n00d8 0000 0000 0000 0000 0000 0000 0000 0000 0000 43f7 0001\n00 01 0 0 0 0 5\n\nc1      POP BC\n    0 MC 0000\n    4 MR 0000 c1\n    4 MC 4143\n    7 MR 4143 ce\n    7 MC 4144\n   10 MR 4144 e8\n0000 e8ce 0000 0000 0000 0000 0000 0000 0000 0000 4145 0001\n00 01 0 0 0 0 10\n\nc2_1    JP NZ,nn\n    0 MC 0000\n    4 MR 0000 c2\n    4 MC 0001\n    7 MR 0001 1b\n    7 MC 0002\n   10 MR 0002 e1\n0087 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 e11b\n00 01 0 0 0 0 10\n\nc2_2    JP NZ,nn\n    0 MC 0000\n    4 MR 0000 c2\n    4 MC 0001\n    7 MC 0002\n00c7 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0003\n00 01 0 0 0 0 10\n\nc3      JP nn\n    0 MC 0000\n    4 MR 0000 c3\n    4 MC 0001\n    7 MR 0001 ed\n    7 MC 0002\n   10 MR 0002 7c\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 7ced\n00 01 0 0 0 0 10\n\nc4_1    CALL NZ,nn\n    0 MC 0000\n    4 MR 0000 c4\n    4 MC 0001\n    7 MR 0001 61\n    7 MC 0002\n   10 MR 0002 9c\n   10 MC 0002\n   11 MC 5697\n   14 MW 5697 00\n   14 MC 5696\n   17 MW 5696 03\n000e 0000 0000 0000 0000 0000 0000 0000 0000 0000 5696 9c61\n00 01 0 0 0 0 17\n5696 03 00 -1\n\nc4_2    CALL NZ,nn\n    0 MC 0000\n    4 MR 0000 c4\n    4 MC 0001\n    7 MC 0002\n004e 0000 0000 0000 0000 0000 0000 0000 0000 0000 5698 0003\n00 01 0 0 0 0 10\n\nc5      PUSH BC\n    0 MC 0000\n    4 MR 0000 c5\n    4 MC 0001\n    5 MC ec11\n    8 MW ec11 14\n    8 MC ec10\n   11 MW ec10 59\n53e3 1459 775f 1a2f 0000 0000 0000 0000 0000 0000 ec10 0001\n00 01 0 0 0 0 11\nec10 59 14 -1\n\nc6      ADD A,n\n    0 MC 0000\n    4 MR 0000 c6\n    4 MC 0001\n    7 MR 0001 6f\n3939 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0002\n00 01 0 0 0 0 7\n\nc7      RST 0H\n    0 MC 6d33\n    4 MR 6d33 c7\n    4 MC 0001\n    5 MC 5506\n    8 MW 5506 6d\n    8 MC 5505\n   11 MW 5505 34\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 5505 0000\n00 01 0 0 0 0 11\n5505 34 6d -1\n\nc8_1    RET Z\n    0 MC 0000\n    4 MR 0000 c8\n    4 MC 0001\n0098 0000 0000 0000 0000 0000 0000 0000 0000 0000 43f7 0001\n00 01 0 0 0 0 5\n\nc8_2    RET Z\n    0 MC 0000\n    4 MR 0000 c8\n    4 MC 0001\n    5 MC 43f7\n    8 MR 43f7 e9\n    8 MC 43f8\n   11 MR 43f8 af\n00d8 0000 0000 0000 0000 0000 0000 0000 0000 0000 43f9 afe9\n00 01 0 0 0 0 11\n\nc9      RET\n    0 MC 0000\n    4 MR 0000 c9\n    4 MC 887e\n    7 MR 887e 36\n    7 MC 887f\n   10 MR 887f 11\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 8880 1136\n00 01 0 0 0 0 10\n\nca_1    JP Z,nn\n    0 MC 0000\n    4 MR 0000 ca\n    4 MC 0001\n    7 MC 0002\n0087 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0003\n00 01 0 0 0 0 10\n\nca_2    JP Z,nn\n    0 MC 0000\n    4 MR 0000 ca\n    4 MC 0001\n    7 MR 0001 1b\n    7 MC 0002\n   10 MR 0002 e1\n00c7 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 e11b\n00 01 0 0 0 0 10\n\ncb00    RLC B\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 00\nda8d c979 552e a806 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb01    RLC C\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 01\n10a0 b3f2 b480 ef65 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb02    RLC D\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 02\n2e09 9adf 5d6e a7f2 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb03    RLC E\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 03\n682c 9995 de7e ca71 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb04    RLC H\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 04\n8c88 beea 0ce4 ceb0 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb05    RLC L\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 05\n3620 e19f 78c9 cb64 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb06    RLC (HL)\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 06\n    8 MC 5b04\n   11 MR 5b04 d4\n   11 MC 5b04\n   12 MC 5b04\n   15 MW 5b04 a9\n8aad db02 8fb1 5b04 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 15\n5b04 a9 -1\n\ncb07    RLC A\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 07\nda88 19cf 7259 dcaa 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb08    RRC B\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 08\n80a1 e6b5 818e 2ee2 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb09    RRC C\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 09\n182c 122e dd97 59c6 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb0a    RRC D\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 0a\n12ad 3ba1 bb24 63ad 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb0b    RRC E\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 0b\n7600 2abf b613 0289 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb0c    RRC H\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 0c\n0e08 6fc5 2f12 1ad9 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb0d    RRC L\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 0d\n630c 95a3 fcd2 514d 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb0e    RRC (HL)\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 0e\n    8 MC 543e\n   11 MR 543e d2\n   11 MC 543e\n   12 MC 543e\n   15 MW 543e 69\nfc2c adf9 4925 543e 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 15\n543e 69 -1\n\ncb0f    RRC A\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 0f\ne1a5 18f3 41b8 070b 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb10    RL B\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 10\nf8ad b825 33b3 0d74 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb11    RL C\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 11\n65ac e2b8 4b8a ed42 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb12    RL D\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 12\n770c 1384 1e50 29c6 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb13    RL E\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 13\nce04 9f17 e150 3ed7 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb14    RL H\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 14\nb2a8 541a 60c7 f89a 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb15    RL L\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 15\n2d81 c1df 6eab 03c4 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb16    RL (HL)\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 16\n    8 MC 684e\n   11 MR 684e c3\n   11 MC 684e\n   12 MC 684e\n   15 MW 684e 86\n3681 3b53 1a4a 684e 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 15\n684e 86 -1\n\ncb17    RL A\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 17\na8a8 d090 f60d 0fa2 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb18    RR B\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 18\n8624 6358 755f 9596 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb19    RR C\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 19\n960d be59 7c22 71c8 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb1a    RR D\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 1a\n3928 882f 2a3b 5279 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb1b    RR E\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 1b\n9e24 b338 8736 e8b4 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb1c    RR H\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 1c\n4b0d b555 238f 181d 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb1d    RR L\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 1d\n212d 3d7e 5e39 e428 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb1e    RR (HL)\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 1e\n    8 MC 00ef\n   11 MR 00ef 91\n   11 MC 00ef\n   12 MC 00ef\n   15 MW 00ef 48\n5e0d 66b9 80dc 00ef 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 15\n00ef 48 -1\n\ncb1f    RR A\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 1f\n7621 b838 8e18 ace7 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb20    SLA B\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 20\nc708 0897 d72b ccb6 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb21    SLA C\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 21\n22ad 5ce8 938e 37a8 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb22    SLA D\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 22\n8589 0950 cee8 0641 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb23    SLA E\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 23\n21a5 2a7c 37a0 aa59 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb24    SLA H\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 24\nfb09 b9de 7014 08b6 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb25    SLA L\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 25\n152d 6bbc 894e 8578 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb26    SLA (HL)\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 26\n    8 MC 283a\n   11 MR 283a ee\n   11 MC 283a\n   12 MC 283a\n   15 MW 283a dc\n0a89 372e e315 283a 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 15\n283a dc -1\n\ncb27    SLA A\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 27\n7e2d bdba 67ab 5ea2 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb28    SRA B\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 28\nc000 0235 3e0f 021b 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb29    SRA C\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 29\n0624 f121 6ada c306 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb2a    SRA D\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 2a\n302d ec3a 3f7d 3473 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb2b    SRA E\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 2b\ne0ac ccf0 bbed b78a 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb2c    SRA H\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 2c\n5b0c 25c0 996d 0f7b 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb2d    SRA L\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 2d\n5ea4 c51b 58e3 78f5 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb2e    SRA (HL)\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 2e\n    8 MC 24bf\n   11 MR 24bf b5\n   11 MC 24bf\n   12 MC 24bf\n   15 MW 24bf da\n3989 a2cd 0629 24bf 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 15\n24bf da -1\n\ncb2f    SRA A\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 2f\nd580 a194 d0e3 5c65 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb30    SLL B*\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 30\ncda4 f581 d67b 656b 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb31    SLL C*\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 31\n28a5 e7f5 6d8c 75a4 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb32    SLL D*\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 32\n13ad 3f36 ed08 5e56 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb33    SLL E*\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 33\nd588 9720 7689 038f 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb34    SLL H*\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 34\n12a1 77f6 0206 f738 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb35    SLL L*\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 35\n3c84 fd68 ea91 78c3 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb36    SLL (HL)*\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 36\n    8 MC 6d38\n   11 MR 6d38 f1\n   11 MC 6d38\n   12 MC 6d38\n   15 MW 6d38 e3\n8aa1 1185 1dde 6d38 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 15\n6d38 e3 -1\n\ncb37    SLL A*\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 37\n8784 d7bc 9133 6e56 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb38    SRL B\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 38\ndf28 3e1b 9f9f 4ff2 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb39    SRL C\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 39\n6600 b701 14f5 3c17 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb3a    SRL D\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 3a\nd124 5c5f 722e f1b1 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb3b    SRL E\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 3b\nb224 38c8 a530 7419 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb3c    SRL H\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 3c\n7800 cfae 66d8 15d8 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb3d    SRL L\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 3d\ne625 dcda 06aa 4666 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb3e    SRL (HL)\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 3e\n    8 MC a96c\n   11 MR a96c a0\n   11 MC a96c\n   12 MC a96c\n   15 MW a96c 50\na904 6a34 e8d0 a96c 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 15\na96c 50 -1\n\ncb3f    SRL A\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 3f\n782d ceea 721e 77f0 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb40    BIT 0,B\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 40\n9e7c bcb2 efaa 505f 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb41    BIT 0,C\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 41\n9e10 1b43 954e 7be9 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb42    BIT 0,D\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 42\nf238 dd12 7d4f 551f 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb43    BIT 0,E\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 43\nad54 c3b3 f1d0 bab4 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb44    BIT 0,H\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 44\nb718 c829 27e3 5b92 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb45    BIT 0,L\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 45\n7718 68ee 0c77 409b 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb46    BIT 0,(HL)\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 46\n    8 MC 6131\n   11 MR 6131 d5\n   11 MC 6131\n7210 7ae3 a11e 6131 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 12\n\ncb47_1  BIT 0,A\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 47\nff38 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb47    BIT 0,A\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 47\n1054 d8ca e2c4 8a8c 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb48    BIT 1,B\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 48\na930 6264 e833 6de0 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb49    BIT 1,C\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 49\n6c30 d0f7 1db7 a040 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb4a    BIT 1,D\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 4a\n4f18 f04c 5b29 77a4 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb4b    BIT 1,E\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 4b\n5518 9848 095f 40ca 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb4c    BIT 1,H\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 4c\n887c 0521 bf31 6d5d 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb4d    BIT 1,L\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 4d\nf95c 27d0 0f7e 158d 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb4e    BIT 1,(HL)\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 4e\n    8 MC ada3\n   11 MR ada3 5b\n   11 MC ada3\n2610 9207 459a ada3 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 12\n\ncb4f_1  BIT 1,A\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 4f\nff38 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb4f    BIT 1,A\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 4f\n1710 2dc1 aca2 0bcc 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb50    BIT 2,B\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 50\n2330 2749 1012 84d2 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb51    BIT 2,C\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 51\n225c b7db e19d aafc 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb52    BIT 2,D\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 52\n8b74 ff7a b0ff ac44 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb53    BIT 2,E\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 53\n6030 31a1 a4f4 7c75 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb54    BIT 2,H\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 54\n385c 7ccc 89cc 1999 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb55    BIT 2,L\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 55\nf95c 1f79 19cd fb4b 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb56    BIT 2,(HL)\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 56\n    8 MC bbf9\n   11 MR bbf9 10\n   11 MC bbf9\n1554 2bfe e3b5 bbf9 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 12\n\ncb57_1  BIT 2,A\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 57\nff38 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb57    BIT 2,A\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 57\n6630 af32 532a da50 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb58    BIT 3,B\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 58\n5018 1aee 2e47 1479 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb59    BIT 3,C\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 59\n7238 5e68 ff28 2075 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb5a    BIT 3,D\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 5a\neb54 fea7 17d1 d99b 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb5b    BIT 3,E\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 5b\n6b74 6f2c 3fe3 1691 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb5c    BIT 3,H\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 5c\n3354 a7e7 2077 13e9 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb5d    BIT 3,L\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 5d\nc118 afcc c8b1 ee49 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb5e    BIT 3,(HL)\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 5e\n    8 MC 349a\n   11 MR 349a 3c\n   11 MC 349a\n3010 ad43 16c1 349a 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 12\n\ncb5f_1  BIT 3,A\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 5f\nff38 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb5f    BIT 3,A\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 5f\n8c18 1b67 2314 6133 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb60    BIT 4,B\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 60\n9930 34b5 0fd8 5273 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb61    BIT 4,C\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 61\nd118 219f 3bb4 7c44 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb62    BIT 4,D\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 62\naf54 bdf8 c536 8cc5 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb63    BIT 4,E\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 63\n2a74 5e16 f627 84ca 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb64    BIT 4,H\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 64\na97c a365 c00b ea94 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb65    BIT 4,L\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 65\n1838 8d58 4256 427a 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb66    BIT 4,(HL)\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 66\n    8 MC a44f\n   11 MR a44f d2\n   11 MC a44f\n4c10 3ef7 e544 a44f 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 12\n\ncb67_1  BIT 4,A\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 67\nff38 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb67    BIT 4,A\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 67\n8654 5e92 2986 394d 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb68    BIT 5,B\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 68\nd75c 0f6a 18a6 ddd2 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb69    BIT 5,C\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 69\nda5c 691b 7c79 1dba 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb6a    BIT 5,D\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 6a\n2254 13e8 86d4 4e09 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb6b    BIT 5,E\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 6b\naf30 5123 7635 1ca9 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb6c    BIT 5,H\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 6c\n4354 faa6 abc2 5605 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb6d    BIT 5,L\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 6d\n7f38 f099 d435 d9ad 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb6e    BIT 5,(HL)\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 6e\n    8 MC d8ba\n   11 MR d8ba 31\n   11 MC d8ba\n4a10 08c9 8177 d8ba 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 12\n\ncb6f_1  BIT 5,A\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 6f\nff38 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb6f    BIT 5,A\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 6f\na130 8c80 4678 4d34 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb70    BIT 6,B\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 70\n1954 958a 5dab f913 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb71    BIT 6,C\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 71\n3d18 095e d6df 42fe 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb72    BIT 6,D\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 72\na518 c0bf 4c8d ad11 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb73    BIT 6,E\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 73\nf238 49a6 b279 2ecc 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb74    BIT 6,H\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 74\n055c 445e 05e9 983d 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb75    BIT 6,L\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 75\n6b5c 83c6 635a d18d 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb76    BIT 6,(HL)\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 76\n    8 MC bc71\n   11 MR bc71 18\n   11 MC bc71\nf854 3057 3629 bc71 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 12\n\ncb77_1  BIT 6,A\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 77\nff38 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb77    BIT 6,A\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 77\n9254 d6f8 5100 736d 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb78    BIT 7,B\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 78\n725c 1cf8 8d2b c76a 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb79    BIT 7,C\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 79\na898 809e 1124 39e8 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb7a    BIT 7,D\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 7a\n5874 7d24 63e1 d9af 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb7b    BIT 7,E\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 7b\n03b8 50ab 05bd 6bd0 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb7c    BIT 7,H\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 7c\nad54 f77b 55ae 063b 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb7d    BIT 7,L\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 7d\n8298 b792 38cb 5f9b 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb7e    BIT 7,(HL)\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 7e\n    8 MC a25e\n   11 MR a25e d7\n   11 MC a25e\n4290 3b91 f59c a25e 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 12\n\ncb7f_1  BIT 7,A\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 7f\nffb8 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb7f    BIT 7,A\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 7f\n6a7c 84ec cf4e 185b 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb80    RES 0,B\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 80\n8f00 702f 17bd a706 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb81    RES 0,C\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 81\nae00 947e 7153 6616 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb82    RES 0,D\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 82\n8100 bed2 c619 4572 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb83    RES 0,E\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 83\ne600 63a2 ccf6 ae9a 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb84    RES 0,H\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 84\nce00 e0cc d305 d6c0 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb85    RES 0,L\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 85\nf300 ed79 9db7 dda0 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb86    RES 0,(HL)\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 86\n    8 MC 1b48\n   11 MR 1b48 62\n   11 MC 1b48\n   12 MC 1b48\n   15 MW 1b48 62\n2a00 b0b9 9426 1b48 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 15\n\ncb87    RES 0,A\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 87\n1000 86dc 1798 dfc5 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb88    RES 1,B\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 88\ne300 8821 e33e 674d 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb89    RES 1,C\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 89\n6000 d184 c5b6 1bd7 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb8a    RES 1,D\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 8a\n3e00 5fcd 0938 b98e 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb8b    RES 1,E\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 8b\n6500 040e 103d 4a07 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb8c    RES 1,H\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 8c\nf800 6d27 9bdf d8ef 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb8d    RES 1,L\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 8d\n3e00 5469 2c28 bd70 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb8e    RES 1,(HL)\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 8e\n    8 MC 63a7\n   11 MR 63a7 d4\n   11 MC 63a7\n   12 MC 63a7\n   15 MW 63a7 d4\n1f00 140b b492 63a7 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 15\n\ncb8f    RES 1,A\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 8f\n2500 c522 ca46 1c1a 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb90    RES 2,B\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 90\n5700 595c 4f0a c73c 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb91    RES 2,C\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 91\n5e00 8f22 a735 97e0 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb92    RES 2,D\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 92\n3300 7d9f 83d0 83d0 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb93    RES 2,E\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 93\nc200 4e05 b3f8 2234 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb94    RES 2,H\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 94\nee00 8f4b 2831 d2a6 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb95    RES 2,L\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 95\n3c00 6af2 b25d 36fb 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb96    RES 2,(HL)\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 96\n    8 MC 3324\n   11 MR 3324 21\n   11 MC 3324\n   12 MC 3324\n   15 MW 3324 21\n7600 b027 d0a5 3324 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 15\n\ncb97    RES 2,A\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 97\n1200 ad09 7902 97bc 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb98    RES 3,B\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 98\n3400 b61c 771d 5d5e 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb99    RES 3,C\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 99\n5100 65b6 1359 8bec 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb9a    RES 3,D\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 9a\n6400 976d 4425 dcb2 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb9b    RES 3,E\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 9b\na100 b58a d264 2bd6 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb9c    RES 3,H\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 9c\nd800 63d6 ac7b c7a0 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb9d    RES 3,L\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 9d\n0d00 d840 0810 0800 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncb9e    RES 3,(HL)\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 9e\n    8 MC 3a65\n   11 MR 3a65 2a\n   11 MC 3a65\n   12 MC 3a65\n   15 MW 3a65 22\n3b00 ebbf 9434 3a65 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 15\n3a65 22 -1\n\ncb9f    RES 3,A\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 9f\nb200 d1de f991 72f6 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncba0    RES 4,B\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 a0\nfa00 c669 71e1 c80d 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncba1    RES 4,C\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 a1\n8200 75e4 a0de d0ba 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncba2    RES 4,D\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 a2\ndd00 2b0d 4554 6fc0 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncba3    RES 4,E\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 a3\n2200 2f0d 4d2c 6666 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncba4    RES 4,H\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 a4\nd600 d8ed 9cd4 8bb1 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncba5    RES 4,L\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 a5\nb400 b393 3e42 88ca 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncba6    RES 4,(HL)\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 a6\n    8 MC e70d\n   11 MR e70d 27\n   11 MC e70d\n   12 MC e70d\n   15 MW e70d 27\n0a00 4c34 f5a7 e70d 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 15\n\ncba7    RES 4,A\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 a7\n4500 af61 569a c77b 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncba8    RES 5,B\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 a8\n6400 d269 bae4 c9e7 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncba9    RES 5,C\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 a9\ne400 7ad4 bf0a ce0b 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbaa    RES 5,D\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 aa\ncd00 d249 4159 fed5 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbab    RES 5,E\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 ab\nac00 939a 5d9b 0812 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbac    RES 5,H\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 ac\n2400 8a7d 2cac dfaa 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbad    RES 5,L\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 ad\n6f00 5ffb 2360 ae15 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbae    RES 5,(HL)\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 ae\n    8 MC 190e\n   11 MR 190e 66\n   11 MC 190e\n   12 MC 190e\n   15 MW 190e 46\n5a00 aa17 12f3 190e 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 15\n190e 46 -1\n\ncbaf    RES 5,A\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 af\ndc00 bb3f 8bb6 5877 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbb0    RES 6,B\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 b0\nb900 3a79 1aaa c3ba 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbb1    RES 6,C\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 b1\n4900 63a4 a544 1190 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbb2    RES 6,D\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 b2\n4d00 2b03 2b23 6ff5 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbb3    RES 6,E\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 b3\n8700 857a e98b 5cb1 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbb4    RES 6,H\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 b4\n2b00 b73e 79c9 a1bb 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbb5    RES 6,L\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 b5\n9b00 d879 2ec9 4bba 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbb6    RES 6,(HL)\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 b6\n    8 MC 4fab\n   11 MR 4fab a5\n   11 MC 4fab\n   12 MC 4fab\n   15 MW 4fab a5\n8600 89bf de4a 4fab 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 15\n\ncbb7    RES 6,A\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 b7\n2200 fb8a 3d6e d4a2 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbb8    RES 7,B\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 b8\nd000 37c6 225a d249 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbb9    RES 7,C\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 b9\na500 1b4a d584 5dee 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbba    RES 7,D\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 ba\n6300 a5fe 742b 34c9 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbbb    RES 7,E\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 bb\n1200 f661 aa4f cb30 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbbc    RES 7,H\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 bc\n9800 adc3 0b29 7b6e 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbbd    RES 7,L\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 bd\nd600 a6e1 8813 1038 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbbe    RES 7,(HL)\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 be\n    8 MC 77d5\n   11 MR 77d5 ea\n   11 MC 77d5\n   12 MC 77d5\n   15 MW 77d5 6a\nca00 ff64 1218 77d5 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 15\n77d5 6a -1\n\ncbbf    RES 7,A\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 bf\n6800 4845 690a 15de 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbc0    SET 0,B\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 c0\ne300 ef71 bffb b3a1 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbc1    SET 0,C\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 c1\n3200 32a1 59ab 3343 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbc2    SET 0,D\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 c2\nc700 b159 c123 e1f3 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbc3    SET 0,E\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 c3\n0400 b463 c211 8f3a 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbc4    SET 0,H\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 c4\n7e00 545a 6ecf 5976 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbc5    SET 0,L\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 c5\n4000 c617 079c 4107 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbc6    SET 0,(HL)\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 c6\n    8 MC f0be\n   11 MR f0be 9c\n   11 MC f0be\n   12 MC f0be\n   15 MW f0be 9d\nb800 0373 b807 f0be 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 15\nf0be 9d -1\n\ncbc7    SET 0,A\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 c7\n7700 3681 9b55 583f 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbc8    SET 1,B\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 c8\n7d00 a772 8682 7cf3 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbc9    SET 1,C\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 c9\n0b00 67ee 30e0 72db 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbca    SET 1,D\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 ca\n9c00 9517 cfbb fbc7 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbcb    SET 1,E\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 cb\ne800 0f3d 336f f70d 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbcc    SET 1,H\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 cc\nfb00 7981 0bbb 1afd 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbcd    SET 1,L\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 cd\n5500 5e78 bf34 2602 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbce    SET 1,(HL)\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 ce\n    8 MC 8ec6\n   11 MR 8ec6 bf\n   11 MC 8ec6\n   12 MC 8ec6\n   15 MW 8ec6 bf\nd500 a111 cb2a 8ec6 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 15\n\ncbcf    SET 1,A\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 cf\na200 6baf 98b2 98a0 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbd0    SET 2,B\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 d0\n2300 7fcb 02e7 1724 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbd1    SET 2,C\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 d1\n5300 581f b775 47f4 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbd2    SET 2,D\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 d2\n6900 c147 b79c 7528 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbd3    SET 2,E\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 d3\nae00 bbc4 ce56 5fba 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbd4    SET 2,H\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 d4\nd800 6e1e af6f bf2e 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbd5    SET 2,L\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 d5\n8400 a19a d2fd 8a77 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbd6    SET 2,(HL)\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 d6\n    8 MC 6029\n   11 MR 6029 b7\n   11 MC 6029\n   12 MC 6029\n   15 MW 6029 b7\na900 f5f3 2180 6029 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 15\n\ncbd7    SET 2,A\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 d7\nb500 c008 8425 290a 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbd8    SET 3,B\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 d8\n8b00 09c4 ddf3 6d7e 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbd9    SET 3,C\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 d9\n3e00 3e3e 30ec efc6 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbda    SET 3,D\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 da\nd000 3e8f 28fe 1c87 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbdb    SET 3,E\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 db\n1200 977a 8c49 bc48 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbdc    SET 3,H\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 dc\n8d00 05de f8d3 b925 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbdd    SET 3,L\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 dd\nc300 08a9 2bc8 5b9f 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbde    SET 3,(HL)\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 de\n    8 MC ba03\n   11 MR ba03 93\n   11 MC ba03\n   12 MC ba03\n   15 MW ba03 9b\n1900 900f d572 ba03 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 15\nba03 9b -1\n\ncbdf    SET 3,A\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 df\n6f00 2745 7e3d 0fa1 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbe0    SET 4,B\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 e0\n3e00 d633 9897 3744 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbe1    SET 4,C\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 e1\n7d00 50b6 0136 5334 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbe2    SET 4,D\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 e2\nd400 6b45 b192 3a4c 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbe3    SET 4,E\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 e3\n3b00 d29c 05f0 2e78 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbe4    SET 4,H\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 e4\n1e00 7d5e 846d 1978 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbe5    SET 4,L\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 e5\nca00 df0d d588 b49f 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbe6    SET 4,(HL)\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 e6\n    8 MC 9f9b\n   11 MR 9f9b f6\n   11 MC 9f9b\n   12 MC 9f9b\n   15 MW 9f9b f6\nb300 52c2 dbfe 9f9b 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 15\n\ncbe7    SET 4,A\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 e7\n9e00 cf02 67ef f2e0 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbe8    SET 5,B\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 e8\n7100 bb18 66ec 4a05 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbe9    SET 5,C\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 e9\n5700 28b7 8f2f a4d0 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbea    SET 5,D\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 ea\nec00 304a 60a1 f32a 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbeb    SET 5,E\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 eb\nf000 532b a1be 1a1a 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbec    SET 5,H\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 ec\nf200 f0f3 a816 ba08 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbed    SET 5,L\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 ed\n1300 5127 adab 2dec 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbee    SET 5,(HL)\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 ee\n    8 MC e90d\n   11 MR e90d f1\n   11 MC e90d\n   12 MC e90d\n   15 MW e90d f1\n9000 b273 50ae e90d 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 15\n\ncbef    SET 5,A\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 ef\n2500 4281 f0d4 2c39 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbf0    SET 6,B\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 f0\nfb00 5802 0c27 6ff5 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbf1    SET 6,C\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 f1\n5500 a143 3ff5 5e1c 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbf2    SET 6,D\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 f2\nf000 625a ef82 9819 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbf3    SET 6,E\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 f3\n8600 d7bd 5dc6 263f 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbf4    SET 6,H\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 f4\n9400 0243 9ec1 75d9 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbf5    SET 6,L\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 f5\nce00 2d42 5e6a 47e6 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbf6    SET 6,(HL)\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 f6\n    8 MC a9bc\n   11 MR a9bc b1\n   11 MC a9bc\n   12 MC a9bc\n   15 MW a9bc f1\n7b00 c2d7 4492 a9bc 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 15\na9bc f1 -1\n\ncbf7    SET 6,A\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 f7\n6d00 abaf 5b5d 188c 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbf8    SET 7,B\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 f8\nc600 b812 a037 d2b0 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbf9    SET 7,C\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 f9\nef00 c5f2 77a8 0730 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbfa    SET 7,D\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 fa\n8700 1581 e3e3 ed03 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbfb    SET 7,E\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 fb\na300 7d27 97c3 d1ae 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbfc    SET 7,H\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 fc\nec00 060a 3ef6 d00f 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbfd    SET 7,L\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 fd\n1100 231a 8563 28c5 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncbfe    SET 7,(HL)\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 fe\n    8 MC 3a24\n   11 MR 3a24 c3\n   11 MC 3a24\n   12 MC 3a24\n   15 MW 3a24 c3\n5300 4948 89dd 3a24 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 15\n\ncbff    SET 7,A\n    0 MC 0000\n    4 MR 0000 cb\n    4 MC 0001\n    8 MR 0001 ff\nf900 799b 6cf7 e3f2 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 8\n\ncc_1    CALL Z,nn\n    0 MC 0000\n    4 MR 0000 cc\n    4 MC 0001\n    7 MR 0001 61\n    7 MC 0002\n   10 MR 0002 9c\n   10 MC 0002\n   11 MC 5697\n   14 MW 5697 00\n   14 MC 5696\n   17 MW 5696 03\n004e 0000 0000 0000 0000 0000 0000 0000 0000 0000 5696 9c61\n00 01 0 0 0 0 17\n5696 03 00 -1\n\ncc_2    CALL Z,nn\n    0 MC 0000\n    4 MR 0000 cc\n    4 MC 0001\n    7 MC 0002\n000e 0000 0000 0000 0000 0000 0000 0000 0000 0000 5698 0003\n00 01 0 0 0 0 10\n\ncd      CALL nn\n    0 MC 0000\n    4 MR 0000 cd\n    4 MC 0001\n    7 MR 0001 5d\n    7 MC 0002\n   10 MR 0002 3a\n   10 MC 0002\n   11 MC b07c\n   14 MW b07c 00\n   14 MC b07b\n   17 MW b07b 03\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 b07b 3a5d\n00 01 0 0 0 0 17\nb07b 03 00 -1\n\nce      ADC A,n\n    0 MC 0000\n    4 MR 0000 ce\n    4 MC 0001\n    7 MR 0001 b2\n1301 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0002\n00 01 0 0 0 0 7\n\ncf      RST 8H\n    0 MC 6d33\n    4 MR 6d33 cf\n    4 MC 0001\n    5 MC 5506\n    8 MW 5506 6d\n    8 MC 5505\n   11 MW 5505 34\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 5505 0008\n00 01 0 0 0 0 11\n5505 34 6d -1\n\nd0_1    RET NC\n    0 MC 0000\n    4 MR 0000 d0\n    4 MC 0001\n    5 MC 43f7\n    8 MR 43f7 e9\n    8 MC 43f8\n   11 MR 43f8 af\n0098 0000 0000 0000 0000 0000 0000 0000 0000 0000 43f9 afe9\n00 01 0 0 0 0 11\n\nd0_2    RET NC\n    0 MC 0000\n    4 MR 0000 d0\n    4 MC 0001\n0099 0000 0000 0000 0000 0000 0000 0000 0000 0000 43f7 0001\n00 01 0 0 0 0 5\n\nd1      POP DE\n    0 MC 0000\n    4 MR 0000 d1\n    4 MC 4143\n    7 MR 4143 ce\n    7 MC 4144\n   10 MR 4144 e8\n0000 0000 e8ce 0000 0000 0000 0000 0000 0000 0000 4145 0001\n00 01 0 0 0 0 10\n\nd2_1    JP NC,nn\n    0 MC 0000\n    4 MR 0000 d2\n    4 MC 0001\n    7 MR 0001 1b\n    7 MC 0002\n   10 MR 0002 e1\n0086 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 e11b\n00 01 0 0 0 0 10\n\nd2_2    JP NC,nn\n    0 MC 0000\n    4 MR 0000 d2\n    4 MC 0001\n    7 MC 0002\n0087 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0003\n00 01 0 0 0 0 10\n\nd3_1    OUT (n),A\n    0 MC 0000\n    4 MR 0000 d3\n    4 MC 0001\n    7 MR 0001 ed\n    8 PW a2ed a2\na200 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0002\n00 01 0 0 0 0 11\n\nd3_2    OUT (n),A\n    0 MC 0000\n    4 MR 0000 d3\n    4 MC 0001\n    7 MR 0001 ec\n    7 PC 42ec\n    8 PW 42ec 42\n    8 PC 42ec\n4200 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0002\n00 01 0 0 0 0 11\n\nd3_3    OUT (n),A\n    0 MC 0000\n    4 MR 0000 d3\n    4 MC 0001\n    7 MR 0001 ed\n    7 PC 42ed\n    8 PW 42ed 42\n    8 PC 42ed\n    9 PC 42ed\n   10 PC 42ed\n4200 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0002\n00 01 0 0 0 0 11\n\nd3      OUT (n),A\n    0 MC 0000\n    4 MR 0000 d3\n    4 MC 0001\n    7 MR 0001 ec\n    8 PW a2ec a2\n    8 PC a2ec\na200 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0002\n00 01 0 0 0 0 11\n\nd4_1    CALL NC,nn\n    0 MC 0000\n    4 MR 0000 d4\n    4 MC 0001\n    7 MR 0001 61\n    7 MC 0002\n   10 MR 0002 9c\n   10 MC 0002\n   11 MC 5697\n   14 MW 5697 00\n   14 MC 5696\n   17 MW 5696 03\n000e 0000 0000 0000 0000 0000 0000 0000 0000 0000 5696 9c61\n00 01 0 0 0 0 17\n5696 03 00 -1\n\nd4_2    CALL NC,nn\n    0 MC 0000\n    4 MR 0000 d4\n    4 MC 0001\n    7 MC 0002\n000f 0000 0000 0000 0000 0000 0000 0000 0000 0000 5698 0003\n00 01 0 0 0 0 10\n\nd5      PUSH DE\n    0 MC 0000\n    4 MR 0000 d5\n    4 MC 0001\n    5 MC ec11\n    8 MW ec11 77\n    8 MC ec10\n   11 MW ec10 5f\n53e3 1459 775f 1a2f 0000 0000 0000 0000 0000 0000 ec10 0001\n00 01 0 0 0 0 11\nec10 5f 77 -1\n\nd6      SUB n\n    0 MC 0000\n    4 MR 0000 d6\n    4 MC 0001\n    7 MR 0001 df\n5a1b 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0002\n00 01 0 0 0 0 7\n\nd7      RST 10H\n    0 MC 6d33\n    4 MR 6d33 d7\n    4 MC 0001\n    5 MC 5506\n    8 MW 5506 6d\n    8 MC 5505\n   11 MW 5505 34\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 5505 0010\n00 01 0 0 0 0 11\n5505 34 6d -1\n\nd8_1    RET C\n    0 MC 0000\n    4 MR 0000 d8\n    4 MC 0001\n0098 0000 0000 0000 0000 0000 0000 0000 0000 0000 43f7 0001\n00 01 0 0 0 0 5\n\nd8_2    RET C\n    0 MC 0000\n    4 MR 0000 d8\n    4 MC 0001\n    5 MC 43f7\n    8 MR 43f7 e9\n    8 MC 43f8\n   11 MR 43f8 af\n0099 0000 0000 0000 0000 0000 0000 0000 0000 0000 43f9 afe9\n00 01 0 0 0 0 11\n\nd9      EXX\n    0 MC 0000\n    4 MR 0000 d9\n4d94 c930 3d01 7d02 1a64 e07a e35b 9d64 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\nda_1    JP C,nn\n    0 MC 0000\n    4 MR 0000 da\n    4 MC 0001\n    7 MR 0001 1b\n    7 MC 0002\n   10 MR 0002 e1\n0087 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 e11b\n00 01 0 0 0 0 10\n\nda_2    JP C,nn\n    0 MC 0000\n    4 MR 0000 da\n    4 MC 0001\n    7 MC 0002\n0086 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0003\n00 01 0 0 0 0 10\n\ndb_1    IN A,(n)\n    0 MC 0000\n    4 MR 0000 db\n    4 MC 0001\n    7 MR 0001 e3\n    8 PR c1e3 c1\nc100 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0002\n00 01 0 0 0 0 11\n\ndb_2    IN A,(n)\n    0 MC 0000\n    4 MR 0000 db\n    4 MC 0001\n    7 MR 0001 e2\n    7 PC 71e2\n    8 PR 71e2 71\n    8 PC 71e2\n7100 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0002\n00 01 0 0 0 0 11\n\ndb_3    IN A,(n)\n    0 MC 0000\n    4 MR 0000 db\n    4 MC 0001\n    7 MR 0001 e3\n    7 PC 71e3\n    8 PR 71e3 71\n    8 PC 71e3\n    9 PC 71e3\n   10 PC 71e3\n7100 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0002\n00 01 0 0 0 0 11\n\ndb      IN A,(n)\n    0 MC 0000\n    4 MR 0000 db\n    4 MC 0001\n    7 MR 0001 e2\n    8 PR c1e2 c1\n    8 PC c1e2\nc100 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0002\n00 01 0 0 0 0 11\n\ndc_1    CALL C,nn\n    0 MC 0000\n    4 MR 0000 dc\n    4 MC 0001\n    7 MR 0001 61\n    7 MC 0002\n   10 MR 0002 9c\n   10 MC 0002\n   11 MC 5697\n   14 MW 5697 00\n   14 MC 5696\n   17 MW 5696 03\n000f 0000 0000 0000 0000 0000 0000 0000 0000 0000 5696 9c61\n00 01 0 0 0 0 17\n5696 03 00 -1\n\ndc_2    CALL C,nn\n    0 MC 0000\n    4 MR 0000 dc\n    4 MC 0001\n    7 MC 0002\n000e 0000 0000 0000 0000 0000 0000 0000 0000 0000 5698 0003\n00 01 0 0 0 0 10\n\ndd00\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 00\n    8 MC 0002\n   12 MR 0002 00\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0003\n00 03 0 0 0 0 12\n\ndd09    ADD IX,BC\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 09\n    8 MC 0002\n    9 MC 0002\n   10 MC 0002\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n0d34 1426 53ce 41e3 0000 0000 0000 0000 b2e6 5c89 0000 0002\n00 02 0 0 0 0 15\n\ndd19    ADD IX,DE\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 19\n    8 MC 0002\n    9 MC 0002\n   10 MC 0002\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n1928 0e0b 2724 be62 0000 0000 0000 0000 a973 760b 0000 0002\n00 02 0 0 0 0 15\n\ndd21    LD IX,nn\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 21\n    8 MC 0002\n   11 MR 0002 f2\n   11 MC 0003\n   14 MR 0003 7c\nc935 4353 bd22 94d5 0000 0000 0000 0000 7cf2 aad6 0000 0004\n00 02 0 0 0 0 14\n\ndd22    LD (nn),IX\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 22\n    8 MC 0002\n   11 MR 0002 4f\n   11 MC 0003\n   14 MR 0003 ad\n   14 MC ad4f\n   17 MW ad4f e7\n   17 MC ad50\n   20 MW ad50 eb\n5b1d 45a1 6de8 39d3 0000 0000 0000 0000 ebe7 05b0 0000 0004\n00 02 0 0 0 0 20\nad4f e7 eb -1\n\ndd23    INC IX\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 23\n    8 MC 0002\n    9 MC 0002\n9095 ac3c 4d90 379b 0000 0000 0000 0000 d50c a157 0000 0002\n00 02 0 0 0 0 10\n\ndd24    INC IXh*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 24\n0688 dcd0 a31b d527 0000 0000 0000 0000 8dda b096 0000 0002\n00 02 0 0 0 0 8\n\ndd25    DEC IXh*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 25\n5aaa 206b ed10 6eab 0000 0000 0000 0000 ba3c 5ebd 0000 0002\n00 02 0 0 0 0 8\n\ndd26    LD IXh,n*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 26\n    8 MC 0002\n   11 MR 0002 ad\n9522 ede0 a352 adea 0000 0000 0000 0000 ad40 82e1 0000 0003\n00 02 0 0 0 0 11\n\ndd29    ADD IX,IX\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 29\n    8 MC 0002\n    9 MC 0002\n   10 MC 0002\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\naca0 0f0e 72c8 1f2a 0000 0000 0000 0000 a32a 7d8a 0000 0002\n00 02 0 0 0 0 15\n\ndd2a    LD IX,(nn)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 2a\n    8 MC 0002\n   11 MR 0002 bc\n   11 MC 0003\n   14 MR 0003 40\n   14 MC 40bc\n   17 MR 40bc b5\n   17 MC 40bd\n   20 MR 40bd 30\n3d36 b24e bdbc ca4e 0000 0000 0000 0000 30b5 e7ce 0000 0004\n00 02 0 0 0 0 20\n\ndd2b    DEC IX\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 2b\n    8 MC 0002\n    9 MC 0002\nad4b d5e6 9377 f132 0000 0000 0000 0000 7a16 2188 0000 0002\n00 02 0 0 0 0 10\n\ndd2c    INC IXl*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 2c\n8830 f2f3 d277 9153 0000 0000 0000 0000 c630 b002 0000 0002\n00 02 0 0 0 0 8\n\ndd2d    DEC IXl*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 2d\n3922 b23c 6e11 5a49 0000 0000 0000 0000 0266 ab03 0000 0002\n00 02 0 0 0 0 8\n\ndd2e    LD IXl,n*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 2e\n    8 MC 0002\n   11 MR 0002 1c\n9aca a04a b49f a4a6 0000 0000 0000 0000 bd1c 38a1 0000 0003\n00 02 0 0 0 0 11\n\ndd34    INC (IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 34\n    8 MC 0002\n   11 MR 0002 e6\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC de8f\n   19 MR de8f 57\n   19 MC de8f\n   20 MC de8f\n   23 MW de8f 58\n8308 d1fc b80b 8082 0000 0000 0000 0000 dea9 6fd8 0000 0003\n00 02 0 0 0 0 23\nde8f 58 -1\n\ndd35    DEC (IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 35\n    8 MC 0002\n   11 MR 0002 60\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC c793\n   19 MR c793 f7\n   19 MC c793\n   20 MC c793\n   23 MW c793 f6\n86a3 4641 1ef6 10ab 0000 0000 0000 0000 c733 8ec4 0000 0003\n00 02 0 0 0 0 23\nc793 f6 -1\n\ndd36    LD (IX+d),n\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 36\n    8 MC 0002\n   11 MR 0002 35\n   11 MC 0003\n   14 MR 0003 b5\n   14 MC 0003\n   15 MC 0003\n   16 MC b5fb\n   19 MW b5fb b5\n76dc 2530 5158 877d 0000 0000 0000 0000 b5c6 8d3c 0000 0004\n00 02 0 0 0 0 19\nb5fb b5 -1\n\ndd39    ADD IX,SP\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 39\n    8 MC 0002\n    9 MC 0002\n   10 MC 0002\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n8769 a334 d79d 59e4 0000 0000 0000 0000 ab64 4c88 fa4a 0002\n00 02 0 0 0 0 15\n\ndd44    LD B,IXh*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 44\nb37e 27b0 36e8 3f45 0000 0000 0000 0000 2702 b3b9 0000 0002\n00 02 0 0 0 0 8\n\ndd45    LD B,IXl*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 45\n4e10 986d d11d 1736 0000 0000 0000 0000 7298 2d10 0000 0002\n00 02 0 0 0 0 8\n\ndd46    LD B,(IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 46\n    8 MC 0002\n   11 MR 0002 68\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC 5d2f\n   19 MR 5d2f 8d\nc758 8d29 66f2 29ef 0000 0000 0000 0000 5cc7 407d 0000 0003\n00 02 0 0 0 0 19\n\ndd4c    LD C,IXh*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 4c\ne15c 753e 7531 ae9e 0000 0000 0000 0000 3ed8 03b7 0000 0002\n00 02 0 0 0 0 8\n\ndd4d    LD C,IXl*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 4d\n469e 78aa 6a5a 00e2 0000 0000 0000 0000 a1aa 0d6f 0000 0002\n00 02 0 0 0 0 8\n\ndd4e    LD C,(IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 4e\n    8 MC 0002\n   11 MR 0002 2e\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC d979\n   19 MR d979 76\n7bf7 6676 8d55 def2 0000 0000 0000 0000 d94b 17fb 0000 0003\n00 02 0 0 0 0 19\n\ndd54    LD D,IXh*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 54\n8376 0d13 4b67 3119 0000 0000 0000 0000 4b6d 030b 0000 0002\n00 02 0 0 0 0 8\n\ndd55    LD D,IXl*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 55\nff78 85e3 d76b 8f3a 0000 0000 0000 0000 d7d7 4e0b 0000 0002\n00 02 0 0 0 0 8\n\ndd56    LD D,(IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 56\n    8 MC 0002\n   11 MR 0002 f4\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC a2fa\n   19 MR a2fa de\n97b3 b617 de50 81d1 0000 0000 0000 0000 a306 7a49 0000 0003\n00 02 0 0 0 0 19\n\ndd5c    LD E,IXh*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 5c\naf82 24bf 27f9 f925 0000 0000 0000 0000 f9a3 0b82 0000 0002\n00 02 0 0 0 0 8\n\ndd5d    LD E,IXl*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 5d\n36cb 97a9 4040 30fe 0000 0000 0000 0000 3340 b3ed 0000 0002\n00 02 0 0 0 0 8\n\ndd5e    LD E,(IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 5e\n    8 MC 0002\n   11 MR 0002 8f\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC 8cc1\n   19 MR 8cc1 ce\na220 389d 2fce 368c 0000 0000 0000 0000 8d32 3512 0000 0003\n00 02 0 0 0 0 19\n\ndd60    LD IXh,B*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 60\n2392 7f6a 3dc0 cefb 0000 0000 0000 0000 7fa0 c424 0000 0002\n00 02 0 0 0 0 8\n\ndd61    LD IXh,C*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 61\n76ed 268c d5c8 bab0 0000 0000 0000 0000 8c50 0a93 0000 0002\n00 02 0 0 0 0 8\n\ndd62    LD IXh,D*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 62\n4c6f b482 fef4 62e7 0000 0000 0000 0000 fe25 9655 0000 0002\n00 02 0 0 0 0 8\n\ndd63    LD IXh,E*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 63\n6e9a 5499 3c8f 1f64 0000 0000 0000 0000 8f35 0df7 0000 0002\n00 02 0 0 0 0 8\n\ndd64    LD IXh,IXh*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 64\n47f6 1b7a a55e 2fc2 0000 0000 0000 0000 efc7 aca0 0000 0002\n00 02 0 0 0 0 8\n\ndd65    LD IXh,IXl*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 65\nd786 7d1d b659 77e8 0000 0000 0000 0000 fafa 006d 0000 0002\n00 02 0 0 0 0 8\n\ndd66    LD H,(IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 66\n    8 MC 0002\n   11 MR 0002 b5\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC ce12\n   19 MR ce12 03\n84c2 79b1 ca4a 03a0 0000 0000 0000 0000 ce5d dd2d 0000 0003\n00 02 0 0 0 0 19\n\ndd67    LD IXh,A*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 67\n967c 511e 336d 40f6 0000 0000 0000 0000 96e7 5be2 0000 0002\n00 02 0 0 0 0 8\n\ndd68    LD IXl,B*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 68\n4a9d efa8 febd 07e4 0000 0000 0000 0000 5fef b23f 0000 0002\n00 02 0 0 0 0 8\n\ndd69    LD IXl,C*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 69\n6466 2142 2523 82b3 0000 0000 0000 0000 6442 04a7 0000 0002\n00 02 0 0 0 0 8\n\ndd6a    LD IXl,D*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 6a\n401f 61f1 4b08 fa88 0000 0000 0000 0000 c34b d8f6 0000 0002\n00 02 0 0 0 0 8\n\ndd6b    LD IXl,E*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 6b\n6dc7 e2ae 40bd f3c0 0000 0000 0000 0000 22bd 2749 0000 0002\n00 02 0 0 0 0 8\n\ndd6c    LD IXl,IXh*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 6c\n3939 90da 62dc 7c31 0000 0000 0000 0000 4141 7211 0000 0002\n00 02 0 0 0 0 8\n\ndd6d    LD IXl,IXl*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 6d\n3964 ff3f 23d4 c7c7 0000 0000 0000 0000 9b70 20c6 0000 0002\n00 02 0 0 0 0 8\n\ndd6e    LD L,(IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 6e\n    8 MC 0002\n   11 MR 0002 2c\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC c674\n   19 MR c674 6b\n223f f661 b61c 0f6b 0000 0000 0000 0000 c648 fae8 0000 0003\n00 02 0 0 0 0 19\n\ndd6f    LD IXl,A*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 6f\n6e84 9cd4 a293 647d 0000 0000 0000 0000 0d6e 4a56 0000 0002\n00 02 0 0 0 0 8\n\ndd70    LD (IX+d),B\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 70\n    8 MC 0002\n   11 MR 0002 f6\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC 05f0\n   19 MW 05f0 fe\nd09f fe00 231e 31ec 0000 0000 0000 0000 05fa ea92 0000 0003\n00 02 0 0 0 0 19\n05f0 fe -1\n\ndd71    LD (IX+d),C\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 71\n    8 MC 0002\n   11 MR 0002 23\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC 3745\n   19 MW 3745 1c\nebee 151c 05c7 ee08 0000 0000 0000 0000 3722 2ec6 0000 0003\n00 02 0 0 0 0 19\n3745 1c -1\n\ndd72    LD (IX+d),D\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 72\n    8 MC 0002\n   11 MR 0002 93\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC 8d92\n   19 MW 8d92 63\n80c9 ac1e 63bd 828b 0000 0000 0000 0000 8dff 94ef 0000 0003\n00 02 0 0 0 0 19\n8d92 63 -1\n\ndd73    LD (IX+d),E\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 73\n    8 MC 0002\n   11 MR 0002 57\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC 7a1d\n   19 MW 7a1d de\n8f3e b5a3 07de 0b0c 0000 0000 0000 0000 79c6 ae79 0000 0003\n00 02 0 0 0 0 19\n7a1d de -1\n\ndd74    LD (IX+d),H\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 74\n    8 MC 0002\n   11 MR 0002 b9\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC 58c9\n   19 MW 58c9 01\n4ae0 49c5 3deb 0125 0000 0000 0000 0000 5910 429a 0000 0003\n00 02 0 0 0 0 19\n58c9 01 -1\n\ndd75    LD (IX+d),L\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 75\n    8 MC 0002\n   11 MR 0002 30\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC ae7c\n   19 MW ae7c 4f\n5772 e833 b63e 734f 0000 0000 0000 0000 ae4c e8c2 0000 0003\n00 02 0 0 0 0 19\nae7c 4f -1\n\ndd77    LD (IX+d),A\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 77\n    8 MC 0002\n   11 MR 0002 8c\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC a10d\n   19 MW a10d dc\ndc56 d893 4116 f2d2 0000 0000 0000 0000 a181 3157 0000 0003\n00 02 0 0 0 0 19\na10d dc -1\n\ndd7c    LD A,IXh*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 7c\n8c58 7705 ac92 a6a1 0000 0000 0000 0000 8cde 7507 0000 0002\n00 02 0 0 0 0 8\n\ndd7d    LD A,IXl*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 7d\ncb18 93fb 6bdd 3a10 0000 0000 0000 0000 d7cb c0f6 0000 0002\n00 02 0 0 0 0 8\n\ndd7e    LD A,(IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 7e\n    8 MC 0002\n   11 MR 0002 bc\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC 1cb0\n   19 MR 1cb0 57\n5766 1f77 6220 0c40 0000 0000 0000 0000 1cf4 1a1f 0000 0003\n00 02 0 0 0 0 19\n\ndd84    ADD A,IXh*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 84\ncd98 1de8 b8b9 78a6 0000 0000 0000 0000 9f1d b11f 0000 0002\n00 02 0 0 0 0 8\n\ndd85    ADD A,IXl*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 85\nc580 b1ff 8d7b 40c0 0000 0000 0000 0000 b513 0688 0000 0002\n00 02 0 0 0 0 8\n\ndd86    ADD A,(IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 86\n    8 MC 0002\n   11 MR 0002 c1\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC b576\n   19 MR b576 5b\na9bc d085 5bac e364 0000 0000 0000 0000 b5b5 fe3a 0000 0003\n00 02 0 0 0 0 19\n\ndd8c    ADC A,IXh*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 8c\ncb98 8fdc ea8f 9734 0000 0000 0000 0000 0eb3 1b54 0000 0002\n00 02 0 0 0 0 8\n\ndd8d    ADC A,IXl*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 8d\n7535 1c81 b6fb d6e5 0000 0000 0000 0000 09be a736 0000 0002\n00 02 0 0 0 0 8\n\ndd8e    ADC A,(IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 8e\n    8 MC 0002\n   11 MR 0002 25\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC bbbc\n   19 MR bbbc 32\n8094 182d ab17 94ae 0000 0000 0000 0000 bb97 87da 0000 0003\n00 02 0 0 0 0 19\n\ndd94    SUB IXh*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 94\n7422 9efe 6ea1 fc55 0000 0000 0000 0000 0a09 89c5 0000 0002\n00 02 0 0 0 0 8\n\ndd95    SUB IXl*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 95\n2c3b 59ab 428c 3a94 0000 0000 0000 0000 44fd f243 0000 0002\n00 02 0 0 0 0 8\n\ndd96    SUB (IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 96\n    8 MC 0002\n   11 MR 0002 5f\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC 2cc5\n   19 MR 2cc5 49\n5206 461f ced7 db3f 0000 0000 0000 0000 2c66 9dbf 0000 0003\n00 02 0 0 0 0 19\n\ndd9c    SBC A,IXh*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 9c\nd282 670e afcc 8b34 0000 0000 0000 0000 285f 1caa 0000 0002\n00 02 0 0 0 0 8\n\ndd9d    SBC A,IXl*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 9d\ne5a2 0cdb df32 d0e4 0000 0000 0000 0000 9b12 7d07 0000 0002\n00 02 0 0 0 0 8\n\ndd9e    SBC A,(IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 9e\n    8 MC 0002\n   11 MR 0002 14\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC b4e0\n   19 MR b4e0 b5\nde9b f9c5 cbc4 ca21 0000 0000 0000 0000 b4cc 46fa 0000 0003\n00 02 0 0 0 0 19\n\ndda4    AND IXh*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 a4\n0210 ba53 acfc 9481 0000 0000 0000 0000 2f8b edf6 0000 0002\n00 02 0 0 0 0 8\n\ndda5    AND IXl*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 a5\naabc a675 d757 f1db 0000 0000 0000 0000 fdef d8ce 0000 0002\n00 02 0 0 0 0 8\n\ndda6    AND (IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 a6\n    8 MC 0002\n   11 MR 0002 41\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC 7ed6\n   19 MR 7ed6 c7\n0514 20c4 ebc3 da8d 0000 0000 0000 0000 7e95 5e8a 0000 0003\n00 02 0 0 0 0 19\n\nddac    XOR IXh*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 ac\n4000 2a7c 17e5 3f6e 0000 0000 0000 0000 affa a0b5 0000 0002\n00 02 0 0 0 0 8\n\nddad    XOR IXl*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 ad\n8284 6ba1 ef1b 5713 0000 0000 0000 0000 ba38 a708 0000 0002\n00 02 0 0 0 0 8\n\nddae    XOR (IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 ae\n    8 MC 0002\n   11 MR 0002 72\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC e97b\n   19 MR e97b c3\n4300 3ad6 a721 2100 0000 0000 0000 0000 e909 87b4 0000 0003\n00 02 0 0 0 0 19\n\nddb4    OR IXh*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 b4\n9c8c 29aa 2e82 4dc8 0000 0000 0000 0000 9c04 8be3 0000 0002\n00 02 0 0 0 0 8\n\nddb5    OR IXl*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 b5\nc780 fc93 7a06 0518 0000 0000 0000 0000 0ac5 4150 0000 0002\n00 02 0 0 0 0 8\n\nddb6    OR (IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 b6\n    8 MC 0002\n   11 MR 0002 31\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC c6a0\n   19 MR c6a0 1c\n5c0c ab81 4287 5ee1 0000 0000 0000 0000 c66f d6cc 0000 0003\n00 02 0 0 0 0 19\n\nddbc    CP IXh*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 bc\n53bf aa98 f7d7 fa0c 0000 0000 0000 0000 be7a a41f 0000 0002\n00 02 0 0 0 0 8\n\nddbd    CP IXl*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 bd\ndc82 80ce 5d2f e999 0000 0000 0000 0000 bb41 a24f 0000 0002\n00 02 0 0 0 0 8\n\nddbe    CP (IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 be\n    8 MC 0002\n   11 MR 0002 48\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC 937a\n   19 MR 937a 5b\n981e bfd5 a299 d34b 0000 0000 0000 0000 9332 b1d5 0000 0003\n00 02 0 0 0 0 19\n\nddcb00  RLC (IX+d),B*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 0d\n   11 MC 0003\n   14 MR 0003 00\n   14 MC 0003\n   15 MC 0003\n   16 MC 1dae\n   19 MR 1dae a1\n   19 MC 1dae\n   20 MC 1dae\n   23 MW 1dae 43\n3c01 43e4 09d1 646b 0000 0000 0000 0000 1da1 f08f 0000 0004\n00 02 0 0 0 0 23\n1dae 43 -1\n\nddcb01  RLC (IX+d),C*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 b7\n   11 MC 0003\n   14 MR 0003 01\n   14 MC 0003\n   15 MC 0003\n   16 MC 28b4\n   19 MR 28b4 e3\n   19 MC 28b4\n   20 MC 28b4\n   23 MW 28b4 c7\nf681 e3c7 2d4a 7725 0000 0000 0000 0000 28fd f31b 0000 0004\n00 02 0 0 0 0 23\n28b4 c7 -1\n\nddcb02  RLC (IX+d),D*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 91\n   11 MC 0003\n   14 MR 0003 02\n   14 MC 0003\n   15 MC 0003\n   16 MC c727\n   19 MR c727 8d\n   19 MC c727\n   20 MC c727\n   23 MW c727 1b\ne20d 836e 1b3a f840 0000 0000 0000 0000 c796 ae9b 0000 0004\n00 02 0 0 0 0 23\nc727 1b -1\n\nddcb03  RLC (IX+d),E*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 48\n   11 MC 0003\n   14 MR 0003 03\n   14 MC 0003\n   15 MC 0003\n   16 MC 0466\n   19 MR 0466 78\n   19 MC 0466\n   20 MC 0466\n   23 MW 0466 f0\n62a4 3571 c5f0 48dc 0000 0000 0000 0000 041e c07b 0000 0004\n00 02 0 0 0 0 23\n0466 f0 -1\n\nddcb04  RLC (IX+d),H*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 48\n   11 MC 0003\n   14 MR 0003 04\n   14 MC 0003\n   15 MC 0003\n   16 MC 5991\n   19 MR 5991 68\n   19 MC 5991\n   20 MC 5991\n   23 MW 5991 d0\nb380 bfc4 64af d022 0000 0000 0000 0000 5949 a989 0000 0004\n00 02 0 0 0 0 23\n5991 d0 -1\n\nddcb05  RLC (IX+d),L*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 ff\n   11 MC 0003\n   14 MR 0003 05\n   14 MC 0003\n   15 MC 0003\n   16 MC 0076\n   19 MR 0076 95\n   19 MC 0076\n   20 MC 0076\n   23 MW 0076 2b\n492d bb04 56ec 9d2b 0000 0000 0000 0000 0077 1349 0000 0004\n00 02 0 0 0 0 23\n0076 2b -1\n\nddcb06  RLC (IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 07\n   11 MC 0003\n   14 MR 0003 06\n   14 MC 0003\n   15 MC 0003\n   16 MC 5428\n   19 MR 5428 97\n   19 MC 5428\n   20 MC 5428\n   23 MW 5428 2f\n0c29 f636 90a6 6117 0000 0000 0000 0000 5421 90ee 0000 0004\n00 02 0 0 0 0 23\n5428 2f -1\n\nddcb07  RLC (IX+d),A*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 42\n   11 MC 0003\n   14 MR 0003 07\n   14 MC 0003\n   15 MC 0003\n   16 MC 9845\n   19 MR 9845 ae\n   19 MC 9845\n   20 MC 9845\n   23 MW 9845 5d\n5d09 9ca3 bdf6 ed50 0000 0000 0000 0000 9803 55f9 0000 0004\n00 02 0 0 0 0 23\n9845 5d -1\n\nddcb08  RRC (IX+d),B*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 0a\n   11 MC 0003\n   14 MR 0003 08\n   14 MC 0003\n   15 MC 0003\n   16 MC ef4a\n   19 MR ef4a da\n   19 MC ef4a\n   20 MC ef4a\n   23 MW ef4a 6d\n0228 6d66 6023 ae06 0000 0000 0000 0000 ef40 b006 0000 0004\n00 02 0 0 0 0 23\nef4a 6d -1\n\nddcb09  RRC (IX+d),C*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 3b\n   11 MC 0003\n   14 MR 0003 09\n   14 MC 0003\n   15 MC 0003\n   16 MC 9d46\n   19 MR 9d46 6f\n   19 MC 9d46\n   20 MC 9d46\n   23 MW 9d46 b7\n98a5 92b7 54d5 5e1e 0000 0000 0000 0000 9d0b 6e58 0000 0004\n00 02 0 0 0 0 23\n9d46 b7 -1\n\nddcb0a  RRC (IX+d),D*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 83\n   11 MC 0003\n   14 MR 0003 0a\n   14 MC 0003\n   15 MC 0003\n   16 MC 1f37\n   19 MR 1f37 78\n   19 MC 1f37\n   20 MC 1f37\n   23 MW 1f37 3c\nd22c 6aac 3c89 9293 0000 0000 0000 0000 1fb4 2498 0000 0004\n00 02 0 0 0 0 23\n1f37 3c -1\n\nddcb0b  RRC (IX+d),E*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 fa\n   11 MC 0003\n   14 MR 0003 0b\n   14 MC 0003\n   15 MC 0003\n   16 MC cd03\n   19 MR cd03 92\n   19 MC cd03\n   20 MC cd03\n   23 MW cd03 49\nb808 b284 2349 7e7d 0000 0000 0000 0000 cd09 6a03 0000 0004\n00 02 0 0 0 0 23\ncd03 49 -1\n\nddcb0c  RRC (IX+d),H*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 79\n   11 MC 0003\n   14 MR 0003 0c\n   14 MC 0003\n   15 MC 0003\n   16 MC bfe4\n   19 MR bfe4 0d\n   19 MC bfe4\n   20 MC bfe4\n   23 MW bfe4 86\ndf81 b6cc ee8d 865a 0000 0000 0000 0000 bf6b 9b7d 0000 0004\n00 02 0 0 0 0 23\nbfe4 86 -1\n\nddcb0d  RRC (IX+d),L*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 e4\n   11 MC 0003\n   14 MR 0003 0d\n   14 MC 0003\n   15 MC 0003\n   16 MC 88a1\n   19 MR 88a1 1f\n   19 MC 88a1\n   20 MC 88a1\n   23 MW 88a1 8f\nba89 ceec bbaa b68f 0000 0000 0000 0000 88bd 503e 0000 0004\n00 02 0 0 0 0 23\n88a1 8f -1\n\nddcb0e  RRC (IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 c6\n   11 MC 0003\n   14 MR 0003 0e\n   14 MC 0003\n   15 MC 0003\n   16 MC fd0f\n   19 MR fd0f ad\n   19 MC fd0f\n   20 MC fd0f\n   23 MW fd0f d6\n1c81 890b 7830 060c 0000 0000 0000 0000 fd49 5d07 0000 0004\n00 02 0 0 0 0 23\nfd0f d6 -1\n\nddcb0f  RRC (IX+d),A*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 57\n   11 MC 0003\n   14 MR 0003 0f\n   14 MC 0003\n   15 MC 0003\n   16 MC 749e\n   19 MR 749e f8\n   19 MC 749e\n   20 MC 749e\n   23 MW 749e 7c\n7c28 fad4 fa4b 9c53 0000 0000 0000 0000 7447 2267 0000 0004\n00 02 0 0 0 0 23\n749e 7c -1\n\nddcb10  RL (IX+d),B*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 4f\n   11 MC 0003\n   14 MR 0003 10\n   14 MC 0003\n   15 MC 0003\n   16 MC bbf1\n   19 MR bbf1 45\n   19 MC bbf1\n   20 MC bbf1\n   23 MW bbf1 8b\nf38c 8b1f 5387 926e 0000 0000 0000 0000 bba2 ca47 0000 0004\n00 02 0 0 0 0 23\nbbf1 8b -1\n\nddcb11  RL (IX+d),C*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 eb\n   11 MC 0003\n   14 MR 0003 11\n   14 MC 0003\n   15 MC 0003\n   16 MC 17f4\n   19 MR 17f4 d9\n   19 MC 17f4\n   20 MC 17f4\n   23 MW 17f4 b3\n2aa1 d6b3 a9aa 5b52 0000 0000 0000 0000 1809 d275 0000 0004\n00 02 0 0 0 0 23\n17f4 b3 -1\n\nddcb12  RL (IX+d),D*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 a6\n   11 MC 0003\n   14 MR 0003 12\n   14 MC 0003\n   15 MC 0003\n   16 MC c0a1\n   19 MR c0a1 e2\n   19 MC c0a1\n   20 MC c0a1\n   23 MW c0a1 c5\n9285 c479 c5d1 10ce 0000 0000 0000 0000 c0fb 2777 0000 0004\n00 02 0 0 0 0 23\nc0a1 c5 -1\n\nddcb13  RL (IX+d),E*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 ff\n   11 MC 0003\n   14 MR 0003 13\n   14 MC 0003\n   15 MC 0003\n   16 MC 5ac3\n   19 MR 5ac3 a7\n   19 MC 5ac3\n   20 MC 5ac3\n   23 MW 5ac3 4f\na509 580a a44f 11cd 0000 0000 0000 0000 5ac4 ccc7 0000 0004\n00 02 0 0 0 0 23\n5ac3 4f -1\n\nddcb14  RL (IX+d),H*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 dd\n   11 MC 0003\n   14 MR 0003 14\n   14 MC 0003\n   15 MC 0003\n   16 MC 0954\n   19 MR 0954 85\n   19 MC 0954\n   20 MC 0954\n   23 MW 0954 0b\n2909 5b89 8467 0b30 0000 0000 0000 0000 0977 c4e8 0000 0004\n00 02 0 0 0 0 23\n0954 0b -1\n\nddcb15  RL (IX+d),L*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 07\n   11 MC 0003\n   14 MR 0003 15\n   14 MC 0003\n   15 MC 0003\n   16 MC edf0\n   19 MR edf0 0e\n   19 MC edf0\n   20 MC edf0\n   23 MW edf0 1d\n1f0c 6d53 5b7c a11d 0000 0000 0000 0000 ede9 a85c 0000 0004\n00 02 0 0 0 0 23\nedf0 1d -1\n\nddcb16  RL (IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 45\n   11 MC 0003\n   14 MR 0003 16\n   14 MC 0003\n   15 MC 0003\n   16 MC 1703\n   19 MR 1703 5b\n   19 MC 1703\n   20 MC 1703\n   23 MW 1703 b6\ndaa0 a1e4 00b0 92c8 0000 0000 0000 0000 16be 2c95 0000 0004\n00 02 0 0 0 0 23\n1703 b6 -1\n\nddcb17  RL (IX+d),A*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 1c\n   11 MC 0003\n   14 MR 0003 17\n   14 MC 0003\n   15 MC 0003\n   16 MC b8e5\n   19 MR b8e5 7e\n   19 MC b8e5\n   20 MC b8e5\n   23 MW b8e5 fc\nfcac cbd1 4e1a cd27 0000 0000 0000 0000 b8c9 e6d4 0000 0004\n00 02 0 0 0 0 23\nb8e5 fc -1\n\nddcb18  RR (IX+d),B*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 0e\n   11 MC 0003\n   14 MR 0003 18\n   14 MC 0003\n   15 MC 0003\n   16 MC a197\n   19 MR a197 90\n   19 MC a197\n   20 MC a197\n   23 MW a197 48\nd90c 48b5 9cf9 b9f1 0000 0000 0000 0000 a189 bd7c 0000 0004\n00 02 0 0 0 0 23\na197 48 -1\n\nddcb19  RR (IX+d),C*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 a3\n   11 MC 0003\n   14 MR 0003 19\n   14 MC 0003\n   15 MC 0003\n   16 MC f08a\n   19 MR f08a 37\n   19 MC f08a\n   20 MC f08a\n   23 MW f08a 9b\n2389 599b a756 cf2e 0000 0000 0000 0000 f0e7 26e4 0000 0004\n00 02 0 0 0 0 23\nf08a 9b -1\n\nddcb1a  RR (IX+d),D*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 ac\n   11 MC 0003\n   14 MR 0003 1a\n   14 MC 0003\n   15 MC 0003\n   16 MC de0d\n   19 MR de0d cc\n   19 MC de0d\n   20 MC de0d\n   23 MW de0d 66\n8b24 7e45 660f 37a6 0000 0000 0000 0000 de61 9cd9 0000 0004\n00 02 0 0 0 0 23\nde0d 66 -1\n\nddcb1b  RR (IX+d),E*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 05\n   11 MC 0003\n   14 MR 0003 1b\n   14 MC 0003\n   15 MC 0003\n   16 MC b7c8\n   19 MR b7c8 91\n   19 MC b7c8\n   20 MC b7c8\n   23 MW b7c8 c8\n5c89 1414 81c8 5881 0000 0000 0000 0000 b7c3 d14f 0000 0004\n00 02 0 0 0 0 23\nb7c8 c8 -1\n\nddcb1c  RR (IX+d),H*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 ff\n   11 MC 0003\n   14 MR 0003 1c\n   14 MC 0003\n   15 MC 0003\n   16 MC fef8\n   19 MR fef8 61\n   19 MC fef8\n   20 MC fef8\n   23 MW fef8 30\nfa25 6277 8b67 3023 0000 0000 0000 0000 fef9 4a66 0000 0004\n00 02 0 0 0 0 23\nfef8 30 -1\n\nddcb1d  RR (IX+d),L*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 3a\n   11 MC 0003\n   14 MR 0003 1d\n   14 MC 0003\n   15 MC 0003\n   16 MC 5b9d\n   19 MR 5b9d f3\n   19 MC 5b9d\n   20 MC 5b9d\n   23 MW 5b9d f9\n76ad 324e e641 58f9 0000 0000 0000 0000 5b63 e18b 0000 0004\n00 02 0 0 0 0 23\n5b9d f9 -1\n\nddcb1e  RR (IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 ce\n   11 MC 0003\n   14 MR 0003 1e\n   14 MC 0003\n   15 MC 0003\n   16 MC 7582\n   19 MR 7582 91\n   19 MC 7582\n   20 MC 7582\n   23 MW 7582 c8\nc589 cd58 8967 f074 0000 0000 0000 0000 75b4 693a 0000 0004\n00 02 0 0 0 0 23\n7582 c8 -1\n\nddcb1f  RR (IX+d),A*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 a8\n   11 MC 0003\n   14 MR 0003 1f\n   14 MC 0003\n   15 MC 0003\n   16 MC 1d43\n   19 MR 1d43 b4\n   19 MC 1d43\n   20 MC 1d43\n   23 MW 1d43 da\nda88 7f6d 2058 63e3 0000 0000 0000 0000 1d9b baba 0000 0004\n00 02 0 0 0 0 23\n1d43 da -1\n\nddcb20  SLA (IX+d),B*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 e8\n   11 MC 0003\n   14 MR 0003 20\n   14 MC 0003\n   15 MC 0003\n   16 MC dc21\n   19 MR dc21 0e\n   19 MC dc21\n   20 MC dc21\n   23 MW dc21 1c\n4c08 1c9e dc6c 18f4 0000 0000 0000 0000 dc39 8b0c 0000 0004\n00 02 0 0 0 0 23\ndc21 1c -1\n\nddcb21  SLA (IX+d),C*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 9e\n   11 MC 0003\n   14 MR 0003 21\n   14 MC 0003\n   15 MC 0003\n   16 MC 3432\n   19 MR 3432 f7\n   19 MC 3432\n   20 MC 3432\n   23 MW 3432 ee\nd2ad 66ee 23ef 9096 0000 0000 0000 0000 3494 b6c3 0000 0004\n00 02 0 0 0 0 23\n3432 ee -1\n\nddcb22  SLA (IX+d),D*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 43\n   11 MC 0003\n   14 MR 0003 22\n   14 MC 0003\n   15 MC 0003\n   16 MC bd82\n   19 MR bd82 9f\n   19 MC bd82\n   20 MC bd82\n   23 MW bd82 3e\nfb29 e0d0 3e02 b4b7 0000 0000 0000 0000 bd3f 385b 0000 0004\n00 02 0 0 0 0 23\nbd82 3e -1\n\nddcb23  SLA (IX+d),E*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 c1\n   11 MC 0003\n   14 MR 0003 23\n   14 MC 0003\n   15 MC 0003\n   16 MC 229e\n   19 MR 229e e0\n   19 MC 229e\n   20 MC 229e\n   23 MW 229e c0\nc385 68b6 dac0 b990 0000 0000 0000 0000 22dd bd27 0000 0004\n00 02 0 0 0 0 23\n229e c0 -1\n\nddcb24  SLA (IX+d),H*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 e8\n   11 MC 0003\n   14 MR 0003 24\n   14 MC 0003\n   15 MC 0003\n   16 MC 31d9\n   19 MR 31d9 c3\n   19 MC 31d9\n   20 MC 31d9\n   23 MW 31d9 86\nba81 7b0b 560b 8633 0000 0000 0000 0000 31f1 ddbd 0000 0004\n00 02 0 0 0 0 23\n31d9 86 -1\n\nddcb25  SLA (IX+d),L*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 c1\n   11 MC 0003\n   14 MR 0003 25\n   14 MC 0003\n   15 MC 0003\n   16 MC cc24\n   19 MR cc24 eb\n   19 MC cc24\n   20 MC cc24\n   23 MW cc24 d6\n4381 a21b 2347 aed6 0000 0000 0000 0000 cc63 fc94 0000 0004\n00 02 0 0 0 0 23\ncc24 d6 -1\n\nddcb26  SLA (IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 f7\n   11 MC 0003\n   14 MR 0003 26\n   14 MC 0003\n   15 MC 0003\n   16 MC 651f\n   19 MR 651f 89\n   19 MC 651f\n   20 MC 651f\n   23 MW 651f 12\n2005 ff37 e41f 70e7 0000 0000 0000 0000 6528 a0d5 0000 0004\n00 02 0 0 0 0 23\n651f 12 -1\n\nddcb27  SLA (IX+d),A*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 c3\n   11 MC 0003\n   14 MR 0003 27\n   14 MC 0003\n   15 MC 0003\n   16 MC 1f2c\n   19 MR 1f2c ac\n   19 MC 1f2c\n   20 MC 1f2c\n   23 MW 1f2c 58\n5809 5669 1bee f62c 0000 0000 0000 0000 1f69 3418 0000 0004\n00 02 0 0 0 0 23\n1f2c 58 -1\n\nddcb28  SRA (IX+d),B*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 b6\n   11 MC 0003\n   14 MR 0003 28\n   14 MC 0003\n   15 MC 0003\n   16 MC 9951\n   19 MR 9951 24\n   19 MC 9951\n   20 MC 9951\n   23 MW 9951 12\n7a04 12b8 51f7 7164 0000 0000 0000 0000 999b 8857 0000 0004\n00 02 0 0 0 0 23\n9951 12 -1\n\nddcb29  SRA (IX+d),C*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 9c\n   11 MC 0003\n   14 MR 0003 29\n   14 MC 0003\n   15 MC 0003\n   16 MC 2083\n   19 MR 2083 82\n   19 MC 2083\n   20 MC 2083\n   23 MW 2083 c1\n0480 b7c1 323f fd34 0000 0000 0000 0000 20e7 c753 0000 0004\n00 02 0 0 0 0 23\n2083 c1 -1\n\nddcb2a  SRA (IX+d),D*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 d8\n   11 MC 0003\n   14 MR 0003 2a\n   14 MC 0003\n   15 MC 0003\n   16 MC 94dd\n   19 MR 94dd 7c\n   19 MC 94dd\n   20 MC 94dd\n   23 MW 94dd 3e\n4528 afde 3e08 75d7 0000 0000 0000 0000 9505 b624 0000 0004\n00 02 0 0 0 0 23\n94dd 3e -1\n\nddcb2b  SRA (IX+d),E*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 bd\n   11 MC 0003\n   14 MR 0003 2b\n   14 MC 0003\n   15 MC 0003\n   16 MC b441\n   19 MR b441 44\n   19 MC b441\n   20 MC b441\n   23 MW b441 22\n8324 e290 2622 7ddd 0000 0000 0000 0000 b484 571c 0000 0004\n00 02 0 0 0 0 23\nb441 22 -1\n\nddcb2c  SRA (IX+d),H*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 2c\n   11 MC 0003\n   14 MR 0003 2c\n   14 MC 0003\n   15 MC 0003\n   16 MC fe54\n   19 MR fe54 81\n   19 MC fe54\n   20 MC fe54\n   23 MW fe54 c0\nc685 0c94 6e4b c0c7 0000 0000 0000 0000 fe28 dc80 0000 0004\n00 02 0 0 0 0 23\nfe54 c0 -1\n\nddcb2d  SRA (IX+d),L*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 9b\n   11 MC 0003\n   14 MR 0003 2d\n   14 MC 0003\n   15 MC 0003\n   16 MC b488\n   19 MR b488 44\n   19 MC b488\n   20 MC b488\n   23 MW b488 22\nce24 d2ae c9be 4222 0000 0000 0000 0000 b4ed 6de3 0000 0004\n00 02 0 0 0 0 23\nb488 22 -1\n\nddcb2e  SRA (IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 3d\n   11 MC 0003\n   14 MR 0003 2e\n   14 MC 0003\n   15 MC 0003\n   16 MC 6a15\n   19 MR 6a15 05\n   19 MC 6a15\n   20 MC 6a15\n   23 MW 6a15 02\n5001 de74 eca8 83ff 0000 0000 0000 0000 69d8 75c7 0000 0004\n00 02 0 0 0 0 23\n6a15 02 -1\n\nddcb2f  SRA (IX+d),A*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 d3\n   11 MC 0003\n   14 MR 0003 2f\n   14 MC 0003\n   15 MC 0003\n   16 MC 7a03\n   19 MR 7a03 f2\n   19 MC 7a03\n   20 MC 7a03\n   23 MW 7a03 f9\nf9ac 759b 3059 01b9 0000 0000 0000 0000 7a30 dd56 0000 0004\n00 02 0 0 0 0 23\n7a03 f9 -1\n\nddcb30  SLL (IX+d),B*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 df\n   11 MC 0003\n   14 MR 0003 30\n   14 MC 0003\n   15 MC 0003\n   16 MC eec7\n   19 MR eec7 32\n   19 MC eec7\n   20 MC eec7\n   23 MW eec7 65\n3c24 65ad 9cc7 a68c 0000 0000 0000 0000 eee8 5a80 0000 0004\n00 02 0 0 0 0 23\neec7 65 -1\n\nddcb31  SLL (IX+d),C*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 49\n   11 MC 0003\n   14 MR 0003 31\n   14 MC 0003\n   15 MC 0003\n   16 MC f276\n   19 MR f276 cd\n   19 MC f276\n   20 MC f276\n   23 MW f276 9b\neb89 419b 929b 7d47 0000 0000 0000 0000 f22d 8943 0000 0004\n00 02 0 0 0 0 23\nf276 9b -1\n\nddcb32  SLL (IX+d),D*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 e0\n   11 MC 0003\n   14 MR 0003 32\n   14 MC 0003\n   15 MC 0003\n   16 MC 577f\n   19 MR 577f e2\n   19 MC 577f\n   20 MC 577f\n   23 MW 577f c5\n9a85 aa64 c509 01ad 0000 0000 0000 0000 579f ec4c 0000 0004\n00 02 0 0 0 0 23\n577f c5 -1\n\nddcb33  SLL (IX+d),E*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 c9\n   11 MC 0003\n   14 MR 0003 33\n   14 MC 0003\n   15 MC 0003\n   16 MC ef75\n   19 MR ef75 0b\n   19 MC ef75\n   20 MC ef75\n   23 MW ef75 17\nb804 b854 5217 9599 0000 0000 0000 0000 efac d9ec 0000 0004\n00 02 0 0 0 0 23\nef75 17 -1\n\nddcb34  SLL (IX+d),H*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 49\n   11 MC 0003\n   14 MR 0003 34\n   14 MC 0003\n   15 MC 0003\n   16 MC ab91\n   19 MR ab91 ef\n   19 MC ab91\n   20 MC ab91\n   23 MW ab91 df\ncd89 4432 20d4 df3e 0000 0000 0000 0000 ab48 c95f 0000 0004\n00 02 0 0 0 0 23\nab91 df -1\n\nddcb35  SLL (IX+d),L*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 b9\n   11 MC 0003\n   14 MR 0003 35\n   14 MC 0003\n   15 MC 0003\n   16 MC ead3\n   19 MR ead3 8f\n   19 MC ead3\n   20 MC ead3\n   23 MW ead3 1f\nde09 c6fc 696d 151f 0000 0000 0000 0000 eb1a 4a12 0000 0004\n00 02 0 0 0 0 23\nead3 1f -1\n\nddcb36  SLL (IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 b4\n   11 MC 0003\n   14 MR 0003 36\n   14 MC 0003\n   15 MC 0003\n   16 MC 12e2\n   19 MR 12e2 02\n   19 MC 12e2\n   20 MC 12e2\n   23 MW 12e2 05\n3d04 443b ff21 63e3 0000 0000 0000 0000 132e fb39 0000 0004\n00 02 0 0 0 0 23\n12e2 05 -1\n\nddcb37  SLL (IX+d),A*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 c6\n   11 MC 0003\n   14 MR 0003 37\n   14 MC 0003\n   15 MC 0003\n   16 MC 503d\n   19 MR 503d 3d\n   19 MC 503d\n   20 MC 503d\n   23 MW 503d 7b\n7b2c bfc9 a69a ec0b 0000 0000 0000 0000 5077 4e3e 0000 0004\n00 02 0 0 0 0 23\n503d 7b -1\n\nddcb38  SRL (IX+d),B*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 8e\n   11 MC 0003\n   14 MR 0003 38\n   14 MC 0003\n   15 MC 0003\n   16 MC f623\n   19 MR f623 5e\n   19 MC f623\n   20 MC f623\n   23 MW f623 2f\n3c28 2fee 38e1 ae9f 0000 0000 0000 0000 f695 44b3 0000 0004\n00 02 0 0 0 0 23\nf623 2f -1\n\nddcb39  SRL (IX+d),C*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 dc\n   11 MC 0003\n   14 MR 0003 39\n   14 MC 0003\n   15 MC 0003\n   16 MC a871\n   19 MR a871 83\n   19 MC a871\n   20 MC a871\n   23 MW a871 41\n0505 9a41 a2db df75 0000 0000 0000 0000 a895 e243 0000 0004\n00 02 0 0 0 0 23\na871 41 -1\n\nddcb3a  SRL (IX+d),D*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 0d\n   11 MC 0003\n   14 MR 0003 3a\n   14 MC 0003\n   15 MC 0003\n   16 MC 259e\n   19 MR 259e 89\n   19 MC 259e\n   20 MC 259e\n   23 MW 259e 44\n0e05 0b9f 443b c01d 0000 0000 0000 0000 2591 49c3 0000 0004\n00 02 0 0 0 0 23\n259e 44 -1\n\nddcb3b  SRL (IX+d),E*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 20\n   11 MC 0003\n   14 MR 0003 3b\n   14 MC 0003\n   15 MC 0003\n   16 MC 700d\n   19 MR 700d a9\n   19 MC 700d\n   20 MC 700d\n   23 MW 700d 54\n1b01 c795 d854 7ccf 0000 0000 0000 0000 6fed 09dc 0000 0004\n00 02 0 0 0 0 23\n700d 54 -1\n\nddcb3c  SRL (IX+d),H*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 e1\n   11 MC 0003\n   14 MR 0003 3c\n   14 MC 0003\n   15 MC 0003\n   16 MC f51c\n   19 MR f51c d0\n   19 MC f51c\n   20 MC f51c\n   23 MW f51c 68\nb628 bdf7 fca3 6829 0000 0000 0000 0000 f53b 018b 0000 0004\n00 02 0 0 0 0 23\nf51c 68 -1\n\nddcb3d  SRL (IX+d),L*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 be\n   11 MC 0003\n   14 MR 0003 3d\n   14 MC 0003\n   15 MC 0003\n   16 MC 02de\n   19 MR 02de 58\n   19 MC 02de\n   20 MC 02de\n   23 MW 02de 2c\n2a28 6e6e cfbd 1d2c 0000 0000 0000 0000 0320 6ab0 0000 0004\n00 02 0 0 0 0 23\n02de 2c -1\n\nddcb3e  SRL (IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 0a\n   11 MC 0003\n   14 MR 0003 3e\n   14 MC 0003\n   15 MC 0003\n   16 MC 7854\n   19 MR 7854 5d\n   19 MC 7854\n   20 MC 7854\n   23 MW 7854 2e\n392d b26e b670 b8a2 0000 0000 0000 0000 784a 7840 0000 0004\n00 02 0 0 0 0 23\n7854 2e -1\n\nddcb3f  SRL (IX+d),A*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 31\n   11 MC 0003\n   14 MR 0003 3f\n   14 MC 0003\n   15 MC 0003\n   16 MC 34b9\n   19 MR 34b9 04\n   19 MC 34b9\n   20 MC 34b9\n   23 MW 34b9 02\n0200 429d d8c0 e069 0000 0000 0000 0000 3488 7150 0000 0004\n00 02 0 0 0 0 23\n34b9 02 -1\n\nddcb40  BIT 0,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 bd\n   11 MC 0003\n   14 MR 0003 40\n   14 MC 0003\n   15 MC 0003\n   16 MC 8bbe\n   19 MR 8bbe e7\n   19 MC 8bbe\n1119 f6ba 079e 0e41 0000 0000 0000 0000 8c01 cd21 0000 0004\n00 02 0 0 0 0 20\n\nddcb41  BIT 0,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 52\n   11 MC 0003\n   14 MR 0003 41\n   14 MC 0003\n   15 MC 0003\n   16 MC ce21\n   19 MR ce21 75\n   19 MC ce21\n2219 c4b0 575b 66b4 0000 0000 0000 0000 cdcf a25c 0000 0004\n00 02 0 0 0 0 20\n\nddcb42  BIT 0,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 1e\n   11 MC 0003\n   14 MR 0003 42\n   14 MC 0003\n   15 MC 0003\n   16 MC f058\n   19 MR f058 90\n   19 MC f058\naf74 7720 aa95 3b0a 0000 0000 0000 0000 f03a 856a 0000 0004\n00 02 0 0 0 0 20\n\nddcb43  BIT 0,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 bc\n   11 MC 0003\n   14 MR 0003 43\n   14 MC 0003\n   15 MC 0003\n   16 MC e872\n   19 MR e872 6b\n   19 MC e872\n7f38 b699 5e71 1827 0000 0000 0000 0000 e8b6 96a8 0000 0004\n00 02 0 0 0 0 20\n\nddcb44  BIT 0,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 e8\n   11 MC 0003\n   14 MR 0003 44\n   14 MC 0003\n   15 MC 0003\n   16 MC edf2\n   19 MR edf2 62\n   19 MC edf2\n5f7c de05 12fd f73b 0000 0000 0000 0000 ee0a 6634 0000 0004\n00 02 0 0 0 0 20\n\nddcb45  BIT 0,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 02\n   11 MC 0003\n   14 MR 0003 45\n   14 MC 0003\n   15 MC 0003\n   16 MC a2c0\n   19 MR a2c0 55\n   19 MC a2c0\nea31 699c 47d3 89c3 0000 0000 0000 0000 a2be d81e 0000 0004\n00 02 0 0 0 0 20\n\nddcb46  BIT 0,(IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 e2\n   11 MC 0003\n   14 MR 0003 46\n   14 MC 0003\n   15 MC 0003\n   16 MC a381\n   19 MR a381 d5\n   19 MC a381\n6030 ac1d 4173 f92a 0000 0000 0000 0000 a39f 12e5 0000 0004\n00 02 0 0 0 0 20\n\nddcb47  BIT 0,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 7a\n   11 MC 0003\n   14 MR 0003 47\n   14 MC 0003\n   15 MC 0003\n   16 MC 52a1\n   19 MR 52a1 6a\n   19 MC 52a1\n1b54 f7c0 22f6 5253 0000 0000 0000 0000 5227 919d 0000 0004\n00 02 0 0 0 0 20\n\nddcb48  BIT 1,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 13\n   11 MC 0003\n   14 MR 0003 48\n   14 MC 0003\n   15 MC 0003\n   16 MC 2759\n   19 MR 2759 a8\n   19 MC 2759\n7274 4509 d68f 3b3d 0000 0000 0000 0000 2746 7f97 0000 0004\n00 02 0 0 0 0 20\n\nddcb49  BIT 1,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 94\n   11 MC 0003\n   14 MR 0003 49\n   14 MC 0003\n   15 MC 0003\n   16 MC 415a\n   19 MR 415a 26\n   19 MC 415a\n7f11 da22 ea9c f480 0000 0000 0000 0000 41c6 75a9 0000 0004\n00 02 0 0 0 0 20\n\nddcb4a  BIT 1,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 3b\n   11 MC 0003\n   14 MR 0003 4a\n   14 MC 0003\n   15 MC 0003\n   16 MC c026\n   19 MR c026 b5\n   19 MC c026\nf155 e6c3 5a42 8b21 0000 0000 0000 0000 bfeb e383 0000 0004\n00 02 0 0 0 0 20\n\nddcb4b  BIT 1,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 b0\n   11 MC 0003\n   14 MR 0003 4b\n   14 MC 0003\n   15 MC 0003\n   16 MC c1e9\n   19 MR c1e9 18\n   19 MC c1e9\n1054 880a 52b2 fb1b 0000 0000 0000 0000 c239 6b40 0000 0004\n00 02 0 0 0 0 20\n\nddcb4c  BIT 1,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 97\n   11 MC 0003\n   14 MR 0003 4c\n   14 MC 0003\n   15 MC 0003\n   16 MC 86e3\n   19 MR 86e3 63\n   19 MC 86e3\n0510 bc63 f081 0a55 0000 0000 0000 0000 874c 80a3 0000 0004\n00 02 0 0 0 0 20\n\nddcb4d  BIT 1,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 15\n   11 MC 0003\n   14 MR 0003 4d\n   14 MC 0003\n   15 MC 0003\n   16 MC 7d3f\n   19 MR 7d3f 60\n   19 MC 7d3f\n7f7c 32b4 03d5 ef66 0000 0000 0000 0000 7d2a 03bc 0000 0004\n00 02 0 0 0 0 20\n\nddcb4e  BIT 1,(IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 b0\n   11 MC 0003\n   14 MR 0003 4e\n   14 MC 0003\n   15 MC 0003\n   16 MC ea8e\n   19 MR ea8e 3b\n   19 MC ea8e\n7c39 fa92 b4d0 9f23 0000 0000 0000 0000 eade 1785 0000 0004\n00 02 0 0 0 0 20\n\nddcb4f  BIT 1,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 8b\n   11 MC 0003\n   14 MR 0003 4f\n   14 MC 0003\n   15 MC 0003\n   16 MC 884b\n   19 MR 884b 4c\n   19 MC 884b\n725c 257b db73 2478 0000 0000 0000 0000 88c0 f151 0000 0004\n00 02 0 0 0 0 20\n\nddcb50  BIT 2,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 12\n   11 MC 0003\n   14 MR 0003 50\n   14 MC 0003\n   15 MC 0003\n   16 MC db04\n   19 MR db04 00\n   19 MC db04\n355c 8e51 406c 2e3c 0000 0000 0000 0000 daf2 413c 0000 0004\n00 02 0 0 0 0 20\n\nddcb51  BIT 2,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 18\n   11 MC 0003\n   14 MR 0003 51\n   14 MC 0003\n   15 MC 0003\n   16 MC 84ca\n   19 MR 84ca 1c\n   19 MC 84ca\na610 ba85 c88c e86c 0000 0000 0000 0000 84b2 cd8e 0000 0004\n00 02 0 0 0 0 20\n\nddcb52  BIT 2,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 42\n   11 MC 0003\n   14 MR 0003 52\n   14 MC 0003\n   15 MC 0003\n   16 MC 6198\n   19 MR 6198 53\n   19 MC 6198\ncb74 1220 1103 a868 0000 0000 0000 0000 6156 cfac 0000 0004\n00 02 0 0 0 0 20\n\nddcb53  BIT 2,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 e3\n   11 MC 0003\n   14 MR 0003 53\n   14 MC 0003\n   15 MC 0003\n   16 MC ae28\n   19 MR ae28 d6\n   19 MC ae28\n5e39 569e f76d 88c6 0000 0000 0000 0000 ae45 623e 0000 0004\n00 02 0 0 0 0 20\n\nddcb54  BIT 2,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 7d\n   11 MC 0003\n   14 MR 0003 54\n   14 MC 0003\n   15 MC 0003\n   16 MC f052\n   19 MR f052 5d\n   19 MC f052\nc331 76fe f1ff 416e 0000 0000 0000 0000 efd5 7576 0000 0004\n00 02 0 0 0 0 20\n\nddcb55  BIT 2,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 88\n   11 MC 0003\n   14 MR 0003 55\n   14 MC 0003\n   15 MC 0003\n   16 MC f2da\n   19 MR f2da 03\n   19 MC f2da\n7074 dcd0 8345 d498 0000 0000 0000 0000 f352 a88b 0000 0004\n00 02 0 0 0 0 20\n\nddcb56  BIT 2,(IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 57\n   11 MC 0003\n   14 MR 0003 56\n   14 MC 0003\n   15 MC 0003\n   16 MC 6d87\n   19 MR 6d87 61\n   19 MC 6d87\n917c 2cb8 571c f4fd 0000 0000 0000 0000 6d30 aec2 0000 0004\n00 02 0 0 0 0 20\n\nddcb57  BIT 2,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 06\n   11 MC 0003\n   14 MR 0003 57\n   14 MC 0003\n   15 MC 0003\n   16 MC 5839\n   19 MR 5839 1d\n   19 MC 5839\n3c19 541a 027c c0b4 0000 0000 0000 0000 5833 160a 0000 0004\n00 02 0 0 0 0 20\n\nddcb58  BIT 3,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 83\n   11 MC 0003\n   14 MR 0003 58\n   14 MC 0003\n   15 MC 0003\n   16 MC 69c9\n   19 MR 69c9 0f\n   19 MC 69c9\nc638 e1a8 9d6c bec3 0000 0000 0000 0000 6a46 b66c 0000 0004\n00 02 0 0 0 0 20\n\nddcb59  BIT 3,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 db\n   11 MC 0003\n   14 MR 0003 59\n   14 MC 0003\n   15 MC 0003\n   16 MC 9170\n   19 MR 9170 10\n   19 MC 9170\nad55 9bda b7ee 63c4 0000 0000 0000 0000 9195 9703 0000 0004\n00 02 0 0 0 0 20\n\nddcb5a  BIT 3,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 d1\n   11 MC 0003\n   14 MR 0003 5a\n   14 MC 0003\n   15 MC 0003\n   16 MC 0db1\n   19 MR 0db1 be\n   19 MC 0db1\n8018 5105 36b0 a37c 0000 0000 0000 0000 0de0 ce7f 0000 0004\n00 02 0 0 0 0 20\n\nddcb5b  BIT 3,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 d5\n   11 MC 0003\n   14 MR 0003 5b\n   14 MC 0003\n   15 MC 0003\n   16 MC 6282\n   19 MR 6282 67\n   19 MC 6282\n2a75 083d 1409 06ba 0000 0000 0000 0000 62ad baff 0000 0004\n00 02 0 0 0 0 20\n\nddcb5c  BIT 3,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 5c\n   11 MC 0003\n   14 MR 0003 5c\n   14 MC 0003\n   15 MC 0003\n   16 MC 9e22\n   19 MR 9e22 c9\n   19 MC 9e22\n4c18 e502 d23c 6da8 0000 0000 0000 0000 9dc6 6f04 0000 0004\n00 02 0 0 0 0 20\n\nddcb5d  BIT 3,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 ff\n   11 MC 0003\n   14 MR 0003 5d\n   14 MC 0003\n   15 MC 0003\n   16 MC d192\n   19 MR d192 0d\n   19 MC d192\n7e11 511b 3cfa 60d3 0000 0000 0000 0000 d193 3fe9 0000 0004\n00 02 0 0 0 0 20\n\nddcb5e  BIT 3,(IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 62\n   11 MC 0003\n   14 MR 0003 5e\n   14 MC 0003\n   15 MC 0003\n   16 MC ed76\n   19 MR ed76 a7\n   19 MC ed76\nce7d 0235 e2b1 7a4c 0000 0000 0000 0000 ed14 d0d6 0000 0004\n00 02 0 0 0 0 20\n\nddcb5f  BIT 3,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 3f\n   11 MC 0003\n   14 MR 0003 5f\n   14 MC 0003\n   15 MC 0003\n   16 MC df85\n   19 MR df85 9e\n   19 MC df85\n0919 20a8 52e1 d783 0000 0000 0000 0000 df46 da41 0000 0004\n00 02 0 0 0 0 20\n\nddcb60  BIT 4,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 65\n   11 MC 0003\n   14 MR 0003 60\n   14 MC 0003\n   15 MC 0003\n   16 MC 3307\n   19 MR 3307 2e\n   19 MC 3307\n4274 0713 dc90 2c89 0000 0000 0000 0000 32a2 c4d4 0000 0004\n00 02 0 0 0 0 20\n\nddcb61  BIT 4,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 a8\n   11 MC 0003\n   14 MR 0003 61\n   14 MC 0003\n   15 MC 0003\n   16 MC 3673\n   19 MR 3673 bc\n   19 MC 3673\n1b30 1403 8b9b c221 0000 0000 0000 0000 36cb 93d4 0000 0004\n00 02 0 0 0 0 20\n\nddcb62  BIT 4,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 d9\n   11 MC 0003\n   14 MR 0003 62\n   14 MC 0003\n   15 MC 0003\n   16 MC 0aa5\n   19 MR 0aa5 ea\n   19 MC 0aa5\n365d 4055 650a 3f98 0000 0000 0000 0000 0acc a102 0000 0004\n00 02 0 0 0 0 20\n\nddcb63  BIT 4,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 79\n   11 MC 0003\n   14 MR 0003 63\n   14 MC 0003\n   15 MC 0003\n   16 MC e6f2\n   19 MR e6f2 83\n   19 MC e6f2\n6574 08df 3ceb 6d24 0000 0000 0000 0000 e679 f98e 0000 0004\n00 02 0 0 0 0 20\n\nddcb64  BIT 4,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 71\n   11 MC 0003\n   14 MR 0003 64\n   14 MC 0003\n   15 MC 0003\n   16 MC ed6c\n   19 MR ed6c 52\n   19 MC ed6c\n3c38 e2a7 6da9 c346 0000 0000 0000 0000 ecfb 85b6 0000 0004\n00 02 0 0 0 0 20\n\nddcb65  BIT 4,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 67\n   11 MC 0003\n   14 MR 0003 65\n   14 MC 0003\n   15 MC 0003\n   16 MC 77e0\n   19 MR 77e0 f5\n   19 MC 77e0\n0931 0abb 3afa 91f5 0000 0000 0000 0000 7779 aef5 0000 0004\n00 02 0 0 0 0 20\n\nddcb66  BIT 4,(IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 63\n   11 MC 0003\n   14 MR 0003 66\n   14 MC 0003\n   15 MC 0003\n   16 MC ee78\n   19 MR ee78 70\n   19 MC ee78\ncc38 d301 9b66 40fb 0000 0000 0000 0000 ee15 0d23 0000 0004\n00 02 0 0 0 0 20\n\nddcb67  BIT 4,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 d7\n   11 MC 0003\n   14 MR 0003 67\n   14 MC 0003\n   15 MC 0003\n   16 MC ee78\n   19 MR ee78 06\n   19 MC ee78\nec7d 342f be3e a79b 0000 0000 0000 0000 eea1 dfae 0000 0004\n00 02 0 0 0 0 20\n\nddcb68  BIT 5,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 b1\n   11 MC 0003\n   14 MR 0003 68\n   14 MC 0003\n   15 MC 0003\n   16 MC e919\n   19 MR e919 20\n   19 MC e919\n8e39 0063 49ad b7d4 0000 0000 0000 0000 e968 864e 0000 0004\n00 02 0 0 0 0 20\n\nddcb69  BIT 5,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 e8\n   11 MC 0003\n   14 MR 0003 69\n   14 MC 0003\n   15 MC 0003\n   16 MC 33dc\n   19 MR 33dc 4f\n   19 MC 33dc\n9f75 42b5 74fe 1116 0000 0000 0000 0000 33f4 46c2 0000 0004\n00 02 0 0 0 0 20\n\nddcb6a  BIT 5,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 33\n   11 MC 0003\n   14 MR 0003 6a\n   14 MC 0003\n   15 MC 0003\n   16 MC 86e9\n   19 MR 86e9 1c\n   19 MC 86e9\n4654 0bd8 0018 1ac3 0000 0000 0000 0000 86b6 1dd2 0000 0004\n00 02 0 0 0 0 20\n\nddcb6b  BIT 5,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 11\n   11 MC 0003\n   14 MR 0003 6b\n   14 MC 0003\n   15 MC 0003\n   16 MC 188c\n   19 MR 188c bc\n   19 MC 188c\n7a18 f79f a78e f867 0000 0000 0000 0000 187b 0023 0000 0004\n00 02 0 0 0 0 20\n\nddcb6c  BIT 5,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 5e\n   11 MC 0003\n   14 MR 0003 6c\n   14 MC 0003\n   15 MC 0003\n   16 MC 3e7f\n   19 MR 3e7f 2a\n   19 MC 3e7f\ndd39 1f1e c1e1 0ea7 0000 0000 0000 0000 3e21 f544 0000 0004\n00 02 0 0 0 0 20\n\nddcb6d  BIT 5,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 dd\n   11 MC 0003\n   14 MR 0003 6d\n   14 MC 0003\n   15 MC 0003\n   16 MC e2f1\n   19 MR e2f1 41\n   19 MC e2f1\nde75 9ae4 fd24 b3c2 0000 0000 0000 0000 e314 ad84 0000 0004\n00 02 0 0 0 0 20\n\nddcb6e  BIT 5,(IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 b2\n   11 MC 0003\n   14 MR 0003 6e\n   14 MC 0003\n   15 MC 0003\n   16 MC 3038\n   19 MR 3038 3f\n   19 MC 3038\nca31 9f16 c700 1dce 0000 0000 0000 0000 3086 d68e 0000 0004\n00 02 0 0 0 0 20\n\nddcb6f  BIT 5,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 be\n   11 MC 0003\n   14 MR 0003 6f\n   14 MC 0003\n   15 MC 0003\n   16 MC fbd9\n   19 MR fbd9 56\n   19 MC fbd9\nd47d 0b39 3e2e c06e 0000 0000 0000 0000 fc1b d592 0000 0004\n00 02 0 0 0 0 20\n\nddcb70  BIT 6,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 b5\n   11 MC 0003\n   14 MR 0003 70\n   14 MC 0003\n   15 MC 0003\n   16 MC 03e1\n   19 MR 03e1 74\n   19 MC 03e1\nf911 09b8 43f8 2a76 0000 0000 0000 0000 042c 7f2d 0000 0004\n00 02 0 0 0 0 20\n\nddcb71  BIT 6,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 f7\n   11 MC 0003\n   14 MR 0003 71\n   14 MC 0003\n   15 MC 0003\n   16 MC 1b2a\n   19 MR 1b2a 08\n   19 MC 1b2a\nac5c 36ad 34cb f950 0000 0000 0000 0000 1b33 aa23 0000 0004\n00 02 0 0 0 0 20\n\nddcb72  BIT 6,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 22\n   11 MC 0003\n   14 MR 0003 72\n   14 MC 0003\n   15 MC 0003\n   16 MC ce47\n   19 MR ce47 08\n   19 MC ce47\nb15d f1e4 9984 c7fb 0000 0000 0000 0000 ce25 c5b6 0000 0004\n00 02 0 0 0 0 20\n\nddcb73  BIT 6,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 12\n   11 MC 0003\n   14 MR 0003 73\n   14 MC 0003\n   15 MC 0003\n   16 MC 6454\n   19 MR 6454 3c\n   19 MC 6454\n2174 592d f406 e21f 0000 0000 0000 0000 6442 cf58 0000 0004\n00 02 0 0 0 0 20\n\nddcb74  BIT 6,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 08\n   11 MC 0003\n   14 MR 0003 74\n   14 MC 0003\n   15 MC 0003\n   16 MC 7dc9\n   19 MR 7dc9 be\n   19 MC 7dc9\n667c 64c1 dbe5 eb48 0000 0000 0000 0000 7dc1 c1fb 0000 0004\n00 02 0 0 0 0 20\n\nddcb75  BIT 6,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 5b\n   11 MC 0003\n   14 MR 0003 75\n   14 MC 0003\n   15 MC 0003\n   16 MC 6108\n   19 MR 6108 cf\n   19 MC 6108\n8730 580e 00dd f4c6 0000 0000 0000 0000 60ad 9b60 0000 0004\n00 02 0 0 0 0 20\n\nddcb76  BIT 6,(IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 73\n   11 MC 0003\n   14 MR 0003 76\n   14 MC 0003\n   15 MC 0003\n   16 MC 7efd\n   19 MR 7efd 1e\n   19 MC 7efd\n657c 5cc2 3058 e258 0000 0000 0000 0000 7e8a b296 0000 0004\n00 02 0 0 0 0 20\n\nddcb77  BIT 6,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 7f\n   11 MC 0003\n   14 MR 0003 77\n   14 MC 0003\n   15 MC 0003\n   16 MC 05b6\n   19 MR 05b6 97\n   19 MC 05b6\ne354 47a0 c510 cf0a 0000 0000 0000 0000 0537 b242 0000 0004\n00 02 0 0 0 0 20\n\nddcb78  BIT 7,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 70\n   11 MC 0003\n   14 MR 0003 78\n   14 MC 0003\n   15 MC 0003\n   16 MC 9407\n   19 MR 9407 76\n   19 MC 9407\n4255 24f6 1632 8a4f 0000 0000 0000 0000 9397 846c 0000 0004\n00 02 0 0 0 0 20\n\nddcb79  BIT 7,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 c3\n   11 MC 0003\n   14 MR 0003 79\n   14 MC 0003\n   15 MC 0003\n   16 MC 41a1\n   19 MR 41a1 b8\n   19 MC 41a1\ne690 eeaa 41f7 5da2 0000 0000 0000 0000 41de 4189 0000 0004\n00 02 0 0 0 0 20\n\nddcb7a  BIT 7,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 3f\n   11 MC 0003\n   14 MR 0003 7a\n   14 MC 0003\n   15 MC 0003\n   16 MC 0ae8\n   19 MR 0ae8 eb\n   19 MC 0ae8\nca99 56aa 6a06 6cd7 0000 0000 0000 0000 0aa9 9812 0000 0004\n00 02 0 0 0 0 20\n\nddcb7b  BIT 7,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 88\n   11 MC 0003\n   14 MR 0003 7b\n   14 MC 0003\n   15 MC 0003\n   16 MC 4fc8\n   19 MR 4fc8 22\n   19 MC 4fc8\nae5d 0227 721f 52a1 0000 0000 0000 0000 5040 b98a 0000 0004\n00 02 0 0 0 0 20\n\nddcb7c  BIT 7,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 9e\n   11 MC 0003\n   14 MR 0003 7c\n   14 MC 0003\n   15 MC 0003\n   16 MC 6821\n   19 MR 6821 3a\n   19 MC 6821\n8a7c a2f1 239a d5cc 0000 0000 0000 0000 6883 b050 0000 0004\n00 02 0 0 0 0 20\n\nddcb7d  BIT 7,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 29\n   11 MC 0003\n   14 MR 0003 7d\n   14 MC 0003\n   15 MC 0003\n   16 MC b04a\n   19 MR b04a 2c\n   19 MC b04a\nc375 cf33 1010 98e6 0000 0000 0000 0000 b021 0356 0000 0004\n00 02 0 0 0 0 20\n\nddcb7e  BIT 7,(IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 4f\n   11 MC 0003\n   14 MR 0003 7e\n   14 MC 0003\n   15 MC 0003\n   16 MC cf3f\n   19 MR cf3f f2\n   19 MC cf3f\n9a99 2f6e 0d0d a83f 0000 0000 0000 0000 cef0 8c15 0000 0004\n00 02 0 0 0 0 20\n\nddcb7f  BIT 7,(IX+d)*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 75\n   11 MC 0003\n   14 MR 0003 7f\n   14 MC 0003\n   15 MC 0003\n   16 MC 5f37\n   19 MR 5f37 a2\n   19 MC 5f37\n5399 1f4e 4837 21b6 0000 0000 0000 0000 5ec2 80c3 0000 0004\n00 02 0 0 0 0 20\n\nddcb80  RES 0,(IX+d),B*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 70\n   11 MC 0003\n   14 MR 0003 80\n   14 MC 0003\n   15 MC 0003\n   16 MC ad35\n   19 MR ad35 30\n   19 MC ad35\n   20 MC ad35\n   23 MW ad35 30\n6319 30f9 c84b bcf2 0000 0000 0000 0000 acc5 a4ed 0000 0004\n00 02 0 0 0 0 23\n\nddcb81  RES 0,(IX+d),C*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 2a\n   11 MC 0003\n   14 MR 0003 81\n   14 MC 0003\n   15 MC 0003\n   16 MC bdfd\n   19 MR bdfd 24\n   19 MC bdfd\n   20 MC bdfd\n   23 MW bdfd 24\nfae1 5a24 9502 dc9b 0000 0000 0000 0000 bdd3 1a52 0000 0004\n00 02 0 0 0 0 23\n\nddcb82  RES 0,(IX+d),D*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 9a\n   11 MC 0003\n   14 MR 0003 82\n   14 MC 0003\n   15 MC 0003\n   16 MC 5e0e\n   19 MR 5e0e 51\n   19 MC 5e0e\n   20 MC 5e0e\n   23 MW 5e0e 50\ndaf6 3260 50ac 1d47 0000 0000 0000 0000 5e74 35e2 0000 0004\n00 02 0 0 0 0 23\n5e0e 50 -1\n\nddcb83  RES 0,(IX+d),E*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 0e\n   11 MC 0003\n   14 MR 0003 83\n   14 MC 0003\n   15 MC 0003\n   16 MC 344f\n   19 MR 344f 01\n   19 MC 344f\n   20 MC 344f\n   23 MW 344f 00\n8e7c 5586 8c00 fb00 0000 0000 0000 0000 3441 d365 0000 0004\n00 02 0 0 0 0 23\n344f 00 -1\n\nddcb84  RES 0,(IX+d),H*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 47\n   11 MC 0003\n   14 MR 0003 84\n   14 MC 0003\n   15 MC 0003\n   16 MC 016a\n   19 MR 016a b0\n   19 MC 016a\n   20 MC 016a\n   23 MW 016a b0\nc1b3 4874 c535 b01c 0000 0000 0000 0000 0123 dd28 0000 0004\n00 02 0 0 0 0 23\n\nddcb85  RES 0,(IX+d),L*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 6c\n   11 MC 0003\n   14 MR 0003 85\n   14 MC 0003\n   15 MC 0003\n   16 MC 0c0f\n   19 MR 0c0f de\n   19 MC 0c0f\n   20 MC 0c0f\n   23 MW 0c0f de\n0928 b0db 4e07 a7de 0000 0000 0000 0000 0ba3 c61c 0000 0004\n00 02 0 0 0 0 23\n\nddcb86  RES 0,(IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 5c\n   11 MC 0003\n   14 MR 0003 86\n   14 MC 0003\n   15 MC 0003\n   16 MC 1121\n   19 MR 1121 7c\n   19 MC 1121\n   20 MC 1121\n   23 MW 1121 7c\n4515 de09 3ce7 1fde 0000 0000 0000 0000 10c5 33ed 0000 0004\n00 02 0 0 0 0 23\n\nddcb87  RES 0,(IX+d),A*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 02\n   11 MC 0003\n   14 MR 0003 87\n   14 MC 0003\n   15 MC 0003\n   16 MC ede8\n   19 MR ede8 c4\n   19 MC ede8\n   20 MC ede8\n   23 MW ede8 c4\nc45e a733 d1dd 1603 0000 0000 0000 0000 ede6 e5fb 0000 0004\n00 02 0 0 0 0 23\n\nddcb88  RES 1,(IX+d),B*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 9b\n   11 MC 0003\n   14 MR 0003 88\n   14 MC 0003\n   15 MC 0003\n   16 MC 8729\n   19 MR 8729 7c\n   19 MC 8729\n   20 MC 8729\n   23 MW 8729 7c\ne4fa 7c25 c266 1b13 0000 0000 0000 0000 878e e695 0000 0004\n00 02 0 0 0 0 23\n\nddcb89  RES 1,(IX+d),C*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 2b\n   11 MC 0003\n   14 MR 0003 89\n   14 MC 0003\n   15 MC 0003\n   16 MC 8f69\n   19 MR 8f69 cf\n   19 MC 8f69\n   20 MC 8f69\n   23 MW 8f69 cd\n933b 6fcd a3a8 2634 0000 0000 0000 0000 8f3e 7727 0000 0004\n00 02 0 0 0 0 23\n8f69 cd -1\n\nddcb8a  RES 1,(IX+d),D*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 0a\n   11 MC 0003\n   14 MR 0003 8a\n   14 MC 0003\n   15 MC 0003\n   16 MC 39b3\n   19 MR 39b3 ea\n   19 MC 39b3\n   20 MC 39b3\n   23 MW 39b3 e8\n6759 ad1e e871 ce52 0000 0000 0000 0000 39a9 38a0 0000 0004\n00 02 0 0 0 0 23\n39b3 e8 -1\n\nddcb8b  RES 1,(IX+d),E*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 62\n   11 MC 0003\n   14 MR 0003 8b\n   14 MC 0003\n   15 MC 0003\n   16 MC 16e7\n   19 MR 16e7 8a\n   19 MC 16e7\n   20 MC 16e7\n   23 MW 16e7 88\n3da2 1833 0388 07e9 0000 0000 0000 0000 1685 d790 0000 0004\n00 02 0 0 0 0 23\n16e7 88 -1\n\nddcb8c  RES 1,(IX+d),H*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 e8\n   11 MC 0003\n   14 MR 0003 8c\n   14 MC 0003\n   15 MC 0003\n   16 MC c68a\n   19 MR c68a 3e\n   19 MC c68a\n   20 MC c68a\n   23 MW c68a 3c\na625 ed31 3946 3cdc 0000 0000 0000 0000 c6a2 7ad6 0000 0004\n00 02 0 0 0 0 23\nc68a 3c -1\n\nddcb8d  RES 1,(IX+d),L*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 cc\n   11 MC 0003\n   14 MR 0003 8d\n   14 MC 0003\n   15 MC 0003\n   16 MC 22b2\n   19 MR 22b2 9e\n   19 MC 22b2\n   20 MC 22b2\n   23 MW 22b2 9c\n016b 5802 a683 259c 0000 0000 0000 0000 22e6 33bb 0000 0004\n00 02 0 0 0 0 23\n22b2 9c -1\n\nddcb8e  RES 1,(IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 0a\n   11 MC 0003\n   14 MR 0003 8e\n   14 MC 0003\n   15 MC 0003\n   16 MC d2f2\n   19 MR d2f2 03\n   19 MC d2f2\n   20 MC d2f2\n   23 MW d2f2 01\nf4f4 f3a8 2843 82cb 0000 0000 0000 0000 d2e8 d367 0000 0004\n00 02 0 0 0 0 23\nd2f2 01 -1\n\nddcb8f  RES 1,(IX+d),A*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 7b\n   11 MC 0003\n   14 MR 0003 8f\n   14 MC 0003\n   15 MC 0003\n   16 MC 4079\n   19 MR 4079 96\n   19 MC 4079\n   20 MC 4079\n   23 MW 4079 94\n941a 8ae2 269b cb2f 0000 0000 0000 0000 3ffe 75dd 0000 0004\n00 02 0 0 0 0 23\n4079 94 -1\n\nddcb90  RES 2,(IX+d),B*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 04\n   11 MC 0003\n   14 MR 0003 90\n   14 MC 0003\n   15 MC 0003\n   16 MC b505\n   19 MR b505 46\n   19 MC b505\n   20 MC b505\n   23 MW b505 42\nc167 42fc 42e7 9e14 0000 0000 0000 0000 b501 84fe 0000 0004\n00 02 0 0 0 0 23\nb505 42 -1\n\nddcb91  RES 2,(IX+d),C*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 11\n   11 MC 0003\n   14 MR 0003 91\n   14 MC 0003\n   15 MC 0003\n   16 MC c998\n   19 MR c998 83\n   19 MC c998\n   20 MC c998\n   23 MW c998 83\ne85e cc83 d249 ea3b 0000 0000 0000 0000 c987 c4d1 0000 0004\n00 02 0 0 0 0 23\n\nddcb92  RES 2,(IX+d),D*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 4b\n   11 MC 0003\n   14 MR 0003 92\n   14 MC 0003\n   15 MC 0003\n   16 MC 91b1\n   19 MR 91b1 aa\n   19 MC 91b1\n   20 MC 91b1\n   23 MW 91b1 aa\n28a3 85ff aa28 47a5 0000 0000 0000 0000 9166 e755 0000 0004\n00 02 0 0 0 0 23\n\nddcb93  RES 2,(IX+d),E*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 03\n   11 MC 0003\n   14 MR 0003 93\n   14 MC 0003\n   15 MC 0003\n   16 MC ac31\n   19 MR ac31 93\n   19 MC ac31\n   20 MC ac31\n   23 MW ac31 93\n58ac c88b 6d93 dbdd 0000 0000 0000 0000 ac2e 5199 0000 0004\n00 02 0 0 0 0 23\n\nddcb94  RES 2,(IX+d),H*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 11\n   11 MC 0003\n   14 MR 0003 94\n   14 MC 0003\n   15 MC 0003\n   16 MC 5e95\n   19 MR 5e95 b7\n   19 MC 5e95\n   20 MC 5e95\n   23 MW 5e95 b3\ne38d 35a5 8d07 b3b8 0000 0000 0000 0000 5e84 5f24 0000 0004\n00 02 0 0 0 0 23\n5e95 b3 -1\n\nddcb95  RES 2,(IX+d),L*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 e6\n   11 MC 0003\n   14 MR 0003 95\n   14 MC 0003\n   15 MC 0003\n   16 MC fb5a\n   19 MR fb5a c6\n   19 MC fb5a\n   20 MC fb5a\n   23 MW fb5a c2\n41f4 9536 dd7d 49c2 0000 0000 0000 0000 fb74 f17d 0000 0004\n00 02 0 0 0 0 23\nfb5a c2 -1\n\nddcb96  RES 2,(IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 d5\n   11 MC 0003\n   14 MR 0003 96\n   14 MC 0003\n   15 MC 0003\n   16 MC 7a56\n   19 MR 7a56 ae\n   19 MC 7a56\n   20 MC 7a56\n   23 MW 7a56 aa\n4a9e 42ef 32d7 18cf 0000 0000 0000 0000 7a81 bb1d 0000 0004\n00 02 0 0 0 0 23\n7a56 aa -1\n\nddcb97  RES 2,(IX+d),A*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 92\n   11 MC 0003\n   14 MR 0003 97\n   14 MC 0003\n   15 MC 0003\n   16 MC 840e\n   19 MR 840e 23\n   19 MC 840e\n   20 MC 840e\n   23 MW 840e 23\n23d3 89f0 73c7 0b1a 0000 0000 0000 0000 847c 4b86 0000 0004\n00 02 0 0 0 0 23\n\nddcb98  RES 3,(IX+d),B*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 dc\n   11 MC 0003\n   14 MR 0003 98\n   14 MC 0003\n   15 MC 0003\n   16 MC 03fa\n   19 MR 03fa 58\n   19 MC 03fa\n   20 MC 03fa\n   23 MW 03fa 50\n6e22 50fd 9fdc 3aed 0000 0000 0000 0000 041e fd79 0000 0004\n00 02 0 0 0 0 23\n03fa 50 -1\n\nddcb99  RES 3,(IX+d),C*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 6d\n   11 MC 0003\n   14 MR 0003 99\n   14 MC 0003\n   15 MC 0003\n   16 MC 0a6a\n   19 MR 0a6a ce\n   19 MC 0a6a\n   20 MC 0a6a\n   23 MW 0a6a c6\na132 38c6 1515 2830 0000 0000 0000 0000 09fd 0473 0000 0004\n00 02 0 0 0 0 23\n0a6a c6 -1\n\nddcb9a  RES 3,(IX+d),D*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 8a\n   11 MC 0003\n   14 MR 0003 9a\n   14 MC 0003\n   15 MC 0003\n   16 MC 6832\n   19 MR 6832 a8\n   19 MC 6832\n   20 MC 6832\n   23 MW 6832 a0\n783d 8f69 a0c4 e38f 0000 0000 0000 0000 68a8 391d 0000 0004\n00 02 0 0 0 0 23\n6832 a0 -1\n\nddcb9b  RES 3,(IX+d),E*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 97\n   11 MC 0003\n   14 MR 0003 9b\n   14 MC 0003\n   15 MC 0003\n   16 MC 0686\n   19 MR 0686 62\n   19 MC 0686\n   20 MC 0686\n   23 MW 0686 62\n955a c7b0 5362 aec6 0000 0000 0000 0000 06ef e991 0000 0004\n00 02 0 0 0 0 23\n\nddcb9c  RES 3,(IX+d),H*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 54\n   11 MC 0003\n   14 MR 0003 9c\n   14 MC 0003\n   15 MC 0003\n   16 MC 84cf\n   19 MR 84cf 1b\n   19 MC 84cf\n   20 MC 84cf\n   23 MW 84cf 13\naf69 f896 e791 13ee 0000 0000 0000 0000 847b 59ed 0000 0004\n00 02 0 0 0 0 23\n84cf 13 -1\n\nddcb9d  RES 3,(IX+d),L*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 0f\n   11 MC 0003\n   14 MR 0003 9d\n   14 MC 0003\n   15 MC 0003\n   16 MC e92f\n   19 MR e92f e8\n   19 MC e92f\n   20 MC e92f\n   23 MW e92f e0\n7d1e 5009 1248 38e0 0000 0000 0000 0000 e920 4fe6 0000 0004\n00 02 0 0 0 0 23\ne92f e0 -1\n\nddcb9e  RES 3,(IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 b5\n   11 MC 0003\n   14 MR 0003 9e\n   14 MC 0003\n   15 MC 0003\n   16 MC d870\n   19 MR d870 ee\n   19 MC d870\n   20 MC d870\n   23 MW d870 e6\nc207 b47c 0e16 e17f 0000 0000 0000 0000 d8bb bb99 0000 0004\n00 02 0 0 0 0 23\nd870 e6 -1\n\nddcb9f  RES 3,(IX+d),A*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 b8\n   11 MC 0003\n   14 MR 0003 9f\n   14 MC 0003\n   15 MC 0003\n   16 MC e5f4\n   19 MR e5f4 a6\n   19 MC e5f4\n   20 MC e5f4\n   23 MW e5f4 a6\na66b 7537 46bb 13c0 0000 0000 0000 0000 e63c 1d98 0000 0004\n00 02 0 0 0 0 23\n\nddcba0  RES 4,(IX+d),B*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 02\n   11 MC 0003\n   14 MR 0003 a0\n   14 MC 0003\n   15 MC 0003\n   16 MC a2f2\n   19 MR a2f2 39\n   19 MC a2f2\n   20 MC a2f2\n   23 MW a2f2 29\n0bbe 2900 8609 5352 0000 0000 0000 0000 a2f0 da02 0000 0004\n00 02 0 0 0 0 23\na2f2 29 -1\n\nddcba1  RES 4,(IX+d),C*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 f5\n   11 MC 0003\n   14 MR 0003 a1\n   14 MC 0003\n   15 MC 0003\n   16 MC 45b0\n   19 MR 45b0 d2\n   19 MC 45b0\n   20 MC 45b0\n   23 MW 45b0 c2\nad0a aac2 0f2d 832c 0000 0000 0000 0000 45bb a22d 0000 0004\n00 02 0 0 0 0 23\n45b0 c2 -1\n\nddcba2  RES 4,(IX+d),D*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 0e\n   11 MC 0003\n   14 MR 0003 a2\n   14 MC 0003\n   15 MC 0003\n   16 MC 6299\n   19 MR 6299 a1\n   19 MC 6299\n   20 MC 6299\n   23 MW 6299 a1\nf586 4a7d a1ab 26fc 0000 0000 0000 0000 628b 6c4d 0000 0004\n00 02 0 0 0 0 23\n\nddcba3  RES 4,(IX+d),E*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 2e\n   11 MC 0003\n   14 MR 0003 a3\n   14 MC 0003\n   15 MC 0003\n   16 MC 043b\n   19 MR 043b 04\n   19 MC 043b\n   20 MC 043b\n   23 MW 043b 04\nde5b a284 d404 c92d 0000 0000 0000 0000 040d 12c0 0000 0004\n00 02 0 0 0 0 23\n\nddcba4  RES 4,(IX+d),H*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 03\n   11 MC 0003\n   14 MR 0003 a4\n   14 MC 0003\n   15 MC 0003\n   16 MC fe50\n   19 MR fe50 27\n   19 MC fe50\n   20 MC fe50\n   23 MW fe50 27\ndfaa ae40 02c3 27b5 0000 0000 0000 0000 fe4d faa3 0000 0004\n00 02 0 0 0 0 23\n\nddcba5  RES 4,(IX+d),L*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 f6\n   11 MC 0003\n   14 MR 0003 a5\n   14 MC 0003\n   15 MC 0003\n   16 MC 7b1d\n   19 MR 7b1d 6b\n   19 MC 7b1d\n   20 MC 7b1d\n   23 MW 7b1d 6b\n1a15 04cb 4352 ee6b 0000 0000 0000 0000 7b27 38a0 0000 0004\n00 02 0 0 0 0 23\n\nddcba6  RES 4,(IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 27\n   11 MC 0003\n   14 MR 0003 a6\n   14 MC 0003\n   15 MC 0003\n   16 MC ae42\n   19 MR ae42 8f\n   19 MC ae42\n   20 MC ae42\n   23 MW ae42 8f\n5e46 b98a b822 04ca 0000 0000 0000 0000 ae1b 8730 0000 0004\n00 02 0 0 0 0 23\n\nddcba7  RES 4,(IX+d),A*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 f2\n   11 MC 0003\n   14 MR 0003 a7\n   14 MC 0003\n   15 MC 0003\n   16 MC 5eba\n   19 MR 5eba 87\n   19 MC 5eba\n   20 MC 5eba\n   23 MW 5eba 87\n87ed 7b11 8cb0 eb3d 0000 0000 0000 0000 5ec8 97cf 0000 0004\n00 02 0 0 0 0 23\n\nddcba8  RES 5,(IX+d),B*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 d0\n   11 MC 0003\n   14 MR 0003 a8\n   14 MC 0003\n   15 MC 0003\n   16 MC e81f\n   19 MR e81f 7e\n   19 MC e81f\n   20 MC e81f\n   23 MW e81f 5e\n5173 5e89 070d e8f9 0000 0000 0000 0000 e84f 55f0 0000 0004\n00 02 0 0 0 0 23\ne81f 5e -1\n\nddcba9  RES 5,(IX+d),C*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 9d\n   11 MC 0003\n   14 MR 0003 a9\n   14 MC 0003\n   15 MC 0003\n   16 MC 0f7a\n   19 MR 0f7a 1f\n   19 MC 0f7a\n   20 MC 0f7a\n   23 MW 0f7a 1f\n4fb8 cc1f 3e9a 2673 0000 0000 0000 0000 0fdd aef2 0000 0004\n00 02 0 0 0 0 23\n\nddcbaa  RES 5,(IX+d),D*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 9f\n   11 MC 0003\n   14 MR 0003 aa\n   14 MC 0003\n   15 MC 0003\n   16 MC 66e6\n   19 MR 66e6 50\n   19 MC 66e6\n   20 MC 66e6\n   23 MW 66e6 50\nfe76 6f96 50eb 0b21 0000 0000 0000 0000 6747 07ba 0000 0004\n00 02 0 0 0 0 23\n\nddcbab  RES 5,(IX+d),E*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 16\n   11 MC 0003\n   14 MR 0003 ab\n   14 MC 0003\n   15 MC 0003\n   16 MC 6698\n   19 MR 6698 eb\n   19 MC 6698\n   20 MC 6698\n   23 MW 6698 cb\n2eb4 36f1 8fcb 36af 0000 0000 0000 0000 6682 9d60 0000 0004\n00 02 0 0 0 0 23\n6698 cb -1\n\nddcbac  RES 5,(IX+d),H*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 c4\n   11 MC 0003\n   14 MR 0003 ac\n   14 MC 0003\n   15 MC 0003\n   16 MC a4a1\n   19 MR a4a1 44\n   19 MC a4a1\n   20 MC a4a1\n   23 MW a4a1 44\naf32 8ca8 6558 44d9 0000 0000 0000 0000 a4dd cd1f 0000 0004\n00 02 0 0 0 0 23\n\nddcbad  RES 5,(IX+d),L*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 49\n   11 MC 0003\n   14 MR 0003 ad\n   14 MC 0003\n   15 MC 0003\n   16 MC ef3e\n   19 MR ef3e 76\n   19 MC ef3e\n   20 MC ef3e\n   23 MW ef3e 56\nfcc9 69a7 0eed ea56 0000 0000 0000 0000 eef5 3ed2 0000 0004\n00 02 0 0 0 0 23\nef3e 56 -1\n\nddcbae  RES 5,(IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 6e\n   11 MC 0003\n   14 MR 0003 ae\n   14 MC 0003\n   15 MC 0003\n   16 MC b374\n   19 MR b374 5a\n   19 MC b374\n   20 MC b374\n   23 MW b374 5a\n5f7a 9c20 f013 c4b7 0000 0000 0000 0000 b306 15dd 0000 0004\n00 02 0 0 0 0 23\n\nddcbaf  RES 5,(IX+d),A*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 c2\n   11 MC 0003\n   14 MR 0003 af\n   14 MC 0003\n   15 MC 0003\n   16 MC 35db\n   19 MR 35db 15\n   19 MC 35db\n   20 MC 35db\n   23 MW 35db 15\n151e 2583 51fa d427 0000 0000 0000 0000 3619 9cef 0000 0004\n00 02 0 0 0 0 23\n\nddcbb0  RES 6,(IX+d),B*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 47\n   11 MC 0003\n   14 MR 0003 b0\n   14 MC 0003\n   15 MC 0003\n   16 MC 591e\n   19 MR 591e 1e\n   19 MC 591e\n   20 MC 591e\n   23 MW 591e 1e\nf43e 1e57 3bf3 0933 0000 0000 0000 0000 58d7 d89f 0000 0004\n00 02 0 0 0 0 23\n\nddcbb1  RES 6,(IX+d),C*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 86\n   11 MC 0003\n   14 MR 0003 b1\n   14 MC 0003\n   15 MC 0003\n   16 MC ad58\n   19 MR ad58 46\n   19 MC ad58\n   20 MC ad58\n   23 MW ad58 06\n35ef bb06 db46 046c 0000 0000 0000 0000 add2 2b6e 0000 0004\n00 02 0 0 0 0 23\nad58 06 -1\n\nddcbb2  RES 6,(IX+d),D*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 70\n   11 MC 0003\n   14 MR 0003 b2\n   14 MC 0003\n   15 MC 0003\n   16 MC e840\n   19 MR e840 48\n   19 MC e840\n   20 MC e840\n   23 MW e840 08\nc26c fd32 087f ab6c 0000 0000 0000 0000 e7d0 501f 0000 0004\n00 02 0 0 0 0 23\ne840 08 -1\n\nddcbb3  RES 6,(IX+d),E*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 de\n   11 MC 0003\n   14 MR 0003 b3\n   14 MC 0003\n   15 MC 0003\n   16 MC 53d9\n   19 MR 53d9 06\n   19 MC 53d9\n   20 MC 53d9\n   23 MW 53d9 06\n36ca b434 e206 f805 0000 0000 0000 0000 53fb b191 0000 0004\n00 02 0 0 0 0 23\n\nddcbb4  RES 6,(IX+d),H*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 6b\n   11 MC 0003\n   14 MR 0003 b4\n   14 MC 0003\n   15 MC 0003\n   16 MC 50d1\n   19 MR 50d1 dd\n   19 MC 50d1\n   20 MC 50d1\n   23 MW 50d1 9d\n0a1c ab67 9ca1 9d98 0000 0000 0000 0000 5066 320c 0000 0004\n00 02 0 0 0 0 23\n50d1 9d -1\n\nddcbb5  RES 6,(IX+d),L*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 ec\n   11 MC 0003\n   14 MR 0003 b5\n   14 MC 0003\n   15 MC 0003\n   16 MC 145a\n   19 MR 145a d6\n   19 MC 145a\n   20 MC 145a\n   23 MW 145a 96\nfd6d 51c9 16d6 1396 0000 0000 0000 0000 146e 2148 0000 0004\n00 02 0 0 0 0 23\n145a 96 -1\n\nddcbb6  RES 6,(IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 15\n   11 MC 0003\n   14 MR 0003 b6\n   14 MC 0003\n   15 MC 0003\n   16 MC 8787\n   19 MR 8787 8c\n   19 MC 8787\n   20 MC 8787\n   23 MW 8787 8c\n1d0b 04e8 109e 1dde 0000 0000 0000 0000 8772 8661 0000 0004\n00 02 0 0 0 0 23\n\nddcbb7  RES 6,(IX+d),A*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 d3\n   11 MC 0003\n   14 MR 0003 b7\n   14 MC 0003\n   15 MC 0003\n   16 MC 60f3\n   19 MR 60f3 54\n   19 MC 60f3\n   20 MC 60f3\n   23 MW 60f3 14\n1412 b87e 65ba a5c8 0000 0000 0000 0000 6120 789d 0000 0004\n00 02 0 0 0 0 23\n60f3 14 -1\n\nddcbb8  RES 7,(IX+d),B*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 13\n   11 MC 0003\n   14 MR 0003 b8\n   14 MC 0003\n   15 MC 0003\n   16 MC 0c09\n   19 MR 0c09 87\n   19 MC 0c09\n   20 MC 0c09\n   23 MW 0c09 07\n8eae 0753 bfa1 5e7e 0000 0000 0000 0000 0bf6 1e35 0000 0004\n00 02 0 0 0 0 23\n0c09 07 -1\n\nddcbb9  RES 7,(IX+d),C*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 56\n   11 MC 0003\n   14 MR 0003 b9\n   14 MC 0003\n   15 MC 0003\n   16 MC 05ba\n   19 MR 05ba c8\n   19 MC 05ba\n   20 MC 05ba\n   23 MW 05ba 48\n5fb7 a848 e2d2 4117 0000 0000 0000 0000 0564 48a1 0000 0004\n00 02 0 0 0 0 23\n05ba 48 -1\n\nddcbba  RES 7,(IX+d),D*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 86\n   11 MC 0003\n   14 MR 0003 ba\n   14 MC 0003\n   15 MC 0003\n   16 MC f566\n   19 MR f566 30\n   19 MC f566\n   20 MC f566\n   23 MW f566 30\n7f6a 47fe 3045 75de 0000 0000 0000 0000 f5e0 032c 0000 0004\n00 02 0 0 0 0 23\n\nddcbbb  RES 7,(IX+d),E*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 ef\n   11 MC 0003\n   14 MR 0003 bb\n   14 MC 0003\n   15 MC 0003\n   16 MC bd20\n   19 MR bd20 c9\n   19 MC bd20\n   20 MC bd20\n   23 MW bd20 49\nc7e3 e49e 9e49 07e7 0000 0000 0000 0000 bd31 9d5f 0000 0004\n00 02 0 0 0 0 23\nbd20 49 -1\n\nddcbbc  RES 7,(IX+d),H*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 c0\n   11 MC 0003\n   14 MR 0003 bc\n   14 MC 0003\n   15 MC 0003\n   16 MC 634e\n   19 MR 634e 28\n   19 MC 634e\n   20 MC 634e\n   23 MW 634e 28\nb430 7ac7 b45f 28f7 0000 0000 0000 0000 638e 3173 0000 0004\n00 02 0 0 0 0 23\n\nddcbbd  RES 7,(IX+d),L*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 b9\n   11 MC 0003\n   14 MR 0003 bd\n   14 MC 0003\n   15 MC 0003\n   16 MC e37d\n   19 MR e37d dd\n   19 MC e37d\n   20 MC e37d\n   23 MW e37d 5d\n4e71 6ffa a3f9 a25d 0000 0000 0000 0000 e3c4 02d4 0000 0004\n00 02 0 0 0 0 23\ne37d 5d -1\n\nddcbbe  RES 7,(IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 4d\n   11 MC 0003\n   14 MR 0003 be\n   14 MC 0003\n   15 MC 0003\n   16 MC 5920\n   19 MR 5920 e8\n   19 MC 5920\n   20 MC 5920\n   23 MW 5920 68\n4af8 99a5 d6fd 7a16 0000 0000 0000 0000 58d3 ce54 0000 0004\n00 02 0 0 0 0 23\n5920 68 -1\n\nddcbbf  RES 7,(IX+d),A*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 26\n   11 MC 0003\n   14 MR 0003 bf\n   14 MC 0003\n   15 MC 0003\n   16 MC 175a\n   19 MR 175a e2\n   19 MC 175a\n   20 MC 175a\n   23 MW 175a 62\n6231 0320 134b 77c3 0000 0000 0000 0000 1734 bc2d 0000 0004\n00 02 0 0 0 0 23\n175a 62 -1\n\nddcbc0  SET 0,(IX+d),B*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 00\n   11 MC 0003\n   14 MR 0003 c0\n   14 MC 0003\n   15 MC 0003\n   16 MC 792e\n   19 MR 792e 92\n   19 MC 792e\n   20 MC 792e\n   23 MW 792e 93\n75be 9393 093d 1128 0000 0000 0000 0000 792e 31f7 0000 0004\n00 02 0 0 0 0 23\n792e 93 -1\n\nddcbc1  SET 0,(IX+d),C*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 f7\n   11 MC 0003\n   14 MR 0003 c1\n   14 MC 0003\n   15 MC 0003\n   16 MC dcc3\n   19 MR dcc3 1c\n   19 MC dcc3\n   20 MC dcc3\n   23 MW dcc3 1d\n313f 821d 5fcc 42c8 0000 0000 0000 0000 dccc d87b 0000 0004\n00 02 0 0 0 0 23\ndcc3 1d -1\n\nddcbc2  SET 0,(IX+d),D*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 85\n   11 MC 0003\n   14 MR 0003 c2\n   14 MC 0003\n   15 MC 0003\n   16 MC 0c7f\n   19 MR 0c7f 30\n   19 MC 0c7f\n   20 MC 0c7f\n   23 MW 0c7f 31\na7e3 bf55 317b 0a9d 0000 0000 0000 0000 0cfa ea4e 0000 0004\n00 02 0 0 0 0 23\n0c7f 31 -1\n\nddcbc3  SET 0,(IX+d),E*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 32\n   11 MC 0003\n   14 MR 0003 c3\n   14 MC 0003\n   15 MC 0003\n   16 MC 5458\n   19 MR 5458 dd\n   19 MC 5458\n   20 MC 5458\n   23 MW 5458 dd\ne076 2760 1edd 9968 0000 0000 0000 0000 5426 a1a0 0000 0004\n00 02 0 0 0 0 23\n\nddcbc4  SET 0,(IX+d),H*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 ae\n   11 MC 0003\n   14 MR 0003 c4\n   14 MC 0003\n   15 MC 0003\n   16 MC 7a7b\n   19 MR 7a7b 27\n   19 MC 7a7b\n   20 MC 7a7b\n   23 MW 7a7b 27\na679 cc05 3f4d 2799 0000 0000 0000 0000 7acd 48d7 0000 0004\n00 02 0 0 0 0 23\n\nddcbc5  SET 0,(IX+d),L*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 9c\n   11 MC 0003\n   14 MR 0003 c5\n   14 MC 0003\n   15 MC 0003\n   16 MC ba35\n   19 MR ba35 20\n   19 MC ba35\n   20 MC ba35\n   23 MW ba35 21\nddfd 64d4 2671 3521 0000 0000 0000 0000 ba99 bd98 0000 0004\n00 02 0 0 0 0 23\nba35 21 -1\n\nddcbc6  SET 0,(IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 c4\n   11 MC 0003\n   14 MR 0003 c6\n   14 MC 0003\n   15 MC 0003\n   16 MC aaf0\n   19 MR aaf0 b8\n   19 MC aaf0\n   20 MC aaf0\n   23 MW aaf0 b9\nb324 dc0c 1e35 8cd5 0000 0000 0000 0000 ab2c b6f3 0000 0004\n00 02 0 0 0 0 23\naaf0 b9 -1\n\nddcbc7  SET 0,(IX+d),A*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 f8\n   11 MC 0003\n   14 MR 0003 c7\n   14 MC 0003\n   15 MC 0003\n   16 MC 64c3\n   19 MR 64c3 94\n   19 MC 64c3\n   20 MC 64c3\n   23 MW 64c3 95\n9554 9e56 6828 3189 0000 0000 0000 0000 64cb dfad 0000 0004\n00 02 0 0 0 0 23\n64c3 95 -1\n\nddcbc8  SET 1,(IX+d),B*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 65\n   11 MC 0003\n   14 MR 0003 c8\n   14 MC 0003\n   15 MC 0003\n   16 MC 6edf\n   19 MR 6edf 8f\n   19 MC 6edf\n   20 MC 6edf\n   23 MW 6edf 8f\n8aca 8f9e e652 248b 0000 0000 0000 0000 6e7a 189a 0000 0004\n00 02 0 0 0 0 23\n\nddcbc9  SET 1,(IX+d),C*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 fb\n   11 MC 0003\n   14 MR 0003 c9\n   14 MC 0003\n   15 MC 0003\n   16 MC b66b\n   19 MR b66b b9\n   19 MC b66b\n   20 MC b66b\n   23 MW b66b bb\nf15f 85bb a21f 8a59 0000 0000 0000 0000 b670 4f79 0000 0004\n00 02 0 0 0 0 23\nb66b bb -1\n\nddcbca  SET 1,(IX+d),D*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 8a\n   11 MC 0003\n   14 MR 0003 ca\n   14 MC 0003\n   15 MC 0003\n   16 MC a811\n   19 MR a811 7e\n   19 MC a811\n   20 MC a811\n   23 MW a811 7e\ndfab a031 7e78 ad3a 0000 0000 0000 0000 a887 7334 0000 0004\n00 02 0 0 0 0 23\n\nddcbcb  SET 1,(IX+d),E*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 a4\n   11 MC 0003\n   14 MR 0003 cb\n   14 MC 0003\n   15 MC 0003\n   16 MC a3eb\n   19 MR a3eb 73\n   19 MC a3eb\n   20 MC a3eb\n   23 MW a3eb 73\nebd6 376e c373 b10c 0000 0000 0000 0000 a447 31d6 0000 0004\n00 02 0 0 0 0 23\n\nddcbcc  SET 1,(IX+d),H*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 65\n   11 MC 0003\n   14 MR 0003 cc\n   14 MC 0003\n   15 MC 0003\n   16 MC 1fbf\n   19 MR 1fbf 72\n   19 MC 1fbf\n   20 MC 1fbf\n   23 MW 1fbf 72\n0212 dc46 8f41 724e 0000 0000 0000 0000 1f5a 07ca 0000 0004\n00 02 0 0 0 0 23\n\nddcbcd  SET 1,(IX+d),L*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 e9\n   11 MC 0003\n   14 MR 0003 cd\n   14 MC 0003\n   15 MC 0003\n   16 MC 535f\n   19 MR 535f 1c\n   19 MC 535f\n   20 MC 535f\n   23 MW 535f 1e\n3344 d73c d6b8 921e 0000 0000 0000 0000 5376 6d3a 0000 0004\n00 02 0 0 0 0 23\n535f 1e -1\n\nddcbce  SET 1,(IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 85\n   11 MC 0003\n   14 MR 0003 ce\n   14 MC 0003\n   15 MC 0003\n   16 MC 0298\n   19 MR 0298 10\n   19 MC 0298\n   20 MC 0298\n   23 MW 0298 12\n9e47 fc93 9ffc aace 0000 0000 0000 0000 0313 7f66 0000 0004\n00 02 0 0 0 0 23\n0298 12 -1\n\nddcbcf  SET 1,(IX+d),A*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 e2\n   11 MC 0003\n   14 MR 0003 cf\n   14 MC 0003\n   15 MC 0003\n   16 MC c5b2\n   19 MR c5b2 b5\n   19 MC c5b2\n   20 MC c5b2\n   23 MW c5b2 b7\nb7e8 d379 87d5 10b0 0000 0000 0000 0000 c5d0 4f7f 0000 0004\n00 02 0 0 0 0 23\nc5b2 b7 -1\n\nddcbd0  SET 2,(IX+d),B*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 7f\n   11 MC 0003\n   14 MR 0003 d0\n   14 MC 0003\n   15 MC 0003\n   16 MC adc2\n   19 MR adc2 51\n   19 MC adc2\n   20 MC adc2\n   23 MW adc2 55\n3278 5514 d25d 1cf8 0000 0000 0000 0000 ad43 99fc 0000 0004\n00 02 0 0 0 0 23\nadc2 55 -1\n\nddcbd1  SET 2,(IX+d),C*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 a6\n   11 MC 0003\n   14 MR 0003 d1\n   14 MC 0003\n   15 MC 0003\n   16 MC 1058\n   19 MR 1058 2c\n   19 MC 1058\n   20 MC 1058\n   23 MW 1058 2c\nc0b8 372c 6472 d92d 0000 0000 0000 0000 10b2 3074 0000 0004\n00 02 0 0 0 0 23\n\nddcbd2  SET 2,(IX+d),D*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 9c\n   11 MC 0003\n   14 MR 0003 d2\n   14 MC 0003\n   15 MC 0003\n   16 MC b93d\n   19 MR b93d 9c\n   19 MC b93d\n   20 MC b93d\n   23 MW b93d 9c\n5bb6 caa8 9cdb af84 0000 0000 0000 0000 b9a1 7b5f 0000 0004\n00 02 0 0 0 0 23\n\nddcbd3  SET 2,(IX+d),E*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 bd\n   11 MC 0003\n   14 MR 0003 d3\n   14 MC 0003\n   15 MC 0003\n   16 MC d9f3\n   19 MR d9f3 60\n   19 MC d9f3\n   20 MC d9f3\n   23 MW d9f3 64\ndb6a 4fe2 9e64 a034 0000 0000 0000 0000 da36 88a0 0000 0004\n00 02 0 0 0 0 23\nd9f3 64 -1\n\nddcbd4  SET 2,(IX+d),H*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 58\n   11 MC 0003\n   14 MR 0003 d4\n   14 MC 0003\n   15 MC 0003\n   16 MC ef7e\n   19 MR ef7e 5e\n   19 MC ef7e\n   20 MC ef7e\n   23 MW ef7e 5e\ncc1c b884 6ad2 5e21 0000 0000 0000 0000 ef26 41de 0000 0004\n00 02 0 0 0 0 23\n\nddcbd5  SET 2,(IX+d),L*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 41\n   11 MC 0003\n   14 MR 0003 d5\n   14 MC 0003\n   15 MC 0003\n   16 MC 8dfd\n   19 MR 8dfd 71\n   19 MC 8dfd\n   20 MC 8dfd\n   23 MW 8dfd 75\nc41d c8b0 cacb 7675 0000 0000 0000 0000 8dbc cc25 0000 0004\n00 02 0 0 0 0 23\n8dfd 75 -1\n\nddcbd6  SET 2,(IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 ea\n   11 MC 0003\n   14 MR 0003 d6\n   14 MC 0003\n   15 MC 0003\n   16 MC 5eed\n   19 MR 5eed 73\n   19 MC 5eed\n   20 MC 5eed\n   23 MW 5eed 77\n09eb 769d 7e07 51f9 0000 0000 0000 0000 5f03 6280 0000 0004\n00 02 0 0 0 0 23\n5eed 77 -1\n\nddcbd7  SET 2,(IX+d),A*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 80\n   11 MC 0003\n   14 MR 0003 d7\n   14 MC 0003\n   15 MC 0003\n   16 MC e6a5\n   19 MR e6a5 60\n   19 MC e6a5\n   20 MC e6a5\n   23 MW e6a5 64\n641b ee10 c152 2f6d 0000 0000 0000 0000 e725 c0d7 0000 0004\n00 02 0 0 0 0 23\ne6a5 64 -1\n\nddcbd8  SET 3,(IX+d),B*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 4c\n   11 MC 0003\n   14 MR 0003 d8\n   14 MC 0003\n   15 MC 0003\n   16 MC b35b\n   19 MR b35b 96\n   19 MC b35b\n   20 MC b35b\n   23 MW b35b 9e\ne3dc 9e81 c97b cb42 0000 0000 0000 0000 b30f b32a 0000 0004\n00 02 0 0 0 0 23\nb35b 9e -1\n\nddcbd9  SET 3,(IX+d),C*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 52\n   11 MC 0003\n   14 MR 0003 d9\n   14 MC 0003\n   15 MC 0003\n   16 MC 2694\n   19 MR 2694 ef\n   19 MC 2694\n   20 MC 2694\n   23 MW 2694 ef\ne9a0 a7ef a476 6057 0000 0000 0000 0000 2642 58a0 0000 0004\n00 02 0 0 0 0 23\n\nddcbda  SET 3,(IX+d),D*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 ea\n   11 MC 0003\n   14 MR 0003 da\n   14 MC 0003\n   15 MC 0003\n   16 MC 2d60\n   19 MR 2d60 82\n   19 MC 2d60\n   20 MC 2d60\n   23 MW 2d60 8a\n6787 26a7 8a94 11d3 0000 0000 0000 0000 2d76 7f80 0000 0004\n00 02 0 0 0 0 23\n2d60 8a -1\n\nddcbdb  SET 3,(IX+d),E*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 4d\n   11 MC 0003\n   14 MR 0003 db\n   14 MC 0003\n   15 MC 0003\n   16 MC 2bca\n   19 MR 2bca 10\n   19 MC 2bca\n   20 MC 2bca\n   23 MW 2bca 18\nf986 6a4b 6518 d2c8 0000 0000 0000 0000 2b7d 5847 0000 0004\n00 02 0 0 0 0 23\n2bca 18 -1\n\nddcbdc  SET 3,(IX+d),H*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 d3\n   11 MC 0003\n   14 MR 0003 dc\n   14 MC 0003\n   15 MC 0003\n   16 MC 7ea7\n   19 MR 7ea7 45\n   19 MC 7ea7\n   20 MC 7ea7\n   23 MW 7ea7 4d\n4c9e d94d 9760 4d07 0000 0000 0000 0000 7ed4 5cc5 0000 0004\n00 02 0 0 0 0 23\n7ea7 4d -1\n\nddcbdd  SET 3,(IX+d),L*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 6f\n   11 MC 0003\n   14 MR 0003 dd\n   14 MC 0003\n   15 MC 0003\n   16 MC 5930\n   19 MR 5930 20\n   19 MC 5930\n   20 MC 5930\n   23 MW 5930 28\n4b3b d351 9be9 2328 0000 0000 0000 0000 58c1 e430 0000 0004\n00 02 0 0 0 0 23\n5930 28 -1\n\nddcbde  SET 3,(IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 14\n   11 MC 0003\n   14 MR 0003 de\n   14 MC 0003\n   15 MC 0003\n   16 MC 89e6\n   19 MR 89e6 5e\n   19 MC 89e6\n   20 MC 89e6\n   23 MW 89e6 5e\n3b62 ca1e a41a 227a 0000 0000 0000 0000 89d2 7011 0000 0004\n00 02 0 0 0 0 23\n\nddcbdf  SET 3,(IX+d),A*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 ef\n   11 MC 0003\n   14 MR 0003 df\n   14 MC 0003\n   15 MC 0003\n   16 MC d216\n   19 MR d216 72\n   19 MC d216\n   20 MC d216\n   23 MW d216 7a\n7a8a 5b42 50dd 4be0 0000 0000 0000 0000 d227 4913 0000 0004\n00 02 0 0 0 0 23\nd216 7a -1\n\nddcbe0  SET 4,(IX+d),B*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 62\n   11 MC 0003\n   14 MR 0003 e0\n   14 MC 0003\n   15 MC 0003\n   16 MC 1cad\n   19 MR 1cad 46\n   19 MC 1cad\n   20 MC 1cad\n   23 MW 1cad 56\n440a 563d acfc f762 0000 0000 0000 0000 1c4b b6ba 0000 0004\n00 02 0 0 0 0 23\n1cad 56 -1\n\nddcbe1  SET 4,(IX+d),C*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 2e\n   11 MC 0003\n   14 MR 0003 e1\n   14 MC 0003\n   15 MC 0003\n   16 MC b95f\n   19 MR b95f 75\n   19 MC b95f\n   20 MC b95f\n   23 MW b95f 75\nc219 aa75 dfbf 6f10 0000 0000 0000 0000 b931 d3d6 0000 0004\n00 02 0 0 0 0 23\n\nddcbe2  SET 4,(IX+d),D*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 85\n   11 MC 0003\n   14 MR 0003 e2\n   14 MC 0003\n   15 MC 0003\n   16 MC eed5\n   19 MR eed5 72\n   19 MC eed5\n   20 MC eed5\n   23 MW eed5 72\n66d7 abd0 7248 8054 0000 0000 0000 0000 ef50 9997 0000 0004\n00 02 0 0 0 0 23\n\nddcbe3  SET 4,(IX+d),E*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 f4\n   11 MC 0003\n   14 MR 0003 e3\n   14 MC 0003\n   15 MC 0003\n   16 MC 7eba\n   19 MR 7eba 34\n   19 MC 7eba\n   20 MC 7eba\n   23 MW 7eba 34\n7013 e7ed 7e34 57fb 0000 0000 0000 0000 7ec6 75eb 0000 0004\n00 02 0 0 0 0 23\n\nddcbe4  SET 4,(IX+d),H*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 bf\n   11 MC 0003\n   14 MR 0003 e4\n   14 MC 0003\n   15 MC 0003\n   16 MC 9586\n   19 MR 9586 34\n   19 MC 9586\n   20 MC 9586\n   23 MW 9586 34\n1108 6e70 f0af 340c 0000 0000 0000 0000 95c7 6501 0000 0004\n00 02 0 0 0 0 23\n\nddcbe5  SET 4,(IX+d),L*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 f2\n   11 MC 0003\n   14 MR 0003 e5\n   14 MC 0003\n   15 MC 0003\n   16 MC 6aa2\n   19 MR 6aa2 2e\n   19 MC 6aa2\n   20 MC 6aa2\n   23 MW 6aa2 3e\n57cc 5511 2696 b83e 0000 0000 0000 0000 6ab0 0e90 0000 0004\n00 02 0 0 0 0 23\n6aa2 3e -1\n\nddcbe6  SET 4,(IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 25\n   11 MC 0003\n   14 MR 0003 e6\n   14 MC 0003\n   15 MC 0003\n   16 MC d88b\n   19 MR d88b 4c\n   19 MC d88b\n   20 MC d88b\n   23 MW d88b 5c\n207a a441 1e03 ac60 0000 0000 0000 0000 d866 5fdc 0000 0004\n00 02 0 0 0 0 23\nd88b 5c -1\n\nddcbe7  SET 4,(IX+d),A*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 f3\n   11 MC 0003\n   14 MR 0003 e7\n   14 MC 0003\n   15 MC 0003\n   16 MC 2a0e\n   19 MR 2a0e eb\n   19 MC 2a0e\n   20 MC 2a0e\n   23 MW 2a0e fb\nfbc5 7fa9 4e07 e02d 0000 0000 0000 0000 2a1b 55b7 0000 0004\n00 02 0 0 0 0 23\n2a0e fb -1\n\nddcbe8  SET 5,(IX+d),B*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 f2\n   11 MC 0003\n   14 MR 0003 e8\n   14 MC 0003\n   15 MC 0003\n   16 MC 4bcc\n   19 MR 4bcc ba\n   19 MC 4bcc\n   20 MC 4bcc\n   23 MW 4bcc ba\n6d1c bac4 93f0 a0b4 0000 0000 0000 0000 4bda 7761 0000 0004\n00 02 0 0 0 0 23\n\nddcbe9  SET 5,(IX+d),C*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 8a\n   11 MC 0003\n   14 MR 0003 e9\n   14 MC 0003\n   15 MC 0003\n   16 MC 7267\n   19 MR 7267 0a\n   19 MC 7267\n   20 MC 7267\n   23 MW 7267 2a\nebe5 0c2a 1a2a 2720 0000 0000 0000 0000 72dd a354 0000 0004\n00 02 0 0 0 0 23\n7267 2a -1\n\nddcbea  SET 5,(IX+d),D*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 04\n   11 MC 0003\n   14 MR 0003 ea\n   14 MC 0003\n   15 MC 0003\n   16 MC a7ed\n   19 MR a7ed 5f\n   19 MC a7ed\n   20 MC a7ed\n   23 MW a7ed 7f\n42d2 da7a 7f7f 6da6 0000 0000 0000 0000 a7e9 b933 0000 0004\n00 02 0 0 0 0 23\na7ed 7f -1\n\nddcbeb  SET 5,(IX+d),E*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 24\n   11 MC 0003\n   14 MR 0003 eb\n   14 MC 0003\n   15 MC 0003\n   16 MC 1703\n   19 MR 1703 f3\n   19 MC 1703\n   20 MC 1703\n   23 MW 1703 f3\ne945 10aa f5f3 7647 0000 0000 0000 0000 16df 93fb 0000 0004\n00 02 0 0 0 0 23\n\nddcbec  SET 5,(IX+d),H*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 60\n   11 MC 0003\n   14 MR 0003 ec\n   14 MC 0003\n   15 MC 0003\n   16 MC dde8\n   19 MR dde8 00\n   19 MC dde8\n   20 MC dde8\n   23 MW dde8 20\n7180 bc85 7dd3 2067 0000 0000 0000 0000 dd88 6a41 0000 0004\n00 02 0 0 0 0 23\ndde8 20 -1\n\nddcbed  SET 5,(IX+d),L*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 be\n   11 MC 0003\n   14 MR 0003 ed\n   14 MC 0003\n   15 MC 0003\n   16 MC f730\n   19 MR f730 6b\n   19 MC f730\n   20 MC f730\n   23 MW f730 6b\n6b2f 9762 1f0a db6b 0000 0000 0000 0000 f772 33e3 0000 0004\n00 02 0 0 0 0 23\n\nddcbee  SET 5,(IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 de\n   11 MC 0003\n   14 MR 0003 ee\n   14 MC 0003\n   15 MC 0003\n   16 MC 6c06\n   19 MR 6c06 bd\n   19 MC 6c06\n   20 MC 6c06\n   23 MW 6c06 bd\n79ea dc8a 7887 3baa 0000 0000 0000 0000 6c28 abbc 0000 0004\n00 02 0 0 0 0 23\n\nddcbef  SET 5,(IX+d),A*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 30\n   11 MC 0003\n   14 MR 0003 ef\n   14 MC 0003\n   15 MC 0003\n   16 MC cc98\n   19 MR cc98 11\n   19 MC cc98\n   20 MC cc98\n   23 MW cc98 31\n31c3 2fc2 8690 a836 0000 0000 0000 0000 cc68 a8ce 0000 0004\n00 02 0 0 0 0 23\ncc98 31 -1\n\nddcbf0  SET 6,(IX+d),B*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 2f\n   11 MC 0003\n   14 MR 0003 f0\n   14 MC 0003\n   15 MC 0003\n   16 MC 13ef\n   19 MR 13ef ad\n   19 MC 13ef\n   20 MC 13ef\n   23 MW 13ef ed\nb330 ed69 362b b515 0000 0000 0000 0000 13c0 6479 0000 0004\n00 02 0 0 0 0 23\n13ef ed -1\n\nddcbf1  SET 6,(IX+d),C*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 40\n   11 MC 0003\n   14 MR 0003 f1\n   14 MC 0003\n   15 MC 0003\n   16 MC 47fa\n   19 MR 47fa 78\n   19 MC 47fa\n   20 MC 47fa\n   23 MW 47fa 78\n94c0 9a78 a0fd 7c1d 0000 0000 0000 0000 47ba 8c81 0000 0004\n00 02 0 0 0 0 23\n\nddcbf2  SET 6,(IX+d),D*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 0f\n   11 MC 0003\n   14 MR 0003 f2\n   14 MC 0003\n   15 MC 0003\n   16 MC c956\n   19 MR c956 21\n   19 MC c956\n   20 MC c956\n   23 MW c956 61\n5302 9204 61ec d640 0000 0000 0000 0000 c947 4ef1 0000 0004\n00 02 0 0 0 0 23\nc956 61 -1\n\nddcbf3  SET 6,(IX+d),E*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 06\n   11 MC 0003\n   14 MR 0003 f3\n   14 MC 0003\n   15 MC 0003\n   16 MC 1d9c\n   19 MR 1d9c e4\n   19 MC 1d9c\n   20 MC 1d9c\n   23 MW 1d9c e4\n9950 a3d2 50e4 5ccc 0000 0000 0000 0000 1d96 7c75 0000 0004\n00 02 0 0 0 0 23\n\nddcbf4  SET 6,(IX+d),H*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 3b\n   11 MC 0003\n   14 MR 0003 f4\n   14 MC 0003\n   15 MC 0003\n   16 MC 173d\n   19 MR 173d e1\n   19 MC 173d\n   20 MC 173d\n   23 MW 173d e1\n3712 1f99 4863 e1de 0000 0000 0000 0000 1702 c042 0000 0004\n00 02 0 0 0 0 23\n\nddcbf5  SET 6,(IX+d),L*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 64\n   11 MC 0003\n   14 MR 0003 f5\n   14 MC 0003\n   15 MC 0003\n   16 MC eba3\n   19 MR eba3 c5\n   19 MC eba3\n   20 MC eba3\n   23 MW eba3 c5\nd83f 1ec9 d0da 41c5 0000 0000 0000 0000 eb3f 1ead 0000 0004\n00 02 0 0 0 0 23\n\nddcbf6  SET 6,(IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 7b\n   11 MC 0003\n   14 MR 0003 f6\n   14 MC 0003\n   15 MC 0003\n   16 MC dcd5\n   19 MR dcd5 a2\n   19 MC dcd5\n   20 MC dcd5\n   23 MW dcd5 e2\n4d6c 93ac 810d cfe1 0000 0000 0000 0000 dc5a c33c 0000 0004\n00 02 0 0 0 0 23\ndcd5 e2 -1\n\nddcbf7  SET 6,(IX+d),A*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 c3\n   11 MC 0003\n   14 MR 0003 f7\n   14 MC 0003\n   15 MC 0003\n   16 MC 2fe1\n   19 MR 2fe1 a9\n   19 MC 2fe1\n   20 MC 2fe1\n   23 MW 2fe1 e9\ne940 7887 b9de c013 0000 0000 0000 0000 301e 9710 0000 0004\n00 02 0 0 0 0 23\n2fe1 e9 -1\n\nddcbf8  SET 7,(IX+d),B*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 59\n   11 MC 0003\n   14 MR 0003 f8\n   14 MC 0003\n   15 MC 0003\n   16 MC 42d8\n   19 MR 42d8 28\n   19 MC 42d8\n   20 MC 42d8\n   23 MW 42d8 a8\n8278 a8a4 1e5c 4952 0000 0000 0000 0000 427f 41e1 0000 0004\n00 02 0 0 0 0 23\n42d8 a8 -1\n\nddcbf9  SET 7,(IX+d),C*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 55\n   11 MC 0003\n   14 MR 0003 f9\n   14 MC 0003\n   15 MC 0003\n   16 MC d8e4\n   19 MR d8e4 14\n   19 MC d8e4\n   20 MC d8e4\n   23 MW d8e4 94\nb2df e994 56c3 16ff 0000 0000 0000 0000 d88f 0bab 0000 0004\n00 02 0 0 0 0 23\nd8e4 94 -1\n\nddcbfa  SET 7,(IX+d),D*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 74\n   11 MC 0003\n   14 MR 0003 fa\n   14 MC 0003\n   15 MC 0003\n   16 MC 9494\n   19 MR 9494 fe\n   19 MC 9494\n   20 MC 9494\n   23 MW 9494 fe\n01f1 bc0d fe76 1510 0000 0000 0000 0000 9420 93a3 0000 0004\n00 02 0 0 0 0 23\n\nddcbfb  SET 7,(IX+d),E*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 af\n   11 MC 0003\n   14 MR 0003 fb\n   14 MC 0003\n   15 MC 0003\n   16 MC 3402\n   19 MR 3402 02\n   19 MC 3402\n   20 MC 3402\n   23 MW 3402 82\n709b 14eb ec82 b844 0000 0000 0000 0000 3453 f2b0 0000 0004\n00 02 0 0 0 0 23\n3402 82 -1\n\nddcbfc  SET 7,(IX+d),H*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 a1\n   11 MC 0003\n   14 MR 0003 fc\n   14 MC 0003\n   15 MC 0003\n   16 MC 60da\n   19 MR 60da 10\n   19 MC 60da\n   20 MC 60da\n   23 MW 60da 90\n6c89 a96e d27b 90a7 0000 0000 0000 0000 6139 b4c1 0000 0004\n00 02 0 0 0 0 23\n60da 90 -1\n\nddcbfd  SET 7,(IX+d),L*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 28\n   11 MC 0003\n   14 MR 0003 fd\n   14 MC 0003\n   15 MC 0003\n   16 MC 3ef8\n   19 MR 3ef8 c2\n   19 MC 3ef8\n   20 MC 3ef8\n   23 MW 3ef8 c2\nfb3f 83f6 2094 33c2 0000 0000 0000 0000 3ed0 6f0e 0000 0004\n00 02 0 0 0 0 23\n\nddcbfe  SET 7,(IX+d)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 ec\n   11 MC 0003\n   14 MR 0003 fe\n   14 MC 0003\n   15 MC 0003\n   16 MC 41a1\n   19 MR 41a1 a1\n   19 MC 41a1\n   20 MC 41a1\n   23 MW 41a1 a1\nfc42 50b7 e98d 3e45 0000 0000 0000 0000 41b5 3410 0000 0004\n00 02 0 0 0 0 23\n\nddcbff  SET 7,(IX+d),A*\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 d3\n   11 MC 0003\n   14 MR 0003 ff\n   14 MC 0003\n   15 MC 0003\n   16 MC 0628\n   19 MR 0628 2b\n   19 MC 0628\n   20 MC 0628\n   23 MW 0628 ab\nab66 94d2 ac90 8f45 0000 0000 0000 0000 0655 ba29 0000 0004\n00 02 0 0 0 0 23\n0628 ab -1\n\ndde1    POP IX\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 e1\n    8 MC 595f\n   11 MR 595f 9a\n   11 MC 5960\n   14 MR 5960 09\n8a15 6bf0 0106 3dd0 0000 0000 0000 0000 099a 8716 5961 0002\n00 02 0 0 0 0 14\n\ndde3    EX (SP),IX\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 e3\n    8 MC 57bd\n   11 MR 57bd 15\n   11 MC 57be\n   14 MR 57be 3f\n   14 MC 57be\n   15 MC 57be\n   18 MW 57be be\n   18 MC 57bd\n   21 MW 57bd 05\n   21 MC 57bd\n   22 MC 57bd\n068e 58e6 2713 500f 0000 0000 0000 0000 3f15 4308 57bd 0002\n00 02 0 0 0 0 23\n57bd 05 be -1\n\ndde5    PUSH IX\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 e5\n    8 MC 0002\n    9 MC 0760\n   12 MW 0760 b2\n   12 MC 075f\n   15 MW 075f 82\n7462 9b6c bfe5 0330 0000 0000 0000 0000 b282 e272 075f 0002\n00 02 0 0 0 0 15\n075f 82 b2 -1\n\ndde9    JP (IX)\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 e9\n75a7 139b f9a3 94bb 0000 0000 0000 0000 64f0 3433 0000 64f0\n00 02 0 0 0 0 8\n\nddf9    LD SP,IX\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 f9\n    8 MC 0002\n    9 MC 0002\n8709 15dd 7fa6 3c5c 0000 0000 0000 0000 d3a7 1d7b d3a7 0002\n00 02 0 0 0 0 10\n\nddfd00\n    0 MC 0000\n    4 MR 0000 dd\n    4 MC 0001\n    8 MR 0001 fd\n    8 MC 0002\n   12 MR 0002 00\n   12 MC 0003\n   16 MR 0003 00\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0004\n00 04 0 0 0 0 16\n\nde      SBC A,n\n    0 MC 0000\n    4 MR 0000 de\n    4 MC 0001\n    7 MR 0001 a1\n4502 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0002\n00 01 0 0 0 0 7\n\ndf      RST 18H\n    0 MC 6d33\n    4 MR 6d33 df\n    4 MC 0001\n    5 MC 5506\n    8 MW 5506 6d\n    8 MC 5505\n   11 MW 5505 34\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 5505 0018\n00 01 0 0 0 0 11\n5505 34 6d -1\n\ne0_1    RET PO\n    0 MC 0000\n    4 MR 0000 e0\n    4 MC 0001\n    5 MC 43f7\n    8 MR 43f7 e9\n    8 MC 43f8\n   11 MR 43f8 af\n0098 0000 0000 0000 0000 0000 0000 0000 0000 0000 43f9 afe9\n00 01 0 0 0 0 11\n\ne0_2    RET PO\n    0 MC 0000\n    4 MR 0000 e0\n    4 MC 0001\n009c 0000 0000 0000 0000 0000 0000 0000 0000 0000 43f7 0001\n00 01 0 0 0 0 5\n\ne1      POP HL\n    0 MC 0000\n    4 MR 0000 e1\n    4 MC 4143\n    7 MR 4143 ce\n    7 MC 4144\n   10 MR 4144 e8\n0000 0000 0000 e8ce 0000 0000 0000 0000 0000 0000 4145 0001\n00 01 0 0 0 0 10\n\ne2_1    JP PO,nn\n    0 MC 0000\n    4 MR 0000 e2\n    4 MC 0001\n    7 MR 0001 1b\n    7 MC 0002\n   10 MR 0002 e1\n0083 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 e11b\n00 01 0 0 0 0 10\n\ne2_2    JP PO,nn\n    0 MC 0000\n    4 MR 0000 e2\n    4 MC 0001\n    7 MC 0002\n0087 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0003\n00 01 0 0 0 0 10\n\ne3      EX (SP),HL\n    0 MC 0000\n    4 MR 0000 e3\n    4 MC 0373\n    7 MR 0373 8e\n    7 MC 0374\n   10 MR 0374 e1\n   10 MC 0374\n   11 MC 0374\n   14 MW 0374 4d\n   14 MC 0373\n   17 MW 0373 22\n   17 MC 0373\n   18 MC 0373\n0000 0000 0000 e18e 0000 0000 0000 0000 0000 0000 0373 0001\n00 01 0 0 0 0 19\n0373 22 4d -1\n\ne4_1    CALL PO,nn\n    0 MC 0000\n    4 MR 0000 e4\n    4 MC 0001\n    7 MR 0001 61\n    7 MC 0002\n   10 MR 0002 9c\n   10 MC 0002\n   11 MC 5697\n   14 MW 5697 00\n   14 MC 5696\n   17 MW 5696 03\n000a 0000 0000 0000 0000 0000 0000 0000 0000 0000 5696 9c61\n00 01 0 0 0 0 17\n5696 03 00 -1\n\ne4_2    CALL PO,nn\n    0 MC 0000\n    4 MR 0000 e4\n    4 MC 0001\n    7 MC 0002\n000e 0000 0000 0000 0000 0000 0000 0000 0000 0000 5698 0003\n00 01 0 0 0 0 10\n\ne5      PUSH HL\n    0 MC 0000\n    4 MR 0000 e5\n    4 MC 0001\n    5 MC ec11\n    8 MW ec11 1a\n    8 MC ec10\n   11 MW ec10 2f\n53e3 1459 775f 1a2f 0000 0000 0000 0000 0000 0000 ec10 0001\n00 01 0 0 0 0 11\nec10 2f 1a -1\n\ne6      AND n\n    0 MC 0000\n    4 MR 0000 e6\n    4 MC 0001\n    7 MR 0001 49\n4114 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0002\n00 01 0 0 0 0 7\n\ne7      RST 20H\n    0 MC 6d33\n    4 MR 6d33 e7\n    4 MC 0001\n    5 MC 5506\n    8 MW 5506 6d\n    8 MC 5505\n   11 MW 5505 34\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 5505 0020\n00 01 0 0 0 0 11\n5505 34 6d -1\n\ne8_1    RET PE\n    0 MC 0000\n    4 MR 0000 e8\n    4 MC 0001\n0098 0000 0000 0000 0000 0000 0000 0000 0000 0000 43f7 0001\n00 01 0 0 0 0 5\n\ne8_2    RET PE\n    0 MC 0000\n    4 MR 0000 e8\n    4 MC 0001\n    5 MC 43f7\n    8 MR 43f7 e9\n    8 MC 43f8\n   11 MR 43f8 af\n009c 0000 0000 0000 0000 0000 0000 0000 0000 0000 43f9 afe9\n00 01 0 0 0 0 11\n\ne9      JP (HL)\n    0 MC 0000\n    4 MR 0000 e9\n0000 0000 0000 caba 0000 0000 0000 0000 0000 0000 0000 caba\n00 01 0 0 0 0 4\n\nea_1    JP PE,nn\n    0 MC 0000\n    4 MR 0000 ea\n    4 MC 0001\n    7 MR 0001 1b\n    7 MC 0002\n   10 MR 0002 e1\n0087 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 e11b\n00 01 0 0 0 0 10\n\nea_2    JP PE,nn\n    0 MC 0000\n    4 MR 0000 ea\n    4 MC 0001\n    7 MC 0002\n0083 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0003\n00 01 0 0 0 0 10\n\neb      EX DE,HL\n    0 MC 0000\n    4 MR 0000 eb\n0000 0000 942e b879 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\nec_1    CALL PE,nn\n    0 MC 0000\n    4 MR 0000 ec\n    4 MC 0001\n    7 MR 0001 61\n    7 MC 0002\n   10 MR 0002 9c\n   10 MC 0002\n   11 MC 5697\n   14 MW 5697 00\n   14 MC 5696\n   17 MW 5696 03\n000e 0000 0000 0000 0000 0000 0000 0000 0000 0000 5696 9c61\n00 01 0 0 0 0 17\n5696 03 00 -1\n\nec_2    CALL PE,nn\n    0 MC 0000\n    4 MR 0000 ec\n    4 MC 0001\n    7 MC 0002\n000a 0000 0000 0000 0000 0000 0000 0000 0000 0000 5698 0003\n00 01 0 0 0 0 10\n\ned40    IN B,(C)\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 40\n    9 PR 296b 29\n8329 296b 7034 1f2f 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 12\n\ned41    OUT (C),B\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 41\n    9 PW 0881 08\n29a2 0881 d7dd ff4e 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 12\n\ned42    SBC HL,BC\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 42\n    8 MC 0002\n    9 MC 0002\n   10 MC 0002\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\ncb12 1c8f d456 14ce 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 15\n\ned43    LD (nn),BC\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 43\n    8 MC 0002\n   11 MR 0002 c6\n   11 MC 0003\n   14 MR 0003 54\n   14 MC 54c6\n   17 MW 54c6 32\n   17 MC 54c7\n   20 MW 54c7 27\nda36 2732 91cc 9798 0000 0000 0000 0000 0000 0000 5f73 0004\n00 02 0 0 0 0 20\n54c6 32 27 -1\n\ned44    NEG\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 44\n0213 040f deb6 afc3 0000 0000 0000 0000 0000 0000 5ca8 0002\n00 02 0 0 0 0 8\n\ned45    RETN\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 45\n    8 MC 3100\n   11 MR 3100 1f\n   11 MC 3101\n   14 MR 3101 22\n001d 5b63 a586 1451 0000 0000 0000 0000 0000 0000 3102 221f\n00 02 1 1 0 0 14\n\ned46    IM 0\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 46\nb6ec 8afb ce09 70a1 0000 0000 0000 0000 0000 0000 8dea 0002\n00 02 0 0 0 0 8\n\ned47    LD I,A\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 47\n    8 MC 0002\n9a99 9e5a 9913 cacc 0000 0000 0000 0000 0000 0000 0000 0002\n9a 02 0 0 0 0 9\n\ned48    IN C,(C)\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 48\n    8 PC 7d1b\n    9 PR 7d1b 7d\n    9 PC 7d1b\n   10 PC 7d1b\n   11 PC 7d1b\ndb2d 7d7d 141d 5fb4 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 12\n\ned49    OUT (C),C\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 49\n    8 PC 59ec\n    9 PW 59ec ec\n    9 PC 59ec\n07a5 59ec f459 4316 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 12\n\ned4a    ADC HL,BC\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 4a\n    8 MC 0002\n    9 MC 0002\n   10 MC 0002\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n57a8 24b5 83d2 bf7e 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 15\n\ned4b    LD BC,(nn)\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 4b\n    8 MC 0002\n   11 MR 0002 1a\n   11 MC 0003\n   14 MR 0003 a4\n   14 MC a41a\n   17 MR a41a f3\n   17 MC a41b\n   20 MR a41b d4\n650c d4f3 0448 a3b9 0000 0000 0000 0000 0000 0000 b554 0004\n00 02 0 0 0 0 20\n\ned4c    NEG*\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 4c\naabb 7dde b049 939d 0000 0000 0000 0000 0000 0000 c7bb 0002\n00 02 0 0 0 0 8\n\ned4d    RETI\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 4d\n    8 MC 680e\n   11 MR 680e 03\n   11 MC 680f\n   14 MR 680f 7c\n1bed c358 5fd5 6093 0000 0000 0000 0000 0000 0000 6810 7c03\n00 02 0 0 0 0 14\n\ned4e    IM 0*\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 4e\n8e01 e7c6 880f d2a2 0000 0000 0000 0000 0000 0000 85da 0002\n00 02 0 0 0 0 8\n\ned4f    LD R,A\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 4f\n    8 MC 0002\n2ae3 c115 eff8 9f6d 0000 0000 0000 0000 0000 0000 0000 0002\n00 2a 0 0 0 0 9\n\ned50    IN D,(C)\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 50\n    9 PR bbcc bb\n    9 PC bbcc\n85ac bbcc bba8 f219 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 12\n\ned51    OUT (C),D\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 51\n    9 PW c0a4 53\n    9 PC c0a4\n2c4c c0a4 5303 bc25 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 12\n\ned52    SBC HL,DE\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 52\n    8 MC 0002\n    9 MC 0002\n   10 MC 0002\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\nfc82 1fc8 47b6 92c5 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 15\n\ned53    LD (nn),DE\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 53\n    8 MC 0002\n   11 MR 0002 ff\n   11 MC 0003\n   14 MR 0003 21\n   14 MC 21ff\n   17 MW 21ff b2\n   17 MC 2200\n   20 MW 2200 5c\n1f88 4692 5cb2 4915 0000 0000 0000 0000 0000 0000 7d8c 0004\n00 02 0 0 0 0 20\n21ff b2 5c -1\n\ned54    NEG*\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 54\n5313 5661 547c c322 0000 0000 0000 0000 0000 0000 d9eb 0002\n00 02 0 0 0 0 8\n\ned55    RETN*\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 55\n    8 MC d4b4\n   11 MR d4b4 ea\n   11 MC d4b5\n   14 MR d4b5 c9\nb05b 5e84 d6e9 cb3e 0000 0000 0000 0000 0000 0000 d4b6 c9ea\n00 02 0 0 0 0 14\n\ned56    IM 1\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 56\n5cc0 9100 356b 4bfd 0000 0000 0000 0000 0000 0000 2c93 0002\n00 02 0 0 1 0 8\n\ned57    LD A,I\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 57\n    8 MC 1e19\n1e08 dfc7 a621 1022 0000 0000 0000 0000 0000 0000 0000 0002\n1e 19 0 0 0 0 9\n\ned58    IN E,(C)\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 58\n    8 PC 4091\n    9 PR 4091 40\n    9 PC 4091\n   10 PC 4091\n   11 PC 4091\nc900 4091 9e40 873a 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 12\n\ned59    OUT (C),E\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 59\n    9 PW d512 c5\n    9 PC d512\n388a d512 ecc5 93af 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 12\n\ned5a    ADC HL,DE\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 5a\n    8 MC 0002\n    9 MC 0002\n   10 MC 0002\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\na408 751c 19ce 1e62 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 15\n\ned5b    LD DE,(nn)\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 5b\n    8 MC 0002\n   11 MR 0002 04\n   11 MC 0003\n   14 MR 0003 9f\n   14 MC 9f04\n   17 MR 9f04 84\n   17 MC 9f05\n   20 MR 9f05 4d\n5df1 982e 4d84 adb9 0000 0000 0000 0000 0000 0000 f398 0004\n00 02 0 0 0 0 20\n\ned5c    NEG*\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 5c\nefbb b86c 2042 c958 0000 0000 0000 0000 0000 0000 93dc 0002\n00 02 0 0 0 0 8\n\ned5d    RETN*\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 5d\n    8 MC 5308\n   11 MR 5308 26\n   11 MC 5309\n   14 MR 5309 e0\n1152 1d20 3f86 64fc 0000 0000 0000 0000 0000 0000 530a e026\n00 02 0 0 0 0 14\n\ned5e    IM 2\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 5e\n611a c8cf f215 d92b 0000 0000 0000 0000 0000 0000 4d86 0002\n00 02 0 0 2 0 8\n\ned5f    LD A,R\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 5f\n    8 MC d7f5\nf5a1 fc09 2dfa bab9 0000 0000 0000 0000 0000 0000 0000 0002\nd7 f5 0 0 0 0 9\n\ned60    IN H,(C)\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 60\n    9 PR 0dae 0d\n    9 PC 0dae\n2c08 0dae 621e 0d66 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 12\n\ned61    OUT (C),H\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 61\n    9 PW 90ca d8\n    9 PC 90ca\nffa8 90ca 0340 d847 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 12\n\ned62    SBC HL,HL\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 62\n    8 MC 0002\n    9 MC 0002\n   10 MC 0002\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\na6bb d9aa 6623 ffff 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 15\n\ned62_1  SBC HL,HL\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 62\n    8 MC 0002\n    9 MC 0002\n   10 MC 0002\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n8942 1563 7e1f 0000 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 15\n\ned63    LD (nn),HL\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 63\n    8 MC 0002\n   11 MR 0002 67\n   11 MC 0003\n   14 MR 0003 65\n   14 MC 6567\n   17 MW 6567 d3\n   17 MC 6568\n   20 MW 6568 e4\n5222 88f9 9d9a e4d3 0000 0000 0000 0000 0000 0000 a2f0 0004\n00 02 0 0 0 0 20\n6567 d3 e4 -1\n\ned64    NEG*\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 64\ndf9b e425 66ac b2a3 0000 0000 0000 0000 0000 0000 43f2 0002\n00 02 0 0 0 0 8\n\ned65    RETN*\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 65\n    8 MC f207\n   11 MR f207 eb\n   11 MC f208\n   14 MR f208 0e\n63d2 1fa1 0788 881c 0000 0000 0000 0000 0000 0000 f209 0eeb\n00 02 1 1 0 0 14\n\ned66    IM 0*\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 66\n4088 a7e1 3ffd 919b 0000 0000 0000 0000 0000 0000 d193 0002\n00 02 0 0 0 0 8\n\ned67    RRD\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 67\n    8 MC b9de\n   11 MR b9de 93\n   11 MC b9de\n   12 MC b9de\n   13 MC b9de\n   14 MC b9de\n   15 MC b9de\n   18 MW b9de 69\n3324 b16a a4db b9de 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 18\nb9de 69 -1\n\ned68    IN L,(C)\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 68\n    8 PC 624b\n    9 PR 624b 62\n    9 PC 624b\n   10 PC 624b\n   11 PC 624b\n5320 624b 7311 3162 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 12\n\ned69    OUT (C),L\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 69\n    9 PW 8d2f d6\nabd8 8d2f 89c7 c3d6 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 12\n\ned6a    ADC HL,HL\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 6a\n    8 MC 0002\n    9 MC 0002\n   10 MC 0002\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\nbb9c 6fed 59bb 9c80 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 15\n\ned6b    LD HL,(nn)\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 6b\n    8 MC 0002\n   11 MR 0002 98\n   11 MC 0003\n   14 MR 0003 61\n   14 MC 6198\n   17 MR 6198 3f\n   17 MC 6199\n   20 MR 6199 be\n9e35 d240 1998 be3f 0000 0000 0000 0000 0000 0000 9275 0004\n00 02 0 0 0 0 20\n\ned6c    NEG*\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 6c\nf1b3 7d5b cadb 0893 0000 0000 0000 0000 0000 0000 d983 0002\n00 02 0 0 0 0 8\n\ned6d    RETN*\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 6d\n    8 MC 5cd3\n   11 MR 5cd3 a9\n   11 MC 5cd4\n   14 MR 5cd4 73\n3860 42da 5935 dc10 0000 0000 0000 0000 0000 0000 5cd5 73a9\n00 02 0 0 0 0 14\n\ned6e    IM 0*\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 6e\n7752 bec3 0457 8c95 0000 0000 0000 0000 0000 0000 a787 0002\n00 02 0 0 0 0 8\n\ned6f    RLD\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 6f\n    8 MC 403c\n   11 MR 403c c4\n   11 MC 403c\n   12 MC 403c\n   13 MC 403c\n   14 MC 403c\n   15 MC 403c\n   18 MW 403c 45\n6c2d 7a7a ecf0 403c 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 18\n403c 45 -1\n\ned70    IN F,(C)*\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 70\n    9 PR f7d6 f7\n    9 PC f7d6\nc6a1 f7d6 a3cb 288d 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 12\n\ned71    OUT (C),0*\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 71\n    9 PW 20b3 00\nafa0 20b3 7b33 4ac1 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 12\n\ned72    SBC HL,SP\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 72\n    8 MC 0002\n    9 MC 0002\n   10 MC 0002\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n5f3e 05cb 0c6c 7daf 0000 0000 0000 0000 0000 0000 53db 0002\n00 02 0 0 0 0 15\n\ned73    LD (nn),SP\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 73\n    8 MC 0002\n   11 MR 0002 2a\n   11 MC 0003\n   14 MR 0003 79\n   14 MC 792a\n   17 MW 792a d5\n   17 MC 792b\n   20 MW 792b ae\n41c4 763a ecb0 ee62 0000 0000 0000 0000 0000 0000 aed5 0004\n00 02 0 0 0 0 20\n792a d5 ae -1\n\ned74    NEG*\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 74\nbcbb f2d2 8340 7e76 0000 0000 0000 0000 0000 0000 0323 0002\n00 02 0 0 0 0 8\n\ned75    RETN*\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 75\n    8 MC 7d00\n   11 MR 7d00 fd\n   11 MC 7d01\n   14 MR 7d01 4f\n7ca4 1615 5d2a a95b 0000 0000 0000 0000 0000 0000 7d02 4ffd\n00 02 1 1 0 0 14\n\ned76    IM 1*\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 76\ncabf ff9a b98c a8e6 0000 0000 0000 0000 0000 0000 fe8e 0002\n00 02 0 0 1 0 8\n\ned78    IN A,(C)\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 78\n    9 PR f206 f2\n    9 PC f206\nf2a1 f206 2d6a af16 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 12\n\ned79    OUT (C),A\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 79\n    8 PC 4243\n    9 PW 4243 e0\n    9 PC 4243\n   10 PC 4243\n   11 PC 4243\ne000 4243 8f7f ed90 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 12\n\ned7a    ADC HL,SP\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 7a\n    8 MC 0002\n    9 MC 0002\n   10 MC 0002\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n32b8 d819 d873 eaf2 0000 0000 0000 0000 0000 0000 5d22 0002\n00 02 0 0 0 0 15\n\ned7b    LD SP,(nn)\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 7b\n    8 MC 0002\n   11 MR 0002 50\n   11 MC 0003\n   14 MR 0003 8c\n   14 MC 8c50\n   17 MR 8c50 d8\n   17 MC 8c51\n   20 MR 8c51 48\n4f97 24b7 e105 1bf2 0000 0000 0000 0000 0000 0000 48d8 0004\n00 02 0 0 0 0 20\n\ned7c    NEG*\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 7c\n2d3b 29ca 9622 b452 0000 0000 0000 0000 0000 0000 0be6 0002\n00 02 0 0 0 0 8\n\ned7d    RETN*\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 7d\n    8 MC 66f0\n   11 MR 66f0 4f\n   11 MC 66f1\n   14 MR 66f1 fb\necb6 073e dc1e 38d9 0000 0000 0000 0000 0000 0000 66f2 fb4f\n00 02 1 1 0 0 14\n\ned7e    IM 2*\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 7e\nb246 1a1a 933a 4b8b 0000 0000 0000 0000 0000 0000 2242 0002\n00 02 0 0 2 0 8\n\neda0    LDI\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 a0\n    8 MC d097\n   11 MR d097 b7\n   11 MC 95c1\n   14 MW 95c1 b7\n   14 MC 95c1\n   15 MC 95c1\n1be5 3d10 95c2 d098 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 16\n95c1 b7 -1\n\neda1    CPI\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 a1\n    8 MC 3bc3\n   11 MR 3bc3 b4\n   11 MC 3bc3\n   12 MC 3bc3\n   13 MC 3bc3\n   14 MC 3bc3\n   15 MC 3bc3\nec0f 7665 537f 3bc4 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 16\n\neda2    INI\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 a2\n    8 MC 0002\n   10 PR 9a82 9a\n   10 PC 9a82\n   13 MC 2666\n   16 MW 2666 9a\n019f 9982 5bbd 2667 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 16\n2666 9a -1\n\neda2_01 INI\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 a2\n    8 MC 0002\n   10 PR 0200 02\n   10 PC 0200\n   13 MC 8000\n   16 MW 8000 02\n0000 0100 0000 8001 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 16\n8000 02 -1\n\neda2_02 INI\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 a2\n    8 MC 0002\n    9 PC 569a\n   10 PR 569a 56\n   10 PC 569a\n   13 MC 8000\n   16 MW 8000 56\n0000 559a 0000 8001 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 16\n8000 56 -1\n\neda2_03 INI\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 a2\n    8 MC 0002\n   10 PR abcc ab\n   10 PC abcc\n   13 MC 8000\n   16 MW 8000 ab\n00bf aacc 0000 8001 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 16\n8000 ab -1\n\neda3    OUTI\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 a3\n    8 MC 0002\n    9 MC 32fa\n   12 MR 32fa b3\n   12 PC 6234\n   13 PW 6234 b3\n   13 PC 6234\n4233 6234 1e28 32fb 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 16\n\neda3_01 OUTI\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 a3\n    8 MC 0002\n    9 MC 01ff\n   12 MR 01ff 00\n   13 PW 0000 00\n   13 PC 0000\n0044 0000 0000 0200 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 16\n\neda3_02 OUTI\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 a3\n    8 MC 0002\n    9 MC 0100\n   12 MR 0100 00\n   13 PW 0000 00\n   13 PC 0000\n0040 0000 0000 0101 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 16\n\neda3_03 OUTI\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 a3\n    8 MC 0002\n    9 MC 0107\n   12 MR 0107 00\n   13 PW 0000 00\n   13 PC 0000\n0044 0000 0000 0108 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 16\n\neda3_04 OUTI\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 a3\n    8 MC 0002\n    9 MC 01ff\n   12 MR 01ff 80\n   13 PW 0000 80\n   13 PC 0000\n0046 0000 0000 0200 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 16\n\neda3_05 OUTI\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 a3\n    8 MC 0002\n    9 MC 01fd\n   12 MR 01fd 12\n   13 PW 0000 12\n   13 PC 0000\n0055 0000 0000 01fe 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 16\n\neda3_06 OUTI\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 a3\n    8 MC 0002\n    9 MC 01fe\n   12 MR 01fe 12\n   13 PW 0000 12\n   13 PC 0000\n0051 0000 0000 01ff 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 16\n\neda3_07 OUTI\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 a3\n    8 MC 0002\n    9 MC 01ff\n   12 MR 01ff 00\n   13 PW 0100 00\n   13 PC 0100\n0000 0100 0000 0200 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 16\n\neda3_08 OUTI\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 a3\n    8 MC 0002\n    9 MC 01fe\n   12 MR 01fe 00\n   13 PW 0700 00\n   13 PC 0700\n0004 0700 0000 01ff 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 16\n\neda3_09 OUTI\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 a3\n    8 MC 0002\n    9 MC 01ff\n   12 MR 01ff 00\n   13 PW 8000 00\n   13 PC 8000\n0080 8000 0000 0200 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 16\n\neda3_10 OUTI\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 a3\n    8 MC 0002\n    9 MC 01ff\n   12 MR 01ff 00\n   13 PW 8100 00\n   13 PC 8100\n0084 8100 0000 0200 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 16\n\neda3_11 OUTI\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 a3\n    8 MC 0002\n    9 MC 01ff\n   12 MR 01ff 00\n   13 PW a800 00\n   13 PC a800\n00a8 a800 0000 0200 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 16\n\neda8    LDD\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 a8\n    8 MC 12e8\n   11 MR 12e8 d8\n   11 MC 5938\n   14 MW 5938 d8\n   14 MC 5938\n   15 MC 5938\n2aa4 1606 5937 12e7 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 16\n5938 d8 -1\n\neda9    CPD\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 a9\n    8 MC 0dbe\n   11 MR 0dbe 89\n   11 MC 0dbe\n   12 MC 0dbe\n   13 MC 0dbe\n   14 MC 0dbe\n   15 MC 0dbe\n14bf fb41 0466 0dbd 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 16\n\nedaa    IND\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 aa\n    8 MC 0002\n   10 PR d791 d7\n   13 MC a533\n   16 MW a533 d7\n2097 d691 a912 a532 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 16\na533 d7 -1\n\nedaa_01 IND\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 aa\n    8 MC 0002\n   10 PR 0101 01\n   13 MC 8000\n   16 MW 8000 01\n0040 0001 0000 7fff 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 16\n8000 01 -1\n\nedaa_02 IND\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 aa\n    8 MC 0002\n    9 PC 56aa\n   10 PR 56aa 56\n   10 PC 56aa\n   13 MC 8000\n   16 MW 8000 56\n0000 55aa 0000 7fff 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 16\n8000 56 -1\n\nedaa_03 IND\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 aa\n    8 MC 0002\n   10 PR abcc ab\n   10 PC abcc\n   13 MC 8000\n   16 MW 8000 ab\n00bf aacc 0000 7fff 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 16\n8000 ab -1\n\nedab    OUTD\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 ab\n    8 MC 0002\n    9 MC 199f\n   12 MR 199f 49\n   13 PW f234 49\n   13 PC f234\n00a4 f234 d3e1 199e 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 16\n\nedab_01 OUTD\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 ab\n    8 MC 0002\n    9 MC 007a\n   12 MR 007a 7f\n   12 PC 5700\n   13 PW 5700 7f\n   13 PC 5700\n0000 5700 0000 0079 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 16\n\nedab_02 OUTD\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 ab\n    8 MC 0002\n    9 MC 00f1\n   12 MR 00f1 cd\n   13 PW aa00 cd\n   13 PC aa00\n00bf aa00 0000 00f0 0000 0000 0000 0000 0000 0000 0000 0002\n00 02 0 0 0 0 16\n\nedb0    LDIR\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 b0\n    8 MC 558e\n   11 MR 558e 53\n   11 MC aad8\n   14 MW aad8 53\n   14 MC aad8\n   15 MC aad8\n   16 MC aad8\n   17 MC aad8\n   18 MC aad8\n   19 MC aad8\n   20 MC aad8\n   21 MC 0000\n   25 MR 0000 ed\n   25 MC 0001\n   29 MR 0001 b0\n   29 MC 558f\n   32 MR 558f 94\n   32 MC aad9\n   35 MW aad9 94\n   35 MC aad9\n   36 MC aad9\n   37 MC aad9\n   38 MC aad9\n   39 MC aad9\n   40 MC aad9\n   41 MC aad9\n   42 MC 0000\n   46 MR 0000 ed\n   46 MC 0001\n   50 MR 0001 b0\n   50 MC 5590\n   53 MR 5590 30\n   53 MC aada\n   56 MW aada 30\n   56 MC aada\n   57 MC aada\n   58 MC aada\n   59 MC aada\n   60 MC aada\n   61 MC aada\n   62 MC aada\n   63 MC 0000\n   67 MR 0000 ed\n   67 MC 0001\n   71 MR 0001 b0\n   71 MC 5591\n   74 MR 5591 05\n   74 MC aadb\n   77 MW aadb 05\n   77 MC aadb\n   78 MC aadb\n   79 MC aadb\n   80 MC aadb\n   81 MC aadb\n   82 MC aadb\n   83 MC aadb\n   84 MC 0000\n   88 MR 0000 ed\n   88 MC 0001\n   92 MR 0001 b0\n   92 MC 5592\n   95 MR 5592 44\n   95 MC aadc\n   98 MW aadc 44\n   98 MC aadc\n   99 MC aadc\n  100 MC aadc\n  101 MC aadc\n  102 MC aadc\n  103 MC aadc\n  104 MC aadc\n  105 MC 0000\n  109 MR 0000 ed\n  109 MC 0001\n  113 MR 0001 b0\n  113 MC 5593\n  116 MR 5593 24\n  116 MC aadd\n  119 MW aadd 24\n  119 MC aadd\n  120 MC aadd\n  121 MC aadd\n  122 MC aadd\n  123 MC aadd\n  124 MC aadd\n  125 MC aadd\n  126 MC 0000\n  130 MR 0000 ed\n  130 MC 0001\n  134 MR 0001 b0\n  134 MC 5594\n  137 MR 5594 22\n  137 MC aade\n  140 MW aade 22\n  140 MC aade\n  141 MC aade\n  142 MC aade\n  143 MC aade\n  144 MC aade\n  145 MC aade\n  146 MC aade\n  147 MC 0000\n  151 MR 0000 ed\n  151 MC 0001\n  155 MR 0001 b0\n  155 MC 5595\n  158 MR 5595 b9\n  158 MC aadf\n  161 MW aadf b9\n  161 MC aadf\n  162 MC aadf\n  163 MC aadf\n  164 MC aadf\n  165 MC aadf\n  166 MC aadf\n  167 MC aadf\n  168 MC 0000\n  172 MR 0000 ed\n  172 MC 0001\n  176 MR 0001 b0\n  176 MC 5596\n  179 MR 5596 e9\n  179 MC aae0\n  182 MW aae0 e9\n  182 MC aae0\n  183 MC aae0\n  184 MC aae0\n  185 MC aae0\n  186 MC aae0\n  187 MC aae0\n  188 MC aae0\n  189 MC 0000\n  193 MR 0000 ed\n  193 MC 0001\n  197 MR 0001 b0\n  197 MC 5597\n  200 MR 5597 77\n  200 MC aae1\n  203 MW aae1 77\n  203 MC aae1\n  204 MC aae1\n  205 MC aae1\n  206 MC aae1\n  207 MC aae1\n  208 MC aae1\n  209 MC aae1\n  210 MC 0000\n  214 MR 0000 ed\n  214 MC 0001\n  218 MR 0001 b0\n  218 MC 5598\n  221 MR 5598 23\n  221 MC aae2\n  224 MW aae2 23\n  224 MC aae2\n  225 MC aae2\n  226 MC aae2\n  227 MC aae2\n  228 MC aae2\n  229 MC aae2\n  230 MC aae2\n  231 MC 0000\n  235 MR 0000 ed\n  235 MC 0001\n  239 MR 0001 b0\n  239 MC 5599\n  242 MR 5599 71\n  242 MC aae3\n  245 MW aae3 71\n  245 MC aae3\n  246 MC aae3\n  247 MC aae3\n  248 MC aae3\n  249 MC aae3\n  250 MC aae3\n  251 MC aae3\n  252 MC 0000\n  256 MR 0000 ed\n  256 MC 0001\n  260 MR 0001 b0\n  260 MC 559a\n  263 MR 559a e2\n  263 MC aae4\n  266 MW aae4 e2\n  266 MC aae4\n  267 MC aae4\n  268 MC aae4\n  269 MC aae4\n  270 MC aae4\n  271 MC aae4\n  272 MC aae4\n  273 MC 0000\n  277 MR 0000 ed\n  277 MC 0001\n  281 MR 0001 b0\n  281 MC 559b\n  284 MR 559b 5c\n  284 MC aae5\n  287 MW aae5 5c\n  287 MC aae5\n  288 MC aae5\n  289 MC aae5\n  290 MC aae5\n  291 MC aae5\n  292 MC aae5\n  293 MC aae5\n  294 MC 0000\n  298 MR 0000 ed\n  298 MC 0001\n  302 MR 0001 b0\n  302 MC 559c\n  305 MR 559c fb\n  305 MC aae6\n  308 MW aae6 fb\n  308 MC aae6\n  309 MC aae6\n  310 MC aae6\n  311 MC aae6\n  312 MC aae6\n  313 MC aae6\n  314 MC aae6\n  315 MC 0000\n  319 MR 0000 ed\n  319 MC 0001\n  323 MR 0001 b0\n  323 MC 559d\n  326 MR 559d 49\n  326 MC aae7\n  329 MW aae7 49\n  329 MC aae7\n  330 MC aae7\n1049 0000 aae8 559e 0000 0000 0000 0000 0000 0000 0000 0002\n00 20 0 0 0 0 331\naad8 53 94 30 05 44 24 22 b9 e9 77 23 71 e2 5c fb 49 -1\n\nedb1    CPIR\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 b1\n    8 MC 9825\n   11 MR 9825 50\n   11 MC 9825\n   12 MC 9825\n   13 MC 9825\n   14 MC 9825\n   15 MC 9825\n   16 MC 9825\n   17 MC 9825\n   18 MC 9825\n   19 MC 9825\n   20 MC 9825\n   21 MC 0000\n   25 MR 0000 ed\n   25 MC 0001\n   29 MR 0001 b1\n   29 MC 9826\n   32 MR 9826 e5\n   32 MC 9826\n   33 MC 9826\n   34 MC 9826\n   35 MC 9826\n   36 MC 9826\n   37 MC 9826\n   38 MC 9826\n   39 MC 9826\n   40 MC 9826\n   41 MC 9826\n   42 MC 0000\n   46 MR 0000 ed\n   46 MC 0001\n   50 MR 0001 b1\n   50 MC 9827\n   53 MR 9827 41\n   53 MC 9827\n   54 MC 9827\n   55 MC 9827\n   56 MC 9827\n   57 MC 9827\n   58 MC 9827\n   59 MC 9827\n   60 MC 9827\n   61 MC 9827\n   62 MC 9827\n   63 MC 0000\n   67 MR 0000 ed\n   67 MC 0001\n   71 MR 0001 b1\n   71 MC 9828\n   74 MR 9828 f4\n   74 MC 9828\n   75 MC 9828\n   76 MC 9828\n   77 MC 9828\n   78 MC 9828\nf447 0004 e4e0 9829 0000 0000 0000 0000 0000 0000 0000 0002\n00 08 0 0 0 0 79\n\nedb2    INIR\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 b2\n    8 MC 0002\n   10 PR 0a40 0a\n   10 PC 0a40\n   13 MC 37ce\n   16 MW 37ce 0a\n   16 MC 37ce\n   17 MC 37ce\n   18 MC 37ce\n   19 MC 37ce\n   20 MC 37ce\n   21 MC 0000\n   25 MR 0000 ed\n   25 MC 0001\n   29 MR 0001 b2\n   29 MC 0004\n   31 PR 0940 09\n   31 PC 0940\n   34 MC 37cf\n   37 MW 37cf 09\n   37 MC 37cf\n   38 MC 37cf\n   39 MC 37cf\n   40 MC 37cf\n   41 MC 37cf\n   42 MC 0000\n   46 MR 0000 ed\n   46 MC 0001\n   50 MR 0001 b2\n   50 MC 0006\n   52 PR 0840 08\n   52 PC 0840\n   55 MC 37d0\n   58 MW 37d0 08\n   58 MC 37d0\n   59 MC 37d0\n   60 MC 37d0\n   61 MC 37d0\n   62 MC 37d0\n   63 MC 0000\n   67 MR 0000 ed\n   67 MC 0001\n   71 MR 0001 b2\n   71 MC 0008\n   73 PR 0740 07\n   73 PC 0740\n   76 MC 37d1\n   79 MW 37d1 07\n   79 MC 37d1\n   80 MC 37d1\n   81 MC 37d1\n   82 MC 37d1\n   83 MC 37d1\n   84 MC 0000\n   88 MR 0000 ed\n   88 MC 0001\n   92 MR 0001 b2\n   92 MC 000a\n   94 PR 0640 06\n   94 PC 0640\n   97 MC 37d2\n  100 MW 37d2 06\n  100 MC 37d2\n  101 MC 37d2\n  102 MC 37d2\n  103 MC 37d2\n  104 MC 37d2\n  105 MC 0000\n  109 MR 0000 ed\n  109 MC 0001\n  113 MR 0001 b2\n  113 MC 000c\n  115 PR 0540 05\n  115 PC 0540\n  118 MC 37d3\n  121 MW 37d3 05\n  121 MC 37d3\n  122 MC 37d3\n  123 MC 37d3\n  124 MC 37d3\n  125 MC 37d3\n  126 MC 0000\n  130 MR 0000 ed\n  130 MC 0001\n  134 MR 0001 b2\n  134 MC 000e\n  136 PR 0440 04\n  136 PC 0440\n  139 MC 37d4\n  142 MW 37d4 04\n  142 MC 37d4\n  143 MC 37d4\n  144 MC 37d4\n  145 MC 37d4\n  146 MC 37d4\n  147 MC 0000\n  151 MR 0000 ed\n  151 MC 0001\n  155 MR 0001 b2\n  155 MC 0010\n  157 PR 0340 03\n  157 PC 0340\n  160 MC 37d5\n  163 MW 37d5 03\n  163 MC 37d5\n  164 MC 37d5\n  165 MC 37d5\n  166 MC 37d5\n  167 MC 37d5\n  168 MC 0000\n  172 MR 0000 ed\n  172 MC 0001\n  176 MR 0001 b2\n  176 MC 0012\n  178 PR 0240 02\n  178 PC 0240\n  181 MC 37d6\n  184 MW 37d6 02\n  184 MC 37d6\n  185 MC 37d6\n  186 MC 37d6\n  187 MC 37d6\n  188 MC 37d6\n  189 MC 0000\n  193 MR 0000 ed\n  193 MC 0001\n  197 MR 0001 b2\n  197 MC 0014\n  199 PR 0140 01\n  199 PC 0140\n  202 MC 37d7\n  205 MW 37d7 01\n8a40 0040 d98c 37d8 0000 0000 0000 0000 0000 0000 0000 0002\n00 14 0 0 0 0 205\n37ce 0a 09 08 07 06 05 04 03 02 01 -1\n\nedb3    OTIR\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 b3\n    8 MC 0002\n    9 MC 1d7c\n   12 MR 1d7c 9d\n   13 PW 02e0 9d\n   13 PC 02e0\n   16 MC 02e0\n   17 MC 02e0\n   18 MC 02e0\n   19 MC 02e0\n   20 MC 02e0\n   21 MC 0000\n   25 MR 0000 ed\n   25 MC 0001\n   29 MR 0001 b3\n   29 MC 0004\n   30 MC 1d7d\n   33 MR 1d7d 24\n   34 PW 01e0 24\n   34 PC 01e0\n   37 MC 01e0\n   38 MC 01e0\n   39 MC 01e0\n   40 MC 01e0\n   41 MC 01e0\n   42 MC 0000\n   46 MR 0000 ed\n   46 MC 0001\n   50 MR 0001 b3\n   50 MC 0006\n   51 MC 1d7e\n   54 MR 1d7e aa\n   55 PW 00e0 aa\n   55 PC 00e0\n3453 00e0 41b9 1d7f 0000 0000 0000 0000 0000 0000 0000 0002\n00 06 0 0 0 0 58\n\nedb8    LDDR\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 b8\n    8 MC 4dcf\n   11 MR 4dcf 0a\n   11 MC 68e8\n   14 MW 68e8 0a\n   14 MC 68e8\n   15 MC 68e8\n   16 MC 68e8\n   17 MC 68e8\n   18 MC 68e8\n   19 MC 68e8\n   20 MC 68e8\n   21 MC 0000\n   25 MR 0000 ed\n   25 MC 0001\n   29 MR 0001 b8\n   29 MC 4dce\n   32 MR 4dce 23\n   32 MC 68e7\n   35 MW 68e7 23\n   35 MC 68e7\n   36 MC 68e7\n   37 MC 68e7\n   38 MC 68e7\n   39 MC 68e7\n   40 MC 68e7\n   41 MC 68e7\n   42 MC 0000\n   46 MR 0000 ed\n   46 MC 0001\n   50 MR 0001 b8\n   50 MC 4dcd\n   53 MR 4dcd 74\n   53 MC 68e6\n   56 MW 68e6 74\n   56 MC 68e6\n   57 MC 68e6\n   58 MC 68e6\n   59 MC 68e6\n   60 MC 68e6\n   61 MC 68e6\n   62 MC 68e6\n   63 MC 0000\n   67 MR 0000 ed\n   67 MC 0001\n   71 MR 0001 b8\n   71 MC 4dcc\n   74 MR 4dcc 55\n   74 MC 68e5\n   77 MW 68e5 55\n   77 MC 68e5\n   78 MC 68e5\n   79 MC 68e5\n   80 MC 68e5\n   81 MC 68e5\n   82 MC 68e5\n   83 MC 68e5\n   84 MC 0000\n   88 MR 0000 ed\n   88 MC 0001\n   92 MR 0001 b8\n   92 MC 4dcb\n   95 MR 4dcb c3\n   95 MC 68e4\n   98 MW 68e4 c3\n   98 MC 68e4\n   99 MC 68e4\n  100 MC 68e4\n  101 MC 68e4\n  102 MC 68e4\n  103 MC 68e4\n  104 MC 68e4\n  105 MC 0000\n  109 MR 0000 ed\n  109 MC 0001\n  113 MR 0001 b8\n  113 MC 4dca\n  116 MR 4dca a7\n  116 MC 68e3\n  119 MW 68e3 a7\n  119 MC 68e3\n  120 MC 68e3\n  121 MC 68e3\n  122 MC 68e3\n  123 MC 68e3\n  124 MC 68e3\n  125 MC 68e3\n  126 MC 0000\n  130 MR 0000 ed\n  130 MC 0001\n  134 MR 0001 b8\n  134 MC 4dc9\n  137 MR 4dc9 85\n  137 MC 68e2\n  140 MW 68e2 85\n  140 MC 68e2\n  141 MC 68e2\n  142 MC 68e2\n  143 MC 68e2\n  144 MC 68e2\n  145 MC 68e2\n  146 MC 68e2\n  147 MC 0000\n  151 MR 0000 ed\n  151 MC 0001\n  155 MR 0001 b8\n  155 MC 4dc8\n  158 MR 4dc8 29\n  158 MC 68e1\n  161 MW 68e1 29\n  161 MC 68e1\n  162 MC 68e1\ne569 0000 68e0 4dc7 0000 0000 0000 0000 0000 0000 0000 0002\n00 10 0 0 0 0 163\n68e1 29 85 a7 c3 55 74 23 0a -1\n\nedb9    CPDR\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 b9\n    8 MC c749\n   11 MR c749 6c\n   11 MC c749\n   12 MC c749\n   13 MC c749\n   14 MC c749\n   15 MC c749\n   16 MC c749\n   17 MC c749\n   18 MC c749\n   19 MC c749\n   20 MC c749\n   21 MC 0000\n   25 MR 0000 ed\n   25 MC 0001\n   29 MR 0001 b9\n   29 MC c748\n   32 MR c748 4e\n   32 MC c748\n   33 MC c748\n   34 MC c748\n   35 MC c748\n   36 MC c748\n   37 MC c748\n   38 MC c748\n   39 MC c748\n   40 MC c748\n   41 MC c748\n   42 MC 0000\n   46 MR 0000 ed\n   46 MC 0001\n   50 MR 0001 b9\n   50 MC c747\n   53 MR c747 01\n   53 MC c747\n   54 MC c747\n   55 MC c747\n   56 MC c747\n   57 MC c747\n   58 MC c747\n   59 MC c747\n   60 MC c747\n   61 MC c747\n   62 MC c747\n   63 MC 0000\n   67 MR 0000 ed\n   67 MC 0001\n   71 MR 0001 b9\n   71 MC c746\n   74 MR c746 5a\n   74 MC c746\n   75 MC c746\n   76 MC c746\n   77 MC c746\n   78 MC c746\n   79 MC c746\n   80 MC c746\n   81 MC c746\n   82 MC c746\n   83 MC c746\n   84 MC 0000\n   88 MR 0000 ed\n   88 MC 0001\n   92 MR 0001 b9\n   92 MC c745\n   95 MR c745 ec\n   95 MC c745\n   96 MC c745\n   97 MC c745\n   98 MC c745\n   99 MC c745\n  100 MC c745\n  101 MC c745\n  102 MC c745\n  103 MC c745\n  104 MC c745\n  105 MC 0000\n  109 MR 0000 ed\n  109 MC 0001\n  113 MR 0001 b9\n  113 MC c744\n  116 MR c744 85\n  116 MC c744\n  117 MC c744\n  118 MC c744\n  119 MC c744\n  120 MC c744\n  121 MC c744\n  122 MC c744\n  123 MC c744\n  124 MC c744\n  125 MC c744\n  126 MC 0000\n  130 MR 0000 ed\n  130 MC 0001\n  134 MR 0001 b9\n  134 MC c743\n  137 MR c743 09\n  137 MC c743\n  138 MC c743\n  139 MC c743\n  140 MC c743\n  141 MC c743\n  142 MC c743\n  143 MC c743\n  144 MC c743\n  145 MC c743\n  146 MC c743\n  147 MC 0000\n  151 MR 0000 ed\n  151 MC 0001\n  155 MR 0001 b9\n  155 MC c742\n  158 MR c742 c6\n  158 MC c742\n  159 MC c742\n  160 MC c742\n  161 MC c742\n  162 MC c742\nff0b 0000 a171 c741 0000 0000 0000 0000 0000 0000 0000 0002\n00 10 0 0 0 0 163\n\nedba    INDR\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 ba\n    8 MC 0002\n   10 PR 069f 06\n   13 MC 6b55\n   16 MW 6b55 06\n   16 MC 6b55\n   17 MC 6b55\n   18 MC 6b55\n   19 MC 6b55\n   20 MC 6b55\n   21 MC 0000\n   25 MR 0000 ed\n   25 MC 0001\n   29 MR 0001 ba\n   29 MC 0004\n   31 PR 059f 05\n   34 MC 6b54\n   37 MW 6b54 05\n   37 MC 6b54\n   38 MC 6b54\n   39 MC 6b54\n   40 MC 6b54\n   41 MC 6b54\n   42 MC 0000\n   46 MR 0000 ed\n   46 MC 0001\n   50 MR 0001 ba\n   50 MC 0006\n   52 PR 049f 04\n   55 MC 6b53\n   58 MW 6b53 04\n   58 MC 6b53\n   59 MC 6b53\n   60 MC 6b53\n   61 MC 6b53\n   62 MC 6b53\n   63 MC 0000\n   67 MR 0000 ed\n   67 MC 0001\n   71 MR 0001 ba\n   71 MC 0008\n   73 PR 039f 03\n   76 MC 6b52\n   79 MW 6b52 03\n   79 MC 6b52\n   80 MC 6b52\n   81 MC 6b52\n   82 MC 6b52\n   83 MC 6b52\n   84 MC 0000\n   88 MR 0000 ed\n   88 MC 0001\n   92 MR 0001 ba\n   92 MC 000a\n   94 PR 029f 02\n   97 MC 6b51\n  100 MW 6b51 02\n  100 MC 6b51\n  101 MC 6b51\n  102 MC 6b51\n  103 MC 6b51\n  104 MC 6b51\n  105 MC 0000\n  109 MR 0000 ed\n  109 MC 0001\n  113 MR 0001 ba\n  113 MC 000c\n  115 PR 019f 01\n  118 MC 6b50\n  121 MW 6b50 01\n2540 009f d40d 6b4f 0000 0000 0000 0000 0000 0000 0000 0002\n00 0c 0 0 0 0 121\n6b50 01 02 03 04 05 06 -1\n\nedbb    OTDR\n    0 MC 0000\n    4 MR 0000 ed\n    4 MC 0001\n    8 MR 0001 bb\n    8 MC 0002\n    9 MC 1dd0\n   12 MR 1dd0 b6\n   13 PW 033b b6\n   16 MC 033b\n   17 MC 033b\n   18 MC 033b\n   19 MC 033b\n   20 MC 033b\n   21 MC 0000\n   25 MR 0000 ed\n   25 MC 0001\n   29 MR 0001 bb\n   29 MC 0004\n   30 MC 1dcf\n   33 MR 1dcf c5\n   34 PW 023b c5\n   37 MC 023b\n   38 MC 023b\n   39 MC 023b\n   40 MC 023b\n   41 MC 023b\n   42 MC 0000\n   46 MR 0000 ed\n   46 MC 0001\n   50 MR 0001 bb\n   50 MC 0006\n   51 MC 1dce\n   54 MR 1dce 71\n   55 PW 013b 71\n   58 MC 013b\n   59 MC 013b\n   60 MC 013b\n   61 MC 013b\n   62 MC 013b\n   63 MC 0000\n   67 MR 0000 ed\n   67 MC 0001\n   71 MR 0001 bb\n   71 MC 0008\n   72 MC 1dcd\n   75 MR 1dcd f9\n   76 PW 003b f9\n0957 003b be49 1dcc 0000 0000 0000 0000 0000 0000 0000 0002\n00 08 0 0 0 0 79\n\nee      XOR n\n    0 MC 0000\n    4 MR 0000 ee\n    4 MC 0001\n    7 MR 0001 d0\neeac 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0002\n00 01 0 0 0 0 7\n\nef      RST 28H\n    0 MC 6d33\n    4 MR 6d33 ef\n    4 MC 0001\n    5 MC 5506\n    8 MW 5506 6d\n    8 MC 5505\n   11 MW 5505 34\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 5505 0028\n00 01 0 0 0 0 11\n5505 34 6d -1\n\nf0_1    RET P\n    0 MC 0000\n    4 MR 0000 f0\n    4 MC 0001\n    5 MC 43f7\n    8 MR 43f7 e9\n    8 MC 43f8\n   11 MR 43f8 af\n0018 0000 0000 0000 0000 0000 0000 0000 0000 0000 43f9 afe9\n00 01 0 0 0 0 11\n\nf0_2    RET P\n    0 MC 0000\n    4 MR 0000 f0\n    4 MC 0001\n0098 0000 0000 0000 0000 0000 0000 0000 0000 0000 43f7 0001\n00 01 0 0 0 0 5\n\nf1      POP AF\n    0 MC 0000\n    4 MR 0000 f1\n    4 MC 4143\n    7 MR 4143 ce\n    7 MC 4144\n   10 MR 4144 e8\ne8ce 0000 0000 0000 0000 0000 0000 0000 0000 0000 4145 0001\n00 01 0 0 0 0 10\n\nf2_1    JP P,nn\n    0 MC 0000\n    4 MR 0000 f2\n    4 MC 0001\n    7 MR 0001 1b\n    7 MC 0002\n   10 MR 0002 e1\n0007 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 e11b\n00 01 0 0 0 0 10\n\nf2_2    JP P,nn\n    0 MC 0000\n    4 MR 0000 f2\n    4 MC 0001\n    7 MC 0002\n0087 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0003\n00 01 0 0 0 0 10\n\nf3      DI\n    0 MC 0000\n    4 MR 0000 f3\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\nf4_1    CALL P,nn\n    0 MC 0000\n    4 MR 0000 f4\n    4 MC 0001\n    7 MR 0001 61\n    7 MC 0002\n   10 MR 0002 9c\n   10 MC 0002\n   11 MC 5697\n   14 MW 5697 00\n   14 MC 5696\n   17 MW 5696 03\n000e 0000 0000 0000 0000 0000 0000 0000 0000 0000 5696 9c61\n00 01 0 0 0 0 17\n5696 03 00 -1\n\nf4_2    CALL P,nn\n    0 MC 0000\n    4 MR 0000 f4\n    4 MC 0001\n    7 MC 0002\n008e 0000 0000 0000 0000 0000 0000 0000 0000 0000 5698 0003\n00 01 0 0 0 0 10\n\nf5      PUSH AF\n    0 MC 0000\n    4 MR 0000 f5\n    4 MC 0001\n    5 MC ec11\n    8 MW ec11 53\n    8 MC ec10\n   11 MW ec10 e3\n53e3 1459 775f 1a2f 0000 0000 0000 0000 0000 0000 ec10 0001\n00 01 0 0 0 0 11\nec10 e3 53 -1\n\nf6      OR n\n    0 MC 0000\n    4 MR 0000 f6\n    4 MC 0001\n    7 MR 0001 a7\na7a0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0002\n00 01 0 0 0 0 7\n\nf7      RST 30H\n    0 MC 6d33\n    4 MR 6d33 f7\n    4 MC 0001\n    5 MC 5506\n    8 MW 5506 6d\n    8 MC 5505\n   11 MW 5505 34\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 5505 0030\n00 01 0 0 0 0 11\n5505 34 6d -1\n\nf8_1    RET M\n    0 MC 0000\n    4 MR 0000 f8\n    4 MC 0001\n0018 0000 0000 0000 0000 0000 0000 0000 0000 0000 43f7 0001\n00 01 0 0 0 0 5\n\nf8_2    RET M\n    0 MC 0000\n    4 MR 0000 f8\n    4 MC 0001\n    5 MC 43f7\n    8 MR 43f7 e9\n    8 MC 43f8\n   11 MR 43f8 af\n0098 0000 0000 0000 0000 0000 0000 0000 0000 0000 43f9 afe9\n00 01 0 0 0 0 11\n\nf9      LD SP,HL\n    0 MC 0000\n    4 MR 0000 f9\n    4 MC 0001\n    5 MC 0001\n0000 0000 0000 ce32 0000 0000 0000 0000 0000 0000 ce32 0001\n00 01 0 0 0 0 6\n\nfa_1    JP M,nn\n    0 MC 0000\n    4 MR 0000 fa\n    4 MC 0001\n    7 MR 0001 1b\n    7 MC 0002\n   10 MR 0002 e1\n0087 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 e11b\n00 01 0 0 0 0 10\n\nfa_2    JP M,nn\n    0 MC 0000\n    4 MR 0000 fa\n    4 MC 0001\n    7 MC 0002\n0007 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0003\n00 01 0 0 0 0 10\n\nfb      EI\n    0 MC 0000\n    4 MR 0000 fb\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 1 1 0 0 4\n\nfc_1    CALL M,nn\n    0 MC 0000\n    4 MR 0000 fc\n    4 MC 0001\n    7 MR 0001 61\n    7 MC 0002\n   10 MR 0002 9c\n   10 MC 0002\n   11 MC 5697\n   14 MW 5697 00\n   14 MC 5696\n   17 MW 5696 03\n008e 0000 0000 0000 0000 0000 0000 0000 0000 0000 5696 9c61\n00 01 0 0 0 0 17\n5696 03 00 -1\n\nfc_2    CALL M,nn\n    0 MC 0000\n    4 MR 0000 fc\n    4 MC 0001\n    7 MC 0002\n000e 0000 0000 0000 0000 0000 0000 0000 0000 0000 5698 0003\n00 01 0 0 0 0 10\n\nfd09    ADD IY,BC\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 09\n    8 MC 0002\n    9 MC 0002\n   10 MC 0002\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n4649 a623 bab2 d788 0000 0000 0000 0000 c9e8 9cbb 0000 0002\n00 02 0 0 0 0 15\n\nfd19    ADD IY,DE\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 19\n    8 MC 0002\n    9 MC 0002\n   10 MC 0002\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\nb3ec 5336 76cb 54e2 0000 0000 0000 0000 b9ce fcef 0000 0002\n00 02 0 0 0 0 15\n\nfd21    LD IY,nn\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 21\n    8 MC 0002\n   11 MR 0002 46\n   11 MC 0003\n   14 MR 0003 47\nc924 5c83 e0e2 eddb 0000 0000 0000 0000 6e9f 4746 0000 0004\n00 02 0 0 0 0 14\n\nfd22    LD (nn),IY\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 22\n    8 MC 0002\n   11 MR 0002 9a\n   11 MC 0003\n   14 MR 0003 e2\n   14 MC e29a\n   17 MW e29a e4\n   17 MC e29b\n   20 MW e29b 81\n1235 f0b6 b74c cc9f 0000 0000 0000 0000 8b00 81e4 0000 0004\n00 02 0 0 0 0 20\ne29a e4 81 -1\n\nfd23    INC IY\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 23\n    8 MC 0002\n    9 MC 0002\n69f2 c1d3 0f6f 2169 0000 0000 0000 0000 e39e 2606 0000 0002\n00 02 0 0 0 0 10\n\nfd24    INC IYh*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 24\n5520 9684 d36a dac3 0000 0000 0000 0000 7803 6534 0000 0002\n00 02 0 0 0 0 8\n\nfd25    DEC IYh*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 25\ncd03 b5e4 a754 9526 0000 0000 0000 0000 3dcb 02b2 0000 0002\n00 02 0 0 0 0 8\n\nfd26    LD IYh,n*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 26\n    8 MC 0002\n   11 MR 0002 77\n2452 300b b4a1 929d 0000 0000 0000 0000 c259 7730 0000 0003\n00 02 0 0 0 0 11\n\nfd29    ADD IY,IY\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 29\n    8 MC 0002\n    9 MC 0002\n   10 MC 0002\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n5830 49d0 ec95 011c 0000 0000 0000 0000 ec6c b298 0000 0002\n00 02 0 0 0 0 15\n\nfd2a    LD IY,(nn)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 2a\n    8 MC 0002\n   11 MR 0002 91\n   11 MC 0003\n   14 MR 0003 f9\n   14 MC f991\n   17 MR f991 92\n   17 MC f992\n   20 MR f992 bf\n0f82 3198 87e3 7c1c 0000 0000 0000 0000 1bb4 bf92 0000 0004\n00 02 0 0 0 0 20\n\nfd2b    DEC IY\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 2b\n    8 MC 0002\n    9 MC 0002\nab27 942f 82fa 6f2f 0000 0000 0000 0000 9438 ebbb 0000 0002\n00 02 0 0 0 0 10\n\nfd2c    INC IYl*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 2c\n66a9 0ab1 5656 e5a9 0000 0000 0000 0000 5fb9 4df8 0000 0002\n00 02 0 0 0 0 8\n\nfd2d    DEC IYl*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 2d\n320b f78a b906 31d0 0000 0000 0000 0000 c72a e91b 0000 0002\n00 02 0 0 0 0 8\n\nfd2e    LD IYl,n*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 2e\n    8 MC 0002\n   11 MR 0002 49\n2114 4923 6e65 006c 0000 0000 0000 0000 da39 c049 0000 0003\n00 02 0 0 0 0 11\n\nfd34    INC (IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 34\n    8 MC 0002\n   11 MR 0002 b8\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC ef7c\n   19 MR ef7c e0\n   19 MC ef7c\n   20 MC ef7c\n   23 MW ef7c e1\nd5a0 6f24 7df7 74f0 0000 0000 0000 0000 365a efc4 0000 0003\n00 02 0 0 0 0 23\nef7c e1 -1\n\nfd35    DEC (IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 35\n    8 MC 0002\n   11 MR 0002 ab\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC ae71\n   19 MR ae71 a6\n   19 MC ae71\n   20 MC ae71\n   23 MW ae71 a5\n8ca2 35d8 7c1a 1c0a 0000 0000 0000 0000 62bb aec6 0000 0003\n00 02 0 0 0 0 23\nae71 a5 -1\n\nfd36    LD (IY+d),n\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 36\n    8 MC 0002\n   11 MR 0002 81\n   11 MC 0003\n   14 MR 0003 c5\n   14 MC 0003\n   15 MC 0003\n   16 MC bd55\n   19 MW bd55 c5\ne0f9 ae1f 4aef c9d5 0000 0000 0000 0000 c0db bdd4 0000 0004\n00 02 0 0 0 0 19\nbd55 c5 -1\n\nfd39    ADD IY,SP\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 39\n    8 MC 0002\n    9 MC 0002\n   10 MC 0002\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n2631 726f 9c7f cd46 0000 0000 0000 0000 dc45 312c dc57 0002\n00 02 0 0 0 0 15\n\nfd44    LD B,IYh*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 44\n0e58 6892 3580 9be4 0000 0000 0000 0000 1b79 685e 0000 0002\n00 02 0 0 0 0 8\n\nfd45    LD B,IYl*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 45\n6555 7788 5ae8 c948 0000 0000 0000 0000 d7b8 a177 0000 0002\n00 02 0 0 0 0 8\n\nfd46    LD B,(IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 46\n    8 MC 0002\n   11 MR 0002 4d\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC 3b49\n   19 MR 3b49 c9\n87f3 c9d5 5eea 830b 0000 0000 0000 0000 dcee 3afc 0000 0003\n00 02 0 0 0 0 19\n\nfd4c    LD C,IYh*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 4c\n7e6b bd01 24b6 ff94 0000 0000 0000 0000 862d 01d0 0000 0002\n00 02 0 0 0 0 8\n\nfd4d    LD C,IYl*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 4d\n50cf e3c9 998e dba2 0000 0000 0000 0000 c4f5 c7c9 0000 0002\n00 02 0 0 0 0 8\n\nfd4e    LD C,(IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 4e\n    8 MC 0002\n   11 MR 0002 67\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC bc01\n   19 MR bc01 9d\n2c0f 699d 748a 9290 0000 0000 0000 0000 904f bb9a 0000 0003\n00 02 0 0 0 0 19\n\nfd54    LD D,IYh*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 54\nd7f9 f65b d401 d4c4 0000 0000 0000 0000 4b8e d437 0000 0002\n00 02 0 0 0 0 8\n\nfd55    LD D,IYl*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 55\nab98 fdab a94a 010e 0000 0000 0000 0000 126b 13a9 0000 0002\n00 02 0 0 0 0 8\n\nfd56    LD D,(IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 56\n    8 MC 0002\n   11 MR 0002 ce\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC fd70\n   19 MR fd70 78\nd3e8 df10 7842 b641 0000 0000 0000 0000 a5a0 fda2 0000 0003\n00 02 0 0 0 0 19\n\nfd5c    LD E,IYh*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 5c\n11d5 c489 e2d8 434e 0000 0000 0000 0000 3244 d8bb 0000 0002\n00 02 0 0 0 0 8\n\nfd5d    LD E,IYl*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 5d\ne945 dbae 324e 4f7e 0000 0000 0000 0000 fa56 074e 0000 0002\n00 02 0 0 0 0 8\n\nfd5e    LD E,(IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 5e\n    8 MC 0002\n   11 MR 0002 c6\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC 8a70\n   19 MR 8a70 8c\n6f3b e9dc 7a8c 14f3 0000 0000 0000 0000 ec76 8aaa 0000 0003\n00 02 0 0 0 0 19\n\nfd60    LD IYh,B*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 60\n8579 005d d9ee faee 0000 0000 0000 0000 382d 0095 0000 0002\n00 02 0 0 0 0 8\n\nfd61    LD IYh,C*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 61\n5682 dbc3 b495 9799 0000 0000 0000 0000 85b2 c31e 0000 0002\n00 02 0 0 0 0 8\n\nfd62    LD IYh,D*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 62\n906b f52e f3d8 1e8c 0000 0000 0000 0000 ddba f302 0000 0002\n00 02 0 0 0 0 8\n\nfd63    LD IYh,E*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 63\n9d59 beb9 d826 0eaa 0000 0000 0000 0000 4290 26b9 0000 0002\n00 02 0 0 0 0 8\n\nfd64    LD IYh,IYh*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 64\n7b0e e394 8a25 cddf 0000 0000 0000 0000 9784 2116 0000 0002\n00 02 0 0 0 0 8\n\nfd65    LD IYh,IYl*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 65\nb827 eb4f f666 c52a 0000 0000 0000 0000 6206 1f1f 0000 0002\n00 02 0 0 0 0 8\n\nfd66    LD H,(IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 66\n    8 MC 0002\n   11 MR 0002 80\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC 5aa4\n   19 MR 5aa4 77\n9129 e4ee e3a3 77ca 0000 0000 0000 0000 4d93 5b24 0000 0003\n00 02 0 0 0 0 19\n\nfd67    LD IYh,A*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 67\ndb7a b40b 7b58 49fd 0000 0000 0000 0000 266f db7b 0000 0002\n00 02 0 0 0 0 8\n\nfd68    LD IYl,B*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 68\n4d1d 4fd9 783e 0745 0000 0000 0000 0000 0c3d 824f 0000 0002\n00 02 0 0 0 0 8\n\nfd69    LD IYl,C*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 69\n1589 5ceb b5db 922a 0000 0000 0000 0000 3c3a dceb 0000 0002\n00 02 0 0 0 0 8\n\nfd6a    LD IYl,D*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 6a\n607a e035 5bb9 dac0 0000 0000 0000 0000 fc04 b55b 0000 0002\n00 02 0 0 0 0 8\n\nfd6b    LD IYl,E*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 6b\ndb2a e244 1182 096f 0000 0000 0000 0000 198e 9182 0000 0002\n00 02 0 0 0 0 8\n\nfd6c    LD IYl,IYh*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 6c\na0be 34ef 8fcd 40a7 0000 0000 0000 0000 4481 c2c2 0000 0002\n00 02 0 0 0 0 8\n\nfd6d    LD IYl,IYl*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 6d\nfdfc 727a b839 50a6 0000 0000 0000 0000 e782 02e5 0000 0002\n00 02 0 0 0 0 8\n\nfd6e    LD L,(IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 6e\n    8 MC 0002\n   11 MR 0002 78\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC b11b\n   19 MR b11b f8\ncfd4 6ef1 c07d ebf8 0000 0000 0000 0000 b0f9 b0a3 0000 0003\n00 02 0 0 0 0 19\n\nfd6f    LD IYl,A*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 6f\n8e1d a138 f20a 298e 0000 0000 0000 0000 b600 0c8e 0000 0002\n00 02 0 0 0 0 8\n\nfd70    LD (IY+d),B\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 70\n    8 MC 0002\n   11 MR 0002 53\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC 23f4\n   19 MW 23f4 33\n2677 33c5 c0dc 262f 0000 0000 0000 0000 d3dc 23a1 0000 0003\n00 02 0 0 0 0 19\n23f4 33 -1\n\nfd71    LD (IY+d),C\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 71\n    8 MC 0002\n   11 MR 0002 b4\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC bf5f\n   19 MW bf5f ae\n892e 04ae d67f 81ec 0000 0000 0000 0000 7757 bfab 0000 0003\n00 02 0 0 0 0 19\nbf5f ae -1\n\nfd72    LD (IY+d),D\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 72\n    8 MC 0002\n   11 MR 0002 e3\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC 7c63\n   19 MW 7c63 dd\nd2dc c23c dd54 6559 0000 0000 0000 0000 b32b 7c80 0000 0003\n00 02 0 0 0 0 19\n7c63 dd -1\n\nfd73    LD (IY+d),E\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 73\n    8 MC 0002\n   11 MR 0002 17\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC 8779\n   19 MW 8779 09\n49ef bff2 8409 02dd 0000 0000 0000 0000 af95 8762 0000 0003\n00 02 0 0 0 0 19\n8779 09 -1\n\nfd74    LD (IY+d),H\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 74\n    8 MC 0002\n   11 MR 0002 f6\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC 92d1\n   19 MW 92d1 1f\n9479 9817 fa2e 1fe0 0000 0000 0000 0000 a395 92db 0000 0003\n00 02 0 0 0 0 19\n92d1 1f -1\n\nfd75    LD (IY+d),L\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 75\n    8 MC 0002\n   11 MR 0002 ab\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC 16cf\n   19 MW 16cf 7b\nc8d6 6aa4 180e e37b 0000 0000 0000 0000 02cf 1724 0000 0003\n00 02 0 0 0 0 19\n16cf 7b -1\n\nfd77    LD (IY+d),A\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 77\n    8 MC 0002\n   11 MR 0002 f7\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC 6b44\n   19 MW 6b44 6f\n6f9e 7475 78ad 2b8c 0000 0000 0000 0000 c6b7 6b4d 0000 0003\n00 02 0 0 0 0 19\n6b44 6f -1\n\nfd7c    LD A,IYh*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 7c\nc628 93fc a3d4 dc9e 0000 0000 0000 0000 21ac c617 0000 0002\n00 02 0 0 0 0 8\n\nfd7d    LD A,IYl*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 7d\nb9e5 3cbe 02c3 26c2 0000 0000 0000 0000 ca81 92b9 0000 0002\n00 02 0 0 0 0 8\n\nfd7e    LD A,(IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 7e\n    8 MC 0002\n   11 MR 0002 e4\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC d443\n   19 MR d443 aa\naa96 daba 147b f362 0000 0000 0000 0000 7110 d45f 0000 0003\n00 02 0 0 0 0 19\n\nfd84    ADD A,IYh*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 84\n7f2d 7cae c4da 7aee 0000 0000 0000 0000 43ee c08e 0000 0002\n00 02 0 0 0 0 8\n\nfd85    ADD A,IYl*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 85\neba8 1dea 324f 84e7 0000 0000 0000 0000 e7a8 f799 0000 0002\n00 02 0 0 0 0 8\n\nfd86    ADD A,(IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 86\n    8 MC 0002\n   11 MR 0002 ce\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC 8b01\n   19 MR 8b01 e1\ndd89 b882 43f9 3e15 0000 0000 0000 0000 9781 8b33 0000 0003\n00 02 0 0 0 0 19\n\nfd8c    ADC A,IYh*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 8c\n3839 42b1 5e8a 081c 0000 0000 0000 0000 cb58 3b4e 0000 0002\n00 02 0 0 0 0 8\n\nfd8d    ADC A,IYl*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 8d\n8f89 7750 8ad6 295c 0000 0000 0000 0000 695c 99fb 0000 0002\n00 02 0 0 0 0 8\n\nfd8e    ADC A,(IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 8e\n    8 MC 0002\n   11 MR 0002 78\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC 1b1a\n   19 MR 1b1a c0\n0101 398f f6dc 06f3 0000 0000 0000 0000 f34a 1aa2 0000 0003\n00 02 0 0 0 0 19\n\nfd94    SUB IYh*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 94\n2f3b d255 b9d6 20bb 0000 0000 0000 0000 1e6a d5ef 0000 0002\n00 02 0 0 0 0 8\n\nfd95    SUB IYl*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 95\nf4a3 b455 2388 ec1e 0000 0000 0000 0000 7637 cb97 0000 0002\n00 02 0 0 0 0 8\n\nfd96    SUB (IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 96\n    8 MC 0002\n   11 MR 0002 55\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC c0e0\n   19 MR c0e0 7b\n2536 22ac 0413 4b13 0000 0000 0000 0000 b44e c08b 0000 0003\n00 02 0 0 0 0 19\n\nfd9c    SBC A,IYh*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 9c\nf3a3 3ecf ced3 66ec 0000 0000 0000 0000 4bff b133 0000 0002\n00 02 0 0 0 0 8\n\nfd9d    SBC A,IYl*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 9d\nfdbb 8bd0 131b 3094 0000 0000 0000 0000 afc3 7409 0000 0002\n00 02 0 0 0 0 8\n\nfd9e    SBC A,(IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 9e\n    8 MC 0002\n   11 MR 0002 f9\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC f665\n   19 MR f665 f3\nc583 981f bb8e d6d5 0000 0000 0000 0000 5c3b f66c 0000 0003\n00 02 0 0 0 0 19\n\nfda4    AND IYh*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 a4\n0054 79c0 2c7c 3e06 0000 0000 0000 0000 7399 037a 0000 0002\n00 02 0 0 0 0 8\n\nfda5    AND IYl*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 a5\n0054 654d 9653 2b33 0000 0000 0000 0000 61a4 8f88 0000 0002\n00 02 0 0 0 0 8\n\nfda6    AND (IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 a6\n    8 MC 0002\n   11 MR 0002 53\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC 65ee\n   19 MR 65ee 95\n9594 40bb 3742 6ff1 0000 0000 0000 0000 ad28 659b 0000 0003\n00 02 0 0 0 0 19\n\nfdac    XOR IYh*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 ac\n2724 72e3 dd4d 1b62 0000 0000 0000 0000 4753 5d63 0000 0002\n00 02 0 0 0 0 8\n\nfdad    XOR IYl*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 ad\neca8 2573 19cc 78fb 0000 0000 0000 0000 5248 8391 0000 0002\n00 02 0 0 0 0 8\n\nfdae    XOR (IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 ae\n    8 MC 0002\n   11 MR 0002 09\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC 8201\n   19 MR 8201 cb\n6b28 bc27 257b 5489 0000 0000 0000 0000 fa59 81f8 0000 0003\n00 02 0 0 0 0 19\n\nfdb4    OR IYh*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 b4\ncf8c 3461 f173 8ad3 0000 0000 0000 0000 c1a2 8265 0000 0002\n00 02 0 0 0 0 8\n\nfdb5    OR IYl*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 b5\n3720 e6ea f919 327c 0000 0000 0000 0000 4299 9733 0000 0002\n00 02 0 0 0 0 8\n\nfdb6    OR (IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 b6\n    8 MC 0002\n   11 MR 0002 4b\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC dfb8\n   19 MR dfb8 64\nffac 3509 d6ca b16a 0000 0000 0000 0000 a099 df6d 0000 0003\n00 02 0 0 0 0 19\n\nfdbc    CP IYh*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 bc\nb49a 9302 e35d 31bc 0000 0000 0000 0000 5c12 1c92 0000 0002\n00 02 0 0 0 0 8\n\nfdbd    CP IYl*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 bd\n391a 7b82 dfeb 03ee 0000 0000 0000 0000 be7b b30f 0000 0002\n00 02 0 0 0 0 8\n\nfdbe    CP (IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 be\n    8 MC 0002\n   11 MR 0002 6b\n   11 MC 0002\n   12 MC 0002\n   13 MC 0002\n   14 MC 0002\n   15 MC 0002\n   16 MC a9d6\n   19 MR a9d6 c0\n0903 0b31 f4ad 9d4c 0000 0000 0000 0000 b95a a96b 0000 0003\n00 02 0 0 0 0 19\n\nfdcb00  RLC (IY+d),B*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 0b\n   11 MC 0003\n   14 MR 0003 00\n   14 MC 0003\n   15 MC 0003\n   16 MC 2781\n   19 MR 2781 50\n   19 MC 2781\n   20 MC 2781\n   23 MW 2781 a0\n85a4 a0d0 a135 20c5 0000 0000 0000 0000 b8de 2776 0000 0004\n00 02 0 0 0 0 23\n2781 a0 -1\n\nfdcb01  RLC (IY+d),C*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 c8\n   11 MC 0003\n   14 MR 0003 01\n   14 MC 0003\n   15 MC 0003\n   16 MC 5bfd\n   19 MR 5bfd cb\n   19 MC 5bfd\n   20 MC 5bfd\n   23 MW 5bfd 97\n5781 2b97 3576 280a 0000 0000 0000 0000 ae22 5c35 0000 0004\n00 02 0 0 0 0 23\n5bfd 97 -1\n\nfdcb02  RLC (IY+d),D*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 14\n   11 MC 0003\n   14 MR 0003 02\n   14 MC 0003\n   15 MC 0003\n   16 MC 3e06\n   19 MR 3e06 58\n   19 MC 3e06\n   20 MC 3e06\n   23 MW 3e06 b0\ndca0 2b37 b0c8 5dd9 0000 0000 0000 0000 b2d2 3df2 0000 0004\n00 02 0 0 0 0 23\n3e06 b0 -1\n\nfdcb03  RLC (IY+d),E*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 3a\n   11 MC 0003\n   14 MR 0003 03\n   14 MC 0003\n   15 MC 0003\n   16 MC 5821\n   19 MR 5821 1a\n   19 MC 5821\n   20 MC 5821\n   23 MW 5821 34\n5720 c179 b234 7058 0000 0000 0000 0000 3f2e 57e7 0000 0004\n00 02 0 0 0 0 23\n5821 34 -1\n\nfdcb04  RLC (IY+d),H*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 67\n   11 MC 0003\n   14 MR 0003 04\n   14 MC 0003\n   15 MC 0003\n   16 MC 50d8\n   19 MR 50d8 92\n   19 MC 50d8\n   20 MC 50d8\n   23 MW 50d8 25\ned21 3f03 3327 255a 0000 0000 0000 0000 cbf2 5071 0000 0004\n00 02 0 0 0 0 23\n50d8 25 -1\n\nfdcb05  RLC (IY+d),L*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 1e\n   11 MC 0003\n   14 MR 0003 05\n   14 MC 0003\n   15 MC 0003\n   16 MC b279\n   19 MR b279 66\n   19 MC b279\n   20 MC b279\n   23 MW b279 cc\n7a8c 0858 db6c dbcc 0000 0000 0000 0000 157a b25b 0000 0004\n00 02 0 0 0 0 23\nb279 cc -1\n\nfdcb06  RLC (IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 72\n   11 MC 0003\n   14 MR 0003 06\n   14 MC 0003\n   15 MC 0003\n   16 MC ff99\n   19 MR ff99 f1\n   19 MC ff99\n   20 MC ff99\n   23 MW ff99 e3\nf2a1 89a2 e78f ef74 0000 0000 0000 0000 140d ff27 0000 0004\n00 02 0 0 0 0 23\nff99 e3 -1\n\nfdcb07  RLC (IY+d),A*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 24\n   11 MC 0003\n   14 MR 0003 07\n   14 MC 0003\n   15 MC 0003\n   16 MC 080f\n   19 MR 080f ae\n   19 MC 080f\n   20 MC 080f\n   23 MW 080f 5d\n5d09 f3a7 3a6e 8f0a 0000 0000 0000 0000 8423 07eb 0000 0004\n00 02 0 0 0 0 23\n080f 5d -1\n\nfdcb08  RRC (IY+d),B*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 25\n   11 MC 0003\n   14 MR 0003 08\n   14 MC 0003\n   15 MC 0003\n   16 MC 615c\n   19 MR 615c 83\n   19 MC 615c\n   20 MC 615c\n   23 MW 615c c1\na681 c1ec c958 7bda 0000 0000 0000 0000 194d 6137 0000 0004\n00 02 0 0 0 0 23\n615c c1 -1\n\nfdcb09  RRC (IY+d),C*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 a0\n   11 MC 0003\n   14 MR 0003 09\n   14 MC 0003\n   15 MC 0003\n   16 MC 197a\n   19 MR 197a 27\n   19 MC 197a\n   20 MC 197a\n   23 MW 197a 93\n5485 fa93 84e8 4fa5 0000 0000 0000 0000 1ad3 19da 0000 0004\n00 02 0 0 0 0 23\n197a 93 -1\n\nfdcb0a  RRC (IY+d),D*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 e1\n   11 MC 0003\n   14 MR 0003 0a\n   14 MC 0003\n   15 MC 0003\n   16 MC eed7\n   19 MR eed7 19\n   19 MC eed7\n   20 MC eed7\n   23 MW eed7 8c\nb389 a2bb 8cd6 9617 0000 0000 0000 0000 f946 eef6 0000 0004\n00 02 0 0 0 0 23\need7 8c -1\n\nfdcb0b  RRC (IY+d),E*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 0c\n   11 MC 0003\n   14 MR 0003 0b\n   14 MC 0003\n   15 MC 0003\n   16 MC c69b\n   19 MR c69b f2\n   19 MC c69b\n   20 MC c69b\n   23 MW c69b 79\nae28 8c4e e179 1c54 0000 0000 0000 0000 e108 c68f 0000 0004\n00 02 0 0 0 0 23\nc69b 79 -1\n\nfdcb0c  RRC (IY+d),H*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 d7\n   11 MC 0003\n   14 MR 0003 0c\n   14 MC 0003\n   15 MC 0003\n   16 MC 8c74\n   19 MR 8c74 ae\n   19 MC 8c74\n   20 MC 8c74\n   23 MW 8c74 57\n8700 6b16 4c3b 570a 0000 0000 0000 0000 175a 8c9d 0000 0004\n00 02 0 0 0 0 23\n8c74 57 -1\n\nfdcb0d  RRC (IY+d),L*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 11\n   11 MC 0003\n   14 MR 0003 0d\n   14 MC 0003\n   15 MC 0003\n   16 MC fe3e\n   19 MR fe3e 1b\n   19 MC fe3e\n   20 MC fe3e\n   23 MW fe3e 8d\n128d e0cb 3ab1 248d 0000 0000 0000 0000 1de4 fe2d 0000 0004\n00 02 0 0 0 0 23\nfe3e 8d -1\n\nfdcb0e  RRC (IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 0c\n   11 MC 0003\n   14 MR 0003 0e\n   14 MC 0003\n   15 MC 0003\n   16 MC f22f\n   19 MR f22f f7\n   19 MC f22f\n   20 MC f22f\n   23 MW f22f fb\n8da9 8f91 fc5a 5e2c 0000 0000 0000 0000 b2f2 f223 0000 0004\n00 02 0 0 0 0 23\nf22f fb -1\n\nfdcb0f  RRC (IY+d),A*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 15\n   11 MC 0003\n   14 MR 0003 0f\n   14 MC 0003\n   15 MC 0003\n   16 MC ce4d\n   19 MR ce4d 44\n   19 MC ce4d\n   20 MC ce4d\n   23 MW ce4d 22\n2224 2ac9 ec6b 6511 0000 0000 0000 0000 c93a ce38 0000 0004\n00 02 0 0 0 0 23\nce4d 22 -1\n\nfdcb10  RL (IY+d),B*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 7a\n   11 MC 0003\n   14 MR 0003 10\n   14 MC 0003\n   15 MC 0003\n   16 MC 431c\n   19 MR 431c 1c\n   19 MC 431c\n   20 MC 431c\n   23 MW 431c 39\n252c 3952 590d ac66 0000 0000 0000 0000 144f 42a2 0000 0004\n00 02 0 0 0 0 23\n431c 39 -1\n\nfdcb11  RL (IY+d),C*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 7b\n   11 MC 0003\n   14 MR 0003 11\n   14 MC 0003\n   15 MC 0003\n   16 MC 9d0b\n   19 MR 9d0b 5e\n   19 MC 9d0b\n   20 MC 9d0b\n   23 MW 9d0b bc\nbca8 61bc f5f8 af24 0000 0000 0000 0000 4019 9c90 0000 0004\n00 02 0 0 0 0 23\n9d0b bc -1\n\nfdcb12  RL (IY+d),D*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 61\n   11 MC 0003\n   14 MR 0003 12\n   14 MC 0003\n   15 MC 0003\n   16 MC 8598\n   19 MR 8598 a7\n   19 MC 8598\n   20 MC 8598\n   23 MW 8598 4f\n4e09 3a25 4f17 bcc7 0000 0000 0000 0000 0d7e 8537 0000 0004\n00 02 0 0 0 0 23\n8598 4f -1\n\nfdcb13  RL (IY+d),E*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 b3\n   11 MC 0003\n   14 MR 0003 13\n   14 MC 0003\n   15 MC 0003\n   16 MC e74b\n   19 MR e74b b3\n   19 MC e74b\n   20 MC e74b\n   23 MW e74b 66\nb225 b79b 8466 ff7d 0000 0000 0000 0000 414c e798 0000 0004\n00 02 0 0 0 0 23\ne74b 66 -1\n\nfdcb14  RL (IY+d),H*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 c4\n   11 MC 0003\n   14 MR 0003 14\n   14 MC 0003\n   15 MC 0003\n   16 MC d900\n   19 MR d900 06\n   19 MC d900\n   20 MC d900\n   23 MW d900 0d\nab08 451a fc65 0da1 0000 0000 0000 0000 0f4d d93c 0000 0004\n00 02 0 0 0 0 23\nd900 0d -1\n\nfdcb15  RL (IY+d),L*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 17\n   11 MC 0003\n   14 MR 0003 15\n   14 MC 0003\n   15 MC 0003\n   16 MC 2d92\n   19 MR 2d92 12\n   19 MC 2d92\n   20 MC 2d92\n   23 MW 2d92 24\n2824 9532 8631 7524 0000 0000 0000 0000 e327 2d7b 0000 0004\n00 02 0 0 0 0 23\n2d92 24 -1\n\nfdcb16  RL (IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 23\n   11 MC 0003\n   14 MR 0003 16\n   14 MC 0003\n   15 MC 0003\n   16 MC f0d7\n   19 MR f0d7 89\n   19 MC f0d7\n   20 MC f0d7\n   23 MW f0d7 12\n0c05 dcd7 adcc 196d 0000 0000 0000 0000 87e2 f0b4 0000 0004\n00 02 0 0 0 0 23\nf0d7 12 -1\n\nfdcb17  RL (IY+d),A*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 8a\n   11 MC 0003\n   14 MR 0003 17\n   14 MC 0003\n   15 MC 0003\n   16 MC 1f9d\n   19 MR 1f9d b8\n   19 MC 1f9d\n   20 MC 1f9d\n   23 MW 1f9d 71\n7125 d016 066e 6638 0000 0000 0000 0000 5e92 2013 0000 0004\n00 02 0 0 0 0 23\n1f9d 71 -1\n\nfdcb18  RR (IY+d),B*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 c0\n   11 MC 0003\n   14 MR 0003 18\n   14 MC 0003\n   15 MC 0003\n   16 MC 31d6\n   19 MR 31d6 fa\n   19 MC 31d6\n   20 MC 31d6\n   23 MW 31d6 fd\n23a8 fd17 16e0 6894 0000 0000 0000 0000 b908 3216 0000 0004\n00 02 0 0 0 0 23\n31d6 fd -1\n\nfdcb19  RR (IY+d),C*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 a2\n   11 MC 0003\n   14 MR 0003 19\n   14 MC 0003\n   15 MC 0003\n   16 MC 4cd0\n   19 MR 4cd0 4b\n   19 MC 4cd0\n   20 MC 4cd0\n   23 MW 4cd0 a5\n11a5 c2a5 a9f3 2014 0000 0000 0000 0000 6db0 4d2e 0000 0004\n00 02 0 0 0 0 23\n4cd0 a5 -1\n\nfdcb1a  RR (IY+d),D*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 78\n   11 MC 0003\n   14 MR 0003 1a\n   14 MC 0003\n   15 MC 0003\n   16 MC 414b\n   19 MR 414b 44\n   19 MC 414b\n   20 MC 414b\n   23 MW 414b 22\nbc24 6168 2241 b630 0000 0000 0000 0000 0207 40d3 0000 0004\n00 02 0 0 0 0 23\n414b 22 -1\n\nfdcb1b  RR (IY+d),E*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 16\n   11 MC 0003\n   14 MR 0003 1b\n   14 MC 0003\n   15 MC 0003\n   16 MC 71c6\n   19 MR 71c6 b8\n   19 MC 71c6\n   20 MC 71c6\n   23 MW 71c6 5c\n7a0c 1286 fe5c c42d 0000 0000 0000 0000 e290 71b0 0000 0004\n00 02 0 0 0 0 23\n71c6 5c -1\n\nfdcb1c  RR (IY+d),H*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 86\n   11 MC 0003\n   14 MR 0003 1c\n   14 MC 0003\n   15 MC 0003\n   16 MC dee8\n   19 MR dee8 8f\n   19 MC dee8\n   20 MC dee8\n   23 MW dee8 c7\n9381 097b 6928 c7a3 0000 0000 0000 0000 ff2d df62 0000 0004\n00 02 0 0 0 0 23\ndee8 c7 -1\n\nfdcb1d  RR (IY+d),L*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 27\n   11 MC 0003\n   14 MR 0003 1d\n   14 MC 0003\n   15 MC 0003\n   16 MC d68e\n   19 MR d68e b7\n   19 MC d68e\n   20 MC d68e\n   23 MW d68e db\n978d 2b30 2645 04db 0000 0000 0000 0000 186a d667 0000 0004\n00 02 0 0 0 0 23\nd68e db -1\n\nfdcb1e  RR (IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 3a\n   11 MC 0003\n   14 MR 0003 1e\n   14 MC 0003\n   15 MC 0003\n   16 MC da72\n   19 MR da72 25\n   19 MC da72\n   20 MC da72\n   23 MW da72 92\n2f81 2470 b521 6ca3 0000 0000 0000 0000 1066 da38 0000 0004\n00 02 0 0 0 0 23\nda72 92 -1\n\nfdcb1f  RR (IY+d),A*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 7b\n   11 MC 0003\n   14 MR 0003 1f\n   14 MC 0003\n   15 MC 0003\n   16 MC 2110\n   19 MR 2110 04\n   19 MC 2110\n   20 MC 2110\n   23 MW 2110 82\n8284 49a3 da18 3afd 0000 0000 0000 0000 a4f1 2095 0000 0004\n00 02 0 0 0 0 23\n2110 82 -1\n\nfdcb20  SLA (IY+d),B*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 7a\n   11 MC 0003\n   14 MR 0003 20\n   14 MC 0003\n   15 MC 0003\n   16 MC da9f\n   19 MR da9f 89\n   19 MC da9f\n   20 MC da9f\n   23 MW da9f 12\n3d05 128f 206f 8894 0000 0000 0000 0000 ddab da25 0000 0004\n00 02 0 0 0 0 23\nda9f 12 -1\n\nfdcb21  SLA (IY+d),C*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 7b\n   11 MC 0003\n   14 MR 0003 21\n   14 MC 0003\n   15 MC 0003\n   16 MC deb1\n   19 MR deb1 23\n   19 MC deb1\n   20 MC deb1\n   23 MW deb1 46\n1600 6046 641a 6598 0000 0000 0000 0000 473b de36 0000 0004\n00 02 0 0 0 0 23\ndeb1 46 -1\n\nfdcb22  SLA (IY+d),D*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 9a\n   11 MC 0003\n   14 MR 0003 22\n   14 MC 0003\n   15 MC 0003\n   16 MC 88c0\n   19 MR 88c0 d4\n   19 MC 88c0\n   20 MC 88c0\n   23 MW 88c0 a8\nada9 efb2 a803 e732 0000 0000 0000 0000 c11d 8926 0000 0004\n00 02 0 0 0 0 23\n88c0 a8 -1\n\nfdcb23  SLA (IY+d),E*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 f5\n   11 MC 0003\n   14 MR 0003 23\n   14 MC 0003\n   15 MC 0003\n   16 MC 524a\n   19 MR 524a 65\n   19 MC 524a\n   20 MC 524a\n   23 MW 524a ca\n218c d678 a7ca 25d7 0000 0000 0000 0000 4ca8 5255 0000 0004\n00 02 0 0 0 0 23\n524a ca -1\n\nfdcb24  SLA (IY+d),H*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 b4\n   11 MC 0003\n   14 MR 0003 24\n   14 MC 0003\n   15 MC 0003\n   16 MC afb2\n   19 MR afb2 7e\n   19 MC afb2\n   20 MC afb2\n   23 MW afb2 fc\n1cac da3e cc7c fc19 0000 0000 0000 0000 572c affe 0000 0004\n00 02 0 0 0 0 23\nafb2 fc -1\n\nfdcb25  SLA (IY+d),L*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 a6\n   11 MC 0003\n   14 MR 0003 25\n   14 MC 0003\n   15 MC 0003\n   16 MC 238f\n   19 MR 238f 26\n   19 MC 238f\n   20 MC 238f\n   23 MW 238f 4c\n9508 097c a341 894c 0000 0000 0000 0000 435d 23e9 0000 0004\n00 02 0 0 0 0 23\n238f 4c -1\n\nfdcb26  SLA (IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 bd\n   11 MC 0003\n   14 MR 0003 26\n   14 MC 0003\n   15 MC 0003\n   16 MC d4a1\n   19 MR d4a1 bf\n   19 MC d4a1\n   20 MC d4a1\n   23 MW d4a1 7e\n582d 0e19 d277 bf7f 0000 0000 0000 0000 6504 d4e4 0000 0004\n00 02 0 0 0 0 23\nd4a1 7e -1\n\nfdcb27  SLA (IY+d),A*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 59\n   11 MC 0003\n   14 MR 0003 27\n   14 MC 0003\n   15 MC 0003\n   16 MC 8d9b\n   19 MR 8d9b a7\n   19 MC 8d9b\n   20 MC 8d9b\n   23 MW 8d9b 4e\n4e0d 8c06 2c4c d7c8 0000 0000 0000 0000 9239 8d42 0000 0004\n00 02 0 0 0 0 23\n8d9b 4e -1\n\nfdcb28  SRA (IY+d),B*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 83\n   11 MC 0003\n   14 MR 0003 28\n   14 MC 0003\n   15 MC 0003\n   16 MC aac6\n   19 MR aac6 5d\n   19 MC aac6\n   20 MC aac6\n   23 MW aac6 2e\n412d 2e9b 7745 76f5 0000 0000 0000 0000 a1bb ab43 0000 0004\n00 02 0 0 0 0 23\naac6 2e -1\n\nfdcb29  SRA (IY+d),C*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 7d\n   11 MC 0003\n   14 MR 0003 29\n   14 MC 0003\n   15 MC 0003\n   16 MC 03c0\n   19 MR 03c0 84\n   19 MC 03c0\n   20 MC 03c0\n   23 MW 03c0 c2\n0b80 afc2 fea6 9478 0000 0000 0000 0000 32bb 0343 0000 0004\n00 02 0 0 0 0 23\n03c0 c2 -1\n\nfdcb2a  SRA (IY+d),D*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 f9\n   11 MC 0003\n   14 MR 0003 2a\n   14 MC 0003\n   15 MC 0003\n   16 MC abe0\n   19 MR abe0 dd\n   19 MC abe0\n   20 MC abe0\n   23 MW abe0 ee\nf2ad 8c31 ee32 7feb 0000 0000 0000 0000 7db7 abe7 0000 0004\n00 02 0 0 0 0 23\nabe0 ee -1\n\nfdcb2b  SRA (IY+d),E*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 4b\n   11 MC 0003\n   14 MR 0003 2b\n   14 MC 0003\n   15 MC 0003\n   16 MC 4adf\n   19 MR 4adf 49\n   19 MC 4adf\n   20 MC 4adf\n   23 MW 4adf 24\n2425 6945 dc24 d643 0000 0000 0000 0000 5be1 4a94 0000 0004\n00 02 0 0 0 0 23\n4adf 24 -1\n\nfdcb2c  SRA (IY+d),H*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 e6\n   11 MC 0003\n   14 MR 0003 2c\n   14 MC 0003\n   15 MC 0003\n   16 MC ccb7\n   19 MR ccb7 3c\n   19 MC ccb7\n   20 MC ccb7\n   23 MW ccb7 1e\n110c b32b e530 1e5a 0000 0000 0000 0000 2416 ccd1 0000 0004\n00 02 0 0 0 0 23\nccb7 1e -1\n\nfdcb2d  SRA (IY+d),L*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 5f\n   11 MC 0003\n   14 MR 0003 2d\n   14 MC 0003\n   15 MC 0003\n   16 MC e545\n   19 MR e545 78\n   19 MC e545\n   20 MC e545\n   23 MW e545 3c\nd02c 344b 1bb0 3e3c 0000 0000 0000 0000 fe11 e4e6 0000 0004\n00 02 0 0 0 0 23\ne545 3c -1\n\nfdcb2e  SRA (IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 06\n   11 MC 0003\n   14 MR 0003 2e\n   14 MC 0003\n   15 MC 0003\n   16 MC 4303\n   19 MR 4303 ad\n   19 MC 4303\n   20 MC 4303\n   23 MW 4303 d6\nf481 b832 4b7f e2b7 0000 0000 0000 0000 9386 42fd 0000 0004\n00 02 0 0 0 0 23\n4303 d6 -1\n\nfdcb2f  SRA (IY+d),A*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 29\n   11 MC 0003\n   14 MR 0003 2f\n   14 MC 0003\n   15 MC 0003\n   16 MC 16e1\n   19 MR 16e1 18\n   19 MC 16e1\n   20 MC 16e1\n   23 MW 16e1 0c\n0c0c f2c2 9f2f c946 0000 0000 0000 0000 5fe0 16b8 0000 0004\n00 02 0 0 0 0 23\n16e1 0c -1\n\nfdcb30  SLL (IY+d),B*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 1b\n   11 MC 0003\n   14 MR 0003 30\n   14 MC 0003\n   15 MC 0003\n   16 MC d661\n   19 MR d661 a5\n   19 MC d661\n   20 MC d661\n   23 MW d661 4b\nac0d 4b32 f9ed cabc 0000 0000 0000 0000 fabd d646 0000 0004\n00 02 0 0 0 0 23\nd661 4b -1\n\nfdcb31  SLL (IY+d),C*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 f0\n   11 MC 0003\n   14 MR 0003 31\n   14 MC 0003\n   15 MC 0003\n   16 MC bfd0\n   19 MR bfd0 f1\n   19 MC bfd0\n   20 MC bfd0\n   23 MW bfd0 e3\n2ba1 51e3 83a7 7eee 0000 0000 0000 0000 7750 bfe0 0000 0004\n00 02 0 0 0 0 23\nbfd0 e3 -1\n\nfdcb32  SLL (IY+d),D*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 c5\n   11 MC 0003\n   14 MR 0003 32\n   14 MC 0003\n   15 MC 0003\n   16 MC 5aa3\n   19 MR 5aa3 59\n   19 MC 5aa3\n   20 MC 5aa3\n   23 MW 5aa3 b3\nb2a0 a4b1 b385 f66e 0000 0000 0000 0000 a9a1 5ade 0000 0004\n00 02 0 0 0 0 23\n5aa3 b3 -1\n\nfdcb33  SLL (IY+d),E*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 7f\n   11 MC 0003\n   14 MR 0003 33\n   14 MC 0003\n   15 MC 0003\n   16 MC 19e3\n   19 MR 19e3 da\n   19 MC 19e3\n   20 MC 19e3\n   23 MW 19e3 b5\n9ca1 2c90 d0b5 2be3 0000 0000 0000 0000 2691 1964 0000 0004\n00 02 0 0 0 0 23\n19e3 b5 -1\n\nfdcb34  SLL (IY+d),H*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 d2\n   11 MC 0003\n   14 MR 0003 34\n   14 MC 0003\n   15 MC 0003\n   16 MC 5668\n   19 MR 5668 d4\n   19 MC 5668\n   20 MC 5668\n   23 MW 5668 a9\n60ad fbcd 5348 a947 0000 0000 0000 0000 5338 5696 0000 0004\n00 02 0 0 0 0 23\n5668 a9 -1\n\nfdcb35  SLL (IY+d),L*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 71\n   11 MC 0003\n   14 MR 0003 35\n   14 MC 0003\n   15 MC 0003\n   16 MC 0169\n   19 MR 0169 0b\n   19 MC 0169\n   20 MC 0169\n   23 MW 0169 17\n9604 21c6 4cb6 b417 0000 0000 0000 0000 673a 00f8 0000 0004\n00 02 0 0 0 0 23\n0169 17 -1\n\nfdcb36  SLL (IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 da\n   11 MC 0003\n   14 MR 0003 36\n   14 MC 0003\n   15 MC 0003\n   16 MC 1ab8\n   19 MR 1ab8 3c\n   19 MC 1ab8\n   20 MC 1ab8\n   23 MW 1ab8 79\ndc28 0892 3cc7 1494 0000 0000 0000 0000 8598 1ade 0000 0004\n00 02 0 0 0 0 23\n1ab8 79 -1\n\nfdcb37  SLL (IY+d),A*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 cb\n   11 MC 0003\n   14 MR 0003 37\n   14 MC 0003\n   15 MC 0003\n   16 MC e7b7\n   19 MR e7b7 9f\n   19 MC e7b7\n   20 MC e7b7\n   23 MW e7b7 3f\n3f2d 4524 208f 076f 0000 0000 0000 0000 ad10 e7ec 0000 0004\n00 02 0 0 0 0 23\ne7b7 3f -1\n\nfdcb38  SRL (IY+d),B*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 8e\n   11 MC 0003\n   14 MR 0003 38\n   14 MC 0003\n   15 MC 0003\n   16 MC d024\n   19 MR d024 0d\n   19 MC d024\n   20 MC d024\n   23 MW d024 06\n4f05 0650 40c6 4fb7 0000 0000 0000 0000 f37e d096 0000 0004\n00 02 0 0 0 0 23\nd024 06 -1\n\nfdcb39  SRL (IY+d),C*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 7f\n   11 MC 0003\n   14 MR 0003 39\n   14 MC 0003\n   15 MC 0003\n   16 MC f4b2\n   19 MR f4b2 f5\n   19 MC f4b2\n   20 MC f4b2\n   23 MW f4b2 7a\nbc29 f57a 8dee e514 0000 0000 0000 0000 48bc f433 0000 0004\n00 02 0 0 0 0 23\nf4b2 7a -1\n\nfdcb3a  SRL (IY+d),D*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 1d\n   11 MC 0003\n   14 MR 0003 3a\n   14 MC 0003\n   15 MC 0003\n   16 MC cb20\n   19 MR cb20 a8\n   19 MC cb20\n   20 MC cb20\n   23 MW cb20 54\nd000 2ef5 5410 9ca5 0000 0000 0000 0000 b155 cb03 0000 0004\n00 02 0 0 0 0 23\ncb20 54 -1\n\nfdcb3b  SRL (IY+d),E*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 05\n   11 MC 0003\n   14 MR 0003 3b\n   14 MC 0003\n   15 MC 0003\n   16 MC d268\n   19 MR d268 b2\n   19 MC d268\n   20 MC d268\n   23 MW d268 59\n500c a85b cf59 de8c 0000 0000 0000 0000 9c5b d263 0000 0004\n00 02 0 0 0 0 23\nd268 59 -1\n\nfdcb3c  SRL (IY+d),H*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 ae\n   11 MC 0003\n   14 MR 0003 3c\n   14 MC 0003\n   15 MC 0003\n   16 MC a7bd\n   19 MR a7bd 96\n   19 MC a7bd\n   20 MC a7bd\n   23 MW a7bd 4b\n970c 4456 0b52 4bad 0000 0000 0000 0000 6d2a a80f 0000 0004\n00 02 0 0 0 0 23\na7bd 4b -1\n\nfdcb3d  SRL (IY+d),L*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 13\n   11 MC 0003\n   14 MR 0003 3d\n   14 MC 0003\n   15 MC 0003\n   16 MC e53d\n   19 MR e53d fb\n   19 MC e53d\n   20 MC e53d\n   23 MW e53d 7d\n7d2d 9303 e12b bf7d 0000 0000 0000 0000 4c0f e52a 0000 0004\n00 02 0 0 0 0 23\ne53d 7d -1\n\nfdcb3e  SRL (IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 2e\n   11 MC 0003\n   14 MR 0003 3e\n   14 MC 0003\n   15 MC 0003\n   16 MC b2ff\n   19 MR b2ff 50\n   19 MC b2ff\n   20 MC b2ff\n   23 MW b2ff 28\n0d2c 3e02 8f74 0f82 0000 0000 0000 0000 85df b2d1 0000 0004\n00 02 0 0 0 0 23\nb2ff 28 -1\n\nfdcb3f  SRL (IY+d),A*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 21\n   11 MC 0003\n   14 MR 0003 3f\n   14 MC 0003\n   15 MC 0003\n   16 MC c1cd\n   19 MR c1cd 78\n   19 MC c1cd\n   20 MC c1cd\n   23 MW c1cd 3c\n3c2c 12f6 426c 52d4 0000 0000 0000 0000 d9f7 c1ac 0000 0004\n00 02 0 0 0 0 23\nc1cd 3c -1\n\nfdcb40  BIT 0,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 3b\n   11 MC 0003\n   14 MR 0003 40\n   14 MC 0003\n   15 MC 0003\n   16 MC 41d0\n   19 MR 41d0 0d\n   19 MC 41d0\n5410 2c34 6784 b376 0000 0000 0000 0000 8ff9 4195 0000 0004\n00 02 0 0 0 0 20\n\nfdcb41  BIT 0,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 cc\n   11 MC 0003\n   14 MR 0003 41\n   14 MC 0003\n   15 MC 0003\n   16 MC 0397\n   19 MR 0397 e9\n   19 MC 0397\n8c11 5a58 b71c 6777 0000 0000 0000 0000 deca 03cb 0000 0004\n00 02 0 0 0 0 20\n\nfdcb42  BIT 0,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 01\n   11 MC 0003\n   14 MR 0003 42\n   14 MC 0003\n   15 MC 0003\n   16 MC 9f57\n   19 MR 9f57 a8\n   19 MC 9f57\n555d 9c29 2feb 97ff 0000 0000 0000 0000 7f17 9f56 0000 0004\n00 02 0 0 0 0 20\n\nfdcb43  BIT 0,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 08\n   11 MC 0003\n   14 MR 0003 43\n   14 MC 0003\n   15 MC 0003\n   16 MC 1fd9\n   19 MR 1fd9 aa\n   19 MC 1fd9\nb45c e58c e62e 2a32 0000 0000 0000 0000 7130 1fd1 0000 0004\n00 02 0 0 0 0 20\n\nfdcb44  BIT 0,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 03\n   11 MC 0003\n   14 MR 0003 44\n   14 MC 0003\n   15 MC 0003\n   16 MC f4f6\n   19 MR f4f6 89\n   19 MC f4f6\na930 68f4 9fa4 7f66 0000 0000 0000 0000 0209 f4f3 0000 0004\n00 02 0 0 0 0 20\n\nfdcb45  BIT 0,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 8d\n   11 MC 0003\n   14 MR 0003 45\n   14 MC 0003\n   15 MC 0003\n   16 MC 937a\n   19 MR 937a 8d\n   19 MC 937a\n7311 8dde 5e4f 84a7 0000 0000 0000 0000 4e24 93ed 0000 0004\n00 02 0 0 0 0 20\n\nfdcb46  BIT 0,(IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 8c\n   11 MC 0003\n   14 MR 0003 46\n   14 MC 0003\n   15 MC 0003\n   16 MC 633d\n   19 MR 633d fe\n   19 MC 633d\n0e74 b1f9 475f ebfc 0000 0000 0000 0000 7765 63b1 0000 0004\n00 02 0 0 0 0 20\n\nfdcb47  BIT 0,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 96\n   11 MC 0003\n   14 MR 0003 47\n   14 MC 0003\n   15 MC 0003\n   16 MC 6da4\n   19 MR 6da4 d6\n   19 MC 6da4\n9b7d 7f38 0753 d5e7 0000 0000 0000 0000 b9c3 6e0e 0000 0004\n00 02 0 0 0 0 20\n\nfdcb48  BIT 1,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 44\n   11 MC 0003\n   14 MR 0003 48\n   14 MC 0003\n   15 MC 0003\n   16 MC abed\n   19 MR abed b0\n   19 MC abed\n7d7c 50a9 2511 8f9f 0000 0000 0000 0000 b612 aba9 0000 0004\n00 02 0 0 0 0 20\n\nfdcb49  BIT 1,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 4e\n   11 MC 0003\n   14 MR 0003 49\n   14 MC 0003\n   15 MC 0003\n   16 MC 3e6f\n   19 MR 3e6f a9\n   19 MC 3e6f\n697c 3a39 b834 74b6 0000 0000 0000 0000 0eb7 3e21 0000 0004\n00 02 0 0 0 0 20\n\nfdcb4a  BIT 1,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 52\n   11 MC 0003\n   14 MR 0003 4a\n   14 MC 0003\n   15 MC 0003\n   16 MC e82d\n   19 MR e82d da\n   19 MC e82d\n3139 68e0 fe2f a2c4 0000 0000 0000 0000 ac96 e7db 0000 0004\n00 02 0 0 0 0 20\n\nfdcb4b  BIT 1,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 ea\n   11 MC 0003\n   14 MR 0003 4b\n   14 MC 0003\n   15 MC 0003\n   16 MC 8829\n   19 MR 8829 4e\n   19 MC 8829\n0919 2453 9186 a32a 0000 0000 0000 0000 71af 883f 0000 0004\n00 02 0 0 0 0 20\n\nfdcb4c  BIT 1,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 ee\n   11 MC 0003\n   14 MR 0003 4c\n   14 MC 0003\n   15 MC 0003\n   16 MC 7f10\n   19 MR 7f10 70\n   19 MC 7f10\n4a7c 1e5b be2e 3ee4 0000 0000 0000 0000 af79 7f22 0000 0004\n00 02 0 0 0 0 20\n\nfdcb4d  BIT 1,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 29\n   11 MC 0003\n   14 MR 0003 4d\n   14 MC 0003\n   15 MC 0003\n   16 MC a799\n   19 MR a799 78\n   19 MC a799\n9f75 6c8f 34f4 5a79 0000 0000 0000 0000 d3cc a770 0000 0004\n00 02 0 0 0 0 20\n\nfdcb4e  BIT 1,(IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 20\n   11 MC 0003\n   14 MR 0003 4e\n   14 MC 0003\n   15 MC 0003\n   16 MC e1e8\n   19 MR e1e8 aa\n   19 MC e1e8\n3031 5626 52bc 5503 0000 0000 0000 0000 303b e1c8 0000 0004\n00 02 0 0 0 0 20\n\nfdcb4f  BIT 1,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 9d\n   11 MC 0003\n   14 MR 0003 4f\n   14 MC 0003\n   15 MC 0003\n   16 MC 1c95\n   19 MR 1c95 18\n   19 MC 1c95\n605c e079 7152 671f 0000 0000 0000 0000 8c22 1cf8 0000 0004\n00 02 0 0 0 0 20\n\nfdcb50  BIT 2,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 6b\n   11 MC 0003\n   14 MR 0003 50\n   14 MC 0003\n   15 MC 0003\n   16 MC c7ca\n   19 MR c7ca fe\n   19 MC c7ca\n8c10 1409 6d69 e5b2 0000 0000 0000 0000 4a0c c75f 0000 0004\n00 02 0 0 0 0 20\n\nfdcb51  BIT 2,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 86\n   11 MC 0003\n   14 MR 0003 51\n   14 MC 0003\n   15 MC 0003\n   16 MC 341b\n   19 MR 341b 13\n   19 MC 341b\n8f75 40cb 9543 9b3a 0000 0000 0000 0000 1942 3495 0000 0004\n00 02 0 0 0 0 20\n\nfdcb52  BIT 2,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 e6\n   11 MC 0003\n   14 MR 0003 52\n   14 MC 0003\n   15 MC 0003\n   16 MC 8af3\n   19 MR 8af3 87\n   19 MC 8af3\n8919 3e41 7ab4 37f6 0000 0000 0000 0000 f82d 8b0d 0000 0004\n00 02 0 0 0 0 20\n\nfdcb53  BIT 2,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 d1\n   11 MC 0003\n   14 MR 0003 53\n   14 MC 0003\n   15 MC 0003\n   16 MC 7eb2\n   19 MR 7eb2 e4\n   19 MC 7eb2\nef38 e345 09a3 f0b2 0000 0000 0000 0000 c378 7ee1 0000 0004\n00 02 0 0 0 0 20\n\nfdcb54  BIT 2,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 08\n   11 MC 0003\n   14 MR 0003 54\n   14 MC 0003\n   15 MC 0003\n   16 MC 5b73\n   19 MR 5b73 07\n   19 MC 5b73\n7218 cb82 d966 2fc6 0000 0000 0000 0000 3c00 5b6b 0000 0004\n00 02 0 0 0 0 20\n\nfdcb55  BIT 2,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 54\n   11 MC 0003\n   14 MR 0003 55\n   14 MC 0003\n   15 MC 0003\n   16 MC b506\n   19 MR b506 46\n   19 MC b506\n8530 c23b 6aab 9b00 0000 0000 0000 0000 fe93 b4b2 0000 0004\n00 02 0 0 0 0 20\n\nfdcb56  BIT 2,(IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 6f\n   11 MC 0003\n   14 MR 0003 56\n   14 MC 0003\n   15 MC 0003\n   16 MC 69a1\n   19 MR 69a1 df\n   19 MC 69a1\nf539 f9f6 1e8c 9e08 0000 0000 0000 0000 716a 6932 0000 0004\n00 02 0 0 0 0 20\n\nfdcb57  BIT 2,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 3c\n   11 MC 0003\n   14 MR 0003 57\n   14 MC 0003\n   15 MC 0003\n   16 MC a3f7\n   19 MR a3f7 6c\n   19 MC a3f7\n3731 b7dc be1c 38ea 0000 0000 0000 0000 5e82 a3bb 0000 0004\n00 02 0 0 0 0 20\n\nfdcb58  BIT 3,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 4e\n   11 MC 0003\n   14 MR 0003 58\n   14 MC 0003\n   15 MC 0003\n   16 MC 1ee2\n   19 MR 1ee2 f6\n   19 MC 1ee2\n755c 7296 3ea5 1143 0000 0000 0000 0000 d7cc 1e94 0000 0004\n00 02 0 0 0 0 20\n\nfdcb59  BIT 3,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 2e\n   11 MC 0003\n   14 MR 0003 59\n   14 MC 0003\n   15 MC 0003\n   16 MC fb01\n   19 MR fb01 6f\n   19 MC fb01\n8038 bf2a 1809 ed31 0000 0000 0000 0000 fe2b fad3 0000 0004\n00 02 0 0 0 0 20\n\nfdcb5a  BIT 3,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 88\n   11 MC 0003\n   14 MR 0003 5a\n   14 MC 0003\n   15 MC 0003\n   16 MC 7b40\n   19 MR 7b40 6e\n   19 MC 7b40\ncc38 a108 65d4 6f66 0000 0000 0000 0000 0008 7bb8 0000 0004\n00 02 0 0 0 0 20\n\nfdcb5b  BIT 3,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 e7\n   11 MC 0003\n   14 MR 0003 5b\n   14 MC 0003\n   15 MC 0003\n   16 MC 3143\n   19 MR 3143 b1\n   19 MC 3143\n5c75 b3bd 25bd 98cf 0000 0000 0000 0000 2ba1 315c 0000 0004\n00 02 0 0 0 0 20\n\nfdcb5c  BIT 3,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 74\n   11 MC 0003\n   14 MR 0003 5c\n   14 MC 0003\n   15 MC 0003\n   16 MC 54b2\n   19 MR 54b2 e3\n   19 MC 54b2\nb354 d43d d9c0 b04d 0000 0000 0000 0000 21a9 543e 0000 0004\n00 02 0 0 0 0 20\n\nfdcb5d  BIT 3,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 dc\n   11 MC 0003\n   14 MR 0003 5d\n   14 MC 0003\n   15 MC 0003\n   16 MC 3b60\n   19 MR 3b60 ef\n   19 MC 3b60\n9f39 43dd ccb3 085a 0000 0000 0000 0000 f130 3b84 0000 0004\n00 02 0 0 0 0 20\n\nfdcb5e  BIT 3,(IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 e2\n   11 MC 0003\n   14 MR 0003 5e\n   14 MC 0003\n   15 MC 0003\n   16 MC e147\n   19 MR e147 17\n   19 MC e147\n6f75 eff5 993b 22b5 0000 0000 0000 0000 0f30 e165 0000 0004\n00 02 0 0 0 0 20\n\nfdcb5f  BIT 3,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 ab\n   11 MC 0003\n   14 MR 0003 5f\n   14 MC 0003\n   15 MC 0003\n   16 MC f7c6\n   19 MR f7c6 e2\n   19 MC f7c6\nd774 a57a aca6 667e 0000 0000 0000 0000 5c33 f81b 0000 0004\n00 02 0 0 0 0 20\n\nfdcb60  BIT 4,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 85\n   11 MC 0003\n   14 MR 0003 60\n   14 MC 0003\n   15 MC 0003\n   16 MC 8bc9\n   19 MR 8bc9 b9\n   19 MC 8bc9\n1519 8d30 43f4 c65e 0000 0000 0000 0000 1e34 8c44 0000 0004\n00 02 0 0 0 0 20\n\nfdcb61  BIT 4,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 be\n   11 MC 0003\n   14 MR 0003 61\n   14 MC 0003\n   15 MC 0003\n   16 MC 92a2\n   19 MR 92a2 28\n   19 MC 92a2\n7b55 d421 5570 cb85 0000 0000 0000 0000 32ec 92e4 0000 0004\n00 02 0 0 0 0 20\n\nfdcb62  BIT 4,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 9d\n   11 MC 0003\n   14 MR 0003 62\n   14 MC 0003\n   15 MC 0003\n   16 MC 7e4e\n   19 MR 7e4e 1a\n   19 MC 7e4e\nba39 4fbb 67a7 c5db 0000 0000 0000 0000 470b 7eb1 0000 0004\n00 02 0 0 0 0 20\n\nfdcb63  BIT 4,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 f4\n   11 MC 0003\n   14 MR 0003 63\n   14 MC 0003\n   15 MC 0003\n   16 MC 1707\n   19 MR 1707 3b\n   19 MC 1707\nc011 2cc2 ce12 e77c 0000 0000 0000 0000 71c5 1713 0000 0004\n00 02 0 0 0 0 20\n\nfdcb64  BIT 4,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 35\n   11 MC 0003\n   14 MR 0003 64\n   14 MC 0003\n   15 MC 0003\n   16 MC b36b\n   19 MR b36b 8c\n   19 MC b36b\n0c75 7847 2494 71eb 0000 0000 0000 0000 315c b336 0000 0004\n00 02 0 0 0 0 20\n\nfdcb65  BIT 4,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 37\n   11 MC 0003\n   14 MR 0003 65\n   14 MC 0003\n   15 MC 0003\n   16 MC 8a2b\n   19 MR 8a2b 08\n   19 MC 8a2b\n525d a82d 1112 8f09 0000 0000 0000 0000 672a 89f4 0000 0004\n00 02 0 0 0 0 20\n\nfdcb66  BIT 4,(IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 9d\n   11 MC 0003\n   14 MR 0003 66\n   14 MC 0003\n   15 MC 0003\n   16 MC 68e5\n   19 MR 68e5 90\n   19 MC 68e5\n5839 c13e b136 6bc5 0000 0000 0000 0000 3ef9 6948 0000 0004\n00 02 0 0 0 0 20\n\nfdcb67  BIT 4,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 cb\n   11 MC 0003\n   14 MR 0003 67\n   14 MC 0003\n   15 MC 0003\n   16 MC 653d\n   19 MR 653d 15\n   19 MC 653d\n3130 0f7d 48b5 cc5f 0000 0000 0000 0000 2103 6572 0000 0004\n00 02 0 0 0 0 20\n\nfdcb68  BIT 5,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 ca\n   11 MC 0003\n   14 MR 0003 68\n   14 MC 0003\n   15 MC 0003\n   16 MC 0388\n   19 MR 0388 83\n   19 MC 0388\ne354 39fb a03a 59bc 0000 0000 0000 0000 e04a 03be 0000 0004\n00 02 0 0 0 0 20\n\nfdcb69  BIT 5,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 e2\n   11 MC 0003\n   14 MR 0003 69\n   14 MC 0003\n   15 MC 0003\n   16 MC a5e5\n   19 MR a5e5 01\n   19 MC a5e5\n1874 5bc2 d4d9 4e8a 0000 0000 0000 0000 3716 a603 0000 0004\n00 02 0 0 0 0 20\n\nfdcb6a  BIT 5,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 ae\n   11 MC 0003\n   14 MR 0003 6a\n   14 MC 0003\n   15 MC 0003\n   16 MC 936c\n   19 MR 936c 33\n   19 MC 936c\n5b11 0099 34f8 3e96 0000 0000 0000 0000 f251 93be 0000 0004\n00 02 0 0 0 0 20\n\nfdcb6b  BIT 5,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 1f\n   11 MC 0003\n   14 MR 0003 6b\n   14 MC 0003\n   15 MC 0003\n   16 MC aa4e\n   19 MR aa4e 7c\n   19 MC aa4e\nbb39 9e6c abd1 515f 0000 0000 0000 0000 73db aa2f 0000 0004\n00 02 0 0 0 0 20\n\nfdcb6c  BIT 5,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 0d\n   11 MC 0003\n   14 MR 0003 6c\n   14 MC 0003\n   15 MC 0003\n   16 MC 86c7\n   19 MR 86c7 25\n   19 MC 86c7\n1411 3af2 8f80 7be5 0000 0000 0000 0000 c379 86ba 0000 0004\n00 02 0 0 0 0 20\n\nfdcb6d  BIT 5,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 f0\n   11 MC 0003\n   14 MR 0003 6d\n   14 MC 0003\n   15 MC 0003\n   16 MC 62b8\n   19 MR 62b8 e3\n   19 MC 62b8\n6330 d077 668d 6e4a 0000 0000 0000 0000 b0a8 62c8 0000 0004\n00 02 0 0 0 0 20\n\nfdcb6e  BIT 5,(IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 93\n   11 MC 0003\n   14 MR 0003 6e\n   14 MC 0003\n   15 MC 0003\n   16 MC 41a3\n   19 MR 41a3 1e\n   19 MC 41a3\n2d54 f872 692d 92c4 0000 0000 0000 0000 36b5 4210 0000 0004\n00 02 0 0 0 0 20\n\nfdcb6f  BIT 5,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 20\n   11 MC 0003\n   14 MR 0003 6f\n   14 MC 0003\n   15 MC 0003\n   16 MC 006e\n   19 MR 006e 37\n   19 MC 006e\ndf11 c7aa 9002 86b8 0000 0000 0000 0000 1347 004e 0000 0004\n00 02 0 0 0 0 20\n\nfdcb70  BIT 6,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 d9\n   11 MC 0003\n   14 MR 0003 70\n   14 MC 0003\n   15 MC 0003\n   16 MC 3e41\n   19 MR 3e41 c9\n   19 MC 3e41\n6e39 018d 5075 cf4e 0000 0000 0000 0000 cd2b 3e68 0000 0004\n00 02 0 0 0 0 20\n\nfdcb71  BIT 6,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 27\n   11 MC 0003\n   14 MR 0003 71\n   14 MC 0003\n   15 MC 0003\n   16 MC 99c1\n   19 MR 99c1 3e\n   19 MC 99c1\n1b5c e3af 94d5 0996 0000 0000 0000 0000 cad5 999a 0000 0004\n00 02 0 0 0 0 20\n\nfdcb72  BIT 6,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 98\n   11 MC 0003\n   14 MR 0003 72\n   14 MC 0003\n   15 MC 0003\n   16 MC fcc9\n   19 MR fcc9 4f\n   19 MC fcc9\ne839 26b1 8608 f3cb 0000 0000 0000 0000 6323 fd31 0000 0004\n00 02 0 0 0 0 20\n\nfdcb73  BIT 6,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 7a\n   11 MC 0003\n   14 MR 0003 73\n   14 MC 0003\n   15 MC 0003\n   16 MC f652\n   19 MR f652 31\n   19 MC f652\n1075 446c c2f9 b9b1 0000 0000 0000 0000 0820 f5d8 0000 0004\n00 02 0 0 0 0 20\n\nfdcb74  BIT 6,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 4b\n   11 MC 0003\n   14 MR 0003 74\n   14 MC 0003\n   15 MC 0003\n   16 MC 5e95\n   19 MR 5e95 fe\n   19 MC 5e95\n6819 38c2 0ea4 0825 0000 0000 0000 0000 d255 5e4a 0000 0004\n00 02 0 0 0 0 20\n\nfdcb75  BIT 6,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 57\n   11 MC 0003\n   14 MR 0003 75\n   14 MC 0003\n   15 MC 0003\n   16 MC 6115\n   19 MR 6115 21\n   19 MC 6115\n5674 c034 6e11 d35e 0000 0000 0000 0000 e702 60be 0000 0004\n00 02 0 0 0 0 20\n\nfdcb76  BIT 6,(IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 53\n   11 MC 0003\n   14 MR 0003 76\n   14 MC 0003\n   15 MC 0003\n   16 MC 6676\n   19 MR 6676 3a\n   19 MC 6676\n7375 caff dd80 c8ed 0000 0000 0000 0000 7e39 6623 0000 0004\n00 02 0 0 0 0 20\n\nfdcb77  BIT 6,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 02\n   11 MC 0003\n   14 MR 0003 77\n   14 MC 0003\n   15 MC 0003\n   16 MC 8843\n   19 MR 8843 d8\n   19 MC 8843\nab18 983e 0bdc 3b46 0000 0000 0000 0000 ae51 8841 0000 0004\n00 02 0 0 0 0 20\n\nfdcb78  BIT 7,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 7d\n   11 MC 0003\n   14 MR 0003 78\n   14 MC 0003\n   15 MC 0003\n   16 MC ff48\n   19 MR ff48 ec\n   19 MC ff48\n27b9 ce2f 4824 6930 0000 0000 0000 0000 ae69 fecb 0000 0004\n00 02 0 0 0 0 20\n\nfdcb79  BIT 7,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 23\n   11 MC 0003\n   14 MR 0003 79\n   14 MC 0003\n   15 MC 0003\n   16 MC 1cd1\n   19 MR 1cd1 87\n   19 MC 1cd1\nb498 6355 7896 8a7c 0000 0000 0000 0000 9090 1cae 0000 0004\n00 02 0 0 0 0 20\n\nfdcb7a  BIT 7,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 42\n   11 MC 0003\n   14 MR 0003 7a\n   14 MC 0003\n   15 MC 0003\n   16 MC d965\n   19 MR d965 b3\n   19 MC d965\n5998 ca21 1482 3fae 0000 0000 0000 0000 c6c9 d923 0000 0004\n00 02 0 0 0 0 20\n\nfdcb7b  BIT 7,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 17\n   11 MC 0003\n   14 MR 0003 7b\n   14 MC 0003\n   15 MC 0003\n   16 MC 0a9a\n   19 MR 0a9a bd\n   19 MC 0a9a\n6398 0240 5efa 5e7b 0000 0000 0000 0000 3e50 0a83 0000 0004\n00 02 0 0 0 0 20\n\nfdcb7c  BIT 7,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 f1\n   11 MC 0003\n   14 MR 0003 7c\n   14 MC 0003\n   15 MC 0003\n   16 MC d362\n   19 MR d362 1b\n   19 MC d362\n2254 aff4 b89b 4dca 0000 0000 0000 0000 0ac2 d371 0000 0004\n00 02 0 0 0 0 20\n\nfdcb7d  BIT 7,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 9f\n   11 MC 0003\n   14 MR 0003 7d\n   14 MC 0003\n   15 MC 0003\n   16 MC abda\n   19 MR abda 8a\n   19 MC abda\n1cb9 d615 825a 5e64 0000 0000 0000 0000 32fb ac3b 0000 0004\n00 02 0 0 0 0 20\n\nfdcb7e  BIT 7,(IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 40\n   11 MC 0003\n   14 MR 0003 7e\n   14 MC 0003\n   15 MC 0003\n   16 MC 94c4\n   19 MR 94c4 9e\n   19 MC 94c4\n5090 8dfe 1019 6778 0000 0000 0000 0000 f7df 9484 0000 0004\n00 02 0 0 0 0 20\n\nfdcb7f  BIT 7,(IY+d)*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 a2\n   11 MC 0003\n   14 MR 0003 7f\n   14 MC 0003\n   15 MC 0003\n   16 MC ce0b\n   19 MR ce0b 47\n   19 MC ce0b\n1b5d 9ec3 14be 5ebe 0000 0000 0000 0000 1178 ce69 0000 0004\n00 02 0 0 0 0 20\n\nfdcb80  RES 0,(IY+d),B*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 8b\n   11 MC 0003\n   14 MR 0003 80\n   14 MC 0003\n   15 MC 0003\n   16 MC 9198\n   19 MR 9198 a9\n   19 MC 9198\n   20 MC 9198\n   23 MW 9198 a8\ne196 a8ea 507e 6457 0000 0000 0000 0000 ab75 920d 0000 0004\n00 02 0 0 0 0 23\n9198 a8 -1\n\nfdcb81  RES 0,(IY+d),C*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 55\n   11 MC 0003\n   14 MR 0003 81\n   14 MC 0003\n   15 MC 0003\n   16 MC 82fa\n   19 MR 82fa fa\n   19 MC 82fa\n   20 MC 82fa\n   23 MW 82fa fa\n3d3d b2fa 8759 0cb0 0000 0000 0000 0000 e078 82a5 0000 0004\n00 02 0 0 0 0 23\n\nfdcb82  RES 0,(IY+d),D*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 9c\n   11 MC 0003\n   14 MR 0003 82\n   14 MC 0003\n   15 MC 0003\n   16 MC 5d74\n   19 MR 5d74 9d\n   19 MC 5d74\n   20 MC 5d74\n   23 MW 5d74 9c\n4e10 5d8d 9ca0 ffff 0000 0000 0000 0000 ee0a 5dd8 0000 0004\n00 02 0 0 0 0 23\n5d74 9c -1\n\nfdcb83  RES 0,(IY+d),E*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 28\n   11 MC 0003\n   14 MR 0003 83\n   14 MC 0003\n   15 MC 0003\n   16 MC 3772\n   19 MR 3772 d5\n   19 MC 3772\n   20 MC 3772\n   23 MW 3772 d4\n3c7f fd81 47d4 9f12 0000 0000 0000 0000 cbf9 374a 0000 0004\n00 02 0 0 0 0 23\n3772 d4 -1\n\nfdcb84  RES 0,(IY+d),H*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 aa\n   11 MC 0003\n   14 MR 0003 84\n   14 MC 0003\n   15 MC 0003\n   16 MC f16d\n   19 MR f16d ea\n   19 MC f16d\n   20 MC f16d\n   23 MW f16d ea\n6872 81b1 1e7a ea7e 0000 0000 0000 0000 9b4c f1c3 0000 0004\n00 02 0 0 0 0 23\n\nfdcb85  RES 0,(IY+d),L*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 6c\n   11 MC 0003\n   14 MR 0003 85\n   14 MC 0003\n   15 MC 0003\n   16 MC 049f\n   19 MR 049f e0\n   19 MC 049f\n   20 MC 049f\n   23 MW 049f e0\n25b3 5694 57cd f3e0 0000 0000 0000 0000 8ed2 0433 0000 0004\n00 02 0 0 0 0 23\n\nfdcb86  RES 0,(IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 7e\n   11 MC 0003\n   14 MR 0003 86\n   14 MC 0003\n   15 MC 0003\n   16 MC 2ace\n   19 MR 2ace 36\n   19 MC 2ace\n   20 MC 2ace\n   23 MW 2ace 36\n152b 8ce1 818d 40f2 0000 0000 0000 0000 9b7a 2a50 0000 0004\n00 02 0 0 0 0 23\n\nfdcb87  RES 0,(IY+d),A*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 59\n   11 MC 0003\n   14 MR 0003 87\n   14 MC 0003\n   15 MC 0003\n   16 MC 24c3\n   19 MR 24c3 65\n   19 MC 24c3\n   20 MC 24c3\n   23 MW 24c3 64\n641d 5353 618d 3266 0000 0000 0000 0000 1a53 246a 0000 0004\n00 02 0 0 0 0 23\n24c3 64 -1\n\nfdcb88  RES 1,(IY+d),B*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 d4\n   11 MC 0003\n   14 MR 0003 88\n   14 MC 0003\n   15 MC 0003\n   16 MC c5e1\n   19 MR c5e1 d6\n   19 MC c5e1\n   20 MC c5e1\n   23 MW c5e1 d4\n7d14 d4ec 1e47 76e1 0000 0000 0000 0000 3871 c60d 0000 0004\n00 02 0 0 0 0 23\nc5e1 d4 -1\n\nfdcb89  RES 1,(IY+d),C*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 c3\n   11 MC 0003\n   14 MR 0003 89\n   14 MC 0003\n   15 MC 0003\n   16 MC 09c4\n   19 MR 09c4 b0\n   19 MC 09c4\n   20 MC 09c4\n   23 MW 09c4 b0\n86c3 50b0 8592 d6ca 0000 0000 0000 0000 947b 0a01 0000 0004\n00 02 0 0 0 0 23\n\nfdcb8a  RES 1,(IY+d),D*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 f9\n   11 MC 0003\n   14 MR 0003 8a\n   14 MC 0003\n   15 MC 0003\n   16 MC d4cb\n   19 MR d4cb d8\n   19 MC d4cb\n   20 MC d4cb\n   23 MW d4cb d8\n599c 961a d8f9 8470 0000 0000 0000 0000 d2a5 d4d2 0000 0004\n00 02 0 0 0 0 23\n\nfdcb8b  RES 1,(IY+d),E*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 ed\n   11 MC 0003\n   14 MR 0003 8b\n   14 MC 0003\n   15 MC 0003\n   16 MC c70b\n   19 MR c70b dc\n   19 MC c70b\n   20 MC c70b\n   23 MW c70b dc\n2715 a209 abdc 3eac 0000 0000 0000 0000 f352 c71e 0000 0004\n00 02 0 0 0 0 23\n\nfdcb8c  RES 1,(IY+d),H*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 97\n   11 MC 0003\n   14 MR 0003 8c\n   14 MC 0003\n   15 MC 0003\n   16 MC a199\n   19 MR a199 67\n   19 MC a199\n   20 MC a199\n   23 MW a199 65\n2818 4259 a9b0 65a0 0000 0000 0000 0000 6471 a202 0000 0004\n00 02 0 0 0 0 23\na199 65 -1\n\nfdcb8d  RES 1,(IY+d),L*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 c9\n   11 MC 0003\n   14 MR 0003 8d\n   14 MC 0003\n   15 MC 0003\n   16 MC 5632\n   19 MR 5632 9a\n   19 MC 5632\n   20 MC 5632\n   23 MW 5632 98\n14e3 c330 9aa2 8498 0000 0000 0000 0000 0d4f 5669 0000 0004\n00 02 0 0 0 0 23\n5632 98 -1\n\nfdcb8e  RES 1,(IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 c2\n   11 MC 0003\n   14 MR 0003 8e\n   14 MC 0003\n   15 MC 0003\n   16 MC 4c43\n   19 MR 4c43 7f\n   19 MC 4c43\n   20 MC 4c43\n   23 MW 4c43 7d\ncb79 0fff b244 c902 0000 0000 0000 0000 6246 4c81 0000 0004\n00 02 0 0 0 0 23\n4c43 7d -1\n\nfdcb8f  RES 1,(IY+d),A*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 d4\n   11 MC 0003\n   14 MR 0003 8f\n   14 MC 0003\n   15 MC 0003\n   16 MC 6b25\n   19 MR 6b25 59\n   19 MC 6b25\n   20 MC 6b25\n   23 MW 6b25 59\n59b4 5fbb 6c9b d0e3 0000 0000 0000 0000 ac5a 6b51 0000 0004\n00 02 0 0 0 0 23\n\nfdcb90  RES 2,(IY+d),B*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 fd\n   11 MC 0003\n   14 MR 0003 90\n   14 MC 0003\n   15 MC 0003\n   16 MC d7f2\n   19 MR d7f2 70\n   19 MC d7f2\n   20 MC d7f2\n   23 MW d7f2 70\n1305 70e1 d627 7402 0000 0000 0000 0000 b470 d7f5 0000 0004\n00 02 0 0 0 0 23\n\nfdcb91  RES 2,(IY+d),C*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 bf\n   11 MC 0003\n   14 MR 0003 91\n   14 MC 0003\n   15 MC 0003\n   16 MC 4791\n   19 MR 4791 0e\n   19 MC 4791\n   20 MC 4791\n   23 MW 4791 0a\n10df c40a 0213 fc7e 0000 0000 0000 0000 bfab 47d2 0000 0004\n00 02 0 0 0 0 23\n4791 0a -1\n\nfdcb92  RES 2,(IY+d),D*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 0b\n   11 MC 0003\n   14 MR 0003 92\n   14 MC 0003\n   15 MC 0003\n   16 MC 3145\n   19 MR 3145 f6\n   19 MC 3145\n   20 MC 3145\n   23 MW 3145 f2\n6a11 f89e f29d c115 0000 0000 0000 0000 bc5d 313a 0000 0004\n00 02 0 0 0 0 23\n3145 f2 -1\n\nfdcb93  RES 2,(IY+d),E*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 52\n   11 MC 0003\n   14 MR 0003 93\n   14 MC 0003\n   15 MC 0003\n   16 MC 2992\n   19 MR 2992 38\n   19 MC 2992\n   20 MC 2992\n   23 MW 2992 38\n61e5 cc2c 9538 b52b 0000 0000 0000 0000 fa64 2940 0000 0004\n00 02 0 0 0 0 23\n\nfdcb94  RES 2,(IY+d),H*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 95\n   11 MC 0003\n   14 MR 0003 94\n   14 MC 0003\n   15 MC 0003\n   16 MC fdb1\n   19 MR fdb1 48\n   19 MC fdb1\n   20 MC fdb1\n   23 MW fdb1 48\n31b4 3e5a fb3d 4883 0000 0000 0000 0000 a801 fe1c 0000 0004\n00 02 0 0 0 0 23\n\nfdcb95  RES 2,(IY+d),L*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 90\n   11 MC 0003\n   14 MR 0003 95\n   14 MC 0003\n   15 MC 0003\n   16 MC e706\n   19 MR e706 eb\n   19 MC e706\n   20 MC e706\n   23 MW e706 eb\n337e 63a7 2918 edeb 0000 0000 0000 0000 b12c e776 0000 0004\n00 02 0 0 0 0 23\n\nfdcb96  RES 2,(IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 9e\n   11 MC 0003\n   14 MR 0003 96\n   14 MC 0003\n   15 MC 0003\n   16 MC e66d\n   19 MR e66d fc\n   19 MC e66d\n   20 MC e66d\n   23 MW e66d f8\n5d99 d9ec b6d0 5ed5 0000 0000 0000 0000 5d9d e6cf 0000 0004\n00 02 0 0 0 0 23\ne66d f8 -1\n\nfdcb97  RES 2,(IY+d),A*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 64\n   11 MC 0003\n   14 MR 0003 97\n   14 MC 0003\n   15 MC 0003\n   16 MC 18e3\n   19 MR 18e3 9d\n   19 MC 18e3\n   20 MC 18e3\n   23 MW 18e3 99\n99b6 8406 72c6 1ba7 0000 0000 0000 0000 6dca 187f 0000 0004\n00 02 0 0 0 0 23\n18e3 99 -1\n\nfdcb98  RES 3,(IY+d),B*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 da\n   11 MC 0003\n   14 MR 0003 98\n   14 MC 0003\n   15 MC 0003\n   16 MC 4392\n   19 MR 4392 15\n   19 MC 4392\n   20 MC 4392\n   23 MW 4392 15\n0495 152f 8000 b749 0000 0000 0000 0000 e9cb 43b8 0000 0004\n00 02 0 0 0 0 23\n\nfdcb99  RES 3,(IY+d),C*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 78\n   11 MC 0003\n   14 MR 0003 99\n   14 MC 0003\n   15 MC 0003\n   16 MC d8e4\n   19 MR d8e4 b5\n   19 MC d8e4\n   20 MC d8e4\n   23 MW d8e4 b5\n2824 a4b5 a30b b286 0000 0000 0000 0000 10b0 d86c 0000 0004\n00 02 0 0 0 0 23\n\nfdcb9a  RES 3,(IY+d),D*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 9c\n   11 MC 0003\n   14 MR 0003 9a\n   14 MC 0003\n   15 MC 0003\n   16 MC d6b3\n   19 MR d6b3 9d\n   19 MC d6b3\n   20 MC d6b3\n   23 MW d6b3 95\nb0cc c40c 951a 014a 0000 0000 0000 0000 2ff9 d717 0000 0004\n00 02 0 0 0 0 23\nd6b3 95 -1\n\nfdcb9b  RES 3,(IY+d),E*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 83\n   11 MC 0003\n   14 MR 0003 9b\n   14 MC 0003\n   15 MC 0003\n   16 MC caa1\n   19 MR caa1 95\n   19 MC caa1\n   20 MC caa1\n   23 MW caa1 95\nd092 a6c2 7995 5448 0000 0000 0000 0000 fab0 cb1e 0000 0004\n00 02 0 0 0 0 23\n\nfdcb9c  RES 3,(IY+d),H*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 1e\n   11 MC 0003\n   14 MR 0003 9c\n   14 MC 0003\n   15 MC 0003\n   16 MC 03d1\n   19 MR 03d1 78\n   19 MC 03d1\n   20 MC 03d1\n   23 MW 03d1 70\nb58d 1ed1 e93b 700c 0000 0000 0000 0000 5605 03b3 0000 0004\n00 02 0 0 0 0 23\n03d1 70 -1\n\nfdcb9d  RES 3,(IY+d),L*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 e6\n   11 MC 0003\n   14 MR 0003 9d\n   14 MC 0003\n   15 MC 0003\n   16 MC c06d\n   19 MR c06d 53\n   19 MC c06d\n   20 MC c06d\n   23 MW c06d 53\nc7e9 18d3 8eed bd53 0000 0000 0000 0000 9a7f c087 0000 0004\n00 02 0 0 0 0 23\n\nfdcb9e  RES 3,(IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 eb\n   11 MC 0003\n   14 MR 0003 9e\n   14 MC 0003\n   15 MC 0003\n   16 MC 41a8\n   19 MR 41a8 61\n   19 MC 41a8\n   20 MC 41a8\n   23 MW 41a8 61\n81c7 71df 45d5 0ca7 0000 0000 0000 0000 648f 41bd 0000 0004\n00 02 0 0 0 0 23\n\nfdcb9f  RES 3,(IY+d),A*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 50\n   11 MC 0003\n   14 MR 0003 9f\n   14 MC 0003\n   15 MC 0003\n   16 MC 9d99\n   19 MR 9d99 89\n   19 MC 9d99\n   20 MC 9d99\n   23 MW 9d99 81\n81f5 dc9f d490 15be 0000 0000 0000 0000 0e12 9d49 0000 0004\n00 02 0 0 0 0 23\n9d99 81 -1\n\nfdcba0  RES 4,(IY+d),B*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 76\n   11 MC 0003\n   14 MR 0003 a0\n   14 MC 0003\n   15 MC 0003\n   16 MC d703\n   19 MR d703 d4\n   19 MC d703\n   20 MC d703\n   23 MW d703 c4\n8ccb c457 bc19 e543 0000 0000 0000 0000 8c5d d68d 0000 0004\n00 02 0 0 0 0 23\nd703 c4 -1\n\nfdcba1  RES 4,(IY+d),C*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 31\n   11 MC 0003\n   14 MR 0003 a1\n   14 MC 0003\n   15 MC 0003\n   16 MC 66f9\n   19 MR 66f9 ec\n   19 MC 66f9\n   20 MC 66f9\n   23 MW 66f9 ec\neee6 6dec 3a20 8bba 0000 0000 0000 0000 1de7 66c8 0000 0004\n00 02 0 0 0 0 23\n\nfdcba2  RES 4,(IY+d),D*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 0e\n   11 MC 0003\n   14 MR 0003 a2\n   14 MC 0003\n   15 MC 0003\n   16 MC 04cd\n   19 MR 04cd 47\n   19 MC 04cd\n   20 MC 04cd\n   23 MW 04cd 47\n3f89 5120 47d1 e669 0000 0000 0000 0000 2993 04bf 0000 0004\n00 02 0 0 0 0 23\n\nfdcba3  RES 4,(IY+d),E*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 05\n   11 MC 0003\n   14 MR 0003 a3\n   14 MC 0003\n   15 MC 0003\n   16 MC ad7c\n   19 MR ad7c 59\n   19 MC ad7c\n   20 MC ad7c\n   23 MW ad7c 49\n4439 6b8b 6149 1246 0000 0000 0000 0000 4cdb ad77 0000 0004\n00 02 0 0 0 0 23\nad7c 49 -1\n\nfdcba4  RES 4,(IY+d),H*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 66\n   11 MC 0003\n   14 MR 0003 a4\n   14 MC 0003\n   15 MC 0003\n   16 MC c133\n   19 MR c133 c5\n   19 MC c133\n   20 MC c133\n   23 MW c133 c5\n3385 261e a487 c5bd 0000 0000 0000 0000 4b8f c0cd 0000 0004\n00 02 0 0 0 0 23\n\nfdcba5  RES 4,(IY+d),L*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 a0\n   11 MC 0003\n   14 MR 0003 a5\n   14 MC 0003\n   15 MC 0003\n   16 MC f141\n   19 MR f141 44\n   19 MC f141\n   20 MC f141\n   23 MW f141 44\n6e70 b7ed 22cd ae44 0000 0000 0000 0000 46de f1a1 0000 0004\n00 02 0 0 0 0 23\n\nfdcba6  RES 4,(IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 76\n   11 MC 0003\n   14 MR 0003 a6\n   14 MC 0003\n   15 MC 0003\n   16 MC 9469\n   19 MR 9469 bc\n   19 MC 9469\n   20 MC 9469\n   23 MW 9469 ac\n814b 6408 3dcb 971f 0000 0000 0000 0000 5716 93f3 0000 0004\n00 02 0 0 0 0 23\n9469 ac -1\n\nfdcba7  RES 4,(IY+d),A*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 66\n   11 MC 0003\n   14 MR 0003 a7\n   14 MC 0003\n   15 MC 0003\n   16 MC 7a2a\n   19 MR 7a2a 2e\n   19 MC 7a2a\n   20 MC 7a2a\n   23 MW 7a2a 2e\n2ec2 679e c313 61df 0000 0000 0000 0000 67e6 79c4 0000 0004\n00 02 0 0 0 0 23\n\nfdcba8  RES 5,(IY+d),B*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 a9\n   11 MC 0003\n   14 MR 0003 a8\n   14 MC 0003\n   15 MC 0003\n   16 MC 0cef\n   19 MR 0cef b7\n   19 MC 0cef\n   20 MC 0cef\n   23 MW 0cef 97\n537c 97ed 6cbb bd26 0000 0000 0000 0000 c638 0d46 0000 0004\n00 02 0 0 0 0 23\n0cef 97 -1\n\nfdcba9  RES 5,(IY+d),C*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 2b\n   11 MC 0003\n   14 MR 0003 a9\n   14 MC 0003\n   15 MC 0003\n   16 MC 0f7f\n   19 MR 0f7f 8f\n   19 MC 0f7f\n   20 MC 0f7f\n   23 MW 0f7f 8f\nba5a 308f cdd7 298d 0000 0000 0000 0000 59ab 0f54 0000 0004\n00 02 0 0 0 0 23\n\nfdcbaa  RES 5,(IY+d),D*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 0b\n   11 MC 0003\n   14 MR 0003 aa\n   14 MC 0003\n   15 MC 0003\n   16 MC b3dc\n   19 MR b3dc 3a\n   19 MC b3dc\n   20 MC b3dc\n   23 MW b3dc 1a\n406a 2ed6 1a8c c633 0000 0000 0000 0000 87cb b3d1 0000 0004\n00 02 0 0 0 0 23\nb3dc 1a -1\n\nfdcbab  RES 5,(IY+d),E*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 a9\n   11 MC 0003\n   14 MR 0003 ab\n   14 MC 0003\n   15 MC 0003\n   16 MC 8e77\n   19 MR 8e77 1f\n   19 MC 8e77\n   20 MC 8e77\n   23 MW 8e77 1f\nda61 0521 a11f c7fa 0000 0000 0000 0000 b71a 8ece 0000 0004\n00 02 0 0 0 0 23\n\nfdcbac  RES 5,(IY+d),H*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 23\n   11 MC 0003\n   14 MR 0003 ac\n   14 MC 0003\n   15 MC 0003\n   16 MC 0548\n   19 MR 0548 9c\n   19 MC 0548\n   20 MC 0548\n   23 MW 0548 9c\n34a3 81ce 07d6 9ca4 0000 0000 0000 0000 430b 0525 0000 0004\n00 02 0 0 0 0 23\n\nfdcbad  RES 5,(IY+d),L*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 4e\n   11 MC 0003\n   14 MR 0003 ad\n   14 MC 0003\n   15 MC 0003\n   16 MC 94dd\n   19 MR 94dd 37\n   19 MC 94dd\n   20 MC 94dd\n   23 MW 94dd 17\n5010 918e ddbc 4f17 0000 0000 0000 0000 88c5 948f 0000 0004\n00 02 0 0 0 0 23\n94dd 17 -1\n\nfdcbae  RES 5,(IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 0c\n   11 MC 0003\n   14 MR 0003 ae\n   14 MC 0003\n   15 MC 0003\n   16 MC 0c29\n   19 MR 0c29 a9\n   19 MC 0c29\n   20 MC 0c29\n   23 MW 0c29 89\nec0d b57e 18c6 7b01 0000 0000 0000 0000 bac6 0c1d 0000 0004\n00 02 0 0 0 0 23\n0c29 89 -1\n\nfdcbaf  RES 5,(IY+d),A*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 0d\n   11 MC 0003\n   14 MR 0003 af\n   14 MC 0003\n   15 MC 0003\n   16 MC 26f8\n   19 MR 26f8 44\n   19 MC 26f8\n   20 MC 26f8\n   23 MW 26f8 44\n4422 6731 daad 8d38 0000 0000 0000 0000 dd8f 26eb 0000 0004\n00 02 0 0 0 0 23\n\nfdcbb0  RES 6,(IY+d),B*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 5a\n   11 MC 0003\n   14 MR 0003 b0\n   14 MC 0003\n   15 MC 0003\n   16 MC a125\n   19 MR a125 76\n   19 MC a125\n   20 MC a125\n   23 MW a125 36\nb984 366c 44b1 fef9 0000 0000 0000 0000 4069 a0cb 0000 0004\n00 02 0 0 0 0 23\na125 36 -1\n\nfdcbb1  RES 6,(IY+d),C*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 82\n   11 MC 0003\n   14 MR 0003 b1\n   14 MC 0003\n   15 MC 0003\n   16 MC f31a\n   19 MR f31a 79\n   19 MC f31a\n   20 MC f31a\n   23 MW f31a 39\n59c3 ab39 42ee b764 0000 0000 0000 0000 8f7f f398 0000 0004\n00 02 0 0 0 0 23\nf31a 39 -1\n\nfdcbb2  RES 6,(IY+d),D*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 23\n   11 MC 0003\n   14 MR 0003 b2\n   14 MC 0003\n   15 MC 0003\n   16 MC 341c\n   19 MR 341c 7b\n   19 MC 341c\n   20 MC 341c\n   23 MW 341c 3b\nf310 ceec 3bfb 3569 0000 0000 0000 0000 4a6f 33f9 0000 0004\n00 02 0 0 0 0 23\n341c 3b -1\n\nfdcbb3  RES 6,(IY+d),E*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 6c\n   11 MC 0003\n   14 MR 0003 b3\n   14 MC 0003\n   15 MC 0003\n   16 MC 523e\n   19 MR 523e 37\n   19 MC 523e\n   20 MC 523e\n   23 MW 523e 37\n9c05 0f92 bd37 553d 0000 0000 0000 0000 c75e 51d2 0000 0004\n00 02 0 0 0 0 23\n\nfdcbb4  RES 6,(IY+d),H*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 c5\n   11 MC 0003\n   14 MR 0003 b4\n   14 MC 0003\n   15 MC 0003\n   16 MC 4cdc\n   19 MR 4cdc e9\n   19 MC 4cdc\n   20 MC 4cdc\n   23 MW 4cdc a9\n3e55 1338 638d a93c 0000 0000 0000 0000 44ad 4d17 0000 0004\n00 02 0 0 0 0 23\n4cdc a9 -1\n\nfdcbb5  RES 6,(IY+d),L*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 50\n   11 MC 0003\n   14 MR 0003 b5\n   14 MC 0003\n   15 MC 0003\n   16 MC 8f2d\n   19 MR 8f2d 0f\n   19 MC 8f2d\n   20 MC 8f2d\n   23 MW 8f2d 0f\n2f3a b709 4167 570f 0000 0000 0000 0000 b543 8edd 0000 0004\n00 02 0 0 0 0 23\n\nfdcbb6  RES 6,(IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 3a\n   11 MC 0003\n   14 MR 0003 b6\n   14 MC 0003\n   15 MC 0003\n   16 MC 1e50\n   19 MR 1e50 13\n   19 MC 1e50\n   20 MC 1e50\n   23 MW 1e50 13\na887 519b c91b cc91 0000 0000 0000 0000 a416 1e16 0000 0004\n00 02 0 0 0 0 23\n\nfdcbb7  RES 6,(IY+d),A*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 c0\n   11 MC 0003\n   14 MR 0003 b7\n   14 MC 0003\n   15 MC 0003\n   16 MC 0069\n   19 MR 0069 38\n   19 MC 0069\n   20 MC 0069\n   23 MW 0069 38\n3835 a599 9fbf c111 0000 0000 0000 0000 8bc5 00a9 0000 0004\n00 02 0 0 0 0 23\n\nfdcbb8  RES 7,(IY+d),B*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 31\n   11 MC 0003\n   14 MR 0003 b8\n   14 MC 0003\n   15 MC 0003\n   16 MC d0b8\n   19 MR d0b8 17\n   19 MC d0b8\n   20 MC d0b8\n   23 MW d0b8 17\nd146 1738 1a45 8259 0000 0000 0000 0000 6a03 d087 0000 0004\n00 02 0 0 0 0 23\n\nfdcbb9  RES 7,(IY+d),C*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 3b\n   11 MC 0003\n   14 MR 0003 b9\n   14 MC 0003\n   15 MC 0003\n   16 MC b889\n   19 MR b889 b4\n   19 MC b889\n   20 MC b889\n   23 MW b889 34\n757b 0b34 767b 2ad1 0000 0000 0000 0000 1498 b84e 0000 0004\n00 02 0 0 0 0 23\nb889 34 -1\n\nfdcbba  RES 7,(IY+d),D*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 38\n   11 MC 0003\n   14 MR 0003 ba\n   14 MC 0003\n   15 MC 0003\n   16 MC 3877\n   19 MR 3877 d6\n   19 MC 3877\n   20 MC 3877\n   23 MW 3877 56\n43ef 1c58 56a3 4519 0000 0000 0000 0000 b67b 383f 0000 0004\n00 02 0 0 0 0 23\n3877 56 -1\n\nfdcbbb  RES 7,(IY+d),E*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 07\n   11 MC 0003\n   14 MR 0003 bb\n   14 MC 0003\n   15 MC 0003\n   16 MC e305\n   19 MR e305 6e\n   19 MC e305\n   20 MC e305\n   23 MW e305 6e\ndccb 7ab3 766e 4161 0000 0000 0000 0000 2942 e2fe 0000 0004\n00 02 0 0 0 0 23\n\nfdcbbc  RES 7,(IY+d),H*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 f8\n   11 MC 0003\n   14 MR 0003 bc\n   14 MC 0003\n   15 MC 0003\n   16 MC af04\n   19 MR af04 cf\n   19 MC af04\n   20 MC af04\n   23 MW af04 4f\n0e07 34f5 0995 4f42 0000 0000 0000 0000 9d42 af0c 0000 0004\n00 02 0 0 0 0 23\naf04 4f -1\n\nfdcbbd  RES 7,(IY+d),L*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 aa\n   11 MC 0003\n   14 MR 0003 bd\n   14 MC 0003\n   15 MC 0003\n   16 MC deb7\n   19 MR deb7 8d\n   19 MC deb7\n   20 MC deb7\n   23 MW deb7 0d\n30ef e60c 9bf0 a10d 0000 0000 0000 0000 bd1c df0d 0000 0004\n00 02 0 0 0 0 23\ndeb7 0d -1\n\nfdcbbe  RES 7,(IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 c8\n   11 MC 0003\n   14 MR 0003 be\n   14 MC 0003\n   15 MC 0003\n   16 MC 3cd7\n   19 MR 3cd7 a1\n   19 MC 3cd7\n   20 MC 3cd7\n   23 MW 3cd7 21\n1133 bef6 5059 1089 0000 0000 0000 0000 d558 3d0f 0000 0004\n00 02 0 0 0 0 23\n3cd7 21 -1\n\nfdcbbf  RES 7,(IY+d),A*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 fd\n   11 MC 0003\n   14 MR 0003 bf\n   14 MC 0003\n   15 MC 0003\n   16 MC bde4\n   19 MR bde4 ac\n   19 MC bde4\n   20 MC bde4\n   23 MW bde4 2c\n2cd6 c893 8db8 716b 0000 0000 0000 0000 0956 bde7 0000 0004\n00 02 0 0 0 0 23\nbde4 2c -1\n\nfdcbc0  SET 0,(IY+d),B*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 0a\n   11 MC 0003\n   14 MR 0003 c0\n   14 MC 0003\n   15 MC 0003\n   16 MC 2b3b\n   19 MR 2b3b ec\n   19 MC 2b3b\n   20 MC 2b3b\n   23 MW 2b3b ed\n3666 ed6c 35e5 db0a 0000 0000 0000 0000 ea93 2b31 0000 0004\n00 02 0 0 0 0 23\n2b3b ed -1\n\nfdcbc1  SET 0,(IY+d),C*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 87\n   11 MC 0003\n   14 MR 0003 c1\n   14 MC 0003\n   15 MC 0003\n   16 MC bcee\n   19 MR bcee ee\n   19 MC bcee\n   20 MC bcee\n   23 MW bcee ef\n3902 d4ef af62 9821 0000 0000 0000 0000 48b8 bd67 0000 0004\n00 02 0 0 0 0 23\nbcee ef -1\n\nfdcbc2  SET 0,(IY+d),D*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 8d\n   11 MC 0003\n   14 MR 0003 c2\n   14 MC 0003\n   15 MC 0003\n   16 MC 5ab9\n   19 MR 5ab9 c2\n   19 MC 5ab9\n   20 MC 5ab9\n   23 MW 5ab9 c3\nad26 5a6d c362 16c9 0000 0000 0000 0000 495a 5b2c 0000 0004\n00 02 0 0 0 0 23\n5ab9 c3 -1\n\nfdcbc3  SET 0,(IY+d),E*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 5a\n   11 MC 0003\n   14 MR 0003 c3\n   14 MC 0003\n   15 MC 0003\n   16 MC e6c0\n   19 MR e6c0 4f\n   19 MC e6c0\n   20 MC e6c0\n   23 MW e6c0 4f\n3e6c 9a74 a24f 9838 0000 0000 0000 0000 eafa e666 0000 0004\n00 02 0 0 0 0 23\n\nfdcbc4  SET 0,(IY+d),H*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 89\n   11 MC 0003\n   14 MR 0003 c4\n   14 MC 0003\n   15 MC 0003\n   16 MC 5c99\n   19 MR 5c99 61\n   19 MC 5c99\n   20 MC 5c99\n   23 MW 5c99 61\nbf68 d00b 5283 61c2 0000 0000 0000 0000 517c 5d10 0000 0004\n00 02 0 0 0 0 23\n\nfdcbc5  SET 0,(IY+d),L*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 a9\n   11 MC 0003\n   14 MR 0003 c5\n   14 MC 0003\n   15 MC 0003\n   16 MC 0264\n   19 MR 0264 cd\n   19 MC 0264\n   20 MC 0264\n   23 MW 0264 cd\n127b db6a 00b9 51cd 0000 0000 0000 0000 98f6 02bb 0000 0004\n00 02 0 0 0 0 23\n\nfdcbc6  SET 0,(IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 ee\n   11 MC 0003\n   14 MR 0003 c6\n   14 MC 0003\n   15 MC 0003\n   16 MC 76b2\n   19 MR 76b2 82\n   19 MC 76b2\n   20 MC 76b2\n   23 MW 76b2 83\n35da 98c2 3f57 44a4 0000 0000 0000 0000 2771 76c4 0000 0004\n00 02 0 0 0 0 23\n76b2 83 -1\n\nfdcbc7  SET 0,(IY+d),A*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 9e\n   11 MC 0003\n   14 MR 0003 c7\n   14 MC 0003\n   15 MC 0003\n   16 MC f2a9\n   19 MR f2a9 d7\n   19 MC f2a9\n   20 MC f2a9\n   23 MW f2a9 d7\nd73f b86f 12d3 7e2d 0000 0000 0000 0000 d870 f30b 0000 0004\n00 02 0 0 0 0 23\n\nfdcbc8  SET 1,(IY+d),B*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 10\n   11 MC 0003\n   14 MR 0003 c8\n   14 MC 0003\n   15 MC 0003\n   16 MC c422\n   19 MR c422 e9\n   19 MC c422\n   20 MC c422\n   23 MW c422 eb\n1f81 ebc0 85da 3cdd 0000 0000 0000 0000 d854 c412 0000 0004\n00 02 0 0 0 0 23\nc422 eb -1\n\nfdcbc9  SET 1,(IY+d),C*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 61\n   11 MC 0003\n   14 MR 0003 c9\n   14 MC 0003\n   15 MC 0003\n   16 MC 8ba3\n   19 MR 8ba3 b7\n   19 MC 8ba3\n   20 MC 8ba3\n   23 MW 8ba3 b7\ned19 3fb7 1370 e084 0000 0000 0000 0000 4fdd 8b42 0000 0004\n00 02 0 0 0 0 23\n\nfdcbca  SET 1,(IY+d),D*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 1a\n   11 MC 0003\n   14 MR 0003 ca\n   14 MC 0003\n   15 MC 0003\n   16 MC 51aa\n   19 MR 51aa 90\n   19 MC 51aa\n   20 MC 51aa\n   23 MW 51aa 92\nc7e5 233b 9212 f7f9 0000 0000 0000 0000 e417 5190 0000 0004\n00 02 0 0 0 0 23\n51aa 92 -1\n\nfdcbcb  SET 1,(IY+d),E*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 5e\n   11 MC 0003\n   14 MR 0003 cb\n   14 MC 0003\n   15 MC 0003\n   16 MC 9ad0\n   19 MR 9ad0 70\n   19 MC 9ad0\n   20 MC 9ad0\n   23 MW 9ad0 72\nbdba a964 ea72 9422 0000 0000 0000 0000 fca3 9a72 0000 0004\n00 02 0 0 0 0 23\n9ad0 72 -1\n\nfdcbcc  SET 1,(IY+d),H*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 2d\n   11 MC 0003\n   14 MR 0003 cc\n   14 MC 0003\n   15 MC 0003\n   16 MC 1526\n   19 MR 1526 4e\n   19 MC 1526\n   20 MC 1526\n   23 MW 1526 4e\n0f4f 0261 21b0 4e97 0000 0000 0000 0000 575d 14f9 0000 0004\n00 02 0 0 0 0 23\n\nfdcbcd  SET 1,(IY+d),L*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 a1\n   11 MC 0003\n   14 MR 0003 cd\n   14 MC 0003\n   15 MC 0003\n   16 MC bb8a\n   19 MR bb8a 66\n   19 MC bb8a\n   20 MC bb8a\n   23 MW bb8a 66\n1b79 8f9f 31bf 9c66 0000 0000 0000 0000 7ecb bbe9 0000 0004\n00 02 0 0 0 0 23\n\nfdcbce  SET 1,(IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 36\n   11 MC 0003\n   14 MR 0003 ce\n   14 MC 0003\n   15 MC 0003\n   16 MC b8d8\n   19 MR b8d8 45\n   19 MC b8d8\n   20 MC b8d8\n   23 MW b8d8 47\n8e13 968e 1784 0a0a 0000 0000 0000 0000 1e87 b8a2 0000 0004\n00 02 0 0 0 0 23\nb8d8 47 -1\n\nfdcbcf  SET 1,(IY+d),A*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 70\n   11 MC 0003\n   14 MR 0003 cf\n   14 MC 0003\n   15 MC 0003\n   16 MC c30c\n   19 MR c30c 7a\n   19 MC c30c\n   20 MC c30c\n   23 MW c30c 7a\n7a0a a073 c4ba 5b69 0000 0000 0000 0000 3b47 c29c 0000 0004\n00 02 0 0 0 0 23\n\nfdcbd0  SET 2,(IY+d),B*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 bc\n   11 MC 0003\n   14 MR 0003 d0\n   14 MC 0003\n   15 MC 0003\n   16 MC 3ba7\n   19 MR 3ba7 20\n   19 MC 3ba7\n   20 MC 3ba7\n   23 MW 3ba7 24\ne2bb 2435 650c 689a 0000 0000 0000 0000 1294 3beb 0000 0004\n00 02 0 0 0 0 23\n3ba7 24 -1\n\nfdcbd1  SET 2,(IY+d),C*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 11\n   11 MC 0003\n   14 MR 0003 d1\n   14 MC 0003\n   15 MC 0003\n   16 MC 8c76\n   19 MR 8c76 b9\n   19 MC 8c76\n   20 MC 8c76\n   23 MW 8c76 bd\n5df8 f7bd 9494 4967 0000 0000 0000 0000 ad00 8c65 0000 0004\n00 02 0 0 0 0 23\n8c76 bd -1\n\nfdcbd2  SET 2,(IY+d),D*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 fb\n   11 MC 0003\n   14 MR 0003 d2\n   14 MC 0003\n   15 MC 0003\n   16 MC c04c\n   19 MR c04c 51\n   19 MC c04c\n   20 MC c04c\n   23 MW c04c 55\n9876 4bd9 5548 665a 0000 0000 0000 0000 7eac c051 0000 0004\n00 02 0 0 0 0 23\nc04c 55 -1\n\nfdcbd3  SET 2,(IY+d),E*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 3e\n   11 MC 0003\n   14 MR 0003 d3\n   14 MC 0003\n   15 MC 0003\n   16 MC 0ac5\n   19 MR 0ac5 e0\n   19 MC 0ac5\n   20 MC 0ac5\n   23 MW 0ac5 e4\n8f90 bacd e8e4 538f 0000 0000 0000 0000 fe5a 0a87 0000 0004\n00 02 0 0 0 0 23\n0ac5 e4 -1\n\nfdcbd4  SET 2,(IY+d),H*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 36\n   11 MC 0003\n   14 MR 0003 d4\n   14 MC 0003\n   15 MC 0003\n   16 MC 94ae\n   19 MR 94ae 7d\n   19 MC 94ae\n   20 MC 94ae\n   23 MW 94ae 7d\n15e2 1820 5588 7d7f 0000 0000 0000 0000 7193 9478 0000 0004\n00 02 0 0 0 0 23\n\nfdcbd5  SET 2,(IY+d),L*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 48\n   11 MC 0003\n   14 MR 0003 d5\n   14 MC 0003\n   15 MC 0003\n   16 MC 8650\n   19 MR 8650 98\n   19 MC 8650\n   20 MC 8650\n   23 MW 8650 9c\n1409 6535 c371 ab9c 0000 0000 0000 0000 2e10 8608 0000 0004\n00 02 0 0 0 0 23\n8650 9c -1\n\nfdcbd6  SET 2,(IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 c9\n   11 MC 0003\n   14 MR 0003 d6\n   14 MC 0003\n   15 MC 0003\n   16 MC 6a6c\n   19 MR 6a6c 7c\n   19 MC 6a6c\n   20 MC 6a6c\n   23 MW 6a6c 7c\n7801 78b6 d191 054a 0000 0000 0000 0000 2065 6aa3 0000 0004\n00 02 0 0 0 0 23\n\nfdcbd7  SET 2,(IY+d),A*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 be\n   11 MC 0003\n   14 MR 0003 d7\n   14 MC 0003\n   15 MC 0003\n   16 MC 3669\n   19 MR 3669 95\n   19 MC 3669\n   20 MC 3669\n   23 MW 3669 95\n956a 266e 387f 7fcb 0000 0000 0000 0000 1941 36ab 0000 0004\n00 02 0 0 0 0 23\n\nfdcbd8  SET 3,(IY+d),B*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 bc\n   11 MC 0003\n   14 MR 0003 d8\n   14 MC 0003\n   15 MC 0003\n   16 MC 43b4\n   19 MR 43b4 d8\n   19 MC 43b4\n   20 MC 43b4\n   23 MW 43b4 d8\n7b1b d891 efee 55b9 0000 0000 0000 0000 f789 43f8 0000 0004\n00 02 0 0 0 0 23\n\nfdcbd9  SET 3,(IY+d),C*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 16\n   11 MC 0003\n   14 MR 0003 d9\n   14 MC 0003\n   15 MC 0003\n   16 MC 0a7c\n   19 MR 0a7c f4\n   19 MC 0a7c\n   20 MC 0a7c\n   23 MW 0a7c fc\n0faf 4efc c556 6ed3 0000 0000 0000 0000 3fc3 0a66 0000 0004\n00 02 0 0 0 0 23\n0a7c fc -1\n\nfdcbda  SET 3,(IY+d),D*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 e8\n   11 MC 0003\n   14 MR 0003 da\n   14 MC 0003\n   15 MC 0003\n   16 MC d0d8\n   19 MR d0d8 6b\n   19 MC d0d8\n   20 MC d0d8\n   23 MW d0d8 6b\n9ea1 8186 6b45 d6e0 0000 0000 0000 0000 34d3 d0f0 0000 0004\n00 02 0 0 0 0 23\n\nfdcbdb  SET 3,(IY+d),E*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 7a\n   11 MC 0003\n   14 MR 0003 db\n   14 MC 0003\n   15 MC 0003\n   16 MC 8ca3\n   19 MR 8ca3 15\n   19 MC 8ca3\n   20 MC 8ca3\n   23 MW 8ca3 1d\n5ee0 bdea d01d 513f 0000 0000 0000 0000 690a 8c29 0000 0004\n00 02 0 0 0 0 23\n8ca3 1d -1\n\nfdcbdc  SET 3,(IY+d),H*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 64\n   11 MC 0003\n   14 MR 0003 dc\n   14 MC 0003\n   15 MC 0003\n   16 MC 599e\n   19 MR 599e 15\n   19 MC 599e\n   20 MC 599e\n   23 MW 599e 1d\n5cfa 2e2b 1d17 1df6 0000 0000 0000 0000 a4f2 593a 0000 0004\n00 02 0 0 0 0 23\n599e 1d -1\n\nfdcbdd  SET 3,(IY+d),L*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 75\n   11 MC 0003\n   14 MR 0003 dd\n   14 MC 0003\n   15 MC 0003\n   16 MC 1e09\n   19 MR 1e09 28\n   19 MC 1e09\n   20 MC 1e09\n   23 MW 1e09 28\n8773 70a6 83ce 5228 0000 0000 0000 0000 35da 1d94 0000 0004\n00 02 0 0 0 0 23\n\nfdcbde  SET 3,(IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 17\n   11 MC 0003\n   14 MR 0003 de\n   14 MC 0003\n   15 MC 0003\n   16 MC c9f7\n   19 MR c9f7 41\n   19 MC c9f7\n   20 MC c9f7\n   23 MW c9f7 49\n8310 fa01 6c69 252a 0000 0000 0000 0000 5291 c9e0 0000 0004\n00 02 0 0 0 0 23\nc9f7 49 -1\n\nfdcbdf  SET 3,(IY+d),A*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 93\n   11 MC 0003\n   14 MR 0003 df\n   14 MC 0003\n   15 MC 0003\n   16 MC ea56\n   19 MR ea56 ef\n   19 MC ea56\n   20 MC ea56\n   23 MW ea56 ef\nef0d a722 e78e 50ba 0000 0000 0000 0000 9d67 eac3 0000 0004\n00 02 0 0 0 0 23\n\nfdcbe0  SET 4,(IY+d),B*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 56\n   11 MC 0003\n   14 MR 0003 e0\n   14 MC 0003\n   15 MC 0003\n   16 MC 155d\n   19 MR 155d b9\n   19 MC 155d\n   20 MC 155d\n   23 MW 155d b9\n10ef b901 2ca5 f752 0000 0000 0000 0000 4747 1507 0000 0004\n00 02 0 0 0 0 23\n\nfdcbe1  SET 4,(IY+d),C*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 d1\n   11 MC 0003\n   14 MR 0003 e1\n   14 MC 0003\n   15 MC 0003\n   16 MC 0dde\n   19 MR 0dde 16\n   19 MC 0dde\n   20 MC 0dde\n   23 MW 0dde 16\ne4cb 6f16 1c11 1426 0000 0000 0000 0000 189b 0e0d 0000 0004\n00 02 0 0 0 0 23\n\nfdcbe2  SET 4,(IY+d),D*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 50\n   11 MC 0003\n   14 MR 0003 e2\n   14 MC 0003\n   15 MC 0003\n   16 MC e4ec\n   19 MR e4ec c2\n   19 MC e4ec\n   20 MC e4ec\n   23 MW e4ec d2\n11a9 bae8 d28b bac4 0000 0000 0000 0000 d8ed e49c 0000 0004\n00 02 0 0 0 0 23\ne4ec d2 -1\n\nfdcbe3  SET 4,(IY+d),E*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 ca\n   11 MC 0003\n   14 MR 0003 e3\n   14 MC 0003\n   15 MC 0003\n   16 MC ad72\n   19 MR ad72 ba\n   19 MC ad72\n   20 MC ad72\n   23 MW ad72 ba\n8832 952b 02ba 26ef 0000 0000 0000 0000 fb55 ada8 0000 0004\n00 02 0 0 0 0 23\n\nfdcbe4  SET 4,(IY+d),H*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 62\n   11 MC 0003\n   14 MR 0003 e4\n   14 MC 0003\n   15 MC 0003\n   16 MC 54d6\n   19 MR 54d6 7b\n   19 MC 54d6\n   20 MC 54d6\n   23 MW 54d6 7b\n3989 4142 89e2 7b5b 0000 0000 0000 0000 0bf7 5474 0000 0004\n00 02 0 0 0 0 23\n\nfdcbe5  SET 4,(IY+d),L*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 da\n   11 MC 0003\n   14 MR 0003 e5\n   14 MC 0003\n   15 MC 0003\n   16 MC a507\n   19 MR a507 4c\n   19 MC a507\n   20 MC a507\n   23 MW a507 5c\ne5c5 b86d 41bb 315c 0000 0000 0000 0000 1a78 a52d 0000 0004\n00 02 0 0 0 0 23\na507 5c -1\n\nfdcbe6  SET 4,(IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 76\n   11 MC 0003\n   14 MR 0003 e6\n   14 MC 0003\n   15 MC 0003\n   16 MC 8b7c\n   19 MR 8b7c 45\n   19 MC 8b7c\n   20 MC 8b7c\n   23 MW 8b7c 55\nfd89 d888 1e2f ddf5 0000 0000 0000 0000 42f5 8b06 0000 0004\n00 02 0 0 0 0 23\n8b7c 55 -1\n\nfdcbe7  SET 4,(IY+d),A*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 11\n   11 MC 0003\n   14 MR 0003 e7\n   14 MC 0003\n   15 MC 0003\n   16 MC b5a8\n   19 MR b5a8 a6\n   19 MC b5a8\n   20 MC b5a8\n   23 MW b5a8 b6\nb625 d3e9 d4b6 aa30 0000 0000 0000 0000 88bd b597 0000 0004\n00 02 0 0 0 0 23\nb5a8 b6 -1\n\nfdcbe8  SET 5,(IY+d),B*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 ed\n   11 MC 0003\n   14 MR 0003 e8\n   14 MC 0003\n   15 MC 0003\n   16 MC 0a64\n   19 MR 0a64 d0\n   19 MC 0a64\n   20 MC 0a64\n   23 MW 0a64 f0\n514d f0ab 37b5 57de 0000 0000 0000 0000 a4ec 0a77 0000 0004\n00 02 0 0 0 0 23\n0a64 f0 -1\n\nfdcbe9  SET 5,(IY+d),C*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 35\n   11 MC 0003\n   14 MR 0003 e9\n   14 MC 0003\n   15 MC 0003\n   16 MC a883\n   19 MR a883 2f\n   19 MC a883\n   20 MC a883\n   23 MW a883 2f\n974e d22f d5cb 6bd4 0000 0000 0000 0000 158a a84e 0000 0004\n00 02 0 0 0 0 23\n\nfdcbea  SET 5,(IY+d),D*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 93\n   11 MC 0003\n   14 MR 0003 ea\n   14 MC 0003\n   15 MC 0003\n   16 MC 7526\n   19 MR 7526 1b\n   19 MC 7526\n   20 MC 7526\n   23 MW 7526 3b\n3ef4 3fc6 3b44 e9a4 0000 0000 0000 0000 c877 7593 0000 0004\n00 02 0 0 0 0 23\n7526 3b -1\n\nfdcbeb  SET 5,(IY+d),E*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 d0\n   11 MC 0003\n   14 MR 0003 eb\n   14 MC 0003\n   15 MC 0003\n   16 MC 23e1\n   19 MR 23e1 47\n   19 MC 23e1\n   20 MC 23e1\n   23 MW 23e1 67\n798f 5e9b 9467 2e52 0000 0000 0000 0000 d6ad 2411 0000 0004\n00 02 0 0 0 0 23\n23e1 67 -1\n\nfdcbec  SET 5,(IY+d),H*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 f3\n   11 MC 0003\n   14 MR 0003 ec\n   14 MC 0003\n   15 MC 0003\n   16 MC d2de\n   19 MR d2de 49\n   19 MC d2de\n   20 MC d2de\n   23 MW d2de 69\n38a4 07c0 6cee 6915 0000 0000 0000 0000 f160 d2eb 0000 0004\n00 02 0 0 0 0 23\nd2de 69 -1\n\nfdcbed  SET 5,(IY+d),L*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 58\n   11 MC 0003\n   14 MR 0003 ed\n   14 MC 0003\n   15 MC 0003\n   16 MC 0f03\n   19 MR 0f03 10\n   19 MC 0f03\n   20 MC 0f03\n   23 MW 0f03 30\ne0bc 70c1 de35 8130 0000 0000 0000 0000 d57f 0eab 0000 0004\n00 02 0 0 0 0 23\n0f03 30 -1\n\nfdcbee  SET 5,(IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 02\n   11 MC 0003\n   14 MR 0003 ee\n   14 MC 0003\n   15 MC 0003\n   16 MC 42be\n   19 MR 42be d0\n   19 MC 42be\n   20 MC 42be\n   23 MW 42be f0\n5fcb 9007 1736 aca8 0000 0000 0000 0000 4bab 42bc 0000 0004\n00 02 0 0 0 0 23\n42be f0 -1\n\nfdcbef  SET 5,(IY+d),A*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 58\n   11 MC 0003\n   14 MR 0003 ef\n   14 MC 0003\n   15 MC 0003\n   16 MC 22ca\n   19 MR 22ca 09\n   19 MC 22ca\n   20 MC 22ca\n   23 MW 22ca 29\n29e3 d344 cb5b aeb5 0000 0000 0000 0000 de5f 2272 0000 0004\n00 02 0 0 0 0 23\n22ca 29 -1\n\nfdcbf0  SET 6,(IY+d),B*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 45\n   11 MC 0003\n   14 MR 0003 f0\n   14 MC 0003\n   15 MC 0003\n   16 MC eee3\n   19 MR eee3 2c\n   19 MC eee3\n   20 MC eee3\n   23 MW eee3 6c\n1080 6c70 1b5b a9b7 0000 0000 0000 0000 e89d ee9e 0000 0004\n00 02 0 0 0 0 23\neee3 6c -1\n\nfdcbf1  SET 6,(IY+d),C*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 2f\n   11 MC 0003\n   14 MR 0003 f1\n   14 MC 0003\n   15 MC 0003\n   16 MC 47b2\n   19 MR 47b2 dc\n   19 MC 47b2\n   20 MC 47b2\n   23 MW 47b2 dc\n1702 c4dc d138 316f 0000 0000 0000 0000 8067 4783 0000 0004\n00 02 0 0 0 0 23\n\nfdcbf2  SET 6,(IY+d),D*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 2c\n   11 MC 0003\n   14 MR 0003 f2\n   14 MC 0003\n   15 MC 0003\n   16 MC eac3\n   19 MR eac3 5e\n   19 MC eac3\n   20 MC eac3\n   23 MW eac3 5e\n732a 4cd1 5efe 4814 0000 0000 0000 0000 42f1 ea97 0000 0004\n00 02 0 0 0 0 23\n\nfdcbf3  SET 6,(IY+d),E*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 38\n   11 MC 0003\n   14 MR 0003 f3\n   14 MC 0003\n   15 MC 0003\n   16 MC 7dc8\n   19 MR 7dc8 0c\n   19 MC 7dc8\n   20 MC 7dc8\n   23 MW 7dc8 4c\n6b97 59d3 f54c 7530 0000 0000 0000 0000 6670 7d90 0000 0004\n00 02 0 0 0 0 23\n7dc8 4c -1\n\nfdcbf4  SET 6,(IY+d),H*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 d0\n   11 MC 0003\n   14 MR 0003 f4\n   14 MC 0003\n   15 MC 0003\n   16 MC 306c\n   19 MR 306c 0e\n   19 MC 306c\n   20 MC 306c\n   23 MW 306c 4e\n7af0 a81f 5d3a 4e9b 0000 0000 0000 0000 e12b 309c 0000 0004\n00 02 0 0 0 0 23\n306c 4e -1\n\nfdcbf5  SET 6,(IY+d),L*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 55\n   11 MC 0003\n   14 MR 0003 f5\n   14 MC 0003\n   15 MC 0003\n   16 MC 6b74\n   19 MR 6b74 f8\n   19 MC 6b74\n   20 MC 6b74\n   23 MW 6b74 f8\n1370 f6b2 aaa2 7ff8 0000 0000 0000 0000 c9f6 6b1f 0000 0004\n00 02 0 0 0 0 23\n\nfdcbf6  SET 6,(IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 56\n   11 MC 0003\n   14 MR 0003 f6\n   14 MC 0003\n   15 MC 0003\n   16 MC c670\n   19 MR c670 5d\n   19 MC c670\n   20 MC c670\n   23 MW c670 5d\n7c43 fcd1 34bd f4ab 0000 0000 0000 0000 ef33 c61a 0000 0004\n00 02 0 0 0 0 23\n\nfdcbf7  SET 6,(IY+d),A*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 9e\n   11 MC 0003\n   14 MR 0003 f7\n   14 MC 0003\n   15 MC 0003\n   16 MC 5727\n   19 MR 5727 66\n   19 MC 5727\n   20 MC 5727\n   23 MW 5727 66\n66da 231a 7bb1 800d 0000 0000 0000 0000 e37e 5789 0000 0004\n00 02 0 0 0 0 23\n\nfdcbf8  SET 7,(IY+d),B*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 54\n   11 MC 0003\n   14 MR 0003 f8\n   14 MC 0003\n   15 MC 0003\n   16 MC dece\n   19 MR dece 7a\n   19 MC dece\n   20 MC dece\n   23 MW dece fa\nfa29 fa74 d7c4 afaf 0000 0000 0000 0000 512c de7a 0000 0004\n00 02 0 0 0 0 23\ndece fa -1\n\nfdcbf9  SET 7,(IY+d),C*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 30\n   11 MC 0003\n   14 MR 0003 f9\n   14 MC 0003\n   15 MC 0003\n   16 MC 9a13\n   19 MR 9a13 c6\n   19 MC 9a13\n   20 MC 9a13\n   23 MW 9a13 c6\n4662 a7c6 5065 ed06 0000 0000 0000 0000 279e 99e3 0000 0004\n00 02 0 0 0 0 23\n\nfdcbfa  SET 7,(IY+d),D*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 09\n   11 MC 0003\n   14 MR 0003 fa\n   14 MC 0003\n   15 MC 0003\n   16 MC bd82\n   19 MR bd82 f4\n   19 MC bd82\n   20 MC bd82\n   23 MW bd82 f4\n9426 53ec f416 6c99 0000 0000 0000 0000 8b99 bd79 0000 0004\n00 02 0 0 0 0 23\n\nfdcbfb  SET 7,(IY+d),E*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 ba\n   11 MC 0003\n   14 MR 0003 fb\n   14 MC 0003\n   15 MC 0003\n   16 MC f82f\n   19 MR f82f ed\n   19 MC f82f\n   20 MC f82f\n   23 MW f82f ed\n5343 b212 09ed e3c6 0000 0000 0000 0000 cd2b f875 0000 0004\n00 02 0 0 0 0 23\n\nfdcbfc  SET 7,(IY+d),H*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 56\n   11 MC 0003\n   14 MR 0003 fc\n   14 MC 0003\n   15 MC 0003\n   16 MC 6679\n   19 MR 6679 65\n   19 MC 6679\n   20 MC 6679\n   23 MW 6679 e5\n0965 4392 ca25 e5aa 0000 0000 0000 0000 f023 6623 0000 0004\n00 02 0 0 0 0 23\n6679 e5 -1\n\nfdcbfd  SET 7,(IY+d),L*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 25\n   11 MC 0003\n   14 MR 0003 fd\n   14 MC 0003\n   15 MC 0003\n   16 MC 5d50\n   19 MR 5d50 27\n   19 MC 5d50\n   20 MC 5d50\n   23 MW 5d50 a7\n1751 233c 6214 d1a7 0000 0000 0000 0000 c415 5d2b 0000 0004\n00 02 0 0 0 0 23\n5d50 a7 -1\n\nfdcbfe  SET 7,(IY+d)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 88\n   11 MC 0003\n   14 MR 0003 fe\n   14 MC 0003\n   15 MC 0003\n   16 MC 4dd7\n   19 MR 4dd7 4a\n   19 MC 4dd7\n   20 MC 4dd7\n   23 MW 4dd7 ca\nb4cf 5639 677b 0ca2 0000 0000 0000 0000 ddc5 4e4f 0000 0004\n00 02 0 0 0 0 23\n4dd7 ca -1\n\nfdcbff  SET 7,(IY+d),A*\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 cb\n    8 MC 0002\n   11 MR 0002 e4\n   11 MC 0003\n   14 MR 0003 ff\n   14 MC 0003\n   15 MC 0003\n   16 MC 2ad1\n   19 MR 2ad1 97\n   19 MC 2ad1\n   20 MC 2ad1\n   23 MW 2ad1 97\n9751 13da 7c56 f025 0000 0000 0000 0000 2b36 2aed 0000 0004\n00 02 0 0 0 0 23\n\nfde1    POP IY\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 e1\n    8 MC 716e\n   11 MR 716e d5\n   11 MC 716f\n   14 MR 716f 92\n828e 078b 1e35 8f1c 0000 0000 0000 0000 4827 92d5 7170 0002\n00 02 0 0 0 0 14\n\nfde3    EX (SP),IY\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 e3\n    8 MC 1a38\n   11 MR 1a38 e0\n   11 MC 1a39\n   14 MR 1a39 0f\n   14 MC 1a39\n   15 MC 1a39\n   18 MW 1a39 95\n   18 MC 1a38\n   21 MW 1a38 10\n   21 MC 1a38\n   22 MC 1a38\n4298 c805 6030 4292 0000 0000 0000 0000 473b 0fe0 1a38 0002\n00 02 0 0 0 0 23\n1a38 10 95 -1\n\nfde5    PUSH IY\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 e5\n    8 MC 0002\n    9 MC a8e0\n   12 MW a8e0 d4\n   12 MC a8df\n   15 MW a8df da\nd139 aa0d bf2b 2a56 0000 0000 0000 0000 e138 d4da a8df 0002\n00 02 0 0 0 0 15\na8df da d4 -1\n\nfde9    JP (IY)\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 e9\nc14f 2eb6 edf0 27cf 0000 0000 0000 0000 09ee a2a4 0000 a2a4\n00 02 0 0 0 0 8\n\nfdf9    LD SP,IY\n    0 MC 0000\n    4 MR 0000 fd\n    4 MC 0001\n    8 MR 0001 f9\n    8 MC 0002\n    9 MC 0002\nc260 992e d544 67fb 0000 0000 0000 0000 ba5e 3596 3596 0002\n00 02 0 0 0 0 10\n\nfe      CP n\n    0 MC 0000\n    4 MR 0000 fe\n    4 MC 0001\n    7 MR 0001 82\n6987 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0002\n00 01 0 0 0 0 7\n\nff      RST 38H\n    0 MC 6d33\n    4 MR 6d33 ff\n    4 MC 0001\n    5 MC 5506\n    8 MW 5506 6d\n    8 MC 5505\n   11 MW 5505 34\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 5505 0038\n00 01 0 0 0 0 11\n5505 34 6d -1\n\n"
  },
  {
    "path": "cpu/toplevel/fuse/tests.in",
    "content": "00      NOP\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 00 -1\n-1\n\n01      LD BC,nn\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 01 12 34 -1\n-1\n\n02      LD (BC),A\n5600 0001 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 02 -1\n-1\n\n03      INC BC\n0000 789a 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 03 -1\n-1\n\n04      INC B\n0000 ff00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 04 -1\n-1\n\n05      DEC B\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 05 -1\n-1\n\n06      LD B,n\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 06 bc -1\n-1\n\n07      RLCA\n8800 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 07 -1\n-1\n\n08      EX AF,AF'\ndef0 0000 0000 0000 1234 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 08 -1\n-1\n\n09      ADD HL,BC\n0000 5678 0000 9abc 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 09 -1\n-1\n\n0a      LD A,(BC)\n0000 0001 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 0a de -1\n-1\n\n0b      DEC BC\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 0b -1\n-1\n\n0c      INC C\n0000 007f 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 0c -1\n-1\n\n0d      DEC C\n0000 0080 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 0d -1\n-1\n\n0e      LD C,n\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 0e f0 -1\n-1\n\n0f      RRCA\n4100 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 0f -1\n-1\n\n10      DJNZ (PC+e)\n0000 0800 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0   132\n0000 00 10 fd 0c -1\n-1\n\n11      LD DE,nn\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 11 9a bc -1\n-1\n\n12      LD (DE),A\n5600 0000 8000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 12 -1\n-1\n\n13      INC DE\n0000 0000 def0 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 13 -1\n-1\n\n14      INC D\n0000 0000 2700 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 14 -1\n-1\n\n15      DEC D\n0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 15 -1\n-1\n\n16      LD D,n\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 16 12 -1\n-1\n\n17      RLA\n0801 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 17 -1\n-1\n\n18      JR e\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 18 40 -1\n-1\n\n19      ADD HL,DE\n0000 0000 3456 789a 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 19 -1\n-1\n\n1a      LD A,(DE)\n0000 0000 8000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 1a -1\n8000 13 -1\n-1\n\n1b      DEC DE\n0000 0000 e5d4 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 1b -1\n-1\n\n1c      INC E\n0000 0000 00aa 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 1c -1\n-1\n\n1d      DEC E\n0000 0000 00aa 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 1d -1\n-1\n\n1e      LD E,n\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 1e ef -1\n-1\n\n1f      RRA\n01c4 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 1f -1\n-1\n\n20_1    JR NZ,e\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 20 40 -1\n-1\n\n20_2    JR NZ,e\n0040 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 20 40 -1\n-1\n\n21      LD HL,nn\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 21 28 ed -1\n-1\n\n22      LD (nn),HL\n0000 0000 0000 c64c 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 22 b0 c3 -1\n-1\n\n23      INC HL\n0000 0000 0000 9c4e 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 23 -1\n-1\n\n24      INC H\n0000 0000 0000 7200 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 24 -1\n-1\n\n25      DEC H\n0000 0000 0000 a500 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 25 -1\n-1\n\n26      LD H,n\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 26 3a -1\n-1\n\n27_1    DAA\n9a02 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 27 -1\n-1\n\n27      DAA\n1f00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 27 -1\n-1\n\n28_1    JR Z,e\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 28 8e -1\n-1\n\n28_2    JR Z,e\n0040 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 28 8e -1\n-1\n\n29      ADD HL,HL\n0000 0000 0000 cdfa 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 29 -1\n-1\n\n2a      LD HL,(nn)\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 2a 45 ac -1\nac45 c4 de -1\n-1\n\n2b      DEC HL\n0000 0000 0000 9e66 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 2b -1\n-1\n\n2c      INC L\n0000 0000 0000 0026 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 2c -1\n-1\n\n2d      DEC L\n0000 0000 0000 0032 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 2d -1\n-1\n\n2e      LD L,n\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 2e 18 -1\n-1\n\n2f      CPL\n8900 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 2f -1\n-1\n\n30_1    JR NC,e\n0036 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 30 50 -1\n-1\n\n30_2    JR NC,e\n0037 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 30 50 -1\n-1\n\n31      LD SP,nn\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 31 d4 61 -1\n-1\n\n32      LD (nn),A\n0e00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 32 ac ad -1\n-1\n\n33      INC SP\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 a55a 0000\n00 00 0 0 0 0     1\n0000 33 -1\n-1\n\n34      INC (HL)\n0000 0000 0000 fe1d 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 34 -1\nfe1d fd -1\n-1\n\n35      DEC (HL)\n0000 0000 0000 470c 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 35 -1\n470c 82 -1\n-1\n\n36      LD (HL),n\n0000 0000 0000 7d29 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 36 7c -1\n-1\n\n37_1    SCF\n00ff 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 37 -1\n-1\n\n37_2    SCF\nff00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 37 -1\n-1\n\n37_3    SCF\nffff 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 37 -1\n-1\n\n37      SCF\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 37 -1\n-1\n\n38_1    JR C,e\n00b2 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 38 66 -1\n-1\n\n38_2    JR C,e\n00b3 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 38 66 -1\n-1\n\n39      ADD HL,SP\n0000 0000 0000 1aef 0000 0000 0000 0000 0000 0000 c534 0000\n00 00 0 0 0 0     1\n0000 29 -1\n-1\n\n3a      LD A,(nn)\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 3a 52 99 -1\n9952 28 -1\n-1\n\n3b      DEC SP\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 9d36 0000\n00 00 0 0 0 0     1\n0000 3b -1\n-1\n\n3c      INC A\ncf00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 3c -1\n-1\n\n3d      DEC A\nea00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 3d -1\n-1\n\n3e      LD A,n\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 3e d6 -1\n-1\n\n3f      CCF\n005b 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 3f -1\n-1\n\n3f_1    CCF\n005A 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 3f -1\n-1\n\n40      LD B,B\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 40 -1\na169 50 -1\n-1\n\n41      LD B,C\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 41 -1\na169 50 -1\n-1\n\n42      LD B,D\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 42 -1\na169 50 -1\n-1\n\n43      LD B,E\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 43 -1\na169 50 -1\n-1\n\n44      LD B,H\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 44 -1\na169 50 -1\n-1\n\n45      LD B,L\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 45 -1\na169 50 -1\n-1\n\n46      LD B,(HL)\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 46 -1\na169 50 -1\n-1\n\n47      LD B,A\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 47 -1\na169 50 -1\n-1\n\n48      LD C,B\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 48 -1\na169 50 -1\n-1\n\n49      LD C,C\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 49 -1\na169 50 -1\n-1\n\n4a      LD C,D\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 4a -1\na169 50 -1\n-1\n\n4b      LD C,E\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 4b -1\na169 50 -1\n-1\n\n4c      LD C,H\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 4c -1\na169 50 -1\n-1\n\n4d      LD C,L\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 4d -1\na169 50 -1\n-1\n\n4e      LD C,(HL)\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 4e -1\na169 50 -1\n-1\n\n4f      LD C,A\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 4f -1\na169 50 -1\n-1\n\n50      LD D,B\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 50 -1\na169 50 -1\n-1\n\n51      LD D,C\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 51 -1\na169 50 -1\n-1\n\n52      LD D,D\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 52 -1\na169 50 -1\n-1\n\n53      LD D,E\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 53 -1\na169 50 -1\n-1\n\n54      LD D,H\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 54 -1\na169 50 -1\n-1\n\n55      LD D,L\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 55 -1\na169 50 -1\n-1\n\n56      LD D,(HL)\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 56 -1\na169 50 -1\n-1\n\n57      LD D,A\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 57 -1\na169 50 -1\n-1\n\n58      LD E,B\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 58 -1\na169 50 -1\n-1\n\n59      LD E,C\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 59 -1\na169 50 -1\n-1\n\n5a      LD E,D\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 5a -1\na169 50 -1\n-1\n\n5b      LD E,E\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 5b -1\na169 50 -1\n-1\n\n5c      LD E,H\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 5c -1\na169 50 -1\n-1\n\n5d      LD E,L\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 5d -1\na169 50 -1\n-1\n\n5e      LD E,(HL)\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 5e -1\na169 50 -1\n-1\n\n5f      LD E,A\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 5f -1\na169 50 -1\n-1\n\n60      LD H,B\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 60 -1\na169 50 -1\n-1\n\n61      LD H,C\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 61 -1\na169 50 -1\n-1\n\n62      LD H,D\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 62 -1\na169 50 -1\n-1\n\n63      LD H,E\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 63 -1\na169 50 -1\n-1\n\n64      LD H,H\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 64 -1\na169 50 -1\n-1\n\n65      LD H,L\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 65 -1\na169 50 -1\n-1\n\n66      LD H,(HL)\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 66 -1\na169 50 -1\n-1\n\n67      LD H,A\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 67 -1\na169 50 -1\n-1\n\n68      LD L,B\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 68 -1\na169 50 -1\n-1\n\n69      LD L,C\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 69 -1\na169 50 -1\n-1\n\n6a      LD L,D\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 6a -1\na169 50 -1\n-1\n\n6b      LD L,E\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 6b -1\na169 50 -1\n-1\n\n6c      LD L,H\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 6c -1\na169 50 -1\n-1\n\n6d      LD L,L\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 6d -1\na169 50 -1\n-1\n\n6e      LD L,(HL)\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 6e -1\na169 50 -1\n-1\n\n6f      LD L,A\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 6f -1\na169 50 -1\n-1\n\n70      LD (HL),B\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 70 -1\na169 50 -1\n-1\n\n71      LD (HL),C\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 71 -1\na169 50 -1\n-1\n\n72      LD (HL),D\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 72 -1\na169 50 -1\n-1\n\n73      LD (HL),E\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 73 -1\na169 50 -1\n-1\n\n74      LD (HL),H\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 74 -1\na169 50 -1\n-1\n\n75      LD (HL),L\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 75 -1\na169 50 -1\n-1\n\n76      HALT\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 76 -1\na169 50 -1\n-1\n\n77      LD (HL),A\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 77 -1\na169 50 -1\n-1\n\n78      LD A,B\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 78 -1\na169 50 -1\n-1\n\n79      LD A,C\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 79 -1\na169 50 -1\n-1\n\n7a      LD A,D\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 7a -1\na169 50 -1\n-1\n\n7b      LD A,E\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 7b -1\na169 50 -1\n-1\n\n7c      LD A,H\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 7c -1\na169 50 -1\n-1\n\n7d      LD A,L\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 7d -1\na169 50 -1\n-1\n\n7e      LD A,(HL)\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 7e -1\na169 50 -1\n-1\n\n7f      LD A,A\n0200 cf98 90d8 a169 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 7f -1\na169 50 -1\n-1\n\n80      ADD A,B\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 80 -1\ndca6 49 -1\n-1\n\n81      ADD A,C\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 81 -1\ndca6 49 -1\n-1\n\n82      ADD A,D\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 82 -1\ndca6 49 -1\n-1\n\n83      ADD A,E\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 83 -1\ndca6 49 -1\n-1\n\n84      ADD A,H\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 84 -1\ndca6 49 -1\n-1\n\n85      ADD A,L\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 85 -1\ndca6 49 -1\n-1\n\n86      ADD A,(HL)\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 86 -1\ndca6 49 -1\n-1\n\n87      ADD A,A\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 87 -1\ndca6 49 -1\n-1\n\n88      ADC A,B\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 88 -1\ndca6 49 -1\n-1\n\n89      ADC A,C\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 89 -1\ndca6 49 -1\n-1\n\n8a      ADC A,D\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 8a -1\ndca6 49 -1\n-1\n\n8b      ADC A,E\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 8b -1\ndca6 49 -1\n-1\n\n8c      ADC A,H\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 8c -1\ndca6 49 -1\n-1\n\n8d      ADC A,L\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 8d -1\ndca6 49 -1\n-1\n\n8e      ADC A,(HL)\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 8e -1\ndca6 49 -1\n-1\n\n8f      ADC A,A\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 8f -1\ndca6 49 -1\n-1\n\n90      SUB B\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 90 -1\ndca6 49 -1\n-1\n\n91      SUB C\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 91 -1\ndca6 49 -1\n-1\n\n92      SUB D\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 92 -1\ndca6 49 -1\n-1\n\n93      SUB E\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 93 -1\ndca6 49 -1\n-1\n\n94      SUB H\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 94 -1\ndca6 49 -1\n-1\n\n95      SUB L\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 95 -1\ndca6 49 -1\n-1\n\n96      SUB (HL)\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 96 -1\ndca6 49 -1\n-1\n\n97      SUB A\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 97 -1\ndca6 49 -1\n-1\n\n98      SBC A,B\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 98 -1\ndca6 49 -1\n-1\n\n99      SBC A,C\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 99 -1\ndca6 49 -1\n-1\n\n9a      SBC A,D\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 9a -1\ndca6 49 -1\n-1\n\n9b      SBC A,E\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 9b -1\ndca6 49 -1\n-1\n\n9c      SBC A,H\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 9c -1\ndca6 49 -1\n-1\n\n9d      SBC A,L\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 9d -1\ndca6 49 -1\n-1\n\n9e      SBC A,(HL)\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 9e -1\ndca6 49 -1\n-1\n\n9f      SBC A,A\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 9f -1\ndca6 49 -1\n-1\n\na0      AND B\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 a0 -1\ndca6 49 -1\n-1\n\na1      AND C\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 a1 -1\ndca6 49 -1\n-1\n\na2      AND D\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 a2 -1\ndca6 49 -1\n-1\n\na3      AND E\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 a3 -1\ndca6 49 -1\n-1\n\na4      AND H\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 a4 -1\ndca6 49 -1\n-1\n\na5      AND L\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 a5 -1\ndca6 49 -1\n-1\n\na6      AND (HL)\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 a6 -1\ndca6 49 -1\n-1\n\na7      AND A\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 a7 -1\ndca6 49 -1\n-1\n\na8      XOR B\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 a8 -1\ndca6 49 -1\n-1\n\na9      XOR C\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 a9 -1\ndca6 49 -1\n-1\n\naa      XOR D\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 aa -1\ndca6 49 -1\n-1\n\nab      XOR E\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ab -1\ndca6 49 -1\n-1\n\nac      XOR H\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ac -1\ndca6 49 -1\n-1\n\nad      XOR L\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ad -1\ndca6 49 -1\n-1\n\nae      XOR (HL)\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ae -1\ndca6 49 -1\n-1\n\naf      XOR A\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 af -1\ndca6 49 -1\n-1\n\nb0      OR B\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 b0 -1\ndca6 49 -1\n-1\n\nb1      OR C\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 b1 -1\ndca6 49 -1\n-1\n\nb2      OR D\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 b2 -1\ndca6 49 -1\n-1\n\nb3      OR E\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 b3 -1\ndca6 49 -1\n-1\n\nb4      OR H\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 b4 -1\ndca6 49 -1\n-1\n\nb5      OR L\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 b5 -1\ndca6 49 -1\n-1\n\nb6      OR (HL)\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 b6 -1\ndca6 49 -1\n-1\n\nb7      OR A\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 b7 -1\ndca6 49 -1\n-1\n\nb8      CP B\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 b8 -1\ndca6 49 -1\n-1\n\nb9      CP C\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 b9 -1\ndca6 49 -1\n-1\n\nba      CP D\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ba -1\ndca6 49 -1\n-1\n\nbb      CP E\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 bb -1\ndca6 49 -1\n-1\n\nbc      CP H\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 bc -1\ndca6 49 -1\n-1\n\nbd      CP L\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 bd -1\ndca6 49 -1\n-1\n\nbe      CP (HL)\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 be -1\ndca6 49 -1\n-1\n\nbf      CP A\nf500 0f3b 200d dca6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 bf -1\ndca6 49 -1\n-1\n\nc0_1    RET NZ\n0098 0000 0000 0000 0000 0000 0000 0000 0000 0000 43f7 0000\n00 00 0 0 0 0     1\n0000 c0 -1\n43f7 e9 af -1\n-1\n\nc0_2    RET NZ\n00d8 0000 0000 0000 0000 0000 0000 0000 0000 0000 43f7 0000\n00 00 0 0 0 0     1\n0000 c0 -1\n43f7 e9 af -1\n-1\n\nc1      POP BC\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4143 0000\n00 00 0 0 0 0     1\n0000 c1 -1\n4143 ce e8 -1\n-1\n\nc2_1    JP NZ,nn\n0087 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 c2 1b e1 -1\n-1\n\nc2_2    JP NZ,nn\n00c7 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 c2 1b e1 -1\n-1\n\nc3      JP nn\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 c3 ed 7c -1\n-1\n\nc4_1    CALL NZ,nn\n000e 0000 0000 0000 0000 0000 0000 0000 0000 0000 5698 0000\n00 00 0 0 0 0     1\n0000 c4 61 9c -1\n-1\n\nc4_2    CALL NZ,nn\n004e 0000 0000 0000 0000 0000 0000 0000 0000 0000 5698 0000\n00 00 0 0 0 0     1\n0000 c4 61 9c -1\n-1\n\nc5      PUSH BC\n53e3 1459 775f 1a2f 0000 0000 0000 0000 0000 0000 ec12 0000\n00 00 0 0 0 0     1\n0000 c5 -1\n-1\n\nc6      ADD A,n\nca00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 c6 6f -1\n-1\n\nc7      RST 0H\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 5507 6d33\n00 00 0 0 0 0     1\n6d33 c7 -1\n-1\n\nc8_1    RET Z\n0098 0000 0000 0000 0000 0000 0000 0000 0000 0000 43f7 0000\n00 00 0 0 0 0     1\n0000 c8 -1\n43f7 e9 af -1\n-1\n\nc8_2    RET Z\n00d8 0000 0000 0000 0000 0000 0000 0000 0000 0000 43f7 0000\n00 00 0 0 0 0     1\n0000 c8 -1\n43f7 e9 af -1\n-1\n\nc9      RET\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 887e 0000\n00 00 0 0 0 0     1\n0000 c9 -1\n887e 36 11 -1\n-1\n\nca_1    JP Z,nn\n0087 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ca 1b e1 -1\n-1\n\nca_2    JP Z,nn\n00c7 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ca 1b e1 -1\n-1\n\ncb00    RLC B\nda00 e479 552e a806 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 00 -1\na806 76 -1\n-1\n\ncb01    RLC C\n1000 b379 b480 ef65 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 01 -1\nef65 fb -1\n-1\n\ncb02    RLC D\n2e00 9adf ae6e a7f2 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 02 -1\na7f2 4a -1\n-1\n\ncb03    RLC E\n6800 9995 de3f ca71 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 03 -1\nca71 e7 -1\n-1\n\ncb04    RLC H\n8c00 beea 0ce4 67b0 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 04 -1\n67b0 cd -1\n-1\n\ncb05    RLC L\n3600 e19f 78c9 cb32 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 05 -1\ncb32 1b -1\n-1\n\ncb06    RLC (HL)\n8a00 db02 8fb1 5b04 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 06 -1\n5b04 d4 -1\n-1\n\ncb07    RLC A\n6d00 19cf 7259 dcaa 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 07 -1\ndcaa 8d -1\n-1\n\ncb08    RRC B\n8000 cdb5 818e 2ee2 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 08 -1\n2ee2 53 -1\n-1\n\ncb09    RRC C\n1800 125c dd97 59c6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 09 -1\n59c6 9e -1\n-1\n\ncb0a    RRC D\n1200 3ba1 7724 63ad 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 0a -1\n63ad 96 -1\n-1\n\ncb0b    RRC E\n7600 2abf b626 0289 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 0b -1\n0289 37 -1\n-1\n\ncb0c    RRC H\n0e00 6fc5 2f12 34d9 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 0c -1\n34d9 50 -1\n-1\n\ncb0d    RRC L\n6300 95a3 fcd2 519a 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 0d -1\n519a 7a -1\n-1\n\ncb0e    RRC (HL)\nfc00 adf9 4925 543e 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 0e -1\n543e d2 -1\n-1\n\ncb0f    RRC A\nc300 18f3 41b8 070b 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 0f -1\n070b 86 -1\n-1\n\ncb10    RL B\nf800 dc25 33b3 0d74 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 10 -1\n0d74 3d -1\n-1\n\ncb11    RL C\n6500 e25c 4b8a ed42 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 11 -1\ned42 b7 -1\n-1\n\ncb12    RL D\n7700 1384 0f50 29c6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 12 -1\n29c6 88 -1\n-1\n\ncb13    RL E\nce00 9f17 e128 3ed7 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 13 -1\n3ed7 ea -1\n-1\n\ncb14    RL H\nb200 541a 60c7 7c9a 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 14 -1\n7c9a 0f -1\n-1\n\ncb15    RL L\n2d00 c1df 6eab 03e2 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 15 -1\n03e2 bc -1\n-1\n\ncb16    RL (HL)\n3600 3b53 1a4a 684e 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 16 -1\n684e c3 -1\n-1\n\ncb17    RL A\n5400 d090 f60d 0fa2 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 17 -1\n0fa2 23 -1\n-1\n\ncb18    RR B\n8600 c658 755f 9596 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 18 -1\n9596 b6 -1\n-1\n\ncb19    RR C\n9600 beb3 7c22 71c8 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 19 -1\n71c8 85 -1\n-1\n\ncb1a    RR D\n3900 882f 543b 5279 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 1a -1\n5279 26 -1\n-1\n\ncb1b    RR E\n9e00 b338 876c e8b4 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 1b -1\ne8b4 b9 -1\n-1\n\ncb1c    RR H\n4b00 b555 238f 311d 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 1c -1\n311d 11 -1\n-1\n\ncb1d    RR L\n2100 3d7e 5e39 e451 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 1d -1\ne451 47 -1\n-1\n\ncb1e    RR (HL)\n5e00 66b9 80dc 00ef 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 1e -1\n00ef 91 -1\n-1\n\ncb1f    RR A\ned00 b838 8e18 ace7 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 1f -1\nace7 82 -1\n-1\n\ncb20    SLA B\nc700 0497 d72b ccb6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 20 -1\nccb6 1a -1\n-1\n\ncb21    SLA C\n2200 5cf4 938e 37a8 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 21 -1\n37a8 dd -1\n-1\n\ncb22    SLA D\n8500 0950 e7e8 0641 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 22 -1\n0641 4d -1\n-1\n\ncb23    SLA E\n2100 2a7c 37d0 aa59 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 23 -1\naa59 c1 -1\n-1\n\ncb24    SLA H\nfb00 b9de 7014 84b6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 24 -1\n84b6 80 -1\n-1\n\ncb25    SLA L\n1500 6bbc 894e 85bc 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 25 -1\n85bc ef -1\n-1\n\ncb26    SLA (HL)\n0a00 372e e315 283a 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 26 -1\n283a ee -1\n-1\n\ncb27    SLA A\nbf00 bdba 67ab 5ea2 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 27 -1\n5ea2 bd -1\n-1\n\ncb28    SRA B\nc000 0435 3e0f 021b 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 28 -1\n021b 90 -1\n-1\n\ncb29    SRA C\n0600 f142 6ada c306 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 29 -1\nc306 5c -1\n-1\n\ncb2a    SRA D\n3000 ec3a 7f7d 3473 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 2a -1\n3473 34 -1\n-1\n\ncb2b    SRA E\ne000 ccf0 bbda b78a 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 2b -1\nb78a ab -1\n-1\n\ncb2c    SRA H\n5b00 25c0 996d 1e7b 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 2c -1\n1e7b 2c -1\n-1\n\ncb2d    SRA L\n5e00 c51b 58e3 78ea 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 2d -1\n78ea 85 -1\n-1\n\ncb2e    SRA (HL)\n3900 a2cd 0629 24bf 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 2e -1\n24bf b5 -1\n-1\n\ncb2f    SRA A\naa00 a194 d0e3 5c65 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 2f -1\n5c65 c9 -1\n-1\n\ncb30    SLL B*\ncd00 7a81 d67b 656b 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 30 -1\n656b 32 -1\n-1\n\ncb31    SLL C*\n2800 e7fa 6d8c 75a4 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 31 -1\n75a4 0c -1\n-1\n\ncb32    SLL D*\n1300 3f36 f608 5e56 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 32 -1\n5e56 8d -1\n-1\n\ncb33    SLL E*\nd500 9720 7644 038f 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 33 -1\n038f ba -1\n-1\n\ncb34    SLL H*\n1200 77f6 0206 fb38 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 34 -1\nfb38 07 -1\n-1\n\ncb35    SLL L*\n3c00 fd68 ea91 7861 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 35 -1\n7861 72 -1\n-1\n\ncb36    SLL (HL)*\n8a00 1185 1dde 6d38 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 36 -1\n6d38 f1 -1\n-1\n\ncb37    SLL A*\n4300 d7bc 9133 6e56 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 37 -1\n6e56 f8 -1\n-1\n\ncb38    SRL B\ndf00 7c1b 9f9f 4ff2 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 38 -1\n4ff2 aa -1\n-1\n\ncb39    SRL C\n6600 b702 14f5 3c17 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 39 -1\n3c17 61 -1\n-1\n\ncb3a    SRL D\nd100 5c5f e42e f1b1 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 3a -1\nf1b1 6e -1\n-1\n\ncb3b    SRL E\nb200 38c8 a560 7419 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 3b -1\n7419 11 -1\n-1\n\ncb3c    SRL H\n7800 cfae 66d8 2ad8 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 3c -1\n2ad8 8d -1\n-1\n\ncb3d    SRL L\ne600 dcda 06aa 46cd 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 3d -1\n46cd f9 -1\n-1\n\ncb3e    SRL (HL)\na900 6a34 e8d0 a96c 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 3e -1\na96c a0 -1\n-1\n\ncb3f    SRL A\nf100 ceea 721e 77f0 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 3f -1\n77f0 7c -1\n-1\n\ncb40    BIT 0,B\n9e00 bcb2 efaa 505f 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 40 -1\n505f 59 -1\n-1\n\ncb41    BIT 0,C\n9e00 1b43 954e 7be9 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 41 -1\n7be9 f7 -1\n-1\n\ncb42    BIT 0,D\nf200 dd12 7d4f 551f 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 42 -1\n551f c9 -1\n-1\n\ncb43    BIT 0,E\nad00 c3b3 f1d0 bab4 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 43 -1\nbab4 76 -1\n-1\n\ncb44    BIT 0,H\nb700 c829 27e3 5b92 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 44 -1\n5b92 78 -1\n-1\n\ncb45    BIT 0,L\n7700 68ee 0c77 409b 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 45 -1\n409b 64 -1\n-1\n\ncb46    BIT 0,(HL)\n7200 7ae3 a11e 6131 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 46 -1\n6131 d5 -1\n-1\n\ncb47_1  BIT 0,A\nff00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 47 -1\n-1\n\ncb47    BIT 0,A\n1000 d8ca e2c4 8a8c 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 47 -1\n8a8c 0e -1\n-1\n\ncb48    BIT 1,B\na900 6264 e833 6de0 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 48 -1\n6de0 8c -1\n-1\n\ncb49    BIT 1,C\n6c00 d0f7 1db7 a040 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 49 -1\na040 5f -1\n-1\n\ncb4a    BIT 1,D\n4f00 f04c 5b29 77a4 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 4a -1\n77a4 96 -1\n-1\n\ncb4b    BIT 1,E\n5500 9848 095f 40ca 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 4b -1\n40ca 8a -1\n-1\n\ncb4c    BIT 1,H\n8800 0521 bf31 6d5d 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 4c -1\n6d5d e7 -1\n-1\n\ncb4d    BIT 1,L\nf900 27d0 0f7e 158d 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 4d -1\n158d e0 -1\n-1\n\ncb4e    BIT 1,(HL)\n2600 9207 459a ada3 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 4e -1\nada3 5b -1\n-1\n\ncb4f_1  BIT 1,A\nff00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 4f -1\n-1\n\ncb4f    BIT 1,A\n1700 2dc1 aca2 0bcc 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 4f -1\n0bcc a3 -1\n-1\n\ncb50    BIT 2,B\n2300 2749 1012 84d2 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 50 -1\n84d2 6a -1\n-1\n\ncb51    BIT 2,C\n2200 b7db e19d aafc 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 51 -1\naafc a6 -1\n-1\n\ncb52    BIT 2,D\n8b00 ff7a b0ff ac44 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 52 -1\nac44 00 -1\n-1\n\ncb53    BIT 2,E\n6000 31a1 a4f4 7c75 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 53 -1\n7c75 ab -1\n-1\n\ncb54    BIT 2,H\n3800 7ccc 89cc 1999 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 54 -1\n1999 98 -1\n-1\n\ncb55    BIT 2,L\nf900 1f79 19cd fb4b 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 55 -1\nfb4b 0b -1\n-1\n\ncb56    BIT 2,(HL)\n1500 2bfe e3b5 bbf9 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 56 -1\nbbf9 10 -1\n-1\n\ncb57_1  BIT 2,A\nff00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 57 -1\n-1\n\ncb57    BIT 2,A\n6600 af32 532a da50 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 57 -1\nda50 30 -1\n-1\n\ncb58    BIT 3,B\n5000 1aee 2e47 1479 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 58 -1\n1479 a0 -1\n-1\n\ncb59    BIT 3,C\n7200 5e68 ff28 2075 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 59 -1\n2075 c1 -1\n-1\n\ncb5a    BIT 3,D\neb00 fea7 17d1 d99b 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 5a -1\nd99b e8 -1\n-1\n\ncb5b    BIT 3,E\n6b00 6f2c 3fe3 1691 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 5b -1\n1691 c7 -1\n-1\n\ncb5c    BIT 3,H\n3300 a7e7 2077 13e9 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 5c -1\n13e9 ae -1\n-1\n\ncb5d    BIT 3,L\nc100 afcc c8b1 ee49 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 5d -1\nee49 a6 -1\n-1\n\ncb5e    BIT 3,(HL)\n3000 ad43 16c1 349a 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 5e -1\n349a 3c -1\n-1\n\ncb5f_1  BIT 3,A\nff00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 5f -1\n-1\n\ncb5f    BIT 3,A\n8c00 1b67 2314 6133 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 5f -1\n6133 90 -1\n-1\n\ncb60    BIT 4,B\n9900 34b5 0fd8 5273 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 60 -1\n5273 0a -1\n-1\n\ncb61    BIT 4,C\nd100 219f 3bb4 7c44 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 61 -1\n7c44 77 -1\n-1\n\ncb62    BIT 4,D\naf00 bdf8 c536 8cc5 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 62 -1\n8cc5 af -1\n-1\n\ncb63    BIT 4,E\n2a00 5e16 f627 84ca 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 63 -1\n84ca e6 -1\n-1\n\ncb64    BIT 4,H\na900 a365 c00b ea94 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 64 -1\nea94 0c -1\n-1\n\ncb65    BIT 4,L\n1800 8d58 4256 427a 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 65 -1\n427a ee -1\n-1\n\ncb66    BIT 4,(HL)\n4c00 3ef7 e544 a44f 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 66 -1\na44f d2 -1\n-1\n\ncb67_1  BIT 4,A\nff00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 67 -1\n-1\n\ncb67    BIT 4,A\n8600 5e92 2986 394d 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 67 -1\n394d 10 -1\n-1\n\ncb68    BIT 5,B\nd700 0f6a 18a6 ddd2 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 68 -1\nddd2 16 -1\n-1\n\ncb69    BIT 5,C\nda00 691b 7c79 1dba 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 69 -1\n1dba 8a -1\n-1\n\ncb6a    BIT 5,D\n2200 13e8 86d4 4e09 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 6a -1\n4e09 d5 -1\n-1\n\ncb6b    BIT 5,E\naf00 5123 7635 1ca9 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 6b -1\n1ca9 86 -1\n-1\n\ncb6c    BIT 5,H\n4300 faa6 abc2 5605 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 6c -1\n5605 2b -1\n-1\n\ncb6d    BIT 5,L\n7f00 f099 d435 d9ad 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 6d -1\nd9ad 4e -1\n-1\n\ncb6e    BIT 5,(HL)\n4a00 08c9 8177 d8ba 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 6e -1\nd8ba 31 -1\n-1\n\ncb6f_1  BIT 5,A\nff00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 6f -1\n-1\n\ncb6f    BIT 5,A\na100 8c80 4678 4d34 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 6f -1\n4d34 78 -1\n-1\n\ncb70    BIT 6,B\n1900 958a 5dab f913 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 70 -1\nf913 cf -1\n-1\n\ncb71    BIT 6,C\n3d00 095e d6df 42fe 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 71 -1\n42fe 24 -1\n-1\n\ncb72    BIT 6,D\na500 c0bf 4c8d ad11 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 72 -1\nad11 3b -1\n-1\n\ncb73    BIT 6,E\nf200 49a6 b279 2ecc 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 73 -1\n2ecc e0 -1\n-1\n\ncb74    BIT 6,H\n0500 445e 05e9 983d 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 74 -1\n983d fa -1\n-1\n\ncb75    BIT 6,L\n6b00 83c6 635a d18d 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 75 -1\nd18d 11 -1\n-1\n\ncb76    BIT 6,(HL)\nf800 3057 3629 bc71 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 76 -1\nbc71 18 -1\n-1\n\ncb77_1  BIT 6,A\nff00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 77 -1\n-1\n\ncb77    BIT 6,A\n9200 d6f8 5100 736d 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 77 -1\n736d 36 -1\n-1\n\ncb78    BIT 7,B\n7200 1cf8 8d2b c76a 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 78 -1\nc76a 1f -1\n-1\n\ncb79    BIT 7,C\na800 809e 1124 39e8 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 79 -1\n39e8 98 -1\n-1\n\ncb7a    BIT 7,D\n5800 7d24 63e1 d9af 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 7a -1\nd9af ed -1\n-1\n\ncb7b    BIT 7,E\n0300 50ab 05bd 6bd0 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 7b -1\n6bd0 a5 -1\n-1\n\ncb7c    BIT 7,H\nad00 f77b 55ae 063b 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 7c -1\n063b 34 -1\n-1\n\ncb7d    BIT 7,L\n8200 b792 38cb 5f9b 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 7d -1\n5f9b 97 -1\n-1\n\ncb7e    BIT 7,(HL)\n4200 3b91 f59c a25e 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 7e -1\na25e d7 -1\n-1\n\ncb7f_1  BIT 7,A\nff00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 7f -1\n-1\n\ncb7f    BIT 7,A\n6a00 84ec cf4e 185b 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 7f -1\n185b f1 -1\n-1\n\ncb80    RES 0,B\n8f00 702f 17bd a706 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 80 -1\na706 0a -1\n-1\n\ncb81    RES 0,C\nae00 947f 7153 6616 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 81 -1\n6616 74 -1\n-1\n\ncb82    RES 0,D\n8100 bed2 c719 4572 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 82 -1\n4572 2f -1\n-1\n\ncb83    RES 0,E\ne600 63a2 ccf7 ae9a 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 83 -1\nae9a 16 -1\n-1\n\ncb84    RES 0,H\nce00 e0cc d305 d6c0 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 84 -1\nd6c0 72 -1\n-1\n\ncb85    RES 0,L\nf300 ed79 9db7 dda0 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 85 -1\ndda0 8a -1\n-1\n\ncb86    RES 0,(HL)\n2a00 b0b9 9426 1b48 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 86 -1\n1b48 62 -1\n-1\n\ncb87    RES 0,A\n1100 86dc 1798 dfc5 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 87 -1\ndfc5 de -1\n-1\n\ncb88    RES 1,B\ne300 8a21 e33e 674d 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 88 -1\n674d 5f -1\n-1\n\ncb89    RES 1,C\n6000 d186 c5b6 1bd7 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 89 -1\n1bd7 f2 -1\n-1\n\ncb8a    RES 1,D\n3e00 5fcd 0b38 b98e 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 8a -1\nb98e 2f -1\n-1\n\ncb8b    RES 1,E\n6500 040e 103f 4a07 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 8b -1\n4a07 3f -1\n-1\n\ncb8c    RES 1,H\nf800 6d27 9bdf daef 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 8c -1\ndaef 0c -1\n-1\n\ncb8d    RES 1,L\n3e00 5469 2c28 bd72 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 8d -1\nbd72 13 -1\n-1\n\ncb8e    RES 1,(HL)\n1f00 140b b492 63a7 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 8e -1\n63a7 d4 -1\n-1\n\ncb8f    RES 1,A\n2500 c522 ca46 1c1a 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 8f -1\n1c1a 37 -1\n-1\n\ncb90    RES 2,B\n5700 595c 4f0a c73c 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 90 -1\nc73c a2 -1\n-1\n\ncb91    RES 2,C\n5e00 8f26 a735 97e0 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 91 -1\n97e0 5e -1\n-1\n\ncb92    RES 2,D\n3300 7d9f 87d0 83d0 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 92 -1\n83d0 2b -1\n-1\n\ncb93    RES 2,E\nc200 4e05 b3f8 2234 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 93 -1\n2234 a0 -1\n-1\n\ncb94    RES 2,H\nee00 8f4b 2831 d6a6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 94 -1\nd6a6 d0 -1\n-1\n\ncb95    RES 2,L\n3c00 6af2 b25d 36ff 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 95 -1\n36ff cd -1\n-1\n\ncb96    RES 2,(HL)\n7600 b027 d0a5 3324 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 96 -1\n3324 21 -1\n-1\n\ncb97    RES 2,A\n1600 ad09 7902 97bc 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 97 -1\n97bc 75 -1\n-1\n\ncb98    RES 3,B\n3400 b61c 771d 5d5e 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 98 -1\n5d5e a4 -1\n-1\n\ncb99    RES 3,C\n5100 65be 1359 8bec 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 99 -1\n8bec 0b -1\n-1\n\ncb9a    RES 3,D\n6400 976d 4c25 dcb2 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 9a -1\ndcb2 09 -1\n-1\n\ncb9b    RES 3,E\na100 b58a d264 2bd6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 9b -1\n2bd6 d3 -1\n-1\n\ncb9c    RES 3,H\nd800 63d6 ac7b c7a0 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 9c -1\nc7a0 75 -1\n-1\n\ncb9d    RES 3,L\n0d00 d840 0810 0800 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 9d -1\n0800 cd -1\n-1\n\ncb9e    RES 3,(HL)\n3b00 ebbf 9434 3a65 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 9e -1\n3a65 2a -1\n-1\n\ncb9f    RES 3,A\nb200 d1de f991 72f6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb 9f -1\n72f6 72 -1\n-1\n\ncba0    RES 4,B\nfa00 d669 71e1 c80d 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb a0 -1\nc80d c0 -1\n-1\n\ncba1    RES 4,C\n8200 75e4 a0de d0ba 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb a1 -1\nd0ba bd -1\n-1\n\ncba2    RES 4,D\ndd00 2b0d 5554 6fc0 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb a2 -1\n6fc0 61 -1\n-1\n\ncba3    RES 4,E\n2200 2f0d 4d2c 6666 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb a3 -1\n6666 8e -1\n-1\n\ncba4    RES 4,H\nd600 d8ed 9cd4 8bb1 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb a4 -1\n8bb1 bb -1\n-1\n\ncba5    RES 4,L\nb400 b393 3e42 88ca 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb a5 -1\n88ca 4f -1\n-1\n\ncba6    RES 4,(HL)\n0a00 4c34 f5a7 e70d 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb a6 -1\ne70d 27 -1\n-1\n\ncba7    RES 4,A\n4500 af61 569a c77b 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb a7 -1\nc77b ff -1\n-1\n\ncba8    RES 5,B\n6400 f269 bae4 c9e7 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb a8 -1\nc9e7 46 -1\n-1\n\ncba9    RES 5,C\ne400 7ad4 bf0a ce0b 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb a9 -1\nce0b 39 -1\n-1\n\ncbaa    RES 5,D\ncd00 d249 4159 fed5 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb aa -1\nfed5 b0 -1\n-1\n\ncbab    RES 5,E\nac00 939a 5d9b 0812 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb ab -1\n0812 f2 -1\n-1\n\ncbac    RES 5,H\n2400 8a7d 2cac ffaa 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb ac -1\nffaa 09 -1\n-1\n\ncbad    RES 5,L\n6f00 5ffb 2360 ae15 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb ad -1\nae15 30 -1\n-1\n\ncbae    RES 5,(HL)\n5a00 aa17 12f3 190e 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb ae -1\n190e 66 -1\n-1\n\ncbaf    RES 5,A\nfc00 bb3f 8bb6 5877 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb af -1\n5877 62 -1\n-1\n\ncbb0    RES 6,B\nb900 7a79 1aaa c3ba 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb b0 -1\nc3ba 4c -1\n-1\n\ncbb1    RES 6,C\n4900 63e4 a544 1190 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb b1 -1\n1190 e3 -1\n-1\n\ncbb2    RES 6,D\n4d00 2b03 6b23 6ff5 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb b2 -1\n6ff5 04 -1\n-1\n\ncbb3    RES 6,E\n8700 857a e98b 5cb1 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb b3 -1\n5cb1 43 -1\n-1\n\ncbb4    RES 6,H\n2b00 b73e 79c9 e1bb 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb b4 -1\ne1bb 78 -1\n-1\n\ncbb5    RES 6,L\n9b00 d879 2ec9 4bba 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb b5 -1\n4bba 70 -1\n-1\n\ncbb6    RES 6,(HL)\n8600 89bf de4a 4fab 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb b6 -1\n4fab a5 -1\n-1\n\ncbb7    RES 6,A\n2200 fb8a 3d6e d4a2 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb b7 -1\nd4a2 f2 -1\n-1\n\ncbb8    RES 7,B\nd000 37c6 225a d249 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb b8 -1\nd249 c4 -1\n-1\n\ncbb9    RES 7,C\na500 1b4a d584 5dee 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb b9 -1\n5dee cc -1\n-1\n\ncbba    RES 7,D\n6300 a5fe f42b 34c9 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb ba -1\n34c9 bc -1\n-1\n\ncbbb    RES 7,E\n1200 f661 aa4f cb30 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb bb -1\ncb30 f4 -1\n-1\n\ncbbc    RES 7,H\n9800 adc3 0b29 7b6e 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb bc -1\n7b6e 45 -1\n-1\n\ncbbd    RES 7,L\nd600 a6e1 8813 10b8 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb bd -1\n10b8 35 -1\n-1\n\ncbbe    RES 7,(HL)\nca00 ff64 1218 77d5 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb be -1\n77d5 ea -1\n-1\n\ncbbf    RES 7,A\n6800 4845 690a 15de 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb bf -1\n15de 1d -1\n-1\n\ncbc0    SET 0,B\ne300 ef71 bffb b3a1 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb c0 -1\nb3a1 5c -1\n-1\n\ncbc1    SET 0,C\n3200 32a1 59ab 3343 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb c1 -1\n3343 aa -1\n-1\n\ncbc2    SET 0,D\nc700 b159 c023 e1f3 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb c2 -1\ne1f3 14 -1\n-1\n\ncbc3    SET 0,E\n0400 b463 c211 8f3a 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb c3 -1\n8f3a 81 -1\n-1\n\ncbc4    SET 0,H\n7e00 545a 6ecf 5876 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb c4 -1\n5876 9d -1\n-1\n\ncbc5    SET 0,L\n4000 c617 079c 4107 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb c5 -1\n4107 cc -1\n-1\n\ncbc6    SET 0,(HL)\nb800 0373 b807 f0be 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb c6 -1\nf0be 9c -1\n-1\n\ncbc7    SET 0,A\n7700 3681 9b55 583f 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb c7 -1\n583f 58 -1\n-1\n\ncbc8    SET 1,B\n7d00 a772 8682 7cf3 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb c8 -1\n7cf3 75 -1\n-1\n\ncbc9    SET 1,C\n0b00 67ee 30e0 72db 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb c9 -1\n72db 87 -1\n-1\n\ncbca    SET 1,D\n9c00 9517 cfbb fbc7 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb ca -1\nfbc7 1a -1\n-1\n\ncbcb    SET 1,E\ne800 0f3d 336f f70d 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb cb -1\nf70d a1 -1\n-1\n\ncbcc    SET 1,H\nfb00 7981 0bbb 18fd 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb cc -1\n18fd fe -1\n-1\n\ncbcd    SET 1,L\n5500 5e78 bf34 2602 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb cd -1\n2602 2d -1\n-1\n\ncbce    SET 1,(HL)\nd500 a111 cb2a 8ec6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb ce -1\n8ec6 bf -1\n-1\n\ncbcf    SET 1,A\na200 6baf 98b2 98a0 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb cf -1\n98a0 d4 -1\n-1\n\ncbd0    SET 2,B\n2300 7bcb 02e7 1724 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb d0 -1\n1724 30 -1\n-1\n\ncbd1    SET 2,C\n5300 581f b775 47f4 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb d1 -1\n47f4 c7 -1\n-1\n\ncbd2    SET 2,D\n6900 c147 b79c 7528 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb d2 -1\n7528 4f -1\n-1\n\ncbd3    SET 2,E\nae00 bbc4 ce52 5fba 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb d3 -1\n5fba 3a -1\n-1\n\ncbd4    SET 2,H\nd800 6e1e af6f bf2e 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb d4 -1\nbf2e 71 -1\n-1\n\ncbd5    SET 2,L\n8400 a19a d2fd 8a77 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb d5 -1\n8a77 52 -1\n-1\n\ncbd6    SET 2,(HL)\na900 f5f3 2180 6029 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb d6 -1\n6029 b7 -1\n-1\n\ncbd7    SET 2,A\nb100 c008 8425 290a 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb d7 -1\n290a 42 -1\n-1\n\ncbd8    SET 3,B\n8b00 09c4 ddf3 6d7e 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb d8 -1\n6d7e 6e -1\n-1\n\ncbd9    SET 3,C\n3e00 3e36 30ec efc6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb d9 -1\nefc6 5b -1\n-1\n\ncbda    SET 3,D\nd000 3e8f 28fe 1c87 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb da -1\n1c87 b9 -1\n-1\n\ncbdb    SET 3,E\n1200 977a 8c49 bc48 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb db -1\nbc48 ef -1\n-1\n\ncbdc    SET 3,H\n8d00 05de f8d3 b125 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb dc -1\nb125 0e -1\n-1\n\ncbdd    SET 3,L\nc300 08a9 2bc8 5b9f 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb dd -1\n5b9f 94 -1\n-1\n\ncbde    SET 3,(HL)\n1900 900f d572 ba03 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb de -1\nba03 93 -1\n-1\n\ncbdf    SET 3,A\n6700 2745 7e3d 0fa1 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb df -1\n0fa1 c5 -1\n-1\n\ncbe0    SET 4,B\n3e00 d633 9897 3744 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb e0 -1\n3744 54 -1\n-1\n\ncbe1    SET 4,C\n7d00 50a6 0136 5334 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb e1 -1\n5334 85 -1\n-1\n\ncbe2    SET 4,D\nd400 6b45 a192 3a4c 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb e2 -1\n3a4c 47 -1\n-1\n\ncbe3    SET 4,E\n3b00 d29c 05e0 2e78 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb e3 -1\n2e78 48 -1\n-1\n\ncbe4    SET 4,H\n1e00 7d5e 846d 0978 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb e4 -1\n0978 84 -1\n-1\n\ncbe5    SET 4,L\nca00 df0d d588 b48f 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb e5 -1\nb48f cf -1\n-1\n\ncbe6    SET 4,(HL)\nb300 52c2 dbfe 9f9b 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb e6 -1\n9f9b f6 -1\n-1\n\ncbe7    SET 4,A\n8e00 cf02 67ef f2e0 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb e7 -1\nf2e0 cf -1\n-1\n\ncbe8    SET 5,B\n7100 bb18 66ec 4a05 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb e8 -1\n4a05 e6 -1\n-1\n\ncbe9    SET 5,C\n5700 2897 8f2f a4d0 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb e9 -1\na4d0 b2 -1\n-1\n\ncbea    SET 5,D\nec00 304a 60a1 f32a 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb ea -1\nf32a 9c -1\n-1\n\ncbeb    SET 5,E\nf000 532b a1be 1a1a 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb eb -1\n1a1a 21 -1\n-1\n\ncbec    SET 5,H\nf200 f0f3 a816 ba08 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb ec -1\nba08 82 -1\n-1\n\ncbed    SET 5,L\n1300 5127 adab 2dec 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb ed -1\n2dec cb -1\n-1\n\ncbee    SET 5,(HL)\n9000 b273 50ae e90d 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb ee -1\ne90d f1 -1\n-1\n\ncbef    SET 5,A\n2500 4281 f0d4 2c39 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb ef -1\n2c39 c8 -1\n-1\n\ncbf0    SET 6,B\nfb00 5802 0c27 6ff5 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb f0 -1\n6ff5 f6 -1\n-1\n\ncbf1    SET 6,C\n5500 a103 3ff5 5e1c 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb f1 -1\n5e1c 37 -1\n-1\n\ncbf2    SET 6,D\nf000 625a af82 9819 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb f2 -1\n9819 e4 -1\n-1\n\ncbf3    SET 6,E\n8600 d7bd 5d86 263f 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb f3 -1\n263f a1 -1\n-1\n\ncbf4    SET 6,H\n9400 0243 9ec1 75d9 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb f4 -1\n75d9 3f -1\n-1\n\ncbf5    SET 6,L\nce00 2d42 5e6a 47e6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb f5 -1\n47e6 ce -1\n-1\n\ncbf6    SET 6,(HL)\n7b00 c2d7 4492 a9bc 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb f6 -1\na9bc b1 -1\n-1\n\ncbf7    SET 6,A\n6d00 abaf 5b5d 188c 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb f7 -1\n188c 6c -1\n-1\n\ncbf8    SET 7,B\nc600 b812 a037 d2b0 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb f8 -1\nd2b0 cb -1\n-1\n\ncbf9    SET 7,C\nef00 c5f2 77a8 0730 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb f9 -1\n0730 ae -1\n-1\n\ncbfa    SET 7,D\n8700 1581 63e3 ed03 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb fa -1\ned03 27 -1\n-1\n\ncbfb    SET 7,E\na300 7d27 97c3 d1ae 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb fb -1\nd1ae f2 -1\n-1\n\ncbfc    SET 7,H\nec00 060a 3ef6 500f 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb fc -1\n500f 94 -1\n-1\n\ncbfd    SET 7,L\n1100 231a 8563 28c5 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb fd -1\n28c5 ab -1\n-1\n\ncbfe    SET 7,(HL)\n5300 4948 89dd 3a24 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb fe -1\n3a24 c3 -1\n-1\n\ncbff    SET 7,A\n7900 799b 6cf7 e3f2 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 cb ff -1\ne3f2 25 -1\n-1\n\ncc_1    CALL Z,nn\n004e 0000 0000 0000 0000 0000 0000 0000 0000 0000 5698 0000\n00 00 0 0 0 0     1\n0000 cc 61 9c -1\n-1\n\ncc_2    CALL Z,nn\n000e 0000 0000 0000 0000 0000 0000 0000 0000 0000 5698 0000\n00 00 0 0 0 0     1\n0000 cc 61 9c -1\n-1\n\ncd      CALL nn\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 b07d 0000\n00 00 0 0 0 0     1\n0000 cd 5d 3a -1\n-1\n\nce      ADC A,n\n60f5 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ce b2 -1\n-1\n\ncf      RST 8H\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 5507 6d33\n00 00 0 0 0 0     1\n6d33 cf -1\n-1\n\nd0_1    RET NC\n0098 0000 0000 0000 0000 0000 0000 0000 0000 0000 43f7 0000\n00 00 0 0 0 0     1\n0000 d0 -1\n43f7 e9 af -1\n-1\n\nd0_2    RET NC\n0099 0000 0000 0000 0000 0000 0000 0000 0000 0000 43f7 0000\n00 00 0 0 0 0     1\n0000 d0 -1\n43f7 e9 af -1\n-1\n\nd1      POP DE\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4143 0000\n00 00 0 0 0 0     1\n0000 d1 -1\n4143 ce e8 -1\n-1\n\nd2_1    JP NC,nn\n0086 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 d2 1b e1 -1\n-1\n\nd2_2    JP NC,nn\n0087 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 d2 1b e1 -1\n-1\n\nd3_1    OUT (n),A\na200 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 d3 ed -1\n-1\n\nd3_2    OUT (n),A\n4200 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 d3 ec -1\n-1\n\nd3_3    OUT (n),A\n4200 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 d3 ed -1\n-1\n\nd3      OUT (n),A\na200 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 d3 ec -1\n-1\n\nd4_1    CALL NC,nn\n000e 0000 0000 0000 0000 0000 0000 0000 0000 0000 5698 0000\n00 00 0 0 0 0     1\n0000 d4 61 9c -1\n-1\n\nd4_2    CALL NC,nn\n000f 0000 0000 0000 0000 0000 0000 0000 0000 0000 5698 0000\n00 00 0 0 0 0     1\n0000 d4 61 9c -1\n-1\n\nd5      PUSH DE\n53e3 1459 775f 1a2f 0000 0000 0000 0000 0000 0000 ec12 0000\n00 00 0 0 0 0     1\n0000 d5 -1\n-1\n\nd6      SUB n\n3900 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 d6 df -1\n-1\n\nd7      RST 10H\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 5507 6d33\n00 00 0 0 0 0     1\n6d33 d7 -1\n-1\n\nd8_1    RET C\n0098 0000 0000 0000 0000 0000 0000 0000 0000 0000 43f7 0000\n00 00 0 0 0 0     1\n0000 d8 -1\n43f7 e9 af -1\n-1\n\nd8_2    RET C\n0099 0000 0000 0000 0000 0000 0000 0000 0000 0000 43f7 0000\n00 00 0 0 0 0     1\n0000 d8 -1\n43f7 e9 af -1\n-1\n\nd9      EXX\n4d94 e07a e35b 9d64 1a64 c930 3d01 7d02 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 d9 -1\n-1\n\nda_1    JP C,nn\n0087 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 da 1b e1 -1\n-1\n\nda_2    JP C,nn\n0086 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 da 1b e1 -1\n-1\n\ndb_1    IN A,(n)\nc100 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 db e3 -1\n-1\n\ndb_2    IN A,(n)\n7100 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 db e2 -1\n-1\n\ndb_3    IN A,(n)\n7100 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 db e3 -1\n-1\n\ndb      IN A,(n)\nc100 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 db e2 -1\n-1\n\ndc_1    CALL C,nn\n000f 0000 0000 0000 0000 0000 0000 0000 0000 0000 5698 0000\n00 00 0 0 0 0     1\n0000 dc 61 9c -1\n-1\n\ndc_2    CALL C,nn\n000e 0000 0000 0000 0000 0000 0000 0000 0000 0000 5698 0000\n00 00 0 0 0 0     1\n0000 dc 61 9c -1\n-1\n\ndd00\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     9\n0000 dd 00 00 -1\n-1\n\ndd09    ADD IX,BC\n0d05 1426 53ce 41e3 0000 0000 0000 0000 9ec0 5c89 0000 0000\n00 00 0 0 0 0     1\n0000 dd 09 -1\n-1\n\ndd19    ADD IX,DE\n1911 0e0b 2724 be62 0000 0000 0000 0000 824f 760b 0000 0000\n00 00 0 0 0 0     1\n0000 dd 19 -1\n-1\n\ndd21    LD IX,nn\nc935 4353 bd22 94d5 0000 0000 0000 0000 dade aad6 0000 0000\n00 00 0 0 0 0     1\n0000 dd 21 f2 7c -1\n-1\n\ndd22    LD (nn),IX\n5b1d 45a1 6de8 39d3 0000 0000 0000 0000 ebe7 05b0 0000 0000\n00 00 0 0 0 0     1\n0000 dd 22 4f ad -1\n-1\n\ndd23    INC IX\n9095 ac3c 4d90 379b 0000 0000 0000 0000 d50b a157 0000 0000\n00 00 0 0 0 0     1\n0000 dd 23 -1\n-1\n\ndd24    INC IXh*\n0698 dcd0 a31b d527 0000 0000 0000 0000 8cda b096 0000 0000\n00 00 0 0 0 0     1\n0000 dd 24 -1\n-1\n\ndd25    DEC IXh*\n5acc 206b ed10 6eab 0000 0000 0000 0000 bb3c 5ebd 0000 0000\n00 00 0 0 0 0     1\n0000 dd 25 -1\n-1\n\ndd26    LD IXh,n*\n9522 ede0 a352 adea 0000 0000 0000 0000 5f40 82e1 0000 0000\n00 00 0 0 0 0     1\n0000 dd 26 ad -1\n-1\n\ndd29    ADD IX,IX\nac80 0f0e 72c8 1f2a 0000 0000 0000 0000 5195 7d8a 0000 0000\n00 00 0 0 0 0     1\n0000 dd 29 -1\n-1\n\ndd2a    LD IX,(nn)\n3d36 b24e bdbc ca4e 0000 0000 0000 0000 ba65 e7ce 0000 0000\n00 00 0 0 0 0     1\n0000 dd 2a bc 40 -1\n40bc b5 30 -1\n-1\n\ndd2b    DEC IX\nad4b d5e6 9377 f132 0000 0000 0000 0000 7a17 2188 0000 0000\n00 00 0 0 0 0     1\n0000 dd 2b -1\n-1\n\ndd2c    INC IXl*\n8838 f2f3 d277 9153 0000 0000 0000 0000 c62f b002 0000 0000\n00 00 0 0 0 0     1\n0000 dd 2c -1\n-1\n\ndd2d    DEC IXl*\n39bc b23c 6e11 5a49 0000 0000 0000 0000 0267 ab03 0000 0000\n00 00 0 0 0 0     1\n0000 dd 2d -1\n-1\n\ndd2e    LD IXl,n*\n9aca a04a b49f a4a6 0000 0000 0000 0000 bd90 38a1 0000 0000\n00 00 0 0 0 0     1\n0000 dd 2e 1c -1\n-1\n\ndd34    INC (IX+d)\n8304 d1fc b80b 8082 0000 0000 0000 0000 dea9 6fd8 0000 0000\n00 00 0 0 0 0     1\n0000 dd 34 e6 -1\nde8f 57 -1\n-1\n\ndd35    DEC (IX+d)\n8681 4641 1ef6 10ab 0000 0000 0000 0000 c733 8ec4 0000 0000\n00 00 0 0 0 0     1\n0000 dd 35 60 -1\nc793 f7 -1\n-1\n\ndd36    LD (IX+d),n\n76dc 2530 5158 877d 0000 0000 0000 0000 b5c6 8d3c 0000 0000\n00 00 0 0 0 0     1\n0000 dd 36 35 b5 -1\n-1\n\ndd39    ADD IX,SP\n875b a334 d79d 59e4 0000 0000 0000 0000 b11a 4c88 fa4a 0000\n00 00 0 0 0 0     1\n0000 dd 39 -1\n-1\n\ndd44    LD B,IXh*\nb37e cbb0 36e8 3f45 0000 0000 0000 0000 2702 b3b9 0000 0000\n00 00 0 0 0 0     1\n0000 dd 44 -1\n-1\n\ndd45    LD B,IXl*\n4e10 5c6d d11d 1736 0000 0000 0000 0000 7298 2d10 0000 0000\n00 00 0 0 0 0     1\n0000 dd 45 -1\n-1\n\ndd46    LD B,(IX+d)\nc758 bf29 66f2 29ef 0000 0000 0000 0000 5cc7 407d 0000 0000\n00 00 0 0 0 0     1\n0000 dd 46 68 -1\n5d2f 8d -1\n-1\n\ndd4c    LD C,IXh*\ne15c 75ec 7531 ae9e 0000 0000 0000 0000 3ed8 03b7 0000 0000\n00 00 0 0 0 0     1\n0000 dd 4c -1\n-1\n\ndd4d    LD C,IXl*\n469e 7864 6a5a 00e2 0000 0000 0000 0000 a1aa 0d6f 0000 0000\n00 00 0 0 0 0     1\n0000 dd 4d -1\n-1\n\ndd4e    LD C,(IX+d)\n7bf7 6605 8d55 def2 0000 0000 0000 0000 d94b 17fb 0000 0000\n00 00 0 0 0 0     1\n0000 dd 4e 2e -1\nd979 76 -1\n-1\n\ndd54    LD D,IXh*\n8376 0d13 c767 3119 0000 0000 0000 0000 4b6d 030b 0000 0000\n00 00 0 0 0 0     1\n0000 dd 54 -1\n-1\n\ndd55    LD D,IXl*\nff78 85e3 566b 8f3a 0000 0000 0000 0000 d7d7 4e0b 0000 0000\n00 00 0 0 0 0     1\n0000 dd 55 -1\n-1\n\ndd56    LD D,(IX+d)\n97b3 b617 bb50 81d1 0000 0000 0000 0000 a306 7a49 0000 0000\n00 00 0 0 0 0     1\n0000 dd 56 f4 -1\na2fa de -1\n-1\n\ndd5c    LD E,IXh*\naf82 24bf 2793 f925 0000 0000 0000 0000 f9a3 0b82 0000 0000\n00 00 0 0 0 0     1\n0000 dd 5c -1\n-1\n\ndd5d    LD E,IXl*\n36cb 97a9 400d 30fe 0000 0000 0000 0000 3340 b3ed 0000 0000\n00 00 0 0 0 0     1\n0000 dd 5d -1\n-1\n\ndd5e    LD E,(IX+d)\na220 389d 2ff8 368c 0000 0000 0000 0000 8d32 3512 0000 0000\n00 00 0 0 0 0     1\n0000 dd 5e 8f -1\n8cc1 ce -1\n-1\n\ndd60    LD IXh,B*\n2392 7f6a 3dc0 cefb 0000 0000 0000 0000 44a0 c424 0000 0000\n00 00 0 0 0 0     1\n0000 dd 60 -1\n-1\n\ndd61    LD IXh,C*\n76ed 268c d5c8 bab0 0000 0000 0000 0000 b650 0a93 0000 0000\n00 00 0 0 0 0     1\n0000 dd 61 -1\n-1\n\ndd62    LD IXh,D*\n4c6f b482 fef4 62e7 0000 0000 0000 0000 6e25 9655 0000 0000\n00 00 0 0 0 0     1\n0000 dd 62 -1\n-1\n\ndd63    LD IXh,E*\n6e9a 5499 3c8f 1f64 0000 0000 0000 0000 bf35 0df7 0000 0000\n00 00 0 0 0 0     1\n0000 dd 63 -1\n-1\n\ndd64    LD IXh,IXh*\n47f6 1b7a a55e 2fc2 0000 0000 0000 0000 efc7 aca0 0000 0000\n00 00 0 0 0 0     1\n0000 dd 64 -1\n-1\n\ndd65    LD IXh,IXl*\nd786 7d1d b659 77e8 0000 0000 0000 0000 58fa 006d 0000 0000\n00 00 0 0 0 0     1\n0000 dd 65 -1\n-1\n\ndd66    LD H,(IX+d)\n84c2 79b1 ca4a aaa0 0000 0000 0000 0000 ce5d dd2d 0000 0000\n00 00 0 0 0 0     1\n0000 dd 66 b5 -1\nce12 03 -1\n-1\n\ndd67    LD IXh,A*\n967c 511e 336d 40f6 0000 0000 0000 0000 66e7 5be2 0000 0000\n00 00 0 0 0 0     1\n0000 dd 67 -1\n-1\n\ndd68    LD IXl,B*\n4a9d efa8 febd 07e4 0000 0000 0000 0000 5fd8 b23f 0000 0000\n00 00 0 0 0 0     1\n0000 dd 68 -1\n-1\n\ndd69    LD IXl,C*\n6466 2142 2523 82b3 0000 0000 0000 0000 6479 04a7 0000 0000\n00 00 0 0 0 0     1\n0000 dd 69 -1\n-1\n\ndd6a    LD IXl,D*\n401f 61f1 4b08 fa88 0000 0000 0000 0000 c37f d8f6 0000 0000\n00 00 0 0 0 0     1\n0000 dd 6a -1\n-1\n\ndd6b    LD IXl,E*\n6dc7 e2ae 40bd f3c0 0000 0000 0000 0000 2290 2749 0000 0000\n00 00 0 0 0 0     1\n0000 dd 6b -1\n-1\n\ndd6c    LD IXl,IXh*\n3939 90da 62dc 7c31 0000 0000 0000 0000 412f 7211 0000 0000\n00 00 0 0 0 0     1\n0000 dd 6c -1\n-1\n\ndd6d    LD IXl,IXl*\n3964 ff3f 23d4 c7c7 0000 0000 0000 0000 9b70 20c6 0000 0000\n00 00 0 0 0 0     1\n0000 dd 6d -1\n-1\n\ndd6e    LD L,(IX+d)\n223f f661 b61c 0f53 0000 0000 0000 0000 c648 fae8 0000 0000\n00 00 0 0 0 0     1\n0000 dd 6e 2c -1\nc674 6b -1\n-1\n\ndd6f    LD IXl,A*\n6e84 9cd4 a293 647d 0000 0000 0000 0000 0d0b 4a56 0000 0000\n00 00 0 0 0 0     1\n0000 dd 6f -1\n-1\n\ndd70    LD (IX+d),B\nd09f fe00 231e 31ec 0000 0000 0000 0000 05fa ea92 0000 0000\n00 00 0 0 0 0     1\n0000 dd 70 f6 -1\n-1\n\ndd71    LD (IX+d),C\nebee 151c 05c7 ee08 0000 0000 0000 0000 3722 2ec6 0000 0000\n00 00 0 0 0 0     1\n0000 dd 71 23 -1\n-1\n\ndd72    LD (IX+d),D\n80c9 ac1e 63bd 828b 0000 0000 0000 0000 8dff 94ef 0000 0000\n00 00 0 0 0 0     1\n0000 dd 72 93 -1\n-1\n\ndd73    LD (IX+d),E\n8f3e b5a3 07de 0b0c 0000 0000 0000 0000 79c6 ae79 0000 0000\n00 00 0 0 0 0     1\n0000 dd 73 57 -1\n-1\n\ndd74    LD (IX+d),H\n4ae0 49c5 3deb 0125 0000 0000 0000 0000 5910 429a 0000 0000\n00 00 0 0 0 0     1\n0000 dd 74 b9 -1\n-1\n\ndd75    LD (IX+d),L\n5772 e833 b63e 734f 0000 0000 0000 0000 ae4c e8c2 0000 0000\n00 00 0 0 0 0     1\n0000 dd 75 30 -1\n-1\n\ndd77    LD (IX+d),A\ndc56 d893 4116 f2d2 0000 0000 0000 0000 a181 3157 0000 0000\n00 00 0 0 0 0     1\n0000 dd 77 8c -1\n-1\n\ndd7c    LD A,IXh*\n7558 7705 ac92 a6a1 0000 0000 0000 0000 8cde 7507 0000 0000\n00 00 0 0 0 0     1\n0000 dd 7c -1\n-1\n\ndd7d    LD A,IXl*\n6c18 93fb 6bdd 3a10 0000 0000 0000 0000 d7cb c0f6 0000 0000\n00 00 0 0 0 0     1\n0000 dd 7d -1\n-1\n\ndd7e    LD A,(IX+d)\n6a66 1f77 6220 0c40 0000 0000 0000 0000 1cf4 1a1f 0000 0000\n00 00 0 0 0 0     1\n0000 dd 7e bc -1\n1cb0 57 -1\n-1\n\ndd84    ADD A,IXh*\n2e47 1de8 b8b9 78a6 0000 0000 0000 0000 9f1d b11f 0000 0000\n00 00 0 0 0 0     1\n0000 dd 84 -1\n-1\n\ndd85    ADD A,IXl*\nb27a b1ff 8d7b 40c0 0000 0000 0000 0000 b513 0688 0000 0000\n00 00 0 0 0 0     1\n0000 dd 85 -1\n-1\n\ndd86    ADD A,(IX+d)\n4efa d085 5bac e364 0000 0000 0000 0000 b5b5 fe3a 0000 0000\n00 00 0 0 0 0     1\n0000 dd 86 c1 -1\nb576 5b -1\n-1\n\ndd8c    ADC A,IXh*\nbc63 8fdc ea8f 9734 0000 0000 0000 0000 0eb3 1b54 0000 0000\n00 00 0 0 0 0     1\n0000 dd 8c -1\n-1\n\ndd8d    ADC A,IXl*\nb61f 1c81 b6fb d6e5 0000 0000 0000 0000 09be a736 0000 0000\n00 00 0 0 0 0     1\n0000 dd 8d -1\n-1\n\ndd8e    ADC A,(IX+d)\n4ed4 182d ab17 94ae 0000 0000 0000 0000 bb97 87da 0000 0000\n00 00 0 0 0 0     1\n0000 dd 8e 25 -1\nbbbc 32 -1\n-1\n\ndd94    SUB IXh*\n7ef1 9efe 6ea1 fc55 0000 0000 0000 0000 0a09 89c5 0000 0000\n00 00 0 0 0 0     1\n0000 dd 94 -1\n-1\n\ndd95    SUB IXl*\n2920 59ab 428c 3a94 0000 0000 0000 0000 44fd f243 0000 0000\n00 00 0 0 0 0     1\n0000 dd 95 -1\n-1\n\ndd96    SUB (IX+d)\n9b76 461f ced7 db3f 0000 0000 0000 0000 2c66 9dbf 0000 0000\n00 00 0 0 0 0     1\n0000 dd 96 5f -1\n2cc5 49 -1\n-1\n\ndd9c    SBC A,IXh*\nfaf4 670e afcc 8b34 0000 0000 0000 0000 285f 1caa 0000 0000\n00 00 0 0 0 0     1\n0000 dd 9c -1\n-1\n\ndd9d    SBC A,IXl*\nf827 0cdb df32 d0e4 0000 0000 0000 0000 9b12 7d07 0000 0000\n00 00 0 0 0 0     1\n0000 dd 9d -1\n-1\n\ndd9e    SBC A,(IX+d)\n938e f9c5 cbc4 ca21 0000 0000 0000 0000 b4cc 46fa 0000 0000\n00 00 0 0 0 0     1\n0000 dd 9e 14 -1\nb4e0 b5 -1\n-1\n\ndda4    AND IXh*\n52f5 ba53 acfc 9481 0000 0000 0000 0000 2f8b edf6 0000 0000\n00 00 0 0 0 0     1\n0000 dd a4 -1\n-1\n\ndda5    AND IXl*\nbaaf a675 d757 f1db 0000 0000 0000 0000 fdef d8ce 0000 0000\n00 00 0 0 0 0     1\n0000 dd a5 -1\n-1\n\ndda6    AND (IX+d)\n1da4 20c4 ebc3 da8d 0000 0000 0000 0000 7e95 5e8a 0000 0000\n00 00 0 0 0 0     1\n0000 dd a6 41 -1\n7ed6 c7 -1\n-1\n\nddac    XOR IXh*\nef15 2a7c 17e5 3f6e 0000 0000 0000 0000 affa a0b5 0000 0000\n00 00 0 0 0 0     1\n0000 dd ac -1\n-1\n\nddad    XOR IXl*\nba2e 6ba1 ef1b 5713 0000 0000 0000 0000 ba38 a708 0000 0000\n00 00 0 0 0 0     1\n0000 dd ad -1\n-1\n\nddae    XOR (IX+d)\n8009 3ad6 a721 2100 0000 0000 0000 0000 e909 87b4 0000 0000\n00 00 0 0 0 0     1\n0000 dd ae 72 -1\ne97b c3 -1\n-1\n\nddb4    OR IXh*\n1ccd 29aa 2e82 4dc8 0000 0000 0000 0000 9c04 8be3 0000 0000\n00 00 0 0 0 0     1\n0000 dd b4 -1\n-1\n\nddb5    OR IXl*\n46b4 fc93 7a06 0518 0000 0000 0000 0000 0ac5 4150 0000 0000\n00 00 0 0 0 0     1\n0000 dd b5 -1\n-1\n\nddb6    OR (IX+d)\n5017 ab81 4287 5ee1 0000 0000 0000 0000 c66f d6cc 0000 0000\n00 00 0 0 0 0     1\n0000 dd b6 31 -1\nc6a0 1c -1\n-1\n\nddbc    CP IXh*\n53e0 aa98 f7d7 fa0c 0000 0000 0000 0000 be7a a41f 0000 0000\n00 00 0 0 0 0     1\n0000 dd bc -1\n-1\n\nddbd    CP IXl*\ndc83 80ce 5d2f e999 0000 0000 0000 0000 bb41 a24f 0000 0000\n00 00 0 0 0 0     1\n0000 dd bd -1\n-1\n\nddbe    CP (IX+d)\n9838 bfd5 a299 d34b 0000 0000 0000 0000 9332 b1d5 0000 0000\n00 00 0 0 0 0     1\n0000 dd be 48 -1\n937a 5b -1\n-1\n\nddcb00  RLC (IX+d),B*\n3c65 f0e4 09d1 646b 0000 0000 0000 0000 1da1 f08f 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 0d 00 -1\n1dae a1 -1\n-1\n\nddcb01  RLC (IX+d),C*\nf68f e33b 2d4a 7725 0000 0000 0000 0000 28fd f31b 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb b7 01 -1\n28b4 e3 -1\n-1\n\nddcb02  RLC (IX+d),D*\ne20c 836e 513a f840 0000 0000 0000 0000 c796 ae9b 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 91 02 -1\nc727 8d -1\n-1\n\nddcb03  RLC (IX+d),E*\n6224 3571 c519 48dc 0000 0000 0000 0000 041e c07b 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 48 03 -1\n0466 78 -1\n-1\n\nddcb04  RLC (IX+d),H*\nb310 bfc4 64af d622 0000 0000 0000 0000 5949 a989 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 48 04 -1\n5991 68 -1\n-1\n\nddcb05  RLC (IX+d),L*\n4954 bb04 56ec 9d58 0000 0000 0000 0000 0077 1349 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb ff 05 -1\n0076 95 -1\n-1\n\nddcb06  RLC (IX+d)\n0cf4 f636 90a6 6117 0000 0000 0000 0000 5421 90ee 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 07 06 -1\n5428 97 -1\n-1\n\nddcb07  RLC (IX+d),A*\n6f4d 9ca3 bdf6 ed50 0000 0000 0000 0000 9803 55f9 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 42 07 -1\n9845 ae -1\n-1\n\nddcb08  RRC (IX+d),B*\n02f4 1c66 6023 ae06 0000 0000 0000 0000 ef40 b006 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 0a 08 -1\nef4a da -1\n-1\n\nddcb09  RRC (IX+d),C*\n9825 9258 54d5 5e1e 0000 0000 0000 0000 9d0b 6e58 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 3b 09 -1\n9d46 6f -1\n-1\n\nddcb0a  RRC (IX+d),D*\nd2dd 6aac e789 9293 0000 0000 0000 0000 1fb4 2498 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 83 0a -1\n1f37 78 -1\n-1\n\nddcb0b  RRC (IX+d),E*\nb82c b284 23f8 7e7d 0000 0000 0000 0000 cd09 6a03 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb fa 0b -1\ncd03 92 -1\n-1\n\nddcb0c  RRC (IX+d),H*\ndf8b b6cc ee8d 855a 0000 0000 0000 0000 bf6b 9b7d 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 79 0c -1\nbfe4 0d -1\n-1\n\nddcb0d  RRC (IX+d),L*\nbae3 ceec bbaa b65e 0000 0000 0000 0000 88bd 503e 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb e4 0d -1\n88a1 1f -1\n-1\n\nddcb0e  RRC (IX+d)\n1c36 890b 7830 060c 0000 0000 0000 0000 fd49 5d07 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb c6 0e -1\nfd0f ad -1\n-1\n\nddcb0f  RRC (IX+d),A*\nf5a7 fad4 fa4b 9c53 0000 0000 0000 0000 7447 2267 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 57 0f -1\n749e f8 -1\n-1\n\nddcb10  RL (IX+d),B*\nf3af ba1f 5387 926e 0000 0000 0000 0000 bba2 ca47 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 4f 10 -1\nbbf1 45 -1\n-1\n\nddcb11  RL (IX+d),C*\n2a69 d604 a9aa 5b52 0000 0000 0000 0000 1809 d275 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb eb 11 -1\n17f4 d9 -1\n-1\n\nddcb12  RL (IX+d),D*\n9287 c479 26d1 10ce 0000 0000 0000 0000 c0fb 2777 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb a6 12 -1\nc0a1 e2 -1\n-1\n\nddcb13  RL (IX+d),E*\na507 580a a48f 11cd 0000 0000 0000 0000 5ac4 ccc7 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb ff 13 -1\n5ac3 a7 -1\n-1\n\nddcb14  RL (IX+d),H*\n294b 5b89 8467 0430 0000 0000 0000 0000 0977 c4e8 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb dd 14 -1\n0954 85 -1\n-1\n\nddcb15  RL (IX+d),L*\n1fd1 6d53 5b7c a134 0000 0000 0000 0000 ede9 a85c 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 07 15 -1\nedf0 0e -1\n-1\n\nddcb16  RL (IX+d)\nda70 a1e4 00b0 92c8 0000 0000 0000 0000 16be 2c95 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 45 16 -1\n1703 5b -1\n-1\n\nddcb17  RL (IX+d),A*\n3300 cbd1 4e1a cd27 0000 0000 0000 0000 b8c9 e6d4 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 1c 17 -1\nb8e5 7e -1\n-1\n\nddcb18  RR (IX+d),B*\nd980 4eb5 9cf9 b9f1 0000 0000 0000 0000 a189 bd7c 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 0e 18 -1\na197 90 -1\n-1\n\nddcb19  RR (IX+d),C*\n23b7 595a a756 cf2e 0000 0000 0000 0000 f0e7 26e4 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb a3 19 -1\nf08a 37 -1\n-1\n\nddcb1a  RR (IX+d),D*\n8b52 7e45 bd0f 37a6 0000 0000 0000 0000 de61 9cd9 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb ac 1a -1\nde0d cc -1\n-1\n\nddcb1b  RR (IX+d),E*\n5c79 1414 811c 5881 0000 0000 0000 0000 b7c3 d14f 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 05 1b -1\nb7c8 91 -1\n-1\n\nddcb1c  RR (IX+d),H*\nfafc 6277 8b67 d423 0000 0000 0000 0000 fef9 4a66 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb ff 1c -1\nfef8 61 -1\n-1\n\nddcb1d  RR (IX+d),L*\n76a5 324e e641 58f9 0000 0000 0000 0000 5b63 e18b 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 3a 1d -1\n5b9d f3 -1\n-1\n\nddcb1e  RR (IX+d)\nc5d9 cd58 8967 f074 0000 0000 0000 0000 75b4 693a 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb ce 1e -1\n7582 91 -1\n-1\n\nddcb1f  RR (IX+d),A*\nd28f 7f6d 2058 63e3 0000 0000 0000 0000 1d9b baba 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb a8 1f -1\n1d43 b4 -1\n-1\n\nddcb20  SLA (IX+d),B*\n4ce5 739e dc6c 18f4 0000 0000 0000 0000 dc39 8b0c 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb e8 20 -1\ndc21 0e -1\n-1\n\nddcb21  SLA (IX+d),C*\nd29d 66dd 23ef 9096 0000 0000 0000 0000 3494 b6c3 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 9e 21 -1\n3432 f7 -1\n-1\n\nddcb22  SLA (IX+d),D*\nfb5d e0d0 7c02 b4b7 0000 0000 0000 0000 bd3f 385b 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 43 22 -1\nbd82 9f -1\n-1\n\nddcb23  SLA (IX+d),E*\nc359 68b6 da84 b990 0000 0000 0000 0000 22dd bd27 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb c1 23 -1\n229e e0 -1\n-1\n\nddcb24  SLA (IX+d),H*\nbaf5 7b0b 560b 7c33 0000 0000 0000 0000 31f1 ddbd 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb e8 24 -1\n31d9 c3 -1\n-1\n\nddcb25  SLA (IX+d),L*\n43bb a21b 2347 ae4a 0000 0000 0000 0000 cc63 fc94 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb c1 25 -1\ncc24 eb -1\n-1\n\nddcb26  SLA (IX+d)\n2065 ff37 e41f 70e7 0000 0000 0000 0000 6528 a0d5 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb f7 26 -1\n651f 89 -1\n-1\n\nddcb27  SLA (IX+d),A*\na806 5669 1bee f62c 0000 0000 0000 0000 1f69 3418 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb c3 27 -1\n1f2c ac -1\n-1\n\nddcb28  SRA (IX+d),B*\n7afd 64b8 51f7 7164 0000 0000 0000 0000 999b 8857 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb b6 28 -1\n9951 24 -1\n-1\n\nddcb29  SRA (IX+d),C*\n0404 b794 323f fd34 0000 0000 0000 0000 20e7 c753 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 9c 29 -1\n2083 82 -1\n-1\n\nddcb2a  SRA (IX+d),D*\n4524 afde 0c08 75d7 0000 0000 0000 0000 9505 b624 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb d8 2a -1\n94dd 7c -1\n-1\n\nddcb2b  SRA (IX+d),E*\n8324 e290 26be 7ddd 0000 0000 0000 0000 b484 571c 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb bd 2b -1\nb441 44 -1\n-1\n\nddcb2c  SRA (IX+d),H*\nc688 0c94 6e4b 7dc7 0000 0000 0000 0000 fe28 dc80 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 2c 2c -1\nfe54 81 -1\n-1\n\nddcb2d  SRA (IX+d),L*\nce28 d2ae c9be 4236 0000 0000 0000 0000 b4ed 6de3 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 9b 2d -1\nb488 44 -1\n-1\n\nddcb2e  SRA (IX+d)\n50b0 de74 eca8 83ff 0000 0000 0000 0000 69d8 75c7 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 3d 2e -1\n6a15 05 -1\n-1\n\nddcb2f  SRA (IX+d),A*\naec6 759b 3059 01b9 0000 0000 0000 0000 7a30 dd56 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb d3 2f -1\n7a03 f2 -1\n-1\n\nddcb30  SLL (IX+d),B*\n3c89 96ad 9cc7 a68c 0000 0000 0000 0000 eee8 5a80 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb df 30 -1\neec7 32 -1\n-1\n\nddcb31  SLL (IX+d),C*\nebf5 41e9 929b 7d47 0000 0000 0000 0000 f22d 8943 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 49 31 -1\nf276 cd -1\n-1\n\nddcb32  SLL (IX+d),D*\n9a1b aa64 4209 01ad 0000 0000 0000 0000 579f ec4c 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb e0 32 -1\n577f e2 -1\n-1\n\nddcb33  SLL (IX+d),E*\nb8b1 b854 524f 9599 0000 0000 0000 0000 efac d9ec 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb c9 33 -1\nef75 0b -1\n-1\n\nddcb34  SLL (IX+d),H*\ncd3c 4432 20d4 0b3e 0000 0000 0000 0000 ab48 c95f 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 49 34 -1\nab91 ef -1\n-1\n\nddcb35  SLL (IX+d),L*\ndeb1 c6fc 696d 150d 0000 0000 0000 0000 eb1a 4a12 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb b9 35 -1\nead3 8f -1\n-1\n\nddcb36  SLL (IX+d)*\n3d81 443b ff21 63e3 0000 0000 0000 0000 132e fb39 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb b4 36 -1\n12e2 02 -1\n-1\n\nddcb37  SLL (IX+d),A*\n72d9 bfc9 a69a ec0b 0000 0000 0000 0000 5077 4e3e 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb c6 37 -1\n503d 3d -1\n-1\n\nddcb38  SRL (IX+d),B*\n3c64 b1ee 38e1 ae9f 0000 0000 0000 0000 f695 44b3 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 8e 38 -1\nf623 5e -1\n-1\n\nddcb39  SRL (IX+d),C*\n05d6 9aad a2db df75 0000 0000 0000 0000 a895 e243 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb dc 39 -1\na871 83 -1\n-1\n\nddcb3a  SRL (IX+d),D*\n0e22 0b9f 873b c01d 0000 0000 0000 0000 2591 49c3 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 0d 3a -1\n259e 89 -1\n-1\n\nddcb3b  SRL (IX+d),E*\n1bd9 c795 d8ae 7ccf 0000 0000 0000 0000 6fed 09dc 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 20 3b -1\n700d a9 -1\n-1\n\nddcb3c  SRL (IX+d),H*\nb651 bdf7 fca3 7529 0000 0000 0000 0000 f53b 018b 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb e1 3c -1\nf51c d0 -1\n-1\n\nddcb3d  SRL (IX+d),L*\n2a2d 6e6e cfbd 1db5 0000 0000 0000 0000 0320 6ab0 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb be 3d -1\n02de 58 -1\n-1\n\nddcb3e  SRL (IX+d)\n39b8 b26e b670 b8a2 0000 0000 0000 0000 784a 7840 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 0a 3e -1\n7854 5d -1\n-1\n\nddcb3f  SRL (IX+d),A*\n2a17 429d d8c0 e069 0000 0000 0000 0000 3488 7150 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 31 3f -1\n34b9 04 -1\n-1\n\nddcb40  BIT 0,(IX+d)*\n119b f6ba 079e 0e41 0000 0000 0000 0000 8c01 cd21 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb bd 40 -1\n8bbe e7 -1\n-1\n\nddcb41  BIT 0,(IX+d)*\n22b3 c4b0 575b 66b4 0000 0000 0000 0000 cdcf a25c 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 52 41 -1\nce21 75 -1\n-1\n\nddcb42  BIT 0,(IX+d)*\naf5e 7720 aa95 3b0a 0000 0000 0000 0000 f03a 856a 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 1e 42 -1\nf058 90 -1\n-1\n\nddcb43  BIT 0,(IX+d)*\n7fa6 b699 5e71 1827 0000 0000 0000 0000 e8b6 96a8 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb bc 43 -1\ne872 6b -1\n-1\n\nddcb44  BIT 0,(IX+d)*\n5faa de05 12fd f73b 0000 0000 0000 0000 ee0a 6634 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb e8 44 -1\nedf2 62 -1\n-1\n\nddcb45  BIT 0,(IX+d)*\neac7 699c 47d3 89c3 0000 0000 0000 0000 a2be d81e 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 02 45 -1\na2c0 55 -1\n-1\n\nddcb46  BIT 0,(IX+d)\n60de ac1d 4173 f92a 0000 0000 0000 0000 a39f 12e5 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb e2 46 -1\na381 d5 -1\n-1\n\nddcb47  BIT 0,(IX+d)*\n1b1a f7c0 22f6 5253 0000 0000 0000 0000 5227 919d 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 7a 47 -1\n52a1 6a -1\n-1\n\nddcb48  BIT 1,(IX+d)*\n721a 4509 d68f 3b3d 0000 0000 0000 0000 2746 7f97 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 13 48 -1\n2759 a8 -1\n-1\n\nddcb49  BIT 1,(IX+d)*\n7fe9 da22 ea9c f480 0000 0000 0000 0000 41c6 75a9 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 94 49 -1\n415a 26 -1\n-1\n\nddcb4a  BIT 1,(IX+d)*\nf16d e6c3 5a42 8b21 0000 0000 0000 0000 bfeb e383 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 3b 4a -1\nc026 b5 -1\n-1\n\nddcb4b  BIT 1,(IX+d)*\n1050 880a 52b2 fb1b 0000 0000 0000 0000 c239 6b40 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb b0 4b -1\nc1e9 18 -1\n-1\n\nddcb4c  BIT 1,(IX+d)*\n0538 bc63 f081 0a55 0000 0000 0000 0000 874c 80a3 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 97 4c -1\n86e3 63 -1\n-1\n\nddcb4d  BIT 1,(IX+d)*\n7f8c 32b4 03d5 ef66 0000 0000 0000 0000 7d2a 03bc 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 15 4d -1\n7d3f 60 -1\n-1\n\nddcb4e  BIT 1,(IX+d)\n7c67 fa92 b4d0 9f23 0000 0000 0000 0000 eade 1785 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb b0 4e -1\nea8e 3b -1\n-1\n\nddcb4f  BIT 1,(IX+d)*\n725c 257b db73 2478 0000 0000 0000 0000 88c0 f151 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 8b 4f -1\n884b 4c -1\n-1\n\nddcb50  BIT 2,(IX+d)*\n35f4 8e51 406c 2e3c 0000 0000 0000 0000 daf2 413c 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 12 50 -1\ndb04 00 -1\n-1\n\nddcb51  BIT 2,(IX+d)*\na630 ba85 c88c e86c 0000 0000 0000 0000 84b2 cd8e 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 18 51 -1\n84ca 1c -1\n-1\n\nddcb52  BIT 2,(IX+d)*\ncb88 1220 1103 a868 0000 0000 0000 0000 6156 cfac 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 42 52 -1\n6198 53 -1\n-1\n\nddcb53  BIT 2,(IX+d)*\n5eb3 569e f76d 88c6 0000 0000 0000 0000 ae45 623e 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb e3 53 -1\nae28 d6 -1\n-1\n\nddcb54  BIT 2,(IX+d)*\nc3c9 76fe f1ff 416e 0000 0000 0000 0000 efd5 7576 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 7d 54 -1\nf052 5d -1\n-1\n\nddcb55  BIT 2,(IX+d)*\n7068 dcd0 8345 d498 0000 0000 0000 0000 f352 a88b 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 88 55 -1\nf2da 03 -1\n-1\n\nddcb56  BIT 2,(IX+d)\n9128 2cb8 571c f4fd 0000 0000 0000 0000 6d30 aec2 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 57 56 -1\n6d87 61 -1\n-1\n\nddcb57  BIT 2,(IX+d)*\n3ca7 541a 027c c0b4 0000 0000 0000 0000 5833 160a 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 06 57 -1\n5839 1d -1\n-1\n\nddcb58  BIT 3,(IX+d)*\nc650 e1a8 9d6c bec3 0000 0000 0000 0000 6a46 b66c 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 83 58 -1\n69c9 0f -1\n-1\n\nddcb59  BIT 3,(IX+d)*\nad07 9bda b7ee 63c4 0000 0000 0000 0000 9195 9703 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb db 59 -1\n9170 10 -1\n-1\n\nddcb5a  BIT 3,(IX+d)*\n80c0 5105 36b0 a37c 0000 0000 0000 0000 0de0 ce7f 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb d1 5a -1\n0db1 be -1\n-1\n\nddcb5b  BIT 3,(IX+d)*\n2a8d 083d 1409 06ba 0000 0000 0000 0000 62ad baff 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb d5 5b -1\n6282 67 -1\n-1\n\nddcb5c  BIT 3,(IX+d)*\n4ca4 e502 d23c 6da8 0000 0000 0000 0000 9dc6 6f04 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 5c 5c -1\n9e22 c9 -1\n-1\n\nddcb5d  BIT 3,(IX+d)*\n7e39 511b 3cfa 60d3 0000 0000 0000 0000 d193 3fe9 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb ff 5d -1\nd192 0d -1\n-1\n\nddcb5e  BIT 3,(IX+d)\ncef1 0235 e2b1 7a4c 0000 0000 0000 0000 ed14 d0d6 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 62 5e -1\ned76 a7 -1\n-1\n\nddcb5f  BIT 3,(IX+d)*\n094f 20a8 52e1 d783 0000 0000 0000 0000 df46 da41 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 3f 5f -1\ndf85 9e -1\n-1\n\nddcb60  BIT 4,(IX+d)*\n42ce 0713 dc90 2c89 0000 0000 0000 0000 32a2 c4d4 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 65 60 -1\n3307 2e -1\n-1\n\nddcb61  BIT 4,(IX+d)*\n1b36 1403 8b9b c221 0000 0000 0000 0000 36cb 93d4 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb a8 61 -1\n3673 bc -1\n-1\n\nddcb62  BIT 4,(IX+d)*\n361b 4055 650a 3f98 0000 0000 0000 0000 0acc a102 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb d9 62 -1\n0aa5 ea -1\n-1\n\nddcb63  BIT 4,(IX+d)*\n6548 08df 3ceb 6d24 0000 0000 0000 0000 e679 f98e 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 79 63 -1\ne6f2 83 -1\n-1\n\nddcb64  BIT 4,(IX+d)*\n3c22 e2a7 6da9 c346 0000 0000 0000 0000 ecfb 85b6 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 71 64 -1\ned6c 52 -1\n-1\n\nddcb65  BIT 4,(IX+d)*\n09bd 0abb 3afa 91f5 0000 0000 0000 0000 7779 aef5 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 67 65 -1\n77e0 f5 -1\n-1\n\nddcb66  BIT 4,(IX+d)\nccbc d301 9b66 40fb 0000 0000 0000 0000 ee15 0d23 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 63 66 -1\nee78 70 -1\n-1\n\nddcb67  BIT 4,(IX+d)*\neccb 342f be3e a79b 0000 0000 0000 0000 eea1 dfae 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb d7 67 -1\nee78 06 -1\n-1\n\nddcb68  BIT 5,(IX+d)*\n8e51 0063 49ad b7d4 0000 0000 0000 0000 e968 864e 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb b1 68 -1\ne919 20 -1\n-1\n\nddcb69  BIT 5,(IX+d)*\n9f11 42b5 74fe 1116 0000 0000 0000 0000 33f4 46c2 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb e8 69 -1\n33dc 4f -1\n-1\n\nddcb6a  BIT 5,(IX+d)*\n4632 0bd8 0018 1ac3 0000 0000 0000 0000 86b6 1dd2 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 33 6a -1\n86e9 1c -1\n-1\n\nddcb6b  BIT 5,(IX+d)*\n7a76 f79f a78e f867 0000 0000 0000 0000 187b 0023 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 11 6b -1\n188c bc -1\n-1\n\nddcb6c  BIT 5,(IX+d)*\ndd91 1f1e c1e1 0ea7 0000 0000 0000 0000 3e21 f544 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 5e 6c -1\n3e7f 2a -1\n-1\n\nddcb6d  BIT 5,(IX+d)*\ndebf 9ae4 fd24 b3c2 0000 0000 0000 0000 e314 ad84 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb dd 6d -1\ne2f1 41 -1\n-1\n\nddcb6e  BIT 5,(IX+d)\nca75 9f16 c700 1dce 0000 0000 0000 0000 3086 d68e 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb b2 6e -1\n3038 3f -1\n-1\n\nddcb6f  BIT 5,(IX+d)*\nd4cd 0b39 3e2e c06e 0000 0000 0000 0000 fc1b d592 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb be 6f -1\nfbd9 56 -1\n-1\n\nddcb70  BIT 6,(IX+d)*\nf901 09b8 43f8 2a76 0000 0000 0000 0000 042c 7f2d 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb b5 70 -1\n03e1 74 -1\n-1\n\nddcb71  BIT 6,(IX+d)*\nac78 36ad 34cb f950 0000 0000 0000 0000 1b33 aa23 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb f7 71 -1\n1b2a 08 -1\n-1\n\nddcb72  BIT 6,(IX+d)*\nb1b3 f1e4 9984 c7fb 0000 0000 0000 0000 ce25 c5b6 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 22 72 -1\nce47 08 -1\n-1\n\nddcb73  BIT 6,(IX+d)*\n21ba 592d f406 e21f 0000 0000 0000 0000 6442 cf58 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 12 73 -1\n6454 3c -1\n-1\n\nddcb74  BIT 6,(IX+d)*\n6642 64c1 dbe5 eb48 0000 0000 0000 0000 7dc1 c1fb 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 08 74 -1\n7dc9 be -1\n-1\n\nddcb75  BIT 6,(IX+d)*\n8778 580e 00dd f4c6 0000 0000 0000 0000 60ad 9b60 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 5b 75 -1\n6108 cf -1\n-1\n\nddcb76  BIT 6,(IX+d)\n65b8 5cc2 3058 e258 0000 0000 0000 0000 7e8a b296 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 73 76 -1\n7efd 1e -1\n-1\n\nddcb77  BIT 6,(IX+d)*\ne3a8 47a0 c510 cf0a 0000 0000 0000 0000 0537 b242 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 7f 77 -1\n05b6 97 -1\n-1\n\nddcb78  BIT 7,(IX+d)*\n424f 24f6 1632 8a4f 0000 0000 0000 0000 9397 846c 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 70 78 -1\n9407 76 -1\n-1\n\nddcb79  BIT 7,(IX+d)*\ne6a0 eeaa 41f7 5da2 0000 0000 0000 0000 41de 4189 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb c3 79 -1\n41a1 b8 -1\n-1\n\nddcb7a  BIT 7,(IX+d)*\ncabf 56aa 6a06 6cd7 0000 0000 0000 0000 0aa9 9812 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 3f 7a -1\n0ae8 eb -1\n-1\n\nddcb7b  BIT 7,(IX+d)*\nae3f 0227 721f 52a1 0000 0000 0000 0000 5040 b98a 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 88 7b -1\n4fc8 22 -1\n-1\n\nddcb7c  BIT 7,(IX+d)*\n8a80 a2f1 239a d5cc 0000 0000 0000 0000 6883 b050 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 9e 7c -1\n6821 3a -1\n-1\n\nddcb7d  BIT 7,(IX+d)*\nc37f cf33 1010 98e6 0000 0000 0000 0000 b021 0356 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 29 7d -1\nb04a 2c -1\n-1\n\nddcb7e  BIT 7,(IX+d)\n9a25 2f6e 0d0d a83f 0000 0000 0000 0000 cef0 8c15 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 4f 7e -1\ncf3f f2 -1\n-1\n\nddcb7f  BIT 7,(IX+d)*\n53b9 1f4e 4837 21b6 0000 0000 0000 0000 5ec2 80c3 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 75 7f -1\n5f37 a2 -1\n-1\n\nddcb80  RES 0,(IX+d),B*\n6319 baf9 c84b bcf2 0000 0000 0000 0000 acc5 a4ed 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 70 80 -1\nad35 30 -1\n-1\n\nddcb81  RES 0,(IX+d),C*\nfae1 5ae5 9502 dc9b 0000 0000 0000 0000 bdd3 1a52 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 2a 81 -1\nbdfd 24 -1\n-1\n\nddcb82  RES 0,(IX+d),D*\ndaf6 3260 f1ac 1d47 0000 0000 0000 0000 5e74 35e2 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 9a 82 -1\n5e0e 51 -1\n-1\n\nddcb83  RES 0,(IX+d),E*\n8e7c 5586 8c92 fb00 0000 0000 0000 0000 3441 d365 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 0e 83 -1\n344f 01 -1\n-1\n\nddcb84  RES 0,(IX+d),H*\nc1b3 4874 c535 0e1c 0000 0000 0000 0000 0123 dd28 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 47 84 -1\n016a b0 -1\n-1\n\nddcb85  RES 0,(IX+d),L*\n0928 b0db 4e07 a7b7 0000 0000 0000 0000 0ba3 c61c 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 6c 85 -1\n0c0f de -1\n-1\n\nddcb86  RES 0,(IX+d)\n4515 de09 3ce7 1fde 0000 0000 0000 0000 10c5 33ed 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 5c 86 -1\n1121 7c -1\n-1\n\nddcb87  RES 0,(IX+d),A*\nd05e a733 d1dd 1603 0000 0000 0000 0000 ede6 e5fb 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 02 87 -1\nede8 c4 -1\n-1\n\nddcb88  RES 1,(IX+d),B*\ne4fa 3325 c266 1b13 0000 0000 0000 0000 878e e695 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 9b 88 -1\n8729 7c -1\n-1\n\nddcb89  RES 1,(IX+d),C*\n933b 6fdd a3a8 2634 0000 0000 0000 0000 8f3e 7727 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 2b 89 -1\n8f69 cf -1\n-1\n\nddcb8a  RES 1,(IX+d),D*\n6759 ad1e 5d71 ce52 0000 0000 0000 0000 39a9 38a0 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 0a 8a -1\n39b3 ea -1\n-1\n\nddcb8b  RES 1,(IX+d),E*\n3da2 1833 03c1 07e9 0000 0000 0000 0000 1685 d790 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 62 8b -1\n16e7 8a -1\n-1\n\nddcb8c  RES 1,(IX+d),H*\na625 ed31 3946 32dc 0000 0000 0000 0000 c6a2 7ad6 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb e8 8c -1\nc68a 3e -1\n-1\n\nddcb8d  RES 1,(IX+d),L*\n016b 5802 a683 2549 0000 0000 0000 0000 22e6 33bb 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb cc 8d -1\n22b2 9e -1\n-1\n\nddcb8e  RES 1,(IX+d)\nf4f4 f3a8 2843 82cb 0000 0000 0000 0000 d2e8 d367 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 0a 8e -1\nd2f2 03 -1\n-1\n\nddcb8f  RES 1,(IX+d),A*\n6b1a 8ae2 269b cb2f 0000 0000 0000 0000 3ffe 75dd 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 7b 8f -1\n4079 96 -1\n-1\n\nddcb90  RES 2,(IX+d),B*\nc167 3dfc 42e7 9e14 0000 0000 0000 0000 b501 84fe 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 04 90 -1\nb505 46 -1\n-1\n\nddcb91  RES 2,(IX+d),C*\ne85e cc89 d249 ea3b 0000 0000 0000 0000 c987 c4d1 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 11 91 -1\nc998 83 -1\n-1\n\nddcb92  RES 2,(IX+d),D*\n28a3 85ff ab28 47a5 0000 0000 0000 0000 9166 e755 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 4b 92 -1\n91b1 aa -1\n-1\n\nddcb93  RES 2,(IX+d),E*\n58ac c88b 6d24 dbdd 0000 0000 0000 0000 ac2e 5199 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 03 93 -1\nac31 93 -1\n-1\n\nddcb94  RES 2,(IX+d),H*\ne38d 35a5 8d07 bfb8 0000 0000 0000 0000 5e84 5f24 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 11 94 -1\n5e95 b7 -1\n-1\n\nddcb95  RES 2,(IX+d),L*\n41f4 9536 dd7d 4948 0000 0000 0000 0000 fb74 f17d 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb e6 95 -1\nfb5a c6 -1\n-1\n\nddcb96  RES 2,(IX+d)\n4a9e 42ef 32d7 18cf 0000 0000 0000 0000 7a81 bb1d 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb d5 96 -1\n7a56 ae -1\n-1\n\nddcb97  RES 2,(IX+d),A*\n9ad3 89f0 73c7 0b1a 0000 0000 0000 0000 847c 4b86 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 92 97 -1\n840e 23 -1\n-1\n\nddcb98  RES 3,(IX+d),B*\n6e22 b9fd 9fdc 3aed 0000 0000 0000 0000 041e fd79 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb dc 98 -1\n03fa 58 -1\n-1\n\nddcb99  RES 3,(IX+d),C*\na132 3891 1515 2830 0000 0000 0000 0000 09fd 0473 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 6d 99 -1\n0a6a ce -1\n-1\n\nddcb9a  RES 3,(IX+d),D*\n783d 8f69 91c4 e38f 0000 0000 0000 0000 68a8 391d 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 8a 9a -1\n6832 a8 -1\n-1\n\nddcb9b  RES 3,(IX+d),E*\n955a c7b0 53b3 aec6 0000 0000 0000 0000 06ef e991 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 97 9b -1\n0686 62 -1\n-1\n\nddcb9c  RES 3,(IX+d),H*\naf69 f896 e791 a2ee 0000 0000 0000 0000 847b 59ed 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 54 9c -1\n84cf 1b -1\n-1\n\nddcb9d  RES 3,(IX+d),L*\n7d1e 5009 1248 380c 0000 0000 0000 0000 e920 4fe6 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 0f 9d -1\ne92f e8 -1\n-1\n\nddcb9e  RES 3,(IX+d)\nc207 b47c 0e16 e17f 0000 0000 0000 0000 d8bb bb99 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb b5 9e -1\nd870 ee -1\n-1\n\nddcb9f  RES 3,(IX+d),A*\nc26b 7537 46bb 13c0 0000 0000 0000 0000 e63c 1d98 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb b8 9f -1\ne5f4 a6 -1\n-1\n\nddcba0  RES 4,(IX+d),B*\n0bbe 8500 8609 5352 0000 0000 0000 0000 a2f0 da02 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 02 a0 -1\na2f2 39 -1\n-1\n\nddcba1  RES 4,(IX+d),C*\nad0a aa76 0f2d 832c 0000 0000 0000 0000 45bb a22d 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb f5 a1 -1\n45b0 d2 -1\n-1\n\nddcba2  RES 4,(IX+d),D*\nf586 4a7d a5ab 26fc 0000 0000 0000 0000 628b 6c4d 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 0e a2 -1\n6299 a1 -1\n-1\n\nddcba3  RES 4,(IX+d),E*\nde5b a284 d40e c92d 0000 0000 0000 0000 040d 12c0 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 2e a3 -1\n043b 04 -1\n-1\n\nddcba4  RES 4,(IX+d),H*\ndfaa ae40 02c3 e0b5 0000 0000 0000 0000 fe4d faa3 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 03 a4 -1\nfe50 27 -1\n-1\n\nddcba5  RES 4,(IX+d),L*\n1a15 04cb 4352 ee39 0000 0000 0000 0000 7b27 38a0 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb f6 a5 -1\n7b1d 6b -1\n-1\n\nddcba6  RES 4,(IX+d)\n5e46 b98a b822 04ca 0000 0000 0000 0000 ae1b 8730 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 27 a6 -1\nae42 8f -1\n-1\n\nddcba7  RES 4,(IX+d),A*\n0eed 7b11 8cb0 eb3d 0000 0000 0000 0000 5ec8 97cf 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb f2 a7 -1\n5eba 87 -1\n-1\n\nddcba8  RES 5,(IX+d),B*\n5173 3089 070d e8f9 0000 0000 0000 0000 e84f 55f0 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb d0 a8 -1\ne81f 7e -1\n-1\n\nddcba9  RES 5,(IX+d),C*\n4fb8 ccb5 3e9a 2673 0000 0000 0000 0000 0fdd aef2 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 9d a9 -1\n0f7a 1f -1\n-1\n\nddcbaa  RES 5,(IX+d),D*\nfe76 6f96 3feb 0b21 0000 0000 0000 0000 6747 07ba 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 9f aa -1\n66e6 50 -1\n-1\n\nddcbab  RES 5,(IX+d),E*\n2eb4 36f1 8f44 36af 0000 0000 0000 0000 6682 9d60 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 16 ab -1\n6698 eb -1\n-1\n\nddcbac  RES 5,(IX+d),H*\naf32 8ca8 6558 06d9 0000 0000 0000 0000 a4dd cd1f 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb c4 ac -1\na4a1 44 -1\n-1\n\nddcbad  RES 5,(IX+d),L*\nfcc9 69a7 0eed eab5 0000 0000 0000 0000 eef5 3ed2 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 49 ad -1\nef3e 76 -1\n-1\n\nddcbae  RES 5,(IX+d)\n5f7a 9c20 f013 c4b7 0000 0000 0000 0000 b306 15dd 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 6e ae -1\nb374 5a -1\n-1\n\nddcbaf  RES 5,(IX+d),A*\nb11e 2583 51fa d427 0000 0000 0000 0000 3619 9cef 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb c2 af -1\n35db 15 -1\n-1\n\nddcbb0  RES 6,(IX+d),B*\nf43e ce57 3bf3 0933 0000 0000 0000 0000 58d7 d89f 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 47 b0 -1\n591e 1e -1\n-1\n\nddcbb1  RES 6,(IX+d),C*\n35ef bbbc db46 046c 0000 0000 0000 0000 add2 2b6e 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 86 b1 -1\nad58 46 -1\n-1\n\nddcbb2  RES 6,(IX+d),D*\nc26c fd32 9b7f ab6c 0000 0000 0000 0000 e7d0 501f 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 70 b2 -1\ne840 48 -1\n-1\n\nddcbb3  RES 6,(IX+d),E*\n36ca b434 e212 f805 0000 0000 0000 0000 53fb b191 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb de b3 -1\n53d9 06 -1\n-1\n\nddcbb4  RES 6,(IX+d),H*\n0a1c ab67 9ca1 2f98 0000 0000 0000 0000 5066 320c 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 6b b4 -1\n50d1 dd -1\n-1\n\nddcbb5  RES 6,(IX+d),L*\nfd6d 51c9 16d6 1373 0000 0000 0000 0000 146e 2148 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb ec b5 -1\n145a d6 -1\n-1\n\nddcbb6  RES 6,(IX+d)\n1d0b 04e8 109e 1dde 0000 0000 0000 0000 8772 8661 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 15 b6 -1\n8787 8c -1\n-1\n\nddcbb7  RES 6,(IX+d),A*\nf012 b87e 65ba a5c8 0000 0000 0000 0000 6120 789d 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb d3 b7 -1\n60f3 54 -1\n-1\n\nddcbb8  RES 7,(IX+d),B*\n8eae 4a53 bfa1 5e7e 0000 0000 0000 0000 0bf6 1e35 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 13 b8 -1\n0c09 87 -1\n-1\n\nddcbb9  RES 7,(IX+d),C*\n5fb7 a81e e2d2 4117 0000 0000 0000 0000 0564 48a1 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 56 b9 -1\n05ba c8 -1\n-1\n\nddcbba  RES 7,(IX+d),D*\n7f6a 47fe ce45 75de 0000 0000 0000 0000 f5e0 032c 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 86 ba -1\nf566 30 -1\n-1\n\nddcbbb  RES 7,(IX+d),E*\nc7e3 e49e 9ec5 07e7 0000 0000 0000 0000 bd31 9d5f 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb ef bb -1\nbd20 c9 -1\n-1\n\nddcbbc  RES 7,(IX+d),H*\nb430 7ac7 b45f fbf7 0000 0000 0000 0000 638e 3173 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb c0 bc -1\n634e 28 -1\n-1\n\nddcbbd  RES 7,(IX+d),L*\n4e71 6ffa a3f9 a2e5 0000 0000 0000 0000 e3c4 02d4 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb b9 bd -1\ne37d dd -1\n-1\n\nddcbbe  RES 7,(IX+d)\n4af8 99a5 d6fd 7a16 0000 0000 0000 0000 58d3 ce54 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 4d be -1\n5920 e8 -1\n-1\n\nddcbbf  RES 7,(IX+d),A*\n6e31 0320 134b 77c3 0000 0000 0000 0000 1734 bc2d 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 26 bf -1\n175a e2 -1\n-1\n\nddcbc0  SET 0,(IX+d),B*\n75be 2b93 093d 1128 0000 0000 0000 0000 792e 31f7 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 00 c0 -1\n792e 92 -1\n-1\n\nddcbc1  SET 0,(IX+d),C*\n313f 8223 5fcc 42c8 0000 0000 0000 0000 dccc d87b 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb f7 c1 -1\ndcc3 1c -1\n-1\n\nddcbc2  SET 0,(IX+d),D*\na7e3 bf55 d27b 0a9d 0000 0000 0000 0000 0cfa ea4e 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 85 c2 -1\n0c7f 30 -1\n-1\n\nddcbc3  SET 0,(IX+d),E*\ne076 2760 1eec 9968 0000 0000 0000 0000 5426 a1a0 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 32 c3 -1\n5458 dd -1\n-1\n\nddcbc4  SET 0,(IX+d),H*\na679 cc05 3f4d c899 0000 0000 0000 0000 7acd 48d7 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb ae c4 -1\n7a7b 27 -1\n-1\n\nddcbc5  SET 0,(IX+d),L*\nddfd 64d4 2671 35e7 0000 0000 0000 0000 ba99 bd98 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 9c c5 -1\nba35 20 -1\n-1\n\nddcbc6  SET 0,(IX+d)\nb324 dc0c 1e35 8cd5 0000 0000 0000 0000 ab2c b6f3 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb c4 c6 -1\naaf0 b8 -1\n-1\n\nddcbc7  SET 0,(IX+d),A*\na254 9e56 6828 3189 0000 0000 0000 0000 64cb dfad 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb f8 c7 -1\n64c3 94 -1\n-1\n\nddcbc8  SET 1,(IX+d),B*\n8aca 139e e652 248b 0000 0000 0000 0000 6e7a 189a 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 65 c8 -1\n6edf 8f -1\n-1\n\nddcbc9  SET 1,(IX+d),C*\nf15f 856e a21f 8a59 0000 0000 0000 0000 b670 4f79 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb fb c9 -1\nb66b b9 -1\n-1\n\nddcbca  SET 1,(IX+d),D*\ndfab a031 1d78 ad3a 0000 0000 0000 0000 a887 7334 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 8a ca -1\na811 7e -1\n-1\n\nddcbcb  SET 1,(IX+d),E*\nebd6 376e c346 b10c 0000 0000 0000 0000 a447 31d6 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb a4 cb -1\na3eb 73 -1\n-1\n\nddcbcc  SET 1,(IX+d),H*\n0212 dc46 8f41 854e 0000 0000 0000 0000 1f5a 07ca 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 65 cc -1\n1fbf 72 -1\n-1\n\nddcbcd  SET 1,(IX+d),L*\n3344 d73c d6b8 929d 0000 0000 0000 0000 5376 6d3a 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb e9 cd -1\n535f 1c -1\n-1\n\nddcbce  SET 1,(IX+d)\n9e47 fc93 9ffc aace 0000 0000 0000 0000 0313 7f66 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 85 ce -1\n0298 10 -1\n-1\n\nddcbcf  SET 1,(IX+d),A*\n53e8 d379 87d5 10b0 0000 0000 0000 0000 c5d0 4f7f 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb e2 cf -1\nc5b2 b5 -1\n-1\n\nddcbd0  SET 2,(IX+d),B*\n3278 6114 d25d 1cf8 0000 0000 0000 0000 ad43 99fc 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 7f d0 -1\nadc2 51 -1\n-1\n\nddcbd1  SET 2,(IX+d),C*\nc0b8 371a 6472 d92d 0000 0000 0000 0000 10b2 3074 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb a6 d1 -1\n1058 2c -1\n-1\n\nddcbd2  SET 2,(IX+d),D*\n5bb6 caa8 e0db af84 0000 0000 0000 0000 b9a1 7b5f 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 9c d2 -1\nb93d 9c -1\n-1\n\nddcbd3  SET 2,(IX+d),E*\ndb6a 4fe2 9e52 a034 0000 0000 0000 0000 da36 88a0 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb bd d3 -1\nd9f3 60 -1\n-1\n\nddcbd4  SET 2,(IX+d),H*\ncc1c b884 6ad2 1621 0000 0000 0000 0000 ef26 41de 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 58 d4 -1\nef7e 5e -1\n-1\n\nddcbd5  SET 2,(IX+d),L*\nc41d c8b0 cacb 7687 0000 0000 0000 0000 8dbc cc25 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 41 d5 -1\n8dfd 71 -1\n-1\n\nddcbd6  SET 2,(IX+d)\n09eb 769d 7e07 51f9 0000 0000 0000 0000 5f03 6280 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb ea d6 -1\n5eed 73 -1\n-1\n\nddcbd7  SET 2,(IX+d),A*\n241b ee10 c152 2f6d 0000 0000 0000 0000 e725 c0d7 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 80 d7 -1\ne6a5 60 -1\n-1\n\nddcbd8  SET 3,(IX+d),B*\ne3dc 1981 c97b cb42 0000 0000 0000 0000 b30f b32a 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 4c d8 -1\nb35b 96 -1\n-1\n\nddcbd9  SET 3,(IX+d),C*\ne9a0 a7c7 a476 6057 0000 0000 0000 0000 2642 58a0 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 52 d9 -1\n2694 ef -1\n-1\n\nddcbda  SET 3,(IX+d),D*\n6787 26a7 a194 11d3 0000 0000 0000 0000 2d76 7f80 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb ea da -1\n2d60 82 -1\n-1\n\nddcbdb  SET 3,(IX+d),E*\nf986 6a4b 6588 d2c8 0000 0000 0000 0000 2b7d 5847 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 4d db -1\n2bca 10 -1\n-1\n\nddcbdc  SET 3,(IX+d),H*\n4c9e d94d 9760 b707 0000 0000 0000 0000 7ed4 5cc5 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb d3 dc -1\n7ea7 45 -1\n-1\n\nddcbdd  SET 3,(IX+d),L*\n4b3b d351 9be9 2310 0000 0000 0000 0000 58c1 e430 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 6f dd -1\n5930 20 -1\n-1\n\nddcbde  SET 3,(IX+d)\n3b62 ca1e a41a 227a 0000 0000 0000 0000 89d2 7011 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 14 de -1\n89e6 5e -1\n-1\n\nddcbdf  SET 3,(IX+d),A*\n4c8a 5b42 50dd 4be0 0000 0000 0000 0000 d227 4913 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb ef df -1\nd216 72 -1\n-1\n\nddcbe0  SET 4,(IX+d),B*\n440a 713d acfc f762 0000 0000 0000 0000 1c4b b6ba 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 62 e0 -1\n1cad 46 -1\n-1\n\nddcbe1  SET 4,(IX+d),C*\nc219 aa6b dfbf 6f10 0000 0000 0000 0000 b931 d3d6 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 2e e1 -1\nb95f 75 -1\n-1\n\nddcbe2  SET 4,(IX+d),D*\n66d7 abd0 cb48 8054 0000 0000 0000 0000 ef50 9997 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 85 e2 -1\need5 72 -1\n-1\n\nddcbe3  SET 4,(IX+d),E*\n7013 e7ed 7e1c 57fb 0000 0000 0000 0000 7ec6 75eb 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb f4 e3 -1\n7eba 34 -1\n-1\n\nddcbe4  SET 4,(IX+d),H*\n1108 6e70 f0af 2f0c 0000 0000 0000 0000 95c7 6501 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb bf e4 -1\n9586 34 -1\n-1\n\nddcbe5  SET 4,(IX+d),L*\n57cc 5511 2696 b83d 0000 0000 0000 0000 6ab0 0e90 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb f2 e5 -1\n6aa2 2e -1\n-1\n\nddcbe6  SET 4,(IX+d)\n207a a441 1e03 ac60 0000 0000 0000 0000 d866 5fdc 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 25 e6 -1\nd88b 4c -1\n-1\n\nddcbe7  SET 4,(IX+d),A*\nc3c5 7fa9 4e07 e02d 0000 0000 0000 0000 2a1b 55b7 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb f3 e7 -1\n2a0e eb -1\n-1\n\nddcbe8  SET 5,(IX+d),B*\n6d1c a0c4 93f0 a0b4 0000 0000 0000 0000 4bda 7761 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb f2 e8 -1\n4bcc ba -1\n-1\n\nddcbe9  SET 5,(IX+d),C*\nebe5 0c2c 1a2a 2720 0000 0000 0000 0000 72dd a354 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 8a e9 -1\n7267 0a -1\n-1\n\nddcbea  SET 5,(IX+d),D*\n42d2 da7a 757f 6da6 0000 0000 0000 0000 a7e9 b933 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 04 ea -1\na7ed 5f -1\n-1\n\nddcbeb  SET 5,(IX+d),E*\ne945 10aa f5f8 7647 0000 0000 0000 0000 16df 93fb 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 24 eb -1\n1703 f3 -1\n-1\n\nddcbec  SET 5,(IX+d),H*\n7180 bc85 7dd3 f467 0000 0000 0000 0000 dd88 6a41 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 60 ec -1\ndde8 00 -1\n-1\n\nddcbed  SET 5,(IX+d),L*\n6b2f 9762 1f0a db61 0000 0000 0000 0000 f772 33e3 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb be ed -1\nf730 6b -1\n-1\n\nddcbee  SET 5,(IX+d)\n79ea dc8a 7887 3baa 0000 0000 0000 0000 6c28 abbc 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb de ee -1\n6c06 bd -1\n-1\n\nddcbef  SET 5,(IX+d),A*\n46c3 2fc2 8690 a836 0000 0000 0000 0000 cc68 a8ce 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 30 ef -1\ncc98 11 -1\n-1\n\nddcbf0  SET 6,(IX+d),B*\nb330 4469 362b b515 0000 0000 0000 0000 13c0 6479 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 2f f0 -1\n13ef ad -1\n-1\n\nddcbf1  SET 6,(IX+d),C*\n94c0 9ab0 a0fd 7c1d 0000 0000 0000 0000 47ba 8c81 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 40 f1 -1\n47fa 78 -1\n-1\n\nddcbf2  SET 6,(IX+d),D*\n5302 9204 20ec d640 0000 0000 0000 0000 c947 4ef1 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 0f f2 -1\nc956 21 -1\n-1\n\nddcbf3  SET 6,(IX+d),E*\n9950 a3d2 5058 5ccc 0000 0000 0000 0000 1d96 7c75 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 06 f3 -1\n1d9c e4 -1\n-1\n\nddcbf4  SET 6,(IX+d),H*\n3712 1f99 4863 47de 0000 0000 0000 0000 1702 c042 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 3b f4 -1\n173d e1 -1\n-1\n\nddcbf5  SET 6,(IX+d),L*\nd83f 1ec9 d0da 4173 0000 0000 0000 0000 eb3f 1ead 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 64 f5 -1\neba3 c5 -1\n-1\n\nddcbf6  SET 6,(IX+d)\n4d6c 93ac 810d cfe1 0000 0000 0000 0000 dc5a c33c 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 7b f6 -1\ndcd5 a2 -1\n-1\n\nddcbf7  SET 6,(IX+d),A*\nfe40 7887 b9de c013 0000 0000 0000 0000 301e 9710 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb c3 f7 -1\n2fe1 a9 -1\n-1\n\nddcbf8  SET 7,(IX+d),B*\n8278 21a4 1e5c 4952 0000 0000 0000 0000 427f 41e1 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 59 f8 -1\n42d8 28 -1\n-1\n\nddcbf9  SET 7,(IX+d),C*\nb2df e9b8 56c3 16ff 0000 0000 0000 0000 d88f 0bab 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 55 f9 -1\nd8e4 14 -1\n-1\n\nddcbfa  SET 7,(IX+d),D*\n01f1 bc0d d476 1510 0000 0000 0000 0000 9420 93a3 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 74 fa -1\n9494 fe -1\n-1\n\nddcbfb  SET 7,(IX+d),E*\n709b 14eb ec1c b844 0000 0000 0000 0000 3453 f2b0 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb af fb -1\n3402 02 -1\n-1\n\nddcbfc  SET 7,(IX+d),H*\n6c89 a96e d27b d6a7 0000 0000 0000 0000 6139 b4c1 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb a1 fc -1\n60da 10 -1\n-1\n\nddcbfd  SET 7,(IX+d),L*\nfb3f 83f6 2094 3349 0000 0000 0000 0000 3ed0 6f0e 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb 28 fd -1\n3ef8 c2 -1\n-1\n\nddcbfe  SET 7,(IX+d)\nfc42 50b7 e98d 3e45 0000 0000 0000 0000 41b5 3410 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb ec fe -1\n41a1 a1 -1\n-1\n\nddcbff  SET 7,(IX+d),A*\ne666 94d2 ac90 8f45 0000 0000 0000 0000 0655 ba29 0000 0000\n00 00 0 0 0 0     1\n0000 dd cb d3 ff -1\n0628 2b -1\n-1\n\ndde1    POP IX\n8a15 6bf0 0106 3dd0 0000 0000 0000 0000 5da4 8716 595f 0000\n00 00 0 0 0 0     1\n0000 dd e1 -1\n595f 9a 09 -1\n-1\n\ndde3    EX (SP),IX\n068e 58e6 2713 500f 0000 0000 0000 0000 be05 4308 57bd 0000\n00 00 0 0 0 0     1\n0000 dd e3 -1\n57bd 15 3f -1\n-1\n\ndde5    PUSH IX\n7462 9b6c bfe5 0330 0000 0000 0000 0000 b282 e272 0761 0000\n00 00 0 0 0 0     1\n0000 dd e5 -1\n-1\n\ndde9    JP (IX)\n75a7 139b f9a3 94bb 0000 0000 0000 0000 64f0 3433 0000 0000\n00 00 0 0 0 0     1\n0000 dd e9 -1\n-1\n\nddf9    LD SP,IX\n8709 15dd 7fa6 3c5c 0000 0000 0000 0000 d3a7 1d7b f67c 0000\n00 00 0 0 0 0     1\n0000 dd f9 -1\n-1\n\nddfd00\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0    13\n0000 dd fd 00 00 -1\n-1\n\nde      SBC A,n\ne78d 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 de a1 -1\n-1\n\ndf      RST 18H\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 5507 6d33\n00 00 0 0 0 0     1\n6d33 df -1\n-1\n\ne0_1    RET PO\n0098 0000 0000 0000 0000 0000 0000 0000 0000 0000 43f7 0000\n00 00 0 0 0 0     1\n0000 e0 -1\n43f7 e9 af -1\n-1\n\ne0_2    RET PO\n009c 0000 0000 0000 0000 0000 0000 0000 0000 0000 43f7 0000\n00 00 0 0 0 0     1\n0000 e0 -1\n43f7 e9 af -1\n-1\n\ne1      POP HL\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4143 0000\n00 00 0 0 0 0     1\n0000 e1 -1\n4143 ce e8 -1\n-1\n\ne2_1    JP PO,nn\n0083 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 e2 1b e1 -1\n-1\n\ne2_2    JP PO,nn\n0087 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 e2 1b e1 -1\n-1\n\ne3      EX (SP),HL\n0000 0000 0000 4d22 0000 0000 0000 0000 0000 0000 0373 0000\n00 00 0 0 0 0     1\n0000 e3 -1\n0373 8e e1 -1\n-1\n\ne4_1    CALL PO,nn\n000a 0000 0000 0000 0000 0000 0000 0000 0000 0000 5698 0000\n00 00 0 0 0 0     1\n0000 e4 61 9c -1\n-1\n\ne4_2    CALL PO,nn\n000e 0000 0000 0000 0000 0000 0000 0000 0000 0000 5698 0000\n00 00 0 0 0 0     1\n0000 e4 61 9c -1\n-1\n\ne5      PUSH HL\n53e3 1459 775f 1a2f 0000 0000 0000 0000 0000 0000 ec12 0000\n00 00 0 0 0 0     1\n0000 e5 -1\n-1\n\ne6      AND n\n7500 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 e6 49 -1\n-1\n\ne7      RST 20H\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 5507 6d33\n00 00 0 0 0 0     1\n6d33 e7 -1\n-1\n\ne8_1    RET PE\n0098 0000 0000 0000 0000 0000 0000 0000 0000 0000 43f7 0000\n00 00 0 0 0 0     1\n0000 e8 -1\n43f7 e9 af -1\n-1\n\ne8_2    RET PE\n009c 0000 0000 0000 0000 0000 0000 0000 0000 0000 43f7 0000\n00 00 0 0 0 0     1\n0000 e8 -1\n43f7 e9 af -1\n-1\n\ne9      JP (HL)\n0000 0000 0000 caba 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 e9 -1\n-1\n\nea_1    JP PE,nn\n0087 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ea 1b e1 -1\n-1\n\nea_2    JP PE,nn\n0083 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ea 1b e1 -1\n-1\n\neb      EX DE,HL\n0000 0000 b879 942e 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 eb -1\n-1\n\nec_1    CALL PE,nn\n000e 0000 0000 0000 0000 0000 0000 0000 0000 0000 5698 0000\n00 00 0 0 0 0     1\n0000 ec 61 9c -1\n-1\n\nec_2    CALL PE,nn\n000a 0000 0000 0000 0000 0000 0000 0000 0000 0000 5698 0000\n00 00 0 0 0 0     1\n0000 ec 61 9c -1\n-1\n\ned40    IN B,(C)\n83f9 296b 7034 1f2f 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed 40 -1\n-1\n\ned41    OUT (C),B\n29a2 0881 d7dd ff4e 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed 41 -1\n-1\n\ned42    SBC HL,BC\ncbd3 1c8f d456 315e 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed 42 -1\n-1\n\ned43    LD (nn),BC\nda36 2732 91cc 9798 0000 0000 0000 0000 0000 0000 5f73  0000\n00 00 0 0 0 0     1\n0000 ed 43 c6 54 -1\n-1\n\ned44    NEG\nfe2b 040f deb6 afc3 0000 0000 0000 0000 0000 0000 5ca8  0000\n00 00 0 0 0 0     1\n0000 ed 44 -1\n-1\n\ned45    RETN\n001d 5b63 a586 1451 0000 0000 0000 0000 0000 0000 3100  0000\n00 00 0 1 0 0     1\n0000 ed 45 -1\n3100 1f 22 -1\n-1\n\ned46    IM 0\nb6ec 8afb ce09 70a1 0000 0000 0000 0000 0000 0000 8dea  0000\n00 00 0 0 0 0     1\n0000 ed 46 -1\n-1\n\ned47    LD I,A\n9a99 9e5a 9913 cacc 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed 47 -1\n-1\n\ned48    IN C,(C)\ndbdd 7d1b 141d 5fb4 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed 48 -1\n-1\n\ned49    OUT (C),C\n07a5 59ec f459 4316 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed 49 -1\n-1\n\ned4a    ADC HL,BC\n5741 24b5 83d2 9ac8 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed 4a -1\n-1\n\ned4b    LD BC,(nn)\n650c d74d 0448 a3b9 0000 0000 0000 0000 0000 0000 b554  0000\n00 00 0 0 0 0     1\n0000 ed 4b 1a a4 -1\na41a f3 d4 -1\n-1\n\ned4c    NEG*\n5682 7dde b049 939d 0000 0000 0000 0000 0000 0000 c7bb  0000\n00 00 0 0 0 0     1\n0000 ed 4c -1\n-1\n\ned4d    RETI\n1bed c358 5fd5 6093 0000 0000 0000 0000 0000 0000 680e  0000\n00 00 0 0 0 0     1\n0000 ed 4d -1\n680e 03 7c -1\n-1\n\ned4e    IM 0*\n8e01 e7c6 880f d2a2 0000 0000 0000 0000 0000 0000 85da  0000\n00 00 0 0 1 0     1\n0000 ed 4e -1\n-1\n\ned4f    LD R,A\n2ae3 c115 eff8 9f6d 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed 4f -1\n-1\n\ned50    IN D,(C)\n85ae bbcc e2a8 f219 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed 50 -1\n-1\n\ned51    OUT (C),D\n2c4c c0a4 5303 bc25 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed 51 -1\n-1\n\ned52    SBC HL,DE\nfc57 1fc8 47b6 da7c 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed 52 -1\n-1\n\ned53    LD (nn),DE\n1f88 4692 5cb2 4915 0000 0000 0000 0000 0000 0000 7d8c  0000\n00 00 0 0 0 0     1\n0000 ed 53 ff 21 -1\n-1\n\ned54    NEG*\nadf9 5661 547c c322 0000 0000 0000 0000 0000 0000 d9eb  0000\n00 00 0 0 0 0     1\n0000 ed 54 -1\n-1\n\ned55    RETN*\nb05b 5e84 d6e9 cb3e 0000 0000 0000 0000 0000 0000 d4b4  0000\n00 00 1 0 0 0     1\n0000 ed 55 -1\nd4b4 ea c9 -1\n-1\n\ned56    IM 1\n5cc0 9100 356b 4bfd 0000 0000 0000 0000 0000 0000 2c93  0000\n00 00 0 0 1 0     1\n0000 ed 56 -1\n-1\n\ned57    LD A,I\nbcfe dfc7 a621 1022 0000 0000 0000 0000 0000 0000 0000 0000\n1e 17 0 0 0 0     1\n0000 ed 57 -1\n-1\n\ned58    IN E,(C)\nc9ee 4091 9e46 873a 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed 58 -1\n-1\n\ned59    OUT (C),E\n388a d512 ecc5 93af 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed 59 -1\n-1\n\ned5a    ADC HL,DE\na41f 751c 19ce 0493 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed 5a -1\n-1\n\ned5b    LD DE,(nn)\n5df1 982e 002f adb9 0000 0000 0000 0000 0000 0000 f398  0000\n00 00 0 0 0 0     1\n0000 ed 5b 04 9f -1\n9f04 84 4d -1\n-1\n\ned5c    NEG*\n11c3 b86c 2042 c958 0000 0000 0000 0000 0000 0000 93dc  0000\n00 00 0 0 0 0     1\n0000 ed 5c -1\n-1\n\ned5d    RETN*\n1152 1d20 3f86 64fc 0000 0000 0000 0000 0000 0000 5308  0000\n00 00 0 0 0 0     1\n0000 ed 5d -1\n5308 26 e0 -1\n-1\n\ned5e    IM 2\n611a c8cf f215 d92b 0000 0000 0000 0000 0000 0000 4d86  0000\n00 00 0 0 1 0     1\n0000 ed 5e -1\n-1\n\ned5f    LD A,R\n1bb5 fc09 2dfa bab9 0000 0000 0000 0000 0000 0000 0000 0000\nd7 f3 0 0 0 0     1\n0000 ed 5f -1\n-1\n\ned60    IN H,(C)\n2c9c 0dae 621e 2f66 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed 60 -1\n-1\n\ned61    OUT (C),H\nffa8 90ca 0340 d847 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed 61 -1\n-1\n\ned62    SBC HL,HL\na60b d9aa 6623 0b1a 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed 62 -1\n-1\n\ned62_1  SBC HL,HL\n89d2 1563 7e1f b339 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed 62 -1\n-1\n\ned63    LD (nn),HL\n5222 88f9 9d9a e4d3 0000 0000 0000 0000 0000 0000 a2f0  0000\n00 00 0 0 0 0     1\n0000 ed 63 67 65 -1\n-1\n\ned64    NEG*\n2127 e425 66ac b2a3 0000 0000 0000 0000 0000 0000 43f2  0000\n00 00 0 0 0 0     1\n0000 ed 64 -1\n-1\n\ned65    RETN*\n63d2 1fa1 0788 881c 0000 0000 0000 0000 0000 0000 f207  0000\n00 00 0 1 0 0     1\n0000 ed 65 -1\nf207 eb 0e -1\n-1\n\ned66    IM 0*\n4088 a7e1 3ffd 919b 0000 0000 0000 0000 0000 0000 d193  0000\n00 00 0 0 1 0     1\n0000 ed 66 -1\n-1\n\ned67    RRD\n3624 b16a a4db b9de 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed 67 -1\nb9de 93 -1\n-1\n\ned68    IN L,(C)\n5316 624b 7311 3106 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed 68 -1\n-1\n\ned69    OUT (C),L\nabd8 8d2f 89c7 c3d6 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed 69 -1\n-1\n\ned6a    ADC HL,HL\nbb5a 6fed 59bb 4e40 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed 6a -1\n-1\n\ned6b    LD HL,(nn)\n9e35 d240 1998 ab19 0000 0000 0000 0000 0000 0000 9275  0000\n00 00 0 0 0 0     1\n0000 ed 6b 98 61 -1\n6198 3f be -1\n-1\n\ned6c    NEG*\n0fb1 7d5b cadb 0893 0000 0000 0000 0000 0000 0000 d983  0000\n00 00 0 0 0 0     1\n0000 ed 6c -1\n-1\n\ned6d    RETN*\n3860 42da 5935 dc10 0000 0000 0000 0000 0000 0000 5cd3  0000\n00 00 0 0 0 0     1\n0000 ed 6d -1\n5cd3 a9 73 -1\n-1\n\ned6e    IM 0*\n7752 bec3 0457 8c95 0000 0000 0000 0000 0000 0000 a787  0000\n00 00 0 0 0 0     1\n0000 ed 6e -1\n-1\n\ned6f    RLD\n658b 7a7a ecf0 403c 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed 6f -1\n403c c4 -1\n-1\n\ned70    IN F,(C)*\nc6a1 f7d6 a3cb 288d 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed 70 -1\n-1\n\ned71    OUT (C),0*\nafa0 20b3 7b33 4ac1 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed 71 -1\n-1\n\ned72    SBC HL,SP\n5fd9 05cb 0c6c d18b 0000 0000 0000 0000 0000 0000 53db 0000\n00 00 0 0 0 0     1\n0000 ed 72 -1\n-1\n\ned73    LD (nn),SP\n41c4 763a ecb0 ee62 0000 0000 0000 0000 0000 0000 aed5  0000\n00 00 0 0 0 0     1\n0000 ed 73 2a 79 -1\n-1\n\ned74    NEG*\n4454 f2d2 8340 7e76 0000 0000 0000 0000 0000 0000 0323  0000\n00 00 0 0 0 0     1\n0000 ed 74 -1\n-1\n\ned75    RETN*\n7ca4 1615 5d2a a95b 0000 0000 0000 0000 0000 0000 7d00  0000\n00 00 1 1 0 0     1\n0000 ed 75 -1\n7d00 fd 4f -1\n-1\n\ned76    IM 1*\ncabf ff9a b98c a8e6 0000 0000 0000 0000 0000 0000 fe8e  0000\n00 00 0 0 2 0     1\n0000 ed 76 -1\n-1\n\ned78    IN A,(C)\n58dd f206 2d6a af16 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed 78 -1\n-1\n\ned79    OUT (C),A\ne000 4243 8f7f ed90 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed 79 -1\n-1\n\ned7a    ADC HL,SP\n32fd d819 d873 8dcf 0000 0000 0000 0000 0000 0000 5d22 0000\n00 00 0 0 0 0     1\n0000 ed 7a -1\n-1\n\ned7b    LD SP,(nn)\n4f97 24b7 e105 1bf2 0000 0000 0000 0000 0000 0000 5e17  0000\n00 00 0 0 0 0     1\n0000 ed 7b 50 8c -1\n8c50 d8 48 -1\n-1\n\ned7c    NEG*\nd333 29ca 9622 b452 0000 0000 0000 0000 0000 0000 0be6  0000\n00 00 0 0 0 0     1\n0000 ed 7c -1\n-1\n\ned7d    RETN*\necb6 073e dc1e 38d9 0000 0000 0000 0000 0000 0000 66f0  0000\n00 00 0 1 0 0     1\n0000 ed 7d -1\n66f0 4f fb -1\n-1\n\ned7e    IM 2*\nb246 1a1a 933a 4b8b 0000 0000 0000 0000 0000 0000 2242  0000\n00 00 0 0 0 0     1\n0000 ed 7e -1\n-1\n\neda0    LDI\n1bc9 3d11 95c1 d097 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed a0 -1\nd097 b7 -1\n-1\n\neda1    CPI\necdb 7666 537f 3bc3 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed a1 -1\n3bc3 b4 -1\n-1\n\neda2    INI\n0121 9a82 5bbd 2666 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed a2 -1\n-1\n\neda2_01 INI\n0000 0200 0000 8000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed a2 -1\n-1\n\neda2_02 INI\n0000 569a 0000 8000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed a2 -1\n-1\n\neda2_03 INI\n0000 abcc 0000 8000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed a2 -1\n-1\n\neda3    OUTI\n42c5 6334 1e28 32fa 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed a3 -1\n32fa b3 -1\n-1\n\neda3_01 OUTI\n0000 0100 0000 01ff 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed a3 -1\n01ff 00 -1\n-1\n\neda3_02 OUTI\n0000 0100 0000 0100 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed a3 -1\n0100 00 -1\n-1\n\neda3_03 OUTI\n0000 0100 0000 0107 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed a3 -1\n0107 00 -1\n-1\n\neda3_04 OUTI\n0000 0100 0000 01ff 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed a3 -1\n01ff 80 -1\n-1\n\neda3_05 OUTI\n0000 0100 0000 01fd 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed a3 -1\n01fd 12 -1\n-1\n\neda3_06 OUTI\n0000 0100 0000 01fe 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed a3 -1\n01fe 12 -1\n-1\n\neda3_07 OUTI\n0000 0200 0000 01ff 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed a3 -1\n01ff 00 -1\n-1\n\neda3_08 OUTI\n0000 0800 0000 01fe 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed a3 -1\n01fe 00 -1\n-1\n\neda3_09 OUTI\n0000 8100 0000 01ff 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed a3 -1\n01ff 00 -1\n-1\n\neda3_10 OUTI\n0000 8200 0000 01ff 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed a3 -1\n01ff 00 -1\n-1\n\neda3_11 OUTI\n0000 a900 0000 01ff 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed a3 -1\n01ff 00 -1\n-1\n\neda8    LDD\n2a8e 1607 5938 12e8 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed a8 -1\n12e8 d8 -1\n-1\n\neda9    CPD\n1495 fb42 0466 0dbe 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed a9 -1\n0dbe 89 -1\n-1\n\nedaa    IND\n2042 d791 a912 a533 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed aa -1\n-1\n\nedaa_01 IND\n0000 0101 0000 8000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed aa -1\n-1\n\nedaa_02 IND\n0000 56aa 0000 8000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed aa -1\n-1\n\nedaa_03 IND\n0000 abcc 0000 8000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed aa -1\n-1\n\nedab    OUTD\n0037 f334 d3e1 199f 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed ab -1\n199f 49 -1\n-1\n\nedab_01 OUTD\n0000 5800 0000 007a 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed ab -1\n007a 7f -1\n-1\n\nedab_02 OUTD\n0000 ab00 0000 00f1 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ed ab -1\n00f1 cd -1\n-1\n\nedb0    LDIR\n1045 0010 aad8 558e 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0   331\n0000 ed b0 -1\n558e 53 94 30 05 44 24 22 b9 e9 77 23 71 e2 5c fb 49 -1\n-1\n\nedb1    CPIR\nf4dd 0008 e4e0 9825 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0    79\n0000 ed b1 -1\n9825 50 e5 41 f4 01 9f 11 85 -1\n-1\n\nedb2    INIR\n8a34 0a40 d98c 37ce 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0   205\n0000 ed b2 -1\n-1\n\nedb3    OTIR\n34ab 03e0 41b9 1d7c 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0    58\n0000 ed b3 -1\n1d7c 9d 24 aa -1\n-1\n\nedb8    LDDR\ne553 0008 68e8 4dcf 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0   163\n0000 ed b8 -1\n4dc8 29 85 a7 c3 55 74 23 0a -1\n-1\n\nedb9    CPDR\nffcd 0008 a171 c749 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0   163\n0000 ed b9 -1\nc742 c6 09 85 ec 5a 01 4e 6c -1\n-1\n\nedba    INDR\n2567 069f d40d 6b55 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0   121\n0000 ed ba -1\n-1\n\nedbb    OTDR\n09c4 043b be49 1dd0 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0    79\n0000 ed bb -1\n1dcd f9 71 c5 b6 -1\n-1\n\nee      XOR n\n3e00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 ee d0 -1\n-1\n\nef      RST 28H\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 5507 6d33\n00 00 0 0 0 0     1\n6d33 ef -1\n-1\n\nf0_1    RET P\n0018 0000 0000 0000 0000 0000 0000 0000 0000 0000 43f7 0000\n00 00 0 0 0 0     1\n0000 f0 -1\n43f7 e9 af -1\n-1\n\nf0_2    RET P\n0098 0000 0000 0000 0000 0000 0000 0000 0000 0000 43f7 0000\n00 00 0 0 0 0     1\n0000 f0 -1\n43f7 e9 af -1\n-1\n\nf1      POP AF\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4143 0000\n00 00 0 0 0 0     1\n0000 f1 -1\n4143 ce e8 -1\n-1\n\nf2_1    JP P,nn\n0007 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 f2 1b e1 -1\n-1\n\nf2_2    JP P,nn\n0087 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 f2 1b e1 -1\n-1\n\nf3      DI\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 1 1 0 0     1\n0000 f3 -1\n-1\n\nf4_1    CALL P,nn\n000e 0000 0000 0000 0000 0000 0000 0000 0000 0000 5698 0000\n00 00 0 0 0 0     1\n0000 f4 61 9c -1\n-1\n\nf4_2    CALL P,nn\n008e 0000 0000 0000 0000 0000 0000 0000 0000 0000 5698 0000\n00 00 0 0 0 0     1\n0000 f4 61 9c -1\n-1\n\nf5      PUSH AF\n53e3 1459 775f 1a2f 0000 0000 0000 0000 0000 0000 ec12 0000\n00 00 0 0 0 0     1\n0000 f5 -1\n-1\n\nf6      OR n\n0600 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 f6 a7 -1\n-1\n\nf7      RST 30H\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 5507 6d33\n00 00 0 0 0 0     1\n6d33 f7 -1\n-1\n\nf8_1    RET M\n0018 0000 0000 0000 0000 0000 0000 0000 0000 0000 43f7 0000\n00 00 0 0 0 0     1\n0000 f8 -1\n43f7 e9 af -1\n-1\n\nf8_2    RET M\n0098 0000 0000 0000 0000 0000 0000 0000 0000 0000 43f7 0000\n00 00 0 0 0 0     1\n0000 f8 -1\n43f7 e9 af -1\n-1\n\nf9      LD SP,HL\n0000 0000 0000 ce32 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 f9 -1\n-1\n\nfa_1    JP M,nn\n0087 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 fa 1b e1 -1\n-1\n\nfa_2    JP M,nn\n0007 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 fa 1b e1 -1\n-1\n\nfb      EI\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 fb -1\n-1\n\nfc_1    CALL M,nn\n008e 0000 0000 0000 0000 0000 0000 0000 0000 0000 5698 0000\n00 00 0 0 0 0     1\n0000 fc 61 9c -1\n-1\n\nfc_2    CALL M,nn\n000e 0000 0000 0000 0000 0000 0000 0000 0000 0000 5698 0000\n00 00 0 0 0 0     1\n0000 fc 61 9c -1\n-1\n\nfd09    ADD IY,BC\n466a a623 bab2 d788 0000 0000 0000 0000 c9e8 f698 0000 0000\n00 00 0 0 0 0     1\n0000 fd 09 -1\n-1\n\nfd19    ADD IY,DE\nb3e5 5336 76cb 54e2 0000 0000 0000 0000 b9ce 8624 0000 0000\n00 00 0 0 0 0     1\n0000 fd 19 -1\n-1\n\nfd21    LD IY,nn\nc924 5c83 e0e2 eddb 0000 0000 0000 0000 6e9f ba55 0000 0000\n00 00 0 0 0 0     1\n0000 fd 21 46 47 -1\n-1\n\nfd22    LD (nn),IY\n1235 f0b6 b74c cc9f 0000 0000 0000 0000 8b00 81e4 0000 0000\n00 00 0 0 0 0     1\n0000 fd 22 9a e2 -1\n-1\n\nfd23    INC IY\n69f2 c1d3 0f6f 2169 0000 0000 0000 0000 e39e 2605 0000 0000\n00 00 0 0 0 0     1\n0000 fd 23 -1\n-1\n\nfd24    INC IYh*\n5554 9684 d36a dac3 0000 0000 0000 0000 7803 6434 0000 0000\n00 00 0 0 0 0     1\n0000 fd 24 -1\n-1\n\nfd25    DEC IYh*\ncd0b b5e4 a754 9526 0000 0000 0000 0000 3dcb 03b2 0000 0000\n00 00 0 0 0 0     1\n0000 fd 25 -1\n-1\n\nfd26    LD IYh,n*\n2452 300b b4a1 929d 0000 0000 0000 0000 c259 3f30 0000 0000\n00 00 0 0 0 0     1\n0000 fd 26 77 -1\n-1\n\nfd29    ADD IY,IY\n5812 49d0 ec95 011c 0000 0000 0000 0000 ec6c 594c 0000 0000\n00 00 0 0 0 0     1\n0000 fd 29 -1\n-1\n\nfd2a    LD IY,(nn)\n0f82 3198 87e3 7c1c 0000 0000 0000 0000 1bb4 eb1a 0000 0000\n00 00 0 0 0 0     1\n0000 fd 2a 91 f9 -1\nf991 92 bf -1\n-1\n\nfd2b    DEC IY\nab27 942f 82fa 6f2f 0000 0000 0000 0000 9438 ebbc 0000 0000\n00 00 0 0 0 0     1\n0000 fd 2b -1\n-1\n\nfd2c    INC IYl*\n665d 0ab1 5656 e5a9 0000 0000 0000 0000 5fb9 4df7 0000 0000\n00 00 0 0 0 0     1\n0000 fd 2c -1\n-1\n\nfd2d    DEC IYl*\n32fb f78a b906 31d0 0000 0000 0000 0000 c72a e91c 0000 0000\n00 00 0 0 0 0     1\n0000 fd 2d -1\n-1\n\nfd2e    LD IYl,n*\n2114 4923 6e65 006c 0000 0000 0000 0000 da39 c0cb 0000 0000\n00 00 0 0 0 0     1\n0000 fd 2e 49 -1\n-1\n\nfd34    INC (IY+d)\nd56a 6f24 7df7 74f0 0000 0000 0000 0000 365a efc4 0000 0000\n00 00 0 0 0 0     1\n0000 fd 34 b8 -1\nef7c e0 -1\n-1\n\nfd35    DEC (IY+d)\n8cda 35d8 7c1a 1c0a 0000 0000 0000 0000 62bb aec6 0000 0000\n00 00 0 0 0 0     1\n0000 fd 35 ab -1\nae71 a6 -1\n-1\n\nfd36    LD (IY+d),n\ne0f9 ae1f 4aef c9d5 0000 0000 0000 0000 c0db bdd4 0000 0000\n00 00 0 0 0 0     1\n0000 fd 36 81 c5 -1\n-1\n\nfd39    ADD IY,SP\n2603 726f 9c7f cd46 0000 0000 0000 0000 dc45 54d5 dc57 0000\n00 00 0 0 0 0     1\n0000 fd 39 -1\n-1\n\nfd44    LD B,IYh*\n0e58 7192 3580 9be4 0000 0000 0000 0000 1b79 685e 0000 0000\n00 00 0 0 0 0     1\n0000 fd 44 -1\n-1\n\nfd45    LD B,IYl*\n6555 a488 5ae8 c948 0000 0000 0000 0000 d7b8 a177 0000 0000\n00 00 0 0 0 0     1\n0000 fd 45 -1\n-1\n\nfd46    LD B,(IY+d)\n87f3 17d5 5eea 830b 0000 0000 0000 0000 dcee 3afc 0000 0000\n00 00 0 0 0 0     1\n0000 fd 46 4d -1\n3b49 c9 -1\n-1\n\nfd4c    LD C,IYh*\n7e6b bd4b 24b6 ff94 0000 0000 0000 0000 862d 01d0 0000 0000\n00 00 0 0 0 0     1\n0000 fd 4c -1\n-1\n\nfd4d    LD C,IYl*\n50cf e3fe 998e dba2 0000 0000 0000 0000 c4f5 c7c9 0000 0000\n00 00 0 0 0 0     1\n0000 fd 4d -1\n-1\n\nfd4e    LD C,(IY+d)\n2c0f 69d7 748a 9290 0000 0000 0000 0000 904f bb9a 0000 0000\n00 00 0 0 0 0     1\n0000 fd 4e 67 -1\nbc01 9d -1\n-1\n\nfd54    LD D,IYh*\nd7f9 f65b b001 d4c4 0000 0000 0000 0000 4b8e d437 0000 0000\n00 00 0 0 0 0     1\n0000 fd 54 -1\n-1\n\nfd55    LD D,IYl*\nab98 fdab 254a 010e 0000 0000 0000 0000 126b 13a9 0000 0000\n00 00 0 0 0 0     1\n0000 fd 55 -1\n-1\n\nfd56    LD D,(IY+d)\nd3e8 df10 5442 b641 0000 0000 0000 0000 a5a0 fda2 0000 0000\n00 00 0 0 0 0     1\n0000 fd 56 ce -1\nfd70 78 -1\n-1\n\nfd5c    LD E,IYh*\n11d5 c489 e220 434e 0000 0000 0000 0000 3244 d8bb 0000 0000\n00 00 0 0 0 0     1\n0000 fd 5c -1\n-1\n\nfd5d    LD E,IYl*\ne945 dbae 32ea 4f7e 0000 0000 0000 0000 fa56 074e 0000 0000\n00 00 0 0 0 0     1\n0000 fd 5d -1\n-1\n\nfd5e    LD E,(IY+d)\n6f3b e9dc 7a06 14f3 0000 0000 0000 0000 ec76 8aaa 0000 0000\n00 00 0 0 0 0     1\n0000 fd 5e c6 -1\n8a70 8c -1\n-1\n\nfd60    LD IYh,B*\n8579 005d d9ee faee 0000 0000 0000 0000 382d 2f95 0000 0000\n00 00 0 0 0 0     1\n0000 fd 60 -1\n-1\n\nfd61    LD IYh,C*\n5682 dbc3 b495 9799 0000 0000 0000 0000 85b2 3c1e 0000 0000\n00 00 0 0 0 0     1\n0000 fd 61 -1\n-1\n\nfd62    LD IYh,D*\n906b f52e f3d8 1e8c 0000 0000 0000 0000 ddba 9a02 0000 0000\n00 00 0 0 0 0     1\n0000 fd 62 -1\n-1\n\nfd63    LD IYh,E*\n9d59 beb9 d826 0eaa 0000 0000 0000 0000 4290 a4b9 0000 0000\n00 00 0 0 0 0     1\n0000 fd 63 -1\n-1\n\nfd64    LD IYh,IYh*\n7b0e e394 8a25 cddf 0000 0000 0000 0000 9784 2116 0000 0000\n00 00 0 0 0 0     1\n0000 fd 64 -1\n-1\n\nfd65    LD IYh,IYl*\nb827 eb4f f666 c52a 0000 0000 0000 0000 6206 831f 0000 0000\n00 00 0 0 0 0     1\n0000 fd 65 -1\n-1\n\nfd66    LD H,(IY+d)\n9129 e4ee e3a3 86ca 0000 0000 0000 0000 4d93 5b24 0000 0000\n00 00 0 0 0 0     1\n0000 fd 66 80 -1\n5aa4 77 -1\n-1\n\nfd67    LD IYh,A*\ndb7a b40b 7b58 49fd 0000 0000 0000 0000 266f 9e7b 0000 0000\n00 00 0 0 0 0     1\n0000 fd 67 -1\n-1\n\nfd68    LD IYl,B*\n4d1d 4fd9 783e 0745 0000 0000 0000 0000 0c3d 82b5 0000 0000\n00 00 0 0 0 0     1\n0000 fd 68 -1\n-1\n\nfd69    LD IYl,C*\n1589 5ceb b5db 922a 0000 0000 0000 0000 3c3a dc98 0000 0000\n00 00 0 0 0 0     1\n0000 fd 69 -1\n-1\n\nfd6a    LD IYl,D*\n607a e035 5bb9 dac0 0000 0000 0000 0000 fc04 b5b7 0000 0000\n00 00 0 0 0 0     1\n0000 fd 6a -1\n-1\n\nfd6b    LD IYl,E*\ndb2a e244 1182 096f 0000 0000 0000 0000 198e 91a6 0000 0000\n00 00 0 0 0 0     1\n0000 fd 6b -1\n-1\n\nfd6c    LD IYl,IYh*\na0be 34ef 8fcd 40a7 0000 0000 0000 0000 4481 c215 0000 0000\n00 00 0 0 0 0     1\n0000 fd 6c -1\n-1\n\nfd6d    LD IYl,IYl*\nfdfc 727a b839 50a6 0000 0000 0000 0000 e782 02e5 0000 0000\n00 00 0 0 0 0     1\n0000 fd 6d -1\n-1\n\nfd6e    LD L,(IY+d)\ncfd4 6ef1 c07d eb96 0000 0000 0000 0000 b0f9 b0a3 0000 0000\n00 00 0 0 0 0     1\n0000 fd 6e 78 -1\nb11b f8 -1\n-1\n\nfd6f    LD IYl,A*\n8e1d a138 f20a 298e 0000 0000 0000 0000 b600 0cf7 0000 0000\n00 00 0 0 0 0     1\n0000 fd 6f -1\n-1\n\nfd70    LD (IY+d),B\n2677 33c5 c0dc 262f 0000 0000 0000 0000 d3dc 23a1 0000 0000\n00 00 0 0 0 0     1\n0000 fd 70 53 -1\n-1\n\nfd71    LD (IY+d),C\n892e 04ae d67f 81ec 0000 0000 0000 0000 7757 bfab 0000 0000\n00 00 0 0 0 0     1\n0000 fd 71 b4 -1\n-1\n\nfd72    LD (IY+d),D\nd2dc c23c dd54 6559 0000 0000 0000 0000 b32b 7c80 0000 0000\n00 00 0 0 0 0     1\n0000 fd 72 e3 -1\n-1\n\nfd73    LD (IY+d),E\n49ef bff2 8409 02dd 0000 0000 0000 0000 af95 8762 0000 0000\n00 00 0 0 0 0     1\n0000 fd 73 17 -1\n-1\n\nfd74    LD (IY+d),H\n9479 9817 fa2e 1fe0 0000 0000 0000 0000 a395 92db 0000 0000\n00 00 0 0 0 0     1\n0000 fd 74 f6 -1\n-1\n\nfd75    LD (IY+d),L\nc8d6 6aa4 180e e37b 0000 0000 0000 0000 02cf 1724 0000 0000\n00 00 0 0 0 0     1\n0000 fd 75 ab -1\n-1\n\nfd77    LD (IY+d),A\n6f9e 7475 78ad 2b8c 0000 0000 0000 0000 c6b7 6b4d 0000 0000\n00 00 0 0 0 0     1\n0000 fd 77 f7 -1\n-1\n\nfd7c    LD A,IYh*\nf228 93fc a3d4 dc9e 0000 0000 0000 0000 21ac c617 0000 0000\n00 00 0 0 0 0     1\n0000 fd 7c -1\n-1\n\nfd7d    LD A,IYl*\n93e5 3cbe 02c3 26c2 0000 0000 0000 0000 ca81 92b9 0000 0000\n00 00 0 0 0 0     1\n0000 fd 7d -1\n-1\n\nfd7e    LD A,(IY+d)\n1596 daba 147b f362 0000 0000 0000 0000 7110 d45f 0000 0000\n00 00 0 0 0 0     1\n0000 fd 7e e4 -1\nd443 aa -1\n-1\n\nfd84    ADD A,IYh*\nbfba 7cae c4da 7aee 0000 0000 0000 0000 43ee c08e 0000 0000\n00 00 0 0 0 0     1\n0000 fd 84 -1\n-1\n\nfd85    ADD A,IYl*\n52dd 1dea 324f 84e7 0000 0000 0000 0000 e7a8 f799 0000 0000\n00 00 0 0 0 0     1\n0000 fd 85 -1\n-1\n\nfd86    ADD A,(IY+d)\nfc9c b882 43f9 3e15 0000 0000 0000 0000 9781 8b33 0000 0000\n00 00 0 0 0 0     1\n0000 fd 86 ce -1\n8b01 e1 -1\n-1\n\nfd8c    ADC A,IYh*\nfd9c 42b1 5e8a 081c 0000 0000 0000 0000 cb58 3b4e 0000 0000\n00 00 0 0 0 0     1\n0000 fd 8c -1\n-1\n\nfd8d    ADC A,IYl*\n9301 7750 8ad6 295c 0000 0000 0000 0000 695c 99fb 0000 0000\n00 00 0 0 0 0     1\n0000 fd 8d -1\n-1\n\nfd8e    ADC A,(IY+d)\n41ee 398f f6dc 06f3 0000 0000 0000 0000 f34a 1aa2 0000 0000\n00 00 0 0 0 0     1\n0000 fd 8e 78 -1\n1b1a c0 -1\n-1\n\nfd94    SUB IYh*\n0431 d255 b9d6 20bb 0000 0000 0000 0000 1e6a d5ef 0000 0000\n00 00 0 0 0 0     1\n0000 fd 94 -1\n-1\n\nfd95    SUB IYl*\n8b5d b455 2388 ec1e 0000 0000 0000 0000 7637 cb97 0000 0000\n00 00 0 0 0 0     1\n0000 fd 95 -1\n-1\n\nfd96    SUB (IY+d)\na0c6 22ac 0413 4b13 0000 0000 0000 0000 b44e c08b 0000 0000\n00 00 0 0 0 0     1\n0000 fd 96 55 -1\nc0e0 7b -1\n-1\n\nfd9c    SBC A,IYh*\na44a 3ecf ced3 66ec 0000 0000 0000 0000 4bff b133 0000 0000\n00 00 0 0 0 0     1\n0000 fd 9c -1\n-1\n\nfd9d    SBC A,IYl*\n06c0 8bd0 131b 3094 0000 0000 0000 0000 afc3 7409 0000 0000\n00 00 0 0 0 0     1\n0000 fd 9d -1\n-1\n\nfd9e    SBC A,(IY+d)\nb983 981f bb8e d6d5 0000 0000 0000 0000 5c3b f66c 0000 0000\n00 00 0 0 0 0     1\n0000 fd 9e f9 -1\nf665 f3 -1\n-1\n\nfda4    AND IYh*\nb079 79c0 2c7c 3e06 0000 0000 0000 0000 7399 037a 0000 0000\n00 00 0 0 0 0     1\n0000 fd a4 -1\n-1\n\nfda5    AND IYl*\n01d2 654d 9653 2b33 0000 0000 0000 0000 61a4 8f88 0000 0000\n00 00 0 0 0 0     1\n0000 fd a5 -1\n-1\n\nfda6    AND (IY+d)\nddb8 40bb 3742 6ff1 0000 0000 0000 0000 ad28 659b 0000 0000\n00 00 0 0 0 0     1\n0000 fd a6 53 -1\n65ee 95 -1\n-1\n\nfdac    XOR IYh*\n7a43 72e3 dd4d 1b62 0000 0000 0000 0000 4753 5d63 0000 0000\n00 00 0 0 0 0     1\n0000 fd ac -1\n-1\n\nfdad    XOR IYl*\n7d8e 2573 19cc 78fb 0000 0000 0000 0000 5248 8391 0000 0000\n00 00 0 0 0 0     1\n0000 fd ad -1\n-1\n\nfdae    XOR (IY+d)\na0da bc27 257b 5489 0000 0000 0000 0000 fa59 81f8 0000 0000\n00 00 0 0 0 0     1\n0000 fd ae 09 -1\n8201 cb -1\n-1\n\nfdb4    OR IYh*\n4f95 3461 f173 8ad3 0000 0000 0000 0000 c1a2 8265 0000 0000\n00 00 0 0 0 0     1\n0000 fd b4 -1\n-1\n\nfdb5    OR IYl*\n17f6 e6ea f919 327c 0000 0000 0000 0000 4299 9733 0000 0000\n00 00 0 0 0 0     1\n0000 fd b5 -1\n-1\n\nfdb6    OR (IY+d)\ndb37 3509 d6ca b16a 0000 0000 0000 0000 a099 df6d 0000 0000\n00 00 0 0 0 0     1\n0000 fd b6 4b -1\ndfb8 64 -1\n-1\n\nfdbc    CP IYh*\nb4fc 9302 e35d 31bc 0000 0000 0000 0000 5c12 1c92 0000 0000\n00 00 0 0 0 0     1\n0000 fd bc -1\n-1\n\nfdbd    CP IYl*\n391c 7b82 dfeb 03ee 0000 0000 0000 0000 be7b b30f 0000 0000\n00 00 0 0 0 0     1\n0000 fd bd -1\n-1\n\nfdbe    CP (IY+d)\n0970 0b31 f4ad 9d4c 0000 0000 0000 0000 b95a a96b 0000 0000\n00 00 0 0 0 0     1\n0000 fd be 6b -1\na9d6 c0 -1\n-1\n\nfdcb00  RLC (IY+d),B*\n85ac 46d0 a135 20c5 0000 0000 0000 0000 b8de 2776 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 0b 00 -1\n2781 50 -1\n-1\n\nfdcb01  RLC (IY+d),C*\n577c 2b76 3576 280a 0000 0000 0000 0000 ae22 5c35 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb c8 01 -1\n5bfd cb -1\n-1\n\nfdcb02  RLC (IY+d),D*\ndc23 2b37 83c8 5dd9 0000 0000 0000 0000 b2d2 3df2 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 14 02 -1\n3e06 58 -1\n-1\n\nfdcb03  RLC (IY+d),E*\n57ee c179 b2b6 7058 0000 0000 0000 0000 3f2e 57e7 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 3a 03 -1\n5821 1a -1\n-1\n\nfdcb04  RLC (IY+d),H*\ned18 3f03 3327 f35a 0000 0000 0000 0000 cbf2 5071 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 67 04 -1\n50d8 92 -1\n-1\n\nfdcb05  RLC (IY+d),L*\n7a39 0858 db6c dbe0 0000 0000 0000 0000 157a b25b 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 1e 05 -1\nb279 66 -1\n-1\n\nfdcb06  RLC (IY+d)\nf285 89a2 e78f ef74 0000 0000 0000 0000 140d ff27 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 72 06 -1\nff99 f1 -1\n-1\n\nfdcb07  RLC (IY+d),A*\n8cce f3a7 3a6e 8f0a 0000 0000 0000 0000 8423 07eb 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 24 07 -1\n080f ae -1\n-1\n\nfdcb08  RRC (IY+d),B*\na611 e8ec c958 7bda 0000 0000 0000 0000 194d 6137 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 25 08 -1\n615c 83 -1\n-1\n\nfdcb09  RRC (IY+d),C*\n54b1 fa1a 84e8 4fa5 0000 0000 0000 0000 1ad3 19da 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb a0 09 -1\n197a 27 -1\n-1\n\nfdcb0a  RRC (IY+d),D*\nb3ef a2bb e5d6 9617 0000 0000 0000 0000 f946 eef6 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb e1 0a -1\need7 19 -1\n-1\n\nfdcb0b  RRC (IY+d),E*\nae10 8c4e e159 1c54 0000 0000 0000 0000 e108 c68f 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 0c 0b -1\nc69b f2 -1\n-1\n\nfdcb0c  RRC (IY+d),H*\n8719 6b16 4c3b 180a 0000 0000 0000 0000 175a 8c9d 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb d7 0c -1\n8c74 ae -1\n-1\n\nfdcb0d  RRC (IY+d),L*\n1204 e0cb 3ab1 2416 0000 0000 0000 0000 1de4 fe2d 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 11 0d -1\nfe3e 1b -1\n-1\n\nfdcb0e  RRC (IY+d)\n8da4 8f91 fc5a 5e2c 0000 0000 0000 0000 b2f2 f223 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 0c 0e -1\nf22f f7 -1\n-1\n\nfdcb0f  RRC (IY+d),A*\nfbb0 2ac9 ec6b 6511 0000 0000 0000 0000 c93a ce38 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 15 0f -1\nce4d 44 -1\n-1\n\nfdcb10  RL (IY+d),B*\n259d 3852 590d ac66 0000 0000 0000 0000 144f 42a2 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 7a 10 -1\n431c 1c -1\n-1\n\nfdcb11  RL (IY+d),C*\nbc60 61c1 f5f8 af24 0000 0000 0000 0000 4019 9c90 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 7b 11 -1\n9d0b 5e -1\n-1\n\nfdcb12  RL (IY+d),D*\n4e45 3a25 3417 bcc7 0000 0000 0000 0000 0d7e 8537 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 61 12 -1\n8598 a7 -1\n-1\n\nfdcb13  RL (IY+d),E*\nb224 b79b 84f1 ff7d 0000 0000 0000 0000 414c e798 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb b3 13 -1\ne74b b3 -1\n-1\n\nfdcb14  RL (IY+d),H*\nabbb 451a fc65 14a1 0000 0000 0000 0000 0f4d d93c 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb c4 14 -1\nd900 06 -1\n-1\n\nfdcb15  RL (IY+d),L*\n2864 9532 8631 751c 0000 0000 0000 0000 e327 2d7b 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 17 15 -1\n2d92 12 -1\n-1\n\nfdcb16  RL (IY+d)\n0c3c dcd7 adcc 196d 0000 0000 0000 0000 87e2 f0b4 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 23 16 -1\nf0d7 89 -1\n-1\n\nfdcb17  RL (IY+d),A*\naf5b d016 066e 6638 0000 0000 0000 0000 5e92 2013 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 8a 17 -1\n1f9d b8 -1\n-1\n\nfdcb18  RR (IY+d),B*\n23f3 4517 16e0 6894 0000 0000 0000 0000 b908 3216 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb c0 18 -1\n31d6 fa -1\n-1\n\nfdcb19  RR (IY+d),C*\n11ed c2b8 a9f3 2014 0000 0000 0000 0000 6db0 4d2e 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb a2 19 -1\n4cd0 4b -1\n-1\n\nfdcb1a  RR (IY+d),D*\nbc5c 6168 e541 b630 0000 0000 0000 0000 0207 40d3 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 78 1a -1\n414b 44 -1\n-1\n\nfdcb1b  RR (IY+d),E*\n7a28 1286 fe50 c42d 0000 0000 0000 0000 e290 71b0 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 16 1b -1\n71c6 b8 -1\n-1\n\nfdcb1c  RR (IY+d),H*\n932b 097b 6928 83a3 0000 0000 0000 0000 ff2d df62 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 86 1c -1\ndee8 8f -1\n-1\n\nfdcb1d  RR (IY+d),L*\n97b1 2b30 2645 04ef 0000 0000 0000 0000 186a d667 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 27 1d -1\nd68e b7 -1\n-1\n\nfdcb1e  RR (IY+d)\n2f39 2470 b521 6ca3 0000 0000 0000 0000 1066 da38 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 3a 1e -1\nda72 25 -1\n-1\n\nfdcb1f  RR (IY+d),A*\n4cdd 49a3 da18 3afd 0000 0000 0000 0000 a4f1 2095 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 7b 1f -1\n2110 04 -1\n-1\n\nfdcb20  SLA (IY+d),B*\n3d74 3a8f 206f 8894 0000 0000 0000 0000 ddab da25 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 7a 20 -1\nda9f 89 -1\n-1\n\nfdcb21  SLA (IY+d),C*\n1674 6025 641a 6598 0000 0000 0000 0000 473b de36 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 7b 21 -1\ndeb1 23 -1\n-1\n\nfdcb22  SLA (IY+d),D*\nada9 efb2 6f03 e732 0000 0000 0000 0000 c11d 8926 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 9a 22 -1\n88c0 d4 -1\n-1\n\nfdcb23  SLA (IY+d),E*\n21e9 d678 a71b 25d7 0000 0000 0000 0000 4ca8 5255 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb f5 23 -1\n524a 65 -1\n-1\n\nfdcb24  SLA (IY+d),H*\n1c51 da3e cc7c cb19 0000 0000 0000 0000 572c affe 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb b4 24 -1\nafb2 7e -1\n-1\n\nfdcb25  SLA (IY+d),L*\n954e 097c a341 89e0 0000 0000 0000 0000 435d 23e9 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb a6 25 -1\n238f 26 -1\n-1\n\nfdcb26  SLA (IY+d)\n5844 0e19 d277 bf7f 0000 0000 0000 0000 6504 d4e4 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb bd 26 -1\nd4a1 bf -1\n-1\n\nfdcb27  SLA (IY+d),A*\n8e0d 8c06 2c4c d7c8 0000 0000 0000 0000 9239 8d42 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 59 27 -1\n8d9b a7 -1\n-1\n\nfdcb28  SRA (IY+d),B*\n4122 af9b 7745 76f5 0000 0000 0000 0000 a1bb ab43 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 83 28 -1\naac6 5d -1\n-1\n\nfdcb29  SRA (IY+d),C*\n0b21 affd fea6 9478 0000 0000 0000 0000 32bb 0343 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 7d 29 -1\n03c0 84 -1\n-1\n\nfdcb2a  SRA (IY+d),D*\nf236 8c31 5932 7feb 0000 0000 0000 0000 7db7 abe7 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb f9 2a -1\nabe0 dd -1\n-1\n\nfdcb2b  SRA (IY+d),E*\n2450 6945 dcfc d643 0000 0000 0000 0000 5be1 4a94 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 4b 2b -1\n4adf 49 -1\n-1\n\nfdcb2c  SRA (IY+d),H*\n117f b32b e530 255a 0000 0000 0000 0000 2416 ccd1 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb e6 2c -1\nccb7 3c -1\n-1\n\nfdcb2d  SRA (IY+d),L*\nd0c3 344b 1bb0 3eab 0000 0000 0000 0000 fe11 e4e6 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 5f 2d -1\ne545 78 -1\n-1\n\nfdcb2e  SRA (IY+d)\nf4ee b832 4b7f e2b7 0000 0000 0000 0000 9386 42fd 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 06 2e -1\n4303 ad -1\n-1\n\nfdcb2f  SRA (IY+d),A*\nff86 f2c2 9f2f c946 0000 0000 0000 0000 5fe0 16b8 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 29 2f -1\n16e1 18 -1\n-1\n\nfdcb30  SLL (IY+d),B*\nacf6 e832 f9ed cabc 0000 0000 0000 0000 fabd d646 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 1b 30 -1\nd661 a5 -1\n-1\n\nfdcb31  SLL (IY+d),C*\n2b96 5134 83a7 7eee 0000 0000 0000 0000 7750 bfe0 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb f0 31 -1\nbfd0 f1 -1\n-1\n\nfdcb32  SLL (IY+d),D*\nb2bc a4b1 b685 f66e 0000 0000 0000 0000 a9a1 5ade 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb c5 32 -1\n5aa3 59 -1\n-1\n\nfdcb33  SLL (IY+d),E*\n9c6d 2c90 d0a9 2be3 0000 0000 0000 0000 2691 1964 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 7f 33 -1\n19e3 da -1\n-1\n\nfdcb34  SLL (IY+d),H*\n6029 fbcd 5348 f947 0000 0000 0000 0000 5338 5696 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb d2 34 -1\n5668 d4 -1\n-1\n\nfdcb35  SLL (IY+d),L*\n96a9 21c6 4cb6 b40b 0000 0000 0000 0000 673a 00f8 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 71 35 -1\n0169 0b -1\n-1\n\nfdcb36  SLL (IY+d)*\ndc6f 0892 3cc7 1494 0000 0000 0000 0000 8598 1ade 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb da 36 -1\n1ab8 3c -1\n-1\n\nfdcb37  SLL (IY+d),A*\nd2b3 4524 208f 076f 0000 0000 0000 0000 ad10 e7ec 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb cb 37 -1\ne7b7 9f -1\n-1\n\nfdcb38  SRL (IY+d),B*\n4f07 0050 40c6 4fb7 0000 0000 0000 0000 f37e d096 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 8e 38 -1\nd024 0d -1\n-1\n\nfdcb39  SRL (IY+d),C*\nbcc2 f5b5 8dee e514 0000 0000 0000 0000 48bc f433 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 7f 39 -1\nf4b2 f5 -1\n-1\n\nfdcb3a  SRL (IY+d),D*\nd012 2ef5 2910 9ca5 0000 0000 0000 0000 b155 cb03 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 1d 3a -1\ncb20 a8 -1\n-1\n\nfdcb3b  SRL (IY+d),E*\n503d a85b cfbb de8c 0000 0000 0000 0000 9c5b d263 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 05 3b -1\nd268 b2 -1\n-1\n\nfdcb3c  SRL (IY+d),H*\n97f0 4456 0b52 fdad 0000 0000 0000 0000 6d2a a80f 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb ae 3c -1\na7bd 96 -1\n-1\n\nfdcb3d  SRL (IY+d),L*\n7d44 9303 e12b bff6 0000 0000 0000 0000 4c0f e52a 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 13 3d -1\ne53d fb -1\n-1\n\nfdcb3e  SRL (IY+d)\n0d95 3e02 8f74 0f82 0000 0000 0000 0000 85df b2d1 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 2e 3e -1\nb2ff 50 -1\n-1\n\nfdcb3f  SRL (IY+d),A*\n89e3 12f6 426c 52d4 0000 0000 0000 0000 d9f7 c1ac 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 21 3f -1\nc1cd 78 -1\n-1\n\nfdcb40  BIT 0,(IY+d)*\n5408 2c34 6784 b376 0000 0000 0000 0000 8ff9 4195 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 3b 40 -1\n41d0 0d -1\n-1\n\nfdcb41  BIT 0,(IY+d)*\n8c35 5a58 b71c 6777 0000 0000 0000 0000 deca 03cb 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb cc 41 -1\n0397 e9 -1\n-1\n\nfdcb42  BIT 0,(IY+d)*\n5535 9c29 2feb 97ff 0000 0000 0000 0000 7f17 9f56 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 01 42 -1\n9f57 a8 -1\n-1\n\nfdcb43  BIT 0,(IY+d)*\nb404 e58c e62e 2a32 0000 0000 0000 0000 7130 1fd1 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 08 43 -1\n1fd9 aa -1\n-1\n\nfdcb44  BIT 0,(IY+d)*\na954 68f4 9fa4 7f66 0000 0000 0000 0000 0209 f4f3 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 03 44 -1\nf4f6 89 -1\n-1\n\nfdcb45  BIT 0,(IY+d)*\n73e5 8dde 5e4f 84a7 0000 0000 0000 0000 4e24 93ed 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 8d 45 -1\n937a 8d -1\n-1\n\nfdcb46  BIT 0,(IY+d)\n0e5a b1f9 475f ebfc 0000 0000 0000 0000 7765 63b1 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 8c 46 -1\n633d fe -1\n-1\n\nfdcb47  BIT 0,(IY+d)*\n9b3d 7f38 0753 d5e7 0000 0000 0000 0000 b9c3 6e0e 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 96 47 -1\n6da4 d6 -1\n-1\n\nfdcb48  BIT 1,(IY+d)*\n7d94 50a9 2511 8f9f 0000 0000 0000 0000 b612 aba9 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 44 48 -1\nabed b0 -1\n-1\n\nfdcb49  BIT 1,(IY+d)*\n691e 3a39 b834 74b6 0000 0000 0000 0000 0eb7 3e21 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 4e 49 -1\n3e6f a9 -1\n-1\n\nfdcb4a  BIT 1,(IY+d)*\n31e3 68e0 fe2f a2c4 0000 0000 0000 0000 ac96 e7db 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 52 4a -1\ne82d da -1\n-1\n\nfdcb4b  BIT 1,(IY+d)*\n09a1 2453 9186 a32a 0000 0000 0000 0000 71af 883f 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb ea 4b -1\n8829 4e -1\n-1\n\nfdcb4c  BIT 1,(IY+d)*\n4a52 1e5b be2e 3ee4 0000 0000 0000 0000 af79 7f22 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb ee 4c -1\n7f10 70 -1\n-1\n\nfdcb4d  BIT 1,(IY+d)*\n9f87 6c8f 34f4 5a79 0000 0000 0000 0000 d3cc a770 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 29 4d -1\na799 78 -1\n-1\n\nfdcb4e  BIT 1,(IY+d)\n30cb 5626 52bc 5503 0000 0000 0000 0000 303b e1c8 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 20 4e -1\ne1e8 aa -1\n-1\n\nfdcb4f  BIT 1,(IY+d)*\n6088 e079 7152 671f 0000 0000 0000 0000 8c22 1cf8 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 9d 4f -1\n1c95 18 -1\n-1\n\nfdcb50  BIT 2,(IY+d)*\n8cde 1409 6d69 e5b2 0000 0000 0000 0000 4a0c c75f 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 6b 50 -1\nc7ca fe -1\n-1\n\nfdcb51  BIT 2,(IY+d)*\n8f59 40cb 9543 9b3a 0000 0000 0000 0000 1942 3495 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 86 51 -1\n341b 13 -1\n-1\n\nfdcb52  BIT 2,(IY+d)*\n8905 3e41 7ab4 37f6 0000 0000 0000 0000 f82d 8b0d 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb e6 52 -1\n8af3 87 -1\n-1\n\nfdcb53  BIT 2,(IY+d)*\nefde e345 09a3 f0b2 0000 0000 0000 0000 c378 7ee1 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb d1 53 -1\n7eb2 e4 -1\n-1\n\nfdcb54  BIT 2,(IY+d)*\n72a6 cb82 d966 2fc6 0000 0000 0000 0000 3c00 5b6b 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 08 54 -1\n5b73 07 -1\n-1\n\nfdcb55  BIT 2,(IY+d)*\n855c c23b 6aab 9b00 0000 0000 0000 0000 fe93 b4b2 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 54 55 -1\nb506 46 -1\n-1\n\nfdcb56  BIT 2,(IY+d)\nf5ad f9f6 1e8c 9e08 0000 0000 0000 0000 716a 6932 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 6f 56 -1\n69a1 df -1\n-1\n\nfdcb57  BIT 2,(IY+d)*\n37d7 b7dc be1c 38ea 0000 0000 0000 0000 5e82 a3bb 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 3c 57 -1\na3f7 6c -1\n-1\n\nfdcb58  BIT 3,(IY+d)*\n752c 7296 3ea5 1143 0000 0000 0000 0000 d7cc 1e94 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 4e 58 -1\n1ee2 f6 -1\n-1\n\nfdcb59  BIT 3,(IY+d)*\n8056 bf2a 1809 ed31 0000 0000 0000 0000 fe2b fad3 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 2e 59 -1\nfb01 6f -1\n-1\n\nfdcb5a  BIT 3,(IY+d)*\ncc74 a108 65d4 6f66 0000 0000 0000 0000 0008 7bb8 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 88 5a -1\n7b40 6e -1\n-1\n\nfdcb5b  BIT 3,(IY+d)*\n5cf1 b3bd 25bd 98cf 0000 0000 0000 0000 2ba1 315c 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb e7 5b -1\n3143 b1 -1\n-1\n\nfdcb5c  BIT 3,(IY+d)*\nb3e0 d43d d9c0 b04d 0000 0000 0000 0000 21a9 543e 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 74 5c -1\n54b2 e3 -1\n-1\n\nfdcb5d  BIT 3,(IY+d)*\n9f49 43dd ccb3 085a 0000 0000 0000 0000 f130 3b84 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb dc 5d -1\n3b60 ef -1\n-1\n\nfdcb5e  BIT 3,(IY+d)\n6f89 eff5 993b 22b5 0000 0000 0000 0000 0f30 e165 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb e2 5e -1\ne147 17 -1\n-1\n\nfdcb5f  BIT 3,(IY+d)*\nd72a a57a aca6 667e 0000 0000 0000 0000 5c33 f81b 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb ab 5f -1\nf7c6 e2 -1\n-1\n\nfdcb60  BIT 4,(IY+d)*\n15e9 8d30 43f4 c65e 0000 0000 0000 0000 1e34 8c44 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 85 60 -1\n8bc9 b9 -1\n-1\n\nfdcb61  BIT 4,(IY+d)*\n7bd1 d421 5570 cb85 0000 0000 0000 0000 32ec 92e4 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb be 61 -1\n92a2 28 -1\n-1\n\nfdcb62  BIT 4,(IY+d)*\nba2f 4fbb 67a7 c5db 0000 0000 0000 0000 470b 7eb1 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 9d 62 -1\n7e4e 1a -1\n-1\n\nfdcb63  BIT 4,(IY+d)*\nc0a1 2cc2 ce12 e77c 0000 0000 0000 0000 71c5 1713 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb f4 63 -1\n1707 3b -1\n-1\n\nfdcb64  BIT 4,(IY+d)*\n0c1f 7847 2494 71eb 0000 0000 0000 0000 315c b336 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 35 64 -1\nb36b 8c -1\n-1\n\nfdcb65  BIT 4,(IY+d)*\n5245 a82d 1112 8f09 0000 0000 0000 0000 672a 89f4 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 37 65 -1\n8a2b 08 -1\n-1\n\nfdcb66  BIT 4,(IY+d)\n583f c13e b136 6bc5 0000 0000 0000 0000 3ef9 6948 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 9d 66 -1\n68e5 90 -1\n-1\n\nfdcb67  BIT 4,(IY+d)*\n31b6 0f7d 48b5 cc5f 0000 0000 0000 0000 2103 6572 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb cb 67 -1\n653d 15 -1\n-1\n\nfdcb68  BIT 5,(IY+d)*\ne330 39fb a03a 59bc 0000 0000 0000 0000 e04a 03be 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb ca 68 -1\n0388 83 -1\n-1\n\nfdcb69  BIT 5,(IY+d)*\n1896 5bc2 d4d9 4e8a 0000 0000 0000 0000 3716 a603 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb e2 69 -1\na5e5 01 -1\n-1\n\nfdcb6a  BIT 5,(IY+d)*\n5bc9 0099 34f8 3e96 0000 0000 0000 0000 f251 93be 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb ae 6a -1\n936c 33 -1\n-1\n\nfdcb6b  BIT 5,(IY+d)*\nbbe5 9e6c abd1 515f 0000 0000 0000 0000 73db aa2f 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 1f 6b -1\naa4e 7c -1\n-1\n\nfdcb6c  BIT 5,(IY+d)*\n144b 3af2 8f80 7be5 0000 0000 0000 0000 c379 86ba 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 0d 6c -1\n86c7 25 -1\n-1\n\nfdcb6d  BIT 5,(IY+d)*\n6392 d077 668d 6e4a 0000 0000 0000 0000 b0a8 62c8 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb f0 6d -1\n62b8 e3 -1\n-1\n\nfdcb6e  BIT 5,(IY+d)\n2da0 f872 692d 92c4 0000 0000 0000 0000 36b5 4210 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 93 6e -1\n41a3 1e -1\n-1\n\nfdcb6f  BIT 5,(IY+d)*\ndf7b c7aa 9002 86b8 0000 0000 0000 0000 1347 004e 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 20 6f -1\n006e 37 -1\n-1\n\nfdcb70  BIT 6,(IY+d)*\n6ea9 018d 5075 cf4e 0000 0000 0000 0000 cd2b 3e68 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb d9 70 -1\n3e41 c9 -1\n-1\n\nfdcb71  BIT 6,(IY+d)*\n1b48 e3af 94d5 0996 0000 0000 0000 0000 cad5 999a 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 27 71 -1\n99c1 3e -1\n-1\n\nfdcb72  BIT 6,(IY+d)*\ne83b 26b1 8608 f3cb 0000 0000 0000 0000 6323 fd31 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 98 72 -1\nfcc9 4f -1\n-1\n\nfdcb73  BIT 6,(IY+d)*\n101b 446c c2f9 b9b1 0000 0000 0000 0000 0820 f5d8 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 7a 73 -1\nf652 31 -1\n-1\n\nfdcb74  BIT 6,(IY+d)*\n6847 38c2 0ea4 0825 0000 0000 0000 0000 d255 5e4a 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 4b 74 -1\n5e95 fe -1\n-1\n\nfdcb75  BIT 6,(IY+d)*\n56f2 c034 6e11 d35e 0000 0000 0000 0000 e702 60be 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 57 75 -1\n6115 21 -1\n-1\n\nfdcb76  BIT 6,(IY+d)\n7375 caff dd80 c8ed 0000 0000 0000 0000 7e39 6623 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 53 76 -1\n6676 3a -1\n-1\n\nfdcb77  BIT 6,(IY+d)*\nab10 983e 0bdc 3b46 0000 0000 0000 0000 ae51 8841 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 02 77 -1\n8843 d8 -1\n-1\n\nfdcb78  BIT 7,(IY+d)*\n2765 ce2f 4824 6930 0000 0000 0000 0000 ae69 fecb 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 7d 78 -1\nff48 ec -1\n-1\n\nfdcb79  BIT 7,(IY+d)*\nb428 6355 7896 8a7c 0000 0000 0000 0000 9090 1cae 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 23 79 -1\n1cd1 87 -1\n-1\n\nfdcb7a  BIT 7,(IY+d)*\n59f4 ca21 1482 3fae 0000 0000 0000 0000 c6c9 d923 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 42 7a -1\nd965 b3 -1\n-1\n\nfdcb7b  BIT 7,(IY+d)*\n6314 0240 5efa 5e7b 0000 0000 0000 0000 3e50 0a83 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 17 7b -1\n0a9a bd -1\n-1\n\nfdcb7c  BIT 7,(IY+d)*\n22a6 aff4 b89b 4dca 0000 0000 0000 0000 0ac2 d371 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb f1 7c -1\nd362 1b -1\n-1\n\nfdcb7d  BIT 7,(IY+d)*\n1c95 d615 825a 5e64 0000 0000 0000 0000 32fb ac3b 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 9f 7d -1\nabda 8a -1\n-1\n\nfdcb7e  BIT 7,(IY+d)\n503c 8dfe 1019 6778 0000 0000 0000 0000 f7df 9484 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 40 7e -1\n94c4 9e -1\n-1\n\nfdcb7f  BIT 7,(IY+d)*\n1b07 9ec3 14be 5ebe 0000 0000 0000 0000 1178 ce69 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb a2 7f -1\nce0b 47 -1\n-1\n\nfdcb80  RES 0,(IY+d),B*\ne196 72ea 507e 6457 0000 0000 0000 0000 ab75 920d 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 8b 80 -1\n9198 a9 -1\n-1\n\nfdcb81  RES 0,(IY+d),C*\n3d3d b255 8759 0cb0 0000 0000 0000 0000 e078 82a5 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 55 81 -1\n82fa fa -1\n-1\n\nfdcb82  RES 0,(IY+d),D*\n4e10 5d8d 27a0 ffff 0000 0000 0000 0000 ee0a 5dd8 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 9c 82 -1\n5d74 9d -1\n-1\n\nfdcb83  RES 0,(IY+d),E*\n3c7f fd81 47fb 9f12 0000 0000 0000 0000 cbf9 374a 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 28 83 -1\n3772 d5 -1\n-1\n\nfdcb84  RES 0,(IY+d),H*\n6872 81b1 1e7a e37e 0000 0000 0000 0000 9b4c f1c3 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb aa 84 -1\nf16d ea -1\n-1\n\nfdcb85  RES 0,(IY+d),L*\n25b3 5694 57cd f34d 0000 0000 0000 0000 8ed2 0433 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 6c 85 -1\n049f e0 -1\n-1\n\nfdcb86  RES 0,(IY+d)\n152b 8ce1 818d 40f2 0000 0000 0000 0000 9b7a 2a50 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 7e 86 -1\n2ace 36 -1\n-1\n\nfdcb87  RES 0,(IY+d),A*\nfe1d 5353 618d 3266 0000 0000 0000 0000 1a53 246a 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 59 87 -1\n24c3 65 -1\n-1\n\nfdcb88  RES 1,(IY+d),B*\n7d14 a0ec 1e47 76e1 0000 0000 0000 0000 3871 c60d 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb d4 88 -1\nc5e1 d6 -1\n-1\n\nfdcb89  RES 1,(IY+d),C*\n86c3 50a6 8592 d6ca 0000 0000 0000 0000 947b 0a01 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb c3 89 -1\n09c4 b0 -1\n-1\n\nfdcb8a  RES 1,(IY+d),D*\n599c 961a 55f9 8470 0000 0000 0000 0000 d2a5 d4d2 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb f9 8a -1\nd4cb d8 -1\n-1\n\nfdcb8b  RES 1,(IY+d),E*\n2715 a209 ab47 3eac 0000 0000 0000 0000 f352 c71e 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb ed 8b -1\nc70b dc -1\n-1\n\nfdcb8c  RES 1,(IY+d),H*\n2818 4259 a9b0 e7a0 0000 0000 0000 0000 6471 a202 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 97 8c -1\na199 67 -1\n-1\n\nfdcb8d  RES 1,(IY+d),L*\n14e3 c330 9aa2 8418 0000 0000 0000 0000 0d4f 5669 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb c9 8d -1\n5632 9a -1\n-1\n\nfdcb8e  RES 1,(IY+d)\ncb79 0fff b244 c902 0000 0000 0000 0000 6246 4c81 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb c2 8e -1\n4c43 7f -1\n-1\n\nfdcb8f  RES 1,(IY+d),A*\n66b4 5fbb 6c9b d0e3 0000 0000 0000 0000 ac5a 6b51 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb d4 8f -1\n6b25 59 -1\n-1\n\nfdcb90  RES 2,(IY+d),B*\n1305 1ce1 d627 7402 0000 0000 0000 0000 b470 d7f5 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb fd 90 -1\nd7f2 70 -1\n-1\n\nfdcb91  RES 2,(IY+d),C*\n10df c48f 0213 fc7e 0000 0000 0000 0000 bfab 47d2 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb bf 91 -1\n4791 0e -1\n-1\n\nfdcb92  RES 2,(IY+d),D*\n6a11 f89e f49d c115 0000 0000 0000 0000 bc5d 313a 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 0b 92 -1\n3145 f6 -1\n-1\n\nfdcb93  RES 2,(IY+d),E*\n61e5 cc2c 959a b52b 0000 0000 0000 0000 fa64 2940 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 52 93 -1\n2992 38 -1\n-1\n\nfdcb94  RES 2,(IY+d),H*\n31b4 3e5a fb3d ab83 0000 0000 0000 0000 a801 fe1c 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 95 94 -1\nfdb1 48 -1\n-1\n\nfdcb95  RES 2,(IY+d),L*\n337e 63a7 2918 ed6b 0000 0000 0000 0000 b12c e776 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 90 95 -1\ne706 eb -1\n-1\n\nfdcb96  RES 2,(IY+d)\n5d99 d9ec b6d0 5ed5 0000 0000 0000 0000 5d9d e6cf 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 9e 96 -1\ne66d fc -1\n-1\n\nfdcb97  RES 2,(IY+d),A*\nccb6 8406 72c6 1ba7 0000 0000 0000 0000 6dca 187f 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 64 97 -1\n18e3 9d -1\n-1\n\nfdcb98  RES 3,(IY+d),B*\n0495 312f 8000 b749 0000 0000 0000 0000 e9cb 43b8 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb da 98 -1\n4392 15 -1\n-1\n\nfdcb99  RES 3,(IY+d),C*\n2824 a485 a30b b286 0000 0000 0000 0000 10b0 d86c 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 78 99 -1\nd8e4 b5 -1\n-1\n\nfdcb9a  RES 3,(IY+d),D*\nb0cc c40c dc1a 014a 0000 0000 0000 0000 2ff9 d717 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 9c 9a -1\nd6b3 9d -1\n-1\n\nfdcb9b  RES 3,(IY+d),E*\nd092 a6c2 7900 5448 0000 0000 0000 0000 fab0 cb1e 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 83 9b -1\ncaa1 95 -1\n-1\n\nfdcb9c  RES 3,(IY+d),H*\nb58d 1ed1 e93b 9e0c 0000 0000 0000 0000 5605 03b3 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 1e 9c -1\n03d1 78 -1\n-1\n\nfdcb9d  RES 3,(IY+d),L*\nc7e9 18d3 8eed bd7d 0000 0000 0000 0000 9a7f c087 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb e6 9d -1\nc06d 53 -1\n-1\n\nfdcb9e  RES 3,(IY+d)\n81c7 71df 45d5 0ca7 0000 0000 0000 0000 648f 41bd 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb eb 9e -1\n41a8 61 -1\n-1\n\nfdcb9f  RES 3,(IY+d),A*\nebf5 dc9f d490 15be 0000 0000 0000 0000 0e12 9d49 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 50 9f -1\n9d99 89 -1\n-1\n\nfdcba0  RES 4,(IY+d),B*\n8ccb 0057 bc19 e543 0000 0000 0000 0000 8c5d d68d 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 76 a0 -1\nd703 d4 -1\n-1\n\nfdcba1  RES 4,(IY+d),C*\neee6 6da4 3a20 8bba 0000 0000 0000 0000 1de7 66c8 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 31 a1 -1\n66f9 ec -1\n-1\n\nfdcba2  RES 4,(IY+d),D*\n3f89 5120 0bd1 e669 0000 0000 0000 0000 2993 04bf 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 0e a2 -1\n04cd 47 -1\n-1\n\nfdcba3  RES 4,(IY+d),E*\n4439 6b8b 6178 1246 0000 0000 0000 0000 4cdb ad77 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 05 a3 -1\nad7c 59 -1\n-1\n\nfdcba4  RES 4,(IY+d),H*\n3385 261e a487 b3bd 0000 0000 0000 0000 4b8f c0cd 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 66 a4 -1\nc133 c5 -1\n-1\n\nfdcba5  RES 4,(IY+d),L*\n6e70 b7ed 22cd aedc 0000 0000 0000 0000 46de f1a1 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb a0 a5 -1\nf141 44 -1\n-1\n\nfdcba6  RES 4,(IY+d)\n814b 6408 3dcb 971f 0000 0000 0000 0000 5716 93f3 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 76 a6 -1\n9469 bc -1\n-1\n\nfdcba7  RES 4,(IY+d),A*\na4c2 679e c313 61df 0000 0000 0000 0000 67e6 79c4 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 66 a7 -1\n7a2a 2e -1\n-1\n\nfdcba8  RES 5,(IY+d),B*\n537c 1fed 6cbb bd26 0000 0000 0000 0000 c638 0d46 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb a9 a8 -1\n0cef b7 -1\n-1\n\nfdcba9  RES 5,(IY+d),C*\nba5a 3076 cdd7 298d 0000 0000 0000 0000 59ab 0f54 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 2b a9 -1\n0f7f 8f -1\n-1\n\nfdcbaa  RES 5,(IY+d),D*\n406a 2ed6 fa8c c633 0000 0000 0000 0000 87cb b3d1 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 0b aa -1\nb3dc 3a -1\n-1\n\nfdcbab  RES 5,(IY+d),E*\nda61 0521 a123 c7fa 0000 0000 0000 0000 b71a 8ece 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb a9 ab -1\n8e77 1f -1\n-1\n\nfdcbac  RES 5,(IY+d),H*\n34a3 81ce 07d6 f3a4 0000 0000 0000 0000 430b 0525 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 23 ac -1\n0548 9c -1\n-1\n\nfdcbad  RES 5,(IY+d),L*\n5010 918e ddbc 4f89 0000 0000 0000 0000 88c5 948f 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 4e ad -1\n94dd 37 -1\n-1\n\nfdcbae  RES 5,(IY+d)\nec0d b57e 18c6 7b01 0000 0000 0000 0000 bac6 0c1d 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 0c ae -1\n0c29 a9 -1\n-1\n\nfdcbaf  RES 5,(IY+d),A*\nb322 6731 daad 8d38 0000 0000 0000 0000 dd8f 26eb 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 0d af -1\n26f8 44 -1\n-1\n\nfdcbb0  RES 6,(IY+d),B*\nb984 796c 44b1 fef9 0000 0000 0000 0000 4069 a0cb 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 5a b0 -1\na125 76 -1\n-1\n\nfdcbb1  RES 6,(IY+d),C*\n59c3 ab13 42ee b764 0000 0000 0000 0000 8f7f f398 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 82 b1 -1\nf31a 79 -1\n-1\n\nfdcbb2  RES 6,(IY+d),D*\nf310 ceec bbfb 3569 0000 0000 0000 0000 4a6f 33f9 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 23 b2 -1\n341c 7b -1\n-1\n\nfdcbb3  RES 6,(IY+d),E*\n9c05 0f92 bd3b 553d 0000 0000 0000 0000 c75e 51d2 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 6c b3 -1\n523e 37 -1\n-1\n\nfdcbb4  RES 6,(IY+d),H*\n3e55 1338 638d 353c 0000 0000 0000 0000 44ad 4d17 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb c5 b4 -1\n4cdc e9 -1\n-1\n\nfdcbb5  RES 6,(IY+d),L*\n2f3a b709 4167 57be 0000 0000 0000 0000 b543 8edd 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 50 b5 -1\n8f2d 0f -1\n-1\n\nfdcbb6  RES 6,(IY+d)\na887 519b c91b cc91 0000 0000 0000 0000 a416 1e16 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 3a b6 -1\n1e50 13 -1\n-1\n\nfdcbb7  RES 6,(IY+d),A*\n1335 a599 9fbf c111 0000 0000 0000 0000 8bc5 00a9 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb c0 b7 -1\n0069 38 -1\n-1\n\nfdcbb8  RES 7,(IY+d),B*\nd146 1138 1a45 8259 0000 0000 0000 0000 6a03 d087 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 31 b8 -1\nd0b8 17 -1\n-1\n\nfdcbb9  RES 7,(IY+d),C*\n757b 0b9e 767b 2ad1 0000 0000 0000 0000 1498 b84e 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 3b b9 -1\nb889 b4 -1\n-1\n\nfdcbba  RES 7,(IY+d),D*\n43ef 1c58 dda3 4519 0000 0000 0000 0000 b67b 383f 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 38 ba -1\n3877 d6 -1\n-1\n\nfdcbbb  RES 7,(IY+d),E*\ndccb 7ab3 7615 4161 0000 0000 0000 0000 2942 e2fe 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 07 bb -1\ne305 6e -1\n-1\n\nfdcbbc  RES 7,(IY+d),H*\n0e07 34f5 0995 cc42 0000 0000 0000 0000 9d42 af0c 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb f8 bc -1\naf04 cf -1\n-1\n\nfdcbbd  RES 7,(IY+d),L*\n30ef e60c 9bf0 a1bf 0000 0000 0000 0000 bd1c df0d 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb aa bd -1\ndeb7 8d -1\n-1\n\nfdcbbe  RES 7,(IY+d)\n1133 bef6 5059 1089 0000 0000 0000 0000 d558 3d0f 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb c8 be -1\n3cd7 a1 -1\n-1\n\nfdcbbf  RES 7,(IY+d),A*\n83d6 c893 8db8 716b 0000 0000 0000 0000 0956 bde7 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb fd bf -1\nbde4 ac -1\n-1\n\nfdcbc0  SET 0,(IY+d),B*\n3666 676c 35e5 db0a 0000 0000 0000 0000 ea93 2b31 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 0a c0 -1\n2b3b ec -1\n-1\n\nfdcbc1  SET 0,(IY+d),C*\n3902 d498 af62 9821 0000 0000 0000 0000 48b8 bd67 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 87 c1 -1\nbcee ee -1\n-1\n\nfdcbc2  SET 0,(IY+d),D*\nad26 5a6d 6762 16c9 0000 0000 0000 0000 495a 5b2c 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 8d c2 -1\n5ab9 c2 -1\n-1\n\nfdcbc3  SET 0,(IY+d),E*\n3e6c 9a74 a2ee 9838 0000 0000 0000 0000 eafa e666 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 5a c3 -1\ne6c0 4f -1\n-1\n\nfdcbc4  SET 0,(IY+d),H*\nbf68 d00b 5283 51c2 0000 0000 0000 0000 517c 5d10 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 89 c4 -1\n5c99 61 -1\n-1\n\nfdcbc5  SET 0,(IY+d),L*\n127b db6a 00b9 5138 0000 0000 0000 0000 98f6 02bb 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb a9 c5 -1\n0264 cd -1\n-1\n\nfdcbc6  SET 0,(IY+d)\n35da 98c2 3f57 44a4 0000 0000 0000 0000 2771 76c4 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb ee c6 -1\n76b2 82 -1\n-1\n\nfdcbc7  SET 0,(IY+d),A*\n763f b86f 12d3 7e2d 0000 0000 0000 0000 d870 f30b 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 9e c7 -1\nf2a9 d7 -1\n-1\n\nfdcbc8  SET 1,(IY+d),B*\n1f81 c7c0 85da 3cdd 0000 0000 0000 0000 d854 c412 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 10 c8 -1\nc422 e9 -1\n-1\n\nfdcbc9  SET 1,(IY+d),C*\ned19 3f88 1370 e084 0000 0000 0000 0000 4fdd 8b42 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 61 c9 -1\n8ba3 b7 -1\n-1\n\nfdcbca  SET 1,(IY+d),D*\nc7e5 233b 2312 f7f9 0000 0000 0000 0000 e417 5190 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 1a ca -1\n51aa 90 -1\n-1\n\nfdcbcb  SET 1,(IY+d),E*\nbdba a964 ea38 9422 0000 0000 0000 0000 fca3 9a72 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 5e cb -1\n9ad0 70 -1\n-1\n\nfdcbcc  SET 1,(IY+d),H*\n0f4f 0261 21b0 2097 0000 0000 0000 0000 575d 14f9 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 2d cc -1\n1526 4e -1\n-1\n\nfdcbcd  SET 1,(IY+d),L*\n1b79 8f9f 31bf 9ca6 0000 0000 0000 0000 7ecb bbe9 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb a1 cd -1\nbb8a 66 -1\n-1\n\nfdcbce  SET 1,(IY+d)\n8e13 968e 1784 0a0a 0000 0000 0000 0000 1e87 b8a2 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 36 ce -1\nb8d8 45 -1\n-1\n\nfdcbcf  SET 1,(IY+d),A*\n8d0a a073 c4ba 5b69 0000 0000 0000 0000 3b47 c29c 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 70 cf -1\nc30c 7a -1\n-1\n\nfdcbd0  SET 2,(IY+d),B*\ne2bb 8635 650c 689a 0000 0000 0000 0000 1294 3beb 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb bc d0 -1\n3ba7 20 -1\n-1\n\nfdcbd1  SET 2,(IY+d),C*\n5df8 f701 9494 4967 0000 0000 0000 0000 ad00 8c65 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 11 d1 -1\n8c76 b9 -1\n-1\n\nfdcbd2  SET 2,(IY+d),D*\n9876 4bd9 3148 665a 0000 0000 0000 0000 7eac c051 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb fb d2 -1\nc04c 51 -1\n-1\n\nfdcbd3  SET 2,(IY+d),E*\n8f90 bacd e87a 538f 0000 0000 0000 0000 fe5a 0a87 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 3e d3 -1\n0ac5 e0 -1\n-1\n\nfdcbd4  SET 2,(IY+d),H*\n15e2 1820 5588 e67f 0000 0000 0000 0000 7193 9478 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 36 d4 -1\n94ae 7d -1\n-1\n\nfdcbd5  SET 2,(IY+d),L*\n1409 6535 c371 abe2 0000 0000 0000 0000 2e10 8608 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 48 d5 -1\n8650 98 -1\n-1\n\nfdcbd6  SET 2,(IY+d)\n7801 78b6 d191 054a 0000 0000 0000 0000 2065 6aa3 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb c9 d6 -1\n6a6c 7c -1\n-1\n\nfdcbd7  SET 2,(IY+d),A*\n1b6a 266e 387f 7fcb 0000 0000 0000 0000 1941 36ab 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb be d7 -1\n3669 95 -1\n-1\n\nfdcbd8  SET 3,(IY+d),B*\n7b1b a191 efee 55b9 0000 0000 0000 0000 f789 43f8 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb bc d8 -1\n43b4 d8 -1\n-1\n\nfdcbd9  SET 3,(IY+d),C*\n0faf 4eda c556 6ed3 0000 0000 0000 0000 3fc3 0a66 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 16 d9 -1\n0a7c f4 -1\n-1\n\nfdcbda  SET 3,(IY+d),D*\n9ea1 8186 c045 d6e0 0000 0000 0000 0000 34d3 d0f0 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb e8 da -1\nd0d8 6b -1\n-1\n\nfdcbdb  SET 3,(IY+d),E*\n5ee0 bdea d00e 513f 0000 0000 0000 0000 690a 8c29 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 7a db -1\n8ca3 15 -1\n-1\n\nfdcbdc  SET 3,(IY+d),H*\n5cfa 2e2b 1d17 dbf6 0000 0000 0000 0000 a4f2 593a 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 64 dc -1\n599e 15 -1\n-1\n\nfdcbdd  SET 3,(IY+d),L*\n8773 70a6 83ce 52b8 0000 0000 0000 0000 35da 1d94 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 75 dd -1\n1e09 28 -1\n-1\n\nfdcbde  SET 3,(IY+d)\n8310 fa01 6c69 252a 0000 0000 0000 0000 5291 c9e0 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 17 de -1\nc9f7 41 -1\n-1\n\nfdcbdf  SET 3,(IY+d),A*\n780d a722 e78e 50ba 0000 0000 0000 0000 9d67 eac3 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 93 df -1\nea56 ef -1\n-1\n\nfdcbe0  SET 4,(IY+d),B*\n10ef 4101 2ca5 f752 0000 0000 0000 0000 4747 1507 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 56 e0 -1\n155d b9 -1\n-1\n\nfdcbe1  SET 4,(IY+d),C*\ne4cb 6f72 1c11 1426 0000 0000 0000 0000 189b 0e0d 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb d1 e1 -1\n0dde 16 -1\n-1\n\nfdcbe2  SET 4,(IY+d),D*\n11a9 bae8 938b bac4 0000 0000 0000 0000 d8ed e49c 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 50 e2 -1\ne4ec c2 -1\n-1\n\nfdcbe3  SET 4,(IY+d),E*\n8832 952b 02b2 26ef 0000 0000 0000 0000 fb55 ada8 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb ca e3 -1\nad72 ba -1\n-1\n\nfdcbe4  SET 4,(IY+d),H*\n3989 4142 89e2 785b 0000 0000 0000 0000 0bf7 5474 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 62 e4 -1\n54d6 7b -1\n-1\n\nfdcbe5  SET 4,(IY+d),L*\ne5c5 b86d 41bb 315e 0000 0000 0000 0000 1a78 a52d 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb da e5 -1\na507 4c -1\n-1\n\nfdcbe6  SET 4,(IY+d)\nfd89 d888 1e2f ddf5 0000 0000 0000 0000 42f5 8b06 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 76 e6 -1\n8b7c 45 -1\n-1\n\nfdcbe7  SET 4,(IY+d),A*\n2025 d3e9 d4b6 aa30 0000 0000 0000 0000 88bd b597 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 11 e7 -1\nb5a8 a6 -1\n-1\n\nfdcbe8  SET 5,(IY+d),B*\n514d c2ab 37b5 57de 0000 0000 0000 0000 a4ec 0a77 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb ed e8 -1\n0a64 d0 -1\n-1\n\nfdcbe9  SET 5,(IY+d),C*\n974e d28e d5cb 6bd4 0000 0000 0000 0000 158a a84e 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 35 e9 -1\na883 2f -1\n-1\n\nfdcbea  SET 5,(IY+d),D*\n3ef4 3fc6 4a44 e9a4 0000 0000 0000 0000 c877 7593 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 93 ea -1\n7526 1b -1\n-1\n\nfdcbeb  SET 5,(IY+d),E*\n798f 5e9b 940e 2e52 0000 0000 0000 0000 d6ad 2411 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb d0 eb -1\n23e1 47 -1\n-1\n\nfdcbec  SET 5,(IY+d),H*\n38a4 07c0 6cee e715 0000 0000 0000 0000 f160 d2eb 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb f3 ec -1\nd2de 49 -1\n-1\n\nfdcbed  SET 5,(IY+d),L*\ne0bc 70c1 de35 81c5 0000 0000 0000 0000 d57f 0eab 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 58 ed -1\n0f03 10 -1\n-1\n\nfdcbee  SET 5,(IY+d)\n5fcb 9007 1736 aca8 0000 0000 0000 0000 4bab 42bc 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 02 ee -1\n42be d0 -1\n-1\n\nfdcbef  SET 5,(IY+d),A*\n4ee3 d344 cb5b aeb5 0000 0000 0000 0000 de5f 2272 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 58 ef -1\n22ca 09 -1\n-1\n\nfdcbf0  SET 6,(IY+d),B*\n1080 b270 1b5b a9b7 0000 0000 0000 0000 e89d ee9e 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 45 f0 -1\neee3 2c -1\n-1\n\nfdcbf1  SET 6,(IY+d),C*\n1702 c43b d138 316f 0000 0000 0000 0000 8067 4783 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 2f f1 -1\n47b2 dc -1\n-1\n\nfdcbf2  SET 6,(IY+d),D*\n732a 4cd1 77fe 4814 0000 0000 0000 0000 42f1 ea97 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 2c f2 -1\neac3 5e -1\n-1\n\nfdcbf3  SET 6,(IY+d),E*\n6b97 59d3 f546 7530 0000 0000 0000 0000 6670 7d90 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 38 f3 -1\n7dc8 0c -1\n-1\n\nfdcbf4  SET 6,(IY+d),H*\n7af0 a81f 5d3a 799b 0000 0000 0000 0000 e12b 309c 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb d0 f4 -1\n306c 0e -1\n-1\n\nfdcbf5  SET 6,(IY+d),L*\n1370 f6b2 aaa2 7f0a 0000 0000 0000 0000 c9f6 6b1f 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 55 f5 -1\n6b74 f8 -1\n-1\n\nfdcbf6  SET 6,(IY+d)\n7c43 fcd1 34bd f4ab 0000 0000 0000 0000 ef33 c61a 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 56 f6 -1\nc670 5d -1\n-1\n\nfdcbf7  SET 6,(IY+d),A*\ne6da 231a 7bb1 800d 0000 0000 0000 0000 e37e 5789 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 9e f7 -1\n5727 66 -1\n-1\n\nfdcbf8  SET 7,(IY+d),B*\nfa29 ee74 d7c4 afaf 0000 0000 0000 0000 512c de7a 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 54 f8 -1\ndece 7a -1\n-1\n\nfdcbf9  SET 7,(IY+d),C*\n4662 a71b 5065 ed06 0000 0000 0000 0000 279e 99e3 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 30 f9 -1\n9a13 c6 -1\n-1\n\nfdcbfa  SET 7,(IY+d),D*\n9426 53ec 5016 6c99 0000 0000 0000 0000 8b99 bd79 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 09 fa -1\nbd82 f4 -1\n-1\n\nfdcbfb  SET 7,(IY+d),E*\n5343 b212 09ca e3c6 0000 0000 0000 0000 cd2b f875 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb ba fb -1\nf82f ed -1\n-1\n\nfdcbfc  SET 7,(IY+d),H*\n0965 4392 ca25 2baa 0000 0000 0000 0000 f023 6623 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 56 fc -1\n6679 65 -1\n-1\n\nfdcbfd  SET 7,(IY+d),L*\n1751 233c 6214 d119 0000 0000 0000 0000 c415 5d2b 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 25 fd -1\n5d50 27 -1\n-1\n\nfdcbfe  SET 7,(IY+d)\nb4cf 5639 677b 0ca2 0000 0000 0000 0000 ddc5 4e4f 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb 88 fe -1\n4dd7 4a -1\n-1\n\nfdcbff  SET 7,(IY+d),A*\nf151 13da 7c56 f025 0000 0000 0000 0000 2b36 2aed 0000 0000\n00 00 0 0 0 0     1\n0000 fd cb e4 ff -1\n2ad1 97 -1\n-1\n\nfde1    POP IY\n828e 078b 1e35 8f1c 0000 0000 0000 0000 4827 b742 716e 0000\n00 00 0 0 0 0     1\n0000 fd e1 -1\n716e d5 92 -1\n-1\n\nfde3    EX (SP),IY\n4298 c805 6030 4292 0000 0000 0000 0000 473b 9510 1a38 0000\n00 00 0 0 0 0     1\n0000 fd e3 -1\n1a38 e0 0f -1\n-1\n\nfde5    PUSH IY\nd139 aa0d bf2b 2a56 0000 0000 0000 0000 e138 d4da a8e1 0000\n00 00 0 0 0 0     1\n0000 fd e5 -1\n-1\n\nfde9    JP (IY)\nc14f 2eb6 edf0 27cf 0000 0000 0000 0000 09ee a2a4 0000 0000\n00 00 0 0 0 0     1\n0000 fd e9 -1\n-1\n\nfdf9    LD SP,IY\nc260 992e d544 67fb 0000 0000 0000 0000 ba5e 3596 353f 0000\n00 00 0 0 0 0     1\n0000 fd f9 -1\n-1\n\nfe      CP n\n6900 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0     1\n0000 fe 82 -1\n-1\n\nff      RST 38H\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 5507 6d33\n00 00 0 0 0 0     1\n6d33 ff -1\n-1\n"
  },
  {
    "path": "cpu/toplevel/gencoremodules.py",
    "content": "#!/usr/bin/env python3\n#\n# This script reads and parses all top-level modules and generates a core block\n# file containing instantiation of these modules. This generated file is included\n# by core.vh\n#\n#-------------------------------------------------------------------------------\n#  Copyright (C) 2016  Goran Devic\n#\n#  This program is free software; you can redistribute it and/or modify it\n#  under the terms of the GNU General Public License as published by the Free\n#  Software Foundation; either version 2 of the License, or (at your option)\n#  any later version.\n#\n#  This program is distributed in the hope that it will be useful, but WITHOUT\n#  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n#  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n#  more details.\n#-------------------------------------------------------------------------------\nimport os\n\n# Define a set of module cross-connections. These are the chip's internal buses\n# which we inject as connections as we generate a list of module instances\nxconnections = [\n    ['interrupts', 'db', 'db0[4:3]'],\n    ['ir', 'db', 'db0[7:0]'],\n    ['alu_control', 'db', 'db1[7:0]'],\n    ['alu_control', 'op543', '{pla[104],pla[103],pla[102]}'],\n    ['alu_flags', 'db', 'db1[7:0]'],\n    ['alu', 'db', 'db2[7:0]'],\n    ['alu', 'bsel', 'db0[5:3]'],\n    ['reg_file', 'db_hi_ds', 'db2[7:0]'],\n    ['reg_file', 'db_lo_ds', 'db1[7:0]'],\n    ['reg_file', 'db_hi_as', 'db_hi_as[7:0]'],\n    ['reg_file', 'db_lo_as', 'db_lo_as[7:0]'],\n    ['address_latch', 'abus', '{db_hi_as[7:0], db_lo_as[7:0]}'],\n    ['bus_control', 'db', 'db0[7:0]']\n]\n\n# Define a list of modules that are not used (but listed in 'top-level-files.txt' )\nskip_modules = ['address_pins', 'data_pins', 'control_pins_n']\n\n# For error-checking, make sure every xconnection entry has been utilized\nxcount = len(xconnections)\n\ndef connect(module, wire):\n    global xcount\n    for xconnection in xconnections:\n        m, w, xcon = xconnection\n        if module==m and wire==w:\n            print(\"Cross-connecting:\", module, wire, \"->\", xcon)\n            xcount -= 1\n            return xcon\n    return wire\n\ndef parse(wires, lines):\n    while(len(lines)>0 and lines[0].startswith(');')==False):\n        line = lines[0].strip()\n        lines.pop(0)\n        if len(line)==0 or line[0]=='(' or line[0]=='/':\n            continue\n        tokens = line.split()\n        if len(tokens)>=3 and tokens[0] in ['input', 'output']:\n            tokens.pop(0)\n        if len(tokens)>=2 and tokens[0] in ['wire', 'reg']:\n            tokens.pop(0)\n        if len(tokens)>=2 and tokens[0].startswith('['):\n            tokens.pop(0)\n        if len(tokens)>=2 and tokens[0]=='`include':\n            include_file = tokens[1].replace('\"', '')\n            with open('../control/' + include_file) as f:\n                included_lines = f.read().splitlines()\n            parse(wires, included_lines)\n            continue\n        name = tokens[0]\n        if name.endswith(','):\n            name = name[:-1]\n        wires.append(name)\n\nwith open('../top-level-files.txt') as f:\n    files = f.read().splitlines()\n\n# Create a file that should be included in the top-level core source\nwith open('coremodules.vh', 'w') as file1:\n    file1.write(\"// Automatically generated by gencoremodules.py\\n\")\n\n# Read and parse each file from the list of input files\nfor infile in files:\n    if not os.path.isfile('../' + infile):\n        continue\n    with open('../' + infile, \"r\") as f:\n        lines = f.read().splitlines()\n\n    # Find 'module' section; read and generate instantiation statement\n    while(len(lines)>0 and lines[0].startswith('module ')==False):\n        lines.pop(0)\n    if len(lines)==0:\n        continue\n\n    module_name = lines[0].split()[1]\n    lines.pop(0)\n    if module_name.endswith('('):\n        module_name = module_name[:-1]\n    if module_name in skip_modules:\n        continue\n\n    # Read a list of input/output wires, one per line\n    wires = []\n    parse(wires, lines)\n\n    # Print the names of all parsed signals in a module instantiation format\n    with open('coremodules.vh', 'a') as file1:\n        file1.write(\"\\n\" + module_name + \" \" + module_name + \"_(\\n\")\n        while(len(wires)>0):\n            wire = wires.pop(0)\n            terminator = ','\n            if len(wires)==0:\n                terminator = \"\\n);\"\n            file1.write(\"    .\" + wire + \" (\" + connect(module_name, wire) + \")\" + terminator + \"\\n\")\n\nassert(xcount==0)\n\n# Touch files that include 'coremodules.vh' to ensure it will recompile correctly\nos.utime(\"core.vh\", None)\n"
  },
  {
    "path": "cpu/toplevel/genfuse.py",
    "content": "#!/usr/bin/env python3\n#\n# This script generates a test include file from a set of \"Fuse\" test vectors.\n#\n# Three common testing configurations are:\n#\n# 1. You want to test a specific instruction only, say 02 LD (BC),A (see Fuse tests.in)\n#    start_test = \"02\"\n#    run_tests = 1\n#    regress = 0\n#\n# 2. You want to run a smaller subset of 'regression' tests:\n#    start_test = \"00\"\n#    run_tests = 1\n#    regress = 1\n#\n# 3. You want to run a full Fuse test suite (all instructions!):\n#    start_test = \"00\"\n#    run_tests = -1\n#    regress = 0\n#\n# Orthogonal to that, set m1wait to a non-zero value to test nWAIT insertion at\n# the first M1 cycle of an instruction. Change it to the number of T-clocks to\n# insert.\n#\n#-------------------------------------------------------------------------------\n#  Copyright (C) 2016  Goran Devic\n#\n#  This program is free software; you can redistribute it and/or modify it\n#  under the terms of the GNU General Public License as published by the Free\n#  Software Foundation; either version 2 of the License, or (at your option)\n#  any later version.\n#\n#  This program is distributed in the hope that it will be useful, but WITHOUT\n#  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n#  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n#  more details.\n#-------------------------------------------------------------------------------\nimport os\n\n# Start with this test name (this is a string; see tests files)\nstart_test = \"00\"\n\n# Number of tests to run; use -1 to run all tests\nrun_tests = 1\n\n# Set this to 1 to use regression test instead of selected or full 'tests.*'\n# Regression test is a shorter set of tests and ignores start_test and run_tests values\nregress = 1\n\n# Set this to a number of WAIT cycles to add at M1 clock period or 0 not to test nWAIT\nm1wait = 0\n\n#------------------------------------------------------------------------------\n# Determine which test files to use\ntests_in = 'fuse/tests.in'\ntests_expected = 'fuse/tests.expected'\n\n# Regression testing executes all regression tests\nif regress:\n    tests_in = 'fuse/regress.in'\n    tests_expected = 'fuse/regress.expected'\n    start_test = \"00\"\n    run_tests = -1\n\nwith open(tests_in) as f1:\n    t1 = f1.read().splitlines()\n# Remove all tests until the one we need to start with. Tests are separated by empty lines.\nwhile t1[0].split(\" \")[0]!=start_test:\n    while len(t1.pop(0))>0:\n        pass\nt1 = list(filter(None, t1)) # Filter out empty lines\n\nwith open(tests_expected) as f2:\n    t2 = f2.read().splitlines()\nwhile t2[0].split(\" \")[0]!=start_test:\n    while len(t2.pop(0))>0:\n        pass\n\n# Count total clocks required to run all selected tests\ntotal_clks = 0\n\ndef RegWrite(reg, hex):\n    global total_clks\n    ftest.write(\"   // Preset \" + reg + \"\\n\")\n    ftest.write(\"   force dut.reg_file_.b2v_latch_\" + reg + \"_lo.we=1;\\n\")\n    ftest.write(\"   force dut.reg_file_.b2v_latch_\" + reg + \"_hi.we=1;\\n\")\n    ftest.write(\"   force dut.reg_file_.b2v_latch_\" + reg + \"_lo.db=8'h\" + hex[2:] + \";\\n\")\n    ftest.write(\"   force dut.reg_file_.b2v_latch_\" + reg + \"_hi.db=8'h\" + hex[0:2] + \";\\n\")\n    ftest.write(\"#2 release dut.reg_file_.b2v_latch_\" + reg + \"_lo.we;\\n\")\n    ftest.write(\"   release dut.reg_file_.b2v_latch_\" + reg + \"_hi.we;\\n\")\n    ftest.write(\"   release dut.reg_file_.b2v_latch_\" + reg + \"_lo.db;\\n\")\n    ftest.write(\"   release dut.reg_file_.b2v_latch_\" + reg + \"_hi.db;\\n\")\n    total_clks = total_clks + 2\n\ndef RegRead(reg, hex):\n    ftest.write(\"   if (dut.reg_file_.b2v_latch_\" + reg + \"_lo.latch!==8'h\" + hex[2:] +  \") $fdisplay(f,\\\"* Reg \" + reg + \" \" + reg[1] + \"=%h !=\" + hex[2:] +  \"\\\",dut.reg_file_.b2v_latch_\" + reg + \"_lo.latch);\\n\")\n    ftest.write(\"   if (dut.reg_file_.b2v_latch_\" + reg + \"_hi.latch!==8'h\" + hex[0:2] + \") $fdisplay(f,\\\"* Reg \" + reg + \" \" + reg[0] + \"=%h !=\" + hex[0:2] + \"\\\",dut.reg_file_.b2v_latch_\" + reg + \"_hi.latch);\\n\")\n\n#---------------------------- START -----------------------------------\n# Create a file that should be included in the test_fuse source\nftest = open('test_fuse.vh', 'w')\nftest.write(\"// Automatically generated by genfuse.py\\n\\n\")\n\n# Initial pre-test state is reset and control signals asserted\nftest.write(\"force dut.resets_.clrpc=0;\\n\")\nftest.write(\"force dut.reg_file_.reg_gp_we=0;\\n\")\nftest.write(\"force dut.reg_control_.ctl_reg_sys_we=0;\\n\")\nftest.write(\"force dut.z80_top_ifc_n.fpga_reset=1;\\n\")\nftest.write(\"#2 // Start test loop\\n\\n\")\ntotal_clks = total_clks + 2\n\n# Read each test from the testdat.in file\nwhile True:\n    if len(t1)==0 or run_tests==0:\n        break\n    run_tests = run_tests-1\n\n    # Clear opcode register before starting a new instruction\n    ftest.write(\"   force dut.ir_.ctl_ir_we=1;\\n\")\n    ftest.write(\"   force dut.ir_.db=0;\\n\")\n    ftest.write(\"#2 release dut.ir_.ctl_ir_we;\\n\")\n    ftest.write(\"   release dut.ir_.db;\\n\")\n    total_clks = total_clks + 2\n\n    # Format of the test.in file:\n    # <arbitrary test description>\n    # AF BC DE HL AF' BC' DE' HL' IX IY SP PC\n    # I R IFF1 IFF2 IM <halted> <tstates>\n    name = t1.pop(0)\n    ftest.write(\"   $fdisplay(f,\\\"Testing opcode \" + name + \"\\\");\\n\")\n    name = name.split(\" \")[0]\n    r = t1.pop(0).split(' ')\n    r = list(filter(None, r))\n    # 0  1  2  3  4   5   6   7   8  9  10 11   (index)\n    # AF BC DE HL AF' BC' DE' HL' IX IY SP PC\n    RegWrite(\"af\", r[0])\n    RegWrite(\"bc\", r[1])\n    RegWrite(\"de\", r[2])\n    RegWrite(\"hl\", r[3])\n    RegWrite(\"af2\", r[4])\n    RegWrite(\"bc2\", r[5])\n    RegWrite(\"de2\", r[6])\n    RegWrite(\"hl2\", r[7])\n    RegWrite(\"ix\", r[8])\n    RegWrite(\"iy\", r[9])\n    RegWrite(\"sp\", r[10])\n    RegWrite(\"wz\", \"0000\")       # Initialize WZ with 0\n    RegWrite(\"pc\", r[11])\n\n    s = t1.pop(0).split(' ')\n    s = list(filter(None, s))\n    # 0 1 2    3    4  5        6          (index)\n    # I R IFF1 IFF2 IM <halted> <tstates?>\n    RegWrite(\"ir\", s[0]+s[1])\n    # TODO: Store IFF1/IFF2, IM, in_halt\n\n    # Read memory configuration from the test.in until the line contains only -1\n    while True:\n        m = t1.pop(0).split(' ')\n        if m[0]==\"-1\":\n            break\n        address = int(m.pop(0),16)\n        ftest.write(\"   // Preset memory\\n\")\n        while True:\n            d = m.pop(0)\n            if d==\"-1\":\n                break\n            ftest.write(\"   ram.Mem[\" + str(address) + \"] = 8'h\" + d + \";\\n\")\n            address = address+1\n\n    # We need to prepare the IO map to be able to handle IN/OUT instructions.\n    # Copy tests.out (so we don't modify it just yet), parse all PR and PW (port read, write)\n    # statements and then fill in our IO map (for IO reads) or stack the check statements to be\n    # used below after the opcode has executed (for IO writes)\n    check_io = []               # List of check statements (for OUT instructions)\n    t2b = list(t2)\n    while True:\n        m = t2b.pop(0).split(' ')\n        m = list(filter(None, m))\n        if len(m)==0 or m[0]==\"-1\":\n            break\n        if len(m)==4 and m[1]==\"PR\":\n            address = int(m[2],16)\n            ftest.write(\"   io.IO[\" + str(address) + \"] = 8'h\" + m[3] + \";\\n\")\n        if len(m)==4 and m[1]==\"PW\":\n            address = int(m[2],16)\n            check_io.append(\"   if (io.IO[\" + str(address) + \"]!==8'h\" + m[3] + \") $fdisplay(f,\\\"* IO[\" + hex(address)[2:] + \"]=%h !=\" + m[3] + \"\\\",io.IO[\" + str(address) + \"]);\\n\")\n\n    # Prepare instruction to be run. By releasing the fpga_reset, internal CPU reset will be active for 1T.\n    # Due to the instruction execution overlap, first 2T of an instruction may be writing\n    # value back to a general purpose register (like AF) and we need to prevent that.\n    # Similarly, we let the execution continues 2T into the next instruction but we prevent\n    # it from writing to system registers so it cannot update PC and IR.\n    ftest.write(\"   force dut.z80_top_ifc_n.fpga_reset=0;\\n\")\n    ftest.write(\"   force dut.address_latch_.Q=16'h\" + r[11] +\";\\n\") # Force PC into the address latch\n    ftest.write(\"   release dut.reg_control_.ctl_reg_sys_we;\\n\")\n    ftest.write(\"   release dut.reg_file_.reg_gp_we;\\n\")\n    ftest.write(\"#2 // Execute: M1/T1 start\\n\") # 1T (#2) overlaps the reset cycle\n    ftest.write(\"#1 release dut.address_latch_.Q;\\n\")\n    total_clks = total_clks + 3 # We borrow 1T (#2) to to force the PC to be what our test wants...\n    ftest.write(\"#1\\n\")\n    total_clks = total_clks + 1\n\n    # Read and parse the tests expected list which contains the expected results of our run,\n    # including the number of clocks for a particular instruction\n    xname = t2.pop(0).split()[0]\n    if name!=xname:\n        print(\"Test \" + name + \" does not correspond to test.expected \" + xname)\n        break\n    # Skip the memory access logs; read to the expected register content list\n    while True:\n        l = t2.pop(0)\n        if l[0]!=' ':\n            break\n    r = l.split(' ')\n    r = list(filter(None, r))\n\n    s = t2.pop(0).split(' ')\n    s = list(filter(None, s))\n\n    ticks = int(s[6]) * 2 - 2       # We return 1T (#2) that we borrowed to set PC\n    total_clks = total_clks + ticks\n\n    # Test WAIT state insertion at the M1 clock cycle\n    if m1wait:\n        ftest.write(\"   z.nWAIT <= 0;\\n\")\n        ftest.write(\"#\" + str(m1wait * 2) + \" z.nWAIT <= 1; // nWAIT during M1\\n\")\n        total_clks = total_clks + m1wait * 2\n\n    ftest.write(\"#\" + str(ticks) + \" // Wait for opcode end\\n\")\n\n    ftest.write(\"   force dut.reg_control_.ctl_reg_sys_we=0;\\n\")\n    ftest.write(\"#2 pc=z.A;\\n\")     # Extra 2T for the next instruction overlap & read PC on the ABus\n    ftest.write(\"#2\\n\")             # Complete this instruction\n    ftest.write(\"#1 force dut.reg_file_.reg_gp_we=0;\\n\")    # Add 1/2 clock for any pending flops to latch (mainly the F register)\n    ftest.write(\"   force dut.z80_top_ifc_n.fpga_reset=1;\\n\")\n    total_clks = total_clks + 5\n\n    # Now we can issue register reading commands\n    # We are guided on what to read and check by the content of \"test.expected\" file\n\n    # Special case are the register exchange instructions and there are 3 of them.\n    # The exchange operations are not tested directly; instead, the latches that control register bank access are\n    if xname==\"08\":                 # EX AF,AF1\n        r[0],r[4] = r[4],r[0]\n        ftest.write(\"   if (dut.reg_control_.bank_af!==1) $fdisplay(f,\\\"* Bank AF!=1\\\");\\n\")\n    if xname==\"eb\":                 # EX DE,HL\n        r[2],r[3] = r[3],r[2]\n        ftest.write(\"   if (dut.reg_control_.bank_hl_de1!==1) $fdisplay(f,\\\"* Bank HL/DE!=1\\\");\\n\")\n    if xname==\"d9\":                 # EXX\n        r[1],r[5] = r[5],r[1]\n        r[2],r[6] = r[6],r[2]\n        r[3],r[7] = r[7],r[3]\n        ftest.write(\"   if (dut.reg_control_.bank_exx!==1) $fdisplay(f,\\\"* Bank EXX!=1\\\");\\n\")\n\n    # Read the result: registers and memory\n    # 0  1  2  3  4   5   6   7   8  9  10 11   (index)\n    # AF BC DE HL AF' BC' DE' HL' IX IY SP PC\n    RegRead(\"af\", r[0])\n    RegRead(\"bc\", r[1])\n    RegRead(\"de\", r[2])\n    RegRead(\"hl\", r[3])\n    RegRead(\"af2\", r[4])\n    RegRead(\"bc2\", r[5])\n    RegRead(\"de2\", r[6])\n    RegRead(\"hl2\", r[7])\n    RegRead(\"ix\", r[8])\n    RegRead(\"iy\", r[9])\n    RegRead(\"sp\", r[10])\n    #RegRead(\"pc\", r[11]) Instead of PC, we read the address bus of the next instruction\n    ftest.write(\"   if (pc!==16'h\" + r[11] +  \") $fdisplay(f,\\\"* PC=%h !=\" + r[11] +  \"\\\",pc);\\n\")\n\n    # 0 1 2    3    4  5        6          (index)\n    # I R IFF1 IFF2 IM <halted> <tstates?>\n    RegRead(\"ir\", s[0]+s[1])\n\n    # Read memory configuration until an empty line or -1 at the end\n    while True:\n        m = t2.pop(0).split(' ')\n        m = list(filter(None, m))\n        if len(m)==0 or m[0]==\"-1\":\n            break\n        address = int(m.pop(0),16)\n        while True:\n            d = m.pop(0)\n            if d==\"-1\":\n                break\n            ftest.write(\"   if (ram.Mem[\" + str(address) + \"]!==8'h\" + d + \") $fdisplay(f,\\\"* Mem[\" + hex(address)[2:] + \"]=%h !=\" + d + \"\\\",ram.Mem[\" + str(address) + \"]);\\n\")\n            address = address+1\n    # Read a list of IO checks that was compiled while parsing the initial condition\n    while len(check_io)>0:\n        ftest.write(check_io.pop(0))\n    ftest.write(\"#1 // End opcode\\n\\n\")\n    total_clks = total_clks + 1\n\n# Write out the total number of clocks that this set of tests takes to execute\nftest.write(\"`define TOTAL_CLKS \" + str(total_clks) + \"\\n\")\nftest.write(\"$fdisplay(f,\\\"=== Tests completed ===\\\");\\n\")\nftest.close()\n\n# Touch a file that includes 'test_fuse.vh' to ensure it will recompile correctly\nos.utime(\"test_fuse.sv\", None)\n"
  },
  {
    "path": "cpu/toplevel/genglobals.py",
    "content": "#!/usr/bin/env python3\n#\n# This script reads and parses selected Verilog and SystemVerilog modules\n# and generates a set of Verilog include files for the Z80 top-level block.\n#\n#-------------------------------------------------------------------------------\n#  Copyright (C) 2014  Goran Devic\n#\n#  This program is free software; you can redistribute it and/or modify it\n#  under the terms of the GNU General Public License as published by the Free\n#  Software Foundation; either version 2 of the License, or (at your option)\n#  any later version.\n#\n#  This program is distributed in the hope that it will be useful, but WITHOUT\n#  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n#  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n#  more details.\n#-------------------------------------------------------------------------------\nimport os\n\nwith open('../top-level-files.txt') as f:\n    files = f.read().splitlines()\n\n# Create a file that should be included in the top-level source\nwith open('globals.vh', 'w') as file1:\n    file1.write(\"// Automatically generated by genglobals.py\\n\")\n\n# Keep track of duplicated symbols across all files\nglobals = []\n\n# Read and parse each file from the list of input files\nfor infile in files:\n    wires = []\n    if not os.path.isfile('../' + infile):\n        continue\n    with open('../' + infile, \"r\") as f:\n        for line in f:\n            info = line.split()\n            if len(info)>2:\n                # There can be only one driver for each signal so we read only the outputs\n                if info[0]==\"output\" and (info[1]==\"wire\" or info[1]==\"reg\" or info[1]==\"logic\"):\n                    # There are 2 cases: wires and buses\n                    if info[2].startswith('['):\n                        wires.append(info[2] + ' ' + info[3].strip(';,'))\n                    else:\n                        wires.append(info[2].strip(';,'))\n\n    if len(wires)>0:\n        with open('globals.vh', 'a') as file1:\n            file1.write(\"\\n// Module: \" + infile + \"\\n\")\n            for wire in wires:\n                # Everything in globals is a wire\n                # (Can't use 'logic' since some buses are bidirectional)\n                if wire in globals:\n                    file1.write(\"// wire \" + wire + \"; (previously defined)\\n\")\n                else:\n                    file1.write(\"wire \" + wire + \";\\n\")\n                    globals.append(wire)\n\n# Touch files that include 'globals.vh' to ensure it will recompile correctly\nos.utime(\"core.vh\", None)\nos.utime(\"z80_top_direct_n.v\", None)\nos.utime(\"z80_top_ifc_n.sv\", None)\n"
  },
  {
    "path": "cpu/toplevel/globals.vh",
    "content": "// Automatically generated by genglobals.py\n\n// Module: control/clk_delay.v\nwire hold_clk_iorq;\nwire hold_clk_wait;\nwire iorq_Tw;\nwire busack;\nwire pin_control_oe;\nwire hold_clk_busrq;\nwire nhold_clk_wait;\n\n// Module: control/decode_state.v\nwire in_halt;\nwire table_cb;\nwire table_ed;\nwire table_xx;\nwire use_ix;\nwire use_ixiy;\nwire in_alu;\nwire repeat_en;\n\n// Module: control/exec_module.vh\nwire ctl_state_iy_set;\nwire ctl_state_ixiy_clr;\nwire ctl_state_ixiy_we;\nwire ctl_state_halt_set;\nwire ctl_state_tbl_ed_set;\nwire ctl_state_tbl_cb_set;\nwire ctl_state_alu;\nwire ctl_repeat_we;\nwire ctl_state_tbl_we;\nwire ctl_iff1_iff2;\nwire ctl_iffx_we;\nwire ctl_iffx_bit;\nwire ctl_im_we;\nwire ctl_no_ints;\nwire ctl_ir_we;\nwire ctl_mRead;\nwire ctl_mWrite;\nwire ctl_iorw;\nwire ctl_shift_en;\nwire ctl_daa_oe;\nwire ctl_alu_op_low;\nwire ctl_cond_short;\nwire ctl_alu_core_hf;\nwire ctl_eval_cond;\nwire ctl_66_oe;\nwire [1:0] ctl_pf_sel;\nwire ctl_alu_oe;\nwire ctl_alu_shift_oe;\nwire ctl_alu_op2_oe;\nwire ctl_alu_res_oe;\nwire ctl_alu_op1_oe;\nwire ctl_alu_bs_oe;\nwire ctl_alu_op1_sel_bus;\nwire ctl_alu_op1_sel_low;\nwire ctl_alu_op1_sel_zero;\nwire ctl_alu_op2_sel_zero;\nwire ctl_alu_op2_sel_bus;\nwire ctl_alu_op2_sel_lq;\nwire ctl_alu_sel_op2_neg;\nwire ctl_alu_sel_op2_high;\nwire ctl_alu_core_R;\nwire ctl_alu_core_V;\nwire ctl_alu_core_S;\nwire ctl_flags_oe;\nwire ctl_flags_bus;\nwire ctl_flags_alu;\nwire ctl_flags_nf_set;\nwire ctl_flags_cf_set;\nwire ctl_flags_cf_cpl;\nwire ctl_flags_cf_we;\nwire ctl_flags_sz_we;\nwire ctl_flags_xy_we;\nwire ctl_flags_hf_we;\nwire ctl_flags_pf_we;\nwire ctl_flags_nf_we;\nwire ctl_flags_cf2_we;\nwire ctl_flags_hf_cpl;\nwire ctl_flags_use_cf2;\nwire ctl_flags_hf2_we;\nwire ctl_flags_nf_clr;\nwire ctl_alu_zero_16bit;\nwire ctl_flags_cf2_sel_shift;\nwire ctl_flags_cf2_sel_daa;\nwire ctl_sw_4u;\nwire ctl_reg_in_hi;\nwire ctl_reg_in_lo;\nwire ctl_reg_out_lo;\nwire ctl_reg_out_hi;\nwire ctl_reg_exx;\nwire ctl_reg_ex_af;\nwire ctl_reg_ex_de_hl;\nwire ctl_reg_use_sp;\nwire ctl_reg_sel_pc;\nwire ctl_reg_sel_ir;\nwire ctl_reg_sel_wz;\nwire ctl_reg_gp_we;\nwire ctl_reg_not_pc;\nwire ctl_reg_sys_we_lo;\nwire ctl_reg_sys_we_hi;\nwire ctl_reg_sys_we;\nwire ctl_sw_4d;\nwire [1:0] ctl_reg_gp_hilo;\nwire [1:0] ctl_reg_gp_sel;\nwire [1:0] ctl_reg_sys_hilo;\nwire ctl_inc_cy;\nwire ctl_inc_dec;\nwire ctl_al_we;\nwire ctl_inc_limit6;\nwire ctl_bus_inc_oe;\nwire ctl_apin_mux;\nwire ctl_apin_mux2;\nwire ctl_bus_ff_oe;\nwire ctl_bus_zero_oe;\nwire ctl_sw_1u;\nwire ctl_sw_1d;\nwire ctl_sw_2u;\nwire ctl_sw_2d;\nwire ctl_sw_mask543_en;\nwire ctl_bus_db_we;\nwire ctl_bus_db_oe;\n\n// Module: control/execute.v\nwire nextM;\nwire setM1;\nwire fFetch;\nwire fMRead;\nwire fMWrite;\nwire fIORead;\nwire fIOWrite;\n\n// Module: control/interrupts.v\nwire iff2;\nwire im1;\nwire im2;\nwire in_nmi;\nwire in_intr;\n\n// Module: control/ir.v\nwire [7:0] opcode;\n\n// Module: control/pin_control.v\nwire bus_ab_pin_we;\nwire bus_db_pin_oe;\nwire bus_db_pin_re;\n\n// Module: control/pla_decode.v\nwire [104:0] pla;\n\n// Module: control/resets.v\nwire clrpc;\nwire nreset;\n\n// Module: control/memory_ifc.v\nwire nM1_out;\nwire nRFSH_out;\nwire nMREQ_out;\nwire nRD_out;\nwire nWR_out;\nwire nIORQ_out;\nwire latch_wait;\nwire wait_m1;\n\n// Module: control/sequencer.v\nwire M1;\nwire M2;\nwire M3;\nwire M4;\nwire M5;\nwire T1;\nwire T2;\nwire T3;\nwire T4;\nwire T5;\nwire T6;\nwire timings_en;\n\n// Module: alu/alu_control.v\nwire alu_shift_in;\nwire alu_shift_right;\nwire alu_shift_left;\nwire shift_cf_out;\nwire alu_parity_in;\nwire flags_cond_true;\nwire daa_cf_out;\nwire pf_sel;\nwire alu_op_low;\nwire alu_core_cf_in;\nwire [7:0] db;\n\n// Module: alu/alu_select.v\nwire alu_oe;\nwire alu_shift_oe;\nwire alu_op2_oe;\nwire alu_res_oe;\nwire alu_op1_oe;\nwire alu_bs_oe;\nwire alu_op1_sel_bus;\nwire alu_op1_sel_low;\nwire alu_op1_sel_zero;\nwire alu_op2_sel_zero;\nwire alu_op2_sel_bus;\nwire alu_op2_sel_lq;\nwire alu_sel_op2_neg;\nwire alu_sel_op2_high;\nwire alu_core_R;\nwire alu_core_V;\nwire alu_core_S;\n\n// Module: alu/alu_flags.v\nwire flags_sf;\nwire flags_zf;\nwire flags_hf;\nwire flags_pf;\nwire flags_cf;\nwire flags_nf;\nwire flags_cf_latch;\nwire flags_hf2;\n\n// Module: alu/alu.v\nwire alu_zero;\nwire alu_parity_out;\nwire alu_high_eq_9;\nwire alu_high_gt_9;\nwire alu_low_gt_9;\nwire alu_shift_db0;\nwire alu_shift_db7;\nwire alu_core_cf_out;\nwire alu_sf_out;\nwire alu_yf_out;\nwire alu_xf_out;\nwire alu_vf_out;\nwire [3:0] test_db_high;\nwire [3:0] test_db_low;\n\n// Module: registers/reg_control.v\nwire reg_sel_bc;\nwire reg_sel_bc2;\nwire reg_sel_ix;\nwire reg_sel_iy;\nwire reg_sel_de;\nwire reg_sel_hl;\nwire reg_sel_de2;\nwire reg_sel_hl2;\nwire reg_sel_af;\nwire reg_sel_af2;\nwire reg_sel_wz;\nwire reg_sel_pc;\nwire reg_sel_ir;\nwire reg_sel_sp;\nwire reg_sel_gp_hi;\nwire reg_sel_gp_lo;\nwire reg_sel_sys_lo;\nwire reg_sel_sys_hi;\nwire reg_gp_we;\nwire reg_sys_we_lo;\nwire reg_sys_we_hi;\nwire reg_sw_4d_lo;\nwire reg_sw_4d_hi;\n\n// Module: bus/address_latch.v\nwire address_is_1;\nwire [15:0] address;\n\n// Module: bus/address_pins.v\nwire [15:0] abus;\n\n// Module: bus/bus_switch.v\nwire bus_sw_1u;\nwire bus_sw_1d;\nwire bus_sw_2u;\nwire bus_sw_2d;\nwire bus_sw_mask543_en;\n\n// Module: bus/control_pins_n.v\nwire nmi;\nwire busrq;\nwire clk;\nwire intr;\nwire mwait;\nwire reset_in;\nwire pin_nM1;\nwire pin_nMREQ;\nwire pin_nIORQ;\nwire pin_nRD;\nwire pin_nWR;\nwire pin_nRFSH;\nwire pin_nHALT;\nwire pin_nBUSACK;\n"
  },
  {
    "path": "cpu/toplevel/simulation/modelsim/io.hex",
    "content": "00"
  },
  {
    "path": "cpu/toplevel/simulation/modelsim/r",
    "content": "restart -f ; run -all\n"
  },
  {
    "path": "cpu/toplevel/simulation/modelsim/ram.hexdump",
    "content": "C3 8F 00 00 00 79 FE 02 CA 11 00 FE 09 CA 21 00 \nC9 01 00 0A ED 78 CB 47 C2 11 00 01 00 08 ED 59 \nC9 D5 E1 5E 7B FE 24 C8 CD 11 00 23 C3 23 00 00 \n00 00 00 00 00 00 00 00 D5 11 4B 00 F5 C5 E5 0E \n09 CD 05 00 E1 C1 F1 D1 FB ED 4D 5F 49 4E 54 5F \n24 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \n00 00 00 00 00 00 F5 C5 D5 E5 11 78 00 0E 09 CD \n05 00 E1 D1 C1 F1 ED 45 5F 4E 4D 49 5F 24 00 00 \n82 00 D5 11 89 00 C3 3C 00 5F 49 4D 32 5F 24 31 \n00 40 ED 5E 3E 00 ED 47 FB C3 00 01 00 00 00 00 \n00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \n00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \n00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \n00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \n00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \n00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \n21 00 00 22 60 01 11 64 01 0E 09 CD 05 00 2A 60 \n01 23 22 60 01 21 66 01 3A 61 01 CD 3F 01 21 68 \n01 3A 60 01 CD 3F 01 ED 73 62 01 21 6B 01 3A 63 \n01 CD 3F 01 21 6D 01 3A 62 01 CD 3F 01 18 C7 F5 \nE6 0F FE 0A DA 49 01 C6 07 C6 30 23 77 2B F1 1F \n1F 1F 1F E6 0F FE 0A DA 5C 01 C6 07 C6 30 77 C9 \n00 00 00 00 0D 0A 30 30 30 30 20 30 30 30 30 20 \n48 65 6C 6C 6F 2C 20 57 6F 72 6C 64 21 0D 0A 24 \n"
  },
  {
    "path": "cpu/toplevel/simulation/modelsim/test_top.mpf",
    "content": "; Copyright 1991-2009 Mentor Graphics Corporation\n;\n; All Rights Reserved.\n;\n; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF\n; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.\n;\n\n[Library]\nstd = $MODEL_TECH/../std\nieee = $MODEL_TECH/../ieee\nverilog = $MODEL_TECH/../verilog\nvital2000 = $MODEL_TECH/../vital2000\nstd_developerskit = $MODEL_TECH/../std_developerskit\nsynopsys = $MODEL_TECH/../synopsys\nmodelsim_lib = $MODEL_TECH/../modelsim_lib\nsv_std = $MODEL_TECH/../sv_std\n\n; Altera Primitive libraries\n;\n; VHDL Section\n;\naltera_mf = $MODEL_TECH/../altera/vhdl/altera_mf\naltera = $MODEL_TECH/../altera/vhdl/altera\naltera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim\nlpm = $MODEL_TECH/../altera/vhdl/220model\n220model = $MODEL_TECH/../altera/vhdl/220model\nmax = $MODEL_TECH/../altera/vhdl/max\nmaxii = $MODEL_TECH/../altera/vhdl/maxii\nmaxv = $MODEL_TECH/../altera/vhdl/maxv\nstratix = $MODEL_TECH/../altera/vhdl/stratix\nstratixii = $MODEL_TECH/../altera/vhdl/stratixii\nstratixiigx = $MODEL_TECH/../altera/vhdl/stratixiigx\nhardcopyii = $MODEL_TECH/../altera/vhdl/hardcopyii\nhardcopyiii = $MODEL_TECH/../altera/vhdl/hardcopyiii\nhardcopyiv = $MODEL_TECH/../altera/vhdl/hardcopyiv\ncyclone = $MODEL_TECH/../altera/vhdl/cyclone\ncycloneii = $MODEL_TECH/../altera/vhdl/cycloneii\ncycloneiii = $MODEL_TECH/../altera/vhdl/cycloneiii\ncycloneiiils = $MODEL_TECH/../altera/vhdl/cycloneiiils\nsgate = $MODEL_TECH/../altera/vhdl/sgate\nstratixgx = $MODEL_TECH/../altera/vhdl/stratixgx\naltgxb = $MODEL_TECH/../altera/vhdl/altgxb\nstratixgx_gxb = $MODEL_TECH/../altera/vhdl/stratixgx_gxb\nstratixiigx_hssi = $MODEL_TECH/../altera/vhdl/stratixiigx_hssi\narriagx_hssi = $MODEL_TECH/../altera/vhdl/arriagx_hssi\narriaii = $MODEL_TECH/../altera/vhdl/arriaii\narriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi\narriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip\narriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz\narriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi\narriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip\narriagx = $MODEL_TECH/../altera/vhdl/arriagx\naltgxb_lib = $MODEL_TECH/../altera/vhdl/altgxb\nstratixiv = $MODEL_TECH/../altera/vhdl/stratixiv\nstratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi\nstratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip\ncycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv\ncycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi\ncycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip\ncycloneive = $MODEL_TECH/../altera/vhdl/cycloneive\nhardcopyiv_hssi = $MODEL_TECH/../altera/vhdl/hardcopyiv_hssi\nhardcopyiv_pcie_hip = $MODEL_TECH/../altera/vhdl/hardcopyiv_pcie_hip\nstratixv = $MODEL_TECH/../altera/vhdl/stratixv\nstratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi\nstratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip\narriavgz = $MODEL_TECH/../altera/vhdl/arriavgz\narriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi\narriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip\narriav = $MODEL_TECH/../altera/vhdl/arriav\ncyclonev = $MODEL_TECH/../altera/vhdl/cyclonev\n;\n; Verilog Section\n;\naltera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf\naltera_ver = $MODEL_TECH/../altera/verilog/altera\naltera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim\nlpm_ver = $MODEL_TECH/../altera/verilog/220model\n220model_ver = $MODEL_TECH/../altera/verilog/220model\nmax_ver = $MODEL_TECH/../altera/verilog/max\nmaxii_ver = $MODEL_TECH/../altera/verilog/maxii\nmaxv_ver = $MODEL_TECH/../altera/verilog/maxv\nstratix_ver = $MODEL_TECH/../altera/verilog/stratix\nstratixii_ver = $MODEL_TECH/../altera/verilog/stratixii\nstratixiigx_ver = $MODEL_TECH/../altera/verilog/stratixiigx\narriagx_ver = $MODEL_TECH/../altera/verilog/arriagx\nhardcopyii_ver = $MODEL_TECH/../altera/verilog/hardcopyii\nhardcopyiii_ver = $MODEL_TECH/../altera/verilog/hardcopyiii\nhardcopyiv_ver = $MODEL_TECH/../altera/verilog/hardcopyiv\ncyclone_ver = $MODEL_TECH/../altera/verilog/cyclone\ncycloneii_ver = $MODEL_TECH/../altera/verilog/cycloneii\ncycloneiii_ver = $MODEL_TECH/../altera/verilog/cycloneiii\ncycloneiiils_ver = $MODEL_TECH/../altera/verilog/cycloneiiils\nsgate_ver = $MODEL_TECH/../altera/verilog/sgate\nstratixgx_ver = $MODEL_TECH/../altera/verilog/stratixgx\naltgxb_ver = $MODEL_TECH/../altera/verilog/altgxb\nstratixgx_gxb_ver = $MODEL_TECH/../altera/verilog/stratixgx_gxb\nstratixiigx_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiigx_hssi\narriagx_hssi_ver = $MODEL_TECH/../altera/verilog/arriagx_hssi\narriaii_ver = $MODEL_TECH/../altera/verilog/arriaii\narriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi\narriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip\narriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz\narriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi\narriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip\nstratixiii_ver = $MODEL_TECH/../altera/verilog/stratixiii\nstratixiii = $MODEL_TECH/../altera/vhdl/stratixiii\nstratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv\nstratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi\nstratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip\nstratixv_ver = $MODEL_TECH/../altera/verilog/stratixv\nstratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi\nstratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip\narriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz\narriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi\narriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip\narriav_ver = $MODEL_TECH/../altera/verilog/arriav\narriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi\narriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip\ncyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev\ncyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi\ncyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip\ncycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv\ncycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi\ncycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip\ncycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive\nhardcopyiv_hssi_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_hssi\nhardcopyiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_pcie_hip\n\n[vcom]\n; VHDL93 variable selects language version as the default.\n; Default is VHDL-2002.\n; Value of 0 or 1987 for VHDL-1987.\n; Value of 1 or 1993 for VHDL-1993.\n; Default or value of 2 or 2002 for VHDL-2002.\n; Default or value of 3 or 2008 for VHDL-2008.\nVHDL93 = 2002\n\n; Show source line containing error. Default is off.\n; Show_source = 1\n\n; Turn off unbound-component warnings. Default is on.\n; Show_Warning1 = 0\n\n; Turn off process-without-a-wait-statement warnings. Default is on.\n; Show_Warning2 = 0\n\n; Turn off null-range warnings. Default is on.\n; Show_Warning3 = 0\n\n; Turn off no-space-in-time-literal warnings. Default is on.\n; Show_Warning4 = 0\n\n; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.\n; Show_Warning5 = 0\n\n; Turn off optimization for IEEE std_logic_1164 package. Default is on.\n; Optimize_1164 = 0\n\n; Turn on resolving of ambiguous function overloading in favor of the\n; \"explicit\" function declaration (not the one automatically created by\n; the compiler for each type declaration). Default is off.\n; The .ini file has Explicit enabled so that std_logic_signed/unsigned\n; will match the behavior of synthesis tools.\nExplicit = 1\n\n; Turn off acceleration of the VITAL packages. Default is to accelerate.\n; NoVital = 1\n\n; Turn off VITAL compliance checking. Default is checking on.\n; NoVitalCheck = 1\n\n; Ignore VITAL compliance checking errors. Default is to not ignore.\n; IgnoreVitalErrors = 1\n\n; Turn off VITAL compliance checking warnings. Default is to show warnings.\n; Show_VitalChecksWarnings = 0\n\n; Keep silent about case statement static warnings.\n; Default is to give a warning.\n; NoCaseStaticError = 1\n\n; Keep silent about warnings caused by aggregates that are not locally static.\n; Default is to give a warning.\n; NoOthersStaticError = 1\n\n; Turn off inclusion of debugging info within design units.\n; Default is to include debugging info.\n; NoDebug = 1\n\n; Turn off \"Loading...\" messages. Default is messages on.\n; Quiet = 1\n\n; Turn on some limited synthesis rule compliance checking. Checks only:\n;    -- signals used (read) by a process must be in the sensitivity list\n; CheckSynthesis = 1\n\n; Activate optimizations on expressions that do not involve signals,\n; waits, or function/procedure/task invocations. Default is off.\n; ScalarOpts = 1\n\n; Require the user to specify a configuration for all bindings,\n; and do not generate a compile time default binding for the\n; component. This will result in an elaboration error of\n; 'component not bound' if the user fails to do so. Avoids the rare\n; issue of a false dependency upon the unused default binding.\n; RequireConfigForAllDefaultBinding = 1\n\n; Inhibit range checking on subscripts of arrays. Range checking on\n; scalars defined with subtypes is inhibited by default.\n; NoIndexCheck = 1\n\n; Inhibit range checks on all (implicit and explicit) assignments to\n; scalar objects defined with subtypes.\n; NoRangeCheck = 1\n\n[vlog]\n\n; Turn off inclusion of debugging info within design units.\n; Default is to include debugging info.\n; NoDebug = 1\n\n; Turn off \"loading...\" messages. Default is messages on.\n; Quiet = 1\n\n; Turn on Verilog hazard checking (order-dependent accessing of global vars).\n; Default is off.\n; Hazard = 1\n\n; Turn on converting regular Verilog identifiers to uppercase. Allows case\n; insensitivity for module names. Default is no conversion.\n; UpCase = 1\n\n; Turn on incremental compilation of modules. Default is off.\n; Incremental = 1\n\n; Turns on lint-style checking.\n; Show_Lint = 1\n\n[vsim]\n; Simulator resolution\n; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.\nResolution = ps\n\n; User time unit for run commands\n; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the\n; unit specified for Resolution. For example, if Resolution is 100ps,\n; then UserTimeUnit defaults to ps.\n; Should generally be set to default.\nUserTimeUnit = default\n\n; Default run length\nRunLength = 1 us\n\n; Maximum iterations that can be run without advancing simulation time\nIterationLimit = 5000\n\n; Directive to license manager:\n; vhdl          Immediately reserve a VHDL license\n; vlog          Immediately reserve a Verilog license\n; plus          Immediately reserve a VHDL and Verilog license\n; nomgc         Do not look for Mentor Graphics Licenses\n; nomti         Do not look for Model Technology Licenses\n; noqueue       Do not wait in the license queue when a license isn't available\n; viewsim\tTry for viewer license but accept simulator license(s) instead\n;\t\tof queuing for viewer license\n; License = plus\n\n; Stop the simulator after a VHDL/Verilog assertion message\n; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal\nBreakOnAssertion = 3\n\n; Assertion Message Format\n; %S - Severity Level\n; %R - Report Message\n; %T - Time of assertion\n; %D - Delta\n; %I - Instance or Region pathname (if available)\n; %% - print '%' character\n; AssertionFormat = \"** %S: %R\\n   Time: %T  Iteration: %D%I\\n\"\n\n; Assertion File - alternate file for storing VHDL/Verilog assertion messages\n; AssertFile = assert.log\n\n; Default radix for all windows and commands...\n; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned\nDefaultRadix = hexadecimal\n\n; VSIM Startup command\n; Startup = do startup.do\n\n; File for saving command transcript\nTranscriptFile = transcript\n\n; File for saving command history\n; CommandHistory = cmdhist.log\n\n; Specify whether paths in simulator commands should be described\n; in VHDL or Verilog format.\n; For VHDL, PathSeparator = /\n; For Verilog, PathSeparator = .\n; Must not be the same character as DatasetSeparator.\nPathSeparator = /\n\n; Specify the dataset separator for fully rooted contexts.\n; The default is ':'. For example, sim:/top\n; Must not be the same character as PathSeparator.\nDatasetSeparator = :\n\n; Disable VHDL assertion messages\n; IgnoreNote = 1\n; IgnoreWarning = 1\n; IgnoreError = 1\n; IgnoreFailure = 1\n\n; Default force kind. May be freeze, drive, deposit, or default\n; or in other terms, fixed, wired, or charged.\n; A value of \"default\" will use the signal kind to determine the\n; force kind, drive for resolved signals, freeze for unresolved signals\n; DefaultForceKind = freeze\n\n; If zero, open files when elaborated; otherwise, open files on\n; first read or write.  Default is 0.\n; DelayFileOpen = 1\n\n; Control VHDL files opened for write.\n;   0 = Buffered, 1 = Unbuffered\nUnbufferedOutput = 0\n\n; Control the number of VHDL files open concurrently.\n; This number should always be less than the current ulimit\n; setting for max file descriptors.\n;   0 = unlimited\nConcurrentFileLimit = 40\n\n; Control the number of hierarchical regions displayed as\n; part of a signal name shown in the Wave window.\n; A value of zero tells VSIM to display the full name.\n; The default is 0.\n; WaveSignalNameWidth = 0\n\n; Turn off warnings from the std_logic_arith, std_logic_unsigned\n; and std_logic_signed packages.\n; StdArithNoWarnings = 1\n\n; Turn off warnings from the IEEE numeric_std and numeric_bit packages.\n; NumericStdNoWarnings = 1\n\n; Control the format of the (VHDL) FOR generate statement label\n; for each iteration.  Do not quote it.\n; The format string here must contain the conversion codes %s and %d,\n; in that order, and no other conversion codes.  The %s represents\n; the generate_label; the %d represents the generate parameter value\n; at a particular generate iteration (this is the position number if\n; the generate parameter is of an enumeration type).  Embedded whitespace\n; is allowed (but discouraged); leading and trailing whitespace is ignored.\n; Application of the format must result in a unique scope name over all\n; such names in the design so that name lookup can function properly.\n; GenerateFormat = %s__%d\n\n; Specify whether checkpoint files should be compressed.\n; The default is 1 (compressed).\n; CheckpointCompressMode = 0\n\n; List of dynamically loaded objects for Verilog PLI applications\n; Veriuser = veriuser.sl\n\n; Specify default options for the restart command. Options can be one\n; or more of: -force -nobreakpoint -nolist -nolog -nowave\n; DefaultRestartOptions = -force\n\n; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs\n; (> 500 megabyte memory footprint). Default is disabled.\n; Specify number of megabytes to lock.\n; LockedMemory = 1000\n\n; Turn on (1) or off (0) WLF file compression.\n; The default is 1 (compress WLF file).\n; WLFCompress = 0\n\n; Specify whether to save all design hierarchy (1) in the WLF file\n; or only regions containing logged signals (0).\n; The default is 0 (save only regions with logged signals).\n; WLFSaveAllRegions = 1\n\n; WLF file time limit.  Limit WLF file by time, as closely as possible,\n; to the specified amount of simulation time.  When the limit is exceeded\n; the earliest times get truncated from the file.\n; If both time and size limits are specified the most restrictive is used.\n; UserTimeUnits are used if time units are not specified.\n; The default is 0 (no limit).  Example: WLFTimeLimit = {100 ms}\n; WLFTimeLimit = 0\n\n; WLF file size limit.  Limit WLF file size, as closely as possible,\n; to the specified number of megabytes.  If both time and size limits\n; are specified then the most restrictive is used.\n; The default is 0 (no limit).\n; WLFSizeLimit = 1000\n\n; Specify whether or not a WLF file should be deleted when the\n; simulation ends.  A value of 1 will cause the WLF file to be deleted.\n; The default is 0 (do not delete WLF file when simulation ends).\n; WLFDeleteOnQuit = 1\n\n; Automatic SDF compilation\n; Disables automatic compilation of SDF files in flows that support it.\n; Default is on, uncomment to turn off.\n; NoAutoSDFCompile = 1\n\n[lmc]\n\n[msg_system]\n; Change a message severity or suppress a message.\n; The format is: <msg directive> = <msg number>[,<msg number>...]\n; Examples:\n;   note = 3009\n;   warning = 3033\n;   error = 3010,3016\n;   fatal = 3016,3033\n;   suppress = 3009,3016,3043\n; The command verror <msg number> can be used to get the complete\n; description of a message.\n\n; Control transcripting of elaboration/runtime messages.\n; The default is to have messages appear in the transcript and\n; recorded in the wlf file (messages that are recorded in the\n; wlf file can be viewed in the MsgViewer).  The other settings\n; are to send messages only to the transcript or only to the\n; wlf file.  The valid values are\n;    both  {default}\n;    tran  {transcript only}\n;    wlf   {wlf file only}\n; msgmode = both\n[Project]\n; Warning -- Do not edit the project properties directly.\n;            Property names are dynamic in nature and property\n;            values have special syntax.  Changing property data directly\n;            can result in a corrupt MPF file.  All project properties\n;            can be modified through project window dialogs.\nProject_Version = 6\nProject_DefaultLib = work\nProject_SortMethod = unused\nProject_Files_Count = 45\nProject_File_0 = $ROOT/cpu/alu/alu.v\nProject_File_P_0 = compile_order 0 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_1 = $ROOT/cpu/alu/alu_bit_select.v\nProject_File_P_1 = compile_order 1 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_2 = $ROOT/cpu/alu/alu_control.v\nProject_File_P_2 = compile_order 2 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_3 = $ROOT/cpu/alu/alu_core.v\nProject_File_P_3 = compile_order 3 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_4 = $ROOT/cpu/alu/alu_flags.v\nProject_File_P_4 = compile_order 4 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_5 = $ROOT/cpu/alu/alu_mux_2.v\nProject_File_P_5 = compile_order 40 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_6 = $ROOT/cpu/alu/alu_mux_2z.v\nProject_File_P_6 = compile_order 5 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_7 = $ROOT/cpu/alu/alu_mux_3z.v\nProject_File_P_7 = compile_order 6 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_8 = $ROOT/cpu/alu/alu_mux_4.v\nProject_File_P_8 = compile_order 7 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_9 = $ROOT/cpu/alu/alu_mux_8.v\nProject_File_P_9 = compile_order 8 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_10 = $ROOT/cpu/alu/alu_prep_daa.v\nProject_File_P_10 = compile_order 9 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_11 = $ROOT/cpu/alu/alu_select.v\nProject_File_P_11 = compile_order 26 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_12 = $ROOT/cpu/alu/alu_shifter_core.v\nProject_File_P_12 = compile_order 10 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_13 = $ROOT/cpu/alu/alu_slice.v\nProject_File_P_13 = compile_order 11 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_14 = $ROOT/cpu/bus/address_latch.v\nProject_File_P_14 = compile_order 12 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_15 = $ROOT/cpu/bus/address_mux.v\nProject_File_P_15 = compile_order 39 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_16 = $ROOT/cpu/bus/address_pins.v\nProject_File_P_16 = compile_order 13 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_17 = $ROOT/cpu/bus/bus_control.v\nProject_File_P_17 = compile_order 32 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_18 = $ROOT/cpu/bus/bus_switch.v\nProject_File_P_18 = compile_order 30 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_19 = $ROOT/cpu/bus/control_pins_n.v\nProject_File_P_19 = compile_order 42 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_20 = $ROOT/cpu/bus/data_pins.v\nProject_File_P_20 = compile_order 14 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_21 = $ROOT/cpu/bus/data_switch.v\nProject_File_P_21 = compile_order 15 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_22 = $ROOT/cpu/bus/data_switch_mask.v\nProject_File_P_22 = compile_order 34 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_23 = $ROOT/cpu/bus/inc_dec.v\nProject_File_P_23 = compile_order 16 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_24 = $ROOT/cpu/bus/inc_dec_2bit.v\nProject_File_P_24 = compile_order 17 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder bus group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_25 = $ROOT/cpu/control/clk_delay.v\nProject_File_P_25 = compile_order 28 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_26 = $ROOT/cpu/control/decode_state.v\nProject_File_P_26 = compile_order 29 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_27 = $ROOT/cpu/control/execute.v\nProject_File_P_27 = compile_order 18 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options +incdir+../../../control vlog_protect 0 vlog_showsource 1 vlog_upper 0 voptflow 1\nProject_File_28 = $ROOT/cpu/control/interrupts.v\nProject_File_P_28 = compile_order 27 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_29 = $ROOT/cpu/control/ir.v\nProject_File_P_29 = compile_order 19 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_30 = $ROOT/cpu/control/memory_ifc.v\nProject_File_P_30 = compile_order 41 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_31 = $ROOT/cpu/control/pin_control.v\nProject_File_P_31 = compile_order 43 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_32 = $ROOT/cpu/control/pla_decode.v\nProject_File_P_32 = compile_order 20 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_33 = $ROOT/cpu/control/resets.v\nProject_File_P_33 = compile_order 37 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_34 = $ROOT/cpu/control/sequencer.v\nProject_File_P_34 = compile_order 21 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder control group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_35 = $ROOT/cpu/registers/reg_control.v\nProject_File_P_35 = compile_order 22 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder registers group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_36 = $ROOT/cpu/registers/reg_file.v\nProject_File_P_36 = compile_order 23 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder registers group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_37 = $ROOT/cpu/registers/reg_latch.v\nProject_File_P_37 = compile_order 24 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder registers group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_38 = $ROOT/cpu/toplevel/tb_io.sv\nProject_File_P_38 = compile_order 35 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder toplevel group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_39 = $ROOT/cpu/toplevel/tb_iorq.sv\nProject_File_P_39 = compile_order 36 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder toplevel group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_40 = $ROOT/cpu/toplevel/tb_ram.sv\nProject_File_P_40 = compile_order 31 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder toplevel group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_41 = $ROOT/cpu/toplevel/test_fuse.sv\nProject_File_P_41 = compile_order 33 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder toplevel group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options +incdir+../../../toplevel vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_42 = $ROOT/cpu/toplevel/test_top.sv\nProject_File_P_42 = compile_order 25 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder toplevel group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options +incdir+../../../toplevel vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_43 = $ROOT/cpu/toplevel/z80.svh\nProject_File_P_43 = compile_order -1 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 1 file_type systemverilog folder toplevel group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_44 = $ROOT/cpu/toplevel/z80_top_ifc_n.sv\nProject_File_P_44 = compile_order 38 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder toplevel group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options +incdir+../../ vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_Sim_Count = 2\nProject_Sim_0 = test_top\nProject_Sim_P_0 = timing default -t default -sdfnoerror 0 -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder {Top Level} +pulse_e {} additional_dus work.test_top -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {}\nProject_Sim_1 = test_fuse\nProject_Sim_P_1 = timing default -t default -sdfnoerror 0 -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder {Top Level} +pulse_e {} additional_dus work.test_fuse -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {}\nProject_Folder_Count = 5\nProject_Folder_0 = registers\nProject_Folder_P_0 = folder {Top Level}\nProject_Folder_1 = control\nProject_Folder_P_1 = folder {Top Level}\nProject_Folder_2 = alu\nProject_Folder_P_2 = folder {Top Level}\nProject_Folder_3 = bus\nProject_Folder_P_3 = folder {Top Level}\nProject_Folder_4 = toplevel\nProject_Folder_P_4 = folder {Top Level}\nEcho_Compile_Output = 0\nSave_Compile_Report = 1\nProject_Opt_Count = 0\nForceSoftPaths = 1\nProjectStatusDelay = 5000\nVERILOG_DoubleClick = Edit\nVERILOG_CustomDoubleClick =\nSYSTEMVERILOG_DoubleClick = Compile\nSYSTEMVERILOG_CustomDoubleClick =\nVHDL_DoubleClick = Edit\nVHDL_CustomDoubleClick =\nPSL_DoubleClick = Edit\nPSL_CustomDoubleClick =\nTEXT_DoubleClick = Edit\nTEXT_CustomDoubleClick =\nSYSTEMC_DoubleClick = Edit\nSYSTEMC_CustomDoubleClick =\nTCL_DoubleClick = Edit\nTCL_CustomDoubleClick =\nMACRO_DoubleClick = Edit\nMACRO_CustomDoubleClick =\nVCD_DoubleClick = Edit\nVCD_CustomDoubleClick =\nSDF_DoubleClick = Edit\nSDF_CustomDoubleClick =\nXML_DoubleClick = Edit\nXML_CustomDoubleClick =\nLOGFILE_DoubleClick = Edit\nLOGFILE_CustomDoubleClick =\nUCDB_DoubleClick = Edit\nUCDB_CustomDoubleClick =\nUPF_DoubleClick = Edit\nUPF_CustomDoubleClick =\nPCF_DoubleClick = Edit\nPCF_CustomDoubleClick =\nPROJECT_DoubleClick = Edit\nPROJECT_CustomDoubleClick =\nVRM_DoubleClick = Edit\nVRM_CustomDoubleClick =\nDEBUGDATABASE_DoubleClick = Edit\nDEBUGDATABASE_CustomDoubleClick =\nDEBUGARCHIVE_DoubleClick = Edit\nDEBUGARCHIVE_CustomDoubleClick =\nProject_Major_Version = 10\nProject_Minor_Version = 1\n"
  },
  {
    "path": "cpu/toplevel/simulation/modelsim/wave_fuse.do",
    "content": "onerror {resume}\r\nquietly virtual function -install /test_fuse/dut/alu_ -env /test_fuse { &{/test_fuse/dut/alu_/op1_high, /test_fuse/dut/alu_/op1_low }} OP1\r\nquietly virtual function -install /test_fuse/dut/alu_ -env /test_fuse { &{/test_fuse/dut/alu_/op2_high, /test_fuse/dut/alu_/op2_low }} OP2\r\nquietly virtual function -install /test_fuse/dut/alu_ -env /test_fuse { &{/test_fuse/dut/alu_/result_hi, /test_fuse/dut/alu_/result_lo }} RESULT\r\nquietly virtual function -install /test_fuse/dut/reg_file_ -env /test_fuse/dut/reg_file_/b2v_latch_af_lo { &{/test_fuse/dut/reg_file_/b2v_latch_af_hi/latch, /test_fuse/dut/reg_file_/b2v_latch_af_lo/latch }} AF\r\nquietly virtual function -install /test_fuse/dut/reg_file_ -env /test_fuse/dut/reg_file_/b2v_latch_pc_lo { &{/test_fuse/dut/reg_file_/b2v_latch_pc_hi/latch, /test_fuse/dut/reg_file_/b2v_latch_pc_lo/latch }} PC\r\nquietly virtual function -install /test_fuse/dut/reg_file_ -env /test_fuse/dut/reg_file_/b2v_latch_ir_lo { &{/test_fuse/dut/reg_file_/b2v_latch_ir_hi/latch, /test_fuse/dut/reg_file_/b2v_latch_ir_lo/latch }} IR\r\nquietly virtual function -install /test_fuse/dut/reg_file_ -env /test_fuse/dut/reg_file_/b2v_latch_bc_lo { &{/test_fuse/dut/reg_file_/b2v_latch_bc_hi/latch, /test_fuse/dut/reg_file_/b2v_latch_bc_lo/latch }} BC\r\nquietly virtual function -install /test_fuse/dut/reg_file_ -env /test_fuse/dut/reg_file_/b2v_latch_de_lo { &{/test_fuse/dut/reg_file_/b2v_latch_de_hi/latch, /test_fuse/dut/reg_file_/b2v_latch_de_lo/latch }} DE\r\nquietly virtual function -install /test_fuse/dut/reg_file_ -env /test_fuse/dut/reg_file_/b2v_latch_hl_lo { &{/test_fuse/dut/reg_file_/b2v_latch_hl_hi/latch, /test_fuse/dut/reg_file_/b2v_latch_hl_lo/latch }} HL\r\nquietly virtual function -install /test_fuse/dut/reg_file_ -env /test_fuse/dut/reg_file_/b2v_latch_sp_lo { &{/test_fuse/dut/reg_file_/b2v_latch_sp_hi/latch, /test_fuse/dut/reg_file_/b2v_latch_sp_lo/latch }} SP\r\nquietly virtual function -install /test_fuse/dut/reg_file_ -env /test_fuse/dut/reg_file_/b2v_latch_wz_lo { &{/test_fuse/dut/reg_file_/b2v_latch_wz_hi/latch, /test_fuse/dut/reg_file_/b2v_latch_wz_lo/latch }} WZ\r\nquietly WaveActivateNextPane {} 0\r\nadd wave -noupdate -expand -group {pads\r\n} /test_fuse/z80/CLK\r\nadd wave -noupdate -expand -group {pads\r\n} /test_fuse/z80/nM1\r\nadd wave -noupdate -expand -group {pads\r\n} -color Gray90 /test_fuse/z80/nMREQ\r\nadd wave -noupdate -expand -group {pads\r\n} /test_fuse/z80/nIORQ\r\nadd wave -noupdate -expand -group {pads\r\n} /test_fuse/z80/nRD\r\nadd wave -noupdate -expand -group {pads\r\n} /test_fuse/z80/nWR\r\nadd wave -noupdate -expand -group {pads\r\n} /test_fuse/z80/nRFSH\r\nadd wave -noupdate -expand -group {pads\r\n} /test_fuse/z80/nBUSRQ\r\nadd wave -noupdate -expand -group {pads\r\n} /test_fuse/z80/nBUSACK\r\nadd wave -noupdate -expand -group {pads\r\n} /test_fuse/z80/nHALT\r\nadd wave -noupdate -expand -group {pads\r\n} /test_fuse/z80/nWAIT\r\nadd wave -noupdate -expand -group {pads\r\n} /test_fuse/z80/nINT\r\nadd wave -noupdate -expand -group {pads\r\n} /test_fuse/z80/nNMI\r\nadd wave -noupdate -expand -group {pads\r\n} -radix hexadecimal /test_fuse/z80/A\r\nadd wave -noupdate -expand -group {pads\r\n} -radix hexadecimal -childformat {{{/test_fuse/z80/D[7]} -radix hexadecimal} {{/test_fuse/z80/D[6]} -radix hexadecimal} {{/test_fuse/z80/D[5]} -radix hexadecimal} {{/test_fuse/z80/D[4]} -radix hexadecimal} {{/test_fuse/z80/D[3]} -radix hexadecimal} {{/test_fuse/z80/D[2]} -radix hexadecimal} {{/test_fuse/z80/D[1]} -radix hexadecimal} {{/test_fuse/z80/D[0]} -radix hexadecimal}} -subitemconfig {{/test_fuse/z80/D[7]} {-height 15 -radix hexadecimal} {/test_fuse/z80/D[6]} {-height 15 -radix hexadecimal} {/test_fuse/z80/D[5]} {-height 15 -radix hexadecimal} {/test_fuse/z80/D[4]} {-height 15 -radix hexadecimal} {/test_fuse/z80/D[3]} {-height 15 -radix hexadecimal} {/test_fuse/z80/D[2]} {-height 15 -radix hexadecimal} {/test_fuse/z80/D[1]} {-height 15 -radix hexadecimal} {/test_fuse/z80/D[0]} {-height 15 -radix hexadecimal}} /test_fuse/z80/D\r\nadd wave -noupdate -group sequencer /test_fuse/dut/sequencer_/nextM\r\nadd wave -noupdate -group sequencer /test_fuse/dut/sequencer_/setM1\r\nadd wave -noupdate -group sequencer -group internal /test_fuse/dut/sequencer_/hold_clk_iorq\r\nadd wave -noupdate -group sequencer -group internal /test_fuse/dut/sequencer_/hold_clk_wait\r\nadd wave -noupdate -group sequencer -group internal /test_fuse/dut/sequencer_/hold_clk_busrq\r\nadd wave -noupdate -group sequencer -group internal /test_fuse/dut/sequencer_/ena_M\r\nadd wave -noupdate -group sequencer -group internal /test_fuse/dut/sequencer_/ena_T\r\nadd wave -noupdate -group sequencer -expand -group function /test_fuse/dut/pin_control_/fFetch\r\nadd wave -noupdate -group sequencer -expand -group function /test_fuse/dut/pin_control_/fMRead\r\nadd wave -noupdate -group sequencer -expand -group function /test_fuse/dut/pin_control_/fMWrite\r\nadd wave -noupdate -group sequencer -expand -group function /test_fuse/dut/pin_control_/fIORead\r\nadd wave -noupdate -group sequencer -expand -group function /test_fuse/dut/pin_control_/fIOWrite\r\nadd wave -noupdate -group sequencer -expand -group M /test_fuse/dut/sequencer_/M1\r\nadd wave -noupdate -group sequencer -expand -group M /test_fuse/dut/sequencer_/M2\r\nadd wave -noupdate -group sequencer -expand -group M /test_fuse/dut/sequencer_/M3\r\nadd wave -noupdate -group sequencer -expand -group M /test_fuse/dut/sequencer_/M4\r\nadd wave -noupdate -group sequencer -expand -group M /test_fuse/dut/sequencer_/M5\r\nadd wave -noupdate -group sequencer -expand -group T /test_fuse/dut/sequencer_/T1\r\nadd wave -noupdate -group sequencer -expand -group T /test_fuse/dut/sequencer_/T2\r\nadd wave -noupdate -group sequencer -expand -group T /test_fuse/dut/sequencer_/T3\r\nadd wave -noupdate -group sequencer -expand -group T /test_fuse/dut/sequencer_/T4\r\nadd wave -noupdate -group sequencer -expand -group T /test_fuse/dut/sequencer_/T5\r\nadd wave -noupdate -group sequencer -expand -group T /test_fuse/dut/sequencer_/T6\r\nadd wave -noupdate -group opcode /test_fuse/dut/ir_/ctl_ir_we\r\nadd wave -noupdate -group opcode /test_fuse/dut/ir_/opcode\r\nadd wave -noupdate -group db -radix hexadecimal /test_fuse/dut/db0\r\nadd wave -noupdate -group db -radix hexadecimal /test_fuse/dut/db1\r\nadd wave -noupdate -group db -radix hexadecimal /test_fuse/dut/db2\r\nadd wave -noupdate -group {bus control} /test_fuse/dut/bus_control_/ctl_bus_ff_oe\r\nadd wave -noupdate -group {bus control} /test_fuse/dut/bus_control_/ctl_bus_zero_oe\r\nadd wave -noupdate -group {bus control} /test_fuse/dut/pin_control_/bus_ab_pin_we\r\nadd wave -noupdate -group {bus control} /test_fuse/dut/pin_control_/bus_db_pin_oe\r\nadd wave -noupdate -group {bus control} /test_fuse/dut/pin_control_/bus_db_pin_re\r\nadd wave -noupdate -group {bus control} /test_fuse/dut/fpga_reset\r\nadd wave -noupdate -group {bus control} /test_fuse/dut/nreset\r\nadd wave -noupdate -group {bus control} /test_fuse/dut/control_pins_/in_halt\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/ctl_reg_exx\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/ctl_reg_ex_af\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/ctl_reg_ex_de_hl\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/ctl_reg_use_sp\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/nreset\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/ctl_reg_sel_pc\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/ctl_reg_sel_ir\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/ctl_reg_sel_wz\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/ctl_reg_gp_we\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/ctl_reg_not_pc\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/use_ixiy\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/use_ix\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/ctl_reg_sys_we_lo\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/ctl_reg_sys_we_hi\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/ctl_reg_sys_we\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/clk\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/ctl_reg_gp_hilo\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/ctl_reg_gp_sel\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/ctl_reg_sys_hilo\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/reg_sel_bc\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/reg_sel_bc2\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/reg_sel_ix\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/reg_sel_iy\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/reg_sel_de\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/reg_sel_hl\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/reg_sel_de2\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/reg_sel_hl2\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/reg_sel_af\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/reg_sel_af2\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/reg_sel_wz\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/reg_sel_pc\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/reg_sel_ir\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/reg_sel_sp\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/reg_sel_gp_hi\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/reg_sel_gp_lo\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/reg_sel_sys_lo\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/reg_sel_sys_hi\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/reg_gp_we\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/reg_sys_we_lo\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/reg_sys_we_hi\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/bank_af\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/bank_exx\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/bank_hl_de1\r\nadd wave -noupdate -group {reg control} /test_fuse/dut/reg_control_/bank_hl_de2\r\nadd wave -noupdate -group regfile /test_fuse/dut/reg_file_/AF\r\nadd wave -noupdate -group regfile /test_fuse/dut/reg_file_/BC\r\nadd wave -noupdate -group regfile /test_fuse/dut/reg_file_/DE\r\nadd wave -noupdate -group regfile /test_fuse/dut/reg_file_/HL\r\nadd wave -noupdate -group regfile /test_fuse/dut/reg_file_/SP\r\nadd wave -noupdate -group regfile /test_fuse/dut/reg_file_/WZ\r\nadd wave -noupdate -group regfile /test_fuse/dut/reg_file_/PC\r\nadd wave -noupdate -group regfile /test_fuse/dut/reg_file_/IR\r\nadd wave -noupdate -group regfile -radix hexadecimal /test_fuse/dut/reg_file_/db_hi_ds\r\nadd wave -noupdate -group regfile -radix hexadecimal /test_fuse/dut/reg_file_/db_lo_ds\r\nadd wave -noupdate -group regfile -group selects -color Thistle /test_fuse/dut/reg_file_/reg_gp_we\r\nadd wave -noupdate -group regfile -group selects -color Gold /test_fuse/dut/reg_file_/reg_sel_gp_lo\r\nadd wave -noupdate -group regfile -group selects -color Gold /test_fuse/dut/reg_file_/reg_sel_gp_hi\r\nadd wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sel_sp\r\nadd wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sel_iy\r\nadd wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sel_ix\r\nadd wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sel_hl2\r\nadd wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sel_hl\r\nadd wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sel_de2\r\nadd wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sel_de\r\nadd wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sel_bc2\r\nadd wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sel_bc\r\nadd wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sel_af2\r\nadd wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sel_af\r\nadd wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sys_we_lo\r\nadd wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sys_we_hi\r\nadd wave -noupdate -group regfile -group selects -color Gold /test_fuse/dut/reg_file_/reg_sel_sys_lo\r\nadd wave -noupdate -group regfile -group selects -color Gold /test_fuse/dut/reg_file_/reg_sel_sys_hi\r\nadd wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sel_wz\r\nadd wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sel_ir\r\nadd wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sel_pc\r\nadd wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sw_4d_lo\r\nadd wave -noupdate -group regfile -group selects /test_fuse/dut/reg_file_/reg_sw_4d_hi\r\nadd wave -noupdate -group regfile -radix hexadecimal /test_fuse/dut/reg_file_/db_hi_as\r\nadd wave -noupdate -group regfile -radix hexadecimal -childformat {{{/test_fuse/dut/reg_file_/db_lo_as[7]} -radix hexadecimal} {{/test_fuse/dut/reg_file_/db_lo_as[6]} -radix hexadecimal} {{/test_fuse/dut/reg_file_/db_lo_as[5]} -radix hexadecimal} {{/test_fuse/dut/reg_file_/db_lo_as[4]} -radix hexadecimal} {{/test_fuse/dut/reg_file_/db_lo_as[3]} -radix hexadecimal} {{/test_fuse/dut/reg_file_/db_lo_as[2]} -radix hexadecimal} {{/test_fuse/dut/reg_file_/db_lo_as[1]} -radix hexadecimal} {{/test_fuse/dut/reg_file_/db_lo_as[0]} -radix hexadecimal}} -subitemconfig {{/test_fuse/dut/reg_file_/db_lo_as[7]} {-height 15 -radix hexadecimal} {/test_fuse/dut/reg_file_/db_lo_as[6]} {-height 15 -radix hexadecimal} {/test_fuse/dut/reg_file_/db_lo_as[5]} {-height 15 -radix hexadecimal} {/test_fuse/dut/reg_file_/db_lo_as[4]} {-height 15 -radix hexadecimal} {/test_fuse/dut/reg_file_/db_lo_as[3]} {-height 15 -radix hexadecimal} {/test_fuse/dut/reg_file_/db_lo_as[2]} {-height 15 -radix hexadecimal} {/test_fuse/dut/reg_file_/db_lo_as[1]} {-height 15 -radix hexadecimal} {/test_fuse/dut/reg_file_/db_lo_as[0]} {-height 15 -radix hexadecimal}} /test_fuse/dut/reg_file_/db_lo_as\r\nadd wave -noupdate -group switch /test_fuse/dut/bus_switch_/ctl_sw_mask543_en\r\nadd wave -noupdate -group switch /test_fuse/dut/bus_switch_/ctl_sw_1u\r\nadd wave -noupdate -group switch /test_fuse/dut/bus_switch_/ctl_sw_1d\r\nadd wave -noupdate -group switch /test_fuse/dut/bus_switch_/ctl_sw_2u\r\nadd wave -noupdate -group switch /test_fuse/dut/bus_switch_/ctl_sw_2d\r\nadd wave -noupdate -group switch /test_fuse/dut/reg_control_/ctl_sw_4d\r\nadd wave -noupdate -group switch -color Aquamarine /test_fuse/dut/reg_file_/ctl_sw_4u\r\nadd wave -noupdate -group {data pins} /test_fuse/dut/data_pins_/bus_db_pin_oe\r\nadd wave -noupdate -group {data pins} /test_fuse/dut/data_pins_/bus_db_pin_re\r\nadd wave -noupdate -group {data pins} /test_fuse/dut/data_pins_/ctl_bus_db_we\r\nadd wave -noupdate -group {data pins} /test_fuse/dut/data_pins_/ctl_bus_db_oe\r\nadd wave -noupdate -group {data pins} -radix hexadecimal /test_fuse/dut/data_pins_/D\r\nadd wave -noupdate -group {data pins} -radix hexadecimal /test_fuse/dut/data_pins_/db\r\nadd wave -noupdate -group {alu\r\n control} /test_fuse/dut/alu_control_/alu_shift_db0\r\nadd wave -noupdate -group {alu\r\n control} /test_fuse/dut/alu_control_/alu_shift_db7\r\nadd wave -noupdate -group {alu\r\n control} /test_fuse/dut/alu_control_/ctl_shift_en\r\nadd wave -noupdate -group {alu\r\n control} /test_fuse/dut/alu_control_/flags_hf\r\nadd wave -noupdate -group {alu\r\n control} /test_fuse/dut/alu_control_/ctl_alu_op_low\r\nadd wave -noupdate -group {alu\r\n control} /test_fuse/dut/alu_control_/alu_parity_out\r\nadd wave -noupdate -group {alu\r\n control} /test_fuse/dut/alu_control_/flags_zf\r\nadd wave -noupdate -group {alu\r\n control} /test_fuse/dut/alu_control_/flags_pf\r\nadd wave -noupdate -group {alu\r\n control} /test_fuse/dut/alu_control_/flags_sf\r\nadd wave -noupdate -group {alu\r\n control} /test_fuse/dut/alu_control_/ctl_cond_short\r\nadd wave -noupdate -group {alu\r\n control} /test_fuse/dut/alu_control_/alu_vf_out\r\nadd wave -noupdate -group {alu\r\n control} /test_fuse/dut/alu_control_/iff2\r\nadd wave -noupdate -group {alu\r\n control} /test_fuse/dut/alu_control_/ctl_pf_sel\r\nadd wave -noupdate -group {alu\r\n control} /test_fuse/dut/alu_control_/op543\r\nadd wave -noupdate -group {alu\r\n control} /test_fuse/dut/alu_control_/alu_shift_in\r\nadd wave -noupdate -group {alu\r\n control} /test_fuse/dut/alu_control_/alu_shift_right\r\nadd wave -noupdate -group {alu\r\n control} /test_fuse/dut/alu_control_/alu_shift_left\r\nadd wave -noupdate -group {alu\r\n control} /test_fuse/dut/alu_control_/shift_cf_out\r\nadd wave -noupdate -group {alu\r\n control} /test_fuse/dut/alu_control_/alu_parity_in\r\nadd wave -noupdate -group {alu\r\n control} /test_fuse/dut/alu_control_/flags_cond_true\r\nadd wave -noupdate -group {alu\r\n control} /test_fuse/dut/alu_control_/pf_sel\r\nadd wave -noupdate -group {alu\r\n control} /test_fuse/dut/alu_control_/alu_op_low\r\nadd wave -noupdate -group {alu\r\n control} /test_fuse/dut/alu_control_/alu_core_cf_in\r\nadd wave -noupdate -group {alu\r\n control} -radix hexadecimal /test_fuse/dut/alu_control_/db\r\nadd wave -noupdate -group {alu\r\n control} -radix hexadecimal /test_fuse/dut/alu_control_/out\r\nadd wave -noupdate -group {alu\r\n control} -radix hexadecimal /test_fuse/dut/alu_control_/sel\r\nadd wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/ctl_flags_oe\r\nadd wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/ctl_flags_bus\r\nadd wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/ctl_flags_alu\r\nadd wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/alu_sf_out\r\nadd wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/alu_yf_out\r\nadd wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/alu_xf_out\r\nadd wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/ctl_flags_nf_set\r\nadd wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/alu_zero\r\nadd wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/shift_cf_out\r\nadd wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/alu_core_cf_out\r\nadd wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/daa_cf_out\r\nadd wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/ctl_flags_cf_set\r\nadd wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/ctl_flags_cf_cpl\r\nadd wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/ctl_flags_hf_cpl\r\nadd wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/pf_sel\r\nadd wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/ctl_flags_cf_we\r\nadd wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/ctl_flags_sz_we\r\nadd wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/ctl_flags_xy_we\r\nadd wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/ctl_flags_hf_we\r\nadd wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/ctl_flags_pf_we\r\nadd wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/ctl_flags_nf_we\r\nadd wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/flags_sf\r\nadd wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/flags_zf\r\nadd wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/flags_pf\r\nadd wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/flags_cf\r\nadd wave -noupdate -group {alu flags} /test_fuse/dut/alu_flags_/flags_nf\r\nadd wave -noupdate -group {alu select} /test_fuse/dut/alu_select_/ctl_alu_oe\r\nadd wave -noupdate -group {alu select} /test_fuse/dut/alu_select_/ctl_alu_shift_oe\r\nadd wave -noupdate -group {alu select} /test_fuse/dut/alu_select_/ctl_alu_op2_oe\r\nadd wave -noupdate -group {alu select} /test_fuse/dut/alu_select_/ctl_alu_res_oe\r\nadd wave -noupdate -group {alu select} /test_fuse/dut/alu_select_/ctl_alu_op1_oe\r\nadd wave -noupdate -group {alu select} /test_fuse/dut/alu_select_/ctl_alu_bs_oe\r\nadd wave -noupdate -group {alu select} /test_fuse/dut/alu_select_/ctl_alu_op1_sel_bus\r\nadd wave -noupdate -group {alu select} /test_fuse/dut/alu_select_/ctl_alu_op1_sel_low\r\nadd wave -noupdate -group {alu select} /test_fuse/dut/alu_select_/ctl_alu_op1_sel_zero\r\nadd wave -noupdate -group {alu select} /test_fuse/dut/alu_select_/ctl_alu_op2_sel_zero\r\nadd wave -noupdate -group {alu select} /test_fuse/dut/alu_select_/ctl_alu_op2_sel_bus\r\nadd wave -noupdate -group {alu select} /test_fuse/dut/alu_select_/ctl_alu_op2_sel_lq\r\nadd wave -noupdate -group {alu select} /test_fuse/dut/alu_select_/ctl_alu_sel_op2_neg\r\nadd wave -noupdate -group {alu select} /test_fuse/dut/alu_select_/ctl_alu_sel_op2_high\r\nadd wave -noupdate -group {alu select} /test_fuse/dut/alu_select_/ctl_alu_core_R\r\nadd wave -noupdate -group {alu select} /test_fuse/dut/alu_select_/ctl_alu_core_V\r\nadd wave -noupdate -group {alu select} /test_fuse/dut/alu_select_/ctl_alu_core_S\r\nadd wave -noupdate -group {alu\r\n} -color Green -radix hexadecimal /test_fuse/dut/alu_/OP1\r\nadd wave -noupdate -group {alu\r\n} -color Green -radix hexadecimal /test_fuse/dut/alu_/OP2\r\nadd wave -noupdate -group {alu\r\n} /test_fuse/dut/alu_/RESULT\r\nadd wave -noupdate -group {alu\r\n} /test_fuse/dut/alu_/alu_bs_oe\r\nadd wave -noupdate -group {alu\r\n} /test_fuse/dut/alu_/alu_parity_in\r\nadd wave -noupdate -group {alu\r\n} /test_fuse/dut/alu_/alu_oe\r\nadd wave -noupdate -group {alu\r\n} /test_fuse/dut/alu_/alu_shift_oe\r\nadd wave -noupdate -group {alu\r\n} /test_fuse/dut/alu_/alu_op2_oe\r\nadd wave -noupdate -group {alu\r\n} /test_fuse/dut/alu_/alu_op1_oe\r\nadd wave -noupdate -group {alu\r\n} /test_fuse/dut/alu_/alu_res_oe\r\nadd wave -noupdate -group {alu\r\n} /test_fuse/dut/alu_/alu_op1_sel_low\r\nadd wave -noupdate -group {alu\r\n} /test_fuse/dut/alu_/alu_op1_sel_zero\r\nadd wave -noupdate -group {alu\r\n} /test_fuse/dut/alu_/alu_op1_sel_bus\r\nadd wave -noupdate -group {alu\r\n} /test_fuse/dut/alu_/alu_op2_sel_zero\r\nadd wave -noupdate -group {alu\r\n} /test_fuse/dut/alu_/alu_op2_sel_bus\r\nadd wave -noupdate -group {alu\r\n} /test_fuse/dut/alu_/alu_op2_sel_lq\r\nadd wave -noupdate -group {alu\r\n} /test_fuse/dut/alu_/alu_op_low\r\nadd wave -noupdate -group {alu\r\n} /test_fuse/dut/alu_/alu_shift_in\r\nadd wave -noupdate -group {alu\r\n} /test_fuse/dut/alu_/alu_sel_op2_neg\r\nadd wave -noupdate -group {alu\r\n} /test_fuse/dut/alu_/alu_sel_op2_high\r\nadd wave -noupdate -group {alu\r\n} /test_fuse/dut/alu_/alu_shift_left\r\nadd wave -noupdate -group {alu\r\n} /test_fuse/dut/alu_/alu_shift_right\r\nadd wave -noupdate -group {alu\r\n} -radix hexadecimal /test_fuse/dut/alu_/bsel\r\nadd wave -noupdate -group {alu\r\n} /test_fuse/dut/alu_/alu_zero\r\nadd wave -noupdate -group {alu\r\n} /test_fuse/dut/alu_/alu_parity_out\r\nadd wave -noupdate -group {alu\r\n} /test_fuse/dut/alu_/alu_high_eq_9\r\nadd wave -noupdate -group {alu\r\n} /test_fuse/dut/alu_/alu_high_gt_9\r\nadd wave -noupdate -group {alu\r\n} /test_fuse/dut/alu_/alu_low_gt_9\r\nadd wave -noupdate -group {alu\r\n} /test_fuse/dut/alu_/alu_shift_db0\r\nadd wave -noupdate -group {alu\r\n} /test_fuse/dut/alu_/alu_shift_db7\r\nadd wave -noupdate -group {alu\r\n} /test_fuse/dut/alu_/alu_sf_out\r\nadd wave -noupdate -group {alu\r\n} /test_fuse/dut/alu_/alu_yf_out\r\nadd wave -noupdate -group {alu\r\n} /test_fuse/dut/alu_/alu_xf_out\r\nadd wave -noupdate -group {alu\r\n} /test_fuse/dut/alu_/alu_vf_out\r\nadd wave -noupdate -group {alu\r\n} -radix hexadecimal /test_fuse/dut/alu_/db\r\nadd wave -noupdate -group {alu\r\n} -radix hexadecimal /test_fuse/dut/alu_/test_db_high\r\nadd wave -noupdate -group {alu\r\n} -radix hexadecimal /test_fuse/dut/alu_/test_db_low\r\nadd wave -noupdate -group {alu\r\n} -color Magenta /test_fuse/dut/alu_/alu_core_R\r\nadd wave -noupdate -group {alu\r\n} -color Magenta /test_fuse/dut/alu_/alu_core_V\r\nadd wave -noupdate -group {alu\r\n} -color Magenta /test_fuse/dut/alu_/alu_core_S\r\nadd wave -noupdate -group {alu\r\n} -color Magenta /test_fuse/dut/alu_/alu_core_cf_in\r\nadd wave -noupdate -group {alu\r\n} -color Magenta -radix hexadecimal /test_fuse/dut/alu_/alu_op1\r\nadd wave -noupdate -group {alu\r\n} -color Magenta -radix hexadecimal /test_fuse/dut/alu_/alu_op2\r\nadd wave -noupdate -group {alu\r\n} -color Red /test_fuse/dut/alu_/alu_core_cf_out\r\nadd wave -noupdate -group {alu\r\n} -radix hexadecimal /test_fuse/dut/alu_/result_hi\r\nadd wave -noupdate -group {alu\r\n} -radix hexadecimal /test_fuse/dut/alu_/result_lo\r\nadd wave -noupdate -group {alu\r\n} -radix hexadecimal /test_fuse/dut/alu_/db_high\r\nadd wave -noupdate -group {alu\r\n} -radix hexadecimal /test_fuse/dut/alu_/db_low\r\nadd wave -noupdate -group {alu\r\n} -radix hexadecimal /test_fuse/dut/alu_/op1_high\r\nadd wave -noupdate -group {alu\r\n} -radix hexadecimal /test_fuse/dut/alu_/op1_low\r\nadd wave -noupdate -group {alu\r\n} -radix hexadecimal /test_fuse/dut/alu_/op2_high\r\nadd wave -noupdate -group {alu\r\n} -radix hexadecimal /test_fuse/dut/alu_/op2_low\r\nadd wave -noupdate -group {address latch} /test_fuse/dut/address_latch_/ctl_inc_cy\r\nadd wave -noupdate -group {address latch} /test_fuse/dut/address_latch_/ctl_inc_dec\r\nadd wave -noupdate -group {address latch} /test_fuse/dut/address_latch_/clrpc\r\nadd wave -noupdate -group {address latch} /test_fuse/dut/address_latch_/ctl_al_we\r\nadd wave -noupdate -group {address latch} /test_fuse/dut/address_latch_/ctl_inc_limit6\r\nadd wave -noupdate -group {address latch} /test_fuse/dut/address_latch_/ctl_bus_inc_oe\r\nadd wave -noupdate -group {address latch} /test_fuse/dut/address_latch_/address_is_1\r\nadd wave -noupdate -group {address latch} /test_fuse/dut/address_latch_/ctl_apin_mux\r\nadd wave -noupdate -group {address latch} /test_fuse/dut/address_latch_/ctl_apin_mux2\r\nadd wave -noupdate -group {address latch} -radix hexadecimal /test_fuse/dut/address_latch_/abus\r\nadd wave -noupdate -group {address latch} -radix hexadecimal -childformat {{{/test_fuse/dut/address_latch_/address[15]} -radix hexadecimal} {{/test_fuse/dut/address_latch_/address[14]} -radix hexadecimal} {{/test_fuse/dut/address_latch_/address[13]} -radix hexadecimal} {{/test_fuse/dut/address_latch_/address[12]} -radix hexadecimal} {{/test_fuse/dut/address_latch_/address[11]} -radix hexadecimal} {{/test_fuse/dut/address_latch_/address[10]} -radix hexadecimal} {{/test_fuse/dut/address_latch_/address[9]} -radix hexadecimal} {{/test_fuse/dut/address_latch_/address[8]} -radix hexadecimal} {{/test_fuse/dut/address_latch_/address[7]} -radix hexadecimal} {{/test_fuse/dut/address_latch_/address[6]} -radix hexadecimal} {{/test_fuse/dut/address_latch_/address[5]} -radix hexadecimal} {{/test_fuse/dut/address_latch_/address[4]} -radix hexadecimal} {{/test_fuse/dut/address_latch_/address[3]} -radix hexadecimal} {{/test_fuse/dut/address_latch_/address[2]} -radix hexadecimal} {{/test_fuse/dut/address_latch_/address[1]} -radix hexadecimal} {{/test_fuse/dut/address_latch_/address[0]} -radix hexadecimal}} -subitemconfig {{/test_fuse/dut/address_latch_/address[15]} {-height 15 -radix hexadecimal} {/test_fuse/dut/address_latch_/address[14]} {-height 15 -radix hexadecimal} {/test_fuse/dut/address_latch_/address[13]} {-height 15 -radix hexadecimal} {/test_fuse/dut/address_latch_/address[12]} {-height 15 -radix hexadecimal} {/test_fuse/dut/address_latch_/address[11]} {-height 15 -radix hexadecimal} {/test_fuse/dut/address_latch_/address[10]} {-height 15 -radix hexadecimal} {/test_fuse/dut/address_latch_/address[9]} {-height 15 -radix hexadecimal} {/test_fuse/dut/address_latch_/address[8]} {-height 15 -radix hexadecimal} {/test_fuse/dut/address_latch_/address[7]} {-height 15 -radix hexadecimal} {/test_fuse/dut/address_latch_/address[6]} {-height 15 -radix hexadecimal} {/test_fuse/dut/address_latch_/address[5]} {-height 15 -radix hexadecimal} {/test_fuse/dut/address_latch_/address[4]} {-height 15 -radix hexadecimal} {/test_fuse/dut/address_latch_/address[3]} {-height 15 -radix hexadecimal} {/test_fuse/dut/address_latch_/address[2]} {-height 15 -radix hexadecimal} {/test_fuse/dut/address_latch_/address[1]} {-height 15 -radix hexadecimal} {/test_fuse/dut/address_latch_/address[0]} {-height 15 -radix hexadecimal}} /test_fuse/dut/address_latch_/address\r\nadd wave -noupdate -group {address pins} /test_fuse/dut/address_pins_/bus_ab_pin_we\r\nadd wave -noupdate -group {address pins} /test_fuse/dut/address_pins_/pin_control_oe\r\nadd wave -noupdate -group {address pins} -label apin_latch /test_fuse/dut/address_pins_/DFFE_apin_latch\r\nadd wave -noupdate -group state /test_fuse/dut/decode_state_/ctl_state_iy_set\r\nadd wave -noupdate -group state /test_fuse/dut/decode_state_/ctl_state_ixiy_clr\r\nadd wave -noupdate -group state /test_fuse/dut/decode_state_/ctl_state_ixiy_we\r\nadd wave -noupdate -group state /test_fuse/dut/decode_state_/ctl_state_halt_set\r\nadd wave -noupdate -group state /test_fuse/dut/decode_state_/ctl_state_tbl_we\r\nadd wave -noupdate -group state /test_fuse/dut/decode_state_/ctl_state_tbl_ed_set\r\nadd wave -noupdate -group state /test_fuse/dut/decode_state_/ctl_state_tbl_cb_set\r\nadd wave -noupdate -group state /test_fuse/dut/decode_state_/ctl_state_alu\r\nadd wave -noupdate -group state /test_fuse/dut/decode_state_/address_is_1\r\nadd wave -noupdate -group state /test_fuse/dut/decode_state_/ctl_repeat_we\r\nadd wave -noupdate -group state /test_fuse/dut/decode_state_/in_intr\r\nadd wave -noupdate -group state /test_fuse/dut/decode_state_/in_nmi\r\nadd wave -noupdate -group state /test_fuse/dut/decode_state_/nreset\r\nadd wave -noupdate -group state /test_fuse/dut/decode_state_/in_halt\r\nadd wave -noupdate -group state /test_fuse/dut/decode_state_/table_cb\r\nadd wave -noupdate -group state /test_fuse/dut/decode_state_/table_ed\r\nadd wave -noupdate -group state /test_fuse/dut/decode_state_/table_xx\r\nadd wave -noupdate -group state /test_fuse/dut/decode_state_/use_ix\r\nadd wave -noupdate -group state /test_fuse/dut/decode_state_/use_ixiy\r\nadd wave -noupdate -group state /test_fuse/dut/decode_state_/in_alu\r\nadd wave -noupdate -group state /test_fuse/dut/decode_state_/repeat_en\r\nadd wave -noupdate -group interrupts /test_fuse/dut/interrupts_/intr\r\nadd wave -noupdate -group interrupts /test_fuse/dut/interrupts_/iff1\r\nadd wave -noupdate -group interrupts /test_fuse/dut/interrupts_/iff2\r\nadd wave -noupdate -group interrupts /test_fuse/dut/interrupts_/im1\r\nadd wave -noupdate -group interrupts /test_fuse/dut/interrupts_/im2\r\nadd wave -noupdate -group interrupts /test_fuse/dut/interrupts_/nmi\r\nadd wave -noupdate -group interrupts /test_fuse/dut/interrupts_/ctl_iff1_iff2\r\nadd wave -noupdate -group interrupts /test_fuse/dut/interrupts_/ctl_iffx_we\r\nadd wave -noupdate -group interrupts /test_fuse/dut/interrupts_/ctl_iffx_bit\r\nadd wave -noupdate -group interrupts /test_fuse/dut/interrupts_/ctl_im_we\r\nadd wave -noupdate -group interrupts /test_fuse/dut/interrupts_/ctl_no_ints\r\nadd wave -noupdate -group interrupts /test_fuse/dut/interrupts_/in_nmi\r\nadd wave -noupdate -group interrupts /test_fuse/dut/interrupts_/in_intr\r\nadd wave -noupdate -group interrupts /test_fuse/dut/interrupts_/int_armed\r\nadd wave -noupdate -group interrupts /test_fuse/dut/interrupts_/nmi_armed\r\nTreeUpdate [SetDefaultTree]\r\nWaveRestoreCursors {Cursor {3900 ns} 0}\r\nquietly wave cursor active 1\r\nconfigure wave -namecolwidth 163\r\nconfigure wave -valuecolwidth 53\r\nconfigure wave -justifyvalue left\r\nconfigure wave -signalnamewidth 1\r\nconfigure wave -snapdistance 10\r\nconfigure wave -datasetprefix 0\r\nconfigure wave -rowmargin 4\r\nconfigure wave -childrowmargin 2\r\nconfigure wave -gridoffset 0\r\nconfigure wave -gridperiod 1\r\nconfigure wave -griddelta 40\r\nconfigure wave -timeline 1\r\nconfigure wave -timelineunits us\r\nupdate\r\nWaveRestoreZoom {0 ns} {7800 ns}\r\n"
  },
  {
    "path": "cpu/toplevel/simulation/modelsim/wave_top.do",
    "content": "onerror {resume}\nquietly virtual function -install /test_top/dut/alu_ -env /test_top { &{/test_top/dut/alu_/op1_high, /test_top/dut/alu_/op1_low }} OP1\nquietly virtual function -install /test_top/dut/alu_ -env /test_top { &{/test_top/dut/alu_/op2_high, /test_top/dut/alu_/op2_low }} OP2\nquietly virtual function -install /test_top/dut/alu_ -env /test_top { &{/test_top/dut/alu_/result_hi, /test_top/dut/alu_/result_lo }} RESULT\nquietly virtual function -install /test_top/dut/reg_file_ -env /test_top/dut/reg_file_/b2v_latch_af_lo { &{/test_top/dut/reg_file_/b2v_latch_af_hi/latch, /test_top/dut/reg_file_/b2v_latch_af_lo/latch }} AF\nquietly virtual function -install /test_top/dut/reg_file_ -env /test_top/dut/reg_file_/b2v_latch_pc_lo { &{/test_top/dut/reg_file_/b2v_latch_pc_hi/latch, /test_top/dut/reg_file_/b2v_latch_pc_lo/latch }} PC\nquietly virtual function -install /test_top/dut/reg_file_ -env /test_top/dut/reg_file_/b2v_latch_ir_lo { &{/test_top/dut/reg_file_/b2v_latch_ir_hi/latch, /test_top/dut/reg_file_/b2v_latch_ir_lo/latch }} IR\nquietly virtual function -install /test_top/dut/reg_file_ -env /test_top/dut/reg_file_/b2v_latch_bc_lo { &{/test_top/dut/reg_file_/b2v_latch_bc_hi/latch, /test_top/dut/reg_file_/b2v_latch_bc_lo/latch }} BC\nquietly virtual function -install /test_top/dut/reg_file_ -env /test_top/dut/reg_file_/b2v_latch_de_lo { &{/test_top/dut/reg_file_/b2v_latch_de_hi/latch, /test_top/dut/reg_file_/b2v_latch_de_lo/latch }} DE\nquietly virtual function -install /test_top/dut/reg_file_ -env /test_top/dut/reg_file_/b2v_latch_hl_lo { &{/test_top/dut/reg_file_/b2v_latch_hl_hi/latch, /test_top/dut/reg_file_/b2v_latch_hl_lo/latch }} HL\nquietly virtual function -install /test_top/dut/reg_file_ -env /test_top/dut/reg_file_/b2v_latch_sp_lo { &{/test_top/dut/reg_file_/b2v_latch_sp_hi/latch, /test_top/dut/reg_file_/b2v_latch_sp_lo/latch }} SP\nquietly virtual function -install /test_top/dut/reg_file_ -env /test_top/dut/reg_file_/b2v_latch_wz_lo { &{/test_top/dut/reg_file_/b2v_latch_wz_hi/latch, /test_top/dut/reg_file_/b2v_latch_wz_lo/latch }} WZ\nquietly WaveActivateNextPane {} 0\nadd wave -noupdate -expand -group {pads\n} /test_top/z80/CLK\nadd wave -noupdate -expand -group {pads\n} /test_top/z80/nM1\nadd wave -noupdate -expand -group {pads\n} -color Gray90 /test_top/z80/nMREQ\nadd wave -noupdate -expand -group {pads\n} /test_top/z80/nIORQ\nadd wave -noupdate -expand -group {pads\n} /test_top/z80/nRD\nadd wave -noupdate -expand -group {pads\n} /test_top/z80/nWR\nadd wave -noupdate -expand -group {pads\n} /test_top/z80/nRFSH\nadd wave -noupdate -expand -group {pads\n} /test_top/z80/nBUSRQ\nadd wave -noupdate -expand -group {pads\n} /test_top/z80/nBUSACK\nadd wave -noupdate -expand -group {pads\n} /test_top/z80/nHALT\nadd wave -noupdate -expand -group {pads\n} /test_top/z80/nWAIT\nadd wave -noupdate -expand -group {pads\n} /test_top/z80/nINT\nadd wave -noupdate -expand -group {pads\n} /test_top/z80/nNMI\nadd wave -noupdate -expand -group {pads\n} -radix hexadecimal /test_top/z80/A\nadd wave -noupdate -expand -group {pads\n} -radix hexadecimal -childformat {{{/test_top/z80/D[7]} -radix hexadecimal} {{/test_top/z80/D[6]} -radix hexadecimal} {{/test_top/z80/D[5]} -radix hexadecimal} {{/test_top/z80/D[4]} -radix hexadecimal} {{/test_top/z80/D[3]} -radix hexadecimal} {{/test_top/z80/D[2]} -radix hexadecimal} {{/test_top/z80/D[1]} -radix hexadecimal} {{/test_top/z80/D[0]} -radix hexadecimal}} -subitemconfig {{/test_top/z80/D[7]} {-height 15 -radix hexadecimal} {/test_top/z80/D[6]} {-height 15 -radix hexadecimal} {/test_top/z80/D[5]} {-height 15 -radix hexadecimal} {/test_top/z80/D[4]} {-height 15 -radix hexadecimal} {/test_top/z80/D[3]} {-height 15 -radix hexadecimal} {/test_top/z80/D[2]} {-height 15 -radix hexadecimal} {/test_top/z80/D[1]} {-height 15 -radix hexadecimal} {/test_top/z80/D[0]} {-height 15 -radix hexadecimal}} /test_top/z80/D\nadd wave -noupdate -group sequencer /test_top/dut/sequencer_/nextM\nadd wave -noupdate -group sequencer /test_top/dut/sequencer_/setM1\nadd wave -noupdate -group sequencer -group internal /test_top/dut/sequencer_/hold_clk_iorq\nadd wave -noupdate -group sequencer -group internal /test_top/dut/sequencer_/hold_clk_wait\nadd wave -noupdate -group sequencer -group internal /test_top/dut/sequencer_/hold_clk_busrq\nadd wave -noupdate -group sequencer -group internal /test_top/dut/sequencer_/ena_M\nadd wave -noupdate -group sequencer -group internal /test_top/dut/sequencer_/ena_T\nadd wave -noupdate -group sequencer -expand -group function /test_top/dut/pin_control_/fFetch\nadd wave -noupdate -group sequencer -expand -group function /test_top/dut/pin_control_/fMRead\nadd wave -noupdate -group sequencer -expand -group function /test_top/dut/pin_control_/fMWrite\nadd wave -noupdate -group sequencer -expand -group function /test_top/dut/pin_control_/fIORead\nadd wave -noupdate -group sequencer -expand -group function /test_top/dut/pin_control_/fIOWrite\nadd wave -noupdate -group sequencer -expand -group M /test_top/dut/sequencer_/M1\nadd wave -noupdate -group sequencer -expand -group M /test_top/dut/sequencer_/M2\nadd wave -noupdate -group sequencer -expand -group M /test_top/dut/sequencer_/M3\nadd wave -noupdate -group sequencer -expand -group M /test_top/dut/sequencer_/M4\nadd wave -noupdate -group sequencer -expand -group M /test_top/dut/sequencer_/M5\nadd wave -noupdate -group sequencer -expand -group T /test_top/dut/sequencer_/T1\nadd wave -noupdate -group sequencer -expand -group T /test_top/dut/sequencer_/T2\nadd wave -noupdate -group sequencer -expand -group T /test_top/dut/sequencer_/T3\nadd wave -noupdate -group sequencer -expand -group T /test_top/dut/sequencer_/T4\nadd wave -noupdate -group sequencer -expand -group T /test_top/dut/sequencer_/T5\nadd wave -noupdate -group sequencer -expand -group T /test_top/dut/sequencer_/T6\nadd wave -noupdate -group opcode /test_top/dut/ir_/ctl_ir_we\nadd wave -noupdate -group opcode /test_top/dut/ir_/opcode\nadd wave -noupdate -group db -radix hexadecimal /test_top/dut/db0\nadd wave -noupdate -group db -radix hexadecimal /test_top/dut/db1\nadd wave -noupdate -group db -radix hexadecimal /test_top/dut/db2\nadd wave -noupdate -group {bus control} /test_top/dut/bus_control_/ctl_bus_ff_oe\nadd wave -noupdate -group {bus control} /test_top/dut/bus_control_/ctl_bus_zero_oe\nadd wave -noupdate -group {bus control} /test_top/dut/pin_control_/bus_ab_pin_we\nadd wave -noupdate -group {bus control} /test_top/dut/pin_control_/bus_db_pin_oe\nadd wave -noupdate -group {bus control} /test_top/dut/pin_control_/bus_db_pin_re\nadd wave -noupdate -group {bus control} /test_top/dut/fpga_reset\nadd wave -noupdate -group {bus control} /test_top/dut/nreset\nadd wave -noupdate -group {bus control} /test_top/dut/control_pins_/in_halt\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/ctl_reg_exx\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/ctl_reg_ex_af\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/ctl_reg_ex_de_hl\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/ctl_reg_use_sp\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/nreset\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/ctl_reg_sel_pc\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/ctl_reg_sel_ir\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/ctl_reg_sel_wz\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/ctl_reg_gp_we\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/ctl_reg_not_pc\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/use_ixiy\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/use_ix\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/ctl_reg_sys_we_lo\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/ctl_reg_sys_we_hi\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/ctl_reg_sys_we\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/clk\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/ctl_reg_gp_hilo\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/ctl_reg_gp_sel\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/ctl_reg_sys_hilo\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/reg_sel_bc\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/reg_sel_bc2\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/reg_sel_ix\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/reg_sel_iy\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/reg_sel_de\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/reg_sel_hl\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/reg_sel_de2\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/reg_sel_hl2\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/reg_sel_af\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/reg_sel_af2\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/reg_sel_wz\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/reg_sel_pc\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/reg_sel_ir\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/reg_sel_sp\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/reg_sel_gp_hi\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/reg_sel_gp_lo\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/reg_sel_sys_lo\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/reg_sel_sys_hi\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/reg_gp_we\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/reg_sys_we_lo\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/reg_sys_we_hi\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/bank_af\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/bank_exx\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/bank_hl_de1\nadd wave -noupdate -group {reg control} /test_top/dut/reg_control_/bank_hl_de2\nadd wave -noupdate -group regfile /test_top/dut/reg_file_/AF\nadd wave -noupdate -group regfile /test_top/dut/reg_file_/BC\nadd wave -noupdate -group regfile /test_top/dut/reg_file_/DE\nadd wave -noupdate -group regfile /test_top/dut/reg_file_/HL\nadd wave -noupdate -group regfile /test_top/dut/reg_file_/SP\nadd wave -noupdate -group regfile /test_top/dut/reg_file_/WZ\nadd wave -noupdate -group regfile /test_top/dut/reg_file_/PC\nadd wave -noupdate -group regfile /test_top/dut/reg_file_/IR\nadd wave -noupdate -group regfile -radix hexadecimal /test_top/dut/reg_file_/db_hi_ds\nadd wave -noupdate -group regfile -radix hexadecimal /test_top/dut/reg_file_/db_lo_ds\nadd wave -noupdate -group regfile -group selects -color Thistle /test_top/dut/reg_file_/reg_gp_we\nadd wave -noupdate -group regfile -group selects -color Gold /test_top/dut/reg_file_/reg_sel_gp_lo\nadd wave -noupdate -group regfile -group selects -color Gold /test_top/dut/reg_file_/reg_sel_gp_hi\nadd wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sel_sp\nadd wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sel_iy\nadd wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sel_ix\nadd wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sel_hl2\nadd wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sel_hl\nadd wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sel_de2\nadd wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sel_de\nadd wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sel_bc2\nadd wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sel_bc\nadd wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sel_af2\nadd wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sel_af\nadd wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sys_we_lo\nadd wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sys_we_hi\nadd wave -noupdate -group regfile -group selects -color Gold /test_top/dut/reg_file_/reg_sel_sys_lo\nadd wave -noupdate -group regfile -group selects -color Gold /test_top/dut/reg_file_/reg_sel_sys_hi\nadd wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sel_wz\nadd wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sel_ir\nadd wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sel_pc\nadd wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sw_4d_lo\nadd wave -noupdate -group regfile -group selects /test_top/dut/reg_file_/reg_sw_4d_hi\nadd wave -noupdate -group regfile -radix hexadecimal /test_top/dut/reg_file_/db_hi_as\nadd wave -noupdate -group regfile -radix hexadecimal -childformat {{{/test_top/dut/reg_file_/db_lo_as[7]} -radix hexadecimal} {{/test_top/dut/reg_file_/db_lo_as[6]} -radix hexadecimal} {{/test_top/dut/reg_file_/db_lo_as[5]} -radix hexadecimal} {{/test_top/dut/reg_file_/db_lo_as[4]} -radix hexadecimal} {{/test_top/dut/reg_file_/db_lo_as[3]} -radix hexadecimal} {{/test_top/dut/reg_file_/db_lo_as[2]} -radix hexadecimal} {{/test_top/dut/reg_file_/db_lo_as[1]} -radix hexadecimal} {{/test_top/dut/reg_file_/db_lo_as[0]} -radix hexadecimal}} -subitemconfig {{/test_top/dut/reg_file_/db_lo_as[7]} {-height 15 -radix hexadecimal} {/test_top/dut/reg_file_/db_lo_as[6]} {-height 15 -radix hexadecimal} {/test_top/dut/reg_file_/db_lo_as[5]} {-height 15 -radix hexadecimal} {/test_top/dut/reg_file_/db_lo_as[4]} {-height 15 -radix hexadecimal} {/test_top/dut/reg_file_/db_lo_as[3]} {-height 15 -radix hexadecimal} {/test_top/dut/reg_file_/db_lo_as[2]} {-height 15 -radix hexadecimal} {/test_top/dut/reg_file_/db_lo_as[1]} {-height 15 -radix hexadecimal} {/test_top/dut/reg_file_/db_lo_as[0]} {-height 15 -radix hexadecimal}} /test_top/dut/reg_file_/db_lo_as\nadd wave -noupdate -group switch /test_top/dut/bus_switch_/ctl_sw_mask543_en\nadd wave -noupdate -group switch /test_top/dut/bus_switch_/ctl_sw_1u\nadd wave -noupdate -group switch /test_top/dut/bus_switch_/ctl_sw_1d\nadd wave -noupdate -group switch /test_top/dut/bus_switch_/ctl_sw_2u\nadd wave -noupdate -group switch /test_top/dut/bus_switch_/ctl_sw_2d\nadd wave -noupdate -group switch /test_top/dut/reg_control_/ctl_sw_4d\nadd wave -noupdate -group switch -color Aquamarine /test_top/dut/reg_file_/ctl_sw_4u\nadd wave -noupdate -group {data pins} /test_top/dut/data_pins_/bus_db_pin_oe\nadd wave -noupdate -group {data pins} /test_top/dut/data_pins_/bus_db_pin_re\nadd wave -noupdate -group {data pins} /test_top/dut/data_pins_/ctl_bus_db_we\nadd wave -noupdate -group {data pins} /test_top/dut/data_pins_/ctl_bus_db_oe\nadd wave -noupdate -group {data pins} -radix hexadecimal /test_top/dut/data_pins_/D\nadd wave -noupdate -group {data pins} -radix hexadecimal /test_top/dut/data_pins_/db\nadd wave -noupdate -group {alu\n control} /test_top/dut/alu_control_/alu_shift_db0\nadd wave -noupdate -group {alu\n control} /test_top/dut/alu_control_/alu_shift_db7\nadd wave -noupdate -group {alu\n control} /test_top/dut/alu_control_/ctl_shift_en\nadd wave -noupdate -group {alu\n control} /test_top/dut/alu_control_/flags_hf\nadd wave -noupdate -group {alu\n control} /test_top/dut/alu_control_/ctl_alu_op_low\nadd wave -noupdate -group {alu\n control} /test_top/dut/alu_control_/alu_parity_out\nadd wave -noupdate -group {alu\n control} /test_top/dut/alu_control_/flags_zf\nadd wave -noupdate -group {alu\n control} /test_top/dut/alu_control_/flags_pf\nadd wave -noupdate -group {alu\n control} /test_top/dut/alu_control_/flags_sf\nadd wave -noupdate -group {alu\n control} /test_top/dut/alu_control_/ctl_cond_short\nadd wave -noupdate -group {alu\n control} /test_top/dut/alu_control_/alu_vf_out\nadd wave -noupdate -group {alu\n control} /test_top/dut/alu_control_/iff2\nadd wave -noupdate -group {alu\n control} /test_top/dut/alu_control_/ctl_pf_sel\nadd wave -noupdate -group {alu\n control} /test_top/dut/alu_control_/op543\nadd wave -noupdate -group {alu\n control} /test_top/dut/alu_control_/alu_shift_in\nadd wave -noupdate -group {alu\n control} /test_top/dut/alu_control_/alu_shift_right\nadd wave -noupdate -group {alu\n control} /test_top/dut/alu_control_/alu_shift_left\nadd wave -noupdate -group {alu\n control} /test_top/dut/alu_control_/shift_cf_out\nadd wave -noupdate -group {alu\n control} /test_top/dut/alu_control_/alu_parity_in\nadd wave -noupdate -group {alu\n control} /test_top/dut/alu_control_/flags_cond_true\nadd wave -noupdate -group {alu\n control} /test_top/dut/alu_control_/pf_sel\nadd wave -noupdate -group {alu\n control} /test_top/dut/alu_control_/alu_op_low\nadd wave -noupdate -group {alu\n control} /test_top/dut/alu_control_/alu_core_cf_in\nadd wave -noupdate -group {alu\n control} -radix hexadecimal /test_top/dut/alu_control_/db\nadd wave -noupdate -group {alu\n control} -radix hexadecimal /test_top/dut/alu_control_/out\nadd wave -noupdate -group {alu\n control} -radix hexadecimal /test_top/dut/alu_control_/sel\nadd wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/ctl_flags_oe\nadd wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/ctl_flags_bus\nadd wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/ctl_flags_alu\nadd wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/alu_sf_out\nadd wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/alu_yf_out\nadd wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/alu_xf_out\nadd wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/ctl_flags_nf_set\nadd wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/alu_zero\nadd wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/shift_cf_out\nadd wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/alu_core_cf_out\nadd wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/daa_cf_out\nadd wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/ctl_flags_cf_set\nadd wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/ctl_flags_cf_cpl\nadd wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/ctl_flags_hf_cpl\nadd wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/pf_sel\nadd wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/ctl_flags_cf_we\nadd wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/ctl_flags_sz_we\nadd wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/ctl_flags_xy_we\nadd wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/ctl_flags_hf_we\nadd wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/ctl_flags_pf_we\nadd wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/ctl_flags_nf_we\nadd wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/flags_sf\nadd wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/flags_zf\nadd wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/flags_pf\nadd wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/flags_cf\nadd wave -noupdate -group {alu flags} /test_top/dut/alu_flags_/flags_nf\nadd wave -noupdate -group {alu select} /test_top/dut/alu_select_/ctl_alu_oe\nadd wave -noupdate -group {alu select} /test_top/dut/alu_select_/ctl_alu_shift_oe\nadd wave -noupdate -group {alu select} /test_top/dut/alu_select_/ctl_alu_op2_oe\nadd wave -noupdate -group {alu select} /test_top/dut/alu_select_/ctl_alu_res_oe\nadd wave -noupdate -group {alu select} /test_top/dut/alu_select_/ctl_alu_op1_oe\nadd wave -noupdate -group {alu select} /test_top/dut/alu_select_/ctl_alu_bs_oe\nadd wave -noupdate -group {alu select} /test_top/dut/alu_select_/ctl_alu_op1_sel_bus\nadd wave -noupdate -group {alu select} /test_top/dut/alu_select_/ctl_alu_op1_sel_low\nadd wave -noupdate -group {alu select} /test_top/dut/alu_select_/ctl_alu_op1_sel_zero\nadd wave -noupdate -group {alu select} /test_top/dut/alu_select_/ctl_alu_op2_sel_zero\nadd wave -noupdate -group {alu select} /test_top/dut/alu_select_/ctl_alu_op2_sel_bus\nadd wave -noupdate -group {alu select} /test_top/dut/alu_select_/ctl_alu_op2_sel_lq\nadd wave -noupdate -group {alu select} /test_top/dut/alu_select_/ctl_alu_sel_op2_neg\nadd wave -noupdate -group {alu select} /test_top/dut/alu_select_/ctl_alu_sel_op2_high\nadd wave -noupdate -group {alu select} /test_top/dut/alu_select_/ctl_alu_core_R\nadd wave -noupdate -group {alu select} /test_top/dut/alu_select_/ctl_alu_core_V\nadd wave -noupdate -group {alu select} /test_top/dut/alu_select_/ctl_alu_core_S\nadd wave -noupdate -group {alu\n} -color Green -radix hexadecimal /test_top/dut/alu_/OP1\nadd wave -noupdate -group {alu\n} -color Green -radix hexadecimal /test_top/dut/alu_/OP2\nadd wave -noupdate -group {alu\n} /test_top/dut/alu_/RESULT\nadd wave -noupdate -group {alu\n} /test_top/dut/alu_/alu_bs_oe\nadd wave -noupdate -group {alu\n} /test_top/dut/alu_/alu_parity_in\nadd wave -noupdate -group {alu\n} /test_top/dut/alu_/alu_oe\nadd wave -noupdate -group {alu\n} /test_top/dut/alu_/alu_shift_oe\nadd wave -noupdate -group {alu\n} /test_top/dut/alu_/alu_op2_oe\nadd wave -noupdate -group {alu\n} /test_top/dut/alu_/alu_op1_oe\nadd wave -noupdate -group {alu\n} /test_top/dut/alu_/alu_res_oe\nadd wave -noupdate -group {alu\n} /test_top/dut/alu_/alu_op1_sel_low\nadd wave -noupdate -group {alu\n} /test_top/dut/alu_/alu_op1_sel_zero\nadd wave -noupdate -group {alu\n} /test_top/dut/alu_/alu_op1_sel_bus\nadd wave -noupdate -group {alu\n} /test_top/dut/alu_/alu_op2_sel_zero\nadd wave -noupdate -group {alu\n} /test_top/dut/alu_/alu_op2_sel_bus\nadd wave -noupdate -group {alu\n} /test_top/dut/alu_/alu_op2_sel_lq\nadd wave -noupdate -group {alu\n} /test_top/dut/alu_/alu_op_low\nadd wave -noupdate -group {alu\n} /test_top/dut/alu_/alu_shift_in\nadd wave -noupdate -group {alu\n} /test_top/dut/alu_/alu_sel_op2_neg\nadd wave -noupdate -group {alu\n} /test_top/dut/alu_/alu_sel_op2_high\nadd wave -noupdate -group {alu\n} /test_top/dut/alu_/alu_shift_left\nadd wave -noupdate -group {alu\n} /test_top/dut/alu_/alu_shift_right\nadd wave -noupdate -group {alu\n} -radix hexadecimal /test_top/dut/alu_/bsel\nadd wave -noupdate -group {alu\n} /test_top/dut/alu_/alu_zero\nadd wave -noupdate -group {alu\n} /test_top/dut/alu_/alu_parity_out\nadd wave -noupdate -group {alu\n} /test_top/dut/alu_/alu_high_eq_9\nadd wave -noupdate -group {alu\n} /test_top/dut/alu_/alu_high_gt_9\nadd wave -noupdate -group {alu\n} /test_top/dut/alu_/alu_low_gt_9\nadd wave -noupdate -group {alu\n} /test_top/dut/alu_/alu_shift_db0\nadd wave -noupdate -group {alu\n} /test_top/dut/alu_/alu_shift_db7\nadd wave -noupdate -group {alu\n} /test_top/dut/alu_/alu_sf_out\nadd wave -noupdate -group {alu\n} /test_top/dut/alu_/alu_yf_out\nadd wave -noupdate -group {alu\n} /test_top/dut/alu_/alu_xf_out\nadd wave -noupdate -group {alu\n} /test_top/dut/alu_/alu_vf_out\nadd wave -noupdate -group {alu\n} -radix hexadecimal /test_top/dut/alu_/db\nadd wave -noupdate -group {alu\n} -radix hexadecimal /test_top/dut/alu_/test_db_high\nadd wave -noupdate -group {alu\n} -radix hexadecimal /test_top/dut/alu_/test_db_low\nadd wave -noupdate -group {alu\n} -color Magenta /test_top/dut/alu_/alu_core_R\nadd wave -noupdate -group {alu\n} -color Magenta /test_top/dut/alu_/alu_core_V\nadd wave -noupdate -group {alu\n} -color Magenta /test_top/dut/alu_/alu_core_S\nadd wave -noupdate -group {alu\n} -color Magenta /test_top/dut/alu_/alu_core_cf_in\nadd wave -noupdate -group {alu\n} -color Magenta -radix hexadecimal /test_top/dut/alu_/alu_op1\nadd wave -noupdate -group {alu\n} -color Magenta -radix hexadecimal /test_top/dut/alu_/alu_op2\nadd wave -noupdate -group {alu\n} -color Red /test_top/dut/alu_/alu_core_cf_out\nadd wave -noupdate -group {alu\n} -radix hexadecimal /test_top/dut/alu_/result_hi\nadd wave -noupdate -group {alu\n} -radix hexadecimal /test_top/dut/alu_/result_lo\nadd wave -noupdate -group {alu\n} -radix hexadecimal /test_top/dut/alu_/db_high\nadd wave -noupdate -group {alu\n} -radix hexadecimal /test_top/dut/alu_/db_low\nadd wave -noupdate -group {alu\n} -radix hexadecimal /test_top/dut/alu_/op1_high\nadd wave -noupdate -group {alu\n} -radix hexadecimal /test_top/dut/alu_/op1_low\nadd wave -noupdate -group {alu\n} -radix hexadecimal /test_top/dut/alu_/op2_high\nadd wave -noupdate -group {alu\n} -radix hexadecimal /test_top/dut/alu_/op2_low\nadd wave -noupdate -group {address latch} /test_top/dut/address_latch_/ctl_inc_cy\nadd wave -noupdate -group {address latch} /test_top/dut/address_latch_/ctl_inc_dec\nadd wave -noupdate -group {address latch} /test_top/dut/address_latch_/clrpc\nadd wave -noupdate -group {address latch} /test_top/dut/address_latch_/ctl_al_we\nadd wave -noupdate -group {address latch} /test_top/dut/address_latch_/ctl_inc_limit6\nadd wave -noupdate -group {address latch} /test_top/dut/address_latch_/ctl_bus_inc_oe\nadd wave -noupdate -group {address latch} /test_top/dut/address_latch_/address_is_1\nadd wave -noupdate -group {address latch} /test_top/dut/address_latch_/ctl_apin_mux\nadd wave -noupdate -group {address latch} /test_top/dut/address_latch_/ctl_apin_mux2\nadd wave -noupdate -group {address latch} -radix hexadecimal /test_top/dut/address_latch_/abus\nadd wave -noupdate -group {address latch} -radix hexadecimal -childformat {{{/test_top/dut/address_latch_/address[15]} -radix hexadecimal} {{/test_top/dut/address_latch_/address[14]} -radix hexadecimal} {{/test_top/dut/address_latch_/address[13]} -radix hexadecimal} {{/test_top/dut/address_latch_/address[12]} -radix hexadecimal} {{/test_top/dut/address_latch_/address[11]} -radix hexadecimal} {{/test_top/dut/address_latch_/address[10]} -radix hexadecimal} {{/test_top/dut/address_latch_/address[9]} -radix hexadecimal} {{/test_top/dut/address_latch_/address[8]} -radix hexadecimal} {{/test_top/dut/address_latch_/address[7]} -radix hexadecimal} {{/test_top/dut/address_latch_/address[6]} -radix hexadecimal} {{/test_top/dut/address_latch_/address[5]} -radix hexadecimal} {{/test_top/dut/address_latch_/address[4]} -radix hexadecimal} {{/test_top/dut/address_latch_/address[3]} -radix hexadecimal} {{/test_top/dut/address_latch_/address[2]} -radix hexadecimal} {{/test_top/dut/address_latch_/address[1]} -radix hexadecimal} {{/test_top/dut/address_latch_/address[0]} -radix hexadecimal}} -subitemconfig {{/test_top/dut/address_latch_/address[15]} {-height 15 -radix hexadecimal} {/test_top/dut/address_latch_/address[14]} {-height 15 -radix hexadecimal} {/test_top/dut/address_latch_/address[13]} {-height 15 -radix hexadecimal} {/test_top/dut/address_latch_/address[12]} {-height 15 -radix hexadecimal} {/test_top/dut/address_latch_/address[11]} {-height 15 -radix hexadecimal} {/test_top/dut/address_latch_/address[10]} {-height 15 -radix hexadecimal} {/test_top/dut/address_latch_/address[9]} {-height 15 -radix hexadecimal} {/test_top/dut/address_latch_/address[8]} {-height 15 -radix hexadecimal} {/test_top/dut/address_latch_/address[7]} {-height 15 -radix hexadecimal} {/test_top/dut/address_latch_/address[6]} {-height 15 -radix hexadecimal} {/test_top/dut/address_latch_/address[5]} {-height 15 -radix hexadecimal} {/test_top/dut/address_latch_/address[4]} {-height 15 -radix hexadecimal} {/test_top/dut/address_latch_/address[3]} {-height 15 -radix hexadecimal} {/test_top/dut/address_latch_/address[2]} {-height 15 -radix hexadecimal} {/test_top/dut/address_latch_/address[1]} {-height 15 -radix hexadecimal} {/test_top/dut/address_latch_/address[0]} {-height 15 -radix hexadecimal}} /test_top/dut/address_latch_/address\nadd wave -noupdate -group {address pins} /test_top/dut/address_pins_/bus_ab_pin_we\nadd wave -noupdate -group {address pins} /test_top/dut/address_pins_/pin_control_oe\nadd wave -noupdate -group {address pins} -label apin_latch /test_top/dut/address_pins_/DFFE_apin_latch\nadd wave -noupdate -group state /test_top/dut/decode_state_/ctl_state_iy_set\nadd wave -noupdate -group state /test_top/dut/decode_state_/ctl_state_ixiy_clr\nadd wave -noupdate -group state /test_top/dut/decode_state_/ctl_state_ixiy_we\nadd wave -noupdate -group state /test_top/dut/decode_state_/ctl_state_halt_set\nadd wave -noupdate -group state /test_top/dut/decode_state_/ctl_state_tbl_we\nadd wave -noupdate -group state /test_top/dut/decode_state_/ctl_state_tbl_ed_set\nadd wave -noupdate -group state /test_top/dut/decode_state_/ctl_state_tbl_cb_set\nadd wave -noupdate -group state /test_top/dut/decode_state_/ctl_state_alu\nadd wave -noupdate -group state /test_top/dut/decode_state_/address_is_1\nadd wave -noupdate -group state /test_top/dut/decode_state_/ctl_repeat_we\nadd wave -noupdate -group state /test_top/dut/decode_state_/in_intr\nadd wave -noupdate -group state /test_top/dut/decode_state_/in_nmi\nadd wave -noupdate -group state /test_top/dut/decode_state_/nreset\nadd wave -noupdate -group state /test_top/dut/decode_state_/in_halt\nadd wave -noupdate -group state /test_top/dut/decode_state_/table_cb\nadd wave -noupdate -group state /test_top/dut/decode_state_/table_ed\nadd wave -noupdate -group state /test_top/dut/decode_state_/table_xx\nadd wave -noupdate -group state /test_top/dut/decode_state_/use_ix\nadd wave -noupdate -group state /test_top/dut/decode_state_/use_ixiy\nadd wave -noupdate -group state /test_top/dut/decode_state_/in_alu\nadd wave -noupdate -group state /test_top/dut/decode_state_/repeat_en\nadd wave -noupdate -group interrupts /test_top/dut/interrupts_/intr\nadd wave -noupdate -group interrupts /test_top/dut/interrupts_/iff1\nadd wave -noupdate -group interrupts /test_top/dut/interrupts_/iff2\nadd wave -noupdate -group interrupts /test_top/dut/interrupts_/im1\nadd wave -noupdate -group interrupts /test_top/dut/interrupts_/im2\nadd wave -noupdate -group interrupts /test_top/dut/interrupts_/nmi\nadd wave -noupdate -group interrupts /test_top/dut/interrupts_/ctl_iff1_iff2\nadd wave -noupdate -group interrupts /test_top/dut/interrupts_/ctl_iffx_we\nadd wave -noupdate -group interrupts /test_top/dut/interrupts_/ctl_iffx_bit\nadd wave -noupdate -group interrupts /test_top/dut/interrupts_/ctl_im_we\nadd wave -noupdate -group interrupts /test_top/dut/interrupts_/ctl_no_ints\nadd wave -noupdate -group interrupts /test_top/dut/interrupts_/in_nmi\nadd wave -noupdate -group interrupts /test_top/dut/interrupts_/in_intr\nadd wave -noupdate -group interrupts /test_top/dut/interrupts_/int_armed\nadd wave -noupdate -group interrupts /test_top/dut/interrupts_/nmi_armed\nTreeUpdate [SetDefaultTree]\nWaveRestoreCursors {Cursor {3900 ns} 0}\nquietly wave cursor active 1\nconfigure wave -namecolwidth 163\nconfigure wave -valuecolwidth 53\nconfigure wave -justifyvalue left\nconfigure wave -signalnamewidth 1\nconfigure wave -snapdistance 10\nconfigure wave -datasetprefix 0\nconfigure wave -rowmargin 4\nconfigure wave -childrowmargin 2\nconfigure wave -gridoffset 0\nconfigure wave -gridperiod 1\nconfigure wave -griddelta 40\nconfigure wave -timeline 1\nconfigure wave -timelineunits us\nupdate\nWaveRestoreZoom {0 ns} {7800 ns}\n"
  },
  {
    "path": "cpu/toplevel/tb_io.sv",
    "content": "//--------------------------------------------------------------\n// Implements I/O Model for simulation\n//--------------------------------------------------------------\nmodule io (Address, Data, CS, WE, OE);\n\n// Set to 1 to have text output to the file \"iolog.txt\"\nint iolog = 1;\n\n// Set to 1 if you want debug printout on each IO access\nint debug = 0;\n\nint fd;\ninput [15:0] Address;\ninout [7:0] Data;\ninput CS, WE, OE;\n\nreg [7:0] IO [0:1<<16];\n\n// Return data for the specified IO address:\n//  1. If the current address is 0A00, that's the UART busy bit (which is never busy for ModelSim), so return 00\n//  2. If the IO map is not defined for the current address, return FF\n//  3. If the IO map is defined, return the value from it\n//  4. Lastly, if !CS and !OE (not selecting the IO), tri-state the data bus\nassign Data = (!CS && !OE) ? (Address==16'h0A00)? 8'h00 : (IO[Address]===8'hxx) ? 8'hFF : IO[Address] : {8{1'bz}};\n\n// Read the initial content of the IO map from file\ninitial begin : init\n    $readmemh(\"io.hex\", IO);\n    // If logging to a file was enabled, clear the file so we can append\n    if (iolog) begin\n        fd = $fopen(\"iolog.txt\", \"wb\");\n        $fclose(fd);\n    end\nend : init\n\nalways @(!CS && !OE) begin\n    if (debug)\n        $strobe(\"[IO] IN A=%H, D=%H\", Address, Data);\nend\n\nalways @(CS or WE)\n    if (!CS && !WE) begin\n        if (debug)\n            $strobe(\"[IO] OUT A=%H, D=%H\", Address, Data);\n        if (Address==8*256) begin\n            $write(\"%c\", Data);\n            // If logging to a file was enabled, append a character\n            if (iolog) begin\n                fd = $fopen(\"iolog.txt\", \"ab\");\n                $fwrite(fd, \"%c\", Data);\n                $fclose(fd);\n            end\n        end\n        IO[Address] = Data;\n    end\n\nalways @(WE or OE)\n    if (!WE && !OE)\n        $display(\"[IO] error: OE and WE both active!\");\n\nendmodule\n"
  },
  {
    "path": "cpu/toplevel/tb_iorq.sv",
    "content": "//--------------------------------------------------------------\n// Interrupt test for simulation\n// This model injects an interrupt opcode on the bus\n//--------------------------------------------------------------\nmodule iorq (Data, M1, IORQ);\n\n// Set to 1 if you want debug printout on each IO access\nint debug = 0;\n\ninout [7:0] Data;\ninput M1, IORQ;\n\n// Define the opcode to be sent through IORQ (FF=RST38, C7=RST0,...)\n\n// To test interrupts in mode 0, uncommend one of these lines (pushed opcode):\n//`define OPCODE  8'hFF\n//`define OPCODE  8'hC7\n\n// To test interrupts in mode 2, uncommend this line (this is a vector):\n`define OPCODE  8'h80\n\n// Return data on an IORQ condition\nassign Data = (!M1 && !IORQ) ? `OPCODE : {8{1'bz}};\n\nint fd;\n\nalways @(!M1 && !IORQ) begin\n    if (debug)\n        $strobe(\"[IORQ] DB=%H\", `OPCODE);\nend\n\nendmodule\n"
  },
  {
    "path": "cpu/toplevel/tb_ram.sv",
    "content": "//--------------------------------------------------------------\n// Implements RAM Model for simulation\n// Loads in a file \"ram.hexdump\" before execution.\n//--------------------------------------------------------------\nmodule ram (Address, Data, CS, WE, OE);\n\n// Set this to 1 if you want debug printout on each RAM access\nint debug = 0;\n\ninput [15:0] Address;\ninout [7:0] Data;\ninput CS, WE, OE;\n\nreg [7:0] Mem [0:1<<16];\n\n// Return data at the specified memory address; return 0x76 for non-initialized memory\nassign Data = (!CS && !OE) ? (Mem[Address]===8'hxx) ? 8'h76 : Mem[Address] : {8{1'bz}};\n\n// Read the initial content of the RAM memory from a file\ninitial begin : init\n    // Read the CPU code (address 0) to simulate\n    $readmemh(\"ram.hexdump\", Mem, 0);\nend : init\n\nalways @(!CS && !OE) begin\n    if (debug)\n        $strobe(\"[ram] RD A=%H, D=%H\", Address, Data);\nend\n\nalways @(CS or WE)\n    if (!CS && !WE) begin\n        if (debug)\n            $strobe(\"[ram] WR A=%H, D=%H\", Address, Data);\n        Mem[Address] = Data;\n    end\n\nalways @(WE or OE)\n    if (!WE && !OE)\n        $display(\"[ram] error: OE and WE both active!\");\n\nendmodule\n"
  },
  {
    "path": "cpu/toplevel/test_fuse.sv",
    "content": "//--------------------------------------------------------------\n// Testbench using Fuse Z80 emulator test vectors\n//--------------------------------------------------------------\n`include \"z80.svh\"\n\nmodule test_bench_fuse(z80_if.tb z);\n\nassign clk = z.CLK;\n\ninteger f;\n// Instead of the PC register, we read the address of the next instruction\nlogic [15:0] pc;\n\ninitial begin : init\n    z.nWAIT <= `CLR;\n    z.nINT <= `CLR;\n    z.nNMI <= `CLR;\n    z.nBUSRQ <= `CLR;\n    z.nRESET <= `CLR;\n\n    // Run all the tests and write the result to a file\n    f = $fopen(\"fuse.result.txt\");\n    `include \"test_fuse.vh\"\n    $fclose(f);\n\nend : init\n\nendmodule\n\nmodule test_fuse();\n\nbit clk = 1;\ninitial repeat (`TOTAL_CLKS) #1 clk = ~clk;\n\nz80_if z80(clk);            // Instantiate the Z80 bus interface\nz80_top_ifc_n dut(z80);     // Create an instance of our Z80 design\ntest_bench_fuse tb(z80);    // Create an instance of the test bench\n\nram ram( .Address(z80.A), .Data(z80.D), .CS(z80.nMREQ), .WE(z80.nWR), .OE(z80.nRD) );\nio  io( .Address(z80.A), .Data(z80.D), .CS(z80.nIORQ), .WE(z80.nWR), .OE(z80.nRD) );\n\nendmodule\n"
  },
  {
    "path": "cpu/toplevel/test_fuse.vh",
    "content": "// Automatically generated by genfuse.py\n\nforce dut.resets_.clrpc=0;\nforce dut.reg_file_.reg_gp_we=0;\nforce dut.reg_control_.ctl_reg_sys_we=0;\nforce dut.z80_top_ifc_n.fpga_reset=1;\n#2 // Start test loop\n\n   force dut.ir_.ctl_ir_we=1;\n   force dut.ir_.db=0;\n#2 release dut.ir_.ctl_ir_we;\n   release dut.ir_.db;\n   $fdisplay(f,\"Testing opcode 00      NOP\");\n   // Preset af\n   force dut.reg_file_.b2v_latch_af_lo.we=1;\n   force dut.reg_file_.b2v_latch_af_hi.we=1;\n   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_af_lo.we;\n   release dut.reg_file_.b2v_latch_af_hi.we;\n   release dut.reg_file_.b2v_latch_af_lo.db;\n   release dut.reg_file_.b2v_latch_af_hi.db;\n   // Preset bc\n   force dut.reg_file_.b2v_latch_bc_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_bc_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_bc_lo.we;\n   release dut.reg_file_.b2v_latch_bc_hi.we;\n   release dut.reg_file_.b2v_latch_bc_lo.db;\n   release dut.reg_file_.b2v_latch_bc_hi.db;\n   // Preset de\n   force dut.reg_file_.b2v_latch_de_lo.we=1;\n   force dut.reg_file_.b2v_latch_de_hi.we=1;\n   force dut.reg_file_.b2v_latch_de_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_de_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_de_lo.we;\n   release dut.reg_file_.b2v_latch_de_hi.we;\n   release dut.reg_file_.b2v_latch_de_lo.db;\n   release dut.reg_file_.b2v_latch_de_hi.db;\n   // Preset hl\n   force dut.reg_file_.b2v_latch_hl_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_hl_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_hl_lo.we;\n   release dut.reg_file_.b2v_latch_hl_hi.we;\n   release dut.reg_file_.b2v_latch_hl_lo.db;\n   release dut.reg_file_.b2v_latch_hl_hi.db;\n   // Preset af2\n   force dut.reg_file_.b2v_latch_af2_lo.we=1;\n   force dut.reg_file_.b2v_latch_af2_hi.we=1;\n   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_af2_lo.we;\n   release dut.reg_file_.b2v_latch_af2_hi.we;\n   release dut.reg_file_.b2v_latch_af2_lo.db;\n   release dut.reg_file_.b2v_latch_af2_hi.db;\n   // Preset bc2\n   force dut.reg_file_.b2v_latch_bc2_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc2_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_bc2_lo.we;\n   release dut.reg_file_.b2v_latch_bc2_hi.we;\n   release dut.reg_file_.b2v_latch_bc2_lo.db;\n   release dut.reg_file_.b2v_latch_bc2_hi.db;\n   // Preset de2\n   force dut.reg_file_.b2v_latch_de2_lo.we=1;\n   force dut.reg_file_.b2v_latch_de2_hi.we=1;\n   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_de2_lo.we;\n   release dut.reg_file_.b2v_latch_de2_hi.we;\n   release dut.reg_file_.b2v_latch_de2_lo.db;\n   release dut.reg_file_.b2v_latch_de2_hi.db;\n   // Preset hl2\n   force dut.reg_file_.b2v_latch_hl2_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl2_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_hl2_lo.we;\n   release dut.reg_file_.b2v_latch_hl2_hi.we;\n   release dut.reg_file_.b2v_latch_hl2_lo.db;\n   release dut.reg_file_.b2v_latch_hl2_hi.db;\n   // Preset ix\n   force dut.reg_file_.b2v_latch_ix_lo.we=1;\n   force dut.reg_file_.b2v_latch_ix_hi.we=1;\n   force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ix_lo.we;\n   release dut.reg_file_.b2v_latch_ix_hi.we;\n   release dut.reg_file_.b2v_latch_ix_lo.db;\n   release dut.reg_file_.b2v_latch_ix_hi.db;\n   // Preset iy\n   force dut.reg_file_.b2v_latch_iy_lo.we=1;\n   force dut.reg_file_.b2v_latch_iy_hi.we=1;\n   force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_iy_lo.we;\n   release dut.reg_file_.b2v_latch_iy_hi.we;\n   release dut.reg_file_.b2v_latch_iy_lo.db;\n   release dut.reg_file_.b2v_latch_iy_hi.db;\n   // Preset sp\n   force dut.reg_file_.b2v_latch_sp_lo.we=1;\n   force dut.reg_file_.b2v_latch_sp_hi.we=1;\n   force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_sp_lo.we;\n   release dut.reg_file_.b2v_latch_sp_hi.we;\n   release dut.reg_file_.b2v_latch_sp_lo.db;\n   release dut.reg_file_.b2v_latch_sp_hi.db;\n   // Preset wz\n   force dut.reg_file_.b2v_latch_wz_lo.we=1;\n   force dut.reg_file_.b2v_latch_wz_hi.we=1;\n   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_wz_lo.we;\n   release dut.reg_file_.b2v_latch_wz_hi.we;\n   release dut.reg_file_.b2v_latch_wz_lo.db;\n   release dut.reg_file_.b2v_latch_wz_hi.db;\n   // Preset pc\n   force dut.reg_file_.b2v_latch_pc_lo.we=1;\n   force dut.reg_file_.b2v_latch_pc_hi.we=1;\n   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_pc_lo.we;\n   release dut.reg_file_.b2v_latch_pc_hi.we;\n   release dut.reg_file_.b2v_latch_pc_lo.db;\n   release dut.reg_file_.b2v_latch_pc_hi.db;\n   // Preset ir\n   force dut.reg_file_.b2v_latch_ir_lo.we=1;\n   force dut.reg_file_.b2v_latch_ir_hi.we=1;\n   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ir_lo.we;\n   release dut.reg_file_.b2v_latch_ir_hi.we;\n   release dut.reg_file_.b2v_latch_ir_lo.db;\n   release dut.reg_file_.b2v_latch_ir_hi.db;\n   // Preset memory\n   ram.Mem[0] = 8'h00;\n   force dut.z80_top_ifc_n.fpga_reset=0;\n   force dut.address_latch_.Q=16'h0000;\n   release dut.reg_control_.ctl_reg_sys_we;\n   release dut.reg_file_.reg_gp_we;\n#2 // Execute: M1/T1 start\n#1 release dut.address_latch_.Q;\n#1\n#6 // Wait for opcode end\n   force dut.reg_control_.ctl_reg_sys_we=0;\n#2 pc=z.A;\n#2\n#1 force dut.reg_file_.reg_gp_we=0;\n   force dut.z80_top_ifc_n.fpga_reset=1;\n   if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h00) $fdisplay(f,\"* Reg af f=%h !=00\",dut.reg_file_.b2v_latch_af_lo.latch);\n   if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h00) $fdisplay(f,\"* Reg af a=%h !=00\",dut.reg_file_.b2v_latch_af_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h00) $fdisplay(f,\"* Reg bc c=%h !=00\",dut.reg_file_.b2v_latch_bc_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h00) $fdisplay(f,\"* Reg bc b=%h !=00\",dut.reg_file_.b2v_latch_bc_hi.latch);\n   if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h00) $fdisplay(f,\"* Reg de e=%h !=00\",dut.reg_file_.b2v_latch_de_lo.latch);\n   if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h00) $fdisplay(f,\"* Reg de d=%h !=00\",dut.reg_file_.b2v_latch_de_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h00) $fdisplay(f,\"* Reg hl l=%h !=00\",dut.reg_file_.b2v_latch_hl_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h00) $fdisplay(f,\"* Reg hl h=%h !=00\",dut.reg_file_.b2v_latch_hl_hi.latch);\n   if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,\"* Reg af2 f=%h !=00\",dut.reg_file_.b2v_latch_af2_lo.latch);\n   if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,\"* Reg af2 a=%h !=00\",dut.reg_file_.b2v_latch_af2_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,\"* Reg bc2 c=%h !=00\",dut.reg_file_.b2v_latch_bc2_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,\"* Reg bc2 b=%h !=00\",dut.reg_file_.b2v_latch_bc2_hi.latch);\n   if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,\"* Reg de2 e=%h !=00\",dut.reg_file_.b2v_latch_de2_lo.latch);\n   if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,\"* Reg de2 d=%h !=00\",dut.reg_file_.b2v_latch_de2_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,\"* Reg hl2 l=%h !=00\",dut.reg_file_.b2v_latch_hl2_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,\"* Reg hl2 h=%h !=00\",dut.reg_file_.b2v_latch_hl2_hi.latch);\n   if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,\"* Reg ix x=%h !=00\",dut.reg_file_.b2v_latch_ix_lo.latch);\n   if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,\"* Reg ix i=%h !=00\",dut.reg_file_.b2v_latch_ix_hi.latch);\n   if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,\"* Reg iy y=%h !=00\",dut.reg_file_.b2v_latch_iy_lo.latch);\n   if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,\"* Reg iy i=%h !=00\",dut.reg_file_.b2v_latch_iy_hi.latch);\n   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,\"* Reg sp p=%h !=00\",dut.reg_file_.b2v_latch_sp_lo.latch);\n   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,\"* Reg sp s=%h !=00\",dut.reg_file_.b2v_latch_sp_hi.latch);\n   if (pc!==16'h0001) $fdisplay(f,\"* PC=%h !=0001\",pc);\n   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,\"* Reg ir r=%h !=01\",dut.reg_file_.b2v_latch_ir_lo.latch);\n   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,\"* Reg ir i=%h !=00\",dut.reg_file_.b2v_latch_ir_hi.latch);\n#1 // End opcode\n\n   force dut.ir_.ctl_ir_we=1;\n   force dut.ir_.db=0;\n#2 release dut.ir_.ctl_ir_we;\n   release dut.ir_.db;\n   $fdisplay(f,\"Testing opcode ed67    RRD\");\n   // Preset af\n   force dut.reg_file_.b2v_latch_af_lo.we=1;\n   force dut.reg_file_.b2v_latch_af_hi.we=1;\n   force dut.reg_file_.b2v_latch_af_lo.db=8'h24;\n   force dut.reg_file_.b2v_latch_af_hi.db=8'h36;\n#2 release dut.reg_file_.b2v_latch_af_lo.we;\n   release dut.reg_file_.b2v_latch_af_hi.we;\n   release dut.reg_file_.b2v_latch_af_lo.db;\n   release dut.reg_file_.b2v_latch_af_hi.db;\n   // Preset bc\n   force dut.reg_file_.b2v_latch_bc_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc_lo.db=8'h6a;\n   force dut.reg_file_.b2v_latch_bc_hi.db=8'hb1;\n#2 release dut.reg_file_.b2v_latch_bc_lo.we;\n   release dut.reg_file_.b2v_latch_bc_hi.we;\n   release dut.reg_file_.b2v_latch_bc_lo.db;\n   release dut.reg_file_.b2v_latch_bc_hi.db;\n   // Preset de\n   force dut.reg_file_.b2v_latch_de_lo.we=1;\n   force dut.reg_file_.b2v_latch_de_hi.we=1;\n   force dut.reg_file_.b2v_latch_de_lo.db=8'hdb;\n   force dut.reg_file_.b2v_latch_de_hi.db=8'ha4;\n#2 release dut.reg_file_.b2v_latch_de_lo.we;\n   release dut.reg_file_.b2v_latch_de_hi.we;\n   release dut.reg_file_.b2v_latch_de_lo.db;\n   release dut.reg_file_.b2v_latch_de_hi.db;\n   // Preset hl\n   force dut.reg_file_.b2v_latch_hl_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl_lo.db=8'hde;\n   force dut.reg_file_.b2v_latch_hl_hi.db=8'hb9;\n#2 release dut.reg_file_.b2v_latch_hl_lo.we;\n   release dut.reg_file_.b2v_latch_hl_hi.we;\n   release dut.reg_file_.b2v_latch_hl_lo.db;\n   release dut.reg_file_.b2v_latch_hl_hi.db;\n   // Preset af2\n   force dut.reg_file_.b2v_latch_af2_lo.we=1;\n   force dut.reg_file_.b2v_latch_af2_hi.we=1;\n   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_af2_lo.we;\n   release dut.reg_file_.b2v_latch_af2_hi.we;\n   release dut.reg_file_.b2v_latch_af2_lo.db;\n   release dut.reg_file_.b2v_latch_af2_hi.db;\n   // Preset bc2\n   force dut.reg_file_.b2v_latch_bc2_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc2_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_bc2_lo.we;\n   release dut.reg_file_.b2v_latch_bc2_hi.we;\n   release dut.reg_file_.b2v_latch_bc2_lo.db;\n   release dut.reg_file_.b2v_latch_bc2_hi.db;\n   // Preset de2\n   force dut.reg_file_.b2v_latch_de2_lo.we=1;\n   force dut.reg_file_.b2v_latch_de2_hi.we=1;\n   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_de2_lo.we;\n   release dut.reg_file_.b2v_latch_de2_hi.we;\n   release dut.reg_file_.b2v_latch_de2_lo.db;\n   release dut.reg_file_.b2v_latch_de2_hi.db;\n   // Preset hl2\n   force dut.reg_file_.b2v_latch_hl2_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl2_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_hl2_lo.we;\n   release dut.reg_file_.b2v_latch_hl2_hi.we;\n   release dut.reg_file_.b2v_latch_hl2_lo.db;\n   release dut.reg_file_.b2v_latch_hl2_hi.db;\n   // Preset ix\n   force dut.reg_file_.b2v_latch_ix_lo.we=1;\n   force dut.reg_file_.b2v_latch_ix_hi.we=1;\n   force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ix_lo.we;\n   release dut.reg_file_.b2v_latch_ix_hi.we;\n   release dut.reg_file_.b2v_latch_ix_lo.db;\n   release dut.reg_file_.b2v_latch_ix_hi.db;\n   // Preset iy\n   force dut.reg_file_.b2v_latch_iy_lo.we=1;\n   force dut.reg_file_.b2v_latch_iy_hi.we=1;\n   force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_iy_lo.we;\n   release dut.reg_file_.b2v_latch_iy_hi.we;\n   release dut.reg_file_.b2v_latch_iy_lo.db;\n   release dut.reg_file_.b2v_latch_iy_hi.db;\n   // Preset sp\n   force dut.reg_file_.b2v_latch_sp_lo.we=1;\n   force dut.reg_file_.b2v_latch_sp_hi.we=1;\n   force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_sp_lo.we;\n   release dut.reg_file_.b2v_latch_sp_hi.we;\n   release dut.reg_file_.b2v_latch_sp_lo.db;\n   release dut.reg_file_.b2v_latch_sp_hi.db;\n   // Preset wz\n   force dut.reg_file_.b2v_latch_wz_lo.we=1;\n   force dut.reg_file_.b2v_latch_wz_hi.we=1;\n   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_wz_lo.we;\n   release dut.reg_file_.b2v_latch_wz_hi.we;\n   release dut.reg_file_.b2v_latch_wz_lo.db;\n   release dut.reg_file_.b2v_latch_wz_hi.db;\n   // Preset pc\n   force dut.reg_file_.b2v_latch_pc_lo.we=1;\n   force dut.reg_file_.b2v_latch_pc_hi.we=1;\n   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_pc_lo.we;\n   release dut.reg_file_.b2v_latch_pc_hi.we;\n   release dut.reg_file_.b2v_latch_pc_lo.db;\n   release dut.reg_file_.b2v_latch_pc_hi.db;\n   // Preset ir\n   force dut.reg_file_.b2v_latch_ir_lo.we=1;\n   force dut.reg_file_.b2v_latch_ir_hi.we=1;\n   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ir_lo.we;\n   release dut.reg_file_.b2v_latch_ir_hi.we;\n   release dut.reg_file_.b2v_latch_ir_lo.db;\n   release dut.reg_file_.b2v_latch_ir_hi.db;\n   // Preset memory\n   ram.Mem[0] = 8'hed;\n   ram.Mem[1] = 8'h67;\n   // Preset memory\n   ram.Mem[47582] = 8'h93;\n   force dut.z80_top_ifc_n.fpga_reset=0;\n   force dut.address_latch_.Q=16'h0000;\n   release dut.reg_control_.ctl_reg_sys_we;\n   release dut.reg_file_.reg_gp_we;\n#2 // Execute: M1/T1 start\n#1 release dut.address_latch_.Q;\n#1\n#34 // Wait for opcode end\n   force dut.reg_control_.ctl_reg_sys_we=0;\n#2 pc=z.A;\n#2\n#1 force dut.reg_file_.reg_gp_we=0;\n   force dut.z80_top_ifc_n.fpga_reset=1;\n   if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h24) $fdisplay(f,\"* Reg af f=%h !=24\",dut.reg_file_.b2v_latch_af_lo.latch);\n   if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h33) $fdisplay(f,\"* Reg af a=%h !=33\",dut.reg_file_.b2v_latch_af_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h6a) $fdisplay(f,\"* Reg bc c=%h !=6a\",dut.reg_file_.b2v_latch_bc_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'hb1) $fdisplay(f,\"* Reg bc b=%h !=b1\",dut.reg_file_.b2v_latch_bc_hi.latch);\n   if (dut.reg_file_.b2v_latch_de_lo.latch!==8'hdb) $fdisplay(f,\"* Reg de e=%h !=db\",dut.reg_file_.b2v_latch_de_lo.latch);\n   if (dut.reg_file_.b2v_latch_de_hi.latch!==8'ha4) $fdisplay(f,\"* Reg de d=%h !=a4\",dut.reg_file_.b2v_latch_de_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'hde) $fdisplay(f,\"* Reg hl l=%h !=de\",dut.reg_file_.b2v_latch_hl_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hb9) $fdisplay(f,\"* Reg hl h=%h !=b9\",dut.reg_file_.b2v_latch_hl_hi.latch);\n   if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,\"* Reg af2 f=%h !=00\",dut.reg_file_.b2v_latch_af2_lo.latch);\n   if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,\"* Reg af2 a=%h !=00\",dut.reg_file_.b2v_latch_af2_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,\"* Reg bc2 c=%h !=00\",dut.reg_file_.b2v_latch_bc2_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,\"* Reg bc2 b=%h !=00\",dut.reg_file_.b2v_latch_bc2_hi.latch);\n   if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,\"* Reg de2 e=%h !=00\",dut.reg_file_.b2v_latch_de2_lo.latch);\n   if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,\"* Reg de2 d=%h !=00\",dut.reg_file_.b2v_latch_de2_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,\"* Reg hl2 l=%h !=00\",dut.reg_file_.b2v_latch_hl2_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,\"* Reg hl2 h=%h !=00\",dut.reg_file_.b2v_latch_hl2_hi.latch);\n   if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,\"* Reg ix x=%h !=00\",dut.reg_file_.b2v_latch_ix_lo.latch);\n   if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,\"* Reg ix i=%h !=00\",dut.reg_file_.b2v_latch_ix_hi.latch);\n   if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,\"* Reg iy y=%h !=00\",dut.reg_file_.b2v_latch_iy_lo.latch);\n   if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,\"* Reg iy i=%h !=00\",dut.reg_file_.b2v_latch_iy_hi.latch);\n   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,\"* Reg sp p=%h !=00\",dut.reg_file_.b2v_latch_sp_lo.latch);\n   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,\"* Reg sp s=%h !=00\",dut.reg_file_.b2v_latch_sp_hi.latch);\n   if (pc!==16'h0002) $fdisplay(f,\"* PC=%h !=0002\",pc);\n   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,\"* Reg ir r=%h !=02\",dut.reg_file_.b2v_latch_ir_lo.latch);\n   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,\"* Reg ir i=%h !=00\",dut.reg_file_.b2v_latch_ir_hi.latch);\n   if (ram.Mem[47582]!==8'h69) $fdisplay(f,\"* Mem[b9de]=%h !=69\",ram.Mem[47582]);\n#1 // End opcode\n\n   force dut.ir_.ctl_ir_we=1;\n   force dut.ir_.db=0;\n#2 release dut.ir_.ctl_ir_we;\n   release dut.ir_.db;\n   $fdisplay(f,\"Testing opcode ed6f    RLD\");\n   // Preset af\n   force dut.reg_file_.b2v_latch_af_lo.we=1;\n   force dut.reg_file_.b2v_latch_af_hi.we=1;\n   force dut.reg_file_.b2v_latch_af_lo.db=8'h8b;\n   force dut.reg_file_.b2v_latch_af_hi.db=8'h65;\n#2 release dut.reg_file_.b2v_latch_af_lo.we;\n   release dut.reg_file_.b2v_latch_af_hi.we;\n   release dut.reg_file_.b2v_latch_af_lo.db;\n   release dut.reg_file_.b2v_latch_af_hi.db;\n   // Preset bc\n   force dut.reg_file_.b2v_latch_bc_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc_lo.db=8'h7a;\n   force dut.reg_file_.b2v_latch_bc_hi.db=8'h7a;\n#2 release dut.reg_file_.b2v_latch_bc_lo.we;\n   release dut.reg_file_.b2v_latch_bc_hi.we;\n   release dut.reg_file_.b2v_latch_bc_lo.db;\n   release dut.reg_file_.b2v_latch_bc_hi.db;\n   // Preset de\n   force dut.reg_file_.b2v_latch_de_lo.we=1;\n   force dut.reg_file_.b2v_latch_de_hi.we=1;\n   force dut.reg_file_.b2v_latch_de_lo.db=8'hf0;\n   force dut.reg_file_.b2v_latch_de_hi.db=8'hec;\n#2 release dut.reg_file_.b2v_latch_de_lo.we;\n   release dut.reg_file_.b2v_latch_de_hi.we;\n   release dut.reg_file_.b2v_latch_de_lo.db;\n   release dut.reg_file_.b2v_latch_de_hi.db;\n   // Preset hl\n   force dut.reg_file_.b2v_latch_hl_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl_lo.db=8'h3c;\n   force dut.reg_file_.b2v_latch_hl_hi.db=8'h40;\n#2 release dut.reg_file_.b2v_latch_hl_lo.we;\n   release dut.reg_file_.b2v_latch_hl_hi.we;\n   release dut.reg_file_.b2v_latch_hl_lo.db;\n   release dut.reg_file_.b2v_latch_hl_hi.db;\n   // Preset af2\n   force dut.reg_file_.b2v_latch_af2_lo.we=1;\n   force dut.reg_file_.b2v_latch_af2_hi.we=1;\n   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_af2_lo.we;\n   release dut.reg_file_.b2v_latch_af2_hi.we;\n   release dut.reg_file_.b2v_latch_af2_lo.db;\n   release dut.reg_file_.b2v_latch_af2_hi.db;\n   // Preset bc2\n   force dut.reg_file_.b2v_latch_bc2_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc2_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_bc2_lo.we;\n   release dut.reg_file_.b2v_latch_bc2_hi.we;\n   release dut.reg_file_.b2v_latch_bc2_lo.db;\n   release dut.reg_file_.b2v_latch_bc2_hi.db;\n   // Preset de2\n   force dut.reg_file_.b2v_latch_de2_lo.we=1;\n   force dut.reg_file_.b2v_latch_de2_hi.we=1;\n   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_de2_lo.we;\n   release dut.reg_file_.b2v_latch_de2_hi.we;\n   release dut.reg_file_.b2v_latch_de2_lo.db;\n   release dut.reg_file_.b2v_latch_de2_hi.db;\n   // Preset hl2\n   force dut.reg_file_.b2v_latch_hl2_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl2_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_hl2_lo.we;\n   release dut.reg_file_.b2v_latch_hl2_hi.we;\n   release dut.reg_file_.b2v_latch_hl2_lo.db;\n   release dut.reg_file_.b2v_latch_hl2_hi.db;\n   // Preset ix\n   force dut.reg_file_.b2v_latch_ix_lo.we=1;\n   force dut.reg_file_.b2v_latch_ix_hi.we=1;\n   force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ix_lo.we;\n   release dut.reg_file_.b2v_latch_ix_hi.we;\n   release dut.reg_file_.b2v_latch_ix_lo.db;\n   release dut.reg_file_.b2v_latch_ix_hi.db;\n   // Preset iy\n   force dut.reg_file_.b2v_latch_iy_lo.we=1;\n   force dut.reg_file_.b2v_latch_iy_hi.we=1;\n   force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_iy_lo.we;\n   release dut.reg_file_.b2v_latch_iy_hi.we;\n   release dut.reg_file_.b2v_latch_iy_lo.db;\n   release dut.reg_file_.b2v_latch_iy_hi.db;\n   // Preset sp\n   force dut.reg_file_.b2v_latch_sp_lo.we=1;\n   force dut.reg_file_.b2v_latch_sp_hi.we=1;\n   force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_sp_lo.we;\n   release dut.reg_file_.b2v_latch_sp_hi.we;\n   release dut.reg_file_.b2v_latch_sp_lo.db;\n   release dut.reg_file_.b2v_latch_sp_hi.db;\n   // Preset wz\n   force dut.reg_file_.b2v_latch_wz_lo.we=1;\n   force dut.reg_file_.b2v_latch_wz_hi.we=1;\n   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_wz_lo.we;\n   release dut.reg_file_.b2v_latch_wz_hi.we;\n   release dut.reg_file_.b2v_latch_wz_lo.db;\n   release dut.reg_file_.b2v_latch_wz_hi.db;\n   // Preset pc\n   force dut.reg_file_.b2v_latch_pc_lo.we=1;\n   force dut.reg_file_.b2v_latch_pc_hi.we=1;\n   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_pc_lo.we;\n   release dut.reg_file_.b2v_latch_pc_hi.we;\n   release dut.reg_file_.b2v_latch_pc_lo.db;\n   release dut.reg_file_.b2v_latch_pc_hi.db;\n   // Preset ir\n   force dut.reg_file_.b2v_latch_ir_lo.we=1;\n   force dut.reg_file_.b2v_latch_ir_hi.we=1;\n   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ir_lo.we;\n   release dut.reg_file_.b2v_latch_ir_hi.we;\n   release dut.reg_file_.b2v_latch_ir_lo.db;\n   release dut.reg_file_.b2v_latch_ir_hi.db;\n   // Preset memory\n   ram.Mem[0] = 8'hed;\n   ram.Mem[1] = 8'h6f;\n   // Preset memory\n   ram.Mem[16444] = 8'hc4;\n   force dut.z80_top_ifc_n.fpga_reset=0;\n   force dut.address_latch_.Q=16'h0000;\n   release dut.reg_control_.ctl_reg_sys_we;\n   release dut.reg_file_.reg_gp_we;\n#2 // Execute: M1/T1 start\n#1 release dut.address_latch_.Q;\n#1\n#34 // Wait for opcode end\n   force dut.reg_control_.ctl_reg_sys_we=0;\n#2 pc=z.A;\n#2\n#1 force dut.reg_file_.reg_gp_we=0;\n   force dut.z80_top_ifc_n.fpga_reset=1;\n   if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h2d) $fdisplay(f,\"* Reg af f=%h !=2d\",dut.reg_file_.b2v_latch_af_lo.latch);\n   if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h6c) $fdisplay(f,\"* Reg af a=%h !=6c\",dut.reg_file_.b2v_latch_af_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h7a) $fdisplay(f,\"* Reg bc c=%h !=7a\",dut.reg_file_.b2v_latch_bc_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h7a) $fdisplay(f,\"* Reg bc b=%h !=7a\",dut.reg_file_.b2v_latch_bc_hi.latch);\n   if (dut.reg_file_.b2v_latch_de_lo.latch!==8'hf0) $fdisplay(f,\"* Reg de e=%h !=f0\",dut.reg_file_.b2v_latch_de_lo.latch);\n   if (dut.reg_file_.b2v_latch_de_hi.latch!==8'hec) $fdisplay(f,\"* Reg de d=%h !=ec\",dut.reg_file_.b2v_latch_de_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h3c) $fdisplay(f,\"* Reg hl l=%h !=3c\",dut.reg_file_.b2v_latch_hl_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h40) $fdisplay(f,\"* Reg hl h=%h !=40\",dut.reg_file_.b2v_latch_hl_hi.latch);\n   if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,\"* Reg af2 f=%h !=00\",dut.reg_file_.b2v_latch_af2_lo.latch);\n   if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,\"* Reg af2 a=%h !=00\",dut.reg_file_.b2v_latch_af2_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,\"* Reg bc2 c=%h !=00\",dut.reg_file_.b2v_latch_bc2_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,\"* Reg bc2 b=%h !=00\",dut.reg_file_.b2v_latch_bc2_hi.latch);\n   if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,\"* Reg de2 e=%h !=00\",dut.reg_file_.b2v_latch_de2_lo.latch);\n   if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,\"* Reg de2 d=%h !=00\",dut.reg_file_.b2v_latch_de2_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,\"* Reg hl2 l=%h !=00\",dut.reg_file_.b2v_latch_hl2_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,\"* Reg hl2 h=%h !=00\",dut.reg_file_.b2v_latch_hl2_hi.latch);\n   if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,\"* Reg ix x=%h !=00\",dut.reg_file_.b2v_latch_ix_lo.latch);\n   if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,\"* Reg ix i=%h !=00\",dut.reg_file_.b2v_latch_ix_hi.latch);\n   if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,\"* Reg iy y=%h !=00\",dut.reg_file_.b2v_latch_iy_lo.latch);\n   if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,\"* Reg iy i=%h !=00\",dut.reg_file_.b2v_latch_iy_hi.latch);\n   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,\"* Reg sp p=%h !=00\",dut.reg_file_.b2v_latch_sp_lo.latch);\n   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,\"* Reg sp s=%h !=00\",dut.reg_file_.b2v_latch_sp_hi.latch);\n   if (pc!==16'h0002) $fdisplay(f,\"* PC=%h !=0002\",pc);\n   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,\"* Reg ir r=%h !=02\",dut.reg_file_.b2v_latch_ir_lo.latch);\n   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,\"* Reg ir i=%h !=00\",dut.reg_file_.b2v_latch_ir_hi.latch);\n   if (ram.Mem[16444]!==8'h45) $fdisplay(f,\"* Mem[403c]=%h !=45\",ram.Mem[16444]);\n#1 // End opcode\n\n   force dut.ir_.ctl_ir_we=1;\n   force dut.ir_.db=0;\n#2 release dut.ir_.ctl_ir_we;\n   release dut.ir_.db;\n   $fdisplay(f,\"Testing opcode 81      ADD A,C\");\n   // Preset af\n   force dut.reg_file_.b2v_latch_af_lo.we=1;\n   force dut.reg_file_.b2v_latch_af_hi.we=1;\n   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af_hi.db=8'hf5;\n#2 release dut.reg_file_.b2v_latch_af_lo.we;\n   release dut.reg_file_.b2v_latch_af_hi.we;\n   release dut.reg_file_.b2v_latch_af_lo.db;\n   release dut.reg_file_.b2v_latch_af_hi.db;\n   // Preset bc\n   force dut.reg_file_.b2v_latch_bc_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc_lo.db=8'h3b;\n   force dut.reg_file_.b2v_latch_bc_hi.db=8'h0f;\n#2 release dut.reg_file_.b2v_latch_bc_lo.we;\n   release dut.reg_file_.b2v_latch_bc_hi.we;\n   release dut.reg_file_.b2v_latch_bc_lo.db;\n   release dut.reg_file_.b2v_latch_bc_hi.db;\n   // Preset de\n   force dut.reg_file_.b2v_latch_de_lo.we=1;\n   force dut.reg_file_.b2v_latch_de_hi.we=1;\n   force dut.reg_file_.b2v_latch_de_lo.db=8'h0d;\n   force dut.reg_file_.b2v_latch_de_hi.db=8'h20;\n#2 release dut.reg_file_.b2v_latch_de_lo.we;\n   release dut.reg_file_.b2v_latch_de_hi.we;\n   release dut.reg_file_.b2v_latch_de_lo.db;\n   release dut.reg_file_.b2v_latch_de_hi.db;\n   // Preset hl\n   force dut.reg_file_.b2v_latch_hl_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl_lo.db=8'ha6;\n   force dut.reg_file_.b2v_latch_hl_hi.db=8'hdc;\n#2 release dut.reg_file_.b2v_latch_hl_lo.we;\n   release dut.reg_file_.b2v_latch_hl_hi.we;\n   release dut.reg_file_.b2v_latch_hl_lo.db;\n   release dut.reg_file_.b2v_latch_hl_hi.db;\n   // Preset af2\n   force dut.reg_file_.b2v_latch_af2_lo.we=1;\n   force dut.reg_file_.b2v_latch_af2_hi.we=1;\n   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_af2_lo.we;\n   release dut.reg_file_.b2v_latch_af2_hi.we;\n   release dut.reg_file_.b2v_latch_af2_lo.db;\n   release dut.reg_file_.b2v_latch_af2_hi.db;\n   // Preset bc2\n   force dut.reg_file_.b2v_latch_bc2_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc2_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_bc2_lo.we;\n   release dut.reg_file_.b2v_latch_bc2_hi.we;\n   release dut.reg_file_.b2v_latch_bc2_lo.db;\n   release dut.reg_file_.b2v_latch_bc2_hi.db;\n   // Preset de2\n   force dut.reg_file_.b2v_latch_de2_lo.we=1;\n   force dut.reg_file_.b2v_latch_de2_hi.we=1;\n   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_de2_lo.we;\n   release dut.reg_file_.b2v_latch_de2_hi.we;\n   release dut.reg_file_.b2v_latch_de2_lo.db;\n   release dut.reg_file_.b2v_latch_de2_hi.db;\n   // Preset hl2\n   force dut.reg_file_.b2v_latch_hl2_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl2_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_hl2_lo.we;\n   release dut.reg_file_.b2v_latch_hl2_hi.we;\n   release dut.reg_file_.b2v_latch_hl2_lo.db;\n   release dut.reg_file_.b2v_latch_hl2_hi.db;\n   // Preset ix\n   force dut.reg_file_.b2v_latch_ix_lo.we=1;\n   force dut.reg_file_.b2v_latch_ix_hi.we=1;\n   force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ix_lo.we;\n   release dut.reg_file_.b2v_latch_ix_hi.we;\n   release dut.reg_file_.b2v_latch_ix_lo.db;\n   release dut.reg_file_.b2v_latch_ix_hi.db;\n   // Preset iy\n   force dut.reg_file_.b2v_latch_iy_lo.we=1;\n   force dut.reg_file_.b2v_latch_iy_hi.we=1;\n   force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_iy_lo.we;\n   release dut.reg_file_.b2v_latch_iy_hi.we;\n   release dut.reg_file_.b2v_latch_iy_lo.db;\n   release dut.reg_file_.b2v_latch_iy_hi.db;\n   // Preset sp\n   force dut.reg_file_.b2v_latch_sp_lo.we=1;\n   force dut.reg_file_.b2v_latch_sp_hi.we=1;\n   force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_sp_lo.we;\n   release dut.reg_file_.b2v_latch_sp_hi.we;\n   release dut.reg_file_.b2v_latch_sp_lo.db;\n   release dut.reg_file_.b2v_latch_sp_hi.db;\n   // Preset wz\n   force dut.reg_file_.b2v_latch_wz_lo.we=1;\n   force dut.reg_file_.b2v_latch_wz_hi.we=1;\n   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_wz_lo.we;\n   release dut.reg_file_.b2v_latch_wz_hi.we;\n   release dut.reg_file_.b2v_latch_wz_lo.db;\n   release dut.reg_file_.b2v_latch_wz_hi.db;\n   // Preset pc\n   force dut.reg_file_.b2v_latch_pc_lo.we=1;\n   force dut.reg_file_.b2v_latch_pc_hi.we=1;\n   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_pc_lo.we;\n   release dut.reg_file_.b2v_latch_pc_hi.we;\n   release dut.reg_file_.b2v_latch_pc_lo.db;\n   release dut.reg_file_.b2v_latch_pc_hi.db;\n   // Preset ir\n   force dut.reg_file_.b2v_latch_ir_lo.we=1;\n   force dut.reg_file_.b2v_latch_ir_hi.we=1;\n   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ir_lo.we;\n   release dut.reg_file_.b2v_latch_ir_hi.we;\n   release dut.reg_file_.b2v_latch_ir_lo.db;\n   release dut.reg_file_.b2v_latch_ir_hi.db;\n   // Preset memory\n   ram.Mem[0] = 8'h81;\n   // Preset memory\n   ram.Mem[56486] = 8'h49;\n   force dut.z80_top_ifc_n.fpga_reset=0;\n   force dut.address_latch_.Q=16'h0000;\n   release dut.reg_control_.ctl_reg_sys_we;\n   release dut.reg_file_.reg_gp_we;\n#2 // Execute: M1/T1 start\n#1 release dut.address_latch_.Q;\n#1\n#6 // Wait for opcode end\n   force dut.reg_control_.ctl_reg_sys_we=0;\n#2 pc=z.A;\n#2\n#1 force dut.reg_file_.reg_gp_we=0;\n   force dut.z80_top_ifc_n.fpga_reset=1;\n   if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h31) $fdisplay(f,\"* Reg af f=%h !=31\",dut.reg_file_.b2v_latch_af_lo.latch);\n   if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h30) $fdisplay(f,\"* Reg af a=%h !=30\",dut.reg_file_.b2v_latch_af_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h3b) $fdisplay(f,\"* Reg bc c=%h !=3b\",dut.reg_file_.b2v_latch_bc_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h0f) $fdisplay(f,\"* Reg bc b=%h !=0f\",dut.reg_file_.b2v_latch_bc_hi.latch);\n   if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h0d) $fdisplay(f,\"* Reg de e=%h !=0d\",dut.reg_file_.b2v_latch_de_lo.latch);\n   if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h20) $fdisplay(f,\"* Reg de d=%h !=20\",dut.reg_file_.b2v_latch_de_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'ha6) $fdisplay(f,\"* Reg hl l=%h !=a6\",dut.reg_file_.b2v_latch_hl_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hdc) $fdisplay(f,\"* Reg hl h=%h !=dc\",dut.reg_file_.b2v_latch_hl_hi.latch);\n   if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,\"* Reg af2 f=%h !=00\",dut.reg_file_.b2v_latch_af2_lo.latch);\n   if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,\"* Reg af2 a=%h !=00\",dut.reg_file_.b2v_latch_af2_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,\"* Reg bc2 c=%h !=00\",dut.reg_file_.b2v_latch_bc2_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,\"* Reg bc2 b=%h !=00\",dut.reg_file_.b2v_latch_bc2_hi.latch);\n   if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,\"* Reg de2 e=%h !=00\",dut.reg_file_.b2v_latch_de2_lo.latch);\n   if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,\"* Reg de2 d=%h !=00\",dut.reg_file_.b2v_latch_de2_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,\"* Reg hl2 l=%h !=00\",dut.reg_file_.b2v_latch_hl2_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,\"* Reg hl2 h=%h !=00\",dut.reg_file_.b2v_latch_hl2_hi.latch);\n   if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,\"* Reg ix x=%h !=00\",dut.reg_file_.b2v_latch_ix_lo.latch);\n   if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,\"* Reg ix i=%h !=00\",dut.reg_file_.b2v_latch_ix_hi.latch);\n   if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,\"* Reg iy y=%h !=00\",dut.reg_file_.b2v_latch_iy_lo.latch);\n   if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,\"* Reg iy i=%h !=00\",dut.reg_file_.b2v_latch_iy_hi.latch);\n   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,\"* Reg sp p=%h !=00\",dut.reg_file_.b2v_latch_sp_lo.latch);\n   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,\"* Reg sp s=%h !=00\",dut.reg_file_.b2v_latch_sp_hi.latch);\n   if (pc!==16'h0001) $fdisplay(f,\"* PC=%h !=0001\",pc);\n   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,\"* Reg ir r=%h !=01\",dut.reg_file_.b2v_latch_ir_lo.latch);\n   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,\"* Reg ir i=%h !=00\",dut.reg_file_.b2v_latch_ir_hi.latch);\n#1 // End opcode\n\n   force dut.ir_.ctl_ir_we=1;\n   force dut.ir_.db=0;\n#2 release dut.ir_.ctl_ir_we;\n   release dut.ir_.db;\n   $fdisplay(f,\"Testing opcode cb41    BIT 0,C\");\n   // Preset af\n   force dut.reg_file_.b2v_latch_af_lo.we=1;\n   force dut.reg_file_.b2v_latch_af_hi.we=1;\n   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af_hi.db=8'h9e;\n#2 release dut.reg_file_.b2v_latch_af_lo.we;\n   release dut.reg_file_.b2v_latch_af_hi.we;\n   release dut.reg_file_.b2v_latch_af_lo.db;\n   release dut.reg_file_.b2v_latch_af_hi.db;\n   // Preset bc\n   force dut.reg_file_.b2v_latch_bc_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc_lo.db=8'h43;\n   force dut.reg_file_.b2v_latch_bc_hi.db=8'h1b;\n#2 release dut.reg_file_.b2v_latch_bc_lo.we;\n   release dut.reg_file_.b2v_latch_bc_hi.we;\n   release dut.reg_file_.b2v_latch_bc_lo.db;\n   release dut.reg_file_.b2v_latch_bc_hi.db;\n   // Preset de\n   force dut.reg_file_.b2v_latch_de_lo.we=1;\n   force dut.reg_file_.b2v_latch_de_hi.we=1;\n   force dut.reg_file_.b2v_latch_de_lo.db=8'h4e;\n   force dut.reg_file_.b2v_latch_de_hi.db=8'h95;\n#2 release dut.reg_file_.b2v_latch_de_lo.we;\n   release dut.reg_file_.b2v_latch_de_hi.we;\n   release dut.reg_file_.b2v_latch_de_lo.db;\n   release dut.reg_file_.b2v_latch_de_hi.db;\n   // Preset hl\n   force dut.reg_file_.b2v_latch_hl_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl_lo.db=8'he9;\n   force dut.reg_file_.b2v_latch_hl_hi.db=8'h7b;\n#2 release dut.reg_file_.b2v_latch_hl_lo.we;\n   release dut.reg_file_.b2v_latch_hl_hi.we;\n   release dut.reg_file_.b2v_latch_hl_lo.db;\n   release dut.reg_file_.b2v_latch_hl_hi.db;\n   // Preset af2\n   force dut.reg_file_.b2v_latch_af2_lo.we=1;\n   force dut.reg_file_.b2v_latch_af2_hi.we=1;\n   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_af2_lo.we;\n   release dut.reg_file_.b2v_latch_af2_hi.we;\n   release dut.reg_file_.b2v_latch_af2_lo.db;\n   release dut.reg_file_.b2v_latch_af2_hi.db;\n   // Preset bc2\n   force dut.reg_file_.b2v_latch_bc2_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc2_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_bc2_lo.we;\n   release dut.reg_file_.b2v_latch_bc2_hi.we;\n   release dut.reg_file_.b2v_latch_bc2_lo.db;\n   release dut.reg_file_.b2v_latch_bc2_hi.db;\n   // Preset de2\n   force dut.reg_file_.b2v_latch_de2_lo.we=1;\n   force dut.reg_file_.b2v_latch_de2_hi.we=1;\n   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_de2_lo.we;\n   release dut.reg_file_.b2v_latch_de2_hi.we;\n   release dut.reg_file_.b2v_latch_de2_lo.db;\n   release dut.reg_file_.b2v_latch_de2_hi.db;\n   // Preset hl2\n   force dut.reg_file_.b2v_latch_hl2_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl2_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_hl2_lo.we;\n   release dut.reg_file_.b2v_latch_hl2_hi.we;\n   release dut.reg_file_.b2v_latch_hl2_lo.db;\n   release dut.reg_file_.b2v_latch_hl2_hi.db;\n   // Preset ix\n   force dut.reg_file_.b2v_latch_ix_lo.we=1;\n   force dut.reg_file_.b2v_latch_ix_hi.we=1;\n   force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ix_lo.we;\n   release dut.reg_file_.b2v_latch_ix_hi.we;\n   release dut.reg_file_.b2v_latch_ix_lo.db;\n   release dut.reg_file_.b2v_latch_ix_hi.db;\n   // Preset iy\n   force dut.reg_file_.b2v_latch_iy_lo.we=1;\n   force dut.reg_file_.b2v_latch_iy_hi.we=1;\n   force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_iy_lo.we;\n   release dut.reg_file_.b2v_latch_iy_hi.we;\n   release dut.reg_file_.b2v_latch_iy_lo.db;\n   release dut.reg_file_.b2v_latch_iy_hi.db;\n   // Preset sp\n   force dut.reg_file_.b2v_latch_sp_lo.we=1;\n   force dut.reg_file_.b2v_latch_sp_hi.we=1;\n   force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_sp_lo.we;\n   release dut.reg_file_.b2v_latch_sp_hi.we;\n   release dut.reg_file_.b2v_latch_sp_lo.db;\n   release dut.reg_file_.b2v_latch_sp_hi.db;\n   // Preset wz\n   force dut.reg_file_.b2v_latch_wz_lo.we=1;\n   force dut.reg_file_.b2v_latch_wz_hi.we=1;\n   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_wz_lo.we;\n   release dut.reg_file_.b2v_latch_wz_hi.we;\n   release dut.reg_file_.b2v_latch_wz_lo.db;\n   release dut.reg_file_.b2v_latch_wz_hi.db;\n   // Preset pc\n   force dut.reg_file_.b2v_latch_pc_lo.we=1;\n   force dut.reg_file_.b2v_latch_pc_hi.we=1;\n   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_pc_lo.we;\n   release dut.reg_file_.b2v_latch_pc_hi.we;\n   release dut.reg_file_.b2v_latch_pc_lo.db;\n   release dut.reg_file_.b2v_latch_pc_hi.db;\n   // Preset ir\n   force dut.reg_file_.b2v_latch_ir_lo.we=1;\n   force dut.reg_file_.b2v_latch_ir_hi.we=1;\n   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ir_lo.we;\n   release dut.reg_file_.b2v_latch_ir_hi.we;\n   release dut.reg_file_.b2v_latch_ir_lo.db;\n   release dut.reg_file_.b2v_latch_ir_hi.db;\n   // Preset memory\n   ram.Mem[0] = 8'hcb;\n   ram.Mem[1] = 8'h41;\n   // Preset memory\n   ram.Mem[31721] = 8'hf7;\n   force dut.z80_top_ifc_n.fpga_reset=0;\n   force dut.address_latch_.Q=16'h0000;\n   release dut.reg_control_.ctl_reg_sys_we;\n   release dut.reg_file_.reg_gp_we;\n#2 // Execute: M1/T1 start\n#1 release dut.address_latch_.Q;\n#1\n#14 // Wait for opcode end\n   force dut.reg_control_.ctl_reg_sys_we=0;\n#2 pc=z.A;\n#2\n#1 force dut.reg_file_.reg_gp_we=0;\n   force dut.z80_top_ifc_n.fpga_reset=1;\n   if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h10) $fdisplay(f,\"* Reg af f=%h !=10\",dut.reg_file_.b2v_latch_af_lo.latch);\n   if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h9e) $fdisplay(f,\"* Reg af a=%h !=9e\",dut.reg_file_.b2v_latch_af_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h43) $fdisplay(f,\"* Reg bc c=%h !=43\",dut.reg_file_.b2v_latch_bc_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h1b) $fdisplay(f,\"* Reg bc b=%h !=1b\",dut.reg_file_.b2v_latch_bc_hi.latch);\n   if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h4e) $fdisplay(f,\"* Reg de e=%h !=4e\",dut.reg_file_.b2v_latch_de_lo.latch);\n   if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h95) $fdisplay(f,\"* Reg de d=%h !=95\",dut.reg_file_.b2v_latch_de_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'he9) $fdisplay(f,\"* Reg hl l=%h !=e9\",dut.reg_file_.b2v_latch_hl_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h7b) $fdisplay(f,\"* Reg hl h=%h !=7b\",dut.reg_file_.b2v_latch_hl_hi.latch);\n   if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,\"* Reg af2 f=%h !=00\",dut.reg_file_.b2v_latch_af2_lo.latch);\n   if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,\"* Reg af2 a=%h !=00\",dut.reg_file_.b2v_latch_af2_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,\"* Reg bc2 c=%h !=00\",dut.reg_file_.b2v_latch_bc2_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,\"* Reg bc2 b=%h !=00\",dut.reg_file_.b2v_latch_bc2_hi.latch);\n   if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,\"* Reg de2 e=%h !=00\",dut.reg_file_.b2v_latch_de2_lo.latch);\n   if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,\"* Reg de2 d=%h !=00\",dut.reg_file_.b2v_latch_de2_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,\"* Reg hl2 l=%h !=00\",dut.reg_file_.b2v_latch_hl2_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,\"* Reg hl2 h=%h !=00\",dut.reg_file_.b2v_latch_hl2_hi.latch);\n   if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,\"* Reg ix x=%h !=00\",dut.reg_file_.b2v_latch_ix_lo.latch);\n   if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,\"* Reg ix i=%h !=00\",dut.reg_file_.b2v_latch_ix_hi.latch);\n   if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,\"* Reg iy y=%h !=00\",dut.reg_file_.b2v_latch_iy_lo.latch);\n   if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,\"* Reg iy i=%h !=00\",dut.reg_file_.b2v_latch_iy_hi.latch);\n   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,\"* Reg sp p=%h !=00\",dut.reg_file_.b2v_latch_sp_lo.latch);\n   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,\"* Reg sp s=%h !=00\",dut.reg_file_.b2v_latch_sp_hi.latch);\n   if (pc!==16'h0002) $fdisplay(f,\"* PC=%h !=0002\",pc);\n   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,\"* Reg ir r=%h !=02\",dut.reg_file_.b2v_latch_ir_lo.latch);\n   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,\"* Reg ir i=%h !=00\",dut.reg_file_.b2v_latch_ir_hi.latch);\n#1 // End opcode\n\n   force dut.ir_.ctl_ir_we=1;\n   force dut.ir_.db=0;\n#2 release dut.ir_.ctl_ir_we;\n   release dut.ir_.db;\n   $fdisplay(f,\"Testing opcode cb93    RES 2,E\");\n   // Preset af\n   force dut.reg_file_.b2v_latch_af_lo.we=1;\n   force dut.reg_file_.b2v_latch_af_hi.we=1;\n   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af_hi.db=8'hc2;\n#2 release dut.reg_file_.b2v_latch_af_lo.we;\n   release dut.reg_file_.b2v_latch_af_hi.we;\n   release dut.reg_file_.b2v_latch_af_lo.db;\n   release dut.reg_file_.b2v_latch_af_hi.db;\n   // Preset bc\n   force dut.reg_file_.b2v_latch_bc_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc_lo.db=8'h05;\n   force dut.reg_file_.b2v_latch_bc_hi.db=8'h4e;\n#2 release dut.reg_file_.b2v_latch_bc_lo.we;\n   release dut.reg_file_.b2v_latch_bc_hi.we;\n   release dut.reg_file_.b2v_latch_bc_lo.db;\n   release dut.reg_file_.b2v_latch_bc_hi.db;\n   // Preset de\n   force dut.reg_file_.b2v_latch_de_lo.we=1;\n   force dut.reg_file_.b2v_latch_de_hi.we=1;\n   force dut.reg_file_.b2v_latch_de_lo.db=8'hf8;\n   force dut.reg_file_.b2v_latch_de_hi.db=8'hb3;\n#2 release dut.reg_file_.b2v_latch_de_lo.we;\n   release dut.reg_file_.b2v_latch_de_hi.we;\n   release dut.reg_file_.b2v_latch_de_lo.db;\n   release dut.reg_file_.b2v_latch_de_hi.db;\n   // Preset hl\n   force dut.reg_file_.b2v_latch_hl_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl_lo.db=8'h34;\n   force dut.reg_file_.b2v_latch_hl_hi.db=8'h22;\n#2 release dut.reg_file_.b2v_latch_hl_lo.we;\n   release dut.reg_file_.b2v_latch_hl_hi.we;\n   release dut.reg_file_.b2v_latch_hl_lo.db;\n   release dut.reg_file_.b2v_latch_hl_hi.db;\n   // Preset af2\n   force dut.reg_file_.b2v_latch_af2_lo.we=1;\n   force dut.reg_file_.b2v_latch_af2_hi.we=1;\n   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_af2_lo.we;\n   release dut.reg_file_.b2v_latch_af2_hi.we;\n   release dut.reg_file_.b2v_latch_af2_lo.db;\n   release dut.reg_file_.b2v_latch_af2_hi.db;\n   // Preset bc2\n   force dut.reg_file_.b2v_latch_bc2_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc2_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_bc2_lo.we;\n   release dut.reg_file_.b2v_latch_bc2_hi.we;\n   release dut.reg_file_.b2v_latch_bc2_lo.db;\n   release dut.reg_file_.b2v_latch_bc2_hi.db;\n   // Preset de2\n   force dut.reg_file_.b2v_latch_de2_lo.we=1;\n   force dut.reg_file_.b2v_latch_de2_hi.we=1;\n   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_de2_lo.we;\n   release dut.reg_file_.b2v_latch_de2_hi.we;\n   release dut.reg_file_.b2v_latch_de2_lo.db;\n   release dut.reg_file_.b2v_latch_de2_hi.db;\n   // Preset hl2\n   force dut.reg_file_.b2v_latch_hl2_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl2_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_hl2_lo.we;\n   release dut.reg_file_.b2v_latch_hl2_hi.we;\n   release dut.reg_file_.b2v_latch_hl2_lo.db;\n   release dut.reg_file_.b2v_latch_hl2_hi.db;\n   // Preset ix\n   force dut.reg_file_.b2v_latch_ix_lo.we=1;\n   force dut.reg_file_.b2v_latch_ix_hi.we=1;\n   force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ix_lo.we;\n   release dut.reg_file_.b2v_latch_ix_hi.we;\n   release dut.reg_file_.b2v_latch_ix_lo.db;\n   release dut.reg_file_.b2v_latch_ix_hi.db;\n   // Preset iy\n   force dut.reg_file_.b2v_latch_iy_lo.we=1;\n   force dut.reg_file_.b2v_latch_iy_hi.we=1;\n   force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_iy_lo.we;\n   release dut.reg_file_.b2v_latch_iy_hi.we;\n   release dut.reg_file_.b2v_latch_iy_lo.db;\n   release dut.reg_file_.b2v_latch_iy_hi.db;\n   // Preset sp\n   force dut.reg_file_.b2v_latch_sp_lo.we=1;\n   force dut.reg_file_.b2v_latch_sp_hi.we=1;\n   force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_sp_lo.we;\n   release dut.reg_file_.b2v_latch_sp_hi.we;\n   release dut.reg_file_.b2v_latch_sp_lo.db;\n   release dut.reg_file_.b2v_latch_sp_hi.db;\n   // Preset wz\n   force dut.reg_file_.b2v_latch_wz_lo.we=1;\n   force dut.reg_file_.b2v_latch_wz_hi.we=1;\n   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_wz_lo.we;\n   release dut.reg_file_.b2v_latch_wz_hi.we;\n   release dut.reg_file_.b2v_latch_wz_lo.db;\n   release dut.reg_file_.b2v_latch_wz_hi.db;\n   // Preset pc\n   force dut.reg_file_.b2v_latch_pc_lo.we=1;\n   force dut.reg_file_.b2v_latch_pc_hi.we=1;\n   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_pc_lo.we;\n   release dut.reg_file_.b2v_latch_pc_hi.we;\n   release dut.reg_file_.b2v_latch_pc_lo.db;\n   release dut.reg_file_.b2v_latch_pc_hi.db;\n   // Preset ir\n   force dut.reg_file_.b2v_latch_ir_lo.we=1;\n   force dut.reg_file_.b2v_latch_ir_hi.we=1;\n   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ir_lo.we;\n   release dut.reg_file_.b2v_latch_ir_hi.we;\n   release dut.reg_file_.b2v_latch_ir_lo.db;\n   release dut.reg_file_.b2v_latch_ir_hi.db;\n   // Preset memory\n   ram.Mem[0] = 8'hcb;\n   ram.Mem[1] = 8'h93;\n   // Preset memory\n   ram.Mem[8756] = 8'ha0;\n   force dut.z80_top_ifc_n.fpga_reset=0;\n   force dut.address_latch_.Q=16'h0000;\n   release dut.reg_control_.ctl_reg_sys_we;\n   release dut.reg_file_.reg_gp_we;\n#2 // Execute: M1/T1 start\n#1 release dut.address_latch_.Q;\n#1\n#14 // Wait for opcode end\n   force dut.reg_control_.ctl_reg_sys_we=0;\n#2 pc=z.A;\n#2\n#1 force dut.reg_file_.reg_gp_we=0;\n   force dut.z80_top_ifc_n.fpga_reset=1;\n   if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h00) $fdisplay(f,\"* Reg af f=%h !=00\",dut.reg_file_.b2v_latch_af_lo.latch);\n   if (dut.reg_file_.b2v_latch_af_hi.latch!==8'hc2) $fdisplay(f,\"* Reg af a=%h !=c2\",dut.reg_file_.b2v_latch_af_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h05) $fdisplay(f,\"* Reg bc c=%h !=05\",dut.reg_file_.b2v_latch_bc_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h4e) $fdisplay(f,\"* Reg bc b=%h !=4e\",dut.reg_file_.b2v_latch_bc_hi.latch);\n   if (dut.reg_file_.b2v_latch_de_lo.latch!==8'hf8) $fdisplay(f,\"* Reg de e=%h !=f8\",dut.reg_file_.b2v_latch_de_lo.latch);\n   if (dut.reg_file_.b2v_latch_de_hi.latch!==8'hb3) $fdisplay(f,\"* Reg de d=%h !=b3\",dut.reg_file_.b2v_latch_de_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h34) $fdisplay(f,\"* Reg hl l=%h !=34\",dut.reg_file_.b2v_latch_hl_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h22) $fdisplay(f,\"* Reg hl h=%h !=22\",dut.reg_file_.b2v_latch_hl_hi.latch);\n   if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,\"* Reg af2 f=%h !=00\",dut.reg_file_.b2v_latch_af2_lo.latch);\n   if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,\"* Reg af2 a=%h !=00\",dut.reg_file_.b2v_latch_af2_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,\"* Reg bc2 c=%h !=00\",dut.reg_file_.b2v_latch_bc2_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,\"* Reg bc2 b=%h !=00\",dut.reg_file_.b2v_latch_bc2_hi.latch);\n   if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,\"* Reg de2 e=%h !=00\",dut.reg_file_.b2v_latch_de2_lo.latch);\n   if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,\"* Reg de2 d=%h !=00\",dut.reg_file_.b2v_latch_de2_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,\"* Reg hl2 l=%h !=00\",dut.reg_file_.b2v_latch_hl2_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,\"* Reg hl2 h=%h !=00\",dut.reg_file_.b2v_latch_hl2_hi.latch);\n   if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,\"* Reg ix x=%h !=00\",dut.reg_file_.b2v_latch_ix_lo.latch);\n   if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,\"* Reg ix i=%h !=00\",dut.reg_file_.b2v_latch_ix_hi.latch);\n   if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,\"* Reg iy y=%h !=00\",dut.reg_file_.b2v_latch_iy_lo.latch);\n   if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,\"* Reg iy i=%h !=00\",dut.reg_file_.b2v_latch_iy_hi.latch);\n   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,\"* Reg sp p=%h !=00\",dut.reg_file_.b2v_latch_sp_lo.latch);\n   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,\"* Reg sp s=%h !=00\",dut.reg_file_.b2v_latch_sp_hi.latch);\n   if (pc!==16'h0002) $fdisplay(f,\"* PC=%h !=0002\",pc);\n   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,\"* Reg ir r=%h !=02\",dut.reg_file_.b2v_latch_ir_lo.latch);\n   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,\"* Reg ir i=%h !=00\",dut.reg_file_.b2v_latch_ir_hi.latch);\n#1 // End opcode\n\n   force dut.ir_.ctl_ir_we=1;\n   force dut.ir_.db=0;\n#2 release dut.ir_.ctl_ir_we;\n   release dut.ir_.db;\n   $fdisplay(f,\"Testing opcode cbe5    SET 4,L\");\n   // Preset af\n   force dut.reg_file_.b2v_latch_af_lo.we=1;\n   force dut.reg_file_.b2v_latch_af_hi.we=1;\n   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af_hi.db=8'hca;\n#2 release dut.reg_file_.b2v_latch_af_lo.we;\n   release dut.reg_file_.b2v_latch_af_hi.we;\n   release dut.reg_file_.b2v_latch_af_lo.db;\n   release dut.reg_file_.b2v_latch_af_hi.db;\n   // Preset bc\n   force dut.reg_file_.b2v_latch_bc_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc_lo.db=8'h0d;\n   force dut.reg_file_.b2v_latch_bc_hi.db=8'hdf;\n#2 release dut.reg_file_.b2v_latch_bc_lo.we;\n   release dut.reg_file_.b2v_latch_bc_hi.we;\n   release dut.reg_file_.b2v_latch_bc_lo.db;\n   release dut.reg_file_.b2v_latch_bc_hi.db;\n   // Preset de\n   force dut.reg_file_.b2v_latch_de_lo.we=1;\n   force dut.reg_file_.b2v_latch_de_hi.we=1;\n   force dut.reg_file_.b2v_latch_de_lo.db=8'h88;\n   force dut.reg_file_.b2v_latch_de_hi.db=8'hd5;\n#2 release dut.reg_file_.b2v_latch_de_lo.we;\n   release dut.reg_file_.b2v_latch_de_hi.we;\n   release dut.reg_file_.b2v_latch_de_lo.db;\n   release dut.reg_file_.b2v_latch_de_hi.db;\n   // Preset hl\n   force dut.reg_file_.b2v_latch_hl_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl_lo.db=8'h8f;\n   force dut.reg_file_.b2v_latch_hl_hi.db=8'hb4;\n#2 release dut.reg_file_.b2v_latch_hl_lo.we;\n   release dut.reg_file_.b2v_latch_hl_hi.we;\n   release dut.reg_file_.b2v_latch_hl_lo.db;\n   release dut.reg_file_.b2v_latch_hl_hi.db;\n   // Preset af2\n   force dut.reg_file_.b2v_latch_af2_lo.we=1;\n   force dut.reg_file_.b2v_latch_af2_hi.we=1;\n   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_af2_lo.we;\n   release dut.reg_file_.b2v_latch_af2_hi.we;\n   release dut.reg_file_.b2v_latch_af2_lo.db;\n   release dut.reg_file_.b2v_latch_af2_hi.db;\n   // Preset bc2\n   force dut.reg_file_.b2v_latch_bc2_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc2_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_bc2_lo.we;\n   release dut.reg_file_.b2v_latch_bc2_hi.we;\n   release dut.reg_file_.b2v_latch_bc2_lo.db;\n   release dut.reg_file_.b2v_latch_bc2_hi.db;\n   // Preset de2\n   force dut.reg_file_.b2v_latch_de2_lo.we=1;\n   force dut.reg_file_.b2v_latch_de2_hi.we=1;\n   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_de2_lo.we;\n   release dut.reg_file_.b2v_latch_de2_hi.we;\n   release dut.reg_file_.b2v_latch_de2_lo.db;\n   release dut.reg_file_.b2v_latch_de2_hi.db;\n   // Preset hl2\n   force dut.reg_file_.b2v_latch_hl2_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl2_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_hl2_lo.we;\n   release dut.reg_file_.b2v_latch_hl2_hi.we;\n   release dut.reg_file_.b2v_latch_hl2_lo.db;\n   release dut.reg_file_.b2v_latch_hl2_hi.db;\n   // Preset ix\n   force dut.reg_file_.b2v_latch_ix_lo.we=1;\n   force dut.reg_file_.b2v_latch_ix_hi.we=1;\n   force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ix_lo.we;\n   release dut.reg_file_.b2v_latch_ix_hi.we;\n   release dut.reg_file_.b2v_latch_ix_lo.db;\n   release dut.reg_file_.b2v_latch_ix_hi.db;\n   // Preset iy\n   force dut.reg_file_.b2v_latch_iy_lo.we=1;\n   force dut.reg_file_.b2v_latch_iy_hi.we=1;\n   force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_iy_lo.we;\n   release dut.reg_file_.b2v_latch_iy_hi.we;\n   release dut.reg_file_.b2v_latch_iy_lo.db;\n   release dut.reg_file_.b2v_latch_iy_hi.db;\n   // Preset sp\n   force dut.reg_file_.b2v_latch_sp_lo.we=1;\n   force dut.reg_file_.b2v_latch_sp_hi.we=1;\n   force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_sp_lo.we;\n   release dut.reg_file_.b2v_latch_sp_hi.we;\n   release dut.reg_file_.b2v_latch_sp_lo.db;\n   release dut.reg_file_.b2v_latch_sp_hi.db;\n   // Preset wz\n   force dut.reg_file_.b2v_latch_wz_lo.we=1;\n   force dut.reg_file_.b2v_latch_wz_hi.we=1;\n   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_wz_lo.we;\n   release dut.reg_file_.b2v_latch_wz_hi.we;\n   release dut.reg_file_.b2v_latch_wz_lo.db;\n   release dut.reg_file_.b2v_latch_wz_hi.db;\n   // Preset pc\n   force dut.reg_file_.b2v_latch_pc_lo.we=1;\n   force dut.reg_file_.b2v_latch_pc_hi.we=1;\n   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_pc_lo.we;\n   release dut.reg_file_.b2v_latch_pc_hi.we;\n   release dut.reg_file_.b2v_latch_pc_lo.db;\n   release dut.reg_file_.b2v_latch_pc_hi.db;\n   // Preset ir\n   force dut.reg_file_.b2v_latch_ir_lo.we=1;\n   force dut.reg_file_.b2v_latch_ir_hi.we=1;\n   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ir_lo.we;\n   release dut.reg_file_.b2v_latch_ir_hi.we;\n   release dut.reg_file_.b2v_latch_ir_lo.db;\n   release dut.reg_file_.b2v_latch_ir_hi.db;\n   // Preset memory\n   ram.Mem[0] = 8'hcb;\n   ram.Mem[1] = 8'he5;\n   // Preset memory\n   ram.Mem[46223] = 8'hcf;\n   force dut.z80_top_ifc_n.fpga_reset=0;\n   force dut.address_latch_.Q=16'h0000;\n   release dut.reg_control_.ctl_reg_sys_we;\n   release dut.reg_file_.reg_gp_we;\n#2 // Execute: M1/T1 start\n#1 release dut.address_latch_.Q;\n#1\n#14 // Wait for opcode end\n   force dut.reg_control_.ctl_reg_sys_we=0;\n#2 pc=z.A;\n#2\n#1 force dut.reg_file_.reg_gp_we=0;\n   force dut.z80_top_ifc_n.fpga_reset=1;\n   if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h00) $fdisplay(f,\"* Reg af f=%h !=00\",dut.reg_file_.b2v_latch_af_lo.latch);\n   if (dut.reg_file_.b2v_latch_af_hi.latch!==8'hca) $fdisplay(f,\"* Reg af a=%h !=ca\",dut.reg_file_.b2v_latch_af_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h0d) $fdisplay(f,\"* Reg bc c=%h !=0d\",dut.reg_file_.b2v_latch_bc_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'hdf) $fdisplay(f,\"* Reg bc b=%h !=df\",dut.reg_file_.b2v_latch_bc_hi.latch);\n   if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h88) $fdisplay(f,\"* Reg de e=%h !=88\",dut.reg_file_.b2v_latch_de_lo.latch);\n   if (dut.reg_file_.b2v_latch_de_hi.latch!==8'hd5) $fdisplay(f,\"* Reg de d=%h !=d5\",dut.reg_file_.b2v_latch_de_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h9f) $fdisplay(f,\"* Reg hl l=%h !=9f\",dut.reg_file_.b2v_latch_hl_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hb4) $fdisplay(f,\"* Reg hl h=%h !=b4\",dut.reg_file_.b2v_latch_hl_hi.latch);\n   if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,\"* Reg af2 f=%h !=00\",dut.reg_file_.b2v_latch_af2_lo.latch);\n   if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,\"* Reg af2 a=%h !=00\",dut.reg_file_.b2v_latch_af2_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,\"* Reg bc2 c=%h !=00\",dut.reg_file_.b2v_latch_bc2_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,\"* Reg bc2 b=%h !=00\",dut.reg_file_.b2v_latch_bc2_hi.latch);\n   if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,\"* Reg de2 e=%h !=00\",dut.reg_file_.b2v_latch_de2_lo.latch);\n   if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,\"* Reg de2 d=%h !=00\",dut.reg_file_.b2v_latch_de2_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,\"* Reg hl2 l=%h !=00\",dut.reg_file_.b2v_latch_hl2_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,\"* Reg hl2 h=%h !=00\",dut.reg_file_.b2v_latch_hl2_hi.latch);\n   if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,\"* Reg ix x=%h !=00\",dut.reg_file_.b2v_latch_ix_lo.latch);\n   if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,\"* Reg ix i=%h !=00\",dut.reg_file_.b2v_latch_ix_hi.latch);\n   if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,\"* Reg iy y=%h !=00\",dut.reg_file_.b2v_latch_iy_lo.latch);\n   if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,\"* Reg iy i=%h !=00\",dut.reg_file_.b2v_latch_iy_hi.latch);\n   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,\"* Reg sp p=%h !=00\",dut.reg_file_.b2v_latch_sp_lo.latch);\n   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,\"* Reg sp s=%h !=00\",dut.reg_file_.b2v_latch_sp_hi.latch);\n   if (pc!==16'h0002) $fdisplay(f,\"* PC=%h !=0002\",pc);\n   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,\"* Reg ir r=%h !=02\",dut.reg_file_.b2v_latch_ir_lo.latch);\n   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,\"* Reg ir i=%h !=00\",dut.reg_file_.b2v_latch_ir_hi.latch);\n#1 // End opcode\n\n   force dut.ir_.ctl_ir_we=1;\n   force dut.ir_.db=0;\n#2 release dut.ir_.ctl_ir_we;\n   release dut.ir_.db;\n   $fdisplay(f,\"Testing opcode 8c      ADC A,H\");\n   // Preset af\n   force dut.reg_file_.b2v_latch_af_lo.we=1;\n   force dut.reg_file_.b2v_latch_af_hi.we=1;\n   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af_hi.db=8'hf5;\n#2 release dut.reg_file_.b2v_latch_af_lo.we;\n   release dut.reg_file_.b2v_latch_af_hi.we;\n   release dut.reg_file_.b2v_latch_af_lo.db;\n   release dut.reg_file_.b2v_latch_af_hi.db;\n   // Preset bc\n   force dut.reg_file_.b2v_latch_bc_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc_lo.db=8'h3b;\n   force dut.reg_file_.b2v_latch_bc_hi.db=8'h0f;\n#2 release dut.reg_file_.b2v_latch_bc_lo.we;\n   release dut.reg_file_.b2v_latch_bc_hi.we;\n   release dut.reg_file_.b2v_latch_bc_lo.db;\n   release dut.reg_file_.b2v_latch_bc_hi.db;\n   // Preset de\n   force dut.reg_file_.b2v_latch_de_lo.we=1;\n   force dut.reg_file_.b2v_latch_de_hi.we=1;\n   force dut.reg_file_.b2v_latch_de_lo.db=8'h0d;\n   force dut.reg_file_.b2v_latch_de_hi.db=8'h20;\n#2 release dut.reg_file_.b2v_latch_de_lo.we;\n   release dut.reg_file_.b2v_latch_de_hi.we;\n   release dut.reg_file_.b2v_latch_de_lo.db;\n   release dut.reg_file_.b2v_latch_de_hi.db;\n   // Preset hl\n   force dut.reg_file_.b2v_latch_hl_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl_lo.db=8'ha6;\n   force dut.reg_file_.b2v_latch_hl_hi.db=8'hdc;\n#2 release dut.reg_file_.b2v_latch_hl_lo.we;\n   release dut.reg_file_.b2v_latch_hl_hi.we;\n   release dut.reg_file_.b2v_latch_hl_lo.db;\n   release dut.reg_file_.b2v_latch_hl_hi.db;\n   // Preset af2\n   force dut.reg_file_.b2v_latch_af2_lo.we=1;\n   force dut.reg_file_.b2v_latch_af2_hi.we=1;\n   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_af2_lo.we;\n   release dut.reg_file_.b2v_latch_af2_hi.we;\n   release dut.reg_file_.b2v_latch_af2_lo.db;\n   release dut.reg_file_.b2v_latch_af2_hi.db;\n   // Preset bc2\n   force dut.reg_file_.b2v_latch_bc2_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc2_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_bc2_lo.we;\n   release dut.reg_file_.b2v_latch_bc2_hi.we;\n   release dut.reg_file_.b2v_latch_bc2_lo.db;\n   release dut.reg_file_.b2v_latch_bc2_hi.db;\n   // Preset de2\n   force dut.reg_file_.b2v_latch_de2_lo.we=1;\n   force dut.reg_file_.b2v_latch_de2_hi.we=1;\n   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_de2_lo.we;\n   release dut.reg_file_.b2v_latch_de2_hi.we;\n   release dut.reg_file_.b2v_latch_de2_lo.db;\n   release dut.reg_file_.b2v_latch_de2_hi.db;\n   // Preset hl2\n   force dut.reg_file_.b2v_latch_hl2_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl2_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_hl2_lo.we;\n   release dut.reg_file_.b2v_latch_hl2_hi.we;\n   release dut.reg_file_.b2v_latch_hl2_lo.db;\n   release dut.reg_file_.b2v_latch_hl2_hi.db;\n   // Preset ix\n   force dut.reg_file_.b2v_latch_ix_lo.we=1;\n   force dut.reg_file_.b2v_latch_ix_hi.we=1;\n   force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ix_lo.we;\n   release dut.reg_file_.b2v_latch_ix_hi.we;\n   release dut.reg_file_.b2v_latch_ix_lo.db;\n   release dut.reg_file_.b2v_latch_ix_hi.db;\n   // Preset iy\n   force dut.reg_file_.b2v_latch_iy_lo.we=1;\n   force dut.reg_file_.b2v_latch_iy_hi.we=1;\n   force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_iy_lo.we;\n   release dut.reg_file_.b2v_latch_iy_hi.we;\n   release dut.reg_file_.b2v_latch_iy_lo.db;\n   release dut.reg_file_.b2v_latch_iy_hi.db;\n   // Preset sp\n   force dut.reg_file_.b2v_latch_sp_lo.we=1;\n   force dut.reg_file_.b2v_latch_sp_hi.we=1;\n   force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_sp_lo.we;\n   release dut.reg_file_.b2v_latch_sp_hi.we;\n   release dut.reg_file_.b2v_latch_sp_lo.db;\n   release dut.reg_file_.b2v_latch_sp_hi.db;\n   // Preset wz\n   force dut.reg_file_.b2v_latch_wz_lo.we=1;\n   force dut.reg_file_.b2v_latch_wz_hi.we=1;\n   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_wz_lo.we;\n   release dut.reg_file_.b2v_latch_wz_hi.we;\n   release dut.reg_file_.b2v_latch_wz_lo.db;\n   release dut.reg_file_.b2v_latch_wz_hi.db;\n   // Preset pc\n   force dut.reg_file_.b2v_latch_pc_lo.we=1;\n   force dut.reg_file_.b2v_latch_pc_hi.we=1;\n   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_pc_lo.we;\n   release dut.reg_file_.b2v_latch_pc_hi.we;\n   release dut.reg_file_.b2v_latch_pc_lo.db;\n   release dut.reg_file_.b2v_latch_pc_hi.db;\n   // Preset ir\n   force dut.reg_file_.b2v_latch_ir_lo.we=1;\n   force dut.reg_file_.b2v_latch_ir_hi.we=1;\n   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ir_lo.we;\n   release dut.reg_file_.b2v_latch_ir_hi.we;\n   release dut.reg_file_.b2v_latch_ir_lo.db;\n   release dut.reg_file_.b2v_latch_ir_hi.db;\n   // Preset memory\n   ram.Mem[0] = 8'h8c;\n   // Preset memory\n   ram.Mem[56486] = 8'h49;\n   force dut.z80_top_ifc_n.fpga_reset=0;\n   force dut.address_latch_.Q=16'h0000;\n   release dut.reg_control_.ctl_reg_sys_we;\n   release dut.reg_file_.reg_gp_we;\n#2 // Execute: M1/T1 start\n#1 release dut.address_latch_.Q;\n#1\n#6 // Wait for opcode end\n   force dut.reg_control_.ctl_reg_sys_we=0;\n#2 pc=z.A;\n#2\n#1 force dut.reg_file_.reg_gp_we=0;\n   force dut.z80_top_ifc_n.fpga_reset=1;\n   if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h91) $fdisplay(f,\"* Reg af f=%h !=91\",dut.reg_file_.b2v_latch_af_lo.latch);\n   if (dut.reg_file_.b2v_latch_af_hi.latch!==8'hd1) $fdisplay(f,\"* Reg af a=%h !=d1\",dut.reg_file_.b2v_latch_af_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h3b) $fdisplay(f,\"* Reg bc c=%h !=3b\",dut.reg_file_.b2v_latch_bc_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h0f) $fdisplay(f,\"* Reg bc b=%h !=0f\",dut.reg_file_.b2v_latch_bc_hi.latch);\n   if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h0d) $fdisplay(f,\"* Reg de e=%h !=0d\",dut.reg_file_.b2v_latch_de_lo.latch);\n   if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h20) $fdisplay(f,\"* Reg de d=%h !=20\",dut.reg_file_.b2v_latch_de_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'ha6) $fdisplay(f,\"* Reg hl l=%h !=a6\",dut.reg_file_.b2v_latch_hl_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hdc) $fdisplay(f,\"* Reg hl h=%h !=dc\",dut.reg_file_.b2v_latch_hl_hi.latch);\n   if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,\"* Reg af2 f=%h !=00\",dut.reg_file_.b2v_latch_af2_lo.latch);\n   if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,\"* Reg af2 a=%h !=00\",dut.reg_file_.b2v_latch_af2_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,\"* Reg bc2 c=%h !=00\",dut.reg_file_.b2v_latch_bc2_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,\"* Reg bc2 b=%h !=00\",dut.reg_file_.b2v_latch_bc2_hi.latch);\n   if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,\"* Reg de2 e=%h !=00\",dut.reg_file_.b2v_latch_de2_lo.latch);\n   if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,\"* Reg de2 d=%h !=00\",dut.reg_file_.b2v_latch_de2_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,\"* Reg hl2 l=%h !=00\",dut.reg_file_.b2v_latch_hl2_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,\"* Reg hl2 h=%h !=00\",dut.reg_file_.b2v_latch_hl2_hi.latch);\n   if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,\"* Reg ix x=%h !=00\",dut.reg_file_.b2v_latch_ix_lo.latch);\n   if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,\"* Reg ix i=%h !=00\",dut.reg_file_.b2v_latch_ix_hi.latch);\n   if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,\"* Reg iy y=%h !=00\",dut.reg_file_.b2v_latch_iy_lo.latch);\n   if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,\"* Reg iy i=%h !=00\",dut.reg_file_.b2v_latch_iy_hi.latch);\n   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,\"* Reg sp p=%h !=00\",dut.reg_file_.b2v_latch_sp_lo.latch);\n   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,\"* Reg sp s=%h !=00\",dut.reg_file_.b2v_latch_sp_hi.latch);\n   if (pc!==16'h0001) $fdisplay(f,\"* PC=%h !=0001\",pc);\n   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,\"* Reg ir r=%h !=01\",dut.reg_file_.b2v_latch_ir_lo.latch);\n   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,\"* Reg ir i=%h !=00\",dut.reg_file_.b2v_latch_ir_hi.latch);\n#1 // End opcode\n\n   force dut.ir_.ctl_ir_we=1;\n   force dut.ir_.db=0;\n#2 release dut.ir_.ctl_ir_we;\n   release dut.ir_.db;\n   $fdisplay(f,\"Testing opcode 92      SUB D\");\n   // Preset af\n   force dut.reg_file_.b2v_latch_af_lo.we=1;\n   force dut.reg_file_.b2v_latch_af_hi.we=1;\n   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af_hi.db=8'hf5;\n#2 release dut.reg_file_.b2v_latch_af_lo.we;\n   release dut.reg_file_.b2v_latch_af_hi.we;\n   release dut.reg_file_.b2v_latch_af_lo.db;\n   release dut.reg_file_.b2v_latch_af_hi.db;\n   // Preset bc\n   force dut.reg_file_.b2v_latch_bc_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc_lo.db=8'h3b;\n   force dut.reg_file_.b2v_latch_bc_hi.db=8'h0f;\n#2 release dut.reg_file_.b2v_latch_bc_lo.we;\n   release dut.reg_file_.b2v_latch_bc_hi.we;\n   release dut.reg_file_.b2v_latch_bc_lo.db;\n   release dut.reg_file_.b2v_latch_bc_hi.db;\n   // Preset de\n   force dut.reg_file_.b2v_latch_de_lo.we=1;\n   force dut.reg_file_.b2v_latch_de_hi.we=1;\n   force dut.reg_file_.b2v_latch_de_lo.db=8'h0d;\n   force dut.reg_file_.b2v_latch_de_hi.db=8'h20;\n#2 release dut.reg_file_.b2v_latch_de_lo.we;\n   release dut.reg_file_.b2v_latch_de_hi.we;\n   release dut.reg_file_.b2v_latch_de_lo.db;\n   release dut.reg_file_.b2v_latch_de_hi.db;\n   // Preset hl\n   force dut.reg_file_.b2v_latch_hl_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl_lo.db=8'ha6;\n   force dut.reg_file_.b2v_latch_hl_hi.db=8'hdc;\n#2 release dut.reg_file_.b2v_latch_hl_lo.we;\n   release dut.reg_file_.b2v_latch_hl_hi.we;\n   release dut.reg_file_.b2v_latch_hl_lo.db;\n   release dut.reg_file_.b2v_latch_hl_hi.db;\n   // Preset af2\n   force dut.reg_file_.b2v_latch_af2_lo.we=1;\n   force dut.reg_file_.b2v_latch_af2_hi.we=1;\n   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_af2_lo.we;\n   release dut.reg_file_.b2v_latch_af2_hi.we;\n   release dut.reg_file_.b2v_latch_af2_lo.db;\n   release dut.reg_file_.b2v_latch_af2_hi.db;\n   // Preset bc2\n   force dut.reg_file_.b2v_latch_bc2_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc2_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_bc2_lo.we;\n   release dut.reg_file_.b2v_latch_bc2_hi.we;\n   release dut.reg_file_.b2v_latch_bc2_lo.db;\n   release dut.reg_file_.b2v_latch_bc2_hi.db;\n   // Preset de2\n   force dut.reg_file_.b2v_latch_de2_lo.we=1;\n   force dut.reg_file_.b2v_latch_de2_hi.we=1;\n   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_de2_lo.we;\n   release dut.reg_file_.b2v_latch_de2_hi.we;\n   release dut.reg_file_.b2v_latch_de2_lo.db;\n   release dut.reg_file_.b2v_latch_de2_hi.db;\n   // Preset hl2\n   force dut.reg_file_.b2v_latch_hl2_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl2_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_hl2_lo.we;\n   release dut.reg_file_.b2v_latch_hl2_hi.we;\n   release dut.reg_file_.b2v_latch_hl2_lo.db;\n   release dut.reg_file_.b2v_latch_hl2_hi.db;\n   // Preset ix\n   force dut.reg_file_.b2v_latch_ix_lo.we=1;\n   force dut.reg_file_.b2v_latch_ix_hi.we=1;\n   force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ix_lo.we;\n   release dut.reg_file_.b2v_latch_ix_hi.we;\n   release dut.reg_file_.b2v_latch_ix_lo.db;\n   release dut.reg_file_.b2v_latch_ix_hi.db;\n   // Preset iy\n   force dut.reg_file_.b2v_latch_iy_lo.we=1;\n   force dut.reg_file_.b2v_latch_iy_hi.we=1;\n   force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_iy_lo.we;\n   release dut.reg_file_.b2v_latch_iy_hi.we;\n   release dut.reg_file_.b2v_latch_iy_lo.db;\n   release dut.reg_file_.b2v_latch_iy_hi.db;\n   // Preset sp\n   force dut.reg_file_.b2v_latch_sp_lo.we=1;\n   force dut.reg_file_.b2v_latch_sp_hi.we=1;\n   force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_sp_lo.we;\n   release dut.reg_file_.b2v_latch_sp_hi.we;\n   release dut.reg_file_.b2v_latch_sp_lo.db;\n   release dut.reg_file_.b2v_latch_sp_hi.db;\n   // Preset wz\n   force dut.reg_file_.b2v_latch_wz_lo.we=1;\n   force dut.reg_file_.b2v_latch_wz_hi.we=1;\n   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_wz_lo.we;\n   release dut.reg_file_.b2v_latch_wz_hi.we;\n   release dut.reg_file_.b2v_latch_wz_lo.db;\n   release dut.reg_file_.b2v_latch_wz_hi.db;\n   // Preset pc\n   force dut.reg_file_.b2v_latch_pc_lo.we=1;\n   force dut.reg_file_.b2v_latch_pc_hi.we=1;\n   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_pc_lo.we;\n   release dut.reg_file_.b2v_latch_pc_hi.we;\n   release dut.reg_file_.b2v_latch_pc_lo.db;\n   release dut.reg_file_.b2v_latch_pc_hi.db;\n   // Preset ir\n   force dut.reg_file_.b2v_latch_ir_lo.we=1;\n   force dut.reg_file_.b2v_latch_ir_hi.we=1;\n   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ir_lo.we;\n   release dut.reg_file_.b2v_latch_ir_hi.we;\n   release dut.reg_file_.b2v_latch_ir_lo.db;\n   release dut.reg_file_.b2v_latch_ir_hi.db;\n   // Preset memory\n   ram.Mem[0] = 8'h92;\n   // Preset memory\n   ram.Mem[56486] = 8'h49;\n   force dut.z80_top_ifc_n.fpga_reset=0;\n   force dut.address_latch_.Q=16'h0000;\n   release dut.reg_control_.ctl_reg_sys_we;\n   release dut.reg_file_.reg_gp_we;\n#2 // Execute: M1/T1 start\n#1 release dut.address_latch_.Q;\n#1\n#6 // Wait for opcode end\n   force dut.reg_control_.ctl_reg_sys_we=0;\n#2 pc=z.A;\n#2\n#1 force dut.reg_file_.reg_gp_we=0;\n   force dut.z80_top_ifc_n.fpga_reset=1;\n   if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h82) $fdisplay(f,\"* Reg af f=%h !=82\",dut.reg_file_.b2v_latch_af_lo.latch);\n   if (dut.reg_file_.b2v_latch_af_hi.latch!==8'hd5) $fdisplay(f,\"* Reg af a=%h !=d5\",dut.reg_file_.b2v_latch_af_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h3b) $fdisplay(f,\"* Reg bc c=%h !=3b\",dut.reg_file_.b2v_latch_bc_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h0f) $fdisplay(f,\"* Reg bc b=%h !=0f\",dut.reg_file_.b2v_latch_bc_hi.latch);\n   if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h0d) $fdisplay(f,\"* Reg de e=%h !=0d\",dut.reg_file_.b2v_latch_de_lo.latch);\n   if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h20) $fdisplay(f,\"* Reg de d=%h !=20\",dut.reg_file_.b2v_latch_de_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'ha6) $fdisplay(f,\"* Reg hl l=%h !=a6\",dut.reg_file_.b2v_latch_hl_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hdc) $fdisplay(f,\"* Reg hl h=%h !=dc\",dut.reg_file_.b2v_latch_hl_hi.latch);\n   if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,\"* Reg af2 f=%h !=00\",dut.reg_file_.b2v_latch_af2_lo.latch);\n   if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,\"* Reg af2 a=%h !=00\",dut.reg_file_.b2v_latch_af2_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,\"* Reg bc2 c=%h !=00\",dut.reg_file_.b2v_latch_bc2_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,\"* Reg bc2 b=%h !=00\",dut.reg_file_.b2v_latch_bc2_hi.latch);\n   if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,\"* Reg de2 e=%h !=00\",dut.reg_file_.b2v_latch_de2_lo.latch);\n   if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,\"* Reg de2 d=%h !=00\",dut.reg_file_.b2v_latch_de2_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,\"* Reg hl2 l=%h !=00\",dut.reg_file_.b2v_latch_hl2_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,\"* Reg hl2 h=%h !=00\",dut.reg_file_.b2v_latch_hl2_hi.latch);\n   if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,\"* Reg ix x=%h !=00\",dut.reg_file_.b2v_latch_ix_lo.latch);\n   if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,\"* Reg ix i=%h !=00\",dut.reg_file_.b2v_latch_ix_hi.latch);\n   if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,\"* Reg iy y=%h !=00\",dut.reg_file_.b2v_latch_iy_lo.latch);\n   if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,\"* Reg iy i=%h !=00\",dut.reg_file_.b2v_latch_iy_hi.latch);\n   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,\"* Reg sp p=%h !=00\",dut.reg_file_.b2v_latch_sp_lo.latch);\n   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,\"* Reg sp s=%h !=00\",dut.reg_file_.b2v_latch_sp_hi.latch);\n   if (pc!==16'h0001) $fdisplay(f,\"* PC=%h !=0001\",pc);\n   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,\"* Reg ir r=%h !=01\",dut.reg_file_.b2v_latch_ir_lo.latch);\n   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,\"* Reg ir i=%h !=00\",dut.reg_file_.b2v_latch_ir_hi.latch);\n#1 // End opcode\n\n   force dut.ir_.ctl_ir_we=1;\n   force dut.ir_.db=0;\n#2 release dut.ir_.ctl_ir_we;\n   release dut.ir_.db;\n   $fdisplay(f,\"Testing opcode 9d      SBC A,L\");\n   // Preset af\n   force dut.reg_file_.b2v_latch_af_lo.we=1;\n   force dut.reg_file_.b2v_latch_af_hi.we=1;\n   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af_hi.db=8'hf5;\n#2 release dut.reg_file_.b2v_latch_af_lo.we;\n   release dut.reg_file_.b2v_latch_af_hi.we;\n   release dut.reg_file_.b2v_latch_af_lo.db;\n   release dut.reg_file_.b2v_latch_af_hi.db;\n   // Preset bc\n   force dut.reg_file_.b2v_latch_bc_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc_lo.db=8'h3b;\n   force dut.reg_file_.b2v_latch_bc_hi.db=8'h0f;\n#2 release dut.reg_file_.b2v_latch_bc_lo.we;\n   release dut.reg_file_.b2v_latch_bc_hi.we;\n   release dut.reg_file_.b2v_latch_bc_lo.db;\n   release dut.reg_file_.b2v_latch_bc_hi.db;\n   // Preset de\n   force dut.reg_file_.b2v_latch_de_lo.we=1;\n   force dut.reg_file_.b2v_latch_de_hi.we=1;\n   force dut.reg_file_.b2v_latch_de_lo.db=8'h0d;\n   force dut.reg_file_.b2v_latch_de_hi.db=8'h20;\n#2 release dut.reg_file_.b2v_latch_de_lo.we;\n   release dut.reg_file_.b2v_latch_de_hi.we;\n   release dut.reg_file_.b2v_latch_de_lo.db;\n   release dut.reg_file_.b2v_latch_de_hi.db;\n   // Preset hl\n   force dut.reg_file_.b2v_latch_hl_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl_lo.db=8'ha6;\n   force dut.reg_file_.b2v_latch_hl_hi.db=8'hdc;\n#2 release dut.reg_file_.b2v_latch_hl_lo.we;\n   release dut.reg_file_.b2v_latch_hl_hi.we;\n   release dut.reg_file_.b2v_latch_hl_lo.db;\n   release dut.reg_file_.b2v_latch_hl_hi.db;\n   // Preset af2\n   force dut.reg_file_.b2v_latch_af2_lo.we=1;\n   force dut.reg_file_.b2v_latch_af2_hi.we=1;\n   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_af2_lo.we;\n   release dut.reg_file_.b2v_latch_af2_hi.we;\n   release dut.reg_file_.b2v_latch_af2_lo.db;\n   release dut.reg_file_.b2v_latch_af2_hi.db;\n   // Preset bc2\n   force dut.reg_file_.b2v_latch_bc2_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc2_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_bc2_lo.we;\n   release dut.reg_file_.b2v_latch_bc2_hi.we;\n   release dut.reg_file_.b2v_latch_bc2_lo.db;\n   release dut.reg_file_.b2v_latch_bc2_hi.db;\n   // Preset de2\n   force dut.reg_file_.b2v_latch_de2_lo.we=1;\n   force dut.reg_file_.b2v_latch_de2_hi.we=1;\n   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_de2_lo.we;\n   release dut.reg_file_.b2v_latch_de2_hi.we;\n   release dut.reg_file_.b2v_latch_de2_lo.db;\n   release dut.reg_file_.b2v_latch_de2_hi.db;\n   // Preset hl2\n   force dut.reg_file_.b2v_latch_hl2_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl2_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_hl2_lo.we;\n   release dut.reg_file_.b2v_latch_hl2_hi.we;\n   release dut.reg_file_.b2v_latch_hl2_lo.db;\n   release dut.reg_file_.b2v_latch_hl2_hi.db;\n   // Preset ix\n   force dut.reg_file_.b2v_latch_ix_lo.we=1;\n   force dut.reg_file_.b2v_latch_ix_hi.we=1;\n   force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ix_lo.we;\n   release dut.reg_file_.b2v_latch_ix_hi.we;\n   release dut.reg_file_.b2v_latch_ix_lo.db;\n   release dut.reg_file_.b2v_latch_ix_hi.db;\n   // Preset iy\n   force dut.reg_file_.b2v_latch_iy_lo.we=1;\n   force dut.reg_file_.b2v_latch_iy_hi.we=1;\n   force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_iy_lo.we;\n   release dut.reg_file_.b2v_latch_iy_hi.we;\n   release dut.reg_file_.b2v_latch_iy_lo.db;\n   release dut.reg_file_.b2v_latch_iy_hi.db;\n   // Preset sp\n   force dut.reg_file_.b2v_latch_sp_lo.we=1;\n   force dut.reg_file_.b2v_latch_sp_hi.we=1;\n   force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_sp_lo.we;\n   release dut.reg_file_.b2v_latch_sp_hi.we;\n   release dut.reg_file_.b2v_latch_sp_lo.db;\n   release dut.reg_file_.b2v_latch_sp_hi.db;\n   // Preset wz\n   force dut.reg_file_.b2v_latch_wz_lo.we=1;\n   force dut.reg_file_.b2v_latch_wz_hi.we=1;\n   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_wz_lo.we;\n   release dut.reg_file_.b2v_latch_wz_hi.we;\n   release dut.reg_file_.b2v_latch_wz_lo.db;\n   release dut.reg_file_.b2v_latch_wz_hi.db;\n   // Preset pc\n   force dut.reg_file_.b2v_latch_pc_lo.we=1;\n   force dut.reg_file_.b2v_latch_pc_hi.we=1;\n   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_pc_lo.we;\n   release dut.reg_file_.b2v_latch_pc_hi.we;\n   release dut.reg_file_.b2v_latch_pc_lo.db;\n   release dut.reg_file_.b2v_latch_pc_hi.db;\n   // Preset ir\n   force dut.reg_file_.b2v_latch_ir_lo.we=1;\n   force dut.reg_file_.b2v_latch_ir_hi.we=1;\n   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ir_lo.we;\n   release dut.reg_file_.b2v_latch_ir_hi.we;\n   release dut.reg_file_.b2v_latch_ir_lo.db;\n   release dut.reg_file_.b2v_latch_ir_hi.db;\n   // Preset memory\n   ram.Mem[0] = 8'h9d;\n   // Preset memory\n   ram.Mem[56486] = 8'h49;\n   force dut.z80_top_ifc_n.fpga_reset=0;\n   force dut.address_latch_.Q=16'h0000;\n   release dut.reg_control_.ctl_reg_sys_we;\n   release dut.reg_file_.reg_gp_we;\n#2 // Execute: M1/T1 start\n#1 release dut.address_latch_.Q;\n#1\n#6 // Wait for opcode end\n   force dut.reg_control_.ctl_reg_sys_we=0;\n#2 pc=z.A;\n#2\n#1 force dut.reg_file_.reg_gp_we=0;\n   force dut.z80_top_ifc_n.fpga_reset=1;\n   if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h1a) $fdisplay(f,\"* Reg af f=%h !=1a\",dut.reg_file_.b2v_latch_af_lo.latch);\n   if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h4f) $fdisplay(f,\"* Reg af a=%h !=4f\",dut.reg_file_.b2v_latch_af_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h3b) $fdisplay(f,\"* Reg bc c=%h !=3b\",dut.reg_file_.b2v_latch_bc_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h0f) $fdisplay(f,\"* Reg bc b=%h !=0f\",dut.reg_file_.b2v_latch_bc_hi.latch);\n   if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h0d) $fdisplay(f,\"* Reg de e=%h !=0d\",dut.reg_file_.b2v_latch_de_lo.latch);\n   if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h20) $fdisplay(f,\"* Reg de d=%h !=20\",dut.reg_file_.b2v_latch_de_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'ha6) $fdisplay(f,\"* Reg hl l=%h !=a6\",dut.reg_file_.b2v_latch_hl_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hdc) $fdisplay(f,\"* Reg hl h=%h !=dc\",dut.reg_file_.b2v_latch_hl_hi.latch);\n   if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,\"* Reg af2 f=%h !=00\",dut.reg_file_.b2v_latch_af2_lo.latch);\n   if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,\"* Reg af2 a=%h !=00\",dut.reg_file_.b2v_latch_af2_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,\"* Reg bc2 c=%h !=00\",dut.reg_file_.b2v_latch_bc2_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,\"* Reg bc2 b=%h !=00\",dut.reg_file_.b2v_latch_bc2_hi.latch);\n   if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,\"* Reg de2 e=%h !=00\",dut.reg_file_.b2v_latch_de2_lo.latch);\n   if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,\"* Reg de2 d=%h !=00\",dut.reg_file_.b2v_latch_de2_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,\"* Reg hl2 l=%h !=00\",dut.reg_file_.b2v_latch_hl2_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,\"* Reg hl2 h=%h !=00\",dut.reg_file_.b2v_latch_hl2_hi.latch);\n   if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,\"* Reg ix x=%h !=00\",dut.reg_file_.b2v_latch_ix_lo.latch);\n   if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,\"* Reg ix i=%h !=00\",dut.reg_file_.b2v_latch_ix_hi.latch);\n   if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,\"* Reg iy y=%h !=00\",dut.reg_file_.b2v_latch_iy_lo.latch);\n   if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,\"* Reg iy i=%h !=00\",dut.reg_file_.b2v_latch_iy_hi.latch);\n   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,\"* Reg sp p=%h !=00\",dut.reg_file_.b2v_latch_sp_lo.latch);\n   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,\"* Reg sp s=%h !=00\",dut.reg_file_.b2v_latch_sp_hi.latch);\n   if (pc!==16'h0001) $fdisplay(f,\"* PC=%h !=0001\",pc);\n   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,\"* Reg ir r=%h !=01\",dut.reg_file_.b2v_latch_ir_lo.latch);\n   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,\"* Reg ir i=%h !=00\",dut.reg_file_.b2v_latch_ir_hi.latch);\n#1 // End opcode\n\n   force dut.ir_.ctl_ir_we=1;\n   force dut.ir_.db=0;\n#2 release dut.ir_.ctl_ir_we;\n   release dut.ir_.db;\n   $fdisplay(f,\"Testing opcode a3      AND E\");\n   // Preset af\n   force dut.reg_file_.b2v_latch_af_lo.we=1;\n   force dut.reg_file_.b2v_latch_af_hi.we=1;\n   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af_hi.db=8'hf5;\n#2 release dut.reg_file_.b2v_latch_af_lo.we;\n   release dut.reg_file_.b2v_latch_af_hi.we;\n   release dut.reg_file_.b2v_latch_af_lo.db;\n   release dut.reg_file_.b2v_latch_af_hi.db;\n   // Preset bc\n   force dut.reg_file_.b2v_latch_bc_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc_lo.db=8'h3b;\n   force dut.reg_file_.b2v_latch_bc_hi.db=8'h0f;\n#2 release dut.reg_file_.b2v_latch_bc_lo.we;\n   release dut.reg_file_.b2v_latch_bc_hi.we;\n   release dut.reg_file_.b2v_latch_bc_lo.db;\n   release dut.reg_file_.b2v_latch_bc_hi.db;\n   // Preset de\n   force dut.reg_file_.b2v_latch_de_lo.we=1;\n   force dut.reg_file_.b2v_latch_de_hi.we=1;\n   force dut.reg_file_.b2v_latch_de_lo.db=8'h0d;\n   force dut.reg_file_.b2v_latch_de_hi.db=8'h20;\n#2 release dut.reg_file_.b2v_latch_de_lo.we;\n   release dut.reg_file_.b2v_latch_de_hi.we;\n   release dut.reg_file_.b2v_latch_de_lo.db;\n   release dut.reg_file_.b2v_latch_de_hi.db;\n   // Preset hl\n   force dut.reg_file_.b2v_latch_hl_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl_lo.db=8'ha6;\n   force dut.reg_file_.b2v_latch_hl_hi.db=8'hdc;\n#2 release dut.reg_file_.b2v_latch_hl_lo.we;\n   release dut.reg_file_.b2v_latch_hl_hi.we;\n   release dut.reg_file_.b2v_latch_hl_lo.db;\n   release dut.reg_file_.b2v_latch_hl_hi.db;\n   // Preset af2\n   force dut.reg_file_.b2v_latch_af2_lo.we=1;\n   force dut.reg_file_.b2v_latch_af2_hi.we=1;\n   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_af2_lo.we;\n   release dut.reg_file_.b2v_latch_af2_hi.we;\n   release dut.reg_file_.b2v_latch_af2_lo.db;\n   release dut.reg_file_.b2v_latch_af2_hi.db;\n   // Preset bc2\n   force dut.reg_file_.b2v_latch_bc2_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc2_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_bc2_lo.we;\n   release dut.reg_file_.b2v_latch_bc2_hi.we;\n   release dut.reg_file_.b2v_latch_bc2_lo.db;\n   release dut.reg_file_.b2v_latch_bc2_hi.db;\n   // Preset de2\n   force dut.reg_file_.b2v_latch_de2_lo.we=1;\n   force dut.reg_file_.b2v_latch_de2_hi.we=1;\n   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_de2_lo.we;\n   release dut.reg_file_.b2v_latch_de2_hi.we;\n   release dut.reg_file_.b2v_latch_de2_lo.db;\n   release dut.reg_file_.b2v_latch_de2_hi.db;\n   // Preset hl2\n   force dut.reg_file_.b2v_latch_hl2_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl2_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_hl2_lo.we;\n   release dut.reg_file_.b2v_latch_hl2_hi.we;\n   release dut.reg_file_.b2v_latch_hl2_lo.db;\n   release dut.reg_file_.b2v_latch_hl2_hi.db;\n   // Preset ix\n   force dut.reg_file_.b2v_latch_ix_lo.we=1;\n   force dut.reg_file_.b2v_latch_ix_hi.we=1;\n   force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ix_lo.we;\n   release dut.reg_file_.b2v_latch_ix_hi.we;\n   release dut.reg_file_.b2v_latch_ix_lo.db;\n   release dut.reg_file_.b2v_latch_ix_hi.db;\n   // Preset iy\n   force dut.reg_file_.b2v_latch_iy_lo.we=1;\n   force dut.reg_file_.b2v_latch_iy_hi.we=1;\n   force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_iy_lo.we;\n   release dut.reg_file_.b2v_latch_iy_hi.we;\n   release dut.reg_file_.b2v_latch_iy_lo.db;\n   release dut.reg_file_.b2v_latch_iy_hi.db;\n   // Preset sp\n   force dut.reg_file_.b2v_latch_sp_lo.we=1;\n   force dut.reg_file_.b2v_latch_sp_hi.we=1;\n   force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_sp_lo.we;\n   release dut.reg_file_.b2v_latch_sp_hi.we;\n   release dut.reg_file_.b2v_latch_sp_lo.db;\n   release dut.reg_file_.b2v_latch_sp_hi.db;\n   // Preset wz\n   force dut.reg_file_.b2v_latch_wz_lo.we=1;\n   force dut.reg_file_.b2v_latch_wz_hi.we=1;\n   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_wz_lo.we;\n   release dut.reg_file_.b2v_latch_wz_hi.we;\n   release dut.reg_file_.b2v_latch_wz_lo.db;\n   release dut.reg_file_.b2v_latch_wz_hi.db;\n   // Preset pc\n   force dut.reg_file_.b2v_latch_pc_lo.we=1;\n   force dut.reg_file_.b2v_latch_pc_hi.we=1;\n   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_pc_lo.we;\n   release dut.reg_file_.b2v_latch_pc_hi.we;\n   release dut.reg_file_.b2v_latch_pc_lo.db;\n   release dut.reg_file_.b2v_latch_pc_hi.db;\n   // Preset ir\n   force dut.reg_file_.b2v_latch_ir_lo.we=1;\n   force dut.reg_file_.b2v_latch_ir_hi.we=1;\n   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ir_lo.we;\n   release dut.reg_file_.b2v_latch_ir_hi.we;\n   release dut.reg_file_.b2v_latch_ir_lo.db;\n   release dut.reg_file_.b2v_latch_ir_hi.db;\n   // Preset memory\n   ram.Mem[0] = 8'ha3;\n   // Preset memory\n   ram.Mem[56486] = 8'h49;\n   force dut.z80_top_ifc_n.fpga_reset=0;\n   force dut.address_latch_.Q=16'h0000;\n   release dut.reg_control_.ctl_reg_sys_we;\n   release dut.reg_file_.reg_gp_we;\n#2 // Execute: M1/T1 start\n#1 release dut.address_latch_.Q;\n#1\n#6 // Wait for opcode end\n   force dut.reg_control_.ctl_reg_sys_we=0;\n#2 pc=z.A;\n#2\n#1 force dut.reg_file_.reg_gp_we=0;\n   force dut.z80_top_ifc_n.fpga_reset=1;\n   if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h14) $fdisplay(f,\"* Reg af f=%h !=14\",dut.reg_file_.b2v_latch_af_lo.latch);\n   if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h05) $fdisplay(f,\"* Reg af a=%h !=05\",dut.reg_file_.b2v_latch_af_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h3b) $fdisplay(f,\"* Reg bc c=%h !=3b\",dut.reg_file_.b2v_latch_bc_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h0f) $fdisplay(f,\"* Reg bc b=%h !=0f\",dut.reg_file_.b2v_latch_bc_hi.latch);\n   if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h0d) $fdisplay(f,\"* Reg de e=%h !=0d\",dut.reg_file_.b2v_latch_de_lo.latch);\n   if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h20) $fdisplay(f,\"* Reg de d=%h !=20\",dut.reg_file_.b2v_latch_de_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'ha6) $fdisplay(f,\"* Reg hl l=%h !=a6\",dut.reg_file_.b2v_latch_hl_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hdc) $fdisplay(f,\"* Reg hl h=%h !=dc\",dut.reg_file_.b2v_latch_hl_hi.latch);\n   if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,\"* Reg af2 f=%h !=00\",dut.reg_file_.b2v_latch_af2_lo.latch);\n   if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,\"* Reg af2 a=%h !=00\",dut.reg_file_.b2v_latch_af2_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,\"* Reg bc2 c=%h !=00\",dut.reg_file_.b2v_latch_bc2_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,\"* Reg bc2 b=%h !=00\",dut.reg_file_.b2v_latch_bc2_hi.latch);\n   if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,\"* Reg de2 e=%h !=00\",dut.reg_file_.b2v_latch_de2_lo.latch);\n   if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,\"* Reg de2 d=%h !=00\",dut.reg_file_.b2v_latch_de2_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,\"* Reg hl2 l=%h !=00\",dut.reg_file_.b2v_latch_hl2_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,\"* Reg hl2 h=%h !=00\",dut.reg_file_.b2v_latch_hl2_hi.latch);\n   if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,\"* Reg ix x=%h !=00\",dut.reg_file_.b2v_latch_ix_lo.latch);\n   if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,\"* Reg ix i=%h !=00\",dut.reg_file_.b2v_latch_ix_hi.latch);\n   if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,\"* Reg iy y=%h !=00\",dut.reg_file_.b2v_latch_iy_lo.latch);\n   if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,\"* Reg iy i=%h !=00\",dut.reg_file_.b2v_latch_iy_hi.latch);\n   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,\"* Reg sp p=%h !=00\",dut.reg_file_.b2v_latch_sp_lo.latch);\n   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,\"* Reg sp s=%h !=00\",dut.reg_file_.b2v_latch_sp_hi.latch);\n   if (pc!==16'h0001) $fdisplay(f,\"* PC=%h !=0001\",pc);\n   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,\"* Reg ir r=%h !=01\",dut.reg_file_.b2v_latch_ir_lo.latch);\n   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,\"* Reg ir i=%h !=00\",dut.reg_file_.b2v_latch_ir_hi.latch);\n#1 // End opcode\n\n   force dut.ir_.ctl_ir_we=1;\n   force dut.ir_.db=0;\n#2 release dut.ir_.ctl_ir_we;\n   release dut.ir_.db;\n   $fdisplay(f,\"Testing opcode ae      XOR (HL)\");\n   // Preset af\n   force dut.reg_file_.b2v_latch_af_lo.we=1;\n   force dut.reg_file_.b2v_latch_af_hi.we=1;\n   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af_hi.db=8'hf5;\n#2 release dut.reg_file_.b2v_latch_af_lo.we;\n   release dut.reg_file_.b2v_latch_af_hi.we;\n   release dut.reg_file_.b2v_latch_af_lo.db;\n   release dut.reg_file_.b2v_latch_af_hi.db;\n   // Preset bc\n   force dut.reg_file_.b2v_latch_bc_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc_lo.db=8'h3b;\n   force dut.reg_file_.b2v_latch_bc_hi.db=8'h0f;\n#2 release dut.reg_file_.b2v_latch_bc_lo.we;\n   release dut.reg_file_.b2v_latch_bc_hi.we;\n   release dut.reg_file_.b2v_latch_bc_lo.db;\n   release dut.reg_file_.b2v_latch_bc_hi.db;\n   // Preset de\n   force dut.reg_file_.b2v_latch_de_lo.we=1;\n   force dut.reg_file_.b2v_latch_de_hi.we=1;\n   force dut.reg_file_.b2v_latch_de_lo.db=8'h0d;\n   force dut.reg_file_.b2v_latch_de_hi.db=8'h20;\n#2 release dut.reg_file_.b2v_latch_de_lo.we;\n   release dut.reg_file_.b2v_latch_de_hi.we;\n   release dut.reg_file_.b2v_latch_de_lo.db;\n   release dut.reg_file_.b2v_latch_de_hi.db;\n   // Preset hl\n   force dut.reg_file_.b2v_latch_hl_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl_lo.db=8'ha6;\n   force dut.reg_file_.b2v_latch_hl_hi.db=8'hdc;\n#2 release dut.reg_file_.b2v_latch_hl_lo.we;\n   release dut.reg_file_.b2v_latch_hl_hi.we;\n   release dut.reg_file_.b2v_latch_hl_lo.db;\n   release dut.reg_file_.b2v_latch_hl_hi.db;\n   // Preset af2\n   force dut.reg_file_.b2v_latch_af2_lo.we=1;\n   force dut.reg_file_.b2v_latch_af2_hi.we=1;\n   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_af2_lo.we;\n   release dut.reg_file_.b2v_latch_af2_hi.we;\n   release dut.reg_file_.b2v_latch_af2_lo.db;\n   release dut.reg_file_.b2v_latch_af2_hi.db;\n   // Preset bc2\n   force dut.reg_file_.b2v_latch_bc2_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc2_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_bc2_lo.we;\n   release dut.reg_file_.b2v_latch_bc2_hi.we;\n   release dut.reg_file_.b2v_latch_bc2_lo.db;\n   release dut.reg_file_.b2v_latch_bc2_hi.db;\n   // Preset de2\n   force dut.reg_file_.b2v_latch_de2_lo.we=1;\n   force dut.reg_file_.b2v_latch_de2_hi.we=1;\n   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_de2_lo.we;\n   release dut.reg_file_.b2v_latch_de2_hi.we;\n   release dut.reg_file_.b2v_latch_de2_lo.db;\n   release dut.reg_file_.b2v_latch_de2_hi.db;\n   // Preset hl2\n   force dut.reg_file_.b2v_latch_hl2_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl2_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_hl2_lo.we;\n   release dut.reg_file_.b2v_latch_hl2_hi.we;\n   release dut.reg_file_.b2v_latch_hl2_lo.db;\n   release dut.reg_file_.b2v_latch_hl2_hi.db;\n   // Preset ix\n   force dut.reg_file_.b2v_latch_ix_lo.we=1;\n   force dut.reg_file_.b2v_latch_ix_hi.we=1;\n   force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ix_lo.we;\n   release dut.reg_file_.b2v_latch_ix_hi.we;\n   release dut.reg_file_.b2v_latch_ix_lo.db;\n   release dut.reg_file_.b2v_latch_ix_hi.db;\n   // Preset iy\n   force dut.reg_file_.b2v_latch_iy_lo.we=1;\n   force dut.reg_file_.b2v_latch_iy_hi.we=1;\n   force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_iy_lo.we;\n   release dut.reg_file_.b2v_latch_iy_hi.we;\n   release dut.reg_file_.b2v_latch_iy_lo.db;\n   release dut.reg_file_.b2v_latch_iy_hi.db;\n   // Preset sp\n   force dut.reg_file_.b2v_latch_sp_lo.we=1;\n   force dut.reg_file_.b2v_latch_sp_hi.we=1;\n   force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_sp_lo.we;\n   release dut.reg_file_.b2v_latch_sp_hi.we;\n   release dut.reg_file_.b2v_latch_sp_lo.db;\n   release dut.reg_file_.b2v_latch_sp_hi.db;\n   // Preset wz\n   force dut.reg_file_.b2v_latch_wz_lo.we=1;\n   force dut.reg_file_.b2v_latch_wz_hi.we=1;\n   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_wz_lo.we;\n   release dut.reg_file_.b2v_latch_wz_hi.we;\n   release dut.reg_file_.b2v_latch_wz_lo.db;\n   release dut.reg_file_.b2v_latch_wz_hi.db;\n   // Preset pc\n   force dut.reg_file_.b2v_latch_pc_lo.we=1;\n   force dut.reg_file_.b2v_latch_pc_hi.we=1;\n   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_pc_lo.we;\n   release dut.reg_file_.b2v_latch_pc_hi.we;\n   release dut.reg_file_.b2v_latch_pc_lo.db;\n   release dut.reg_file_.b2v_latch_pc_hi.db;\n   // Preset ir\n   force dut.reg_file_.b2v_latch_ir_lo.we=1;\n   force dut.reg_file_.b2v_latch_ir_hi.we=1;\n   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ir_lo.we;\n   release dut.reg_file_.b2v_latch_ir_hi.we;\n   release dut.reg_file_.b2v_latch_ir_lo.db;\n   release dut.reg_file_.b2v_latch_ir_hi.db;\n   // Preset memory\n   ram.Mem[0] = 8'hae;\n   // Preset memory\n   ram.Mem[56486] = 8'h49;\n   force dut.z80_top_ifc_n.fpga_reset=0;\n   force dut.address_latch_.Q=16'h0000;\n   release dut.reg_control_.ctl_reg_sys_we;\n   release dut.reg_file_.reg_gp_we;\n#2 // Execute: M1/T1 start\n#1 release dut.address_latch_.Q;\n#1\n#12 // Wait for opcode end\n   force dut.reg_control_.ctl_reg_sys_we=0;\n#2 pc=z.A;\n#2\n#1 force dut.reg_file_.reg_gp_we=0;\n   force dut.z80_top_ifc_n.fpga_reset=1;\n   if (dut.reg_file_.b2v_latch_af_lo.latch!==8'ha8) $fdisplay(f,\"* Reg af f=%h !=a8\",dut.reg_file_.b2v_latch_af_lo.latch);\n   if (dut.reg_file_.b2v_latch_af_hi.latch!==8'hbc) $fdisplay(f,\"* Reg af a=%h !=bc\",dut.reg_file_.b2v_latch_af_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h3b) $fdisplay(f,\"* Reg bc c=%h !=3b\",dut.reg_file_.b2v_latch_bc_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h0f) $fdisplay(f,\"* Reg bc b=%h !=0f\",dut.reg_file_.b2v_latch_bc_hi.latch);\n   if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h0d) $fdisplay(f,\"* Reg de e=%h !=0d\",dut.reg_file_.b2v_latch_de_lo.latch);\n   if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h20) $fdisplay(f,\"* Reg de d=%h !=20\",dut.reg_file_.b2v_latch_de_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'ha6) $fdisplay(f,\"* Reg hl l=%h !=a6\",dut.reg_file_.b2v_latch_hl_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hdc) $fdisplay(f,\"* Reg hl h=%h !=dc\",dut.reg_file_.b2v_latch_hl_hi.latch);\n   if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,\"* Reg af2 f=%h !=00\",dut.reg_file_.b2v_latch_af2_lo.latch);\n   if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,\"* Reg af2 a=%h !=00\",dut.reg_file_.b2v_latch_af2_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,\"* Reg bc2 c=%h !=00\",dut.reg_file_.b2v_latch_bc2_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,\"* Reg bc2 b=%h !=00\",dut.reg_file_.b2v_latch_bc2_hi.latch);\n   if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,\"* Reg de2 e=%h !=00\",dut.reg_file_.b2v_latch_de2_lo.latch);\n   if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,\"* Reg de2 d=%h !=00\",dut.reg_file_.b2v_latch_de2_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,\"* Reg hl2 l=%h !=00\",dut.reg_file_.b2v_latch_hl2_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,\"* Reg hl2 h=%h !=00\",dut.reg_file_.b2v_latch_hl2_hi.latch);\n   if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,\"* Reg ix x=%h !=00\",dut.reg_file_.b2v_latch_ix_lo.latch);\n   if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,\"* Reg ix i=%h !=00\",dut.reg_file_.b2v_latch_ix_hi.latch);\n   if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,\"* Reg iy y=%h !=00\",dut.reg_file_.b2v_latch_iy_lo.latch);\n   if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,\"* Reg iy i=%h !=00\",dut.reg_file_.b2v_latch_iy_hi.latch);\n   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,\"* Reg sp p=%h !=00\",dut.reg_file_.b2v_latch_sp_lo.latch);\n   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,\"* Reg sp s=%h !=00\",dut.reg_file_.b2v_latch_sp_hi.latch);\n   if (pc!==16'h0001) $fdisplay(f,\"* PC=%h !=0001\",pc);\n   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,\"* Reg ir r=%h !=01\",dut.reg_file_.b2v_latch_ir_lo.latch);\n   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,\"* Reg ir i=%h !=00\",dut.reg_file_.b2v_latch_ir_hi.latch);\n#1 // End opcode\n\n   force dut.ir_.ctl_ir_we=1;\n   force dut.ir_.db=0;\n#2 release dut.ir_.ctl_ir_we;\n   release dut.ir_.db;\n   $fdisplay(f,\"Testing opcode b4      OR H\");\n   // Preset af\n   force dut.reg_file_.b2v_latch_af_lo.we=1;\n   force dut.reg_file_.b2v_latch_af_hi.we=1;\n   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af_hi.db=8'hf5;\n#2 release dut.reg_file_.b2v_latch_af_lo.we;\n   release dut.reg_file_.b2v_latch_af_hi.we;\n   release dut.reg_file_.b2v_latch_af_lo.db;\n   release dut.reg_file_.b2v_latch_af_hi.db;\n   // Preset bc\n   force dut.reg_file_.b2v_latch_bc_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc_lo.db=8'h3b;\n   force dut.reg_file_.b2v_latch_bc_hi.db=8'h0f;\n#2 release dut.reg_file_.b2v_latch_bc_lo.we;\n   release dut.reg_file_.b2v_latch_bc_hi.we;\n   release dut.reg_file_.b2v_latch_bc_lo.db;\n   release dut.reg_file_.b2v_latch_bc_hi.db;\n   // Preset de\n   force dut.reg_file_.b2v_latch_de_lo.we=1;\n   force dut.reg_file_.b2v_latch_de_hi.we=1;\n   force dut.reg_file_.b2v_latch_de_lo.db=8'h0d;\n   force dut.reg_file_.b2v_latch_de_hi.db=8'h20;\n#2 release dut.reg_file_.b2v_latch_de_lo.we;\n   release dut.reg_file_.b2v_latch_de_hi.we;\n   release dut.reg_file_.b2v_latch_de_lo.db;\n   release dut.reg_file_.b2v_latch_de_hi.db;\n   // Preset hl\n   force dut.reg_file_.b2v_latch_hl_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl_lo.db=8'ha6;\n   force dut.reg_file_.b2v_latch_hl_hi.db=8'hdc;\n#2 release dut.reg_file_.b2v_latch_hl_lo.we;\n   release dut.reg_file_.b2v_latch_hl_hi.we;\n   release dut.reg_file_.b2v_latch_hl_lo.db;\n   release dut.reg_file_.b2v_latch_hl_hi.db;\n   // Preset af2\n   force dut.reg_file_.b2v_latch_af2_lo.we=1;\n   force dut.reg_file_.b2v_latch_af2_hi.we=1;\n   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_af2_lo.we;\n   release dut.reg_file_.b2v_latch_af2_hi.we;\n   release dut.reg_file_.b2v_latch_af2_lo.db;\n   release dut.reg_file_.b2v_latch_af2_hi.db;\n   // Preset bc2\n   force dut.reg_file_.b2v_latch_bc2_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc2_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_bc2_lo.we;\n   release dut.reg_file_.b2v_latch_bc2_hi.we;\n   release dut.reg_file_.b2v_latch_bc2_lo.db;\n   release dut.reg_file_.b2v_latch_bc2_hi.db;\n   // Preset de2\n   force dut.reg_file_.b2v_latch_de2_lo.we=1;\n   force dut.reg_file_.b2v_latch_de2_hi.we=1;\n   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_de2_lo.we;\n   release dut.reg_file_.b2v_latch_de2_hi.we;\n   release dut.reg_file_.b2v_latch_de2_lo.db;\n   release dut.reg_file_.b2v_latch_de2_hi.db;\n   // Preset hl2\n   force dut.reg_file_.b2v_latch_hl2_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl2_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_hl2_lo.we;\n   release dut.reg_file_.b2v_latch_hl2_hi.we;\n   release dut.reg_file_.b2v_latch_hl2_lo.db;\n   release dut.reg_file_.b2v_latch_hl2_hi.db;\n   // Preset ix\n   force dut.reg_file_.b2v_latch_ix_lo.we=1;\n   force dut.reg_file_.b2v_latch_ix_hi.we=1;\n   force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ix_lo.we;\n   release dut.reg_file_.b2v_latch_ix_hi.we;\n   release dut.reg_file_.b2v_latch_ix_lo.db;\n   release dut.reg_file_.b2v_latch_ix_hi.db;\n   // Preset iy\n   force dut.reg_file_.b2v_latch_iy_lo.we=1;\n   force dut.reg_file_.b2v_latch_iy_hi.we=1;\n   force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_iy_lo.we;\n   release dut.reg_file_.b2v_latch_iy_hi.we;\n   release dut.reg_file_.b2v_latch_iy_lo.db;\n   release dut.reg_file_.b2v_latch_iy_hi.db;\n   // Preset sp\n   force dut.reg_file_.b2v_latch_sp_lo.we=1;\n   force dut.reg_file_.b2v_latch_sp_hi.we=1;\n   force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_sp_lo.we;\n   release dut.reg_file_.b2v_latch_sp_hi.we;\n   release dut.reg_file_.b2v_latch_sp_lo.db;\n   release dut.reg_file_.b2v_latch_sp_hi.db;\n   // Preset wz\n   force dut.reg_file_.b2v_latch_wz_lo.we=1;\n   force dut.reg_file_.b2v_latch_wz_hi.we=1;\n   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_wz_lo.we;\n   release dut.reg_file_.b2v_latch_wz_hi.we;\n   release dut.reg_file_.b2v_latch_wz_lo.db;\n   release dut.reg_file_.b2v_latch_wz_hi.db;\n   // Preset pc\n   force dut.reg_file_.b2v_latch_pc_lo.we=1;\n   force dut.reg_file_.b2v_latch_pc_hi.we=1;\n   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_pc_lo.we;\n   release dut.reg_file_.b2v_latch_pc_hi.we;\n   release dut.reg_file_.b2v_latch_pc_lo.db;\n   release dut.reg_file_.b2v_latch_pc_hi.db;\n   // Preset ir\n   force dut.reg_file_.b2v_latch_ir_lo.we=1;\n   force dut.reg_file_.b2v_latch_ir_hi.we=1;\n   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ir_lo.we;\n   release dut.reg_file_.b2v_latch_ir_hi.we;\n   release dut.reg_file_.b2v_latch_ir_lo.db;\n   release dut.reg_file_.b2v_latch_ir_hi.db;\n   // Preset memory\n   ram.Mem[0] = 8'hb4;\n   // Preset memory\n   ram.Mem[56486] = 8'h49;\n   force dut.z80_top_ifc_n.fpga_reset=0;\n   force dut.address_latch_.Q=16'h0000;\n   release dut.reg_control_.ctl_reg_sys_we;\n   release dut.reg_file_.reg_gp_we;\n#2 // Execute: M1/T1 start\n#1 release dut.address_latch_.Q;\n#1\n#6 // Wait for opcode end\n   force dut.reg_control_.ctl_reg_sys_we=0;\n#2 pc=z.A;\n#2\n#1 force dut.reg_file_.reg_gp_we=0;\n   force dut.z80_top_ifc_n.fpga_reset=1;\n   if (dut.reg_file_.b2v_latch_af_lo.latch!==8'ha8) $fdisplay(f,\"* Reg af f=%h !=a8\",dut.reg_file_.b2v_latch_af_lo.latch);\n   if (dut.reg_file_.b2v_latch_af_hi.latch!==8'hfd) $fdisplay(f,\"* Reg af a=%h !=fd\",dut.reg_file_.b2v_latch_af_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h3b) $fdisplay(f,\"* Reg bc c=%h !=3b\",dut.reg_file_.b2v_latch_bc_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h0f) $fdisplay(f,\"* Reg bc b=%h !=0f\",dut.reg_file_.b2v_latch_bc_hi.latch);\n   if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h0d) $fdisplay(f,\"* Reg de e=%h !=0d\",dut.reg_file_.b2v_latch_de_lo.latch);\n   if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h20) $fdisplay(f,\"* Reg de d=%h !=20\",dut.reg_file_.b2v_latch_de_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'ha6) $fdisplay(f,\"* Reg hl l=%h !=a6\",dut.reg_file_.b2v_latch_hl_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hdc) $fdisplay(f,\"* Reg hl h=%h !=dc\",dut.reg_file_.b2v_latch_hl_hi.latch);\n   if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,\"* Reg af2 f=%h !=00\",dut.reg_file_.b2v_latch_af2_lo.latch);\n   if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,\"* Reg af2 a=%h !=00\",dut.reg_file_.b2v_latch_af2_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,\"* Reg bc2 c=%h !=00\",dut.reg_file_.b2v_latch_bc2_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,\"* Reg bc2 b=%h !=00\",dut.reg_file_.b2v_latch_bc2_hi.latch);\n   if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,\"* Reg de2 e=%h !=00\",dut.reg_file_.b2v_latch_de2_lo.latch);\n   if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,\"* Reg de2 d=%h !=00\",dut.reg_file_.b2v_latch_de2_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,\"* Reg hl2 l=%h !=00\",dut.reg_file_.b2v_latch_hl2_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,\"* Reg hl2 h=%h !=00\",dut.reg_file_.b2v_latch_hl2_hi.latch);\n   if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,\"* Reg ix x=%h !=00\",dut.reg_file_.b2v_latch_ix_lo.latch);\n   if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,\"* Reg ix i=%h !=00\",dut.reg_file_.b2v_latch_ix_hi.latch);\n   if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,\"* Reg iy y=%h !=00\",dut.reg_file_.b2v_latch_iy_lo.latch);\n   if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,\"* Reg iy i=%h !=00\",dut.reg_file_.b2v_latch_iy_hi.latch);\n   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,\"* Reg sp p=%h !=00\",dut.reg_file_.b2v_latch_sp_lo.latch);\n   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,\"* Reg sp s=%h !=00\",dut.reg_file_.b2v_latch_sp_hi.latch);\n   if (pc!==16'h0001) $fdisplay(f,\"* PC=%h !=0001\",pc);\n   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,\"* Reg ir r=%h !=01\",dut.reg_file_.b2v_latch_ir_lo.latch);\n   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,\"* Reg ir i=%h !=00\",dut.reg_file_.b2v_latch_ir_hi.latch);\n#1 // End opcode\n\n   force dut.ir_.ctl_ir_we=1;\n   force dut.ir_.db=0;\n#2 release dut.ir_.ctl_ir_we;\n   release dut.ir_.db;\n   $fdisplay(f,\"Testing opcode bf      CP A\");\n   // Preset af\n   force dut.reg_file_.b2v_latch_af_lo.we=1;\n   force dut.reg_file_.b2v_latch_af_hi.we=1;\n   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af_hi.db=8'hf5;\n#2 release dut.reg_file_.b2v_latch_af_lo.we;\n   release dut.reg_file_.b2v_latch_af_hi.we;\n   release dut.reg_file_.b2v_latch_af_lo.db;\n   release dut.reg_file_.b2v_latch_af_hi.db;\n   // Preset bc\n   force dut.reg_file_.b2v_latch_bc_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc_lo.db=8'h3b;\n   force dut.reg_file_.b2v_latch_bc_hi.db=8'h0f;\n#2 release dut.reg_file_.b2v_latch_bc_lo.we;\n   release dut.reg_file_.b2v_latch_bc_hi.we;\n   release dut.reg_file_.b2v_latch_bc_lo.db;\n   release dut.reg_file_.b2v_latch_bc_hi.db;\n   // Preset de\n   force dut.reg_file_.b2v_latch_de_lo.we=1;\n   force dut.reg_file_.b2v_latch_de_hi.we=1;\n   force dut.reg_file_.b2v_latch_de_lo.db=8'h0d;\n   force dut.reg_file_.b2v_latch_de_hi.db=8'h20;\n#2 release dut.reg_file_.b2v_latch_de_lo.we;\n   release dut.reg_file_.b2v_latch_de_hi.we;\n   release dut.reg_file_.b2v_latch_de_lo.db;\n   release dut.reg_file_.b2v_latch_de_hi.db;\n   // Preset hl\n   force dut.reg_file_.b2v_latch_hl_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl_lo.db=8'ha6;\n   force dut.reg_file_.b2v_latch_hl_hi.db=8'hdc;\n#2 release dut.reg_file_.b2v_latch_hl_lo.we;\n   release dut.reg_file_.b2v_latch_hl_hi.we;\n   release dut.reg_file_.b2v_latch_hl_lo.db;\n   release dut.reg_file_.b2v_latch_hl_hi.db;\n   // Preset af2\n   force dut.reg_file_.b2v_latch_af2_lo.we=1;\n   force dut.reg_file_.b2v_latch_af2_hi.we=1;\n   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_af2_lo.we;\n   release dut.reg_file_.b2v_latch_af2_hi.we;\n   release dut.reg_file_.b2v_latch_af2_lo.db;\n   release dut.reg_file_.b2v_latch_af2_hi.db;\n   // Preset bc2\n   force dut.reg_file_.b2v_latch_bc2_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc2_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_bc2_lo.we;\n   release dut.reg_file_.b2v_latch_bc2_hi.we;\n   release dut.reg_file_.b2v_latch_bc2_lo.db;\n   release dut.reg_file_.b2v_latch_bc2_hi.db;\n   // Preset de2\n   force dut.reg_file_.b2v_latch_de2_lo.we=1;\n   force dut.reg_file_.b2v_latch_de2_hi.we=1;\n   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_de2_lo.we;\n   release dut.reg_file_.b2v_latch_de2_hi.we;\n   release dut.reg_file_.b2v_latch_de2_lo.db;\n   release dut.reg_file_.b2v_latch_de2_hi.db;\n   // Preset hl2\n   force dut.reg_file_.b2v_latch_hl2_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl2_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_hl2_lo.we;\n   release dut.reg_file_.b2v_latch_hl2_hi.we;\n   release dut.reg_file_.b2v_latch_hl2_lo.db;\n   release dut.reg_file_.b2v_latch_hl2_hi.db;\n   // Preset ix\n   force dut.reg_file_.b2v_latch_ix_lo.we=1;\n   force dut.reg_file_.b2v_latch_ix_hi.we=1;\n   force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ix_lo.we;\n   release dut.reg_file_.b2v_latch_ix_hi.we;\n   release dut.reg_file_.b2v_latch_ix_lo.db;\n   release dut.reg_file_.b2v_latch_ix_hi.db;\n   // Preset iy\n   force dut.reg_file_.b2v_latch_iy_lo.we=1;\n   force dut.reg_file_.b2v_latch_iy_hi.we=1;\n   force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_iy_lo.we;\n   release dut.reg_file_.b2v_latch_iy_hi.we;\n   release dut.reg_file_.b2v_latch_iy_lo.db;\n   release dut.reg_file_.b2v_latch_iy_hi.db;\n   // Preset sp\n   force dut.reg_file_.b2v_latch_sp_lo.we=1;\n   force dut.reg_file_.b2v_latch_sp_hi.we=1;\n   force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_sp_lo.we;\n   release dut.reg_file_.b2v_latch_sp_hi.we;\n   release dut.reg_file_.b2v_latch_sp_lo.db;\n   release dut.reg_file_.b2v_latch_sp_hi.db;\n   // Preset wz\n   force dut.reg_file_.b2v_latch_wz_lo.we=1;\n   force dut.reg_file_.b2v_latch_wz_hi.we=1;\n   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_wz_lo.we;\n   release dut.reg_file_.b2v_latch_wz_hi.we;\n   release dut.reg_file_.b2v_latch_wz_lo.db;\n   release dut.reg_file_.b2v_latch_wz_hi.db;\n   // Preset pc\n   force dut.reg_file_.b2v_latch_pc_lo.we=1;\n   force dut.reg_file_.b2v_latch_pc_hi.we=1;\n   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_pc_lo.we;\n   release dut.reg_file_.b2v_latch_pc_hi.we;\n   release dut.reg_file_.b2v_latch_pc_lo.db;\n   release dut.reg_file_.b2v_latch_pc_hi.db;\n   // Preset ir\n   force dut.reg_file_.b2v_latch_ir_lo.we=1;\n   force dut.reg_file_.b2v_latch_ir_hi.we=1;\n   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ir_lo.we;\n   release dut.reg_file_.b2v_latch_ir_hi.we;\n   release dut.reg_file_.b2v_latch_ir_lo.db;\n   release dut.reg_file_.b2v_latch_ir_hi.db;\n   // Preset memory\n   ram.Mem[0] = 8'hbf;\n   // Preset memory\n   ram.Mem[56486] = 8'h49;\n   force dut.z80_top_ifc_n.fpga_reset=0;\n   force dut.address_latch_.Q=16'h0000;\n   release dut.reg_control_.ctl_reg_sys_we;\n   release dut.reg_file_.reg_gp_we;\n#2 // Execute: M1/T1 start\n#1 release dut.address_latch_.Q;\n#1\n#6 // Wait for opcode end\n   force dut.reg_control_.ctl_reg_sys_we=0;\n#2 pc=z.A;\n#2\n#1 force dut.reg_file_.reg_gp_we=0;\n   force dut.z80_top_ifc_n.fpga_reset=1;\n   if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h62) $fdisplay(f,\"* Reg af f=%h !=62\",dut.reg_file_.b2v_latch_af_lo.latch);\n   if (dut.reg_file_.b2v_latch_af_hi.latch!==8'hf5) $fdisplay(f,\"* Reg af a=%h !=f5\",dut.reg_file_.b2v_latch_af_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h3b) $fdisplay(f,\"* Reg bc c=%h !=3b\",dut.reg_file_.b2v_latch_bc_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h0f) $fdisplay(f,\"* Reg bc b=%h !=0f\",dut.reg_file_.b2v_latch_bc_hi.latch);\n   if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h0d) $fdisplay(f,\"* Reg de e=%h !=0d\",dut.reg_file_.b2v_latch_de_lo.latch);\n   if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h20) $fdisplay(f,\"* Reg de d=%h !=20\",dut.reg_file_.b2v_latch_de_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'ha6) $fdisplay(f,\"* Reg hl l=%h !=a6\",dut.reg_file_.b2v_latch_hl_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hdc) $fdisplay(f,\"* Reg hl h=%h !=dc\",dut.reg_file_.b2v_latch_hl_hi.latch);\n   if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,\"* Reg af2 f=%h !=00\",dut.reg_file_.b2v_latch_af2_lo.latch);\n   if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,\"* Reg af2 a=%h !=00\",dut.reg_file_.b2v_latch_af2_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,\"* Reg bc2 c=%h !=00\",dut.reg_file_.b2v_latch_bc2_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,\"* Reg bc2 b=%h !=00\",dut.reg_file_.b2v_latch_bc2_hi.latch);\n   if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,\"* Reg de2 e=%h !=00\",dut.reg_file_.b2v_latch_de2_lo.latch);\n   if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,\"* Reg de2 d=%h !=00\",dut.reg_file_.b2v_latch_de2_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,\"* Reg hl2 l=%h !=00\",dut.reg_file_.b2v_latch_hl2_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,\"* Reg hl2 h=%h !=00\",dut.reg_file_.b2v_latch_hl2_hi.latch);\n   if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,\"* Reg ix x=%h !=00\",dut.reg_file_.b2v_latch_ix_lo.latch);\n   if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,\"* Reg ix i=%h !=00\",dut.reg_file_.b2v_latch_ix_hi.latch);\n   if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,\"* Reg iy y=%h !=00\",dut.reg_file_.b2v_latch_iy_lo.latch);\n   if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,\"* Reg iy i=%h !=00\",dut.reg_file_.b2v_latch_iy_hi.latch);\n   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,\"* Reg sp p=%h !=00\",dut.reg_file_.b2v_latch_sp_lo.latch);\n   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,\"* Reg sp s=%h !=00\",dut.reg_file_.b2v_latch_sp_hi.latch);\n   if (pc!==16'h0001) $fdisplay(f,\"* PC=%h !=0001\",pc);\n   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,\"* Reg ir r=%h !=01\",dut.reg_file_.b2v_latch_ir_lo.latch);\n   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,\"* Reg ir i=%h !=00\",dut.reg_file_.b2v_latch_ir_hi.latch);\n#1 // End opcode\n\n   force dut.ir_.ctl_ir_we=1;\n   force dut.ir_.db=0;\n#2 release dut.ir_.ctl_ir_we;\n   release dut.ir_.db;\n   $fdisplay(f,\"Testing opcode 43      LD B,E\");\n   // Preset af\n   force dut.reg_file_.b2v_latch_af_lo.we=1;\n   force dut.reg_file_.b2v_latch_af_hi.we=1;\n   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af_hi.db=8'h02;\n#2 release dut.reg_file_.b2v_latch_af_lo.we;\n   release dut.reg_file_.b2v_latch_af_hi.we;\n   release dut.reg_file_.b2v_latch_af_lo.db;\n   release dut.reg_file_.b2v_latch_af_hi.db;\n   // Preset bc\n   force dut.reg_file_.b2v_latch_bc_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc_lo.db=8'h98;\n   force dut.reg_file_.b2v_latch_bc_hi.db=8'hcf;\n#2 release dut.reg_file_.b2v_latch_bc_lo.we;\n   release dut.reg_file_.b2v_latch_bc_hi.we;\n   release dut.reg_file_.b2v_latch_bc_lo.db;\n   release dut.reg_file_.b2v_latch_bc_hi.db;\n   // Preset de\n   force dut.reg_file_.b2v_latch_de_lo.we=1;\n   force dut.reg_file_.b2v_latch_de_hi.we=1;\n   force dut.reg_file_.b2v_latch_de_lo.db=8'hd8;\n   force dut.reg_file_.b2v_latch_de_hi.db=8'h90;\n#2 release dut.reg_file_.b2v_latch_de_lo.we;\n   release dut.reg_file_.b2v_latch_de_hi.we;\n   release dut.reg_file_.b2v_latch_de_lo.db;\n   release dut.reg_file_.b2v_latch_de_hi.db;\n   // Preset hl\n   force dut.reg_file_.b2v_latch_hl_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl_lo.db=8'h69;\n   force dut.reg_file_.b2v_latch_hl_hi.db=8'ha1;\n#2 release dut.reg_file_.b2v_latch_hl_lo.we;\n   release dut.reg_file_.b2v_latch_hl_hi.we;\n   release dut.reg_file_.b2v_latch_hl_lo.db;\n   release dut.reg_file_.b2v_latch_hl_hi.db;\n   // Preset af2\n   force dut.reg_file_.b2v_latch_af2_lo.we=1;\n   force dut.reg_file_.b2v_latch_af2_hi.we=1;\n   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_af2_lo.we;\n   release dut.reg_file_.b2v_latch_af2_hi.we;\n   release dut.reg_file_.b2v_latch_af2_lo.db;\n   release dut.reg_file_.b2v_latch_af2_hi.db;\n   // Preset bc2\n   force dut.reg_file_.b2v_latch_bc2_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc2_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_bc2_lo.we;\n   release dut.reg_file_.b2v_latch_bc2_hi.we;\n   release dut.reg_file_.b2v_latch_bc2_lo.db;\n   release dut.reg_file_.b2v_latch_bc2_hi.db;\n   // Preset de2\n   force dut.reg_file_.b2v_latch_de2_lo.we=1;\n   force dut.reg_file_.b2v_latch_de2_hi.we=1;\n   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_de2_lo.we;\n   release dut.reg_file_.b2v_latch_de2_hi.we;\n   release dut.reg_file_.b2v_latch_de2_lo.db;\n   release dut.reg_file_.b2v_latch_de2_hi.db;\n   // Preset hl2\n   force dut.reg_file_.b2v_latch_hl2_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl2_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_hl2_lo.we;\n   release dut.reg_file_.b2v_latch_hl2_hi.we;\n   release dut.reg_file_.b2v_latch_hl2_lo.db;\n   release dut.reg_file_.b2v_latch_hl2_hi.db;\n   // Preset ix\n   force dut.reg_file_.b2v_latch_ix_lo.we=1;\n   force dut.reg_file_.b2v_latch_ix_hi.we=1;\n   force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ix_lo.we;\n   release dut.reg_file_.b2v_latch_ix_hi.we;\n   release dut.reg_file_.b2v_latch_ix_lo.db;\n   release dut.reg_file_.b2v_latch_ix_hi.db;\n   // Preset iy\n   force dut.reg_file_.b2v_latch_iy_lo.we=1;\n   force dut.reg_file_.b2v_latch_iy_hi.we=1;\n   force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_iy_lo.we;\n   release dut.reg_file_.b2v_latch_iy_hi.we;\n   release dut.reg_file_.b2v_latch_iy_lo.db;\n   release dut.reg_file_.b2v_latch_iy_hi.db;\n   // Preset sp\n   force dut.reg_file_.b2v_latch_sp_lo.we=1;\n   force dut.reg_file_.b2v_latch_sp_hi.we=1;\n   force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_sp_lo.we;\n   release dut.reg_file_.b2v_latch_sp_hi.we;\n   release dut.reg_file_.b2v_latch_sp_lo.db;\n   release dut.reg_file_.b2v_latch_sp_hi.db;\n   // Preset wz\n   force dut.reg_file_.b2v_latch_wz_lo.we=1;\n   force dut.reg_file_.b2v_latch_wz_hi.we=1;\n   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_wz_lo.we;\n   release dut.reg_file_.b2v_latch_wz_hi.we;\n   release dut.reg_file_.b2v_latch_wz_lo.db;\n   release dut.reg_file_.b2v_latch_wz_hi.db;\n   // Preset pc\n   force dut.reg_file_.b2v_latch_pc_lo.we=1;\n   force dut.reg_file_.b2v_latch_pc_hi.we=1;\n   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_pc_lo.we;\n   release dut.reg_file_.b2v_latch_pc_hi.we;\n   release dut.reg_file_.b2v_latch_pc_lo.db;\n   release dut.reg_file_.b2v_latch_pc_hi.db;\n   // Preset ir\n   force dut.reg_file_.b2v_latch_ir_lo.we=1;\n   force dut.reg_file_.b2v_latch_ir_hi.we=1;\n   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ir_lo.we;\n   release dut.reg_file_.b2v_latch_ir_hi.we;\n   release dut.reg_file_.b2v_latch_ir_lo.db;\n   release dut.reg_file_.b2v_latch_ir_hi.db;\n   // Preset memory\n   ram.Mem[0] = 8'h43;\n   // Preset memory\n   ram.Mem[41321] = 8'h50;\n   force dut.z80_top_ifc_n.fpga_reset=0;\n   force dut.address_latch_.Q=16'h0000;\n   release dut.reg_control_.ctl_reg_sys_we;\n   release dut.reg_file_.reg_gp_we;\n#2 // Execute: M1/T1 start\n#1 release dut.address_latch_.Q;\n#1\n#6 // Wait for opcode end\n   force dut.reg_control_.ctl_reg_sys_we=0;\n#2 pc=z.A;\n#2\n#1 force dut.reg_file_.reg_gp_we=0;\n   force dut.z80_top_ifc_n.fpga_reset=1;\n   if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h00) $fdisplay(f,\"* Reg af f=%h !=00\",dut.reg_file_.b2v_latch_af_lo.latch);\n   if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h02) $fdisplay(f,\"* Reg af a=%h !=02\",dut.reg_file_.b2v_latch_af_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h98) $fdisplay(f,\"* Reg bc c=%h !=98\",dut.reg_file_.b2v_latch_bc_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'hd8) $fdisplay(f,\"* Reg bc b=%h !=d8\",dut.reg_file_.b2v_latch_bc_hi.latch);\n   if (dut.reg_file_.b2v_latch_de_lo.latch!==8'hd8) $fdisplay(f,\"* Reg de e=%h !=d8\",dut.reg_file_.b2v_latch_de_lo.latch);\n   if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h90) $fdisplay(f,\"* Reg de d=%h !=90\",dut.reg_file_.b2v_latch_de_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h69) $fdisplay(f,\"* Reg hl l=%h !=69\",dut.reg_file_.b2v_latch_hl_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'ha1) $fdisplay(f,\"* Reg hl h=%h !=a1\",dut.reg_file_.b2v_latch_hl_hi.latch);\n   if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,\"* Reg af2 f=%h !=00\",dut.reg_file_.b2v_latch_af2_lo.latch);\n   if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,\"* Reg af2 a=%h !=00\",dut.reg_file_.b2v_latch_af2_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,\"* Reg bc2 c=%h !=00\",dut.reg_file_.b2v_latch_bc2_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,\"* Reg bc2 b=%h !=00\",dut.reg_file_.b2v_latch_bc2_hi.latch);\n   if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,\"* Reg de2 e=%h !=00\",dut.reg_file_.b2v_latch_de2_lo.latch);\n   if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,\"* Reg de2 d=%h !=00\",dut.reg_file_.b2v_latch_de2_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,\"* Reg hl2 l=%h !=00\",dut.reg_file_.b2v_latch_hl2_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,\"* Reg hl2 h=%h !=00\",dut.reg_file_.b2v_latch_hl2_hi.latch);\n   if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,\"* Reg ix x=%h !=00\",dut.reg_file_.b2v_latch_ix_lo.latch);\n   if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,\"* Reg ix i=%h !=00\",dut.reg_file_.b2v_latch_ix_hi.latch);\n   if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,\"* Reg iy y=%h !=00\",dut.reg_file_.b2v_latch_iy_lo.latch);\n   if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,\"* Reg iy i=%h !=00\",dut.reg_file_.b2v_latch_iy_hi.latch);\n   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,\"* Reg sp p=%h !=00\",dut.reg_file_.b2v_latch_sp_lo.latch);\n   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,\"* Reg sp s=%h !=00\",dut.reg_file_.b2v_latch_sp_hi.latch);\n   if (pc!==16'h0001) $fdisplay(f,\"* PC=%h !=0001\",pc);\n   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,\"* Reg ir r=%h !=01\",dut.reg_file_.b2v_latch_ir_lo.latch);\n   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,\"* Reg ir i=%h !=00\",dut.reg_file_.b2v_latch_ir_hi.latch);\n#1 // End opcode\n\n   force dut.ir_.ctl_ir_we=1;\n   force dut.ir_.db=0;\n#2 release dut.ir_.ctl_ir_we;\n   release dut.ir_.db;\n   $fdisplay(f,\"Testing opcode 6e      LD L,(HL)\");\n   // Preset af\n   force dut.reg_file_.b2v_latch_af_lo.we=1;\n   force dut.reg_file_.b2v_latch_af_hi.we=1;\n   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af_hi.db=8'h02;\n#2 release dut.reg_file_.b2v_latch_af_lo.we;\n   release dut.reg_file_.b2v_latch_af_hi.we;\n   release dut.reg_file_.b2v_latch_af_lo.db;\n   release dut.reg_file_.b2v_latch_af_hi.db;\n   // Preset bc\n   force dut.reg_file_.b2v_latch_bc_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc_lo.db=8'h98;\n   force dut.reg_file_.b2v_latch_bc_hi.db=8'hcf;\n#2 release dut.reg_file_.b2v_latch_bc_lo.we;\n   release dut.reg_file_.b2v_latch_bc_hi.we;\n   release dut.reg_file_.b2v_latch_bc_lo.db;\n   release dut.reg_file_.b2v_latch_bc_hi.db;\n   // Preset de\n   force dut.reg_file_.b2v_latch_de_lo.we=1;\n   force dut.reg_file_.b2v_latch_de_hi.we=1;\n   force dut.reg_file_.b2v_latch_de_lo.db=8'hd8;\n   force dut.reg_file_.b2v_latch_de_hi.db=8'h90;\n#2 release dut.reg_file_.b2v_latch_de_lo.we;\n   release dut.reg_file_.b2v_latch_de_hi.we;\n   release dut.reg_file_.b2v_latch_de_lo.db;\n   release dut.reg_file_.b2v_latch_de_hi.db;\n   // Preset hl\n   force dut.reg_file_.b2v_latch_hl_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl_lo.db=8'h69;\n   force dut.reg_file_.b2v_latch_hl_hi.db=8'ha1;\n#2 release dut.reg_file_.b2v_latch_hl_lo.we;\n   release dut.reg_file_.b2v_latch_hl_hi.we;\n   release dut.reg_file_.b2v_latch_hl_lo.db;\n   release dut.reg_file_.b2v_latch_hl_hi.db;\n   // Preset af2\n   force dut.reg_file_.b2v_latch_af2_lo.we=1;\n   force dut.reg_file_.b2v_latch_af2_hi.we=1;\n   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_af2_lo.we;\n   release dut.reg_file_.b2v_latch_af2_hi.we;\n   release dut.reg_file_.b2v_latch_af2_lo.db;\n   release dut.reg_file_.b2v_latch_af2_hi.db;\n   // Preset bc2\n   force dut.reg_file_.b2v_latch_bc2_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc2_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_bc2_lo.we;\n   release dut.reg_file_.b2v_latch_bc2_hi.we;\n   release dut.reg_file_.b2v_latch_bc2_lo.db;\n   release dut.reg_file_.b2v_latch_bc2_hi.db;\n   // Preset de2\n   force dut.reg_file_.b2v_latch_de2_lo.we=1;\n   force dut.reg_file_.b2v_latch_de2_hi.we=1;\n   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_de2_lo.we;\n   release dut.reg_file_.b2v_latch_de2_hi.we;\n   release dut.reg_file_.b2v_latch_de2_lo.db;\n   release dut.reg_file_.b2v_latch_de2_hi.db;\n   // Preset hl2\n   force dut.reg_file_.b2v_latch_hl2_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl2_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_hl2_lo.we;\n   release dut.reg_file_.b2v_latch_hl2_hi.we;\n   release dut.reg_file_.b2v_latch_hl2_lo.db;\n   release dut.reg_file_.b2v_latch_hl2_hi.db;\n   // Preset ix\n   force dut.reg_file_.b2v_latch_ix_lo.we=1;\n   force dut.reg_file_.b2v_latch_ix_hi.we=1;\n   force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ix_lo.we;\n   release dut.reg_file_.b2v_latch_ix_hi.we;\n   release dut.reg_file_.b2v_latch_ix_lo.db;\n   release dut.reg_file_.b2v_latch_ix_hi.db;\n   // Preset iy\n   force dut.reg_file_.b2v_latch_iy_lo.we=1;\n   force dut.reg_file_.b2v_latch_iy_hi.we=1;\n   force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_iy_lo.we;\n   release dut.reg_file_.b2v_latch_iy_hi.we;\n   release dut.reg_file_.b2v_latch_iy_lo.db;\n   release dut.reg_file_.b2v_latch_iy_hi.db;\n   // Preset sp\n   force dut.reg_file_.b2v_latch_sp_lo.we=1;\n   force dut.reg_file_.b2v_latch_sp_hi.we=1;\n   force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_sp_lo.we;\n   release dut.reg_file_.b2v_latch_sp_hi.we;\n   release dut.reg_file_.b2v_latch_sp_lo.db;\n   release dut.reg_file_.b2v_latch_sp_hi.db;\n   // Preset wz\n   force dut.reg_file_.b2v_latch_wz_lo.we=1;\n   force dut.reg_file_.b2v_latch_wz_hi.we=1;\n   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_wz_lo.we;\n   release dut.reg_file_.b2v_latch_wz_hi.we;\n   release dut.reg_file_.b2v_latch_wz_lo.db;\n   release dut.reg_file_.b2v_latch_wz_hi.db;\n   // Preset pc\n   force dut.reg_file_.b2v_latch_pc_lo.we=1;\n   force dut.reg_file_.b2v_latch_pc_hi.we=1;\n   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_pc_lo.we;\n   release dut.reg_file_.b2v_latch_pc_hi.we;\n   release dut.reg_file_.b2v_latch_pc_lo.db;\n   release dut.reg_file_.b2v_latch_pc_hi.db;\n   // Preset ir\n   force dut.reg_file_.b2v_latch_ir_lo.we=1;\n   force dut.reg_file_.b2v_latch_ir_hi.we=1;\n   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ir_lo.we;\n   release dut.reg_file_.b2v_latch_ir_hi.we;\n   release dut.reg_file_.b2v_latch_ir_lo.db;\n   release dut.reg_file_.b2v_latch_ir_hi.db;\n   // Preset memory\n   ram.Mem[0] = 8'h6e;\n   // Preset memory\n   ram.Mem[41321] = 8'h50;\n   force dut.z80_top_ifc_n.fpga_reset=0;\n   force dut.address_latch_.Q=16'h0000;\n   release dut.reg_control_.ctl_reg_sys_we;\n   release dut.reg_file_.reg_gp_we;\n#2 // Execute: M1/T1 start\n#1 release dut.address_latch_.Q;\n#1\n#12 // Wait for opcode end\n   force dut.reg_control_.ctl_reg_sys_we=0;\n#2 pc=z.A;\n#2\n#1 force dut.reg_file_.reg_gp_we=0;\n   force dut.z80_top_ifc_n.fpga_reset=1;\n   if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h00) $fdisplay(f,\"* Reg af f=%h !=00\",dut.reg_file_.b2v_latch_af_lo.latch);\n   if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h02) $fdisplay(f,\"* Reg af a=%h !=02\",dut.reg_file_.b2v_latch_af_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h98) $fdisplay(f,\"* Reg bc c=%h !=98\",dut.reg_file_.b2v_latch_bc_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'hcf) $fdisplay(f,\"* Reg bc b=%h !=cf\",dut.reg_file_.b2v_latch_bc_hi.latch);\n   if (dut.reg_file_.b2v_latch_de_lo.latch!==8'hd8) $fdisplay(f,\"* Reg de e=%h !=d8\",dut.reg_file_.b2v_latch_de_lo.latch);\n   if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h90) $fdisplay(f,\"* Reg de d=%h !=90\",dut.reg_file_.b2v_latch_de_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h50) $fdisplay(f,\"* Reg hl l=%h !=50\",dut.reg_file_.b2v_latch_hl_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'ha1) $fdisplay(f,\"* Reg hl h=%h !=a1\",dut.reg_file_.b2v_latch_hl_hi.latch);\n   if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,\"* Reg af2 f=%h !=00\",dut.reg_file_.b2v_latch_af2_lo.latch);\n   if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,\"* Reg af2 a=%h !=00\",dut.reg_file_.b2v_latch_af2_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,\"* Reg bc2 c=%h !=00\",dut.reg_file_.b2v_latch_bc2_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,\"* Reg bc2 b=%h !=00\",dut.reg_file_.b2v_latch_bc2_hi.latch);\n   if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,\"* Reg de2 e=%h !=00\",dut.reg_file_.b2v_latch_de2_lo.latch);\n   if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,\"* Reg de2 d=%h !=00\",dut.reg_file_.b2v_latch_de2_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,\"* Reg hl2 l=%h !=00\",dut.reg_file_.b2v_latch_hl2_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,\"* Reg hl2 h=%h !=00\",dut.reg_file_.b2v_latch_hl2_hi.latch);\n   if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,\"* Reg ix x=%h !=00\",dut.reg_file_.b2v_latch_ix_lo.latch);\n   if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,\"* Reg ix i=%h !=00\",dut.reg_file_.b2v_latch_ix_hi.latch);\n   if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,\"* Reg iy y=%h !=00\",dut.reg_file_.b2v_latch_iy_lo.latch);\n   if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,\"* Reg iy i=%h !=00\",dut.reg_file_.b2v_latch_iy_hi.latch);\n   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,\"* Reg sp p=%h !=00\",dut.reg_file_.b2v_latch_sp_lo.latch);\n   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,\"* Reg sp s=%h !=00\",dut.reg_file_.b2v_latch_sp_hi.latch);\n   if (pc!==16'h0001) $fdisplay(f,\"* PC=%h !=0001\",pc);\n   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,\"* Reg ir r=%h !=01\",dut.reg_file_.b2v_latch_ir_lo.latch);\n   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,\"* Reg ir i=%h !=00\",dut.reg_file_.b2v_latch_ir_hi.latch);\n#1 // End opcode\n\n   force dut.ir_.ctl_ir_we=1;\n   force dut.ir_.db=0;\n#2 release dut.ir_.ctl_ir_we;\n   release dut.ir_.db;\n   $fdisplay(f,\"Testing opcode e3      EX (SP),HL\");\n   // Preset af\n   force dut.reg_file_.b2v_latch_af_lo.we=1;\n   force dut.reg_file_.b2v_latch_af_hi.we=1;\n   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_af_lo.we;\n   release dut.reg_file_.b2v_latch_af_hi.we;\n   release dut.reg_file_.b2v_latch_af_lo.db;\n   release dut.reg_file_.b2v_latch_af_hi.db;\n   // Preset bc\n   force dut.reg_file_.b2v_latch_bc_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_bc_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_bc_lo.we;\n   release dut.reg_file_.b2v_latch_bc_hi.we;\n   release dut.reg_file_.b2v_latch_bc_lo.db;\n   release dut.reg_file_.b2v_latch_bc_hi.db;\n   // Preset de\n   force dut.reg_file_.b2v_latch_de_lo.we=1;\n   force dut.reg_file_.b2v_latch_de_hi.we=1;\n   force dut.reg_file_.b2v_latch_de_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_de_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_de_lo.we;\n   release dut.reg_file_.b2v_latch_de_hi.we;\n   release dut.reg_file_.b2v_latch_de_lo.db;\n   release dut.reg_file_.b2v_latch_de_hi.db;\n   // Preset hl\n   force dut.reg_file_.b2v_latch_hl_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl_lo.db=8'h22;\n   force dut.reg_file_.b2v_latch_hl_hi.db=8'h4d;\n#2 release dut.reg_file_.b2v_latch_hl_lo.we;\n   release dut.reg_file_.b2v_latch_hl_hi.we;\n   release dut.reg_file_.b2v_latch_hl_lo.db;\n   release dut.reg_file_.b2v_latch_hl_hi.db;\n   // Preset af2\n   force dut.reg_file_.b2v_latch_af2_lo.we=1;\n   force dut.reg_file_.b2v_latch_af2_hi.we=1;\n   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_af2_lo.we;\n   release dut.reg_file_.b2v_latch_af2_hi.we;\n   release dut.reg_file_.b2v_latch_af2_lo.db;\n   release dut.reg_file_.b2v_latch_af2_hi.db;\n   // Preset bc2\n   force dut.reg_file_.b2v_latch_bc2_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc2_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_bc2_lo.we;\n   release dut.reg_file_.b2v_latch_bc2_hi.we;\n   release dut.reg_file_.b2v_latch_bc2_lo.db;\n   release dut.reg_file_.b2v_latch_bc2_hi.db;\n   // Preset de2\n   force dut.reg_file_.b2v_latch_de2_lo.we=1;\n   force dut.reg_file_.b2v_latch_de2_hi.we=1;\n   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_de2_lo.we;\n   release dut.reg_file_.b2v_latch_de2_hi.we;\n   release dut.reg_file_.b2v_latch_de2_lo.db;\n   release dut.reg_file_.b2v_latch_de2_hi.db;\n   // Preset hl2\n   force dut.reg_file_.b2v_latch_hl2_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl2_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_hl2_lo.we;\n   release dut.reg_file_.b2v_latch_hl2_hi.we;\n   release dut.reg_file_.b2v_latch_hl2_lo.db;\n   release dut.reg_file_.b2v_latch_hl2_hi.db;\n   // Preset ix\n   force dut.reg_file_.b2v_latch_ix_lo.we=1;\n   force dut.reg_file_.b2v_latch_ix_hi.we=1;\n   force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ix_lo.we;\n   release dut.reg_file_.b2v_latch_ix_hi.we;\n   release dut.reg_file_.b2v_latch_ix_lo.db;\n   release dut.reg_file_.b2v_latch_ix_hi.db;\n   // Preset iy\n   force dut.reg_file_.b2v_latch_iy_lo.we=1;\n   force dut.reg_file_.b2v_latch_iy_hi.we=1;\n   force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_iy_lo.we;\n   release dut.reg_file_.b2v_latch_iy_hi.we;\n   release dut.reg_file_.b2v_latch_iy_lo.db;\n   release dut.reg_file_.b2v_latch_iy_hi.db;\n   // Preset sp\n   force dut.reg_file_.b2v_latch_sp_lo.we=1;\n   force dut.reg_file_.b2v_latch_sp_hi.we=1;\n   force dut.reg_file_.b2v_latch_sp_lo.db=8'h73;\n   force dut.reg_file_.b2v_latch_sp_hi.db=8'h03;\n#2 release dut.reg_file_.b2v_latch_sp_lo.we;\n   release dut.reg_file_.b2v_latch_sp_hi.we;\n   release dut.reg_file_.b2v_latch_sp_lo.db;\n   release dut.reg_file_.b2v_latch_sp_hi.db;\n   // Preset wz\n   force dut.reg_file_.b2v_latch_wz_lo.we=1;\n   force dut.reg_file_.b2v_latch_wz_hi.we=1;\n   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_wz_lo.we;\n   release dut.reg_file_.b2v_latch_wz_hi.we;\n   release dut.reg_file_.b2v_latch_wz_lo.db;\n   release dut.reg_file_.b2v_latch_wz_hi.db;\n   // Preset pc\n   force dut.reg_file_.b2v_latch_pc_lo.we=1;\n   force dut.reg_file_.b2v_latch_pc_hi.we=1;\n   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_pc_lo.we;\n   release dut.reg_file_.b2v_latch_pc_hi.we;\n   release dut.reg_file_.b2v_latch_pc_lo.db;\n   release dut.reg_file_.b2v_latch_pc_hi.db;\n   // Preset ir\n   force dut.reg_file_.b2v_latch_ir_lo.we=1;\n   force dut.reg_file_.b2v_latch_ir_hi.we=1;\n   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ir_lo.we;\n   release dut.reg_file_.b2v_latch_ir_hi.we;\n   release dut.reg_file_.b2v_latch_ir_lo.db;\n   release dut.reg_file_.b2v_latch_ir_hi.db;\n   // Preset memory\n   ram.Mem[0] = 8'he3;\n   // Preset memory\n   ram.Mem[883] = 8'h8e;\n   ram.Mem[884] = 8'he1;\n   force dut.z80_top_ifc_n.fpga_reset=0;\n   force dut.address_latch_.Q=16'h0000;\n   release dut.reg_control_.ctl_reg_sys_we;\n   release dut.reg_file_.reg_gp_we;\n#2 // Execute: M1/T1 start\n#1 release dut.address_latch_.Q;\n#1\n#36 // Wait for opcode end\n   force dut.reg_control_.ctl_reg_sys_we=0;\n#2 pc=z.A;\n#2\n#1 force dut.reg_file_.reg_gp_we=0;\n   force dut.z80_top_ifc_n.fpga_reset=1;\n   if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h00) $fdisplay(f,\"* Reg af f=%h !=00\",dut.reg_file_.b2v_latch_af_lo.latch);\n   if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h00) $fdisplay(f,\"* Reg af a=%h !=00\",dut.reg_file_.b2v_latch_af_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h00) $fdisplay(f,\"* Reg bc c=%h !=00\",dut.reg_file_.b2v_latch_bc_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h00) $fdisplay(f,\"* Reg bc b=%h !=00\",dut.reg_file_.b2v_latch_bc_hi.latch);\n   if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h00) $fdisplay(f,\"* Reg de e=%h !=00\",dut.reg_file_.b2v_latch_de_lo.latch);\n   if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h00) $fdisplay(f,\"* Reg de d=%h !=00\",dut.reg_file_.b2v_latch_de_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h8e) $fdisplay(f,\"* Reg hl l=%h !=8e\",dut.reg_file_.b2v_latch_hl_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'he1) $fdisplay(f,\"* Reg hl h=%h !=e1\",dut.reg_file_.b2v_latch_hl_hi.latch);\n   if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,\"* Reg af2 f=%h !=00\",dut.reg_file_.b2v_latch_af2_lo.latch);\n   if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,\"* Reg af2 a=%h !=00\",dut.reg_file_.b2v_latch_af2_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,\"* Reg bc2 c=%h !=00\",dut.reg_file_.b2v_latch_bc2_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,\"* Reg bc2 b=%h !=00\",dut.reg_file_.b2v_latch_bc2_hi.latch);\n   if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,\"* Reg de2 e=%h !=00\",dut.reg_file_.b2v_latch_de2_lo.latch);\n   if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,\"* Reg de2 d=%h !=00\",dut.reg_file_.b2v_latch_de2_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,\"* Reg hl2 l=%h !=00\",dut.reg_file_.b2v_latch_hl2_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,\"* Reg hl2 h=%h !=00\",dut.reg_file_.b2v_latch_hl2_hi.latch);\n   if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,\"* Reg ix x=%h !=00\",dut.reg_file_.b2v_latch_ix_lo.latch);\n   if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,\"* Reg ix i=%h !=00\",dut.reg_file_.b2v_latch_ix_hi.latch);\n   if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,\"* Reg iy y=%h !=00\",dut.reg_file_.b2v_latch_iy_lo.latch);\n   if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,\"* Reg iy i=%h !=00\",dut.reg_file_.b2v_latch_iy_hi.latch);\n   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h73) $fdisplay(f,\"* Reg sp p=%h !=73\",dut.reg_file_.b2v_latch_sp_lo.latch);\n   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h03) $fdisplay(f,\"* Reg sp s=%h !=03\",dut.reg_file_.b2v_latch_sp_hi.latch);\n   if (pc!==16'h0001) $fdisplay(f,\"* PC=%h !=0001\",pc);\n   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,\"* Reg ir r=%h !=01\",dut.reg_file_.b2v_latch_ir_lo.latch);\n   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,\"* Reg ir i=%h !=00\",dut.reg_file_.b2v_latch_ir_hi.latch);\n   if (ram.Mem[883]!==8'h22) $fdisplay(f,\"* Mem[373]=%h !=22\",ram.Mem[883]);\n   if (ram.Mem[884]!==8'h4d) $fdisplay(f,\"* Mem[374]=%h !=4d\",ram.Mem[884]);\n#1 // End opcode\n\n   force dut.ir_.ctl_ir_we=1;\n   force dut.ir_.db=0;\n#2 release dut.ir_.ctl_ir_we;\n   release dut.ir_.db;\n   $fdisplay(f,\"Testing opcode 03      INC BC\");\n   // Preset af\n   force dut.reg_file_.b2v_latch_af_lo.we=1;\n   force dut.reg_file_.b2v_latch_af_hi.we=1;\n   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_af_lo.we;\n   release dut.reg_file_.b2v_latch_af_hi.we;\n   release dut.reg_file_.b2v_latch_af_lo.db;\n   release dut.reg_file_.b2v_latch_af_hi.db;\n   // Preset bc\n   force dut.reg_file_.b2v_latch_bc_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc_lo.db=8'h9a;\n   force dut.reg_file_.b2v_latch_bc_hi.db=8'h78;\n#2 release dut.reg_file_.b2v_latch_bc_lo.we;\n   release dut.reg_file_.b2v_latch_bc_hi.we;\n   release dut.reg_file_.b2v_latch_bc_lo.db;\n   release dut.reg_file_.b2v_latch_bc_hi.db;\n   // Preset de\n   force dut.reg_file_.b2v_latch_de_lo.we=1;\n   force dut.reg_file_.b2v_latch_de_hi.we=1;\n   force dut.reg_file_.b2v_latch_de_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_de_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_de_lo.we;\n   release dut.reg_file_.b2v_latch_de_hi.we;\n   release dut.reg_file_.b2v_latch_de_lo.db;\n   release dut.reg_file_.b2v_latch_de_hi.db;\n   // Preset hl\n   force dut.reg_file_.b2v_latch_hl_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_hl_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_hl_lo.we;\n   release dut.reg_file_.b2v_latch_hl_hi.we;\n   release dut.reg_file_.b2v_latch_hl_lo.db;\n   release dut.reg_file_.b2v_latch_hl_hi.db;\n   // Preset af2\n   force dut.reg_file_.b2v_latch_af2_lo.we=1;\n   force dut.reg_file_.b2v_latch_af2_hi.we=1;\n   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_af2_lo.we;\n   release dut.reg_file_.b2v_latch_af2_hi.we;\n   release dut.reg_file_.b2v_latch_af2_lo.db;\n   release dut.reg_file_.b2v_latch_af2_hi.db;\n   // Preset bc2\n   force dut.reg_file_.b2v_latch_bc2_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc2_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_bc2_lo.we;\n   release dut.reg_file_.b2v_latch_bc2_hi.we;\n   release dut.reg_file_.b2v_latch_bc2_lo.db;\n   release dut.reg_file_.b2v_latch_bc2_hi.db;\n   // Preset de2\n   force dut.reg_file_.b2v_latch_de2_lo.we=1;\n   force dut.reg_file_.b2v_latch_de2_hi.we=1;\n   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_de2_lo.we;\n   release dut.reg_file_.b2v_latch_de2_hi.we;\n   release dut.reg_file_.b2v_latch_de2_lo.db;\n   release dut.reg_file_.b2v_latch_de2_hi.db;\n   // Preset hl2\n   force dut.reg_file_.b2v_latch_hl2_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl2_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_hl2_lo.we;\n   release dut.reg_file_.b2v_latch_hl2_hi.we;\n   release dut.reg_file_.b2v_latch_hl2_lo.db;\n   release dut.reg_file_.b2v_latch_hl2_hi.db;\n   // Preset ix\n   force dut.reg_file_.b2v_latch_ix_lo.we=1;\n   force dut.reg_file_.b2v_latch_ix_hi.we=1;\n   force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ix_lo.we;\n   release dut.reg_file_.b2v_latch_ix_hi.we;\n   release dut.reg_file_.b2v_latch_ix_lo.db;\n   release dut.reg_file_.b2v_latch_ix_hi.db;\n   // Preset iy\n   force dut.reg_file_.b2v_latch_iy_lo.we=1;\n   force dut.reg_file_.b2v_latch_iy_hi.we=1;\n   force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_iy_lo.we;\n   release dut.reg_file_.b2v_latch_iy_hi.we;\n   release dut.reg_file_.b2v_latch_iy_lo.db;\n   release dut.reg_file_.b2v_latch_iy_hi.db;\n   // Preset sp\n   force dut.reg_file_.b2v_latch_sp_lo.we=1;\n   force dut.reg_file_.b2v_latch_sp_hi.we=1;\n   force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_sp_lo.we;\n   release dut.reg_file_.b2v_latch_sp_hi.we;\n   release dut.reg_file_.b2v_latch_sp_lo.db;\n   release dut.reg_file_.b2v_latch_sp_hi.db;\n   // Preset wz\n   force dut.reg_file_.b2v_latch_wz_lo.we=1;\n   force dut.reg_file_.b2v_latch_wz_hi.we=1;\n   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_wz_lo.we;\n   release dut.reg_file_.b2v_latch_wz_hi.we;\n   release dut.reg_file_.b2v_latch_wz_lo.db;\n   release dut.reg_file_.b2v_latch_wz_hi.db;\n   // Preset pc\n   force dut.reg_file_.b2v_latch_pc_lo.we=1;\n   force dut.reg_file_.b2v_latch_pc_hi.we=1;\n   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_pc_lo.we;\n   release dut.reg_file_.b2v_latch_pc_hi.we;\n   release dut.reg_file_.b2v_latch_pc_lo.db;\n   release dut.reg_file_.b2v_latch_pc_hi.db;\n   // Preset ir\n   force dut.reg_file_.b2v_latch_ir_lo.we=1;\n   force dut.reg_file_.b2v_latch_ir_hi.we=1;\n   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ir_lo.we;\n   release dut.reg_file_.b2v_latch_ir_hi.we;\n   release dut.reg_file_.b2v_latch_ir_lo.db;\n   release dut.reg_file_.b2v_latch_ir_hi.db;\n   // Preset memory\n   ram.Mem[0] = 8'h03;\n   force dut.z80_top_ifc_n.fpga_reset=0;\n   force dut.address_latch_.Q=16'h0000;\n   release dut.reg_control_.ctl_reg_sys_we;\n   release dut.reg_file_.reg_gp_we;\n#2 // Execute: M1/T1 start\n#1 release dut.address_latch_.Q;\n#1\n#10 // Wait for opcode end\n   force dut.reg_control_.ctl_reg_sys_we=0;\n#2 pc=z.A;\n#2\n#1 force dut.reg_file_.reg_gp_we=0;\n   force dut.z80_top_ifc_n.fpga_reset=1;\n   if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h00) $fdisplay(f,\"* Reg af f=%h !=00\",dut.reg_file_.b2v_latch_af_lo.latch);\n   if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h00) $fdisplay(f,\"* Reg af a=%h !=00\",dut.reg_file_.b2v_latch_af_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h9b) $fdisplay(f,\"* Reg bc c=%h !=9b\",dut.reg_file_.b2v_latch_bc_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h78) $fdisplay(f,\"* Reg bc b=%h !=78\",dut.reg_file_.b2v_latch_bc_hi.latch);\n   if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h00) $fdisplay(f,\"* Reg de e=%h !=00\",dut.reg_file_.b2v_latch_de_lo.latch);\n   if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h00) $fdisplay(f,\"* Reg de d=%h !=00\",dut.reg_file_.b2v_latch_de_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h00) $fdisplay(f,\"* Reg hl l=%h !=00\",dut.reg_file_.b2v_latch_hl_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h00) $fdisplay(f,\"* Reg hl h=%h !=00\",dut.reg_file_.b2v_latch_hl_hi.latch);\n   if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,\"* Reg af2 f=%h !=00\",dut.reg_file_.b2v_latch_af2_lo.latch);\n   if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,\"* Reg af2 a=%h !=00\",dut.reg_file_.b2v_latch_af2_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,\"* Reg bc2 c=%h !=00\",dut.reg_file_.b2v_latch_bc2_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,\"* Reg bc2 b=%h !=00\",dut.reg_file_.b2v_latch_bc2_hi.latch);\n   if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,\"* Reg de2 e=%h !=00\",dut.reg_file_.b2v_latch_de2_lo.latch);\n   if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,\"* Reg de2 d=%h !=00\",dut.reg_file_.b2v_latch_de2_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,\"* Reg hl2 l=%h !=00\",dut.reg_file_.b2v_latch_hl2_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,\"* Reg hl2 h=%h !=00\",dut.reg_file_.b2v_latch_hl2_hi.latch);\n   if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,\"* Reg ix x=%h !=00\",dut.reg_file_.b2v_latch_ix_lo.latch);\n   if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,\"* Reg ix i=%h !=00\",dut.reg_file_.b2v_latch_ix_hi.latch);\n   if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,\"* Reg iy y=%h !=00\",dut.reg_file_.b2v_latch_iy_lo.latch);\n   if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,\"* Reg iy i=%h !=00\",dut.reg_file_.b2v_latch_iy_hi.latch);\n   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,\"* Reg sp p=%h !=00\",dut.reg_file_.b2v_latch_sp_lo.latch);\n   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,\"* Reg sp s=%h !=00\",dut.reg_file_.b2v_latch_sp_hi.latch);\n   if (pc!==16'h0001) $fdisplay(f,\"* PC=%h !=0001\",pc);\n   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,\"* Reg ir r=%h !=01\",dut.reg_file_.b2v_latch_ir_lo.latch);\n   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,\"* Reg ir i=%h !=00\",dut.reg_file_.b2v_latch_ir_hi.latch);\n#1 // End opcode\n\n   force dut.ir_.ctl_ir_we=1;\n   force dut.ir_.db=0;\n#2 release dut.ir_.ctl_ir_we;\n   release dut.ir_.db;\n   $fdisplay(f,\"Testing opcode 3b      DEC SP\");\n   // Preset af\n   force dut.reg_file_.b2v_latch_af_lo.we=1;\n   force dut.reg_file_.b2v_latch_af_hi.we=1;\n   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_af_lo.we;\n   release dut.reg_file_.b2v_latch_af_hi.we;\n   release dut.reg_file_.b2v_latch_af_lo.db;\n   release dut.reg_file_.b2v_latch_af_hi.db;\n   // Preset bc\n   force dut.reg_file_.b2v_latch_bc_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_bc_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_bc_lo.we;\n   release dut.reg_file_.b2v_latch_bc_hi.we;\n   release dut.reg_file_.b2v_latch_bc_lo.db;\n   release dut.reg_file_.b2v_latch_bc_hi.db;\n   // Preset de\n   force dut.reg_file_.b2v_latch_de_lo.we=1;\n   force dut.reg_file_.b2v_latch_de_hi.we=1;\n   force dut.reg_file_.b2v_latch_de_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_de_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_de_lo.we;\n   release dut.reg_file_.b2v_latch_de_hi.we;\n   release dut.reg_file_.b2v_latch_de_lo.db;\n   release dut.reg_file_.b2v_latch_de_hi.db;\n   // Preset hl\n   force dut.reg_file_.b2v_latch_hl_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_hl_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_hl_lo.we;\n   release dut.reg_file_.b2v_latch_hl_hi.we;\n   release dut.reg_file_.b2v_latch_hl_lo.db;\n   release dut.reg_file_.b2v_latch_hl_hi.db;\n   // Preset af2\n   force dut.reg_file_.b2v_latch_af2_lo.we=1;\n   force dut.reg_file_.b2v_latch_af2_hi.we=1;\n   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_af2_lo.we;\n   release dut.reg_file_.b2v_latch_af2_hi.we;\n   release dut.reg_file_.b2v_latch_af2_lo.db;\n   release dut.reg_file_.b2v_latch_af2_hi.db;\n   // Preset bc2\n   force dut.reg_file_.b2v_latch_bc2_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc2_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_bc2_lo.we;\n   release dut.reg_file_.b2v_latch_bc2_hi.we;\n   release dut.reg_file_.b2v_latch_bc2_lo.db;\n   release dut.reg_file_.b2v_latch_bc2_hi.db;\n   // Preset de2\n   force dut.reg_file_.b2v_latch_de2_lo.we=1;\n   force dut.reg_file_.b2v_latch_de2_hi.we=1;\n   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_de2_lo.we;\n   release dut.reg_file_.b2v_latch_de2_hi.we;\n   release dut.reg_file_.b2v_latch_de2_lo.db;\n   release dut.reg_file_.b2v_latch_de2_hi.db;\n   // Preset hl2\n   force dut.reg_file_.b2v_latch_hl2_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl2_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_hl2_lo.we;\n   release dut.reg_file_.b2v_latch_hl2_hi.we;\n   release dut.reg_file_.b2v_latch_hl2_lo.db;\n   release dut.reg_file_.b2v_latch_hl2_hi.db;\n   // Preset ix\n   force dut.reg_file_.b2v_latch_ix_lo.we=1;\n   force dut.reg_file_.b2v_latch_ix_hi.we=1;\n   force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ix_lo.we;\n   release dut.reg_file_.b2v_latch_ix_hi.we;\n   release dut.reg_file_.b2v_latch_ix_lo.db;\n   release dut.reg_file_.b2v_latch_ix_hi.db;\n   // Preset iy\n   force dut.reg_file_.b2v_latch_iy_lo.we=1;\n   force dut.reg_file_.b2v_latch_iy_hi.we=1;\n   force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_iy_lo.we;\n   release dut.reg_file_.b2v_latch_iy_hi.we;\n   release dut.reg_file_.b2v_latch_iy_lo.db;\n   release dut.reg_file_.b2v_latch_iy_hi.db;\n   // Preset sp\n   force dut.reg_file_.b2v_latch_sp_lo.we=1;\n   force dut.reg_file_.b2v_latch_sp_hi.we=1;\n   force dut.reg_file_.b2v_latch_sp_lo.db=8'h36;\n   force dut.reg_file_.b2v_latch_sp_hi.db=8'h9d;\n#2 release dut.reg_file_.b2v_latch_sp_lo.we;\n   release dut.reg_file_.b2v_latch_sp_hi.we;\n   release dut.reg_file_.b2v_latch_sp_lo.db;\n   release dut.reg_file_.b2v_latch_sp_hi.db;\n   // Preset wz\n   force dut.reg_file_.b2v_latch_wz_lo.we=1;\n   force dut.reg_file_.b2v_latch_wz_hi.we=1;\n   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_wz_lo.we;\n   release dut.reg_file_.b2v_latch_wz_hi.we;\n   release dut.reg_file_.b2v_latch_wz_lo.db;\n   release dut.reg_file_.b2v_latch_wz_hi.db;\n   // Preset pc\n   force dut.reg_file_.b2v_latch_pc_lo.we=1;\n   force dut.reg_file_.b2v_latch_pc_hi.we=1;\n   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_pc_lo.we;\n   release dut.reg_file_.b2v_latch_pc_hi.we;\n   release dut.reg_file_.b2v_latch_pc_lo.db;\n   release dut.reg_file_.b2v_latch_pc_hi.db;\n   // Preset ir\n   force dut.reg_file_.b2v_latch_ir_lo.we=1;\n   force dut.reg_file_.b2v_latch_ir_hi.we=1;\n   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ir_lo.we;\n   release dut.reg_file_.b2v_latch_ir_hi.we;\n   release dut.reg_file_.b2v_latch_ir_lo.db;\n   release dut.reg_file_.b2v_latch_ir_hi.db;\n   // Preset memory\n   ram.Mem[0] = 8'h3b;\n   force dut.z80_top_ifc_n.fpga_reset=0;\n   force dut.address_latch_.Q=16'h0000;\n   release dut.reg_control_.ctl_reg_sys_we;\n   release dut.reg_file_.reg_gp_we;\n#2 // Execute: M1/T1 start\n#1 release dut.address_latch_.Q;\n#1\n#10 // Wait for opcode end\n   force dut.reg_control_.ctl_reg_sys_we=0;\n#2 pc=z.A;\n#2\n#1 force dut.reg_file_.reg_gp_we=0;\n   force dut.z80_top_ifc_n.fpga_reset=1;\n   if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h00) $fdisplay(f,\"* Reg af f=%h !=00\",dut.reg_file_.b2v_latch_af_lo.latch);\n   if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h00) $fdisplay(f,\"* Reg af a=%h !=00\",dut.reg_file_.b2v_latch_af_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h00) $fdisplay(f,\"* Reg bc c=%h !=00\",dut.reg_file_.b2v_latch_bc_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h00) $fdisplay(f,\"* Reg bc b=%h !=00\",dut.reg_file_.b2v_latch_bc_hi.latch);\n   if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h00) $fdisplay(f,\"* Reg de e=%h !=00\",dut.reg_file_.b2v_latch_de_lo.latch);\n   if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h00) $fdisplay(f,\"* Reg de d=%h !=00\",dut.reg_file_.b2v_latch_de_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h00) $fdisplay(f,\"* Reg hl l=%h !=00\",dut.reg_file_.b2v_latch_hl_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h00) $fdisplay(f,\"* Reg hl h=%h !=00\",dut.reg_file_.b2v_latch_hl_hi.latch);\n   if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,\"* Reg af2 f=%h !=00\",dut.reg_file_.b2v_latch_af2_lo.latch);\n   if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,\"* Reg af2 a=%h !=00\",dut.reg_file_.b2v_latch_af2_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,\"* Reg bc2 c=%h !=00\",dut.reg_file_.b2v_latch_bc2_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,\"* Reg bc2 b=%h !=00\",dut.reg_file_.b2v_latch_bc2_hi.latch);\n   if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,\"* Reg de2 e=%h !=00\",dut.reg_file_.b2v_latch_de2_lo.latch);\n   if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,\"* Reg de2 d=%h !=00\",dut.reg_file_.b2v_latch_de2_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,\"* Reg hl2 l=%h !=00\",dut.reg_file_.b2v_latch_hl2_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,\"* Reg hl2 h=%h !=00\",dut.reg_file_.b2v_latch_hl2_hi.latch);\n   if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,\"* Reg ix x=%h !=00\",dut.reg_file_.b2v_latch_ix_lo.latch);\n   if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,\"* Reg ix i=%h !=00\",dut.reg_file_.b2v_latch_ix_hi.latch);\n   if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,\"* Reg iy y=%h !=00\",dut.reg_file_.b2v_latch_iy_lo.latch);\n   if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,\"* Reg iy i=%h !=00\",dut.reg_file_.b2v_latch_iy_hi.latch);\n   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h35) $fdisplay(f,\"* Reg sp p=%h !=35\",dut.reg_file_.b2v_latch_sp_lo.latch);\n   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h9d) $fdisplay(f,\"* Reg sp s=%h !=9d\",dut.reg_file_.b2v_latch_sp_hi.latch);\n   if (pc!==16'h0001) $fdisplay(f,\"* PC=%h !=0001\",pc);\n   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,\"* Reg ir r=%h !=01\",dut.reg_file_.b2v_latch_ir_lo.latch);\n   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,\"* Reg ir i=%h !=00\",dut.reg_file_.b2v_latch_ir_hi.latch);\n#1 // End opcode\n\n   force dut.ir_.ctl_ir_we=1;\n   force dut.ir_.db=0;\n#2 release dut.ir_.ctl_ir_we;\n   release dut.ir_.db;\n   $fdisplay(f,\"Testing opcode 07      RLCA\");\n   // Preset af\n   force dut.reg_file_.b2v_latch_af_lo.we=1;\n   force dut.reg_file_.b2v_latch_af_hi.we=1;\n   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af_hi.db=8'h88;\n#2 release dut.reg_file_.b2v_latch_af_lo.we;\n   release dut.reg_file_.b2v_latch_af_hi.we;\n   release dut.reg_file_.b2v_latch_af_lo.db;\n   release dut.reg_file_.b2v_latch_af_hi.db;\n   // Preset bc\n   force dut.reg_file_.b2v_latch_bc_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_bc_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_bc_lo.we;\n   release dut.reg_file_.b2v_latch_bc_hi.we;\n   release dut.reg_file_.b2v_latch_bc_lo.db;\n   release dut.reg_file_.b2v_latch_bc_hi.db;\n   // Preset de\n   force dut.reg_file_.b2v_latch_de_lo.we=1;\n   force dut.reg_file_.b2v_latch_de_hi.we=1;\n   force dut.reg_file_.b2v_latch_de_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_de_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_de_lo.we;\n   release dut.reg_file_.b2v_latch_de_hi.we;\n   release dut.reg_file_.b2v_latch_de_lo.db;\n   release dut.reg_file_.b2v_latch_de_hi.db;\n   // Preset hl\n   force dut.reg_file_.b2v_latch_hl_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_hl_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_hl_lo.we;\n   release dut.reg_file_.b2v_latch_hl_hi.we;\n   release dut.reg_file_.b2v_latch_hl_lo.db;\n   release dut.reg_file_.b2v_latch_hl_hi.db;\n   // Preset af2\n   force dut.reg_file_.b2v_latch_af2_lo.we=1;\n   force dut.reg_file_.b2v_latch_af2_hi.we=1;\n   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_af2_lo.we;\n   release dut.reg_file_.b2v_latch_af2_hi.we;\n   release dut.reg_file_.b2v_latch_af2_lo.db;\n   release dut.reg_file_.b2v_latch_af2_hi.db;\n   // Preset bc2\n   force dut.reg_file_.b2v_latch_bc2_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc2_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_bc2_lo.we;\n   release dut.reg_file_.b2v_latch_bc2_hi.we;\n   release dut.reg_file_.b2v_latch_bc2_lo.db;\n   release dut.reg_file_.b2v_latch_bc2_hi.db;\n   // Preset de2\n   force dut.reg_file_.b2v_latch_de2_lo.we=1;\n   force dut.reg_file_.b2v_latch_de2_hi.we=1;\n   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_de2_lo.we;\n   release dut.reg_file_.b2v_latch_de2_hi.we;\n   release dut.reg_file_.b2v_latch_de2_lo.db;\n   release dut.reg_file_.b2v_latch_de2_hi.db;\n   // Preset hl2\n   force dut.reg_file_.b2v_latch_hl2_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl2_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_hl2_lo.we;\n   release dut.reg_file_.b2v_latch_hl2_hi.we;\n   release dut.reg_file_.b2v_latch_hl2_lo.db;\n   release dut.reg_file_.b2v_latch_hl2_hi.db;\n   // Preset ix\n   force dut.reg_file_.b2v_latch_ix_lo.we=1;\n   force dut.reg_file_.b2v_latch_ix_hi.we=1;\n   force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ix_lo.we;\n   release dut.reg_file_.b2v_latch_ix_hi.we;\n   release dut.reg_file_.b2v_latch_ix_lo.db;\n   release dut.reg_file_.b2v_latch_ix_hi.db;\n   // Preset iy\n   force dut.reg_file_.b2v_latch_iy_lo.we=1;\n   force dut.reg_file_.b2v_latch_iy_hi.we=1;\n   force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_iy_lo.we;\n   release dut.reg_file_.b2v_latch_iy_hi.we;\n   release dut.reg_file_.b2v_latch_iy_lo.db;\n   release dut.reg_file_.b2v_latch_iy_hi.db;\n   // Preset sp\n   force dut.reg_file_.b2v_latch_sp_lo.we=1;\n   force dut.reg_file_.b2v_latch_sp_hi.we=1;\n   force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_sp_lo.we;\n   release dut.reg_file_.b2v_latch_sp_hi.we;\n   release dut.reg_file_.b2v_latch_sp_lo.db;\n   release dut.reg_file_.b2v_latch_sp_hi.db;\n   // Preset wz\n   force dut.reg_file_.b2v_latch_wz_lo.we=1;\n   force dut.reg_file_.b2v_latch_wz_hi.we=1;\n   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_wz_lo.we;\n   release dut.reg_file_.b2v_latch_wz_hi.we;\n   release dut.reg_file_.b2v_latch_wz_lo.db;\n   release dut.reg_file_.b2v_latch_wz_hi.db;\n   // Preset pc\n   force dut.reg_file_.b2v_latch_pc_lo.we=1;\n   force dut.reg_file_.b2v_latch_pc_hi.we=1;\n   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_pc_lo.we;\n   release dut.reg_file_.b2v_latch_pc_hi.we;\n   release dut.reg_file_.b2v_latch_pc_lo.db;\n   release dut.reg_file_.b2v_latch_pc_hi.db;\n   // Preset ir\n   force dut.reg_file_.b2v_latch_ir_lo.we=1;\n   force dut.reg_file_.b2v_latch_ir_hi.we=1;\n   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ir_lo.we;\n   release dut.reg_file_.b2v_latch_ir_hi.we;\n   release dut.reg_file_.b2v_latch_ir_lo.db;\n   release dut.reg_file_.b2v_latch_ir_hi.db;\n   // Preset memory\n   ram.Mem[0] = 8'h07;\n   force dut.z80_top_ifc_n.fpga_reset=0;\n   force dut.address_latch_.Q=16'h0000;\n   release dut.reg_control_.ctl_reg_sys_we;\n   release dut.reg_file_.reg_gp_we;\n#2 // Execute: M1/T1 start\n#1 release dut.address_latch_.Q;\n#1\n#6 // Wait for opcode end\n   force dut.reg_control_.ctl_reg_sys_we=0;\n#2 pc=z.A;\n#2\n#1 force dut.reg_file_.reg_gp_we=0;\n   force dut.z80_top_ifc_n.fpga_reset=1;\n   if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h01) $fdisplay(f,\"* Reg af f=%h !=01\",dut.reg_file_.b2v_latch_af_lo.latch);\n   if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h11) $fdisplay(f,\"* Reg af a=%h !=11\",dut.reg_file_.b2v_latch_af_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h00) $fdisplay(f,\"* Reg bc c=%h !=00\",dut.reg_file_.b2v_latch_bc_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h00) $fdisplay(f,\"* Reg bc b=%h !=00\",dut.reg_file_.b2v_latch_bc_hi.latch);\n   if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h00) $fdisplay(f,\"* Reg de e=%h !=00\",dut.reg_file_.b2v_latch_de_lo.latch);\n   if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h00) $fdisplay(f,\"* Reg de d=%h !=00\",dut.reg_file_.b2v_latch_de_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h00) $fdisplay(f,\"* Reg hl l=%h !=00\",dut.reg_file_.b2v_latch_hl_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h00) $fdisplay(f,\"* Reg hl h=%h !=00\",dut.reg_file_.b2v_latch_hl_hi.latch);\n   if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,\"* Reg af2 f=%h !=00\",dut.reg_file_.b2v_latch_af2_lo.latch);\n   if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,\"* Reg af2 a=%h !=00\",dut.reg_file_.b2v_latch_af2_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,\"* Reg bc2 c=%h !=00\",dut.reg_file_.b2v_latch_bc2_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,\"* Reg bc2 b=%h !=00\",dut.reg_file_.b2v_latch_bc2_hi.latch);\n   if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,\"* Reg de2 e=%h !=00\",dut.reg_file_.b2v_latch_de2_lo.latch);\n   if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,\"* Reg de2 d=%h !=00\",dut.reg_file_.b2v_latch_de2_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,\"* Reg hl2 l=%h !=00\",dut.reg_file_.b2v_latch_hl2_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,\"* Reg hl2 h=%h !=00\",dut.reg_file_.b2v_latch_hl2_hi.latch);\n   if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,\"* Reg ix x=%h !=00\",dut.reg_file_.b2v_latch_ix_lo.latch);\n   if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,\"* Reg ix i=%h !=00\",dut.reg_file_.b2v_latch_ix_hi.latch);\n   if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,\"* Reg iy y=%h !=00\",dut.reg_file_.b2v_latch_iy_lo.latch);\n   if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,\"* Reg iy i=%h !=00\",dut.reg_file_.b2v_latch_iy_hi.latch);\n   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,\"* Reg sp p=%h !=00\",dut.reg_file_.b2v_latch_sp_lo.latch);\n   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,\"* Reg sp s=%h !=00\",dut.reg_file_.b2v_latch_sp_hi.latch);\n   if (pc!==16'h0001) $fdisplay(f,\"* PC=%h !=0001\",pc);\n   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,\"* Reg ir r=%h !=01\",dut.reg_file_.b2v_latch_ir_lo.latch);\n   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,\"* Reg ir i=%h !=00\",dut.reg_file_.b2v_latch_ir_hi.latch);\n#1 // End opcode\n\n   force dut.ir_.ctl_ir_we=1;\n   force dut.ir_.db=0;\n#2 release dut.ir_.ctl_ir_we;\n   release dut.ir_.db;\n   $fdisplay(f,\"Testing opcode 1f      RRA\");\n   // Preset af\n   force dut.reg_file_.b2v_latch_af_lo.we=1;\n   force dut.reg_file_.b2v_latch_af_hi.we=1;\n   force dut.reg_file_.b2v_latch_af_lo.db=8'hc4;\n   force dut.reg_file_.b2v_latch_af_hi.db=8'h01;\n#2 release dut.reg_file_.b2v_latch_af_lo.we;\n   release dut.reg_file_.b2v_latch_af_hi.we;\n   release dut.reg_file_.b2v_latch_af_lo.db;\n   release dut.reg_file_.b2v_latch_af_hi.db;\n   // Preset bc\n   force dut.reg_file_.b2v_latch_bc_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_bc_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_bc_lo.we;\n   release dut.reg_file_.b2v_latch_bc_hi.we;\n   release dut.reg_file_.b2v_latch_bc_lo.db;\n   release dut.reg_file_.b2v_latch_bc_hi.db;\n   // Preset de\n   force dut.reg_file_.b2v_latch_de_lo.we=1;\n   force dut.reg_file_.b2v_latch_de_hi.we=1;\n   force dut.reg_file_.b2v_latch_de_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_de_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_de_lo.we;\n   release dut.reg_file_.b2v_latch_de_hi.we;\n   release dut.reg_file_.b2v_latch_de_lo.db;\n   release dut.reg_file_.b2v_latch_de_hi.db;\n   // Preset hl\n   force dut.reg_file_.b2v_latch_hl_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_hl_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_hl_lo.we;\n   release dut.reg_file_.b2v_latch_hl_hi.we;\n   release dut.reg_file_.b2v_latch_hl_lo.db;\n   release dut.reg_file_.b2v_latch_hl_hi.db;\n   // Preset af2\n   force dut.reg_file_.b2v_latch_af2_lo.we=1;\n   force dut.reg_file_.b2v_latch_af2_hi.we=1;\n   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_af2_lo.we;\n   release dut.reg_file_.b2v_latch_af2_hi.we;\n   release dut.reg_file_.b2v_latch_af2_lo.db;\n   release dut.reg_file_.b2v_latch_af2_hi.db;\n   // Preset bc2\n   force dut.reg_file_.b2v_latch_bc2_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc2_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_bc2_lo.we;\n   release dut.reg_file_.b2v_latch_bc2_hi.we;\n   release dut.reg_file_.b2v_latch_bc2_lo.db;\n   release dut.reg_file_.b2v_latch_bc2_hi.db;\n   // Preset de2\n   force dut.reg_file_.b2v_latch_de2_lo.we=1;\n   force dut.reg_file_.b2v_latch_de2_hi.we=1;\n   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_de2_lo.we;\n   release dut.reg_file_.b2v_latch_de2_hi.we;\n   release dut.reg_file_.b2v_latch_de2_lo.db;\n   release dut.reg_file_.b2v_latch_de2_hi.db;\n   // Preset hl2\n   force dut.reg_file_.b2v_latch_hl2_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl2_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_hl2_lo.we;\n   release dut.reg_file_.b2v_latch_hl2_hi.we;\n   release dut.reg_file_.b2v_latch_hl2_lo.db;\n   release dut.reg_file_.b2v_latch_hl2_hi.db;\n   // Preset ix\n   force dut.reg_file_.b2v_latch_ix_lo.we=1;\n   force dut.reg_file_.b2v_latch_ix_hi.we=1;\n   force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ix_lo.we;\n   release dut.reg_file_.b2v_latch_ix_hi.we;\n   release dut.reg_file_.b2v_latch_ix_lo.db;\n   release dut.reg_file_.b2v_latch_ix_hi.db;\n   // Preset iy\n   force dut.reg_file_.b2v_latch_iy_lo.we=1;\n   force dut.reg_file_.b2v_latch_iy_hi.we=1;\n   force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_iy_lo.we;\n   release dut.reg_file_.b2v_latch_iy_hi.we;\n   release dut.reg_file_.b2v_latch_iy_lo.db;\n   release dut.reg_file_.b2v_latch_iy_hi.db;\n   // Preset sp\n   force dut.reg_file_.b2v_latch_sp_lo.we=1;\n   force dut.reg_file_.b2v_latch_sp_hi.we=1;\n   force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_sp_lo.we;\n   release dut.reg_file_.b2v_latch_sp_hi.we;\n   release dut.reg_file_.b2v_latch_sp_lo.db;\n   release dut.reg_file_.b2v_latch_sp_hi.db;\n   // Preset wz\n   force dut.reg_file_.b2v_latch_wz_lo.we=1;\n   force dut.reg_file_.b2v_latch_wz_hi.we=1;\n   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_wz_lo.we;\n   release dut.reg_file_.b2v_latch_wz_hi.we;\n   release dut.reg_file_.b2v_latch_wz_lo.db;\n   release dut.reg_file_.b2v_latch_wz_hi.db;\n   // Preset pc\n   force dut.reg_file_.b2v_latch_pc_lo.we=1;\n   force dut.reg_file_.b2v_latch_pc_hi.we=1;\n   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_pc_lo.we;\n   release dut.reg_file_.b2v_latch_pc_hi.we;\n   release dut.reg_file_.b2v_latch_pc_lo.db;\n   release dut.reg_file_.b2v_latch_pc_hi.db;\n   // Preset ir\n   force dut.reg_file_.b2v_latch_ir_lo.we=1;\n   force dut.reg_file_.b2v_latch_ir_hi.we=1;\n   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ir_lo.we;\n   release dut.reg_file_.b2v_latch_ir_hi.we;\n   release dut.reg_file_.b2v_latch_ir_lo.db;\n   release dut.reg_file_.b2v_latch_ir_hi.db;\n   // Preset memory\n   ram.Mem[0] = 8'h1f;\n   force dut.z80_top_ifc_n.fpga_reset=0;\n   force dut.address_latch_.Q=16'h0000;\n   release dut.reg_control_.ctl_reg_sys_we;\n   release dut.reg_file_.reg_gp_we;\n#2 // Execute: M1/T1 start\n#1 release dut.address_latch_.Q;\n#1\n#6 // Wait for opcode end\n   force dut.reg_control_.ctl_reg_sys_we=0;\n#2 pc=z.A;\n#2\n#1 force dut.reg_file_.reg_gp_we=0;\n   force dut.z80_top_ifc_n.fpga_reset=1;\n   if (dut.reg_file_.b2v_latch_af_lo.latch!==8'hc5) $fdisplay(f,\"* Reg af f=%h !=c5\",dut.reg_file_.b2v_latch_af_lo.latch);\n   if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h00) $fdisplay(f,\"* Reg af a=%h !=00\",dut.reg_file_.b2v_latch_af_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h00) $fdisplay(f,\"* Reg bc c=%h !=00\",dut.reg_file_.b2v_latch_bc_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h00) $fdisplay(f,\"* Reg bc b=%h !=00\",dut.reg_file_.b2v_latch_bc_hi.latch);\n   if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h00) $fdisplay(f,\"* Reg de e=%h !=00\",dut.reg_file_.b2v_latch_de_lo.latch);\n   if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h00) $fdisplay(f,\"* Reg de d=%h !=00\",dut.reg_file_.b2v_latch_de_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h00) $fdisplay(f,\"* Reg hl l=%h !=00\",dut.reg_file_.b2v_latch_hl_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h00) $fdisplay(f,\"* Reg hl h=%h !=00\",dut.reg_file_.b2v_latch_hl_hi.latch);\n   if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,\"* Reg af2 f=%h !=00\",dut.reg_file_.b2v_latch_af2_lo.latch);\n   if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,\"* Reg af2 a=%h !=00\",dut.reg_file_.b2v_latch_af2_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,\"* Reg bc2 c=%h !=00\",dut.reg_file_.b2v_latch_bc2_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,\"* Reg bc2 b=%h !=00\",dut.reg_file_.b2v_latch_bc2_hi.latch);\n   if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,\"* Reg de2 e=%h !=00\",dut.reg_file_.b2v_latch_de2_lo.latch);\n   if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,\"* Reg de2 d=%h !=00\",dut.reg_file_.b2v_latch_de2_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,\"* Reg hl2 l=%h !=00\",dut.reg_file_.b2v_latch_hl2_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,\"* Reg hl2 h=%h !=00\",dut.reg_file_.b2v_latch_hl2_hi.latch);\n   if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,\"* Reg ix x=%h !=00\",dut.reg_file_.b2v_latch_ix_lo.latch);\n   if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,\"* Reg ix i=%h !=00\",dut.reg_file_.b2v_latch_ix_hi.latch);\n   if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,\"* Reg iy y=%h !=00\",dut.reg_file_.b2v_latch_iy_lo.latch);\n   if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,\"* Reg iy i=%h !=00\",dut.reg_file_.b2v_latch_iy_hi.latch);\n   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,\"* Reg sp p=%h !=00\",dut.reg_file_.b2v_latch_sp_lo.latch);\n   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,\"* Reg sp s=%h !=00\",dut.reg_file_.b2v_latch_sp_hi.latch);\n   if (pc!==16'h0001) $fdisplay(f,\"* PC=%h !=0001\",pc);\n   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,\"* Reg ir r=%h !=01\",dut.reg_file_.b2v_latch_ir_lo.latch);\n   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,\"* Reg ir i=%h !=00\",dut.reg_file_.b2v_latch_ir_hi.latch);\n#1 // End opcode\n\n   force dut.ir_.ctl_ir_we=1;\n   force dut.ir_.db=0;\n#2 release dut.ir_.ctl_ir_we;\n   release dut.ir_.db;\n   $fdisplay(f,\"Testing opcode cb09    RRC C\");\n   // Preset af\n   force dut.reg_file_.b2v_latch_af_lo.we=1;\n   force dut.reg_file_.b2v_latch_af_hi.we=1;\n   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af_hi.db=8'h18;\n#2 release dut.reg_file_.b2v_latch_af_lo.we;\n   release dut.reg_file_.b2v_latch_af_hi.we;\n   release dut.reg_file_.b2v_latch_af_lo.db;\n   release dut.reg_file_.b2v_latch_af_hi.db;\n   // Preset bc\n   force dut.reg_file_.b2v_latch_bc_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc_lo.db=8'h5c;\n   force dut.reg_file_.b2v_latch_bc_hi.db=8'h12;\n#2 release dut.reg_file_.b2v_latch_bc_lo.we;\n   release dut.reg_file_.b2v_latch_bc_hi.we;\n   release dut.reg_file_.b2v_latch_bc_lo.db;\n   release dut.reg_file_.b2v_latch_bc_hi.db;\n   // Preset de\n   force dut.reg_file_.b2v_latch_de_lo.we=1;\n   force dut.reg_file_.b2v_latch_de_hi.we=1;\n   force dut.reg_file_.b2v_latch_de_lo.db=8'h97;\n   force dut.reg_file_.b2v_latch_de_hi.db=8'hdd;\n#2 release dut.reg_file_.b2v_latch_de_lo.we;\n   release dut.reg_file_.b2v_latch_de_hi.we;\n   release dut.reg_file_.b2v_latch_de_lo.db;\n   release dut.reg_file_.b2v_latch_de_hi.db;\n   // Preset hl\n   force dut.reg_file_.b2v_latch_hl_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl_lo.db=8'hc6;\n   force dut.reg_file_.b2v_latch_hl_hi.db=8'h59;\n#2 release dut.reg_file_.b2v_latch_hl_lo.we;\n   release dut.reg_file_.b2v_latch_hl_hi.we;\n   release dut.reg_file_.b2v_latch_hl_lo.db;\n   release dut.reg_file_.b2v_latch_hl_hi.db;\n   // Preset af2\n   force dut.reg_file_.b2v_latch_af2_lo.we=1;\n   force dut.reg_file_.b2v_latch_af2_hi.we=1;\n   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_af2_lo.we;\n   release dut.reg_file_.b2v_latch_af2_hi.we;\n   release dut.reg_file_.b2v_latch_af2_lo.db;\n   release dut.reg_file_.b2v_latch_af2_hi.db;\n   // Preset bc2\n   force dut.reg_file_.b2v_latch_bc2_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc2_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_bc2_lo.we;\n   release dut.reg_file_.b2v_latch_bc2_hi.we;\n   release dut.reg_file_.b2v_latch_bc2_lo.db;\n   release dut.reg_file_.b2v_latch_bc2_hi.db;\n   // Preset de2\n   force dut.reg_file_.b2v_latch_de2_lo.we=1;\n   force dut.reg_file_.b2v_latch_de2_hi.we=1;\n   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_de2_lo.we;\n   release dut.reg_file_.b2v_latch_de2_hi.we;\n   release dut.reg_file_.b2v_latch_de2_lo.db;\n   release dut.reg_file_.b2v_latch_de2_hi.db;\n   // Preset hl2\n   force dut.reg_file_.b2v_latch_hl2_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl2_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_hl2_lo.we;\n   release dut.reg_file_.b2v_latch_hl2_hi.we;\n   release dut.reg_file_.b2v_latch_hl2_lo.db;\n   release dut.reg_file_.b2v_latch_hl2_hi.db;\n   // Preset ix\n   force dut.reg_file_.b2v_latch_ix_lo.we=1;\n   force dut.reg_file_.b2v_latch_ix_hi.we=1;\n   force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ix_lo.we;\n   release dut.reg_file_.b2v_latch_ix_hi.we;\n   release dut.reg_file_.b2v_latch_ix_lo.db;\n   release dut.reg_file_.b2v_latch_ix_hi.db;\n   // Preset iy\n   force dut.reg_file_.b2v_latch_iy_lo.we=1;\n   force dut.reg_file_.b2v_latch_iy_hi.we=1;\n   force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_iy_lo.we;\n   release dut.reg_file_.b2v_latch_iy_hi.we;\n   release dut.reg_file_.b2v_latch_iy_lo.db;\n   release dut.reg_file_.b2v_latch_iy_hi.db;\n   // Preset sp\n   force dut.reg_file_.b2v_latch_sp_lo.we=1;\n   force dut.reg_file_.b2v_latch_sp_hi.we=1;\n   force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_sp_lo.we;\n   release dut.reg_file_.b2v_latch_sp_hi.we;\n   release dut.reg_file_.b2v_latch_sp_lo.db;\n   release dut.reg_file_.b2v_latch_sp_hi.db;\n   // Preset wz\n   force dut.reg_file_.b2v_latch_wz_lo.we=1;\n   force dut.reg_file_.b2v_latch_wz_hi.we=1;\n   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_wz_lo.we;\n   release dut.reg_file_.b2v_latch_wz_hi.we;\n   release dut.reg_file_.b2v_latch_wz_lo.db;\n   release dut.reg_file_.b2v_latch_wz_hi.db;\n   // Preset pc\n   force dut.reg_file_.b2v_latch_pc_lo.we=1;\n   force dut.reg_file_.b2v_latch_pc_hi.we=1;\n   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_pc_lo.we;\n   release dut.reg_file_.b2v_latch_pc_hi.we;\n   release dut.reg_file_.b2v_latch_pc_lo.db;\n   release dut.reg_file_.b2v_latch_pc_hi.db;\n   // Preset ir\n   force dut.reg_file_.b2v_latch_ir_lo.we=1;\n   force dut.reg_file_.b2v_latch_ir_hi.we=1;\n   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ir_lo.we;\n   release dut.reg_file_.b2v_latch_ir_hi.we;\n   release dut.reg_file_.b2v_latch_ir_lo.db;\n   release dut.reg_file_.b2v_latch_ir_hi.db;\n   // Preset memory\n   ram.Mem[0] = 8'hcb;\n   ram.Mem[1] = 8'h09;\n   // Preset memory\n   ram.Mem[22982] = 8'h9e;\n   force dut.z80_top_ifc_n.fpga_reset=0;\n   force dut.address_latch_.Q=16'h0000;\n   release dut.reg_control_.ctl_reg_sys_we;\n   release dut.reg_file_.reg_gp_we;\n#2 // Execute: M1/T1 start\n#1 release dut.address_latch_.Q;\n#1\n#14 // Wait for opcode end\n   force dut.reg_control_.ctl_reg_sys_we=0;\n#2 pc=z.A;\n#2\n#1 force dut.reg_file_.reg_gp_we=0;\n   force dut.z80_top_ifc_n.fpga_reset=1;\n   if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h2c) $fdisplay(f,\"* Reg af f=%h !=2c\",dut.reg_file_.b2v_latch_af_lo.latch);\n   if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h18) $fdisplay(f,\"* Reg af a=%h !=18\",dut.reg_file_.b2v_latch_af_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h2e) $fdisplay(f,\"* Reg bc c=%h !=2e\",dut.reg_file_.b2v_latch_bc_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h12) $fdisplay(f,\"* Reg bc b=%h !=12\",dut.reg_file_.b2v_latch_bc_hi.latch);\n   if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h97) $fdisplay(f,\"* Reg de e=%h !=97\",dut.reg_file_.b2v_latch_de_lo.latch);\n   if (dut.reg_file_.b2v_latch_de_hi.latch!==8'hdd) $fdisplay(f,\"* Reg de d=%h !=dd\",dut.reg_file_.b2v_latch_de_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'hc6) $fdisplay(f,\"* Reg hl l=%h !=c6\",dut.reg_file_.b2v_latch_hl_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h59) $fdisplay(f,\"* Reg hl h=%h !=59\",dut.reg_file_.b2v_latch_hl_hi.latch);\n   if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,\"* Reg af2 f=%h !=00\",dut.reg_file_.b2v_latch_af2_lo.latch);\n   if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,\"* Reg af2 a=%h !=00\",dut.reg_file_.b2v_latch_af2_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,\"* Reg bc2 c=%h !=00\",dut.reg_file_.b2v_latch_bc2_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,\"* Reg bc2 b=%h !=00\",dut.reg_file_.b2v_latch_bc2_hi.latch);\n   if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,\"* Reg de2 e=%h !=00\",dut.reg_file_.b2v_latch_de2_lo.latch);\n   if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,\"* Reg de2 d=%h !=00\",dut.reg_file_.b2v_latch_de2_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,\"* Reg hl2 l=%h !=00\",dut.reg_file_.b2v_latch_hl2_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,\"* Reg hl2 h=%h !=00\",dut.reg_file_.b2v_latch_hl2_hi.latch);\n   if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,\"* Reg ix x=%h !=00\",dut.reg_file_.b2v_latch_ix_lo.latch);\n   if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,\"* Reg ix i=%h !=00\",dut.reg_file_.b2v_latch_ix_hi.latch);\n   if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,\"* Reg iy y=%h !=00\",dut.reg_file_.b2v_latch_iy_lo.latch);\n   if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,\"* Reg iy i=%h !=00\",dut.reg_file_.b2v_latch_iy_hi.latch);\n   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,\"* Reg sp p=%h !=00\",dut.reg_file_.b2v_latch_sp_lo.latch);\n   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,\"* Reg sp s=%h !=00\",dut.reg_file_.b2v_latch_sp_hi.latch);\n   if (pc!==16'h0002) $fdisplay(f,\"* PC=%h !=0002\",pc);\n   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,\"* Reg ir r=%h !=02\",dut.reg_file_.b2v_latch_ir_lo.latch);\n   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,\"* Reg ir i=%h !=00\",dut.reg_file_.b2v_latch_ir_hi.latch);\n#1 // End opcode\n\n   force dut.ir_.ctl_ir_we=1;\n   force dut.ir_.db=0;\n#2 release dut.ir_.ctl_ir_we;\n   release dut.ir_.db;\n   $fdisplay(f,\"Testing opcode cb11    RL C\");\n   // Preset af\n   force dut.reg_file_.b2v_latch_af_lo.we=1;\n   force dut.reg_file_.b2v_latch_af_hi.we=1;\n   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af_hi.db=8'h65;\n#2 release dut.reg_file_.b2v_latch_af_lo.we;\n   release dut.reg_file_.b2v_latch_af_hi.we;\n   release dut.reg_file_.b2v_latch_af_lo.db;\n   release dut.reg_file_.b2v_latch_af_hi.db;\n   // Preset bc\n   force dut.reg_file_.b2v_latch_bc_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc_lo.db=8'h5c;\n   force dut.reg_file_.b2v_latch_bc_hi.db=8'he2;\n#2 release dut.reg_file_.b2v_latch_bc_lo.we;\n   release dut.reg_file_.b2v_latch_bc_hi.we;\n   release dut.reg_file_.b2v_latch_bc_lo.db;\n   release dut.reg_file_.b2v_latch_bc_hi.db;\n   // Preset de\n   force dut.reg_file_.b2v_latch_de_lo.we=1;\n   force dut.reg_file_.b2v_latch_de_hi.we=1;\n   force dut.reg_file_.b2v_latch_de_lo.db=8'h8a;\n   force dut.reg_file_.b2v_latch_de_hi.db=8'h4b;\n#2 release dut.reg_file_.b2v_latch_de_lo.we;\n   release dut.reg_file_.b2v_latch_de_hi.we;\n   release dut.reg_file_.b2v_latch_de_lo.db;\n   release dut.reg_file_.b2v_latch_de_hi.db;\n   // Preset hl\n   force dut.reg_file_.b2v_latch_hl_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl_lo.db=8'h42;\n   force dut.reg_file_.b2v_latch_hl_hi.db=8'hed;\n#2 release dut.reg_file_.b2v_latch_hl_lo.we;\n   release dut.reg_file_.b2v_latch_hl_hi.we;\n   release dut.reg_file_.b2v_latch_hl_lo.db;\n   release dut.reg_file_.b2v_latch_hl_hi.db;\n   // Preset af2\n   force dut.reg_file_.b2v_latch_af2_lo.we=1;\n   force dut.reg_file_.b2v_latch_af2_hi.we=1;\n   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_af2_lo.we;\n   release dut.reg_file_.b2v_latch_af2_hi.we;\n   release dut.reg_file_.b2v_latch_af2_lo.db;\n   release dut.reg_file_.b2v_latch_af2_hi.db;\n   // Preset bc2\n   force dut.reg_file_.b2v_latch_bc2_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc2_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_bc2_lo.we;\n   release dut.reg_file_.b2v_latch_bc2_hi.we;\n   release dut.reg_file_.b2v_latch_bc2_lo.db;\n   release dut.reg_file_.b2v_latch_bc2_hi.db;\n   // Preset de2\n   force dut.reg_file_.b2v_latch_de2_lo.we=1;\n   force dut.reg_file_.b2v_latch_de2_hi.we=1;\n   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_de2_lo.we;\n   release dut.reg_file_.b2v_latch_de2_hi.we;\n   release dut.reg_file_.b2v_latch_de2_lo.db;\n   release dut.reg_file_.b2v_latch_de2_hi.db;\n   // Preset hl2\n   force dut.reg_file_.b2v_latch_hl2_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl2_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_hl2_lo.we;\n   release dut.reg_file_.b2v_latch_hl2_hi.we;\n   release dut.reg_file_.b2v_latch_hl2_lo.db;\n   release dut.reg_file_.b2v_latch_hl2_hi.db;\n   // Preset ix\n   force dut.reg_file_.b2v_latch_ix_lo.we=1;\n   force dut.reg_file_.b2v_latch_ix_hi.we=1;\n   force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ix_lo.we;\n   release dut.reg_file_.b2v_latch_ix_hi.we;\n   release dut.reg_file_.b2v_latch_ix_lo.db;\n   release dut.reg_file_.b2v_latch_ix_hi.db;\n   // Preset iy\n   force dut.reg_file_.b2v_latch_iy_lo.we=1;\n   force dut.reg_file_.b2v_latch_iy_hi.we=1;\n   force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_iy_lo.we;\n   release dut.reg_file_.b2v_latch_iy_hi.we;\n   release dut.reg_file_.b2v_latch_iy_lo.db;\n   release dut.reg_file_.b2v_latch_iy_hi.db;\n   // Preset sp\n   force dut.reg_file_.b2v_latch_sp_lo.we=1;\n   force dut.reg_file_.b2v_latch_sp_hi.we=1;\n   force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_sp_lo.we;\n   release dut.reg_file_.b2v_latch_sp_hi.we;\n   release dut.reg_file_.b2v_latch_sp_lo.db;\n   release dut.reg_file_.b2v_latch_sp_hi.db;\n   // Preset wz\n   force dut.reg_file_.b2v_latch_wz_lo.we=1;\n   force dut.reg_file_.b2v_latch_wz_hi.we=1;\n   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_wz_lo.we;\n   release dut.reg_file_.b2v_latch_wz_hi.we;\n   release dut.reg_file_.b2v_latch_wz_lo.db;\n   release dut.reg_file_.b2v_latch_wz_hi.db;\n   // Preset pc\n   force dut.reg_file_.b2v_latch_pc_lo.we=1;\n   force dut.reg_file_.b2v_latch_pc_hi.we=1;\n   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_pc_lo.we;\n   release dut.reg_file_.b2v_latch_pc_hi.we;\n   release dut.reg_file_.b2v_latch_pc_lo.db;\n   release dut.reg_file_.b2v_latch_pc_hi.db;\n   // Preset ir\n   force dut.reg_file_.b2v_latch_ir_lo.we=1;\n   force dut.reg_file_.b2v_latch_ir_hi.we=1;\n   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ir_lo.we;\n   release dut.reg_file_.b2v_latch_ir_hi.we;\n   release dut.reg_file_.b2v_latch_ir_lo.db;\n   release dut.reg_file_.b2v_latch_ir_hi.db;\n   // Preset memory\n   ram.Mem[0] = 8'hcb;\n   ram.Mem[1] = 8'h11;\n   // Preset memory\n   ram.Mem[60738] = 8'hb7;\n   force dut.z80_top_ifc_n.fpga_reset=0;\n   force dut.address_latch_.Q=16'h0000;\n   release dut.reg_control_.ctl_reg_sys_we;\n   release dut.reg_file_.reg_gp_we;\n#2 // Execute: M1/T1 start\n#1 release dut.address_latch_.Q;\n#1\n#14 // Wait for opcode end\n   force dut.reg_control_.ctl_reg_sys_we=0;\n#2 pc=z.A;\n#2\n#1 force dut.reg_file_.reg_gp_we=0;\n   force dut.z80_top_ifc_n.fpga_reset=1;\n   if (dut.reg_file_.b2v_latch_af_lo.latch!==8'hac) $fdisplay(f,\"* Reg af f=%h !=ac\",dut.reg_file_.b2v_latch_af_lo.latch);\n   if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h65) $fdisplay(f,\"* Reg af a=%h !=65\",dut.reg_file_.b2v_latch_af_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'hb8) $fdisplay(f,\"* Reg bc c=%h !=b8\",dut.reg_file_.b2v_latch_bc_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'he2) $fdisplay(f,\"* Reg bc b=%h !=e2\",dut.reg_file_.b2v_latch_bc_hi.latch);\n   if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h8a) $fdisplay(f,\"* Reg de e=%h !=8a\",dut.reg_file_.b2v_latch_de_lo.latch);\n   if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h4b) $fdisplay(f,\"* Reg de d=%h !=4b\",dut.reg_file_.b2v_latch_de_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h42) $fdisplay(f,\"* Reg hl l=%h !=42\",dut.reg_file_.b2v_latch_hl_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hed) $fdisplay(f,\"* Reg hl h=%h !=ed\",dut.reg_file_.b2v_latch_hl_hi.latch);\n   if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,\"* Reg af2 f=%h !=00\",dut.reg_file_.b2v_latch_af2_lo.latch);\n   if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,\"* Reg af2 a=%h !=00\",dut.reg_file_.b2v_latch_af2_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,\"* Reg bc2 c=%h !=00\",dut.reg_file_.b2v_latch_bc2_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,\"* Reg bc2 b=%h !=00\",dut.reg_file_.b2v_latch_bc2_hi.latch);\n   if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,\"* Reg de2 e=%h !=00\",dut.reg_file_.b2v_latch_de2_lo.latch);\n   if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,\"* Reg de2 d=%h !=00\",dut.reg_file_.b2v_latch_de2_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,\"* Reg hl2 l=%h !=00\",dut.reg_file_.b2v_latch_hl2_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,\"* Reg hl2 h=%h !=00\",dut.reg_file_.b2v_latch_hl2_hi.latch);\n   if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,\"* Reg ix x=%h !=00\",dut.reg_file_.b2v_latch_ix_lo.latch);\n   if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,\"* Reg ix i=%h !=00\",dut.reg_file_.b2v_latch_ix_hi.latch);\n   if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,\"* Reg iy y=%h !=00\",dut.reg_file_.b2v_latch_iy_lo.latch);\n   if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,\"* Reg iy i=%h !=00\",dut.reg_file_.b2v_latch_iy_hi.latch);\n   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,\"* Reg sp p=%h !=00\",dut.reg_file_.b2v_latch_sp_lo.latch);\n   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,\"* Reg sp s=%h !=00\",dut.reg_file_.b2v_latch_sp_hi.latch);\n   if (pc!==16'h0002) $fdisplay(f,\"* PC=%h !=0002\",pc);\n   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,\"* Reg ir r=%h !=02\",dut.reg_file_.b2v_latch_ir_lo.latch);\n   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,\"* Reg ir i=%h !=00\",dut.reg_file_.b2v_latch_ir_hi.latch);\n#1 // End opcode\n\n   force dut.ir_.ctl_ir_we=1;\n   force dut.ir_.db=0;\n#2 release dut.ir_.ctl_ir_we;\n   release dut.ir_.db;\n   $fdisplay(f,\"Testing opcode cb36    SLL (HL)*\");\n   // Preset af\n   force dut.reg_file_.b2v_latch_af_lo.we=1;\n   force dut.reg_file_.b2v_latch_af_hi.we=1;\n   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af_hi.db=8'h8a;\n#2 release dut.reg_file_.b2v_latch_af_lo.we;\n   release dut.reg_file_.b2v_latch_af_hi.we;\n   release dut.reg_file_.b2v_latch_af_lo.db;\n   release dut.reg_file_.b2v_latch_af_hi.db;\n   // Preset bc\n   force dut.reg_file_.b2v_latch_bc_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc_lo.db=8'h85;\n   force dut.reg_file_.b2v_latch_bc_hi.db=8'h11;\n#2 release dut.reg_file_.b2v_latch_bc_lo.we;\n   release dut.reg_file_.b2v_latch_bc_hi.we;\n   release dut.reg_file_.b2v_latch_bc_lo.db;\n   release dut.reg_file_.b2v_latch_bc_hi.db;\n   // Preset de\n   force dut.reg_file_.b2v_latch_de_lo.we=1;\n   force dut.reg_file_.b2v_latch_de_hi.we=1;\n   force dut.reg_file_.b2v_latch_de_lo.db=8'hde;\n   force dut.reg_file_.b2v_latch_de_hi.db=8'h1d;\n#2 release dut.reg_file_.b2v_latch_de_lo.we;\n   release dut.reg_file_.b2v_latch_de_hi.we;\n   release dut.reg_file_.b2v_latch_de_lo.db;\n   release dut.reg_file_.b2v_latch_de_hi.db;\n   // Preset hl\n   force dut.reg_file_.b2v_latch_hl_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl_lo.db=8'h38;\n   force dut.reg_file_.b2v_latch_hl_hi.db=8'h6d;\n#2 release dut.reg_file_.b2v_latch_hl_lo.we;\n   release dut.reg_file_.b2v_latch_hl_hi.we;\n   release dut.reg_file_.b2v_latch_hl_lo.db;\n   release dut.reg_file_.b2v_latch_hl_hi.db;\n   // Preset af2\n   force dut.reg_file_.b2v_latch_af2_lo.we=1;\n   force dut.reg_file_.b2v_latch_af2_hi.we=1;\n   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_af2_lo.we;\n   release dut.reg_file_.b2v_latch_af2_hi.we;\n   release dut.reg_file_.b2v_latch_af2_lo.db;\n   release dut.reg_file_.b2v_latch_af2_hi.db;\n   // Preset bc2\n   force dut.reg_file_.b2v_latch_bc2_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc2_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_bc2_lo.we;\n   release dut.reg_file_.b2v_latch_bc2_hi.we;\n   release dut.reg_file_.b2v_latch_bc2_lo.db;\n   release dut.reg_file_.b2v_latch_bc2_hi.db;\n   // Preset de2\n   force dut.reg_file_.b2v_latch_de2_lo.we=1;\n   force dut.reg_file_.b2v_latch_de2_hi.we=1;\n   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_de2_lo.we;\n   release dut.reg_file_.b2v_latch_de2_hi.we;\n   release dut.reg_file_.b2v_latch_de2_lo.db;\n   release dut.reg_file_.b2v_latch_de2_hi.db;\n   // Preset hl2\n   force dut.reg_file_.b2v_latch_hl2_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl2_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_hl2_lo.we;\n   release dut.reg_file_.b2v_latch_hl2_hi.we;\n   release dut.reg_file_.b2v_latch_hl2_lo.db;\n   release dut.reg_file_.b2v_latch_hl2_hi.db;\n   // Preset ix\n   force dut.reg_file_.b2v_latch_ix_lo.we=1;\n   force dut.reg_file_.b2v_latch_ix_hi.we=1;\n   force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ix_lo.we;\n   release dut.reg_file_.b2v_latch_ix_hi.we;\n   release dut.reg_file_.b2v_latch_ix_lo.db;\n   release dut.reg_file_.b2v_latch_ix_hi.db;\n   // Preset iy\n   force dut.reg_file_.b2v_latch_iy_lo.we=1;\n   force dut.reg_file_.b2v_latch_iy_hi.we=1;\n   force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_iy_lo.we;\n   release dut.reg_file_.b2v_latch_iy_hi.we;\n   release dut.reg_file_.b2v_latch_iy_lo.db;\n   release dut.reg_file_.b2v_latch_iy_hi.db;\n   // Preset sp\n   force dut.reg_file_.b2v_latch_sp_lo.we=1;\n   force dut.reg_file_.b2v_latch_sp_hi.we=1;\n   force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_sp_lo.we;\n   release dut.reg_file_.b2v_latch_sp_hi.we;\n   release dut.reg_file_.b2v_latch_sp_lo.db;\n   release dut.reg_file_.b2v_latch_sp_hi.db;\n   // Preset wz\n   force dut.reg_file_.b2v_latch_wz_lo.we=1;\n   force dut.reg_file_.b2v_latch_wz_hi.we=1;\n   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_wz_lo.we;\n   release dut.reg_file_.b2v_latch_wz_hi.we;\n   release dut.reg_file_.b2v_latch_wz_lo.db;\n   release dut.reg_file_.b2v_latch_wz_hi.db;\n   // Preset pc\n   force dut.reg_file_.b2v_latch_pc_lo.we=1;\n   force dut.reg_file_.b2v_latch_pc_hi.we=1;\n   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_pc_lo.we;\n   release dut.reg_file_.b2v_latch_pc_hi.we;\n   release dut.reg_file_.b2v_latch_pc_lo.db;\n   release dut.reg_file_.b2v_latch_pc_hi.db;\n   // Preset ir\n   force dut.reg_file_.b2v_latch_ir_lo.we=1;\n   force dut.reg_file_.b2v_latch_ir_hi.we=1;\n   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ir_lo.we;\n   release dut.reg_file_.b2v_latch_ir_hi.we;\n   release dut.reg_file_.b2v_latch_ir_lo.db;\n   release dut.reg_file_.b2v_latch_ir_hi.db;\n   // Preset memory\n   ram.Mem[0] = 8'hcb;\n   ram.Mem[1] = 8'h36;\n   // Preset memory\n   ram.Mem[27960] = 8'hf1;\n   force dut.z80_top_ifc_n.fpga_reset=0;\n   force dut.address_latch_.Q=16'h0000;\n   release dut.reg_control_.ctl_reg_sys_we;\n   release dut.reg_file_.reg_gp_we;\n#2 // Execute: M1/T1 start\n#1 release dut.address_latch_.Q;\n#1\n#28 // Wait for opcode end\n   force dut.reg_control_.ctl_reg_sys_we=0;\n#2 pc=z.A;\n#2\n#1 force dut.reg_file_.reg_gp_we=0;\n   force dut.z80_top_ifc_n.fpga_reset=1;\n   if (dut.reg_file_.b2v_latch_af_lo.latch!==8'ha1) $fdisplay(f,\"* Reg af f=%h !=a1\",dut.reg_file_.b2v_latch_af_lo.latch);\n   if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h8a) $fdisplay(f,\"* Reg af a=%h !=8a\",dut.reg_file_.b2v_latch_af_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h85) $fdisplay(f,\"* Reg bc c=%h !=85\",dut.reg_file_.b2v_latch_bc_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h11) $fdisplay(f,\"* Reg bc b=%h !=11\",dut.reg_file_.b2v_latch_bc_hi.latch);\n   if (dut.reg_file_.b2v_latch_de_lo.latch!==8'hde) $fdisplay(f,\"* Reg de e=%h !=de\",dut.reg_file_.b2v_latch_de_lo.latch);\n   if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h1d) $fdisplay(f,\"* Reg de d=%h !=1d\",dut.reg_file_.b2v_latch_de_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h38) $fdisplay(f,\"* Reg hl l=%h !=38\",dut.reg_file_.b2v_latch_hl_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h6d) $fdisplay(f,\"* Reg hl h=%h !=6d\",dut.reg_file_.b2v_latch_hl_hi.latch);\n   if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,\"* Reg af2 f=%h !=00\",dut.reg_file_.b2v_latch_af2_lo.latch);\n   if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,\"* Reg af2 a=%h !=00\",dut.reg_file_.b2v_latch_af2_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,\"* Reg bc2 c=%h !=00\",dut.reg_file_.b2v_latch_bc2_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,\"* Reg bc2 b=%h !=00\",dut.reg_file_.b2v_latch_bc2_hi.latch);\n   if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,\"* Reg de2 e=%h !=00\",dut.reg_file_.b2v_latch_de2_lo.latch);\n   if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,\"* Reg de2 d=%h !=00\",dut.reg_file_.b2v_latch_de2_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,\"* Reg hl2 l=%h !=00\",dut.reg_file_.b2v_latch_hl2_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,\"* Reg hl2 h=%h !=00\",dut.reg_file_.b2v_latch_hl2_hi.latch);\n   if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,\"* Reg ix x=%h !=00\",dut.reg_file_.b2v_latch_ix_lo.latch);\n   if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,\"* Reg ix i=%h !=00\",dut.reg_file_.b2v_latch_ix_hi.latch);\n   if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,\"* Reg iy y=%h !=00\",dut.reg_file_.b2v_latch_iy_lo.latch);\n   if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,\"* Reg iy i=%h !=00\",dut.reg_file_.b2v_latch_iy_hi.latch);\n   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,\"* Reg sp p=%h !=00\",dut.reg_file_.b2v_latch_sp_lo.latch);\n   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,\"* Reg sp s=%h !=00\",dut.reg_file_.b2v_latch_sp_hi.latch);\n   if (pc!==16'h0002) $fdisplay(f,\"* PC=%h !=0002\",pc);\n   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,\"* Reg ir r=%h !=02\",dut.reg_file_.b2v_latch_ir_lo.latch);\n   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,\"* Reg ir i=%h !=00\",dut.reg_file_.b2v_latch_ir_hi.latch);\n   if (ram.Mem[27960]!==8'he3) $fdisplay(f,\"* Mem[6d38]=%h !=e3\",ram.Mem[27960]);\n#1 // End opcode\n\n   force dut.ir_.ctl_ir_we=1;\n   force dut.ir_.db=0;\n#2 release dut.ir_.ctl_ir_we;\n   release dut.ir_.db;\n   $fdisplay(f,\"Testing opcode cb52    BIT 2,D\");\n   // Preset af\n   force dut.reg_file_.b2v_latch_af_lo.we=1;\n   force dut.reg_file_.b2v_latch_af_hi.we=1;\n   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af_hi.db=8'h8b;\n#2 release dut.reg_file_.b2v_latch_af_lo.we;\n   release dut.reg_file_.b2v_latch_af_hi.we;\n   release dut.reg_file_.b2v_latch_af_lo.db;\n   release dut.reg_file_.b2v_latch_af_hi.db;\n   // Preset bc\n   force dut.reg_file_.b2v_latch_bc_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc_lo.db=8'h7a;\n   force dut.reg_file_.b2v_latch_bc_hi.db=8'hff;\n#2 release dut.reg_file_.b2v_latch_bc_lo.we;\n   release dut.reg_file_.b2v_latch_bc_hi.we;\n   release dut.reg_file_.b2v_latch_bc_lo.db;\n   release dut.reg_file_.b2v_latch_bc_hi.db;\n   // Preset de\n   force dut.reg_file_.b2v_latch_de_lo.we=1;\n   force dut.reg_file_.b2v_latch_de_hi.we=1;\n   force dut.reg_file_.b2v_latch_de_lo.db=8'hff;\n   force dut.reg_file_.b2v_latch_de_hi.db=8'hb0;\n#2 release dut.reg_file_.b2v_latch_de_lo.we;\n   release dut.reg_file_.b2v_latch_de_hi.we;\n   release dut.reg_file_.b2v_latch_de_lo.db;\n   release dut.reg_file_.b2v_latch_de_hi.db;\n   // Preset hl\n   force dut.reg_file_.b2v_latch_hl_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl_lo.db=8'h44;\n   force dut.reg_file_.b2v_latch_hl_hi.db=8'hac;\n#2 release dut.reg_file_.b2v_latch_hl_lo.we;\n   release dut.reg_file_.b2v_latch_hl_hi.we;\n   release dut.reg_file_.b2v_latch_hl_lo.db;\n   release dut.reg_file_.b2v_latch_hl_hi.db;\n   // Preset af2\n   force dut.reg_file_.b2v_latch_af2_lo.we=1;\n   force dut.reg_file_.b2v_latch_af2_hi.we=1;\n   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_af2_lo.we;\n   release dut.reg_file_.b2v_latch_af2_hi.we;\n   release dut.reg_file_.b2v_latch_af2_lo.db;\n   release dut.reg_file_.b2v_latch_af2_hi.db;\n   // Preset bc2\n   force dut.reg_file_.b2v_latch_bc2_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc2_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_bc2_lo.we;\n   release dut.reg_file_.b2v_latch_bc2_hi.we;\n   release dut.reg_file_.b2v_latch_bc2_lo.db;\n   release dut.reg_file_.b2v_latch_bc2_hi.db;\n   // Preset de2\n   force dut.reg_file_.b2v_latch_de2_lo.we=1;\n   force dut.reg_file_.b2v_latch_de2_hi.we=1;\n   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_de2_lo.we;\n   release dut.reg_file_.b2v_latch_de2_hi.we;\n   release dut.reg_file_.b2v_latch_de2_lo.db;\n   release dut.reg_file_.b2v_latch_de2_hi.db;\n   // Preset hl2\n   force dut.reg_file_.b2v_latch_hl2_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl2_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_hl2_lo.we;\n   release dut.reg_file_.b2v_latch_hl2_hi.we;\n   release dut.reg_file_.b2v_latch_hl2_lo.db;\n   release dut.reg_file_.b2v_latch_hl2_hi.db;\n   // Preset ix\n   force dut.reg_file_.b2v_latch_ix_lo.we=1;\n   force dut.reg_file_.b2v_latch_ix_hi.we=1;\n   force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ix_lo.we;\n   release dut.reg_file_.b2v_latch_ix_hi.we;\n   release dut.reg_file_.b2v_latch_ix_lo.db;\n   release dut.reg_file_.b2v_latch_ix_hi.db;\n   // Preset iy\n   force dut.reg_file_.b2v_latch_iy_lo.we=1;\n   force dut.reg_file_.b2v_latch_iy_hi.we=1;\n   force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_iy_lo.we;\n   release dut.reg_file_.b2v_latch_iy_hi.we;\n   release dut.reg_file_.b2v_latch_iy_lo.db;\n   release dut.reg_file_.b2v_latch_iy_hi.db;\n   // Preset sp\n   force dut.reg_file_.b2v_latch_sp_lo.we=1;\n   force dut.reg_file_.b2v_latch_sp_hi.we=1;\n   force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_sp_lo.we;\n   release dut.reg_file_.b2v_latch_sp_hi.we;\n   release dut.reg_file_.b2v_latch_sp_lo.db;\n   release dut.reg_file_.b2v_latch_sp_hi.db;\n   // Preset wz\n   force dut.reg_file_.b2v_latch_wz_lo.we=1;\n   force dut.reg_file_.b2v_latch_wz_hi.we=1;\n   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_wz_lo.we;\n   release dut.reg_file_.b2v_latch_wz_hi.we;\n   release dut.reg_file_.b2v_latch_wz_lo.db;\n   release dut.reg_file_.b2v_latch_wz_hi.db;\n   // Preset pc\n   force dut.reg_file_.b2v_latch_pc_lo.we=1;\n   force dut.reg_file_.b2v_latch_pc_hi.we=1;\n   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_pc_lo.we;\n   release dut.reg_file_.b2v_latch_pc_hi.we;\n   release dut.reg_file_.b2v_latch_pc_lo.db;\n   release dut.reg_file_.b2v_latch_pc_hi.db;\n   // Preset ir\n   force dut.reg_file_.b2v_latch_ir_lo.we=1;\n   force dut.reg_file_.b2v_latch_ir_hi.we=1;\n   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ir_lo.we;\n   release dut.reg_file_.b2v_latch_ir_hi.we;\n   release dut.reg_file_.b2v_latch_ir_lo.db;\n   release dut.reg_file_.b2v_latch_ir_hi.db;\n   // Preset memory\n   ram.Mem[0] = 8'hcb;\n   ram.Mem[1] = 8'h52;\n   // Preset memory\n   ram.Mem[44100] = 8'h00;\n   force dut.z80_top_ifc_n.fpga_reset=0;\n   force dut.address_latch_.Q=16'h0000;\n   release dut.reg_control_.ctl_reg_sys_we;\n   release dut.reg_file_.reg_gp_we;\n#2 // Execute: M1/T1 start\n#1 release dut.address_latch_.Q;\n#1\n#14 // Wait for opcode end\n   force dut.reg_control_.ctl_reg_sys_we=0;\n#2 pc=z.A;\n#2\n#1 force dut.reg_file_.reg_gp_we=0;\n   force dut.z80_top_ifc_n.fpga_reset=1;\n   if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h74) $fdisplay(f,\"* Reg af f=%h !=74\",dut.reg_file_.b2v_latch_af_lo.latch);\n   if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h8b) $fdisplay(f,\"* Reg af a=%h !=8b\",dut.reg_file_.b2v_latch_af_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h7a) $fdisplay(f,\"* Reg bc c=%h !=7a\",dut.reg_file_.b2v_latch_bc_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'hff) $fdisplay(f,\"* Reg bc b=%h !=ff\",dut.reg_file_.b2v_latch_bc_hi.latch);\n   if (dut.reg_file_.b2v_latch_de_lo.latch!==8'hff) $fdisplay(f,\"* Reg de e=%h !=ff\",dut.reg_file_.b2v_latch_de_lo.latch);\n   if (dut.reg_file_.b2v_latch_de_hi.latch!==8'hb0) $fdisplay(f,\"* Reg de d=%h !=b0\",dut.reg_file_.b2v_latch_de_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h44) $fdisplay(f,\"* Reg hl l=%h !=44\",dut.reg_file_.b2v_latch_hl_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hac) $fdisplay(f,\"* Reg hl h=%h !=ac\",dut.reg_file_.b2v_latch_hl_hi.latch);\n   if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,\"* Reg af2 f=%h !=00\",dut.reg_file_.b2v_latch_af2_lo.latch);\n   if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,\"* Reg af2 a=%h !=00\",dut.reg_file_.b2v_latch_af2_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,\"* Reg bc2 c=%h !=00\",dut.reg_file_.b2v_latch_bc2_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,\"* Reg bc2 b=%h !=00\",dut.reg_file_.b2v_latch_bc2_hi.latch);\n   if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,\"* Reg de2 e=%h !=00\",dut.reg_file_.b2v_latch_de2_lo.latch);\n   if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,\"* Reg de2 d=%h !=00\",dut.reg_file_.b2v_latch_de2_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,\"* Reg hl2 l=%h !=00\",dut.reg_file_.b2v_latch_hl2_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,\"* Reg hl2 h=%h !=00\",dut.reg_file_.b2v_latch_hl2_hi.latch);\n   if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,\"* Reg ix x=%h !=00\",dut.reg_file_.b2v_latch_ix_lo.latch);\n   if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,\"* Reg ix i=%h !=00\",dut.reg_file_.b2v_latch_ix_hi.latch);\n   if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,\"* Reg iy y=%h !=00\",dut.reg_file_.b2v_latch_iy_lo.latch);\n   if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,\"* Reg iy i=%h !=00\",dut.reg_file_.b2v_latch_iy_hi.latch);\n   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,\"* Reg sp p=%h !=00\",dut.reg_file_.b2v_latch_sp_lo.latch);\n   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,\"* Reg sp s=%h !=00\",dut.reg_file_.b2v_latch_sp_hi.latch);\n   if (pc!==16'h0002) $fdisplay(f,\"* PC=%h !=0002\",pc);\n   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,\"* Reg ir r=%h !=02\",dut.reg_file_.b2v_latch_ir_lo.latch);\n   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,\"* Reg ir i=%h !=00\",dut.reg_file_.b2v_latch_ir_hi.latch);\n#1 // End opcode\n\n   force dut.ir_.ctl_ir_we=1;\n   force dut.ir_.db=0;\n#2 release dut.ir_.ctl_ir_we;\n   release dut.ir_.db;\n   $fdisplay(f,\"Testing opcode cb93    RES 2,E\");\n   // Preset af\n   force dut.reg_file_.b2v_latch_af_lo.we=1;\n   force dut.reg_file_.b2v_latch_af_hi.we=1;\n   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af_hi.db=8'hc2;\n#2 release dut.reg_file_.b2v_latch_af_lo.we;\n   release dut.reg_file_.b2v_latch_af_hi.we;\n   release dut.reg_file_.b2v_latch_af_lo.db;\n   release dut.reg_file_.b2v_latch_af_hi.db;\n   // Preset bc\n   force dut.reg_file_.b2v_latch_bc_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc_lo.db=8'h05;\n   force dut.reg_file_.b2v_latch_bc_hi.db=8'h4e;\n#2 release dut.reg_file_.b2v_latch_bc_lo.we;\n   release dut.reg_file_.b2v_latch_bc_hi.we;\n   release dut.reg_file_.b2v_latch_bc_lo.db;\n   release dut.reg_file_.b2v_latch_bc_hi.db;\n   // Preset de\n   force dut.reg_file_.b2v_latch_de_lo.we=1;\n   force dut.reg_file_.b2v_latch_de_hi.we=1;\n   force dut.reg_file_.b2v_latch_de_lo.db=8'hf8;\n   force dut.reg_file_.b2v_latch_de_hi.db=8'hb3;\n#2 release dut.reg_file_.b2v_latch_de_lo.we;\n   release dut.reg_file_.b2v_latch_de_hi.we;\n   release dut.reg_file_.b2v_latch_de_lo.db;\n   release dut.reg_file_.b2v_latch_de_hi.db;\n   // Preset hl\n   force dut.reg_file_.b2v_latch_hl_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl_lo.db=8'h34;\n   force dut.reg_file_.b2v_latch_hl_hi.db=8'h22;\n#2 release dut.reg_file_.b2v_latch_hl_lo.we;\n   release dut.reg_file_.b2v_latch_hl_hi.we;\n   release dut.reg_file_.b2v_latch_hl_lo.db;\n   release dut.reg_file_.b2v_latch_hl_hi.db;\n   // Preset af2\n   force dut.reg_file_.b2v_latch_af2_lo.we=1;\n   force dut.reg_file_.b2v_latch_af2_hi.we=1;\n   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_af2_lo.we;\n   release dut.reg_file_.b2v_latch_af2_hi.we;\n   release dut.reg_file_.b2v_latch_af2_lo.db;\n   release dut.reg_file_.b2v_latch_af2_hi.db;\n   // Preset bc2\n   force dut.reg_file_.b2v_latch_bc2_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc2_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_bc2_lo.we;\n   release dut.reg_file_.b2v_latch_bc2_hi.we;\n   release dut.reg_file_.b2v_latch_bc2_lo.db;\n   release dut.reg_file_.b2v_latch_bc2_hi.db;\n   // Preset de2\n   force dut.reg_file_.b2v_latch_de2_lo.we=1;\n   force dut.reg_file_.b2v_latch_de2_hi.we=1;\n   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_de2_lo.we;\n   release dut.reg_file_.b2v_latch_de2_hi.we;\n   release dut.reg_file_.b2v_latch_de2_lo.db;\n   release dut.reg_file_.b2v_latch_de2_hi.db;\n   // Preset hl2\n   force dut.reg_file_.b2v_latch_hl2_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl2_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_hl2_lo.we;\n   release dut.reg_file_.b2v_latch_hl2_hi.we;\n   release dut.reg_file_.b2v_latch_hl2_lo.db;\n   release dut.reg_file_.b2v_latch_hl2_hi.db;\n   // Preset ix\n   force dut.reg_file_.b2v_latch_ix_lo.we=1;\n   force dut.reg_file_.b2v_latch_ix_hi.we=1;\n   force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ix_lo.we;\n   release dut.reg_file_.b2v_latch_ix_hi.we;\n   release dut.reg_file_.b2v_latch_ix_lo.db;\n   release dut.reg_file_.b2v_latch_ix_hi.db;\n   // Preset iy\n   force dut.reg_file_.b2v_latch_iy_lo.we=1;\n   force dut.reg_file_.b2v_latch_iy_hi.we=1;\n   force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_iy_lo.we;\n   release dut.reg_file_.b2v_latch_iy_hi.we;\n   release dut.reg_file_.b2v_latch_iy_lo.db;\n   release dut.reg_file_.b2v_latch_iy_hi.db;\n   // Preset sp\n   force dut.reg_file_.b2v_latch_sp_lo.we=1;\n   force dut.reg_file_.b2v_latch_sp_hi.we=1;\n   force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_sp_lo.we;\n   release dut.reg_file_.b2v_latch_sp_hi.we;\n   release dut.reg_file_.b2v_latch_sp_lo.db;\n   release dut.reg_file_.b2v_latch_sp_hi.db;\n   // Preset wz\n   force dut.reg_file_.b2v_latch_wz_lo.we=1;\n   force dut.reg_file_.b2v_latch_wz_hi.we=1;\n   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_wz_lo.we;\n   release dut.reg_file_.b2v_latch_wz_hi.we;\n   release dut.reg_file_.b2v_latch_wz_lo.db;\n   release dut.reg_file_.b2v_latch_wz_hi.db;\n   // Preset pc\n   force dut.reg_file_.b2v_latch_pc_lo.we=1;\n   force dut.reg_file_.b2v_latch_pc_hi.we=1;\n   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_pc_lo.we;\n   release dut.reg_file_.b2v_latch_pc_hi.we;\n   release dut.reg_file_.b2v_latch_pc_lo.db;\n   release dut.reg_file_.b2v_latch_pc_hi.db;\n   // Preset ir\n   force dut.reg_file_.b2v_latch_ir_lo.we=1;\n   force dut.reg_file_.b2v_latch_ir_hi.we=1;\n   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ir_lo.we;\n   release dut.reg_file_.b2v_latch_ir_hi.we;\n   release dut.reg_file_.b2v_latch_ir_lo.db;\n   release dut.reg_file_.b2v_latch_ir_hi.db;\n   // Preset memory\n   ram.Mem[0] = 8'hcb;\n   ram.Mem[1] = 8'h93;\n   // Preset memory\n   ram.Mem[8756] = 8'ha0;\n   force dut.z80_top_ifc_n.fpga_reset=0;\n   force dut.address_latch_.Q=16'h0000;\n   release dut.reg_control_.ctl_reg_sys_we;\n   release dut.reg_file_.reg_gp_we;\n#2 // Execute: M1/T1 start\n#1 release dut.address_latch_.Q;\n#1\n#14 // Wait for opcode end\n   force dut.reg_control_.ctl_reg_sys_we=0;\n#2 pc=z.A;\n#2\n#1 force dut.reg_file_.reg_gp_we=0;\n   force dut.z80_top_ifc_n.fpga_reset=1;\n   if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h00) $fdisplay(f,\"* Reg af f=%h !=00\",dut.reg_file_.b2v_latch_af_lo.latch);\n   if (dut.reg_file_.b2v_latch_af_hi.latch!==8'hc2) $fdisplay(f,\"* Reg af a=%h !=c2\",dut.reg_file_.b2v_latch_af_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h05) $fdisplay(f,\"* Reg bc c=%h !=05\",dut.reg_file_.b2v_latch_bc_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h4e) $fdisplay(f,\"* Reg bc b=%h !=4e\",dut.reg_file_.b2v_latch_bc_hi.latch);\n   if (dut.reg_file_.b2v_latch_de_lo.latch!==8'hf8) $fdisplay(f,\"* Reg de e=%h !=f8\",dut.reg_file_.b2v_latch_de_lo.latch);\n   if (dut.reg_file_.b2v_latch_de_hi.latch!==8'hb3) $fdisplay(f,\"* Reg de d=%h !=b3\",dut.reg_file_.b2v_latch_de_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h34) $fdisplay(f,\"* Reg hl l=%h !=34\",dut.reg_file_.b2v_latch_hl_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h22) $fdisplay(f,\"* Reg hl h=%h !=22\",dut.reg_file_.b2v_latch_hl_hi.latch);\n   if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,\"* Reg af2 f=%h !=00\",dut.reg_file_.b2v_latch_af2_lo.latch);\n   if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,\"* Reg af2 a=%h !=00\",dut.reg_file_.b2v_latch_af2_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,\"* Reg bc2 c=%h !=00\",dut.reg_file_.b2v_latch_bc2_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,\"* Reg bc2 b=%h !=00\",dut.reg_file_.b2v_latch_bc2_hi.latch);\n   if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,\"* Reg de2 e=%h !=00\",dut.reg_file_.b2v_latch_de2_lo.latch);\n   if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,\"* Reg de2 d=%h !=00\",dut.reg_file_.b2v_latch_de2_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,\"* Reg hl2 l=%h !=00\",dut.reg_file_.b2v_latch_hl2_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,\"* Reg hl2 h=%h !=00\",dut.reg_file_.b2v_latch_hl2_hi.latch);\n   if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,\"* Reg ix x=%h !=00\",dut.reg_file_.b2v_latch_ix_lo.latch);\n   if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,\"* Reg ix i=%h !=00\",dut.reg_file_.b2v_latch_ix_hi.latch);\n   if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,\"* Reg iy y=%h !=00\",dut.reg_file_.b2v_latch_iy_lo.latch);\n   if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,\"* Reg iy i=%h !=00\",dut.reg_file_.b2v_latch_iy_hi.latch);\n   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,\"* Reg sp p=%h !=00\",dut.reg_file_.b2v_latch_sp_lo.latch);\n   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,\"* Reg sp s=%h !=00\",dut.reg_file_.b2v_latch_sp_hi.latch);\n   if (pc!==16'h0002) $fdisplay(f,\"* PC=%h !=0002\",pc);\n   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,\"* Reg ir r=%h !=02\",dut.reg_file_.b2v_latch_ir_lo.latch);\n   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,\"* Reg ir i=%h !=00\",dut.reg_file_.b2v_latch_ir_hi.latch);\n#1 // End opcode\n\n   force dut.ir_.ctl_ir_we=1;\n   force dut.ir_.db=0;\n#2 release dut.ir_.ctl_ir_we;\n   release dut.ir_.db;\n   $fdisplay(f,\"Testing opcode cbc4    SET 0,H\");\n   // Preset af\n   force dut.reg_file_.b2v_latch_af_lo.we=1;\n   force dut.reg_file_.b2v_latch_af_hi.we=1;\n   force dut.reg_file_.b2v_latch_af_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af_hi.db=8'h7e;\n#2 release dut.reg_file_.b2v_latch_af_lo.we;\n   release dut.reg_file_.b2v_latch_af_hi.we;\n   release dut.reg_file_.b2v_latch_af_lo.db;\n   release dut.reg_file_.b2v_latch_af_hi.db;\n   // Preset bc\n   force dut.reg_file_.b2v_latch_bc_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc_lo.db=8'h5a;\n   force dut.reg_file_.b2v_latch_bc_hi.db=8'h54;\n#2 release dut.reg_file_.b2v_latch_bc_lo.we;\n   release dut.reg_file_.b2v_latch_bc_hi.we;\n   release dut.reg_file_.b2v_latch_bc_lo.db;\n   release dut.reg_file_.b2v_latch_bc_hi.db;\n   // Preset de\n   force dut.reg_file_.b2v_latch_de_lo.we=1;\n   force dut.reg_file_.b2v_latch_de_hi.we=1;\n   force dut.reg_file_.b2v_latch_de_lo.db=8'hcf;\n   force dut.reg_file_.b2v_latch_de_hi.db=8'h6e;\n#2 release dut.reg_file_.b2v_latch_de_lo.we;\n   release dut.reg_file_.b2v_latch_de_hi.we;\n   release dut.reg_file_.b2v_latch_de_lo.db;\n   release dut.reg_file_.b2v_latch_de_hi.db;\n   // Preset hl\n   force dut.reg_file_.b2v_latch_hl_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl_lo.db=8'h76;\n   force dut.reg_file_.b2v_latch_hl_hi.db=8'h58;\n#2 release dut.reg_file_.b2v_latch_hl_lo.we;\n   release dut.reg_file_.b2v_latch_hl_hi.we;\n   release dut.reg_file_.b2v_latch_hl_lo.db;\n   release dut.reg_file_.b2v_latch_hl_hi.db;\n   // Preset af2\n   force dut.reg_file_.b2v_latch_af2_lo.we=1;\n   force dut.reg_file_.b2v_latch_af2_hi.we=1;\n   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_af2_lo.we;\n   release dut.reg_file_.b2v_latch_af2_hi.we;\n   release dut.reg_file_.b2v_latch_af2_lo.db;\n   release dut.reg_file_.b2v_latch_af2_hi.db;\n   // Preset bc2\n   force dut.reg_file_.b2v_latch_bc2_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc2_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_bc2_lo.we;\n   release dut.reg_file_.b2v_latch_bc2_hi.we;\n   release dut.reg_file_.b2v_latch_bc2_lo.db;\n   release dut.reg_file_.b2v_latch_bc2_hi.db;\n   // Preset de2\n   force dut.reg_file_.b2v_latch_de2_lo.we=1;\n   force dut.reg_file_.b2v_latch_de2_hi.we=1;\n   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_de2_lo.we;\n   release dut.reg_file_.b2v_latch_de2_hi.we;\n   release dut.reg_file_.b2v_latch_de2_lo.db;\n   release dut.reg_file_.b2v_latch_de2_hi.db;\n   // Preset hl2\n   force dut.reg_file_.b2v_latch_hl2_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl2_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_hl2_lo.we;\n   release dut.reg_file_.b2v_latch_hl2_hi.we;\n   release dut.reg_file_.b2v_latch_hl2_lo.db;\n   release dut.reg_file_.b2v_latch_hl2_hi.db;\n   // Preset ix\n   force dut.reg_file_.b2v_latch_ix_lo.we=1;\n   force dut.reg_file_.b2v_latch_ix_hi.we=1;\n   force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ix_lo.we;\n   release dut.reg_file_.b2v_latch_ix_hi.we;\n   release dut.reg_file_.b2v_latch_ix_lo.db;\n   release dut.reg_file_.b2v_latch_ix_hi.db;\n   // Preset iy\n   force dut.reg_file_.b2v_latch_iy_lo.we=1;\n   force dut.reg_file_.b2v_latch_iy_hi.we=1;\n   force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_iy_lo.we;\n   release dut.reg_file_.b2v_latch_iy_hi.we;\n   release dut.reg_file_.b2v_latch_iy_lo.db;\n   release dut.reg_file_.b2v_latch_iy_hi.db;\n   // Preset sp\n   force dut.reg_file_.b2v_latch_sp_lo.we=1;\n   force dut.reg_file_.b2v_latch_sp_hi.we=1;\n   force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_sp_lo.we;\n   release dut.reg_file_.b2v_latch_sp_hi.we;\n   release dut.reg_file_.b2v_latch_sp_lo.db;\n   release dut.reg_file_.b2v_latch_sp_hi.db;\n   // Preset wz\n   force dut.reg_file_.b2v_latch_wz_lo.we=1;\n   force dut.reg_file_.b2v_latch_wz_hi.we=1;\n   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_wz_lo.we;\n   release dut.reg_file_.b2v_latch_wz_hi.we;\n   release dut.reg_file_.b2v_latch_wz_lo.db;\n   release dut.reg_file_.b2v_latch_wz_hi.db;\n   // Preset pc\n   force dut.reg_file_.b2v_latch_pc_lo.we=1;\n   force dut.reg_file_.b2v_latch_pc_hi.we=1;\n   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_pc_lo.we;\n   release dut.reg_file_.b2v_latch_pc_hi.we;\n   release dut.reg_file_.b2v_latch_pc_lo.db;\n   release dut.reg_file_.b2v_latch_pc_hi.db;\n   // Preset ir\n   force dut.reg_file_.b2v_latch_ir_lo.we=1;\n   force dut.reg_file_.b2v_latch_ir_hi.we=1;\n   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ir_lo.we;\n   release dut.reg_file_.b2v_latch_ir_hi.we;\n   release dut.reg_file_.b2v_latch_ir_lo.db;\n   release dut.reg_file_.b2v_latch_ir_hi.db;\n   // Preset memory\n   ram.Mem[0] = 8'hcb;\n   ram.Mem[1] = 8'hc4;\n   // Preset memory\n   ram.Mem[22646] = 8'h9d;\n   force dut.z80_top_ifc_n.fpga_reset=0;\n   force dut.address_latch_.Q=16'h0000;\n   release dut.reg_control_.ctl_reg_sys_we;\n   release dut.reg_file_.reg_gp_we;\n#2 // Execute: M1/T1 start\n#1 release dut.address_latch_.Q;\n#1\n#14 // Wait for opcode end\n   force dut.reg_control_.ctl_reg_sys_we=0;\n#2 pc=z.A;\n#2\n#1 force dut.reg_file_.reg_gp_we=0;\n   force dut.z80_top_ifc_n.fpga_reset=1;\n   if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h00) $fdisplay(f,\"* Reg af f=%h !=00\",dut.reg_file_.b2v_latch_af_lo.latch);\n   if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h7e) $fdisplay(f,\"* Reg af a=%h !=7e\",dut.reg_file_.b2v_latch_af_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h5a) $fdisplay(f,\"* Reg bc c=%h !=5a\",dut.reg_file_.b2v_latch_bc_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h54) $fdisplay(f,\"* Reg bc b=%h !=54\",dut.reg_file_.b2v_latch_bc_hi.latch);\n   if (dut.reg_file_.b2v_latch_de_lo.latch!==8'hcf) $fdisplay(f,\"* Reg de e=%h !=cf\",dut.reg_file_.b2v_latch_de_lo.latch);\n   if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h6e) $fdisplay(f,\"* Reg de d=%h !=6e\",dut.reg_file_.b2v_latch_de_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h76) $fdisplay(f,\"* Reg hl l=%h !=76\",dut.reg_file_.b2v_latch_hl_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h59) $fdisplay(f,\"* Reg hl h=%h !=59\",dut.reg_file_.b2v_latch_hl_hi.latch);\n   if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,\"* Reg af2 f=%h !=00\",dut.reg_file_.b2v_latch_af2_lo.latch);\n   if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,\"* Reg af2 a=%h !=00\",dut.reg_file_.b2v_latch_af2_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,\"* Reg bc2 c=%h !=00\",dut.reg_file_.b2v_latch_bc2_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,\"* Reg bc2 b=%h !=00\",dut.reg_file_.b2v_latch_bc2_hi.latch);\n   if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,\"* Reg de2 e=%h !=00\",dut.reg_file_.b2v_latch_de2_lo.latch);\n   if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,\"* Reg de2 d=%h !=00\",dut.reg_file_.b2v_latch_de2_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,\"* Reg hl2 l=%h !=00\",dut.reg_file_.b2v_latch_hl2_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,\"* Reg hl2 h=%h !=00\",dut.reg_file_.b2v_latch_hl2_hi.latch);\n   if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,\"* Reg ix x=%h !=00\",dut.reg_file_.b2v_latch_ix_lo.latch);\n   if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,\"* Reg ix i=%h !=00\",dut.reg_file_.b2v_latch_ix_hi.latch);\n   if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,\"* Reg iy y=%h !=00\",dut.reg_file_.b2v_latch_iy_lo.latch);\n   if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,\"* Reg iy i=%h !=00\",dut.reg_file_.b2v_latch_iy_hi.latch);\n   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,\"* Reg sp p=%h !=00\",dut.reg_file_.b2v_latch_sp_lo.latch);\n   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,\"* Reg sp s=%h !=00\",dut.reg_file_.b2v_latch_sp_hi.latch);\n   if (pc!==16'h0002) $fdisplay(f,\"* PC=%h !=0002\",pc);\n   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,\"* Reg ir r=%h !=02\",dut.reg_file_.b2v_latch_ir_lo.latch);\n   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,\"* Reg ir i=%h !=00\",dut.reg_file_.b2v_latch_ir_hi.latch);\n#1 // End opcode\n\n   force dut.ir_.ctl_ir_we=1;\n   force dut.ir_.db=0;\n#2 release dut.ir_.ctl_ir_we;\n   release dut.ir_.db;\n   $fdisplay(f,\"Testing opcode dd75    LD (IX+d),L\");\n   // Preset af\n   force dut.reg_file_.b2v_latch_af_lo.we=1;\n   force dut.reg_file_.b2v_latch_af_hi.we=1;\n   force dut.reg_file_.b2v_latch_af_lo.db=8'h72;\n   force dut.reg_file_.b2v_latch_af_hi.db=8'h57;\n#2 release dut.reg_file_.b2v_latch_af_lo.we;\n   release dut.reg_file_.b2v_latch_af_hi.we;\n   release dut.reg_file_.b2v_latch_af_lo.db;\n   release dut.reg_file_.b2v_latch_af_hi.db;\n   // Preset bc\n   force dut.reg_file_.b2v_latch_bc_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc_lo.db=8'h33;\n   force dut.reg_file_.b2v_latch_bc_hi.db=8'he8;\n#2 release dut.reg_file_.b2v_latch_bc_lo.we;\n   release dut.reg_file_.b2v_latch_bc_hi.we;\n   release dut.reg_file_.b2v_latch_bc_lo.db;\n   release dut.reg_file_.b2v_latch_bc_hi.db;\n   // Preset de\n   force dut.reg_file_.b2v_latch_de_lo.we=1;\n   force dut.reg_file_.b2v_latch_de_hi.we=1;\n   force dut.reg_file_.b2v_latch_de_lo.db=8'h3e;\n   force dut.reg_file_.b2v_latch_de_hi.db=8'hb6;\n#2 release dut.reg_file_.b2v_latch_de_lo.we;\n   release dut.reg_file_.b2v_latch_de_hi.we;\n   release dut.reg_file_.b2v_latch_de_lo.db;\n   release dut.reg_file_.b2v_latch_de_hi.db;\n   // Preset hl\n   force dut.reg_file_.b2v_latch_hl_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl_lo.db=8'h4f;\n   force dut.reg_file_.b2v_latch_hl_hi.db=8'h73;\n#2 release dut.reg_file_.b2v_latch_hl_lo.we;\n   release dut.reg_file_.b2v_latch_hl_hi.we;\n   release dut.reg_file_.b2v_latch_hl_lo.db;\n   release dut.reg_file_.b2v_latch_hl_hi.db;\n   // Preset af2\n   force dut.reg_file_.b2v_latch_af2_lo.we=1;\n   force dut.reg_file_.b2v_latch_af2_hi.we=1;\n   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_af2_lo.we;\n   release dut.reg_file_.b2v_latch_af2_hi.we;\n   release dut.reg_file_.b2v_latch_af2_lo.db;\n   release dut.reg_file_.b2v_latch_af2_hi.db;\n   // Preset bc2\n   force dut.reg_file_.b2v_latch_bc2_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc2_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_bc2_lo.we;\n   release dut.reg_file_.b2v_latch_bc2_hi.we;\n   release dut.reg_file_.b2v_latch_bc2_lo.db;\n   release dut.reg_file_.b2v_latch_bc2_hi.db;\n   // Preset de2\n   force dut.reg_file_.b2v_latch_de2_lo.we=1;\n   force dut.reg_file_.b2v_latch_de2_hi.we=1;\n   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_de2_lo.we;\n   release dut.reg_file_.b2v_latch_de2_hi.we;\n   release dut.reg_file_.b2v_latch_de2_lo.db;\n   release dut.reg_file_.b2v_latch_de2_hi.db;\n   // Preset hl2\n   force dut.reg_file_.b2v_latch_hl2_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl2_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_hl2_lo.we;\n   release dut.reg_file_.b2v_latch_hl2_hi.we;\n   release dut.reg_file_.b2v_latch_hl2_lo.db;\n   release dut.reg_file_.b2v_latch_hl2_hi.db;\n   // Preset ix\n   force dut.reg_file_.b2v_latch_ix_lo.we=1;\n   force dut.reg_file_.b2v_latch_ix_hi.we=1;\n   force dut.reg_file_.b2v_latch_ix_lo.db=8'h4c;\n   force dut.reg_file_.b2v_latch_ix_hi.db=8'hae;\n#2 release dut.reg_file_.b2v_latch_ix_lo.we;\n   release dut.reg_file_.b2v_latch_ix_hi.we;\n   release dut.reg_file_.b2v_latch_ix_lo.db;\n   release dut.reg_file_.b2v_latch_ix_hi.db;\n   // Preset iy\n   force dut.reg_file_.b2v_latch_iy_lo.we=1;\n   force dut.reg_file_.b2v_latch_iy_hi.we=1;\n   force dut.reg_file_.b2v_latch_iy_lo.db=8'hc2;\n   force dut.reg_file_.b2v_latch_iy_hi.db=8'he8;\n#2 release dut.reg_file_.b2v_latch_iy_lo.we;\n   release dut.reg_file_.b2v_latch_iy_hi.we;\n   release dut.reg_file_.b2v_latch_iy_lo.db;\n   release dut.reg_file_.b2v_latch_iy_hi.db;\n   // Preset sp\n   force dut.reg_file_.b2v_latch_sp_lo.we=1;\n   force dut.reg_file_.b2v_latch_sp_hi.we=1;\n   force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_sp_lo.we;\n   release dut.reg_file_.b2v_latch_sp_hi.we;\n   release dut.reg_file_.b2v_latch_sp_lo.db;\n   release dut.reg_file_.b2v_latch_sp_hi.db;\n   // Preset wz\n   force dut.reg_file_.b2v_latch_wz_lo.we=1;\n   force dut.reg_file_.b2v_latch_wz_hi.we=1;\n   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_wz_lo.we;\n   release dut.reg_file_.b2v_latch_wz_hi.we;\n   release dut.reg_file_.b2v_latch_wz_lo.db;\n   release dut.reg_file_.b2v_latch_wz_hi.db;\n   // Preset pc\n   force dut.reg_file_.b2v_latch_pc_lo.we=1;\n   force dut.reg_file_.b2v_latch_pc_hi.we=1;\n   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_pc_lo.we;\n   release dut.reg_file_.b2v_latch_pc_hi.we;\n   release dut.reg_file_.b2v_latch_pc_lo.db;\n   release dut.reg_file_.b2v_latch_pc_hi.db;\n   // Preset ir\n   force dut.reg_file_.b2v_latch_ir_lo.we=1;\n   force dut.reg_file_.b2v_latch_ir_hi.we=1;\n   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ir_lo.we;\n   release dut.reg_file_.b2v_latch_ir_hi.we;\n   release dut.reg_file_.b2v_latch_ir_lo.db;\n   release dut.reg_file_.b2v_latch_ir_hi.db;\n   // Preset memory\n   ram.Mem[0] = 8'hdd;\n   ram.Mem[1] = 8'h75;\n   ram.Mem[2] = 8'h30;\n   force dut.z80_top_ifc_n.fpga_reset=0;\n   force dut.address_latch_.Q=16'h0000;\n   release dut.reg_control_.ctl_reg_sys_we;\n   release dut.reg_file_.reg_gp_we;\n#2 // Execute: M1/T1 start\n#1 release dut.address_latch_.Q;\n#1\n#36 // Wait for opcode end\n   force dut.reg_control_.ctl_reg_sys_we=0;\n#2 pc=z.A;\n#2\n#1 force dut.reg_file_.reg_gp_we=0;\n   force dut.z80_top_ifc_n.fpga_reset=1;\n   if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h72) $fdisplay(f,\"* Reg af f=%h !=72\",dut.reg_file_.b2v_latch_af_lo.latch);\n   if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h57) $fdisplay(f,\"* Reg af a=%h !=57\",dut.reg_file_.b2v_latch_af_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h33) $fdisplay(f,\"* Reg bc c=%h !=33\",dut.reg_file_.b2v_latch_bc_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'he8) $fdisplay(f,\"* Reg bc b=%h !=e8\",dut.reg_file_.b2v_latch_bc_hi.latch);\n   if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h3e) $fdisplay(f,\"* Reg de e=%h !=3e\",dut.reg_file_.b2v_latch_de_lo.latch);\n   if (dut.reg_file_.b2v_latch_de_hi.latch!==8'hb6) $fdisplay(f,\"* Reg de d=%h !=b6\",dut.reg_file_.b2v_latch_de_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h4f) $fdisplay(f,\"* Reg hl l=%h !=4f\",dut.reg_file_.b2v_latch_hl_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h73) $fdisplay(f,\"* Reg hl h=%h !=73\",dut.reg_file_.b2v_latch_hl_hi.latch);\n   if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,\"* Reg af2 f=%h !=00\",dut.reg_file_.b2v_latch_af2_lo.latch);\n   if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,\"* Reg af2 a=%h !=00\",dut.reg_file_.b2v_latch_af2_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,\"* Reg bc2 c=%h !=00\",dut.reg_file_.b2v_latch_bc2_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,\"* Reg bc2 b=%h !=00\",dut.reg_file_.b2v_latch_bc2_hi.latch);\n   if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,\"* Reg de2 e=%h !=00\",dut.reg_file_.b2v_latch_de2_lo.latch);\n   if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,\"* Reg de2 d=%h !=00\",dut.reg_file_.b2v_latch_de2_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,\"* Reg hl2 l=%h !=00\",dut.reg_file_.b2v_latch_hl2_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,\"* Reg hl2 h=%h !=00\",dut.reg_file_.b2v_latch_hl2_hi.latch);\n   if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h4c) $fdisplay(f,\"* Reg ix x=%h !=4c\",dut.reg_file_.b2v_latch_ix_lo.latch);\n   if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'hae) $fdisplay(f,\"* Reg ix i=%h !=ae\",dut.reg_file_.b2v_latch_ix_hi.latch);\n   if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'hc2) $fdisplay(f,\"* Reg iy y=%h !=c2\",dut.reg_file_.b2v_latch_iy_lo.latch);\n   if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'he8) $fdisplay(f,\"* Reg iy i=%h !=e8\",dut.reg_file_.b2v_latch_iy_hi.latch);\n   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,\"* Reg sp p=%h !=00\",dut.reg_file_.b2v_latch_sp_lo.latch);\n   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,\"* Reg sp s=%h !=00\",dut.reg_file_.b2v_latch_sp_hi.latch);\n   if (pc!==16'h0003) $fdisplay(f,\"* PC=%h !=0003\",pc);\n   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,\"* Reg ir r=%h !=02\",dut.reg_file_.b2v_latch_ir_lo.latch);\n   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,\"* Reg ir i=%h !=00\",dut.reg_file_.b2v_latch_ir_hi.latch);\n   if (ram.Mem[44668]!==8'h4f) $fdisplay(f,\"* Mem[ae7c]=%h !=4f\",ram.Mem[44668]);\n#1 // End opcode\n\n   force dut.ir_.ctl_ir_we=1;\n   force dut.ir_.db=0;\n#2 release dut.ir_.ctl_ir_we;\n   release dut.ir_.db;\n   $fdisplay(f,\"Testing opcode dd4e    LD C,(IX+d)\");\n   // Preset af\n   force dut.reg_file_.b2v_latch_af_lo.we=1;\n   force dut.reg_file_.b2v_latch_af_hi.we=1;\n   force dut.reg_file_.b2v_latch_af_lo.db=8'hf7;\n   force dut.reg_file_.b2v_latch_af_hi.db=8'h7b;\n#2 release dut.reg_file_.b2v_latch_af_lo.we;\n   release dut.reg_file_.b2v_latch_af_hi.we;\n   release dut.reg_file_.b2v_latch_af_lo.db;\n   release dut.reg_file_.b2v_latch_af_hi.db;\n   // Preset bc\n   force dut.reg_file_.b2v_latch_bc_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc_lo.db=8'h05;\n   force dut.reg_file_.b2v_latch_bc_hi.db=8'h66;\n#2 release dut.reg_file_.b2v_latch_bc_lo.we;\n   release dut.reg_file_.b2v_latch_bc_hi.we;\n   release dut.reg_file_.b2v_latch_bc_lo.db;\n   release dut.reg_file_.b2v_latch_bc_hi.db;\n   // Preset de\n   force dut.reg_file_.b2v_latch_de_lo.we=1;\n   force dut.reg_file_.b2v_latch_de_hi.we=1;\n   force dut.reg_file_.b2v_latch_de_lo.db=8'h55;\n   force dut.reg_file_.b2v_latch_de_hi.db=8'h8d;\n#2 release dut.reg_file_.b2v_latch_de_lo.we;\n   release dut.reg_file_.b2v_latch_de_hi.we;\n   release dut.reg_file_.b2v_latch_de_lo.db;\n   release dut.reg_file_.b2v_latch_de_hi.db;\n   // Preset hl\n   force dut.reg_file_.b2v_latch_hl_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl_lo.db=8'hf2;\n   force dut.reg_file_.b2v_latch_hl_hi.db=8'hde;\n#2 release dut.reg_file_.b2v_latch_hl_lo.we;\n   release dut.reg_file_.b2v_latch_hl_hi.we;\n   release dut.reg_file_.b2v_latch_hl_lo.db;\n   release dut.reg_file_.b2v_latch_hl_hi.db;\n   // Preset af2\n   force dut.reg_file_.b2v_latch_af2_lo.we=1;\n   force dut.reg_file_.b2v_latch_af2_hi.we=1;\n   force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_af2_lo.we;\n   release dut.reg_file_.b2v_latch_af2_hi.we;\n   release dut.reg_file_.b2v_latch_af2_lo.db;\n   release dut.reg_file_.b2v_latch_af2_hi.db;\n   // Preset bc2\n   force dut.reg_file_.b2v_latch_bc2_lo.we=1;\n   force dut.reg_file_.b2v_latch_bc2_hi.we=1;\n   force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_bc2_lo.we;\n   release dut.reg_file_.b2v_latch_bc2_hi.we;\n   release dut.reg_file_.b2v_latch_bc2_lo.db;\n   release dut.reg_file_.b2v_latch_bc2_hi.db;\n   // Preset de2\n   force dut.reg_file_.b2v_latch_de2_lo.we=1;\n   force dut.reg_file_.b2v_latch_de2_hi.we=1;\n   force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_de2_lo.we;\n   release dut.reg_file_.b2v_latch_de2_hi.we;\n   release dut.reg_file_.b2v_latch_de2_lo.db;\n   release dut.reg_file_.b2v_latch_de2_hi.db;\n   // Preset hl2\n   force dut.reg_file_.b2v_latch_hl2_lo.we=1;\n   force dut.reg_file_.b2v_latch_hl2_hi.we=1;\n   force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_hl2_lo.we;\n   release dut.reg_file_.b2v_latch_hl2_hi.we;\n   release dut.reg_file_.b2v_latch_hl2_lo.db;\n   release dut.reg_file_.b2v_latch_hl2_hi.db;\n   // Preset ix\n   force dut.reg_file_.b2v_latch_ix_lo.we=1;\n   force dut.reg_file_.b2v_latch_ix_hi.we=1;\n   force dut.reg_file_.b2v_latch_ix_lo.db=8'h4b;\n   force dut.reg_file_.b2v_latch_ix_hi.db=8'hd9;\n#2 release dut.reg_file_.b2v_latch_ix_lo.we;\n   release dut.reg_file_.b2v_latch_ix_hi.we;\n   release dut.reg_file_.b2v_latch_ix_lo.db;\n   release dut.reg_file_.b2v_latch_ix_hi.db;\n   // Preset iy\n   force dut.reg_file_.b2v_latch_iy_lo.we=1;\n   force dut.reg_file_.b2v_latch_iy_hi.we=1;\n   force dut.reg_file_.b2v_latch_iy_lo.db=8'hfb;\n   force dut.reg_file_.b2v_latch_iy_hi.db=8'h17;\n#2 release dut.reg_file_.b2v_latch_iy_lo.we;\n   release dut.reg_file_.b2v_latch_iy_hi.we;\n   release dut.reg_file_.b2v_latch_iy_lo.db;\n   release dut.reg_file_.b2v_latch_iy_hi.db;\n   // Preset sp\n   force dut.reg_file_.b2v_latch_sp_lo.we=1;\n   force dut.reg_file_.b2v_latch_sp_hi.we=1;\n   force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_sp_lo.we;\n   release dut.reg_file_.b2v_latch_sp_hi.we;\n   release dut.reg_file_.b2v_latch_sp_lo.db;\n   release dut.reg_file_.b2v_latch_sp_hi.db;\n   // Preset wz\n   force dut.reg_file_.b2v_latch_wz_lo.we=1;\n   force dut.reg_file_.b2v_latch_wz_hi.we=1;\n   force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_wz_lo.we;\n   release dut.reg_file_.b2v_latch_wz_hi.we;\n   release dut.reg_file_.b2v_latch_wz_lo.db;\n   release dut.reg_file_.b2v_latch_wz_hi.db;\n   // Preset pc\n   force dut.reg_file_.b2v_latch_pc_lo.we=1;\n   force dut.reg_file_.b2v_latch_pc_hi.we=1;\n   force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_pc_lo.we;\n   release dut.reg_file_.b2v_latch_pc_hi.we;\n   release dut.reg_file_.b2v_latch_pc_lo.db;\n   release dut.reg_file_.b2v_latch_pc_hi.db;\n   // Preset ir\n   force dut.reg_file_.b2v_latch_ir_lo.we=1;\n   force dut.reg_file_.b2v_latch_ir_hi.we=1;\n   force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;\n   force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;\n#2 release dut.reg_file_.b2v_latch_ir_lo.we;\n   release dut.reg_file_.b2v_latch_ir_hi.we;\n   release dut.reg_file_.b2v_latch_ir_lo.db;\n   release dut.reg_file_.b2v_latch_ir_hi.db;\n   // Preset memory\n   ram.Mem[0] = 8'hdd;\n   ram.Mem[1] = 8'h4e;\n   ram.Mem[2] = 8'h2e;\n   // Preset memory\n   ram.Mem[55673] = 8'h76;\n   force dut.z80_top_ifc_n.fpga_reset=0;\n   force dut.address_latch_.Q=16'h0000;\n   release dut.reg_control_.ctl_reg_sys_we;\n   release dut.reg_file_.reg_gp_we;\n#2 // Execute: M1/T1 start\n#1 release dut.address_latch_.Q;\n#1\n#36 // Wait for opcode end\n   force dut.reg_control_.ctl_reg_sys_we=0;\n#2 pc=z.A;\n#2\n#1 force dut.reg_file_.reg_gp_we=0;\n   force dut.z80_top_ifc_n.fpga_reset=1;\n   if (dut.reg_file_.b2v_latch_af_lo.latch!==8'hf7) $fdisplay(f,\"* Reg af f=%h !=f7\",dut.reg_file_.b2v_latch_af_lo.latch);\n   if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h7b) $fdisplay(f,\"* Reg af a=%h !=7b\",dut.reg_file_.b2v_latch_af_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h76) $fdisplay(f,\"* Reg bc c=%h !=76\",dut.reg_file_.b2v_latch_bc_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h66) $fdisplay(f,\"* Reg bc b=%h !=66\",dut.reg_file_.b2v_latch_bc_hi.latch);\n   if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h55) $fdisplay(f,\"* Reg de e=%h !=55\",dut.reg_file_.b2v_latch_de_lo.latch);\n   if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h8d) $fdisplay(f,\"* Reg de d=%h !=8d\",dut.reg_file_.b2v_latch_de_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'hf2) $fdisplay(f,\"* Reg hl l=%h !=f2\",dut.reg_file_.b2v_latch_hl_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hde) $fdisplay(f,\"* Reg hl h=%h !=de\",dut.reg_file_.b2v_latch_hl_hi.latch);\n   if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,\"* Reg af2 f=%h !=00\",dut.reg_file_.b2v_latch_af2_lo.latch);\n   if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,\"* Reg af2 a=%h !=00\",dut.reg_file_.b2v_latch_af2_hi.latch);\n   if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,\"* Reg bc2 c=%h !=00\",dut.reg_file_.b2v_latch_bc2_lo.latch);\n   if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,\"* Reg bc2 b=%h !=00\",dut.reg_file_.b2v_latch_bc2_hi.latch);\n   if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,\"* Reg de2 e=%h !=00\",dut.reg_file_.b2v_latch_de2_lo.latch);\n   if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,\"* Reg de2 d=%h !=00\",dut.reg_file_.b2v_latch_de2_hi.latch);\n   if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,\"* Reg hl2 l=%h !=00\",dut.reg_file_.b2v_latch_hl2_lo.latch);\n   if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,\"* Reg hl2 h=%h !=00\",dut.reg_file_.b2v_latch_hl2_hi.latch);\n   if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h4b) $fdisplay(f,\"* Reg ix x=%h !=4b\",dut.reg_file_.b2v_latch_ix_lo.latch);\n   if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'hd9) $fdisplay(f,\"* Reg ix i=%h !=d9\",dut.reg_file_.b2v_latch_ix_hi.latch);\n   if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'hfb) $fdisplay(f,\"* Reg iy y=%h !=fb\",dut.reg_file_.b2v_latch_iy_lo.latch);\n   if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h17) $fdisplay(f,\"* Reg iy i=%h !=17\",dut.reg_file_.b2v_latch_iy_hi.latch);\n   if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,\"* Reg sp p=%h !=00\",dut.reg_file_.b2v_latch_sp_lo.latch);\n   if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,\"* Reg sp s=%h !=00\",dut.reg_file_.b2v_latch_sp_hi.latch);\n   if (pc!==16'h0003) $fdisplay(f,\"* PC=%h !=0003\",pc);\n   if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,\"* Reg ir r=%h !=02\",dut.reg_file_.b2v_latch_ir_lo.latch);\n   if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,\"* Reg ir i=%h !=00\",dut.reg_file_.b2v_latch_ir_hi.latch);\n#1 // End opcode\n\n`define TOTAL_CLKS 1588\n$fdisplay(f,\"=== Tests completed ===\");\n"
  },
  {
    "path": "cpu/toplevel/test_top.sv",
    "content": "//--------------------------------------------------------------\n// Testbench for the top level design\n//--------------------------------------------------------------\n`include \"z80.svh\"\n\nmodule test_bench_top(z80_if.tb z);\n\nassign clk = z.CLK;\n\ninitial begin : init\n    $display(\"Test: Start of test at %d\", $time);\n    z.nWAIT <= `CLR;\n    z.nINT <= `CLR;\n    z.nNMI <= `CLR;\n    z.nBUSRQ <= `CLR;\n    z.nRESET <= `SET;\n#2  repeat (3) @(posedge clk);\n    z.nRESET <= `CLR;\nend : init\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// Testbench for interrupt testing\n// Enable one or more interrupt generators and run them with the\n// 'hello world' code\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\n// Infuse a NMI at a certain clock\ninitial begin : nmi_once\n    repeat (500) @(posedge clk);\n//    z.nNMI <= `SET;\n    repeat (1) @(posedge clk);\n    z.nNMI <= `CLR;\nend : nmi_once\n\n// Test sending a *periodic* NMI\nalways begin : nmi_rep\n    repeat (3000) @(posedge clk);\n//    z.nNMI <= `SET;\n    repeat (1) @(posedge clk);\n    z.nNMI <= `CLR;\nend : nmi_rep\n\n// Infuse an INT at a certain clock\ninitial begin : int_once\n    repeat (1000) @(posedge clk);\n//    z.nINT <= `SET;\n    repeat (300) @(posedge clk);\n    z.nINT <= `CLR;\nend : int_once\n\n// Test sending a *periodic* INT\nalways begin : int_rep\n    repeat (5000) @(posedge clk);\n//    z.nINT <= `SET;\n    repeat (300) @(posedge clk);\n    z.nINT <= `CLR;\nend : int_rep\n\n// Test WAIT.. inject at will\ninitial begin : wait_once\n    repeat (1008) @(posedge clk);\n//    z.nWAIT <= `SET;\n    repeat (2) @(posedge clk);\n    z.nWAIT <= `CLR;\nend : wait_once\n\n// Test BUSRQ / BUSACK\ninitial begin : busrq_once\n    repeat (10) @(posedge clk);\n//    z.nBUSRQ <= `SET;\n    repeat (10) @(posedge clk);\n    z.nBUSRQ <= `CLR;\nend : busrq_once\n\n// Test special RESET\ninitial begin : spc_reset\n    repeat (40) @(posedge clk);\n//    z.nRESET <= `SET;\n    repeat (1) @(posedge clk);\n    z.nRESET <= `CLR;\nend : spc_reset\n\nendmodule\n\nmodule test_top();\n\n// Although the clock is going forever, we will stop simulation at some point\nbit clk = 1;\ninitial forever #1 clk = ~clk;\n\n// Stop after printing \"Hello, World!\"\ninitial begin : stopme\n    #70000 $stop();\nend : stopme\n\nz80_if z80(clk);            // Instantiate the Z80 bus interface\nz80_top_ifc_n dut(z80);     // Create an instance of our Z80 design\ntest_bench_top tb(z80);     // Create an instance of the test bench\n\nram  ram( .Address(z80.A), .Data(z80.D), .CS(z80.nMREQ), .WE(z80.nWR), .OE(z80.nRD) );\nio   io( .Address(z80.A), .Data(z80.D), .CS(z80.nIORQ), .WE(z80.nWR), .OE(z80.nRD) );\niorq iorq( .Data(z80.D), .M1(z80.nM1), .IORQ(z80.nIORQ) );\n\nendmodule\n"
  },
  {
    "path": "cpu/toplevel/toplevel.bdf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"graphic\" (version \"1.4\"))\n(properties\n\t(page_setup \"orientation\\n1\\npaper_size\\n2\\npaper_source\\n12\\nmargin\\n0.400:1.000:0.400:0.400\\n\")\n)\n(alias \"<<__$DEF_ALIAS430>>\"\"nBUSACK\")\n(alias \"<<__$DEF_ALIAS6200>>\"\"db0[7..0]\")\n(alias \"<<__$DEF_ALIAS423>>\"\"nM1\")\n(alias \"<<__$DEF_ALIAS89>>\"\"nNMI\")\n(alias \"<<__$DEF_ALIAS90>>\"\"nRESET\")\n(alias \"<<__$DEF_ALIAS424>>\"\"nMREQ\")\n(alias \"<<__$DEF_ALIAS91>>\"\"nBUSRQ\")\n(alias \"<<__$DEF_ALIAS425>>\"\"nIORQ\")\n(alias \"<<__$DEF_ALIAS92>>\"\"CLK\")\n(alias \"<<__$DEF_ALIAS426>>\"\"nRD\")\n(alias \"<<__$DEF_ALIAS427>>\"\"nWR\")\n(alias \"<<__$DEF_ALIAS5116>>\"\"db0[7..0]\")\n(alias \"<<__$DEF_ALIAS428>>\"\"nM1;nMREQ;nIORQ;nRD;nWR;nRFSH;nHALT;nWAIT;nBUSACK;nINT;nNMI;nRESET;nBUSRQ;CLK\")\n(alias \"<<__$DEF_ALIAS5171>>\"\"db0[7..0]\")\n(alias \"<<__$DEF_ALIAS429>>\"\"nHALT\")\n(alias \"<<__$DEF_ALIAS87>>\"\"nWAIT\")\n(alias \"<<__$DEF_ALIAS5119>>\"\"db0[7..0]\")\n(alias \"<<__$DEF_ALIAS6208>>\"\"db0[7..0]\")\n(alias \"<<__$DEF_ALIAS88>>\"\"nINT\")\n(pin\n\t(input)\n\t(rect 32 192 208 208)\n\t(text \"INPUT\" (rect 133 0 161 10)(font \"Arial\" (font_size 6)))\n\t(text \"nWAIT\" (rect 9 0 42 12)(font \"Arial\" ))\n\t(pt 176 8)\n\t(drawing\n\t\t(line (pt 92 12)(pt 117 12))\n\t\t(line (pt 92 4)(pt 117 4))\n\t\t(line (pt 121 8)(pt 176 8))\n\t\t(line (pt 92 12)(pt 92 4))\n\t\t(line (pt 117 4)(pt 121 8))\n\t\t(line (pt 117 12)(pt 121 8))\n\t)\n\t(text \"VCC\" (rect 136 7 156 17)(font \"Arial\" (font_size 6)))\n)\n(pin\n\t(input)\n\t(rect 32 208 208 224)\n\t(text \"INPUT\" (rect 133 0 161 10)(font \"Arial\" (font_size 6)))\n\t(text \"nINT\" (rect 9 0 32 12)(font \"Arial\" ))\n\t(pt 176 8)\n\t(drawing\n\t\t(line (pt 92 12)(pt 117 12))\n\t\t(line (pt 92 4)(pt 117 4))\n\t\t(line (pt 121 8)(pt 176 8))\n\t\t(line (pt 92 12)(pt 92 4))\n\t\t(line (pt 117 4)(pt 121 8))\n\t\t(line (pt 117 12)(pt 121 8))\n\t)\n\t(text \"VCC\" (rect 136 7 156 17)(font \"Arial\" (font_size 6)))\n)\n(pin\n\t(input)\n\t(rect 32 224 208 240)\n\t(text \"INPUT\" (rect 133 0 161 10)(font \"Arial\" (font_size 6)))\n\t(text \"nNMI\" (rect 9 0 34 12)(font \"Arial\" ))\n\t(pt 176 8)\n\t(drawing\n\t\t(line (pt 92 12)(pt 117 12))\n\t\t(line (pt 92 4)(pt 117 4))\n\t\t(line (pt 121 8)(pt 176 8))\n\t\t(line (pt 92 12)(pt 92 4))\n\t\t(line (pt 117 4)(pt 121 8))\n\t\t(line (pt 117 12)(pt 121 8))\n\t)\n\t(text \"VCC\" (rect 136 7 156 17)(font \"Arial\" (font_size 6)))\n)\n(pin\n\t(input)\n\t(rect 32 240 208 256)\n\t(text \"INPUT\" (rect 133 0 161 10)(font \"Arial\" (font_size 6)))\n\t(text \"nRESET\" (rect 9 0 50 12)(font \"Arial\" ))\n\t(pt 176 8)\n\t(drawing\n\t\t(line (pt 92 12)(pt 117 12))\n\t\t(line (pt 92 4)(pt 117 4))\n\t\t(line (pt 121 8)(pt 176 8))\n\t\t(line (pt 92 12)(pt 92 4))\n\t\t(line (pt 117 4)(pt 121 8))\n\t\t(line (pt 117 12)(pt 121 8))\n\t)\n\t(text \"VCC\" (rect 136 7 156 17)(font \"Arial\" (font_size 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80)\n\t\t(bidir)\n\t\t)\n)\n(block\n\t(rect 1136 120 1264 200)\n\t(text \"INSTRUCTION REGISTER\" (rect 5 5 139 17)(font \"Arial\" ))\t(text \"instruction_reg_\" (rect 5 78 82 90)(font \"Arial\" ))\t(block_io \"db[7..0]\" (input))\n\t(block_io \"clk\" (input))\n\t(block_io \"ctl_ir_we\" (input))\n\t(block_io \"opcode[7..0]\" (output))\n\t(mapper\n\t\t(pt 128 40)\n\t\t(bidir)\n\t\t(mapping \"db[7..0]\" \"db0[7..0]\" )\n\t\t(annotation_block (mapping)(rect 1312 176 1416 208))\n\t)\n\t(mapper\n\t\t(pt 0 56)\n\t\t(bidir)\n\t\t)\n\t(mapper\n\t\t(pt 88 80)\n\t\t(bidir)\n\t\t)\n)\n(block\n\t(rect 216 24 320 328)\n\t(text \"CONTROL PINS\" (rect 5 5 87 17)(font \"Arial\" ))\t(text \"control_pins_\" (rect 5 302 69 314)(font \"Arial\" ))\t(block_io \"nM1_out\" (input))\n\t(block_io \"pin_control_oe\" (input))\n\t(block_io \"nMREQ_out\" (input))\n\t(block_io \"nIORQ_out\" (input))\n\t(block_io \"nRD_out\" (input))\n\t(block_io \"nWR_out\" (input))\n\t(block_io \"nRFSH_out\" (input))\n\t(block_io \"in_halt\" (input))\n\t(block_io \"pin_nWAIT\" (input))\n\t(block_io \"pin_nBUSRQ\" (input))\n\t(block_io \"busack\" (input))\n\t(block_io \"CPUCLK\" (input))\n\t(block_io \"pin_nINT\" (input))\n\t(block_io \"pin_nNMI\" (input))\n\t(block_io \"pin_nRESET\" (input))\n\t(block_io \"pin_nM1\" (output))\n\t(block_io \"pin_nMREQ\" (output))\n\t(block_io \"pin_nIORQ\" (output))\n\t(block_io \"pin_nRD\" (output))\n\t(block_io \"pin_nWR\" (output))\n\t(block_io \"pin_nRFSH\" (output))\n\t(block_io \"pin_nHALT\" (output))\n\t(block_io \"mwait\" (output))\n\t(block_io \"busrq\" (output))\n\t(block_io \"pin_nBUSACK\" (output))\n\t(block_io \"clk\" (output))\n\t(block_io \"intr\" (output))\n\t(block_io \"nmi\" (output))\n\t(block_io \"reset_in\" (output))\n\t(mapper\n\t\t(pt 0 32)\n\t\t(bidir)\n\t\t(mapping \"pin_nM1\" \"nM1\" )\n\t\t(annotation_block (mapping)(rect 96 72 200 104))\n\t)\n\t(mapper\n\t\t(pt 0 48)\n\t\t(bidir)\n\t\t(mapping \"pin_nMREQ\" \"nMREQ\" )\n\t\t(annotation_block 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248))\n\t)\n\t(mapper\n\t\t(pt 0 192)\n\t\t(bidir)\n\t\t(mapping \"pin_nINT\" \"nINT\" )\n\t\t(annotation_block (mapping)(rect 96 232 200 264))\n\t)\n\t(mapper\n\t\t(pt 0 208)\n\t\t(bidir)\n\t\t(mapping \"pin_nNMI\" \"nNMI\" )\n\t\t(annotation_block (mapping)(rect 88 248 200 280))\n\t)\n\t(mapper\n\t\t(pt 0 224)\n\t\t(bidir)\n\t\t(mapping \"pin_nRESET\" \"nRESET\" )\n\t\t(annotation_block (mapping)(rect 80 264 200 296))\n\t)\n\t(mapper\n\t\t(pt 0 264)\n\t\t(bidir)\n\t\t(mapping \"CPUCLK\" \"CLK\" )\n\t\t(annotation_block (mapping)(rect 96 304 200 336))\n\t)\n\t(mapper\n\t\t(pt 0 240)\n\t\t(bidir)\n\t\t(mapping \"pin_nBUSRQ\" \"nBUSRQ\" )\n\t\t(annotation_block (mapping)(rect 80 280 201 308))\n\t)\n)\n(block\n\t(rect 336 24 1280 80)\n\t(text \"TIMINGS FOR CONTROL PINS\" (rect 5 5 163 17)(font \"Arial\" ))\t(text \"memory_ifc_\" (rect 5 54 71 66)(font \"Arial\" ))\t(block_io \"nM1_int\" (input))\n\t(block_io \"clk\" (input))\n\t(block_io \"nreset\" (input))\n\t(block_io \"setM1\" (input))\n\t(block_io \"timings_en\" (input))\n\t(block_io \"in_intr\" (input))\n\t(block_io \"ctl_mRead\" (input))\n\t(block_io \"ctl_mWrite\" (input))\n\t(block_io \"ctl_iorw\" (input))\n\t(block_io \"fIORead\" (input))\n\t(block_io \"fIOWrite\" (input))\n\t(block_io \"iorq_Tw\" (input))\n\t(block_io \"hold_clk_wait\" (input))\n\t(block_io \"nM1_out\" (output))\n\t(block_io \"nRFSH_out\" (output))\n\t(block_io \"nMREQ_out\" (output))\n\t(block_io \"nRD_out\" (output))\n\t(block_io \"nWR_out\" (output))\n\t(block_io \"nIORQ_out\" (output))\n\t(block_io \"latch_wait\" (output))\n)\n(block\n\t(rect 352 376 456 472)\n\t(text \"RESET UNIT\" (rect 5 5 69 17)(font \"Arial\" ))\t(text \"resets_\" (rect 5 94 41 106)(font \"Arial\" ))\t(block_io \"fpga_reset\" (input))\n\t(block_io \"reset_in\" (input))\n\t(block_io \"M1\" (input))\n\t(block_io \"T2\" (input))\n\t(block_io \"clk\" (input))\n\t(block_io \"clrpc\" (output))\n\t(block_io \"nreset\" (output))\n)\n(block\n\t(rect 488 400 656 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56)\n\t\t(bidir)\n\t\t)\n)\n(block\n\t(rect 488 224 656 376)\n\t(text \"THE SEQUENCER\" (rect 5 5 99 17)(font \"Arial\" ))\t(text \"sequencer_\" (rect 5 150 61 162)(font \"Arial\" ))\t(block_io \"setM1\" (input))\n\t(block_io \"clk\" (input))\n\t(block_io \"nreset\" (input))\n\t(block_io \"nextM\" (input))\n\t(block_io \"hold_clk_iorq\" (input))\n\t(block_io \"hold_clk_wait\" (input))\n\t(block_io \"hold_clk_busrq\" (input))\n\t(block_io \"M1\" (output))\n\t(block_io \"M2\" (output))\n\t(block_io \"M3\" (output))\n\t(block_io \"M4\" (output))\n\t(block_io \"M5\" (output))\n\t(block_io \"T1\" (output))\n\t(block_io \"T2\" (output))\n\t(block_io \"T3\" (output))\n\t(block_io \"T4\" (output))\n\t(block_io \"T5\" (output))\n\t(block_io \"T6\" (output))\n\t(block_io \"timings_en\" (output))\n\t(mapper\n\t\t(pt 168 72)\n\t\t(bidir)\n\t\t)\n)\n(block\n\t(rect 1144 592 1264 664)\n\t(text \"ALU CONTROL\" (rect 5 5 82 17)(font \"Arial\" ))\t(text \"alu_select_\" (rect 5 70 60 82)(font \"Arial\" ))\t(block_io \"ctl_alu_oe\" (input))\n\t(block_io \"ctl_alu_shift_oe\" (input))\n\t(block_io \"ctl_alu_op2_oe\" (input))\n\t(block_io \"ctl_alu_res_oe\" (input))\n\t(block_io \"ctl_alu_op1_oe\" (input))\n\t(block_io \"ctl_alu_bs_oe\" (input))\n\t(block_io \"ctl_alu_op1_sel_bus\" (input))\n\t(block_io \"ctl_alu_op1_sel_low\" (input))\n\t(block_io \"ctl_alu_op1_sel_zero\" (input))\n\t(block_io \"ctl_alu_op2_sel_zero\" (input))\n\t(block_io \"ctl_alu_op2_sel_bus\" (input))\n\t(block_io \"ctl_alu_op2_sel_lq\" (input))\n\t(block_io \"ctl_alu_sel_op2_neg\" (input))\n\t(block_io \"ctl_alu_sel_op2_high\" (input))\n\t(block_io \"ctl_alu_core_R\" (input))\n\t(block_io \"ctl_alu_core_V\" (input))\n\t(block_io \"ctl_alu_core_S\" (input))\n\t(block_io \"alu_oe\" (output))\n\t(block_io \"alu_shift_oe\" (output))\n\t(block_io \"alu_op2_oe\" (output))\n\t(block_io \"alu_res_oe\" (output))\n\t(block_io \"alu_op1_oe\" (output))\n\t(block_io \"alu_bs_oe\" (output))\n\t(block_io \"alu_op1_sel_bus\" (output))\n\t(block_io \"alu_op1_sel_low\" (output))\n\t(block_io \"alu_op1_sel_zero\" (output))\n\t(block_io \"alu_op2_sel_zero\" (output))\n\t(block_io \"alu_op2_sel_bus\" (output))\n\t(block_io \"alu_op2_sel_lq\" (output))\n\t(block_io \"alu_sel_op2_neg\" (output))\n\t(block_io \"alu_sel_op2_high\" (output))\n\t(block_io \"alu_core_R\" (output))\n\t(block_io \"alu_core_V\" (output))\n\t(block_io \"alu_core_S\" (output))\n\t(mapper\n\t\t(pt 64 72)\n\t\t(bidir)\n\t\t)\n\t(mapper\n\t\t(pt 64 0)\n\t\t(bidir)\n\t\t)\n)\n(block\n\t(rect 1344 528 1432 584)\n\t(text \"SW CTRL\" (rect 5 5 54 17)(font \"Arial\" ))\t(text \"bus_switch_\" (rect 5 54 65 66)(font \"Arial\" ))\t(block_io \"ctl_sw_1u\" (input))\n\t(block_io \"ctl_sw_1d\" (input))\n\t(block_io \"ctl_sw_2u\" (input))\n\t(block_io \"ctl_sw_2d\" (input))\n\t(block_io \"ctl_sw_mask543_en\" (input))\n\t(block_io \"bus_sw_1u\" (output))\n\t(block_io \"bus_sw_1d\" (output))\n\t(block_io \"bus_sw_2u\" (output))\n\t(block_io \"bus_sw_2d\" (output))\n\t(block_io \"bus_sw_mask543_en\" (output))\n)\n(block\n\t(rect 352 120 456 232)\n\t(text \"INTERRUPT CONTROL\" (rect 5 5 124 17)(font \"Arial\" ))\t(text \"interrupts_\" (rect 5 110 56 122)(font \"Arial\" ))\t(block_io \"ctl_iff1_iff2\" (input))\n\t(block_io \"ctl_iffx_we\" (input))\n\t(block_io \"ctl_iffx_bit\" (input))\n\t(block_io \"nmi\" (input))\n\t(block_io \"intr\" (input))\n\t(block_io \"setM1\" (input))\n\t(block_io \"ctl_no_ints\" (input))\n\t(block_io \"db[1..0]\" (input))\n\t(block_io \"clk\" (input))\n\t(block_io \"ctl_im_we\" (input))\n\t(block_io \"nreset\" (input))\n\t(block_io \"iff1\" (output))\n\t(block_io \"iff2\" (output))\n\t(block_io \"in_nmi\" (output))\n\t(block_io \"in_intr\" (output))\n\t(block_io \"im1\" (output))\n\t(block_io \"im2\" (output))\n)\n(connector\n\t(pt 1104 176)\n\t(pt 1136 176)\n\t(conduit)\n\t(color 85 0 127)\n)\n(connector\n\t(pt 872 200)\n\t(pt 872 224)\n\t(conduit)\n)\n(connector\n\t(pt 1224 200)\n\t(pt 1224 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160)\n\t(conduit)\n\t(color 255 0 0)\n)\n(connector\n\t(pt 1448 368)\n\t(pt 1448 728)\n\t(conduit)\n)\n(connector\n\t(text \"<<__$DEF_ALIAS423>>\" (rect -240 -96 -122 -84)(font \"Arial\" )(invisible))\n\t(pt 216 56)\n\t(pt 208 56)\n\t(conduit)\n)\n(connector\n\t(text \"<<__$DEF_ALIAS424>>\" (rect -240 -96 -122 -84)(font \"Arial\" )(invisible))\n\t(pt 216 72)\n\t(pt 208 72)\n\t(conduit)\n)\n(connector\n\t(text \"<<__$DEF_ALIAS425>>\" (rect -240 -96 -122 -84)(font \"Arial\" )(invisible))\n\t(pt 216 88)\n\t(pt 208 88)\n\t(conduit)\n)\n(connector\n\t(text \"<<__$DEF_ALIAS426>>\" (rect -240 -96 -122 -84)(font \"Arial\" )(invisible))\n\t(pt 216 104)\n\t(pt 208 104)\n\t(conduit)\n)\n(connector\n\t(text \"<<__$DEF_ALIAS427>>\" (rect -240 -96 -122 -84)(font \"Arial\" )(invisible))\n\t(pt 216 120)\n\t(pt 208 120)\n\t(conduit)\n)\n(connector\n\t(text \"<<__$DEF_ALIAS428>>\" (rect -240 -96 -122 -84)(font \"Arial\" )(invisible))\n\t(pt 216 136)\n\t(pt 208 136)\n\t(conduit)\n)\n(connector\n\t(text \"<<__$DEF_ALIAS429>>\" (rect -240 -96 -122 -84)(font \"Arial\" )(invisible))\n\t(pt 216 152)\n\t(pt 208 152)\n\t(conduit)\n)\n(connector\n\t(text \"<<__$DEF_ALIAS430>>\" (rect -240 -96 -122 -84)(font \"Arial\" )(invisible))\n\t(pt 216 168)\n\t(pt 208 168)\n\t(conduit)\n)\n(connector\n\t(text \"<<__$DEF_ALIAS87>>\" (rect -240 -96 -128 -84)(font \"Arial\" )(invisible))\n\t(pt 216 200)\n\t(pt 208 200)\n\t(conduit)\n)\n(connector\n\t(text \"<<__$DEF_ALIAS88>>\" (rect -240 -96 -128 -84)(font \"Arial\" )(invisible))\n\t(pt 216 216)\n\t(pt 208 216)\n\t(conduit)\n)\n(connector\n\t(text \"<<__$DEF_ALIAS89>>\" (rect -240 -96 -128 -84)(font \"Arial\" )(invisible))\n\t(pt 216 232)\n\t(pt 208 232)\n\t(conduit)\n)\n(connector\n\t(text \"<<__$DEF_ALIAS90>>\" (rect -240 -96 -128 -84)(font \"Arial\" )(invisible))\n\t(pt 216 248)\n\t(pt 208 248)\n\t(conduit)\n)\n(connector\n\t(text \"<<__$DEF_ALIAS91>>\" (rect -240 -96 -128 -84)(font \"Arial\" )(invisible))\n\t(pt 216 264)\n\t(pt 208 264)\n\t(conduit)\n)\n(connector\n\t(text \"<<__$DEF_ALIAS92>>\" (rect -240 -96 -128 -84)(font \"Arial\" )(invisible))\n\t(pt 216 288)\n\t(pt 208 288)\n\t(conduit)\n)\n(connector\n\t(pt 1280 976)\n\t(pt 1288 976)\n\t(conduit)\n)\n(junction (pt 1320 160))\n(junction (pt 1320 448))\n(junction (pt 792 840))\n(text \"CONTROL UNIT\" (rect 688 80 901 110)(font \"Arial Black\" (color 0 0 0)(font_size 16)))\n(text \"ALU\" (rect 880 536 936 566)(font \"Arial Black\" (color 0 0 0)(font_size 16)))\n(text \"REGISTER FILE\" (rect 416 536 623 566)(font \"Arial Black\" (color 0 0 0)(font_size 16)))\n(text \"ADDRESS INCR\" (rect 216 632 421 662)(font \"Arial Black\" (color 0 0 0)(font_size 16)))\n(text \"DB0\" (rect 1332 288 1354 332)(font \"Arial\" (color 0 0 0)(font_size 14))(vertical))\n(text \"DB1\" (rect 1064 672 1108 694)(font \"Arial\" (color 0 0 0)(font_size 14)))\n(text \"DB2\" (rect 768 856 812 878)(font \"Arial\" (color 0 0 0)(font_size 14)))\n(text \"SW1\" (rect 1328 752 1378 774)(font \"Arial\" (color 0 0 0)(font_size 14)))\n(text \"SW2\" (rect 768 648 818 670)(font \"Arial\" (color 0 0 0)(font_size 14)))\n(text \"A-Z80 is internally modelled on the\\noriginal Zilog Z80 CPU. This is a\\nhigh-level block diagram that also\\napproximates the location of modules,\\nbuses and switches on a die.\\n\\nwww.baltazarstudios.com\\n\" (rect 56 432 315 560)(font \"Arial\" (font_size 10)))\n(rectangle (rect 336 104 1280 520)(fill (color 217 255 255)))\n(rectangle (rect 872 576 1280 928)(fill (color 217 255 255)))\n(rectangle (rect 416 576 712 928)(fill (color 217 255 255)))\n(rectangle (rect 200 672 384 928)(fill (color 217 255 255)))\n(rectangle (rect 776 784 808 824)(color 255 255 255)(fill (color 253 211 206)))\n(rectangle (rect 696 824 888 856)(color 253 211 206)(fill (color 253 211 206)))\n(rectangle (rect 384 768 416 832)(color 253 211 206)(fill (color 253 211 206)))\n(rectangle (rect 696 720 744 752)(color 253 211 206)(fill (color 253 211 206)))\n(rectangle (rect 840 680 1296 712)(color 253 211 206)(fill (color 253 211 206)))\n(rectangle (rect 1304 144 1336 624)(color 253 211 206)(fill (color 253 211 206)))\n(rectangle (rect 1280 144 1368 176)(color 253 211 206)(fill (color 253 211 206)))\n(title_block\n\t(rect 56 688 117 1009)\n\t(name \"title-custom-medium\")\n\t(rotate90)\n\t(section (rect 41 81 60 321)(text \"DATE\" (rect 0 210 12 238)(font \"Arial\" )(vertical))(text \"November 16, 2014\" (rect 3 54 19 184)(font \"Arial\" (font_size 10))(vertical))(border))\n\t(section (rect 21 1 40 321)(text \"DESIGNER\" (rect 0 261 12 318)(font \"Arial\" )(vertical))(text \"Goran Devic\" (rect 2 169 19 264)(font \"Arial\" (font_size 11))(vertical))(border))\n\t(section (rect 0 1 20 191)(text \"MODULE\" (rect 1 142 13 188)(font \"Arial\" )(vertical))(text \"CPU TOP LEVEL\" (rect 2 -5 21 147)(font \"Arial\" (font_size 12)(bold))(vertical))(border))\n\t(section (rect 0 1 20 321)(text \"PROJECT\" (rect 0 268 12 318)(font \"Arial\" )(vertical))(text \"A-Z80\" (rect 2 214 21 264)(font \"Arial\" (font_size 12)(bold))(vertical))(border))\n\t(section (rect 41 1 60 80)(text \"REV\" (rect 1 54 13 77)(font \"Arial\" )(vertical))(text \"1.0\" (rect 3 15 19 36)(font \"Arial\" (font_size 10))(vertical))(border))\n\t(drawing\n\t)\n)\n"
  },
  {
    "path": "cpu/toplevel/toplevel.qpf",
    "content": "# -------------------------------------------------------------------------- #\n#\n# Copyright (C) 1991-2013 Altera Corporation\n# Your use of Altera Corporation's design tools, logic functions \n# and other software and tools, and its AMPP partner logic \n# functions, and any output files from any of the foregoing \n# (including device programming or simulation files), and any \n# associated documentation or information are expressly subject \n# to the terms and conditions of the Altera Program License \n# Subscription Agreement, Altera MegaCore Function License \n# Agreement, or other applicable license agreement, including, \n# without limitation, that your use is for the sole purpose of \n# programming logic devices manufactured by Altera and sold by \n# Altera or its authorized distributors.  Please refer to the \n# applicable agreement for further details.\n#\n# -------------------------------------------------------------------------- #\n#\n# Quartus II 64-Bit\n# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\n# Date created = 09:31:29  October 13, 2014\n#\n# -------------------------------------------------------------------------- #\n\nQUARTUS_VERSION = \"13.0\"\nDATE = \"09:31:29  October 13, 2014\"\n\n# Revisions\n\nPROJECT_REVISION = \"toplevel\"\n"
  },
  {
    "path": "cpu/toplevel/toplevel.qsf",
    "content": "# -------------------------------------------------------------------------- #\n#\n# Copyright (C) 1991-2013 Altera Corporation\n# Your use of Altera Corporation's design tools, logic functions \n# and other software and tools, and its AMPP partner logic \n# functions, and any output files from any of the foregoing \n# (including device programming or simulation files), and any \n# associated documentation or information are expressly subject \n# to the terms and conditions of the Altera Program License \n# Subscription Agreement, Altera MegaCore Function License \n# Agreement, or other applicable license agreement, including, \n# without limitation, that your use is for the sole purpose of \n# programming logic devices manufactured by Altera and sold by \n# Altera or its authorized distributors.  Please refer to the \n# applicable agreement for further details.\n#\n# -------------------------------------------------------------------------- #\n#\n# Quartus II 64-Bit\n# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\n# Date created = 09:31:29  October 13, 2014\n#\n# -------------------------------------------------------------------------- #\n#\n# Notes:\n#\n# 1) The default values for assignments are stored in the file:\n#\t\ttoplevel_assignment_defaults.qdf\n#    If this file doesn't exist, see file:\n#\t\tassignment_defaults.qdf\n#\n# 2) Altera recommends that you do not modify this file. This\n#    file is updated automatically by the Quartus II software\n#    and any changes you make may be lost or overwritten.\n#\n# -------------------------------------------------------------------------- #\n\n###########################################################################\n# System Clocks\n###########################################################################\nset_location_assignment PIN_D12 -to CLOCK_27\nset_location_assignment PIN_E12 -to CLOCK_27_1\nset_location_assignment PIN_B12 -to CLOCK_24\nset_location_assignment PIN_A12 -to CLOCK_24_1\nset_location_assignment PIN_L1 -to CLOCK_50\nset_location_assignment PIN_M21 -to EXT_CLOCK\nset_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_27\nset_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_27_1\nset_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_24\nset_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_24_1\nset_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_50\nset_instance_assignment -name IO_STANDARD LVTTL -to EXT_CLOCK\n\n###########################################################################\n# Pushbuttons\n###########################################################################\nset_location_assignment PIN_R22 -to KEY0\nset_location_assignment PIN_R21 -to KEY1\nset_location_assignment PIN_T22 -to KEY2\nset_location_assignment PIN_T21 -to KEY3\nset_instance_assignment -name IO_STANDARD LVTTL -to KEY0\nset_instance_assignment -name IO_STANDARD LVTTL -to KEY1\nset_instance_assignment -name IO_STANDARD LVTTL -to KEY2\nset_instance_assignment -name IO_STANDARD LVTTL -to KEY3\n\n###########################################################################\n# Toggle switches\n###########################################################################\nset_location_assignment PIN_L22 -to SW0\nset_location_assignment PIN_L21 -to SW1\nset_location_assignment PIN_M22 -to SW2\nset_location_assignment PIN_V12 -to SW3\nset_location_assignment PIN_W12 -to SW4\nset_location_assignment PIN_U12 -to SW5\nset_location_assignment PIN_U11 -to SW6\nset_location_assignment PIN_M2 -to SW7\nset_location_assignment PIN_M1 -to SW8\nset_location_assignment PIN_L2 -to SW9\nset_instance_assignment -name IO_STANDARD LVTTL -to SW0\nset_instance_assignment -name IO_STANDARD LVTTL -to SW1\nset_instance_assignment -name IO_STANDARD LVTTL -to SW2\nset_instance_assignment -name IO_STANDARD LVTTL -to SW3\nset_instance_assignment -name IO_STANDARD LVTTL -to SW4\nset_instance_assignment -name IO_STANDARD LVTTL -to SW5\nset_instance_assignment -name IO_STANDARD LVTTL -to SW6\nset_instance_assignment -name IO_STANDARD LVTTL -to SW7\nset_instance_assignment -name IO_STANDARD LVTTL -to SW8\nset_instance_assignment -name IO_STANDARD LVTTL -to SW9\n\n###########################################################################\n# LEDs\n###########################################################################\nset_location_assignment PIN_R20 -to LEDR[0]\nset_location_assignment PIN_R19 -to LEDR[1]\nset_location_assignment PIN_U19 -to LEDR[2]\nset_location_assignment PIN_Y19 -to LEDR[3]\nset_location_assignment PIN_T18 -to LEDR[4]\nset_location_assignment PIN_V19 -to LEDR[5]\nset_location_assignment PIN_Y18 -to LEDR[6]\nset_location_assignment PIN_U18 -to LEDR[7]\nset_location_assignment PIN_R18 -to LEDR[8]\nset_location_assignment PIN_R17 -to LEDR[9]\nset_location_assignment PIN_U22 -to LEDG[0]\nset_location_assignment PIN_U21 -to LEDG[1]\nset_location_assignment PIN_V22 -to LEDG[2]\nset_location_assignment PIN_V21 -to LEDG[3]\nset_location_assignment PIN_W22 -to LEDG[4]\nset_location_assignment PIN_W21 -to LEDG[5]\nset_location_assignment PIN_Y22 -to LEDG[6]\nset_location_assignment PIN_Y21 -to LEDG[7]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDR[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDR[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDR[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDR[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDR[4]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDR[5]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDR[6]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDR[7]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDR[8]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDR[9]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDG[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDG[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDG[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDG[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDG[4]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDG[5]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDG[6]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDG[7]\n\n###########################################################################\n# 7-Segment displays\n###########################################################################\nset_location_assignment PIN_J2 -to HEX0[0]\nset_location_assignment PIN_J1 -to HEX0[1]\nset_location_assignment PIN_H2 -to HEX0[2]\nset_location_assignment PIN_H1 -to HEX0[3]\nset_location_assignment PIN_F2 -to HEX0[4]\nset_location_assignment PIN_F1 -to HEX0[5]\nset_location_assignment PIN_E2 -to HEX0[6]\nset_location_assignment PIN_E1 -to HEX1[0]\nset_location_assignment PIN_H6 -to HEX1[1]\nset_location_assignment PIN_H5 -to HEX1[2]\nset_location_assignment PIN_H4 -to HEX1[3]\nset_location_assignment PIN_G3 -to HEX1[4]\nset_location_assignment PIN_D2 -to HEX1[5]\nset_location_assignment PIN_D1 -to HEX1[6]\nset_location_assignment PIN_G5 -to HEX2[0]\nset_location_assignment PIN_G6 -to HEX2[1]\nset_location_assignment PIN_C2 -to HEX2[2]\nset_location_assignment PIN_C1 -to HEX2[3]\nset_location_assignment PIN_E3 -to HEX2[4]\nset_location_assignment PIN_E4 -to HEX2[5]\nset_location_assignment PIN_D3 -to HEX2[6]\nset_location_assignment PIN_F4 -to HEX3[0]\nset_location_assignment PIN_D5 -to HEX3[1]\nset_location_assignment PIN_D6 -to HEX3[2]\nset_location_assignment PIN_J4 -to HEX3[3]\nset_location_assignment PIN_L8 -to HEX3[4]\nset_location_assignment PIN_F3 -to HEX3[5]\nset_location_assignment PIN_D4 -to HEX3[6]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX0[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX0[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX0[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX0[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX0[4]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX0[5]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX0[6]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX1[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX1[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX1[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX1[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX1[4]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX1[5]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX1[6]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX2[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX2[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX2[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX2[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX2[4]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX2[5]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX2[6]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX3[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX3[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX3[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX3[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX3[4]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX3[5]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX3[6]\n\n###########################################################################\n# VGA\n###########################################################################\nset_location_assignment PIN_D9 -to VGA_R[0]\nset_location_assignment PIN_C9 -to VGA_R[1]\nset_location_assignment PIN_A7 -to VGA_R[2]\nset_location_assignment PIN_B7 -to VGA_R[3]\nset_location_assignment PIN_B8 -to VGA_G[0]\nset_location_assignment PIN_C10 -to VGA_G[1]\nset_location_assignment PIN_B9 -to VGA_G[2]\nset_location_assignment PIN_A8 -to VGA_G[3]\nset_location_assignment PIN_A9 -to VGA_B[0]\nset_location_assignment PIN_D11 -to VGA_B[1]\nset_location_assignment PIN_A10 -to VGA_B[2]\nset_location_assignment PIN_B10 -to VGA_B[3]\nset_location_assignment PIN_A11 -to VGA_HS\nset_location_assignment PIN_B11 -to VGA_VS\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_HS\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_VS\n\n###########################################################################\n# Audio Codec\n###########################################################################\nset_location_assignment PIN_A3 -to I2C_SCLK\nset_location_assignment PIN_B3 -to I2C_SDAT\nset_location_assignment PIN_A6 -to AUD_ADCLRCK\nset_location_assignment PIN_B6 -to AUD_ADCDAT\nset_location_assignment PIN_A5 -to AUD_DACLRCK\nset_location_assignment PIN_B5 -to AUD_DACDAT\nset_location_assignment PIN_B4 -to AUD_XCK\nset_location_assignment PIN_A4 -to AUD_BCLK\nset_instance_assignment -name IO_STANDARD LVTTL -to I2C_SCLK\nset_instance_assignment -name IO_STANDARD LVTTL -to I2C_SDAT\nset_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCLRCK\nset_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCDAT\nset_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACLRCK\nset_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACDAT\nset_instance_assignment -name IO_STANDARD LVTTL -to AUD_XCK\nset_instance_assignment -name IO_STANDARD LVTTL -to AUD_BCLK\n\n###########################################################################\n# Serial (UART)\n###########################################################################\nset_location_assignment PIN_F14 -to UART_RXD\nset_location_assignment PIN_G12 -to UART_TXD\nset_instance_assignment -name IO_STANDARD LVTTL -to UART_RXD\nset_instance_assignment -name IO_STANDARD LVTTL -to UART_TXD\n\n###########################################################################\n# PS/2\n###########################################################################\nset_location_assignment PIN_H15 -to PS2_CLK\nset_location_assignment PIN_J14 -to PS2_DAT\nset_instance_assignment -name IO_STANDARD LVTTL -to PS2_CLK\nset_instance_assignment -name IO_STANDARD LVTTL -to PS2_DAT\n\n###########################################################################\n# SD Card\n###########################################################################\nset_location_assignment PIN_E8 -to TDI\nset_location_assignment PIN_D8 -to TCS\nset_location_assignment PIN_C7 -to TCK\nset_location_assignment PIN_D7 -to TDO\nset_instance_assignment -name IO_STANDARD LVTTL -to TDI\nset_instance_assignment -name IO_STANDARD LVTTL -to TCS\nset_instance_assignment -name IO_STANDARD LVTTL -to TCK\nset_instance_assignment -name IO_STANDARD LVTTL -to TDO\n\n###########################################################################\n# SDRAM\n###########################################################################\nset_location_assignment PIN_W4 -to DRAM_ADDR[0]\nset_location_assignment PIN_W5 -to DRAM_ADDR[1]\nset_location_assignment PIN_Y3 -to DRAM_ADDR[2]\nset_location_assignment PIN_Y4 -to DRAM_ADDR[3]\nset_location_assignment PIN_R6 -to DRAM_ADDR[4]\nset_location_assignment PIN_R5 -to DRAM_ADDR[5]\nset_location_assignment PIN_P6 -to DRAM_ADDR[6]\nset_location_assignment PIN_P5 -to DRAM_ADDR[7]\nset_location_assignment PIN_P3 -to DRAM_ADDR[8]\nset_location_assignment PIN_N4 -to DRAM_ADDR[9]\nset_location_assignment PIN_W3 -to DRAM_ADDR[10]\nset_location_assignment PIN_N6 -to DRAM_ADDR[11]\nset_location_assignment PIN_U1 -to DRAM_DQ[0]\nset_location_assignment PIN_U2 -to DRAM_DQ[1]\nset_location_assignment PIN_V1 -to DRAM_DQ[2]\nset_location_assignment PIN_V2 -to DRAM_DQ[3]\nset_location_assignment PIN_W1 -to DRAM_DQ[4]\nset_location_assignment PIN_W2 -to DRAM_DQ[5]\nset_location_assignment PIN_Y1 -to DRAM_DQ[6]\nset_location_assignment PIN_Y2 -to DRAM_DQ[7]\nset_location_assignment PIN_N1 -to DRAM_DQ[8]\nset_location_assignment PIN_N2 -to DRAM_DQ[9]\nset_location_assignment PIN_P1 -to DRAM_DQ[10]\nset_location_assignment PIN_P2 -to DRAM_DQ[11]\nset_location_assignment PIN_R1 -to DRAM_DQ[12]\nset_location_assignment PIN_R2 -to DRAM_DQ[13]\nset_location_assignment PIN_T1 -to DRAM_DQ[14]\nset_location_assignment PIN_T2 -to DRAM_DQ[15]\nset_location_assignment PIN_U3 -to DRAM_BA_0\nset_location_assignment PIN_V4 -to DRAM_BA_1\nset_location_assignment PIN_R7 -to DRAM_LDQM\nset_location_assignment PIN_M5 -to DRAM_UDQM\nset_location_assignment PIN_T5 -to DRAM_RAS_N\nset_location_assignment PIN_T3 -to DRAM_CAS_N\nset_location_assignment PIN_N3 -to DRAM_CKE\nset_location_assignment PIN_U4 -to DRAM_CLK\nset_location_assignment PIN_R8 -to DRAM_WE_N\nset_location_assignment PIN_T6 -to DRAM_CS_N\n\n###########################################################################\n# SRAM\n###########################################################################\nset_location_assignment PIN_AA3 -to SRAM_ADDR[0]\nset_location_assignment PIN_AB3 -to SRAM_ADDR[1]\nset_location_assignment PIN_AA4 -to SRAM_ADDR[2]\nset_location_assignment PIN_AB4 -to SRAM_ADDR[3]\nset_location_assignment PIN_AA5 -to SRAM_ADDR[4]\nset_location_assignment PIN_AB10 -to SRAM_ADDR[5]\nset_location_assignment PIN_AA11 -to SRAM_ADDR[6]\nset_location_assignment PIN_AB11 -to SRAM_ADDR[7]\nset_location_assignment PIN_V11 -to SRAM_ADDR[8]\nset_location_assignment PIN_W11 -to SRAM_ADDR[9]\nset_location_assignment PIN_R11 -to SRAM_ADDR[10]\nset_location_assignment PIN_T11 -to SRAM_ADDR[11]\nset_location_assignment PIN_Y10 -to SRAM_ADDR[12]\nset_location_assignment PIN_U10 -to SRAM_ADDR[13]\nset_location_assignment PIN_R10 -to SRAM_ADDR[14]\nset_location_assignment PIN_T7 -to SRAM_ADDR[15]\nset_location_assignment PIN_Y6 -to SRAM_ADDR[16]\nset_location_assignment PIN_Y5 -to SRAM_ADDR[17]\nset_location_assignment PIN_AA6 -to SRAM_DQ[0]\nset_location_assignment PIN_AB6 -to SRAM_DQ[1]\nset_location_assignment PIN_AA7 -to SRAM_DQ[2]\nset_location_assignment PIN_AB7 -to SRAM_DQ[3]\nset_location_assignment PIN_AA8 -to SRAM_DQ[4]\nset_location_assignment PIN_AB8 -to SRAM_DQ[5]\nset_location_assignment PIN_AA9 -to SRAM_DQ[6]\nset_location_assignment PIN_AB9 -to SRAM_DQ[7]\nset_location_assignment PIN_Y9 -to SRAM_DQ[8]\nset_location_assignment PIN_W9 -to SRAM_DQ[9]\nset_location_assignment PIN_V9 -to SRAM_DQ[10]\nset_location_assignment PIN_U9 -to SRAM_DQ[11]\nset_location_assignment PIN_R9 -to SRAM_DQ[12]\nset_location_assignment PIN_W8 -to SRAM_DQ[13]\nset_location_assignment PIN_V8 -to SRAM_DQ[14]\nset_location_assignment PIN_U8 -to SRAM_DQ[15]\nset_location_assignment PIN_AB5 -to SRAM_CE_N\nset_location_assignment PIN_T8 -to SRAM_OE_N\nset_location_assignment PIN_AA10 -to SRAM_WE_N\nset_location_assignment PIN_W7 -to SRAM_UB_N\nset_location_assignment PIN_Y7 -to SRAM_LB_N\n\n###########################################################################\n# FLASH\n###########################################################################\nset_location_assignment PIN_AB20 -to FL_ADDR[0]\nset_location_assignment PIN_AA14 -to FL_ADDR[1]\nset_location_assignment PIN_Y16 -to FL_ADDR[2]\nset_location_assignment PIN_R15 -to FL_ADDR[3]\nset_location_assignment PIN_T15 -to FL_ADDR[4]\nset_location_assignment PIN_U15 -to FL_ADDR[5]\nset_location_assignment PIN_V15 -to FL_ADDR[6]\nset_location_assignment PIN_W15 -to FL_ADDR[7]\nset_location_assignment PIN_R14 -to FL_ADDR[8]\nset_location_assignment PIN_Y13 -to FL_ADDR[9]\nset_location_assignment PIN_R12 -to FL_ADDR[10]\nset_location_assignment PIN_T12 -to FL_ADDR[11]\nset_location_assignment PIN_AB14 -to FL_ADDR[12]\nset_location_assignment PIN_AA13 -to FL_ADDR[13]\nset_location_assignment PIN_AB13 -to FL_ADDR[14]\nset_location_assignment PIN_AA12 -to FL_ADDR[15]\nset_location_assignment PIN_AB12 -to FL_ADDR[16]\nset_location_assignment PIN_AA20 -to FL_ADDR[17]\nset_location_assignment PIN_U14 -to FL_ADDR[18]\nset_location_assignment PIN_V14 -to FL_ADDR[19]\nset_location_assignment PIN_U13 -to FL_ADDR[20]\nset_location_assignment PIN_R13 -to FL_ADDR[21]\nset_location_assignment PIN_AB16 -to FL_DQ[0]\nset_location_assignment PIN_AA16 -to FL_DQ[1]\nset_location_assignment PIN_AB17 -to FL_DQ[2]\nset_location_assignment PIN_AA17 -to FL_DQ[3]\nset_location_assignment PIN_AB18 -to FL_DQ[4]\nset_location_assignment PIN_AA18 -to FL_DQ[5]\nset_location_assignment PIN_AB19 -to FL_DQ[6]\nset_location_assignment PIN_AA19 -to FL_DQ[7]\nset_location_assignment PIN_AB15 -to FL_CE_N\nset_location_assignment PIN_AA15 -to FL_OE_N\nset_location_assignment PIN_Y14 -to FL_WE_N\nset_location_assignment PIN_W14 -to FL_RST_N\n\n###########################################################################\n# GPIO-0 Expansion Header 1\n###########################################################################\nset_location_assignment PIN_A13 -to D[0]\nset_location_assignment PIN_B13 -to D[1]\nset_location_assignment PIN_A14 -to D[2]\nset_location_assignment PIN_B14 -to D[3]\nset_location_assignment PIN_A15 -to D[4]\nset_location_assignment PIN_B15 -to D[5]\nset_location_assignment PIN_A16 -to D[6]\nset_location_assignment PIN_B16 -to D[7]\nset_location_assignment PIN_A17 -to A[0]\nset_location_assignment PIN_B17 -to A[1]\nset_location_assignment PIN_A18 -to A[2]\nset_location_assignment PIN_B18 -to A[3]\nset_location_assignment PIN_A19 -to A[4]\nset_location_assignment PIN_B19 -to A[5]\nset_location_assignment PIN_A20 -to A[6]\nset_location_assignment PIN_B20 -to A[7]\nset_location_assignment PIN_C21 -to A[8]\nset_location_assignment PIN_C22 -to A[9]\nset_location_assignment PIN_D21 -to A[10]\nset_location_assignment PIN_D22 -to A[11]\nset_location_assignment PIN_E21 -to A[12]\nset_location_assignment PIN_E22 -to A[13]\nset_location_assignment PIN_F21 -to A[14]\nset_location_assignment PIN_F22 -to A[15]\nset_location_assignment PIN_G21 -to GPIO_0[24]\nset_location_assignment PIN_G22 -to GPIO_0[25]\nset_location_assignment PIN_J21 -to GPIO_0[26]\nset_location_assignment PIN_J22 -to GPIO_0[27]\nset_location_assignment PIN_K21 -to GPIO_0[28]\nset_location_assignment PIN_K22 -to GPIO_0[29]\nset_location_assignment PIN_J19 -to GPIO_0[30]\nset_location_assignment PIN_J20 -to GPIO_0[31]\nset_location_assignment PIN_J18 -to GPIO_0[32]\nset_location_assignment PIN_K20 -to GPIO_0[33]\nset_location_assignment PIN_L19 -to GPIO_0[34]\nset_location_assignment PIN_L18 -to GPIO_0[35]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[4]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[5]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[6]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[7]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[8]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[9]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[10]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[11]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[12]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[13]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[14]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[15]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[16]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[17]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[18]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[19]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[20]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[21]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[22]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[23]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[24]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[25]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[26]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[27]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[28]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[29]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[30]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[31]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[32]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[33]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[34]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[35]\n\n###########################################################################\n# GPIO-1 Expansion Header 2\n###########################################################################\nset_location_assignment PIN_H12 -to GPIO_1[0]\nset_location_assignment PIN_H13 -to GPIO_1[1]\nset_location_assignment PIN_H14 -to GPIO_1[2]\nset_location_assignment PIN_G15 -to GPIO_1[3]\nset_location_assignment PIN_E14 -to GPIO_1[4]\nset_location_assignment PIN_E15 -to GPIO_1[5]\nset_location_assignment PIN_F15 -to GPIO_1[6]\nset_location_assignment PIN_G16 -to GPIO_1[7]\nset_location_assignment PIN_F12 -to GPIO_1[8]\nset_location_assignment PIN_F13 -to GPIO_1[9]\nset_location_assignment PIN_C14 -to GPIO_1[10]\nset_location_assignment PIN_D14 -to GPIO_1[11]\nset_location_assignment PIN_D15 -to GPIO_1[12]\nset_location_assignment PIN_D16 -to GPIO_1[13]\nset_location_assignment PIN_C17 -to GPIO_1[14]\nset_location_assignment PIN_C18 -to GPIO_1[15]\nset_location_assignment PIN_C19 -to GPIO_1[16]\nset_location_assignment PIN_C20 -to GPIO_1[17]\nset_location_assignment PIN_D19 -to GPIO_1[18]\nset_location_assignment PIN_D20 -to GPIO_1[19]\nset_location_assignment PIN_E20 -to GPIO_1[20]\nset_location_assignment PIN_F20 -to GPIO_1[21]\nset_location_assignment PIN_E19 -to GPIO_1[22]\nset_location_assignment PIN_E18 -to GPIO_1[23]\nset_location_assignment PIN_G20 -to GPIO_1[24]\nset_location_assignment PIN_G18 -to GPIO_1[25]\nset_location_assignment PIN_G17 -to GPIO_1[26]\nset_location_assignment PIN_H17 -to GPIO_1[27]\nset_location_assignment PIN_J15 -to GPIO_1[28]\nset_location_assignment PIN_H18 -to GPIO_1[29]\nset_location_assignment PIN_N22 -to GPIO_1[30]\nset_location_assignment PIN_N21 -to GPIO_1[31]\nset_location_assignment PIN_P15 -to GPIO_1[32]\nset_location_assignment PIN_N15 -to GPIO_1[33]\nset_location_assignment PIN_P17 -to GPIO_1[34]\nset_location_assignment PIN_P18 -to GPIO_1[35]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[4]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[5]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[6]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[7]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[8]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[9]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[10]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[11]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[12]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[13]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[14]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[15]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[16]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[17]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[18]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[19]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[20]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[21]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[22]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[23]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[24]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[25]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[26]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[27]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[28]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[29]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[30]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[31]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[32]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[33]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[34]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[35]\n\n#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n# These are some common settings that all DE1 boards might want to have\n# without having to be manually set each time\n#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n\nset_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files\nset_global_assignment -name MIN_CORE_JUNCTION_TEMP 0\nset_global_assignment -name MAX_CORE_JUNCTION_TEMP 85\nset_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1\nset_global_assignment -name USE_CONFIGURATION_DEVICE ON\nset_global_assignment -name RESERVE_ALL_UNUSED_PINS \"AS INPUT TRI-STATED WITH WEAK PULL-UP\"\nset_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON\nset_global_assignment -name SMART_RECOMPILE ON\nset_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON\nset_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4\nset_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS \"NORMAL COMPILATION\"\nset_global_assignment -name OPTIMIZE_POWER_DURING_FITTING \"NORMAL COMPILATION\"\nset_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005\nset_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF\nset_global_assignment -name POWER_PRESET_COOLING_SOLUTION \"23 MM HEAT SINK WITH 200 LFPM AIRFLOW\"\nset_global_assignment -name POWER_BOARD_THERMAL_MODEL \"NONE (CONSERVATIVE)\"\nset_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON\nset_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON\nset_global_assignment -name FITTER_EFFORT \"STANDARD FIT\"\n\n#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n# Quartus managed\n#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n\nset_global_assignment -name FAMILY \"Cyclone II\"\nset_global_assignment -name DEVICE EP2C20F484C7\nset_global_assignment -name TOP_LEVEL_ENTITY toplevel\nset_global_assignment -name ORIGINAL_QUARTUS_VERSION \"13.0 SP1\"\nset_global_assignment -name PROJECT_CREATION_TIME_DATE \"09:31:29  OCTOBER 13, 2014\"\nset_global_assignment -name LAST_QUARTUS_VERSION \"13.0 SP1\"\n\nset_global_assignment -name OPTIMIZE_HOLD_TIMING \"IO PATHS AND MINIMUM TPD PATHS\"\nset_global_assignment -name NUM_PARALLEL_PROCESSORS ALL\nset_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE OPTIMISTIC\nset_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON\nset_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON\nset_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON\nset_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON\nset_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON\nset_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON\nset_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF\nset_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED\n\nset_global_assignment -name SEARCH_PATH \"../alu\"\nset_global_assignment -name SEARCH_PATH \"../bus\"\nset_global_assignment -name SEARCH_PATH \"../control\"\nset_global_assignment -name SEARCH_PATH \"../registers\"\n\nset_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top\nset_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top\nset_global_assignment -name PARTITION_COLOR 16764057 -section_id Top\nset_global_assignment -name STRATIX_DEVICE_IO_STANDARD \"3.3-V LVTTL\"\nset_global_assignment -name BDF_FILE toplevel.bdf\nset_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top"
  },
  {
    "path": "cpu/toplevel/z80.svh",
    "content": "//============================================================================\n// Z80 Top level interface\n//============================================================================\n`ifndef Z80_IFC\n`define Z80_IFC\n\n`timescale 100 ns/ 100 ns\n\n// Define set and clear for the negative logic pins\n`define CLR 1\n`define SET 0\n\ninterface z80_if (input logic CLK);\n    logic nM1, nMREQ, nIORQ, nRD, nWR, nRFSH, nHALT, nBUSACK;\n    logic nWAIT, nINT, nNMI, nRESET, nBUSRQ;\n    logic [15:0] A;\n    wire  [7:0] D;\n\n//=================================================\n// Modport for the CPU module (internal) interface\n// Also considered \"design under test\" port\n//=================================================\nmodport dut (\n    output nM1, nMREQ, nIORQ, nRD, nWR, nRFSH, nHALT, nBUSACK,\n    input  nWAIT, nINT, nNMI, nRESET, nBUSRQ,\n    input  CLK,\n    output A,\n    inout  D);\n\n//=================================================\n// Modport for the user (external) pin interface\n// Also considered a \"test bench\" port\n//=================================================\nmodport tb (\n    input  nM1, nMREQ, nIORQ, nRD, nWR, nRFSH, nHALT, nBUSACK,\n    output nWAIT, nINT, nNMI, nRESET, nBUSRQ,\n    input  CLK,\n    input  A,\n    inout  D);\n\nendinterface : z80_if\n\n`endif\n"
  },
  {
    "path": "cpu/toplevel/z80_top_direct_n.v",
    "content": "//============================================================================\n// Z80 Top level using the direct module declaration\n//============================================================================\n`timescale 1us/ 100 ns\n\nmodule z80_top_direct_n(\n    output wire nM1,\n    output wire nMREQ,\n    output wire nIORQ,\n    output wire nRD,\n    output wire nWR,\n    output wire nRFSH,\n    output wire nHALT,\n    output wire nBUSACK,\n\n    input wire nWAIT,\n    input wire nINT,\n    input wire nNMI,\n    input wire nRESET,\n    input wire nBUSRQ,\n\n    input wire CLK,\n    output wire [15:0] A,\n    inout wire [7:0] D\n);\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// Include core A-Z80 level connecting all internal modules\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n`include \"core.vh\"\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// Address, Data and Control bus drivers connecting to external pins\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\naddress_pins address_pins_(\n    .clk            (clk),\n    .bus_ab_pin_we  (bus_ab_pin_we),\n    .pin_control_oe (pin_control_oe),\n    .address        (address),\n    .abus           (A)\n);\n\ndata_pins data_pins_(\n    .bus_db_pin_oe  (bus_db_pin_oe),\n    .bus_db_pin_re  (bus_db_pin_re),\n    .ctl_bus_db_we  (ctl_bus_db_we),\n    .ctl_bus_db_oe  (ctl_bus_db_oe),\n    .clk            (clk),\n    .db             (db0),\n    .D              (D)\n);\n\ncontrol_pins_n control_pins_(\n    .busack        (busack),\n    .CPUCLK        (CLK),\n    .pin_control_oe(pin_control_oe),\n    .in_halt       (in_halt),\n    .pin_nWAIT     (nWAIT),\n    .pin_nBUSRQ    (nBUSRQ),\n    .pin_nINT      (nINT),\n    .pin_nNMI      (nNMI),\n    .pin_nRESET    (nRESET),\n    .nM1_out       (nM1_out),\n    .nRFSH_out     (nRFSH_out),\n    .nRD_out       (nRD_out),\n    .nWR_out       (nWR_out),\n    .nIORQ_out     (nIORQ_out),\n    .nMREQ_out     (nMREQ_out),\n    .nmi           (nmi),\n    .busrq         (busrq),\n    .clk           (clk),\n    .intr          (intr),\n    .mwait         (mwait),\n    .reset_in      (reset_in),\n    .pin_nM1       (nM1),\n    .pin_nMREQ     (nMREQ),\n    .pin_nIORQ     (nIORQ),\n    .pin_nRD       (nRD),\n    .pin_nWR       (nWR),\n    .pin_nRFSH     (nRFSH),\n    .pin_nHALT     (nHALT),\n    .pin_nBUSACK   (nBUSACK)\n );\n\nendmodule\n"
  },
  {
    "path": "cpu/toplevel/z80_top_ifc_n.sv",
    "content": "//============================================================================\n// Z80 Top level using the interface declaration\n//============================================================================\n`include \"z80.svh\"\n\nmodule z80_top_ifc_n (z80_if.dut z80);\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// Include core A-Z80 level connecting all internal modules\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n`include \"core.vh\"\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// Address, Data and Control bus drivers connecting to external pins\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\naddress_pins   address_pins_( .*, .abus(z80.A[15:0]) );\ndata_pins      data_pins_   ( .*, .db(db0[7:0]), .D(z80.D[7:0]) );\ncontrol_pins_n control_pins_( .*,\n    .pin_nM1      (z80.nM1),\n    .pin_nMREQ    (z80.nMREQ),\n    .pin_nIORQ    (z80.nIORQ),\n    .pin_nRD      (z80.nRD),\n    .pin_nWR      (z80.nWR),\n    .pin_nRFSH    (z80.nRFSH),\n    .pin_nHALT    (z80.nHALT),\n    .pin_nWAIT    (z80.nWAIT),\n    .pin_nBUSACK  (z80.nBUSACK),\n    .pin_nINT     (z80.nINT),\n    .pin_nNMI     (z80.nNMI),\n    .pin_nRESET   (z80.nRESET),\n    .pin_nBUSRQ   (z80.nBUSRQ),\n    .CPUCLK       (z80.CLK)\n );\n\nendmodule\n"
  },
  {
    "path": "host/basic_de1/basic_de1.qpf",
    "content": "# -------------------------------------------------------------------------- #\n#\n# Copyright (C) 1991-2013 Altera Corporation\n# Your use of Altera Corporation's design tools, logic functions\n# and other software and tools, and its AMPP partner logic\n# functions, and any output files from any of the foregoing\n# (including device programming or simulation files), and any\n# associated documentation or information are expressly subject\n# to the terms and conditions of the Altera Program License\n# Subscription Agreement, Altera MegaCore Function License\n# Agreement, or other applicable license agreement, including,\n# without limitation, that your use is for the sole purpose of\n# programming logic devices manufactured by Altera and sold by\n# Altera or its authorized distributors.  Please refer to the\n# applicable agreement for further details.\n#\n# -------------------------------------------------------------------------- #\n#\n# Quartus II 64-Bit\n# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\n# Date created = 13:17:10  October 11, 2014\n#\n# -------------------------------------------------------------------------- #\n\nQUARTUS_VERSION = \"13.0\"\nDATE = \"13:17:10  October 11, 2014\"\n\n# Revisions\n\nPROJECT_REVISION = \"basic_de1\"\n"
  },
  {
    "path": "host/basic_de1/basic_de1.qsf",
    "content": "# -------------------------------------------------------------------------- #\n#\n# Copyright (C) 1991-2013 Altera Corporation\n# Your use of Altera Corporation's design tools, logic functions\n# and other software and tools, and its AMPP partner logic\n# functions, and any output files from any of the foregoing\n# (including device programming or simulation files), and any\n# associated documentation or information are expressly subject\n# to the terms and conditions of the Altera Program License\n# Subscription Agreement, Altera MegaCore Function License\n# Agreement, or other applicable license agreement, including,\n# without limitation, that your use is for the sole purpose of\n# programming logic devices manufactured by Altera and sold by\n# Altera or its authorized distributors.  Please refer to the\n# applicable agreement for further details.\n#\n# -------------------------------------------------------------------------- #\n#\n# Quartus II 64-Bit\n# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\n# Date created = 13:17:10  October 11, 2014\n#\n# -------------------------------------------------------------------------- #\n#\n# Notes:\n#\n# 1) The default values for assignments are stored in the file:\n#       host_de1_assignment_defaults.qdf\n#    If this file doesn't exist, see file:\n#       assignment_defaults.qdf\n#\n# 2) Altera recommends that you do not modify this file. This\n#    file is updated automatically by the Quartus II software\n#    and any changes you make may be lost or overwritten.\n#\n# -------------------------------------------------------------------------- #\n\n###########################################################################\n# System Clocks\n###########################################################################\nset_location_assignment PIN_D12 -to CLOCK_27\nset_location_assignment PIN_E12 -to CLOCK_27_1\nset_location_assignment PIN_B12 -to CLOCK_24\nset_location_assignment PIN_A12 -to CLOCK_24_1\nset_location_assignment PIN_L1 -to CLOCK_50\nset_location_assignment PIN_M21 -to EXT_CLOCK\nset_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_27\nset_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_27_1\nset_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_24\nset_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_24_1\nset_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_50\nset_instance_assignment -name IO_STANDARD LVTTL -to EXT_CLOCK\n\n###########################################################################\n# Pushbuttons\n###########################################################################\nset_location_assignment PIN_R22 -to KEY0\nset_location_assignment PIN_R21 -to KEY1\nset_location_assignment PIN_T22 -to KEY2\nset_location_assignment PIN_T21 -to KEY3\nset_instance_assignment -name IO_STANDARD LVTTL -to KEY0\nset_instance_assignment -name IO_STANDARD LVTTL -to KEY1\nset_instance_assignment -name IO_STANDARD LVTTL -to KEY2\nset_instance_assignment -name IO_STANDARD LVTTL -to KEY3\n\n###########################################################################\n# Toggle switches\n###########################################################################\nset_location_assignment PIN_L22 -to SW0\nset_location_assignment PIN_L21 -to SW1\nset_location_assignment PIN_M22 -to SW2\nset_location_assignment PIN_V12 -to SW3\nset_location_assignment PIN_W12 -to SW4\nset_location_assignment PIN_U12 -to SW5\nset_location_assignment PIN_U11 -to SW6\nset_location_assignment PIN_M2 -to SW7\nset_location_assignment PIN_M1 -to SW8\nset_location_assignment PIN_L2 -to SW9\nset_instance_assignment -name IO_STANDARD LVTTL -to SW0\nset_instance_assignment -name IO_STANDARD LVTTL -to SW1\nset_instance_assignment -name IO_STANDARD LVTTL -to SW2\nset_instance_assignment -name IO_STANDARD LVTTL -to SW3\nset_instance_assignment -name IO_STANDARD LVTTL -to SW4\nset_instance_assignment -name IO_STANDARD LVTTL -to SW5\nset_instance_assignment -name IO_STANDARD LVTTL -to SW6\nset_instance_assignment -name IO_STANDARD LVTTL -to SW7\nset_instance_assignment -name IO_STANDARD LVTTL -to SW8\nset_instance_assignment -name IO_STANDARD LVTTL -to SW9\n\n###########################################################################\n# LEDs\n###########################################################################\nset_location_assignment PIN_R20 -to LEDR[0]\nset_location_assignment PIN_R19 -to LEDR[1]\nset_location_assignment PIN_U19 -to LEDR[2]\nset_location_assignment PIN_Y19 -to LEDR[3]\nset_location_assignment PIN_T18 -to LEDR[4]\nset_location_assignment PIN_V19 -to LEDR[5]\nset_location_assignment PIN_Y18 -to LEDR[6]\nset_location_assignment PIN_U18 -to LEDR[7]\nset_location_assignment PIN_R18 -to LEDR[8]\nset_location_assignment PIN_R17 -to LEDR[9]\nset_location_assignment PIN_U22 -to LEDG[0]\nset_location_assignment PIN_U21 -to LEDG[1]\nset_location_assignment PIN_V22 -to LEDG[2]\nset_location_assignment PIN_V21 -to LEDG[3]\nset_location_assignment PIN_W22 -to LEDG[4]\nset_location_assignment PIN_W21 -to LEDG[5]\nset_location_assignment PIN_Y22 -to LEDG[6]\nset_location_assignment PIN_Y21 -to LEDG[7]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDR[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDR[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDR[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDR[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDR[4]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDR[5]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDR[6]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDR[7]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDR[8]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDR[9]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDG[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDG[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDG[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDG[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDG[4]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDG[5]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDG[6]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDG[7]\n\n###########################################################################\n# 7-Segment displays\n###########################################################################\nset_location_assignment PIN_J2 -to HEX0[0]\nset_location_assignment PIN_J1 -to HEX0[1]\nset_location_assignment PIN_H2 -to HEX0[2]\nset_location_assignment PIN_H1 -to HEX0[3]\nset_location_assignment PIN_F2 -to HEX0[4]\nset_location_assignment PIN_F1 -to HEX0[5]\nset_location_assignment PIN_E2 -to HEX0[6]\nset_location_assignment PIN_E1 -to HEX1[0]\nset_location_assignment PIN_H6 -to HEX1[1]\nset_location_assignment PIN_H5 -to HEX1[2]\nset_location_assignment PIN_H4 -to HEX1[3]\nset_location_assignment PIN_G3 -to HEX1[4]\nset_location_assignment PIN_D2 -to HEX1[5]\nset_location_assignment PIN_D1 -to HEX1[6]\nset_location_assignment PIN_G5 -to HEX2[0]\nset_location_assignment PIN_G6 -to HEX2[1]\nset_location_assignment PIN_C2 -to HEX2[2]\nset_location_assignment PIN_C1 -to HEX2[3]\nset_location_assignment PIN_E3 -to HEX2[4]\nset_location_assignment PIN_E4 -to HEX2[5]\nset_location_assignment PIN_D3 -to HEX2[6]\nset_location_assignment PIN_F4 -to HEX3[0]\nset_location_assignment PIN_D5 -to HEX3[1]\nset_location_assignment PIN_D6 -to HEX3[2]\nset_location_assignment PIN_J4 -to HEX3[3]\nset_location_assignment PIN_L8 -to HEX3[4]\nset_location_assignment PIN_F3 -to HEX3[5]\nset_location_assignment PIN_D4 -to HEX3[6]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX0[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX0[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX0[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX0[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX0[4]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX0[5]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX0[6]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX1[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX1[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX1[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX1[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX1[4]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX1[5]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX1[6]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX2[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX2[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX2[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX2[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX2[4]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX2[5]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX2[6]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX3[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX3[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX3[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX3[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX3[4]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX3[5]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX3[6]\n\n###########################################################################\n# VGA\n###########################################################################\nset_location_assignment PIN_D9 -to VGA_R[0]\nset_location_assignment PIN_C9 -to VGA_R[1]\nset_location_assignment PIN_A7 -to VGA_R[2]\nset_location_assignment PIN_B7 -to VGA_R[3]\nset_location_assignment PIN_B8 -to VGA_G[0]\nset_location_assignment PIN_C10 -to VGA_G[1]\nset_location_assignment PIN_B9 -to VGA_G[2]\nset_location_assignment PIN_A8 -to VGA_G[3]\nset_location_assignment PIN_A9 -to VGA_B[0]\nset_location_assignment PIN_D11 -to VGA_B[1]\nset_location_assignment PIN_A10 -to VGA_B[2]\nset_location_assignment PIN_B10 -to VGA_B[3]\nset_location_assignment PIN_A11 -to VGA_HS\nset_location_assignment PIN_B11 -to VGA_VS\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_HS\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_VS\n\n###########################################################################\n# Audio Codec\n###########################################################################\nset_location_assignment PIN_A3 -to I2C_SCLK\nset_location_assignment PIN_B3 -to I2C_SDAT\nset_location_assignment PIN_A6 -to AUD_ADCLRCK\nset_location_assignment PIN_B6 -to AUD_ADCDAT\nset_location_assignment PIN_A5 -to AUD_DACLRCK\nset_location_assignment PIN_B5 -to AUD_DACDAT\nset_location_assignment PIN_B4 -to AUD_XCK\nset_location_assignment PIN_A4 -to AUD_BCLK\nset_instance_assignment -name IO_STANDARD LVTTL -to I2C_SCLK\nset_instance_assignment -name IO_STANDARD LVTTL -to I2C_SDAT\nset_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCLRCK\nset_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCDAT\nset_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACLRCK\nset_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACDAT\nset_instance_assignment -name IO_STANDARD LVTTL -to AUD_XCK\nset_instance_assignment -name IO_STANDARD LVTTL -to AUD_BCLK\n\n###########################################################################\n# Serial (UART)\n###########################################################################\nset_location_assignment PIN_F14 -to UART_RXD\nset_location_assignment PIN_G12 -to UART_TXD\nset_instance_assignment -name IO_STANDARD LVTTL -to UART_RXD\nset_instance_assignment -name IO_STANDARD LVTTL -to UART_TXD\n\n###########################################################################\n# PS/2\n###########################################################################\nset_location_assignment PIN_H15 -to PS2_CLK\nset_location_assignment PIN_J14 -to PS2_DAT\nset_instance_assignment -name IO_STANDARD LVTTL -to PS2_CLK\nset_instance_assignment -name IO_STANDARD LVTTL -to PS2_DAT\n\n###########################################################################\n# SD Card\n###########################################################################\nset_location_assignment PIN_E8 -to TDI\nset_location_assignment PIN_D8 -to TCS\nset_location_assignment PIN_C7 -to TCK\nset_location_assignment PIN_D7 -to TDO\nset_instance_assignment -name IO_STANDARD LVTTL -to TDI\nset_instance_assignment -name IO_STANDARD LVTTL -to TCS\nset_instance_assignment -name IO_STANDARD LVTTL -to TCK\nset_instance_assignment -name IO_STANDARD LVTTL -to TDO\n\n###########################################################################\n# SDRAM\n###########################################################################\nset_location_assignment PIN_W4 -to DRAM_ADDR[0]\nset_location_assignment PIN_W5 -to DRAM_ADDR[1]\nset_location_assignment PIN_Y3 -to DRAM_ADDR[2]\nset_location_assignment PIN_Y4 -to DRAM_ADDR[3]\nset_location_assignment PIN_R6 -to DRAM_ADDR[4]\nset_location_assignment PIN_R5 -to DRAM_ADDR[5]\nset_location_assignment PIN_P6 -to DRAM_ADDR[6]\nset_location_assignment PIN_P5 -to DRAM_ADDR[7]\nset_location_assignment PIN_P3 -to DRAM_ADDR[8]\nset_location_assignment PIN_N4 -to DRAM_ADDR[9]\nset_location_assignment PIN_W3 -to DRAM_ADDR[10]\nset_location_assignment PIN_N6 -to DRAM_ADDR[11]\nset_location_assignment PIN_U1 -to DRAM_DQ[0]\nset_location_assignment PIN_U2 -to DRAM_DQ[1]\nset_location_assignment PIN_V1 -to DRAM_DQ[2]\nset_location_assignment PIN_V2 -to DRAM_DQ[3]\nset_location_assignment PIN_W1 -to DRAM_DQ[4]\nset_location_assignment PIN_W2 -to DRAM_DQ[5]\nset_location_assignment PIN_Y1 -to DRAM_DQ[6]\nset_location_assignment PIN_Y2 -to DRAM_DQ[7]\nset_location_assignment PIN_N1 -to DRAM_DQ[8]\nset_location_assignment PIN_N2 -to DRAM_DQ[9]\nset_location_assignment PIN_P1 -to DRAM_DQ[10]\nset_location_assignment PIN_P2 -to DRAM_DQ[11]\nset_location_assignment PIN_R1 -to DRAM_DQ[12]\nset_location_assignment PIN_R2 -to DRAM_DQ[13]\nset_location_assignment PIN_T1 -to DRAM_DQ[14]\nset_location_assignment PIN_T2 -to DRAM_DQ[15]\nset_location_assignment PIN_U3 -to DRAM_BA_0\nset_location_assignment PIN_V4 -to DRAM_BA_1\nset_location_assignment PIN_R7 -to DRAM_LDQM\nset_location_assignment PIN_M5 -to DRAM_UDQM\nset_location_assignment PIN_T5 -to DRAM_RAS_N\nset_location_assignment PIN_T3 -to DRAM_CAS_N\nset_location_assignment PIN_N3 -to DRAM_CKE\nset_location_assignment PIN_U4 -to DRAM_CLK\nset_location_assignment PIN_R8 -to DRAM_WE_N\nset_location_assignment PIN_T6 -to DRAM_CS_N\n\n###########################################################################\n# SRAM\n###########################################################################\nset_location_assignment PIN_AA3 -to SRAM_ADDR[0]\nset_location_assignment PIN_AB3 -to SRAM_ADDR[1]\nset_location_assignment PIN_AA4 -to SRAM_ADDR[2]\nset_location_assignment PIN_AB4 -to SRAM_ADDR[3]\nset_location_assignment PIN_AA5 -to SRAM_ADDR[4]\nset_location_assignment PIN_AB10 -to SRAM_ADDR[5]\nset_location_assignment PIN_AA11 -to SRAM_ADDR[6]\nset_location_assignment PIN_AB11 -to SRAM_ADDR[7]\nset_location_assignment PIN_V11 -to SRAM_ADDR[8]\nset_location_assignment PIN_W11 -to SRAM_ADDR[9]\nset_location_assignment PIN_R11 -to SRAM_ADDR[10]\nset_location_assignment PIN_T11 -to SRAM_ADDR[11]\nset_location_assignment PIN_Y10 -to SRAM_ADDR[12]\nset_location_assignment PIN_U10 -to SRAM_ADDR[13]\nset_location_assignment PIN_R10 -to SRAM_ADDR[14]\nset_location_assignment PIN_T7 -to SRAM_ADDR[15]\nset_location_assignment PIN_Y6 -to SRAM_ADDR[16]\nset_location_assignment PIN_Y5 -to SRAM_ADDR[17]\nset_location_assignment PIN_AA6 -to SRAM_DQ[0]\nset_location_assignment PIN_AB6 -to SRAM_DQ[1]\nset_location_assignment PIN_AA7 -to SRAM_DQ[2]\nset_location_assignment PIN_AB7 -to SRAM_DQ[3]\nset_location_assignment PIN_AA8 -to SRAM_DQ[4]\nset_location_assignment PIN_AB8 -to SRAM_DQ[5]\nset_location_assignment PIN_AA9 -to SRAM_DQ[6]\nset_location_assignment PIN_AB9 -to SRAM_DQ[7]\nset_location_assignment PIN_Y9 -to SRAM_DQ[8]\nset_location_assignment PIN_W9 -to SRAM_DQ[9]\nset_location_assignment PIN_V9 -to SRAM_DQ[10]\nset_location_assignment PIN_U9 -to SRAM_DQ[11]\nset_location_assignment PIN_R9 -to SRAM_DQ[12]\nset_location_assignment PIN_W8 -to SRAM_DQ[13]\nset_location_assignment PIN_V8 -to SRAM_DQ[14]\nset_location_assignment PIN_U8 -to SRAM_DQ[15]\nset_location_assignment PIN_AB5 -to SRAM_CE_N\nset_location_assignment PIN_T8 -to SRAM_OE_N\nset_location_assignment PIN_AA10 -to SRAM_WE_N\nset_location_assignment PIN_W7 -to SRAM_UB_N\nset_location_assignment PIN_Y7 -to SRAM_LB_N\n\n###########################################################################\n# FLASH\n###########################################################################\nset_location_assignment PIN_AB20 -to FL_ADDR[0]\nset_location_assignment PIN_AA14 -to FL_ADDR[1]\nset_location_assignment PIN_Y16 -to FL_ADDR[2]\nset_location_assignment PIN_R15 -to FL_ADDR[3]\nset_location_assignment PIN_T15 -to FL_ADDR[4]\nset_location_assignment PIN_U15 -to FL_ADDR[5]\nset_location_assignment PIN_V15 -to FL_ADDR[6]\nset_location_assignment PIN_W15 -to FL_ADDR[7]\nset_location_assignment PIN_R14 -to FL_ADDR[8]\nset_location_assignment PIN_Y13 -to FL_ADDR[9]\nset_location_assignment PIN_R12 -to FL_ADDR[10]\nset_location_assignment PIN_T12 -to FL_ADDR[11]\nset_location_assignment PIN_AB14 -to FL_ADDR[12]\nset_location_assignment PIN_AA13 -to FL_ADDR[13]\nset_location_assignment PIN_AB13 -to FL_ADDR[14]\nset_location_assignment PIN_AA12 -to FL_ADDR[15]\nset_location_assignment PIN_AB12 -to FL_ADDR[16]\nset_location_assignment PIN_AA20 -to FL_ADDR[17]\nset_location_assignment PIN_U14 -to FL_ADDR[18]\nset_location_assignment PIN_V14 -to FL_ADDR[19]\nset_location_assignment PIN_U13 -to FL_ADDR[20]\nset_location_assignment PIN_R13 -to FL_ADDR[21]\nset_location_assignment PIN_AB16 -to FL_DQ[0]\nset_location_assignment PIN_AA16 -to FL_DQ[1]\nset_location_assignment PIN_AB17 -to FL_DQ[2]\nset_location_assignment PIN_AA17 -to FL_DQ[3]\nset_location_assignment PIN_AB18 -to FL_DQ[4]\nset_location_assignment PIN_AA18 -to FL_DQ[5]\nset_location_assignment PIN_AB19 -to FL_DQ[6]\nset_location_assignment PIN_AA19 -to FL_DQ[7]\nset_location_assignment PIN_AB15 -to FL_CE_N\nset_location_assignment PIN_AA15 -to FL_OE_N\nset_location_assignment PIN_Y14 -to FL_WE_N\nset_location_assignment PIN_W14 -to FL_RST_N\n\n###########################################################################\n# GPIO-0 Expansion Header 1\n###########################################################################\nset_location_assignment PIN_A13 -to GPIO_0[0]\nset_location_assignment PIN_B13 -to GPIO_0[1]\nset_location_assignment PIN_A14 -to GPIO_0[2]\nset_location_assignment PIN_B14 -to GPIO_0[3]\nset_location_assignment PIN_A15 -to GPIO_0[4]\nset_location_assignment PIN_B15 -to GPIO_0[5]\nset_location_assignment PIN_A16 -to GPIO_0[6]\nset_location_assignment PIN_B16 -to GPIO_0[7]\nset_location_assignment PIN_A17 -to GPIO_0[8]\nset_location_assignment PIN_B17 -to GPIO_0[9]\nset_location_assignment PIN_A18 -to GPIO_0[10]\nset_location_assignment PIN_B18 -to GPIO_0[11]\nset_location_assignment PIN_A19 -to GPIO_0[12]\nset_location_assignment PIN_B19 -to GPIO_0[13]\nset_location_assignment PIN_A20 -to GPIO_0[14]\nset_location_assignment PIN_B20 -to GPIO_0[15]\nset_location_assignment PIN_C21 -to GPIO_0[16]\nset_location_assignment PIN_C22 -to GPIO_0[17]\nset_location_assignment PIN_D21 -to GPIO_0[18]\nset_location_assignment PIN_D22 -to GPIO_0[19]\nset_location_assignment PIN_E21 -to GPIO_0[20]\nset_location_assignment PIN_E22 -to GPIO_0[21]\nset_location_assignment PIN_F21 -to GPIO_0[22]\nset_location_assignment PIN_F22 -to GPIO_0[23]\nset_location_assignment PIN_G21 -to GPIO_0[24]\nset_location_assignment PIN_G22 -to GPIO_0[25]\nset_location_assignment PIN_J21 -to GPIO_0[26]\nset_location_assignment PIN_J22 -to GPIO_0[27]\nset_location_assignment PIN_K21 -to GPIO_0[28]\nset_location_assignment PIN_K22 -to GPIO_0[29]\nset_location_assignment PIN_J19 -to GPIO_0[30]\nset_location_assignment PIN_J20 -to GPIO_0[31]\nset_location_assignment PIN_J18 -to GPIO_0[32]\nset_location_assignment PIN_K20 -to GPIO_0[33]\nset_location_assignment PIN_L19 -to GPIO_0[34]\nset_location_assignment PIN_L18 -to GPIO_0[35]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[4]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[5]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[6]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[7]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[8]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[9]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[10]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[11]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[12]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[13]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[14]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[15]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[16]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[17]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[18]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[19]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[20]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[21]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[22]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[23]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[24]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[25]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[26]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[27]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[28]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[29]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[30]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[31]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[32]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[33]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[34]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[35]\n\n###########################################################################\n# GPIO-1 Expansion Header 2\n###########################################################################\nset_location_assignment PIN_H12 -to GPIO_1[0]\nset_location_assignment PIN_H13 -to GPIO_1[1]\nset_location_assignment PIN_H14 -to GPIO_1[2]\nset_location_assignment PIN_G15 -to GPIO_1[3]\nset_location_assignment PIN_E14 -to GPIO_1[4]\nset_location_assignment PIN_E15 -to GPIO_1[5]\nset_location_assignment PIN_F15 -to GPIO_1[6]\nset_location_assignment PIN_G16 -to GPIO_1[7]\nset_location_assignment PIN_F12 -to GPIO_1[8]\nset_location_assignment PIN_F13 -to GPIO_1[9]\nset_location_assignment PIN_C14 -to GPIO_1[10]\nset_location_assignment PIN_D14 -to GPIO_1[11]\nset_location_assignment PIN_D15 -to GPIO_1[12]\nset_location_assignment PIN_D16 -to GPIO_1[13]\nset_location_assignment PIN_C17 -to GPIO_1[14]\nset_location_assignment PIN_C18 -to GPIO_1[15]\nset_location_assignment PIN_C19 -to GPIO_1[16]\nset_location_assignment PIN_C20 -to GPIO_1[17]\nset_location_assignment PIN_D19 -to GPIO_1[18]\nset_location_assignment PIN_D20 -to GPIO_1[19]\nset_location_assignment PIN_E20 -to GPIO_1[20]\nset_location_assignment PIN_F20 -to GPIO_1[21]\nset_location_assignment PIN_E19 -to GPIO_1[22]\nset_location_assignment PIN_E18 -to GPIO_1[23]\nset_location_assignment PIN_G20 -to GPIO_1[24]\nset_location_assignment PIN_G18 -to GPIO_1[25]\nset_location_assignment PIN_G17 -to GPIO_1[26]\nset_location_assignment PIN_H17 -to GPIO_1[27]\nset_location_assignment PIN_J15 -to GPIO_1[28]\nset_location_assignment PIN_H18 -to GPIO_1[29]\nset_location_assignment PIN_N22 -to GPIO_1[30]\nset_location_assignment PIN_N21 -to GPIO_1[31]\nset_location_assignment PIN_P15 -to GPIO_1[32]\nset_location_assignment PIN_N15 -to GPIO_1[33]\nset_location_assignment PIN_P17 -to GPIO_1[34]\nset_location_assignment PIN_P18 -to GPIO_1[35]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[4]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[5]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[6]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[7]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[8]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[9]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[10]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[11]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[12]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[13]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[14]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[15]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[16]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[17]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[18]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[19]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[20]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[21]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[22]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[23]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[24]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[25]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[26]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[27]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[28]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[29]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[30]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[31]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[32]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[33]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[34]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[35]\n\n#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n# These are some common settings that all DE1 boards might want to have\n# without having to be manually set each time\n#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n\nset_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files\nset_global_assignment -name MIN_CORE_JUNCTION_TEMP 0\nset_global_assignment -name MAX_CORE_JUNCTION_TEMP 85\nset_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1\nset_global_assignment -name USE_CONFIGURATION_DEVICE ON\nset_global_assignment -name RESERVE_ALL_UNUSED_PINS \"AS INPUT TRI-STATED WITH WEAK PULL-UP\"\nset_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON\nset_global_assignment -name SMART_RECOMPILE ON\nset_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON\nset_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4\nset_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS \"NORMAL COMPILATION\"\nset_global_assignment -name OPTIMIZE_POWER_DURING_FITTING \"NORMAL COMPILATION\"\nset_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005\nset_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF\nset_global_assignment -name POWER_PRESET_COOLING_SOLUTION \"23 MM HEAT SINK WITH 200 LFPM AIRFLOW\"\nset_global_assignment -name POWER_BOARD_THERMAL_MODEL \"NONE (CONSERVATIVE)\"\nset_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON\nset_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON\nset_global_assignment -name FITTER_EFFORT \"STANDARD FIT\"\n\n#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n# Quartus managed\n#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n\nset_global_assignment -name FAMILY \"Cyclone II\"\nset_global_assignment -name DEVICE EP2C20F484C7\nset_global_assignment -name TOP_LEVEL_ENTITY host\nset_global_assignment -name ORIGINAL_QUARTUS_VERSION \"13.0 SP1\"\nset_global_assignment -name PROJECT_CREATION_TIME_DATE \"13:17:10  OCTOBER 11, 2014\"\nset_global_assignment -name LAST_QUARTUS_VERSION \"13.0 SP1\"\nset_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top\nset_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top\nset_global_assignment -name PARTITION_COLOR 16764057 -section_id Top\nset_global_assignment -name STRATIX_DEVICE_IO_STANDARD \"3.3-V LVTTL\"\n\n\nset_global_assignment -name OPTIMIZE_HOLD_TIMING \"ALL PATHS\"\nset_global_assignment -name NUM_PARALLEL_PROCESSORS ALL\nset_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE OPTIMISTIC\nset_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON\nset_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF\nset_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF\nset_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF\nset_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF\nset_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF\nset_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF\nset_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED\n\n\nset_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT FAST\nset_global_assignment -name TIMEQUEST_DO_REPORT_TIMING OFF\nset_global_assignment -name SDC_FILE basic_de1.sdc\nset_global_assignment -name VERILOG_FILE ../../cpu/bus/bus_switch.v\nset_global_assignment -name VERILOG_FILE ../../cpu/control/execute.v\nset_global_assignment -name VERILOG_FILE ../../cpu/control/pla_decode.v\nset_global_assignment -name VERILOG_FILE ../../cpu/toplevel/z80_top_direct_n.v\nset_global_assignment -name VERILOG_FILE ../../cpu/alu/alu.v\nset_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_bit_select.v\nset_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_control.v\nset_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_core.v\nset_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_flags.v\nset_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_mux_2.v\nset_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_mux_2z.v\nset_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_mux_3z.v\nset_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_mux_4.v\nset_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_mux_8.v\nset_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_prep_daa.v\nset_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_select.v\nset_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_shifter_core.v\nset_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_slice.v\nset_global_assignment -name VERILOG_FILE ../../cpu/bus/address_latch.v\nset_global_assignment -name VERILOG_FILE ../../cpu/bus/address_mux.v\nset_global_assignment -name VERILOG_FILE ../../cpu/bus/address_pins.v\nset_global_assignment -name VERILOG_FILE ../../cpu/bus/bus_control.v\nset_global_assignment -name VERILOG_FILE ../../cpu/bus/control_pins_n.v\nset_global_assignment -name VERILOG_FILE ../../cpu/bus/data_pins.v\nset_global_assignment -name VERILOG_FILE ../../cpu/bus/data_switch.v\nset_global_assignment -name VERILOG_FILE ../../cpu/bus/data_switch_mask.v\nset_global_assignment -name VERILOG_FILE ../../cpu/bus/inc_dec.v\nset_global_assignment -name VERILOG_FILE ../../cpu/bus/inc_dec_2bit.v\nset_global_assignment -name VERILOG_FILE ../../cpu/control/clk_delay.v\nset_global_assignment -name VERILOG_FILE ../../cpu/control/decode_state.v\nset_global_assignment -name VERILOG_FILE ../../cpu/control/interrupts.v\nset_global_assignment -name VERILOG_FILE ../../cpu/control/ir.v\nset_global_assignment -name VERILOG_FILE ../../cpu/control/memory_ifc.v\nset_global_assignment -name VERILOG_FILE ../../cpu/control/pin_control.v\nset_global_assignment -name VERILOG_FILE ../../cpu/control/resets.v\nset_global_assignment -name VERILOG_FILE ../../cpu/control/sequencer.v\nset_global_assignment -name VERILOG_FILE ../../cpu/registers/reg_control.v\nset_global_assignment -name VERILOG_FILE ../../cpu/registers/reg_file.v\nset_global_assignment -name VERILOG_FILE ../../cpu/registers/reg_latch.v\nset_global_assignment -name VERILOG_FILE ../common/uart.v\nset_global_assignment -name VERILOG_FILE ../common/wait_state.v\nset_global_assignment -name VERILOG_FILE basic_de1_fpga.sv\nset_global_assignment -name QIP_FILE ram.qip\nset_global_assignment -name QIP_FILE pll.qip\nset_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top"
  },
  {
    "path": "host/basic_de1/basic_de1.sdc",
    "content": "## Generated SDC file \"basic_de1.sdc\"\n\n## Copyright (C) 1991-2013 Altera Corporation\n## Your use of Altera Corporation's design tools, logic functions\n## and other software and tools, and its AMPP partner logic\n## functions, and any output files from any of the foregoing\n## (including device programming or simulation files), and any\n## associated documentation or information are expressly subject\n## to the terms and conditions of the Altera Program License\n## Subscription Agreement, Altera MegaCore Function License\n## Agreement, or other applicable license agreement, including,\n## without limitation, that your use is for the sole purpose of\n## programming logic devices manufactured by Altera and sold by\n## Altera or its authorized distributors.  Please refer to the\n## applicable agreement for further details.\n\n## VENDOR  \"Altera\"\n## PROGRAM \"Quartus II\"\n## VERSION \"Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\"\n\n##\n## DEVICE  \"EP2C20F484C7\"\n##\n\n#**************************************************************\n# Time Information\n#**************************************************************\n\nset_time_format -unit ns -decimal_places 3\n\n#**************************************************************\n# Create Clock\n#**************************************************************\n\ncreate_clock -name {CLOCK_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {CLOCK_50}]\ncreate_clock -name {KEY2} -period 20.000 -waveform { 0.000 10.000 } [get_ports {KEY2}]\n\n#**************************************************************\n# Create Generated Clock\n#**************************************************************\n\ncreate_generated_clock -name {pll_|altpll_component|pll|clk[0]} -source [get_pins {pll_|altpll_component|pll|inclk[0]}] -duty_cycle 50.000 -multiply_by 1 -master_clock {CLOCK_50} [get_pins {pll_|altpll_component|pll|clk[0]}]\ncreate_generated_clock -name {clk_cpu} -source [get_nets {pll_|altpll_component|_clk0}] -divide_by 4 -master_clock {pll_|altpll_component|pll|clk[0]} [get_nets {clk_cpu}]\n\n#**************************************************************\n# Set Clock Latency\n#**************************************************************\n\n\n#**************************************************************\n# Set Clock Uncertainty\n#**************************************************************\n\nderive_clock_uncertainty\n\n#**************************************************************\n# Set Input Delay\n#**************************************************************\n\nset_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}]  2.000 [get_ports {CLOCK_50}]\nset_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {CLOCK_50}]\nset_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}]  2.000 [get_ports {KEY0}]\nset_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {KEY0}]\nset_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}]  2.000 [get_ports {KEY1}]\nset_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {KEY1}]\nset_input_delay -add_delay -max -clock [get_clocks {CLOCK_50}]  2.000 [get_ports {KEY2}]\nset_input_delay -add_delay -min -clock [get_clocks {CLOCK_50}]  1.000 [get_ports {KEY2}]\n\n#**************************************************************\n# Set Output Delay\n#**************************************************************\n\nset_output_delay -add_delay -max -clock [get_clocks {CLOCK_50}]  9.000 [get_ports {GPIO_0[0]}]\nset_output_delay -add_delay -min -clock [get_clocks {CLOCK_50}]  -5.000 [get_ports {GPIO_0[0]}]\nset_output_delay -add_delay -max -clock [get_clocks {CLOCK_50}]  6.000 [get_ports {GPIO_0[1]}]\nset_output_delay -add_delay -min -clock [get_clocks {CLOCK_50}]  -5.000 [get_ports {GPIO_0[1]}]\nset_output_delay -add_delay -max -clock [get_clocks {CLOCK_50}]  6.000 [get_ports {GPIO_0[2]}]\nset_output_delay -add_delay -min -clock [get_clocks {CLOCK_50}]  -5.000 [get_ports {GPIO_0[2]}]\nset_output_delay -add_delay -max -clock [get_clocks {CLOCK_50}]  6.000 [get_ports {GPIO_0[3]}]\nset_output_delay -add_delay -min -clock [get_clocks {CLOCK_50}]  -5.000 [get_ports {GPIO_0[3]}]\nset_output_delay -add_delay -max -clock [get_clocks {CLOCK_50}]  6.000 [get_ports {GPIO_0[4]}]\nset_output_delay -add_delay -min -clock [get_clocks {CLOCK_50}]  -5.000 [get_ports {GPIO_0[4]}]\nset_output_delay -add_delay -max -clock [get_clocks {CLOCK_50}]  6.000 [get_ports {GPIO_0[5]}]\nset_output_delay -add_delay -min -clock [get_clocks {CLOCK_50}]  -5.000 [get_ports {GPIO_0[5]}]\nset_output_delay -add_delay -max -clock [get_clocks {CLOCK_50}]  6.000 [get_ports {UART_TXD}]\nset_output_delay -add_delay -min -clock [get_clocks {CLOCK_50}]  -5.000 [get_ports {UART_TXD}]\nset_output_delay -add_delay -max -clock [get_clocks {CLOCK_50}]  6.000 [get_ports {~LVDS91p/nCEO~}]\nset_output_delay -add_delay -min -clock [get_clocks {CLOCK_50}]  -5.000 [get_ports {~LVDS91p/nCEO~}]\n\n#**************************************************************\n# Set Clock Groups\n#**************************************************************\n\nset_clock_groups -asynchronous -group [get_clocks {CLOCK_50}] -group [get_clocks {KEY2}]\n\n#**************************************************************\n# Set False Path\n#**************************************************************\n\n\n#**************************************************************\n# Set Multicycle Path\n#**************************************************************\n\n\n#**************************************************************\n# Set Maximum Delay\n#**************************************************************\n\n\n#**************************************************************\n# Set Minimum Delay\n#**************************************************************\n\n\n#**************************************************************\n# Set Input Transition\n#**************************************************************\n\n"
  },
  {
    "path": "host/basic_de1/basic_de1_ModelSim.sv",
    "content": "//============================================================================\n// Host design containing A-Z80 and a few peripherials\n//\n// This module does not define a physical board but is only meant to be\n// compiled within the ModelSim host test.\n//\n//  Copyright (C) 2014-2016  Goran Devic\n//\n//  This program is free software; you can redistribute it and/or modify it\n//  under the terms of the GNU General Public License as published by the Free\n//  Software Foundation; either version 2 of the License, or (at your option)\n//  any later version.\n//\n//  This program is distributed in the hope that it will be useful, but WITHOUT\n//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n//  more details.\n//\n//  You should have received a copy of the GNU General Public License along\n//  with this program; if not, write to the Free Software Foundation, Inc.,\n//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n//============================================================================\nmodule host\n(\n    input wire clk,\n    input wire reset,\n    input wire nint,\n    input wire nnmi,\n    output wire uart_tx\n);\n\n// ----------------- CPU PINS -----------------\nwire nM1;\nwire nMREQ;\nwire nIORQ;\nwire nRD;\nwire nWR;\nwire nRFSH;\nwire nHALT;\nwire nBUSACK;\n\nwire nWAIT;\nwire nINT = nint;\nwire nNMI = nnmi;\nwire nBUSRQ = 1;\n\nwire [15:0] A;\nwire [7:0] D;\n\n// This is an optional, test feature: add M1/Memory Wait states as described in the Zilog manual\nreg nWAIT_M1_sig;\nreg nWAIT_Mem_sig;\n\n// *** Uncomment one of the following 3 choices ***:\n//assign nWAIT = nWAIT_M1_sig;  // Add one wait state to an M1 cycle\n//assign nWAIT = nWAIT_Mem_sig; // Add one wait state to any memory cycle (M1 + memory read/write)\nassign nWAIT = 1;               // Do not add wait cycles\n\n// ----------------- INTERNAL WIRES -----------------\nwire [7:0] RamData;                     // RamData is a data writer from the RAM module\nwire RamWE;\nassign RamWE = nIORQ==1 && nRD==1 && nWR==0;\n\nwire uart_busy;\nwire UartWE = nIORQ==0 && nRD==1 && nWR==0;\n\n// Memory map:\n//   0000 - 3FFF  16K RAM\nassign D[7:0] = (A[15:14]=='h0 && nIORQ==1 && nRD==0 && nWR==1) ? RamData :\n                (nIORQ==0 && nRD==1 && nWR==1) ? 8'h80 :\n                (nIORQ==0 && nRD==0 && nWR==1) ? {7'h0,uart_busy} :\n                {8{1'bz}};\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// Instantiate A-Z80 CPU module\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nz80_top_direct_n z80_( .*, .nRESET(reset), .CLK(clk) );\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// Instantiate gates to add Wait states to M1 and Memory cycles (for testing)\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nwait_state wait_state_inst\n(\n    .CLK(clk),\n    .nM1(nM1),\n    .nMREQ((nMREQ === z) ? 1'b1 : nMREQ), // Correct nMREQ from being tri-stated after reset\n    .nWAIT_M1(nWAIT_M1_sig),\n    .nWAIT_Mem(nWAIT_Mem_sig)\n);\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// Instantiate 16Kb of RAM memory\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nram ram_( .address(A[13:0]), .clock(clk), .data(D[7:0]), .wren(RamWE), .q(RamData[7:0]) );\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// Instantiate UART module\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nuart #( .BAUD(115200), .IN_CLOCK(10000000) ) uart_(\n   // Outputs\n   .busy(uart_busy),\n   .uart_tx(uart_tx),\n   // Inputs\n   .wr(UartWE),\n   .data(D[7:0]),\n   .clk(clk),\n   .reset(!reset)\n);\n\nendmodule\n"
  },
  {
    "path": "host/basic_de1/basic_de1_fpga.sv",
    "content": "//============================================================================\n// Host design containing A-Z80 and a few peripherials\n//\n// This module defines a host board to be run on an FPGA.\n//\n//  Copyright (C) 2014-2016  Goran Devic\n//\n//  This program is free software; you can redistribute it and/or modify it\n//  under the terms of the GNU General Public License as published by the Free\n//  Software Foundation; either version 2 of the License, or (at your option)\n//  any later version.\n//\n//  This program is distributed in the hope that it will be useful, but WITHOUT\n//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n//  more details.\n//\n//  You should have received a copy of the GNU General Public License along\n//  with this program; if not, write to the Free Software Foundation, Inc.,\n//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n//============================================================================\nmodule host\n(\n    input wire CLOCK_50,\n    input wire KEY0,            // KEY0 is reset\n    input wire KEY1,            // KEY1 generates a maskable interrupt (INT)\n    input wire KEY2,            // KEY2 generates a non-maskable interrupt (NMI)\n    output wire UART_TXD,\n\n    output wire [5:0] GPIO_0    // Test points\n);\n`default_nettype none\n\n// Export selected pins to the extension connector\nassign GPIO_0[0] = reset;\nassign GPIO_0[1] = locked;\nassign GPIO_0[2] = nM1;\nassign GPIO_0[3] = nMREQ;\nassign GPIO_0[4] = nRD;\nassign GPIO_0[5] = nWR;\n\n// Basic wires and the reset logic\nwire uart_tx;\nwire uart_busy;\nwire UartWE;\nwire reset;\nwire locked;\n\nassign reset = locked & KEY0;\nassign UART_TXD = uart_tx;\n\n// ----------------- CPU PINS -----------------\nwire nM1;\nwire nMREQ;\nwire nIORQ;\nwire nRD;\nwire nWR;\nwire nRFSH;\nwire nHALT;\nwire nBUSACK;\n\nwire nWAIT;\nwire nBUSRQ = 1;\nwire nINT = KEY1;\nwire nNMI = KEY2;\n\nwire [15:0] A;\nwire [7:0] D;\n\n// This is an optional, test feature: add M1/Memory Wait states as described in the Zilog manual\nreg nWAIT_M1_sig;\nreg nWAIT_Mem_sig;\n\n// *** Uncomment one of the following 3 choices ***:\n//assign nWAIT = nWAIT_M1_sig;  // Add one wait state to an M1 cycle\n//assign nWAIT = nWAIT_Mem_sig; // Add one wait state to any memory cycle (M1 + memory read/write)\nassign nWAIT = 1;               // Do not add wait cycles\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// Instantiate PLL\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nwire pll_clk;\npll pll_( .locked(locked), .inclk0(CLOCK_50), .c0(pll_clk) );\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// Generate the CPU clock by dividing input clock by a factor of a power of 2\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nreg clk_cpu = 0;                        // Final CPU clock\n// Note: In order to test at 3.5 MHz, the PLL needs to be set to generate 14 MHz\n// and then this divider-by-4 brings the effective clock down to 3.5 MHz\nreg [0:0] counter = 0;                  // Clock divider counter\n\nalways @(posedge pll_clk)\nbegin\n    if (counter=='0)\n        clk_cpu <= ~clk_cpu;\n    counter <= counter - 1'b1;\nend\n\n// ----------------- INTERNAL WIRES -----------------\nwire [7:0] RamData; // Data writer from the RAM module\nwire RamWE;\nassign RamWE = nIORQ==1 && nRD==1 && nWR==0;\nassign UartWE = nIORQ==0 && nRD==1 && nWR==0;\n\n// Memory map:\n//   0000 - 3FFF  16K RAM\nalways_comb\nbegin\n    case ({nIORQ,nRD,nWR})\n        3'b101: begin   // Memory read\n                casez (A[15:14])\n                    2'b00:  D[7:0] = RamData;\n                default:\n                    D[7:0] = 8'h76; // HALT\n                endcase\n                end\n        3'b001: D[7:0] = {7'h0,uart_busy};\n        // IO read *** Interrupts test ***\n        // This value will be pushed on the data bus on an IORQ access which\n        // means that:\n        // In IM0: this is the opcode of an instruction to execute, set it to 0xFF\n        // In IM2: this is a vector, set it to 0x80 (to correspond to a test program Hello World)\n        3'b011: D[7:0] = 8'h80;\n    default:\n        D[7:0] = {8{1'bz}};\n    endcase\nend\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// Instantiate A-Z80 CPU module\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nz80_top_direct_n z80_( .*, .nRESET(reset), .CLK(clk_cpu) );\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// Instantiate gates to add Wait states to M1 and Memory cycles (for testing)\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nwait_state wait_state_inst\n(\n    .CLK(clk_cpu),\n    .nM1(nM1),\n    .nMREQ(nMREQ),\n    .nWAIT_M1(nWAIT_M1_sig),\n    .nWAIT_Mem(nWAIT_Mem_sig)\n);\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// Instantiate 16Kb of RAM memory\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nram ram_( .address(A[13:0]), .clock(pll_clk), .data(D[7:0]), .wren(RamWE), .q(RamData[7:0]) );\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// Instantiate UART module\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nuart #( .BAUD(115200), .IN_CLOCK(50000000) ) uart_(\n   // Outputs\n   .busy(uart_busy),\n   .uart_tx(uart_tx),\n   // Inputs\n   .wr(UartWE),\n   .data(D[7:0]),\n   .clk(CLOCK_50),\n   .reset(!reset)\n);\n\nendmodule\n"
  },
  {
    "path": "host/basic_de1/fpga.hex",
    "content": ":20000000C38F00000079FE02CA1100FE09CA2100C901000AED78CB47C21100010008ED59DB\n:20002000C9D5E15E7BFE24C8CD110023C32300000000000000000000D5114B00F5C5E50EB9\n:2000400009CD0500E1C1F1D1FBED4D5F494E545F240000000000000000000000000000005F\n:20006000000000000000F5C5D5E51178000E09CD0500E1D1C1F1ED455F4E4D495F2400003E\n:200080008200D5118900C33C005F494D325F24310040ED5E3E00ED47FBC3000100000000D9\n:2000A000000000000000000000000000000000000000000000000000000000000000000040\n:2000C000000000000000000000000000000000000000000000000000000000000000000020\n:2000E000000000000000000000000000000000000000000000000000000000000000000000\n:20010000210000225E011162010E09CD05002A5E0123225E012164013A5F01CD3D01216601\n:20012000013A5E01CD3D01ED736001216901ED57CD3D01216B01ED5FCD3D0118C9F5E60FD0\n:20014000FE0ADA4701C607C63023772BF11F1F1F1FE60FFE0ADA5A01C607C63077C900004B\n:1C01600000000D0A30303030202D2D2D2D2048656C6C6F2C20576F726C6421242B\n:00000001FF\n"
  },
  {
    "path": "host/basic_de1/pll.ppf",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\" ?>\n<!DOCTYPE pinplan>\n<pinplan intended_family=\"Cyclone II\" variation_name=\"pll\" megafunction_name=\"ALTPLL\" specifies=\"all_ports\">\n<global>\n<pin name=\"inclk0\" direction=\"input\" scope=\"external\" source=\"clock\"  />\n<pin name=\"c0\" direction=\"output\" scope=\"external\" source=\"clock\"  />\n<pin name=\"locked\" direction=\"output\" scope=\"external\"  />\n\n</global>\n</pinplan>\n"
  },
  {
    "path": "host/basic_de1/pll.qip",
    "content": "set_global_assignment -name IP_TOOL_NAME \"ALTPLL\"\nset_global_assignment -name IP_TOOL_VERSION \"13.0\"\nset_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) \"pll.v\"]\nset_global_assignment -name MISC_FILE [file join $::quartus(qip_path) \"pll.ppf\"]\n"
  },
  {
    "path": "host/basic_de1/pll.v",
    "content": "// megafunction wizard: %ALTPLL%\n// GENERATION: STANDARD\n// VERSION: WM1.0\n// MODULE: altpll \n\n// ============================================================\n// File Name: pll.v\n// Megafunction Name(s):\n// \t\t\taltpll\n//\n// Simulation Library Files(s):\n// \t\t\taltera_mf\n// ============================================================\n// ************************************************************\n// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!\n//\n// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition\n// ************************************************************\n\n\n//Copyright (C) 1991-2013 Altera Corporation\n//Your use of Altera Corporation's design tools, logic functions \n//and other software and tools, and its AMPP partner logic \n//functions, and any output files from any of the foregoing \n//(including device programming or simulation files), and any \n//associated documentation or information are expressly subject \n//to the terms and conditions of the Altera Program License \n//Subscription Agreement, Altera MegaCore Function License \n//Agreement, or other applicable license agreement, including, \n//without limitation, that your use is for the sole purpose of \n//programming logic devices manufactured by Altera and sold by \n//Altera or its authorized distributors.  Please refer to the \n//applicable agreement for further details.\n\n\n// synopsys translate_off\n`timescale 1 ps / 1 ps\n// synopsys translate_on\nmodule pll (\n\tinclk0,\n\tc0,\n\tlocked);\n\n\tinput\t  inclk0;\n\toutput\t  c0;\n\toutput\t  locked;\n\n\twire [5:0] sub_wire0;\n\twire  sub_wire2;\n\twire [0:0] sub_wire5 = 1'h0;\n\twire [0:0] sub_wire1 = sub_wire0[0:0];\n\twire  c0 = sub_wire1;\n\twire  locked = sub_wire2;\n\twire  sub_wire3 = inclk0;\n\twire [1:0] sub_wire4 = {sub_wire5, sub_wire3};\n\n\taltpll\taltpll_component (\n\t\t\t\t.inclk (sub_wire4),\n\t\t\t\t.clk (sub_wire0),\n\t\t\t\t.locked (sub_wire2),\n\t\t\t\t.activeclock (),\n\t\t\t\t.areset (1'b0),\n\t\t\t\t.clkbad (),\n\t\t\t\t.clkena ({6{1'b1}}),\n\t\t\t\t.clkloss (),\n\t\t\t\t.clkswitch (1'b0),\n\t\t\t\t.configupdate (1'b0),\n\t\t\t\t.enable0 (),\n\t\t\t\t.enable1 (),\n\t\t\t\t.extclk (),\n\t\t\t\t.extclkena ({4{1'b1}}),\n\t\t\t\t.fbin (1'b1),\n\t\t\t\t.fbmimicbidir (),\n\t\t\t\t.fbout (),\n\t\t\t\t.fref (),\n\t\t\t\t.icdrclk (),\n\t\t\t\t.pfdena (1'b1),\n\t\t\t\t.phasecounterselect ({4{1'b1}}),\n\t\t\t\t.phasedone (),\n\t\t\t\t.phasestep (1'b1),\n\t\t\t\t.phaseupdown (1'b1),\n\t\t\t\t.pllena (1'b1),\n\t\t\t\t.scanaclr (1'b0),\n\t\t\t\t.scanclk (1'b0),\n\t\t\t\t.scanclkena (1'b1),\n\t\t\t\t.scandata (1'b0),\n\t\t\t\t.scandataout (),\n\t\t\t\t.scandone (),\n\t\t\t\t.scanread (1'b0),\n\t\t\t\t.scanwrite (1'b0),\n\t\t\t\t.sclkout0 (),\n\t\t\t\t.sclkout1 (),\n\t\t\t\t.vcooverrange (),\n\t\t\t\t.vcounderrange ());\n\tdefparam\n\t\taltpll_component.clk0_divide_by = 1,\n\t\taltpll_component.clk0_duty_cycle = 50,\n\t\taltpll_component.clk0_multiply_by = 1,\n\t\taltpll_component.clk0_phase_shift = \"0\",\n\t\taltpll_component.compensate_clock = \"CLK0\",\n\t\taltpll_component.gate_lock_counter = 10000,\n\t\taltpll_component.gate_lock_signal = \"YES\",\n\t\taltpll_component.inclk0_input_frequency = 20000,\n\t\taltpll_component.intended_device_family = \"Cyclone II\",\n\t\taltpll_component.invalid_lock_multiplier = 5,\n\t\taltpll_component.lpm_hint = \"CBX_MODULE_PREFIX=pll\",\n\t\taltpll_component.lpm_type = \"altpll\",\n\t\taltpll_component.operation_mode = \"NORMAL\",\n\t\taltpll_component.port_activeclock = \"PORT_UNUSED\",\n\t\taltpll_component.port_areset = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkbad0 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkbad1 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkloss = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkswitch = \"PORT_UNUSED\",\n\t\taltpll_component.port_configupdate = \"PORT_UNUSED\",\n\t\taltpll_component.port_fbin = \"PORT_UNUSED\",\n\t\taltpll_component.port_inclk0 = \"PORT_USED\",\n\t\taltpll_component.port_inclk1 = \"PORT_UNUSED\",\n\t\taltpll_component.port_locked = \"PORT_USED\",\n\t\taltpll_component.port_pfdena = \"PORT_UNUSED\",\n\t\taltpll_component.port_phasecounterselect = \"PORT_UNUSED\",\n\t\taltpll_component.port_phasedone = \"PORT_UNUSED\",\n\t\taltpll_component.port_phasestep = \"PORT_UNUSED\",\n\t\taltpll_component.port_phaseupdown = \"PORT_UNUSED\",\n\t\taltpll_component.port_pllena = \"PORT_UNUSED\",\n\t\taltpll_component.port_scanaclr = \"PORT_UNUSED\",\n\t\taltpll_component.port_scanclk = \"PORT_UNUSED\",\n\t\taltpll_component.port_scanclkena = \"PORT_UNUSED\",\n\t\taltpll_component.port_scandata = \"PORT_UNUSED\",\n\t\taltpll_component.port_scandataout = \"PORT_UNUSED\",\n\t\taltpll_component.port_scandone = \"PORT_UNUSED\",\n\t\taltpll_component.port_scanread = \"PORT_UNUSED\",\n\t\taltpll_component.port_scanwrite = \"PORT_UNUSED\",\n\t\taltpll_component.port_clk0 = \"PORT_USED\",\n\t\taltpll_component.port_clk1 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clk2 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clk3 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clk4 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clk5 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkena0 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkena1 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkena2 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkena3 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkena4 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkena5 = \"PORT_UNUSED\",\n\t\taltpll_component.port_extclk0 = \"PORT_UNUSED\",\n\t\taltpll_component.port_extclk1 = \"PORT_UNUSED\",\n\t\taltpll_component.port_extclk2 = \"PORT_UNUSED\",\n\t\taltpll_component.port_extclk3 = \"PORT_UNUSED\",\n\t\taltpll_component.valid_lock_multiplier = 1;\n\n\nendmodule\n\n// ============================================================\n// CNX file retrieval info\n// ============================================================\n// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: BANDWIDTH STRING \"1.000\"\n// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING \"0\"\n// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING \"MHz\"\n// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING \"Low\"\n// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING \"1\"\n// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING \"0\"\n// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING \"0\"\n// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING \"1\"\n// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING \"0\"\n// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING \"c0\"\n// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING \"c0\"\n// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING \"7\"\n// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC \"1\"\n// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING \"50.00000000\"\n// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING \"50.000000\"\n// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING \"0\"\n// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING \"0\"\n// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING \"1\"\n// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING \"1\"\n// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING \"1\"\n// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC \"10000\"\n// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING \"1\"\n// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING \"50.000\"\n// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING \"MHz\"\n// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING \"0.000\"\n// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING \"1\"\n// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING \"1\"\n// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING \"MHz\"\n// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING \"Cyclone II\"\n// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING \"1\"\n// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING \"1\"\n// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING \"1\"\n// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING \"Not Available\"\n// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC \"0\"\n// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING \"deg\"\n// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING \"Any\"\n// Retrieval info: PRIVATE: MIRROR_CLK0 STRING \"0\"\n// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC \"1\"\n// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING \"1\"\n// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING \"50.00000000\"\n// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING \"1\"\n// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING \"MHz\"\n// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING \"0\"\n// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING \"0.00000000\"\n// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING \"deg\"\n// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC \"1\"\n// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC \"0\"\n// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC \"0\"\n// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC \"0\"\n// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC \"0\"\n// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING \"inclk0\"\n// Retrieval info: PRIVATE: RECONFIG_FILE STRING \"pll.mif\"\n// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING \"0\"\n// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING \"0\"\n// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING \"0\"\n// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING \"0\"\n// Retrieval info: PRIVATE: SPREAD_FREQ STRING \"50.000\"\n// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING \"KHz\"\n// Retrieval info: PRIVATE: SPREAD_PERCENT STRING \"0.500\"\n// Retrieval info: PRIVATE: SPREAD_USE STRING \"0\"\n// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING \"0\"\n// Retrieval info: PRIVATE: STICKY_CLK0 STRING \"1\"\n// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC \"1\"\n// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING \"1\"\n// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING \"0\"\n// Retrieval info: PRIVATE: USE_CLK0 STRING \"1\"\n// Retrieval info: PRIVATE: USE_CLKENA0 STRING \"0\"\n// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC \"0\"\n// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING \"0\"\n// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all\n// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC \"1\"\n// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC \"50\"\n// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC \"1\"\n// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING \"0\"\n// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING \"CLK0\"\n// Retrieval info: CONSTANT: GATE_LOCK_COUNTER NUMERIC \"10000\"\n// Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING \"YES\"\n// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC \"20000\"\n// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING \"Cyclone II\"\n// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC \"5\"\n// Retrieval info: CONSTANT: LPM_TYPE STRING \"altpll\"\n// Retrieval info: CONSTANT: OPERATION_MODE STRING \"NORMAL\"\n// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_ARESET STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_CLKLOSS STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_FBIN STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_INCLK0 STRING \"PORT_USED\"\n// Retrieval info: CONSTANT: PORT_INCLK1 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_LOCKED STRING \"PORT_USED\"\n// Retrieval info: CONSTANT: PORT_PFDENA STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_PHASEDONE STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_PHASESTEP STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_PLLENA STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_SCANACLR STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_SCANCLK STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_SCANDATA STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_SCANDONE STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_SCANREAD STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_SCANWRITE STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clk0 STRING \"PORT_USED\"\n// Retrieval info: CONSTANT: PORT_clk1 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clk2 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clk3 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clk4 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clk5 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clkena0 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clkena1 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clkena2 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clkena3 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clkena4 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clkena5 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_extclk0 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_extclk1 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_extclk2 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_extclk3 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC \"1\"\n// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC \"@clk[5..0]\"\n// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC \"@extclk[3..0]\"\n// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC \"c0\"\n// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND \"inclk0\"\n// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND \"locked\"\n// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0\n// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0\n// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0\n// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0\n// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE\n// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE\n// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE\n// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE\n// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE\n// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE\n// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE\n// Retrieval info: LIB_FILE: altera_mf\n// Retrieval info: CBX_MODULE_PREFIX: ON\n"
  },
  {
    "path": "host/basic_de1/ram.qip",
    "content": "set_global_assignment -name IP_TOOL_NAME \"RAM: 1-PORT\"\nset_global_assignment -name IP_TOOL_VERSION \"13.0\"\nset_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) \"ram.v\"]\n"
  },
  {
    "path": "host/basic_de1/ram.v",
    "content": "// megafunction wizard: %RAM: 1-PORT%\n// GENERATION: STANDARD\n// VERSION: WM1.0\n// MODULE: altsyncram \n\n// ============================================================\n// File Name: ram.v\n// Megafunction Name(s):\n// \t\t\taltsyncram\n//\n// Simulation Library Files(s):\n// \t\t\taltera_mf\n// ============================================================\n// ************************************************************\n// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!\n//\n// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition\n// ************************************************************\n\n\n//Copyright (C) 1991-2013 Altera Corporation\n//Your use of Altera Corporation's design tools, logic functions \n//and other software and tools, and its AMPP partner logic \n//functions, and any output files from any of the foregoing \n//(including device programming or simulation files), and any \n//associated documentation or information are expressly subject \n//to the terms and conditions of the Altera Program License \n//Subscription Agreement, Altera MegaCore Function License \n//Agreement, or other applicable license agreement, including, \n//without limitation, that your use is for the sole purpose of \n//programming logic devices manufactured by Altera and sold by \n//Altera or its authorized distributors.  Please refer to the \n//applicable agreement for further details.\n\n\n// synopsys translate_off\n`timescale 1 ps / 1 ps\n// synopsys translate_on\nmodule ram (\n\taddress,\n\tclock,\n\tdata,\n\twren,\n\tq);\n\n\tinput\t[13:0]  address;\n\tinput\t  clock;\n\tinput\t[7:0]  data;\n\tinput\t  wren;\n\toutput\t[7:0]  q;\n`ifndef ALTERA_RESERVED_QIS\n// synopsys translate_off\n`endif\n\ttri1\t  clock;\n`ifndef ALTERA_RESERVED_QIS\n// synopsys translate_on\n`endif\n\n\twire [7:0] sub_wire0;\n\twire [7:0] q = sub_wire0[7:0];\n\n\taltsyncram\taltsyncram_component (\n\t\t\t\t.address_a (address),\n\t\t\t\t.clock0 (clock),\n\t\t\t\t.data_a (data),\n\t\t\t\t.wren_a (wren),\n\t\t\t\t.q_a (sub_wire0),\n\t\t\t\t.aclr0 (1'b0),\n\t\t\t\t.aclr1 (1'b0),\n\t\t\t\t.address_b (1'b1),\n\t\t\t\t.addressstall_a (1'b0),\n\t\t\t\t.addressstall_b (1'b0),\n\t\t\t\t.byteena_a (1'b1),\n\t\t\t\t.byteena_b (1'b1),\n\t\t\t\t.clock1 (1'b1),\n\t\t\t\t.clocken0 (1'b1),\n\t\t\t\t.clocken1 (1'b1),\n\t\t\t\t.clocken2 (1'b1),\n\t\t\t\t.clocken3 (1'b1),\n\t\t\t\t.data_b (1'b1),\n\t\t\t\t.eccstatus (),\n\t\t\t\t.q_b (),\n\t\t\t\t.rden_a (1'b1),\n\t\t\t\t.rden_b (1'b1),\n\t\t\t\t.wren_b (1'b0));\n\tdefparam\n\t\taltsyncram_component.clock_enable_input_a = \"BYPASS\",\n\t\taltsyncram_component.clock_enable_output_a = \"BYPASS\",\n`ifdef NO_PLI\n\t\taltsyncram_component.init_file = \"fpga.rif\"\n`else\n\t\taltsyncram_component.init_file = \"fpga.hex\"\n`endif\n,\n\t\taltsyncram_component.intended_device_family = \"Cyclone II\",\n\t\taltsyncram_component.lpm_hint = \"ENABLE_RUNTIME_MOD=NO\",\n\t\taltsyncram_component.lpm_type = \"altsyncram\",\n\t\taltsyncram_component.numwords_a = 16384,\n\t\taltsyncram_component.operation_mode = \"SINGLE_PORT\",\n\t\taltsyncram_component.outdata_aclr_a = \"NONE\",\n\t\taltsyncram_component.outdata_reg_a = \"UNREGISTERED\",\n\t\taltsyncram_component.power_up_uninitialized = \"FALSE\",\n\t\taltsyncram_component.widthad_a = 14,\n\t\taltsyncram_component.width_a = 8,\n\t\taltsyncram_component.width_byteena_a = 1;\n\n\nendmodule\n\n// ============================================================\n// CNX file retrieval info\n// ============================================================\n// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC \"0\"\n// Retrieval info: PRIVATE: AclrAddr NUMERIC \"0\"\n// Retrieval info: PRIVATE: AclrByte NUMERIC \"0\"\n// Retrieval info: PRIVATE: AclrData NUMERIC \"0\"\n// Retrieval info: PRIVATE: AclrOutput NUMERIC \"0\"\n// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC \"0\"\n// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC \"8\"\n// Retrieval info: PRIVATE: BlankMemory NUMERIC \"0\"\n// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC \"0\"\n// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC \"0\"\n// Retrieval info: PRIVATE: Clken NUMERIC \"0\"\n// Retrieval info: PRIVATE: DataBusSeparated NUMERIC \"1\"\n// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC \"0\"\n// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING \"PORT_A\"\n// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC \"0\"\n// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING \"Cyclone II\"\n// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC \"0\"\n// Retrieval info: PRIVATE: JTAG_ID STRING \"NONE\"\n// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC \"0\"\n// Retrieval info: PRIVATE: MIFfilename STRING \"fpga.hex\"\n// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC \"16384\"\n// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC \"0\"\n// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC \"3\"\n// Retrieval info: PRIVATE: RegAddr NUMERIC \"1\"\n// Retrieval info: PRIVATE: RegData NUMERIC \"1\"\n// Retrieval info: PRIVATE: RegOutput NUMERIC \"0\"\n// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING \"0\"\n// Retrieval info: PRIVATE: SingleClock NUMERIC \"1\"\n// Retrieval info: PRIVATE: UseDQRAM NUMERIC \"1\"\n// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC \"0\"\n// Retrieval info: PRIVATE: WidthAddr NUMERIC \"14\"\n// Retrieval info: PRIVATE: WidthData NUMERIC \"8\"\n// Retrieval info: PRIVATE: rden NUMERIC \"0\"\n// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all\n// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING \"BYPASS\"\n// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING \"BYPASS\"\n// Retrieval info: CONSTANT: INIT_FILE STRING \"fpga.hex\"\n// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING \"Cyclone II\"\n// Retrieval info: CONSTANT: LPM_HINT STRING \"ENABLE_RUNTIME_MOD=NO\"\n// Retrieval info: CONSTANT: LPM_TYPE STRING \"altsyncram\"\n// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC \"16384\"\n// Retrieval info: CONSTANT: OPERATION_MODE STRING \"SINGLE_PORT\"\n// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING \"NONE\"\n// Retrieval info: CONSTANT: OUTDATA_REG_A STRING \"UNREGISTERED\"\n// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING \"FALSE\"\n// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC \"14\"\n// Retrieval info: CONSTANT: WIDTH_A NUMERIC \"8\"\n// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC \"1\"\n// Retrieval info: USED_PORT: address 0 0 14 0 INPUT NODEFVAL \"address[13..0]\"\n// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC \"clock\"\n// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL \"data[7..0]\"\n// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL \"q[7..0]\"\n// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL \"wren\"\n// Retrieval info: CONNECT: @address_a 0 0 14 0 address 0 0 14 0\n// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0\n// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0\n// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0\n// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0\n// Retrieval info: GEN_FILE: TYPE_NORMAL ram.v TRUE\n// Retrieval info: GEN_FILE: TYPE_NORMAL ram.inc FALSE\n// Retrieval info: GEN_FILE: TYPE_NORMAL ram.cmp FALSE\n// Retrieval info: GEN_FILE: TYPE_NORMAL ram.bsf FALSE\n// Retrieval info: GEN_FILE: TYPE_NORMAL ram_inst.v FALSE\n// Retrieval info: GEN_FILE: TYPE_NORMAL ram_bb.v FALSE\n// Retrieval info: LIB_FILE: altera_mf\n"
  },
  {
    "path": "host/basic_de1/readme.txt",
    "content": "Target board: DE1 Altera Cyclone II EP2C20 FPGA Development Board\n\nThis folder contains a simple \"basic\" board computer with the A-Z80,\nsome RAM and UART which can run selected Z80 executable files.\n\nConnect UART at 115200 baud to see the output.\n\n./tools/zmac contains few Z80 sample programs to run and batch scripts\nto assemble and copy them into this directory.\n"
  },
  {
    "path": "host/basic_de1/simulation/modelsim/fpga.hex",
    "content": ":20000000C38F00000079FE02CA1100FE09CA2100C901000AED78CB47C21100010008ED59DB\n:20002000C9D5E15E7BFE24C8CD110023C32300000000000000000000D5114B00F5C5E50EB9\n:2000400009CD0500E1C1F1D1FBED4D5F494E545F240000000000000000000000000000005F\n:20006000000000000000F5C5D5E51178000E09CD0500E1D1C1F1ED455F4E4D495F2400003E\n:200080008200D5118900C33C005F494D325F24310040ED5E3E00ED47FBC3000100000000D9\n:2000A000000000000000000000000000000000000000000000000000000000000000000040\n:2000C000000000000000000000000000000000000000000000000000000000000000000020\n:2000E000000000000000000000000000000000000000000000000000000000000000000000\n:20010000210000225E011162010E09CD05002A5E0123225E012164013A5F01CD3D01216601\n:20012000013A5E01CD3D01ED736001216901ED57CD3D01216B01ED5FCD3D0118C9F5E60FD0\n:20014000FE0ADA4701C607C63023772BF11F1F1F1FE60FFE0ADA5A01C607C63077C900004B\n:1C01600000000D0A30303030202D2D2D2D2048656C6C6F2C20576F726C6421242B\n:00000001FF\n"
  },
  {
    "path": "host/basic_de1/simulation/modelsim/r",
    "content": "restart -f ; run 10us\n"
  },
  {
    "path": "host/basic_de1/simulation/modelsim/test_host.mpf",
    "content": "; Copyright 1991-2009 Mentor Graphics Corporation\n;\n; All Rights Reserved.\n;\n; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF\n; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.\n;\n\n[Library]\nstd = $MODEL_TECH/../std\nieee = $MODEL_TECH/../ieee\nverilog = $MODEL_TECH/../verilog\nvital2000 = $MODEL_TECH/../vital2000\nstd_developerskit = $MODEL_TECH/../std_developerskit\nsynopsys = $MODEL_TECH/../synopsys\nmodelsim_lib = $MODEL_TECH/../modelsim_lib\nsv_std = $MODEL_TECH/../sv_std\n\n; Altera Primitive libraries\n;\n; VHDL Section\n;\naltera_mf = $MODEL_TECH/../altera/vhdl/altera_mf\naltera = $MODEL_TECH/../altera/vhdl/altera\naltera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim\nlpm = $MODEL_TECH/../altera/vhdl/220model\n220model = $MODEL_TECH/../altera/vhdl/220model\nmax = $MODEL_TECH/../altera/vhdl/max\nmaxii = $MODEL_TECH/../altera/vhdl/maxii\nmaxv = $MODEL_TECH/../altera/vhdl/maxv\nstratix = $MODEL_TECH/../altera/vhdl/stratix\nstratixii = $MODEL_TECH/../altera/vhdl/stratixii\nstratixiigx = $MODEL_TECH/../altera/vhdl/stratixiigx\nhardcopyii = $MODEL_TECH/../altera/vhdl/hardcopyii\nhardcopyiii = $MODEL_TECH/../altera/vhdl/hardcopyiii\nhardcopyiv = $MODEL_TECH/../altera/vhdl/hardcopyiv\ncyclone = $MODEL_TECH/../altera/vhdl/cyclone\ncycloneii = $MODEL_TECH/../altera/vhdl/cycloneii\ncycloneiii = $MODEL_TECH/../altera/vhdl/cycloneiii\ncycloneiiils = $MODEL_TECH/../altera/vhdl/cycloneiiils\nsgate = $MODEL_TECH/../altera/vhdl/sgate\nstratixgx = $MODEL_TECH/../altera/vhdl/stratixgx\naltgxb = $MODEL_TECH/../altera/vhdl/altgxb\nstratixgx_gxb = $MODEL_TECH/../altera/vhdl/stratixgx_gxb\nstratixiigx_hssi = $MODEL_TECH/../altera/vhdl/stratixiigx_hssi\narriagx_hssi = $MODEL_TECH/../altera/vhdl/arriagx_hssi\narriaii = $MODEL_TECH/../altera/vhdl/arriaii\narriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi\narriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip\narriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz\narriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi\narriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip\narriagx = $MODEL_TECH/../altera/vhdl/arriagx\naltgxb_lib = $MODEL_TECH/../altera/vhdl/altgxb\nstratixiv = $MODEL_TECH/../altera/vhdl/stratixiv\nstratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi\nstratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip\ncycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv\ncycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi\ncycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip\ncycloneive = $MODEL_TECH/../altera/vhdl/cycloneive\nhardcopyiv_hssi = $MODEL_TECH/../altera/vhdl/hardcopyiv_hssi\nhardcopyiv_pcie_hip = $MODEL_TECH/../altera/vhdl/hardcopyiv_pcie_hip\nstratixv = $MODEL_TECH/../altera/vhdl/stratixv\nstratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi\nstratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip\narriavgz = $MODEL_TECH/../altera/vhdl/arriavgz\narriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi\narriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip\narriav = $MODEL_TECH/../altera/vhdl/arriav\ncyclonev = $MODEL_TECH/../altera/vhdl/cyclonev\n;\n; Verilog Section\n;\naltera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf\naltera_ver = $MODEL_TECH/../altera/verilog/altera\naltera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim\nlpm_ver = $MODEL_TECH/../altera/verilog/220model\n220model_ver = $MODEL_TECH/../altera/verilog/220model\nmax_ver = $MODEL_TECH/../altera/verilog/max\nmaxii_ver = $MODEL_TECH/../altera/verilog/maxii\nmaxv_ver = $MODEL_TECH/../altera/verilog/maxv\nstratix_ver = $MODEL_TECH/../altera/verilog/stratix\nstratixii_ver = $MODEL_TECH/../altera/verilog/stratixii\nstratixiigx_ver = $MODEL_TECH/../altera/verilog/stratixiigx\narriagx_ver = $MODEL_TECH/../altera/verilog/arriagx\nhardcopyii_ver = $MODEL_TECH/../altera/verilog/hardcopyii\nhardcopyiii_ver = $MODEL_TECH/../altera/verilog/hardcopyiii\nhardcopyiv_ver = $MODEL_TECH/../altera/verilog/hardcopyiv\ncyclone_ver = $MODEL_TECH/../altera/verilog/cyclone\ncycloneii_ver = $MODEL_TECH/../altera/verilog/cycloneii\ncycloneiii_ver = $MODEL_TECH/../altera/verilog/cycloneiii\ncycloneiiils_ver = $MODEL_TECH/../altera/verilog/cycloneiiils\nsgate_ver = $MODEL_TECH/../altera/verilog/sgate\nstratixgx_ver = $MODEL_TECH/../altera/verilog/stratixgx\naltgxb_ver = $MODEL_TECH/../altera/verilog/altgxb\nstratixgx_gxb_ver = $MODEL_TECH/../altera/verilog/stratixgx_gxb\nstratixiigx_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiigx_hssi\narriagx_hssi_ver = $MODEL_TECH/../altera/verilog/arriagx_hssi\narriaii_ver = $MODEL_TECH/../altera/verilog/arriaii\narriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi\narriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip\narriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz\narriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi\narriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip\nstratixiii_ver = $MODEL_TECH/../altera/verilog/stratixiii\nstratixiii = $MODEL_TECH/../altera/vhdl/stratixiii\nstratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv\nstratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi\nstratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip\nstratixv_ver = $MODEL_TECH/../altera/verilog/stratixv\nstratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi\nstratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip\narriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz\narriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi\narriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip\narriav_ver = $MODEL_TECH/../altera/verilog/arriav\narriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi\narriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip\ncyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev\ncyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi\ncyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip\ncycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv\ncycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi\ncycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip\ncycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive\nhardcopyiv_hssi_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_hssi\nhardcopyiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_pcie_hip\n\nwork = work\n[vcom]\n; VHDL93 variable selects language version as the default.\n; Default is VHDL-2002.\n; Value of 0 or 1987 for VHDL-1987.\n; Value of 1 or 1993 for VHDL-1993.\n; Default or value of 2 or 2002 for VHDL-2002.\n; Default or value of 3 or 2008 for VHDL-2008.\nVHDL93 = 2002\n\n; Show source line containing error. Default is off.\n; Show_source = 1\n\n; Turn off unbound-component warnings. Default is on.\n; Show_Warning1 = 0\n\n; Turn off process-without-a-wait-statement warnings. Default is on.\n; Show_Warning2 = 0\n\n; Turn off null-range warnings. Default is on.\n; Show_Warning3 = 0\n\n; Turn off no-space-in-time-literal warnings. Default is on.\n; Show_Warning4 = 0\n\n; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.\n; Show_Warning5 = 0\n\n; Turn off optimization for IEEE std_logic_1164 package. Default is on.\n; Optimize_1164 = 0\n\n; Turn on resolving of ambiguous function overloading in favor of the\n; \"explicit\" function declaration (not the one automatically created by\n; the compiler for each type declaration). Default is off.\n; The .ini file has Explicit enabled so that std_logic_signed/unsigned\n; will match the behavior of synthesis tools.\nExplicit = 1\n\n; Turn off acceleration of the VITAL packages. Default is to accelerate.\n; NoVital = 1\n\n; Turn off VITAL compliance checking. Default is checking on.\n; NoVitalCheck = 1\n\n; Ignore VITAL compliance checking errors. Default is to not ignore.\n; IgnoreVitalErrors = 1\n\n; Turn off VITAL compliance checking warnings. Default is to show warnings.\n; Show_VitalChecksWarnings = 0\n\n; Keep silent about case statement static warnings.\n; Default is to give a warning.\n; NoCaseStaticError = 1\n\n; Keep silent about warnings caused by aggregates that are not locally static.\n; Default is to give a warning.\n; NoOthersStaticError = 1\n\n; Turn off inclusion of debugging info within design units.\n; Default is to include debugging info.\n; NoDebug = 1\n\n; Turn off \"Loading...\" messages. Default is messages on.\n; Quiet = 1\n\n; Turn on some limited synthesis rule compliance checking. Checks only:\n;    -- signals used (read) by a process must be in the sensitivity list\n; CheckSynthesis = 1\n\n; Activate optimizations on expressions that do not involve signals,\n; waits, or function/procedure/task invocations. Default is off.\n; ScalarOpts = 1\n\n; Require the user to specify a configuration for all bindings,\n; and do not generate a compile time default binding for the\n; component. This will result in an elaboration error of\n; 'component not bound' if the user fails to do so. Avoids the rare\n; issue of a false dependency upon the unused default binding.\n; RequireConfigForAllDefaultBinding = 1\n\n; Inhibit range checking on subscripts of arrays. Range checking on\n; scalars defined with subtypes is inhibited by default.\n; NoIndexCheck = 1\n\n; Inhibit range checks on all (implicit and explicit) assignments to\n; scalar objects defined with subtypes.\n; NoRangeCheck = 1\n\n[vlog]\n\n; Turn off inclusion of debugging info within design units.\n; Default is to include debugging info.\n; NoDebug = 1\n\n; Turn off \"loading...\" messages. Default is messages on.\n; Quiet = 1\n\n; Turn on Verilog hazard checking (order-dependent accessing of global vars).\n; Default is off.\n; Hazard = 1\n\n; Turn on converting regular Verilog identifiers to uppercase. Allows case\n; insensitivity for module names. Default is no conversion.\n; UpCase = 1\n\n; Turn on incremental compilation of modules. Default is off.\n; Incremental = 1\n\n; Turns on lint-style checking.\n; Show_Lint = 1\n\n[vsim]\n; Simulator resolution\n; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.\nResolution = ps\n\n; User time unit for run commands\n; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the\n; unit specified for Resolution. For example, if Resolution is 100ps,\n; then UserTimeUnit defaults to ps.\n; Should generally be set to default.\nUserTimeUnit = default\n\n; Default run length\nRunLength = 1 ms\n\n; Maximum iterations that can be run without advancing simulation time\nIterationLimit = 5000\n\n; Directive to license manager:\n; vhdl          Immediately reserve a VHDL license\n; vlog          Immediately reserve a Verilog license\n; plus          Immediately reserve a VHDL and Verilog license\n; nomgc         Do not look for Mentor Graphics Licenses\n; nomti         Do not look for Model Technology Licenses\n; noqueue       Do not wait in the license queue when a license isn't available\n; viewsim\tTry for viewer license but accept simulator license(s) instead\n;\t\tof queuing for viewer license\n; License = plus\n\n; Stop the simulator after a VHDL/Verilog assertion message\n; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal\nBreakOnAssertion = 3\n\n; Assertion Message Format\n; %S - Severity Level\n; %R - Report Message\n; %T - Time of assertion\n; %D - Delta\n; %I - Instance or Region pathname (if available)\n; %% - print '%' character\n; AssertionFormat = \"** %S: %R\\n   Time: %T  Iteration: %D%I\\n\"\n\n; Assertion File - alternate file for storing VHDL/Verilog assertion messages\n; AssertFile = assert.log\n\n; Default radix for all windows and commands...\n; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned\nDefaultRadix = hexadecimal\n\n; VSIM Startup command\n; Startup = do startup.do\n\n; File for saving command transcript\nTranscriptFile = transcript\n\n; File for saving command history\n; CommandHistory = cmdhist.log\n\n; Specify whether paths in simulator commands should be described\n; in VHDL or Verilog format.\n; For VHDL, PathSeparator = /\n; For Verilog, PathSeparator = .\n; Must not be the same character as DatasetSeparator.\nPathSeparator = /\n\n; Specify the dataset separator for fully rooted contexts.\n; The default is ':'. For example, sim:/top\n; Must not be the same character as PathSeparator.\nDatasetSeparator = :\n\n; Disable VHDL assertion messages\n; IgnoreNote = 1\n; IgnoreWarning = 1\n; IgnoreError = 1\n; IgnoreFailure = 1\n\n; Default force kind. May be freeze, drive, deposit, or default\n; or in other terms, fixed, wired, or charged.\n; A value of \"default\" will use the signal kind to determine the\n; force kind, drive for resolved signals, freeze for unresolved signals\n; DefaultForceKind = freeze\n\n; If zero, open files when elaborated; otherwise, open files on\n; first read or write.  Default is 0.\n; DelayFileOpen = 1\n\n; Control VHDL files opened for write.\n;   0 = Buffered, 1 = Unbuffered\nUnbufferedOutput = 0\n\n; Control the number of VHDL files open concurrently.\n; This number should always be less than the current ulimit\n; setting for max file descriptors.\n;   0 = unlimited\nConcurrentFileLimit = 40\n\n; Control the number of hierarchical regions displayed as\n; part of a signal name shown in the Wave window.\n; A value of zero tells VSIM to display the full name.\n; The default is 0.\n; WaveSignalNameWidth = 0\n\n; Turn off warnings from the std_logic_arith, std_logic_unsigned\n; and std_logic_signed packages.\n; StdArithNoWarnings = 1\n\n; Turn off warnings from the IEEE numeric_std and numeric_bit packages.\n; NumericStdNoWarnings = 1\n\n; Control the format of the (VHDL) FOR generate statement label\n; for each iteration.  Do not quote it.\n; The format string here must contain the conversion codes %s and %d,\n; in that order, and no other conversion codes.  The %s represents\n; the generate_label; the %d represents the generate parameter value\n; at a particular generate iteration (this is the position number if\n; the generate parameter is of an enumeration type).  Embedded whitespace\n; is allowed (but discouraged); leading and trailing whitespace is ignored.\n; Application of the format must result in a unique scope name over all\n; such names in the design so that name lookup can function properly.\n; GenerateFormat = %s__%d\n\n; Specify whether checkpoint files should be compressed.\n; The default is 1 (compressed).\n; CheckpointCompressMode = 0\n\n; List of dynamically loaded objects for Verilog PLI applications\n; Veriuser = veriuser.sl\n\n; Specify default options for the restart command. Options can be one\n; or more of: -force -nobreakpoint -nolist -nolog -nowave\n; DefaultRestartOptions = -force\n\n; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs\n; (> 500 megabyte memory footprint). Default is disabled.\n; Specify number of megabytes to lock.\n; LockedMemory = 1000\n\n; Turn on (1) or off (0) WLF file compression.\n; The default is 1 (compress WLF file).\n; WLFCompress = 0\n\n; Specify whether to save all design hierarchy (1) in the WLF file\n; or only regions containing logged signals (0).\n; The default is 0 (save only regions with logged signals).\n; WLFSaveAllRegions = 1\n\n; WLF file time limit.  Limit WLF file by time, as closely as possible,\n; to the specified amount of simulation time.  When the limit is exceeded\n; the earliest times get truncated from the file.\n; If both time and size limits are specified the most restrictive is used.\n; UserTimeUnits are used if time units are not specified.\n; The default is 0 (no limit).  Example: WLFTimeLimit = {100 ms}\n; WLFTimeLimit = 0\n\n; WLF file size limit.  Limit WLF file size, as closely as possible,\n; to the specified number of megabytes.  If both time and size limits\n; are specified then the most restrictive is used.\n; The default is 0 (no limit).\n; WLFSizeLimit = 1000\n\n; Specify whether or not a WLF file should be deleted when the\n; simulation ends.  A value of 1 will cause the WLF file to be deleted.\n; The default is 0 (do not delete WLF file when simulation ends).\n; WLFDeleteOnQuit = 1\n\n; Automatic SDF compilation\n; Disables automatic compilation of SDF files in flows that support it.\n; Default is on, uncomment to turn off.\n; NoAutoSDFCompile = 1\n\n[lmc]\n\n[msg_system]\n; Change a message severity or suppress a message.\n; The format is: <msg directive> = <msg number>[,<msg number>...]\n; Examples:\n;   note = 3009\n;   warning = 3033\n;   error = 3010,3016\n;   fatal = 3016,3033\n;   suppress = 3009,3016,3043\n; The command verror <msg number> can be used to get the complete\n; description of a message.\n\n; Control transcripting of elaboration/runtime messages.\n; The default is to have messages appear in the transcript and\n; recorded in the wlf file (messages that are recorded in the\n; wlf file can be viewed in the MsgViewer).  The other settings\n; are to send messages only to the transcript or only to the\n; wlf file.  The valid values are\n;    both  {default}\n;    tran  {transcript only}\n;    wlf   {wlf file only}\n; msgmode = both\n[Project]\n; Warning -- Do not edit the project properties directly.\n;            Property names are dynamic in nature and property\n;            values have special syntax.  Changing property data directly\n;            can result in a corrupt MPF file.  All project properties\n;            can be modified through project window dialogs.\nProject_Version = 6\nProject_DefaultLib = work\nProject_SortMethod = unused\nProject_Files_Count = 44\nProject_File_0 = $ROOT/cpu/alu/alu.v\nProject_File_P_0 = compile_order 11 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder cpu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_1 = $ROOT/cpu/alu/alu_bit_select.v\nProject_File_P_1 = compile_order 12 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder cpu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_2 = $ROOT/cpu/alu/alu_control.v\nProject_File_P_2 = compile_order 13 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder cpu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_3 = $ROOT/cpu/alu/alu_core.v\nProject_File_P_3 = compile_order 14 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder cpu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_4 = $ROOT/cpu/alu/alu_flags.v\nProject_File_P_4 = compile_order 15 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder cpu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_5 = $ROOT/cpu/alu/alu_mux_2.v\nProject_File_P_5 = compile_order 16 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder cpu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_6 = $ROOT/cpu/alu/alu_mux_2z.v\nProject_File_P_6 = compile_order 17 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder cpu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_7 = $ROOT/cpu/alu/alu_mux_3z.v\nProject_File_P_7 = compile_order 18 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder cpu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_8 = $ROOT/cpu/alu/alu_mux_4.v\nProject_File_P_8 = compile_order 19 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder cpu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_9 = $ROOT/cpu/alu/alu_mux_8.v\nProject_File_P_9 = compile_order 20 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder cpu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_10 = $ROOT/cpu/alu/alu_prep_daa.v\nProject_File_P_10 = compile_order 21 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder cpu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_11 = $ROOT/cpu/alu/alu_select.v\nProject_File_P_11 = compile_order 22 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder cpu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_12 = $ROOT/cpu/alu/alu_shifter_core.v\nProject_File_P_12 = compile_order 23 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder cpu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_13 = $ROOT/cpu/alu/alu_slice.v\nProject_File_P_13 = compile_order 24 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder cpu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_14 = $ROOT/cpu/bus/address_latch.v\nProject_File_P_14 = compile_order 26 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder cpu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_15 = $ROOT/cpu/bus/address_mux.v\nProject_File_P_15 = compile_order 40 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder cpu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_16 = $ROOT/cpu/bus/address_pins.v\nProject_File_P_16 = compile_order 27 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder cpu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_17 = $ROOT/cpu/bus/bus_control.v\nProject_File_P_17 = compile_order 28 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder cpu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_18 = $ROOT/cpu/bus/bus_switch.v\nProject_File_P_18 = compile_order 25 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder cpu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_19 = $ROOT/cpu/bus/control_pins_n.v\nProject_File_P_19 = compile_order 35 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder cpu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_20 = $ROOT/cpu/bus/data_pins.v\nProject_File_P_20 = compile_order 29 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder cpu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_21 = $ROOT/cpu/bus/data_switch.v\nProject_File_P_21 = compile_order 30 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder cpu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_22 = $ROOT/cpu/bus/data_switch_mask.v\nProject_File_P_22 = compile_order 31 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder cpu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_23 = $ROOT/cpu/bus/inc_dec.v\nProject_File_P_23 = compile_order 32 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder cpu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_24 = $ROOT/cpu/bus/inc_dec_2bit.v\nProject_File_P_24 = compile_order 33 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder cpu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_25 = $ROOT/cpu/control/clk_delay.v\nProject_File_P_25 = compile_order 5 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder cpu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_26 = $ROOT/cpu/control/decode_state.v\nProject_File_P_26 = compile_order 6 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder cpu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_27 = $ROOT/cpu/control/execute.v\nProject_File_P_27 = compile_order 3 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder cpu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options +incdir+../../../../cpu/control vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_28 = $ROOT/cpu/control/interrupts.v\nProject_File_P_28 = compile_order 7 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder cpu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_29 = $ROOT/cpu/control/ir.v\nProject_File_P_29 = compile_order 8 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder cpu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_30 = $ROOT/cpu/control/memory_ifc.v\nProject_File_P_30 = compile_order 41 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder cpu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_31 = $ROOT/cpu/control/pin_control.v\nProject_File_P_31 = compile_order 39 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder cpu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_32 = $ROOT/cpu/control/pla_decode.v\nProject_File_P_32 = compile_order 4 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder cpu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_33 = $ROOT/cpu/control/resets.v\nProject_File_P_33 = compile_order 9 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder cpu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_34 = $ROOT/cpu/control/sequencer.v\nProject_File_P_34 = compile_order 10 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder cpu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_35 = $ROOT/cpu/registers/reg_control.v\nProject_File_P_35 = compile_order 0 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder cpu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_36 = $ROOT/cpu/registers/reg_file.v\nProject_File_P_36 = compile_order 1 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder cpu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_37 = $ROOT/cpu/registers/reg_latch.v\nProject_File_P_37 = compile_order 2 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder cpu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_38 = $ROOT/cpu/toplevel/z80_top_direct_n.v\nProject_File_P_38 = compile_order 34 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options +incdir+../../../../cpu/toplevel vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_39 = $ROOT/host/basic_de1/basic_de1_ModelSim.sv\nProject_File_P_39 = compile_order 36 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_40 = $ROOT/host/basic_de1/ram.v\nProject_File_P_40 = compile_order 37 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_41 = $ROOT/host/basic_de1/test_host.sv\nProject_File_P_41 = compile_order 38 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_42 = $ROOT/host/common/uart.v\nProject_File_P_42 = compile_order 42 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder uart group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_File_43 = $ROOT/host/common/wait_state.v\nProject_File_P_43 = compile_order 43 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1\nProject_Sim_Count = 1\nProject_Sim_0 = test_host\nProject_Sim_P_0 = timing default -t ps -sdfnoerror 0 -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder {Top Level} +pulse_e {} additional_dus work.test_bench_host -assertfile {} -std_output {} -L altera_mf_ver -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 +plusarg {} -coverage 0 vopt_env 1 -wlf {} -assertdebug 0 -std_input {} -sdfnowarn 0\nProject_Folder_Count = 2\nProject_Folder_0 = uart\nProject_Folder_P_0 = folder {Top Level}\nProject_Folder_1 = cpu\nProject_Folder_P_1 = folder {Top Level}\nEcho_Compile_Output = 0\nSave_Compile_Report = 1\nProject_Opt_Count = 0\nForceSoftPaths = 1\nProjectStatusDelay = 5000\nVERILOG_DoubleClick = Edit\nVERILOG_CustomDoubleClick =\nSYSTEMVERILOG_DoubleClick = Edit\nSYSTEMVERILOG_CustomDoubleClick =\nVHDL_DoubleClick = Edit\nVHDL_CustomDoubleClick =\nPSL_DoubleClick = Edit\nPSL_CustomDoubleClick =\nTEXT_DoubleClick = Edit\nTEXT_CustomDoubleClick =\nSYSTEMC_DoubleClick = Edit\nSYSTEMC_CustomDoubleClick =\nTCL_DoubleClick = Edit\nTCL_CustomDoubleClick =\nMACRO_DoubleClick = Edit\nMACRO_CustomDoubleClick =\nVCD_DoubleClick = Edit\nVCD_CustomDoubleClick =\nSDF_DoubleClick = Edit\nSDF_CustomDoubleClick =\nXML_DoubleClick = Edit\nXML_CustomDoubleClick =\nLOGFILE_DoubleClick = Edit\nLOGFILE_CustomDoubleClick =\nUCDB_DoubleClick = Edit\nUCDB_CustomDoubleClick =\nUPF_DoubleClick = Edit\nUPF_CustomDoubleClick =\nPCF_DoubleClick = Edit\nPCF_CustomDoubleClick =\nPROJECT_DoubleClick = Edit\nPROJECT_CustomDoubleClick =\nVRM_DoubleClick = Edit\nVRM_CustomDoubleClick =\nDEBUGDATABASE_DoubleClick = Edit\nDEBUGDATABASE_CustomDoubleClick =\nDEBUGARCHIVE_DoubleClick = Edit\nDEBUGARCHIVE_CustomDoubleClick =\nProject_Major_Version = 10\nProject_Minor_Version = 1\n"
  },
  {
    "path": "host/basic_de1/simulation/modelsim/wave_host.do",
    "content": "onerror {resume}\nquietly WaveActivateNextPane {} 0\nadd wave -noupdate /test_bench_host/reset\nadd wave -noupdate /test_bench_host/uart_tx\nadd wave -noupdate /test_bench_host/clk\nadd wave -noupdate -expand -group {CPU\n} /test_bench_host/host_/z80_/nM1\nadd wave -noupdate -expand -group {CPU\n} /test_bench_host/host_/z80_/nMREQ\nadd wave -noupdate -expand -group {CPU\n} /test_bench_host/host_/z80_/nIORQ\nadd wave -noupdate -expand -group {CPU\n} /test_bench_host/host_/z80_/nRD\nadd wave -noupdate -expand -group {CPU\n} /test_bench_host/host_/z80_/nWR\nadd wave -noupdate -expand -group {CPU\n} /test_bench_host/host_/z80_/nRFSH\nadd wave -noupdate -expand -group {CPU\n} /test_bench_host/host_/z80_/nHALT\nadd wave -noupdate -expand -group {CPU\n} /test_bench_host/host_/z80_/nBUSACK\nadd wave -noupdate -expand -group {CPU\n} /test_bench_host/host_/z80_/nWAIT\nadd wave -noupdate -expand -group {CPU\n} /test_bench_host/host_/z80_/nINT\nadd wave -noupdate -expand -group {CPU\n} /test_bench_host/host_/z80_/nNMI\nadd wave -noupdate -expand -group {CPU\n} /test_bench_host/host_/z80_/nRESET\nadd wave -noupdate -expand -group {CPU\n} /test_bench_host/host_/z80_/nBUSRQ\nadd wave -noupdate -expand -group {CPU\n} /test_bench_host/host_/z80_/CLK\nadd wave -noupdate -expand -group {CPU\n} /test_bench_host/host_/z80_/A\nadd wave -noupdate -expand -group {CPU\n} /test_bench_host/host_/z80_/D\nadd wave -noupdate -expand -group {host\n} /test_bench_host/host_/A\nadd wave -noupdate -expand -group {host\n} /test_bench_host/host_/D\nadd wave -noupdate -expand -group {host\n} /test_bench_host/host_/RamData\nadd wave -noupdate /test_bench_host/host_/nWAIT_M1_sig\nadd wave -noupdate /test_bench_host/host_/nWAIT_Mem_sig\nadd wave -noupdate -group {RAM\n} /test_bench_host/host_/ram_/address\nadd wave -noupdate -group {RAM\n} /test_bench_host/host_/ram_/clock\nadd wave -noupdate -group {RAM\n} /test_bench_host/host_/ram_/data\nadd wave -noupdate -group {RAM\n} /test_bench_host/host_/ram_/wren\nadd wave -noupdate -group {RAM\n} /test_bench_host/host_/ram_/q\nadd wave -noupdate -group UART /test_bench_host/host_/uart_/BAUD\nadd wave -noupdate -group UART /test_bench_host/host_/uart_/IN_CLOCK\nadd wave -noupdate -group UART /test_bench_host/host_/uart_/busy\nadd wave -noupdate -group UART /test_bench_host/host_/uart_/uart_tx\nadd wave -noupdate -group UART /test_bench_host/host_/uart_/wr\nadd wave -noupdate -group UART /test_bench_host/host_/uart_/data\nadd wave -noupdate -group UART /test_bench_host/host_/uart_/clk\nadd wave -noupdate -group UART /test_bench_host/host_/uart_/reset\nadd wave -noupdate -group UART /test_bench_host/host_/uart_/bitcount\nadd wave -noupdate -group UART /test_bench_host/host_/uart_/shifter\nadd wave -noupdate -group UART /test_bench_host/host_/uart_/sending\nadd wave -noupdate -group UART -radix hexadecimal /test_bench_host/host_/uart_/d\nadd wave -noupdate -group UART -radix hexadecimal /test_bench_host/host_/uart_/inc\nadd wave -noupdate -group UART -radix hexadecimal /test_bench_host/host_/uart_/delta\nadd wave -noupdate -group UART -radix hexadecimal /test_bench_host/host_/uart_/ser_clk\nTreeUpdate [SetDefaultTree]\nWaveRestoreCursors {Cursor {168431 ps} 0}\nquietly wave cursor active 1\nconfigure wave -namecolwidth 184\nconfigure wave -valuecolwidth 60\nconfigure wave -justifyvalue right\nconfigure wave -signalnamewidth 2\nconfigure wave -snapdistance 10\nconfigure wave -datasetprefix 0\nconfigure wave -rowmargin 4\nconfigure wave -childrowmargin 2\nconfigure wave -gridoffset 0\nconfigure wave -gridperiod 1\nconfigure wave -griddelta 40\nconfigure wave -timeline 0\nconfigure wave -timelineunits us\nupdate\nWaveRestoreZoom {0 ps} {2036140 ps}\n"
  },
  {
    "path": "host/basic_de1/test_host.sv",
    "content": "//--------------------------------------------------------------\n// Testbench for the host board\n//--------------------------------------------------------------\n`timescale 10 ns/ 10 ns\n\nmodule test_bench_host();\n\nreg reset;\nreg nint;\nreg nnmi;\nwire uart_tx;\n\n// Proper sequence for the ModelSim reset\ninitial begin : init\n    reset = 0;\n    nint = 1;\n    nnmi = 1;\n#10 reset = 1;\nend : init\n\nreg clk = 1;\ninitial forever #1 clk = ~clk;\n\nhost host_( .nint(nint), .nnmi(nnmi), .clk(clk), .reset(reset), .uart_tx(uart_tx) );\n\nendmodule\n"
  },
  {
    "path": "host/basic_nexys3/Nexys3_master.ucf",
    "content": "## This file is a general .ucf for Nexys3 rev B board\n## To use it in a project:\n## - remove or comment the lines corresponding to unused pins\n## - rename the used signals according to the project\n\n## Clock signal\nNET \"CLOCK_100\"       LOC = \"V10\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 2, pin name = IO_L30N_GCLK0_USERCCLK,            Sch name = GCLK\n#Net \"clk\" TNM_NET = sys_clk_pin;\n#TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz;\n\nNET \"KEY0\" CLOCK_DEDICATED_ROUTE = FALSE;\nNET \"KEY1\" CLOCK_DEDICATED_ROUTE = FALSE;\nNET \"KEY2\" CLOCK_DEDICATED_ROUTE = FALSE;\n\nPIN \"KEY2_BUFGP/BUFG.O\" CLOCK_DEDICATED_ROUTE = FALSE;\n\n## onBoard USB controller\n## NOTE: DEPP and DSTM net names use some of the same pins, if trying to use both DEPP and DSTM use a signle net name for each shared pin.\n\n## Data bus for both the DEPP and DSTM interfaces uncomment lines 15-22 if using either one\n#NET \"DB<0>\"          LOC = \"E1\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L50N_M3BA2,                     Sch name = U-FD0\n#NET \"DB<1>\"          LOC = \"F4\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L51P_M3A10,                     Sch name = U-FD1\n#NET \"DB<2>\"          LOC = \"F3\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L51N_M3A4,                      Sch name = U-FD2\n#NET \"DB<3>\"          LOC = \"D2\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L52P_M3A8,                      Sch name = U-FD3\n#NET \"DB<4>\"          LOC = \"D1\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L52N_M3A9,                      Sch name = U-FD4\n#NET \"DB<5>\"          LOC = \"H7\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L53P_M3CKE,                     Sch name = U-FD5\n#NET \"DB<6>\"          LOC = \"G6\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L53N_M3A12,                     Sch name = U-FD6\n#NET \"DB<7>\"          LOC = \"E4\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L54P_M3RESET,                   Sch name = U-FD7\n\n## If using the DEPP interface uncomment lines 25-28\n#NET \"EppWRITE\"       LOC = \"F5\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L55N_M3A14,                     Sch name = U-FLAGC\n#NET \"EppASTB\"        LOC = \"H1\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L41N_GCLK26_M3DQ5,              Sch name = U-FLAGA\n#NET \"EppDSTB\"        LOC = \"K4\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L42P_GCLK25_TRDY2_M3UDM,        Sch name = U-FLAGB\n#NET \"EppWAIT\"        LOC = \"C2\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L83P,                           Sch name = U-SLRD\n\n## If using the DSTM interface uncomment lines 31-40\n#NET \"DstmIFCLK\"      LOC = \"H2\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L41P_GCLK27_M3DQ4,              Sch name = U-IFCLK\n#NET \"DstmSLCS\"       LOC = \"F6\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L55P_M3A13,                     Sch name = U-SLCS\n#NET \"DstmFLAGA\"      LOC = \"H1\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L41N_GCLK26_M3DQ5,              Sch name = U-FLAGA\n#NET \"DstmFLAGB\"      LOC = \"K4\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L42P_GCLK25_TRDY2_M3UDM,        Sch name = U-FLAGB\n#NET \"DstmADR<0>\"     LOC = \"H5\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L49N_M3A2,                      Sch name = U-FIFOAD0\n#NET \"DstmADR<1>\"     LOC = \"E3\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L50P_M3WE,                      Sch name = U-FIFOAD1\n#Net \"DstmSLRD\"       LOC = \"C2\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L83P,                           Sch name = U-SLRD\n#NET \"DstmSLWR\"       LOC = \"C1\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L83N_VREF,                      Sch name = U-SLWR\n#NET \"DstmSLOE\"       LOC = \"H6\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L49P_M3A7,                      Sch name = U-SLOE\n#NET \"DstmPKTEND\"     LOC = \"D3\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L54N_M3A11,                     Sch name = U-PKTEND\n\n#NET \"UsbMode\"        LOC = \"F1\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L48N_M3BA1,                     Sch name = U-INT0#\n\n\n## onBoard Cellular RAM, Numonyx StrataFlash and Numonyx Quad Flash\n#NET \"MemOE\"          LOC = \"L18\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L46N_FOE_B_M1DQ3,               Sch name = P30-OE\n#NET \"MemWR\"          LOC = \"M16\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L47P_FWE_B_M1DQ0,               Sch name = P30-WE\n\n#NET \"RamAdv\"         LOC = \"H18\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L43N_GCLK4_M1DQ5,               Sch name = P30-ADV\n#NET \"RamCS\"          LOC = \"L15\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L42P_GCLK7_M1UDM,               Sch name = MT-CE\n#NET \"RamClk\"         LOC = \"R10\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 2, Pin name = IO_L29P_GCLK3,                     Sch name = P30-CLK\n#NET \"RamCRE\"         LOC = \"M18\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L47N_LDC_M1DQ1,                 Sch name = MT-CRE\n#NET \"RamLB\"          LOC = \"K16\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L41N_GCLK8_M1CASN,              Sch name = MT-LB\n#NET \"RamUB\"          LOC = \"K15\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L41P_GCLK9_IRDY1_M1RASN,        Sch name = MT-UB\n#NET \"RamWait\"        LOC = \"V4\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 2, Pin name = IO_L63N,                           Sch name = P30-WAIT\n\n#NET \"FlashRp\"        LOC = \"T4\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 2, Pin name = IO_L63P,                           Sch name = P30-RST\n#NET \"FlashCS\"        LOC = \"L17\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L46P_FCS_B_M1DQ2,               Sch name = P30-CE\n\n#NET \"QuadSpiFlashCS\"    LOC=\"V3\"  | IOSTANDARD = \"LVCMOS33\";  #Bank = MISC, Pin name = IO_L65N_CSO_B_2,                Sch name = CS\n#NET \"QuadSpiFlashSck\"   LOC=\"R15\" | IOSTANDARD = \"LVCMOS33\";  #Bank = MISC, Pin name = IO_L1P_CCLK_2,                  Sch name = SCK\n#NET \"QuadSpiFlashDB<0>\" LOC=\"T13\" | IOSTANDARD = \"LVCMOS33\";  #Dual/Quad SPI Flash DB<0>, Bank = MISC, Pin name = IO_L3N_MOSI_CSI_B_MISO0_2, Sch name = SDI\n\n#NET \"MemAdr<1>\"      LOC = \"K18\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L45N_A0_M1LDQSN,                Sch name = P30-A0\n#NET \"MemAdr<2>\"      LOC = \"K17\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L45P_A1_M1LDQS,                 Sch name = P30-A1\n#NET \"MemAdr<3>\"      LOC = \"J18\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L44N_A2_M1DQ7,                  Sch name = P30-A2\n#NET \"MemAdr<4>\"      LOC = \"J16\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L44P_A3_M1DQ6,                  Sch name = P30-A3\n#NET \"MemAdr<5>\"      LOC = \"G18\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L38N_A4_M1CLKN,                 Sch name = P30-A4\n#NET \"MemAdr<6>\"      LOC = \"G16\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L38P_A5_M1CLK,                  Sch name = P30-A5\n#NET \"MemAdr<7>\"      LOC = \"H16\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L37N_A6_M1A1,                   Sch name = P30-A6\n#NET \"MemAdr<8>\"      LOC = \"H15\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L37P_A7_M1A0,                   Sch name = P30-A7\n#NET \"MemAdr<9>\"      LOC = \"H14\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L36N_A8_M1BA1,                  Sch name = P30-A8\n#NET \"MemAdr<10>\"     LOC = \"H13\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L36P_A9_M1BA0,                  Sch name = P30-A9\n#NET \"MemAdr<11>\"     LOC = \"F18\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L35N_A10_M1A2,                  Sch name = P30-A10\n#NET \"MemAdr<12>\"     LOC = \"F17\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L35P_A11_M1A7,                  Sch name = P30-A11\n#NET \"MemAdr<13>\"     LOC = \"K13\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L34N_A12_M1BA2,                 Sch name = P30-A12\n#NET \"MemAdr<14>\"     LOC = \"K12\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L34P_A13_M1WE,                  Sch name = P30-A13\n#NET \"MemAdr<15>\"     LOC = \"E18\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L33N_A14_M1A4,                  Sch name = P30-A14\n#NET \"MemAdr<16>\"     LOC = \"E16\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L33P_A15_M1A10,                 Sch name = P30-A15\n#NET \"MemAdr<17>\"     LOC = \"G13\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L32N_A16_M1A9,                  Sch name = P30-A16\n#NET \"MemAdr<18>\"     LOC = \"H12\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L32P_A17_M1A8,                  Sch name = P30-A17\n#NET \"MemAdr<19>\"     LOC = \"D18\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L31N_A18_M1A12,                 Sch name = P30-A18\n#NET \"MemAdr<20>\"     LOC = \"D17\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L31P_A19_M1CKE,                 Sch name = P30-A19\n#NET \"MemAdr<21>\"     LOC = \"G14\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L30N_A20_M1A11,                 Sch name = P30-A20\n#NET \"MemAdr<22>\"     LOC = \"F14\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L30P_A21_M1RESET                Sch name = P30-A21\n#NET \"MemAdr<23>\"     LOC = \"C18\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L29N_A22_M1A14,                 Sch name = P30-A22\n#NET \"MemAdr<24>\"     LOC = \"C17\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L29P_A23_M1A13,                 Sch name = P30-A23\n#NET \"MemAdr<25>\"     LOC = \"F16\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L1N_A24_VREF,                   Sch name = P30-A24\n#NET \"MemAdr<26>\"     LOC = \"F15\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L1P_A25,                        Sch name = P30-A25\n\n#NET \"MemDB<0>\"       LOC = \"R13\" | IOSTANDARD = \"LVCMOS33\";   #Ram or Numonyx Paralell Flash DB<0>, or Dual/Quad SPI Flash DB<1>, Bank = MISC, Pin name = IO_L3P_D0_DIN_MISO_MISO1_2,     Sch name = P30-DQ0\n#NET \"MemDB<1>\"       LOC = \"T14\" | IOSTANDARD = \"LVCMOS33\";   #Ram or Numonyx Paralell Flash DB<1>, or Quad SPI Flash DB<2>, Bank = MISC, Pin name = IO_L12P_D1_MISO2_2,                      Sch name = P30-DQ1\n#NET \"MemDB<2>\"       LOC = \"V14\" | IOSTANDARD = \"LVCMOS33\";   #Ram or Numonyx Paralell Flash DB<2>, or Quad SPI Flash DB<3>, Bank = MISC, Pin name = IO_L12N_D2_MISO3_2,                      Sch name = P30-DQ2\n#NET \"MemDB<3>\"       LOC = \"U5\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 2, Pin name = IO_49P_D3,                         Sch name = P30-DQ3\n#NET \"MemDB<4>\"       LOC = \"V5\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 2, Pin name = IO_49N_D4,                         Sch name = P30-DQ4\n#NET \"MemDB<5>\"       LOC = \"R3\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 2, Pin name = IO_L62P_D5,                        Sch name = P30-DQ5\n#NET \"MemDB<6>\"       LOC = \"T3\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 2, Pin name = IO_L62N_D6,                        Sch name = P30-DQ6\n#NET \"MemDB<7>\"       LOC = \"R5\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 2, Pin name = IO_L48P_D7,                        Sch name = P30-DQ7\n#NET \"MemDB<8>\"       LOC = \"N5\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 2, Pin name = IO_L64P_D8,                        Sch name = P30-DQ8\n#NET \"MemDB<9>\"       LOC = \"P6\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 2, Pin name = IO_L64N_D9,                        Sch name = P30-DQ9\n#NET \"MemDB<10>\"      LOC = \"P12\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 2, Pin name = IO_L13N_D10,                       Sch name = P30-DQ10\n#NET \"MemDB<11>\"      LOC = \"U13\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 2, Pin name = IO_L14P_D11,                       Sch name = P30-DQ11\n#NET \"MemDB<12>\"      LOC = \"V13\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 2, Pin name = IO_L14N_D12,                       Sch name = P30-DQ12\n#NET \"MemDB<13>\"      LOC = \"U10\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 2, Pin name = IO_L30P_GCLK1_D13,                 Sch name = P30-DQ13\n#NET \"MemDB<14>\"      LOC = \"R8\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 2, Pin name = IO_L31P_GCLK31_D14,                Sch name = P30-DQ14\n#NET \"MemDB<15>\"      LOC = \"T8\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 2, Pin name = IO_L31N_GCLK30_D15,                Sch name = P30-DQ15\n\n\n## 7 segment display\n#NET \"seg<0>\"         LOC = \"T17\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L51P_M1DQ12,                    Sch name = CA\n#NET \"seg<1>\"         LOC = \"T18\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L51N_M1DQ13,                    Sch name = CB\n#NET \"seg<2>\"         LOC = \"U17\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L52P_M1DQ14,                    Sch name = CC\n#NET \"seg<3>\"         LOC = \"U18\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L52N_M1DQ15,                    Sch name = CD\n#NET \"seg<4>\"         LOC = \"M14\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L53P,                           Sch name = CE\n#NET \"seg<5>\"         LOC = \"N14\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L53N_VREF,                      Sch name = CF\n#NET \"seg<6>\"         LOC = \"L14\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L61P,                           Sch name = CG\n#NET \"seg<7>\"         LOC = \"M13\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L61N,                           Sch name = DP\n\n#NET \"an<0>\"          LOC = \"N16\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L50N_M1UDQSN,                   Sch name = AN0\n#NET \"an<1>\"          LOC = \"N15\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L50P_M1UDQS,                    Sch name = AN1\n#NET \"an<2>\"          LOC = \"P18\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L49N_M1DQ11,                    Sch name = AN2\n#NET \"an<3>\"          LOC = \"P17\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L49P_M1DQ10,                    Sch name = AN3\n\n\n## Leds\n#NET \"Led<0>\"         LOC = \"U16\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 2, Pin name = IO_L2P_CMPCLK,                     Sch name = LD0\n#NET \"Led<1>\"         LOC = \"V16\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 2, Pin name = IO_L2N_CMPMOSI,                    Sch name = LD1\n#NET \"Led<2>\"         LOC = \"U15\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 2, Pin name = IO_L5P,                            Sch name = LD2\n#NET \"Led<3>\"         LOC = \"V15\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 2, Pin name = IO_L5N,                            Sch name = LD3\n#NET \"Led<4>\"         LOC = \"M11\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 2, Pin name = IO_L15P,                           Sch name = LD4\n#NET \"Led<5>\"         LOC = \"N11\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 2, Pin name = IO_L15N,                           Sch name = LD5\n#NET \"Led<6>\"         LOC = \"R11\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 2, Pin name = IO_L16P,                           Sch name = LD6\n#NET \"Led<7>\"         LOC = \"T11\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 2, Pin name = IO_L16N_VREF,                      Sch name = LD7\n\n\n## Switches\n#NET \"sw<0>\"          LOC = \"T10\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 2, Pin name = IO_L29N_GCLK2,                     Sch name = SW0\n#NET \"sw<1>\"          LOC = \"T9\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 2, Pin name = IO_L32P_GCLK29,                    Sch name = SW1\n#NET \"sw<2>\"          LOC = \"V9\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 2, Pin name = IO_L32N_GCLK28,                    Sch name = SW2\n#NET \"sw<3>\"          LOC = \"M8\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 2, Pin name = IO_L40P,                           Sch name = SW3\n#NET \"sw<4>\"          LOC = \"N8\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 2, Pin name = IO_L40N,                           Sch name = SW4\n#NET \"sw<5>\"          LOC = \"U8\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 2, Pin name = IO_L41P,                           Sch name = SW5\n#NET \"sw<6>\"          LOC = \"V8\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 2, Pin name = IO_L41N_VREF,                      Sch name = SW6\n#NET \"sw<7>\"          LOC = \"T5\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = MISC, Pin name = IO_L48N_RDWR_B_VREF_2,          Sch name = SW7\n\n\n## Buttons\nNET \"KEY0\"            LOC = \"B8\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L33P,                           Sch name = BTNS\nNET \"KEY1\"            LOC = \"A8\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L33N,                           Sch name = BTNU\nNET \"KEY2\"            LOC = \"C4\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L1N_VREF,                       Sch name = BTNL\n#NET \"btn<3>\"         LOC = \"C9\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L34N_GCLK18,                    Sch name = BTND\n#NET \"btn<4>\"         LOC = \"D9\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L34P_GCLK19,                    Sch name = BTNR\n\n\n## VGA Connector\n#NET \"vgaRed<0>\"      LOC = \"U7\"  | IOSTANDARD = \"LVCMOS33\";   # Bank = 2, Pin name = IO_L43P,                          Sch name = RED0\n#NET \"vgaRed<1>\"      LOC = \"V7\"  | IOSTANDARD = \"LVCMOS33\";   # Bank = 2, Pin name = IO_L43N,                          Sch name = RED1\n#NET \"vgaRed<2>\"      LOC = \"N7\"  | IOSTANDARD = \"LVCMOS33\";   # Bank = 2, Pin name = IO_L44P,                          Sch name = RED2\n#NET \"vgaGreen<0>\"    LOC = \"P8\"  | IOSTANDARD = \"LVCMOS33\";   # Bank = 2, Pin name = IO_L44N,                          Sch name = GRN0\n#NET \"vgaGreen<1>\"    LOC = \"T6\"  | IOSTANDARD = \"LVCMOS33\";   # Bank = 2, Pin name = IO_L45P,                          Sch name = GRN1\n#NET \"vgaGreen<2>\"    LOC = \"V6\"  | IOSTANDARD = \"LVCMOS33\";   # Bank = 2, Pin name = IO_L45N,                          Sch name = GRN2\n#NET \"vgaBlue<1>\"     LOC = \"R7\"  | IOSTANDARD = \"LVCMOS33\";   # Bank = 2, Pin name = IO_L46P,                          Sch name = BLU1\n#NET \"vgaBlue<2>\"     LOC = \"T7\"  | IOSTANDARD = \"LVCMOS33\";   # Bank = 2, Pin name = IO_L46N,                          Sch name = BLU2\n\n#NET \"Hsync\"          LOC = \"N6\"  | IOSTANDARD = \"LVCMOS33\";   # Bank = 2, Pin name = IO_L47P,                          Sch name = HSYNC\n#NET \"Vsync\"          LOC = \"P7\"  | IOSTANDARD = \"LVCMOS33\";   # Bank = 2, Pin name = IO_L47N,                          Sch name = VSYNC\n\n\n## 12 pin connectors\n\n##JA\nNET \"GPIO_0<0>\"          LOC = \"T12\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 2, Pin name = IO_L19P,                           Sch name = JA1\nNET \"GPIO_0<1>\"          LOC = \"V12\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 2, Pin name = IO_L19N,                           Sch name = JA2  \nNET \"GPIO_0<2>\"          LOC = \"N10\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 2, Pin name = IO_L20P,                           Sch name = JA3\nNET \"GPIO_0<3>\"          LOC = \"P11\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 2, Pin name = IO_L20N,                           Sch name = JA4\nNET \"GPIO_0<4>\"          LOC = \"M10\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 2, Pin name = IO_L22P,                           Sch name = JA7\nNET \"GPIO_0<5>\"          LOC = \"N9\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 2, Pin name = IO_L22N,                           Sch name = JA8\nNET \"GPIO_0<6>\"          LOC = \"U11\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 2, Pin name = IO_L23P,                           Sch name = JA9\nNET \"GPIO_0<7>\"          LOC = \"V11\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 2, Pin name = IO_L23N,                           Sch name = JA10\n\n##JB\nNET \"GPIO_1<0>\"           LOC = \"K2\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L38P_M3DQ2,                     Sch name = JB1\nNET \"GPIO_1<1>\"           LOC = \"K1\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L38N_M3DQ3,                     Sch name = JB2\nNET \"GPIO_1<2>\"           LOC = \"L4\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L39P_M3LDQS,                    Sch name = JB3\nNET \"GPIO_1<3>\"           LOC = \"L3\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L39N_M3LDQSN,                   Sch name = JB4\nNET \"GPIO_1<4>\"           LOC = \"J3\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L40P_M3DQ6,                     Sch name = JB7\nNET \"GPIO_1<5>\"           LOC = \"J1\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L40N_M3DQ7,                     Sch name = JB8\nNET \"GPIO_1<6>\"           LOC = \"K3\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L42N_GCLK24_M3LDM,              Sch name = JB9\nNET \"GPIO_1<7>\"           LOC = \"K5\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L43N_GCLK22_IRDY2_M3CASN,       Sch name = JB10\n\n##JC\nNET \"GPIO_2<0>\"          LOC = \"H3\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L44N_GCLK20_M3A6,               Sch name = JC1\nNET \"GPIO_2<1>\"          LOC = \"L7\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L45P_M3A3,                      Sch name = JC2\nNET \"GPIO_2<2>\"          LOC = \"K6\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L45N_M3ODT,                     Sch name = JC3\nNET \"GPIO_2<3>\"          LOC = \"G3\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L46P_M3CLK,                     Sch name = JC4\nNET \"GPIO_2<4>\"          LOC = \"G1\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L46N_M3CLKN,                    Sch name = JC7\nNET \"GPIO_2<5>\"          LOC = \"J7\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L47P_M3A0,                      Sch name = JC8\nNET \"GPIO_2<6>\"          LOC = \"J6\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L47N_M3A1,                      Sch name = JC9\nNET \"GPIO_2<7>\"          LOC = \"F2\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L48P_M3BA0,                     Sch name = JC10\n\n##JD, LX16 Die only\nNET \"GPIO_3<0>\"          LOC = \"G11\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L40P,                           Sch name = JD1\nNET \"GPIO_3<1>\"          LOC = \"F10\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L40N,                           Sch name = JD2\nNET \"GPIO_3<2>\"          LOC = \"F11\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L42P,                           Sch name = JD3\nNET \"GPIO_3<3>\"          LOC = \"E11\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L42N,                           Sch name = JD4\nNET \"GPIO_3<4>\"          LOC = \"D12\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L47P,                           Sch name = JD7\nNET \"GPIO_3<5>\"          LOC = \"C12\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L47N,                           Sch name = JD8\nNET \"GPIO_3<6>\"          LOC = \"F12\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L51P,                           Sch name = JD9\nNET \"GPIO_3<7>\"          LOC = \"E12\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L51N,                           Sch name = JD10\n\n\n## SMSC ethernet PHY\n#NET \"PhyRstn\"        LOC = \"P3\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L2N,                            Sch name = ETH-RST\n#NET \"PhyCrs\"         LOC = \"N3\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L1N_VREF,                       Sch name = ETH-CRS\n#NET \"PhyCol\"         LOC = \"P4\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L2P,                            Sch name = ETH-COL\n#NET \"PhyClk25Mhz\"    LOC = \"N4\"  | IOSTANDARD = \"LVCMOS33\";   #Unconnected if R172 is not loaded, Bank = 3, Pin name = IO_L1P, Sch name = ETH-CLK25MHZ\n\n#NET \"PhyTxd<3>\"      LOC = \"T1\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L33N_M3DQ13,                    Sch name = ETH-TXD3 \n#NET \"PhyTxd<2>\"      LOC = \"T2\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L33P_M3DQ12,                    Sch name = ETH-TXD2\n#NET \"PhyTxd<1>\"      LOC = \"U1\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L32N_M3DQ15,                    Sch name = ETH-TXD1\n#NET \"PhyTxd<0>\"      LOC = \"U2\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L32P_M3DQ14,                    Sch name = ETH-TXD0\n#NET \"PhyTxEn\"        LOC = \"L2\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L37P_M3DQ0,                     Sch name = ETH-TX_EN\n#NET \"PhyTxClk\"       LOC = \"L5\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L43P_GCLK23_M3RASN,             Sch name = ETH-TX_CLK\n#NET \"PhyTxEr\"        LOC = \"P2\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L34P_M3UDQS,                    Sch name = ETH-TXD4\n\n#NET \"PhyRxd<3>\"      LOC = \"M3\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L36P_M3DQ8,                     Sch name = ETH-RXD3\n#NET \"PhyRxd<2>\"      LOC = \"N1\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L35N_M3DQ11,                    Sch name = ETH-RXD2\n#NET \"PhyRxd<1>\"      LOC = \"N2\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L35P_M3DQ10,                    Sch name = ETH-RXD1\n#NET \"PhyRxd<0>\"      LOC = \"P1\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L34N_M3UDQSN,                   Sch name = ETH-RXD0\n#NET \"PhyRxDv\"        LOC = \"L1\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L37N_M3DQ1,                     Sch name = ETH-RX_DV\n#NET \"PhyRxEr\"        LOC = \"M1\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L36N_M3DQ9,                     Sch name = ETH-RXD4\n#NET \"PhyRxClk\"       LOC = \"H4\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L44P_GCLK21_M3A5,               Sch name = ETH-RX_CLK\n\n#NET \"PhyMdc\"         LOC = \"M5\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L31N_VREF,                      Sch name = ETH-MDC\n#NET \"PhyMdio\"        LOC = \"L6\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 3, Pin name = IO_L31P,                           Sch name = ETH-MDIO\n\n\n## Pic USB-HID interface\n#NET \"PS2KeyboardData\" LOC = \"J13\" | IOSTANDARD = \"LVCMOS33\" | PULLUP;  #Bank = 1, Pin name = IO_L39P_M1A3,             Sch name = PIC-SDI1\n#NET \"PS2KeyboardClk\"  LOC = \"L12\" | IOSTANDARD = \"LVCMOS33\" | PULLUP;  #Bank = 1, Pin name = IO_L40P_GCLK11_M1A5,      Sch name = PIC-SCK1\n\n#NET \"PS2MouseData\"   LOC = \"K14\" | IOSTANDARD = \"LVCMOS33\" | PULLUP;   #Bank = 1, Pin name = IO_L39N_M1ODT,            Sch name = PIC-SDO1\n#NET \"PS2MouseClk\"    LOC = \"L13\" | IOSTANDARD = \"LVCMOS33\" | PULLUP;   #Bank = 1, Pin name = IO_L40N_GCLK10_M1A6,      Sch name = PIC-SS1\n\n#NET \"PicGpio<0>\"     LOC = \"L16\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L42N_GCLK6_TRDY1_M1LDM,         Sch name = PIC-GPIO0\n#NET \"PicGpio<1>\"     LOC = \"H17\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L43P_GCLK5_M1DQ4,               Sch name = PIC-GPIO1\n\n\n## Usb-RS232 interface\n#NET \"RsRx\"           LOC = \"N17\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L48P_HDC_M1DQ8,                 Sch name = MCU-RX\nNET \"UART_TXD\"        LOC = \"N18\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 1, Pin name = IO_L48N_M1DQ9,                     Sch name = MCU-TX\n\n\n## VHDCI Connector\n#NET \"EXP-IO_P<0>\"    LOC = \"B2\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L2P,                            Sch name = EXP_IO1_P\n#NET \"EXP-IO_N<0>\"    LOC = \"A2\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L2N,                            Sch name = EXP_IO1_N\n#NET \"EXP-IO_P<1>\"    LOC = \"D6\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L3P,                            Sch name = EXP_IO2_P\n#NET \"EXP-IO_N<1>\"    LOC = \"C6\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L3N,                            Sch name = EXP_IO2_N\n#NET \"EXP-IO_P<2>\"    LOC = \"B3\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L4P,                            Sch name = EXP_IO3_P\n#NET \"EXP-IO_N<2>\"    LOC = \"A3\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L4N,                            Sch name = EXP_IO3_N\n#NET \"EXP-IO_P<3>\"    LOC = \"B4\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L5P,                            Sch name = EXP_IO4_P\n#NET \"EXP-IO_N<3>\"    LOC = \"A4\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L5N,                            Sch name = EXP_IO4_N\n#NET \"EXP-IO_P<4>\"    LOC = \"C5\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L6P,                            Sch name = EXP_IO5_P\n#NET \"EXP-IO_N<4>\"    LOC = \"A5\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L6N,                            Sch name = EXP_IO5_N\n#NET \"EXP-IO_P<5>\"    LOC = \"B6\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L8P,                            Sch name = EXP_IO6_P\n#NET \"EXP-IO_N<5>\"    LOC = \"A6\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L8N_VREF,                       Sch name = EXP_IO6_N\n#NET \"EXP-IO_P<6>\"    LOC = \"C7\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L10P,                           Sch name = EXP_IO7_P\n#NET \"EXP-IO_N<6>\"    LOC = \"A7\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L10N,                           Sch name = EXP_IO7_N\n#NET \"EXP-IO_P<7>\"    LOC = \"D8\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L11P,                           Sch name = EXP_IO8_P\n#NET \"EXP-IO_N<7>\"    LOC = \"C8\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L11N,                           Sch name = EXP_IO8_N\n#NET \"EXP-IO_P<8>\"    LOC = \"B9\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L35P_GCLK17,                    Sch name = EXP_IO9_P\n#NET \"EXP-IO_N<8>\"    LOC = \"A9\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L35N_GCLK16,                    Sch name = EXP_IO9_N\n#NET \"EXP-IO_P<9>\"    LOC = \"D11\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L36P_GCLK15,                    Sch name = EXP_IO10_P\n#NET \"EXP-IO_N<9>\"    LOC = \"C11\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L36N_GCLK14,                    Sch name = EXP_IO10_N\n#NET \"EXP-IO_P<10>\"   LOC = \"C10\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L37P_GCLK13,                    Sch name = EXP_IO11_P\n#NET \"EXP-IO_N<10>\"   LOC = \"A10\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L37N_GCLK12,                    Sch name = EXP_IO11_N\n#NET \"EXP-IO_P<11>\"   LOC = \"G9\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L38P,                           Sch name = EXP_IO12_P\n#NET \"EXP-IO_N<11>\"   LOC = \"F9\"  | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L38N_VREF,                      Sch name = EXP_IO12_N\n#NET \"EXP-IO_P<12>\"   LOC = \"B11\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L39P,                           Sch name = EXP_IO13_P\n#NET \"EXP-IO_N<12>\"   LOC = \"A11\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L39N,                           Sch name = EXP_IO13_N\n#NET \"EXP-IO_P<13>\"   LOC = \"B12\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L41P,                           Sch name = EXP_IO14_P\n#NET \"EXP-IO_N<13>\"   LOC = \"A12\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L41N,                           Sch name = EXP_IO14_N\n#NET \"EXP-IO_P<14>\"   LOC = \"C13\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L50P,                           Sch name = EXP_IO15_P\n#NET \"EXP-IO_N<14>\"   LOC = \"A13\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L50N,                           Sch name = EXP_IO15_N\n#NET \"EXP-IO_P<15>\"   LOC = \"B14\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L62P,                           Sch name = EXP_IO16_P\n#NET \"EXP-IO_N<15>\"   LOC = \"A14\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L62N_VREF,                      Sch name = EXP_IO16_N\n#NET \"EXP-IO_P<16>\"   LOC = \"F13\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L63P_SCP7,                      Sch name = EXP_IO17_P\n#NET \"EXP-IO_N<16>\"   LOC = \"E13\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L63N_SCP6,                      Sch name = EXP_IO17_N\n#NET \"EXP-IO_P<17>\"   LOC = \"C15\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L64P_SCP5,                      Sch name = EXP_IO18_P\n#NET \"EXP-IO_N<17>\"   LOC = \"A15\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L64N_SCP4,                      Sch name = EXP_IO18_N\n#NET \"EXP-IO_P<18>\"   LOC = \"D14\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L65P_SCP3,                      Sch name = EXP_IO19_P\n#NET \"EXP-IO_N<18>\"   LOC = \"C14\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L65N_SCP2,                      Sch name = EXP_IO19_N\n#NET \"EXP-IO_P<19>\"   LOC = \"B16\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L66P_SCP1,                      Sch name = EXP_IO20_P\n#NET \"EXP-IO_N<19>\"   LOC = \"A16\" | IOSTANDARD = \"LVCMOS33\";   #Bank = 0, Pin name = IO_L66N_SCP0,                      Sch name = EXP_IO20_N\n"
  },
  {
    "path": "host/basic_nexys3/basic_nexys3.xise",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\" standalone=\"no\" ?>\n<project xmlns=\"http://www.xilinx.com/XMLSchema\" xmlns:xil_pn=\"http://www.xilinx.com/XMLSchema\">\n\n  <header>\n    <!-- ISE source project file created by Project Navigator.             -->\n    <!--                                                                   -->\n    <!-- This file contains project source information including a list of -->\n    <!-- project source files, project and process properties.  This file, -->\n    <!-- along with the project source files, is sufficient to open and    -->\n    <!-- implement in ISE Project Navigator.                               -->\n    <!--                                                                   -->\n    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->\n  </header>\n\n  <version xil_pn:ise_version=\"14.7\" xil_pn:schema_version=\"2\"/>\n\n  <files>\n    <file xil_pn:name=\"basic_nexys3_fpga.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"43\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"43\"/>\n    </file>\n    <file xil_pn:name=\"../../cpu/toplevel/z80_top_direct_n.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"42\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"42\"/>\n    </file>\n    <file xil_pn:name=\"../../cpu/control/clk_delay.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"26\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"26\"/>\n    </file>\n    <file xil_pn:name=\"../../cpu/control/decode_state.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"25\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"25\"/>\n    </file>\n    <file xil_pn:name=\"../../cpu/control/execute.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"24\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"24\"/>\n    </file>\n    <file xil_pn:name=\"../../cpu/control/interrupts.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"23\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"23\"/>\n    </file>\n    <file xil_pn:name=\"../../cpu/control/ir.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"22\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"22\"/>\n    </file>\n    <file xil_pn:name=\"../../cpu/control/pin_control.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"20\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"20\"/>\n    </file>\n    <file xil_pn:name=\"../../cpu/control/pla_decode.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"19\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"19\"/>\n    </file>\n    <file xil_pn:name=\"../../cpu/control/resets.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"18\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"18\"/>\n    </file>\n    <file xil_pn:name=\"../../cpu/control/memory_ifc.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"21\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"21\"/>\n    </file>\n    <file xil_pn:name=\"../../cpu/control/sequencer.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"17\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"17\"/>\n    </file>\n    <file xil_pn:name=\"../../cpu/alu/alu_control.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"37\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"37\"/>\n    </file>\n    <file xil_pn:name=\"../../cpu/alu/alu_mux_4.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"9\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"9\"/>\n    </file>\n    <file xil_pn:name=\"../../cpu/alu/alu_mux_8.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"8\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"8\"/>\n    </file>\n    <file xil_pn:name=\"../../cpu/alu/alu_select.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"35\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"35\"/>\n    </file>\n    <file xil_pn:name=\"../../cpu/alu/alu_flags.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"36\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"36\"/>\n    </file>\n    <file xil_pn:name=\"../../cpu/alu/alu_mux_2.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"12\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"12\"/>\n    </file>\n    <file xil_pn:name=\"../../cpu/alu/alu.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"38\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"38\"/>\n    </file>\n    <file xil_pn:name=\"../../cpu/alu/alu_core.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"13\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"13\"/>\n    </file>\n    <file xil_pn:name=\"../../cpu/alu/alu_slice.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"2\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"2\"/>\n    </file>\n    <file xil_pn:name=\"../../cpu/alu/alu_bit_select.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"14\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"14\"/>\n    </file>\n    <file xil_pn:name=\"../../cpu/alu/alu_shifter_core.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"6\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"6\"/>\n    </file>\n    <file xil_pn:name=\"../../cpu/alu/alu_mux_2z.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"11\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"11\"/>\n    </file>\n    <file xil_pn:name=\"../../cpu/alu/alu_mux_3z.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"10\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"10\"/>\n    </file>\n    <file xil_pn:name=\"../../cpu/alu/alu_prep_daa.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"7\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"7\"/>\n    </file>\n    <file xil_pn:name=\"../../cpu/registers/reg_file.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"15\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"15\"/>\n    </file>\n    <file xil_pn:name=\"../../cpu/registers/reg_control.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"16\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"16\"/>\n    </file>\n    <file xil_pn:name=\"../../cpu/registers/reg_latch.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"3\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"3\"/>\n    </file>\n    <file xil_pn:name=\"../../cpu/bus/address_latch.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"34\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"34\"/>\n    </file>\n    <file xil_pn:name=\"../../cpu/bus/address_mux.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"5\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"5\"/>\n    </file>\n    <file xil_pn:name=\"../../cpu/bus/bus_control.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"32\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"32\"/>\n    </file>\n    <file xil_pn:name=\"../../cpu/bus/bus_switch.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"31\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"31\"/>\n    </file>\n    <file xil_pn:name=\"../../cpu/bus/inc_dec.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"4\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"4\"/>\n    </file>\n    <file xil_pn:name=\"../../cpu/bus/data_switch.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"28\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"28\"/>\n    </file>\n    <file xil_pn:name=\"../../cpu/bus/inc_dec_2bit.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"1\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"1\"/>\n    </file>\n    <file xil_pn:name=\"../../cpu/bus/data_switch_mask.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"27\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"27\"/>\n    </file>\n    <file xil_pn:name=\"../../cpu/bus/address_pins.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"33\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"33\"/>\n    </file>\n    <file xil_pn:name=\"../../cpu/bus/data_pins.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"29\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"29\"/>\n    </file>\n    <file xil_pn:name=\"../../cpu/bus/control_pins_n.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"30\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"30\"/>\n    </file>\n    <file xil_pn:name=\"ipcore_dir/clock.xco\" xil_pn:type=\"FILE_COREGEN\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"41\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"41\"/>\n    </file>\n    <file xil_pn:name=\"Nexys3_master.ucf\" xil_pn:type=\"FILE_UCF\">\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"0\"/>\n    </file>\n    <file xil_pn:name=\"test_host.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"44\"/>\n      <association xil_pn:name=\"PostMapSimulation\" xil_pn:seqID=\"76\"/>\n      <association xil_pn:name=\"PostRouteSimulation\" xil_pn:seqID=\"76\"/>\n      <association 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<property xil_pn:name=\"Ignore Version Check\" xil_pn:value=\"false\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"Implementation Top\" xil_pn:value=\"Module|host\" xil_pn:valueState=\"non-default\"/>\n    <property xil_pn:name=\"Implementation Top File\" xil_pn:value=\"../basic_nexys3_fpga.v\" xil_pn:valueState=\"non-default\"/>\n    <property xil_pn:name=\"Implementation Top Instance Path\" xil_pn:value=\"/host\" xil_pn:valueState=\"non-default\"/>\n    <property xil_pn:name=\"Include 'uselib Directive in Verilog File\" xil_pn:value=\"false\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"Include SIMPRIM Models in Verilog File\" xil_pn:value=\"false\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"Include UNISIM Models in Verilog File\" xil_pn:value=\"false\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"Include sdf_annotate task in Verilog File\" xil_pn:value=\"true\" xil_pn:valueState=\"default\"/>\n    <property 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<property xil_pn:name=\"LUT Combining Xst\" xil_pn:value=\"Auto\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"Language\" xil_pn:value=\"VHDL\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"Last Applied Goal\" xil_pn:value=\"Minimum Runtime\" xil_pn:valueState=\"non-default\"/>\n    <property xil_pn:name=\"Last Applied Strategy\" xil_pn:value=\"Runtime Strategy 1;E:/Xilinx/14.7/ISE_DS/ISE/spartan6/data/spartan6_runtime.xds\" xil_pn:valueState=\"non-default\"/>\n    <property xil_pn:name=\"Last Unlock Status\" xil_pn:value=\"false\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"Launch SDK after Export\" xil_pn:value=\"true\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"Library for Verilog Sources\" xil_pn:value=\"\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"List window\" xil_pn:value=\"false\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"Load glbl\" xil_pn:value=\"true\" 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<property xil_pn:name=\"Post Place &amp; Route Simulation Model Name\" xil_pn:value=\"host_timesim.v\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"Post Synthesis Simulation Model Name\" xil_pn:value=\"host_synthesis.v\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"Post Translate Simulation Model Name\" xil_pn:value=\"host_translate.v\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"Power Reduction Map spartan6\" xil_pn:value=\"Off\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"Power Reduction Par\" xil_pn:value=\"false\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"Power Reduction Xst\" xil_pn:value=\"false\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"Preferred Language\" xil_pn:value=\"Verilog\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"Process window\" xil_pn:value=\"false\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"Produce Verbose Report\" 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xil_pn:value=\"E:/Xilinx/14.7/ISE_DS/ISE/spartan6/data/spartan6_runtime.xds\" xil_pn:valueState=\"non-default\"/>\n    <property xil_pn:name=\"UserID Code (8 Digit Hexadecimal)\" xil_pn:value=\"0xFFFFFFFF\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"VCCAUX Voltage Level spartan6\" xil_pn:value=\"2.5V\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"VHDL Source Analysis Standard\" xil_pn:value=\"VHDL-93\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"VHDL Syntax\" xil_pn:value=\"93\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"Value Range Check\" xil_pn:value=\"false\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"Variables window\" xil_pn:value=\"false\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"Verilog Macros\" xil_pn:value=\"\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"Wait for DCM and PLL Lock (Output Events) spartan6\" xil_pn:value=\"Default (NoWait)\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"Wakeup Clock spartan6\" xil_pn:value=\"Startup Clock\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"Watchdog Timer Value spartan6\" xil_pn:value=\"0xFFFF\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"Wave window\" xil_pn:value=\"true\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"Working Directory\" xil_pn:value=\"work\" xil_pn:valueState=\"non-default\"/>\n    <property xil_pn:name=\"Write Timing Constraints\" xil_pn:value=\"false\" xil_pn:valueState=\"default\"/>\n    <!--                                                                                  -->\n    <!-- The following properties are for internal use only. These should not be modified.-->\n    <!--                                                                                  -->\n    <property xil_pn:name=\"PROP_BehavioralSimTop\" xil_pn:value=\"Module|test_host\" xil_pn:valueState=\"non-default\"/>\n    <property xil_pn:name=\"PROP_DesignName\" xil_pn:value=\"host\" xil_pn:valueState=\"non-default\"/>\n    <property xil_pn:name=\"PROP_DevFamilyPMName\" xil_pn:value=\"spartan6\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"PROP_FPGAConfiguration\" xil_pn:value=\"FPGAConfiguration\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"PROP_PostMapSimTop\" xil_pn:value=\"\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"PROP_PostParSimTop\" xil_pn:value=\"\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"PROP_PostSynthSimTop\" xil_pn:value=\"\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"PROP_PostXlateSimTop\" xil_pn:value=\"\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"PROP_PreSynthesis\" xil_pn:value=\"PreSynthesis\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"PROP_intProjectCreationTimestamp\" xil_pn:value=\"2016-02-10T11:01:37\" xil_pn:valueState=\"non-default\"/>\n    <property xil_pn:name=\"PROP_intWbtProjectID\" xil_pn:value=\"3027F024D290423D81D3236EFC90CCC8\" xil_pn:valueState=\"non-default\"/>\n    <property xil_pn:name=\"PROP_intWorkingDirLocWRTProjDir\" xil_pn:value=\"UnderProjDir\" xil_pn:valueState=\"non-default\"/>\n    <property xil_pn:name=\"PROP_intWorkingDirUsed\" xil_pn:value=\"Yes\" xil_pn:valueState=\"non-default\"/>\n  </properties>\n\n  <bindings/>\n\n  <libraries/>\n\n  <autoManagedFiles>\n    <!-- The following files are identified by `include statements in verilog -->\n    <!-- source files and are automatically managed by Project Navigator.     -->\n    <!--                                                                      -->\n    <!-- Do not hand-edit this section, as it will be overwritten when the    -->\n    <!-- project is analyzed based on files automatically identified as       -->\n    <!-- include files.                                                       -->\n    <file xil_pn:name=\"../../cpu/control/exec_module.vh\" xil_pn:type=\"FILE_VERILOG\"/>\n    <file xil_pn:name=\"../../cpu/control/temp_wires.vh\" xil_pn:type=\"FILE_VERILOG\"/>\n    <file xil_pn:name=\"../../cpu/control/exec_zero.vh\" xil_pn:type=\"FILE_VERILOG\"/>\n    <file xil_pn:name=\"../../cpu/control/exec_matrix_compiled.vh\" xil_pn:type=\"FILE_VERILOG\"/>\n    <file xil_pn:name=\"../../cpu/toplevel/core.vh\" xil_pn:type=\"FILE_VERILOG\"/>\n    <file xil_pn:name=\"../../cpu/toplevel/globals.vh\" xil_pn:type=\"FILE_VERILOG\"/>\n    <file xil_pn:name=\"../../cpu/toplevel/coremodules.vh\" xil_pn:type=\"FILE_VERILOG\"/>\n  </autoManagedFiles>\n\n</project>\n"
  },
  {
    "path": "host/basic_nexys3/basic_nexys3_fpga.v",
    "content": "//============================================================================\n// Host design containing A-Z80 and a few peripherials\n//\n// This module defines a host board to be run on an FPGA.\n//\n//  Copyright (C) 2016  Goran Devic\n//\n//  This program is free software; you can redistribute it and/or modify it\n//  under the terms of the GNU General Public License as published by the Free\n//  Software Foundation; either version 2 of the License, or (at your option)\n//  any later version.\n//\n//  This program is distributed in the hope that it will be useful, but WITHOUT\n//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n//  more details.\n//\n//  You should have received a copy of the GNU General Public License along\n//  with this program; if not, write to the Free Software Foundation, Inc.,\n//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n//============================================================================\nmodule host\n(\n    input wire CLOCK_100,\n    input wire KEY0,            // KEY0 is reset\n    input wire KEY1,            // KEY1 generates a maskable interrupt (INT)\n    input wire KEY2,            // KEY2 generates a non-maskable interrupt (NMI)\n    output wire UART_TXD,\n\n    inout wire [7:0] GPIO_0,    // Test points\n    output wire [7:0] GPIO_1,\n    output wire [7:0] GPIO_2,\n    inout wire [7:0] GPIO_3\n);\n`default_nettype none\n\n// Export selected pins to the extension connector\nassign GPIO_0[7:0] = A[7:0];\nassign GPIO_1[7:0] = A[15:8];\nassign GPIO_2[7:0] = D[7:0];\nassign GPIO_3 = {reset, uart_tx, nM1, nMREQ, nRFSH, nHALT, nBUSACK};\n\n// Basic wires and the reset logic\nwire uart_tx;\nwire reset;\nwire locked;\n\nassign reset = locked & ~KEY0;\nassign UART_TXD = uart_tx;\n\n// ----------------- CPU PINS -----------------\nwire nM1;\nwire nMREQ;\nwire nIORQ;\nwire nRD;\nwire nWR;\nwire nRFSH;\nwire nHALT;\nwire nBUSACK;\n\nwire nWAIT = 1;\nwire nBUSRQ = 1;\nwire nINT = ~KEY1;\nwire nNMI = ~KEY2;\n\nwire [15:0] A;\nreg [7:0] D /* synthesis keep */;\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// Instantiate PLL\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nwire pll_clk;\nwire clk_uart; // 50MHz clock for UART\n\nclock pll ( .CLK_IN1(CLOCK_100), .CLK_OUT1(pll_clk), .CLK_OUT2(clk_uart), .LOCKED(locked) );\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// Clocks\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nwire clk_cpu = pll_clk; // CPU clock == PLL1 clock\n\n// Test code: Divide pll clock with a power of 2 to reduce effective CPU clock\n// reg [0:0] counter = 0;\n// always @(posedge pll_clk)\n// begin\n//     if (counter==1'b0)\n//         clk_cpu <= ~clk_cpu;\n//     counter <= counter - 1'b1;\n// end\n\n// ----------------- INTERNAL WIRES -----------------\nwire [7:0] RamData; // Data writer from the RAM module\nwire [7:0] CpuData;\nassign CpuData = nRD==0 ? D[7:0] : {nIORQ,nRD,nWR}==3'b011 ? 8'h80 : {8{1'bz}};\n\nwire RamWE;\nassign RamWE = nIORQ==1 && nRD==1 && nWR==0;\n\nwire uart_busy;\nwire UartWE;\nassign UartWE = nIORQ==0 && nRD==1 && nWR==0;\n\n// Memory map:\n//   0000 - 3FFF  16Kb RAM\nalways @(*) // always_comb\nbegin\n    case ({nIORQ,nRD,nWR})\n        // -------------------------------- Memory read --------------------------------\n        3'b101: D[7:0] = RamData;\n        // -------------------------------- Memory write -------------------------------\n        3'b110: D[7:0] = CpuData;\n        // ---------------------------------- IO write ---------------------------------\n        3'b010: D[7:0] = CpuData;\n        // ---------------------------------- IO read ----------------------------------\n        3'b001: D[7:0] = {7'b0000000, uart_busy};\n        // IO read *** Interrupts test ***\n        // This value will be pushed on the data bus on an IORQ access which\n        // means that:\n        // In IM0: this is the opcode of an instruction to execute, set it to 0xFF\n        // In IM2: this is a vector, set it to 0x80 (to correspond to a test program Hello World)\n        3'b011: D[7:0] = 8'h80;\n    default:\n        D[7:0] = {8{1'bz}};\n    endcase\nend\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// Instantiate A-Z80 CPU module\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nz80_top_direct_n z80_(\n    .nM1 (nM1),\n    .nMREQ (nMREQ),\n    .nIORQ (nIORQ),\n    .nRD (nRD),\n    .nWR (nWR),\n    .nRFSH (nRFSH),\n    .nHALT (nHALT),\n    .nBUSACK (nBUSACK),\n\n    .nWAIT (nWAIT),\n    .nINT (nINT),\n    .nNMI (nNMI),\n    .nRESET (reset),\n    .nBUSRQ (nBUSRQ),\n\n    .CLK (clk_cpu),\n    .A (A),\n    .D (CpuData)\n);\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// Instantiate 16K of RAM memory\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nram #( .n(14)) ram_(\n    .addr(A[13:0]),\n    .clk(clk_cpu),\n    .data_in(D),\n    .we(RamWE),\n    .data_out(RamData)\n);\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// Instantiate UART module\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nuart #( .BAUD(115200), .IN_CLOCK(50000000) ) uart_(\n   // Outputs\n   .busy(uart_busy),\n   .uart_tx(uart_tx),\n   // Inputs\n   .wr(UartWE),\n   .data(D),\n   .clk(clk_uart),\n   .reset(!reset)\n);\n\nendmodule\n"
  },
  {
    "path": "host/basic_nexys3/cscope.cdc",
    "content": "#ChipScope Core Inserter Project File Version 3.0\n#Sat Mar 05 11:38:40 CST 2016\nProject.device.designInputFile=R\\:\\\\Z80\\\\host\\\\basic_nexys3\\\\work\\\\host_cs.ngc\nProject.device.designOutputFile=R\\:\\\\Z80\\\\host\\\\basic_nexys3\\\\work\\\\host_cs.ngc\nProject.device.deviceFamily=18\nProject.device.enableRPMs=true\nProject.device.outputDirectory=R\\:\\\\Z80\\\\host\\\\basic_nexys3\\\\work\\\\_ngo\nProject.device.useSRL16=true\nProject.filter.dimension=19\nProject.filter<0>=\nProject.filter<10>=*d*\nProject.filter<11>=*sw*\nProject.filter<12>=*4u*\nProject.filter<13>=*db2*\nProject.filter<14>=*db1*\nProject.filter<15>=*db0*\nProject.filter<16>=*rfsh*\nProject.filter<17>=*M1*\nProject.filter<18>=m1\nProject.filter<1>=bus_*\nProject.filter<2>=GPIO_1*\nProject.filter<3>=GPIO_0*\nProject.filter<4>=*T*\nProject.filter<5>=T*\nProject.filter<6>=*ctl_reg*\nProject.filter<7>=ctl_reg*\nProject.filter<8>=GPIO_2*\nProject.filter<9>=*D*\nProject.icon.boundaryScanChain=1\nProject.icon.enableExtTriggerIn=false\nProject.icon.enableExtTriggerOut=false\nProject.icon.triggerInPinName=\nProject.icon.triggerOutPinName=\nProject.unit.dimension=1\nProject.unit<0>.clockChannel=clk_cpu\nProject.unit<0>.clockEdge=Rising\nProject.unit<0>.dataChannel<0>=GPIO_0_0_OBUF\nProject.unit<0>.dataChannel<10>=GPIO_2_0_OBUFT\nProject.unit<0>.dataChannel<11>=GPIO_2_1_OBUFT\nProject.unit<0>.dataChannel<12>=GPIO_2_2_OBUFT\nProject.unit<0>.dataChannel<13>=GPIO_2_3_OBUFT\nProject.unit<0>.dataChannel<14>=GPIO_2_4_OBUFT\nProject.unit<0>.dataChannel<15>=GPIO_2_5_OBUFT\nProject.unit<0>.dataChannel<16>=GPIO_2_6_OBUFT\nProject.unit<0>.dataChannel<17>=GPIO_2_7_OBUFT\nProject.unit<0>.dataChannel<18>=z80_/ir_ opcode<0>\nProject.unit<0>.dataChannel<19>=z80_/ir_ opcode<1>\nProject.unit<0>.dataChannel<1>=GPIO_0_1_OBUF\nProject.unit<0>.dataChannel<20>=z80_/ir_ opcode<2>\nProject.unit<0>.dataChannel<21>=z80_/ir_ opcode<3>\nProject.unit<0>.dataChannel<22>=z80_/ir_ opcode<4>\nProject.unit<0>.dataChannel<23>=z80_/ir_ opcode<5>\nProject.unit<0>.dataChannel<24>=z80_/ir_ opcode<6>\nProject.unit<0>.dataChannel<25>=z80_/ir_ opcode<7>\nProject.unit<0>.dataChannel<26>=nRD\nProject.unit<0>.dataChannel<27>=nWR\nProject.unit<0>.dataChannel<28>=z80_/nM1_out\nProject.unit<0>.dataChannel<29>=z80_/nRFSH_out\nProject.unit<0>.dataChannel<2>=GPIO_0_2_OBUF\nProject.unit<0>.dataChannel<30>=z80_/db0<0>\nProject.unit<0>.dataChannel<31>=z80_/db0<1>\nProject.unit<0>.dataChannel<32>=z80_/db1<0>\nProject.unit<0>.dataChannel<33>=z80_/db1<1>\nProject.unit<0>.dataChannel<34>=z80_/db2<0>\nProject.unit<0>.dataChannel<35>=z80_/db2<1>\nProject.unit<0>.dataChannel<36>=z80_/ctl_reg_out_hi\nProject.unit<0>.dataChannel<37>=z80_/ctl_reg_out_lo\nProject.unit<0>.dataChannel<38>=z80_/ctl_sw_4u\nProject.unit<0>.dataChannel<39>=z80_/ctl_sw_4d\nProject.unit<0>.dataChannel<3>=GPIO_0_3_OBUF\nProject.unit<0>.dataChannel<40>=z80_/ctl_reg_in_lo\nProject.unit<0>.dataChannel<41>=z80_/ctl_reg_in_hi\nProject.unit<0>.dataChannel<42>=z80_/sequencer_ DFFE_T1_ff\nProject.unit<0>.dataChannel<43>=z80_/sequencer_ DFFE_T2_ff\nProject.unit<0>.dataChannel<44>=z80_/sequencer_ DFFE_T3_ff\nProject.unit<0>.dataChannel<45>=z80_/sequencer_ DFFE_T4_ff\nProject.unit<0>.dataChannel<46>=z80_/sequencer_ DFFE_T5_ff\nProject.unit<0>.dataChannel<47>=z80_/pin_control_ bus_db_pin_re\nProject.unit<0>.dataChannel<48>=z80_/pin_control_ bus_ab_pin_we\nProject.unit<0>.dataChannel<49>=z80_/pin_control_ bus_db_pin_oe\nProject.unit<0>.dataChannel<4>=GPIO_0_4_OBUF\nProject.unit<0>.dataChannel<5>=GPIO_0_5_OBUF\nProject.unit<0>.dataChannel<6>=GPIO_0_6_OBUF\nProject.unit<0>.dataChannel<7>=GPIO_0_7_OBUF\nProject.unit<0>.dataChannel<8>=GPIO_1_0_OBUF\nProject.unit<0>.dataChannel<9>=GPIO_1_1_OBUF\nProject.unit<0>.dataDepth=1024\nProject.unit<0>.dataEqualsTrigger=false\nProject.unit<0>.dataPortWidth=50\nProject.unit<0>.enableGaps=false\nProject.unit<0>.enableStorageQualification=true\nProject.unit<0>.enableTimestamps=false\nProject.unit<0>.timestampDepth=0\nProject.unit<0>.timestampWidth=0\nProject.unit<0>.triggerChannel<0><0>=z80_/nreset\nProject.unit<0>.triggerConditionCountWidth=0\nProject.unit<0>.triggerMatchCount<0>=1\nProject.unit<0>.triggerMatchCountWidth<0><0>=0\nProject.unit<0>.triggerMatchType<0><0>=5\nProject.unit<0>.triggerPortCount=1\nProject.unit<0>.triggerPortIsData<0>=true\nProject.unit<0>.triggerPortWidth<0>=1\nProject.unit<0>.triggerSequencerLevels=16\nProject.unit<0>.triggerSequencerType=1\nProject.unit<0>.type=ilapro\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock/example_design/clock_exdes.ucf",
    "content": "# file: clock_exdes.ucf\n# \n# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\n# \n# This file contains confidential and proprietary information\n# of Xilinx, Inc. and is protected under U.S. and\n# international copyright and other intellectual property\n# laws.\n# \n# DISCLAIMER\n# This disclaimer is not a license and does not grant any\n# rights to the materials distributed herewith. Except as\n# otherwise provided in a valid license issued to you by\n# Xilinx, and to the maximum extent permitted by applicable\n# law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n# (2) Xilinx shall not be liable (whether in contract or tort,\n# including negligence, or under any other theory of\n# liability) for any loss or damage of any kind or nature\n# related to, arising under or in connection with these\n# materials, including for any direct, or any indirect,\n# special, incidental, or consequential loss or damage\n# (including loss of data, profits, goodwill, or any type of\n# loss or damage suffered as a result of any action brought\n# by a third party) even if such damage or loss was\n# reasonably foreseeable or Xilinx had been advised of the\n# possibility of the same.\n# \n# CRITICAL APPLICATIONS\n# Xilinx products are not designed or intended to be fail-\n# safe, or for use in any application requiring fail-safe\n# performance, such as life-support or safety devices or\n# systems, Class III medical devices, nuclear facilities,\n# applications related to the deployment of airbags, or any\n# other applications that could lead to death, personal\n# injury, or severe property or environmental damage\n# (individually and collectively, \"Critical\n# Applications\"). Customer assumes the sole risk and\n# liability of any use of Xilinx products in Critical\n# Applications, subject only to applicable laws and\n# regulations governing limitations on product liability.\n# \n# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n# PART OF THIS FILE AT ALL TIMES.\n# \n\n# Input clock periods. These duplicate the values entered for the\n#  input clocks. You can use these to time your system\n#----------------------------------------------------------------\nNET \"CLK_IN1\" TNM_NET = \"CLK_IN1\";\nTIMESPEC \"TS_CLK_IN1\" = PERIOD \"CLK_IN1\" 10.0 ns HIGH 50% INPUT_JITTER 100.0ps;\n\n\n# FALSE PATH constraints \nPIN \"COUNTER_RESET\" TIG;\n\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock/example_design/clock_exdes.v",
    "content": "// file: clock_exdes.v\n// \n// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n\n//----------------------------------------------------------------------------\n// Clocking wizard example design\n//----------------------------------------------------------------------------\n// This example design instantiates the created clocking network, where each\n//   output clock drives a counter. The high bit of each counter is ported.\n//----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\nmodule clock_exdes \n #( \n  parameter TCQ = 100\n  )\n (// Clock in ports\n  input         CLK_IN1,\n  // Reset that only drives logic in example design\n  input         COUNTER_RESET,\n  output [2:1]  CLK_OUT,\n  // High bits of counters driven by clocks\n  output [2:1]  COUNT,\n  // Status and control signals\n  output        LOCKED\n );\n\n  // Parameters for the counters\n  //-------------------------------\n  // Counter width\n  localparam    C_W       = 16;\n  localparam    NUM_C     = 2;\n  genvar        count_gen;\n  // When the clock goes out of lock, reset the counters\n  wire          reset_int = !LOCKED || COUNTER_RESET;\n\n   reg [NUM_C:1] rst_sync;\n   reg [NUM_C:1] rst_sync_int;\n   reg [NUM_C:1] rst_sync_int1;\n   reg [NUM_C:1] rst_sync_int2;\n\n\n  // Declare the clocks and counters\n  wire [NUM_C:1] clk_int;\n  wire [NUM_C:1] clk_n;\n  wire [NUM_C:1] clk;\n  reg [C_W-1:0]  counter [NUM_C:1];\n\n  // Instantiation of the clocking network\n  //--------------------------------------\n  clock clknetwork\n   (// Clock in ports\n    .CLK_IN1            (CLK_IN1),\n    // Clock out ports\n    .CLK_OUT1           (clk_int[1]),\n    .CLK_OUT2           (clk_int[2]),\n    // Status and control signals\n    .LOCKED             (LOCKED));\n\ngenvar clk_out_pins;\n\ngenerate \n  for (clk_out_pins = 1; clk_out_pins <= NUM_C; clk_out_pins = clk_out_pins + 1) \n  begin: gen_outclk_oddr\n  assign clk_n[clk_out_pins] = ~clk[clk_out_pins];\n\n  ODDR2 clkout_oddr\n   (.Q  (CLK_OUT[clk_out_pins]),\n    .C0 (clk[clk_out_pins]),\n    .C1 (clk_n[clk_out_pins]),\n    .CE (1'b1),\n    .D0 (1'b1),\n    .D1 (1'b0),\n    .R  (1'b0),\n    .S  (1'b0));\n  end\nendgenerate\n\n  // Connect the output clocks to the design\n  //-----------------------------------------\n  assign clk[1] = clk_int[1];\n  assign clk[2] = clk_int[2];\n\n\n  // Reset synchronizer\n  //-----------------------------------\n  generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters_1\n    always @(posedge reset_int or posedge clk[count_gen]) begin\n       if (reset_int) begin\n            rst_sync[count_gen] <= 1'b1;\n            rst_sync_int[count_gen]<= 1'b1;\n            rst_sync_int1[count_gen]<= 1'b1;\n            rst_sync_int2[count_gen]<= 1'b1;\n       end\n       else begin\n            rst_sync[count_gen] <= 1'b0;\n            rst_sync_int[count_gen] <= rst_sync[count_gen];     \n            rst_sync_int1[count_gen] <= rst_sync_int[count_gen]; \n            rst_sync_int2[count_gen] <= rst_sync_int1[count_gen];\n       end\n    end\n  end\n  endgenerate\n\n\n  // Output clock sampling\n  //-----------------------------------\n  generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters\n\n    always @(posedge clk[count_gen] or posedge rst_sync_int2[count_gen]) begin\n      if (rst_sync_int2[count_gen]) begin\n        counter[count_gen] <= #TCQ { C_W { 1'b 0 } };\n      end else begin\n        counter[count_gen] <= #TCQ counter[count_gen] + 1'b 1;\n      end\n    end\n    // alias the high bit of each counter to the corresponding\n    //   bit in the output bus\n    assign COUNT[count_gen] = counter[count_gen][C_W-1];\n  end\n  endgenerate\n\n\n\n\n\nendmodule\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock/example_design/clock_exdes.xdc",
    "content": "# file: clock_exdes.xdc\n# \n# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\n# \n# This file contains confidential and proprietary information\n# of Xilinx, Inc. and is protected under U.S. and\n# international copyright and other intellectual property\n# laws.\n# \n# DISCLAIMER\n# This disclaimer is not a license and does not grant any\n# rights to the materials distributed herewith. Except as\n# otherwise provided in a valid license issued to you by\n# Xilinx, and to the maximum extent permitted by applicable\n# law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n# (2) Xilinx shall not be liable (whether in contract or tort,\n# including negligence, or under any other theory of\n# liability) for any loss or damage of any kind or nature\n# related to, arising under or in connection with these\n# materials, including for any direct, or any indirect,\n# special, incidental, or consequential loss or damage\n# (including loss of data, profits, goodwill, or any type of\n# loss or damage suffered as a result of any action brought\n# by a third party) even if such damage or loss was\n# reasonably foreseeable or Xilinx had been advised of the\n# possibility of the same.\n# \n# CRITICAL APPLICATIONS\n# Xilinx products are not designed or intended to be fail-\n# safe, or for use in any application requiring fail-safe\n# performance, such as life-support or safety devices or\n# systems, Class III medical devices, nuclear facilities,\n# applications related to the deployment of airbags, or any\n# other applications that could lead to death, personal\n# injury, or severe property or environmental damage\n# (individually and collectively, \"Critical\n# Applications\"). Customer assumes the sole risk and\n# liability of any use of Xilinx products in Critical\n# Applications, subject only to applicable laws and\n# regulations governing limitations on product liability.\n# \n# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n# PART OF THIS FILE AT ALL TIMES.\n# \n\n# Input clock periods. These duplicate the values entered for the\n#  input clocks. You can use these to time your system\n#----------------------------------------------------------------\ncreate_clock -name CLK_IN1 -period 10.0 [get_ports CLK_IN1]\nset_propagated_clock CLK_IN1\nset_input_jitter CLK_IN1 0.1\n\n# FALSE PATH constraint added on COUNTER_RESET \nset_false_path -from [get_ports \"COUNTER_RESET\"]\n\n# Derived clock periods. These are commented out because they are \n#   automatically propogated by the tools\n# However, if you'd like to use them for module level testing, you \n#   can copy them into your module level timing checks\n#-----------------------------------------------------------------\n\n#-----------------------------------------------------------------\n\n#-----------------------------------------------------------------\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock/implement/implement.bat",
    "content": "REM file: implement.bat\nREM \nREM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\nREM \nREM This file contains confidential and proprietary information\nREM of Xilinx, Inc. and is protected under U.S. and\nREM international copyright and other intellectual property\nREM laws.\nREM \nREM DISCLAIMER\nREM This disclaimer is not a license and does not grant any\nREM rights to the materials distributed herewith. Except as\nREM otherwise provided in a valid license issued to you by\nREM Xilinx, and to the maximum extent permitted by applicable\nREM law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\nREM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\nREM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\nREM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\nREM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\nREM (2) Xilinx shall not be liable (whether in contract or tort,\nREM including negligence, or under any other theory of\nREM liability) for any loss or damage of any kind or nature\nREM related to, arising under or in connection with these\nREM materials, including for any direct, or any indirect,\nREM special, incidental, or consequential loss or damage\nREM (including loss of data, profits, goodwill, or any type of\nREM loss or damage suffered as a result of any action brought\nREM by a third party) even if such damage or loss was\nREM reasonably foreseeable or Xilinx had been advised of the\nREM possibility of the same.\nREM \nREM CRITICAL APPLICATIONS\nREM Xilinx products are not designed or intended to be fail-\nREM safe, or for use in any application requiring fail-safe\nREM performance, such as life-support or safety devices or\nREM systems, Class III medical devices, nuclear facilities,\nREM applications related to the deployment of airbags, or any\nREM other applications that could lead to death, personal\nREM injury, or severe property or environmental damage\nREM (individually and collectively, \"Critical\nREM Applications\"). Customer assumes the sole risk and\nREM liability of any use of Xilinx products in Critical\nREM Applications, subject only to applicable laws and\nREM regulations governing limitations on product liability.\nREM \nREM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\nREM PART OF THIS FILE AT ALL TIMES.\nREM \n\nREM -----------------------------------------------------------------------------\nREM  Script to synthesize and implement the RTL provided for the clocking wizard\nREM -----------------------------------------------------------------------------\n\nREM Clean up the results directory\nrmdir /S /Q results\nmkdir results\n\nREM Copy unisim_comp.v file to results directory\ncopy %XILINX%\\verilog\\src\\iSE\\unisim_comp.v .\\results\\\n\nREM Synthesize the Verilog Wrapper Files\necho 'Synthesizing Clocking Wizard design with XST'\nxst -ifn xst.scr\nmove clock_exdes.ngc results\\\n\nREM  Copy the constraints files generated by Coregen\necho 'Copying files from constraints directory to results directory'\ncopy ..\\example_design\\clock_exdes.ucf results\\\n\ncd results\n\necho 'Running ngdbuild'\nngdbuild -uc clock_exdes.ucf clock_exdes\n\necho 'Running map'\nmap -timing -pr b clock_exdes -o mapped.ncd\n\necho 'Running par'\npar -w mapped.ncd routed mapped.pcf\n\necho 'Running trce'\ntrce -e 10 routed -o routed mapped.pcf\n\necho 'Running design through bitgen'\nbitgen -w routed\n\necho 'Running netgen to create gate level model for the clocking wizard example design'\nnetgen -ofmt verilog -sim -sdf_anno false -tm clock_exdes -w routed.ncd routed.v\ncd ..\n\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock/implement/implement.sh",
    "content": "#!/bin/sh\n# file: implement.sh\n# \n# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\n# \n# This file contains confidential and proprietary information\n# of Xilinx, Inc. and is protected under U.S. and\n# international copyright and other intellectual property\n# laws.\n# \n# DISCLAIMER\n# This disclaimer is not a license and does not grant any\n# rights to the materials distributed herewith. Except as\n# otherwise provided in a valid license issued to you by\n# Xilinx, and to the maximum extent permitted by applicable\n# law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n# (2) Xilinx shall not be liable (whether in contract or tort,\n# including negligence, or under any other theory of\n# liability) for any loss or damage of any kind or nature\n# related to, arising under or in connection with these\n# materials, including for any direct, or any indirect,\n# special, incidental, or consequential loss or damage\n# (including loss of data, profits, goodwill, or any type of\n# loss or damage suffered as a result of any action brought\n# by a third party) even if such damage or loss was\n# reasonably foreseeable or Xilinx had been advised of the\n# possibility of the same.\n# \n# CRITICAL APPLICATIONS\n# Xilinx products are not designed or intended to be fail-\n# safe, or for use in any application requiring fail-safe\n# performance, such as life-support or safety devices or\n# systems, Class III medical devices, nuclear facilities,\n# applications related to the deployment of airbags, or any\n# other applications that could lead to death, personal\n# injury, or severe property or environmental damage\n# (individually and collectively, \"Critical\n# Applications\"). Customer assumes the sole risk and\n# liability of any use of Xilinx products in Critical\n# Applications, subject only to applicable laws and\n# regulations governing limitations on product liability.\n# \n# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n# PART OF THIS FILE AT ALL TIMES.\n# \n\n#-----------------------------------------------------------------------------\n# Script to synthesize and implement the RTL provided for the clocking wizard\n#-----------------------------------------------------------------------------\n\n# Clean up the results directory\nrm -rf results\nmkdir results\n\n# Copy unisim_comp.v file to results directory\ncp $XILINX/verilog/src/iSE/unisim_comp.v ./results/\n\n# Synthesize the Verilog Wrapper Files\necho 'Synthesizing Clocking Wizard design with XST'\nxst -ifn xst.scr\nmv clock_exdes.ngc results/\n\n#  Copy the constraints files generated by Coregen\necho 'Copying files from constraints directory to results directory'\ncp ../example_design/clock_exdes.ucf results/\n\ncd results\n\necho 'Running ngdbuild'\nngdbuild -uc clock_exdes.ucf clock_exdes\n\necho 'Running map'\nmap -timing clock_exdes -o mapped.ncd\n\necho 'Running par'\npar -w mapped.ncd routed mapped.pcf\n\necho 'Running trce'\ntrce -e 10 routed -o routed mapped.pcf\n\necho 'Running design through bitgen'\nbitgen -w routed\n\necho 'Running netgen to create gate level model for the clocking wizard example design'\nnetgen -ofmt verilog -sim -sdf_anno false -tm clock_exdes -w routed.ncd routed.v\n\ncd ..\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock/implement/planAhead_ise.bat",
    "content": "REM file: planAhead_ise.bat\nREM \nREM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\nREM \nREM This file contains confidential and proprietary information\nREM of Xilinx, Inc. and is protected under U.S. and\nREM international copyright and other intellectual property\nREM laws.\nREM \nREM DISCLAIMER\nREM This disclaimer is not a license and does not grant any\nREM rights to the materials distributed herewith. Except as\nREM otherwise provided in a valid license issued to you by\nREM Xilinx, and to the maximum extent permitted by applicable\nREM law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\nREM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\nREM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\nREM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\nREM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\nREM (2) Xilinx shall not be liable (whether in contract or tort,\nREM including negligence, or under any other theory of\nREM liability) for any loss or damage of any kind or nature\nREM related to, arising under or in connection with these\nREM materials, including for any direct, or any indirect,\nREM special, incidental, or consequential loss or damage\nREM (including loss of data, profits, goodwill, or any type of\nREM loss or damage suffered as a result of any action brought\nREM by a third party) even if such damage or loss was\nREM reasonably foreseeable or Xilinx had been advised of the\nREM possibility of the same.\nREM \nREM CRITICAL APPLICATIONS\nREM Xilinx products are not designed or intended to be fail-\nREM safe, or for use in any application requiring fail-safe\nREM performance, such as life-support or safety devices or\nREM systems, Class III medical devices, nuclear facilities,\nREM applications related to the deployment of airbags, or any\nREM other applications that could lead to death, personal\nREM injury, or severe property or environmental damage\nREM (individually and collectively, \"Critical\nREM Applications\"). Customer assumes the sole risk and\nREM liability of any use of Xilinx products in Critical\nREM Applications, subject only to applicable laws and\nREM regulations governing limitations on product liability.\nREM \nREM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\nREM PART OF THIS FILE AT ALL TIMES.\nREM \n\nREM-----------------------------------------------------------------------------\nREM Script to synthesize and implement the RTL provided for the clocking wizard\nREM-----------------------------------------------------------------------------\n\ndel \\f results\nmkdir results\ncd results\n\nplanAhead -mode batch -source ..\\planAhead_ise.tcl\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock/implement/planAhead_ise.sh",
    "content": "#!/bin/sh\n# file: planAhead_ise.sh\n# \n# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\n# \n# This file contains confidential and proprietary information\n# of Xilinx, Inc. and is protected under U.S. and\n# international copyright and other intellectual property\n# laws.\n# \n# DISCLAIMER\n# This disclaimer is not a license and does not grant any\n# rights to the materials distributed herewith. Except as\n# otherwise provided in a valid license issued to you by\n# Xilinx, and to the maximum extent permitted by applicable\n# law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n# (2) Xilinx shall not be liable (whether in contract or tort,\n# including negligence, or under any other theory of\n# liability) for any loss or damage of any kind or nature\n# related to, arising under or in connection with these\n# materials, including for any direct, or any indirect,\n# special, incidental, or consequential loss or damage\n# (including loss of data, profits, goodwill, or any type of\n# loss or damage suffered as a result of any action brought\n# by a third party) even if such damage or loss was\n# reasonably foreseeable or Xilinx had been advised of the\n# possibility of the same.\n# \n# CRITICAL APPLICATIONS\n# Xilinx products are not designed or intended to be fail-\n# safe, or for use in any application requiring fail-safe\n# performance, such as life-support or safety devices or\n# systems, Class III medical devices, nuclear facilities,\n# applications related to the deployment of airbags, or any\n# other applications that could lead to death, personal\n# injury, or severe property or environmental damage\n# (individually and collectively, \"Critical\n# Applications\"). Customer assumes the sole risk and\n# liability of any use of Xilinx products in Critical\n# Applications, subject only to applicable laws and\n# regulations governing limitations on product liability.\n# \n# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n# PART OF THIS FILE AT ALL TIMES.\n# \n\n#-----------------------------------------------------------------------------\n# Script to synthesize and implement the RTL provided for the clocking wizard\n#-----------------------------------------------------------------------------\n\nrm -rf results\nmkdir results\ncd results\n\nplanAhead -mode batch -source ../planAhead_ise.tcl\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock/implement/planAhead_ise.tcl",
    "content": "# file: planAhead_ise.tcl\n# \n# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\n# \n# This file contains confidential and proprietary information\n# of Xilinx, Inc. and is protected under U.S. and\n# international copyright and other intellectual property\n# laws.\n# \n# DISCLAIMER\n# This disclaimer is not a license and does not grant any\n# rights to the materials distributed herewith. Except as\n# otherwise provided in a valid license issued to you by\n# Xilinx, and to the maximum extent permitted by applicable\n# law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n# (2) Xilinx shall not be liable (whether in contract or tort,\n# including negligence, or under any other theory of\n# liability) for any loss or damage of any kind or nature\n# related to, arising under or in connection with these\n# materials, including for any direct, or any indirect,\n# special, incidental, or consequential loss or damage\n# (including loss of data, profits, goodwill, or any type of\n# loss or damage suffered as a result of any action brought\n# by a third party) even if such damage or loss was\n# reasonably foreseeable or Xilinx had been advised of the\n# possibility of the same.\n# \n# CRITICAL APPLICATIONS\n# Xilinx products are not designed or intended to be fail-\n# safe, or for use in any application requiring fail-safe\n# performance, such as life-support or safety devices or\n# systems, Class III medical devices, nuclear facilities,\n# applications related to the deployment of airbags, or any\n# other applications that could lead to death, personal\n# injury, or severe property or environmental damage\n# (individually and collectively, \"Critical\n# Applications\"). Customer assumes the sole risk and\n# liability of any use of Xilinx products in Critical\n# Applications, subject only to applicable laws and\n# regulations governing limitations on product liability.\n# \n# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n# PART OF THIS FILE AT ALL TIMES.\n# \n\nset projDir [file dirname [info script]]\nset projName clock\nset topName clock_exdes\nset device xc6slx16csg324-2\n\ncreate_project $projName $projDir/results/$projName -part $device\n\nset_property design_mode RTL [get_filesets sources_1]\n\n## Source files\n#set verilogSources [glob $srcDir/*.v]\nimport_files -fileset [get_filesets sources_1] -force -norecurse ../../example_design/clock_exdes.v\nimport_files -fileset [get_filesets sources_1] -force -norecurse ../../../clock.v\n\n\n#UCF file\nimport_files -fileset [get_filesets constrs_1] -force -norecurse ../../example_design/clock_exdes.ucf\n\nset_property top $topName [get_property srcset [current_run]]\n\nlaunch_runs -runs synth_1\nwait_on_run synth_1\n\nset_property add_step Bitgen [get_runs impl_1]\nlaunch_runs -runs impl_1\nwait_on_run impl_1\n\n\n\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock/implement/planAhead_rdn.bat",
    "content": "REM file: planAhead_rdn.sh\nREM \nREM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\nREM \nREM This file contains confidential and proprietary information\nREM of Xilinx, Inc. and is protected under U.S. and\nREM international copyright and other intellectual property\nREM laws.\nREM \nREM DISCLAIMER\nREM This disclaimer is not a license and does not grant any\nREM rights to the materials distributed herewith. Except as\nREM otherwise provided in a valid license issued to you by\nREM Xilinx, and to the maximum extent permitted by applicable\nREM law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\nREM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\nREM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\nREM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\nREM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\nREM (2) Xilinx shall not be liable (whether in contract or tort,\nREM including negligence, or under any other theory of\nREM liability) for any loss or damage of any kind or nature\nREM related to, arising under or in connection with these\nREM materials, including for any direct, or any indirect,\nREM special, incidental, or consequential loss or damage\nREM (including loss of data, profits, goodwill, or any type of\nREM loss or damage suffered as a result of any action brought\nREM by a third party) even if such damage or loss was\nREM reasonably foreseeable or Xilinx had been advised of the\nREM possibility of the same.\nREM \nREM CRITICAL APPLICATIONS\nREM Xilinx products are not designed or intended to be fail-\nREM safe, or for use in any application requiring fail-safe\nREM performance, such as life-support or safety devices or\nREM systems, Class III medical devices, nuclear facilities,\nREM applications related to the deployment of airbags, or any\nREM other applications that could lead to death, personal\nREM injury, or severe property or environmental damage\nREM (individually and collectively, \"Critical\nREM Applications\"). Customer assumes the sole risk and\nREM liability of any use of Xilinx products in Critical\nREM Applications, subject only to applicable laws and\nREM regulations governing limitations on product liability.\nREM \nREM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\nREM PART OF THIS FILE AT ALL TIMES.\nREM \n\nREM-----------------------------------------------------------------------------\nREM Script to synthesize and implement the RTL provided for the XADC wizard\nREM-----------------------------------------------------------------------------\n\ndel \\f results\nmkdir results\ncd results\n\nplanAhead -mode batch -source ..\\planAhead_rdn.tcl\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock/implement/planAhead_rdn.sh",
    "content": "#!/bin/sh\n# file: planAhead_rdn.sh\n# \n# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\n# \n# This file contains confidential and proprietary information\n# of Xilinx, Inc. and is protected under U.S. and\n# international copyright and other intellectual property\n# laws.\n# \n# DISCLAIMER\n# This disclaimer is not a license and does not grant any\n# rights to the materials distributed herewith. Except as\n# otherwise provided in a valid license issued to you by\n# Xilinx, and to the maximum extent permitted by applicable\n# law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n# (2) Xilinx shall not be liable (whether in contract or tort,\n# including negligence, or under any other theory of\n# liability) for any loss or damage of any kind or nature\n# related to, arising under or in connection with these\n# materials, including for any direct, or any indirect,\n# special, incidental, or consequential loss or damage\n# (including loss of data, profits, goodwill, or any type of\n# loss or damage suffered as a result of any action brought\n# by a third party) even if such damage or loss was\n# reasonably foreseeable or Xilinx had been advised of the\n# possibility of the same.\n# \n# CRITICAL APPLICATIONS\n# Xilinx products are not designed or intended to be fail-\n# safe, or for use in any application requiring fail-safe\n# performance, such as life-support or safety devices or\n# systems, Class III medical devices, nuclear facilities,\n# applications related to the deployment of airbags, or any\n# other applications that could lead to death, personal\n# injury, or severe property or environmental damage\n# (individually and collectively, \"Critical\n# Applications\"). Customer assumes the sole risk and\n# liability of any use of Xilinx products in Critical\n# Applications, subject only to applicable laws and\n# regulations governing limitations on product liability.\n# \n# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n# PART OF THIS FILE AT ALL TIMES.\n# \n\n#-----------------------------------------------------------------------------\n# Script to synthesize and implement the RTL provided for the XADC wizard\n#-----------------------------------------------------------------------------\nrm -rf results\nmkdir results\ncd results\nplanAhead -mode batch -source ../planAhead_rdn.tcl\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock/implement/planAhead_rdn.tcl",
    "content": "# file : planAhead_rdn.tcl\n# \n# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\n# \n# This file contains confidential and proprietary information\n# of Xilinx, Inc. and is protected under U.S. and\n# international copyright and other intellectual property\n# laws.\n# \n# DISCLAIMER\n# This disclaimer is not a license and does not grant any\n# rights to the materials distributed herewith. Except as\n# otherwise provided in a valid license issued to you by\n# Xilinx, and to the maximum extent permitted by applicable\n# law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n# (2) Xilinx shall not be liable (whether in contract or tort,\n# including negligence, or under any other theory of\n# liability) for any loss or damage of any kind or nature\n# related to, arising under or in connection with these\n# materials, including for any direct, or any indirect,\n# special, incidental, or consequential loss or damage\n# (including loss of data, profits, goodwill, or any type of\n# loss or damage suffered as a result of any action brought\n# by a third party) even if such damage or loss was\n# reasonably foreseeable or Xilinx had been advised of the\n# possibility of the same.\n# \n# CRITICAL APPLICATIONS\n# Xilinx products are not designed or intended to be fail-\n# safe, or for use in any application requiring fail-safe\n# performance, such as life-support or safety devices or\n# systems, Class III medical devices, nuclear facilities,\n# applications related to the deployment of airbags, or any\n# other applications that could lead to death, personal\n# injury, or severe property or environmental damage\n# (individually and collectively, \"Critical\n# Applications\"). Customer assumes the sole risk and\n# liability of any use of Xilinx products in Critical\n# Applications, subject only to applicable laws and\n# regulations governing limitations on product liability.\n# \n# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n# PART OF THIS FILE AT ALL TIMES.\n# \n\nset device xc6slx16csg324-2\nset projName clock\nset design clock\nset projDir [file dirname [info script]]\ncreate_project $projName $projDir/results/$projName -part $device -force\nset_property design_mode RTL [current_fileset -srcset]\nset top_module clock_exdes\nset_property top clock_exdes [get_property srcset [current_run]]\nadd_files -norecurse {../../../clock.v}\nadd_files -norecurse {../../example_design/clock_exdes.v}\nimport_files -fileset [get_filesets constrs_1 ] -force -norecurse {../../example_design/clock_exdes.xdc}\nsynth_design\nopt_design \nplace_design \nroute_design \nwrite_sdf -rename_top_module clock_exdes -file routed.sdf \nwrite_verilog -nolib -mode timesim -sdf_anno false -rename_top_module clock_exdes -file routed.v\nreport_timing -nworst 30 -path_type full -file routed.twr\nreport_drc -file report.drc\nwrite_bitstream -bitgen_options {-g UnconstrainedPins:Allow} -file routed.bit\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock/implement/xst.prj",
    "content": "verilog work ../../clock.v\nverilog work ../example_design/clock_exdes.v\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock/implement/xst.scr",
    "content": "run\n-ifmt MIXED\n-top clock_exdes\n-p xc6slx16-csg324-2\n-ifn xst.prj\n-ofn clock_exdes\n-keep_hierarchy soft \n-equivalent_register_removal no \n-max_fanout 65535\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock/simulation/clock_tb.v",
    "content": "// file: clock_tb.v\n// \n// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n\n//----------------------------------------------------------------------------\n// Clocking wizard demonstration testbench\n//----------------------------------------------------------------------------\n// This demonstration testbench instantiates the example design for the \n//   clocking wizard. Input clocks are toggled, which cause the clocking\n//   network to lock and the counters to increment.\n//----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\n`define wait_lock @(posedge LOCKED)\n\nmodule clock_tb ();\n\n  // Clock to Q delay of 100ps\n  localparam  TCQ              = 100;\n\n\n  // timescale is 1ps/1ps\n  localparam  ONE_NS      = 1000;\n  localparam  PHASE_ERR_MARGIN   = 100; // 100ps\n  // how many cycles to run\n  localparam  COUNT_PHASE = 1024;\n  // we'll be using the period in many locations\n  localparam time PER1    = 10.0*ONE_NS;\n  localparam time PER1_1  = PER1/2;\n  localparam time PER1_2  = PER1 - PER1/2;\n\n  // Declare the input clock signals\n  reg         CLK_IN1     = 1;\n\n  // The high bits of the sampling counters\n  wire [2:1]  COUNT;\n  // Status and control signals\n  wire        LOCKED;\n  reg         COUNTER_RESET = 0;\nwire [2:1] CLK_OUT;\n//Freq Check using the M & D values setting and actual Frequency generated\n\n\n  // Input clock generation\n  //------------------------------------\n  always begin\n    CLK_IN1 = #PER1_1 ~CLK_IN1;\n    CLK_IN1 = #PER1_2 ~CLK_IN1;\n  end\n\n  // Test sequence\n  reg [15*8-1:0] test_phase = \"\";\n  initial begin\n    // Set up any display statements using time to be readable\n    $timeformat(-12, 2, \"ps\", 10);\n    COUNTER_RESET = 0;\n    test_phase = \"wait lock\";\n    `wait_lock;\n    #(PER1*6);\n    COUNTER_RESET = 1;\n    #(PER1*20)\n    COUNTER_RESET = 0;\n\n    test_phase = \"counting\";\n    #(PER1*COUNT_PHASE);\n\n    $display(\"SIMULATION PASSED\");\n    $display(\"SYSTEM_CLOCK_COUNTER : %0d\\n\",$time/PER1);\n    $finish;\n  end\n\n  // Instantiation of the example design containing the clock\n  //    network and sampling counters\n  //---------------------------------------------------------\n  clock_exdes \n  #(\n    .TCQ (TCQ)\n   ) dut\n   (// Clock in ports\n    .CLK_IN1            (CLK_IN1),\n    // Reset for logic in example design\n    .COUNTER_RESET      (COUNTER_RESET),\n    .CLK_OUT            (CLK_OUT),\n    // High bits of the counters\n    .COUNT              (COUNT),\n    // Status and control signals\n    .LOCKED             (LOCKED));\n\n// Freq Check \n\nendmodule\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock/simulation/functional/simcmds.tcl",
    "content": "# file: simcmds.tcl\n\n# create the simulation script\nvcd dumpfile isim.vcd\nvcd dumpvars -m /clock_tb -l 0\nwave add /\nrun 50000ns\nquit\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock/simulation/functional/simulate_isim.bat",
    "content": "REM file: simulate_isim.bat\nREM  \nREM  (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\nREM  \nREM  This file contains confidential and proprietary information\nREM  of Xilinx, Inc. and is protected under U.S. and\nREM  international copyright and other intellectual property\nREM  laws.\nREM  \nREM  DISCLAIMER\nREM  This disclaimer is not a license and does not grant any\nREM  rights to the materials distributed herewith. Except as\nREM  otherwise provided in a valid license issued to you by\nREM  Xilinx, and to the maximum extent permitted by applicable\nREM  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\nREM  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\nREM  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\nREM  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\nREM  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\nREM  (2) Xilinx shall not be liable (whether in contract or tort,\nREM  including negligence, or under any other theory of\nREM  liability) for any loss or damage of any kind or nature\nREM  related to, arising under or in connection with these\nREM  materials, including for any direct, or any indirect,\nREM  special, incidental, or consequential loss or damage\nREM  (including loss of data, profits, goodwill, or any type of\nREM  loss or damage suffered as a result of any action brought\nREM  by a third party) even if such damage or loss was\nREM  reasonably foreseeable or Xilinx had been advised of the\nREM  possibility of the same.\nREM  \nREM  CRITICAL APPLICATIONS\nREM  Xilinx products are not designed or intended to be fail-\nREM  safe, or for use in any application requiring fail-safe\nREM  performance, such as life-support or safety devices or\nREM  systems, Class III medical devices, nuclear facilities,\nREM  applications related to the deployment of airbags, or any\nREM  other applications that could lead to death, personal\nREM  injury, or severe property or environmental damage\nREM  (individually and collectively, \"Critical\nREM  Applications\"). Customer assumes the sole risk and\nREM  liability of any use of Xilinx products in Critical\nREM  Applications, subject only to applicable laws and\nREM  regulations governing limitations on product liability.\nREM  \nREM  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\nREM  PART OF THIS FILE AT ALL TIMES.\nREM  \n\nvlogcomp -work work %XILINX%\\verilog\\src\\glbl.v\nvlogcomp -work work ..\\..\\..\\clock.v\nvlogcomp -work work ..\\..\\example_design\\clock_exdes.v\nvlogcomp -work work ..\\clock_tb.v\n\nREM compile the project\nfuse work.clock_tb work.glbl -L unisims_ver -o clock_isim.exe\n\nREM run the simulation script\n.\\clock_isim.exe -gui -tclbatch simcmds.tcl\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock/simulation/functional/simulate_isim.sh",
    "content": "# file: simulate_isim.sh\n# \n# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\n# \n# This file contains confidential and proprietary information\n# of Xilinx, Inc. and is protected under U.S. and\n# international copyright and other intellectual property\n# laws.\n# \n# DISCLAIMER\n# This disclaimer is not a license and does not grant any\n# rights to the materials distributed herewith. Except as\n# otherwise provided in a valid license issued to you by\n# Xilinx, and to the maximum extent permitted by applicable\n# law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n# (2) Xilinx shall not be liable (whether in contract or tort,\n# including negligence, or under any other theory of\n# liability) for any loss or damage of any kind or nature\n# related to, arising under or in connection with these\n# materials, including for any direct, or any indirect,\n# special, incidental, or consequential loss or damage\n# (including loss of data, profits, goodwill, or any type of\n# loss or damage suffered as a result of any action brought\n# by a third party) even if such damage or loss was\n# reasonably foreseeable or Xilinx had been advised of the\n# possibility of the same.\n# \n# CRITICAL APPLICATIONS\n# Xilinx products are not designed or intended to be fail-\n# safe, or for use in any application requiring fail-safe\n# performance, such as life-support or safety devices or\n# systems, Class III medical devices, nuclear facilities,\n# applications related to the deployment of airbags, or any\n# other applications that could lead to death, personal\n# injury, or severe property or environmental damage\n# (individually and collectively, \"Critical\n# Applications\"). Customer assumes the sole risk and\n# liability of any use of Xilinx products in Critical\n# Applications, subject only to applicable laws and\n# regulations governing limitations on product liability.\n# \n# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n# PART OF THIS FILE AT ALL TIMES.\n# \n\n# nt64\n# create the project\nvlogcomp -work work ${XILINX}/verilog/src/glbl.v\nvlogcomp -work work ../../../clock.v\nvlogcomp -work work ../../example_design/clock_exdes.v\nvlogcomp -work work ../clock_tb.v\n\n# compile the project\nfuse work.clock_tb work.glbl -L unisims_ver -o clock_isim.exe\n\n# run the simulation script\n./clock_isim.exe -gui -tclbatch simcmds.tcl\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock/simulation/functional/simulate_mti.bat",
    "content": "REM file: simulate_mti.bat\nREM  \nREM  (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\nREM  \nREM  This file contains confidential and proprietary information\nREM  of Xilinx, Inc. and is protected under U.S. and\nREM  international copyright and other intellectual property\nREM  laws.\nREM  \nREM  DISCLAIMER\nREM  This disclaimer is not a license and does not grant any\nREM  rights to the materials distributed herewith. Except as\nREM  otherwise provided in a valid license issued to you by\nREM  Xilinx, and to the maximum extent permitted by applicable\nREM  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\nREM  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\nREM  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\nREM  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\nREM  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\nREM  (2) Xilinx shall not be liable (whether in contract or tort,\nREM  including negligence, or under any other theory of\nREM  liability) for any loss or damage of any kind or nature\nREM  related to, arising under or in connection with these\nREM  materials, including for any direct, or any indirect,\nREM  special, incidental, or consequential loss or damage\nREM  (including loss of data, profits, goodwill, or any type of\nREM  loss or damage suffered as a result of any action brought\nREM  by a third party) even if such damage or loss was\nREM  reasonably foreseeable or Xilinx had been advised of the\nREM  possibility of the same.\nREM  \nREM  CRITICAL APPLICATIONS\nREM  Xilinx products are not designed or intended to be fail-\nREM  safe, or for use in any application requiring fail-safe\nREM  performance, such as life-support or safety devices or\nREM  systems, Class III medical devices, nuclear facilities,\nREM  applications related to the deployment of airbags, or any\nREM  other applications that could lead to death, personal\nREM  injury, or severe property or environmental damage\nREM  (individually and collectively, \"Critical\nREM  Applications\"). Customer assumes the sole risk and\nREM  liability of any use of Xilinx products in Critical\nREM  Applications, subject only to applicable laws and\nREM  regulations governing limitations on product liability.\nREM  \nREM  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\nREM  PART OF THIS FILE AT ALL TIMES.\nREM  \n\nREM set up the working directory\nvlib work\n\nREM compile all of the files\nvlog -work work %XILINX%\\verilog\\src\\glbl.v\nvlog -work work ..\\..\\..\\clock.v\nvlog -work work ..\\..\\example_design\\clock_exdes.v\nvlog -work work ..\\clock_tb.v\n\nREM run the simulation\nvsim -c -t ps -voptargs=\"+acc\" -L secureip -L unisims_ver work.clock_tb work.glbl\n\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock/simulation/functional/simulate_mti.do",
    "content": "# file: simulate_mti.do\n# \n# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\n# \n# This file contains confidential and proprietary information\n# of Xilinx, Inc. and is protected under U.S. and\n# international copyright and other intellectual property\n# laws.\n# \n# DISCLAIMER\n# This disclaimer is not a license and does not grant any\n# rights to the materials distributed herewith. Except as\n# otherwise provided in a valid license issued to you by\n# Xilinx, and to the maximum extent permitted by applicable\n# law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n# (2) Xilinx shall not be liable (whether in contract or tort,\n# including negligence, or under any other theory of\n# liability) for any loss or damage of any kind or nature\n# related to, arising under or in connection with these\n# materials, including for any direct, or any indirect,\n# special, incidental, or consequential loss or damage\n# (including loss of data, profits, goodwill, or any type of\n# loss or damage suffered as a result of any action brought\n# by a third party) even if such damage or loss was\n# reasonably foreseeable or Xilinx had been advised of the\n# possibility of the same.\n# \n# CRITICAL APPLICATIONS\n# Xilinx products are not designed or intended to be fail-\n# safe, or for use in any application requiring fail-safe\n# performance, such as life-support or safety devices or\n# systems, Class III medical devices, nuclear facilities,\n# applications related to the deployment of airbags, or any\n# other applications that could lead to death, personal\n# injury, or severe property or environmental damage\n# (individually and collectively, \"Critical\n# Applications\"). Customer assumes the sole risk and\n# liability of any use of Xilinx products in Critical\n# Applications, subject only to applicable laws and\n# regulations governing limitations on product liability.\n# \n# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n# PART OF THIS FILE AT ALL TIMES.\n# \n\n# set up the working directory\nset work work\nvlib work\n\n# compile all of the files\nvlog -work work $env(XILINX)/verilog/src/glbl.v\nvlog -work work ../../../clock.v\nvlog -work work ../../example_design/clock_exdes.v\nvlog -work work ../clock_tb.v\n\n# run the simulation\nvsim  -t ps -voptargs=\"+acc\" -L unisims_ver work.clock_tb work.glbl\ndo wave.do\nlog clock_tb/dut/counter\nlog -r /*\nrun 50000ns\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock/simulation/functional/simulate_mti.sh",
    "content": "#/bin/sh\n# file: simulate_mti.sh\n# \n# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\n# \n# This file contains confidential and proprietary information\n# of Xilinx, Inc. and is protected under U.S. and\n# international copyright and other intellectual property\n# laws.\n# \n# DISCLAIMER\n# This disclaimer is not a license and does not grant any\n# rights to the materials distributed herewith. Except as\n# otherwise provided in a valid license issued to you by\n# Xilinx, and to the maximum extent permitted by applicable\n# law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n# (2) Xilinx shall not be liable (whether in contract or tort,\n# including negligence, or under any other theory of\n# liability) for any loss or damage of any kind or nature\n# related to, arising under or in connection with these\n# materials, including for any direct, or any indirect,\n# special, incidental, or consequential loss or damage\n# (including loss of data, profits, goodwill, or any type of\n# loss or damage suffered as a result of any action brought\n# by a third party) even if such damage or loss was\n# reasonably foreseeable or Xilinx had been advised of the\n# possibility of the same.\n# \n# CRITICAL APPLICATIONS\n# Xilinx products are not designed or intended to be fail-\n# safe, or for use in any application requiring fail-safe\n# performance, such as life-support or safety devices or\n# systems, Class III medical devices, nuclear facilities,\n# applications related to the deployment of airbags, or any\n# other applications that could lead to death, personal\n# injury, or severe property or environmental damage\n# (individually and collectively, \"Critical\n# Applications\"). Customer assumes the sole risk and\n# liability of any use of Xilinx products in Critical\n# Applications, subject only to applicable laws and\n# regulations governing limitations on product liability.\n# \n# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n# PART OF THIS FILE AT ALL TIMES.\n# \n# set up the working directory\nset work work\nvlib work\n\n# compile all of the files\nvlog -work work $XILINX/verilog/src/glbl.v\nvlog -work work ../../../clock.v\nvlog -work work ../../example_design/clock_exdes.v\nvlog -work work ../clock_tb.v\n\n# run the simulation\nvsim -c -t ps -voptargs=\"+acc\" -L secureip -L unisims_ver work.clock_tb work.glbl\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock/simulation/functional/simulate_ncsim.sh",
    "content": "#/bin/sh\n# file: simulate_ncsim.sh\n# \n# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\n# \n# This file contains confidential and proprietary information\n# of Xilinx, Inc. and is protected under U.S. and\n# international copyright and other intellectual property\n# laws.\n# \n# DISCLAIMER\n# This disclaimer is not a license and does not grant any\n# rights to the materials distributed herewith. Except as\n# otherwise provided in a valid license issued to you by\n# Xilinx, and to the maximum extent permitted by applicable\n# law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n# (2) Xilinx shall not be liable (whether in contract or tort,\n# including negligence, or under any other theory of\n# liability) for any loss or damage of any kind or nature\n# related to, arising under or in connection with these\n# materials, including for any direct, or any indirect,\n# special, incidental, or consequential loss or damage\n# (including loss of data, profits, goodwill, or any type of\n# loss or damage suffered as a result of any action brought\n# by a third party) even if such damage or loss was\n# reasonably foreseeable or Xilinx had been advised of the\n# possibility of the same.\n# \n# CRITICAL APPLICATIONS\n# Xilinx products are not designed or intended to be fail-\n# safe, or for use in any application requiring fail-safe\n# performance, such as life-support or safety devices or\n# systems, Class III medical devices, nuclear facilities,\n# applications related to the deployment of airbags, or any\n# other applications that could lead to death, personal\n# injury, or severe property or environmental damage\n# (individually and collectively, \"Critical\n# Applications\"). Customer assumes the sole risk and\n# liability of any use of Xilinx products in Critical\n# Applications, subject only to applicable laws and\n# regulations governing limitations on product liability.\n# \n# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n# PART OF THIS FILE AT ALL TIMES.\n# \n\n# set up the working directory\nmkdir work\n\n# compile all of the files\nncvlog -work work ${XILINX}/verilog/src/glbl.v\nncvlog -work work ../../../clock.v\nncvlog -work work ../../example_design/clock_exdes.v\nncvlog -work work ../clock_tb.v\n\n# elaborate and run the simulation\nncelab -work work -access +wc work.clock_tb work.glbl\nncsim -input  \"@database -open -shm nc; probe -create -database nc -all -depth all; probe dut.counter; run 50000ns; exit\" work.clock_tb\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock/simulation/functional/simulate_vcs.sh",
    "content": "#!/bin/sh\n# file: simulate_vcs.sh\n# \n# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\n# \n# This file contains confidential and proprietary information\n# of Xilinx, Inc. and is protected under U.S. and\n# international copyright and other intellectual property\n# laws.\n# \n# DISCLAIMER\n# This disclaimer is not a license and does not grant any\n# rights to the materials distributed herewith. Except as\n# otherwise provided in a valid license issued to you by\n# Xilinx, and to the maximum extent permitted by applicable\n# law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n# (2) Xilinx shall not be liable (whether in contract or tort,\n# including negligence, or under any other theory of\n# liability) for any loss or damage of any kind or nature\n# related to, arising under or in connection with these\n# materials, including for any direct, or any indirect,\n# special, incidental, or consequential loss or damage\n# (including loss of data, profits, goodwill, or any type of\n# loss or damage suffered as a result of any action brought\n# by a third party) even if such damage or loss was\n# reasonably foreseeable or Xilinx had been advised of the\n# possibility of the same.\n# \n# CRITICAL APPLICATIONS\n# Xilinx products are not designed or intended to be fail-\n# safe, or for use in any application requiring fail-safe\n# performance, such as life-support or safety devices or\n# systems, Class III medical devices, nuclear facilities,\n# applications related to the deployment of airbags, or any\n# other applications that could lead to death, personal\n# injury, or severe property or environmental damage\n# (individually and collectively, \"Critical\n# Applications\"). Customer assumes the sole risk and\n# liability of any use of Xilinx products in Critical\n# Applications, subject only to applicable laws and\n# regulations governing limitations on product liability.\n# \n# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n# PART OF THIS FILE AT ALL TIMES.\n# \n\n# remove old files\nrm -rf simv* csrc DVEfiles AN.DB\n\n# compile all of the files\n# Note that -sverilog is not strictly required- You can\n#   remove the -sverilog if you change the type of the\n#   localparam for the periods in the testbench file to \n#   [63:0] from time\nvlogan -sverilog \\\n      ${XILINX}/verilog/src/glbl.v \\\n      ../../../clock.v \\\n      ../../example_design/clock_exdes.v \\\n      ../clock_tb.v\n\n# prepare the simulation \nvcs +vcs+lic+wait -debug clock_tb glbl\n\n# run the simulation\n./simv -ucli -i ucli_commands.key\n\n# launch the viewer\ndve -vpd vcdplus.vpd -session vcs_session.tcl\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock/simulation/functional/ucli_commands.key",
    "content": "call {$vcdpluson}\ncall {$vcdplusmemon(clock_tb.dut.counter)}\nrun\ncall {$vcdplusclose}\nquit\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock/simulation/functional/vcs_session.tcl",
    "content": "gui_open_window Wave\ngui_sg_create clock_group\ngui_list_add_group -id Wave.1 {clock_group}\ngui_sg_addsignal -group clock_group {clock_tb.test_phase}\ngui_set_radix -radix {ascii} -signals {clock_tb.test_phase}\ngui_sg_addsignal -group clock_group {{Input_clocks}} -divider\ngui_sg_addsignal -group clock_group {clock_tb.CLK_IN1}\ngui_sg_addsignal -group clock_group {{Output_clocks}} -divider\ngui_sg_addsignal -group clock_group {clock_tb.dut.clk}\ngui_list_expand -id Wave.1 clock_tb.dut.clk\ngui_sg_addsignal -group clock_group {{Status_control}} -divider\ngui_sg_addsignal -group clock_group {clock_tb.LOCKED}\ngui_sg_addsignal -group clock_group {{Counters}} -divider\ngui_sg_addsignal -group clock_group {clock_tb.COUNT}\ngui_sg_addsignal -group clock_group {clock_tb.dut.counter}\ngui_list_expand -id Wave.1 clock_tb.dut.counter\ngui_zoom -window Wave.1 -full\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock/simulation/functional/wave.do",
    "content": "# file: wave.do\n# \n# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\n# \n# This file contains confidential and proprietary information\n# of Xilinx, Inc. and is protected under U.S. and\n# international copyright and other intellectual property\n# laws.\n# \n# DISCLAIMER\n# This disclaimer is not a license and does not grant any\n# rights to the materials distributed herewith. Except as\n# otherwise provided in a valid license issued to you by\n# Xilinx, and to the maximum extent permitted by applicable\n# law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n# (2) Xilinx shall not be liable (whether in contract or tort,\n# including negligence, or under any other theory of\n# liability) for any loss or damage of any kind or nature\n# related to, arising under or in connection with these\n# materials, including for any direct, or any indirect,\n# special, incidental, or consequential loss or damage\n# (including loss of data, profits, goodwill, or any type of\n# loss or damage suffered as a result of any action brought\n# by a third party) even if such damage or loss was\n# reasonably foreseeable or Xilinx had been advised of the\n# possibility of the same.\n# \n# CRITICAL APPLICATIONS\n# Xilinx products are not designed or intended to be fail-\n# safe, or for use in any application requiring fail-safe\n# performance, such as life-support or safety devices or\n# systems, Class III medical devices, nuclear facilities,\n# applications related to the deployment of airbags, or any\n# other applications that could lead to death, personal\n# injury, or severe property or environmental damage\n# (individually and collectively, \"Critical\n# Applications\"). Customer assumes the sole risk and\n# liability of any use of Xilinx products in Critical\n# Applications, subject only to applicable laws and\n# regulations governing limitations on product liability.\n# \n# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n# PART OF THIS FILE AT ALL TIMES.\n# \n\nadd wave -noupdate -format Literal -radix ascii /clock_tb/test_phase\nadd wave -noupdate -divider {Input clocks}\nadd wave -noupdate -format Logic /clock_tb/CLK_IN1\nadd wave -noupdate -divider {Output clocks}\nadd wave -noupdate -format Literal -expand /clock_tb/dut/clk\nadd wave -noupdate -divider Status/control\nadd wave -noupdate -format Logic /clock_tb/LOCKED\nadd wave -noupdate -divider Counters\nadd wave -noupdate -format Literal -radix hexadecimal /clock_tb/COUNT\nadd wave -noupdate -format Literal -radix hexadecimal -expand /clock_tb/dut/counter\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock/simulation/functional/wave.sv",
    "content": "# file: wave.sv\n# \n# (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.\n# \n# This file contains confidential and proprietary information\n# of Xilinx, Inc. and is protected under U.S. and\n# international copyright and other intellectual property\n# laws.\n# \n# DISCLAIMER\n# This disclaimer is not a license and does not grant any\n# rights to the materials distributed herewith. Except as\n# otherwise provided in a valid license issued to you by\n# Xilinx, and to the maximum extent permitted by applicable\n# law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n# (2) Xilinx shall not be liable (whether in contract or tort,\n# including negligence, or under any other theory of\n# liability) for any loss or damage of any kind or nature\n# related to, arising under or in connection with these\n# materials, including for any direct, or any indirect,\n# special, incidental, or consequential loss or damage\n# (including loss of data, profits, goodwill, or any type of\n# loss or damage suffered as a result of any action brought\n# by a third party) even if such damage or loss was\n# reasonably foreseeable or Xilinx had been advised of the\n# possibility of the same.\n# \n# CRITICAL APPLICATIONS\n# Xilinx products are not designed or intended to be fail-\n# safe, or for use in any application requiring fail-safe\n# performance, such as life-support or safety devices or\n# systems, Class III medical devices, nuclear facilities,\n# applications related to the deployment of airbags, or any\n# other applications that could lead to death, personal\n# injury, or severe property or environmental damage\n# (individually and collectively, \"Critical\n# Applications\"). Customer assumes the sole risk and\n# liability of any use of Xilinx products in Critical\n# Applications, subject only to applicable laws and\n# regulations governing limitations on product liability.\n# \n# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n# PART OF THIS FILE AT ALL TIMES.\n#\n# Get the windows set up\n#\nif {[catch {window new WatchList -name \"Design Browser 1\" -geometry 1054x819+536+322}] != \"\"} {\n    window geometry \"Design Browser 1\" 1054x819+536+322\n}\nwindow target \"Design Browser 1\" on\nbrowser using {Design Browser 1}\nbrowser set \\\n    -scope nc::clock_tb\nbrowser yview see nc::clock_tb\nbrowser timecontrol set -lock 0\n\nif {[catch {window new WaveWindow -name \"Waveform 1\" -geometry 1010x600+0+541}] != \"\"} {\n    window geometry \"Waveform 1\" 1010x600+0+541\n}\nwindow target \"Waveform 1\" on\nwaveform using {Waveform 1}\nwaveform sidebar visibility partial\nwaveform set \\\n    -primarycursor TimeA \\\n    -signalnames name \\\n    -signalwidth 175 \\\n    -units ns \\\n    -valuewidth 75\ncursor set -using TimeA -time 0\nwaveform baseline set -time 0\nwaveform xview limits 0 20000n\n\n#\n# Define signal groups\n#\ncatch {group new -name {Output clocks} -overlay 0}\ncatch {group new -name {Status/control} -overlay 0}\ncatch {group new -name {Counters} -overlay 0}\n\nset id [waveform add -signals [list {nc::clock_tb.CLK_IN1}]]\n\ngroup using {Output clocks}\ngroup set -overlay 0\ngroup set -comment {}\ngroup clear 0 end\n\ngroup insert \\\n    {clock_tb.dut.clk[1]} \\\n    {clock_tb.dut.clk[2]} \ngroup using {Counters}\ngroup set -overlay 0\ngroup set -comment {}\ngroup clear 0 end\n\ngroup insert \\\n    {clock_tb.dut.counter[1]} \\\n    {clock_tb.dut.counter[2]} \ngroup using {Status/control}\ngroup set -overlay 0\ngroup set -comment {}\ngroup clear 0 end\n\ngroup insert \\\n   {nc::clock_tb.LOCKED}\n\n\nset id [waveform add -signals [list {nc::clock_tb.COUNT} ]]\n\nset id [waveform add -signals [list {nc::clock_tb.test_phase} ]]\nwaveform format $id -radix %a\n\nset groupId [waveform add -groups {{Input clocks}}]\nset groupId [waveform add -groups {{Output clocks}}]\nset groupId [waveform add -groups {{Status/control}}]\nset groupId [waveform add -groups {{Counters}}]\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock/simulation/timing/clock_tb.v",
    "content": "// file: clock_tb.v\n// \n// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n\n//----------------------------------------------------------------------------\n// Clocking wizard demonstration testbench\n//----------------------------------------------------------------------------\n// This demonstration testbench instantiates the example design for the \n//   clocking wizard. Input clocks are toggled, which cause the clocking\n//   network to lock and the counters to increment.\n//----------------------------------------------------------------------------\n\n`timescale 1ps/1ps\n\n`define wait_lock @(posedge LOCKED)\n\nmodule clock_tb ();\n\n  // Clock to Q delay of 100ps\n  localparam  TCQ              = 100;\n\n\n  // timescale is 1ps/1ps\n  localparam  ONE_NS      = 1000;\n  localparam  PHASE_ERR_MARGIN   = 100; // 100ps\n  // how many cycles to run\n  localparam  COUNT_PHASE = 1024;\n  // we'll be using the period in many locations\n  localparam time PER1    = 10.0*ONE_NS;\n  localparam time PER1_1  = PER1/2;\n  localparam time PER1_2  = PER1 - PER1/2;\n\n  // Declare the input clock signals\n  reg         CLK_IN1     = 1;\n\n  // The high bits of the sampling counters\n  wire [2:1]  COUNT;\n  // Status and control signals\n  wire        LOCKED;\n  reg         COUNTER_RESET = 0;\nwire [2:1] CLK_OUT;\n//Freq Check using the M & D values setting and actual Frequency generated \n\n  reg [13:0]  timeout_counter = 14'b00000000000000;\n\n  // Input clock generation\n  //------------------------------------\n  always begin\n    CLK_IN1 = #PER1_1 ~CLK_IN1;\n    CLK_IN1 = #PER1_2 ~CLK_IN1;\n  end\n\n  // Test sequence\n  reg [15*8-1:0] test_phase = \"\";\n  initial begin\n    // Set up any display statements using time to be readable\n    $timeformat(-12, 2, \"ps\", 10);\n    $display (\"Timing checks are not valid\");\n    COUNTER_RESET = 0;\n    test_phase = \"wait lock\";\n    `wait_lock;\n    #(PER1*6);\n    COUNTER_RESET = 1;\n    #(PER1*19.5)\n    COUNTER_RESET = 0;\n    #(PER1*1)\n    $display (\"Timing checks are valid\");\n    test_phase = \"counting\";\n    #(PER1*COUNT_PHASE);\n\n    $display(\"SIMULATION PASSED\");\n    $display(\"SYSTEM_CLOCK_COUNTER : %0d\\n\",$time/PER1);\n    $finish;\n  end\n\n\n   always@(posedge CLK_IN1) begin\n      timeout_counter <= timeout_counter + 1'b1;\n      if (timeout_counter == 14'b10000000000000) begin\n         if (LOCKED != 1'b1) begin\n            $display(\"ERROR : NO LOCK signal\");\n            $display(\"SYSTEM_CLOCK_COUNTER : %0d\\n\",$time/PER1);\n            $finish;\n         end\n      end\n   end\n\n  // Instantiation of the example design containing the clock\n  //    network and sampling counters\n  //---------------------------------------------------------\n  clock_exdes \n    dut\n   (// Clock in ports\n    .CLK_IN1            (CLK_IN1),\n    // Reset for logic in example design\n    .COUNTER_RESET      (COUNTER_RESET),\n    .CLK_OUT            (CLK_OUT),\n    // High bits of the counters\n    .COUNT              (COUNT),\n    // Status and control signals\n    .LOCKED             (LOCKED));\n\n\n// Freq Check \n\nendmodule\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock/simulation/timing/sdf_cmd_file",
    "content": "COMPILED_SDF_FILE = \"../../implement/results/routed.sdf.X\",\nSCOPE = clock_tb.dut;\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock/simulation/timing/simcmds.tcl",
    "content": "# file: simcmds.tcl\n\n# create the simulation script\nvcd dumpfile isim.vcd\nvcd dumpvars -m /clock_tb -l 0\nwave add /\nrun 50000ns\nquit\n\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock/simulation/timing/simulate_isim.sh",
    "content": "# file: simulate_isim.sh\n# \n# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\n# \n# This file contains confidential and proprietary information\n# of Xilinx, Inc. and is protected under U.S. and\n# international copyright and other intellectual property\n# laws.\n# \n# DISCLAIMER\n# This disclaimer is not a license and does not grant any\n# rights to the materials distributed herewith. Except as\n# otherwise provided in a valid license issued to you by\n# Xilinx, and to the maximum extent permitted by applicable\n# law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n# (2) Xilinx shall not be liable (whether in contract or tort,\n# including negligence, or under any other theory of\n# liability) for any loss or damage of any kind or nature\n# related to, arising under or in connection with these\n# materials, including for any direct, or any indirect,\n# special, incidental, or consequential loss or damage\n# (including loss of data, profits, goodwill, or any type of\n# loss or damage suffered as a result of any action brought\n# by a third party) even if such damage or loss was\n# reasonably foreseeable or Xilinx had been advised of the\n# possibility of the same.\n# \n# CRITICAL APPLICATIONS\n# Xilinx products are not designed or intended to be fail-\n# safe, or for use in any application requiring fail-safe\n# performance, such as life-support or safety devices or\n# systems, Class III medical devices, nuclear facilities,\n# applications related to the deployment of airbags, or any\n# other applications that could lead to death, personal\n# injury, or severe property or environmental damage\n# (individually and collectively, \"Critical\n# Applications\"). Customer assumes the sole risk and\n# liability of any use of Xilinx products in Critical\n# Applications, subject only to applicable laws and\n# regulations governing limitations on product liability.\n# \n# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n# PART OF THIS FILE AT ALL TIMES.\n# \n\n# create the project\nvlogcomp -work work ${XILINX}/verilog/src/glbl.v\nvlogcomp -work work ../../implement/results/routed.v\nvlogcomp -work work clock_tb.v\n\n# compile the project\nfuse work.clock_tb work.glbl -L secureip -L simprims_ver -o clock_isim.exe\n\n# run the simulation script\n./clock_isim.exe -tclbatch simcmds.tcl -sdfmax /clock_tb/dut=../../implement/results/routed.sdf\n\n# run the simulation script\n#./clock_isim.exe -gui -tclbatch simcmds.tcl\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock/simulation/timing/simulate_mti.bat",
    "content": "REM file: simulate_mti.bat\nREM  \nREM  (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\nREM  \nREM  This file contains confidential and proprietary information\nREM  of Xilinx, Inc. and is protected under U.S. and\nREM  international copyright and other intellectual property\nREM  laws.\nREM  \nREM  DISCLAIMER\nREM  This disclaimer is not a license and does not grant any\nREM  rights to the materials distributed herewith. Except as\nREM  otherwise provided in a valid license issued to you by\nREM  Xilinx, and to the maximum extent permitted by applicable\nREM  law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\nREM  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\nREM  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\nREM  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\nREM  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\nREM  (2) Xilinx shall not be liable (whether in contract or tort,\nREM  including negligence, or under any other theory of\nREM  liability) for any loss or damage of any kind or nature\nREM  related to, arising under or in connection with these\nREM  materials, including for any direct, or any indirect,\nREM  special, incidental, or consequential loss or damage\nREM  (including loss of data, profits, goodwill, or any type of\nREM  loss or damage suffered as a result of any action brought\nREM  by a third party) even if such damage or loss was\nREM  reasonably foreseeable or Xilinx had been advised of the\nREM  possibility of the same.\nREM  \nREM  CRITICAL APPLICATIONS\nREM  Xilinx products are not designed or intended to be fail-\nREM  safe, or for use in any application requiring fail-safe\nREM  performance, such as life-support or safety devices or\nREM  systems, Class III medical devices, nuclear facilities,\nREM  applications related to the deployment of airbags, or any\nREM  other applications that could lead to death, personal\nREM  injury, or severe property or environmental damage\nREM  (individually and collectively, \"Critical\nREM  Applications\"). Customer assumes the sole risk and\nREM  liability of any use of Xilinx products in Critical\nREM  Applications, subject only to applicable laws and\nREM  regulations governing limitations on product liability.\nREM  \nREM  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\nREM  PART OF THIS FILE AT ALL TIMES.\nREM  \n# set up the working directory\nset work work\nvlib work\n\nREM compile all of the files\nvlog -work work %XILINX%\\verilog\\src\\glbl.v\nvlog -work work ..\\..\\implement\\results\\routed.v\nvlog -work work clock_tb.v\n\nREM run the simulation\nvsim -c -t ps +transport_int_delays -voptargs=\"+acc\" -L secureip -L simprims_ver -sdfmax clock_tb\\dut=..\\..\\implement\\results\\routed.sdf +no_notifier work.clock_tb work.glbl\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock/simulation/timing/simulate_mti.do",
    "content": "# file: simulate_mti.do\n# \n# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\n# \n# This file contains confidential and proprietary information\n# of Xilinx, Inc. and is protected under U.S. and\n# international copyright and other intellectual property\n# laws.\n# \n# DISCLAIMER\n# This disclaimer is not a license and does not grant any\n# rights to the materials distributed herewith. Except as\n# otherwise provided in a valid license issued to you by\n# Xilinx, and to the maximum extent permitted by applicable\n# law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n# (2) Xilinx shall not be liable (whether in contract or tort,\n# including negligence, or under any other theory of\n# liability) for any loss or damage of any kind or nature\n# related to, arising under or in connection with these\n# materials, including for any direct, or any indirect,\n# special, incidental, or consequential loss or damage\n# (including loss of data, profits, goodwill, or any type of\n# loss or damage suffered as a result of any action brought\n# by a third party) even if such damage or loss was\n# reasonably foreseeable or Xilinx had been advised of the\n# possibility of the same.\n# \n# CRITICAL APPLICATIONS\n# Xilinx products are not designed or intended to be fail-\n# safe, or for use in any application requiring fail-safe\n# performance, such as life-support or safety devices or\n# systems, Class III medical devices, nuclear facilities,\n# applications related to the deployment of airbags, or any\n# other applications that could lead to death, personal\n# injury, or severe property or environmental damage\n# (individually and collectively, \"Critical\n# Applications\"). Customer assumes the sole risk and\n# liability of any use of Xilinx products in Critical\n# Applications, subject only to applicable laws and\n# regulations governing limitations on product liability.\n# \n# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n# PART OF THIS FILE AT ALL TIMES.\n# \n\n# set up the working directory\nset work work\nvlib work\n\n# compile all of the files\nvlog -work work $env(XILINX)/verilog/src/glbl.v\nvlog -work work ../../implement/results/routed.v\nvlog -work work clock_tb.v\n\n# run the simulation\nvsim -t ps +transport_int_delays -voptargs=\"+acc\" -L secureip -L simprims_ver -sdfmax clock_tb/dut=../../implement/results/routed.sdf +no_notifier work.clock_tb work.glbl\n#do wave.do\n#log -r /*\nrun 50000ns\n\n\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock/simulation/timing/simulate_mti.sh",
    "content": "#/bin/sh\n# file: simulate_mti.sh\n# \n# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\n# \n# This file contains confidential and proprietary information\n# of Xilinx, Inc. and is protected under U.S. and\n# international copyright and other intellectual property\n# laws.\n# \n# DISCLAIMER\n# This disclaimer is not a license and does not grant any\n# rights to the materials distributed herewith. Except as\n# otherwise provided in a valid license issued to you by\n# Xilinx, and to the maximum extent permitted by applicable\n# law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n# (2) Xilinx shall not be liable (whether in contract or tort,\n# including negligence, or under any other theory of\n# liability) for any loss or damage of any kind or nature\n# related to, arising under or in connection with these\n# materials, including for any direct, or any indirect,\n# special, incidental, or consequential loss or damage\n# (including loss of data, profits, goodwill, or any type of\n# loss or damage suffered as a result of any action brought\n# by a third party) even if such damage or loss was\n# reasonably foreseeable or Xilinx had been advised of the\n# possibility of the same.\n# \n# CRITICAL APPLICATIONS\n# Xilinx products are not designed or intended to be fail-\n# safe, or for use in any application requiring fail-safe\n# performance, such as life-support or safety devices or\n# systems, Class III medical devices, nuclear facilities,\n# applications related to the deployment of airbags, or any\n# other applications that could lead to death, personal\n# injury, or severe property or environmental damage\n# (individually and collectively, \"Critical\n# Applications\"). Customer assumes the sole risk and\n# liability of any use of Xilinx products in Critical\n# Applications, subject only to applicable laws and\n# regulations governing limitations on product liability.\n# \n# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n# PART OF THIS FILE AT ALL TIMES.\n# \n\n# set up the working directory\nset work work\nvlib work\n\n# compile all of the files\nvlog -work work $XILINX/verilog/src/glbl.v\nvlog -work work ../../implement/results/routed.v\nvlog -work work clock_tb.v\n\n# run the simulation\nvsim -c -t ps +transport_int_delays -voptargs=\"+acc\" -L secureip -L simprims_ver -sdfmax clock_tb/dut=../../implement/results/routed.sdf +no_notifier work.clock_tb work.glbl\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock/simulation/timing/simulate_ncsim.sh",
    "content": "#!/bin/sh\n# file: simulate_ncsim.sh\n# \n# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\n# \n# This file contains confidential and proprietary information\n# of Xilinx, Inc. and is protected under U.S. and\n# international copyright and other intellectual property\n# laws.\n# \n# DISCLAIMER\n# This disclaimer is not a license and does not grant any\n# rights to the materials distributed herewith. Except as\n# otherwise provided in a valid license issued to you by\n# Xilinx, and to the maximum extent permitted by applicable\n# law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n# (2) Xilinx shall not be liable (whether in contract or tort,\n# including negligence, or under any other theory of\n# liability) for any loss or damage of any kind or nature\n# related to, arising under or in connection with these\n# materials, including for any direct, or any indirect,\n# special, incidental, or consequential loss or damage\n# (including loss of data, profits, goodwill, or any type of\n# loss or damage suffered as a result of any action brought\n# by a third party) even if such damage or loss was\n# reasonably foreseeable or Xilinx had been advised of the\n# possibility of the same.\n# \n# CRITICAL APPLICATIONS\n# Xilinx products are not designed or intended to be fail-\n# safe, or for use in any application requiring fail-safe\n# performance, such as life-support or safety devices or\n# systems, Class III medical devices, nuclear facilities,\n# applications related to the deployment of airbags, or any\n# other applications that could lead to death, personal\n# injury, or severe property or environmental damage\n# (individually and collectively, \"Critical\n# Applications\"). Customer assumes the sole risk and\n# liability of any use of Xilinx products in Critical\n# Applications, subject only to applicable laws and\n# regulations governing limitations on product liability.\n# \n# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n# PART OF THIS FILE AT ALL TIMES.\n# \n\n# set up the working directory\nmkdir work\n\n# compile all of the files\nncvlog -work work ${XILINX}/verilog/src/glbl.v\nncvlog -work work ../../implement/results/routed.v\nncvlog -work work clock_tb.v\n\n# elaborate and run the simulation\nncsdfc ../../implement/results/routed.sdf\n\nncelab -work work -access +wc -pulse_r 10 -nonotifier work.clock_tb work.glbl -sdf_cmd_file sdf_cmd_file\nncsim -input  \"@database -open -shm nc; probe -create -database nc -all -depth all; run 50000ns; exit\" work.clock_tb\n\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock/simulation/timing/simulate_vcs.sh",
    "content": "#!/bin/sh\n# file: simulate_vcs.sh\n# \n# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\n# \n# This file contains confidential and proprietary information\n# of Xilinx, Inc. and is protected under U.S. and\n# international copyright and other intellectual property\n# laws.\n# \n# DISCLAIMER\n# This disclaimer is not a license and does not grant any\n# rights to the materials distributed herewith. Except as\n# otherwise provided in a valid license issued to you by\n# Xilinx, and to the maximum extent permitted by applicable\n# law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n# (2) Xilinx shall not be liable (whether in contract or tort,\n# including negligence, or under any other theory of\n# liability) for any loss or damage of any kind or nature\n# related to, arising under or in connection with these\n# materials, including for any direct, or any indirect,\n# special, incidental, or consequential loss or damage\n# (including loss of data, profits, goodwill, or any type of\n# loss or damage suffered as a result of any action brought\n# by a third party) even if such damage or loss was\n# reasonably foreseeable or Xilinx had been advised of the\n# possibility of the same.\n# \n# CRITICAL APPLICATIONS\n# Xilinx products are not designed or intended to be fail-\n# safe, or for use in any application requiring fail-safe\n# performance, such as life-support or safety devices or\n# systems, Class III medical devices, nuclear facilities,\n# applications related to the deployment of airbags, or any\n# other applications that could lead to death, personal\n# injury, or severe property or environmental damage\n# (individually and collectively, \"Critical\n# Applications\"). Customer assumes the sole risk and\n# liability of any use of Xilinx products in Critical\n# Applications, subject only to applicable laws and\n# regulations governing limitations on product liability.\n# \n# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n# PART OF THIS FILE AT ALL TIMES.\n# \n\n# remove old files\nrm -rf simv* csrc DVEfiles AN.DB\n\n# compile all of the files\n# Note that -sverilog is not strictly required- You can\n#   remove the -sverilog if you change the type of the\n#   localparam for the periods in the testbench file to \n#   [63:0] from time\n  vlogan -sverilog \\\n           clock_tb.v \\\n           ../../implement/results/routed.v\n\n\n# prepare the simulation\nvcs -sdf max:clock_exdes:../../implement/results/routed.sdf +v2k -y $XILINX/verilog/src/simprims \\\n        +libext+.v -debug clock_tb.v ../../implement/results/routed.v\n\n# run the simulation\n./simv -ucli -i ucli_commands.key\n\n# launch the viewer\n#dve -vpd vcdplus.vpd -session vcs_session.tcl\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock/simulation/timing/ucli_commands.key",
    "content": "\ncall {$vcdpluson}\nrun 50000ns\ncall {$vcdplusclose}\nquit\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock/simulation/timing/vcs_session.tcl",
    "content": "gui_open_window Wave\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock/simulation/timing/wave.do",
    "content": "# file: wave.do\n# \n# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\n# \n# This file contains confidential and proprietary information\n# of Xilinx, Inc. and is protected under U.S. and\n# international copyright and other intellectual property\n# laws.\n# \n# DISCLAIMER\n# This disclaimer is not a license and does not grant any\n# rights to the materials distributed herewith. Except as\n# otherwise provided in a valid license issued to you by\n# Xilinx, and to the maximum extent permitted by applicable\n# law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n# (2) Xilinx shall not be liable (whether in contract or tort,\n# including negligence, or under any other theory of\n# liability) for any loss or damage of any kind or nature\n# related to, arising under or in connection with these\n# materials, including for any direct, or any indirect,\n# special, incidental, or consequential loss or damage\n# (including loss of data, profits, goodwill, or any type of\n# loss or damage suffered as a result of any action brought\n# by a third party) even if such damage or loss was\n# reasonably foreseeable or Xilinx had been advised of the\n# possibility of the same.\n# \n# CRITICAL APPLICATIONS\n# Xilinx products are not designed or intended to be fail-\n# safe, or for use in any application requiring fail-safe\n# performance, such as life-support or safety devices or\n# systems, Class III medical devices, nuclear facilities,\n# applications related to the deployment of airbags, or any\n# other applications that could lead to death, personal\n# injury, or severe property or environmental damage\n# (individually and collectively, \"Critical\n# Applications\"). Customer assumes the sole risk and\n# liability of any use of Xilinx products in Critical\n# Applications, subject only to applicable laws and\n# regulations governing limitations on product liability.\n# \n# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n# PART OF THIS FILE AT ALL TIMES.\n# \n\nonerror {resume}\nquietly WaveActivateNextPane {} 0\nadd wave -noupdate /clock_tb/CLK_IN1\nadd wave -noupdate /clock_tb/COUNT\nadd wave -noupdate /clock_tb/LOCKED\nTreeUpdate [SetDefaultTree]\nWaveRestoreCursors {{Cursor 1} {3223025 ps} 0}\nconfigure wave -namecolwidth 238\nconfigure wave -valuecolwidth 107\nconfigure wave -justifyvalue left\nconfigure wave -signalnamewidth 0\nconfigure wave -snapdistance 10\nconfigure wave -datasetprefix 0\nconfigure wave -rowmargin 4\nconfigure wave -childrowmargin 2\nconfigure wave -gridoffset 0\nconfigure wave -gridperiod 1\nconfigure wave -griddelta 40\nconfigure wave -timeline 0\nconfigure wave -timelineunits ps\nupdate\nWaveRestoreZoom {0 ps} {74848022 ps}\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock.asy",
    "content": "Version 4\nSymbolType BLOCK\nTEXT 32 32 LEFT 4 clock\nRECTANGLE Normal 32 32 576 1088\nLINE Normal 0 80 32 80\nPIN 0 80 LEFT 36\nPINATTR PinName clk_in1\nPINATTR Polarity IN\nLINE Normal 608 80 576 80\nPIN 608 80 RIGHT 36\nPINATTR PinName clk_out1\nPINATTR Polarity OUT\nLINE Normal 608 176 576 176\nPIN 608 176 RIGHT 36\nPINATTR PinName clk_out2\nPINATTR Polarity OUT\nLINE Normal 608 976 576 976\nPIN 608 976 RIGHT 36\nPINATTR PinName locked\nPINATTR Polarity OUT\n\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock.gise",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\" standalone=\"no\" ?>\n<generated_project xmlns=\"http://www.xilinx.com/XMLSchema\" xmlns:xil_pn=\"http://www.xilinx.com/XMLSchema\">\n\n  <!--                                                          -->\n\n  <!--             For tool use only. Do not edit.              -->\n\n  <!--                                                          -->\n\n  <!-- ProjectNavigator created generated project file.         -->\n\n  <!-- For use in tracking generated file and other information -->\n\n  <!-- allowing preservation of process status.                 -->\n\n  <!--                                                          -->\n\n  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->\n\n  <version xmlns=\"http://www.xilinx.com/XMLSchema\">11.1</version>\n\n  <sourceproject xmlns=\"http://www.xilinx.com/XMLSchema\" xil_pn:fileType=\"FILE_XISE\" xil_pn:name=\"clock.xise\"/>\n\n  <files xmlns=\"http://www.xilinx.com/XMLSchema\">\n    <file xil_pn:fileType=\"FILE_ASY\" xil_pn:name=\"clock.asy\" xil_pn:origination=\"imported\"/>\n    <file xil_pn:fileType=\"FILE_VEO\" xil_pn:name=\"clock.veo\" xil_pn:origination=\"imported\"/>\n  </files>\n\n  <transforms xmlns=\"http://www.xilinx.com/XMLSchema\">\n    <transform xil_pn:end_ts=\"1457185692\" xil_pn:name=\"TRAN_copyInitialToXSTAbstractSynthesis\" xil_pn:start_ts=\"1457185692\">\n      <status xil_pn:value=\"SuccessfullyRun\"/>\n      <status xil_pn:value=\"ReadyToRun\"/>\n    </transform>\n    <transform xil_pn:end_ts=\"1457187899\" xil_pn:name=\"TRAN_schematicsToHdl\" xil_pn:prop_ck=\"4091465420829589889\" xil_pn:start_ts=\"1457187899\">\n      <status xil_pn:value=\"SuccessfullyRun\"/>\n      <status xil_pn:value=\"ReadyToRun\"/>\n    </transform>\n    <transform xil_pn:end_ts=\"1457187899\" xil_pn:name=\"TRAN_regenerateCores\" xil_pn:prop_ck=\"-6032470188061926161\" xil_pn:start_ts=\"1457187899\">\n      <status xil_pn:value=\"SuccessfullyRun\"/>\n      <status xil_pn:value=\"ReadyToRun\"/>\n    </transform>\n    <transform xil_pn:end_ts=\"1457187899\" xil_pn:name=\"TRAN_SubProjectAbstractToPreProxy\" xil_pn:start_ts=\"1457187899\">\n      <status xil_pn:value=\"SuccessfullyRun\"/>\n      <status xil_pn:value=\"ReadyToRun\"/>\n    </transform>\n    <transform xil_pn:end_ts=\"1457187899\" xil_pn:name=\"TRAN_xawsTohdl\" xil_pn:prop_ck=\"-9015061866812943677\" xil_pn:start_ts=\"1457187899\">\n      <status xil_pn:value=\"SuccessfullyRun\"/>\n      <status xil_pn:value=\"ReadyToRun\"/>\n    </transform>\n  </transforms>\n\n</generated_project>\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock.ucf",
    "content": "# file: clock.ucf\n# \n# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\n# \n# This file contains confidential and proprietary information\n# of Xilinx, Inc. and is protected under U.S. and\n# international copyright and other intellectual property\n# laws.\n# \n# DISCLAIMER\n# This disclaimer is not a license and does not grant any\n# rights to the materials distributed herewith. Except as\n# otherwise provided in a valid license issued to you by\n# Xilinx, and to the maximum extent permitted by applicable\n# law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n# (2) Xilinx shall not be liable (whether in contract or tort,\n# including negligence, or under any other theory of\n# liability) for any loss or damage of any kind or nature\n# related to, arising under or in connection with these\n# materials, including for any direct, or any indirect,\n# special, incidental, or consequential loss or damage\n# (including loss of data, profits, goodwill, or any type of\n# loss or damage suffered as a result of any action brought\n# by a third party) even if such damage or loss was\n# reasonably foreseeable or Xilinx had been advised of the\n# possibility of the same.\n# \n# CRITICAL APPLICATIONS\n# Xilinx products are not designed or intended to be fail-\n# safe, or for use in any application requiring fail-safe\n# performance, such as life-support or safety devices or\n# systems, Class III medical devices, nuclear facilities,\n# applications related to the deployment of airbags, or any\n# other applications that could lead to death, personal\n# injury, or severe property or environmental damage\n# (individually and collectively, \"Critical\n# Applications\"). Customer assumes the sole risk and\n# liability of any use of Xilinx products in Critical\n# Applications, subject only to applicable laws and\n# regulations governing limitations on product liability.\n# \n# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n# PART OF THIS FILE AT ALL TIMES.\n# \n\n# Input clock periods. These duplicate the values entered for the\n#  input clocks. You can use these to time your system\n#----------------------------------------------------------------\nNET \"CLK_IN1\" TNM_NET = \"CLK_IN1\";\nTIMESPEC \"TS_CLK_IN1\" = PERIOD \"CLK_IN1\" 10.0 ns HIGH 50% INPUT_JITTER 100.0ps;\n\n\n# FALSE PATH constraints \n\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock.v",
    "content": "// file: clock.v\n// \n// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n//----------------------------------------------------------------------------\n// User entered comments\n//----------------------------------------------------------------------------\n// None\n//\n//----------------------------------------------------------------------------\n// \"Output    Output      Phase     Duty      Pk-to-Pk        Phase\"\n// \"Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)\"\n//----------------------------------------------------------------------------\n// CLK_OUT1____10.000______0.000______50.0_____1200.000____150.000\n// CLK_OUT2____50.000______0.000______50.0______200.000____150.000\n//\n//----------------------------------------------------------------------------\n// \"Input Clock   Freq (MHz)    Input Jitter (UI)\"\n//----------------------------------------------------------------------------\n// __primary_________100.000____________0.010\n\n`timescale 1ps/1ps\n\n(* CORE_GENERATION_INFO = \"clock,clk_wiz_v3_6,{component_name=clock,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}\" *)\nmodule clock\n (// Clock in ports\n  input         CLK_IN1,\n  // Clock out ports\n  output        CLK_OUT1,\n  output        CLK_OUT2,\n  // Status and control signals\n  output        LOCKED\n );\n\n  // Input buffering\n  //------------------------------------\n  IBUFG clkin1_buf\n   (.O (clkin1),\n    .I (CLK_IN1));\n\n\n  // Clocking primitive\n  //------------------------------------\n\n  // Instantiation of the DCM primitive\n  //    * Unused inputs are tied off\n  //    * Unused outputs are labeled unused\n  wire        psdone_unused;\n  wire        locked_int;\n  wire [7:0]  status_int;\n  wire clkfb;\n  wire clk0;\n  wire clkfx;\n\n  DCM_SP\n  #(.CLKDV_DIVIDE          (5.000),\n    .CLKFX_DIVIDE          (10),\n    .CLKFX_MULTIPLY        (2),\n    .CLKIN_DIVIDE_BY_2     (\"TRUE\"),\n    .CLKIN_PERIOD          (10.0),\n    .CLKOUT_PHASE_SHIFT    (\"NONE\"),\n    .CLK_FEEDBACK          (\"1X\"),\n    .DESKEW_ADJUST         (\"SYSTEM_SYNCHRONOUS\"),\n    .PHASE_SHIFT           (0),\n    .STARTUP_WAIT          (\"FALSE\"))\n  dcm_sp_inst\n    // Input clock\n   (.CLKIN                 (clkin1),\n    .CLKFB                 (clkfb),\n    // Output clocks\n    .CLK0                  (clk0),\n    .CLK90                 (),\n    .CLK180                (),\n    .CLK270                (),\n    .CLK2X                 (),\n    .CLK2X180              (),\n    .CLKFX                 (clkfx),\n    .CLKFX180              (),\n    .CLKDV                 (),\n    // Ports for dynamic phase shift\n    .PSCLK                 (1'b0),\n    .PSEN                  (1'b0),\n    .PSINCDEC              (1'b0),\n    .PSDONE                (),\n    // Other control and status signals\n    .LOCKED                (locked_int),\n    .STATUS                (status_int),\n    .RST                   (1'b0),\n    // Unused pin- tie low\n    .DSSEN                 (1'b0));\n\n    assign LOCKED = locked_int;\n\n  // Output buffering\n  //-----------------------------------\n  assign clkfb = CLK_OUT2;\n\n  BUFG clkout1_buf\n   (.O   (CLK_OUT1),\n    .I   (clkfx));\n\n\n  BUFG clkout2_buf\n   (.O   (CLK_OUT2),\n    .I   (clk0));\n\n\n\nendmodule\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock.veo",
    "content": "// \n// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\n// \n// This file contains confidential and proprietary information\n// of Xilinx, Inc. and is protected under U.S. and\n// international copyright and other intellectual property\n// laws.\n// \n// DISCLAIMER\n// This disclaimer is not a license and does not grant any\n// rights to the materials distributed herewith. Except as\n// otherwise provided in a valid license issued to you by\n// Xilinx, and to the maximum extent permitted by applicable\n// law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND\n// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\n// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\n// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\n// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\n// (2) Xilinx shall not be liable (whether in contract or tort,\n// including negligence, or under any other theory of\n// liability) for any loss or damage of any kind or nature\n// related to, arising under or in connection with these\n// materials, including for any direct, or any indirect,\n// special, incidental, or consequential loss or damage\n// (including loss of data, profits, goodwill, or any type of\n// loss or damage suffered as a result of any action brought\n// by a third party) even if such damage or loss was\n// reasonably foreseeable or Xilinx had been advised of the\n// possibility of the same.\n// \n// CRITICAL APPLICATIONS\n// Xilinx products are not designed or intended to be fail-\n// safe, or for use in any application requiring fail-safe\n// performance, such as life-support or safety devices or\n// systems, Class III medical devices, nuclear facilities,\n// applications related to the deployment of airbags, or any\n// other applications that could lead to death, personal\n// injury, or severe property or environmental damage\n// (individually and collectively, \"Critical\n// Applications\"). Customer assumes the sole risk and\n// liability of any use of Xilinx products in Critical\n// Applications, subject only to applicable laws and\n// regulations governing limitations on product liability.\n// \n// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\n// PART OF THIS FILE AT ALL TIMES.\n// \n//----------------------------------------------------------------------------\n// User entered comments\n//----------------------------------------------------------------------------\n// None\n//\n//----------------------------------------------------------------------------\n// \"Output    Output      Phase     Duty      Pk-to-Pk        Phase\"\n// \"Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)\"\n//----------------------------------------------------------------------------\n// CLK_OUT1____10.000______0.000______50.0_____1200.000____150.000\n// CLK_OUT2____50.000______0.000______50.0______200.000____150.000\n//\n//----------------------------------------------------------------------------\n// \"Input Clock   Freq (MHz)    Input Jitter (UI)\"\n//----------------------------------------------------------------------------\n// __primary_________100.000____________0.010\n\n// The following must be inserted into your Verilog file for this\n// core to be instantiated. Change the instance name and port connections\n// (in parentheses) to your own signal names.\n\n//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG\n\n  clock instance_name\n   (// Clock in ports\n    .CLK_IN1(CLK_IN1),      // IN\n    // Clock out ports\n    .CLK_OUT1(CLK_OUT1),     // OUT\n    .CLK_OUT2(CLK_OUT2),     // OUT\n    // Status and control signals\n    .LOCKED(LOCKED));      // OUT\n// INST_TAG_END ------ End INSTANTIATION Template ---------\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock.xco",
    "content": "##############################################################\n#\n# Xilinx Core Generator version 14.7\n# Date: Sat Mar 05 15:25:10 2016\n#\n##############################################################\n#\n#  This file contains the customisation parameters for a\n#  Xilinx CORE Generator IP GUI. It is strongly recommended\n#  that you do not manually alter this file as it may cause\n#  unexpected and unsupported behavior.\n#\n##############################################################\n#\n#  Generated from component: xilinx.com:ip:clk_wiz:3.6\n#\n##############################################################\n#\n# BEGIN Project Options\nSET addpads = false\nSET asysymbol = true\nSET busformat = BusFormatAngleBracketNotRipped\nSET createndf = false\nSET designentry = Verilog\nSET device = xc6slx16\nSET devicefamily = spartan6\nSET flowvendor = Other\nSET formalverification = false\nSET foundationsym = false\nSET implementationfiletype = Ngc\nSET package = csg324\nSET removerpms = false\nSET simulationfiles = Behavioral\nSET speedgrade = -2\nSET verilogsim = true\nSET vhdlsim = false\n# END Project Options\n# BEGIN Select\nSELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6\n# END Select\n# BEGIN Parameters\nCSET calc_done=DONE\nCSET clk_in_sel_port=CLK_IN_SEL\nCSET clk_out1_port=CLK_OUT1\nCSET clk_out1_use_fine_ps_gui=false\nCSET clk_out2_port=CLK_OUT2\nCSET clk_out2_use_fine_ps_gui=false\nCSET clk_out3_port=CLK_OUT3\nCSET clk_out3_use_fine_ps_gui=false\nCSET clk_out4_port=CLK_OUT4\nCSET clk_out4_use_fine_ps_gui=false\nCSET clk_out5_port=CLK_OUT5\nCSET clk_out5_use_fine_ps_gui=false\nCSET clk_out6_port=CLK_OUT6\nCSET clk_out6_use_fine_ps_gui=false\nCSET clk_out7_port=CLK_OUT7\nCSET clk_out7_use_fine_ps_gui=false\nCSET clk_valid_port=CLK_VALID\nCSET clkfb_in_n_port=CLKFB_IN_N\nCSET clkfb_in_p_port=CLKFB_IN_P\nCSET clkfb_in_port=CLKFB_IN\nCSET clkfb_in_signaling=SINGLE\nCSET clkfb_out_n_port=CLKFB_OUT_N\nCSET clkfb_out_p_port=CLKFB_OUT_P\nCSET clkfb_out_port=CLKFB_OUT\nCSET clkfb_stopped_port=CLKFB_STOPPED\nCSET clkin1_jitter_ps=100.0\nCSET clkin1_ui_jitter=0.010\nCSET clkin2_jitter_ps=100.0\nCSET clkin2_ui_jitter=0.010\nCSET clkout1_drives=BUFG\nCSET clkout1_requested_duty_cycle=50.000\nCSET clkout1_requested_out_freq=10\nCSET clkout1_requested_phase=0.000\nCSET clkout2_drives=BUFG\nCSET clkout2_requested_duty_cycle=50.000\nCSET clkout2_requested_out_freq=50\nCSET clkout2_requested_phase=0.000\nCSET clkout2_used=true\nCSET clkout3_drives=BUFG\nCSET clkout3_requested_duty_cycle=50.000\nCSET clkout3_requested_out_freq=100\nCSET clkout3_requested_phase=0.000\nCSET clkout3_used=false\nCSET clkout4_drives=BUFG\nCSET clkout4_requested_duty_cycle=50.000\nCSET clkout4_requested_out_freq=100.000\nCSET clkout4_requested_phase=0.000\nCSET clkout4_used=false\nCSET clkout5_drives=BUFG\nCSET clkout5_requested_duty_cycle=50.000\nCSET clkout5_requested_out_freq=100.000\nCSET clkout5_requested_phase=0.000\nCSET clkout5_used=false\nCSET clkout6_drives=BUFG\nCSET clkout6_requested_duty_cycle=50.000\nCSET clkout6_requested_out_freq=100.000\nCSET clkout6_requested_phase=0.000\nCSET clkout6_used=false\nCSET clkout7_drives=BUFG\nCSET clkout7_requested_duty_cycle=50.000\nCSET clkout7_requested_out_freq=100.000\nCSET clkout7_requested_phase=0.000\nCSET clkout7_used=false\nCSET clock_mgr_type=AUTO\nCSET component_name=clock\nCSET daddr_port=DADDR\nCSET dclk_port=DCLK\nCSET dcm_clk_feedback=1X\nCSET dcm_clk_out1_port=CLKFX\nCSET dcm_clk_out2_port=CLK0\nCSET dcm_clk_out3_port=CLK2X\nCSET dcm_clk_out4_port=CLK0\nCSET dcm_clk_out5_port=CLK0\nCSET dcm_clk_out6_port=CLK0\nCSET dcm_clkdv_divide=5.0\nCSET dcm_clkfx_divide=10\nCSET dcm_clkfx_multiply=2\nCSET dcm_clkgen_clk_out1_port=CLKFX\nCSET dcm_clkgen_clk_out2_port=CLKFX\nCSET dcm_clkgen_clk_out3_port=CLKFX\nCSET dcm_clkgen_clkfx_divide=1\nCSET dcm_clkgen_clkfx_md_max=0.000\nCSET dcm_clkgen_clkfx_multiply=4\nCSET dcm_clkgen_clkfxdv_divide=2\nCSET dcm_clkgen_clkin_period=10.000\nCSET dcm_clkgen_notes=None\nCSET dcm_clkgen_spread_spectrum=NONE\nCSET dcm_clkgen_startup_wait=false\nCSET dcm_clkin_divide_by_2=true\nCSET dcm_clkin_period=10.000\nCSET dcm_clkout_phase_shift=NONE\nCSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS\nCSET dcm_notes=None\nCSET dcm_phase_shift=0\nCSET dcm_pll_cascade=NONE\nCSET dcm_startup_wait=false\nCSET den_port=DEN\nCSET din_port=DIN\nCSET dout_port=DOUT\nCSET drdy_port=DRDY\nCSET dwe_port=DWE\nCSET feedback_source=FDBK_AUTO\nCSET in_freq_units=Units_MHz\nCSET in_jitter_units=Units_UI\nCSET input_clk_stopped_port=INPUT_CLK_STOPPED\nCSET jitter_options=UI\nCSET jitter_sel=No_Jitter\nCSET locked_port=LOCKED\nCSET mmcm_bandwidth=OPTIMIZED\nCSET mmcm_clkfbout_mult_f=4.000\nCSET mmcm_clkfbout_phase=0.000\nCSET mmcm_clkfbout_use_fine_ps=false\nCSET mmcm_clkin1_period=10.000\nCSET mmcm_clkin2_period=10.000\nCSET mmcm_clkout0_divide_f=4.000\nCSET mmcm_clkout0_duty_cycle=0.500\nCSET mmcm_clkout0_phase=0.000\nCSET mmcm_clkout0_use_fine_ps=false\nCSET mmcm_clkout1_divide=1\nCSET mmcm_clkout1_duty_cycle=0.500\nCSET mmcm_clkout1_phase=0.000\nCSET mmcm_clkout1_use_fine_ps=false\nCSET mmcm_clkout2_divide=1\nCSET mmcm_clkout2_duty_cycle=0.500\nCSET mmcm_clkout2_phase=0.000\nCSET mmcm_clkout2_use_fine_ps=false\nCSET mmcm_clkout3_divide=1\nCSET mmcm_clkout3_duty_cycle=0.500\nCSET mmcm_clkout3_phase=0.000\nCSET mmcm_clkout3_use_fine_ps=false\nCSET mmcm_clkout4_cascade=false\nCSET mmcm_clkout4_divide=1\nCSET mmcm_clkout4_duty_cycle=0.500\nCSET mmcm_clkout4_phase=0.000\nCSET mmcm_clkout4_use_fine_ps=false\nCSET mmcm_clkout5_divide=1\nCSET mmcm_clkout5_duty_cycle=0.500\nCSET mmcm_clkout5_phase=0.000\nCSET mmcm_clkout5_use_fine_ps=false\nCSET mmcm_clkout6_divide=1\nCSET mmcm_clkout6_duty_cycle=0.500\nCSET mmcm_clkout6_phase=0.000\nCSET mmcm_clkout6_use_fine_ps=false\nCSET mmcm_clock_hold=false\nCSET mmcm_compensation=ZHOLD\nCSET mmcm_divclk_divide=1\nCSET mmcm_notes=None\nCSET mmcm_ref_jitter1=0.010\nCSET mmcm_ref_jitter2=0.010\nCSET mmcm_startup_wait=false\nCSET num_out_clks=2\nCSET override_dcm=false\nCSET override_dcm_clkgen=false\nCSET override_mmcm=false\nCSET override_pll=false\nCSET platform=nt64\nCSET pll_bandwidth=OPTIMIZED\nCSET pll_clk_feedback=CLKFBOUT\nCSET pll_clkfbout_mult=4\nCSET pll_clkfbout_phase=0.000\nCSET pll_clkin_period=10.0\nCSET pll_clkout0_divide=40\nCSET pll_clkout0_duty_cycle=0.500\nCSET pll_clkout0_phase=0.000\nCSET pll_clkout1_divide=80\nCSET pll_clkout1_duty_cycle=0.500\nCSET pll_clkout1_phase=0.000\nCSET pll_clkout2_divide=7\nCSET pll_clkout2_duty_cycle=0.500\nCSET pll_clkout2_phase=0.000\nCSET pll_clkout3_divide=1\nCSET pll_clkout3_duty_cycle=0.500\nCSET pll_clkout3_phase=0.000\nCSET pll_clkout4_divide=1\nCSET pll_clkout4_duty_cycle=0.500\nCSET pll_clkout4_phase=0.000\nCSET pll_clkout5_divide=1\nCSET pll_clkout5_duty_cycle=0.500\nCSET pll_clkout5_phase=0.000\nCSET pll_compensation=SYSTEM_SYNCHRONOUS\nCSET pll_divclk_divide=1\nCSET pll_notes=None\nCSET pll_ref_jitter=0.010\nCSET power_down_port=POWER_DOWN\nCSET prim_in_freq=100.000\nCSET prim_in_jitter=0.010\nCSET prim_source=Single_ended_clock_capable_pin\nCSET primary_port=CLK_IN1\nCSET primitive=MMCM\nCSET primtype_sel=PLL_BASE\nCSET psclk_port=PSCLK\nCSET psdone_port=PSDONE\nCSET psen_port=PSEN\nCSET psincdec_port=PSINCDEC\nCSET relative_inclk=REL_PRIMARY\nCSET reset_port=RESET\nCSET secondary_in_freq=100.000\nCSET secondary_in_jitter=0.010\nCSET secondary_port=CLK_IN2\nCSET secondary_source=Single_ended_clock_capable_pin\nCSET ss_mod_freq=250\nCSET ss_mode=CENTER_HIGH\nCSET status_port=STATUS\nCSET summary_strings=empty\nCSET use_clk_valid=false\nCSET use_clkfb_stopped=false\nCSET use_dyn_phase_shift=false\nCSET use_dyn_reconfig=false\nCSET use_freeze=false\nCSET use_freq_synth=true\nCSET use_inclk_stopped=false\nCSET use_inclk_switchover=false\nCSET use_locked=true\nCSET use_max_i_jitter=false\nCSET use_min_o_jitter=false\nCSET use_min_power=false\nCSET use_phase_alignment=true\nCSET use_power_down=false\nCSET use_reset=false\nCSET use_spread_spectrum=false\nCSET use_spread_spectrum_1=false\nCSET use_status=false\n# END Parameters\n# BEGIN Extra information\nMISC pkg_timestamp=2012-05-10T12:44:55Z\n# END Extra information\nGENERATE\n# CRC: de7f6af0\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/clock.xise",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\" standalone=\"no\" ?>\n<project xmlns=\"http://www.xilinx.com/XMLSchema\" xmlns:xil_pn=\"http://www.xilinx.com/XMLSchema\">\n\n  <header>\n    <!-- ISE source project file created by Project Navigator.             -->\n    <!--                                                                   -->\n    <!-- This file contains project source information including a list of -->\n    <!-- project source files, project and process properties.  This file, -->\n    <!-- along with the project source files, is sufficient to open and    -->\n    <!-- implement in ISE Project Navigator.                               -->\n    <!--                                                                   -->\n    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->\n  </header>\n\n  <version xil_pn:ise_version=\"14.7\" xil_pn:schema_version=\"2\"/>\n\n  <files>\n    <file xil_pn:name=\"clock.ucf\" xil_pn:type=\"FILE_UCF\">\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"0\"/>\n    </file>\n    <file xil_pn:name=\"clock.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"3\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"1\"/>\n      <association xil_pn:name=\"PostMapSimulation\" xil_pn:seqID=\"3\"/>\n      <association xil_pn:name=\"PostRouteSimulation\" xil_pn:seqID=\"3\"/>\n      <association xil_pn:name=\"PostTranslateSimulation\" xil_pn:seqID=\"3\"/>\n    </file>\n  </files>\n\n  <properties>\n    <property xil_pn:name=\"Auto Implementation Top\" xil_pn:value=\"false\" xil_pn:valueState=\"non-default\"/>\n    <property xil_pn:name=\"Device\" xil_pn:value=\"xc6slx16\" xil_pn:valueState=\"non-default\"/>\n    <property xil_pn:name=\"Device Family\" xil_pn:value=\"Spartan6\" xil_pn:valueState=\"non-default\"/>\n    <property xil_pn:name=\"Enable Internal Done Pipe\" xil_pn:value=\"true\" xil_pn:valueState=\"non-default\"/>\n    <property xil_pn:name=\"Implementation Stop View\" xil_pn:value=\"PreSynthesis\" xil_pn:valueState=\"non-default\"/>\n    <property xil_pn:name=\"Implementation Top\" xil_pn:value=\"Module|clock\" xil_pn:valueState=\"non-default\"/>\n    <property xil_pn:name=\"Implementation Top File\" xil_pn:value=\"clock.v\" xil_pn:valueState=\"non-default\"/>\n    <property xil_pn:name=\"Implementation Top Instance Path\" xil_pn:value=\"/clock\" xil_pn:valueState=\"non-default\"/>\n    <property xil_pn:name=\"Package\" xil_pn:value=\"csg324\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"Preferred Language\" xil_pn:value=\"Verilog\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"Project Generator\" xil_pn:value=\"CoreGen\" xil_pn:valueState=\"non-default\"/>\n    <property xil_pn:name=\"Property Specification in Project File\" xil_pn:value=\"Store all values\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"Simulator\" xil_pn:value=\"ISim (VHDL/Verilog)\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"Speed Grade\" xil_pn:value=\"-2\" xil_pn:valueState=\"non-default\"/>\n    <property xil_pn:name=\"Synthesis Tool\" xil_pn:value=\"XST (VHDL/Verilog)\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"Top-Level Source Type\" xil_pn:value=\"HDL\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"Working Directory\" xil_pn:value=\".\" xil_pn:valueState=\"non-default\"/>\n    <!--                                                                                  -->\n    <!-- The following properties are for internal use only. These should not be modified.-->\n    <!--                                                                                  -->\n    <property xil_pn:name=\"PROP_DesignName\" xil_pn:value=\"clock\" xil_pn:valueState=\"non-default\"/>\n    <property xil_pn:name=\"PROP_DevFamilyPMName\" xil_pn:value=\"spartan6\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"PROP_intProjectCreationTimestamp\" xil_pn:value=\"2016-03-05T09:25:25\" xil_pn:valueState=\"non-default\"/>\n    <property xil_pn:name=\"PROP_intWbtProjectID\" xil_pn:value=\"A6C54BFF8CB6403BA660F792F2855E16\" xil_pn:valueState=\"non-default\"/>\n    <property xil_pn:name=\"PROP_intWorkingDirLocWRTProjDir\" xil_pn:value=\"Same\" xil_pn:valueState=\"non-default\"/>\n    <property xil_pn:name=\"PROP_intWorkingDirUsed\" xil_pn:value=\"No\" xil_pn:valueState=\"non-default\"/>\n  </properties>\n\n  <bindings>\n    <binding xil_pn:location=\"/clock\" xil_pn:name=\"clock.ucf\"/>\n  </bindings>\n\n  <libraries/>\n\n  <autoManagedFiles>\n    <!-- The following files are identified by `include statements in verilog -->\n    <!-- source files and are automatically managed by Project Navigator.     -->\n    <!--                                                                      -->\n    <!-- Do not hand-edit this section, as it will be overwritten when the    -->\n    <!-- project is analyzed based on files automatically identified as       -->\n    <!-- include files.                                                       -->\n  </autoManagedFiles>\n\n</project>\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/coregen.cgp",
    "content": "SET busformat = BusFormatAngleBracketNotRipped\nSET designentry = Verilog\nSET device = xc6slx16\nSET devicefamily = spartan6\nSET flowvendor = Other\nSET package = csg324\nSET speedgrade = -2\nSET verilogsim = true\nSET vhdlsim = false\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/ila.asy",
    "content": "Version 4\nSymbolType BLOCK\nTEXT 32 32 LEFT 4 ila\nRECTANGLE Normal 32 32 288 704\nLINE Wide 0 80 32 80\nPIN 0 80 LEFT 36\nPINATTR PinName control[35:0]\nPINATTR Polarity IN\nLINE Normal 0 112 32 112\nPIN 0 112 LEFT 36\nPINATTR PinName clk\nPINATTR Polarity IN\nLINE Wide 0 144 32 144\nPIN 0 144 LEFT 36\nPINATTR PinName data[7:0]\nPINATTR Polarity IN\nLINE Wide 0 176 32 176\nPIN 0 176 LEFT 36\nPINATTR PinName trig0[7:0]\nPINATTR Polarity IN\n\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/ila.cdc",
    "content": "#ChipScope Core Generator Project File Version 3.0\n#Tue Feb 23 19:15:38 Central Standard Time 2016\nSignalExport.clockChannel=CLK\nSignalExport.dataChannel<0000>=DATA[0]\nSignalExport.dataChannel<0001>=DATA[1]\nSignalExport.dataChannel<0002>=DATA[2]\nSignalExport.dataChannel<0003>=DATA[3]\nSignalExport.dataChannel<0004>=DATA[4]\nSignalExport.dataChannel<0005>=DATA[5]\nSignalExport.dataChannel<0006>=DATA[6]\nSignalExport.dataChannel<0007>=DATA[7]\nSignalExport.dataEqualsTrigger=false\nSignalExport.dataPortWidth=8\nSignalExport.triggerChannel<0000><0000>=TRIG0[0]\nSignalExport.triggerChannel<0000><0001>=TRIG0[1]\nSignalExport.triggerChannel<0000><0002>=TRIG0[2]\nSignalExport.triggerChannel<0000><0003>=TRIG0[3]\nSignalExport.triggerChannel<0000><0004>=TRIG0[4]\nSignalExport.triggerChannel<0000><0005>=TRIG0[5]\nSignalExport.triggerChannel<0000><0006>=TRIG0[6]\nSignalExport.triggerChannel<0000><0007>=TRIG0[7]\nSignalExport.triggerPort<0000>.name=TRIG0\nSignalExport.triggerPortCount=1\nSignalExport.triggerPortIsData<0000>=false\nSignalExport.triggerPortWidth<0000>=8\nSignalExport.type=ila\n\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/ila.constraints/ila.ucf",
    "content": "#\n# Clock constraints\n#\nNET \"CLK\" TNM_NET = D_CLK ;\nINST \"U0/*/U_STAT/U_DIRTY_LDC\" TNM = D2_CLK;\nTIMESPEC TS_D2_TO_T2_ila = FROM D2_CLK TO \"FFS\" TIG;\nTIMESPEC TS_J2_TO_D2_ila = FROM \"FFS\" TO D2_CLK TIG;\nTIMESPEC TS_J3_TO_D2_ila = FROM \"FFS\" TO D2_CLK TIG;\nTIMESPEC TS_J4_TO_D2_ila = FROM \"FFS\" TO D2_CLK TIG;\n\n#\n# Input keep/save net constraints\n#\nNET \"TRIG0<*\" S;\nNET \"TRIG0<*\" KEEP;\nNET \"DATA<*\" S;\nNET \"DATA<*\" KEEP;\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/ila.constraints/ila.xdc",
    "content": "#\n# Clock constraints\n#\nset_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]]\nset_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]\nset_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/ila.gise",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\" standalone=\"no\" ?>\n<generated_project xmlns=\"http://www.xilinx.com/XMLSchema\" xmlns:xil_pn=\"http://www.xilinx.com/XMLSchema\">\n\n  <!--                                                          -->\n\n  <!--             For tool use only. Do not edit.              -->\n\n  <!--                                                          -->\n\n  <!-- ProjectNavigator created generated project file.         -->\n\n  <!-- For use in tracking generated file and other information -->\n\n  <!-- allowing preservation of process status.                 -->\n\n  <!--                                                          -->\n\n  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->\n\n  <version xmlns=\"http://www.xilinx.com/XMLSchema\">11.1</version>\n\n  <sourceproject xmlns=\"http://www.xilinx.com/XMLSchema\" xil_pn:fileType=\"FILE_XISE\" xil_pn:name=\"ila.xise\"/>\n\n  <files xmlns=\"http://www.xilinx.com/XMLSchema\">\n    <file xil_pn:fileType=\"FILE_ASY\" xil_pn:name=\"ila.asy\" xil_pn:origination=\"imported\"/>\n    <file xil_pn:fileType=\"FILE_VEO\" xil_pn:name=\"ila.veo\" xil_pn:origination=\"imported\"/>\n  </files>\n\n  <transforms xmlns=\"http://www.xilinx.com/XMLSchema\"/>\n\n</generated_project>\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/ila.ncf",
    "content": "#\n# Clock constraints\n#\nNET \"CLK\" TNM_NET = D_CLK ;\nINST \"U0/*/U_STAT/U_DIRTY_LDC\" TNM = D2_CLK;\nTIMESPEC TS_D2_TO_T2 = FROM D2_CLK TO \"FFS\" TIG;\nTIMESPEC TS_J2_TO_D2 = FROM \"FFS\" TO D2_CLK TIG;\nTIMESPEC TS_J3_TO_D2 = FROM \"FFS\" TO D2_CLK TIG;\nTIMESPEC TS_J4_TO_D2 = FROM \"FFS\" TO D2_CLK TIG;\n\n#\n# Input keep/save net constraints\n#\nNET \"TRIG0<*\" S;\nNET \"TRIG0<*\" KEEP;\nNET \"DATA<*\" S;\nNET \"DATA<*\" KEEP;\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/ila.ngc",
    "content": "XILINX-XDB 0.1 STUB 0.1 ASCII\nXILINX-XDM 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  },
  {
    "path": "host/basic_nexys3/ipcore_dir/ila.sym",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<symbol version=\"7\" name=\"ila\">\n    <symboltype>BLOCK</symboltype>\n    <timestamp>2016-2-24T1:15:39</timestamp>\n    <pin polarity=\"Input\" x=\"0\" y=\"80\" name=\"control[35:0]\" />\n    <pin polarity=\"Input\" x=\"0\" y=\"112\" name=\"clk\" />\n    <pin polarity=\"Input\" x=\"0\" y=\"144\" name=\"data[7:0]\" />\n    <pin polarity=\"Input\" x=\"0\" y=\"176\" name=\"trig0[7:0]\" />\n    <graph>\n        <text style=\"fontsize:40;fontname:Arial\" x=\"32\" y=\"32\">ila</text>\n        <rect width=\"256\" x=\"32\" y=\"32\" height=\"672\" />\n        <line x2=\"32\" y1=\"80\" y2=\"80\" style=\"linewidth:W\" x1=\"0\" />\n        <attrtext style=\"fontsize:24;fontname:Arial\" attrname=\"PinName\" x=\"36\" y=\"80\" type=\"pin control[35:0]\" />\n        <line x2=\"32\" y1=\"112\" y2=\"112\" x1=\"0\" />\n        <attrtext style=\"fontsize:24;fontname:Arial\" attrname=\"PinName\" x=\"36\" y=\"112\" type=\"pin clk\" />\n        <line x2=\"32\" y1=\"144\" y2=\"144\" style=\"linewidth:W\" x1=\"0\" />\n        <attrtext style=\"fontsize:24;fontname:Arial\" attrname=\"PinName\" x=\"36\" y=\"144\" type=\"pin data[7:0]\" />\n        <line x2=\"32\" y1=\"176\" y2=\"176\" style=\"linewidth:W\" x1=\"0\" />\n        <attrtext style=\"fontsize:24;fontname:Arial\" attrname=\"PinName\" x=\"36\" y=\"176\" type=\"pin trig0[7:0]\" />\n    </graph>\n</symbol>\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/ila.ucf",
    "content": "#\n# Clock constraints\n#\nNET \"CLK\" TNM_NET = D_CLK ;\nINST \"U0/*/U_STAT/U_DIRTY_LDC\" TNM = D2_CLK;\nTIMESPEC TS_D2_TO_T2_ila = FROM D2_CLK TO \"FFS\" TIG;\nTIMESPEC TS_J2_TO_D2_ila = FROM \"FFS\" TO D2_CLK TIG;\nTIMESPEC TS_J3_TO_D2_ila = FROM \"FFS\" TO D2_CLK TIG;\nTIMESPEC TS_J4_TO_D2_ila = FROM \"FFS\" TO D2_CLK TIG;\n\n#\n# Input keep/save net constraints\n#\nNET \"TRIG0<*\" S;\nNET \"TRIG0<*\" KEEP;\nNET \"DATA<*\" S;\nNET \"DATA<*\" KEEP;\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/ila.v",
    "content": "///////////////////////////////////////////////////////////////////////////////\n// Copyright (c) 2016 Xilinx, Inc.\n// All Rights Reserved\n///////////////////////////////////////////////////////////////////////////////\n//   ____  ____\n//  /   /\\/   /\n// /___/  \\  /    Vendor     : Xilinx\n// \\   \\   \\/     Version    : 14.7\n//  \\   \\         Application: Xilinx CORE Generator\n//  /   /         Filename   : ila.v\n// /___/   /\\     Timestamp  : Tue Feb 23 19:15:38 Central Standard Time 2016\n// \\   \\  /  \\\n//  \\___\\/\\___\\\n//\n// Design Name: Verilog Synthesis Wrapper\n///////////////////////////////////////////////////////////////////////////////\n// This wrapper is used to integrate with Project Navigator and PlanAhead\n\n`timescale 1ns/1ps\n\nmodule ila(\n    CONTROL,\n    CLK,\n    DATA,\n    TRIG0) /* synthesis syn_black_box syn_noprune=1 */;\n\n\ninout [35 : 0] CONTROL;\ninput CLK;\ninput [7 : 0] DATA;\ninput [7 : 0] TRIG0;\n\nendmodule\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/ila.veo",
    "content": "///////////////////////////////////////////////////////////////////////////////\n// Copyright (c) 2016 Xilinx, Inc.\n// All Rights Reserved\n///////////////////////////////////////////////////////////////////////////////\n//   ____  ____\n//  /   /\\/   /\n// /___/  \\  /    Vendor     : Xilinx\n// \\   \\   \\/     Version    : 14.7\n//  \\   \\         Application: Xilinx CORE Generator\n//  /   /         Filename   : ila.veo\n// /___/   /\\     Timestamp  : Tue Feb 23 19:15:38 Central Standard Time 2016\n// \\   \\  /  \\\n//  \\___\\/\\___\\\n//\n// Design Name: ISE Instantiation template\n///////////////////////////////////////////////////////////////////////////////\n\n// The following must be inserted into your Verilog file for this\n// core to be instantiated. Change the instance name and port connections\n// (in parentheses) to your own signal names.\n\n//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG\nila YourInstanceName (\n    .CONTROL(CONTROL), // INOUT BUS [35:0]\n    .CLK(CLK), // IN\n    .DATA(DATA), // IN BUS [7:0]\n    .TRIG0(TRIG0) // IN BUS [7:0]\n);\n\n// INST_TAG_END ------ End INSTANTIATION Template ---------\n\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/ila.xco",
    "content": "##############################################################\n#\n# Xilinx Core Generator version 14.7\n# Date: Wed Feb 24 01:14:14 2016\n#\n##############################################################\n#\n#  This file contains the customisation parameters for a\n#  Xilinx CORE Generator IP GUI. It is strongly recommended\n#  that you do not manually alter this file as it may cause\n#  unexpected and unsupported behavior.\n#\n##############################################################\n#\n#  Generated from component: xilinx.com:ip:chipscope_ila:1.05.a\n#\n##############################################################\n#\n# BEGIN Project Options\nSET addpads = false\nSET asysymbol = true\nSET busformat = BusFormatAngleBracketNotRipped\nSET createndf = false\nSET designentry = Verilog\nSET device = xc6slx16\nSET devicefamily = spartan6\nSET flowvendor = Other\nSET formalverification = false\nSET foundationsym = false\nSET implementationfiletype = Ngc\nSET package = csg324\nSET removerpms = false\nSET simulationfiles = Structural\nSET speedgrade = -2\nSET verilogsim = true\nSET vhdlsim = false\n# END Project Options\n# BEGIN Select\nSELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a\n# END Select\n# BEGIN Parameters\nCSET check_bramcount=false\nCSET component_name=ila\nCSET constraint_type=external\nCSET counter_width_1=Disabled\nCSET counter_width_10=Disabled\nCSET counter_width_11=Disabled\nCSET counter_width_12=Disabled\nCSET counter_width_13=Disabled\nCSET counter_width_14=Disabled\nCSET counter_width_15=Disabled\nCSET counter_width_16=Disabled\nCSET counter_width_2=Disabled\nCSET counter_width_3=Disabled\nCSET counter_width_4=Disabled\nCSET counter_width_5=Disabled\nCSET counter_width_6=Disabled\nCSET counter_width_7=Disabled\nCSET counter_width_8=Disabled\nCSET counter_width_9=Disabled\nCSET data_port_width=8\nCSET data_same_as_trigger=false\nCSET disable_save_keep=false\nCSET enable_storage_qualification=true\nCSET enable_trigger_output_port=false\nCSET example_design=false\nCSET exclude_from_data_storage_1=true\nCSET exclude_from_data_storage_10=true\nCSET exclude_from_data_storage_11=true\nCSET exclude_from_data_storage_12=true\nCSET exclude_from_data_storage_13=true\nCSET exclude_from_data_storage_14=true\nCSET exclude_from_data_storage_15=true\nCSET exclude_from_data_storage_16=true\nCSET exclude_from_data_storage_2=true\nCSET exclude_from_data_storage_3=true\nCSET exclude_from_data_storage_4=true\nCSET exclude_from_data_storage_5=true\nCSET exclude_from_data_storage_6=true\nCSET exclude_from_data_storage_7=true\nCSET exclude_from_data_storage_8=true\nCSET exclude_from_data_storage_9=true\nCSET match_type_1=basic_with_edges\nCSET match_type_10=basic_with_edges\nCSET match_type_11=basic_with_edges\nCSET match_type_12=basic_with_edges\nCSET match_type_13=basic_with_edges\nCSET match_type_14=basic_with_edges\nCSET match_type_15=basic_with_edges\nCSET match_type_16=basic_with_edges\nCSET match_type_2=basic_with_edges\nCSET match_type_3=basic_with_edges\nCSET match_type_4=basic_with_edges\nCSET match_type_5=basic_with_edges\nCSET match_type_6=basic_with_edges\nCSET match_type_7=basic_with_edges\nCSET match_type_8=basic_with_edges\nCSET match_type_9=basic_with_edges\nCSET match_units_1=1\nCSET match_units_10=1\nCSET match_units_11=1\nCSET match_units_12=1\nCSET match_units_13=1\nCSET match_units_14=1\nCSET match_units_15=1\nCSET match_units_16=1\nCSET match_units_2=1\nCSET match_units_3=1\nCSET match_units_4=1\nCSET match_units_5=1\nCSET match_units_6=1\nCSET match_units_7=1\nCSET match_units_8=1\nCSET match_units_9=1\nCSET max_sequence_levels=1\nCSET number_of_trigger_ports=1\nCSET sample_data_depth=1024\nCSET sample_on=Rising\nCSET trigger_port_width_1=8\nCSET trigger_port_width_10=8\nCSET trigger_port_width_11=8\nCSET trigger_port_width_12=8\nCSET trigger_port_width_13=8\nCSET trigger_port_width_14=8\nCSET trigger_port_width_15=8\nCSET trigger_port_width_16=8\nCSET trigger_port_width_2=8\nCSET trigger_port_width_3=8\nCSET trigger_port_width_4=8\nCSET trigger_port_width_5=8\nCSET trigger_port_width_6=8\nCSET trigger_port_width_7=8\nCSET trigger_port_width_8=8\nCSET trigger_port_width_9=8\nCSET use_rpms=false\n# END Parameters\n# BEGIN Extra information\nMISC pkg_timestamp=2013-10-13T14:13:15Z\n# END Extra information\nGENERATE\n# CRC: 14648912\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/ila.xdc",
    "content": "#\n# Clock constraints\n#\nset_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]]\nset_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]\nset_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/ila.xise",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\" standalone=\"no\" ?>\n<project xmlns=\"http://www.xilinx.com/XMLSchema\" xmlns:xil_pn=\"http://www.xilinx.com/XMLSchema\">\n\n  <header>\n    <!-- ISE source project file created by Project Navigator.             -->\n    <!--                                                                   -->\n    <!-- This file contains project source information including a list of -->\n    <!-- project source files, project and process properties.  This file, -->\n    <!-- along with the project source files, is sufficient to open and    -->\n    <!-- implement in ISE Project Navigator.                               -->\n    <!--                                                                   -->\n    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->\n  </header>\n\n  <version xil_pn:ise_version=\"14.7\" xil_pn:schema_version=\"2\"/>\n\n  <files>\n    <file xil_pn:name=\"ila.ngc\" xil_pn:type=\"FILE_NGC\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"2\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"2\"/>\n    </file>\n    <file xil_pn:name=\"ila.v\" xil_pn:type=\"FILE_VERILOG\">\n      <association xil_pn:name=\"BehavioralSimulation\" xil_pn:seqID=\"3\"/>\n      <association xil_pn:name=\"Implementation\" xil_pn:seqID=\"3\"/>\n      <association xil_pn:name=\"PostMapSimulation\" xil_pn:seqID=\"3\"/>\n      <association xil_pn:name=\"PostRouteSimulation\" xil_pn:seqID=\"3\"/>\n      <association xil_pn:name=\"PostTranslateSimulation\" xil_pn:seqID=\"3\"/>\n    </file>\n  </files>\n\n  <properties>\n    <property xil_pn:name=\"Auto Implementation Top\" xil_pn:value=\"false\" xil_pn:valueState=\"non-default\"/>\n    <property xil_pn:name=\"Device\" xil_pn:value=\"xc6slx16\" xil_pn:valueState=\"non-default\"/>\n    <property xil_pn:name=\"Device Family\" xil_pn:value=\"Spartan6\" xil_pn:valueState=\"non-default\"/>\n    <property xil_pn:name=\"Enable Internal Done Pipe\" xil_pn:value=\"true\" xil_pn:valueState=\"non-default\"/>\n    <property xil_pn:name=\"Implementation Stop View\" xil_pn:value=\"PreSynthesis\" xil_pn:valueState=\"non-default\"/>\n    <property xil_pn:name=\"Implementation Top\" xil_pn:value=\"Module|ila\" xil_pn:valueState=\"non-default\"/>\n    <property xil_pn:name=\"Implementation Top File\" xil_pn:value=\"ila.ngc\" xil_pn:valueState=\"non-default\"/>\n    <property xil_pn:name=\"Implementation Top Instance Path\" xil_pn:value=\"/ila\" xil_pn:valueState=\"non-default\"/>\n    <property xil_pn:name=\"Package\" xil_pn:value=\"csg324\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"Preferred Language\" xil_pn:value=\"Verilog\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"Project Generator\" xil_pn:value=\"CoreGen\" xil_pn:valueState=\"non-default\"/>\n    <property xil_pn:name=\"Property Specification in Project File\" xil_pn:value=\"Store all values\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"Simulator\" xil_pn:value=\"ISim (VHDL/Verilog)\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"Speed Grade\" xil_pn:value=\"-2\" xil_pn:valueState=\"non-default\"/>\n    <property xil_pn:name=\"Synthesis Tool\" xil_pn:value=\"XST (VHDL/Verilog)\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"Top-Level Source Type\" xil_pn:value=\"HDL\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"Working Directory\" xil_pn:value=\".\" xil_pn:valueState=\"non-default\"/>\n    <!--                                                                                  -->\n    <!-- The following properties are for internal use only. These should not be modified.-->\n    <!--                                                                                  -->\n    <property xil_pn:name=\"PROP_DesignName\" xil_pn:value=\"ila\" xil_pn:valueState=\"non-default\"/>\n    <property xil_pn:name=\"PROP_DevFamilyPMName\" xil_pn:value=\"spartan6\" xil_pn:valueState=\"default\"/>\n    <property xil_pn:name=\"PROP_intProjectCreationTimestamp\" xil_pn:value=\"2016-02-23T19:15:40\" xil_pn:valueState=\"non-default\"/>\n    <property xil_pn:name=\"PROP_intWbtProjectID\" xil_pn:value=\"C2DE383CFC354DC6A0426B5955176195\" xil_pn:valueState=\"non-default\"/>\n    <property xil_pn:name=\"PROP_intWorkingDirLocWRTProjDir\" xil_pn:value=\"Same\" xil_pn:valueState=\"non-default\"/>\n    <property xil_pn:name=\"PROP_intWorkingDirUsed\" xil_pn:value=\"No\" xil_pn:valueState=\"non-default\"/>\n  </properties>\n\n  <bindings/>\n\n  <libraries/>\n\n  <autoManagedFiles>\n    <!-- The following files are identified by `include statements in verilog -->\n    <!-- source files and are automatically managed by Project Navigator.     -->\n    <!--                                                                      -->\n    <!-- Do not hand-edit this section, as it will be overwritten when the    -->\n    <!-- project is analyzed based on files automatically identified as       -->\n    <!-- include files.                                                       -->\n  </autoManagedFiles>\n\n</project>\n"
  },
  {
    "path": "host/basic_nexys3/ipcore_dir/ila_xmdf.tcl",
    "content": "# The package naming convention is <core_name>_xmdf\npackage provide ila_xmdf 1.0\n\n# This includes some utilities that support common XMDF operations\npackage require utilities_xmdf\n\n# Define a namespace for this package. The name of the name space\n# is <core_name>_xmdf\nnamespace eval ::ila_xmdf {\n# Use this to define any statics\n}\n\n# Function called by client to rebuild the params and port arrays\n# Optional when the use context does not require the param or ports\n# arrays to be available.\nproc ::ila_xmdf::xmdfInit { instance } {\n# Variable containing name of library into which module is compiled\n# Recommendation: <module_name>\n# Required\nutilities_xmdf::xmdfSetData $instance Module Attributes Name ila\n}\n# ::ila_xmdf::xmdfInit\n\n# Function called by client to fill in all the xmdf* data variables\n# based on the current settings of the parameters\nproc ::ila_xmdf::xmdfApplyParams { instance } {\n\nset fcount 0\n# Array containing libraries that are assumed to exist\n# Examples include unisim and xilinxcorelib\n# Optional\n# In this example, we assume that the unisim library will\n# be available to the simulation and synthesis tool\nutilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library\nutilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim\nincr fcount\n\n\nutilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ila.asy\nutilities_xmdf::xmdfSetData $instance FileSet $fcount type asy\nincr fcount\n\nutilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ila.cdc\nutilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView\nincr fcount\n\n\nutilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ila.constraints/ila.ucf\nutilities_xmdf::xmdfSetData $instance FileSet $fcount type Ucf\nincr fcount\n\n\nutilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ila.ncf\nutilities_xmdf::xmdfSetData $instance FileSet $fcount type Ncf\nincr fcount\n\nutilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ila.constraints/ila.xdc\nutilities_xmdf::xmdfSetData $instance FileSet $fcount type Xdc\nincr fcount\n\nutilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ila.ngc\nutilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc\nincr fcount\n\nutilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ila.v\nutilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog\nincr fcount\n\nutilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ila.veo\nutilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template\nincr fcount\n\nutilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ila.xco\nutilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip\nincr fcount\n\nutilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ila_xmdf.tcl\nutilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView\nincr fcount\n\nutilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module ila\nincr fcount\n\n}\n\n# ::gen_comp_name_xmdf::xmdfApplyParams\n\n"
  },
  {
    "path": "host/basic_nexys3/ram.v",
    "content": "module ram(clk, addr, we, data_in, data_out);\nparameter n = 4;\n\ninput clk, we;\ninput [n-1:0] addr;\ninput [7:0] data_in;\noutput reg [7:0] data_out;\n\nreg [7:0] reg_array [2**n-1:0];\n\ninitial $readmemb(\"ram.mif\", reg_array);\n\nalways @(posedge clk)\nbegin\n    if (we == 1)\n        reg_array[addr] <= data_in;\n    data_out = reg_array[addr];\nend\n\nendmodule\n"
  },
  {
    "path": "host/basic_nexys3/readme.txt",
    "content": "Target board: Nexys3 Digilent Xilinx Spartan-6 Development Board\n\nThis folder contains a simple \"basic\" board computer with the A-Z80,\nsome RAM and UART which can run selected Z80 executable files.\n\nConnect UART at 115200 baud to see the output.\n\n./tools/zmac contains few Z80 sample programs to run and batch scripts\nto assemble and copy them into this directory.\n"
  },
  {
    "path": "host/basic_nexys3/test_host.v",
    "content": "`timescale 1ns / 1ps\n\n////////////////////////////////////////////////////////////////////////////////\n// Company:\n// Engineer:\n//\n// Create Date:   00:18:56 02/14/2016\n// Design Name:   host\n// Module Name:   R:/Z80/host/basic_nexys3/test_host.v\n// Project Name:  host_nexys3\n// Target Device:\n// Tool versions:\n// Description:\n//\n// Verilog Test Fixture created by ISE for module: host\n//\n// Dependencies:\n//\n// Revision:\n// Revision 0.01 - File Created\n// Additional Comments:\n//\n////////////////////////////////////////////////////////////////////////////////\n\nmodule test_host;\n\n    // Inputs\n    reg CLOCK_100;\n    reg KEY0;\n    reg KEY1;\n    reg KEY2;\n\n    // Outputs\n    wire UART_TXD;\n    wire [7:0] GPIO_1;\n    wire [7:0] GPIO_2;\n\n    // Bidirs\n    wire [7:0] GPIO_0;\n    wire [7:0] GPIO_3;\n\n    // Instantiate the Unit Under Test (UUT)\n    host uut (\n        .CLOCK_100(CLOCK_100),\n        .KEY0(KEY0),\n        .KEY1(KEY1),\n        .KEY2(KEY2),\n        .UART_TXD(UART_TXD),\n        .GPIO_0(GPIO_0),\n        .GPIO_1(GPIO_1),\n        .GPIO_2(GPIO_2),\n        .GPIO_3(GPIO_3)\n    );\n\n    initial begin\n        CLOCK_100 = 0;\n        KEY0 = 1;\n        KEY1 = 0;\n        KEY2 = 0;\n        // 100 MHz -> 10MHz (pll) -> div 4 (clk divider)\n        #(100/10*4 * 3); // hold for 3 CPU clock cycles\n        #(100/10*4 * 3); // ...twice, due to the way our CLOCK_100 gen below works\n        KEY0 = 0;\n    end\n\n    initial begin\n        forever #1 CLOCK_100 = ~CLOCK_100;\n    end\n\nendmodule\n\n"
  },
  {
    "path": "host/basic_nexys3/work/ram.mif",
    "content": "11000011\n10001111\n00000000\n00000000\n00000000\n01111001\n11111110\n00000010\n11001010\n00010001\n00000000\n11111110\n00001001\n11001010\n00100001\n00000000\n11001001\n00000001\n00000000\n00001010\n11101101\n01111000\n11001011\n01000111\n11000010\n00010001\n00000000\n00000001\n00000000\n00001000\n11101101\n01011001\n11001001\n11010101\n11100001\n01011110\n01111011\n11111110\n00100100\n11001000\n11001101\n00010001\n00000000\n00100011\n11000011\n00100011\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n11010101\n00010001\n01001011\n00000000\n11110101\n11000101\n11100101\n00001110\n00001001\n11001101\n00000101\n00000000\n11100001\n11000001\n11110001\n11010001\n11111011\n11101101\n01001101\n01011111\n01001001\n01001110\n01010100\n01011111\n00100100\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n11110101\n11000101\n11010101\n11100101\n00010001\n01111000\n00000000\n00001110\n00001001\n11001101\n00000101\n00000000\n11100001\n11010001\n11000001\n11110001\n11101101\n01000101\n01011111\n01001110\n01001101\n01001001\n01011111\n00100100\n00000000\n00000000\n10000010\n00000000\n11010101\n00010001\n10001001\n00000000\n11000011\n00111100\n00000000\n01011111\n01001001\n01001101\n00110010\n01011111\n00100100\n00110001\n00000000\n01000000\n11101101\n01011110\n00111110\n00000000\n11101101\n01000111\n11111011\n11000011\n00000000\n00000001\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00000000\n00100001\n00000000\n00000000\n00100010\n01011110\n00000001\n00010001\n01100010\n00000001\n00001110\n00001001\n11001101\n00000101\n00000000\n00101010\n01011110\n00000001\n00100011\n00100010\n01011110\n00000001\n00100001\n01100100\n00000001\n00111010\n01011111\n00000001\n11001101\n00111101\n00000001\n00100001\n01100110\n00000001\n00111010\n01011110\n00000001\n11001101\n00111101\n00000001\n11101101\n01110011\n01100000\n00000001\n00100001\n01101001\n00000001\n11101101\n01010111\n11001101\n00111101\n00000001\n00100001\n01101011\n00000001\n11101101\n01011111\n11001101\n00111101\n00000001\n00011000\n11001001\n11110101\n11100110\n00001111\n11111110\n00001010\n11011010\n01000111\n00000001\n11000110\n00000111\n11000110\n00110000\n00100011\n01110111\n00101011\n11110001\n00011111\n00011111\n00011111\n00011111\n11100110\n00001111\n11111110\n00001010\n11011010\n01011010\n00000001\n11000110\n00000111\n11000110\n00110000\n01110111\n11001001\n00000000\n00000000\n00000000\n00000000\n00001101\n00001010\n00110000\n00110000\n00110000\n00110000\n00100000\n00101101\n00101101\n00101101\n00101101\n00100000\n01001000\n01100101\n01101100\n01101100\n01101111\n00101100\n00100000\n01010111\n01101111\n01110010\n01101100\n01100100\n00100001\n00100100\n"
  },
  {
    "path": "host/common/uart.v",
    "content": "// Simple transmit-only UART model\n\nmodule uart #(\n    parameter [28:0] BAUD = 115200,\n    parameter [28:0] IN_CLOCK = 50000000)\n(\n    // Outputs\n    output wire busy,          // Set when busy transmitting\n    output reg uart_tx,        // UART transmit wire\n    // Inputs\n    input wire wr,             // Write a new byte to transmit\n    input wire [7:0] data,     // 8-bit data\n    input wire clk,\n    input wire reset\n);\n\nreg [3:0] bitcount;\nreg [8:0] shifter;\n\nassign busy = |bitcount[3:1];\nwire sending = |bitcount;\n\n// Calculate UART clock based on the input clock\nreg [28:0] d;\nwire [28:0] inc = d[28] ? (BAUD) : (BAUD - IN_CLOCK);\nwire [28:0] delta = d + inc;\n\nalways @(posedge clk)\nbegin\n    if (reset)\n    begin\n        d = 0;\n    end else\n    begin\n        d = delta;\n    end\nend\n\nwire ser_clk = ~d[28]; // UART clock\n\nalways @(posedge clk) begin\n    if (reset)\n    begin\n        uart_tx <= 1;\n        bitcount <= 0;\n        shifter <= 0;\n    end else\n    begin\n        if (wr & ~busy)\n        begin\n            // synopsys translate_off\n            $strobe(\"[UART] %c\", data[7:0]);\n            // synopsys translate_on\n            shifter <= { data[7:0], 1'h0 };\n            bitcount <= 4'd11; // 1 + 8 + 2\n        end\n\n        if (sending & ser_clk)\n        begin\n            { shifter, uart_tx } <= { 1'h1, shifter };\n            bitcount <= bitcount - 4'd1;\n        end\n    end\nend\n\nendmodule\n"
  },
  {
    "path": "host/common/wait_state.bdf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"graphic\" (version \"1.4\"))\n(pin\n\t(input)\n\t(rect 64 216 240 232)\n\t(text \"INPUT\" (rect 133 0 161 10)(font \"Arial\" (font_size 6)))\n\t(text \"CLK\" (rect 9 0 30 12)(font \"Arial\" ))\n\t(pt 176 8)\n\t(drawing\n\t\t(line (pt 92 12)(pt 117 12))\n\t\t(line (pt 92 4)(pt 117 4))\n\t\t(line (pt 121 8)(pt 176 8))\n\t\t(line (pt 92 12)(pt 92 4))\n\t\t(line (pt 117 4)(pt 121 8))\n\t\t(line (pt 117 12)(pt 121 8))\n\t)\n\t(text \"VCC\" (rect 136 7 156 17)(font \"Arial\" (font_size 6)))\n)\n(pin\n\t(input)\n\t(rect 64 136 240 152)\n\t(text \"INPUT\" (rect 133 0 161 10)(font \"Arial\" (font_size 6)))\n\t(text \"nM1\" (rect 9 0 29 12)(font \"Arial\" ))\n\t(pt 176 8)\n\t(drawing\n\t\t(line (pt 92 12)(pt 117 12))\n\t\t(line (pt 92 4)(pt 117 4))\n\t\t(line (pt 121 8)(pt 176 8))\n\t\t(line (pt 92 12)(pt 92 4))\n\t\t(line (pt 117 4)(pt 121 8))\n\t\t(line (pt 117 12)(pt 121 8))\n\t)\n\t(text \"VCC\" (rect 136 7 156 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184)(font \"Arial\" (font_size 10)))\n(text \"Adding One Wait State to Any Memory Cycle\" (rect 528 408 839 424)(font \"Arial\" (font_size 10)))\n(line (pt 64 272)(pt 784 272)(color 0 255 0))\n"
  },
  {
    "path": "host/common/wait_state.bsf",
    "content": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the block that represents it in\nthe Block Editor! File corruption is VERY likely to occur.\n*/\n/*\nCopyright (C) 1991-2013 Altera Corporation\nYour use of Altera Corporation's design tools, logic functions \nand other software and tools, and its AMPP partner logic \nfunctions, and any output files from any of the foregoing \n(including device programming or simulation files), and any \nassociated documentation or information are expressly subject \nto the terms and conditions of the Altera Program License \nSubscription Agreement, Altera MegaCore Function License \nAgreement, or other applicable license agreement, including, \nwithout limitation, that your use is for the sole purpose of \nprogramming logic devices manufactured by Altera and sold by \nAltera or its authorized distributors.  Please refer to the \napplicable agreement for further details.\n*/\n(header \"symbol\" (version \"1.2\"))\n(symbol\n\t(rect 16 16 184 112)\n\t(text \"wait_state\" (rect 5 0 65 14)(font \"Arial\" (font_size 8)))\n\t(text \"inst\" (rect 8 80 25 92)(font \"Arial\" ))\n\t(port\n\t\t(pt 0 32)\n\t\t(input)\n\t\t(text \"nM1\" (rect 0 0 23 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"nM1\" (rect 21 27 44 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 32)(pt 16 32))\n\t)\n\t(port\n\t\t(pt 0 48)\n\t\t(input)\n\t\t(text \"CLK\" (rect 0 0 23 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"CLK\" (rect 21 43 44 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 48)(pt 16 48))\n\t)\n\t(port\n\t\t(pt 0 64)\n\t\t(input)\n\t\t(text \"nMREQ\" (rect 0 0 41 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"nMREQ\" (rect 21 59 62 73)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 0 64)(pt 16 64))\n\t)\n\t(port\n\t\t(pt 168 32)\n\t\t(output)\n\t\t(text \"nWAIT_M1\" (rect 0 0 61 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"nWAIT_M1\" (rect 86 27 147 41)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 168 32)(pt 152 32))\n\t)\n\t(port\n\t\t(pt 168 48)\n\t\t(output)\n\t\t(text \"nWAIT_Mem\" (rect 0 0 70 14)(font \"Arial\" (font_size 8)))\n\t\t(text \"nWAIT_Mem\" (rect 77 43 147 57)(font \"Arial\" (font_size 8)))\n\t\t(line (pt 168 48)(pt 152 48))\n\t)\n\t(drawing\n\t\t(rectangle (rect 16 16 152 80))\n\t)\n)\n"
  },
  {
    "path": "host/common/wait_state.v",
    "content": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and other software and tools, and its AMPP partner logic \n// functions, and any output files from any of the foregoing \n// (including device programming or simulation files), and any \n// associated documentation or information are expressly subject \n// to the terms and conditions of the Altera Program License \n// Subscription Agreement, Altera MegaCore Function License \n// Agreement, or other applicable license agreement, including, \n// without limitation, that your use is for the sole purpose of \n// programming logic devices manufactured by Altera and sold by \n// Altera or its authorized distributors.  Please refer to the \n// applicable agreement for further details.\n\n// PROGRAM\t\t\"Quartus II 64-Bit\"\n// VERSION\t\t\"Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\"\n// CREATED\t\t\"Thu Dec 08 00:16:50 2016\"\n\nmodule wait_state(\n\tCLK,\n\tnM1,\n\tnMREQ,\n\tnWAIT_M1,\n\tnWAIT_Mem\n);\n\n\ninput wire\tCLK;\ninput wire\tnM1;\ninput wire\tnMREQ;\noutput wire\tnWAIT_M1;\noutput wire\tnWAIT_Mem;\n\nreg\tSYNTHESIZED_WIRE_1;\nreg\tDFF_inst3;\nreg\tDFF_inst2;\nreg\tDFF_inst5;\nwire\tSYNTHESIZED_WIRE_0;\n\nassign\tnWAIT_M1 = DFF_inst2;\n\n\n\nassign\tSYNTHESIZED_WIRE_0 =  ~SYNTHESIZED_WIRE_1;\n\n\nalways@(posedge CLK or negedge DFF_inst3)\nbegin\nif (!DFF_inst3)\n\tbegin\n\tDFF_inst2 <= 1;\n\tend\nelse\n\tbegin\n\tDFF_inst2 <= nM1;\n\tend\nend\n\n\nalways@(posedge CLK)\nbegin\n\tbegin\n\tDFF_inst3 <= DFF_inst2;\n\tend\nend\n\n\nalways@(posedge CLK)\nbegin\n\tbegin\n\tSYNTHESIZED_WIRE_1 <= nMREQ;\n\tend\nend\n\n\nalways@(posedge CLK)\nbegin\n\tbegin\n\tDFF_inst5 <= SYNTHESIZED_WIRE_1;\n\tend\nend\n\nassign\tnWAIT_Mem = ~(DFF_inst5 & SYNTHESIZED_WIRE_0);\n\n\nendmodule\n"
  },
  {
    "path": "host/zxspectrum_de1/pll.ppf",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\" ?>\n<!DOCTYPE pinplan>\n<pinplan intended_family=\"Cyclone II\" variation_name=\"pll\" megafunction_name=\"ALTPLL\" specifies=\"all_ports\">\n<global>\n<pin name=\"inclk0\" direction=\"input\" scope=\"external\" source=\"clock\"  />\n<pin name=\"c0\" direction=\"output\" scope=\"external\" source=\"clock\"  />\n<pin name=\"c1\" direction=\"output\" scope=\"external\" source=\"clock\"  />\n<pin name=\"locked\" direction=\"output\" scope=\"external\"  />\n\n</global>\n</pinplan>\n"
  },
  {
    "path": "host/zxspectrum_de1/pll.qip",
    "content": "set_global_assignment -name IP_TOOL_NAME \"ALTPLL\"\nset_global_assignment -name IP_TOOL_VERSION \"13.0\"\nset_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) \"pll.v\"]\nset_global_assignment -name MISC_FILE [file join $::quartus(qip_path) \"pll.ppf\"]\n"
  },
  {
    "path": "host/zxspectrum_de1/pll.v",
    "content": "// megafunction wizard: %ALTPLL%\n// GENERATION: STANDARD\n// VERSION: WM1.0\n// MODULE: altpll \n\n// ============================================================\n// File Name: pll.v\n// Megafunction Name(s):\n// \t\t\taltpll\n//\n// Simulation Library Files(s):\n// \t\t\taltera_mf\n// ============================================================\n// ************************************************************\n// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!\n//\n// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition\n// ************************************************************\n\n\n//Copyright (C) 1991-2013 Altera Corporation\n//Your use of Altera Corporation's design tools, logic functions \n//and other software and tools, and its AMPP partner logic \n//functions, and any output files from any of the foregoing \n//(including device programming or simulation files), and any \n//associated documentation or information are expressly subject \n//to the terms and conditions of the Altera Program License \n//Subscription Agreement, Altera MegaCore Function License \n//Agreement, or other applicable license agreement, including, \n//without limitation, that your use is for the sole purpose of \n//programming logic devices manufactured by Altera and sold by \n//Altera or its authorized distributors.  Please refer to the \n//applicable agreement for further details.\n\n\n// synopsys translate_off\n`timescale 1 ps / 1 ps\n// synopsys translate_on\nmodule pll (\n\tinclk0,\n\tc0,\n\tc1,\n\tlocked);\n\n\tinput\t  inclk0;\n\toutput\t  c0;\n\toutput\t  c1;\n\toutput\t  locked;\n\n\twire [5:0] sub_wire0;\n\twire  sub_wire2;\n\twire [0:0] sub_wire6 = 1'h0;\n\twire [0:0] sub_wire3 = sub_wire0[0:0];\n\twire [1:1] sub_wire1 = sub_wire0[1:1];\n\twire  c1 = sub_wire1;\n\twire  locked = sub_wire2;\n\twire  c0 = sub_wire3;\n\twire  sub_wire4 = inclk0;\n\twire [1:0] sub_wire5 = {sub_wire6, sub_wire4};\n\n\taltpll\taltpll_component (\n\t\t\t\t.inclk (sub_wire5),\n\t\t\t\t.clk (sub_wire0),\n\t\t\t\t.locked (sub_wire2),\n\t\t\t\t.activeclock (),\n\t\t\t\t.areset (1'b0),\n\t\t\t\t.clkbad (),\n\t\t\t\t.clkena ({6{1'b1}}),\n\t\t\t\t.clkloss (),\n\t\t\t\t.clkswitch (1'b0),\n\t\t\t\t.configupdate (1'b0),\n\t\t\t\t.enable0 (),\n\t\t\t\t.enable1 (),\n\t\t\t\t.extclk (),\n\t\t\t\t.extclkena ({4{1'b1}}),\n\t\t\t\t.fbin (1'b1),\n\t\t\t\t.fbmimicbidir (),\n\t\t\t\t.fbout (),\n\t\t\t\t.fref (),\n\t\t\t\t.icdrclk (),\n\t\t\t\t.pfdena (1'b1),\n\t\t\t\t.phasecounterselect ({4{1'b1}}),\n\t\t\t\t.phasedone (),\n\t\t\t\t.phasestep (1'b1),\n\t\t\t\t.phaseupdown (1'b1),\n\t\t\t\t.pllena (1'b1),\n\t\t\t\t.scanaclr (1'b0),\n\t\t\t\t.scanclk (1'b0),\n\t\t\t\t.scanclkena (1'b1),\n\t\t\t\t.scandata (1'b0),\n\t\t\t\t.scandataout (),\n\t\t\t\t.scandone (),\n\t\t\t\t.scanread (1'b0),\n\t\t\t\t.scanwrite (1'b0),\n\t\t\t\t.sclkout0 (),\n\t\t\t\t.sclkout1 (),\n\t\t\t\t.vcooverrange (),\n\t\t\t\t.vcounderrange ());\n\tdefparam\n\t\taltpll_component.clk0_divide_by = 1080,\n\t\taltpll_component.clk0_duty_cycle = 50,\n\t\taltpll_component.clk0_multiply_by = 1007,\n\t\taltpll_component.clk0_phase_shift = \"0\",\n\t\taltpll_component.clk1_divide_by = 27,\n\t\taltpll_component.clk1_duty_cycle = 50,\n\t\taltpll_component.clk1_multiply_by = 14,\n\t\taltpll_component.clk1_phase_shift = \"0\",\n\t\taltpll_component.compensate_clock = \"CLK0\",\n\t\taltpll_component.gate_lock_counter = 10000,\n\t\taltpll_component.gate_lock_signal = \"YES\",\n\t\taltpll_component.inclk0_input_frequency = 37037,\n\t\taltpll_component.intended_device_family = \"Cyclone II\",\n\t\taltpll_component.invalid_lock_multiplier = 5,\n\t\taltpll_component.lpm_hint = \"CBX_MODULE_PREFIX=pll\",\n\t\taltpll_component.lpm_type = \"altpll\",\n\t\taltpll_component.operation_mode = \"NORMAL\",\n\t\taltpll_component.port_activeclock = \"PORT_UNUSED\",\n\t\taltpll_component.port_areset = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkbad0 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkbad1 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkloss = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkswitch = \"PORT_UNUSED\",\n\t\taltpll_component.port_configupdate = \"PORT_UNUSED\",\n\t\taltpll_component.port_fbin = \"PORT_UNUSED\",\n\t\taltpll_component.port_inclk0 = \"PORT_USED\",\n\t\taltpll_component.port_inclk1 = \"PORT_UNUSED\",\n\t\taltpll_component.port_locked = \"PORT_USED\",\n\t\taltpll_component.port_pfdena = \"PORT_UNUSED\",\n\t\taltpll_component.port_phasecounterselect = \"PORT_UNUSED\",\n\t\taltpll_component.port_phasedone = \"PORT_UNUSED\",\n\t\taltpll_component.port_phasestep = \"PORT_UNUSED\",\n\t\taltpll_component.port_phaseupdown = \"PORT_UNUSED\",\n\t\taltpll_component.port_pllena = \"PORT_UNUSED\",\n\t\taltpll_component.port_scanaclr = \"PORT_UNUSED\",\n\t\taltpll_component.port_scanclk = \"PORT_UNUSED\",\n\t\taltpll_component.port_scanclkena = \"PORT_UNUSED\",\n\t\taltpll_component.port_scandata = \"PORT_UNUSED\",\n\t\taltpll_component.port_scandataout = \"PORT_UNUSED\",\n\t\taltpll_component.port_scandone = \"PORT_UNUSED\",\n\t\taltpll_component.port_scanread = \"PORT_UNUSED\",\n\t\taltpll_component.port_scanwrite = \"PORT_UNUSED\",\n\t\taltpll_component.port_clk0 = \"PORT_USED\",\n\t\taltpll_component.port_clk1 = \"PORT_USED\",\n\t\taltpll_component.port_clk2 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clk3 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clk4 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clk5 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkena0 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkena1 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkena2 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkena3 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkena4 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkena5 = \"PORT_UNUSED\",\n\t\taltpll_component.port_extclk0 = \"PORT_UNUSED\",\n\t\taltpll_component.port_extclk1 = \"PORT_UNUSED\",\n\t\taltpll_component.port_extclk2 = \"PORT_UNUSED\",\n\t\taltpll_component.port_extclk3 = \"PORT_UNUSED\",\n\t\taltpll_component.valid_lock_multiplier = 1;\n\n\nendmodule\n\n// ============================================================\n// CNX file retrieval info\n// ============================================================\n// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: BANDWIDTH STRING \"1.000\"\n// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING \"0\"\n// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING \"MHz\"\n// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING \"Low\"\n// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING \"1\"\n// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING \"0\"\n// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING \"0\"\n// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING \"0\"\n// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING \"c0\"\n// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING \"c0\"\n// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING \"7\"\n// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC \"1\"\n// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC \"1\"\n// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING \"50.00000000\"\n// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING \"50.00000000\"\n// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING \"25.174999\"\n// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING \"14.000000\"\n// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING \"0\"\n// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING \"0\"\n// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING \"1\"\n// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING \"1\"\n// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING \"1\"\n// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC \"10000\"\n// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING \"0\"\n// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING \"27.000\"\n// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING \"MHz\"\n// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING \"50.000\"\n// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING \"1\"\n// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING \"1\"\n// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING \"MHz\"\n// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING \"Cyclone II\"\n// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING \"1\"\n// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING \"1\"\n// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING \"1\"\n// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING \"Not Available\"\n// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC \"0\"\n// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING \"deg\"\n// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING \"deg\"\n// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING \"Any\"\n// Retrieval info: PRIVATE: MIRROR_CLK0 STRING \"0\"\n// Retrieval info: PRIVATE: MIRROR_CLK1 STRING \"0\"\n// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC \"1\"\n// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC \"1\"\n// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING \"1\"\n// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING \"25.17500000\"\n// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING \"14.00000000\"\n// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING \"1\"\n// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING \"1\"\n// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING \"MHz\"\n// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING \"MHz\"\n// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING \"0\"\n// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING \"0.00000000\"\n// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING \"0.00000000\"\n// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING \"deg\"\n// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING \"deg\"\n// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC \"1\"\n// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC \"0\"\n// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC \"0\"\n// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC \"0\"\n// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC \"0\"\n// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING \"inclk0\"\n// Retrieval info: PRIVATE: RECONFIG_FILE STRING \"pll.mif\"\n// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING \"0\"\n// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING \"0\"\n// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING \"0\"\n// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING \"0\"\n// Retrieval info: PRIVATE: SPREAD_FREQ STRING \"50.000\"\n// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING \"KHz\"\n// Retrieval info: PRIVATE: SPREAD_PERCENT STRING \"0.500\"\n// Retrieval info: PRIVATE: SPREAD_USE STRING \"0\"\n// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING \"0\"\n// Retrieval info: PRIVATE: STICKY_CLK0 STRING \"1\"\n// Retrieval info: PRIVATE: STICKY_CLK1 STRING \"1\"\n// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC \"1\"\n// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING \"1\"\n// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING \"0\"\n// Retrieval info: PRIVATE: USE_CLK0 STRING \"1\"\n// Retrieval info: PRIVATE: USE_CLK1 STRING \"1\"\n// Retrieval info: PRIVATE: USE_CLKENA0 STRING \"0\"\n// Retrieval info: PRIVATE: USE_CLKENA1 STRING \"0\"\n// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC \"0\"\n// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING \"0\"\n// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all\n// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC \"1080\"\n// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC \"50\"\n// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC \"1007\"\n// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING \"0\"\n// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC \"27\"\n// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC \"50\"\n// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC \"14\"\n// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING \"0\"\n// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING \"CLK0\"\n// Retrieval info: CONSTANT: GATE_LOCK_COUNTER NUMERIC \"10000\"\n// Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING \"YES\"\n// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC \"37037\"\n// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING \"Cyclone II\"\n// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC \"5\"\n// Retrieval info: CONSTANT: LPM_TYPE STRING \"altpll\"\n// Retrieval info: CONSTANT: OPERATION_MODE STRING \"NORMAL\"\n// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_ARESET STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_CLKLOSS STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_FBIN STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_INCLK0 STRING \"PORT_USED\"\n// Retrieval info: CONSTANT: PORT_INCLK1 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_LOCKED STRING \"PORT_USED\"\n// Retrieval info: CONSTANT: PORT_PFDENA STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_PHASEDONE STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_PHASESTEP STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_PLLENA STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_SCANACLR STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_SCANCLK STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_SCANDATA STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_SCANDONE STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_SCANREAD STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_SCANWRITE STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clk0 STRING \"PORT_USED\"\n// Retrieval info: CONSTANT: PORT_clk1 STRING \"PORT_USED\"\n// Retrieval info: CONSTANT: PORT_clk2 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clk3 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clk4 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clk5 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clkena0 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clkena1 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clkena2 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clkena3 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clkena4 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clkena5 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_extclk0 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_extclk1 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_extclk2 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_extclk3 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC \"1\"\n// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC \"@clk[5..0]\"\n// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC \"@extclk[3..0]\"\n// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC \"c0\"\n// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC \"c1\"\n// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND \"inclk0\"\n// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND \"locked\"\n// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0\n// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0\n// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0\n// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1\n// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0\n// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE\n// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE\n// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE\n// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE\n// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE\n// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE\n// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE\n// Retrieval info: LIB_FILE: altera_mf\n// Retrieval info: CBX_MODULE_PREFIX: ON\n"
  },
  {
    "path": "host/zxspectrum_de1/ram16.qip",
    "content": "set_global_assignment -name IP_TOOL_NAME \"RAM: 2-PORT\"\nset_global_assignment -name IP_TOOL_VERSION \"13.0\"\nset_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) \"ram16.v\"]\n"
  },
  {
    "path": "host/zxspectrum_de1/ram16.v",
    "content": "// megafunction wizard: %RAM: 2-PORT%\n// GENERATION: STANDARD\n// VERSION: WM1.0\n// MODULE: altsyncram \n\n// ============================================================\n// File Name: ram16.v\n// Megafunction Name(s):\n// \t\t\taltsyncram\n//\n// Simulation Library Files(s):\n// \t\t\taltera_mf\n// ============================================================\n// ************************************************************\n// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!\n//\n// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition\n// ************************************************************\n\n\n//Copyright (C) 1991-2013 Altera Corporation\n//Your use of Altera Corporation's design tools, logic functions \n//and other software and tools, and its AMPP partner logic \n//functions, and any output files from any of the foregoing \n//(including device programming or simulation files), and any \n//associated documentation or information are expressly subject \n//to the terms and conditions of the Altera Program License \n//Subscription Agreement, Altera MegaCore Function License \n//Agreement, or other applicable license agreement, including, \n//without limitation, that your use is for the sole purpose of \n//programming logic devices manufactured by Altera and sold by \n//Altera or its authorized distributors.  Please refer to the \n//applicable agreement for further details.\n\n\n// synopsys translate_off\n`timescale 1 ps / 1 ps\n// synopsys translate_on\nmodule ram16 (\n\taddress_a,\n\taddress_b,\n\tclock,\n\tdata_a,\n\tdata_b,\n\twren_a,\n\twren_b,\n\tq_a,\n\tq_b);\n\n\tinput\t[13:0]  address_a;\n\tinput\t[13:0]  address_b;\n\tinput\t  clock;\n\tinput\t[7:0]  data_a;\n\tinput\t[7:0]  data_b;\n\tinput\t  wren_a;\n\tinput\t  wren_b;\n\toutput\t[7:0]  q_a;\n\toutput\t[7:0]  q_b;\n`ifndef ALTERA_RESERVED_QIS\n// synopsys translate_off\n`endif\n\ttri1\t  clock;\n\ttri0\t  wren_a;\n\ttri0\t  wren_b;\n`ifndef ALTERA_RESERVED_QIS\n// synopsys translate_on\n`endif\n\n\twire [7:0] sub_wire0;\n\twire [7:0] sub_wire1;\n\twire [7:0] q_a = sub_wire0[7:0];\n\twire [7:0] q_b = sub_wire1[7:0];\n\n\taltsyncram\taltsyncram_component (\n\t\t\t\t.clock0 (clock),\n\t\t\t\t.wren_a (wren_a),\n\t\t\t\t.address_b (address_b),\n\t\t\t\t.data_b (data_b),\n\t\t\t\t.wren_b (wren_b),\n\t\t\t\t.address_a (address_a),\n\t\t\t\t.data_a (data_a),\n\t\t\t\t.q_a (sub_wire0),\n\t\t\t\t.q_b (sub_wire1),\n\t\t\t\t.aclr0 (1'b0),\n\t\t\t\t.aclr1 (1'b0),\n\t\t\t\t.addressstall_a (1'b0),\n\t\t\t\t.addressstall_b (1'b0),\n\t\t\t\t.byteena_a (1'b1),\n\t\t\t\t.byteena_b (1'b1),\n\t\t\t\t.clock1 (1'b1),\n\t\t\t\t.clocken0 (1'b1),\n\t\t\t\t.clocken1 (1'b1),\n\t\t\t\t.clocken2 (1'b1),\n\t\t\t\t.clocken3 (1'b1),\n\t\t\t\t.eccstatus (),\n\t\t\t\t.rden_a (1'b1),\n\t\t\t\t.rden_b (1'b1));\n\tdefparam\n\t\taltsyncram_component.address_reg_b = \"CLOCK0\",\n\t\taltsyncram_component.clock_enable_input_a = \"BYPASS\",\n\t\taltsyncram_component.clock_enable_input_b = \"BYPASS\",\n\t\taltsyncram_component.clock_enable_output_a = \"BYPASS\",\n\t\taltsyncram_component.clock_enable_output_b = \"BYPASS\",\n\t\taltsyncram_component.indata_reg_b = \"CLOCK0\",\n\t\taltsyncram_component.intended_device_family = \"Cyclone II\",\n\t\taltsyncram_component.lpm_type = \"altsyncram\",\n\t\taltsyncram_component.numwords_a = 16384,\n\t\taltsyncram_component.numwords_b = 16384,\n\t\taltsyncram_component.operation_mode = \"BIDIR_DUAL_PORT\",\n\t\taltsyncram_component.outdata_aclr_a = \"NONE\",\n\t\taltsyncram_component.outdata_aclr_b = \"NONE\",\n\t\taltsyncram_component.outdata_reg_a = \"UNREGISTERED\",\n\t\taltsyncram_component.outdata_reg_b = \"UNREGISTERED\",\n\t\taltsyncram_component.power_up_uninitialized = \"FALSE\",\n\t\taltsyncram_component.read_during_write_mode_mixed_ports = \"DONT_CARE\",\n\t\taltsyncram_component.widthad_a = 14,\n\t\taltsyncram_component.widthad_b = 14,\n\t\taltsyncram_component.width_a = 8,\n\t\taltsyncram_component.width_b = 8,\n\t\taltsyncram_component.width_byteena_a = 1,\n\t\taltsyncram_component.width_byteena_b = 1,\n\t\taltsyncram_component.wrcontrol_wraddress_reg_b = \"CLOCK0\";\n\n\nendmodule\n\n// ============================================================\n// CNX file retrieval info\n// ============================================================\n// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC \"0\"\n// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC \"0\"\n// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC \"0\"\n// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC \"0\"\n// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC \"0\"\n// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC \"0\"\n// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC \"8\"\n// Retrieval info: PRIVATE: BlankMemory NUMERIC \"1\"\n// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC \"0\"\n// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC \"0\"\n// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC \"0\"\n// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC \"0\"\n// Retrieval info: PRIVATE: CLRdata NUMERIC \"0\"\n// Retrieval info: PRIVATE: CLRq NUMERIC \"0\"\n// Retrieval info: PRIVATE: CLRrdaddress NUMERIC \"0\"\n// Retrieval info: PRIVATE: CLRrren NUMERIC \"0\"\n// Retrieval info: PRIVATE: CLRwraddress NUMERIC \"0\"\n// Retrieval info: PRIVATE: CLRwren NUMERIC \"0\"\n// Retrieval info: PRIVATE: Clock NUMERIC \"0\"\n// Retrieval info: PRIVATE: Clock_A NUMERIC \"0\"\n// Retrieval info: PRIVATE: Clock_B NUMERIC \"0\"\n// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC \"0\"\n// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC \"0\"\n// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC \"1\"\n// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING \"PORT_A\"\n// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC \"0\"\n// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING \"Cyclone II\"\n// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC \"0\"\n// Retrieval info: PRIVATE: JTAG_ID STRING \"NONE\"\n// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC \"0\"\n// Retrieval info: PRIVATE: MEMSIZE NUMERIC \"131072\"\n// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC \"0\"\n// Retrieval info: PRIVATE: MIFfilename STRING \"test_scr.hex\"\n// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC \"3\"\n// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC \"0\"\n// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC \"0\"\n// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC \"0\"\n// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC \"2\"\n// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC \"3\"\n// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC \"3\"\n// Retrieval info: PRIVATE: REGdata NUMERIC \"1\"\n// Retrieval info: PRIVATE: REGq NUMERIC \"0\"\n// Retrieval info: PRIVATE: REGrdaddress NUMERIC \"0\"\n// Retrieval info: PRIVATE: REGrren NUMERIC \"0\"\n// Retrieval info: PRIVATE: REGwraddress NUMERIC \"1\"\n// Retrieval info: PRIVATE: REGwren NUMERIC \"1\"\n// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING \"0\"\n// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC \"0\"\n// Retrieval info: PRIVATE: UseDPRAM NUMERIC \"1\"\n// Retrieval info: PRIVATE: VarWidth NUMERIC \"0\"\n// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC \"8\"\n// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC \"8\"\n// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC \"8\"\n// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC \"8\"\n// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC \"0\"\n// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC \"1\"\n// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC \"0\"\n// Retrieval info: PRIVATE: enable NUMERIC \"0\"\n// Retrieval info: PRIVATE: rden NUMERIC \"0\"\n// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all\n// Retrieval info: CONSTANT: ADDRESS_REG_B STRING \"CLOCK0\"\n// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING \"BYPASS\"\n// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING \"BYPASS\"\n// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING \"BYPASS\"\n// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING \"BYPASS\"\n// Retrieval info: CONSTANT: INDATA_REG_B STRING \"CLOCK0\"\n// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING \"Cyclone II\"\n// Retrieval info: CONSTANT: LPM_TYPE STRING \"altsyncram\"\n// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC \"16384\"\n// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC \"16384\"\n// Retrieval info: CONSTANT: OPERATION_MODE STRING \"BIDIR_DUAL_PORT\"\n// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING \"NONE\"\n// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING \"NONE\"\n// Retrieval info: CONSTANT: OUTDATA_REG_A STRING \"UNREGISTERED\"\n// Retrieval info: CONSTANT: OUTDATA_REG_B STRING \"UNREGISTERED\"\n// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING \"FALSE\"\n// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING \"DONT_CARE\"\n// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC \"14\"\n// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC \"14\"\n// Retrieval info: CONSTANT: WIDTH_A NUMERIC \"8\"\n// Retrieval info: CONSTANT: WIDTH_B NUMERIC \"8\"\n// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC \"1\"\n// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC \"1\"\n// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING \"CLOCK0\"\n// Retrieval info: USED_PORT: address_a 0 0 14 0 INPUT NODEFVAL \"address_a[13..0]\"\n// Retrieval info: USED_PORT: address_b 0 0 14 0 INPUT NODEFVAL \"address_b[13..0]\"\n// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC \"clock\"\n// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL \"data_a[7..0]\"\n// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL \"data_b[7..0]\"\n// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL \"q_a[7..0]\"\n// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL \"q_b[7..0]\"\n// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND \"wren_a\"\n// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND \"wren_b\"\n// Retrieval info: CONNECT: @address_a 0 0 14 0 address_a 0 0 14 0\n// Retrieval info: CONNECT: @address_b 0 0 14 0 address_b 0 0 14 0\n// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0\n// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0\n// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0\n// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0\n// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0\n// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0\n// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0\n// Retrieval info: GEN_FILE: TYPE_NORMAL ram16.v TRUE\n// Retrieval info: GEN_FILE: TYPE_NORMAL ram16.inc FALSE\n// Retrieval info: GEN_FILE: TYPE_NORMAL ram16.cmp FALSE\n// Retrieval info: GEN_FILE: TYPE_NORMAL ram16.bsf FALSE\n// Retrieval info: GEN_FILE: TYPE_NORMAL ram16_inst.v FALSE\n// Retrieval info: GEN_FILE: TYPE_NORMAL ram16_bb.v FALSE\n// Retrieval info: LIB_FILE: altera_mf\n"
  },
  {
    "path": "host/zxspectrum_de1/readme.txt",
    "content": "Target board: DE1 Altera Cyclone II EP2C20 FPGA Development Board\n\nThis folder contains an implementation of the legendary Sinclair\nZX Spectrum computer using the A-Z80 CPU, RAM, ROM and ULA.\n"
  },
  {
    "path": "host/zxspectrum_de1/rom/assemble.bat",
    "content": "REM Assembles the ZX Spectrum ROM\nREM\ntasm.exe -b -80 zxspectrum_rom.asm rom.bin\n"
  },
  {
    "path": "host/zxspectrum_de1/rom/readme.txt",
    "content": "The \"original\" ZX Spectrum ROM\n==============================\nhttp://www.wearmouth.demon.co.uk/zx82.htm\n* \"fixed\" the NMI bug so the KEY1 which is connected to the NMI pin can be used.\n* Added a custom NMI handler that provides a way to enter a POKE for a game by typing\n  in the address (5 decimal digits) followed by the value (3 decimal digits)\n  after which the value will be stored to the selected location.\n\nThe GOSH WONDERFUL ROM\n======================\nhttp://www.wearmouth.demon.co.uk/gw03/gw03info.htm\n\nFlash the \"combined.bin\" into the flash of your DE1 board at the address 0.\nSW0 selects which ROM image (which 16K block) is used.\n\nSee the User's Guide for more information on this design.\n\nCREATE ROM IMAGES\n=================\nRun assemble.bat to create ZX Spectrum ROM (rom.bin)\nRun this command to append the two images:\ncopy /b rom.bin + gw03.rom combined.rom\n"
  },
  {
    "path": "host/zxspectrum_de1/rom/tasm80.tab",
    "content": "\"TASM Z80 Assembler.     \"\n/****************************************************************************\n/* $Id: tasm80.tab 1.2 1998/02/28 14:31:22 toma Exp $\n/****************************************************************************\n/* This is the instruction set definition table \n/*   for the Z80 version of TASM.\n/*      Thomas N. Anderson, Speech Technology Incorporated\n/*      This table authored and submitted by Carl A. Wall, VE3APY.\n/*\n/*      Class bits assigned as follows:\n/*        Bit-0 = Z80          (base instruction set)\n/*        Bit-1 = HD64180      (extended instructions)\n/*  See TASM manual for info on table structure.\n/* \n/*INSTR ARGS OP BYTES RULE CLASS SHIFT OR */\n/*-------------------------------------------*/\n\nADC  A,(HL)  8E   1 NOP 1\nADC  A,(IX*) 8EDD 3 ZIX 1\nADC  A,(IY*) 8EFD 3 ZIX 1\nADC  A,A     8F   1 NOP 1\nADC  A,B     88   1 NOP 1\nADC  A,C     89   1 NOP 1\nADC  A,D     8A   1 NOP 1\nADC  A,E     8B   1 NOP 1\nADC  A,H     8C   1 NOP 1\nADC  A,L     8D   1 NOP 1\nADC  A,*     CE   2 NOP 1\nADC  HL,BC   4AED 2 NOP 1\nADC  HL,DE   5AED 2 NOP 1\nADC  HL,HL   6AED 2 NOP 1\nADC  HL,SP   7AED 2 NOP 1\n\nADD  A,(HL)  86   1 NOP 1\nADD  A,(IX*) 86DD 3 ZIX 1\nADD  A,(IY*) 86FD 3 ZIX 1\nADD  A,A     87   1 NOP 1\nADD  A,B     80   1 NOP 1\nADD  A,C     81   1 NOP 1\nADD  A,D     82   1 NOP 1\nADD  A,E     83   1 NOP 1\nADD  A,H     84   1 NOP 1\nADD  A,L     85   1 NOP 1\nADD  A,*     C6   2 NOP 1\nADD  HL,BC   09   1 NOP 1\nADD  HL,DE   19   1 NOP 1\nADD  HL,HL   29   1 NOP 1\nADD  HL,SP   39   1 NOP 1\nADD  IX,BC   09DD 2 NOP 1\nADD  IX,DE   19DD 2 NOP 1\nADD  IX,IX   29DD 2 NOP 1\nADD  IX,SP   39DD 2 NOP 1\nADD  IY,BC   09FD 2 NOP 1\nADD  IY,DE   19FD 2 NOP 1\nADD  IY,IY   29FD 2 NOP 1\nADD  IY,SP   39FD 2 NOP 1\n\nAND  (HL)    A6   1 NOP 1\nAND  (IX*)   A6DD 3 ZIX 1\nAND  (IY*)   A6FD 3 ZIX 1\nAND  A       A7   1 NOP 1\nAND  B       A0   1 NOP 1\nAND  C       A1   1 NOP 1\nAND  D       A2   1 NOP 1\nAND  E       A3   1 NOP 1\nAND  H       A4   1 NOP 1\nAND  L       A5   1 NOP 1\nAND  *       E6   2 NOP 1\n\nBIT  *,(HL)  46CB 2 ZBIT 1\nBIT  *,(IX*) CBDD 4 ZBIT 1 0 4600\nBIT  *,(IY*) CBFD 4 ZBIT 1 0 4600\nBIT  *,A     47CB 2 ZBIT 1\nBIT  *,B     40CB 2 ZBIT 1\nBIT  *,C     41CB 2 ZBIT 1\nBIT  *,D     42CB 2 ZBIT 1\nBIT  *,E     43CB 2 ZBIT 1\nBIT  *,H     44CB 2 ZBIT 1\nBIT  *,L     45CB 2 ZBIT 1\n\nCALL C,*     DC   3 NOP 1\nCALL M,*     FC   3 NOP 1\nCALL NC,*    D4   3 NOP 1\nCALL NZ,*    C4   3 NOP 1\nCALL P,*     F4   3 NOP 1\nCALL PE,*    EC   3 NOP 1\nCALL PO,*    E4   3 NOP 1\nCALL Z,*     CC   3 NOP 1\nCALL *       CD   3 NOP 1\n\nCCF  \"\"      3F   1 NOP 1\n\nCP   (HL)    BE   1 NOP 1\nCP   (IX*)   BEDD 3 ZIX 1\nCP   (IY*)   BEFD 3 ZIX 1\nCP   A       BF   1 NOP 1\nCP   B       B8   1 NOP 1\nCP   C       B9   1 NOP 1\nCP   D       BA   1 NOP 1\nCP   E       BB   1 NOP 1\nCP   H       BC   1 NOP 1\nCP   L       BD   1 NOP 1\nCP   *       FE   2 NOP 1\nCPD  \"\"      A9ED 2 NOP 1\nCPDR \"\"      B9ED 2 NOP 1\nCPIR \"\"      B1ED 2 NOP 1\nCPI  \"\"      A1ED 2 NOP 1\nCPL  \"\"      2F   1 NOP 1\n\nDAA  \"\"      27   1 NOP 1\n\nDEC  (HL)    35   1 NOP 1\nDEC  (IX*)   35DD 3 ZIX 1\nDEC  (IY*)   35FD 3 ZIX 1\nDEC  A       3D   1 NOP 1\nDEC  B       05   1 NOP 1\nDEC  BC      0B   1 NOP 1\nDEC  C       0D   1 NOP 1\nDEC  D       15   1 NOP 1\nDEC  DE      1B   1 NOP 1\nDEC  E       1D   1 NOP 1\nDEC  H       25   1 NOP 1\nDEC  HL      2B   1 NOP 1\nDEC  IX      2BDD 2 NOP 1\nDEC  IY      2BFD 2 NOP 1\nDEC  L       2D   1 NOP 1\nDEC  SP      3B   1 NOP 1\nDI   \"\"      F3   1 NOP 1\nDJNZ *       10   2 R1  1\n\nEI   \"\"      FB   1 NOP 1\nEX   (SP),HL E3   1 NOP 1\nEX   (SP),IX E3DD 2 NOP 1\nEX   (SP),IY E3FD 2 NOP 1\nEX   AF,AF'  08   1 NOP 1\nEX   DE,HL   EB   1 NOP 1\nEXX  \"\"      D9   1 NOP 1\nHALT \"\"      76   1 NOP 1\n\nIM   0       46ED 2 NOP 1\nIM   1       56ED 2 NOP 1\nIM   2       5EED 2 NOP 1\n\n/* Alternate form of above\nIM0          46ED 2 NOP 1\nIM1          56ED 2 NOP 1\nIM2          5EED 2 NOP 1\n\nIN   A,(C)   78ED 2 NOP 1\nIN   B,(C)   40ED 2 NOP 1\nIN   C,(C)   48ED 2 NOP 1\nIN   D,(C)   50ED 2 NOP 1\nIN   E,(C)   58ED 2 NOP 1\nIN   H,(C)   60ED 2 NOP 1\nIN   L,(C)   68ED 2 NOP 1\n\nIN   A,(*)   DB   2 NOP 1\n\nIN0   A,(*)  38ED 3 NOP 2\nIN0   B,(*)  00ED 3 NOP 2\nIN0   C,(*)  08ED 3 NOP 2\nIN0   D,(*)  10ED 3 NOP 2\nIN0   E,(*)  18ED 3 NOP 2\nIN0   H,(*)  20ED 3 NOP 2\nIN0   L,(*)  28ED 3 NOP 2\n\nINC  (HL)    34   1 NOP 1\nINC  (IX*)   34DD 3 ZIX 1\nINC  (IY*)   34FD 3 ZIX 1\nINC  A       3C   1 NOP 1\nINC  B       04   1 NOP 1\nINC  BC      03   1 NOP 1\nINC  C       0C   1 NOP 1\nINC  D       14   1 NOP 1\nINC  DE      13   1 NOP 1\nINC  E       1C   1 NOP 1\nINC  H       24   1 NOP 1\nINC  HL      23   1 NOP 1\nINC  IX      23DD 2 NOP 1\nINC  IY      23FD 2 NOP 1\nINC  L       2C   1 NOP 1\nINC  SP      33   1 NOP 1\n\n\nIND  \"\"      AAED 2 NOP 1\nINDR \"\"      BAED 2 NOP 1\nINI  \"\"      A2ED 2 NOP 1\nINIR \"\"      B2ED 2 NOP 1\n\nJP   (HL)    E9   1 NOP 1\nJP   (IX)    E9DD 2 NOP 1\nJP   (IY)    E9FD 2 NOP 1\nJP   C,*     DA   3 NOP 1\nJP   M,*     FA   3 NOP 1\nJP   NC,*    D2   3 NOP 1\nJP   NZ,*    C2   3 NOP 1\nJP   P,*     F2   3 NOP 1\nJP   PE,*    EA   3 NOP 1\nJP   PO,*    E2   3 NOP 1\nJP   Z,*     CA   3 NOP 1\nJP   *       C3   3 NOP 1\n\nJR   C,*     38   2 R1  1\nJR   NC,*    30   2 R1  1\nJR   NZ,*    20   2 R1  1\nJR   Z,*     28   2 R1  1\nJR   *       18   2 R1  1\n\nLD   (BC),A  02   1 NOP 1\nLD   (DE),A  12   1 NOP 1\nLD   (HL),A  77   1 NOP 1\nLD   (HL),B  70   1 NOP 1\nLD   (HL),C  71   1 NOP 1\nLD   (HL),D  72   1 NOP 1\nLD   (HL),E  73   1 NOP 1\nLD   (HL),H  74   1 NOP 1\nLD   (HL),L  75   1 NOP 1\nLD   (HL),*  36   2 NOP 1\nLD   (IX*),A 77DD 3 ZIX 1\nLD   (IX*),B 70DD 3 ZIX 1\nLD   (IX*),C 71DD 3 ZIX 1\nLD   (IX*),D 72DD 3 ZIX 1\nLD   (IX*),E 73DD 3 ZIX 1\nLD   (IX*),H 74DD 3 ZIX 1\nLD   (IX*),L 75DD 3 ZIX 1\nLD   (IX*),* 36DD 4 ZIX 1\nLD   (IY*),A 77FD 3 ZIX 1\nLD   (IY*),B 70FD 3 ZIX 1\nLD   (IY*),C 71FD 3 ZIX 1\nLD   (IY*),D 72FD 3 ZIX 1\nLD   (IY*),E 73FD 3 ZIX 1\nLD   (IY*),H 74FD 3 ZIX 1\nLD   (IY*),L 75FD 3 ZIX 1\nLD   (IY*),* 36FD 4 ZIX 1\nLD   (*),A   32   3 NOP 1\nLD   (*),BC  43ED 4 NOP 1\nLD   (*),DE  53ED 4 NOP 1\nLD   (*),HL  22   3 NOP 1\nLD   (*),IX  22DD 4 NOP 1\nLD   (*),IY  22FD 4 NOP 1\nLD   (*),SP  73ED 4 NOP 1\nLD   A,(BC)  0A   1 NOP 1\nLD   A,(DE)  1A   1 NOP 1\nLD   A,(HL)  7E   1 NOP 1\nLD   A,(IX*) 7EDD 3 ZIX 1\nLD   A,(IY*) 7EFD 3 ZIX 1\nLD   A,A     7F   1 NOP 1\nLD   A,B     78   1 NOP 1\nLD   A,C     79   1 NOP 1\nLD   A,D     7A   1 NOP 1\nLD   A,E     7B   1 NOP 1\nLD   A,H     7C   1 NOP 1\nLD   A,I     57ED 2 NOP 1\nLD   A,L     7D   1 NOP 1\nLD   A,R     5FED 2 NOP 1\nLD   A,(*)   3A   3 NOP 1\nLD   A,*     3E   2 NOP 1\nLD   B,(HL)  46   1 NOP 1\nLD   B,(IX*) 46DD 3 ZIX 1\nLD   B,(IY*) 46FD 3 ZIX 1\nLD   B,A     47   1 NOP 1\nLD   B,B     40   1 NOP 1\nLD   B,C     41   1 NOP 1\nLD   B,D     42   1 NOP 1\nLD   B,E     43   1 NOP 1\nLD   B,H     44   1 NOP 1\nLD   B,L     45   1 NOP 1\nLD   B,*     06   2 NOP 1\nLD   BC,(*)  4BED 4 NOP 1\nLD   BC,*    01   3 NOP 1\nLD   C,(HL)  4E   1 NOP 1\nLD   C,(IX*) 4EDD 3 ZIX 1\nLD   C,(IY*) 4EFD 3 ZIX 1\nLD   C,A     4F   1 NOP 1\nLD   C,B     48   1 NOP 1\nLD   C,C     49   1 NOP 1\nLD   C,D     4A   1 NOP 1\nLD   C,E     4B   1 NOP 1\nLD   C,H     4C   1 NOP 1\nLD   C,L     4D   1 NOP 1\nLD   C,*     0E   2 NOP 1\nLD   D,(HL)  56   1 NOP 1\nLD   D,(IX*) 56DD 3 ZIX 1\nLD   D,(IY*) 56FD 3 ZIX 1\nLD   D,A     57   1 NOP 1\nLD   D,B     50   1 NOP 1\nLD   D,C     51   1 NOP 1\nLD   D,D     52   1 NOP 1\nLD   D,E     53   1 NOP 1\nLD   D,H     54   1 NOP 1\nLD   D,L     55   1 NOP 1\nLD   D,*     16   2 NOP 1\nLD   DE,(*)  5BED 4 NOP 1\nLD   DE,*    11   3 NOP 1\nLD   E,(HL)  5E   1 NOP 1\nLD   E,(IX*) 5EDD 3 ZIX 1\nLD   E,(IY*) 5EFD 3 ZIX 1\nLD   E,A     5F   1 NOP 1\nLD   E,B     58   1 NOP 1\nLD   E,C     59   1 NOP 1\nLD   E,D     5A   1 NOP 1\nLD   E,E     5B   1 NOP 1\nLD   E,H     5C   1 NOP 1\nLD   E,L     5D   1 NOP 1\nLD   E,*     1E   2 NOP 1\nLD   H,(HL)  66   1 NOP 1\nLD   H,(IX*) 66DD 3 ZIX 1\nLD   H,(IY*) 66FD 3 ZIX 1\nLD   H,A     67   1 NOP 1\nLD   H,B     60   1 NOP 1\nLD   H,C     61   1 NOP 1\nLD   H,D     62   1 NOP 1\nLD   H,E     63   1 NOP 1\nLD   H,H     64   1 NOP 1\nLD   H,L     65   1 NOP 1\nLD   H,*     26   2 NOP 1\nLD   HL,(*)  2A   3 NOP 1\nLD   HL,*    21   3 NOP 1\nLD   I,A     47ED 2 NOP 1\nLD   IX,(*)  2ADD 4 NOP 1\nLD   IX,*    21DD 4 NOP 1\nLD   IY,(*)  2AFD 4 NOP 1\nLD   IY,*    21FD 4 NOP 1\nLD   L,(HL)  6E   1 NOP 1\nLD   L,(IX*) 6EDD 3 ZIX 1\nLD   L,(IY*) 6EFD 3 ZIX 1\nLD   L,A     6F   1 NOP 1\nLD   L,B     68   1 NOP 1\nLD   L,C     69   1 NOP 1\nLD   L,D     6A   1 NOP 1\nLD   L,E     6B   1 NOP 1\nLD   L,H     6C   1 NOP 1\nLD   L,L     6D   1 NOP 1\nLD   L,*     2E   2 NOP 1\nLD   R,A     4FED 2 NOP 1\nLD   SP,(*)  7BED 4 NOP 1\nLD   SP,HL   F9   1 NOP 1\nLD   SP,IX   F9DD 2 NOP 1\nLD   SP,IY   F9FD 2 NOP 1\nLD   SP,*    31   3 NOP 1\nLDD  \"\"      A8ED 2 NOP 1\nLDDR \"\"      B8ED 2 NOP 1\nLDI  \"\"      A0ED 2 NOP 1\nLDIR \"\"      B0ED 2 NOP 1\nNEG  \"\"      44ED 2 NOP 1\nNOP  \"\"      00   1 NOP 1\n\nMLT BC       4CED 2 NOP 2\nMLT DE       5CED 2 NOP 2\nMLT HL       6CED 2 NOP 2\nMLT SP       7CED 2 NOP 2\n\nOR   (HL)    B6   1 NOP 1\nOR   (IX*)   B6DD 3 ZIX 1\nOR   (IY*)   B6FD 3 ZIX 1\nOR   A       B7   1 NOP 1\nOR   B       B0   1 NOP 1\nOR   C       B1   1 NOP 1\nOR   D       B2   1 NOP 1\nOR   E       B3   1 NOP 1\nOR   H       B4   1 NOP 1\nOR   L       B5   1 NOP 1\nOR   *       F6   2 NOP 1\n\nOTDM \"\"      8BED 2 NOP 2\nOTDMR \"\"     9BED 2 NOP 2\nOTDR \"\"      BBED 2 NOP 1\nOTIM \"\"      83ED 2 NOP 2\nOTIMR \"\"     93ED 2 NOP 2\nOTIR \"\"      B3ED 2 NOP 1\n\nOUT  (C),A   79ED 2 NOP 1\nOUT  (C),B   41ED 2 NOP 1\nOUT  (C),C   49ED 2 NOP 1\nOUT  (C),D   51ED 2 NOP 1\nOUT  (C),E   59ED 2 NOP 1\nOUT  (C),H   61ED 2 NOP 1\nOUT  (C),L   69ED 2 NOP 1\nOUT  (*),A   D3   2 NOP 1\n\nOUT0 (*),A   39ED 3 NOP 2\nOUT0 (*),B   01ED 3 NOP 2\nOUT0 (*),C   09ED 3 NOP 2\nOUT0 (*),D   11ED 3 NOP 2\nOUT0 (*),E   19ED 3 NOP 2\nOUT0 (*),H   21ED 3 NOP 2\nOUT0 (*),L   29ED 3 NOP 2\n\nOUTD \"\"      ABED 2 NOP 1\nOUTI \"\"      A3ED 2 NOP 1\n\nPOP  AF      F1   1 NOP 1\nPOP  BC      C1   1 NOP 1\nPOP  DE      D1   1 NOP 1\nPOP  HL      E1   1 NOP 1\nPOP  IX      E1DD 2 NOP 1\nPOP  IY      E1FD 2 NOP 1\n\nPUSH AF      F5   1 NOP 1\nPUSH BC      C5   1 NOP 1\nPUSH DE      D5   1 NOP 1\nPUSH HL      E5   1 NOP 1\nPUSH IX      E5DD 2 NOP 1\nPUSH IY      E5FD 2 NOP 1\n\nRES  *,(HL)  86CB 2 ZBIT 1\nRES  *,(IX*) CBDD 4 ZBIT 1 0 8600\nRES  *,(IY*) CBFD 4 ZBIT 1 0 8600\nRES  *,A     87CB 2 ZBIT 1\nRES  *,B     80CB 2 ZBIT 1\nRES  *,C     81CB 2 ZBIT 1\nRES  *,D     82CB 2 ZBIT 1\nRES  *,E     83CB 2 ZBIT 1\nRES  *,H     84CB 2 ZBIT 1\nRES  *,L     85CB 2 ZBIT 1\n\nRET  \"\"      C9   1 NOP 1\nRET  C       D8   1 NOP 1\nRET  M       F8   1 NOP 1\nRET  NC      D0   1 NOP 1\nRET  NZ      C0   1 NOP 1\nRET  P       F0   1 NOP 1\nRET  PE      E8   1 NOP 1\nRET  PO      E0   1 NOP 1\nRET  Z       C8   1 NOP 1\nRETI \"\"      4DED 2 NOP 1\nRETN \"\"      45ED 2 NOP 1\n\nRL   (HL)    16CB 2 NOP 1\nRL   (IX*)   CBDD 4 ZIX 1 0 1600\nRL   (IY*)   CBFD 4 ZIX 1 0 1600\nRL   A       17CB 2 NOP 1\nRL   B       10CB 2 NOP 1\nRL   C       11CB 2 NOP 1\nRL   D       12CB 2 NOP 1\nRL   E       13CB 2 NOP 1\nRL   H       14CB 2 NOP 1\nRL   L       15CB 2 NOP 1\nRLA  \"\"      17   1 NOP 1\n\nRLC  (HL)    06CB 2 NOP 1\nRLC  (IX*)   CBDD 4 ZIX 1 0 0600\nRLC  (IY*)   CBFD 4 ZIX 1 0 0600\nRLC  A       07CB 2 NOP 1\nRLC  B       00CB 2 NOP 1\nRLC  C       01CB 2 NOP 1\nRLC  D       02CB 2 NOP 1\nRLC  E       03CB 2 NOP 1\nRLC  H       04CB 2 NOP 1\nRLC  L       05CB 2 NOP 1\nRLCA \"\"      07   1 NOP 1\nRLD  \"\"      6FED 2 NOP 1\n\nRR   (HL)    1ECB 2 NOP 1\nRR   (IX*)   CBDD 4 ZIX 1 0 1E00\nRR   (IY*)   CBFD 4 ZIX 1 0 1E00 \nRR   A       1FCB 2 NOP 1\nRR   B       18CB 2 NOP 1\nRR   C       19CB 2 NOP 1\nRR   D       1ACB 2 NOP 1\nRR   E       1BCB 2 NOP 1\nRR   H       1CCB 2 NOP 1\nRR   L       1DCB 2 NOP 1\nRRA  \"\"      1F   1 NOP 1\nRRC  (HL)    0ECB 2 NOP 1\nRRC  (IX*)   CBDD 4 ZIX 1 0 0E00\nRRC  (IY*)   CBFD 4 ZIX 1 0 0E00\nRRC  A       0FCB 2 NOP 1\nRRC  B       08CB 2 NOP 1\nRRC  C       09CB 2 NOP 1\nRRC  D       0ACB 2 NOP 1\nRRC  E       0BCB 2 NOP 1\nRRC  H       0CCB 2 NOP 1\nRRC  L       0DCB 2 NOP 1\nRRCA \"\"      0F   1 NOP 1\nRRD  \"\"      67ED 2 NOP 1\n\nRST  00H     C7   1 NOP 1\nRST  08H     CF   1 NOP 1\nRST  10H     D7   1 NOP 1\nRST  18H     DF   1 NOP 1\nRST  20H     E7   1 NOP 1\nRST  28H     EF   1 NOP 1\nRST  30H     F7   1 NOP 1\nRST  38H     FF   1 NOP 1\n\n/* Alternate form of above\nRST  00      C7   1 NOP 1\nRST  08      CF   1 NOP 1\nRST  10      D7   1 NOP 1\nRST  18      DF   1 NOP 1\nRST  20      E7   1 NOP 1\nRST  28      EF   1 NOP 1\nRST  30      F7   1 NOP 1\nRST  38      FF   1 NOP 1\n\nSBC  A,(HL)  9E   1 NOP 1\nSBC  A,(IX*) 9EDD 3 ZIX 1\nSBC  A,(IY*) 9EFD 3 ZIX 1\nSBC  A,A     9F   1 NOP 1\nSBC  A,B     98   1 NOP 1\nSBC  A,C     99   1 NOP 1\nSBC  A,D     9A   1 NOP 1\nSBC  A,E     9B   1 NOP 1\nSBC  A,H     9C   1 NOP 1\nSBC  A,L     9D   1 NOP 1\nSBC  HL,BC   42ED 2 NOP 1\nSBC  HL,DE   52ED 2 NOP 1\nSBC  HL,HL   62ED 2 NOP 1\nSBC  HL,SP   72ED 2 NOP 1\nSBC  A,*     DE   2 NOP 1\nSCF  \"\"      37   1 NOP 1\n\nSET  *,(HL)  C6CB 2 ZBIT 1\nSET  *,(IX*) CBDD 4 ZBIT 1 0 C600\nSET  *,(IY*) CBFD 4 ZBIT 1 0 C600\nSET  *,A     C7CB 2 ZBIT 1\nSET  *,B     C0CB 2 ZBIT 1\nSET  *,C     C1CB 2 ZBIT 1\nSET  *,D     C2CB 2 ZBIT 1\nSET  *,E     C3CB 2 ZBIT 1\nSET  *,H     C4CB 2 ZBIT 1\nSET  *,L     C5CB 2 ZBIT 1\n\nSLA  (HL)    26CB 2 NOP 1\nSLA  (IX*)   CBDD 4 ZIX 1 0 2600\nSLA  (IY*)   CBFD 4 ZIX 1 0 2600\nSLA  A       27CB 2 NOP 1\nSLA  B       20CB 2 NOP 1\nSLA  C       21CB 2 NOP 1\nSLA  D       22CB 2 NOP 1\nSLA  E       23CB 2 NOP 1\nSLA  H       24CB 2 NOP 1\nSLA  L       25CB 2 NOP 1\n\nSLP  \"\"      76ED 2 NOP 2\n\nSRA  (HL)    2ECB 2 NOP 1\nSRA  (IX*)   CBDD 4 ZIX 1 0 2E00\nSRA  (IY*)   CBFD 4 ZIX 1 0 2E00\nSRA  A       2FCB 2 NOP 1\nSRA  B       28CB 2 NOP 1\nSRA  C       29CB 2 NOP 1\nSRA  D       2ACB 2 NOP 1\nSRA  E       2BCB 2 NOP 1\nSRA  H       2CCB 2 NOP 1\nSRA  L       2DCB 2 NOP 1\n\nSRL  (HL)    3ECB 2 NOP 1\nSRL  (IX*)   CBDD 4 ZIX 1 0 3E00\nSRL  (IY*)   CBFD 4 ZIX 1 0 3E00\nSRL  A       3FCB 2 NOP 1\nSRL  B       38CB 2 NOP 1\nSRL  C       39CB 2 NOP 1\nSRL  D       3ACB 2 NOP 1\nSRL  E       3BCB 2 NOP 1\nSRL  H       3CCB 2 NOP 1\nSRL  L       3DCB 2 NOP 1\n\nSUB  (HL)    96   1 NOP 1\nSUB  (IX*)   96DD 3 ZIX 1\nSUB  (IY*)   96FD 3 ZIX 1\nSUB  A       97   1 NOP 1\nSUB  B       90   1 NOP 1\nSUB  C       91   1 NOP 1\nSUB  D       92   1 NOP 1\nSUB  E       93   1 NOP 1\nSUB  H       94   1 NOP 1\nSUB  L       95   1 NOP 1\nSUB  *       D6   2 NOP 1\n\nTST  A       3CED 2 NOP 2\nTST  B       04ED 2 NOP 2\nTST  C       0CED 2 NOP 2\nTST  D       14ED 2 NOP 2\nTST  E       1CED 2 NOP 2\nTST  H       24ED 2 NOP 2\nTST  L       2CED 2 NOP 2\nTST  (HL)    34ED 2 NOP 2\nTST  *       64ED 3 NOP 2\n\nTSTIO *      74ED 3 NOP 2\n\nXOR  (HL)    AE   1 NOP 1\nXOR  (IX*)   AEDD 3 ZIX 1\nXOR  (IY*)   AEFD 3 ZIX 1\nXOR  A       AF   1 NOP 1\nXOR  B       A8   1 NOP 1\nXOR  C       A9   1 NOP 1\nXOR  D       AA   1 NOP 1\nXOR  E       AB   1 NOP 1\nXOR  H       AC   1 NOP 1\nXOR  L       AD   1 NOP 1\nXOR  *       EE   2 NOP 1\n"
  },
  {
    "path": "host/zxspectrum_de1/rom/zxspectrum_rom.asm",
    "content": ";************************************************************************\n;** An Assembly File Listing to generate a 16K ROM for the ZX Spectrum **\n;************************************************************************\n;\n; 03-13-2016:\n; Add custom NMI handler and a function to enter game pokes after pressing the NMI button\n;\n; 11-10-2014:\n; This version has been updated to correctly handle the NMI jump.\n;\n; -------------------------\n; Last updated: 13-DEC-2004\n; -------------------------\n\n; TASM cross-assembler directives.\n; ( comment out, perhaps, for other assemblers - see Notes at end.)\n\n#define DEFB .BYTE\n#define DEFW .WORD\n#define DEFM .TEXT\n#define ORG  .ORG\n#define EQU  .EQU\n#define equ  .EQU\n\n;   It is always a good idea to anchor, using ORGs, important sections such as\n;   the character bitmaps so that they don't move as code is added and removed.\n\n;   Generally most approaches try to maintain main entry points as they are\n;   often used by third-party software.\n\nORG 0000\n\n;*****************************************\n;** Part 1. RESTART ROUTINES AND TABLES **\n;*****************************************\n\n; -----------\n; THE 'START'\n; -----------\n;   At switch on, the Z80 chip is in Interrupt Mode 0.\n;   The Spectrum uses Interrupt Mode 1.\n;   This location can also be 'called' to reset the machine.\n;   Typically with PRINT USR 0.\n\n;; START\nL0000:  DI                      ; Disable Interrupts.\n        XOR     A               ; Signal coming from START.\n        LD      DE,$FFFF        ; Set pointer to top of possible physical RAM.\n        JP      L11CB           ; Jump forward to common code at START-NEW.\n\n; -------------------\n; THE 'ERROR' RESTART\n; -------------------\n;   The error pointer is made to point to the position of the error to enable\n;   the editor to highlight the error position if it occurred during syntax\n;   checking.  It is used at 37 places in the program.  An instruction fetch\n;   on address $0008 may page in a peripheral ROM such as the Sinclair\n;   Interface 1 or Disciple Disk Interface.  This was not an original design\n;   concept and not all errors pass through here.\n\n;; ERROR-1\nL0008:  LD      HL,($5C5D)      ; Fetch the character address from CH_ADD.\n        LD      ($5C5F),HL      ; Copy it to the error pointer X_PTR.\n        JR      L0053           ; Forward to continue at ERROR-2.\n\n; -----------------------------\n; THE 'PRINT CHARACTER' RESTART\n; -----------------------------\n;   The A register holds the code of the character that is to be sent to\n;   the output stream of the current channel.  The alternate register set is\n;   used to output a character in the A register so there is no need to\n;   preserve any of the current main registers (HL, DE, BC).\n;   This restart is used 21 times.\n\n;; PRINT-A\nL0010:  JP      L15F2           ; Jump forward to continue at PRINT-A-2.\n\n; ---\n\n        DEFB    $FF, $FF, $FF   ; Five unused locations.\n        DEFB    $FF, $FF        ;\n\n; -------------------------------\n; THE 'COLLECT CHARACTER' RESTART\n; -------------------------------\n;   The contents of the location currently addressed by CH_ADD are fetched.\n;   A return is made if the value represents a character that has\n;   relevance to the BASIC parser. Otherwise CH_ADD is incremented and the\n;   tests repeated. CH_ADD will be addressing somewhere -\n;   1) in the BASIC program area during line execution.\n;   2) in workspace if evaluating, for example, a string expression.\n;   3) in the edit buffer if parsing a direct command or a new BASIC line.\n;   4) in workspace if accepting input but not that from INPUT LINE.\n\n;; GET-CHAR\nL0018:  LD      HL,($5C5D)      ; fetch the address from CH_ADD.\n        LD      A,(HL)          ; use it to pick up current character.\n\n;; TEST-CHAR\nL001C:  CALL    L007D           ; routine SKIP-OVER tests if the character is\n                                ; relevant.\n        RET     NC              ; Return if it is significant.\n\n; ------------------------------------\n; THE 'COLLECT NEXT CHARACTER' RESTART\n; ------------------------------------\n;   As the BASIC commands and expressions are interpreted, this routine is\n;   called repeatedly to step along the line.  It is used 83 times.\n\n;; NEXT-CHAR\nL0020:  CALL    L0074           ; routine CH-ADD+1 fetches the next immediate\n                                ; character.\n        JR      L001C           ; jump back to TEST-CHAR until a valid\n                                ; character is found.\n\n; ---\n\n        DEFB    $FF, $FF, $FF   ; unused\n\n; -----------------------\n; THE 'CALCULATE' RESTART\n; -----------------------\n;   This restart enters the Spectrum's internal, floating-point, stack-based,\n;   FORTH-like language.\n;   It is further used recursively from within the calculator.\n;   It is used on 77 occasions.\n\n;; FP-CALC\nL0028:  JP      L335B           ; jump forward to the CALCULATE routine.\n\n; ---\n\n        DEFB    $FF, $FF, $FF   ; spare - note that on the ZX81, space being a\n        DEFB    $FF, $FF        ; little cramped, these same locations were\n                                ; used for the five-byte end-calc literal.\n\n; ------------------------------\n; THE 'CREATE BC SPACES' RESTART\n; ------------------------------\n;   This restart is used on only 12 occasions to create BC spaces\n;   between workspace and the calculator stack.\n\n;; BC-SPACES\nL0030:  PUSH    BC              ; Save number of spaces.\n        LD      HL,($5C61)      ; Fetch WORKSP.\n        PUSH    HL              ; Save address of workspace.\n        JP      L169E           ; Jump forward to continuation code RESERVE.\n\n; --------------------------------\n; THE 'MASKABLE INTERRUPT' ROUTINE\n; --------------------------------\n;   This routine increments the Spectrum's three-byte FRAMES counter fifty\n;   times a second (sixty times a second in the USA ).\n;   Both this routine and the called KEYBOARD subroutine use the IY register\n;   to access system variables and flags so a user-written program must\n;   disable interrupts to make use of the IY register.\n\n;; MASK-INT\nL0038:  PUSH    AF              ; Save the registers that will be used but not\n        PUSH    HL              ; the IY register unfortunately.\n        LD      HL,($5C78)      ; Fetch the first two bytes at FRAMES1.\n        INC     HL              ; Increment lowest two bytes of counter.\n        LD      ($5C78),HL      ; Place back in FRAMES1.\n        LD      A,H             ; Test if the result was zero.\n        OR      L               ;\n        JR      NZ,L0048        ; Forward, if not, to KEY-INT\n\n        INC     (IY+$40)        ; otherwise increment FRAMES3 the third byte.\n\n;   Now save the rest of the main registers and read and decode the keyboard.\n\n;; KEY-INT\nL0048:  PUSH    BC              ; Save the other main registers.\n        PUSH    DE              ;\n\n        CALL    L02BF           ; Routine KEYBOARD executes a stage in the\n                                ; process of reading a key-press.\n        POP     DE              ;\n        POP     BC              ; Restore registers.\n\n        POP     HL              ;\n        POP     AF              ;\n\n        EI                      ; Enable Interrupts.\n        RET                     ; Return.\n\n; ---------------------\n; THE 'ERROR-2' ROUTINE\n; ---------------------\n;   A continuation of the code at 0008.\n;   The error code is stored and after clearing down stacks, an indirect jump\n;   is made to MAIN-4, etc. to handle the error.\n\n;; ERROR-2\nL0053:  POP     HL              ; drop the return address - the location\n                                ; after the RST 08H instruction.\n        LD      L,(HL)          ; fetch the error code that follows.\n                                ; (nice to see this instruction used.)\n\n;   Note. this entry point is used when out of memory at REPORT-4.\n;   The L register has been loaded with the report code but X-PTR is not\n;   updated.\n\n;; ERROR-3\nL0055:  LD      (IY+$00),L      ; Store it in the system variable ERR_NR.\n        LD      SP,($5C3D)      ; ERR_SP points to an error handler on the\n                                ; machine stack. There may be a hierarchy\n                                ; of routines.\n                                ; To MAIN-4 initially at base.\n                                ; or REPORT-G on line entry.\n                                ; or  ED-ERROR when editing.\n                                ; or   ED-FULL during ed-enter.\n                                ; or  IN-VAR-1 during runtime input etc.\n\n        JP      L16C5           ; Jump to SET-STK to clear the calculator stack\n                                ; and reset MEM to usual place in the systems\n                                ; variables area and then indirectly to MAIN-4,\n                                ; etc.\n\n; ---\n\n        DEFB    $FF, $FF, $FF   ; Unused locations\n        DEFB    $FF, $FF, $FF   ; before the fixed-position\n        DEFB    $FF             ; NMI routine.\n\n; ------------------------------------\n; THE 'NON-MASKABLE INTERRUPT' ROUTINE\n; ------------------------------------\n;\n;   There is no NMI switch on the standard Spectrum or its peripherals.\n;   When the NMI line is held low, then no matter what the Z80 was doing at\n;   the time, it will now execute the code at 66 Hex.\n;   This Interrupt Service Routine will jump to location zero if the contents\n;   of the system variable NMIADD are zero or return if the location holds a\n;   non-zero address.   So attaching a simple switch to the NMI as in the book\n;   \"Spectrum Hardware Manual\" causes a reset.  The logic was obviously\n;   intended to work the other way.  Sinclair Research said that, since they\n;   had never advertised the NMI, they had no plans to fix the error \"until\n;   the opportunity arose\".\n;\n;   Note. The location NMIADD was, in fact, later used by Sinclair Research\n;   to enhance the text channel on the ZX Interface 1.\n;   On later Amstrad-made Spectrums, and the Brazilian Spectrum, the logic of\n;   this routine was indeed reversed but not as at first intended.\n;\n;   It can be deduced by looking elsewhere in this ROM that the NMIADD system\n;   variable pointed to L121C and that this enabled a Warm Restart to be\n;   performed at any time, even while playing machine code games, or while\n;   another Spectrum has been allowed to gain control of this one.\n;\n;   Software houses would have been able to protect their games from attack by\n;   placing two zeros in the NMIADD system variable.\n\n;; RESET\nL0066:  PUSH    AF              ; save the\n        PUSH    HL              ; registers.\n;       LD      HL,($5CB0)      ; fetch the system variable NMIADD.\n        LD      HL, nmi_handler ; Custom NMI handler\n        LD      A,H             ; test address\n        OR      L               ; for zero.\n\n;       JR      NZ,L0070       ; skip to NO-RESET if NOT ZERO\n        JR      Z,L0070         ; **FIXED**\n\n        JP      (HL)            ; jump to routine ( i.e. L0000 )\n\n;; NO-RESET\nL0070:  POP     HL              ; restore the\n        POP     AF              ; registers.\n        RETN                    ; return to previous interrupt state.\n\n; ---------------------------\n; THE 'CH ADD + 1' SUBROUTINE\n; ---------------------------\n;   This subroutine is called from RST 20, and three times from elsewhere\n;   to fetch the next immediate character following the current valid character\n;   address and update the associated system variable.\n;   The entry point TEMP-PTR1 is used from the SCANNING routine.\n;   Both TEMP-PTR1 and TEMP-PTR2 are used by the READ command routine.\n\n;; CH-ADD+1\nL0074:  LD      HL,($5C5D)      ; fetch address from CH_ADD.\n\n;; TEMP-PTR1\nL0077:  INC     HL              ; increase the character address by one.\n\n;; TEMP-PTR2\nL0078:  LD      ($5C5D),HL      ; update CH_ADD with character address.\n\nX007B:  LD      A,(HL)          ; load character to A from HL.\n        RET                     ; and return.\n\n; --------------------------\n; THE 'SKIP OVER' SUBROUTINE\n; --------------------------\n;   This subroutine is called once from RST 18 to skip over white-space and\n;   other characters irrelevant to the parsing of a BASIC line etc. .\n;   Initially the A register holds the character to be considered\n;   and HL holds its address which will not be within quoted text\n;   when a BASIC line is parsed.\n;   Although the 'tab' and 'at' characters will not appear in a BASIC line,\n;   they could be present in a string expression, and in other situations.\n;   Note. although white-space is usually placed in a program to indent loops\n;   and make it more readable, it can also be used for the opposite effect and\n;   spaces may appear in variable names although the parser never sees them.\n;   It is this routine that helps make the variables 'Anum bEr5 3BUS' and\n;   'a number 53 bus' appear the same to the parser.\n\n;; SKIP-OVER\nL007D:  CP      $21             ; test if higher than space.\n        RET     NC              ; return with carry clear if so.\n\n        CP      $0D             ; carriage return ?\n        RET     Z               ; return also with carry clear if so.\n\n                                ; all other characters have no relevance\n                                ; to the parser and must be returned with\n                                ; carry set.\n\n        CP      $10             ; test if 0-15d\n        RET     C               ; return, if so, with carry set.\n\n        CP      $18             ; test if 24-32d\n        CCF                     ; complement carry flag.\n        RET     C               ; return with carry set if so.\n\n                                ; now leaves 16d-23d\n\n        INC     HL              ; all above have at least one extra character\n                                ; to be stepped over.\n\n        CP      $16             ; controls 22d ('at') and 23d ('tab') have two.\n        JR      C,L0090         ; forward to SKIPS with ink, paper, flash,\n                                ; bright, inverse or over controls.\n                                ; Note. the high byte of tab is for RS232 only.\n                                ; it has no relevance on this machine.\n\n        INC     HL              ; step over the second character of 'at'/'tab'.\n\n;; SKIPS\nL0090:  SCF                     ; set the carry flag\n        LD      ($5C5D),HL      ; update the CH_ADD system variable.\n        RET                     ; return with carry set.\n\n\n; ------------------\n; THE 'TOKEN' TABLES\n; ------------------\n;   The tokenized characters 134d (RND) to 255d (COPY) are expanded using\n;   this table. The last byte of a token is inverted to denote the end of\n;   the word. The first is an inverted step-over byte.\n\n;; TKN-TABLE\nL0095:  DEFB    '?'+$80\n        DEFM    \"RN\"\n        DEFB    'D'+$80\n        DEFM    \"INKEY\"\n        DEFB    '$'+$80\n        DEFB    'P','I'+$80\n        DEFB    'F','N'+$80\n        DEFM    \"POIN\"\n        DEFB    'T'+$80\n        DEFM    \"SCREEN\"\n        DEFB    '$'+$80\n        DEFM    \"ATT\"\n        DEFB    'R'+$80\n        DEFB    'A','T'+$80\n        DEFM    \"TA\"\n        DEFB    'B'+$80\n        DEFM    \"VAL\"\n        DEFB    '$'+$80\n        DEFM    \"COD\"\n        DEFB    'E'+$80\n        DEFM    \"VA\"\n        DEFB    'L'+$80\n        DEFM    \"LE\"\n        DEFB    'N'+$80\n        DEFM    \"SI\"\n        DEFB    'N'+$80\n        DEFM    \"CO\"\n        DEFB    'S'+$80\n        DEFM    \"TA\"\n        DEFB    'N'+$80\n        DEFM    \"AS\"\n        DEFB    'N'+$80\n        DEFM    \"AC\"\n        DEFB    'S'+$80\n        DEFM    \"AT\"\n        DEFB    'N'+$80\n        DEFB    'L','N'+$80\n        DEFM    \"EX\"\n        DEFB    'P'+$80\n        DEFM    \"IN\"\n        DEFB    'T'+$80\n        DEFM    \"SQ\"\n        DEFB    'R'+$80\n        DEFM    \"SG\"\n        DEFB    'N'+$80\n        DEFM    \"AB\"\n        DEFB    'S'+$80\n        DEFM    \"PEE\"\n        DEFB    'K'+$80\n        DEFB    'I','N'+$80\n        DEFM    \"US\"\n        DEFB    'R'+$80\n        DEFM    \"STR\"\n        DEFB    '$'+$80\n        DEFM    \"CHR\"\n        DEFB    '$'+$80\n        DEFM    \"NO\"\n        DEFB    'T'+$80\n        DEFM    \"BI\"\n        DEFB    'N'+$80\n\n;   The previous 32 function-type words are printed without a leading space\n;   The following have a leading space if they begin with a letter\n\n        DEFB    'O','R'+$80\n        DEFM    \"AN\"\n        DEFB    'D'+$80\n        DEFB    $3C,'='+$80             ; <=\n        DEFB    $3E,'='+$80             ; >=\n        DEFB    $3C,$3E+$80             ; <>\n        DEFM    \"LIN\"\n        DEFB    'E'+$80\n        DEFM    \"THE\"\n        DEFB    'N'+$80\n        DEFB    'T','O'+$80\n        DEFM    \"STE\"\n        DEFB    'P'+$80\n        DEFM    \"DEF F\"\n        DEFB    'N'+$80\n        DEFM    \"CA\"\n        DEFB    'T'+$80\n        DEFM    \"FORMA\"\n        DEFB    'T'+$80\n        DEFM    \"MOV\"\n        DEFB    'E'+$80\n        DEFM    \"ERAS\"\n        DEFB    'E'+$80\n        DEFM    \"OPEN \"\n        DEFB    '#'+$80\n        DEFM    \"CLOSE \"\n        DEFB    '#'+$80\n        DEFM    \"MERG\"\n        DEFB    'E'+$80\n        DEFM    \"VERIF\"\n        DEFB    'Y'+$80\n        DEFM    \"BEE\"\n        DEFB    'P'+$80\n        DEFM    \"CIRCL\"\n        DEFB    'E'+$80\n        DEFM    \"IN\"\n        DEFB    'K'+$80\n        DEFM    \"PAPE\"\n        DEFB    'R'+$80\n        DEFM    \"FLAS\"\n        DEFB    'H'+$80\n        DEFM    \"BRIGH\"\n        DEFB    'T'+$80\n        DEFM    \"INVERS\"\n        DEFB    'E'+$80\n        DEFM    \"OVE\"\n        DEFB    'R'+$80\n        DEFM    \"OU\"\n        DEFB    'T'+$80\n        DEFM    \"LPRIN\"\n        DEFB    'T'+$80\n        DEFM    \"LLIS\"\n        DEFB    'T'+$80\n        DEFM    \"STO\"\n        DEFB    'P'+$80\n        DEFM    \"REA\"\n        DEFB    'D'+$80\n        DEFM    \"DAT\"\n        DEFB    'A'+$80\n        DEFM    \"RESTOR\"\n        DEFB    'E'+$80\n        DEFM    \"NE\"\n        DEFB    'W'+$80\n        DEFM    \"BORDE\"\n        DEFB    'R'+$80\n        DEFM    \"CONTINU\"\n        DEFB    'E'+$80\n        DEFM    \"DI\"\n        DEFB    'M'+$80\n        DEFM    \"RE\"\n        DEFB    'M'+$80\n        DEFM    \"FO\"\n        DEFB    'R'+$80\n        DEFM    \"GO T\"\n        DEFB    'O'+$80\n        DEFM    \"GO SU\"\n        DEFB    'B'+$80\n        DEFM    \"INPU\"\n        DEFB    'T'+$80\n        DEFM    \"LOA\"\n        DEFB    'D'+$80\n        DEFM    \"LIS\"\n        DEFB    'T'+$80\n        DEFM    \"LE\"\n        DEFB    'T'+$80\n        DEFM    \"PAUS\"\n        DEFB    'E'+$80\n        DEFM    \"NEX\"\n        DEFB    'T'+$80\n        DEFM    \"POK\"\n        DEFB    'E'+$80\n        DEFM    \"PRIN\"\n        DEFB    'T'+$80\n        DEFM    \"PLO\"\n        DEFB    'T'+$80\n        DEFM    \"RU\"\n        DEFB    'N'+$80\n        DEFM    \"SAV\"\n        DEFB    'E'+$80\n        DEFM    \"RANDOMIZ\"\n        DEFB    'E'+$80\n        DEFB    'I','F'+$80\n        DEFM    \"CL\"\n        DEFB    'S'+$80\n        DEFM    \"DRA\"\n        DEFB    'W'+$80\n        DEFM    \"CLEA\"\n        DEFB    'R'+$80\n        DEFM    \"RETUR\"\n        DEFB    'N'+$80\n        DEFM    \"COP\"\n        DEFB    'Y'+$80\n\n; ----------------\n; THE 'KEY' TABLES\n; ----------------\n;   These six look-up tables are used by the keyboard reading routine\n;   to decode the key values.\n;\n;   The first table contains the maps for the 39 keys of the standard\n;   40-key Spectrum keyboard. The remaining key [SHIFT $27] is read directly.\n;   The keys consist of the 26 upper-case alphabetic characters, the 10 digit\n;   keys and the space, ENTER and symbol shift key.\n;   Unshifted alphabetic keys have $20 added to the value.\n;   The keywords for the main alphabetic keys are obtained by adding $A5 to\n;   the values obtained from this table.\n\n;; MAIN-KEYS\nL0205:  DEFB    $42             ; B\n        DEFB    $48             ; H\n        DEFB    $59             ; Y\n        DEFB    $36             ; 6\n        DEFB    $35             ; 5\n        DEFB    $54             ; T\n        DEFB    $47             ; G\n        DEFB    $56             ; V\n        DEFB    $4E             ; N\n        DEFB    $4A             ; J\n        DEFB    $55             ; U\n        DEFB    $37             ; 7\n        DEFB    $34             ; 4\n        DEFB    $52             ; R\n        DEFB    $46             ; F\n        DEFB    $43             ; C\n        DEFB    $4D             ; M\n        DEFB    $4B             ; K\n        DEFB    $49             ; I\n        DEFB    $38             ; 8\n        DEFB    $33             ; 3\n        DEFB    $45             ; E\n        DEFB    $44             ; D\n        DEFB    $58             ; X\n        DEFB    $0E             ; SYMBOL SHIFT\n        DEFB    $4C             ; L\n        DEFB    $4F             ; O\n        DEFB    $39             ; 9\n        DEFB    $32             ; 2\n        DEFB    $57             ; W\n        DEFB    $53             ; S\n        DEFB    $5A             ; Z\n        DEFB    $20             ; SPACE\n        DEFB    $0D             ; ENTER\n        DEFB    $50             ; P\n        DEFB    $30             ; 0\n        DEFB    $31             ; 1\n        DEFB    $51             ; Q\n        DEFB    $41             ; A\n\n\n;; E-UNSHIFT\n;  The 26 unshifted extended mode keys for the alphabetic characters.\n;  The green keywords on the original keyboard.\nL022C:  DEFB    $E3             ; READ\n        DEFB    $C4             ; BIN\n        DEFB    $E0             ; LPRINT\n        DEFB    $E4             ; DATA\n        DEFB    $B4             ; TAN\n        DEFB    $BC             ; SGN\n        DEFB    $BD             ; ABS\n        DEFB    $BB             ; SQR\n        DEFB    $AF             ; CODE\n        DEFB    $B0             ; VAL\n        DEFB    $B1             ; LEN\n        DEFB    $C0             ; USR\n        DEFB    $A7             ; PI\n        DEFB    $A6             ; INKEY$\n        DEFB    $BE             ; PEEK\n        DEFB    $AD             ; TAB\n        DEFB    $B2             ; SIN\n        DEFB    $BA             ; INT\n        DEFB    $E5             ; RESTORE\n        DEFB    $A5             ; RND\n        DEFB    $C2             ; CHR$\n        DEFB    $E1             ; LLIST\n        DEFB    $B3             ; COS\n        DEFB    $B9             ; EXP\n        DEFB    $C1             ; STR$\n        DEFB    $B8             ; LN\n\n\n;; EXT-SHIFT\n;  The 26 shifted extended mode keys for the alphabetic characters.\n;  The red keywords below keys on the original keyboard.\nL0246:  DEFB    $7E             ; ~\n        DEFB    $DC             ; BRIGHT\n        DEFB    $DA             ; PAPER\n        DEFB    $5C             ; \\\n        DEFB    $B7             ; ATN\n        DEFB    $7B             ; {\n        DEFB    $7D             ; }\n        DEFB    $D8             ; CIRCLE\n        DEFB    $BF             ; IN\n        DEFB    $AE             ; VAL$\n        DEFB    $AA             ; SCREEN$\n        DEFB    $AB             ; ATTR\n        DEFB    $DD             ; INVERSE\n        DEFB    $DE             ; OVER\n        DEFB    $DF             ; OUT\n        DEFB    $7F             ; (Copyright character)\n        DEFB    $B5             ; ASN\n        DEFB    $D6             ; VERIFY\n        DEFB    $7C             ; |\n        DEFB    $D5             ; MERGE\n        DEFB    $5D             ; ]\n        DEFB    $DB             ; FLASH\n        DEFB    $B6             ; ACS\n        DEFB    $D9             ; INK\n        DEFB    $5B             ; [\n        DEFB    $D7             ; BEEP\n\n\n;; CTL-CODES\n;  The ten control codes assigned to the top line of digits when the shift\n;  key is pressed.\nL0260:  DEFB    $0C             ; DELETE\n        DEFB    $07             ; EDIT\n        DEFB    $06             ; CAPS LOCK\n        DEFB    $04             ; TRUE VIDEO\n        DEFB    $05             ; INVERSE VIDEO\n        DEFB    $08             ; CURSOR LEFT\n        DEFB    $0A             ; CURSOR DOWN\n        DEFB    $0B             ; CURSOR UP\n        DEFB    $09             ; CURSOR RIGHT\n        DEFB    $0F             ; GRAPHICS\n\n\n;; SYM-CODES\n;  The 26 red symbols assigned to the alphabetic characters of the keyboard.\n;  The ten single-character digit symbols are converted without the aid of\n;  a table using subtraction and minor manipulation.\nL026A:  DEFB    $E2             ; STOP\n        DEFB    $2A             ; *\n        DEFB    $3F             ; ?\n        DEFB    $CD             ; STEP\n        DEFB    $C8             ; >=\n        DEFB    $CC             ; TO\n        DEFB    $CB             ; THEN\n        DEFB    $5E             ; ^\n        DEFB    $AC             ; AT\n        DEFB    $2D             ; -\n        DEFB    $2B             ; +\n        DEFB    $3D             ; =\n        DEFB    $2E             ; .\n        DEFB    $2C             ; ,\n        DEFB    $3B             ; ;\n        DEFB    $22             ; \"\n        DEFB    $C7             ; <=\n        DEFB    $3C             ; <\n        DEFB    $C3             ; NOT\n        DEFB    $3E             ; >\n        DEFB    $C5             ; OR\n        DEFB    $2F             ; /\n        DEFB    $C9             ; <>\n        DEFB    $60             ; pound\n        DEFB    $C6             ; AND\n        DEFB    $3A             ; :\n\n;; E-DIGITS\n;  The ten keywords assigned to the digits in extended mode.\n;  The remaining red keywords below the keys.\nL0284:  DEFB    $D0             ; FORMAT\n        DEFB    $CE             ; DEF FN\n        DEFB    $A8             ; FN\n        DEFB    $CA             ; LINE\n        DEFB    $D3             ; OPEN #\n        DEFB    $D4             ; CLOSE #\n        DEFB    $D1             ; MOVE\n        DEFB    $D2             ; ERASE\n        DEFB    $A9             ; POINT\n        DEFB    $CF             ; CAT\n\n\n;*******************************\n;** Part 2. KEYBOARD ROUTINES **\n;*******************************\n\n;   Using shift keys and a combination of modes the Spectrum 40-key keyboard\n;   can be mapped to 256 input characters\n\n; ---------------------------------------------------------------------------\n;\n;         0     1     2     3     4 -Bits-  4     3     2     1     0\n; PORT                                                                    PORT\n;\n; F7FE  [ 1 ] [ 2 ] [ 3 ] [ 4 ] [ 5 ]  |  [ 6 ] [ 7 ] [ 8 ] [ 9 ] [ 0 ]   EFFE\n;  ^                                   |                                   v\n; FBFE  [ Q ] [ W ] [ E ] [ R ] [ T ]  |  [ Y ] [ U ] [ I ] [ O ] [ P ]   DFFE\n;  ^                                   |                                   v\n; FDFE  [ A ] [ S ] [ D ] [ F ] [ G ]  |  [ H ] [ J ] [ K ] [ L ] [ ENT ] BFFE\n;  ^                                   |                                   v\n; FEFE  [SHI] [ Z ] [ X ] [ C ] [ V ]  |  [ B ] [ N ] [ M ] [sym] [ SPC ] 7FFE\n;  ^     $27                                                 $18           v\n; Start                                                                   End\n;        00100111                                            00011000\n;\n; ---------------------------------------------------------------------------\n;   The above map may help in reading.\n;   The neat arrangement of ports means that the B register need only be\n;   rotated left to work up the left hand side and then down the right\n;   hand side of the keyboard. When the reset bit drops into the carry\n;   then all 8 half-rows have been read. Shift is the first key to be\n;   read. The lower six bits of the shifts are unambiguous.\n\n; -------------------------------\n; THE 'KEYBOARD SCANNING' ROUTINE\n; -------------------------------\n;   From keyboard and s-inkey$\n;   Returns 1 or 2 keys in DE, most significant shift first if any\n;   key values 0-39 else 255\n\n;; KEY-SCAN\nL028E:  LD      L,$2F           ; initial key value\n                                ; valid values are obtained by subtracting\n                                ; eight five times.\n        LD      DE,$FFFF        ; a buffer to receive 2 keys.\n\n        LD      BC,$FEFE        ; the commencing port address\n                                ; B holds 11111110 initially and is also\n                                ; used to count the 8 half-rows\n;; KEY-LINE\nL0296:  IN      A,(C)           ; read the port to A - bits will be reset\n                                ; if a key is pressed else set.\n        CPL                     ; complement - pressed key-bits are now set\n        AND     $1F             ; apply 00011111 mask to pick up the\n                                ; relevant set bits.\n\n        JR      Z,L02AB         ; forward to KEY-DONE if zero and therefore\n                                ; no keys pressed in row at all.\n\n        LD      H,A             ; transfer row bits to H\n        LD      A,L             ; load the initial key value to A\n\n;; KEY-3KEYS\nL029F:  INC     D               ; now test the key buffer\n        RET     NZ              ; if we have collected 2 keys already\n                                ; then too many so quit.\n\n;; KEY-BITS\nL02A1:  SUB     $08             ; subtract 8 from the key value\n                                ; cycling through key values (top = $27)\n                                ; e.g. 2F>   27>1F>17>0F>07\n                                ;      2E>   26>1E>16>0E>06\n        SRL     H               ; shift key bits right into carry.\n        JR      NC,L02A1        ; back to KEY-BITS if not pressed\n                                ; but if pressed we have a value (0-39d)\n\n        LD      D,E             ; transfer a possible previous key to D\n        LD      E,A             ; transfer the new key to E\n        JR      NZ,L029F        ; back to KEY-3KEYS if there were more\n                                ; set bits - H was not yet zero.\n\n;; KEY-DONE\nL02AB:  DEC     L               ; cycles 2F>2E>2D>2C>2B>2A>29>28 for\n                                ; each half-row.\n        RLC     B               ; form next port address e.g. FEFE > FDFE\n        JR      C,L0296         ; back to KEY-LINE if still more rows to do.\n\n        LD      A,D             ; now test if D is still FF ?\n        INC     A               ; if it is zero we have at most 1 key\n                                ; range now $01-$28  (1-40d)\n        RET     Z               ; return if one key or no key.\n\n        CP      $28             ; is it capsshift (was $27) ?\n        RET     Z               ; return if so.\n\n        CP      $19             ; is it symbol shift (was $18) ?\n        RET     Z               ; return also\n\n        LD      A,E             ; now test E\n        LD      E,D             ; but first switch\n        LD      D,A             ; the two keys.\n        CP      $18             ; is it symbol shift ?\n        RET                     ; return (with zero set if it was).\n                                ; but with symbol shift now in D\n\n; ----------------------\n; THE 'KEYBOARD' ROUTINE\n; ----------------------\n;   Called from the interrupt 50 times a second.\n;\n\n;; KEYBOARD\nL02BF:  CALL    L028E           ; routine KEY-SCAN\n        RET     NZ              ; return if invalid combinations\n\n;   then decrease the counters within the two key-state maps\n;   as this could cause one to become free.\n;   if the keyboard has not been pressed during the last five interrupts\n;   then both sets will be free.\n\n\n        LD      HL,$5C00        ; point to KSTATE-0\n\n;; K-ST-LOOP\nL02C6:  BIT     7,(HL)          ; is it free ?  (i.e. $FF)\n        JR      NZ,L02D1        ; forward to K-CH-SET if so\n\n        INC     HL              ; address the 5-counter\n        DEC     (HL)            ; decrease the counter\n        DEC     HL              ; step back\n\n        JR      NZ,L02D1        ; forward to K-CH-SET if not at end of count\n\n        LD      (HL),$FF        ; else mark this particular map free.\n\n;; K-CH-SET\nL02D1:  LD      A,L             ; make a copy of the low address byte.\n        LD      HL,$5C04        ; point to KSTATE-4\n                                ; (ld l,$04 would do)\n        CP      L               ; have both sets been considered ?\n        JR      NZ,L02C6        ; back to K-ST-LOOP to consider this 2nd set\n\n;   now the raw key (0-38d) is converted to a main key (uppercase).\n\n        CALL    L031E           ; routine K-TEST to get main key in A\n\n        RET     NC              ; return if just a single shift\n\n        LD      HL,$5C00        ; point to KSTATE-0\n        CP      (HL)            ; does the main key code match ?\n        JR      Z,L0310         ; forward to K-REPEAT if so\n\n;   if not consider the second key map.\n\n        EX      DE,HL           ; save kstate-0 in de\n        LD      HL,$5C04        ; point to KSTATE-4\n        CP      (HL)            ; does the main key code match ?\n        JR      Z,L0310         ; forward to K-REPEAT if so\n\n;   having excluded a repeating key we can now consider a new key.\n;   the second set is always examined before the first.\n\n        BIT     7,(HL)          ; is the key map free ?\n        JR      NZ,L02F1        ; forward to K-NEW if so.\n\n        EX      DE,HL           ; bring back KSTATE-0\n        BIT     7,(HL)          ; is it free ?\n        RET     Z               ; return if not.\n                                ; as we have a key but nowhere to put it yet.\n\n;   continue or jump to here if one of the buffers was free.\n\n;; K-NEW\nL02F1:  LD      E,A             ; store key in E\n        LD      (HL),A          ; place in free location\n        INC     HL              ; advance to the interrupt counter\n        LD      (HL),$05        ; and initialize counter to 5\n        INC     HL              ; advance to the delay\n        LD      A,($5C09)       ; pick up the system variable REPDEL\n        LD      (HL),A          ; and insert that for first repeat delay.\n        INC     HL              ; advance to last location of state map.\n\n        LD      C,(IY+$07)      ; pick up MODE  (3 bytes)\n        LD      D,(IY+$01)      ; pick up FLAGS (3 bytes)\n        PUSH    HL              ; save state map location\n                                ; Note. could now have used, to avoid IY,\n                                ; ld l,$41; ld c,(hl); ld l,$3B; ld d,(hl).\n                                ; six and two threes of course.\n\n        CALL    L0333           ; routine K-DECODE\n\n        POP     HL              ; restore map pointer\n        LD      (HL),A          ; put the decoded key in last location of map.\n\n;; K-END\nL0308:  LD      ($5C08),A       ; update LASTK system variable.\n        SET     5,(IY+$01)      ; update FLAGS  - signal a new key.\n        RET                     ; return to interrupt routine.\n\n; -----------------------\n; THE 'REPEAT KEY' BRANCH\n; -----------------------\n;   A possible repeat has been identified. HL addresses the raw key.\n;   The last location of the key map holds the decoded key from the first\n;   context.  This could be a keyword and, with the exception of NOT a repeat\n;   is syntactically incorrect and not really desirable.\n\n;; K-REPEAT\nL0310:  INC     HL              ; increment the map pointer to second location.\n        LD      (HL),$05        ; maintain interrupt counter at 5.\n        INC     HL              ; now point to third location.\n        DEC     (HL)            ; decrease the REPDEL value which is used to\n                                ; time the delay of a repeat key.\n\n        RET     NZ              ; return if not yet zero.\n\n        LD      A,($5C0A)       ; fetch the system variable value REPPER.\n        LD      (HL),A          ; for subsequent repeats REPPER will be used.\n\n        INC     HL              ; advance\n                                ;\n        LD      A,(HL)          ; pick up the key decoded possibly in another\n                                ; context.\n                                ; Note. should compare with $A5 (RND) and make\n                                ; a simple return if this is a keyword.\n                                ; e.g. cp $a5; ret nc; (3 extra bytes)\n        JR      L0308           ; back to K-END\n\n; ----------------------\n; THE 'KEY-TEST' ROUTINE\n; ----------------------\n;   also called from s-inkey$\n;   begin by testing for a shift with no other.\n\n;; K-TEST\nL031E:  LD      B,D             ; load most significant key to B\n                                ; will be $FF if not shift.\n        LD      D,$00           ; and reset D to index into main table\n        LD      A,E             ; load least significant key from E\n        CP      $27             ; is it higher than 39d   i.e. FF\n        RET     NC              ; return with just a shift (in B now)\n\n        CP      $18             ; is it symbol shift ?\n        JR      NZ,L032C        ; forward to K-MAIN if not\n\n;   but we could have just symbol shift and no other\n\n        BIT     7,B             ; is other key $FF (ie not shift)\n        RET     NZ              ; return with solitary symbol shift\n\n\n;; K-MAIN\nL032C:  LD      HL,L0205        ; address: MAIN-KEYS\n        ADD     HL,DE           ; add offset 0-38\n        LD      A,(HL)          ; pick up main key value\n        SCF                     ; set carry flag\n        RET                     ; return    (B has other key still)\n\n; ----------------------------------\n; THE 'KEYBOARD DECODING' SUBROUTINE\n; ----------------------------------\n;   also called from s-inkey$\n\n;; K-DECODE\nL0333:  LD      A,E             ; pick up the stored main key\n        CP      $3A             ; an arbitrary point between digits and letters\n        JR      C,L0367         ; forward to K-DIGIT with digits, space, enter.\n\n        DEC     C               ; decrease MODE ( 0='KLC', 1='E', 2='G')\n\n        JP      M,L034F         ; to K-KLC-LET if was zero\n\n        JR      Z,L0341         ; to K-E-LET if was 1 for extended letters.\n\n;   proceed with graphic codes.\n;   Note. should selectively drop return address if code > 'U' ($55).\n;   i.e. abort the KEYBOARD call.\n;   e.g. cp 'V'; jr c,addit; pop af ;pop af ;;addit etc. (6 extra bytes).\n;   (s-inkey$ never gets into graphics mode.)\n\n;; addit\n        ADD     A,$4F           ; add offset to augment 'A' to graphics A say.\n        RET                     ; return.\n                                ; Note. ( but [GRAPH] V gives RND, etc ).\n\n; ---\n\n;   the jump was to here with extended mode with uppercase A-Z.\n\n;; K-E-LET\nL0341:  LD      HL,L022C-$41    ; base address of E-UNSHIFT L022c.\n                                ; ( $01EB in standard ROM ).\n        INC     B               ; test B is it empty i.e. not a shift.\n        JR      Z,L034A         ; forward to K-LOOK-UP if neither shift.\n\n        LD      HL,L0246-$41    ; Address: $0205 L0246-$41 EXT-SHIFT base\n\n;; K-LOOK-UP\nL034A:  LD      D,$00           ; prepare to index.\n        ADD     HL,DE           ; add the main key value.\n        LD      A,(HL)          ; pick up other mode value.\n        RET                     ; return.\n\n; ---\n\n;   the jump was here with mode = 0\n\n;; K-KLC-LET\nL034F:  LD      HL,L026A-$41    ; prepare base of sym-codes\n        BIT     0,B             ; shift=$27 sym-shift=$18\n        JR      Z,L034A         ; back to K-LOOK-UP with symbol-shift\n\n        BIT     3,D             ; test FLAGS is it 'K' mode (from OUT-CURS)\n        JR      Z,L0364         ; skip to K-TOKENS if so\n\n        BIT     3,(IY+$30)      ; test FLAGS2 - consider CAPS LOCK ?\n        RET     NZ              ; return if so with main code.\n\n        INC     B               ; is shift being pressed ?\n                                ; result zero if not\n        RET     NZ              ; return if shift pressed.\n\n        ADD     A,$20           ; else convert the code to lower case.\n        RET                     ; return.\n\n; ---\n\n;   the jump was here for tokens\n\n;; K-TOKENS\nL0364:  ADD     A,$A5           ; add offset to main code so that 'A'\n                                ; becomes 'NEW' etc.\n\n        RET                     ; return.\n\n; ---\n\n;   the jump was here with digits, space, enter and symbol shift (< $xx)\n\n;; K-DIGIT\nL0367:  CP      $30             ; is it '0' or higher ?\n        RET     C               ; return with space, enter and symbol-shift\n\n        DEC     C               ; test MODE (was 0='KLC', 1='E', 2='G')\n        JP      M,L039D         ; jump to K-KLC-DGT if was 0.\n\n        JR      NZ,L0389        ; forward to K-GRA-DGT if mode was 2.\n\n;   continue with extended digits 0-9.\n\n        LD      HL,L0284-$30    ; $0254 - base of E-DIGITS\n        BIT     5,B             ; test - shift=$27 sym-shift=$18\n        JR      Z,L034A         ; to K-LOOK-UP if sym-shift\n\n        CP      $38             ; is character '8' ?\n        JR      NC,L0382        ; to K-8-&-9 if greater than '7'\n\n        SUB     $20             ; reduce to ink range $10-$17\n        INC     B               ; shift ?\n        RET     Z               ; return if not.\n\n        ADD     A,$08           ; add 8 to give paper range $18 - $1F\n        RET                     ; return\n\n; ---\n\n;   89\n\n;; K-8-&-9\nL0382:  SUB     $36             ; reduce to 02 and 03  bright codes\n        INC     B               ; test if shift pressed.\n        RET     Z               ; return if not.\n\n        ADD     A,$FE           ; subtract 2 setting carry\n        RET                     ; to give 0 and 1    flash codes.\n\n; ---\n\n;   graphics mode with digits\n\n;; K-GRA-DGT\nL0389:  LD      HL,L0260-$30    ; $0230 base address of CTL-CODES\n\n        CP      $39             ; is key '9' ?\n        JR      Z,L034A         ; back to K-LOOK-UP - changed to $0F, GRAPHICS.\n\n        CP      $30             ; is key '0' ?\n        JR      Z,L034A         ; back to K-LOOK-UP - changed to $0C, delete.\n\n;   for keys '0' - '7' we assign a mosaic character depending on shift.\n\n        AND     $07             ; convert character to number. 0 - 7.\n        ADD     A,$80           ; add offset - they start at $80\n\n        INC     B               ; destructively test for shift\n        RET     Z               ; and return if not pressed.\n\n        XOR     $0F             ; toggle bits becomes range $88-$8F\n        RET                     ; return.\n\n; ---\n\n;   now digits in 'KLC' mode\n\n;; K-KLC-DGT\nL039D:  INC     B               ; return with digit codes if neither\n        RET     Z               ; shift key pressed.\n\n        BIT     5,B             ; test for caps shift.\n\n        LD      HL,L0260-$30    ; prepare base of table CTL-CODES.\n        JR      NZ,L034A        ; back to K-LOOK-UP if shift pressed.\n\n;   must have been symbol shift\n\n        SUB     $10             ; for ASCII most will now be correct\n                                ; on a standard typewriter.\n\n        CP      $22             ; but '@' is not - see below.\n        JR      Z,L03B2         ; forward to K-@-CHAR if so\n\n        CP      $20             ; '_' is the other one that fails\n        RET     NZ              ; return if not.\n\n        LD      A,$5F           ; substitute ASCII '_'\n        RET                     ; return.\n\n; ---\n\n;; K-@-CHAR\nL03B2:  LD      A,$40           ; substitute ASCII '@'\n        RET                     ; return.\n\n\n; ------------------------------------------------------------------------\n;   The Spectrum Input character keys. One or two are abbreviated.\n;   From $00 Flash 0 to $FF COPY. The routine above has decoded all these.\n\n;  | 00 Fl0| 01 Fl1| 02 Br0| 03 Br1| 04 In0| 05 In1| 06 CAP| 07 EDT|\n;  | 08 LFT| 09 RIG| 0A DWN| 0B UP | 0C DEL| 0D ENT| 0E SYM| 0F GRA|\n;  | 10 Ik0| 11 Ik1| 12 Ik2| 13 Ik3| 14 Ik4| 15 Ik5| 16 Ik6| 17 Ik7|\n;  | 18 Pa0| 19 Pa1| 1A Pa2| 1B Pa3| 1C Pa4| 1D Pa5| 1E Pa6| 1F Pa7|\n;  | 20 SP | 21  ! | 22  \" | 23  # | 24  $ | 25  % | 26  & | 27  ' |\n;  | 28  ( | 29  ) | 2A  * | 2B  + | 2C  , | 2D  - | 2E  . | 2F  / |\n;  | 30  0 | 31  1 | 32  2 | 33  3 | 34  4 | 35  5 | 36  6 | 37  7 |\n;  | 38  8 | 39  9 | 3A  : | 3B  ; | 3C  < | 3D  = | 3E  > | 3F  ? |\n;  | 40  @ | 41  A | 42  B | 43  C | 44  D | 45  E | 46  F | 47  G |\n;  | 48  H | 49  I | 4A  J | 4B  K | 4C  L | 4D  M | 4E  N | 4F  O |\n;  | 50  P | 51  Q | 52  R | 53  S | 54  T | 55  U | 56  V | 57  W |\n;  | 58  X | 59  Y | 5A  Z | 5B  [ | 5C  \\ | 5D  ] | 5E  ^ | 5F  _ |\n;  | 60  £ | 61  a | 62  b | 63  c | 64  d | 65  e | 66  f | 67  g |\n;  | 68  h | 69  i | 6A  j | 6B  k | 6C  l | 6D  m | 6E  n | 6F  o |\n;  | 70  p | 71  q | 72  r | 73  s | 74  t | 75  u | 76  v | 77  w |\n;  | 78  x | 79  y | 7A  z | 7B  { | 7C  | | 7D  } | 7E  ~ | 7F  © |\n;  | 80 128| 81 129| 82 130| 83 131| 84 132| 85 133| 86 134| 87 135|\n;  | 88 136| 89 137| 8A 138| 8B 139| 8C 140| 8D 141| 8E 142| 8F 143|\n;  | 90 [A]| 91 [B]| 92 [C]| 93 [D]| 94 [E]| 95 [F]| 96 [G]| 97 [H]|\n;  | 98 [I]| 99 [J]| 9A [K]| 9B [L]| 9C [M]| 9D [N]| 9E [O]| 9F [P]|\n;  | A0 [Q]| A1 [R]| A2 [S]| A3 [T]| A4 [U]| A5 RND| A6 IK$| A7 PI |\n;  | A8 FN | A9 PNT| AA SC$| AB ATT| AC AT | AD TAB| AE VL$| AF COD|\n;  | B0 VAL| B1 LEN| B2 SIN| B3 COS| B4 TAN| B5 ASN| B6 ACS| B7 ATN|\n;  | B8 LN | B9 EXP| BA INT| BB SQR| BC SGN| BD ABS| BE PEK| BF IN |\n;  | C0 USR| C1 ST$| C2 CH$| C3 NOT| C4 BIN| C5 OR | C6 AND| C7 <= |\n;  | C8 >= | C9 <> | CA LIN| CB THN| CC TO | CD STP| CE DEF| CF CAT|\n;  | D0 FMT| D1 MOV| D2 ERS| D3 OPN| D4 CLO| D5 MRG| D6 VFY| D7 BEP|\n;  | D8 CIR| D9 INK| DA PAP| DB FLA| DC BRI| DD INV| DE OVR| DF OUT|\n;  | E0 LPR| E1 LLI| E2 STP| E3 REA| E4 DAT| E5 RES| E6 NEW| E7 BDR|\n;  | E8 CON| E9 DIM| EA REM| EB FOR| EC GTO| ED GSB| EE INP| EF LOA|\n;  | F0 LIS| F1 LET| F2 PAU| F3 NXT| F4 POK| F5 PRI| F6 PLO| F7 RUN|\n;  | F8 SAV| F9 RAN| FA IF | FB CLS| FC DRW| FD CLR| FE RET| FF CPY|\n\n;   Note that for simplicity, Sinclair have located all the control codes\n;   below the space character.\n;   ASCII DEL, $7F, has been made a copyright symbol.\n;   Also $60, '`', not used in BASIC but used in other languages, has been\n;   allocated the local currency symbol for the relevant country -\n;    £  in most Spectrums.\n\n; ------------------------------------------------------------------------\n\n\n;**********************************\n;** Part 3. LOUDSPEAKER ROUTINES **\n;**********************************\n\n; Documented by Alvin Albrecht.\n\n; ------------------------------\n; Routine to control loudspeaker\n; ------------------------------\n; Outputs a square wave of given duration and frequency\n; to the loudspeaker.\n;   Enter with: DE = #cycles - 1\n;               HL = tone period as described next\n;\n; The tone period is measured in T states and consists of\n; three parts: a coarse part (H register), a medium part\n; (bits 7..2 of L) and a fine part (bits 1..0 of L) which\n; contribute to the waveform timing as follows:\n;\n;                          coarse    medium       fine\n; duration of low  = 118 + 1024*H + 16*(L>>2) + 4*(L&0x3)\n; duration of hi   = 118 + 1024*H + 16*(L>>2) + 4*(L&0x3)\n; Tp = tone period = 236 + 2048*H + 32*(L>>2) + 8*(L&0x3)\n;                  = 236 + 2048*H + 8*L = 236 + 8*HL\n;\n; As an example, to output five seconds of middle C (261.624 Hz):\n;   (a) Tone period = 1/261.624 = 3.822ms\n;   (b) Tone period in T-States = 3.822ms*fCPU = 13378\n;         where fCPU = clock frequency of the CPU = 3.5MHz\n;    ©  Find H and L for desired tone period:\n;         HL = (Tp - 236) / 8 = (13378 - 236) / 8 = 1643 = 0x066B\n;   (d) Tone duration in cycles = 5s/3.822ms = 1308 cycles\n;         DE = 1308 - 1 = 0x051B\n;\n; The resulting waveform has a duty ratio of exactly 50%.\n;\n;\n;; BEEPER\nL03B5:  DI                      ; Disable Interrupts so they don't disturb timing\n        LD      A,L             ;\n        SRL     L               ;\n        SRL     L               ; L = medium part of tone period\n        CPL                     ;\n        AND     $03             ; A = 3 - fine part of tone period\n        LD      C,A             ;\n        LD      B,$00           ;\n        LD      IX,L03D1        ; Address: BE-IX+3\n        ADD     IX,BC           ;   IX holds address of entry into the loop\n                                ;   the loop will contain 0-3 NOPs, implementing\n                                ;   the fine part of the tone period.\n        LD      A,($5C48)       ; BORDCR\n        AND     $38             ; bits 5..3 contain border colour\n        RRCA                    ; border colour bits moved to 2..0\n        RRCA                    ;   to match border bits on port #FE\n        RRCA                    ;\n        OR       $08            ; bit 3 set (tape output bit on port #FE)\n                                ;   for loud sound output\n;; BE-IX+3\nL03D1:  NOP              ;(4)   ; optionally executed NOPs for small\n                                ;   adjustments to tone period\n;; BE-IX+2\nL03D2:  NOP              ;(4)   ;\n\n;; BE-IX+1\nL03D3:  NOP              ;(4)   ;\n\n;; BE-IX+0\nL03D4:  INC     B        ;(4)   ;\n        INC     C        ;(4)   ;\n\n;; BE-H&L-LP\nL03D6:  DEC     C        ;(4)   ; timing loop for duration of\n        JR      NZ,L03D6 ;(12/7);   high or low pulse of waveform\n\n        LD      C,$3F    ;(7)   ;\n        DEC     B        ;(4)   ;\n        JP      NZ,L03D6 ;(10)  ; to BE-H&L-LP\n\n        XOR     $10      ;(7)   ; toggle output beep bit\n        OUT     ($FE),A  ;(11)  ; output pulse\n        LD      B,H      ;(4)   ; B = coarse part of tone period\n        LD      C,A      ;(4)   ; save port #FE output byte\n        BIT     4,A      ;(8)   ; if new output bit is high, go\n        JR      NZ,L03F2 ;(12/7);   to BE-AGAIN\n\n        LD      A,D      ;(4)   ; one cycle of waveform has completed\n        OR      E        ;(4)   ;   (low->low). if cycle countdown = 0\n        JR      Z,L03F6  ;(12/7);   go to BE-END\n\n        LD      A,C      ;(4)   ; restore output byte for port #FE\n        LD      C,L      ;(4)   ; C = medium part of tone period\n        DEC     DE       ;(6)   ; decrement cycle count\n        JP      (IX)     ;(8)   ; do another cycle\n\n;; BE-AGAIN                     ; halfway through cycle\nL03F2:  LD      C,L      ;(4)   ; C = medium part of tone period\n        INC     C        ;(4)   ; adds 16 cycles to make duration of high = duration of low\n        JP      (IX)     ;(8)   ; do high pulse of tone\n\n;; BE-END\nL03F6:  EI                      ; Enable Interrupts\n        RET                     ;\n\n\n; ------------------\n; THE 'BEEP' COMMAND\n; ------------------\n; BASIC interface to BEEPER subroutine.\n; Invoked in BASIC with:\n;   BEEP dur, pitch\n;   where dur   = duration in seconds\n;         pitch = # of semitones above/below middle C\n;\n; Enter with: pitch on top of calculator stack\n;             duration next on calculator stack\n;\n;; beep\nL03F8:  RST     28H             ;; FP-CALC\n        DEFB    $31             ;;duplicate                  ; duplicate pitch\n        DEFB    $27             ;;int                        ; convert to integer\n        DEFB    $C0             ;;st-mem-0                   ; store integer pitch to memory 0\n        DEFB    $03             ;;subtract                   ; calculate fractional part of pitch = fp_pitch - int_pitch\n        DEFB    $34             ;;stk-data                   ; push constant\n        DEFB    $EC             ;;Exponent: $7C, Bytes: 4    ; constant = 0.05762265\n        DEFB    $6C,$98,$1F,$F5 ;;($6C,$98,$1F,$F5)\n        DEFB    $04             ;;multiply                   ; compute:\n        DEFB    $A1             ;;stk-one                    ; 1 + 0.05762265 * fraction_part(pitch)\n        DEFB    $0F             ;;addition\n        DEFB    $38             ;;end-calc                   ; leave on calc stack\n\n        LD      HL,$5C92        ; MEM-0: number stored here is in 16 bit integer format (pitch)\n                                ;   0, 0/FF (pos/neg), LSB, MSB, 0\n                                ;   LSB/MSB is stored in two's complement\n                                ; In the following, the pitch is checked if it is in the range -128<=p<=127\n        LD      A,(HL)          ; First byte must be zero, otherwise\n        AND     A               ;   error in integer conversion\n        JR      NZ,L046C        ; to REPORT-B\n\n        INC     HL              ;\n        LD      C,(HL)          ; C = pos/neg flag = 0/FF\n        INC     HL              ;\n        LD      B,(HL)          ; B = LSB, two's complement\n        LD      A,B             ;\n        RLA                     ;\n        SBC     A,A             ; A = 0/FF if B is pos/neg\n        CP      C               ; must be the same as C if the pitch is -128<=p<=127\n        JR      NZ,L046C        ; if no, error REPORT-B\n\n        INC     HL              ; if -128<=p<=127, MSB will be 0/FF if B is pos/neg\n        CP      (HL)            ; verify this\n        JR      NZ,L046C        ; if no, error REPORT-B\n                                ; now we know -128<=p<=127\n        LD      A,B             ; A = pitch + 60\n        ADD     A,$3C           ; if -60<=pitch<=67,\n        JP      P,L0425         ;   goto BE-i-OK\n\n        JP      PO,L046C        ; if pitch <= 67 goto REPORT-B\n                                ;   lower bound of pitch set at -60\n\n;; BE-I-OK                      ; here, -60<=pitch<=127\n                                ; and A=pitch+60 -> 0<=A<=187\n\nL0425:  LD      B,$FA           ; 6 octaves below middle C\n\n;; BE-OCTAVE                    ; A=# semitones above 5 octaves below middle C\nL0427:  INC     B               ; increment octave\n        SUB     $0C             ; 12 semitones = one octave\n        JR      NC,L0427        ; to BE-OCTAVE\n\n        ADD     A,$0C           ; A = # semitones above C (0-11)\n        PUSH    BC              ; B = octave displacement from middle C, 2's complement: -5<=B<=10\n        LD      HL,L046E        ; Address: semi-tone\n        CALL    L3406           ; routine LOC-MEM\n                                ;   HL = 5*A + $046E\n        CALL    L33B4           ; routine STACK-NUM\n                                ;   read FP value (freq) from semitone table (HL) and push onto calc stack\n\n        RST     28H             ;; FP-CALC\n        DEFB    $04             ;;multiply   mult freq by 1 + 0.0576 * fraction_part(pitch) stacked earlier\n                                ;;             thus taking into account fractional part of pitch.\n                                ;;           the number 0.0576*frequency is the distance in Hz to the next\n                                ;;             note (verify with the frequencies recorded in the semitone\n                                ;;             table below) so that the fraction_part of the pitch does\n                                ;;             indeed represent a fractional distance to the next note.\n        DEFB    $38             ;;end-calc   HL points to first byte of fp num on stack = middle frequency to generate\n\n        POP     AF              ; A = octave displacement from middle C, 2's complement: -5<=A<=10\n        ADD     A,(HL)          ; increase exponent by A (equivalent to multiplying by 2^A)\n        LD      (HL),A          ;\n\n        RST     28H             ;; FP-CALC\n        DEFB    $C0             ;;st-mem-0          ; store frequency in memory 0\n        DEFB    $02             ;;delete            ; remove from calc stack\n        DEFB    $31             ;;duplicate         ; duplicate duration (seconds)\n        DEFB    $38             ;;end-calc\n\n        CALL    L1E94           ; routine FIND-INT1 ; FP duration to A\n        CP      $0B             ; if dur > 10 seconds,\n        JR      NC,L046C        ;   goto REPORT-B\n\n        ;;; The following calculation finds the tone period for HL and the cycle count\n        ;;; for DE expected in the BEEPER subroutine.  From the example in the BEEPER comments,\n        ;;;\n        ;;; HL = ((fCPU / f) - 236) / 8 = fCPU/8/f - 236/8 = 437500/f -29.5\n        ;;; DE = duration * frequency - 1\n        ;;;\n        ;;; Note the different constant (30.125) used in the calculation of HL\n        ;;; below.  This is probably an error.\n\n        RST     28H             ;; FP-CALC\n        DEFB    $E0             ;;get-mem-0                 ; push frequency\n        DEFB    $04             ;;multiply                  ; result1: #cycles = duration * frequency\n        DEFB    $E0             ;;get-mem-0                 ; push frequency\n        DEFB    $34             ;;stk-data                  ; push constant\n        DEFB    $80             ;;Exponent $93, Bytes: 3    ; constant = 437500\n        DEFB    $43,$55,$9F,$80 ;;($55,$9F,$80,$00)\n        DEFB    $01             ;;exchange                  ; frequency on top\n        DEFB    $05             ;;division                  ; 437500 / frequency\n        DEFB    $34             ;;stk-data                  ; push constant\n        DEFB    $35             ;;Exponent: $85, Bytes: 1   ; constant = 30.125\n        DEFB    $71             ;;($71,$00,$00,$00)\n        DEFB    $03             ;;subtract                  ; result2: tone_period(HL) = 437500 / freq - 30.125\n        DEFB    $38             ;;end-calc\n\n        CALL    L1E99           ; routine FIND-INT2\n        PUSH    BC              ;   BC = tone_period(HL)\n        CALL    L1E99           ; routine FIND-INT2, BC = #cycles to generate\n        POP     HL              ; HL = tone period\n        LD      D,B             ;\n        LD      E,C             ; DE = #cycles\n        LD      A,D             ;\n        OR      E               ;\n        RET     Z               ; if duration = 0, skip BEEP and avoid 65536 cycle\n                                ;   boondoggle that would occur next\n        DEC     DE              ; DE = #cycles - 1\n        JP      L03B5           ; to BEEPER\n\n; ---\n\n\n;; REPORT-B\nL046C:  RST     08H             ; ERROR-1\n        DEFB    $0A             ; Error Report: Integer out of range\n\n\n\n; ---------------------\n; THE 'SEMI-TONE' TABLE\n; ---------------------\n;\n;   Holds frequencies corresponding to semitones in middle octave.\n;   To move n octaves higher or lower, frequencies are multiplied by 2^n.\n\n;; semi-tone         five byte fp         decimal freq     note (middle)\nL046E:  DEFB    $89, $02, $D0, $12, $86;  261.625565290         C\n        DEFB    $89, $0A, $97, $60, $75;  277.182631135         C#\n        DEFB    $89, $12, $D5, $17, $1F;  293.664768100         D\n        DEFB    $89, $1B, $90, $41, $02;  311.126983881         D#\n        DEFB    $89, $24, $D0, $53, $CA;  329.627557039         E\n        DEFB    $89, $2E, $9D, $36, $B1;  349.228231549         F\n        DEFB    $89, $38, $FF, $49, $3E;  369.994422674         F#\n        DEFB    $89, $43, $FF, $6A, $73;  391.995436072         G\n        DEFB    $89, $4F, $A7, $00, $54;  415.304697513         G#\n        DEFB    $89, $5C, $00, $00, $00;  440.000000000         A\n        DEFB    $89, $69, $14, $F6, $24;  466.163761616         A#\n        DEFB    $89, $76, $F1, $10, $05;  493.883301378         B\n\n\n;   \"Music is the hidden mathematical endeavour of a soul unconscious it\n;    is calculating\" - Gottfried Wilhelm Liebnitz 1646 - 1716\n\n\n;****************************************\n;** Part 4. CASSETTE HANDLING ROUTINES **\n;****************************************\n\n;   These routines begin with the service routines followed by a single\n;   command entry point.\n;   The first of these service routines is a curiosity.\n\n; -----------------------\n; THE 'ZX81 NAME' ROUTINE\n; -----------------------\n;   This routine fetches a filename in ZX81 format and is not used by the\n;   cassette handling routines in this ROM.\n\n;; zx81-name\nL04AA:  CALL    L24FB           ; routine SCANNING to evaluate expression.\n        LD      A,($5C3B)       ; fetch system variable FLAGS.\n        ADD     A,A             ; test bit 7 - syntax, bit 6 - result type.\n        JP      M,L1C8A         ; to REPORT-C if not string result\n                                ; 'Nonsense in BASIC'.\n\n        POP     HL              ; drop return address.\n        RET     NC              ; return early if checking syntax.\n\n        PUSH    HL              ; re-save return address.\n        CALL    L2BF1           ; routine STK-FETCH fetches string parameters.\n        LD      H,D             ; transfer start of filename\n        LD      L,E             ; to the HL register.\n        DEC     C               ; adjust to point to last character and\n        RET     M               ; return if the null string.\n                                ; or multiple of 256!\n\n        ADD     HL,BC           ; find last character of the filename.\n                                ; and also clear carry.\n        SET     7,(HL)          ; invert it.\n        RET                     ; return.\n\n; =========================================\n;\n; PORT 254 ($FE)\n;\n;                      spk mic { border  }\n;          ___ ___ ___ ___ ___ ___ ___ ___\n; PORT    |   |   |   |   |   |   |   |   |\n; 254     |   |   |   |   |   |   |   |   |\n; $FE     |___|___|___|___|___|___|___|___|\n;           7   6   5   4   3   2   1   0\n;\n\n; ----------------------------------\n; Save header and program/data bytes\n; ----------------------------------\n;   This routine saves a section of data. It is called from SA-CTRL to save the\n;   seventeen bytes of header data. It is also the exit route from that routine\n;   when it is set up to save the actual data.\n;   On entry -\n;   HL points to start of data.\n;   IX points to descriptor.\n;   The accumulator is set to  $00 for a header, $FF for data.\n\n;; SA-BYTES\nL04C2:  LD      HL,L053F        ; address: SA/LD-RET\n        PUSH    HL              ; is pushed as common exit route.\n                                ; however there is only one non-terminal exit\n                                ; point.\n\n        LD      HL,$1F80        ; a timing constant H=$1F, L=$80\n                                ; inner and outer loop counters\n                                ; a five second lead-in is used for a header.\n\n        BIT     7,A             ; test one bit of accumulator.\n                                ; (AND A ?)\n        JR      Z,L04D0         ; skip to SA-FLAG if a header is being saved.\n\n;   else is data bytes and a shorter lead-in is used.\n\n        LD      HL,$0C98        ; another timing value H=$0C, L=$98.\n                                ; a two second lead-in is used for the data.\n\n\n;; SA-FLAG\nL04D0:  EX      AF,AF'          ; save flag\n        INC     DE              ; increase length by one.\n        DEC     IX              ; decrease start.\n\n        DI                      ; disable interrupts\n\n        LD      A,$02           ; select red for border, microphone bit on.\n        LD      B,A             ; also does as an initial slight counter value.\n\n;; SA-LEADER\nL04D8:  DJNZ    L04D8           ; self loop to SA-LEADER for delay.\n                                ; after initial loop, count is $A4 (or $A3)\n\n        OUT     ($FE),A         ; output byte $02/$0D to tape port.\n\n        XOR     $0F             ; switch from RED (mic on) to CYAN (mic off).\n\n        LD      B,$A4           ; hold count. also timed instruction.\n\n        DEC     L               ; originally $80 or $98.\n                                ; but subsequently cycles 256 times.\n        JR      NZ,L04D8        ; back to SA-LEADER until L is zero.\n\n;   the outer loop is counted by H\n\n        DEC     B               ; decrement count\n        DEC     H               ; originally  twelve or thirty-one.\n        JP      P,L04D8         ; back to SA-LEADER until H becomes $FF\n\n;   now send a sync pulse. At this stage mic is off and A holds value\n;   for mic on.\n;   A sync pulse is much shorter than the steady pulses of the lead-in.\n\n        LD      B,$2F           ; another short timed delay.\n\n;; SA-SYNC-1\nL04EA:  DJNZ    L04EA           ; self loop to SA-SYNC-1\n\n        OUT     ($FE),A         ; switch to mic on and red.\n        LD      A,$0D           ; prepare mic off - cyan\n        LD      B,$37           ; another short timed delay.\n\n;; SA-SYNC-2\nL04F2:  DJNZ    L04F2           ; self loop to SA-SYNC-2\n\n        OUT     ($FE),A         ; output mic off, cyan border.\n        LD      BC,$3B0E        ; B=$3B time(*), C=$0E, YELLOW, MIC OFF.\n\n;\n\n        EX      AF,AF'          ; restore saved flag\n                                ; which is 1st byte to be saved.\n\n        LD      L,A             ; and transfer to L.\n                                ; the initial parity is A, $FF or $00.\n        JP      L0507           ; JUMP forward to SA-START     ->\n                                ; the mid entry point of loop.\n\n; -------------------------\n;   During the save loop a parity byte is maintained in H.\n;   the save loop begins by testing if reduced length is zero and if so\n;   the final parity byte is saved reducing count to $FFFF.\n\n;; SA-LOOP\nL04FE:  LD      A,D             ; fetch high byte\n        OR      E               ; test against low byte.\n        JR      Z,L050E         ; forward to SA-PARITY if zero.\n\n        LD      L,(IX+$00)      ; load currently addressed byte to L.\n\n;; SA-LOOP-P\nL0505:  LD      A,H             ; fetch parity byte.\n        XOR     L               ; exclusive or with new byte.\n\n; -> the mid entry point of loop.\n\n;; SA-START\nL0507:  LD      H,A             ; put parity byte in H.\n        LD      A,$01           ; prepare blue, mic=on.\n        SCF                     ; set carry flag ready to rotate in.\n        JP      L0525           ; JUMP forward to SA-8-BITS            -8->\n\n; ---\n\n;; SA-PARITY\nL050E:  LD      L,H             ; transfer the running parity byte to L and\n        JR      L0505           ; back to SA-LOOP-P\n                                ; to output that byte before quitting normally.\n\n; ---\n\n;   The entry point to save yellow part of bit.\n;   A bit consists of a period with mic on and blue border followed by\n;   a period of mic off with yellow border.\n;   Note. since the DJNZ instruction does not affect flags, the zero flag is\n;   used to indicate which of the two passes is in effect and the carry\n;   maintains the state of the bit to be saved.\n\n;; SA-BIT-2\nL0511:  LD      A,C             ; fetch 'mic on and yellow' which is\n                                ; held permanently in C.\n        BIT     7,B             ; set the zero flag. B holds $3E.\n\n;   The entry point to save 1 entire bit. For first bit B holds $3B(*).\n;   Carry is set if saved bit is 1. zero is reset NZ on entry.\n\n;; SA-BIT-1\nL0514:  DJNZ    L0514           ; self loop for delay to SA-BIT-1\n\n        JR      NC,L051C        ; forward to SA-OUT if bit is 0.\n\n;   but if bit is 1 then the mic state is held for longer.\n\n        LD      B,$42           ; set timed delay. (66 decimal)\n\n;; SA-SET\nL051A:  DJNZ    L051A           ; self loop to SA-SET\n                                ; (roughly an extra 66*13 clock cycles)\n\n;; SA-OUT\nL051C:  OUT     ($FE),A         ; blue and mic on OR  yellow and mic off.\n\n        LD      B,$3E           ; set up delay\n        JR      NZ,L0511        ; back to SA-BIT-2 if zero reset NZ (first pass)\n\n;   proceed when the blue and yellow bands have been output.\n\n        DEC     B               ; change value $3E to $3D.\n        XOR     A               ; clear carry flag (ready to rotate in).\n        INC     A               ; reset zero flag i.e. NZ.\n\n; -8->\n\n;; SA-8-BITS\nL0525:  RL      L               ; rotate left through carry\n                                ; C<76543210<C\n        JP      NZ,L0514        ; JUMP back to SA-BIT-1\n                                ; until all 8 bits done.\n\n;   when the initial set carry is passed out again then a byte is complete.\n\n        DEC     DE              ; decrease length\n        INC     IX              ; increase byte pointer\n        LD      B,$31           ; set up timing.\n\n        LD      A,$7F           ; test the space key and\n        IN      A,($FE)         ; return to common exit (to restore border)\n        RRA                     ; if a space is pressed\n        RET     NC              ; return to SA/LD-RET.   - - >\n\n;   now test if byte counter has reached $FFFF.\n\n        LD      A,D             ; fetch high byte\n        INC     A               ; increment.\n        JP      NZ,L04FE        ; JUMP to SA-LOOP if more bytes.\n\n        LD      B,$3B           ; a final delay.\n\n;; SA-DELAY\nL053C:  DJNZ    L053C           ; self loop to SA-DELAY\n\n        RET                     ; return - - >\n\n; ------------------------------\n; THE 'SAVE/LOAD RETURN' ROUTINE\n; ------------------------------\n;   The address of this routine is pushed on the stack prior to any load/save\n;   operation and it handles normal completion with the restoration of the\n;   border and also abnormal termination when the break key, or to be more\n;   precise the space key is pressed during a tape operation.\n;\n; - - >\n\n;; SA/LD-RET\nL053F:  PUSH    AF              ; preserve accumulator throughout.\n        LD      A,($5C48)       ; fetch border colour from BORDCR.\n        AND     $38             ; mask off paper bits.\n        RRCA                    ; rotate\n        RRCA                    ; to the\n        RRCA                    ; range 0-7.\n\n        OUT     ($FE),A         ; change the border colour.\n\n        LD      A,$7F           ; read from port address $7FFE the\n        IN      A,($FE)         ; row with the space key at outside.\n\n        RRA                     ; test for space key pressed.\n        EI                      ; enable interrupts\n        JR      C,L0554         ; forward to SA/LD-END if not\n\n\n;; REPORT-Da\nL0552:  RST     08H             ; ERROR-1\n        DEFB    $0C             ; Error Report: BREAK - CONT repeats\n\n; ---\n\n;; SA/LD-END\nL0554:  POP     AF              ; restore the accumulator.\n        RET                     ; return.\n\n; ------------------------------------\n; Load header or block of information\n; ------------------------------------\n;   This routine is used to load bytes and on entry A is set to $00 for a\n;   header or to $FF for data.  IX points to the start of receiving location\n;   and DE holds the length of bytes to be loaded. If, on entry the carry flag\n;   is set then data is loaded, if reset then it is verified.\n\n;; LD-BYTES\nL0556:  INC     D               ; reset the zero flag without disturbing carry.\n        EX      AF,AF'          ; preserve entry flags.\n        DEC     D               ; restore high byte of length.\n\n        DI                      ; disable interrupts\n\n        LD      A,$0F           ; make the border white and mic off.\n        OUT     ($FE),A         ; output to port.\n\n        LD      HL,L053F        ; Address: SA/LD-RET\n        PUSH    HL              ; is saved on stack as terminating routine.\n\n;   the reading of the EAR bit (D6) will always be preceded by a test of the\n;   space key (D0), so store the initial post-test state.\n\n        IN      A,($FE)         ; read the ear state - bit 6.\n        RRA                     ; rotate to bit 5.\n        AND     $20             ; isolate this bit.\n        OR      $02             ; combine with red border colour.\n        LD      C,A             ; and store initial state long-term in C.\n        CP      A               ; set the zero flag.\n\n;\n\n;; LD-BREAK\nL056B:  RET     NZ              ; return if at any time space is pressed.\n\n;; LD-START\nL056C:  CALL    L05E7           ; routine LD-EDGE-1\n        JR      NC,L056B        ; back to LD-BREAK with time out and no\n                                ; edge present on tape.\n\n;   but continue when a transition is found on tape.\n\n        LD      HL,$0415        ; set up 16-bit outer loop counter for\n                                ; approx 1 second delay.\n\n;; LD-WAIT\nL0574:  DJNZ    L0574           ; self loop to LD-WAIT (for 256 times)\n\n        DEC     HL              ; decrease outer loop counter.\n        LD      A,H             ; test for\n        OR      L               ; zero.\n        JR      NZ,L0574        ; back to LD-WAIT, if not zero, with zero in B.\n\n;   continue after delay with H holding zero and B also.\n;   sample 256 edges to check that we are in the middle of a lead-in section.\n\n        CALL    L05E3           ; routine LD-EDGE-2\n        JR      NC,L056B        ; back to LD-BREAK\n                                ; if no edges at all.\n\n;; LD-LEADER\nL0580:  LD      B,$9C           ; set timing value.\n        CALL    L05E3           ; routine LD-EDGE-2\n        JR      NC,L056B        ; back to LD-BREAK if time-out\n\n        LD      A,$C6           ; two edges must be spaced apart.\n        CP      B               ; compare\n        JR      NC,L056C        ; back to LD-START if too close together for a\n                                ; lead-in.\n\n        INC     H               ; proceed to test 256 edged sample.\n        JR      NZ,L0580        ; back to LD-LEADER while more to do.\n\n;   sample indicates we are in the middle of a two or five second lead-in.\n;   Now test every edge looking for the terminal sync signal.\n\n;; LD-SYNC\nL058F:  LD      B,$C9           ; initial timing value in B.\n        CALL    L05E7           ; routine LD-EDGE-1\n        JR      NC,L056B        ; back to LD-BREAK with time-out.\n\n        LD      A,B             ; fetch augmented timing value from B.\n        CP      $D4             ; compare\n        JR      NC,L058F        ; back to LD-SYNC if gap too big, that is,\n                                ; a normal lead-in edge gap.\n\n;   but a short gap will be the sync pulse.\n;   in which case another edge should appear before B rises to $FF\n\n        CALL    L05E7           ; routine LD-EDGE-1\n        RET     NC              ; return with time-out.\n\n; proceed when the sync at the end of the lead-in is found.\n; We are about to load data so change the border colours.\n\n        LD      A,C             ; fetch long-term mask from C\n        XOR     $03             ; and make blue/yellow.\n\n        LD      C,A             ; store the new long-term byte.\n\n        LD      H,$00           ; set up parity byte as zero.\n        LD      B,$B0           ; timing.\n        JR      L05C8           ; forward to LD-MARKER\n                                ; the loop mid entry point with the alternate\n                                ; zero flag reset to indicate first byte\n                                ; is discarded.\n\n; --------------\n;   the loading loop loads each byte and is entered at the mid point.\n\n;; LD-LOOP\nL05A9:  EX      AF,AF'          ; restore entry flags and type in A.\n        JR      NZ,L05B3        ; forward to LD-FLAG if awaiting initial flag\n                                ; which is to be discarded.\n\n        JR      NC,L05BD        ; forward to LD-VERIFY if not to be loaded.\n\n        LD      (IX+$00),L      ; place loaded byte at memory location.\n        JR      L05C2           ; forward to LD-NEXT\n\n; ---\n\n;; LD-FLAG\nL05B3:  RL      C               ; preserve carry (verify) flag in long-term\n                                ; state byte. Bit 7 can be lost.\n\n        XOR     L               ; compare type in A with first byte in L.\n        RET     NZ              ; return if no match e.g. CODE vs. DATA.\n\n;   continue when data type matches.\n\n        LD      A,C             ; fetch byte with stored carry\n        RRA                     ; rotate it to carry flag again\n        LD      C,A             ; restore long-term port state.\n\n        INC     DE              ; increment length ??\n        JR      L05C4           ; forward to LD-DEC.\n                                ; but why not to location after ?\n\n; ---\n;   for verification the byte read from tape is compared with that in memory.\n\n;; LD-VERIFY\nL05BD:  LD      A,(IX+$00)      ; fetch byte from memory.\n        XOR     L               ; compare with that on tape\n        RET     NZ              ; return if not zero.\n\n;; LD-NEXT\nL05C2:  INC     IX              ; increment byte pointer.\n\n;; LD-DEC\nL05C4:  DEC     DE              ; decrement length.\n        EX      AF,AF'          ; store the flags.\n        LD      B,$B2           ; timing.\n\n;   when starting to read 8 bits the receiving byte is marked with bit at right.\n;   when this is rotated out again then 8 bits have been read.\n\n;; LD-MARKER\nL05C8:  LD      L,$01           ; initialize as %00000001\n\n;; LD-8-BITS\nL05CA:  CALL    L05E3           ; routine LD-EDGE-2 increments B relative to\n                                ; gap between 2 edges.\n        RET     NC              ; return with time-out.\n\n        LD      A,$CB           ; the comparison byte.\n        CP      B               ; compare to incremented value of B.\n                                ; if B is higher then bit on tape was set.\n                                ; if <= then bit on tape is reset.\n\n        RL      L               ; rotate the carry bit into L.\n\n        LD      B,$B0           ; reset the B timer byte.\n        JP      NC,L05CA        ; JUMP back to LD-8-BITS\n\n;   when carry set then marker bit has been passed out and byte is complete.\n\n        LD      A,H             ; fetch the running parity byte.\n        XOR     L               ; include the new byte.\n        LD      H,A             ; and store back in parity register.\n\n        LD      A,D             ; check length of\n        OR      E               ; expected bytes.\n        JR      NZ,L05A9        ; back to LD-LOOP\n                                ; while there are more.\n\n;   when all bytes loaded then parity byte should be zero.\n\n        LD      A,H             ; fetch parity byte.\n        CP      $01             ; set carry if zero.\n        RET                     ; return\n                                ; in no carry then error as checksum disagrees.\n\n; -------------------------\n; Check signal being loaded\n; -------------------------\n;   An edge is a transition from one mic state to another.\n;   More specifically a change in bit 6 of value input from port $FE.\n;   Graphically it is a change of border colour, say, blue to yellow.\n;   The first entry point looks for two adjacent edges. The second entry point\n;   is used to find a single edge.\n;   The B register holds a count, up to 256, within which the edge (or edges)\n;   must be found. The gap between two edges will be more for a '1' than a '0'\n;   so the value of B denotes the state of the bit (two edges) read from tape.\n\n; ->\n\n;; LD-EDGE-2\nL05E3:  CALL    L05E7           ; call routine LD-EDGE-1 below.\n        RET     NC              ; return if space pressed or time-out.\n                                ; else continue and look for another adjacent\n                                ; edge which together represent a bit on the\n                                ; tape.\n\n; ->\n;   this entry point is used to find a single edge from above but also\n;   when detecting a read-in signal on the tape.\n\n;; LD-EDGE-1\nL05E7:  LD      A,$16           ; a delay value of twenty two.\n\n;; LD-DELAY\nL05E9:  DEC     A               ; decrement counter\n        JR      NZ,L05E9        ; loop back to LD-DELAY 22 times.\n\n        AND      A              ; clear carry.\n\n;; LD-SAMPLE\nL05ED:  INC     B               ; increment the time-out counter.\n        RET     Z               ; return with failure when $FF passed.\n\n        LD      A,$7F           ; prepare to read keyboard and EAR port\n        IN      A,($FE)         ; row $7FFE. bit 6 is EAR, bit 0 is SPACE key.\n        RRA                     ; test outer key the space. (bit 6 moves to 5)\n        RET     NC              ; return if space pressed.  >>>\n\n        XOR     C               ; compare with initial long-term state.\n        AND     $20             ; isolate bit 5\n        JR      Z,L05ED         ; back to LD-SAMPLE if no edge.\n\n;   but an edge, a transition of the EAR bit, has been found so switch the\n;   long-term comparison byte containing both border colour and EAR bit.\n\n        LD      A,C             ; fetch comparison value.\n        CPL                     ; switch the bits\n        LD      C,A             ; and put back in C for long-term.\n\n        AND     $07             ; isolate new colour bits.\n        OR      $08             ; set bit 3 - MIC off.\n        OUT     ($FE),A         ; send to port to effect the change of colour.\n\n        SCF                     ; set carry flag signaling edge found within\n                                ; time allowed.\n        RET                     ; return.\n\n; ---------------------------------\n; Entry point for all tape commands\n; ---------------------------------\n;   This is the single entry point for the four tape commands.\n;   The routine first determines in what context it has been called by examining\n;   the low byte of the Syntax table entry which was stored in T_ADDR.\n;   Subtracting $EO (the present arrangement) gives a value of\n;   $00 - SAVE\n;   $01 - LOAD\n;   $02 - VERIFY\n;   $03 - MERGE\n;   As with all commands the address STMT-RET is on the stack.\n\n;; SAVE-ETC\nL0605:  POP     AF              ; discard address STMT-RET.\n        LD      A,($5C74)       ; fetch T_ADDR\n\n;   Now reduce the low byte of the Syntax table entry to give command.\n;   Note. For ZASM use SUB $E0 as next instruction.\n\nL0609:  SUB     L1ADF + 1 % 256 ; subtract the known offset.\n                                ; ( is SUB $E0 in standard ROM )\n\n        LD      ($5C74),A       ; and put back in T_ADDR as 0,1,2, or 3\n                                ; for future reference.\n\n        CALL    L1C8C           ; routine EXPT-EXP checks that a string\n                                ; expression follows and stacks the\n                                ; parameters in run-time.\n\n        CALL    L2530           ; routine SYNTAX-Z\n        JR      Z,L0652         ; forward to SA-DATA if checking syntax.\n\n        LD      BC,$0011        ; presume seventeen bytes for a header.\n        LD      A,($5C74)       ; fetch command from T_ADDR.\n        AND     A               ; test for zero - SAVE.\n        JR      Z,L0621         ; forward to SA-SPACE if so.\n\n        LD      C,$22           ; else double length to thirty four.\n\n;; SA-SPACE\nL0621:  RST     30H             ; BC-SPACES creates 17/34 bytes in workspace.\n\n        PUSH    DE              ; transfer the start of new space to\n        POP     IX              ; the available index register.\n\n;   ten spaces are required for the default filename but it is simpler to\n;   overwrite the first file-type indicator byte as well.\n\n        LD      B,$0B           ; set counter to eleven.\n        LD      A,$20           ; prepare a space.\n\n;; SA-BLANK\nL0629:  LD      (DE),A          ; set workspace location to space.\n        INC     DE              ; next location.\n        DJNZ    L0629           ; loop back to SA-BLANK till all eleven done.\n\n        LD      (IX+$01),$FF    ; set first byte of ten character filename\n                                ; to $FF as a default to signal null string.\n\n        CALL    L2BF1           ; routine STK-FETCH fetches the filename\n                                ; parameters from the calculator stack.\n                                ; length of string in BC.\n                                ; start of string in DE.\n\n        LD      HL,$FFF6        ; prepare the value minus ten.\n        DEC     BC              ; decrement length.\n                                ; ten becomes nine, zero becomes $FFFF.\n        ADD     HL,BC           ; trial addition.\n        INC     BC              ; restore true length.\n        JR      NC,L064B        ; forward to SA-NAME if length is one to ten.\n\n;   the filename is more than ten characters in length or the null string.\n\n        LD      A,($5C74)       ; fetch command from T_ADDR.\n        AND     A               ; test for zero - SAVE.\n        JR      NZ,L0644        ; forward to SA-NULL if not the SAVE command.\n\n;   but no more than ten characters are allowed for SAVE.\n;   The first ten characters of any other command parameter are acceptable.\n;   Weird, but necessary, if saving to sectors.\n;   Note. the golden rule that there are no restriction on anything is broken.\n\n;; REPORT-Fa\nL0642:  RST     08H             ; ERROR-1\n        DEFB    $0E             ; Error Report: Invalid file name\n\n;   continue with LOAD, MERGE, VERIFY and also SAVE within ten character limit.\n\n;; SA-NULL\nL0644:  LD      A,B             ; test length of filename\n        OR      C               ; for zero.\n        JR      Z,L0652         ; forward to SA-DATA if so using the 255\n                                ; indicator followed by spaces.\n\n        LD      BC,$000A        ; else trim length to ten.\n\n;   other paths rejoin here with BC holding length in range 1 - 10.\n\n;; SA-NAME\nL064B:  PUSH    IX              ; push start of file descriptor.\n        POP     HL              ; and pop into HL.\n\n        INC     HL              ; HL now addresses first byte of filename.\n        EX      DE,HL           ; transfer destination address to DE, start\n                                ; of string in command to HL.\n        LDIR                    ; copy up to ten bytes\n                                ; if less than ten then trailing spaces follow.\n\n;   the case for the null string rejoins here.\n\n;; SA-DATA\nL0652:  RST     18H             ; GET-CHAR\n        CP      $E4             ; is character after filename the token 'DATA' ?\n        JR      NZ,L06A0        ; forward to SA-SCR$ to consider SCREEN$ if\n                                ; not.\n\n;   continue to consider DATA.\n\n        LD      A,($5C74)       ; fetch command from T_ADDR\n        CP      $03             ; is it 'VERIFY' ?\n        JP      Z,L1C8A         ; jump forward to REPORT-C if so.\n                                ; 'Nonsense in BASIC'\n                                ; VERIFY \"d\" DATA is not allowed.\n\n;   continue with SAVE, LOAD, MERGE of DATA.\n\n        RST     20H             ; NEXT-CHAR\n        CALL    L28B2           ; routine LOOK-VARS searches variables area\n                                ; returning with carry reset if found or\n                                ; checking syntax.\n        SET     7,C             ; this converts a simple string to a\n                                ; string array. The test for an array or string\n                                ; comes later.\n        JR      NC,L0672        ; forward to SA-V-OLD if variable found.\n\n        LD      HL,$0000        ; set destination to zero as not fixed.\n        LD      A,($5C74)       ; fetch command from T_ADDR\n        DEC     A               ; test for 1 - LOAD\n        JR      Z,L0685         ; forward to SA-V-NEW with LOAD DATA.\n                                ; to load a new array.\n\n;   otherwise the variable was not found in run-time with SAVE/MERGE.\n\n;; REPORT-2a\nL0670:  RST     08H             ; ERROR-1\n        DEFB    $01             ; Error Report: Variable not found\n\n;   continue with SAVE/LOAD  DATA\n\n;; SA-V-OLD\nL0672:  JP      NZ,L1C8A        ; to REPORT-C if not an array variable.\n                                ; or erroneously a simple string.\n                                ; 'Nonsense in BASIC'\n\n\n        CALL    L2530           ; routine SYNTAX-Z\n        JR      Z,L0692         ; forward to SA-DATA-1 if checking syntax.\n\n        INC     HL              ; step past single character variable name.\n        LD      A,(HL)          ; fetch low byte of length.\n        LD      (IX+$0B),A      ; place in descriptor.\n        INC     HL              ; point to high byte.\n        LD      A,(HL)          ; and transfer that\n        LD      (IX+$0C),A      ; to descriptor.\n        INC     HL              ; increase pointer within variable.\n\n;; SA-V-NEW\nL0685:  LD      (IX+$0E),C      ; place character array name in  header.\n        LD      A,$01           ; default to type numeric.\n        BIT     6,C             ; test result from look-vars.\n        JR      Z,L068F         ; forward to SA-V-TYPE if numeric.\n\n        INC     A               ; set type to 2 - string array.\n\n;; SA-V-TYPE\nL068F:  LD      (IX+$00),A      ; place type 0, 1 or 2 in descriptor.\n\n;; SA-DATA-1\nL0692:  EX      DE,HL           ; save var pointer in DE\n\n        RST     20H             ; NEXT-CHAR\n        CP      $29             ; is character ')' ?\n        JR      NZ,L0672        ; back if not to SA-V-OLD to report\n                                ; 'Nonsense in BASIC'\n\n        RST     20H             ; NEXT-CHAR advances character address.\n        CALL    L1BEE           ; routine CHECK-END errors if not end of\n                                ; the statement.\n\n        EX      DE,HL           ; bring back variables data pointer.\n        JP      L075A           ; jump forward to SA-ALL\n\n; ---\n;   the branch was here to consider a 'SCREEN$', the display file.\n\n;; SA-SCR$\nL06A0:  CP      $AA             ; is character the token 'SCREEN$' ?\n        JR      NZ,L06C3        ; forward to SA-CODE if not.\n\n        LD      A,($5C74)       ; fetch command from T_ADDR\n        CP      $03             ; is it MERGE ?\n        JP       Z,L1C8A        ; jump to REPORT-C if so.\n                                ; 'Nonsense in BASIC'\n\n;   continue with SAVE/LOAD/VERIFY SCREEN$.\n\n        RST     20H             ; NEXT-CHAR\n        CALL    L1BEE           ; routine CHECK-END errors if not at end of\n                                ; statement.\n\n;   continue in runtime.\n\n        LD      (IX+$0B),$00    ; set descriptor length\n        LD      (IX+$0C),$1B    ; to $1b00 to include bitmaps and attributes.\n\n        LD      HL,$4000        ; set start to display file start.\n        LD      (IX+$0D),L      ; place start in\n        LD      (IX+$0E),H      ; the descriptor.\n        JR      L0710           ; forward to SA-TYPE-3\n\n; ---\n;   the branch was here to consider CODE.\n\n;; SA-CODE\nL06C3:  CP      $AF             ; is character the token 'CODE' ?\n        JR      NZ,L0716        ; forward if not to SA-LINE to consider an\n                                ; auto-started BASIC program.\n\n        LD      A,($5C74)       ; fetch command from T_ADDR\n        CP      $03             ; is it MERGE ?\n        JP      Z,L1C8A         ; jump forward to REPORT-C if so.\n                                ; 'Nonsense in BASIC'\n\n\n        RST     20H             ; NEXT-CHAR advances character address.\n        CALL    L2048           ; routine PR-ST-END checks if a carriage\n                                ; return or ':' follows.\n        JR      NZ,L06E1        ; forward to SA-CODE-1 if there are parameters.\n\n        LD      A,($5C74)       ; else fetch the command from T_ADDR.\n        AND     A               ; test for zero - SAVE without a specification.\n        JP      Z,L1C8A         ; jump to REPORT-C if so.\n                                ; 'Nonsense in BASIC'\n\n;   for LOAD/VERIFY put zero on stack to signify handle at location saved from.\n\n        CALL    L1CE6           ; routine USE-ZERO\n        JR      L06F0           ; forward to SA-CODE-2\n\n; ---\n\n;   if there are more characters after CODE expect start and possibly length.\n\n;; SA-CODE-1\nL06E1:  CALL    L1C82           ; routine EXPT-1NUM checks for numeric\n                                ; expression and stacks it in run-time.\n\n        RST     18H             ; GET-CHAR\n        CP      $2C             ; does a comma follow ?\n        JR      Z,L06F5         ; forward if so to SA-CODE-3\n\n;   else allow saved code to be loaded to a specified address.\n\n        LD      A,($5C74)       ; fetch command from T_ADDR.\n        AND     A               ; is the command SAVE which requires length ?\n        JP      Z,L1C8A         ; jump to REPORT-C if so.\n                                ; 'Nonsense in BASIC'\n\n;   the command LOAD code may rejoin here with zero stacked as start.\n\n;; SA-CODE-2\nL06F0:  CALL    L1CE6           ; routine USE-ZERO stacks zero for length.\n        JR      L06F9           ; forward to SA-CODE-4\n\n; ---\n;   the branch was here with SAVE CODE start,\n\n;; SA-CODE-3\nL06F5:  RST     20H             ; NEXT-CHAR advances character address.\n        CALL    L1C82           ; routine EXPT-1NUM checks for expression\n                                ; and stacks in run-time.\n\n;   paths converge here and nothing must follow.\n\n;; SA-CODE-4\nL06F9:  CALL    L1BEE           ; routine CHECK-END errors with extraneous\n                                ; characters and quits if checking syntax.\n\n;   in run-time there are two 16-bit parameters on the calculator stack.\n\n        CALL    L1E99           ; routine FIND-INT2 gets length.\n        LD      (IX+$0B),C      ; place length\n        LD      (IX+$0C),B      ; in descriptor.\n        CALL    L1E99           ; routine FIND-INT2 gets start.\n        LD      (IX+$0D),C      ; place start\n        LD      (IX+$0E),B      ; in descriptor.\n        LD      H,B             ; transfer the\n        LD      L,C             ; start to HL also.\n\n;; SA-TYPE-3\nL0710:  LD      (IX+$00),$03    ; place type 3 - code in descriptor.\n        JR      L075A           ; forward to SA-ALL.\n\n; ---\n;   the branch was here with BASIC to consider an optional auto-start line\n;   number.\n\n;; SA-LINE\nL0716:  CP      $CA             ; is character the token 'LINE' ?\n        JR      Z,L0723         ; forward to SA-LINE-1 if so.\n\n;   else all possibilities have been considered and nothing must follow.\n\n        CALL    L1BEE           ; routine CHECK-END\n\n;   continue in run-time to save BASIC without auto-start.\n\n        LD      (IX+$0E),$80    ; place high line number in descriptor to\n                                ; disable auto-start.\n        JR      L073A           ; forward to SA-TYPE-0 to save program.\n\n; ---\n;   the branch was here to consider auto-start.\n\n;; SA-LINE-1\nL0723:  LD      A,($5C74)       ; fetch command from T_ADDR\n        AND     A               ; test for SAVE.\n        JP      NZ,L1C8A        ; jump forward to REPORT-C with anything else.\n                                ; 'Nonsense in BASIC'\n\n;\n\n        RST     20H             ; NEXT-CHAR\n        CALL    L1C82           ; routine EXPT-1NUM checks for numeric\n                                ; expression and stacks in run-time.\n        CALL    L1BEE           ; routine CHECK-END quits if syntax path.\n        CALL    L1E99           ; routine FIND-INT2 fetches the numeric\n                                ; expression.\n        LD      (IX+$0D),C      ; place the auto-start\n        LD      (IX+$0E),B      ; line number in the descriptor.\n\n;   Note. this isn't checked, but is subsequently handled by the system.\n;   If the user typed 40000 instead of 4000 then it won't auto-start\n;   at line 4000, or indeed, at all.\n\n;   continue to save program and any variables.\n\n;; SA-TYPE-0\nL073A:  LD      (IX+$00),$00    ; place type zero - program in descriptor.\n        LD      HL,($5C59)      ; fetch E_LINE to HL.\n        LD      DE,($5C53)      ; fetch PROG to DE.\n        SCF                     ; set carry flag to calculate from end of\n                                ; variables E_LINE -1.\n        SBC     HL,DE           ; subtract to give total length.\n\n        LD      (IX+$0B),L      ; place total length\n        LD      (IX+$0C),H      ; in descriptor.\n        LD      HL,($5C4B)      ; load HL from system variable VARS\n        SBC     HL,DE           ; subtract to give program length.\n        LD      (IX+$0F),L      ; place length of program\n        LD      (IX+$10),H      ; in the descriptor.\n        EX      DE,HL           ; start to HL, length to DE.\n\n;; SA-ALL\nL075A:  LD      A,($5C74)       ; fetch command from T_ADDR\n        AND     A               ; test for zero - SAVE.\n        JP      Z,L0970         ; jump forward to SA-CONTRL with SAVE  ->\n\n; ---\n;   continue with LOAD, MERGE and VERIFY.\n\n        PUSH    HL              ; save start.\n        LD      BC,$0011        ; prepare to add seventeen\n        ADD     IX,BC           ; to point IX at second descriptor.\n\n;; LD-LOOK-H\nL0767:  PUSH    IX              ; save IX\n        LD      DE,$0011        ; seventeen bytes\n        XOR     A               ; reset zero flag\n        SCF                     ; set carry flag\n        CALL    L0556           ; routine LD-BYTES loads a header from tape\n                                ; to second descriptor.\n        POP     IX              ; restore IX.\n        JR      NC,L0767        ; loop back to LD-LOOK-H until header found.\n\n        LD      A,$FE           ; select system channel 'S'\n        CALL    L1601           ; routine CHAN-OPEN opens it.\n\n        LD      (IY+$52),$03    ; set SCR_CT to 3 lines.\n\n        LD      C,$80           ; C has bit 7 set to indicate type mismatch as\n                                ; a default startpoint.\n\n        LD      A,(IX+$00)      ; fetch loaded header type to A\n        CP      (IX-$11)        ; compare with expected type.\n        JR      NZ,L078A        ; forward to LD-TYPE with mis-match.\n\n        LD      C,$F6           ; set C to minus ten - will count characters\n                                ; up to zero.\n\n;; LD-TYPE\nL078A:  CP      $04             ; check if type in acceptable range 0 - 3.\n        JR      NC,L0767        ; back to LD-LOOK-H with 4 and over.\n\n;   else A indicates type 0-3.\n\n        LD      DE,L09C0        ; address base of last 4 tape messages\n        PUSH    BC              ; save BC\n        CALL    L0C0A           ; routine PO-MSG outputs relevant message.\n                                ; Note. all messages have a leading newline.\n        POP     BC              ; restore BC\n\n        PUSH    IX              ; transfer IX,\n        POP     DE              ; the 2nd descriptor, to DE.\n        LD      HL,$FFF0        ; prepare minus seventeen.\n        ADD     HL,DE           ; add to point HL to 1st descriptor.\n        LD      B,$0A           ; the count will be ten characters for the\n                                ; filename.\n\n        LD      A,(HL)          ; fetch first character and test for\n        INC     A               ; value 255.\n        JR      NZ,L07A6        ; forward to LD-NAME if not the wildcard.\n\n;   but if it is the wildcard, then add ten to C which is minus ten for a type\n;   match or -128 for a type mismatch. Although characters have to be counted\n;   bit 7 of C will not alter from state set here.\n\n        LD      A,C             ; transfer $F6 or $80 to A\n        ADD     A,B             ; add $0A\n        LD      C,A             ; place result, zero or -118, in C.\n\n;   At this point we have either a type mismatch, a wildcard match or ten\n;   characters to be counted. The characters must be shown on the screen.\n\n;; LD-NAME\nL07A6:  INC     DE              ; address next input character\n        LD      A,(DE)          ; fetch character\n        CP      (HL)            ; compare to expected\n        INC     HL              ; address next expected character\n        JR      NZ,L07AD        ; forward to LD-CH-PR with mismatch\n\n        INC     C               ; increment matched character count\n\n;; LD-CH-PR\nL07AD:  RST     10H             ; PRINT-A prints character\n        DJNZ    L07A6           ; loop back to LD-NAME for ten characters.\n\n;   if ten characters matched and the types previously matched then C will\n;   now hold zero.\n\n        BIT     7,C             ; test if all matched\n        JR      NZ,L0767        ; back to LD-LOOK-H if not\n\n;   else print a terminal carriage return.\n\n        LD      A,$0D           ; prepare carriage return.\n        RST     10H             ; PRINT-A outputs it.\n\n;   The various control routines for LOAD, VERIFY and MERGE are executed\n;   during the one-second gap following the header on tape.\n\n        POP     HL              ; restore xx\n        LD      A,(IX+$00)      ; fetch incoming type\n        CP      $03             ; compare with CODE\n        JR      Z,L07CB         ; forward to VR-CONTRL if it is CODE.\n\n;  type is a program or an array.\n\n        LD      A,($5C74)       ; fetch command from T_ADDR\n        DEC     A               ; was it LOAD ?\n        JP      Z,L0808         ; JUMP forward to LD-CONTRL if so to\n                                ; load BASIC or variables.\n\n        CP      $02             ; was command MERGE ?\n        JP      Z,L08B6         ; jump forward to ME-CONTRL if so.\n\n;   else continue into VERIFY control routine to verify.\n\n; ----------------------------\n; THE 'VERIFY CONTROL' ROUTINE\n; ----------------------------\n;   There are two branches to this routine.\n;   1) From above to verify a program or array\n;   2) from earlier with no carry to load or verify code.\n\n;; VR-CONTRL\nL07CB:  PUSH    HL              ; save pointer to data.\n        LD      L,(IX-$06)      ; fetch length of old data\n        LD      H,(IX-$05)      ; to HL.\n        LD      E,(IX+$0B)      ; fetch length of new data\n        LD      D,(IX+$0C)      ; to DE.\n        LD      A,H             ; check length of old\n        OR      L               ; for zero.\n        JR      Z,L07E9         ; forward to VR-CONT-1 if length unspecified\n                                ; e.g. LOAD \"x\" CODE\n\n;   as opposed to, say, LOAD 'x' CODE 32768,300.\n\n        SBC     HL,DE           ; subtract the two lengths.\n        JR      C,L0806         ; forward to REPORT-R if the length on tape is\n                                ; larger than that specified in command.\n                                ; 'Tape loading error'\n\n        JR      Z,L07E9         ; forward to VR-CONT-1 if lengths match.\n\n;   a length on tape shorter than expected is not allowed for CODE\n\n        LD      A,(IX+$00)      ; else fetch type from tape.\n        CP      $03             ; is it CODE ?\n        JR      NZ,L0806        ; forward to REPORT-R if so\n                                ; 'Tape loading error'\n\n;; VR-CONT-1\nL07E9:  POP     HL              ; pop pointer to data\n        LD      A,H             ; test for zero\n        OR      L               ; e.g. LOAD 'x' CODE\n        JR      NZ,L07F4        ; forward to VR-CONT-2 if destination specified.\n\n        LD      L,(IX+$0D)      ; else use the destination in the header\n        LD      H,(IX+$0E)      ; and load code at address saved from.\n\n;; VR-CONT-2\nL07F4:  PUSH    HL              ; push pointer to start of data block.\n        POP     IX              ; transfer to IX.\n        LD      A,($5C74)       ; fetch reduced command from T_ADDR\n        CP      $02             ; is it VERIFY ?\n        SCF                     ; prepare a set carry flag\n        JR      NZ,L0800        ; skip to VR-CONT-3 if not\n\n        AND     A               ; clear carry flag for VERIFY so that\n                                ; data is not loaded.\n\n;; VR-CONT-3\nL0800:  LD      A,$FF           ; signal data block to be loaded\n\n; -----------------\n; Load a data block\n; -----------------\n;   This routine is called from 3 places other than above to load a data block.\n;   In all cases the accumulator is first set to $FF so the routine could be\n;   called at the previous instruction.\n\n;; LD-BLOCK\nL0802:  CALL    L0556           ; routine LD-BYTES\n        RET     C               ; return if successful.\n\n\n;; REPORT-R\nL0806:  RST     08H             ; ERROR-1\n        DEFB    $1A             ; Error Report: Tape loading error\n\n; --------------------------\n; THE 'LOAD CONTROL' ROUTINE\n; --------------------------\n;   This branch is taken when the command is LOAD with type 0, 1 or 2.\n\n;; LD-CONTRL\nL0808:  LD      E,(IX+$0B)      ; fetch length of found data block\n        LD      D,(IX+$0C)      ; from 2nd descriptor.\n        PUSH    HL              ; save destination\n        LD      A,H             ; test for zero\n        OR      L               ;\n        JR      NZ,L0819        ; forward if not to LD-CONT-1\n\n        INC     DE              ; increase length\n        INC     DE              ; for letter name\n        INC     DE              ; and 16-bit length\n        EX      DE,HL           ; length to HL,\n        JR      L0825           ; forward to LD-CONT-2\n\n; ---\n\n;; LD-CONT-1\nL0819:  LD      L,(IX-$06)      ; fetch length from\n        LD      H,(IX-$05)      ; the first header.\n        EX      DE,HL           ;\n        SCF                     ; set carry flag\n        SBC     HL,DE           ;\n        JR      C,L082E         ; to LD-DATA\n\n;; LD-CONT-2\nL0825:  LD      DE,$0005        ; allow overhead of five bytes.\n        ADD     HL,DE           ; add in the difference in data lengths.\n        LD      B,H             ; transfer to\n        LD      C,L             ; the BC register pair\n        CALL    L1F05           ; routine TEST-ROOM fails if not enough room.\n\n;; LD-DATA\nL082E:  POP     HL              ; pop destination\n        LD      A,(IX+$00)      ; fetch type 0, 1 or 2.\n        AND     A               ; test for program and variables.\n        JR      Z,L0873         ; forward if so to LD-PROG\n\n;   the type is a numeric or string array.\n\n        LD      A,H             ; test the destination for zero\n        OR      L               ; indicating variable does not already exist.\n        JR      Z,L084C         ; forward if so to LD-DATA-1\n\n;   else the destination is the first dimension within the array structure\n\n        DEC     HL              ; address high byte of total length\n        LD      B,(HL)          ; transfer to B.\n        DEC     HL              ; address low byte of total length.\n        LD      C,(HL)          ; transfer to C.\n        DEC     HL              ; point to letter of variable.\n        INC     BC              ; adjust length to\n        INC     BC              ; include these\n        INC     BC              ; three bytes also.\n        LD      ($5C5F),IX      ; save header pointer in X_PTR.\n        CALL    L19E8           ; routine RECLAIM-2 reclaims the old variable\n                                ; sliding workspace including the two headers\n                                ; downwards.\n        LD      IX,($5C5F)      ; reload IX from X_PTR which will have been\n                                ; adjusted down by POINTERS routine.\n\n;; LD-DATA-1\nL084C:  LD      HL,($5C59)      ; address E_LINE\n        DEC     HL              ; now point to the $80 variables end-marker.\n        LD      C,(IX+$0B)      ; fetch new data length\n        LD      B,(IX+$0C)      ; from 2nd header.\n        PUSH    BC              ; * save it.\n        INC     BC              ; adjust the\n        INC     BC              ; length to include\n        INC     BC              ; letter name and total length.\n        LD      A,(IX-$03)      ; fetch letter name from old header.\n        PUSH    AF              ; preserve accumulator though not corrupted.\n\n        CALL    L1655           ; routine MAKE-ROOM creates space for variable\n                                ; sliding workspace up. IX no longer addresses\n                                ; anywhere meaningful.\n        INC     HL              ; point to first new location.\n\n        POP     AF              ; fetch back the letter name.\n        LD      (HL),A          ; place in first new location.\n        POP     DE              ; * pop the data length.\n        INC     HL              ; address 2nd location\n        LD      (HL),E          ; store low byte of length.\n        INC     HL              ; address next.\n        LD      (HL),D          ; store high byte.\n        INC     HL              ; address start of data.\n        PUSH    HL              ; transfer address\n        POP     IX              ; to IX register pair.\n        SCF                     ; set carry flag indicating load not verify.\n        LD      A,$FF           ; signal data not header.\n        JP      L0802           ; JUMP back to LD-BLOCK\n\n; -----------------\n;   the branch is here when a program as opposed to an array is to be loaded.\n\n;; LD-PROG\nL0873:  EX      DE,HL           ; transfer dest to DE.\n        LD      HL,($5C59)      ; address E_LINE\n        DEC     HL              ; now variables end-marker.\n        LD      ($5C5F),IX      ; place the IX header pointer in X_PTR\n        LD      C,(IX+$0B)      ; get new length\n        LD      B,(IX+$0C)      ; from 2nd header\n        PUSH    BC              ; and save it.\n\n        CALL    L19E5           ; routine RECLAIM-1 reclaims program and vars.\n                                ; adjusting X-PTR.\n\n        POP     BC              ; restore new length.\n        PUSH    HL              ; * save start\n        PUSH    BC              ; ** and length.\n\n        CALL    L1655           ; routine MAKE-ROOM creates the space.\n\n        LD      IX,($5C5F)      ; reload IX from adjusted X_PTR\n        INC     HL              ; point to start of new area.\n        LD      C,(IX+$0F)      ; fetch length of BASIC on tape\n        LD      B,(IX+$10)      ; from 2nd descriptor\n        ADD     HL,BC           ; add to address the start of variables.\n        LD      ($5C4B),HL      ; set system variable VARS\n\n        LD      H,(IX+$0E)      ; fetch high byte of autostart line number.\n        LD      A,H             ; transfer to A\n        AND     $C0             ; test if greater than $3F.\n        JR      NZ,L08AD        ; forward to LD-PROG-1 if so with no autostart.\n\n        LD      L,(IX+$0D)      ; else fetch the low byte.\n        LD      ($5C42),HL      ; set system variable to line number NEWPPC\n        LD      (IY+$0A),$00    ; set statement NSPPC to zero.\n\n;; LD-PROG-1\nL08AD:  POP     DE              ; ** pop the length\n        POP     IX              ; * and start.\n        SCF                     ; set carry flag\n        LD      A,$FF           ; signal data as opposed to a header.\n        JP      L0802           ; jump back to LD-BLOCK\n\n; ---------------------------\n; THE 'MERGE CONTROL' ROUTINE\n; ---------------------------\n;   the branch was here to merge a program and its variables or an array.\n;\n\n;; ME-CONTRL\nL08B6:  LD      C,(IX+$0B)      ; fetch length\n        LD      B,(IX+$0C)      ; of data block on tape.\n        PUSH    BC              ; save it.\n        INC     BC              ; one for the pot.\n\n        RST     30H             ; BC-SPACES creates room in workspace.\n                                ; HL addresses last new location.\n        LD      (HL),$80        ; place end-marker at end.\n        EX      DE,HL           ; transfer first location to HL.\n        POP     DE              ; restore length to DE.\n        PUSH    HL              ; save start.\n\n        PUSH    HL              ; and transfer it\n        POP     IX              ; to IX register.\n        SCF                     ; set carry flag to load data on tape.\n        LD      A,$FF           ; signal data not a header.\n        CALL    L0802           ; routine LD-BLOCK loads to workspace.\n        POP     HL              ; restore first location in workspace to HL.\nX08CE   LD      DE,($5C53)      ; set DE from system variable PROG.\n\n;   now enter a loop to merge the data block in workspace with the program and\n;   variables.\n\n;; ME-NEW-LP\nL08D2:  LD      A,(HL)          ; fetch next byte from workspace.\n        AND     $C0             ; compare with $3F.\n        JR      NZ,L08F0        ; forward to ME-VAR-LP if a variable or\n                                ; end-marker.\n\n;   continue when HL addresses a BASIC line number.\n\n;; ME-OLD-LP\nL08D7:  LD      A,(DE)          ; fetch high byte from program area.\n        INC     DE              ; bump prog address.\n        CP      (HL)            ; compare with that in workspace.\n        INC     HL              ; bump workspace address.\n        JR      NZ,L08DF        ; forward to ME-OLD-L1 if high bytes don't match\n\n        LD      A,(DE)          ; fetch the low byte of program line number.\n        CP      (HL)            ; compare with that in workspace.\n\n;; ME-OLD-L1\nL08DF:  DEC     DE              ; point to start of\n        DEC     HL              ; respective lines again.\n        JR      NC,L08EB        ; forward to ME-NEW-L2 if line number in\n                                ; workspace is less than or equal to current\n                                ; program line as has to be added to program.\n\n        PUSH    HL              ; else save workspace pointer.\n        EX      DE,HL           ; transfer prog pointer to HL\n        CALL    L19B8           ; routine NEXT-ONE finds next line in DE.\n        POP     HL              ; restore workspace pointer\n        JR      L08D7           ; back to ME-OLD-LP until destination position\n                                ; in program area found.\n\n; ---\n;   the branch was here with an insertion or replacement point.\n\n;; ME-NEW-L2\nL08EB:  CALL    L092C           ; routine ME-ENTER enters the line\n        JR      L08D2           ; loop back to ME-NEW-LP.\n\n; ---\n;   the branch was here when the location in workspace held a variable.\n\n;; ME-VAR-LP\nL08F0:  LD      A,(HL)          ; fetch first byte of workspace variable.\n        LD      C,A             ; copy to C also.\n        CP      $80             ; is it the end-marker ?\n        RET     Z               ; return if so as complete.  >>>>>\n\n        PUSH    HL              ; save workspace area pointer.\n        LD      HL,($5C4B)      ; load HL with VARS - start of variables area.\n\n;; ME-OLD-VP\nL08F9:  LD      A,(HL)          ; fetch first byte.\n        CP      $80             ; is it the end-marker ?\n        JR      Z,L0923         ; forward if so to ME-VAR-L2 to add\n                                ; variable at end of variables area.\n\n        CP      C               ; compare with variable in workspace area.\n        JR      Z,L0909         ; forward to ME-OLD-V2 if a match to replace.\n\n;   else entire variables area has to be searched.\n\n;; ME-OLD-V1\nL0901:  PUSH    BC              ; save character in C.\n        CALL    L19B8           ; routine NEXT-ONE gets following variable\n                                ; address in DE.\n        POP     BC              ; restore character in C\n        EX      DE,HL           ; transfer next address to HL.\n        JR      L08F9           ; loop back to ME-OLD-VP\n\n; ---\n;   the branch was here when first characters of name matched.\n\n;; ME-OLD-V2\nL0909:  AND     $E0             ; keep bits 11100000\n        CP      $A0             ; compare   10100000 - a long-named variable.\n\n        JR      NZ,L0921        ; forward to ME-VAR-L1 if just one-character.\n\n;   but long-named variables have to be matched character by character.\n\n        POP     DE              ; fetch workspace 1st character pointer\n        PUSH    DE              ; and save it on the stack again.\n        PUSH    HL              ; save variables area pointer on stack.\n\n;; ME-OLD-V3\nL0912:  INC     HL              ; address next character in vars area.\n        INC     DE              ; address next character in workspace area.\n        LD      A,(DE)          ; fetch workspace character.\n        CP      (HL)            ; compare to variables character.\n        JR      NZ,L091E        ; forward to ME-OLD-V4 with a mismatch.\n\n        RLA                     ; test if the terminal inverted character.\n        JR      NC,L0912        ; loop back to ME-OLD-V3 if more to test.\n\n;   otherwise the long name matches in its entirety.\n\n        POP     HL              ; restore pointer to first character of variable\n        JR      L0921           ; forward to ME-VAR-L1\n\n; ---\n;   the branch is here when two characters don't match\n\n;; ME-OLD-V4\nL091E:  POP     HL              ; restore the prog/vars pointer.\n        JR      L0901           ; back to ME-OLD-V1 to resume search.\n\n; ---\n;   branch here when variable is to replace an existing one\n\n;; ME-VAR-L1\nL0921:  LD      A,$FF           ; indicate a replacement.\n\n;   this entry point is when A holds $80 indicating a new variable.\n\n;; ME-VAR-L2\nL0923:  POP     DE              ; pop workspace pointer.\n        EX      DE,HL           ; now make HL workspace pointer, DE vars pointer\n        INC     A               ; zero flag set if replacement.\n        SCF                     ; set carry flag indicating a variable not a\n                                ; program line.\n        CALL    L092C           ; routine ME-ENTER copies variable in.\n        JR      L08F0           ; loop back to ME-VAR-LP\n\n; ------------------------\n; Merge a Line or Variable\n; ------------------------\n;   A BASIC line or variable is inserted at the current point. If the line\n;   number or variable names match (zero flag set) then a replacement takes\n;   place.\n\n;; ME-ENTER\nL092C:  JR      NZ,L093E        ; forward to ME-ENT-1 for insertion only.\n\n;   but the program line or variable matches so old one is reclaimed.\n\n        EX      AF,AF'          ; save flag??\n        LD      ($5C5F),HL      ; preserve workspace pointer in dynamic X_PTR\n        EX      DE,HL           ; transfer program dest pointer to HL.\n        CALL    L19B8           ; routine NEXT-ONE finds following location\n                                ; in program or variables area.\n        CALL    L19E8           ; routine RECLAIM-2 reclaims the space between.\n        EX      DE,HL           ; transfer program dest pointer back to DE.\n        LD      HL,($5C5F)      ; fetch adjusted workspace pointer from X_PTR\n        EX      AF,AF'          ; restore flags.\n\n;   now the new line or variable is entered.\n\n;; ME-ENT-1\nL093E:  EX      AF,AF'          ; save or re-save flags.\n        PUSH    DE              ; save dest pointer in prog/vars area.\n        CALL    L19B8           ; routine NEXT-ONE finds next in workspace.\n                                ; gets next in DE, difference in BC.\n                                ; prev addr in HL\n        LD      ($5C5F),HL      ; store pointer in X_PTR\n        LD      HL,($5C53)      ; load HL from system variable PROG\n        EX      (SP),HL         ; swap with prog/vars pointer on stack.\n        PUSH    BC              ; ** save length of new program line/variable.\n        EX      AF,AF'          ; fetch flags back.\n        JR      C,L0955         ; skip to ME-ENT-2 if variable\n\n        DEC     HL              ; address location before pointer\n        CALL    L1655           ; routine MAKE-ROOM creates room for BASIC line\n        INC     HL              ; address next.\n        JR      L0958           ; forward to ME-ENT-3\n\n; ---\n\n;; ME-ENT-2\nL0955:  CALL    L1655           ; routine MAKE-ROOM creates room for variable.\n\n;; ME-ENT-3\nL0958:  INC     HL              ; address next?\n\n        POP     BC              ; ** pop length\n        POP     DE              ; * pop value for PROG which may have been\n                                ; altered by POINTERS if first line.\n        LD      ($5C53),DE      ; set PROG to original value.\n        LD      DE,($5C5F)      ; fetch adjusted workspace pointer from X_PTR\n        PUSH    BC              ; save length\n        PUSH    DE              ; and workspace pointer\n        EX      DE,HL           ; make workspace pointer source, prog/vars\n                                ; pointer the destination\n        LDIR                    ; copy bytes of line or variable into new area.\n        POP     HL              ; restore workspace pointer.\n        POP     BC              ; restore length.\n        PUSH    DE              ; save new prog/vars pointer.\n        CALL    L19E8           ; routine RECLAIM-2 reclaims the space used\n                                ; by the line or variable in workspace block\n                                ; as no longer required and space could be\n                                ; useful for adding more lines.\n        POP     DE              ; restore the prog/vars pointer\n        RET                     ; return.\n\n; --------------------------\n; THE 'SAVE CONTROL' ROUTINE\n; --------------------------\n;   A branch from the main SAVE-ETC routine at SAVE-ALL.\n;   First the header data is saved. Then after a wait of 1 second\n;   the data itself is saved.\n;   HL points to start of data.\n;   IX points to start of descriptor.\n\n;; SA-CONTRL\nL0970:  PUSH    HL              ; save start of data\n\n        LD      A,$FD           ; select system channel 'S'\n        CALL    L1601           ; routine CHAN-OPEN\n\n        XOR     A               ; clear to address table directly\n        LD      DE,L09A1        ; address: tape-msgs\n        CALL    L0C0A           ; routine PO-MSG -\n                                ; 'Start tape then press any key.'\n\n        SET     5,(IY+$02)      ; TV_FLAG  - Signal lower screen requires\n                                ; clearing\n        CALL    L15D4           ; routine WAIT-KEY\n\n        PUSH    IX              ; save pointer to descriptor.\n        LD      DE,$0011        ; there are seventeen bytes.\n        XOR     A               ; signal a header.\n        CALL    L04C2           ; routine SA-BYTES\n\n        POP     IX              ; restore descriptor pointer.\n\n        LD      B,$32           ; wait for a second - 50 interrupts.\n\n;; SA-1-SEC\nL0991:  HALT                    ; wait for interrupt\n        DJNZ    L0991           ; back to SA-1-SEC until pause complete.\n\n        LD      E,(IX+$0B)      ; fetch length of bytes from the\n        LD      D,(IX+$0C)      ; descriptor.\n\n        LD      A,$FF           ; signal data bytes.\n\n        POP     IX              ; retrieve pointer to start\n        JP      L04C2           ; jump back to SA-BYTES\n\n\n;   Arrangement of two headers in workspace.\n;   Originally IX addresses first location and only one header is required\n;   when saving.\n;\n;   OLD     NEW         PROG   DATA  DATA  CODE\n;   HEADER  HEADER             num   chr          NOTES.\n;   ------  ------      ----   ----  ----  ----   -----------------------------\n;   IX-$11  IX+$00      0      1     2     3      Type.\n;   IX-$10  IX+$01      x      x     x     x      F  ($FF if filename is null).\n;   IX-$0F  IX+$02      x      x     x     x      i\n;   IX-$0E  IX+$03      x      x     x     x      l\n;   IX-$0D  IX+$04      x      x     x     x      e\n;   IX-$0C  IX+$05      x      x     x     x      n\n;   IX-$0B  IX+$06      x      x     x     x      a\n;   IX-$0A  IX+$07      x      x     x     x      m\n;   IX-$09  IX+$08      x      x     x     x      e\n;   IX-$08  IX+$09      x      x     x     x      .\n;   IX-$07  IX+$0A      x      x     x     x      (terminal spaces).\n;   IX-$06  IX+$0B      lo     lo    lo    lo     Total\n;   IX-$05  IX+$0C      hi     hi    hi    hi     Length of datablock.\n;   IX-$04  IX+$0D      Auto   -     -     Start  Various\n;   IX-$03  IX+$0E      Start  a-z   a-z   addr   ($80 if no autostart).\n;   IX-$02  IX+$0F      lo     -     -     -      Length of Program\n;   IX-$01  IX+$10      hi     -     -     -      only i.e. without variables.\n;\n\n\n; ------------------------\n; Canned cassette messages\n; ------------------------\n;   The last-character-inverted Cassette messages.\n;   Starts with normal initial step-over byte.\n\n;; tape-msgs\nL09A1:  DEFB    $80\n        DEFM    \"Start tape, then press any key\"\nL09C0:  DEFB    '.'+$80\n        DEFB    $0D\n        DEFM    \"Program:\"\n        DEFB    ' '+$80\n        DEFB    $0D\n        DEFM    \"Number array:\"\n        DEFB    ' '+$80\n        DEFB    $0D\n        DEFM    \"Character array:\"\n        DEFB    ' '+$80\n        DEFB    $0D\n        DEFM    \"Bytes:\"\n        DEFB    ' '+$80\n\n\n;**************************************************\n;** Part 5. SCREEN AND PRINTER HANDLING ROUTINES **\n;**************************************************\n\n; --------------------------\n; THE 'PRINT OUTPUT' ROUTINE\n; --------------------------\n;   This is the routine most often used by the RST 10 restart although the\n;   subroutine is on two occasions called directly when it is known that\n;   output will definitely be to the lower screen.\n\n;; PRINT-OUT\nL09F4:  CALL    L0B03           ; routine PO-FETCH fetches print position\n                                ; to HL register pair.\n        CP      $20             ; is character a space or higher ?\n        JP      NC,L0AD9        ; jump forward to PO-ABLE if so.\n\n        CP      $06             ; is character in range 00-05 ?\n        JR      C,L0A69         ; to PO-QUEST to print '?' if so.\n\n        CP      $18             ; is character in range 24d - 31d ?\n        JR      NC,L0A69        ; to PO-QUEST to also print '?' if so.\n\n        LD      HL,L0A11 - 6    ; address 0A0B - the base address of control\n                                ; character table - where zero would be.\n        LD      E,A             ; control character 06 - 23d\n        LD      D,$00           ; is transferred to DE.\n\n        ADD     HL,DE           ; index into table.\n\n        LD      E,(HL)          ; fetch the offset to routine.\n        ADD     HL,DE           ; add to make HL the address.\n        PUSH    HL              ; push the address.\n\n        JP      L0B03           ; Jump forward to PO-FETCH,\n                                ; as the screen/printer position has been\n                                ; disturbed, and then indirectly to the PO-STORE\n                                ; routine on stack.\n\n; -----------------------------\n; THE 'CONTROL CHARACTER' TABLE\n; -----------------------------\n;   For control characters in the range 6 - 23d the following table\n;   is indexed to provide an offset to the handling routine that\n;   follows the table.\n\n;; ctlchrtab\nL0A11:  DEFB    L0A5F - $       ; 06d offset $4E to Address: PO-COMMA\n        DEFB    L0A69 - $       ; 07d offset $57 to Address: PO-QUEST\n        DEFB    L0A23 - $       ; 08d offset $10 to Address: PO-BACK-1\n        DEFB    L0A3D - $       ; 09d offset $29 to Address: PO-RIGHT\n        DEFB    L0A69 - $       ; 10d offset $54 to Address: PO-QUEST\n        DEFB    L0A69 - $       ; 11d offset $53 to Address: PO-QUEST\n        DEFB    L0A69 - $       ; 12d offset $52 to Address: PO-QUEST\n        DEFB    L0A4F - $       ; 13d offset $37 to Address: PO-ENTER\n        DEFB    L0A69 - $       ; 14d offset $50 to Address: PO-QUEST\n        DEFB    L0A69 - $       ; 15d offset $4F to Address: PO-QUEST\n        DEFB    L0A7A - $       ; 16d offset $5F to Address: PO-1-OPER\n        DEFB    L0A7A - $       ; 17d offset $5E to Address: PO-1-OPER\n        DEFB    L0A7A - $       ; 18d offset $5D to Address: PO-1-OPER\n        DEFB    L0A7A - $       ; 19d offset $5C to Address: PO-1-OPER\n        DEFB    L0A7A - $       ; 20d offset $5B to Address: PO-1-OPER\n        DEFB    L0A7A - $       ; 21d offset $5A to Address: PO-1-OPER\n        DEFB    L0A75 - $       ; 22d offset $54 to Address: PO-2-OPER\n        DEFB    L0A75 - $       ; 23d offset $53 to Address: PO-2-OPER\n\n\n; -------------------------\n; THE 'CURSOR LEFT' ROUTINE\n; -------------------------\n;   Backspace and up a line if that action is from the left of screen.\n;   For ZX printer backspace up to first column but not beyond.\n\n;; PO-BACK-1\nL0A23:  INC     C               ; move left one column.\n        LD      A,$22           ; value $21 is leftmost column.\n        CP      C               ; have we passed ?\n        JR      NZ,L0A3A        ; to PO-BACK-3 if not and store new position.\n\n        BIT     1,(IY+$01)      ; test FLAGS  - is printer in use ?\n        JR      NZ,L0A38        ; to PO-BACK-2 if so, as we are unable to\n                                ; backspace from the leftmost position.\n\n\n        INC     B               ; move up one screen line\n        LD      C,$02           ; the rightmost column position.\n        LD      A,$18           ; Note. This should be $19\n                                ; credit. Dr. Frank O'Hara, 1982\n\n        CP      B               ; has position moved past top of screen ?\n        JR      NZ,L0A3A        ; to PO-BACK-3 if not and store new position.\n\n        DEC     B               ; else back to $18.\n\n;; PO-BACK-2\nL0A38:  LD      C,$21           ; the leftmost column position.\n\n;; PO-BACK-3\nL0A3A:  JP      L0DD9           ; to CL-SET and PO-STORE to save new\n                                ; position in system variables.\n\n; --------------------------\n; THE 'CURSOR RIGHT' ROUTINE\n; --------------------------\n;   This moves the print position to the right leaving a trail in the\n;   current background colour.\n;   \"However the programmer has failed to store the new print position\n;   so CHR$ 9 will only work if the next print position is at a newly\n;   defined place.\n;   e.g. PRINT PAPER 2; CHR$ 9; AT 4,0;\n;   does work but is not very helpful\"\n;   - Dr. Ian Logan, Understanding Your Spectrum, 1982.\n\n;; PO-RIGHT\nL0A3D:  LD      A,($5C91)       ; fetch P_FLAG value\n        PUSH    AF              ; and save it on stack.\n\n        LD      (IY+$57),$01    ; temporarily set P_FLAG 'OVER 1'.\n        LD      A,$20           ; prepare a space.\n        CALL    L0B65           ; routine PO-CHAR to print it.\n                                ; Note. could be PO-ABLE which would update\n                                ; the column position.\n\n        POP     AF              ; restore the permanent flag.\n        LD      ($5C91),A       ; and restore system variable P_FLAG\n\n        RET                     ; return without updating column position\n\n; -----------------------\n; Perform carriage return\n; -----------------------\n; A carriage return is 'printed' to screen or printer buffer.\n\n;; PO-ENTER\nL0A4F:  BIT     1,(IY+$01)      ; test FLAGS  - is printer in use ?\n        JP      NZ,L0ECD        ; to COPY-BUFF if so, to flush buffer and reset\n                                ; the print position.\n\n        LD      C,$21           ; the leftmost column position.\n        CALL    L0C55           ; routine PO-SCR handles any scrolling required.\n        DEC     B               ; to next screen line.\n        JP      L0DD9           ; jump forward to CL-SET to store new position.\n\n; -----------\n; Print comma\n; -----------\n; The comma control character. The 32 column screen has two 16 character\n; tabstops.  The routine is only reached via the control character table.\n\n;; PO-COMMA\nL0A5F:  CALL    L0B03           ; routine PO-FETCH - seems unnecessary.\n\n        LD      A,C             ; the column position. $21-$01\n        DEC     A               ; move right. $20-$00\n        DEC     A               ; and again   $1F-$00 or $FF if trailing\n        AND     $10             ; will be $00 or $10.\n        JR      L0AC3           ; forward to PO-FILL\n\n; -------------------\n; Print question mark\n; -------------------\n; This routine prints a question mark which is commonly\n; used to print an unassigned control character in range 0-31d.\n; there are a surprising number yet to be assigned.\n\n;; PO-QUEST\nL0A69:  LD      A,$3F           ; prepare the character '?'.\n        JR      L0AD9           ; forward to PO-ABLE.\n\n; --------------------------------\n; Control characters with operands\n; --------------------------------\n; Certain control characters are followed by 1 or 2 operands.\n; The entry points from control character table are PO-2-OPER and PO-1-OPER.\n; The routines alter the output address of the current channel so that\n; subsequent RST $10 instructions take the appropriate action\n; before finally resetting the output address back to PRINT-OUT.\n\n;; PO-TV-2\nL0A6D:  LD      DE,L0A87        ; address: PO-CONT will be next output routine\n        LD      ($5C0F),A       ; store first operand in TVDATA-hi\n        JR      L0A80           ; forward to PO-CHANGE >>\n\n; ---\n\n; -> This initial entry point deals with two operands - AT or TAB.\n\n;; PO-2-OPER\nL0A75:  LD      DE,L0A6D        ; address: PO-TV-2 will be next output routine\n        JR      L0A7D           ; forward to PO-TV-1\n\n; ---\n\n; -> This initial entry point deals with one operand INK to OVER.\n\n;; PO-1-OPER\nL0A7A:  LD      DE,L0A87        ; address: PO-CONT will be next output routine\n\n;; PO-TV-1\nL0A7D:  LD      ($5C0E),A       ; store control code in TVDATA-lo\n\n;; PO-CHANGE\nL0A80:  LD      HL,($5C51)      ; use CURCHL to find current output channel.\n        LD      (HL),E          ; make it\n        INC     HL              ; the supplied\n        LD      (HL),D          ; address from DE.\n        RET                     ; return.\n\n; ---\n\n;; PO-CONT\nL0A87:  LD      DE,L09F4        ; Address: PRINT-OUT\n        CALL    L0A80           ; routine PO-CHANGE to restore normal channel.\n        LD      HL,($5C0E)      ; TVDATA gives control code and possible\n                                ; subsequent character\n        LD      D,A             ; save current character\n        LD      A,L             ; the stored control code\n        CP      $16             ; was it INK to OVER (1 operand) ?\n        JP      C,L2211         ; to CO-TEMP-5\n\n        JR      NZ,L0AC2        ; to PO-TAB if not 22d i.e. 23d TAB.\n\n                                ; else must have been 22d AT.\n        LD      B,H             ; line to H   (0-23d)\n        LD      C,D             ; column to C (0-31d)\n        LD      A,$1F           ; the value 31d\n        SUB     C               ; reverse the column number.\n        JR      C,L0AAC         ; to PO-AT-ERR if C was greater than 31d.\n\n        ADD     A,$02           ; transform to system range $02-$21\n        LD      C,A             ; and place in column register.\n\n        BIT     1,(IY+$01)      ; test FLAGS  - is printer in use ?\n        JR      NZ,L0ABF        ; to PO-AT-SET as line can be ignored.\n\n        LD      A,$16           ; 22 decimal\n        SUB     B               ; subtract line number to reverse\n                                ; 0 - 22 becomes 22 - 0.\n\n;; PO-AT-ERR\nL0AAC:  JP      C,L1E9F         ; to REPORT-B if higher than 22 decimal\n                                ; Integer out of range.\n\n        INC     A               ; adjust for system range $01-$17\n        LD      B,A             ; place in line register\n        INC     B               ; adjust to system range  $02-$18\n        BIT     0,(IY+$02)      ; TV_FLAG  - Lower screen in use ?\n        JP      NZ,L0C55        ; exit to PO-SCR to test for scrolling\n\n        CP      (IY+$31)        ; Compare against DF_SZ\n        JP      C,L0C86         ; to REPORT-5 if too low\n                                ; Out of screen.\n\n;; PO-AT-SET\nL0ABF:  JP      L0DD9           ; print position is valid so exit via CL-SET\n\n; ---\n\n; Continue here when dealing with TAB.\n; Note. In BASIC, TAB is followed by a 16-bit number and was initially\n; designed to work with any output device.\n\n;; PO-TAB\nL0AC2:  LD      A,H             ; transfer parameter to A\n                                ; Losing current character -\n                                ; High byte of TAB parameter.\n\n\n;; PO-FILL\nL0AC3:  CALL    L0B03           ; routine PO-FETCH, HL-addr, BC=line/column.\n                                ; column 1 (right), $21 (left)\n        ADD     A,C             ; add operand to current column\n        DEC     A               ; range 0 - 31+\n        AND     $1F             ; make range 0 - 31d\n        RET     Z               ; return if result zero\n\n        LD      D,A             ; Counter to D\n        SET     0,(IY+$01)      ; update FLAGS  - signal suppress leading space.\n\n;; PO-SPACE\nL0AD0:  LD      A,$20           ; space character.\n\n        CALL    L0C3B           ; routine PO-SAVE prints the character\n                                ; using alternate set (normal output routine)\n\n        DEC     D               ; decrement counter.\n        JR      NZ,L0AD0        ; to PO-SPACE until done\n\n        RET                     ; return\n\n; ----------------------\n; Printable character(s)\n; ----------------------\n; This routine prints printable characters and continues into\n; the position store routine\n\n;; PO-ABLE\nL0AD9:  CALL    L0B24           ; routine PO-ANY\n                                ; and continue into position store routine.\n\n; ----------------------------\n; THE 'POSITION STORE' ROUTINE\n; ----------------------------\n;   This routine updates the system variables associated with the main screen,\n;   the lower screen/input buffer or the ZX printer.\n\n;; PO-STORE\nL0ADC:  BIT     1,(IY+$01)      ; Test FLAGS - is printer in use ?\n        JR      NZ,L0AFC        ; Forward, if so, to PO-ST-PR\n\n        BIT     0,(IY+$02)      ; Test TV_FLAG - is lower screen in use ?\n        JR      NZ,L0AF0        ; Forward, if so, to PO-ST-E\n\n;   This section deals with the upper screen.\n\n        LD      ($5C88),BC      ; Update S_POSN - line/column upper screen\n        LD      ($5C84),HL      ; Update DF_CC - upper display file address\n\n        RET                     ; Return.\n\n; ---\n\n;   This section deals with the lower screen.\n\n;; PO-ST-E\nL0AF0:  LD      ($5C8A),BC      ; Update SPOSNL line/column lower screen\n        LD      ($5C82),BC      ; Update ECHO_E line/column input buffer\n        LD      ($5C86),HL      ; Update DFCCL  lower screen memory address\n        RET                     ; Return.\n\n; ---\n\n;   This section deals with the ZX Printer.\n\n;; PO-ST-PR\nL0AFC:  LD      (IY+$45),C      ; Update P_POSN column position printer\n        LD      ($5C80),HL      ; Update PR_CC - full printer buffer memory\n                                ; address\n        RET                     ; Return.\n\n;   Note. that any values stored in location 23681 will be overwritten with\n;   the value 91 decimal.\n;   Credit April 1983, Dilwyn Jones. \"Delving Deeper into your ZX Spectrum\".\n\n; ----------------------------\n; THE 'POSITION FETCH' ROUTINE\n; ----------------------------\n;   This routine fetches the line/column and display file address of the upper\n;   and lower screen or, if the printer is in use, the column position and\n;   absolute memory address.\n;   Note. that PR-CC-hi (23681) is used by this routine and if, in accordance\n;   with the manual (that says this is unused), the location has been used for\n;   other purposes, then subsequent output to the printer buffer could corrupt\n;   a 256-byte section of memory.\n\n;; PO-FETCH\nL0B03:  BIT     1,(IY+$01)      ; Test FLAGS - is printer in use ?\n        JR      NZ,L0B1D        ; Forward, if so, to PO-F-PR\n\n;   assume upper screen in use and thus optimize for path that requires speed.\n\n        LD      BC,($5C88)      ; Fetch line/column from S_POSN\n        LD      HL,($5C84)      ; Fetch DF_CC display file address\n\n        BIT     0,(IY+$02)      ; Test TV_FLAG - lower screen in use ?\n        RET     Z               ; Return if upper screen in use.\n\n;   Overwrite registers with values for lower screen.\n\n        LD      BC,($5C8A)      ; Fetch line/column from SPOSNL\n        LD      HL,($5C86)      ; Fetch display file address from DFCCL\n        RET                     ; Return.\n\n; ---\n\n;   This section deals with the ZX Printer.\n\n;; PO-F-PR\nL0B1D:  LD      C,(IY+$45)      ; Fetch column from P_POSN.\n        LD      HL,($5C80)      ; Fetch printer buffer address from PR_CC.\n        RET                     ; Return.\n\n; ---------------------------------\n; THE 'PRINT ANY CHARACTER' ROUTINE\n; ---------------------------------\n;   This routine is used to print any character in range 32d - 255d\n;   It is only called from PO-ABLE which continues into PO-STORE\n\n;; PO-ANY\nL0B24:  CP      $80             ; ASCII ?\n        JR      C,L0B65         ; to PO-CHAR is so.\n\n        CP      $90             ; test if a block graphic character.\n        JR      NC,L0B52        ; to PO-T&UDG to print tokens and UDGs\n\n; The 16 2*2 mosaic characters 128-143 decimal are formed from\n; bits 0-3 of the character.\n\n        LD      B,A             ; save character\n        CALL    L0B38           ; routine PO-GR-1 to construct top half\n                                ; then bottom half.\n        CALL    L0B03           ; routine PO-FETCH fetches print position.\n        LD      DE,$5C92        ; MEM-0 is location of 8 bytes of character\n        JR      L0B7F           ; to PR-ALL to print to screen or printer\n\n; ---\n\n;; PO-GR-1\nL0B38:  LD      HL,$5C92        ; address MEM-0 - a temporary buffer in\n                                ; systems variables which is normally used\n                                ; by the calculator.\n        CALL    L0B3E           ; routine PO-GR-2 to construct top half\n                                ; and continue into routine to construct\n                                ; bottom half.\n\n;; PO-GR-2\nL0B3E:  RR      B               ; rotate bit 0/2 to carry\n        SBC     A,A             ; result $00 or $FF\n        AND     $0F             ; mask off right hand side\n        LD      C,A             ; store part in C\n        RR      B               ; rotate bit 1/3 of original chr to carry\n        SBC     A,A             ; result $00 or $FF\n        AND     $F0             ; mask off left hand side\n        OR      C               ; combine with stored pattern\n        LD      C,$04           ; four bytes for top/bottom half\n\n;; PO-GR-3\nL0B4C:  LD      (HL),A          ; store bit patterns in temporary buffer\n        INC     HL              ; next address\n        DEC     C               ; jump back to\n        JR      NZ,L0B4C        ; to PO-GR-3 until byte is stored 4 times\n\n        RET                     ; return\n\n; ---\n\n; Tokens and User defined graphics are now separated.\n\n;; PO-T&UDG\nL0B52:  SUB     $A5             ; the 'RND' character\n        JR      NC,L0B5F        ; to PO-T to print tokens\n\n        ADD     A,$15           ; add 21d to restore to 0 - 20\n        PUSH    BC              ; save current print position\n        LD      BC,($5C7B)      ; fetch UDG to address bit patterns\n        JR      L0B6A           ; to PO-CHAR-2 - common code to lay down\n                                ; a bit patterned character\n\n; ---\n\n;; PO-T\nL0B5F:  CALL    L0C10           ; routine PO-TOKENS prints tokens\n        JP      L0B03           ; exit via a JUMP to PO-FETCH as this routine\n                                ; must continue into PO-STORE.\n                                ; A JR instruction could be used.\n\n; This point is used to print ASCII characters  32d - 127d.\n\n;; PO-CHAR\nL0B65:  PUSH    BC              ; save print position\n        LD      BC,($5C36)      ; address CHARS\n\n; This common code is used to transfer the character bytes to memory.\n\n;; PO-CHAR-2\nL0B6A:  EX      DE,HL           ; transfer destination address to DE\n        LD      HL,$5C3B        ; point to FLAGS\n        RES     0,(HL)          ; allow for leading space\n        CP      $20             ; is it a space ?\n        JR      NZ,L0B76        ; to PO-CHAR-3 if not\n\n        SET     0,(HL)          ; signal no leading space to FLAGS\n\n;; PO-CHAR-3\nL0B76:  LD      H,$00           ; set high byte to 0\n        LD      L,A             ; character to A\n                                ; 0-21 UDG or 32-127 ASCII.\n        ADD     HL,HL           ; multiply\n        ADD     HL,HL           ; by\n        ADD     HL,HL           ; eight\n        ADD     HL,BC           ; HL now points to first byte of character\n        POP     BC              ; the source address CHARS or UDG\n        EX      DE,HL           ; character address to DE\n\n; ----------------------------------\n; THE 'PRINT ALL CHARACTERS' ROUTINE\n; ----------------------------------\n;   This entry point entered from above to print ASCII and UDGs but also from\n;   earlier to print mosaic characters.\n;   HL=destination\n;   DE=character source\n;   BC=line/column\n\n;; PR-ALL\nL0B7F:  LD      A,C             ; column to A\n        DEC     A               ; move right\n        LD      A,$21           ; pre-load with leftmost position\n        JR      NZ,L0B93        ; but if not zero to PR-ALL-1\n\n        DEC     B               ; down one line\n        LD      C,A             ; load C with $21\n        BIT     1,(IY+$01)      ; test FLAGS  - Is printer in use\n        JR      Z,L0B93         ; to PR-ALL-1 if not\n\n        PUSH    DE              ; save source address\n        CALL    L0ECD           ; routine COPY-BUFF outputs line to printer\n        POP     DE              ; restore character source address\n        LD      A,C             ; the new column number ($21) to C\n\n;; PR-ALL-1\nL0B93:  CP      C               ; this test is really for screen - new line ?\n        PUSH    DE              ; save source\n\n        CALL    Z,L0C55         ; routine PO-SCR considers scrolling\n\n        POP     DE              ; restore source\n        PUSH    BC              ; save line/column\n        PUSH    HL              ; and destination\n        LD      A,($5C91)       ; fetch P_FLAG to accumulator\n        LD      B,$FF           ; prepare OVER mask in B.\n        RRA                     ; bit 0 set if OVER 1\n        JR      C,L0BA4         ; to PR-ALL-2\n\n        INC     B               ; set OVER mask to 0\n\n;; PR-ALL-2\nL0BA4:  RRA                     ; skip bit 1 of P_FLAG\n        RRA                     ; bit 2 is INVERSE\n        SBC     A,A             ; will be FF for INVERSE 1 else zero\n        LD      C,A             ; transfer INVERSE mask to C\n        LD      A,$08           ; prepare to count 8 bytes\n        AND     A               ; clear carry to signal screen\n        BIT     1,(IY+$01)      ; test FLAGS  - is printer in use ?\n        JR      Z,L0BB6         ; to PR-ALL-3 if screen\n\n        SET     1,(IY+$30)      ; update FLAGS2  - signal printer buffer has\n                                ; been used.\n        SCF                     ; set carry flag to signal printer.\n\n;; PR-ALL-3\nL0BB6:  EX      DE,HL           ; now HL=source, DE=destination\n\n;; PR-ALL-4\nL0BB7:  EX      AF,AF'          ; save printer/screen flag\n        LD      A,(DE)          ; fetch existing destination byte\n        AND     B               ; consider OVER\n        XOR     (HL)            ; now XOR with source\n        XOR     C               ; now with INVERSE MASK\n        LD      (DE),A          ; update screen/printer\n        EX      AF,AF'          ; restore flag\n        JR      C,L0BD3         ; to PR-ALL-6 - printer address update\n\n        INC     D               ; gives next pixel line down screen\n\n;; PR-ALL-5\nL0BC1:  INC     HL              ; address next character byte\n        DEC     A               ; the byte count is decremented\n        JR      NZ,L0BB7        ; back to PR-ALL-4 for all 8 bytes\n\n        EX      DE,HL           ; destination to HL\n        DEC     H               ; bring back to last updated screen position\n        BIT     1,(IY+$01)      ; test FLAGS  - is printer in use ?\n        CALL    Z,L0BDB         ; if not, call routine PO-ATTR to update\n                                ; corresponding colour attribute.\n        POP     HL              ; restore original screen/printer position\n        POP     BC              ; and line column\n        DEC     C               ; move column to right\n        INC     HL              ; increase screen/printer position\n        RET                     ; return and continue into PO-STORE\n                                ; within PO-ABLE\n\n; ---\n\n;   This branch is used to update the printer position by 32 places\n;   Note. The high byte of the address D remains constant (which it should).\n\n;; PR-ALL-6\nL0BD3:  EX      AF,AF'          ; save the flag\n        LD      A,$20           ; load A with 32 decimal\n        ADD     A,E             ; add this to E\n        LD      E,A             ; and store result in E\n        EX      AF,AF'          ; fetch the flag\n        JR      L0BC1           ; back to PR-ALL-5\n\n; -----------------------------------\n; THE 'GET ATTRIBUTE ADDRESS' ROUTINE\n; -----------------------------------\n;   This routine is entered with the HL register holding the last screen\n;   address to be updated by PRINT or PLOT.\n;   The Spectrum screen arrangement leads to the L register holding the correct\n;   value for the attribute file and it is only necessary to manipulate H to\n;   form the correct colour attribute address.\n\n;; PO-ATTR\nL0BDB:  LD       A,H            ; fetch high byte $40 - $57\n        RRCA                    ; shift\n        RRCA                    ; bits 3 and 4\n        RRCA                    ; to right.\n        AND     $03             ; range is now 0 - 2\n        OR      $58             ; form correct high byte for third of screen\n        LD      H,A             ; HL is now correct\n        LD      DE,($5C8F)      ; make D hold ATTR_T, E hold MASK-T\n        LD      A,(HL)          ; fetch existing attribute\n        XOR     E               ; apply masks\n        AND     D               ;\n        XOR     E               ;\n        BIT     6,(IY+$57)      ; test P_FLAG  - is this PAPER 9 ??\n        JR      Z,L0BFA         ; skip to PO-ATTR-1 if not.\n\n        AND     $C7             ; set paper\n        BIT     2,A             ; to contrast with ink\n        JR      NZ,L0BFA        ; skip to PO-ATTR-1\n\n        XOR     $38             ;\n\n;; PO-ATTR-1\nL0BFA:  BIT     4,(IY+$57)      ; test P_FLAG  - Is this INK 9 ??\n        JR      Z,L0C08         ; skip to PO-ATTR-2 if not\n\n        AND     $F8             ; make ink\n        BIT     5,A             ; contrast with paper.\n        JR      NZ,L0C08        ; to PO-ATTR-2\n\n        XOR     $07             ;\n\n;; PO-ATTR-2\nL0C08:  LD      (HL),A          ; save the new attribute.\n        RET                     ; return.\n\n; ---------------------------------\n; THE 'MESSAGE PRINTING' SUBROUTINE\n; ---------------------------------\n;   This entry point is used to print tape, boot-up, scroll? and error messages.\n;   On entry the DE register points to an initial step-over byte or the\n;   inverted end-marker of the previous entry in the table.\n;   Register A contains the message number, often zero to print first message.\n;   (HL has nothing important usually P_FLAG)\n\n;; PO-MSG\nL0C0A:  PUSH    HL              ; put hi-byte zero on stack to suppress\n        LD      H,$00           ; trailing spaces\n        EX      (SP),HL         ; ld h,0; push hl would have done ?.\n        JR      L0C14           ; forward to PO-TABLE.\n\n; ---\n\n;   This entry point prints the BASIC keywords, '<>' etc. from alt set\n\n;; PO-TOKENS\nL0C10:  LD      DE,L0095        ; address: TKN-TABLE\n        PUSH    AF              ; save the token number to control\n                                ; trailing spaces - see later *\n\n; ->\n\n;; PO-TABLE\nL0C14:  CALL    L0C41           ; routine PO-SEARCH will set carry for\n                                ; all messages and function words.\n\n        JR      C,L0C22         ; forward to PO-EACH if not a command, '<>' etc.\n\n        LD      A,$20           ; prepare leading space\n        BIT     0,(IY+$01)      ; test FLAGS  - leading space if not set\n\n        CALL    Z,L0C3B         ; routine PO-SAVE to print a space without\n                                ; disturbing registers.\n\n;; PO-EACH\nL0C22:  LD      A,(DE)          ; Fetch character from the table.\n        AND     $7F             ; Cancel any inverted bit.\n\n        CALL    L0C3B           ; Routine PO-SAVE to print using the alternate\n                                ; set of registers.\n\n        LD      A,(DE)          ; Re-fetch character from table.\n        INC     DE              ; Address next character in the table.\n\n        ADD     A,A             ; Was character inverted ?\n                                ; (this also doubles character)\n        JR      NC,L0C22        ; back to PO-EACH if not.\n\n        POP     DE              ; * re-fetch trailing space byte to D\n\n        CP      $48             ; was the last character '$' ?\n        JR      Z,L0C35         ; forward to PO-TR-SP to consider trailing\n                                ; space if so.\n\n        CP      $82             ; was it < 'A' i.e. '#','>','=' from tokens\n                                ; or ' ','.' (from tape) or '?' from scroll\n\n        RET     C               ; Return if so as no trailing space required.\n\n;; PO-TR-SP\nL0C35:  LD      A,D             ; The trailing space flag (zero if an error msg)\n\n        CP      $03             ; Test against RND, INKEY$ and PI which have no\n                                ; parameters and therefore no trailing space.\n\n        RET     C               ; Return if no trailing space.\n\n        LD      A,$20           ; Prepare the space character and continue to\n                                ; print and make an indirect return.\n\n; -----------------------------------\n; THE 'RECURSIVE PRINTING' SUBROUTINE\n; -----------------------------------\n;   This routine which is part of PRINT-OUT allows RST $10 to be used\n;   recursively to print tokens and the spaces associated with them.\n;   It is called on three occasions when the value of DE must be preserved.\n\n;; PO-SAVE\nL0C3B:  PUSH    DE              ; Save DE value.\n        EXX                     ; Switch in main set\n\n        RST     10H             ; PRINT-A prints using this alternate set.\n\n        EXX                     ; Switch back to this alternate set.\n        POP     DE              ; Restore the initial DE value.\n\n        RET                     ; Return.\n\n; ------------\n; Table search\n; ------------\n; This subroutine searches a message or the token table for the\n; message number held in A. DE holds the address of the table.\n\n;; PO-SEARCH\nL0C41:  PUSH    AF              ; save the message/token number\n        EX      DE,HL           ; transfer DE to HL\n        INC     A               ; adjust for initial step-over byte\n\n;; PO-STEP\nL0C44:  BIT     7,(HL)          ; is character inverted ?\n        INC     HL              ; address next\n        JR      Z,L0C44         ; back to PO-STEP if not inverted.\n\n        DEC     A               ; decrease counter\n        JR      NZ,L0C44        ; back to PO-STEP if not zero\n\n        EX      DE,HL           ; transfer address to DE\n        POP     AF              ; restore message/token number\n        CP      $20             ; return with carry set\n        RET     C               ; for all messages and function tokens\n\n        LD      A,(DE)          ; test first character of token\n        SUB     $41             ; and return with carry set\n        RET                     ; if it is less that 'A'\n                                ; i.e. '<>', '<=', '>='\n\n; ---------------\n; Test for scroll\n; ---------------\n; This test routine is called when printing carriage return, when considering\n; PRINT AT and from the general PRINT ALL characters routine to test if\n; scrolling is required, prompting the user if necessary.\n; This is therefore using the alternate set.\n; The B register holds the current line.\n\n;; PO-SCR\nL0C55:  BIT     1,(IY+$01)      ; test FLAGS  - is printer in use ?\n        RET     NZ              ; return immediately if so.\n\n        LD      DE,L0DD9        ; set DE to address: CL-SET\n        PUSH    DE              ; and push for return address.\n\n        LD      A,B             ; transfer the line to A.\n        BIT     0,(IY+$02)      ; test TV_FLAG - lower screen in use ?\n        JP      NZ,L0D02        ; jump forward to PO-SCR-4 if so.\n\n        CP      (IY+$31)        ; greater than DF_SZ display file size ?\n        JR      C,L0C86         ; forward to REPORT-5 if less.\n                                ; 'Out of screen'\n\n        RET     NZ              ; return (via CL-SET) if greater\n\n        BIT     4,(IY+$02)      ; test TV_FLAG  - Automatic listing ?\n        JR      Z,L0C88         ; forward to PO-SCR-2 if not.\n\n        LD      E,(IY+$2D)      ; fetch BREG - the count of scroll lines to E.\n        DEC     E               ; decrease and jump\n        JR      Z,L0CD2         ; to PO-SCR-3 if zero and scrolling required.\n\n        LD      A,$00           ; explicit - select channel zero.\n        CALL    L1601           ; routine CHAN-OPEN opens it.\n\n        LD      SP,($5C3F)      ; set stack pointer to LIST_SP\n\n        RES     4,(IY+$02)      ; reset TV_FLAG  - signal auto listing finished.\n        RET                     ; return ignoring pushed value, CL-SET\n                                ; to MAIN or EDITOR without updating\n                                ; print position                         >>\n\n; ---\n\n\n;; REPORT-5\nL0C86:  RST     08H             ; ERROR-1\n        DEFB    $04             ; Error Report: Out of screen\n\n; continue here if not an automatic listing.\n\n;; PO-SCR-2\nL0C88:  DEC     (IY+$52)        ; decrease SCR_CT\n        JR      NZ,L0CD2        ; forward to PO-SCR-3 to scroll display if\n                                ; result not zero.\n\n; now produce prompt.\n\n        LD      A,$18           ; reset\n        SUB     B               ; the\n        LD      ($5C8C),A       ; SCR_CT scroll count\n        LD      HL,($5C8F)      ; L=ATTR_T, H=MASK_T\n        PUSH    HL              ; save on stack\n        LD      A,($5C91)       ; P_FLAG\n        PUSH    AF              ; save on stack to prevent lower screen\n                                ; attributes (BORDCR etc.) being applied.\n        LD      A,$FD           ; select system channel 'K'\n        CALL    L1601           ; routine CHAN-OPEN opens it\n        XOR     A               ; clear to address message directly\n        LD      DE,L0CF8        ; make DE address: scrl-mssg\n        CALL    L0C0A           ; routine PO-MSG prints to lower screen\n        SET     5,(IY+$02)      ; set TV_FLAG  - signal lower screen requires\n                                ; clearing\n        LD      HL,$5C3B        ; make HL address FLAGS\n        SET     3,(HL)          ; signal 'L' mode.\n        RES     5,(HL)          ; signal 'no new key'.\n        EXX                     ; switch to main set.\n                                ; as calling chr input from alternative set.\n        CALL    L15D4           ; routine WAIT-KEY waits for new key\n                                ; Note. this is the right routine but the\n                                ; stream in use is unsatisfactory. From the\n                                ; choices available, it is however the best.\n\n        EXX                     ; switch back to alternate set.\n        CP      $20             ; space is considered as BREAK\n        JR      Z,L0D00         ; forward to REPORT-D if so\n                                ; 'BREAK - CONT repeats'\n\n        CP      $E2             ; is character 'STOP' ?\n        JR      Z,L0D00         ; forward to REPORT-D if so\n\n        OR      $20             ; convert to lower-case\n        CP      $6E             ; is character 'n' ?\n        JR      Z,L0D00         ; forward to REPORT-D if so else scroll.\n\n        LD      A,$FE           ; select system channel 'S'\n        CALL    L1601           ; routine CHAN-OPEN\n        POP     AF              ; restore original P_FLAG\n        LD      ($5C91),A       ; and save in P_FLAG.\n        POP     HL              ; restore original ATTR_T, MASK_T\n        LD      ($5C8F),HL      ; and reset ATTR_T, MASK-T as 'scroll?' has\n                                ; been printed.\n\n;; PO-SCR-3\nL0CD2:  CALL    L0DFE           ; routine CL-SC-ALL to scroll whole display\n        LD      B,(IY+$31)      ; fetch DF_SZ to B\n        INC     B               ; increase to address last line of display\n        LD      C,$21           ; set C to $21 (was $21 from above routine)\n        PUSH    BC              ; save the line and column in BC.\n\n        CALL    L0E9B           ; routine CL-ADDR finds display address.\n\n        LD      A,H             ; now find the corresponding attribute byte\n        RRCA                    ; (this code sequence is used twice\n        RRCA                    ; elsewhere and is a candidate for\n        RRCA                    ; a subroutine.)\n        AND     $03             ;\n        OR      $58             ;\n        LD      H,A             ;\n\n        LD      DE,$5AE0        ; start of last 'line' of attribute area\n        LD      A,(DE)          ; get attribute for last line\n        LD      C,(HL)          ; transfer to base line of upper part\n        LD      B,$20           ; there are thirty two bytes\n        EX      DE,HL           ; swap the pointers.\n\n;; PO-SCR-3A\nL0CF0:  LD      (DE),A          ; transfer\n        LD      (HL),C          ; attributes.\n        INC     DE              ; address next.\n        INC     HL              ; address next.\n        DJNZ    L0CF0           ; loop back to PO-SCR-3A for all adjacent\n                                ; attribute lines.\n\n        POP     BC              ; restore the line/column.\n        RET                     ; return via CL-SET (was pushed on stack).\n\n; ---\n\n; The message 'scroll?' appears here with last byte inverted.\n\n;; scrl-mssg\nL0CF8:  DEFB    $80             ; initial step-over byte.\n        DEFM    \"scroll\"\n        DEFB    '?'+$80\n\n;; REPORT-D\nL0D00:  RST     08H             ; ERROR-1\n        DEFB    $0C             ; Error Report: BREAK - CONT repeats\n\n; continue here if using lower display - A holds line number.\n\n;; PO-SCR-4\nL0D02:  CP      $02             ; is line number less than 2 ?\n        JR      C,L0C86         ; to REPORT-5 if so\n                                ; 'Out of Screen'.\n\n        ADD     A,(IY+$31)      ; add DF_SZ\n        SUB     $19             ;\n        RET     NC              ; return if scrolling unnecessary\n\n        NEG                     ; Negate to give number of scrolls required.\n        PUSH    BC              ; save line/column\n        LD      B,A             ; count to B\n        LD      HL,($5C8F)      ; fetch current ATTR_T, MASK_T to HL.\n        PUSH    HL              ; and save\n        LD      HL,($5C91)      ; fetch P_FLAG\n        PUSH    HL              ; and save.\n                                ; to prevent corruption by input AT\n\n        CALL    L0D4D           ; routine TEMPS sets to BORDCR etc\n        LD      A,B             ; transfer scroll number to A.\n\n;; PO-SCR-4A\nL0D1C:  PUSH    AF              ; save scroll number.\n        LD      HL,$5C6B        ; address DF_SZ\n        LD      B,(HL)          ; fetch old value\n        LD      A,B             ; transfer to A\n        INC     A               ; and increment\n        LD      (HL),A          ; then put back.\n        LD      HL,$5C89        ; address S_POSN_hi - line\n        CP      (HL)            ; compare\n        JR      C,L0D2D         ; forward to PO-SCR-4B if scrolling required\n\n        INC     (HL)            ; else increment S_POSN_hi\n        LD      B,$18           ; set count to whole display ??\n                                ; Note. should be $17 and the top line will be\n                                ; scrolled into the ROM which is harmless on\n                                ; the standard set up.\n                                ; credit P.Giblin 1984.\n\n;; PO-SCR-4B\nL0D2D:  CALL    L0E00           ; routine CL-SCROLL scrolls B lines\n        POP     AF              ; restore scroll counter.\n        DEC     A               ; decrease\n        JR      NZ,L0D1C        ; back to PO-SCR-4A until done\n\n        POP     HL              ; restore original P_FLAG.\n        LD      (IY+$57),L      ; and overwrite system variable P_FLAG.\n\n        POP     HL              ; restore original ATTR_T/MASK_T.\n        LD      ($5C8F),HL      ; and update system variables.\n\n        LD      BC,($5C88)      ; fetch S_POSN to BC.\n        RES     0,(IY+$02)      ; signal to TV_FLAG  - main screen in use.\n        CALL    L0DD9           ; call routine CL-SET for upper display.\n\n        SET     0,(IY+$02)      ; signal to TV_FLAG  - lower screen in use.\n        POP     BC              ; restore line/column\n        RET                     ; return via CL-SET for lower display.\n\n; ----------------------\n; Temporary colour items\n; ----------------------\n; This subroutine is called 11 times to copy the permanent colour items\n; to the temporary ones.\n\n;; TEMPS\nL0D4D:  XOR     A               ; clear the accumulator\n        LD      HL,($5C8D)      ; fetch L=ATTR_P and H=MASK_P\n        BIT     0,(IY+$02)      ; test TV_FLAG  - is lower screen in use ?\n        JR      Z,L0D5B         ; skip to TEMPS-1 if not\n\n        LD      H,A             ; set H, MASK P, to 00000000.\n        LD      L,(IY+$0E)      ; fetch BORDCR to L which is used for lower\n                                ; screen.\n\n;; TEMPS-1\nL0D5B:  LD      ($5C8F),HL      ; transfer values to ATTR_T and MASK_T\n\n; for the print flag the permanent values are odd bits, temporary even bits.\n\n        LD      HL,$5C91        ; address P_FLAG.\n        JR      NZ,L0D65        ; skip to TEMPS-2 if lower screen using A=0.\n\n        LD      A,(HL)          ; else pick up flag bits.\n        RRCA                    ; rotate permanent bits to temporary bits.\n\n;; TEMPS-2\nL0D65:  XOR     (HL)            ;\n        AND     $55             ; BIN 01010101\n        XOR     (HL)            ; permanent now as original\n        LD      (HL),A          ; apply permanent bits to temporary bits.\n        RET                     ; and return.\n\n; -----------------\n; THE 'CLS' COMMAND\n; -----------------\n;    This command clears the display.\n;    The routine is also called during initialization and by the CLEAR command.\n;    If it's difficult to write it should be difficult to read.\n\n;; CLS\nL0D6B:  CALL    L0DAF           ; Routine CL-ALL clears the entire display and\n                                ; sets the attributes to the permanent ones\n                                ; from ATTR-P.\n\n;   Having cleared all 24 lines of the display area, continue into the\n;   subroutine that clears the lower display area.  Note that at the moment\n;   the attributes for the lower lines are the same as upper ones and have\n;   to be changed to match the BORDER colour.\n\n; --------------------------\n; THE 'CLS-LOWER' SUBROUTINE\n; --------------------------\n;   This routine is called from INPUT, and from the MAIN execution loop.\n;   This is very much a housekeeping routine which clears between 2 and 23\n;   lines of the display, setting attributes and correcting situations where\n;   errors have occurred while the normal input and output routines have been\n;   temporarily diverted to deal with, say colour control codes.\n\n;; CLS-LOWER\nL0D6E:  LD      HL,$5C3C        ; address System Variable TV_FLAG.\n        RES     5,(HL)          ; TV_FLAG - signal do not clear lower screen.\n        SET     0,(HL)          ; TV_FLAG - signal lower screen in use.\n\n        CALL    L0D4D           ; routine TEMPS applies permanent attributes,\n                                ; in this case BORDCR to ATTR_T.\n                                ; Note. this seems unnecessary and is repeated\n                                ; within CL-LINE.\n\n        LD      B,(IY+$31)      ; fetch lower screen display file size DF_SZ\n\n        CALL    L0E44           ; routine CL-LINE clears lines to bottom of the\n                                ; display and sets attributes from BORDCR while\n                                ; preserving the B register.\n\n        LD      HL,$5AC0        ; set initial attribute address to the leftmost\n                                ; cell of second line up.\n\n        LD      A,($5C8D)       ; fetch permanent attribute from ATTR_P.\n\n        DEC     B               ; decrement lower screen display file size.\n\n        JR      L0D8E           ; forward to enter the backfill loop at CLS-3\n                                ; where B is decremented again.\n\n; ---\n\n;   The backfill loop is entered at midpoint and ensures, if more than 2\n;   lines have been cleared, that any other lines take the permanent screen\n;   attributes.\n\n;; CLS-1\nL0D87:  LD      C,$20           ; set counter to 32 character cells per line\n\n;; CLS-2\nL0D89:  DEC     HL              ; decrease attribute address.\n        LD      (HL),A          ; and place attributes in next line up.\n        DEC     C               ; decrease the 32 counter.\n        JR      NZ,L0D89        ; loop back to CLS-2 until all 32 cells done.\n\n;; CLS-3\nL0D8E:  DJNZ    L0D87           ; decrease B counter and back to CLS-1\n                                ; if not zero.\n\n        LD      (IY+$31),$02    ; now set DF_SZ lower screen to 2\n\n; This entry point is also called from CL-ALL below to\n; reset the system channel input and output addresses to normal.\n\n;; CL-CHAN\nL0D94:  LD      A,$FD           ; select system channel 'K'\n\n        CALL    L1601           ; routine CHAN-OPEN opens it.\n\n        LD      HL,($5C51)      ; fetch CURCHL to HL to address current channel\n        LD      DE,L09F4        ; set address to PRINT-OUT for first pass.\n        AND     A               ; clear carry for first pass.\n\n;; CL-CHAN-A\nL0DA0:  LD      (HL),E          ; Insert the output address on the first pass\n        INC     HL              ; or the input address on the second pass.\n        LD      (HL),D          ;\n        INC     HL              ;\n\n        LD      DE,L10A8        ; fetch address KEY-INPUT for second pass\n        CCF                     ; complement carry flag - will set on pass 1.\n\n        JR      C,L0DA0         ; back to CL-CHAN-A if first pass else done.\n\n        LD      BC,$1721        ; line 23 for lower screen\n        JR      L0DD9           ; exit via CL-SET to set column\n                                ; for lower display\n\n; ---------------------------\n; Clearing whole display area\n; ---------------------------\n; This subroutine called from CLS, AUTO-LIST and MAIN-3\n; clears 24 lines of the display and resets the relevant system variables.\n; This routine also recovers from an error situation where, for instance, an\n; invalid colour or position control code has left the output routine addressing\n; PO-TV-2 or PO-CONT.\n\n;; CL-ALL\nL0DAF:  LD      HL,$0000        ; Initialize plot coordinates.\n        LD      ($5C7D),HL      ; Set system variable COORDS to 0,0.\n\n        RES     0,(IY+$30)      ; update FLAGS2  - signal main screen is clear.\n\n        CALL    L0D94           ; routine CL-CHAN makes channel 'K' 'normal'.\n\n        LD      A,$FE           ; select system channel 'S'\n        CALL    L1601           ; routine CHAN-OPEN opens it.\n\n        CALL    L0D4D           ; routine TEMPS applies permanent attributes,\n                                ; in this case ATTR_P, to ATTR_T.\n                                ; Note. this seems unnecessary.\n\n        LD      B,$18           ; There are 24 lines.\n\n        CALL    L0E44           ; routine CL-LINE clears 24 text lines and sets\n                                ; attributes from ATTR-P.\n                                ; This routine preserves B and sets C to $21.\n\n        LD      HL,($5C51)      ; fetch CURCHL make HL address output routine.\n\n        LD      DE,L09F4        ; address: PRINT-OUT\n        LD      (HL),E          ; is made\n        INC     HL              ; the normal\n        LD      (HL),D          ; output address.\n\n        LD      (IY+$52),$01    ; set SCR_CT - scroll count - to default.\n\n;   Note. BC already contains $1821.\n\n        LD      BC,$1821        ; reset column and line to 0,0\n                                ; and continue into CL-SET, below, exiting\n                                ; via PO-STORE (for the upper screen).\n\n; --------------------\n; THE 'CL-SET' ROUTINE\n; --------------------\n; This important subroutine is used to calculate the character output\n; address for screens or printer based on the line/column for screens\n; or the column for printer.\n\n;; CL-SET\nL0DD9:  LD      HL,$5B00        ; the base address of printer buffer\n        BIT     1,(IY+$01)      ; test FLAGS  - is printer in use ?\n        JR      NZ,L0DF4        ; forward to CL-SET-2 if so.\n\n        LD      A,B             ; transfer line to A.\n        BIT     0,(IY+$02)      ; test TV_FLAG  - lower screen in use ?\n        JR      Z,L0DEE         ; skip to CL-SET-1 if handling upper part\n\n        ADD     A,(IY+$31)      ; add DF_SZ for lower screen\n        SUB     $18             ; and adjust.\n\n;; CL-SET-1\nL0DEE:  PUSH    BC              ; save the line/column.\n        LD      B,A             ; transfer line to B\n                                ; (adjusted if lower screen)\n\n        CALL    L0E9B           ; routine CL-ADDR calculates address at left\n                                ; of screen.\n        POP     BC              ; restore the line/column.\n\n;; CL-SET-2\nL0DF4:  LD      A,$21           ; the column $01-$21 is reversed\n        SUB     C               ; to range $00 - $20\n        LD      E,A             ; now transfer to DE\n        LD      D,$00           ; prepare for addition\n        ADD     HL,DE           ; and add to base address\n\n        JP      L0ADC           ; exit via PO-STORE to update the relevant\n                                ; system variables.\n; ----------------\n; Handle scrolling\n; ----------------\n; The routine CL-SC-ALL is called once from PO to scroll all the display\n; and from the routine CL-SCROLL, once, to scroll part of the display.\n\n;; CL-SC-ALL\nL0DFE:  LD      B,$17           ; scroll 23 lines, after 'scroll?'.\n\n;; CL-SCROLL\nL0E00:  CALL    L0E9B           ; routine CL-ADDR gets screen address in HL.\n        LD      C,$08           ; there are 8 pixel lines to scroll.\n\n;; CL-SCR-1\nL0E05:  PUSH    BC              ; save counters.\n        PUSH    HL              ; and initial address.\n        LD      A,B             ; get line count.\n        AND     $07             ; will set zero if all third to be scrolled.\n        LD      A,B             ; re-fetch the line count.\n        JR      NZ,L0E19        ; forward to CL-SCR-3 if partial scroll.\n\n; HL points to top line of third and must be copied to bottom of previous 3rd.\n; ( so HL = $4800 or $5000 ) ( but also sometimes $4000 )\n\n;; CL-SCR-2\nL0E0D:  EX      DE,HL           ; copy HL to DE.\n        LD      HL,$F8E0        ; subtract $08 from H and add $E0 to L -\n        ADD     HL,DE           ; to make destination bottom line of previous\n                                ; third.\n        EX      DE,HL           ; restore the source and destination.\n        LD      BC,$0020        ; thirty-two bytes are to be copied.\n        DEC     A               ; decrement the line count.\n        LDIR                    ; copy a pixel line to previous third.\n\n;; CL-SCR-3\nL0E19:  EX      DE,HL           ; save source in DE.\n        LD      HL,$FFE0        ; load the value -32.\n        ADD     HL,DE           ; add to form destination in HL.\n        EX      DE,HL           ; switch source and destination\n        LD      B,A             ; save the count in B.\n        AND     $07             ; mask to find count applicable to current\n        RRCA                    ; third and\n        RRCA                    ; multiply by\n        RRCA                    ; thirty two (same as 5 RLCAs)\n\n        LD      C,A             ; transfer byte count to C ($E0 at most)\n        LD      A,B             ; store line count to A\n        LD      B,$00           ; make B zero\n        LDIR                    ; copy bytes (BC=0, H incremented, L=0)\n        LD      B,$07           ; set B to 7, C is zero.\n        ADD     HL,BC           ; add 7 to H to address next third.\n        AND     $F8             ; has last third been done ?\n        JR      NZ,L0E0D        ; back to CL-SCR-2 if not.\n\n        POP     HL              ; restore topmost address.\n        INC     H               ; next pixel line down.\n        POP     BC              ; restore counts.\n        DEC     C               ; reduce pixel line count.\n        JR      NZ,L0E05        ; back to CL-SCR-1 if all eight not done.\n\n        CALL    L0E88           ; routine CL-ATTR gets address in attributes\n                                ; from current 'ninth line', count in BC.\n\n        LD      HL,$FFE0        ; set HL to the 16-bit value -32.\n        ADD     HL,DE           ; and add to form destination address.\n        EX      DE,HL           ; swap source and destination addresses.\n        LDIR                    ; copy bytes scrolling the linear attributes.\n        LD      B,$01           ; continue to clear the bottom line.\n\n; ------------------------------\n; THE 'CLEAR TEXT LINES' ROUTINE\n; ------------------------------\n; This subroutine, called from CL-ALL, CLS-LOWER and AUTO-LIST and above,\n; clears text lines at bottom of display.\n; The B register holds on entry the number of lines to be cleared 1-24.\n\n;; CL-LINE\nL0E44:  PUSH    BC              ; save line count\n        CALL    L0E9B           ; routine CL-ADDR gets top address\n        LD      C,$08           ; there are eight screen lines to a text line.\n\n;; CL-LINE-1\nL0E4A:  PUSH    BC              ; save pixel line count\n        PUSH    HL              ; and save the address\n        LD      A,B             ; transfer the line to A (1-24).\n\n;; CL-LINE-2\nL0E4D:  AND     $07             ; mask 0-7 to consider thirds at a time\n        RRCA                    ; multiply\n        RRCA                    ; by 32  (same as five RLCA instructions)\n        RRCA                    ; now 32 - 256(0)\n        LD      C,A             ; store result in C\n        LD      A,B             ; save line in A (1-24)\n        LD      B,$00           ; set high byte to 0, prepare for ldir.\n        DEC     C               ; decrement count 31-255.\n        LD      D,H             ; copy HL\n        LD      E,L             ; to DE.\n        LD      (HL),$00        ; blank the first byte.\n        INC     DE              ; make DE point to next byte.\n        LDIR                    ; ldir will clear lines.\n        LD      DE,$0701        ; now address next third adjusting\n        ADD     HL,DE           ; register E to address left hand side\n        DEC     A               ; decrease the line count.\n        AND     $F8             ; will be 16, 8 or 0  (AND $18 will do).\n        LD      B,A             ; transfer count to B.\n        JR      NZ,L0E4D        ; back to CL-LINE-2 if 16 or 8 to do\n                                ; the next third.\n\n        POP     HL              ; restore start address.\n        INC     H               ; address next line down.\n        POP     BC              ; fetch counts.\n        DEC     C               ; decrement pixel line count\n        JR      NZ,L0E4A        ; back to CL-LINE-1 till all done.\n\n        CALL    L0E88           ; routine CL-ATTR gets attribute address\n                                ; in DE and B * 32 in BC.\n\n        LD      H,D             ; transfer the address\n        LD      L,E             ; to HL.\n\n        INC     DE              ; make DE point to next location.\n\n        LD      A,($5C8D)       ; fetch ATTR_P - permanent attributes\n        BIT     0,(IY+$02)      ; test TV_FLAG  - lower screen in use ?\n        JR      Z,L0E80         ; skip to CL-LINE-3 if not.\n\n        LD      A,($5C48)       ; else lower screen uses BORDCR as attribute.\n\n;; CL-LINE-3\nL0E80:  LD      (HL),A          ; put attribute in first byte.\n        DEC     BC              ; decrement the counter.\n        LDIR                    ; copy bytes to set all attributes.\n        POP     BC              ; restore the line $01-$24.\n        LD      C,$21           ; make column $21. (No use is made of this)\n        RET                     ; return to the calling routine.\n\n; ------------------\n; Attribute handling\n; ------------------\n; This subroutine is called from CL-LINE or CL-SCROLL with the HL register\n; pointing to the 'ninth' line and H needs to be decremented before or after\n; the division. Had it been done first then either present code or that used\n; at the start of PO-ATTR could have been used.\n; The Spectrum screen arrangement leads to the L register already holding\n; the correct value for the attribute file and it is only necessary\n; to manipulate H to form the correct colour attribute address.\n\n;; CL-ATTR\nL0E88:  LD      A,H             ; fetch H to A - $48, $50, or $58.\n        RRCA                    ; divide by\n        RRCA                    ; eight.\n        RRCA                    ; $09, $0A or $0B.\n        DEC     A               ; $08, $09 or $0A.\n        OR      $50             ; $58, $59 or $5A.\n        LD      H,A             ; save high byte of attributes.\n\n        EX      DE,HL           ; transfer attribute address to DE\n        LD      H,C             ; set H to zero - from last LDIR.\n        LD      L,B             ; load L with the line from B.\n        ADD     HL,HL           ; multiply\n        ADD     HL,HL           ; by\n        ADD     HL,HL           ; thirty two\n        ADD     HL,HL           ; to give count of attribute\n        ADD     HL,HL           ; cells to the end of display.\n\n        LD      B,H             ; transfer the result\n        LD      C,L             ; to register BC.\n\n        RET                     ; return.\n\n; -------------------------------\n; Handle display with line number\n; -------------------------------\n; This subroutine is called from four places to calculate the address\n; of the start of a screen character line which is supplied in B.\n\n;; CL-ADDR\nL0E9B:  LD      A,$18           ; reverse the line number\n        SUB     B               ; to range $00 - $17.\n        LD      D,A             ; save line in D for later.\n        RRCA                    ; multiply\n        RRCA                    ; by\n        RRCA                    ; thirty-two.\n\n        AND     $E0             ; mask off low bits to make\n        LD      L,A             ; L a multiple of 32.\n\n        LD      A,D             ; bring back the line to A.\n\n        AND     $18             ; now $00, $08 or $10.\n\n        OR      $40             ; add the base address of screen.\n\n        LD      H,A             ; HL now has the correct address.\n        RET                     ; return.\n\n; -------------------\n; Handle COPY command\n; -------------------\n; This command copies the top 176 lines to the ZX Printer\n; It is popular to call this from machine code at point\n; L0EAF with B holding 192 (and interrupts disabled) for a full-screen\n; copy. This particularly applies to 16K Spectrums as time-critical\n; machine code routines cannot be written in the first 16K of RAM as\n; it is shared with the ULA which has precedence over the Z80 chip.\n\n;; COPY\nL0EAC:  DI                      ; disable interrupts as this is time-critical.\n\n        LD      B,$B0           ; top 176 lines.\nL0EAF:  LD      HL,$4000        ; address start of the display file.\n\n; now enter a loop to handle each pixel line.\n\n;; COPY-1\nL0EB2:  PUSH    HL              ; save the screen address.\n        PUSH    BC              ; and the line counter.\n\n        CALL    L0EF4           ; routine COPY-LINE outputs one line.\n\n        POP     BC              ; restore the line counter.\n        POP     HL              ; and display address.\n        INC     H               ; next line down screen within 'thirds'.\n        LD      A,H             ; high byte to A.\n        AND     $07             ; result will be zero if we have left third.\n        JR      NZ,L0EC9        ; forward to COPY-2 if not to continue loop.\n\n        LD      A,L             ; consider low byte first.\n        ADD     A,$20           ; increase by 32 - sets carry if back to zero.\n        LD      L,A             ; will be next group of 8.\n        CCF                     ; complement - carry set if more lines in\n                                ; the previous third.\n        SBC     A,A             ; will be FF, if more, else 00.\n        AND     $F8             ; will be F8 (-8) or 00.\n        ADD     A,H             ; that is subtract 8, if more to do in third.\n        LD      H,A             ; and reset address.\n\n;; COPY-2\nL0EC9:  DJNZ    L0EB2           ; back to COPY-1 for all lines.\n\n        JR      L0EDA           ; forward to COPY-END to switch off the printer\n                                ; motor and enable interrupts.\n                                ; Note. Nothing else is required.\n\n; ------------------------------\n; Pass printer buffer to printer\n; ------------------------------\n; This routine is used to copy 8 text lines from the printer buffer\n; to the ZX Printer. These text lines are mapped linearly so HL does\n; not need to be adjusted at the end of each line.\n\n;; COPY-BUFF\nL0ECD:  DI                      ; disable interrupts\n        LD      HL,$5B00        ; the base address of the Printer Buffer.\n        LD      B,$08           ; set count to 8 lines of 32 bytes.\n\n;; COPY-3\nL0ED3:  PUSH    BC              ; save counter.\n\n        CALL    L0EF4           ; routine COPY-LINE outputs 32 bytes\n\n        POP     BC              ; restore counter.\n        DJNZ    L0ED3           ; loop back to COPY-3 for all 8 lines.\n                                ; then stop motor and clear buffer.\n\n; Note. the COPY command rejoins here, essentially to execute the next\n; three instructions.\n\n;; COPY-END\nL0EDA:  LD      A,$04           ; output value 4 to port\n        OUT     ($FB),A         ; to stop the slowed printer motor.\n        EI                      ; enable interrupts.\n\n; --------------------\n; Clear Printer Buffer\n; --------------------\n; This routine clears an arbitrary 256 bytes of memory.\n; Note. The routine seems designed to clear a buffer that follows the\n; system variables.\n; The routine should check a flag or HL address and simply return if COPY\n; is in use.\n; As a consequence of this omission the buffer will needlessly\n; be cleared when COPY is used and the screen/printer position may be set to\n; the start of the buffer and the line number to 0 (B)\n; giving an 'Out of Screen' error.\n; There seems to have been an unsuccessful attempt to circumvent the use\n; of PR_CC_hi.\n\n;; CLEAR-PRB\nL0EDF:  LD      HL,$5B00        ; the location of the buffer.\n        LD      (IY+$46),L      ; update PR_CC_lo - set to zero - superfluous.\n        XOR     A               ; clear the accumulator.\n        LD      B,A             ; set count to 256 bytes.\n\n;; PRB-BYTES\nL0EE7:  LD      (HL),A          ; set addressed location to zero.\n        INC     HL              ; address next byte - Note. not INC L.\n        DJNZ    L0EE7           ; back to PRB-BYTES. repeat for 256 bytes.\n\n        RES     1,(IY+$30)      ; set FLAGS2 - signal printer buffer is clear.\n        LD      C,$21           ; set the column position .\n        JP      L0DD9           ; exit via CL-SET and then PO-STORE.\n\n; -----------------\n; Copy line routine\n; -----------------\n; This routine is called from COPY and COPY-BUFF to output a line of\n; 32 bytes to the ZX Printer.\n; Output to port $FB -\n; bit 7 set - activate stylus.\n; bit 7 low - deactivate stylus.\n; bit 2 set - stops printer.\n; bit 2 reset - starts printer\n; bit 1 set - slows printer.\n; bit 1 reset - normal speed.\n\n;; COPY-LINE\nL0EF4:  LD      A,B             ; fetch the counter 1-8 or 1-176\n        CP      $03             ; is it 01 or 02 ?.\n        SBC     A,A             ; result is $FF if so else $00.\n        AND     $02             ; result is 02 now else 00.\n                                ; bit 1 set slows the printer.\n        OUT     ($FB),A         ; slow the printer for the\n                                ; last two lines.\n        LD      D,A             ; save the mask to control the printer later.\n\n;; COPY-L-1\nL0EFD:  CALL    L1F54           ; call BREAK-KEY to read keyboard immediately.\n        JR      C,L0F0C         ; forward to COPY-L-2 if 'break' not pressed.\n\n        LD      A,$04           ; else stop the\n        OUT     ($FB),A         ; printer motor.\n        EI                      ; enable interrupts.\n        CALL    L0EDF           ; call routine CLEAR-PRB.\n                                ; Note. should not be cleared if COPY in use.\n\n;; REPORT-Dc\nL0F0A:  RST     08H             ; ERROR-1\n        DEFB    $0C             ; Error Report: BREAK - CONT repeats\n\n;; COPY-L-2\nL0F0C:  IN      A,($FB)         ; test now to see if\n        ADD     A,A             ; a printer is attached.\n        RET     M               ; return if not - but continue with parent\n                                ; command.\n\n        JR      NC,L0EFD        ; back to COPY-L-1 if stylus of printer not\n                                ; in position.\n\n        LD      C,$20           ; set count to 32 bytes.\n\n;; COPY-L-3\nL0F14:  LD      E,(HL)          ; fetch a byte from line.\n        INC     HL              ; address next location. Note. not INC L.\n        LD      B,$08           ; count the bits.\n\n;; COPY-L-4\nL0F18:  RL      D               ; prepare mask to receive bit.\n        RL      E               ; rotate leftmost print bit to carry\n        RR      D               ; and back to bit 7 of D restoring bit 1\n\n;; COPY-L-5\nL0F1E:  IN      A,($FB)         ; read the port.\n        RRA                     ; bit 0 to carry.\n        JR      NC,L0F1E        ; back to COPY-L-5 if stylus not in position.\n\n        LD      A,D             ; transfer command bits to A.\n        OUT     ($FB),A         ; and output to port.\n        DJNZ    L0F18           ; loop back to COPY-L-4 for all 8 bits.\n\n        DEC     C               ; decrease the byte count.\n        JR      NZ,L0F14        ; back to COPY-L-3 until 256 bits done.\n\n        RET                     ; return to calling routine COPY/COPY-BUFF.\n\n\n; ----------------------------------\n; Editor routine for BASIC and INPUT\n; ----------------------------------\n; The editor is called to prepare or edit a BASIC line.\n; It is also called from INPUT to input a numeric or string expression.\n; The behaviour and options are quite different in the various modes\n; and distinguished by bit 5 of FLAGX.\n;\n; This is a compact and highly versatile routine.\n\n;; EDITOR\nL0F2C:  LD      HL,($5C3D)      ; fetch ERR_SP\n        PUSH    HL              ; save on stack\n\n;; ED-AGAIN\nL0F30:  LD      HL,L107F        ; address: ED-ERROR\n        PUSH    HL              ; save address on stack and\n        LD      ($5C3D),SP      ; make ERR_SP point to it.\n\n; Note. While in editing/input mode should an error occur then RST 08 will\n; update X_PTR to the location reached by CH_ADD and jump to ED-ERROR\n; where the error will be cancelled and the loop begin again from ED-AGAIN\n; above. The position of the error will be apparent when the lower screen is\n; reprinted. If no error then the re-iteration is to ED-LOOP below when\n; input is arriving from the keyboard.\n\n;; ED-LOOP\nL0F38:  CALL    L15D4           ; routine WAIT-KEY gets key possibly\n                                ; changing the mode.\n        PUSH    AF              ; save key.\n        LD      D,$00           ; and give a short click based\n        LD      E,(IY-$01)      ; on PIP value for duration.\n        LD      HL,$00C8        ; and pitch.\n        CALL    L03B5           ; routine BEEPER gives click - effective\n                                ; with rubber keyboard.\n        POP     AF              ; get saved key value.\n        LD      HL,L0F38        ; address: ED-LOOP is loaded to HL.\n        PUSH    HL              ; and pushed onto stack.\n\n; At this point there is a looping return address on the stack, an error\n; handler and an input stream set up to supply characters.\n; The character that has been received can now be processed.\n\n        CP      $18             ; range 24 to 255 ?\n        JR      NC,L0F81        ; forward to ADD-CHAR if so.\n\n        CP      $07             ; lower than 7 ?\n        JR      C,L0F81         ; forward to ADD-CHAR also.\n                                ; Note. This is a 'bug' and chr$ 6, the comma\n                                ; control character, should have had an\n                                ; entry in the ED-KEYS table.\n                                ; Steven Vickers, 1984, Pitman.\n\n        CP      $10             ; less than 16 ?\n        JR      C,L0F92         ; forward to ED-KEYS if editing control\n                                ; range 7 to 15 dealt with by a table\n\n        LD      BC,$0002        ; prepare for ink/paper etc.\n        LD      D,A             ; save character in D\n        CP      $16             ; is it ink/paper/bright etc. ?\n        JR      C,L0F6C         ; forward to ED-CONTR if so\n\n                                ; leaves 22d AT and 23d TAB\n                                ; which can't be entered via KEY-INPUT.\n                                ; so this code is never normally executed\n                                ; when the keyboard is used for input.\n\n        INC     BC              ; if it was AT/TAB - 3 locations required\n        BIT     7,(IY+$37)      ; test FLAGX  - Is this INPUT LINE ?\n        JP      Z,L101E         ; jump to ED-IGNORE if not, else\n\n        CALL    L15D4           ; routine WAIT-KEY - input address is KEY-NEXT\n                                ; but is reset to KEY-INPUT\n        LD      E,A             ; save first in E\n\n;; ED-CONTR\nL0F6C:  CALL    L15D4           ; routine WAIT-KEY for control.\n                                ; input address will be key-next.\n\n        PUSH    DE              ; saved code/parameters\n        LD      HL,($5C5B)      ; fetch address of keyboard cursor from K_CUR\n        RES     0,(IY+$07)      ; set MODE to 'L'\n\n        CALL    L1655           ; routine MAKE-ROOM makes 2/3 spaces at cursor\n\n        POP     BC              ; restore code/parameters\n        INC     HL              ; address first location\n        LD      (HL),B          ; place code (ink etc.)\n        INC     HL              ; address next\n        LD      (HL),C          ; place possible parameter. If only one\n                                ; then DE points to this location also.\n        JR      L0F8B           ; forward to ADD-CH-1\n\n; ------------------------\n; Add code to current line\n; ------------------------\n; this is the branch used to add normal non-control characters\n; with ED-LOOP as the stacked return address.\n; it is also the OUTPUT service routine for system channel 'R'.\n\n;; ADD-CHAR\nL0F81:  RES     0,(IY+$07)      ; set MODE to 'L'\n\nX0F85:  LD      HL,($5C5B)      ; fetch address of keyboard cursor from K_CUR\n\n        CALL    L1652           ; routine ONE-SPACE creates one space.\n\n; either a continuation of above or from ED-CONTR with ED-LOOP on stack.\n\n;; ADD-CH-1\nL0F8B:  LD      (DE),A          ; load current character to last new location.\n        INC     DE              ; address next\n        LD      ($5C5B),DE      ; and update K_CUR system variable.\n        RET                     ; return - either a simple return\n                                ; from ADD-CHAR or to ED-LOOP on stack.\n\n; ---\n\n; a branch of the editing loop to deal with control characters\n; using a look-up table.\n\n;; ED-KEYS\nL0F92:  LD      E,A             ; character to E.\n        LD      D,$00           ; prepare to add.\n        LD      HL,L0FA0 - 7    ; base address of editing keys table. $0F99\n        ADD     HL,DE           ; add E\n        LD      E,(HL)          ; fetch offset to E\n        ADD     HL,DE           ; add offset for address of handling routine.\n        PUSH    HL              ; push the address on machine stack.\n        LD      HL,($5C5B)      ; load address of cursor from K_CUR.\n        RET                     ; Make an indirect jump forward to routine.\n\n; ------------------\n; Editing keys table\n; ------------------\n; For each code in the range $07 to $0F this table contains a\n; single offset byte to the routine that services that code.\n; Note. for what was intended there should also have been an\n; entry for chr$ 6 with offset to ed-symbol.\n\n;; ed-keys-t\nL0FA0:  DEFB    L0FA9 - $  ; 07d offset $09 to Address: ED-EDIT\n        DEFB    L1007 - $  ; 08d offset $66 to Address: ED-LEFT\n        DEFB    L100C - $  ; 09d offset $6A to Address: ED-RIGHT\n        DEFB    L0FF3 - $  ; 10d offset $50 to Address: ED-DOWN\n        DEFB    L1059 - $  ; 11d offset $B5 to Address: ED-UP\n        DEFB    L1015 - $  ; 12d offset $70 to Address: ED-DELETE\n        DEFB    L1024 - $  ; 13d offset $7E to Address: ED-ENTER\n        DEFB    L1076 - $  ; 14d offset $CF to Address: ED-SYMBOL\n        DEFB    L107C - $  ; 15d offset $D4 to Address: ED-GRAPH\n\n; ---------------\n; Handle EDIT key\n; ---------------\n; The user has pressed SHIFT 1 to bring edit line down to bottom of screen.\n; Alternatively the user wishes to clear the input buffer and start again.\n; Alternatively ...\n\n;; ED-EDIT\nL0FA9:  LD      HL,($5C49)      ; fetch E_PPC the last line number entered.\n                                ; Note. may not exist and may follow program.\n        BIT     5,(IY+$37)      ; test FLAGX  - input mode ?\n        JP      NZ,L1097        ; jump forward to CLEAR-SP if not in editor.\n\n        CALL    L196E           ; routine LINE-ADDR to find address of line\n                                ; or following line if it doesn't exist.\n        CALL    L1695           ; routine LINE-NO will get line number from\n                                ; address or previous line if at end-marker.\n        LD      A,D             ; if there is no program then DE will\n        OR      E               ; contain zero so test for this.\n        JP      Z,L1097         ; jump to CLEAR-SP if so.\n\n; Note. at this point we have a validated line number, not just an\n; approximation and it would be best to update E_PPC with the true\n; cursor line value which would enable the line cursor to be suppressed\n; in all situations - see shortly.\n\n        PUSH    HL              ; save address of line.\n        INC     HL              ; address low byte of length.\n        LD      C,(HL)          ; transfer to C\n        INC     HL              ; next to high byte\n        LD      B,(HL)          ; transfer to B.\n        LD      HL,$000A        ; an overhead of ten bytes\n        ADD     HL,BC           ; is added to length.\n        LD      B,H             ; transfer adjusted value\n        LD      C,L             ; to BC register.\n        CALL    L1F05           ; routine TEST-ROOM checks free memory.\n        CALL    L1097           ; routine CLEAR-SP clears editing area.\n        LD      HL,($5C51)      ; address CURCHL\n        EX      (SP),HL         ; swap with line address on stack\n        PUSH    HL              ; save line address underneath\n\n        LD      A,$FF           ; select system channel 'R'\n        CALL    L1601           ; routine CHAN-OPEN opens it\n\n        POP     HL              ; drop line address\n        DEC     HL              ; make it point to first byte of line num.\n        DEC     (IY+$0F)        ; decrease E_PPC_lo to suppress line cursor.\n                                ; Note. ineffective when E_PPC is one\n                                ; greater than last line of program perhaps\n                                ; as a result of a delete.\n                                ; credit. Paul Harrison 1982.\n\n        CALL    L1855           ; routine OUT-LINE outputs the BASIC line\n                                ; to the editing area.\n        INC     (IY+$0F)        ; restore E_PPC_lo to the previous value.\n        LD      HL,($5C59)      ; address E_LINE in editing area.\n        INC     HL              ; advance\n        INC     HL              ; past space\n        INC     HL              ; and digit characters\n        INC     HL              ; of line number.\n\n        LD      ($5C5B),HL      ; update K_CUR to address start of BASIC.\n        POP     HL              ; restore the address of CURCHL.\n        CALL    L1615           ; routine CHAN-FLAG sets flags for it.\n\n        RET                     ; RETURN to ED-LOOP.\n\n; -------------------\n; Cursor down editing\n; -------------------\n;   The BASIC lines are displayed at the top of the screen and the user\n;   wishes to move the cursor down one line in edit mode.\n;   With INPUT LINE, this key must be used instead of entering STOP.\n\n;; ED-DOWN\nL0FF3:  BIT     5,(IY+$37)      ; test FLAGX  - Input Mode ?\n        JR      NZ,L1001        ; skip to ED-STOP if so\n\n        LD      HL,$5C49        ; address E_PPC - 'current line'\n        CALL    L190F           ; routine LN-FETCH fetches number of next\n                                ; line or same if at end of program.\n        JR      L106E           ; forward to ED-LIST to produce an\n                                ; automatic listing.\n\n; ---\n\n;; ED-STOP\nL1001:  LD      (IY+$00),$10    ; set ERR_NR to 'STOP in INPUT' code\n        JR      L1024           ; forward to ED-ENTER to produce error.\n\n; -------------------\n; Cursor left editing\n; -------------------\n; This acts on the cursor in the lower section of the screen in both\n; editing and input mode.\n\n;; ED-LEFT\nL1007:  CALL    L1031           ; routine ED-EDGE moves left if possible\n        JR      L1011           ; forward to ED-CUR to update K-CUR\n                                ; and return to ED-LOOP.\n\n; --------------------\n; Cursor right editing\n; --------------------\n; This acts on the cursor in the lower screen in both editing and input\n; mode and moves it to the right.\n\n;; ED-RIGHT\nL100C:  LD      A,(HL)          ; fetch addressed character.\n        CP      $0D             ; is it carriage return ?\n        RET     Z               ; return if so to ED-LOOP\n\n        INC     HL              ; address next character\n\n;; ED-CUR\nL1011:  LD      ($5C5B),HL      ; update K_CUR system variable\n        RET                     ; return to ED-LOOP\n\n; --------------\n; DELETE editing\n; --------------\n; This acts on the lower screen and deletes the character to left of\n; cursor. If control characters are present these are deleted first\n; leaving the naked parameter (0-7) which appears as a '?' except in the\n; case of chr$ 6 which is the comma control character. It is not mandatory\n; to delete these second characters.\n\n;; ED-DELETE\nL1015:  CALL    L1031           ; routine ED-EDGE moves cursor to left.\n        LD      BC,$0001        ; of character to be deleted.\n        JP      L19E8           ; to RECLAIM-2 reclaim the character.\n\n; ------------------------------------------\n; Ignore next 2 codes from key-input routine\n; ------------------------------------------\n; Since AT and TAB cannot be entered this point is never reached\n; from the keyboard. If inputting from a tape device or network then\n; the control and two following characters are ignored and processing\n; continues as if a carriage return had been received.\n; Here, perhaps, another Spectrum has said print #15; AT 0,0; \"This is yellow\"\n; and this one is interpreting input #15; a$.\n\n;; ED-IGNORE\nL101E:  CALL    L15D4           ; routine WAIT-KEY to ignore keystroke.\n        CALL    L15D4           ; routine WAIT-KEY to ignore next key.\n\n; -------------\n; Enter/newline\n; -------------\n; The enter key has been pressed to have BASIC line or input accepted.\n\n;; ED-ENTER\nL1024:  POP     HL              ; discard address ED-LOOP\n        POP     HL              ; drop address ED-ERROR\n\n;; ED-END\nL1026:  POP     HL              ; the previous value of ERR_SP\n        LD      ($5C3D),HL      ; is restored to ERR_SP system variable\n        BIT     7,(IY+$00)      ; is ERR_NR $FF (= 'OK') ?\n        RET     NZ              ; return if so\n\n        LD      SP,HL           ; else put error routine on stack\n        RET                     ; and make an indirect jump to it.\n\n; -----------------------------\n; Move cursor left when editing\n; -----------------------------\n; This routine moves the cursor left. The complication is that it must\n; not position the cursor between control codes and their parameters.\n; It is further complicated in that it deals with TAB and AT characters\n; which are never present from the keyboard.\n; The method is to advance from the beginning of the line each time,\n; jumping one, two, or three characters as necessary saving the original\n; position at each jump in DE. Once it arrives at the cursor then the next\n; legitimate leftmost position is in DE.\n\n;; ED-EDGE\nL1031:  SCF                     ; carry flag must be set to call the nested\n        CALL    L1195           ; subroutine SET-DE.\n                                ; if input   then DE=WORKSP\n                                ; if editing then DE=E_LINE\n        SBC     HL,DE           ; subtract address from start of line\n        ADD     HL,DE           ; and add back.\n        INC     HL              ; adjust for carry.\n        POP     BC              ; drop return address\n        RET     C               ; return to ED-LOOP if already at left\n                                ; of line.\n\n        PUSH    BC              ; resave return address - ED-LOOP.\n        LD      B,H             ; transfer HL - cursor address\n        LD      C,L             ; to BC register pair.\n                                ; at this point DE addresses start of line.\n\n;; ED-EDGE-1\nL103E:  LD      H,D             ; transfer DE - leftmost pointer\n        LD      L,E             ; to HL\n        INC     HL              ; address next leftmost character to\n                                ; advance position each time.\n        LD      A,(DE)          ; pick up previous in A\n        AND     $F0             ; lose the low bits\n        CP      $10             ; is it INK to TAB $10-$1F ?\n                                ; that is, is it followed by a parameter ?\n        JR      NZ,L1051        ; to ED-EDGE-2 if not\n                                ; HL has been incremented once\n\n        INC     HL              ; address next as at least one parameter.\n\n; in fact since 'tab' and 'at' cannot be entered the next section seems\n; superfluous.\n; The test will always fail and the jump to ED-EDGE-2 will be taken.\n\n        LD      A,(DE)          ; reload leftmost character\n        SUB     $17             ; decimal 23 ('tab')\n        ADC     A,$00           ; will be 0 for 'tab' and 'at'.\n        JR      NZ,L1051        ; forward to ED-EDGE-2 if not\n                                ; HL has been incremented twice\n\n        INC     HL              ; increment a third time for 'at'/'tab'\n\n;; ED-EDGE-2\nL1051:  AND     A               ; prepare for true subtraction\n        SBC     HL,BC           ; subtract cursor address from pointer\n        ADD     HL,BC           ; and add back\n                                ; Note when HL matches the cursor position BC,\n                                ; there is no carry and the previous\n                                ; position is in DE.\n        EX      DE,HL           ; transfer result to DE if looping again.\n                                ; transfer DE to HL to be used as K-CUR\n                                ; if exiting loop.\n        JR      C,L103E         ; back to ED-EDGE-1 if cursor not matched.\n\n        RET                     ; return.\n\n; -----------------\n; Cursor up editing\n; -----------------\n; The main screen displays part of the BASIC program and the user wishes\n; to move up one line scrolling if necessary.\n; This has no alternative use in input mode.\n\n;; ED-UP\nL1059:  BIT     5,(IY+$37)      ; test FLAGX  - input mode ?\n        RET     NZ              ; return if not in editor - to ED-LOOP.\n\n        LD      HL,($5C49)      ; get current line from E_PPC\n        CALL    L196E           ; routine LINE-ADDR gets address\n        EX      DE,HL           ; and previous in DE\n        CALL    L1695           ; routine LINE-NO gets prev line number\n        LD      HL,$5C4A        ; set HL to E_PPC_hi as next routine stores\n                                ; top first.\n        CALL    L191C           ; routine LN-STORE loads DE value to HL\n                                ; high byte first - E_PPC_lo takes E\n\n; this branch is also taken from ed-down.\n\n;; ED-LIST\nL106E:  CALL    L1795           ; routine AUTO-LIST lists to upper screen\n                                ; including adjusted current line.\n        LD      A,$00           ; select lower screen again\n        JP      L1601           ; exit via CHAN-OPEN to ED-LOOP\n\n; --------------------------------\n; Use of symbol and graphics codes\n; --------------------------------\n; These will not be encountered with the keyboard but would be handled\n; otherwise as follows.\n; As noted earlier, Vickers says there should have been an entry in\n; the KEYS table for chr$ 6 which also pointed here.\n; If, for simplicity, two Spectrums were both using #15 as a bi-directional\n; channel connected to each other:-\n; then when the other Spectrum has said PRINT #15; x, y\n; input #15; i ; j  would treat the comma control as a newline and the\n; control would skip to input j.\n; You can get round the missing chr$ 6 handler by sending multiple print\n; items separated by a newline '.\n\n; chr$14 would have the same functionality.\n\n; This is chr$ 14.\n;; ED-SYMBOL\nL1076:  BIT     7,(IY+$37)      ; test FLAGX - is this INPUT LINE ?\n        JR      Z,L1024         ; back to ED-ENTER if not to treat as if\n                                ; enter had been pressed.\n                                ; else continue and add code to buffer.\n\n; Next is chr$ 15\n; Note that ADD-CHAR precedes the table so we can't offset to it directly.\n\n;; ED-GRAPH\nL107C:  JP      L0F81           ; jump back to ADD-CHAR\n\n; --------------------\n; Editor error routine\n; --------------------\n; If an error occurs while editing, or inputting, then ERR_SP\n; points to the stack location holding address ED_ERROR.\n\n;; ED-ERROR\nL107F:  BIT     4,(IY+$30)      ; test FLAGS2  - is K channel in use ?\n        JR      Z,L1026         ; back to ED-END if not.\n\n; but as long as we're editing lines or inputting from the keyboard, then\n; we've run out of memory so give a short rasp.\n\n        LD      (IY+$00),$FF    ; reset ERR_NR to 'OK'.\n        LD      D,$00           ; prepare for beeper.\n        LD      E,(IY-$02)      ; use RASP value.\n        LD      HL,$1A90        ; set the pitch - or tone period.\n        CALL    L03B5           ; routine BEEPER emits a warning rasp.\n        JP      L0F30           ; to ED-AGAIN to re-stack address of\n                                ; this routine and make ERR_SP point to it.\n\n; ---------------------\n; Clear edit/work space\n; ---------------------\n; The editing area or workspace is cleared depending on context.\n; This is called from ED-EDIT to clear workspace if edit key is\n; used during input, to clear editing area if no program exists\n; and to clear editing area prior to copying the edit line to it.\n; It is also used by the error routine to clear the respective\n; area depending on FLAGX.\n\n;; CLEAR-SP\nL1097:  PUSH    HL              ; preserve HL\n        CALL    L1190           ; routine SET-HL\n                                ; if in edit   HL = WORKSP-1, DE = E_LINE\n                                ; if in input  HL = STKBOT,   DE = WORKSP\n        DEC     HL              ; adjust\n        CALL    L19E5           ; routine RECLAIM-1 reclaims space\n        LD      ($5C5B),HL      ; set K_CUR to start of empty area\n        LD      (IY+$07),$00    ; set MODE to 'KLC'\n        POP     HL              ; restore HL.\n        RET                     ; return.\n\n; ----------------------------\n; THE 'KEYBOARD INPUT' ROUTINE\n; ----------------------------\n; This is the service routine for the input stream of the keyboard channel 'K'.\n\n;; KEY-INPUT\nL10A8:  BIT     3,(IY+$02)      ; test TV_FLAG  - has a key been pressed in\n                                ; editor ?\n\n        CALL    NZ,L111D        ; routine ED-COPY, if so, to reprint the lower\n                                ; screen at every keystroke/mode change.\n\n        AND     A               ; clear carry flag - required exit condition.\n\n        BIT     5,(IY+$01)      ; test FLAGS  - has a new key been pressed ?\n        RET     Z               ; return if not.                        >>\n\n        LD      A,($5C08)       ; system variable LASTK will hold last key -\n                                ; from the interrupt routine.\n\n        RES     5,(IY+$01)      ; update FLAGS  - reset the new key flag.\n        PUSH    AF              ; save the input character.\n\n        BIT     5,(IY+$02)      ; test TV_FLAG  - clear lower screen ?\n\n        CALL    NZ,L0D6E        ; routine CLS-LOWER if so.\n\n        POP     AF              ; restore the character code.\n\n        CP      $20             ; if space or higher then\n        JR      NC,L111B        ; forward to KEY-DONE2 and return with carry\n                                ; set to signal key-found.\n\n        CP      $10             ; with 16d INK and higher skip\n        JR      NC,L10FA        ; forward to KEY-CONTR.\n\n        CP      $06             ; for 6 - 15d\n        JR      NC,L10DB        ; skip forward to KEY-M-CL to handle Modes\n                                ; and CapsLock.\n\n; that only leaves 0-5, the flash bright inverse switches.\n\n        LD      B,A             ; save character in B\n        AND     $01             ; isolate the embedded parameter (0/1).\n        LD      C,A             ; and store in C\n        LD      A,B             ; re-fetch copy (0-5)\n        RRA                     ; halve it 0, 1 or 2.\n        ADD     A,$12           ; add 18d gives 'flash', 'bright'\n                                ; and 'inverse'.\n        JR      L1105           ; forward to KEY-DATA with the\n                                ; parameter (0/1) in C.\n\n; ---\n\n; Now separate capslock 06 from modes 7-15.\n\n;; KEY-M-CL\nL10DB:  JR      NZ,L10E6        ; forward to KEY-MODE if not 06 (capslock)\n\n        LD      HL,$5C6A        ; point to FLAGS2\n        LD      A,$08           ; value 00001000\n        XOR     (HL)            ; toggle BIT 3 of FLAGS2 the capslock bit\n        LD      (HL),A          ; and store result in FLAGS2 again.\n        JR      L10F4           ; forward to KEY-FLAG to signal no-key.\n\n; ---\n\n;; KEY-MODE\nL10E6:  CP      $0E             ; compare with chr 14d\n        RET     C               ; return with carry set \"key found\" for\n                                ; codes 7 - 13d leaving 14d and 15d\n                                ; which are converted to mode codes.\n\n        SUB     $0D             ; subtract 13d leaving 1 and 2\n                                ; 1 is 'E' mode, 2 is 'G' mode.\n        LD      HL,$5C41        ; address the MODE system variable.\n        CP      (HL)            ; compare with existing value before\n        LD      (HL),A          ; inserting the new value.\n        JR      NZ,L10F4        ; forward to KEY-FLAG if it has changed.\n\n        LD      (HL),$00        ; else make MODE zero - KLC mode\n                                ; Note. while in Extended/Graphics mode,\n                                ; the Extended Mode/Graphics key is pressed\n                                ; again to get out.\n\n;; KEY-FLAG\nL10F4:  SET     3,(IY+$02)      ; update TV_FLAG  - show key state has changed\n        CP      A               ; clear carry and reset zero flags -\n                                ; no actual key returned.\n        RET                     ; make the return.\n\n; ---\n\n; now deal with colour controls - 16-23 ink, 24-31 paper\n\n;; KEY-CONTR\nL10FA:  LD      B,A             ; make a copy of character.\n        AND     $07             ; mask to leave bits 0-7\n        LD      C,A             ; and store in C.\n        LD      A,$10           ; initialize to 16d - INK.\n        BIT     3,B             ; was it paper ?\n        JR      NZ,L1105        ; forward to KEY-DATA with INK 16d and\n                                ; colour in C.\n\n        INC     A               ; else change from INK to PAPER (17d) if so.\n\n;; KEY-DATA\nL1105:  LD      (IY-$2D),C      ; put the colour (0-7)/state(0/1) in KDATA\n        LD      DE,L110D        ; address: KEY-NEXT will be next input stream\n        JR      L1113           ; forward to KEY-CHAN to change it ...\n\n; ---\n\n; ... so that INPUT_AD directs control to here at next call to WAIT-KEY\n\n;; KEY-NEXT\nL110D:  LD      A,($5C0D)       ; pick up the parameter stored in KDATA.\n        LD      DE,L10A8        ; address: KEY-INPUT will be next input stream\n                                ; continue to restore default channel and\n                                ; make a return with the control code.\n\n;; KEY-CHAN\nL1113:  LD      HL,($5C4F)      ; address start of CHANNELS area using CHANS\n                                ; system variable.\n                                ; Note. One might have expected CURCHL to\n                                ; have been used.\n        INC     HL              ; step over the\n        INC     HL              ; output address\n        LD      (HL),E          ; and update the input\n        INC     HL              ; routine address for\n        LD      (HL),D          ; the next call to WAIT-KEY.\n\n;; KEY-DONE2\nL111B:  SCF                     ; set carry flag to show a key has been found\n        RET                     ; and return.\n\n; --------------------\n; Lower screen copying\n; --------------------\n; This subroutine is called whenever the line in the editing area or\n; input workspace is required to be printed to the lower screen.\n; It is by calling this routine after any change that the cursor, for\n; instance, appears to move to the left.\n; Remember the edit line will contain characters and tokens\n; e.g. \"1000 LET a=1\" is 8 characters.\n\n;; ED-COPY\nL111D:  CALL    L0D4D           ; routine TEMPS sets temporary attributes.\n        RES     3,(IY+$02)      ; update TV_FLAG  - signal no change in mode\n        RES     5,(IY+$02)      ; update TV_FLAG  - signal don't clear lower\n                                ; screen.\n        LD      HL,($5C8A)      ; fetch SPOSNL\n        PUSH    HL              ; and save on stack.\n\n        LD      HL,($5C3D)      ; fetch ERR_SP\n        PUSH    HL              ; and save also\n        LD      HL,L1167        ; address: ED-FULL\n        PUSH    HL              ; is pushed as the error routine\n        LD      ($5C3D),SP      ; and ERR_SP made to point to it.\n\n        LD      HL,($5C82)      ; fetch ECHO_E\n        PUSH    HL              ; and push also\n\n        SCF                     ; set carry flag to control SET-DE\n        CALL    L1195           ; call routine SET-DE\n                                ; if in input DE = WORKSP\n                                ; if in edit  DE = E_LINE\n        EX      DE,HL           ; start address to HL\n\n        CALL    L187D           ; routine OUT-LINE2 outputs entire line up to\n                                ; carriage return including initial\n                                ; characterized line number when present.\n        EX      DE,HL           ; transfer new address to DE\n        CALL    L18E1           ; routine OUT-CURS considers a\n                                ; terminating cursor.\n\n        LD      HL,($5C8A)      ; fetch updated SPOSNL\n        EX      (SP),HL         ; exchange with ECHO_E on stack\n        EX      DE,HL           ; transfer ECHO_E to DE\n        CALL    L0D4D           ; routine TEMPS to re-set attributes\n                                ; if altered.\n\n; the lower screen was not cleared, at the outset, so if deleting then old\n; text from a previous print may follow this line and requires blanking.\n\n;; ED-BLANK\nL1150:  LD      A,($5C8B)       ; fetch SPOSNL_hi is current line\n        SUB     D               ; compare with old\n        JR      C,L117C         ; forward to ED-C-DONE if no blanking\n\n        JR      NZ,L115E        ; forward to ED-SPACES if line has changed\n\n        LD      A,E             ; old column to A\n        SUB     (IY+$50)        ; subtract new in SPOSNL_lo\n        JR      NC,L117C        ; forward to ED-C-DONE if no backfilling.\n\n;; ED-SPACES\nL115E:  LD      A,$20           ; prepare a space.\n        PUSH    DE              ; save old line/column.\n        CALL    L09F4           ; routine PRINT-OUT prints a space over\n                                ; any text from previous print.\n                                ; Note. Since the blanking only occurs when\n                                ; using $09F4 to print to the lower screen,\n                                ; there is no need to vector via a RST 10\n                                ; and we can use this alternate set.\n        POP     DE              ; restore the old line column.\n        JR      L1150           ; back to ED-BLANK until all old text blanked.\n\n; -------------------------------\n; THE 'EDITOR-FULL' ERROR ROUTINE\n; -------------------------------\n;   This is the error routine addressed by ERR_SP.  This is not for the out of\n;   memory situation as we're just printing.  The pitch and duration are exactly\n;   the same as used by ED-ERROR from which this has been augmented.  The\n;   situation is that the lower screen is full and a rasp is given to suggest\n;   that this is perhaps not the best idea you've had that day.\n\n;; ED-FULL\nL1167:  LD      D,$00           ; prepare to moan.\n        LD      E,(IY-$02)      ; fetch RASP value.\n        LD      HL,$1A90        ; set pitch or tone period.\n\n        CALL    L03B5           ; routine BEEPER.\n\n        LD      (IY+$00),$FF    ; clear ERR_NR.\n        LD      DE,($5C8A)      ; fetch SPOSNL.\n        JR      L117E           ; forward to ED-C-END\n\n; -------\n\n; the exit point from line printing continues here.\n\n;; ED-C-DONE\nL117C:  POP     DE              ; fetch new line/column.\n        POP     HL              ; fetch the error address.\n\n; the error path rejoins here.\n\n;; ED-C-END\nL117E:  POP     HL              ; restore the old value of ERR_SP.\n        LD      ($5C3D),HL      ; update the system variable ERR_SP\n\n        POP     BC              ; old value of SPOSN_L\n        PUSH    DE              ; save new value\n\n        CALL    L0DD9           ; routine CL-SET and PO-STORE\n                                ; update ECHO_E and SPOSN_L from BC\n\n        POP     HL              ; restore new value\n        LD      ($5C82),HL      ; and overwrite ECHO_E\n\n        LD      (IY+$26),$00    ; make error pointer X_PTR_hi out of bounds\n\n        RET                     ; return\n\n; -----------------------------------------------\n; Point to first and last locations of work space\n; -----------------------------------------------\n;   These two nested routines ensure that the appropriate pointers are\n;   selected for the editing area or workspace. The routines that call\n;   these routines are designed to work on either area.\n\n; this routine is called once\n\n;; SET-HL\nL1190:  LD      HL,($5C61)      ; fetch WORKSP to HL.\n        DEC     HL              ; point to last location of editing area.\n        AND     A               ; clear carry to limit exit points to first\n                                ; or last.\n\n; this routine is called with carry set and exits at a conditional return.\n\n;; SET-DE\nL1195:  LD      DE,($5C59)      ; fetch E_LINE to DE\n        BIT     5,(IY+$37)      ; test FLAGX  - Input Mode ?\n        RET     Z               ; return now if in editing mode\n\n        LD      DE,($5C61)      ; fetch WORKSP to DE\n        RET     C               ; return if carry set ( entry = set-de)\n\n        LD      HL,($5C63)      ; fetch STKBOT to HL as well\n        RET                     ; and return  (entry = set-hl (in input))\n\n; -----------------------------------\n; THE 'REMOVE FLOATING POINT' ROUTINE\n; -----------------------------------\n;   When a BASIC LINE or the INPUT BUFFER is parsed any numbers will have\n;   an invisible chr 14d inserted after them and the 5-byte integer or\n;   floating point form inserted after that.  Similar invisible value holders\n;   are also created after the numeric and string variables in a DEF FN list.\n;   This routine removes these 'compiled' numbers from the edit line or\n;   input workspace.\n\n;; REMOVE-FP\nL11A7:  LD      A,(HL)          ; fetch character\n        CP      $0E             ; is it the CHR$ 14 number marker ?\n        LD      BC,$0006        ; prepare to strip six bytes\n\n        CALL    Z,L19E8         ; routine RECLAIM-2 reclaims bytes if CHR$ 14.\n\n        LD      A,(HL)          ; reload next (or same) character\n        INC     HL              ; and advance address\n        CP      $0D             ; end of line or input buffer ?\n        JR      NZ,L11A7        ; back to REMOVE-FP until entire line done.\n\n        RET                     ; return.\n\n\n; *********************************\n; ** Part 6. EXECUTIVE ROUTINES  **\n; *********************************\n\n\n; The memory.\n;\n; +---------+-----------+------------+--------------+-------------+--\n; | BASIC   |  Display  | Attributes | ZX Printer   |    System   |\n; |  ROM    |   File    |    File    |   Buffer     |  Variables  |\n; +---------+-----------+------------+--------------+-------------+--\n; ^         ^           ^            ^              ^             ^\n; $0000   $4000       $5800        $5B00          $5C00         $5CB6 = CHANS\n;\n;\n;  --+----------+---+---------+-----------+---+------------+--+---+--\n;    | Channel  |$80|  BASIC  | Variables |$80| Edit Line  |NL|$80|\n;    |   Info   |   | Program |   Area    |   | or Command |  |   |\n;  --+----------+---+---------+-----------+---+------------+--+---+--\n;    ^              ^         ^               ^                   ^\n;  CHANS           PROG      VARS           E_LINE              WORKSP\n;\n;\n;                             ---5-->         <---2---  <--3---\n;  --+-------+--+------------+-------+-------+---------+-------+-+---+------+\n;    | INPUT |NL| Temporary  | Calc. | Spare | Machine | GOSUB |?|$3E| UDGs |\n;    | data  |  | Work Space | Stack |       |  Stack  | Stack | |   |      |\n;  --+-------+--+------------+-------+-------+---------+-------+-+---+------+\n;    ^                       ^       ^       ^                   ^   ^      ^\n;  WORKSP                  STKBOT  STKEND   sp               RAMTOP UDG  P_RAMT\n;\n\n; -----------------\n; THE 'NEW' COMMAND\n; -----------------\n;   The NEW command is about to set all RAM below RAMTOP to zero and then\n;   re-initialize the system.  All RAM above RAMTOP should, and will be,\n;   preserved.\n;   There is nowhere to store values in RAM or on the stack which becomes\n;   inoperable. Similarly PUSH and CALL instructions cannot be used to store\n;   values or section common code. The alternate register set is the only place\n;   available to store 3 persistent 16-bit system variables.\n\n;; NEW\nL11B7:  DI                      ; Disable Interrupts - machine stack will be\n                                ; cleared.\n        LD      A,$FF           ; Flag coming from NEW.\n        LD      DE,($5CB2)      ; Fetch RAMTOP as top value.\n        EXX                     ; Switch in alternate set.\n        LD      BC,($5CB4)      ; Fetch P-RAMT differs on 16K/48K machines.\n        LD      DE,($5C38)      ; Fetch RASP/PIP.\n        LD      HL,($5C7B)      ; Fetch UDG    differs on 16K/48K machines.\n        EXX                     ; Switch back to main set and continue into...\n\n; ----------------------\n; THE 'START-NEW' BRANCH\n; ----------------------\n;   This branch is taken from above and from RST 00h.\n;   The common code tests RAM and sets it to zero re-initializing all the\n;   non-zero system variables and channel information.  The A register flags\n;   if coming from START or NEW.\n\n;; START-NEW\nL11CB:  LD      B,A             ; Save the flag to control later branching.\n\n        LD      A,$07           ; Select a white border\n        OUT     ($FE),A         ; and set it now by writing to a port.\n\n        LD      A,$3F           ; Load the accumulator with last page in ROM.\n        LD      I,A             ; Set the I register - this remains constant\n                                ; and can't be in the range $40 - $7F as 'snow'\n                                ; appears on the screen.\n\n        LD      HL, NMI_VECT    ; Initialize the NMI jump vector\n        LD      ($5CB0), HL\n        ;NOP                     ; These seem unnecessary.\n        ;NOP                     ; Note: They are a placeholder for the two\n        ;NOP                     ; instructions above that initialize NMI junp.\n        ;NOP                     ; This way the rest of the code is not moved.\n        ;NOP                     ;\n        ;NOP                     ;\n\n; -----------------------\n; THE 'RAM CHECK' SECTION\n; -----------------------\n;   Typically, a Spectrum will have 16K or 48K of RAM and this code will test\n;   it all till it finds an unpopulated location or, less likely, a faulty\n;   location.  Usually it stops when it reaches the top $FFFF, or in the case\n;   of NEW the supplied top value.  The entire screen turns black with\n;   sometimes red stripes on black paper just visible.\n\n;; ram-check\nL11DA:  LD      H,D             ; Transfer the top value to the HL register\n        LD      L,E             ; pair.\n\n;; RAM-FILL\nL11DC:  LD      (HL),$02        ; Load memory with $02 - red ink on black paper.\n        DEC     HL              ; Decrement memory address.\n        CP      H               ; Have we reached ROM - $3F ?\n        JR      NZ,L11DC        ; Back to RAM-FILL if not.\n\n;; RAM-READ\nL11E2:  AND     A               ; Clear carry - prepare to subtract.\n        SBC     HL,DE           ; subtract and add back setting\n        ADD     HL,DE           ; carry when back at start.\n        INC     HL              ; and increment for next iteration.\n        JR      NC,L11EF        ; forward to RAM-DONE if we've got back to\n                                ; starting point with no errors.\n\n        DEC     (HL)            ; decrement to 1.\n        JR      Z,L11EF         ; forward to RAM-DONE if faulty.\n\n        DEC     (HL)            ; decrement to zero.\n        JR      Z,L11E2         ; back to RAM-READ if zero flag was set.\n\n;; RAM-DONE\nL11EF:  DEC     HL              ; step back to last valid location.\n        EXX                     ; regardless of state, set up possibly\n                                ; stored system variables in case from NEW.\n        LD      ($5CB4),BC      ; insert P-RAMT.\n        LD      ($5C38),DE      ; insert RASP/PIP.\n        LD      ($5C7B),HL      ; insert UDG.\n        EXX                     ; switch in main set.\n        INC     B               ; now test if we arrived here from NEW.\n        JR      Z,L1219         ; forward to RAM-SET if we did.\n\n;   This section applies to START only.\n\n        LD      ($5CB4),HL      ; set P-RAMT to the highest working RAM\n                                ; address.\n        LD      DE,$3EAF        ; address of last byte of 'U' bitmap in ROM.\n        LD      BC,$00A8        ; there are 21 user defined graphics.\n        EX      DE,HL           ; switch pointers and make the UDGs a\n        LDDR                    ; copy of the standard characters A - U.\n        EX      DE,HL           ; switch the pointer to HL.\n        INC     HL              ; update to start of 'A' in RAM.\n        LD      ($5C7B),HL      ; make UDG system variable address the first\n                                ; bitmap.\n        DEC     HL              ; point at RAMTOP again.\n\n        LD      BC,$0040        ; set the values of\n        LD      ($5C38),BC      ; the PIP and RASP system variables.\n\n;   The NEW command path rejoins here.\n\n;; RAM-SET\nL1219:  LD      ($5CB2),HL      ; set system variable RAMTOP to HL.\n\n;\n;   Note. this entry point is a disabled Warm Restart that was almost certainly\n;   once pointed to by the System Variable NMIADD.  It would be essential that\n;   any NMI Handler would perform the tasks from here to the EI instruction\n;   below.\n\nNMI_VECT:\nL121C:\n        LD      HL,$3C00        ; a strange place to set the pointer to the\n        LD      ($5C36),HL      ; character set, CHARS - as no printing yet.\n\n        LD      HL,($5CB2)      ; fetch RAMTOP to HL again as we've lost it.\n\n        LD      (HL),$3E        ; top of user ram holds GOSUB end marker\n                                ; an impossible line number - see RETURN.\n                                ; no significance in the number $3E. It has\n                                ; been traditional since the ZX80.\n\n        DEC     HL              ; followed by empty byte (not important).\n        LD      SP,HL           ; set up the machine stack pointer.\n        DEC     HL              ;\n        DEC     HL              ;\n        LD      ($5C3D),HL      ; ERR_SP is where the error pointer is\n                                ; at moment empty - will take address MAIN-4\n                                ; at the call preceding that address,\n                                ; although interrupts and calls will make use\n                                ; of this location in meantime.\n\n        IM      1               ; select interrupt mode 1.\n\n        LD      IY,$5C3A        ; set IY to ERR_NR. IY can reach all standard\n                                ; system variables but shadow ROM system\n                                ; variables will be mostly out of range.\n\n        EI                      ; enable interrupts now that we have a stack.\n\n;   If, as suggested above, the NMI service routine pointed to this section of\n;   code then a decision would have to be made at this point to jump forward,\n;   in a Warm Restart scenario, to produce a report code, leaving any program\n;   intact.\n\n        LD      HL,$5CB6        ; The address of the channels - initially\n                                ; following system variables.\n        LD      ($5C4F),HL      ; Set the CHANS system variable.\n\n        LD      DE,L15AF        ; Address: init-chan in ROM.\n        LD      BC,$0015        ; There are 21 bytes of initial data in ROM.\n        EX      DE,HL           ; swap the pointers.\n        LDIR                    ; Copy the bytes to RAM.\n\n        EX      DE,HL           ; Swap pointers. HL points to program area.\n        DEC     HL              ; Decrement address.\n        LD      ($5C57),HL      ; Set DATADD to location before program area.\n        INC     HL              ; Increment again.\n\n        LD      ($5C53),HL      ; Set PROG the location where BASIC starts.\n        LD      ($5C4B),HL      ; Set VARS to same location with a\n        LD      (HL),$80        ; variables end-marker.\n        INC     HL              ; Advance address.\n        LD      ($5C59),HL      ; Set E_LINE, where the edit line\n                                ; will be created.\n                                ; Note. it is not strictly necessary to\n                                ; execute the next fifteen bytes of code\n                                ; as this will be done by the call to SET-MIN.\n                                ; --\n        LD      (HL),$0D        ; initially just has a carriage return\n        INC     HL              ; followed by\n        LD      (HL),$80        ; an end-marker.\n        INC     HL              ; address the next location.\n        LD      ($5C61),HL      ; set WORKSP - empty workspace.\n        LD      ($5C63),HL      ; set STKBOT - bottom of the empty stack.\n        LD      ($5C65),HL      ; set STKEND to the end of the empty stack.\n                                ; --\n        LD      A,$38           ; the colour system is set to white paper,\n                                ; black ink, no flash or bright.\n        LD      ($5C8D),A       ; set ATTR_P permanent colour attributes.\n        LD      ($5C8F),A       ; set ATTR_T temporary colour attributes.\n        LD      ($5C48),A       ; set BORDCR the border colour/lower screen\n                                ; attributes.\n\n        LD      HL,$0523        ; The keyboard repeat and delay values are\n        LD      ($5C09),HL      ; loaded to REPDEL and REPPER.\n\n        DEC     (IY-$3A)        ; set KSTATE-0 to $FF - keyboard map available.\n        DEC     (IY-$36)        ; set KSTATE-4 to $FF - keyboard map available.\n\n        LD      HL,L15C6        ; set source to ROM Address: init-strm\n        LD      DE,$5C10        ; set destination to system variable STRMS-FD\n        LD      BC,$000E        ; copy the 14 bytes of initial 7 streams data\n        LDIR                    ; from ROM to RAM.\n\n        SET     1,(IY+$01)      ; update FLAGS  - signal printer in use.\n        CALL    L0EDF           ; call routine CLEAR-PRB to initialize system\n                                ; variables associated with printer.\n                                ; The buffer is clear.\n\n        LD      (IY+$31),$02    ; set DF_SZ the lower screen display size to\n                                ; two lines\n        CALL    L0D6B           ; call routine CLS to set up system\n                                ; variables associated with screen and clear\n                                ; the screen and set attributes.\n        XOR     A               ; clear accumulator so that we can address\n        LD      DE,L1539 - 1    ; the message table directly.\n        CALL    L0C0A           ; routine PO-MSG puts\n                                ; ' ©  1982 Sinclair Research Ltd'\n                                ; at bottom of display.\n        SET     5,(IY+$02)      ; update TV_FLAG  - signal lower screen will\n                                ; require clearing.\n\n        JR      L12A9           ; forward to MAIN-1\n\n; -------------------------\n; THE 'MAIN EXECUTION LOOP'\n; -------------------------\n;\n;\n\n;; MAIN-EXEC\nL12A2:  LD      (IY+$31),$02    ; set DF_SZ lower screen display file size to\n                                ; two lines.\n        CALL    L1795           ; routine AUTO-LIST\n\n;; MAIN-1\nL12A9:  CALL    L16B0           ; routine SET-MIN clears work areas.\n\n;; MAIN-2\nL12AC:  LD      A,$00           ; select channel 'K' the keyboard\n\n        CALL    L1601           ; routine CHAN-OPEN opens it\n\n        CALL    L0F2C           ; routine EDITOR is called.\n                                ; Note the above routine is where the Spectrum\n                                ; waits for user-interaction. Perhaps the\n                                ; most common input at this stage\n                                ; is LOAD \"\".\n\n        CALL    L1B17           ; routine LINE-SCAN scans the input.\n\n        BIT     7,(IY+$00)      ; test ERR_NR - will be $FF if syntax is OK.\n        JR      NZ,L12CF        ; forward, if correct, to MAIN-3.\n\n;\n\n        BIT     4,(IY+$30)      ; test FLAGS2 - K channel in use ?\n        JR      Z,L1303         ; forward to MAIN-4 if not.\n\n;\n\n        LD      HL,($5C59)      ; an editing error so address E_LINE.\n        CALL    L11A7           ; routine REMOVE-FP removes the hidden\n                                ; floating-point forms.\n        LD      (IY+$00),$FF    ; system variable ERR_NR is reset to 'OK'.\n        JR      L12AC           ; back to MAIN-2 to allow user to correct.\n\n; ---\n\n; the branch was here if syntax has passed test.\n\n;; MAIN-3\nL12CF:  LD      HL,($5C59)      ; fetch the edit line address from E_LINE.\n\n        LD      ($5C5D),HL      ; system variable CH_ADD is set to first\n                                ; character of edit line.\n                                ; Note. the above two instructions are a little\n                                ; inadequate.\n                                ; They are repeated with a subtle difference\n                                ; at the start of the next subroutine and are\n                                ; therefore not required above.\n\n        CALL    L19FB           ; routine E-LINE-NO will fetch any line\n                                ; number to BC if this is a program line.\n\n        LD      A,B             ; test if the number of\n        OR      C               ; the line is non-zero.\n        JP      NZ,L155D        ; jump forward to MAIN-ADD if so to add the\n                                ; line to the BASIC program.\n\n; Has the user just pressed the ENTER key ?\n\n        RST     18H             ; GET-CHAR gets character addressed by CH_ADD.\n        CP      $0D             ; is it a carriage return ?\n        JR      Z,L12A2         ; back to MAIN-EXEC if so for an automatic\n                                ; listing.\n\n; this must be a direct command.\n\n        BIT     0,(IY+$30)      ; test FLAGS2 - clear the main screen ?\n\n        CALL    NZ,L0DAF        ; routine CL-ALL, if so, e.g. after listing.\n\n        CALL    L0D6E           ; routine CLS-LOWER anyway.\n\n        LD      A,$19           ; compute scroll count as 25 minus\n        SUB     (IY+$4F)        ; value of S_POSN_hi.\n        LD      ($5C8C),A       ; update SCR_CT system variable.\n        SET     7,(IY+$01)      ; update FLAGS - signal running program.\n        LD      (IY+$00),$FF    ; set ERR_NR to 'OK'.\n        LD      (IY+$0A),$01    ; set NSPPC to one for first statement.\n        CALL    L1B8A           ; call routine LINE-RUN to run the line.\n                                ; sysvar ERR_SP therefore addresses MAIN-4\n\n; Examples of direct commands are RUN, CLS, LOAD \"\", PRINT USR 40000,\n; LPRINT \"A\"; etc..\n; If a user written machine-code program disables interrupts then it\n; must enable them to pass the next step. We also jumped to here if the\n; keyboard was not being used.\n\n;; MAIN-4\nL1303:  HALT                    ; wait for interrupt the only routine that can\n                                ; set bit 5 of FLAGS.\n\n        RES     5,(IY+$01)      ; update bit 5 of FLAGS - signal no new key.\n\n        BIT     1,(IY+$30)      ; test FLAGS2 - is printer buffer clear ?\n        CALL    NZ,L0ECD        ; call routine COPY-BUFF if not.\n                                ; Note. the programmer has neglected\n                                ; to set bit 1 of FLAGS first.\n\n        LD      A,($5C3A)       ; fetch ERR_NR\n        INC     A               ; increment to give true code.\n\n; Now deal with a runtime error as opposed to an editing error.\n; However if the error code is now zero then the OK message will be printed.\n\n;; MAIN-G\nL1313:  PUSH    AF              ; save the error number.\n\n        LD      HL,$0000        ; prepare to clear some system variables.\n        LD      (IY+$37),H      ; clear all the bits of FLAGX.\n        LD      (IY+$26),H      ; blank X_PTR_hi to suppress error marker.\n        LD      ($5C0B),HL      ; blank DEFADD to signal that no defined\n                                ; function is currently being evaluated.\n\n        LD      HL,$0001        ; explicit - inc hl would do.\n        LD      ($5C16),HL      ; ensure STRMS-00 is keyboard.\n\n        CALL    L16B0           ; routine SET-MIN clears workspace etc.\n        RES     5,(IY+$37)      ; update FLAGX - signal in EDIT not INPUT mode.\n                                ; Note. all the bits were reset earlier.\n\n        CALL    L0D6E           ; call routine CLS-LOWER.\n\n        SET     5,(IY+$02)      ; update TV_FLAG - signal lower screen\n                                ; requires clearing.\n\n        POP     AF              ; bring back the true error number\n        LD      B,A             ; and make a copy in B.\n        CP      $0A             ; is it a print-ready digit ?\n        JR      C,L133C         ; forward to MAIN-5 if so.\n\n        ADD     A,$07           ; add ASCII offset to letters.\n\n;; MAIN-5\nL133C:  CALL    L15EF           ; call routine OUT-CODE to print the code.\n\n        LD      A,$20           ; followed by a space.\n        RST     10H             ; PRINT-A\n\n        LD      A,B             ; fetch stored report code.\n        LD      DE,L1391        ; address: rpt-mesgs.\n\n        CALL    L0C0A           ; call routine PO-MSG to print the message.\n\nX1349:  XOR     A               ; clear accumulator to directly\n        LD      DE,L1537 - 1    ; address the comma and space message.\n\n        CALL    L0C0A           ; routine PO-MSG prints ', ' although it would\n                                ; be more succinct to use RST $10.\n\n        LD      BC,($5C45)      ; fetch PPC the current line number.\n        CALL    L1A1B           ; routine OUT-NUM-1 will print that\n\n        LD      A,$3A           ; then a ':' character.\n        RST     10H             ; PRINT-A\n\n        LD      C,(IY+$0D)      ; then SUBPPC for statement\n        LD      B,$00           ; limited to 127\n        CALL    L1A1B           ; routine OUT-NUM-1 prints BC.\n\n        CALL    L1097           ; routine CLEAR-SP clears editing area which\n                                ; probably contained 'RUN'.\n\n        LD      A,($5C3A)       ; fetch ERR_NR again\n        INC     A               ; test for no error originally $FF.\n        JR      Z,L1386         ; forward to MAIN-9 if no error.\n\n        CP      $09             ; is code Report 9 STOP ?\n        JR      Z,L1373         ; forward to MAIN-6 if so\n\n        CP      $15             ; is code Report L Break ?\n        JR      NZ,L1376        ; forward to MAIN-7 if not\n\n; Stop or Break was encountered so consider CONTINUE.\n\n;; MAIN-6\nL1373:  INC     (IY+$0D)        ; increment SUBPPC to next statement.\n\n;; MAIN-7\nL1376:  LD      BC,$0003        ; prepare to copy 3 system variables to\n        LD      DE,$5C70        ; address OSPPC - statement for CONTINUE.\n                                ; also updating OLDPPC line number below.\n\n        LD      HL,$5C44        ; set source top to NSPPC next statement.\n        BIT     7,(HL)          ; did BREAK occur before the jump ?\n                                ; e.g. between GO TO and next statement.\n        JR      Z,L1384         ; skip forward to MAIN-8, if not, as set-up\n                                ; is correct.\n\n        ADD     HL,BC           ; set source to SUBPPC number of current\n                                ; statement/line which will be repeated.\n\n;; MAIN-8\nL1384:  LDDR                    ; copy PPC to OLDPPC and SUBPPC to OSPCC\n                                ; or NSPPC to OLDPPC and NEWPPC to OSPCC\n\n;; MAIN-9\nL1386:  LD      (IY+$0A),$FF    ; update NSPPC - signal 'no jump'.\n        RES     3,(IY+$01)      ; update FLAGS - signal use 'K' mode for\n                                ; the first character in the editor and\n\n        JP      L12AC           ; jump back to MAIN-2.\n\n\n; ----------------------\n; Canned report messages\n; ----------------------\n; The Error reports with the last byte inverted. The first entry\n; is a dummy entry. The last, which begins with $7F, the Spectrum\n; character for copyright symbol, is placed here for convenience\n; as is the preceding comma and space.\n; The report line must accommodate a 4-digit line number and a 3-digit\n; statement number which limits the length of the message text to twenty\n; characters.\n; e.g.  \"B Integer out of range, 1000:127\"\n\n;; rpt-mesgs\nL1391:  DEFB    $80\n        DEFB    'O','K'+$80                             ; 0\n        DEFM    \"NEXT without FO\"\n        DEFB    'R'+$80                                 ; 1\n        DEFM    \"Variable not foun\"\n        DEFB    'd'+$80                                 ; 2\n        DEFM    \"Subscript wron\"\n        DEFB    'g'+$80                                 ; 3\n        DEFM    \"Out of memor\"\n        DEFB    'y'+$80                                 ; 4\n        DEFM    \"Out of scree\"\n        DEFB    'n'+$80                                 ; 5\n        DEFM    \"Number too bi\"\n        DEFB    'g'+$80                                 ; 6\n        DEFM    \"RETURN without GOSU\"\n        DEFB    'B'+$80                                 ; 7\n        DEFM    \"End of fil\"\n        DEFB    'e'+$80                                 ; 8\n        DEFM    \"STOP statemen\"\n        DEFB    't'+$80                                 ; 9\n        DEFM    \"Invalid argumen\"\n        DEFB    't'+$80                                 ; A\n        DEFM    \"Integer out of rang\"\n        DEFB    'e'+$80                                 ; B\n        DEFM    \"Nonsense in BASI\"\n        DEFB    'C'+$80                                 ; C\n        DEFM    \"BREAK - CONT repeat\"\n        DEFB    's'+$80                                 ; D\n        DEFM    \"Out of DAT\"\n        DEFB    'A'+$80                                 ; E\n        DEFM    \"Invalid file nam\"\n        DEFB    'e'+$80                                 ; F\n        DEFM    \"No room for lin\"\n        DEFB    'e'+$80                                 ; G\n        DEFM    \"STOP in INPU\"\n        DEFB    'T'+$80                                 ; H\n        DEFM    \"FOR without NEX\"\n        DEFB    'T'+$80                                 ; I\n        DEFM    \"Invalid I/O devic\"\n        DEFB    'e'+$80                                 ; J\n        DEFM    \"Invalid colou\"\n        DEFB    'r'+$80                                 ; K\n        DEFM    \"BREAK into progra\"\n        DEFB    'm'+$80                                 ; L\n        DEFM    \"RAMTOP no goo\"\n        DEFB    'd'+$80                                 ; M\n        DEFM    \"Statement los\"\n        DEFB    't'+$80                                 ; N\n        DEFM    \"Invalid strea\"\n        DEFB    'm'+$80                                 ; O\n        DEFM    \"FN without DE\"\n        DEFB    'F'+$80                                 ; P\n        DEFM    \"Parameter erro\"\n        DEFB    'r'+$80                                 ; Q\n        DEFM    \"Tape loading erro\"\n        DEFB    'r'+$80                                 ; R\n;; comma-sp\nL1537:  DEFB    ',',' '+$80                             ; used in report line.\n;; copyright\nL1539:  DEFB    $7F                                     ; copyright\n        DEFM    \" 1982 Sinclair Research Lt\"\n        DEFB    'd'+$80\n\n\n; -------------\n; REPORT-G\n; -------------\n; Note ERR_SP points here during line entry which allows the\n; normal 'Out of Memory' report to be augmented to the more\n; precise 'No Room for line' report.\n\n;; REPORT-G\n; No Room for line\nL1555:  LD      A,$10           ; i.e. 'G' -$30 -$07\n        LD      BC,$0000        ; this seems unnecessary.\n        JP      L1313           ; jump back to MAIN-G\n\n; -----------------------------\n; Handle addition of BASIC line\n; -----------------------------\n; Note this is not a subroutine but a branch of the main execution loop.\n; System variable ERR_SP still points to editing error handler.\n; A new line is added to the BASIC program at the appropriate place.\n; An existing line with same number is deleted first.\n; Entering an existing line number deletes that line.\n; Entering a non-existent line allows the subsequent line to be edited next.\n\n;; MAIN-ADD\nL155D:  LD      ($5C49),BC      ; set E_PPC to extracted line number.\n        LD      HL,($5C5D)      ; fetch CH_ADD - points to location after the\n                                ; initial digits (set in E_LINE_NO).\n        EX      DE,HL           ; save start of BASIC in DE.\n\n        LD      HL,L1555        ; Address: REPORT-G\n        PUSH    HL              ; is pushed on stack and addressed by ERR_SP.\n                                ; the only error that can occur is\n                                ; 'Out of memory'.\n\n        LD      HL,($5C61)      ; fetch WORKSP - end of line.\n        SCF                     ; prepare for true subtraction.\n        SBC     HL,DE           ; find length of BASIC and\n        PUSH    HL              ; save it on stack.\n        LD      H,B             ; transfer line number\n        LD      L,C             ; to HL register.\n        CALL    L196E           ; routine LINE-ADDR will see if\n                                ; a line with the same number exists.\n        JR      NZ,L157D        ; forward if no existing line to MAIN-ADD1.\n\n        CALL    L19B8           ; routine NEXT-ONE finds the existing line.\n        CALL    L19E8           ; routine RECLAIM-2 reclaims it.\n\n;; MAIN-ADD1\nL157D:  POP     BC              ; retrieve the length of the new line.\n        LD      A,C             ; and test if carriage return only\n        DEC     A               ; i.e. one byte long.\n        OR      B               ; result would be zero.\n        JR      Z,L15AB         ; forward to MAIN-ADD2 is so.\n\n        PUSH    BC              ; save the length again.\n        INC     BC              ; adjust for inclusion\n        INC     BC              ; of line number (two bytes)\n        INC     BC              ; and line length\n        INC     BC              ; (two bytes).\n        DEC     HL              ; HL points to location before the destination\n\n        LD      DE,($5C53)      ; fetch the address of PROG\n        PUSH    DE              ; and save it on the stack\n        CALL    L1655           ; routine MAKE-ROOM creates BC spaces in\n                                ; program area and updates pointers.\n        POP     HL              ; restore old program pointer.\n        LD      ($5C53),HL      ; and put back in PROG as it may have been\n                                ; altered by the POINTERS routine.\n\n        POP     BC              ; retrieve BASIC length\n        PUSH    BC              ; and save again.\n\n        INC     DE              ; points to end of new area.\n        LD      HL,($5C61)      ; set HL to WORKSP - location after edit line.\n        DEC     HL              ; decrement to address end marker.\n        DEC     HL              ; decrement to address carriage return.\n        LDDR                    ; copy the BASIC line back to initial command.\n\n        LD      HL,($5C49)      ; fetch E_PPC - line number.\n        EX      DE,HL           ; swap it to DE, HL points to last of\n                                ; four locations.\n        POP     BC              ; retrieve length of line.\n        LD      (HL),B          ; high byte last.\n        DEC     HL              ;\n        LD      (HL),C          ; then low byte of length.\n        DEC     HL              ;\n        LD      (HL),E          ; then low byte of line number.\n        DEC     HL              ;\n        LD      (HL),D          ; then high byte range $0 - $27 (1-9999).\n\n;; MAIN-ADD2\nL15AB:  POP     AF              ; drop the address of Report G\n        JP      L12A2           ; and back to MAIN-EXEC producing a listing\n                                ; and to reset ERR_SP in EDITOR.\n\n\n; ---------------------------------\n; THE 'INITIAL CHANNEL' INFORMATION\n; ---------------------------------\n;   This initial channel information is copied from ROM to RAM, during\n;   initialization.  It's new location is after the system variables and is\n;   addressed by the system variable CHANS which means that it can slide up and\n;   down in memory.  The table is never searched, by this ROM, and the last\n;   character, which could be anything other than a comma, provides a\n;   convenient resting place for DATADD.\n\n;; init-chan\nL15AF:  DEFW    L09F4           ; PRINT-OUT\n        DEFW    L10A8           ; KEY-INPUT\n        DEFB    $4B             ; 'K'\n        DEFW    L09F4           ; PRINT-OUT\n        DEFW    L15C4           ; REPORT-J\n        DEFB    $53             ; 'S'\n        DEFW    L0F81           ; ADD-CHAR\n        DEFW    L15C4           ; REPORT-J\n        DEFB    $52             ; 'R'\n        DEFW    L09F4           ; PRINT-OUT\n        DEFW    L15C4           ; REPORT-J\n        DEFB    $50             ; 'P'\n\n        DEFB    $80             ; End Marker\n\n;; REPORT-J\nL15C4:  RST     08H             ; ERROR-1\n        DEFB    $12             ; Error Report: Invalid I/O device\n\n\n; -------------------------\n; THE 'INITIAL STREAM' DATA\n; -------------------------\n;   This is the initial stream data for the seven streams $FD - $03 that is\n;   copied from ROM to the STRMS system variables area during initialization.\n;   There are reserved locations there for another 12 streams.  Each location\n;   contains an offset to the second byte of a channel.  The first byte of a\n;   channel can't be used as that would result in an offset of zero for some\n;   and zero is used to denote that a stream is closed.\n\n;; init-strm\nL15C6:  DEFB    $01, $00        ; stream $FD offset to channel 'K'\n        DEFB    $06, $00        ; stream $FE offset to channel 'S'\n        DEFB    $0B, $00        ; stream $FF offset to channel 'R'\n\n        DEFB    $01, $00        ; stream $00 offset to channel 'K'\n        DEFB    $01, $00        ; stream $01 offset to channel 'K'\n        DEFB    $06, $00        ; stream $02 offset to channel 'S'\n        DEFB    $10, $00        ; stream $03 offset to channel 'P'\n\n; ------------------------------\n; THE 'INPUT CONTROL' SUBROUTINE\n; ------------------------------\n;\n\n;; WAIT-KEY\nL15D4:  BIT     5,(IY+$02)      ; test TV_FLAG - clear lower screen ?\n        JR      NZ,L15DE        ; forward to WAIT-KEY1 if so.\n\n        SET     3,(IY+$02)      ; update TV_FLAG - signal reprint the edit\n                                ; line to the lower screen.\n\n;; WAIT-KEY1\nL15DE:  CALL    L15E6           ; routine INPUT-AD is called.\n\n        RET     C               ; return with acceptable keys.\n\n        JR      Z,L15DE         ; back to WAIT-KEY1 if no key is pressed\n                                ; or it has been handled within INPUT-AD.\n\n;   Note. When inputting from the keyboard all characters are returned with\n;   above conditions so this path is never taken.\n\n;; REPORT-8\nL15E4:  RST     08H             ; ERROR-1\n        DEFB    $07             ; Error Report: End of file\n\n; ---------------------------\n; THE 'INPUT ADDRESS' ROUTINE\n; ---------------------------\n;   This routine fetches the address of the input stream from the current\n;   channel area using the system variable CURCHL.\n\n;; INPUT-AD\nL15E6:  EXX                     ; switch in alternate set.\n        PUSH    HL              ; save HL register\n        LD      HL,($5C51)      ; fetch address of CURCHL - current channel.\n        INC     HL              ; step over output routine\n        INC     HL              ; to point to low byte of input routine.\n        JR      L15F7           ; forward to CALL-SUB.\n\n; -------------------------\n; THE 'CODE OUTPUT' ROUTINE\n; -------------------------\n;   This routine is called on five occasions to print the ASCII equivalent of\n;   a value 0-9.\n\n;; OUT-CODE\nL15EF:  LD      E,$30           ; add 48 decimal to give the ASCII character\n        ADD     A,E             ; '0' to '9' and continue into the main output\n                                ; routine.\n\n; -------------------------\n; THE 'MAIN OUTPUT' ROUTINE\n; -------------------------\n;   PRINT-A-2 is a continuation of the RST 10 restart that prints any character.\n;   The routine prints to the current channel and the printing of control codes\n;   may alter that channel to divert subsequent RST 10 instructions to temporary\n;   routines. The normal channel is $09F4.\n\n;; PRINT-A-2\nL15F2:  EXX                     ; switch in alternate set\n        PUSH    HL              ; save HL register\n        LD      HL,($5C51)      ; fetch CURCHL the current channel.\n\n; input-ad rejoins here also.\n\n;; CALL-SUB\nL15F7:  LD      E,(HL)          ; put the low byte in E.\n        INC     HL              ; advance address.\n        LD      D,(HL)          ; put the high byte to D.\n        EX      DE,HL           ; transfer the stream to HL.\n        CALL    L162C           ; use routine CALL-JUMP.\n                                ; in effect CALL (HL).\n\n        POP     HL              ; restore saved HL register.\n        EXX                     ; switch back to the main set and\n        RET                     ; return.\n\n; --------------------------\n; THE 'OPEN CHANNEL' ROUTINE\n; --------------------------\n;   This subroutine is used by the ROM to open a channel 'K', 'S', 'R' or 'P'.\n;   This is either for its own use or in response to a user's request, for\n;   example, when '#' is encountered with output - PRINT, LIST etc.\n;   or with input - INPUT, INKEY$ etc.\n;   It is entered with a system stream $FD - $FF, or a user stream $00 - $0F\n;   in the accumulator.\n\n;; CHAN-OPEN\nL1601:  ADD     A,A             ; double the stream ($FF will become $FE etc.)\n        ADD     A,$16           ; add the offset to stream 0 from $5C00\n        LD      L,A             ; result to L\n        LD      H,$5C           ; now form the address in STRMS area.\n        LD      E,(HL)          ; fetch low byte of CHANS offset\n        INC     HL              ; address next\n        LD      D,(HL)          ; fetch high byte of offset\n        LD      A,D             ; test that the stream is open.\n        OR      E               ; zero if closed.\n        JR      NZ,L1610        ; forward to CHAN-OP-1 if open.\n\n;; REPORT-Oa\nL160E:  RST     08H             ; ERROR-1\n        DEFB    $17             ; Error Report: Invalid stream\n\n; continue here if stream was open. Note that the offset is from CHANS\n; to the second byte of the channel.\n\n;; CHAN-OP-1\nL1610:  DEC     DE              ; reduce offset so it points to the channel.\n        LD      HL,($5C4F)      ; fetch CHANS the location of the base of\n                                ; the channel information area\n        ADD     HL,DE           ; and add the offset to address the channel.\n                                ; and continue to set flags.\n\n; -----------------\n; Set channel flags\n; -----------------\n; This subroutine is used from ED-EDIT, str$ and read-in to reset the\n; current channel when it has been temporarily altered.\n\n;; CHAN-FLAG\nL1615:  LD      ($5C51),HL      ; set CURCHL system variable to the\n                                ; address in HL\n        RES     4,(IY+$30)      ; update FLAGS2  - signal K channel not in use.\n                                ; Note. provide a default for channel 'R'.\n        INC     HL              ; advance past\n        INC     HL              ; output routine.\n        INC     HL              ; advance past\n        INC     HL              ; input routine.\n        LD      C,(HL)          ; pick up the letter.\n        LD      HL,L162D        ; address: chn-cd-lu\n        CALL    L16DC           ; routine INDEXER finds offset to a\n                                ; flag-setting routine.\n\n        RET     NC              ; but if the letter wasn't found in the\n                                ; table just return now. - channel 'R'.\n\n        LD      D,$00           ; prepare to add\n        LD      E,(HL)          ; offset to E\n        ADD     HL,DE           ; add offset to location of offset to form\n                                ; address of routine\n\n;; CALL-JUMP\nL162C:  JP      (HL)            ; jump to the routine\n\n; Footnote. calling any location that holds JP (HL) is the equivalent to\n; a pseudo Z80 instruction CALL (HL). The ROM uses the instruction above.\n\n; --------------------------\n; Channel code look-up table\n; --------------------------\n; This table is used by the routine above to find one of the three\n; flag setting routines below it.\n; A zero end-marker is required as channel 'R' is not present.\n\n;; chn-cd-lu\nL162D:  DEFB    'K', L1634-$-1  ; offset $06 to CHAN-K\n        DEFB    'S', L1642-$-1  ; offset $12 to CHAN-S\n        DEFB    'P', L164D-$-1  ; offset $1B to CHAN-P\n\n        DEFB    $00             ; end marker.\n\n; --------------\n; Channel K flag\n; --------------\n; routine to set flags for lower screen/keyboard channel.\n\n;; CHAN-K\nL1634:  SET     0,(IY+$02)      ; update TV_FLAG  - signal lower screen in use\n        RES     5,(IY+$01)      ; update FLAGS    - signal no new key\n        SET     4,(IY+$30)      ; update FLAGS2   - signal K channel in use\n        JR      L1646           ; forward to CHAN-S-1 for indirect exit\n\n; --------------\n; Channel S flag\n; --------------\n; routine to set flags for upper screen channel.\n\n;; CHAN-S\nL1642:  RES     0,(IY+$02)      ; TV_FLAG  - signal main screen in use\n\n;; CHAN-S-1\nL1646:  RES     1,(IY+$01)      ; update FLAGS  - signal printer not in use\n        JP      L0D4D           ; jump back to TEMPS and exit via that\n                                ; routine after setting temporary attributes.\n; --------------\n; Channel P flag\n; --------------\n; This routine sets a flag so that subsequent print related commands\n; print to printer or update the relevant system variables.\n; This status remains in force until reset by the routine above.\n\n;; CHAN-P\nL164D:  SET     1,(IY+$01)      ; update FLAGS  - signal printer in use\n        RET                     ; return\n\n; --------------------------\n; THE 'ONE SPACE' SUBROUTINE\n; --------------------------\n; This routine is called once only to create a single space\n; in workspace by ADD-CHAR.\n\n;; ONE-SPACE\nL1652:  LD      BC,$0001        ; create space for a single character.\n\n; ---------\n; Make Room\n; ---------\n; This entry point is used to create BC spaces in various areas such as\n; program area, variables area, workspace etc..\n; The entire free RAM is available to each BASIC statement.\n; On entry, HL addresses where the first location is to be created.\n; Afterwards, HL will point to the location before this.\n\n;; MAKE-ROOM\nL1655:  PUSH    HL              ; save the address pointer.\n        CALL    L1F05           ; routine TEST-ROOM checks if room\n                                ; exists and generates an error if not.\n        POP     HL              ; restore the address pointer.\n        CALL    L1664           ; routine POINTERS updates the\n                                ; dynamic memory location pointers.\n                                ; DE now holds the old value of STKEND.\n        LD      HL,($5C65)      ; fetch new STKEND the top destination.\n\n        EX      DE,HL           ; HL now addresses the top of the area to\n                                ; be moved up - old STKEND.\n        LDDR                    ; the program, variables, etc are moved up.\n        RET                     ; return with new area ready to be populated.\n                                ; HL points to location before new area,\n                                ; and DE to last of new locations.\n\n; -----------------------------------------------\n; Adjust pointers before making or reclaiming room\n; -----------------------------------------------\n; This routine is called by MAKE-ROOM to adjust upwards and by RECLAIM to\n; adjust downwards the pointers within dynamic memory.\n; The fourteen pointers to dynamic memory, starting with VARS and ending\n; with STKEND, are updated adding BC if they are higher than the position\n; in HL.\n; The system variables are in no particular order except that STKEND, the first\n; free location after dynamic memory must be the last encountered.\n\n;; POINTERS\nL1664:  PUSH    AF              ; preserve accumulator.\n        PUSH    HL              ; put pos pointer on stack.\n        LD      HL,$5C4B        ; address VARS the first of the\n        LD      A,$0E           ; fourteen variables to consider.\n\n;; PTR-NEXT\nL166B:  LD      E,(HL)          ; fetch the low byte of the system variable.\n        INC     HL              ; advance address.\n        LD      D,(HL)          ; fetch high byte of the system variable.\n        EX      (SP),HL         ; swap pointer on stack with the variable\n                                ; pointer.\n        AND     A               ; prepare to subtract.\n        SBC     HL,DE           ; subtract variable address\n        ADD     HL,DE           ; and add back\n        EX      (SP),HL         ; swap pos with system variable pointer\n        JR      NC,L167F        ; forward to PTR-DONE if var before pos\n\n        PUSH    DE              ; save system variable address.\n        EX      DE,HL           ; transfer to HL\n        ADD     HL,BC           ; add the offset\n        EX      DE,HL           ; back to DE\n        LD      (HL),D          ; load high byte\n        DEC     HL              ; move back\n        LD      (HL),E          ; load low byte\n        INC     HL              ; advance to high byte\n        POP     DE              ; restore old system variable address.\n\n;; PTR-DONE\nL167F:  INC     HL              ; address next system variable.\n        DEC     A               ; decrease counter.\n        JR      NZ,L166B        ; back to PTR-NEXT if more.\n        EX      DE,HL           ; transfer old value of STKEND to HL.\n                                ; Note. this has always been updated.\n        POP     DE              ; pop the address of the position.\n\n        POP     AF              ; pop preserved accumulator.\n        AND     A               ; clear carry flag preparing to subtract.\n\n        SBC     HL,DE           ; subtract position from old stkend\n        LD      B,H             ; to give number of data bytes\n        LD      C,L             ; to be moved.\n        INC     BC              ; increment as we also copy byte at old STKEND.\n        ADD     HL,DE           ; recompute old stkend.\n        EX      DE,HL           ; transfer to DE.\n        RET                     ; return.\n\n\n\n; -------------------\n; Collect line number\n; -------------------\n; This routine extracts a line number, at an address that has previously\n; been found using LINE-ADDR, and it is entered at LINE-NO. If it encounters\n; the program 'end-marker' then the previous line is used and if that\n; should also be unacceptable then zero is used as it must be a direct\n; command. The program end-marker is the variables end-marker $80, or\n; if variables exist, then the first character of any variable name.\n\n;; LINE-ZERO\nL168F:  DEFB    $00, $00        ; dummy line number used for direct commands\n\n\n;; LINE-NO-A\nL1691:  EX      DE,HL           ; fetch the previous line to HL and set\n        LD      DE,L168F        ; DE to LINE-ZERO should HL also fail.\n\n; -> The Entry Point.\n\n;; LINE-NO\nL1695:  LD      A,(HL)          ; fetch the high byte - max $2F\n        AND     $C0             ; mask off the invalid bits.\n        JR      NZ,L1691        ; to LINE-NO-A if an end-marker.\n\n        LD      D,(HL)          ; reload the high byte.\n        INC     HL              ; advance address.\n        LD      E,(HL)          ; pick up the low byte.\n        RET                     ; return from here.\n\n; -------------------\n; Handle reserve room\n; -------------------\n; This is a continuation of the restart BC-SPACES\n\n;; RESERVE\nL169E:  LD      HL,($5C63)      ; STKBOT first location of calculator stack\n        DEC     HL              ; make one less than new location\n        CALL    L1655           ; routine MAKE-ROOM creates the room.\n        INC     HL              ; address the first new location\n        INC     HL              ; advance to second\n        POP     BC              ; restore old WORKSP\n        LD      ($5C61),BC      ; system variable WORKSP was perhaps\n                                ; changed by POINTERS routine.\n        POP     BC              ; restore count for return value.\n        EX      DE,HL           ; switch. DE = location after first new space\n        INC     HL              ; HL now location after new space\n        RET                     ; return.\n\n; ---------------------------\n; Clear various editing areas\n; ---------------------------\n; This routine sets the editing area, workspace and calculator stack\n; to their minimum configurations as at initialization and indeed this\n; routine could have been relied on to perform that task.\n; This routine uses HL only and returns with that register holding\n; WORKSP/STKBOT/STKEND though no use is made of this. The routines also\n; reset MEM to its usual place in the systems variable area should it\n; have been relocated to a FOR-NEXT variable. The main entry point\n; SET-MIN is called at the start of the MAIN-EXEC loop and prior to\n; displaying an error.\n\n;; SET-MIN\nL16B0:  LD      HL,($5C59)      ; fetch E_LINE\n        LD      (HL),$0D        ; insert carriage return\n        LD      ($5C5B),HL      ; make K_CUR keyboard cursor point there.\n        INC     HL              ; next location\n        LD      (HL),$80        ; holds end-marker $80\n        INC     HL              ; next location becomes\n        LD      ($5C61),HL      ; start of WORKSP\n\n; This entry point is used prior to input and prior to the execution,\n; or parsing, of each statement.\n\n;; SET-WORK\nL16BF:  LD      HL,($5C61)      ; fetch WORKSP value\n        LD      ($5C63),HL      ; and place in STKBOT\n\n; This entry point is used to move the stack back to its normal place\n; after temporary relocation during line entry and also from ERROR-3\n\n;; SET-STK\nL16C5:  LD      HL,($5C63)      ; fetch STKBOT value\n        LD      ($5C65),HL      ; and place in STKEND.\n\n        PUSH    HL              ; perhaps an obsolete entry point.\n        LD      HL,$5C92        ; normal location of MEM-0\n        LD      ($5C68),HL      ; is restored to system variable MEM.\n        POP     HL              ; saved value not required.\n        RET                     ; return.\n\n; ------------------\n; Reclaim edit-line?\n; ------------------\n; This seems to be legacy code from the ZX80/ZX81 as it is\n; not used in this ROM.\n; That task, in fact, is performed here by the dual-area routine CLEAR-SP.\n; This routine is designed to deal with something that is known to be in the\n; edit buffer and not workspace.\n; On entry, HL must point to the end of the something to be deleted.\n\n;; REC-EDIT\nL16D4:  LD      DE,($5C59)      ; fetch start of edit line from E_LINE.\n        JP      L19E5           ; jump forward to RECLAIM-1.\n\n; --------------------------\n; The Table INDEXING routine\n; --------------------------\n; This routine is used to search two-byte hash tables for a character\n; held in C, returning the address of the following offset byte.\n; if it is known that the character is in the table e.g. for priorities,\n; then the table requires no zero end-marker. If this is not known at the\n; outset then a zero end-marker is required and carry is set to signal\n; success.\n\n;; INDEXER-1\nL16DB:  INC     HL              ; address the next pair of values.\n\n; -> The Entry Point.\n\n;; INDEXER\nL16DC:  LD      A,(HL)          ; fetch the first byte of pair\n        AND     A               ; is it the end-marker ?\n        RET     Z               ; return with carry reset if so.\n\n        CP      C               ; is it the required character ?\n        INC     HL              ; address next location.\n        JR      NZ,L16DB        ; back to INDEXER-1 if no match.\n\n        SCF                     ; else set the carry flag.\n        RET                     ; return with carry set\n\n; --------------------------------\n; The Channel and Streams Routines\n; --------------------------------\n; A channel is an input/output route to a hardware device\n; and is identified to the system by a single letter e.g. 'K' for\n; the keyboard. A channel can have an input and output route\n; associated with it in which case it is bi-directional like\n; the keyboard. Others like the upper screen 'S' are output\n; only and the input routine usually points to a report message.\n; Channels 'K' and 'S' are system channels and it would be inappropriate\n; to close the associated streams so a mechanism is provided to\n; re-attach them. When the re-attachment is no longer required, then\n; closing these streams resets them as at initialization.\n; Early adverts said that the network and RS232 were in this ROM.\n; Channels 'N' and 'B' are user channels and have been removed successfully\n; if, as seems possible, they existed.\n; Ironically the tape streamer is not accessed through streams and\n; channels.\n; Early demonstrations of the Spectrum showed a single microdrive being\n; controlled by the main ROM.\n\n; ---------------------\n; THE 'CLOSE #' COMMAND\n; ---------------------\n;   This command allows streams to be closed after use.\n;   Any temporary memory areas used by the stream would be reclaimed and\n;   finally flags set or reset if necessary.\n\n;; CLOSE\nL16E5:  CALL    L171E           ; routine STR-DATA fetches parameter\n                                ; from calculator stack and gets the\n                                ; existing STRMS data pointer address in HL\n                                ; and stream offset from CHANS in BC.\n\n                                ; Note. this offset could be zero if the\n                                ; stream is already closed. A check for this\n                                ; should occur now and an error should be\n                                ; generated, for example,\n                                ; Report S 'Stream status closed'.\n\n        CALL    L1701           ; routine CLOSE-2 would perform any actions\n                                ; peculiar to that stream without disturbing\n                                ; data pointer to STRMS entry in HL.\n\n        LD      BC,$0000        ; the stream is to be blanked.\n        LD      DE,$A3E2        ; the number of bytes from stream 4, $5C1E,\n                                ; to $10000\n        EX      DE,HL           ; transfer offset to HL, STRMS data pointer\n                                ; to DE.\n        ADD     HL,DE           ; add the offset to the data pointer.\n        JR      C,L16FC         ; forward to CLOSE-1 if a non-system stream.\n                                ; i.e. higher than 3.\n\n; proceed with a negative result.\n\n        LD      BC,L15C6 + 14   ; prepare the address of the byte after\n                                ; the initial stream data in ROM. ($15D4)\n        ADD     HL,BC           ; index into the data table with negative value.\n        LD      C,(HL)          ; low byte to C\n        INC     HL              ; address next.\n        LD      B,(HL)          ; high byte to B.\n\n;   and for streams 0 - 3 just enter the initial data back into the STRMS entry\n;   streams 0 - 2 can't be closed as they are shared by the operating system.\n;   -> for streams 4 - 15 then blank the entry.\n\n;; CLOSE-1\nL16FC:  EX      DE,HL           ; address of stream to HL.\n        LD      (HL),C          ; place zero (or low byte).\n        INC     HL              ; next address.\n        LD      (HL),B          ; place zero (or high byte).\n        RET                     ; return.\n\n; ------------------------\n; THE 'CLOSE-2' SUBROUTINE\n; ------------------------\n;   There is not much point in coming here.\n;   The purpose was once to find the offset to a special closing routine,\n;   in this ROM and within 256 bytes of the close stream look up table that\n;   would reclaim any buffers associated with a stream. At least one has been\n;   removed.\n;   Any attempt to CLOSE streams $00 to $04, without first opening the stream,\n;   will lead to either a system restart or the production of a strange report.\n;   credit: Martin Wren-Hilton 1982.\n\n;; CLOSE-2\nL1701:  PUSH    HL              ; * save address of stream data pointer\n                                ; in STRMS on the machine stack.\n        LD      HL,($5C4F)      ; fetch CHANS address to HL\n        ADD     HL,BC           ; add the offset to address the second\n                                ; byte of the output routine hopefully.\n        INC     HL              ; step past\n        INC     HL              ; the input routine.\n\n;    Note. When the Sinclair Interface1 is fitted then an instruction fetch\n;    on the next address pages this ROM out and the shadow ROM in.\n\n;; ROM_TRAP\nL1708:  INC     HL              ; to address channel's letter\n        LD      C,(HL)          ; pick it up in C.\n                                ; Note. but if stream is already closed we\n                                ; get the value $10 (the byte preceding 'K').\n\n        EX      DE,HL           ; save the pointer to the letter in DE.\n\n;   Note. The string pointer is saved but not used!!\n\n        LD      HL,L1716        ; address: cl-str-lu in ROM.\n        CALL    L16DC           ; routine INDEXER uses the code to get\n                                ; the 8-bit offset from the current point to\n                                ; the address of the closing routine in ROM.\n                                ; Note. it won't find $10 there!\n\n        LD      C,(HL)          ; transfer the offset to C.\n        LD      B,$00           ; prepare to add.\n        ADD     HL,BC           ; add offset to point to the address of the\n                                ; routine that closes the stream.\n                                ; (and presumably removes any buffers that\n                                ; are associated with it.)\n        JP      (HL)            ; jump to that routine.\n\n; --------------------------------\n; THE 'CLOSE STREAM LOOK-UP' TABLE\n; --------------------------------\n;   This table contains an entry for a letter found in the CHANS area.\n;   followed by an 8-bit displacement, from that byte's address in the\n;   table to the routine that performs any ancillary actions associated\n;   with closing the stream of that channel.\n;   The table doesn't require a zero end-marker as the letter has been\n;   picked up from a channel that has an open stream.\n\n;; cl-str-lu\nL1716:  DEFB    'K', L171C-$-1  ; offset 5 to CLOSE-STR\n        DEFB    'S', L171C-$-1  ; offset 3 to CLOSE-STR\n        DEFB    'P', L171C-$-1  ; offset 1 to CLOSE-STR\n\n\n; ------------------------------\n; THE 'CLOSE STREAM' SUBROUTINES\n; ------------------------------\n; The close stream routines in fact have no ancillary actions to perform\n; which is not surprising with regard to 'K' and 'S'.\n\n;; CLOSE-STR\nL171C:  POP     HL              ; * now just restore the stream data pointer\n        RET                     ; in STRMS and return.\n\n; -----------\n; Stream data\n; -----------\n; This routine finds the data entry in the STRMS area for the specified\n; stream which is passed on the calculator stack. It returns with HL\n; pointing to this system variable and BC holding a displacement from\n; the CHANS area to the second byte of the stream's channel. If BC holds\n; zero, then that signifies that the stream is closed.\n\n;; STR-DATA\nL171E:  CALL    L1E94           ; routine FIND-INT1 fetches parameter to A\n        CP      $10             ; is it less than 16d ?\n        JR      C,L1727         ; skip forward to STR-DATA1 if so.\n\n;; REPORT-Ob\nL1725:  RST     08H             ; ERROR-1\n        DEFB    $17             ; Error Report: Invalid stream\n\n;; STR-DATA1\nL1727:  ADD     A,$03           ; add the offset for 3 system streams.\n                                ; range 00 - 15d becomes 3 - 18d.\n        RLCA                    ; double as there are two bytes per\n                                ; stream - now 06 - 36d\n        LD      HL,$5C10        ; address STRMS - the start of the streams\n                                ; data area in system variables.\n        LD      C,A             ; transfer the low byte to A.\n        LD      B,$00           ; prepare to add offset.\n        ADD     HL,BC           ; add to address the data entry in STRMS.\n\n; the data entry itself contains an offset from CHANS to the address of the\n; stream\n\n        LD      C,(HL)          ; low byte of displacement to C.\n        INC     HL              ; address next.\n        LD      B,(HL)          ; high byte of displacement to B.\n        DEC     HL              ; step back to leave HL pointing to STRMS\n                                ; data entry.\n        RET                     ; return with CHANS displacement in BC\n                                ; and address of stream data entry in HL.\n\n; --------------------\n; Handle OPEN# command\n; --------------------\n; Command syntax example: OPEN #5,\"s\"\n; On entry the channel code entry is on the calculator stack with the next\n; value containing the stream identifier. They have to swapped.\n\n;; OPEN\nL1736:  RST     28H             ;; FP-CALC    ;s,c.\n        DEFB    $01             ;;exchange    ;c,s.\n        DEFB    $38             ;;end-calc\n\n        CALL    L171E           ; routine STR-DATA fetches the stream off\n                                ; the stack and returns with the CHANS\n                                ; displacement in BC and HL addressing\n                                ; the STRMS data entry.\n        LD      A,B             ; test for zero which\n        OR      C               ; indicates the stream is closed.\n        JR      Z,L1756         ; skip forward to OPEN-1 if so.\n\n; if it is a system channel then it can re-attached.\n\n        EX      DE,HL           ; save STRMS address in DE.\n        LD      HL,($5C4F)      ; fetch CHANS.\n        ADD     HL,BC           ; add the offset to address the second\n                                ; byte of the channel.\n        INC     HL              ; skip over the\n        INC     HL              ; input routine.\n        INC     HL              ; and address the letter.\n        LD      A,(HL)          ; pick up the letter.\n        EX      DE,HL           ; save letter pointer and bring back\n                                ; the STRMS pointer.\n\n        CP      $4B             ; is it 'K' ?\n        JR      Z,L1756         ; forward to OPEN-1 if so\n\n        CP      $53             ; is it 'S' ?\n        JR      Z,L1756         ; forward to OPEN-1 if so\n\n        CP      $50             ; is it 'P' ?\n        JR      NZ,L1725        ; back to REPORT-Ob if not.\n                                ; to report 'Invalid stream'.\n\n; continue if one of the upper-case letters was found.\n; and rejoin here from above if stream was closed.\n\n;; OPEN-1\nL1756:  CALL    L175D           ; routine OPEN-2 opens the stream.\n\n; it now remains to update the STRMS variable.\n\n        LD      (HL),E          ; insert or overwrite the low byte.\n        INC     HL              ; address high byte in STRMS.\n        LD      (HL),D          ; insert or overwrite the high byte.\n        RET                     ; return.\n\n; -----------------\n; OPEN-2 Subroutine\n; -----------------\n; There is some point in coming here as, as well as once creating buffers,\n; this routine also sets flags.\n\n;; OPEN-2\nL175D:  PUSH    HL              ; * save the STRMS data entry pointer.\n        CALL    L2BF1           ; routine STK-FETCH now fetches the\n                                ; parameters of the channel string.\n                                ; start in DE, length in BC.\n\n        LD      A,B             ; test that it is not\n        OR      C               ; the null string.\n        JR      NZ,L1767        ; skip forward to OPEN-3 with 1 character\n                                ; or more!\n\n;; REPORT-Fb\nL1765:  RST     08H             ; ERROR-1\n        DEFB    $0E             ; Error Report: Invalid file name\n\n;; OPEN-3\nL1767:  PUSH    BC              ; save the length of the string.\n        LD      A,(DE)          ; pick up the first character.\n                                ; Note. There can be more than one character.\n        AND     $DF             ; make it upper-case.\n        LD      C,A             ; place it in C.\n        LD      HL,L177A        ; address: op-str-lu is loaded.\n        CALL    L16DC           ; routine INDEXER will search for letter.\n        JR      NC,L1765        ; back to REPORT-F if not found\n                                ; 'Invalid filename'\n\n        LD      C,(HL)          ; fetch the displacement to opening routine.\n        LD      B,$00           ; prepare to add.\n        ADD     HL,BC           ; now form address of opening routine.\n        POP     BC              ; restore the length of string.\n        JP      (HL)            ; now jump forward to the relevant routine.\n\n; -------------------------\n; OPEN stream look-up table\n; -------------------------\n; The open stream look-up table consists of matched pairs.\n; The channel letter is followed by an 8-bit displacement to the\n; associated stream-opening routine in this ROM.\n; The table requires a zero end-marker as the letter has been\n; provided by the user and not the operating system.\n\n;; op-str-lu\nL177A:  DEFB    'K', L1781-$-1  ; $06 offset to OPEN-K\n        DEFB    'S', L1785-$-1  ; $08 offset to OPEN-S\n        DEFB    'P', L1789-$-1  ; $0A offset to OPEN-P\n\n        DEFB    $00             ; end-marker.\n\n; ----------------------------\n; The Stream Opening Routines.\n; ----------------------------\n; These routines would have opened any buffers associated with the stream\n; before jumping forward to OPEN-END with the displacement value in E\n; and perhaps a modified value in BC. The strange pathing does seem to\n; provide for flexibility in this respect.\n;\n; There is no need to open the printer buffer as it is there already\n; even if you are still saving up for a ZX Printer or have moved onto\n; something bigger. In any case it would have to be created after\n; the system variables but apart from that it is a simple task\n; and all but one of the ROM routines can handle a buffer in that position.\n; (PR-ALL-6 would require an extra 3 bytes of code).\n; However it wouldn't be wise to have two streams attached to the ZX Printer\n; as you can now, so one assumes that if PR_CC_hi was non-zero then\n; the OPEN-P routine would have refused to attach a stream if another\n; stream was attached.\n\n; Something of significance is being passed to these ghost routines in the\n; second character. Strings 'RB', 'RT' perhaps or a drive/station number.\n; The routine would have to deal with that and exit to OPEN_END with BC\n; containing $0001 or more likely there would be an exit within the routine.\n; Anyway doesn't matter, these routines are long gone.\n\n; -----------------\n; OPEN-K Subroutine\n; -----------------\n; Open Keyboard stream.\n\n;; OPEN-K\nL1781:  LD      E,$01           ; 01 is offset to second byte of channel 'K'.\n        JR      L178B           ; forward to OPEN-END\n\n; -----------------\n; OPEN-S Subroutine\n; -----------------\n; Open Screen stream.\n\n;; OPEN-S\nL1785:  LD      E,$06           ; 06 is offset to 2nd byte of channel 'S'\n        JR      L178B           ; to OPEN-END\n\n; -----------------\n; OPEN-P Subroutine\n; -----------------\n; Open Printer stream.\n\n;; OPEN-P\nL1789:  LD      E,$10           ; 16d is offset to 2nd byte of channel 'P'\n\n;; OPEN-END\nL178B:  DEC     BC              ; the stored length of 'K','S','P' or\n                                ; whatever is now tested. ??\n        LD      A,B             ; test now if initial or residual length\n        OR      C               ; is one character.\n        JR      NZ,L1765        ; to REPORT-Fb 'Invalid file name' if not.\n\n        LD      D,A             ; load D with zero to form the displacement\n                                ; in the DE register.\n        POP     HL              ; * restore the saved STRMS pointer.\n        RET                     ; return to update STRMS entry thereby\n                                ; signaling stream is open.\n\n; ----------------------------------------\n; Handle CAT, ERASE, FORMAT, MOVE commands\n; ----------------------------------------\n; These just generate an error report as the ROM is 'incomplete'.\n;\n; Luckily this provides a mechanism for extending these in a shadow ROM\n; but without the powerful mechanisms set up in this ROM.\n; An instruction fetch on $0008 may page in a peripheral ROM,\n; e.g. the Sinclair Interface 1 ROM, to handle these commands.\n; However that wasn't the plan.\n; Development of this ROM continued for another three months until the cost\n; of replacing it and the manual became unfeasible.\n; The ultimate power of channels and streams died at birth.\n\n;; CAT-ETC\nL1793:  JR      L1725           ; to REPORT-Ob\n\n; -----------------\n; Perform AUTO-LIST\n; -----------------\n; This produces an automatic listing in the upper screen.\n\n;; AUTO-LIST\nL1795:  LD      ($5C3F),SP      ; save stack pointer in LIST_SP\n        LD      (IY+$02),$10    ; update TV_FLAG set bit 3\n        CALL    L0DAF           ; routine CL-ALL.\n        SET     0,(IY+$02)      ; update TV_FLAG  - signal lower screen in use\n\n        LD      B,(IY+$31)      ; fetch DF_SZ to B.\n        CALL    L0E44           ; routine CL-LINE clears lower display\n                                ; preserving B.\n        RES     0,(IY+$02)      ; update TV_FLAG  - signal main screen in use\n        SET     0,(IY+$30)      ; update FLAGS2 - signal will be necessary to\n                                ; clear main screen.\n        LD      HL,($5C49)      ; fetch E_PPC current edit line to HL.\n        LD      DE,($5C6C)      ; fetch S_TOP to DE, the current top line\n                                ; (initially zero)\n        AND     A               ; prepare for true subtraction.\n        SBC     HL,DE           ; subtract and\n        ADD     HL,DE           ; add back.\n        JR      C,L17E1         ; to AUTO-L-2 if S_TOP higher than E_PPC\n                                ; to set S_TOP to E_PPC\n\n        PUSH    DE              ; save the top line number.\n        CALL    L196E           ; routine LINE-ADDR gets address of E_PPC.\n        LD      DE,$02C0        ; prepare known number of characters in\n                                ; the default upper screen.\n        EX      DE,HL           ; offset to HL, program address to DE.\n        SBC     HL,DE           ; subtract high value from low to obtain\n                                ; negated result used in addition.\n        EX      (SP),HL         ; swap result with top line number on stack.\n        CALL    L196E           ; routine LINE-ADDR  gets address of that\n                                ; top line in HL and next line in DE.\n        POP     BC              ; restore the result to balance stack.\n\n;; AUTO-L-1\nL17CE:  PUSH    BC              ; save the result.\n        CALL    L19B8           ; routine NEXT-ONE gets address in HL of\n                                ; line after auto-line (in DE).\n        POP     BC              ; restore result.\n        ADD     HL,BC           ; compute back.\n        JR      C,L17E4         ; to AUTO-L-3 if line 'should' appear\n\n        EX      DE,HL           ; address of next line to HL.\n        LD      D,(HL)          ; get line\n        INC     HL              ; number\n        LD      E,(HL)          ; in DE.\n        DEC     HL              ; adjust back to start.\n        LD      ($5C6C),DE      ; update S_TOP.\n        JR      L17CE           ; to AUTO-L-1 until estimate reached.\n\n; ---\n\n; the jump was to here if S_TOP was greater than E_PPC\n\n;; AUTO-L-2\nL17E1:  LD      ($5C6C),HL      ; make S_TOP the same as E_PPC.\n\n; continue here with valid starting point from above or good estimate\n; from computation\n\n;; AUTO-L-3\nL17E4:  LD      HL,($5C6C)      ; fetch S_TOP line number to HL.\n        CALL    L196E           ; routine LINE-ADDR gets address in HL.\n                                ; address of next in DE.\n        JR      Z,L17ED         ; to AUTO-L-4 if line exists.\n\n        EX      DE,HL           ; else use address of next line.\n\n;; AUTO-L-4\nL17ED:  CALL    L1833           ; routine LIST-ALL                >>>\n\n; The return will be to here if no scrolling occurred\n\n        RES     4,(IY+$02)      ; update TV_FLAG  - signal no auto listing.\n        RET                     ; return.\n\n; ------------\n; Handle LLIST\n; ------------\n; A short form of LIST #3. The listing goes to stream 3 - default printer.\n\n;; LLIST\nL17F5:  LD      A,$03           ; the usual stream for ZX Printer\n        JR      L17FB           ; forward to LIST-1\n\n; -----------\n; Handle LIST\n; -----------\n; List to any stream.\n; Note. While a starting line can be specified it is\n; not possible to specify an end line.\n; Just listing a line makes it the current edit line.\n\n;; LIST\nL17F9:  LD      A,$02           ; default is stream 2 - the upper screen.\n\n;; LIST-1\nL17FB:  LD      (IY+$02),$00    ; the TV_FLAG is initialized with bit 0 reset\n                                ; indicating upper screen in use.\n        CALL    L2530           ; routine SYNTAX-Z - checking syntax ?\n        CALL    NZ,L1601        ; routine CHAN-OPEN if in run-time.\n\n        RST     18H             ; GET-CHAR\n        CALL    L2070           ; routine STR-ALTER will alter if '#'.\n        JR      C,L181F         ; forward to LIST-4 not a '#' .\n\n\n        RST     18H             ; GET-CHAR\n        CP      $3B             ; is it ';' ?\n        JR      Z,L1814         ; skip to LIST-2 if so.\n\n        CP      $2C             ; is it ',' ?\n        JR      NZ,L181A        ; forward to LIST-3 if neither separator.\n\n; we have, say,  LIST #15, and a number must follow the separator.\n\n;; LIST-2\nL1814:  RST     20H             ; NEXT-CHAR\n        CALL    L1C82           ; routine EXPT-1NUM\n        JR      L1822           ; forward to LIST-5\n\n; ---\n\n; the branch was here with just LIST #3 etc.\n\n;; LIST-3\nL181A:  CALL    L1CE6           ; routine USE-ZERO\n        JR      L1822           ; forward to LIST-5\n\n; ---\n\n; the branch was here with LIST\n\n;; LIST-4\nL181F:  CALL    L1CDE           ; routine FETCH-NUM checks if a number\n                                ; follows else uses zero.\n\n;; LIST-5\nL1822:  CALL    L1BEE           ; routine CHECK-END quits if syntax OK >>>\n\n        CALL    L1E99           ; routine FIND-INT2 fetches the number\n                                ; from the calculator stack in run-time.\n        LD      A,B             ; fetch high byte of line number and\n        AND     $3F             ; make less than $40 so that NEXT-ONE\n                                ; (from LINE-ADDR) doesn't lose context.\n                                ; Note. this is not satisfactory and the typo\n                                ; LIST 20000 will list an entirely different\n                                ; section than LIST 2000. Such typos are not\n                                ; available for checking if they are direct\n                                ; commands.\n\n        LD      H,A             ; transfer the modified\n        LD      L,C             ; line number to HL.\n        LD      ($5C49),HL      ; update E_PPC to new line number.\n        CALL    L196E           ; routine LINE-ADDR gets the address of the\n                                ; line.\n\n; This routine is called from AUTO-LIST\n\n;; LIST-ALL\nL1833:  LD      E,$01           ; signal current line not yet printed\n\n;; LIST-ALL-2\nL1835:  CALL    L1855           ; routine OUT-LINE outputs a BASIC line\n                                ; using PRINT-OUT and makes an early return\n                                ; when no more lines to print. >>>\n\n        RST     10H             ; PRINT-A prints the carriage return (in A)\n\n        BIT     4,(IY+$02)      ; test TV_FLAG  - automatic listing ?\n        JR      Z,L1835         ; back to LIST-ALL-2 if not\n                                ; (loop exit is via OUT-LINE)\n\n; continue here if an automatic listing required.\n\n        LD      A,($5C6B)       ; fetch DF_SZ lower display file size.\n        SUB     (IY+$4F)        ; subtract S_POSN_hi ithe current line number.\n        JR      NZ,L1835        ; back to LIST-ALL-2 if upper screen not full.\n\n        XOR     E               ; A contains zero, E contains one if the\n                                ; current edit line has not been printed\n                                ; or zero if it has (from OUT-LINE).\n        RET     Z               ; return if the screen is full and the line\n                                ; has been printed.\n\n; continue with automatic listings if the screen is full and the current\n; edit line is missing. OUT-LINE will scroll automatically.\n\n        PUSH    HL              ; save the pointer address.\n        PUSH    DE              ; save the E flag.\n        LD      HL,$5C6C        ; fetch S_TOP the rough estimate.\n        CALL    L190F           ; routine LN-FETCH updates S_TOP with\n                                ; the number of the next line.\n        POP     DE              ; restore the E flag.\n        POP     HL              ; restore the address of the next line.\n        JR      L1835           ; back to LIST-ALL-2.\n\n; ------------------------\n; Print a whole BASIC line\n; ------------------------\n; This routine prints a whole BASIC line and it is called\n; from LIST-ALL to output the line to current channel\n; and from ED-EDIT to 'sprint' the line to the edit buffer.\n\n;; OUT-LINE\nL1855:  LD      BC,($5C49)      ; fetch E_PPC the current line which may be\n                                ; unchecked and not exist.\n        CALL    L1980           ; routine CP-LINES finds match or line after.\n        LD      D,$3E           ; prepare cursor '>' in D.\n        JR      Z,L1865         ; to OUT-LINE1 if matched or line after.\n\n        LD      DE,$0000        ; put zero in D, to suppress line cursor.\n        RL      E               ; pick up carry in E if line before current\n                                ; leave E zero if same or after.\n\n;; OUT-LINE1\nL1865:  LD      (IY+$2D),E      ; save flag in BREG which is spare.\n        LD      A,(HL)          ; get high byte of line number.\n        CP      $40             ; is it too high ($2F is maximum possible) ?\n        POP     BC              ; drop the return address and\n        RET     NC              ; make an early return if so >>>\n\n        PUSH    BC              ; save return address\n        CALL    L1A28           ; routine OUT-NUM-2 to print addressed number\n                                ; with leading space.\n        INC     HL              ; skip low number byte.\n        INC     HL              ; and the two\n        INC     HL              ; length bytes.\n        RES     0,(IY+$01)      ; update FLAGS - signal leading space required.\n        LD      A,D             ; fetch the cursor.\n        AND     A               ; test for zero.\n        JR      Z,L1881         ; to OUT-LINE3 if zero.\n\n\n        RST     10H             ; PRINT-A prints '>' the current line cursor.\n\n; this entry point is called from ED-COPY\n\n;; OUT-LINE2\nL187D:  SET     0,(IY+$01)      ; update FLAGS - suppress leading space.\n\n;; OUT-LINE3\nL1881:  PUSH    DE              ; save flag E for a return value.\n        EX      DE,HL           ; save HL address in DE.\n        RES     2,(IY+$30)      ; update FLAGS2 - signal NOT in QUOTES.\n\n        LD      HL,$5C3B        ; point to FLAGS.\n        RES     2,(HL)          ; signal 'K' mode. (starts before keyword)\n        BIT     5,(IY+$37)      ; test FLAGX - input mode ?\n        JR      Z,L1894         ; forward to OUT-LINE4 if not.\n\n        SET     2,(HL)          ; signal 'L' mode. (used for input)\n\n;; OUT-LINE4\nL1894:  LD      HL,($5C5F)      ; fetch X_PTR - possibly the error pointer\n                                ; address.\n        AND     A               ; clear the carry flag.\n        SBC     HL,DE           ; test if an error address has been reached.\n        JR      NZ,L18A1        ; forward to OUT-LINE5 if not.\n\n        LD      A,$3F           ; load A with '?' the error marker.\n        CALL    L18C1           ; routine OUT-FLASH to print flashing marker.\n\n;; OUT-LINE5\nL18A1:  CALL    L18E1           ; routine OUT-CURS will print the cursor if\n                                ; this is the right position.\n        EX      DE,HL           ; restore address pointer to HL.\n        LD      A,(HL)          ; fetch the addressed character.\n        CALL    L18B6           ; routine NUMBER skips a hidden floating\n                                ; point number if present.\n        INC     HL              ; now increment the pointer.\n        CP      $0D             ; is character end-of-line ?\n        JR      Z,L18B4         ; to OUT-LINE6, if so, as line is finished.\n\n        EX      DE,HL           ; save the pointer in DE.\n        CALL    L1937           ; routine OUT-CHAR to output character/token.\n\n        JR      L1894           ; back to OUT-LINE4 until entire line is done.\n\n; ---\n\n;; OUT-LINE6\nL18B4:  POP     DE              ; bring back the flag E, zero if current\n                                ; line printed else 1 if still to print.\n        RET                     ; return with A holding $0D\n\n; -------------------------\n; Check for a number marker\n; -------------------------\n; this subroutine is called from two processes. while outputting BASIC lines\n; and while searching statements within a BASIC line.\n; during both, this routine will pass over an invisible number indicator\n; and the five bytes floating-point number that follows it.\n; Note that this causes floating point numbers to be stripped from\n; the BASIC line when it is fetched to the edit buffer by OUT_LINE.\n; the number marker also appears after the arguments of a DEF FN statement\n; and may mask old 5-byte string parameters.\n\n;; NUMBER\nL18B6:  CP      $0E             ; character fourteen ?\n        RET     NZ              ; return if not.\n\n        INC     HL              ; skip the character\n        INC     HL              ; and five bytes\n        INC     HL              ; following.\n        INC     HL              ;\n        INC     HL              ;\n        INC     HL              ;\n        LD      A,(HL)          ; fetch the following character\n        RET                     ; for return value.\n\n; --------------------------\n; Print a flashing character\n; --------------------------\n; This subroutine is called from OUT-LINE to print a flashing error\n; marker '?' or from the next routine to print a flashing cursor e.g. 'L'.\n; However, this only gets called from OUT-LINE when printing the edit line\n; or the input buffer to the lower screen so a direct call to $09F4 can\n; be used, even though out-line outputs to other streams.\n; In fact the alternate set is used for the whole routine.\n\n;; OUT-FLASH\nL18C1:  EXX                     ; switch in alternate set\n\n        LD      HL,($5C8F)      ; fetch L = ATTR_T, H = MASK-T\n        PUSH    HL              ; save masks.\n        RES     7,H             ; reset flash mask bit so active.\n        SET     7,L             ; make attribute FLASH.\n        LD      ($5C8F),HL      ; resave ATTR_T and MASK-T\n\n        LD      HL,$5C91        ; address P_FLAG\n        LD      D,(HL)          ; fetch to D\n        PUSH    DE              ; and save.\n        LD      (HL),$00        ; clear inverse, over, ink/paper 9\n\n        CALL    L09F4           ; routine PRINT-OUT outputs character\n                                ; without the need to vector via RST 10.\n\n        POP     HL              ; pop P_FLAG to H.\n        LD      (IY+$57),H      ; and restore system variable P_FLAG.\n        POP     HL              ; restore temporary masks\n        LD      ($5C8F),HL      ; and restore system variables ATTR_T/MASK_T\n\n        EXX                     ; switch back to main set\n        RET                     ; return\n\n; ----------------\n; Print the cursor\n; ----------------\n; This routine is called before any character is output while outputting\n; a BASIC line or the input buffer. This includes listing to a printer\n; or screen, copying a BASIC line to the edit buffer and printing the\n; input buffer or edit buffer to the lower screen. It is only in the\n; latter two cases that it has any relevance and in the last case it\n; performs another very important function also.\n\n;; OUT-CURS\nL18E1:  LD      HL,($5C5B)      ; fetch K_CUR the current cursor address\n        AND     A               ; prepare for true subtraction.\n        SBC     HL,DE           ; test against pointer address in DE and\n        RET     NZ              ; return if not at exact position.\n\n; the value of MODE, maintained by KEY-INPUT, is tested and if non-zero\n; then this value 'E' or 'G' will take precedence.\n\n        LD      A,($5C41)       ; fetch MODE  0='KLC', 1='E', 2='G'.\n        RLC     A               ; double the value and set flags.\n        JR      Z,L18F3         ; to OUT-C-1 if still zero ('KLC').\n\n        ADD     A,$43           ; add 'C' - will become 'E' if originally 1\n                                ; or 'G' if originally 2.\n        JR      L1909           ; forward to OUT-C-2 to print.\n\n; ---\n\n; If mode was zero then, while printing a BASIC line, bit 2 of flags has been\n; set if 'THEN' or ':' was encountered as a main character and reset otherwise.\n; This is now used to determine if the 'K' cursor is to be printed but this\n; transient state is also now transferred permanently to bit 3 of FLAGS\n; to let the interrupt routine know how to decode the next key.\n\n;; OUT-C-1\nL18F3:  LD      HL,$5C3B        ; Address FLAGS\n        RES     3,(HL)          ; signal 'K' mode initially.\n        LD      A,$4B           ; prepare letter 'K'.\n        BIT     2,(HL)          ; test FLAGS - was the\n                                ; previous main character ':' or 'THEN' ?\n        JR      Z,L1909         ; forward to OUT-C-2 if so to print.\n\n        SET     3,(HL)          ; signal 'L' mode to interrupt routine.\n                                ; Note. transient bit has been made permanent.\n        INC     A               ; augment from 'K' to 'L'.\n\n        BIT     3,(IY+$30)      ; test FLAGS2 - consider caps lock ?\n                                ; which is maintained by KEY-INPUT.\n        JR      Z,L1909         ; forward to OUT-C-2 if not set to print.\n\n        LD      A,$43           ; alter 'L' to 'C'.\n\n;; OUT-C-2\nL1909:  PUSH    DE              ; save address pointer but OK as OUT-FLASH\n                                ; uses alternate set without RST 10.\n\n        CALL    L18C1           ; routine OUT-FLASH to print.\n\n        POP     DE              ; restore and\n        RET                     ; return.\n\n; ----------------------------\n; Get line number of next line\n; ----------------------------\n; These two subroutines are called while editing.\n; This entry point is from ED-DOWN with HL addressing E_PPC\n; to fetch the next line number.\n; Also from AUTO-LIST with HL addressing S_TOP just to update S_TOP\n; with the value of the next line number. It gets fetched but is discarded.\n; These routines never get called while the editor is being used for input.\n\n;; LN-FETCH\nL190F:  LD      E,(HL)          ; fetch low byte\n        INC     HL              ; address next\n        LD      D,(HL)          ; fetch high byte.\n        PUSH    HL              ; save system variable hi pointer.\n        EX      DE,HL           ; line number to HL,\n        INC     HL              ; increment as a starting point.\n        CALL    L196E           ; routine LINE-ADDR gets address in HL.\n        CALL    L1695           ; routine LINE-NO gets line number in DE.\n        POP     HL              ; restore system variable hi pointer.\n\n; This entry point is from the ED-UP with HL addressing E_PPC_hi\n\n;; LN-STORE\nL191C:  BIT     5,(IY+$37)      ; test FLAGX - input mode ?\n        RET     NZ              ; return if so.\n                                ; Note. above already checked by ED-UP/ED-DOWN.\n\n        LD      (HL),D          ; save high byte of line number.\n        DEC     HL              ; address lower\n        LD      (HL),E          ; save low byte of line number.\n        RET                     ; return.\n\n; -----------------------------------------\n; Outputting numbers at start of BASIC line\n; -----------------------------------------\n; This routine entered at OUT-SP-NO is used to compute then output the first\n; three digits of a 4-digit BASIC line printing a space if necessary.\n; The line number, or residual part, is held in HL and the BC register\n; holds a subtraction value -1000, -100 or -10.\n; Note. for example line number 200 -\n; space(out_char), 2(out_code), 0(out_char) final number always out-code.\n\n;; OUT-SP-2\nL1925:  LD      A,E             ; will be space if OUT-CODE not yet called.\n                                ; or $FF if spaces are suppressed.\n                                ; else $30 ('0').\n                                ; (from the first instruction at OUT-CODE)\n                                ; this guy is just too clever.\n        AND     A               ; test bit 7 of A.\n        RET     M               ; return if $FF, as leading spaces not\n                                ; required. This is set when printing line\n                                ; number and statement in MAIN-5.\n\n        JR      L1937           ; forward to exit via OUT-CHAR.\n\n; ---\n\n; -> the single entry point.\n\n;; OUT-SP-NO\nL192A:  XOR     A               ; initialize digit to 0\n\n;; OUT-SP-1\nL192B:  ADD     HL,BC           ; add negative number to HL.\n        INC     A               ; increment digit\n        JR      C,L192B         ; back to OUT-SP-1 until no carry from\n                                ; the addition.\n\n        SBC     HL,BC           ; cancel the last addition\n        DEC     A               ; and decrement the digit.\n        JR      Z,L1925         ; back to OUT-SP-2 if it is zero.\n\n        JP      L15EF           ; jump back to exit via OUT-CODE.    ->\n\n\n; -------------------------------------\n; Outputting characters in a BASIC line\n; -------------------------------------\n; This subroutine ...\n\n;; OUT-CHAR\nL1937:  CALL    L2D1B           ; routine NUMERIC tests if it is a digit ?\n        JR      NC,L196C        ; to OUT-CH-3 to print digit without\n                                ; changing mode. Will be 'K' mode if digits\n                                ; are at beginning of edit line.\n\n        CP      $21             ; less than quote character ?\n        JR      C,L196C         ; to OUT-CH-3 to output controls and space.\n\n        RES     2,(IY+$01)      ; initialize FLAGS to 'K' mode and leave\n                                ; unchanged if this character would precede\n                                ; a keyword.\n\n        CP      $CB             ; is character 'THEN' token ?\n        JR      Z,L196C         ; to OUT-CH-3 to output if so.\n\n        CP      $3A             ; is it ':' ?\n        JR      NZ,L195A        ; to OUT-CH-1 if not statement separator\n                                ; to change mode back to 'L'.\n\n        BIT     5,(IY+$37)      ; FLAGX  - Input Mode ??\n        JR      NZ,L1968        ; to OUT-CH-2 if in input as no statements.\n                                ; Note. this check should seemingly be at\n                                ; the start. Commands seem inappropriate in\n                                ; INPUT mode and are rejected by the syntax\n                                ; checker anyway.\n                                ; unless INPUT LINE is being used.\n\n        BIT     2,(IY+$30)      ; test FLAGS2 - is the ':' within quotes ?\n        JR      Z,L196C         ; to OUT-CH-3 if ':' is outside quoted text.\n\n        JR      L1968           ; to OUT-CH-2 as ':' is within quotes\n\n; ---\n\n;; OUT-CH-1\nL195A:  CP      $22             ; is it quote character '\"'  ?\n        JR      NZ,L1968        ; to OUT-CH-2 with others to set 'L' mode.\n\n        PUSH    AF              ; save character.\n        LD      A,($5C6A)       ; fetch FLAGS2.\n        XOR     $04             ; toggle the quotes flag.\n        LD      ($5C6A),A       ; update FLAGS2\n        POP     AF              ; and restore character.\n\n;; OUT-CH-2\nL1968:  SET     2,(IY+$01)      ; update FLAGS - signal L mode if the cursor\n                                ; is next.\n\n;; OUT-CH-3\nL196C:  RST     10H             ; PRINT-A vectors the character to\n                                ; channel 'S', 'K', 'R' or 'P'.\n        RET                     ; return.\n\n; -------------------------------------------\n; Get starting address of line, or line after\n; -------------------------------------------\n; This routine is used often to get the address, in HL, of a BASIC line\n; number supplied in HL, or failing that the address of the following line\n; and the address of the previous line in DE.\n\n;; LINE-ADDR\nL196E:  PUSH    HL              ; save line number in HL register\n        LD      HL,($5C53)      ; fetch start of program from PROG\n        LD      D,H             ; transfer address to\n        LD      E,L             ; the DE register pair.\n\n;; LINE-AD-1\nL1974:  POP     BC              ; restore the line number to BC\n        CALL    L1980           ; routine CP-LINES compares with that\n                                ; addressed by HL\n        RET     NC              ; return if line has been passed or matched.\n                                ; if NZ, address of previous is in DE\n\n        PUSH    BC              ; save the current line number\n        CALL    L19B8           ; routine NEXT-ONE finds address of next\n                                ; line number in DE, previous in HL.\n        EX      DE,HL           ; switch so next in HL\n        JR      L1974           ; back to LINE-AD-1 for another comparison\n\n; --------------------\n; Compare line numbers\n; --------------------\n; This routine compares a line number supplied in BC with an addressed\n; line number pointed to by HL.\n\n;; CP-LINES\nL1980:  LD      A,(HL)          ; Load the high byte of line number and\n        CP      B               ; compare with that of supplied line number.\n        RET     NZ              ; return if yet to match (carry will be set).\n\n        INC     HL              ; address low byte of\n        LD      A,(HL)          ; number and pick up in A.\n        DEC     HL              ; step back to first position.\n        CP      C               ; now compare.\n        RET                     ; zero set if exact match.\n                                ; carry set if yet to match.\n                                ; no carry indicates a match or\n                                ; next available BASIC line or\n                                ; program end marker.\n\n; -------------------\n; Find each statement\n; -------------------\n; The single entry point EACH-STMT is used to\n; 1) To find the D'th statement in a line.\n; 2) To find a token in held E.\n\n;; not-used\nL1988:  INC     HL              ;\n        INC     HL              ;\n        INC     HL              ;\n\n; -> entry point.\n\n;; EACH-STMT\nL198B:  LD      ($5C5D),HL      ; save HL in CH_ADD\n        LD      C,$00           ; initialize quotes flag\n\n;; EACH-S-1\nL1990:  DEC     D               ; decrease statement count\n        RET     Z               ; return if zero\n\n\n        RST     20H             ; NEXT-CHAR\n        CP      E               ; is it the search token ?\n        JR      NZ,L199A        ; forward to EACH-S-3 if not\n\n        AND     A               ; clear carry\n        RET                     ; return signalling success.\n\n; ---\n\n;; EACH-S-2\nL1998:  INC     HL              ; next address\n        LD      A,(HL)          ; next character\n\n;; EACH-S-3\nL199A:  CALL    L18B6           ; routine NUMBER skips if number marker\n        LD      ($5C5D),HL      ; save in CH_ADD\n        CP      $22             ; is it quotes '\"' ?\n        JR      NZ,L19A5        ; to EACH-S-4 if not\n\n        DEC     C               ; toggle bit 0 of C\n\n;; EACH-S-4\nL19A5:  CP      $3A             ; is it ':'\n        JR      Z,L19AD         ; to EACH-S-5\n\n        CP      $CB             ; 'THEN'\n        JR      NZ,L19B1        ; to EACH-S-6\n\n;; EACH-S-5\nL19AD:  BIT     0,C             ; is it in quotes\n        JR      Z,L1990         ; to EACH-S-1 if not\n\n;; EACH-S-6\nL19B1:  CP      $0D             ; end of line ?\n        JR      NZ,L1998        ; to EACH-S-2\n\n        DEC     D               ; decrease the statement counter\n                                ; which should be zero else\n                                ; 'Statement Lost'.\n        SCF                     ; set carry flag - not found\n        RET                     ; return\n\n; -----------------------------------------------------------------------\n; Storage of variables. For full details - see chapter 24.\n; ZX Spectrum BASIC Programming by Steven Vickers 1982.\n; It is bits 7-5 of the first character of a variable that allow\n; the six types to be distinguished. Bits 4-0 are the reduced letter.\n; So any variable name is higher that $3F and can be distinguished\n; also from the variables area end-marker $80.\n;\n; 76543210 meaning                               brief outline of format.\n; -------- ------------------------              -----------------------\n; 010      string variable.                      2 byte length + contents.\n; 110      string array.                         2 byte length + contents.\n; 100      array of numbers.                     2 byte length + contents.\n; 011      simple numeric variable.              5 bytes.\n; 101      variable length named numeric.        5 bytes.\n; 111      for-next loop variable.               18 bytes.\n; 10000000 the variables area end-marker.\n;\n; Note. any of the above seven will serve as a program end-marker.\n;\n; -----------------------------------------------------------------------\n\n; ------------\n; Get next one\n; ------------\n; This versatile routine is used to find the address of the next line\n; in the program area or the next variable in the variables area.\n; The reason one routine is made to handle two apparently unrelated tasks\n; is that it can be called indiscriminately when merging a line or a\n; variable.\n\n;; NEXT-ONE\nL19B8:  PUSH    HL              ; save the pointer address.\n        LD      A,(HL)          ; get first byte.\n        CP      $40             ; compare with upper limit for line numbers.\n        JR      C,L19D5         ; forward to NEXT-O-3 if within BASIC area.\n\n; the continuation here is for the next variable unless the supplied\n; line number was erroneously over 16383. see RESTORE command.\n\n        BIT     5,A             ; is it a string or an array variable ?\n        JR      Z,L19D6         ; forward to NEXT-O-4 to compute length.\n\n        ADD     A,A             ; test bit 6 for single-character variables.\n        JP      M,L19C7         ; forward to NEXT-O-1 if so\n\n        CCF                     ; clear the carry for long-named variables.\n                                ; it remains set for for-next loop variables.\n\n;; NEXT-O-1\nL19C7:  LD      BC,$0005        ; set BC to 5 for floating point number\n        JR      NC,L19CE        ; forward to NEXT-O-2 if not a for/next\n                                ; variable.\n\n        LD      C,$12           ; set BC to eighteen locations.\n                                ; value, limit, step, line and statement.\n\n; now deal with long-named variables\n\n;; NEXT-O-2\nL19CE:  RLA                     ; test if character inverted. carry will also\n                                ; be set for single character variables\n        INC     HL              ; address next location.\n        LD      A,(HL)          ; and load character.\n        JR      NC,L19CE        ; back to NEXT-O-2 if not inverted bit.\n                                ; forward immediately with single character\n                                ; variable names.\n\n        JR      L19DB           ; forward to NEXT-O-5 to add length of\n                                ; floating point number(s etc.).\n\n; ---\n\n; this branch is for line numbers.\n\n;; NEXT-O-3\nL19D5:  INC     HL              ; increment pointer to low byte of line no.\n\n; strings and arrays rejoin here\n\n;; NEXT-O-4\nL19D6:  INC     HL              ; increment to address the length low byte.\n        LD      C,(HL)          ; transfer to C and\n        INC     HL              ; point to high byte of length.\n        LD      B,(HL)          ; transfer that to B\n        INC     HL              ; point to start of BASIC/variable contents.\n\n; the three types of numeric variables rejoin here\n\n;; NEXT-O-5\nL19DB:  ADD     HL,BC           ; add the length to give address of next\n                                ; line/variable in HL.\n        POP     DE              ; restore previous address to DE.\n\n; ------------------\n; Difference routine\n; ------------------\n; This routine terminates the above routine and is also called from the\n; start of the next routine to calculate the length to reclaim.\n\n;; DIFFER\nL19DD:  AND     A               ; prepare for true subtraction.\n        SBC     HL,DE           ; subtract the two pointers.\n        LD      B,H             ; transfer result\n        LD      C,L             ; to BC register pair.\n        ADD     HL,DE           ; add back\n        EX      DE,HL           ; and switch pointers\n        RET                     ; return values are the length of area in BC,\n                                ; low pointer (previous) in HL,\n                                ; high pointer (next) in DE.\n\n; -----------------------\n; Handle reclaiming space\n; -----------------------\n;\n\n;; RECLAIM-1\nL19E5:  CALL    L19DD           ; routine DIFFER immediately above\n\n;; RECLAIM-2\nL19E8:  PUSH    BC              ;\n\n        LD      A,B             ;\n        CPL                     ;\n        LD      B,A             ;\n        LD      A,C             ;\n        CPL                     ;\n        LD      C,A             ;\n        INC     BC              ;\n\n        CALL    L1664           ; routine POINTERS\n        EX      DE,HL           ;\n        POP     HL              ;\n\n        ADD     HL,DE           ;\n        PUSH    DE              ;\n        LDIR                    ; copy bytes\n\n        POP     HL              ;\n        RET                     ;\n\n; ----------------------------------------\n; Read line number of line in editing area\n; ----------------------------------------\n; This routine reads a line number in the editing area returning the number\n; in the BC register or zero if no digits exist before commands.\n; It is called from LINE-SCAN to check the syntax of the digits.\n; It is called from MAIN-3 to extract the line number in preparation for\n; inclusion of the line in the BASIC program area.\n;\n; Interestingly the calculator stack is moved from its normal place at the\n; end of dynamic memory to an adequate area within the system variables area.\n; This ensures that in a low memory situation, that valid line numbers can\n; be extracted without raising an error and that memory can be reclaimed\n; by deleting lines. If the stack was in its normal place then a situation\n; arises whereby the Spectrum becomes locked with no means of reclaiming space.\n\n;; E-LINE-NO\nL19FB:  LD      HL,($5C59)      ; load HL from system variable E_LINE.\n\n        DEC     HL              ; decrease so that NEXT_CHAR can be used\n                                ; without skipping the first digit.\n\n        LD      ($5C5D),HL      ; store in the system variable CH_ADD.\n\n        RST     20H             ; NEXT-CHAR skips any noise and white-space\n                                ; to point exactly at the first digit.\n\n        LD      HL,$5C92        ; use MEM-0 as a temporary calculator stack\n                                ; an overhead of three locations are needed.\n        LD      ($5C65),HL      ; set new STKEND.\n\n        CALL    L2D3B           ; routine INT-TO-FP will read digits till\n                                ; a non-digit found.\n        CALL    L2DA2           ; routine FP-TO-BC will retrieve number\n                                ; from stack at membot.\n        JR      C,L1A15         ; forward to E-L-1 if overflow i.e. > 65535.\n                                ; 'Nonsense in BASIC'\n\n        LD      HL,$D8F0        ; load HL with value -9999\n        ADD     HL,BC           ; add to line number in BC\n\n;; E-L-1\nL1A15:  JP      C,L1C8A         ; to REPORT-C 'Nonsense in BASIC' if over.\n                                ; Note. As ERR_SP points to ED_ERROR\n                                ; the report is never produced although\n                                ; the RST $08 will update X_PTR leading to\n                                ; the error marker being displayed when\n                                ; the ED_LOOP is reiterated.\n                                ; in fact, since it is immediately\n                                ; cancelled, any report will do.\n\n; a line in the range 0 - 9999 has been entered.\n\n        JP      L16C5           ; jump back to SET-STK to set the calculator\n                                ; stack back to its normal place and exit\n                                ; from there.\n\n; ---------------------------------\n; Report and line number outputting\n; ---------------------------------\n; Entry point OUT-NUM-1 is used by the Error Reporting code to print\n; the line number and later the statement number held in BC.\n; If the statement was part of a direct command then -2 is used as a\n; dummy line number so that zero will be printed in the report.\n; This routine is also used to print the exponent of E-format numbers.\n;\n; Entry point OUT-NUM-2 is used from OUT-LINE to output the line number\n; addressed by HL with leading spaces if necessary.\n\n;; OUT-NUM-1\nL1A1B:  PUSH    DE              ; save the\n        PUSH    HL              ; registers.\n        XOR     A               ; set A to zero.\n        BIT     7,B             ; is the line number minus two ?\n        JR      NZ,L1A42        ; forward to OUT-NUM-4 if so to print zero\n                                ; for a direct command.\n\n        LD      H,B             ; transfer the\n        LD      L,C             ; number to HL.\n        LD      E,$FF           ; signal 'no leading zeros'.\n        JR      L1A30           ; forward to continue at OUT-NUM-3\n\n; ---\n\n; from OUT-LINE - HL addresses line number.\n\n;; OUT-NUM-2\nL1A28:  PUSH    DE              ; save flags\n        LD      D,(HL)          ; high byte to D\n        INC     HL              ; address next\n        LD      E,(HL)          ; low byte to E\n        PUSH    HL              ; save pointer\n        EX      DE,HL           ; transfer number to HL\n        LD      E,$20           ; signal 'output leading spaces'\n\n;; OUT-NUM-3\nL1A30:  LD      BC,$FC18        ; value -1000\n        CALL    L192A           ; routine OUT-SP-NO outputs space or number\n        LD      BC,$FF9C        ; value -100\n        CALL    L192A           ; routine OUT-SP-NO\n        LD      C,$F6           ; value -10 ( B is still $FF )\n        CALL    L192A           ; routine OUT-SP-NO\n        LD      A,L             ; remainder to A.\n\n;; OUT-NUM-4\nL1A42:  CALL    L15EF           ; routine OUT-CODE for final digit.\n                                ; else report code zero wouldn't get\n                                ; printed.\n        POP     HL              ; restore the\n        POP     DE              ; registers and\n        RET                     ; return.\n\n\n;***************************************************\n;** Part 7. BASIC LINE AND COMMAND INTERPRETATION **\n;***************************************************\n\n; ----------------\n; The offset table\n; ----------------\n; The BASIC interpreter has found a command code $CE - $FF\n; which is then reduced to range $00 - $31 and added to the base address\n; of this table to give the address of an offset which, when added to\n; the offset therein, gives the location in the following parameter table\n; where a list of class codes, separators and addresses relevant to the\n; command exists.\n\n;; offst-tbl\nL1A48:  DEFB    L1AF9 - $       ; B1 offset to Address: P-DEF-FN\n        DEFB    L1B14 - $       ; CB offset to Address: P-CAT\n        DEFB    L1B06 - $       ; BC offset to Address: P-FORMAT\n        DEFB    L1B0A - $       ; BF offset to Address: P-MOVE\n        DEFB    L1B10 - $       ; C4 offset to Address: P-ERASE\n        DEFB    L1AFC - $       ; AF offset to Address: P-OPEN\n        DEFB    L1B02 - $       ; B4 offset to Address: P-CLOSE\n        DEFB    L1AE2 - $       ; 93 offset to Address: P-MERGE\n        DEFB    L1AE1 - $       ; 91 offset to Address: P-VERIFY\n        DEFB    L1AE3 - $       ; 92 offset to Address: P-BEEP\n        DEFB    L1AE7 - $       ; 95 offset to Address: P-CIRCLE\n        DEFB    L1AEB - $       ; 98 offset to Address: P-INK\n        DEFB    L1AEC - $       ; 98 offset to Address: P-PAPER\n        DEFB    L1AED - $       ; 98 offset to Address: P-FLASH\n        DEFB    L1AEE - $       ; 98 offset to Address: P-BRIGHT\n        DEFB    L1AEF - $       ; 98 offset to Address: P-INVERSE\n        DEFB    L1AF0 - $       ; 98 offset to Address: P-OVER\n        DEFB    L1AF1 - $       ; 98 offset to Address: P-OUT\n        DEFB    L1AD9 - $       ; 7F offset to Address: P-LPRINT\n        DEFB    L1ADC - $       ; 81 offset to Address: P-LLIST\n        DEFB    L1A8A - $       ; 2E offset to Address: P-STOP\n        DEFB    L1AC9 - $       ; 6C offset to Address: P-READ\n        DEFB    L1ACC - $       ; 6E offset to Address: P-DATA\n        DEFB    L1ACF - $       ; 70 offset to Address: P-RESTORE\n        DEFB    L1AA8 - $       ; 48 offset to Address: P-NEW\n        DEFB    L1AF5 - $       ; 94 offset to Address: P-BORDER\n        DEFB    L1AB8 - $       ; 56 offset to Address: P-CONT\n        DEFB    L1AA2 - $       ; 3F offset to Address: P-DIM\n        DEFB    L1AA5 - $       ; 41 offset to Address: P-REM\n        DEFB    L1A90 - $       ; 2B offset to Address: P-FOR\n        DEFB    L1A7D - $       ; 17 offset to Address: P-GO-TO\n        DEFB    L1A86 - $       ; 1F offset to Address: P-GO-SUB\n        DEFB    L1A9F - $       ; 37 offset to Address: P-INPUT\n        DEFB    L1AE0 - $       ; 77 offset to Address: P-LOAD\n        DEFB    L1AAE - $       ; 44 offset to Address: P-LIST\n        DEFB    L1A7A - $       ; 0F offset to Address: P-LET\n        DEFB    L1AC5 - $       ; 59 offset to Address: P-PAUSE\n        DEFB    L1A98 - $       ; 2B offset to Address: P-NEXT\n        DEFB    L1AB1 - $       ; 43 offset to Address: P-POKE\n        DEFB    L1A9C - $       ; 2D offset to Address: P-PRINT\n        DEFB    L1AC1 - $       ; 51 offset to Address: P-PLOT\n        DEFB    L1AAB - $       ; 3A offset to Address: P-RUN\n        DEFB    L1ADF - $       ; 6D offset to Address: P-SAVE\n        DEFB    L1AB5 - $       ; 42 offset to Address: P-RANDOM\n        DEFB    L1A81 - $       ; 0D offset to Address: P-IF\n        DEFB    L1ABE - $       ; 49 offset to Address: P-CLS\n        DEFB    L1AD2 - $       ; 5C offset to Address: P-DRAW\n        DEFB    L1ABB - $       ; 44 offset to Address: P-CLEAR\n        DEFB    L1A8D - $       ; 15 offset to Address: P-RETURN\n        DEFB    L1AD6 - $       ; 5D offset to Address: P-COPY\n\n\n; -------------------------------\n; The parameter or \"Syntax\" table\n; -------------------------------\n; For each command there exists a variable list of parameters.\n; If the character is greater than a space it is a required separator.\n; If less, then it is a command class in the range 00 - 0B.\n; Note that classes 00, 03 and 05 will fetch the addresses from this table.\n; Some classes e.g. 07 and 0B have the same address in all invocations\n; and the command is re-computed from the low-byte of the parameter address.\n; Some e.g. 02 are only called once so a call to the command is made from\n; within the class routine rather than holding the address within the table.\n; Some class routines check syntax entirely and some leave this task for the\n; command itself.\n; Others for example CIRCLE (x,y,z) check the first part (x,y) using the\n; class routine and the final part (,z) within the command.\n; The last few commands appear to have been added in a rush but their syntax\n; is rather simple e.g. MOVE \"M1\",\"M2\"\n\n;; P-LET\nL1A7A:  DEFB    $01             ; Class-01 - A variable is required.\n        DEFB    $3D             ; Separator:  '='\n        DEFB    $02             ; Class-02 - An expression, numeric or string,\n                                ; must follow.\n\n;; P-GO-TO\nL1A7D:  DEFB    $06             ; Class-06 - A numeric expression must follow.\n        DEFB    $00             ; Class-00 - No further operands.\n        DEFW    L1E67           ; Address: $1E67; Address: GO-TO\n\n;; P-IF\nL1A81:  DEFB    $06             ; Class-06 - A numeric expression must follow.\n        DEFB    $CB             ; Separator:  'THEN'\n        DEFB    $05             ; Class-05 - Variable syntax checked\n                                ; by routine.\n        DEFW    L1CF0           ; Address: $1CF0; Address: IF\n\n;; P-GO-SUB\nL1A86:  DEFB    $06             ; Class-06 - A numeric expression must follow.\n        DEFB    $00             ; Class-00 - No further operands.\n        DEFW    L1EED           ; Address: $1EED; Address: GO-SUB\n\n;; P-STOP\nL1A8A:  DEFB    $00             ; Class-00 - No further operands.\n        DEFW    L1CEE           ; Address: $1CEE; Address: STOP\n\n;; P-RETURN\nL1A8D:  DEFB    $00             ; Class-00 - No further operands.\n        DEFW    L1F23           ; Address: $1F23; Address: RETURN\n\n;; P-FOR\nL1A90:  DEFB    $04             ; Class-04 - A single character variable must\n                                ; follow.\n        DEFB    $3D             ; Separator:  '='\n        DEFB    $06             ; Class-06 - A numeric expression must follow.\n        DEFB    $CC             ; Separator:  'TO'\n        DEFB    $06             ; Class-06 - A numeric expression must follow.\n        DEFB    $05             ; Class-05 - Variable syntax checked\n                                ; by routine.\n        DEFW    L1D03           ; Address: $1D03; Address: FOR\n\n;; P-NEXT\nL1A98:  DEFB    $04             ; Class-04 - A single character variable must\n                                ; follow.\n        DEFB    $00             ; Class-00 - No further operands.\n        DEFW    L1DAB           ; Address: $1DAB; Address: NEXT\n\n;; P-PRINT\nL1A9C:  DEFB    $05             ; Class-05 - Variable syntax checked entirely\n                                ; by routine.\n        DEFW    L1FCD           ; Address: $1FCD; Address: PRINT\n\n;; P-INPUT\nL1A9F:  DEFB    $05             ; Class-05 - Variable syntax checked entirely\n                                ; by routine.\n        DEFW    L2089           ; Address: $2089; Address: INPUT\n\n;; P-DIM\nL1AA2:  DEFB    $05             ; Class-05 - Variable syntax checked entirely\n                                ; by routine.\n        DEFW    L2C02           ; Address: $2C02; Address: DIM\n\n;; P-REM\nL1AA5:  DEFB    $05             ; Class-05 - Variable syntax checked entirely\n                                ; by routine.\n        DEFW    L1BB2           ; Address: $1BB2; Address: REM\n\n;; P-NEW\nL1AA8:  DEFB    $00             ; Class-00 - No further operands.\n        DEFW    L11B7           ; Address: $11B7; Address: NEW\n\n;; P-RUN\nL1AAB:  DEFB    $03             ; Class-03 - A numeric expression may follow\n                                ; else default to zero.\n        DEFW    L1EA1           ; Address: $1EA1; Address: RUN\n\n;; P-LIST\nL1AAE:  DEFB    $05             ; Class-05 - Variable syntax checked entirely\n                                ; by routine.\n        DEFW    L17F9           ; Address: $17F9; Address: LIST\n\n;; P-POKE\nL1AB1:  DEFB    $08             ; Class-08 - Two comma-separated numeric\n                                ; expressions required.\n        DEFB    $00             ; Class-00 - No further operands.\n        DEFW    L1E80           ; Address: $1E80; Address: POKE\n\n;; P-RANDOM\nL1AB5:  DEFB    $03             ; Class-03 - A numeric expression may follow\n                                ; else default to zero.\n        DEFW    L1E4F           ; Address: $1E4F; Address: RANDOMIZE\n\n;; P-CONT\nL1AB8:  DEFB    $00             ; Class-00 - No further operands.\n        DEFW    L1E5F           ; Address: $1E5F; Address: CONTINUE\n\n;; P-CLEAR\nL1ABB:  DEFB    $03             ; Class-03 - A numeric expression may follow\n                                ; else default to zero.\n        DEFW    L1EAC           ; Address: $1EAC; Address: CLEAR\n\n;; P-CLS\nL1ABE:  DEFB    $00             ; Class-00 - No further operands.\n        DEFW    L0D6B           ; Address: $0D6B; Address: CLS\n\n;; P-PLOT\nL1AC1:  DEFB    $09             ; Class-09 - Two comma-separated numeric\n                                ; expressions required with optional colour\n                                ; items.\n        DEFB    $00             ; Class-00 - No further operands.\n        DEFW    L22DC           ; Address: $22DC; Address: PLOT\n\n;; P-PAUSE\nL1AC5:  DEFB    $06             ; Class-06 - A numeric expression must follow.\n        DEFB    $00             ; Class-00 - No further operands.\n        DEFW    L1F3A           ; Address: $1F3A; Address: PAUSE\n\n;; P-READ\nL1AC9:  DEFB    $05             ; Class-05 - Variable syntax checked entirely\n                                ; by routine.\n        DEFW    L1DED           ; Address: $1DED; Address: READ\n\n;; P-DATA\nL1ACC:  DEFB    $05             ; Class-05 - Variable syntax checked entirely\n                                ; by routine.\n        DEFW    L1E27           ; Address: $1E27; Address: DATA\n\n;; P-RESTORE\nL1ACF:  DEFB    $03             ; Class-03 - A numeric expression may follow\n                                ; else default to zero.\n        DEFW    L1E42           ; Address: $1E42; Address: RESTORE\n\n;; P-DRAW\nL1AD2:  DEFB    $09             ; Class-09 - Two comma-separated numeric\n                                ; expressions required with optional colour\n                                ; items.\n        DEFB    $05             ; Class-05 - Variable syntax checked\n                                ; by routine.\n        DEFW    L2382           ; Address: $2382; Address: DRAW\n\n;; P-COPY\nL1AD6:  DEFB    $00             ; Class-00 - No further operands.\n        DEFW    L0EAC           ; Address: $0EAC; Address: COPY\n\n;; P-LPRINT\nL1AD9:  DEFB    $05             ; Class-05 - Variable syntax checked entirely\n                                ; by routine.\n        DEFW    L1FC9           ; Address: $1FC9; Address: LPRINT\n\n;; P-LLIST\nL1ADC:  DEFB    $05             ; Class-05 - Variable syntax checked entirely\n                                ; by routine.\n        DEFW    L17F5           ; Address: $17F5; Address: LLIST\n\n;; P-SAVE\nL1ADF:  DEFB    $0B             ; Class-0B - Offset address converted to tape\n                                ; command.\n\n;; P-LOAD\nL1AE0:  DEFB    $0B             ; Class-0B - Offset address converted to tape\n                                ; command.\n\n;; P-VERIFY\nL1AE1:  DEFB    $0B             ; Class-0B - Offset address converted to tape\n                                ; command.\n\n;; P-MERGE\nL1AE2:  DEFB    $0B             ; Class-0B - Offset address converted to tape\n                                ; command.\n\n;; P-BEEP\nL1AE3:  DEFB    $08             ; Class-08 - Two comma-separated numeric\n                                ; expressions required.\n        DEFB    $00             ; Class-00 - No further operands.\n        DEFW    L03F8           ; Address: $03F8; Address: BEEP\n\n;; P-CIRCLE\nL1AE7:  DEFB    $09             ; Class-09 - Two comma-separated numeric\n                                ; expressions required with optional colour\n                                ; items.\n        DEFB    $05             ; Class-05 - Variable syntax checked\n                                ; by routine.\n        DEFW    L2320           ; Address: $2320; Address: CIRCLE\n\n;; P-INK\nL1AEB:  DEFB    $07             ; Class-07 - Offset address is converted to\n                                ; colour code.\n\n;; P-PAPER\nL1AEC:  DEFB    $07             ; Class-07 - Offset address is converted to\n                                ; colour code.\n\n;; P-FLASH\nL1AED:  DEFB    $07             ; Class-07 - Offset address is converted to\n                                ; colour code.\n\n;; P-BRIGHT\nL1AEE:  DEFB    $07             ; Class-07 - Offset address is converted to\n                                ; colour code.\n\n;; P-INVERSE\nL1AEF:  DEFB    $07             ; Class-07 - Offset address is converted to\n                                ; colour code.\n\n;; P-OVER\nL1AF0:  DEFB    $07             ; Class-07 - Offset address is converted to\n                                ; colour code.\n\n;; P-OUT\nL1AF1:  DEFB    $08             ; Class-08 - Two comma-separated numeric\n                                ; expressions required.\n        DEFB    $00             ; Class-00 - No further operands.\n        DEFW    L1E7A           ; Address: $1E7A; Address: OUT\n\n;; P-BORDER\nL1AF5:  DEFB    $06             ; Class-06 - A numeric expression must follow.\n        DEFB    $00             ; Class-00 - No further operands.\n        DEFW    L2294           ; Address: $2294; Address: BORDER\n\n;; P-DEF-FN\nL1AF9:  DEFB    $05             ; Class-05 - Variable syntax checked entirely\n                                ; by routine.\n        DEFW    L1F60           ; Address: $1F60; Address: DEF-FN\n\n;; P-OPEN\nL1AFC:  DEFB    $06             ; Class-06 - A numeric expression must follow.\n        DEFB    $2C             ; Separator:  ','          see Footnote *\n        DEFB    $0A             ; Class-0A - A string expression must follow.\n        DEFB    $00             ; Class-00 - No further operands.\n        DEFW    L1736           ; Address: $1736; Address: OPEN\n\n;; P-CLOSE\nL1B02:  DEFB    $06             ; Class-06 - A numeric expression must follow.\n        DEFB    $00             ; Class-00 - No further operands.\n        DEFW    L16E5           ; Address: $16E5; Address: CLOSE\n\n;; P-FORMAT\nL1B06:  DEFB    $0A             ; Class-0A - A string expression must follow.\n        DEFB    $00             ; Class-00 - No further operands.\n        DEFW    L1793           ; Address: $1793; Address: CAT-ETC\n\n;; P-MOVE\nL1B0A:  DEFB    $0A             ; Class-0A - A string expression must follow.\n        DEFB    $2C             ; Separator:  ','\n        DEFB    $0A             ; Class-0A - A string expression must follow.\n        DEFB    $00             ; Class-00 - No further operands.\n        DEFW    L1793           ; Address: $1793; Address: CAT-ETC\n\n;; P-ERASE\nL1B10:  DEFB    $0A             ; Class-0A - A string expression must follow.\n        DEFB    $00             ; Class-00 - No further operands.\n        DEFW    L1793           ; Address: $1793; Address: CAT-ETC\n\n;; P-CAT\nL1B14:  DEFB    $00             ; Class-00 - No further operands.\n        DEFW    L1793           ; Address: $1793; Address: CAT-ETC\n\n; * Note that a comma is required as a separator with the OPEN command\n; but the Interface 1 programmers relaxed this allowing ';' as an\n; alternative for their channels creating a confusing mixture of\n; allowable syntax as it is this ROM which opens or re-opens the\n; normal channels.\n\n; -------------------------------\n; Main parser (BASIC interpreter)\n; -------------------------------\n; This routine is called once from MAIN-2 when the BASIC line is to\n; be entered or re-entered into the Program area and the syntax\n; requires checking.\n\n;; LINE-SCAN\nL1B17:  RES     7,(IY+$01)      ; update FLAGS - signal checking syntax\n        CALL    L19FB           ; routine E-LINE-NO              >>\n                                ; fetches the line number if in range.\n\n        XOR     A               ; clear the accumulator.\n        LD      ($5C47),A       ; set statement number SUBPPC to zero.\n        DEC     A               ; set accumulator to $FF.\n        LD      ($5C3A),A       ; set ERR_NR to 'OK' - 1.\n        JR      L1B29           ; forward to continue at STMT-L-1.\n\n; --------------\n; Statement loop\n; --------------\n;\n;\n\n;; STMT-LOOP\nL1B28:  RST     20H             ; NEXT-CHAR\n\n; -> the entry point from above or LINE-RUN\n;; STMT-L-1\nL1B29:  CALL    L16BF           ; routine SET-WORK clears workspace etc.\n\n        INC     (IY+$0D)        ; increment statement number SUBPPC\n        JP      M,L1C8A         ; to REPORT-C to raise\n                                ; 'Nonsense in BASIC' if over 127.\n\n        RST     18H             ; GET-CHAR\n\n        LD      B,$00           ; set B to zero for later indexing.\n                                ; early so any other reason ???\n\n        CP      $0D             ; is character carriage return ?\n                                ; i.e. an empty statement.\n        JR      Z,L1BB3         ; forward to LINE-END if so.\n\n        CP      $3A             ; is it statement end marker ':' ?\n                                ; i.e. another type of empty statement.\n        JR      Z,L1B28         ; back to STMT-LOOP if so.\n\n        LD      HL,L1B76        ; address: STMT-RET\n        PUSH    HL              ; is now pushed as a return address\n        LD      C,A             ; transfer the current character to C.\n\n; advance CH_ADD to a position after command and test if it is a command.\n\n        RST     20H             ; NEXT-CHAR to advance pointer\n        LD      A,C             ; restore current character\n        SUB     $CE             ; subtract 'DEF FN' - first command\n        JP      C,L1C8A         ; jump to REPORT-C if less than a command\n                                ; raising\n                                ; 'Nonsense in BASIC'\n\n        LD      C,A             ; put the valid command code back in C.\n                                ; register B is zero.\n        LD      HL,L1A48        ; address: offst-tbl\n        ADD     HL,BC           ; index into table with one of 50 commands.\n        LD      C,(HL)          ; pick up displacement to syntax table entry.\n        ADD     HL,BC           ; add to address the relevant entry.\n        JR      L1B55           ; forward to continue at GET-PARAM\n\n; ----------------------\n; The main scanning loop\n; ----------------------\n; not documented properly\n;\n\n;; SCAN-LOOP\nL1B52:  LD      HL,($5C74)      ; fetch temporary address from T_ADDR\n                                ; during subsequent loops.\n\n; -> the initial entry point with HL addressing start of syntax table entry.\n\n;; GET-PARAM\nL1B55:  LD      A,(HL)          ; pick up the parameter.\n        INC     HL              ; address next one.\n        LD      ($5C74),HL      ; save pointer in system variable T_ADDR\n\n        LD      BC,L1B52        ; address: SCAN-LOOP\n        PUSH    BC              ; is now pushed on stack as looping address.\n        LD      C,A             ; store parameter in C.\n        CP      $20             ; is it greater than ' '  ?\n        JR      NC,L1B6F        ; forward to SEPARATOR to check that correct\n                                ; separator appears in statement if so.\n\n        LD      HL,L1C01        ; address: class-tbl.\n        LD      B,$00           ; prepare to index into the class table.\n        ADD     HL,BC           ; index to find displacement to routine.\n        LD      C,(HL)          ; displacement to BC\n        ADD     HL,BC           ; add to address the CLASS routine.\n        PUSH    HL              ; push the address on the stack.\n\n        RST     18H             ; GET-CHAR - HL points to place in statement.\n\n        DEC     B               ; reset the zero flag - the initial state\n                                ; for all class routines.\n\n        RET                     ; and make an indirect jump to routine\n                                ; and then SCAN-LOOP (also on stack).\n\n; Note. one of the class routines will eventually drop the return address\n; off the stack breaking out of the above seemingly endless loop.\n\n; -----------------------\n; THE 'SEPARATOR' ROUTINE\n; -----------------------\n;   This routine is called once to verify that the mandatory separator\n;   present in the parameter table is also present in the correct\n;   location following the command.  For example, the 'THEN' token after\n;   the 'IF' token and expression.\n\n;; SEPARATOR\nL1B6F:  RST     18H             ; GET-CHAR\n        CP      C               ; does it match the character in C ?\n        JP      NZ,L1C8A        ; jump forward to REPORT-C if not\n                                ; 'Nonsense in BASIC'.\n\n        RST     20H             ; NEXT-CHAR advance to next character\n        RET                     ; return.\n\n; ------------------------------\n; Come here after interpretation\n; ------------------------------\n;\n;\n\n;; STMT-RET\nL1B76:  CALL    L1F54           ; routine BREAK-KEY is tested after every\n                                ; statement.\n        JR      C,L1B7D         ; step forward to STMT-R-1 if not pressed.\n\n;; REPORT-L\nL1B7B:  RST     08H             ; ERROR-1\n        DEFB    $14             ; Error Report: BREAK into program\n\n;; STMT-R-1\nL1B7D:  BIT     7,(IY+$0A)      ; test NSPPC - will be set if $FF -\n                                ; no jump to be made.\n        JR      NZ,L1BF4        ; forward to STMT-NEXT if a program line.\n\n        LD      HL,($5C42)      ; fetch line number from NEWPPC\n        BIT     7,H             ; will be set if minus two - direct command(s)\n        JR      Z,L1B9E         ; forward to LINE-NEW if a jump is to be\n                                ; made to a new program line/statement.\n\n; --------------------\n; Run a direct command\n; --------------------\n; A direct command is to be run or, if continuing from above,\n; the next statement of a direct command is to be considered.\n\n;; LINE-RUN\nL1B8A:  LD      HL,$FFFE        ; The dummy value minus two\n        LD      ($5C45),HL      ; is set/reset as line number in PPC.\n        LD      HL,($5C61)      ; point to end of line + 1 - WORKSP.\n        DEC     HL              ; now point to $80 end-marker.\n        LD      DE,($5C59)      ; address the start of line E_LINE.\n        DEC     DE              ; now location before - for GET-CHAR.\n        LD      A,($5C44)       ; load statement to A from NSPPC.\n        JR      L1BD1           ; forward to NEXT-LINE.\n\n; ------------------------------\n; Find start address of new line\n; ------------------------------\n; The branch was to here if a jump is to made to a new line number\n; and statement.\n; That is the previous statement was a GO TO, GO SUB, RUN, RETURN, NEXT etc..\n\n;; LINE-NEW\nL1B9E:  CALL    L196E           ; routine LINE-ADDR gets address of line\n                                ; returning zero flag set if line found.\n        LD      A,($5C44)       ; fetch new statement from NSPPC\n        JR      Z,L1BBF         ; forward to LINE-USE if line matched.\n\n; continue as must be a direct command.\n\n        AND     A               ; test statement which should be zero\n        JR      NZ,L1BEC        ; forward to REPORT-N if not.\n                                ; 'Statement lost'\n\n;\n\n        LD      B,A             ; save statement in B.??\n        LD      A,(HL)          ; fetch high byte of line number.\n        AND     $C0             ; test if using direct command\n                                ; a program line is less than $3F\n        LD      A,B             ; retrieve statement.\n                                ; (we can assume it is zero).\n        JR      Z,L1BBF         ; forward to LINE-USE if was a program line\n\n; Alternatively a direct statement has finished correctly.\n\n;; REPORT-0\nL1BB0:  RST     08H             ; ERROR-1\n        DEFB    $FF             ; Error Report: OK\n\n; -----------------\n; THE 'REM' COMMAND\n; -----------------\n; The REM command routine.\n; The return address STMT-RET is dropped and the rest of line ignored.\n\n;; REM\nL1BB2:  POP     BC              ; drop return address STMT-RET and\n                                ; continue ignoring rest of line.\n\n; ------------\n; End of line?\n; ------------\n;\n;\n\n;; LINE-END\nL1BB3:  CALL    L2530           ; routine SYNTAX-Z  (UNSTACK-Z?)\n        RET     Z               ; return if checking syntax.\n\n        LD      HL,($5C55)      ; fetch NXTLIN to HL.\n        LD      A,$C0           ; test against the\n        AND     (HL)            ; system limit $3F.\n        RET     NZ              ; return if more as must be\n                                ; end of program.\n                                ; (or direct command)\n\n        XOR     A               ; set statement to zero.\n\n; and continue to set up the next following line and then consider this new one.\n\n; ---------------------\n; General line checking\n; ---------------------\n; The branch was here from LINE-NEW if BASIC is branching.\n; or a continuation from above if dealing with a new sequential line.\n; First make statement zero number one leaving others unaffected.\n\n;; LINE-USE\nL1BBF:  CP      $01             ; will set carry if zero.\n        ADC     A,$00           ; add in any carry.\n\n        LD      D,(HL)          ; high byte of line number to D.\n        INC     HL              ; advance pointer.\n        LD      E,(HL)          ; low byte of line number to E.\n        LD      ($5C45),DE      ; set system variable PPC.\n\n        INC     HL              ; advance pointer.\n        LD      E,(HL)          ; low byte of line length to E.\n        INC     HL              ; advance pointer.\n        LD      D,(HL)          ; high byte of line length to D.\n\n        EX      DE,HL           ; swap pointer to DE before\n        ADD     HL,DE           ; adding to address the end of line.\n        INC     HL              ; advance to start of next line.\n\n; -----------------------------\n; Update NEXT LINE but consider\n; previous line or edit line.\n; -----------------------------\n; The pointer will be the next line if continuing from above or to\n; edit line end-marker ($80) if from LINE-RUN.\n\n;; NEXT-LINE\nL1BD1:  LD      ($5C55),HL      ; store pointer in system variable NXTLIN\n\n        EX      DE,HL           ; bring back pointer to previous or edit line\n        LD      ($5C5D),HL      ; and update CH_ADD with character address.\n\n        LD      D,A             ; store statement in D.\n        LD      E,$00           ; set E to zero to suppress token searching\n                                ; if EACH-STMT is to be called.\n        LD      (IY+$0A),$FF    ; set statement NSPPC to $FF signalling\n                                ; no jump to be made.\n        DEC     D               ; decrement and test statement\n        LD      (IY+$0D),D      ; set SUBPPC to decremented statement number.\n        JP      Z,L1B28         ; to STMT-LOOP if result zero as statement is\n                                ; at start of line and address is known.\n\n        INC     D               ; else restore statement.\n        CALL    L198B           ; routine EACH-STMT finds the D'th statement\n                                ; address as E does not contain a token.\n        JR      Z,L1BF4         ; forward to STMT-NEXT if address found.\n\n;; REPORT-N\nL1BEC:  RST     08H             ; ERROR-1\n        DEFB    $16             ; Error Report: Statement lost\n\n; -----------------\n; End of statement?\n; -----------------\n; This combination of routines is called from 20 places when\n; the end of a statement should have been reached and all preceding\n; syntax is in order.\n\n;; CHECK-END\nL1BEE:  CALL    L2530           ; routine SYNTAX-Z\n        RET     NZ              ; return immediately in runtime\n\n        POP     BC              ; drop address of calling routine.\n        POP     BC              ; drop address STMT-RET.\n                                ; and continue to find next statement.\n\n; --------------------\n; Go to next statement\n; --------------------\n; Acceptable characters at this point are carriage return and ':'.\n; If so go to next statement which in the first case will be on next line.\n\n;; STMT-NEXT\nL1BF4:  RST     18H             ; GET-CHAR - ignoring white space etc.\n\n        CP      $0D             ; is it carriage return ?\n        JR      Z,L1BB3         ; back to LINE-END if so.\n\n        CP      $3A             ; is it ':' ?\n        JP      Z,L1B28         ; jump back to STMT-LOOP to consider\n                                ; further statements\n\n        JP      L1C8A           ; jump to REPORT-C with any other character\n                                ; 'Nonsense in BASIC'.\n\n; Note. the two-byte sequence 'rst 08; defb $0b' could replace the above jp.\n\n; -------------------\n; Command class table\n; -------------------\n;\n\n;; class-tbl\nL1C01:  DEFB    L1C10 - $       ; 0F offset to Address: CLASS-00\n        DEFB    L1C1F - $       ; 1D offset to Address: CLASS-01\n        DEFB    L1C4E - $       ; 4B offset to Address: CLASS-02\n        DEFB    L1C0D - $       ; 09 offset to Address: CLASS-03\n        DEFB    L1C6C - $       ; 67 offset to Address: CLASS-04\n        DEFB    L1C11 - $       ; 0B offset to Address: CLASS-05\n        DEFB    L1C82 - $       ; 7B offset to Address: CLASS-06\n        DEFB    L1C96 - $       ; 8E offset to Address: CLASS-07\n        DEFB    L1C7A - $       ; 71 offset to Address: CLASS-08\n        DEFB    L1CBE - $       ; B4 offset to Address: CLASS-09\n        DEFB    L1C8C - $       ; 81 offset to Address: CLASS-0A\n        DEFB    L1CDB - $       ; CF offset to Address: CLASS-0B\n\n\n; --------------------------------\n; Command classes---00, 03, and 05\n; --------------------------------\n; class-03 e.g. RUN or RUN 200   ;  optional operand\n; class-00 e.g. CONTINUE         ;  no operand\n; class-05 e.g. PRINT            ;  variable syntax checked by routine\n\n;; CLASS-03\nL1C0D:  CALL    L1CDE           ; routine FETCH-NUM\n\n;; CLASS-00\n\nL1C10:  CP      A               ; reset zero flag.\n\n; if entering here then all class routines are entered with zero reset.\n\n;; CLASS-05\nL1C11:  POP     BC              ; drop address SCAN-LOOP.\n        CALL    Z,L1BEE         ; if zero set then call routine CHECK-END >>>\n                                ; as should be no further characters.\n\n        EX      DE,HL           ; save HL to DE.\n        LD      HL,($5C74)      ; fetch T_ADDR\n        LD      C,(HL)          ; fetch low byte of routine\n        INC     HL              ; address next.\n        LD      B,(HL)          ; fetch high byte of routine.\n        EX      DE,HL           ; restore HL from DE\n        PUSH    BC              ; push the address\n        RET                     ; and make an indirect jump to the command.\n\n; --------------------------------\n; Command classes---01, 02, and 04\n; --------------------------------\n; class-01  e.g. LET A = 2*3     ; a variable is reqd\n\n; This class routine is also called from INPUT and READ to find the\n; destination variable for an assignment.\n\n;; CLASS-01\nL1C1F:  CALL    L28B2           ; routine LOOK-VARS returns carry set if not\n                                ; found in runtime.\n\n; ----------------------\n; Variable in assignment\n; ----------------------\n;\n;\n\n;; VAR-A-1\nL1C22:  LD      (IY+$37),$00    ; set FLAGX to zero\n        JR      NC,L1C30        ; forward to VAR-A-2 if found or checking\n                                ; syntax.\n\n        SET     1,(IY+$37)      ; FLAGX  - Signal a new variable\n        JR      NZ,L1C46        ; to VAR-A-3 if not assigning to an array\n                                ; e.g. LET a$(3,3) = \"X\"\n\n;; REPORT-2\nL1C2E:  RST     08H             ; ERROR-1\n        DEFB    $01             ; Error Report: Variable not found\n\n;; VAR-A-2\nL1C30:  CALL    Z,L2996         ; routine STK-VAR considers a subscript/slice\n        BIT     6,(IY+$01)      ; test FLAGS  - Numeric or string result ?\n        JR      NZ,L1C46        ; to VAR-A-3 if numeric\n\n        XOR     A               ; default to array/slice - to be retained.\n        CALL    L2530           ; routine SYNTAX-Z\n        CALL    NZ,L2BF1        ; routine STK-FETCH is called in runtime\n                                ; may overwrite A with 1.\n        LD      HL,$5C71        ; address system variable FLAGX\n        OR      (HL)            ; set bit 0 if simple variable to be reclaimed\n        LD      (HL),A          ; update FLAGX\n        EX      DE,HL           ; start of string/subscript to DE\n\n;; VAR-A-3\nL1C46:  LD      ($5C72),BC      ; update STRLEN\n        LD      ($5C4D),HL      ; and DEST of assigned string.\n        RET                     ; return.\n\n; -------------------------------------------------\n; class-02 e.g. LET a = 1 + 1   ; an expression must follow\n\n;; CLASS-02\nL1C4E:  POP     BC              ; drop return address SCAN-LOOP\n        CALL    L1C56           ; routine VAL-FET-1 is called to check\n                                ; expression and assign result in runtime\n        CALL    L1BEE           ; routine CHECK-END checks nothing else\n                                ; is present in statement.\n        RET                     ; Return\n\n; -------------\n; Fetch a value\n; -------------\n;\n;\n\n;; VAL-FET-1\nL1C56:  LD      A,($5C3B)       ; initial FLAGS to A\n\n;; VAL-FET-2\nL1C59:  PUSH    AF              ; save A briefly\n        CALL    L24FB           ; routine SCANNING evaluates expression.\n        POP     AF              ; restore A\n        LD      D,(IY+$01)      ; post-SCANNING FLAGS to D\n        XOR     D               ; xor the two sets of flags\n        AND     $40             ; pick up bit 6 of xored FLAGS should be zero\n        JR      NZ,L1C8A        ; forward to REPORT-C if not zero\n                                ; 'Nonsense in BASIC' - results don't agree.\n\n        BIT     7,D             ; test FLAGS - is syntax being checked ?\n        JP      NZ,L2AFF        ; jump forward to LET to make the assignment\n                                ; in runtime.\n\n        RET                     ; but return from here if checking syntax.\n\n; ------------------\n; Command class---04\n; ------------------\n; class-04 e.g. FOR i            ; a single character variable must follow\n\n;; CLASS-04\nL1C6C:  CALL    L28B2           ; routine LOOK-VARS\n        PUSH    AF              ; preserve flags.\n        LD      A,C             ; fetch type - should be 011xxxxx\n        OR      $9F             ; combine with 10011111.\n        INC     A               ; test if now $FF by incrementing.\n        JR      NZ,L1C8A        ; forward to REPORT-C if result not zero.\n\n        POP     AF              ; else restore flags.\n        JR      L1C22           ; back to VAR-A-1\n\n\n; --------------------------------\n; Expect numeric/string expression\n; --------------------------------\n; This routine is used to get the two coordinates of STRING$, ATTR and POINT.\n; It is also called from PRINT-ITEM to get the two numeric expressions that\n; follow the AT ( in PRINT AT, INPUT AT).\n\n;; NEXT-2NUM\nL1C79:  RST     20H             ; NEXT-CHAR advance past 'AT' or '('.\n\n; --------\n; class-08 e.g. POKE 65535,2     ; two numeric expressions separated by comma\n;; CLASS-08\n;; EXPT-2NUM\nL1C7A:  CALL    L1C82           ; routine EXPT-1NUM is called for first\n                                ; numeric expression\n        CP      $2C             ; is character ',' ?\n        JR      NZ,L1C8A        ; to REPORT-C if not required separator.\n                                ; 'Nonsense in BASIC'.\n\n        RST     20H             ; NEXT-CHAR\n\n; ->\n;  class-06  e.g. GOTO a*1000   ; a numeric expression must follow\n;; CLASS-06\n;; EXPT-1NUM\nL1C82:  CALL    L24FB           ; routine SCANNING\n        BIT     6,(IY+$01)      ; test FLAGS  - Numeric or string result ?\n        RET     NZ              ; return if result is numeric.\n\n;; REPORT-C\nL1C8A:  RST     08H             ; ERROR-1\n        DEFB    $0B             ; Error Report: Nonsense in BASIC\n\n; ---------------------------------------------------------------\n; class-0A e.g. ERASE \"????\"    ; a string expression must follow.\n;                               ; these only occur in unimplemented commands\n;                               ; although the routine expt-exp is called\n;                               ; from SAVE-ETC\n\n;; CLASS-0A\n;; EXPT-EXP\nL1C8C:  CALL    L24FB           ; routine SCANNING\n        BIT     6,(IY+$01)      ; test FLAGS  - Numeric or string result ?\n        RET     Z               ; return if string result.\n\n        JR      L1C8A           ; back to REPORT-C if numeric.\n\n; ---------------------\n; Set permanent colours\n; class 07\n; ---------------------\n; class-07 e.g. PAPER 6          ; a single class for a collection of\n;                               ; similar commands. Clever.\n;\n; Note. these commands should ensure that current channel is 'S'\n\n;; CLASS-07\nL1C96:  BIT     7,(IY+$01)      ; test FLAGS - checking syntax only ?\n                                ; Note. there is a subroutine to do this.\n        RES     0,(IY+$02)      ; update TV_FLAG - signal main screen in use\n        CALL    NZ,L0D4D        ; routine TEMPS is called in runtime.\n        POP     AF              ; drop return address SCAN-LOOP\n        LD      A,($5C74)       ; T_ADDR_lo to accumulator.\n                                ; points to '$07' entry + 1\n                                ; e.g. for INK points to $EC now\n\n; Note if you move alter the syntax table next line may have to be altered.\n\n; Note. For ZASM assembler replace following expression with SUB $13.\n\nL1CA5:  SUB     L1AEB-$D8 % 256 ; convert $EB to $D8 ('INK') etc.\n                                ; ( is SUB $13 in standard ROM )\n\n        CALL    L21FC           ; routine CO-TEMP-4\n        CALL    L1BEE           ; routine CHECK-END check that nothing else\n                                ; in statement.\n\n; return here in runtime.\n\n        LD      HL,($5C8F)      ; pick up ATTR_T and MASK_T\n        LD      ($5C8D),HL      ; and store in ATTR_P and MASK_P\n        LD      HL,$5C91        ; point to P_FLAG.\n        LD      A,(HL)          ; pick up in A\n        RLCA                    ; rotate to left\n        XOR     (HL)            ; combine with HL\n        AND     $AA             ; 10101010\n        XOR     (HL)            ; only permanent bits affected\n        LD      (HL),A          ; reload into P_FLAG.\n        RET                     ; return.\n\n; ------------------\n; Command class---09\n; ------------------\n; e.g. PLOT PAPER 0; 128,88     ; two coordinates preceded by optional\n;                               ; embedded colour items.\n;\n; Note. this command should ensure that current channel is actually 'S'.\n\n;; CLASS-09\nL1CBE:  CALL    L2530           ; routine SYNTAX-Z\n        JR      Z,L1CD6         ; forward to CL-09-1 if checking syntax.\n\n        RES     0,(IY+$02)      ; update TV_FLAG - signal main screen in use\n        CALL    L0D4D           ; routine TEMPS is called.\n        LD      HL,$5C90        ; point to MASK_T\n        LD      A,(HL)          ; fetch mask to accumulator.\n        OR      $F8             ; or with 11111000 paper/bright/flash 8\n        LD      (HL),A          ; mask back to MASK_T system variable.\n        RES     6,(IY+$57)      ; reset P_FLAG  - signal NOT PAPER 9 ?\n\n        RST     18H             ; GET-CHAR\n\n;; CL-09-1\nL1CD6:  CALL    L21E2           ; routine CO-TEMP-2 deals with any embedded\n                                ; colour items.\n        JR      L1C7A           ; exit via EXPT-2NUM to check for x,y.\n\n; Note. if either of the numeric expressions contain STR$ then the flag setting\n; above will be undone when the channel flags are reset during STR$.\n; e.g.\n; 10 BORDER 3 : PLOT VAL STR$ 128, VAL STR$ 100\n; credit John Elliott.\n\n; ------------------\n; Command class---0B\n; ------------------\n; Again a single class for four commands.\n; This command just jumps back to SAVE-ETC to handle the four tape commands.\n; The routine itself works out which command has called it by examining the\n; address in T_ADDR_lo. Note therefore that the syntax table has to be\n; located where these and other sequential command addresses are not split\n; over a page boundary.\n\n;; CLASS-0B\nL1CDB:  JP      L0605           ; jump way back to SAVE-ETC\n\n; --------------\n; Fetch a number\n; --------------\n; This routine is called from CLASS-03 when a command may be followed by\n; an optional numeric expression e.g. RUN. If the end of statement has\n; been reached then zero is used as the default.\n; Also called from LIST-4.\n\n;; FETCH-NUM\nL1CDE:  CP      $0D             ; is character a carriage return ?\n        JR      Z,L1CE6         ; forward to USE-ZERO if so\n\n        CP      $3A             ; is it ':' ?\n        JR      NZ,L1C82        ; forward to EXPT-1NUM if not.\n                                ; else continue and use zero.\n\n; ----------------\n; Use zero routine\n; ----------------\n; This routine is called four times to place the value zero on the\n; calculator stack as a default value in runtime.\n\n;; USE-ZERO\nL1CE6:  CALL    L2530           ; routine SYNTAX-Z  (UNSTACK-Z?)\n        RET     Z               ;\n\n        RST     28H             ;; FP-CALC\n        DEFB    $A0             ;;stk-zero       ;0.\n        DEFB    $38             ;;end-calc\n\n        RET                     ; return.\n\n; -------------------\n; Handle STOP command\n; -------------------\n; Command Syntax: STOP\n; One of the shortest and least used commands. As with 'OK' not an error.\n\n;; REPORT-9\n;; STOP\nL1CEE:  RST     08H             ; ERROR-1\n        DEFB    $08             ; Error Report: STOP statement\n\n; -----------------\n; Handle IF command\n; -----------------\n; e.g. IF score>100 THEN PRINT \"You Win\"\n; The parser has already checked the expression the result of which is on\n; the calculator stack. The presence of the 'THEN' separator has also been\n; checked and CH-ADD points to the command after THEN.\n;\n\n;; IF\nL1CF0:  POP     BC              ; drop return address - STMT-RET\n        CALL    L2530           ; routine SYNTAX-Z\n        JR      Z,L1D00         ; forward to IF-1 if checking syntax\n                                ; to check syntax of PRINT \"You Win\"\n\n\n        RST     28H             ;; FP-CALC    score>100 (1=TRUE 0=FALSE)\n        DEFB    $02             ;;delete      .\n        DEFB    $38             ;;end-calc\n\n        EX      DE,HL           ; make HL point to deleted value\n        CALL    L34E9           ; routine TEST-ZERO\n        JP      C,L1BB3         ; jump to LINE-END if FALSE (0)\n\n;; IF-1\nL1D00:  JP      L1B29           ; to STMT-L-1, if true (1) to execute command\n                                ; after 'THEN' token.\n\n; ------------------\n; Handle FOR command\n; ------------------\n; e.g. FOR i = 0 TO 1 STEP 0.1\n; Using the syntax tables, the parser has already checked for a start and\n; limit value and also for the intervening separator.\n; the two values v,l are on the calculator stack.\n; CLASS-04 has also checked the variable and the name is in STRLEN_lo.\n; The routine begins by checking for an optional STEP.\n\n;; FOR\nL1D03:  CP      $CD             ; is there a 'STEP' ?\n        JR      NZ,L1D10        ; to F-USE-1 if not to use 1 as default.\n\n        RST     20H             ; NEXT-CHAR\n        CALL    L1C82           ; routine EXPT-1NUM\n        CALL    L1BEE           ; routine CHECK-END\n        JR      L1D16           ; to F-REORDER\n\n; ---\n\n;; F-USE-1\nL1D10:  CALL    L1BEE           ; routine CHECK-END\n\n        RST     28H             ;; FP-CALC      v,l.\n        DEFB    $A1             ;;stk-one       v,l,1=s.\n        DEFB    $38             ;;end-calc\n\n\n;; F-REORDER\nL1D16:  RST     28H             ;; FP-CALC       v,l,s.\n        DEFB    $C0             ;;st-mem-0       v,l,s.\n        DEFB    $02             ;;delete         v,l.\n        DEFB    $01             ;;exchange       l,v.\n        DEFB    $E0             ;;get-mem-0      l,v,s.\n        DEFB    $01             ;;exchange       l,s,v.\n        DEFB    $38             ;;end-calc\n\n        CALL    L2AFF           ; routine LET assigns the initial value v to\n                                ; the variable altering type if necessary.\n        LD      ($5C68),HL      ; The system variable MEM is made to point to\n                                ; the variable instead of its normal\n                                ; location MEMBOT\n        DEC     HL              ; point to single-character name\n        LD      A,(HL)          ; fetch name\n        SET     7,(HL)          ; set bit 7 at location\n        LD      BC,$0006        ; add six to HL\n        ADD     HL,BC           ; to address where limit should be.\n        RLCA                    ; test bit 7 of original name.\n        JR      C,L1D34         ; forward to F-L-S if already a FOR/NEXT\n                                ; variable\n\n        LD      C,$0D           ; otherwise an additional 13 bytes are needed.\n                                ; 5 for each value, two for line number and\n                                ; 1 byte for looping statement.\n        CALL    L1655           ; routine MAKE-ROOM creates them.\n        INC     HL              ; make HL address limit.\n\n;; F-L-S\nL1D34:  PUSH    HL              ; save position.\n\n        RST     28H             ;; FP-CALC         l,s.\n        DEFB    $02             ;;delete           l.\n        DEFB    $02             ;;delete           .\n        DEFB    $38             ;;end-calc\n                                ; DE points to STKEND, l.\n\n        POP     HL              ; restore variable position\n        EX      DE,HL           ; swap pointers\n        LD      C,$0A           ; ten bytes to move\n        LDIR                    ; Copy 'deleted' values to variable.\n        LD      HL,($5C45)      ; Load with current line number from PPC\n        EX      DE,HL           ; exchange pointers.\n        LD      (HL),E          ; save the looping line\n        INC     HL              ; in the next\n        LD      (HL),D          ; two locations.\n        LD      D,(IY+$0D)      ; fetch statement from SUBPPC system variable.\n        INC     D               ; increment statement.\n        INC     HL              ; and pointer\n        LD      (HL),D          ; and store the looping statement.\n                                ;\n        CALL    L1DDA           ; routine NEXT-LOOP considers an initial\n        RET     NC              ; iteration. Return to STMT-RET if a loop is\n                                ; possible to execute next statement.\n\n; no loop is possible so execution continues after the matching 'NEXT'\n\n        LD      B,(IY+$38)      ; get single-character name from STRLEN_lo\n        LD      HL,($5C45)      ; get the current line from PPC\n        LD      ($5C42),HL      ; and store it in NEWPPC\n        LD      A,($5C47)       ; fetch current statement from SUBPPC\n        NEG                     ; Negate as counter decrements from zero\n                                ; initially and we are in the middle of a\n                                ; line.\n        LD      D,A             ; Store result in D.\n        LD      HL,($5C5D)      ; get current address from CH_ADD\n        LD      E,$F3           ; search will be for token 'NEXT'\n\n;; F-LOOP\nL1D64:  PUSH    BC              ; save variable name.\n        LD      BC,($5C55)      ; fetch NXTLIN\n        CALL    L1D86           ; routine LOOK-PROG searches for 'NEXT' token.\n        LD      ($5C55),BC      ; update NXTLIN\n        POP     BC              ; and fetch the letter\n        JR      C,L1D84         ; forward to REPORT-I if the end of program\n                                ; was reached by LOOK-PROG.\n                                ; 'FOR without NEXT'\n\n        RST     20H             ; NEXT-CHAR fetches character after NEXT\n        OR      $20             ; ensure it is upper-case.\n        CP      B               ; compare with FOR variable name\n        JR      Z,L1D7C         ; forward to F-FOUND if it matches.\n\n; but if no match i.e. nested FOR/NEXT loops then continue search.\n\n        RST     20H             ; NEXT-CHAR\n        JR      L1D64           ; back to F-LOOP\n\n; ---\n\n\n;; F-FOUND\nL1D7C:  RST     20H             ; NEXT-CHAR\n        LD      A,$01           ; subtract the negated counter from 1\n        SUB     D               ; to give the statement after the NEXT\n        LD      ($5C44),A       ; set system variable NSPPC\n        RET                     ; return to STMT-RET to branch to new\n                                ; line and statement. ->\n; ---\n\n;; REPORT-I\nL1D84:  RST     08H             ; ERROR-1\n        DEFB    $11             ; Error Report: FOR without NEXT\n\n; ---------\n; LOOK-PROG\n; ---------\n; Find DATA, DEF FN or NEXT.\n; This routine searches the program area for one of the above three keywords.\n; On entry, HL points to start of search area.\n; The token is in E, and D holds a statement count, decremented from zero.\n\n;; LOOK-PROG\nL1D86:  LD      A,(HL)          ; fetch current character\n        CP      $3A             ; is it ':' a statement separator ?\n        JR      Z,L1DA3         ; forward to LOOK-P-2 if so.\n\n; The starting point was PROG - 1 or the end of a line.\n\n;; LOOK-P-1\nL1D8B:  INC     HL              ; increment pointer to address\n        LD      A,(HL)          ; the high byte of line number\n        AND     $C0             ; test for program end marker $80 or a\n                                ; variable\n        SCF                     ; Set Carry Flag\n        RET     NZ              ; return with carry set if at end\n                                ; of program.           ->\n\n        LD      B,(HL)          ; high byte of line number to B\n        INC     HL              ;\n        LD      C,(HL)          ; low byte to C.\n        LD      ($5C42),BC      ; set system variable NEWPPC.\n        INC     HL              ;\n        LD      C,(HL)          ; low byte of line length to C.\n        INC     HL              ;\n        LD      B,(HL)          ; high byte to B.\n        PUSH    HL              ; save address\n        ADD     HL,BC           ; add length to position.\n        LD      B,H             ; and save result\n        LD      C,L             ; in BC.\n        POP     HL              ; restore address.\n        LD      D,$00           ; initialize statement counter to zero.\n\n;; LOOK-P-2\nL1DA3:  PUSH    BC              ; save address of next line\n        CALL    L198B           ; routine EACH-STMT searches current line.\n        POP     BC              ; restore address.\n        RET     NC              ; return if match was found. ->\n\n        JR      L1D8B           ; back to LOOK-P-1 for next line.\n\n; -------------------\n; Handle NEXT command\n; -------------------\n; e.g. NEXT i\n; The parameter tables have already evaluated the presence of a variable\n\n;; NEXT\nL1DAB:  BIT     1,(IY+$37)      ; test FLAGX - handling a new variable ?\n        JP      NZ,L1C2E        ; jump back to REPORT-2 if so\n                                ; 'Variable not found'\n\n; now test if found variable is a simple variable uninitialized by a FOR.\n\n        LD      HL,($5C4D)      ; load address of variable from DEST\n        BIT     7,(HL)          ; is it correct type ?\n        JR      Z,L1DD8         ; forward to REPORT-1 if not\n                                ; 'NEXT without FOR'\n\n        INC     HL              ; step past variable name\n        LD      ($5C68),HL      ; and set MEM to point to three 5-byte values\n                                ; value, limit, step.\n\n        RST     28H             ;; FP-CALC     add step and re-store\n        DEFB    $E0             ;;get-mem-0    v.\n        DEFB    $E2             ;;get-mem-2    v,s.\n        DEFB    $0F             ;;addition     v+s.\n        DEFB    $C0             ;;st-mem-0     v+s.\n        DEFB    $02             ;;delete       .\n        DEFB    $38             ;;end-calc\n\n        CALL    L1DDA           ; routine NEXT-LOOP tests against limit.\n        RET     C               ; return if no more iterations possible.\n\n        LD      HL,($5C68)      ; find start of variable contents from MEM.\n        LD      DE,$000F        ; add 3*5 to\n        ADD     HL,DE           ; address the looping line number\n        LD      E,(HL)          ; low byte to E\n        INC     HL              ;\n        LD      D,(HL)          ; high byte to D\n        INC     HL              ; address looping statement\n        LD      H,(HL)          ; and store in H\n        EX      DE,HL           ; swap registers\n        JP      L1E73           ; exit via GO-TO-2 to execute another loop.\n\n; ---\n\n;; REPORT-1\nL1DD8:  RST     08H             ; ERROR-1\n        DEFB    $00             ; Error Report: NEXT without FOR\n\n\n; -----------------\n; Perform NEXT loop\n; -----------------\n; This routine is called from the FOR command to test for an initial\n; iteration and from the NEXT command to test for all subsequent iterations.\n; the system variable MEM addresses the variable's contents which, in the\n; latter case, have had the step, possibly negative, added to the value.\n\n;; NEXT-LOOP\nL1DDA:  RST     28H             ;; FP-CALC\n        DEFB    $E1             ;;get-mem-1        l.\n        DEFB    $E0             ;;get-mem-0        l,v.\n        DEFB    $E2             ;;get-mem-2        l,v,s.\n        DEFB    $36             ;;less-0           l,v,(1/0) negative step ?\n        DEFB    $00             ;;jump-true        l,v.(1/0)\n\n        DEFB    $02             ;;to L1DE2, NEXT-1 if step negative\n\n        DEFB    $01             ;;exchange         v,l.\n\n;; NEXT-1\nL1DE2:  DEFB    $03             ;;subtract         l-v OR v-l.\n        DEFB    $37             ;;greater-0        (1/0)\n        DEFB    $00             ;;jump-true        .\n\n        DEFB    $04             ;;to L1DE9, NEXT-2 if no more iterations.\n\n        DEFB    $38             ;;end-calc         .\n\n        AND     A               ; clear carry flag signalling another loop.\n        RET                     ; return\n\n; ---\n\n;; NEXT-2\nL1DE9:  DEFB    $38             ;;end-calc         .\n\n        SCF                     ; set carry flag signalling looping exhausted.\n        RET                     ; return\n\n\n; -------------------\n; Handle READ command\n; -------------------\n; e.g. READ a, b$, c$(1000 TO 3000)\n; A list of comma-separated variables is assigned from a list of\n; comma-separated expressions.\n; As it moves along the first list, the character address CH_ADD is stored\n; in X_PTR while CH_ADD is used to read the second list.\n\n;; READ-3\nL1DEC:  RST     20H             ; NEXT-CHAR\n\n; -> Entry point.\n;; READ\nL1DED:  CALL    L1C1F           ; routine CLASS-01 checks variable.\n        CALL    L2530           ; routine SYNTAX-Z\n        JR      Z,L1E1E         ; forward to READ-2 if checking syntax\n\n\n        RST     18H             ; GET-CHAR\n        LD      ($5C5F),HL      ; save character position in X_PTR.\n        LD      HL,($5C57)      ; load HL with Data Address DATADD, which is\n                                ; the start of the program or the address\n                                ; after the last expression that was read or\n                                ; the address of the line number of the\n                                ; last RESTORE command.\n        LD      A,(HL)          ; fetch character\n        CP      $2C             ; is it a comma ?\n        JR      Z,L1E0A         ; forward to READ-1 if so.\n\n; else all data in this statement has been read so look for next DATA token\n\n        LD      E,$E4           ; token 'DATA'\n        CALL    L1D86           ; routine LOOK-PROG\n        JR      NC,L1E0A        ; forward to READ-1 if DATA found\n\n; else report the error.\n\n;; REPORT-E\nL1E08:  RST     08H             ; ERROR-1\n        DEFB    $0D             ; Error Report: Out of DATA\n\n;; READ-1\nL1E0A:  CALL    L0077           ; routine TEMP-PTR1 advances updating CH_ADD\n                                ; with new DATADD position.\n        CALL    L1C56           ; routine VAL-FET-1 assigns value to variable\n                                ; checking type match and adjusting CH_ADD.\n\n        RST     18H             ; GET-CHAR fetches adjusted character position\n        LD      ($5C57),HL      ; store back in DATADD\n        LD      HL,($5C5F)      ; fetch X_PTR  the original READ CH_ADD\n        LD      (IY+$26),$00    ; now nullify X_PTR_hi\n        CALL    L0078           ; routine TEMP-PTR2 restores READ CH_ADD\n\n;; READ-2\nL1E1E:  RST     18H             ; GET-CHAR\n        CP      $2C             ; is it ',' indicating more variables to read ?\n        JR      Z,L1DEC         ; back to READ-3 if so\n\n        CALL    L1BEE           ; routine CHECK-END\n        RET                     ; return from here in runtime to STMT-RET.\n\n; -------------------\n; Handle DATA command\n; -------------------\n; In runtime this 'command' is passed by but the syntax is checked when such\n; a statement is found while parsing a line.\n; e.g. DATA 1, 2, \"text\", score-1, a$(location, room, object), FN r(49),\n;         wages - tax, TRUE, The meaning of life\n\n;; DATA\nL1E27:  CALL    L2530           ; routine SYNTAX-Z to check status\n        JR      NZ,L1E37        ; forward to DATA-2 if in runtime\n\n;; DATA-1\nL1E2C:  CALL    L24FB           ; routine SCANNING to check syntax of\n                                ; expression\n        CP      $2C             ; is it a comma ?\n        CALL    NZ,L1BEE        ; routine CHECK-END checks that statement\n                                ; is complete. Will make an early exit if\n                                ; so. >>>\n        RST     20H             ; NEXT-CHAR\n        JR      L1E2C           ; back to DATA-1\n\n; ---\n\n;; DATA-2\nL1E37:  LD      A,$E4           ; set token to 'DATA' and continue into\n                                ; the PASS-BY routine.\n\n\n; ----------------------------------\n; Check statement for DATA or DEF FN\n; ----------------------------------\n; This routine is used to backtrack to a command token and then\n; forward to the next statement in runtime.\n\n;; PASS-BY\nL1E39:  LD      B,A             ; Give BC enough space to find token.\n        CPDR                    ; Compare decrement and repeat. (Only use).\n                                ; Work backwards till keyword is found which\n                                ; is start of statement before any quotes.\n                                ; HL points to location before keyword.\n        LD      DE,$0200        ; count 1+1 statements, dummy value in E to\n                                ; inhibit searching for a token.\n        JP      L198B           ; to EACH-STMT to find next statement\n\n; -----------------------------------------------------------------------\n; A General Note on Invalid Line Numbers.\n; =======================================\n; One of the revolutionary concepts of Sinclair BASIC was that it supported\n; virtual line numbers. That is the destination of a GO TO, RESTORE etc. need\n; not exist. It could be a point before or after an actual line number.\n; Zero suffices for a before but the after should logically be infinity.\n; Since the maximum actual line limit is 9999 then the system limit, 16383\n; when variables kick in, would serve fine as a virtual end point.\n; However, ironically, only the LOAD command gets it right. It will not\n; autostart a program that has been saved with a line higher than 16383.\n; All the other commands deal with the limit unsatisfactorily.\n; LIST, RUN, GO TO, GO SUB and RESTORE have problems and the latter may\n; crash the machine when supplied with an inappropriate virtual line number.\n; This is puzzling as very careful consideration must have been given to\n; this point when the new variable types were allocated their masks and also\n; when the routine NEXT-ONE was successfully re-written to reflect this.\n; An enigma.\n; -------------------------------------------------------------------------\n\n; ----------------------\n; Handle RESTORE command\n; ----------------------\n; The restore command sets the system variable for the data address to\n; point to the location before the supplied line number or first line\n; thereafter.\n; This alters the position where subsequent READ commands look for data.\n; Note. If supplied with inappropriate high numbers the system may crash\n; in the LINE-ADDR routine as it will pass the program/variables end-marker\n; and then lose control of what it is looking for - variable or line number.\n; - observation, Steven Vickers, 1984, Pitman.\n\n;; RESTORE\nL1E42:  CALL    L1E99           ; routine FIND-INT2 puts integer in BC.\n                                ; Note. B should be checked against limit $3F\n                                ; and an error generated if higher.\n\n; this entry point is used from RUN command with BC holding zero\n\n;; REST-RUN\nL1E45:  LD      H,B             ; transfer the line\n        LD      L,C             ; number to the HL register.\n        CALL    L196E           ; routine LINE-ADDR to fetch the address.\n        DEC     HL              ; point to the location before the line.\n        LD      ($5C57),HL      ; update system variable DATADD.\n        RET                     ; return to STMT-RET (or RUN)\n\n; ------------------------\n; Handle RANDOMIZE command\n; ------------------------\n; This command sets the SEED for the RND function to a fixed value.\n; With the parameter zero, a random start point is used depending on\n; how long the computer has been switched on.\n\n;; RANDOMIZE\nL1E4F:  CALL    L1E99           ; routine FIND-INT2 puts parameter in BC.\n        LD      A,B             ; test this\n        OR      C               ; for zero.\n        JR      NZ,L1E5A        ; forward to RAND-1 if not zero.\n\n        LD      BC,($5C78)      ; use the lower two bytes at FRAMES1.\n\n;; RAND-1\nL1E5A:  LD      ($5C76),BC      ; place in SEED system variable.\n        RET                     ; return to STMT-RET\n\n; -----------------------\n; Handle CONTINUE command\n; -----------------------\n; The CONTINUE command transfers the OLD (but incremented) values of\n; line number and statement to the equivalent \"NEW VALUE\" system variables\n; by using the last part of GO TO and exits indirectly to STMT-RET.\n\n;; CONTINUE\nL1E5F:  LD      HL,($5C6E)      ; fetch OLDPPC line number.\n        LD      D,(IY+$36)      ; fetch OSPPC statement.\n        JR      L1E73           ; forward to GO-TO-2\n\n; --------------------\n; Handle GO TO command\n; --------------------\n; The GO TO command routine is also called by GO SUB and RUN routines\n; to evaluate the parameters of both commands.\n; It updates the system variables used to fetch the next line/statement.\n; It is at STMT-RET that the actual change in control takes place.\n; Unlike some BASICs the line number need not exist.\n; Note. the high byte of the line number is incorrectly compared with $F0\n; instead of $3F. This leads to commands with operands greater than 32767\n; being considered as having been run from the editing area and the\n; error report 'Statement Lost' is given instead of 'OK'.\n; - Steven Vickers, 1984.\n\n;; GO-TO\nL1E67:  CALL    L1E99           ; routine FIND-INT2 puts operand in BC\n        LD      H,B             ; transfer line\n        LD      L,C             ; number to HL.\n        LD      D,$00           ; set statement to 0 - first.\n        LD      A,H             ; compare high byte only\n        CP      $F0             ; to $F0 i.e. 61439 in full.\n        JR      NC,L1E9F        ; forward to REPORT-B if above.\n\n; This call entry point is used to update the system variables e.g. by RETURN.\n\n;; GO-TO-2\nL1E73:  LD      ($5C42),HL      ; save line number in NEWPPC\n        LD      (IY+$0A),D      ; and statement in NSPPC\n        RET                     ; to STMT-RET (or GO-SUB command)\n\n; ------------------\n; Handle OUT command\n; ------------------\n; Syntax has been checked and the two comma-separated values are on the\n; calculator stack.\n\n;; OUT\nL1E7A:  CALL    L1E85           ; routine TWO-PARAM fetches values\n                                ; to BC and A.\n        OUT     (C),A           ; perform the operation.\n        RET                     ; return to STMT-RET.\n\n; -------------------\n; Handle POKE command\n; -------------------\n; This routine alters a single byte in the 64K address space.\n; Happily no check is made as to whether ROM or RAM is addressed.\n; Sinclair BASIC requires no poking of system variables.\n\n;; POKE\nL1E80:  CALL    L1E85           ; routine TWO-PARAM fetches values\n                                ; to BC and A.\n        LD      (BC),A          ; load memory location with A.\n        RET                     ; return to STMT-RET.\n\n; ------------------------------------\n; Fetch two  parameters from calculator stack\n; ------------------------------------\n; This routine fetches a byte and word from the calculator stack\n; producing an error if either is out of range.\n\n;; TWO-PARAM\nL1E85:  CALL    L2DD5           ; routine FP-TO-A\n        JR      C,L1E9F         ; forward to REPORT-B if overflow occurred\n\n        JR      Z,L1E8E         ; forward to TWO-P-1 if positive\n\n        NEG                     ; negative numbers are made positive\n\n;; TWO-P-1\nL1E8E:  PUSH    AF              ; save the value\n        CALL    L1E99           ; routine FIND-INT2 gets integer to BC\n        POP     AF              ; restore the value\n        RET                     ; return\n\n; -------------\n; Find integers\n; -------------\n; The first of these routines fetches a 8-bit integer (range 0-255) from the\n; calculator stack to the accumulator and is used for colours, streams,\n; durations and coordinates.\n; The second routine fetches 16-bit integers to the BC register pair\n; and is used to fetch command and function arguments involving line numbers\n; or memory addresses and also array subscripts and tab arguments.\n; ->\n\n;; FIND-INT1\nL1E94:  CALL    L2DD5           ; routine FP-TO-A\n        JR      L1E9C           ; forward to FIND-I-1 for common exit routine.\n\n; ---\n\n; ->\n\n;; FIND-INT2\nL1E99:  CALL    L2DA2           ; routine FP-TO-BC\n\n;; FIND-I-1\nL1E9C:  JR      C,L1E9F         ; to REPORT-Bb with overflow.\n\n        RET     Z               ; return if positive.\n\n\n;; REPORT-Bb\nL1E9F:  RST     08H             ; ERROR-1\n        DEFB    $0A             ; Error Report: Integer out of range\n\n; ------------------\n; Handle RUN command\n; ------------------\n; This command runs a program starting at an optional line.\n; It performs a 'RESTORE 0' then CLEAR\n\n;; RUN\nL1EA1:  CALL    L1E67           ; routine GO-TO puts line number in\n                                ; system variables.\n        LD      BC,$0000        ; prepare to set DATADD to first line.\n        CALL    L1E45           ; routine REST-RUN does the 'restore'.\n                                ; Note BC still holds zero.\n        JR      L1EAF           ; forward to CLEAR-RUN to clear variables\n                                ; without disturbing RAMTOP and\n                                ; exit indirectly to STMT-RET\n\n; --------------------\n; Handle CLEAR command\n; --------------------\n; This command reclaims the space used by the variables.\n; It also clears the screen and the GO SUB stack.\n; With an integer expression, it sets the uppermost memory\n; address within the BASIC system.\n; \"Contrary to the manual, CLEAR doesn't execute a RESTORE\" -\n; Steven Vickers, Pitman Pocket Guide to the Spectrum, 1984.\n\n;; CLEAR\nL1EAC:  CALL    L1E99           ; routine FIND-INT2 fetches to BC.\n\n;; CLEAR-RUN\nL1EAF:  LD      A,B             ; test for\n        OR      C               ; zero.\n        JR      NZ,L1EB7        ; skip to CLEAR-1 if not zero.\n\n        LD      BC,($5CB2)      ; use the existing value of RAMTOP if zero.\n\n;; CLEAR-1\nL1EB7:  PUSH    BC              ; save ramtop value.\n\n        LD      DE,($5C4B)      ; fetch VARS\n        LD      HL,($5C59)      ; fetch E_LINE\n        DEC     HL              ; adjust to point at variables end-marker.\n        CALL    L19E5           ; routine RECLAIM-1 reclaims the space used by\n                                ; the variables.\n\n        CALL    L0D6B           ; routine CLS to clear screen.\n\n        LD      HL,($5C65)      ; fetch STKEND the start of free memory.\n        LD      DE,$0032        ; allow for another 50 bytes.\n        ADD     HL,DE           ; add the overhead to HL.\n\n        POP     DE              ; restore the ramtop value.\n        SBC     HL,DE           ; if HL is greater than the value then jump\n        JR      NC,L1EDA        ; forward to REPORT-M\n                                ; 'RAMTOP no good'\n\n        LD      HL,($5CB4)      ; now P-RAMT ($7FFF on 16K RAM machine)\n        AND     A               ; exact this time.\n        SBC     HL,DE           ; new ramtop must be lower or the same.\n        JR      NC,L1EDC        ; skip to CLEAR-2 if in actual RAM.\n\n;; REPORT-M\nL1EDA:  RST     08H             ; ERROR-1\n        DEFB    $15             ; Error Report: RAMTOP no good\n\n;; CLEAR-2\nL1EDC:  EX      DE,HL           ; transfer ramtop value to HL.\n        LD      ($5CB2),HL      ; update system variable RAMTOP.\n        POP     DE              ; pop the return address STMT-RET.\n        POP     BC              ; pop the Error Address.\n        LD      (HL),$3E        ; now put the GO SUB end-marker at RAMTOP.\n        DEC     HL              ; leave a location beneath it.\n        LD      SP,HL           ; initialize the machine stack pointer.\n        PUSH    BC              ; push the error address.\n        LD      ($5C3D),SP      ; make ERR_SP point to location.\n        EX      DE,HL           ; put STMT-RET in HL.\n        JP      (HL)            ; and go there directly.\n\n; ---------------------\n; Handle GO SUB command\n; ---------------------\n; The GO SUB command diverts BASIC control to a new line number\n; in a very similar manner to GO TO but\n; the current line number and current statement + 1\n; are placed on the GO SUB stack as a RETURN point.\n\n;; GO-SUB\nL1EED:  POP     DE              ; drop the address STMT-RET\n        LD      H,(IY+$0D)      ; fetch statement from SUBPPC and\n        INC     H               ; increment it\n        EX      (SP),HL         ; swap - error address to HL,\n                                ; H (statement) at top of stack,\n                                ; L (unimportant) beneath.\n        INC     SP              ; adjust to overwrite unimportant byte\n        LD      BC,($5C45)      ; fetch the current line number from PPC\n        PUSH    BC              ; and PUSH onto GO SUB stack.\n                                ; the empty machine-stack can be rebuilt\n        PUSH    HL              ; push the error address.\n        LD      ($5C3D),SP      ; make system variable ERR_SP point to it.\n        PUSH    DE              ; push the address STMT-RET.\n        CALL    L1E67           ; call routine GO-TO to update the system\n                                ; variables NEWPPC and NSPPC.\n                                ; then make an indirect exit to STMT-RET via\n        LD      BC,$0014        ; a 20-byte overhead memory check.\n\n; ----------------------\n; Check available memory\n; ----------------------\n; This routine is used on many occasions when extending a dynamic area\n; upwards or the GO SUB stack downwards.\n\n;; TEST-ROOM\nL1F05:  LD      HL,($5C65)      ; fetch STKEND\n        ADD     HL,BC           ; add the supplied test value\n        JR      C,L1F15         ; forward to REPORT-4 if over $FFFF\n\n        EX      DE,HL           ; was less so transfer to DE\n        LD      HL,$0050        ; test against another 80 bytes\n        ADD     HL,DE           ; anyway\n        JR      C,L1F15         ; forward to REPORT-4 if this passes $FFFF\n\n        SBC     HL,SP           ; if less than the machine stack pointer\n        RET     C               ; then return - OK.\n\n;; REPORT-4\nL1F15:  LD      L,$03           ; prepare 'Out of Memory'\n        JP      L0055           ; jump back to ERROR-3 at $0055\n                                ; Note. this error can't be trapped at $0008\n\n; ------------------------------\n; THE 'FREE MEMORY' USER ROUTINE\n; ------------------------------\n; This routine is not used by the ROM but allows users to evaluate\n; approximate free memory with PRINT 65536 - USR 7962.\n\n;; free-mem\nL1F1A:  LD      BC,$0000        ; allow no overhead.\n\n        CALL    L1F05           ; routine TEST-ROOM.\n\n        LD      B,H             ; transfer the result\n        LD      C,L             ; to the BC register.\n        RET                     ; the USR function returns value of BC.\n\n; --------------------\n; THE 'RETURN' COMMAND\n; --------------------\n; As with any command, there are two values on the machine stack at the time\n; it is invoked.  The machine stack is below the GOSUB stack.  Both grow\n; downwards, the machine stack by two bytes, the GOSUB stack by 3 bytes.\n; The highest location is a statement byte followed by a two-byte line number.\n\n;; RETURN\nL1F23:  POP     BC              ; drop the address STMT-RET.\n        POP     HL              ; now the error address.\n        POP     DE              ; now a possible BASIC return line.\n        LD      A,D             ; the high byte $00 - $27 is\n        CP      $3E             ; compared with the traditional end-marker $3E.\n        JR      Z,L1F36         ; forward to REPORT-7 with a match.\n                                ; 'RETURN without GOSUB'\n\n; It was not the end-marker so a single statement byte remains at the base of\n; the calculator stack. It can't be popped off.\n\n        DEC     SP              ; adjust stack pointer to create room for two\n                                ; bytes.\n        EX      (SP),HL         ; statement to H, error address to base of\n                                ; new machine stack.\n        EX      DE,HL           ; statement to D,  BASIC line number to HL.\n        LD      ($5C3D),SP      ; adjust ERR_SP to point to new stack pointer\n        PUSH    BC              ; now re-stack the address STMT-RET\n        JP      L1E73           ; to GO-TO-2 to update statement and line\n                                ; system variables and exit indirectly to the\n                                ; address just pushed on stack.\n\n; ---\n\n;; REPORT-7\nL1F36:  PUSH    DE              ; replace the end-marker.\n        PUSH    HL              ; now restore the error address\n                                ; as will be required in a few clock cycles.\n\n        RST     08H             ; ERROR-1\n        DEFB    $06             ; Error Report: RETURN without GOSUB\n\n; --------------------\n; Handle PAUSE command\n; --------------------\n; The pause command takes as its parameter the number of interrupts\n; for which to wait. PAUSE 50 pauses for about a second.\n; PAUSE 0 pauses indefinitely.\n; Both forms can be finished by pressing a key.\n\n;; PAUSE\nL1F3A:  CALL    L1E99           ; routine FIND-INT2 puts value in BC\n\n;; PAUSE-1\nL1F3D:  HALT                    ; wait for interrupt.\n        DEC     BC              ; decrease counter.\n        LD      A,B             ; test if\n        OR      C               ; result is zero.\n        JR      Z,L1F4F         ; forward to PAUSE-END if so.\n\n        LD      A,B             ; test if\n        AND     C               ; now $FFFF\n        INC     A               ; that is, initially zero.\n        JR      NZ,L1F49        ; skip forward to PAUSE-2 if not.\n\n        INC     BC              ; restore counter to zero.\n\n;; PAUSE-2\nL1F49:  BIT     5,(IY+$01)      ; test FLAGS - has a new key been pressed ?\n        JR      Z,L1F3D         ; back to PAUSE-1 if not.\n\n;; PAUSE-END\nL1F4F:  RES     5,(IY+$01)      ; update FLAGS - signal no new key\n        RET                     ; and return.\n\n; -------------------\n; Check for BREAK key\n; -------------------\n; This routine is called from COPY-LINE, when interrupts are disabled,\n; to test if BREAK (SHIFT - SPACE) is being pressed.\n; It is also called at STMT-RET after every statement.\n\n;; BREAK-KEY\nL1F54:  LD      A,$7F           ; Input address: $7FFE\n        IN      A,($FE)         ; read lower right keys\n        RRA                     ; rotate bit 0 - SPACE\n        RET     C               ; return if not reset\n\n        LD      A,$FE           ; Input address: $FEFE\n        IN      A,($FE)         ; read lower left keys\n        RRA                     ; rotate bit 0 - SHIFT\n        RET                     ; carry will be set if not pressed.\n                                ; return with no carry if both keys\n                                ; pressed.\n\n; ---------------------\n; Handle DEF FN command\n; ---------------------\n; e.g. DEF FN r$(a$,a) = a$(a TO )\n; this 'command' is ignored in runtime but has its syntax checked\n; during line-entry.\n\n;; DEF-FN\nL1F60:  CALL    L2530           ; routine SYNTAX-Z\n        JR      Z,L1F6A         ; forward to DEF-FN-1 if parsing\n\n        LD      A,$CE           ; else load A with 'DEF FN' and\n        JP      L1E39           ; jump back to PASS-BY\n\n; ---\n\n; continue here if checking syntax.\n\n;; DEF-FN-1\nL1F6A:  SET      6,(IY+$01)     ; set FLAGS  - Assume numeric result\n        CALL    L2C8D           ; call routine ALPHA\n        JR      NC,L1F89        ; if not then to DEF-FN-4 to jump to\n                                ; 'Nonsense in BASIC'\n\n\n        RST     20H             ; NEXT-CHAR\n        CP      $24             ; is it '$' ?\n        JR      NZ,L1F7D        ; to DEF-FN-2 if not as numeric.\n\n        RES     6,(IY+$01)      ; set FLAGS  - Signal string result\n\n        RST     20H             ; get NEXT-CHAR\n\n;; DEF-FN-2\nL1F7D:  CP      $28             ; is it '(' ?\n        JR      NZ,L1FBD        ; to DEF-FN-7 'Nonsense in BASIC'\n\n\n        RST     20H             ; NEXT-CHAR\n        CP      $29             ; is it ')' ?\n        JR      Z,L1FA6         ; to DEF-FN-6 if null argument\n\n;; DEF-FN-3\nL1F86:  CALL    L2C8D           ; routine ALPHA checks that it is the expected\n                                ; alphabetic character.\n\n;; DEF-FN-4\nL1F89:  JP      NC,L1C8A        ; to REPORT-C  if not\n                                ; 'Nonsense in BASIC'.\n\n        EX      DE,HL           ; save pointer in DE\n\n        RST     20H             ; NEXT-CHAR re-initializes HL from CH_ADD\n                                ; and advances.\n        CP      $24             ; '$' ? is it a string argument.\n        JR      NZ,L1F94        ; forward to DEF-FN-5 if not.\n\n        EX      DE,HL           ; save pointer to '$' in DE\n\n        RST     20H             ; NEXT-CHAR re-initializes HL and advances\n\n;; DEF-FN-5\nL1F94:  EX      DE,HL           ; bring back pointer.\n        LD      BC,$0006        ; the function requires six hidden bytes for\n                                ; each parameter passed.\n                                ; The first byte will be $0E\n                                ; then 5-byte numeric value\n                                ; or 5-byte string pointer.\n\n        CALL    L1655           ; routine MAKE-ROOM creates space in program\n                                ; area.\n\n        INC     HL              ; adjust HL (set by LDDR)\n        INC     HL              ; to point to first location.\n        LD      (HL),$0E        ; insert the 'hidden' marker.\n\n; Note. these invisible storage locations hold nothing meaningful for the\n; moment. They will be used every time the corresponding function is\n; evaluated in runtime.\n; Now consider the following character fetched earlier.\n\n        CP      $2C             ; is it ',' ? (more than one parameter)\n        JR      NZ,L1FA6        ; to DEF-FN-6 if not\n\n\n        RST     20H             ; else NEXT-CHAR\n        JR      L1F86           ; and back to DEF-FN-3\n\n; ---\n\n;; DEF-FN-6\nL1FA6:  CP      $29             ; should close with a ')'\n        JR      NZ,L1FBD        ; to DEF-FN-7 if not\n                                ; 'Nonsense in BASIC'\n\n\n        RST     20H             ; get NEXT-CHAR\n        CP      $3D             ; is it '=' ?\n        JR      NZ,L1FBD        ; to DEF-FN-7 if not 'Nonsense...'\n\n\n        RST     20H             ; address NEXT-CHAR\n        LD      A,($5C3B)       ; get FLAGS which has been set above\n        PUSH    AF              ; and preserve\n\n        CALL    L24FB           ; routine SCANNING checks syntax of expression\n                                ; and also sets flags.\n\n        POP     AF              ; restore previous flags\n        XOR     (IY+$01)        ; xor with FLAGS - bit 6 should be same\n                                ; therefore will be reset.\n        AND     $40             ; isolate bit 6.\n\n;; DEF-FN-7\nL1FBD:  JP      NZ,L1C8A        ; jump back to REPORT-C if the expected result\n                                ; is not the same type.\n                                ; 'Nonsense in BASIC'\n\n        CALL    L1BEE           ; routine CHECK-END will return early if\n                                ; at end of statement and move onto next\n                                ; else produce error report. >>>\n\n                                ; There will be no return to here.\n\n; -------------------------------\n; Returning early from subroutine\n; -------------------------------\n; All routines are capable of being run in two modes - syntax checking mode\n; and runtime mode.  This routine is called often to allow a routine to return\n; early if checking syntax.\n\n;; UNSTACK-Z\nL1FC3:  CALL    L2530           ; routine SYNTAX-Z sets zero flag if syntax\n                                ; is being checked.\n\n        POP     HL              ; drop the return address.\n        RET      Z              ; return to previous call in chain if checking\n                                ; syntax.\n\n        JP      (HL)            ; jump to return address as BASIC program is\n                                ; actually running.\n\n; ---------------------\n; Handle LPRINT command\n; ---------------------\n; A simple form of 'PRINT #3' although it can output to 16 streams.\n; Probably for compatibility with other BASICs particularly ZX81 BASIC.\n; An extra UDG might have been better.\n\n;; LPRINT\nL1FC9:  LD      A,$03           ; the printer channel\n        JR      L1FCF           ; forward to PRINT-1\n\n; ---------------------\n; Handle PRINT commands\n; ---------------------\n; The Spectrum's main stream output command.\n; The default stream is stream 2 which is normally the upper screen\n; of the computer. However the stream can be altered in range 0 - 15.\n\n;; PRINT\nL1FCD:  LD      A,$02           ; the stream for the upper screen.\n\n; The LPRINT command joins here.\n\n;; PRINT-1\nL1FCF:  CALL    L2530           ; routine SYNTAX-Z checks if program running\n        CALL    NZ,L1601        ; routine CHAN-OPEN if so\n        CALL    L0D4D           ; routine TEMPS sets temporary colours.\n        CALL    L1FDF           ; routine PRINT-2 - the actual item\n        CALL    L1BEE           ; routine CHECK-END gives error if not at end\n                                ; of statement\n        RET                     ; and return >>>\n\n; ------------------------------------\n; this subroutine is called from above\n; and also from INPUT.\n\n;; PRINT-2\nL1FDF:  RST     18H             ; GET-CHAR gets printable character\n        CALL    L2045           ; routine PR-END-Z checks if more printing\n        JR      Z,L1FF2         ; to PRINT-4 if not     e.g. just 'PRINT :'\n\n; This tight loop deals with combinations of positional controls and\n; print items. An early return can be made from within the loop\n; if the end of a print sequence is reached.\n\n;; PRINT-3\nL1FE5:  CALL    L204E           ; routine PR-POSN-1 returns zero if more\n                                ; but returns early at this point if\n                                ; at end of statement!\n                                ;\n        JR      Z,L1FE5         ; to PRINT-3 if consecutive positioners\n\n        CALL    L1FFC           ; routine PR-ITEM-1 deals with strings etc.\n        CALL    L204E           ; routine PR-POSN-1 for more position codes\n        JR      Z,L1FE5         ; loop back to PRINT-3 if so\n\n;; PRINT-4\nL1FF2:  CP      $29             ; return now if this is ')' from input-item.\n                                ; (see INPUT.)\n        RET     Z               ; or continue and print carriage return in\n                                ; runtime\n\n; ---------------------\n; Print carriage return\n; ---------------------\n; This routine which continues from above prints a carriage return\n; in run-time. It is also called once from PRINT-POSN.\n\n;; PRINT-CR\nL1FF5:  CALL    L1FC3           ; routine UNSTACK-Z\n\n        LD      A,$0D           ; prepare a carriage return\n\n        RST     10H             ; PRINT-A\n        RET                     ; return\n\n\n; -----------\n; Print items\n; -----------\n; This routine deals with print items as in\n; PRINT AT 10,0;\"The value of A is \";a\n; It returns once a single item has been dealt with as it is part\n; of a tight loop that considers sequences of positional and print items\n\n;; PR-ITEM-1\nL1FFC:  RST     18H             ; GET-CHAR\n        CP      $AC             ; is character 'AT' ?\n        JR      NZ,L200E        ; forward to PR-ITEM-2 if not.\n\n        CALL    L1C79           ; routine NEXT-2NUM  check for two comma\n                                ; separated numbers placing them on the\n                                ; calculator stack in runtime.\n        CALL    L1FC3           ; routine UNSTACK-Z quits if checking syntax.\n\n        CALL    L2307           ; routine STK-TO-BC get the numbers in B and C.\n        LD      A,$16           ; prepare the 'at' control.\n        JR      L201E           ; forward to PR-AT-TAB to print the sequence.\n\n; ---\n\n;; PR-ITEM-2\nL200E:  CP      $AD             ; is character 'TAB' ?\n        JR      NZ,L2024        ; to PR-ITEM-3 if not\n\n\n        RST     20H             ; NEXT-CHAR to address next character\n        CALL    L1C82           ; routine EXPT-1NUM\n        CALL    L1FC3           ; routine UNSTACK-Z quits if checking syntax.\n\n        CALL    L1E99           ; routine FIND-INT2 puts integer in BC.\n        LD      A,$17           ; prepare the 'tab' control.\n\n;; PR-AT-TAB\nL201E:  RST     10H             ; PRINT-A outputs the control\n\n        LD      A,C             ; first value to A\n        RST     10H             ; PRINT-A outputs it.\n\n        LD      A,B             ; second value\n        RST     10H             ; PRINT-A\n\n        RET                     ; return - item finished >>>\n\n; ---\n\n; Now consider paper 2; #2; a$\n\n;; PR-ITEM-3\nL2024:  CALL    L21F2           ; routine CO-TEMP-3 will print any colour\n        RET     NC              ; items - return if success.\n\n        CALL    L2070           ; routine STR-ALTER considers new stream\n        RET     NC              ; return if altered.\n\n        CALL    L24FB           ; routine SCANNING now to evaluate expression\n        CALL    L1FC3           ; routine UNSTACK-Z if not runtime.\n\n        BIT     6,(IY+$01)      ; test FLAGS  - Numeric or string result ?\n        CALL    Z,L2BF1         ; routine STK-FETCH if string.\n                                ; note no flags affected.\n        JP      NZ,L2DE3        ; to PRINT-FP to print if numeric >>>\n\n; It was a string expression - start in DE, length in BC\n; Now enter a loop to print it\n\n;; PR-STRING\nL203C:  LD      A,B             ; this tests if the\n        OR      C               ; length is zero and sets flag accordingly.\n        DEC     BC              ; this doesn't but decrements counter.\n        RET     Z               ; return if zero.\n\n        LD      A,(DE)          ; fetch character.\n        INC     DE              ; address next location.\n\n        RST     10H             ; PRINT-A.\n\n        JR      L203C           ; loop back to PR-STRING.\n\n; ---------------\n; End of printing\n; ---------------\n; This subroutine returns zero if no further printing is required\n; in the current statement.\n; The first terminator is found in  escaped input items only,\n; the others in print_items.\n\n;; PR-END-Z\nL2045:  CP      $29             ; is character a ')' ?\n        RET     Z               ; return if so -        e.g. INPUT (p$); a$\n\n;; PR-ST-END\nL2048:  CP      $0D             ; is it a carriage return ?\n        RET     Z               ; return also -         e.g. PRINT a\n\n        CP      $3A             ; is character a ':' ?\n        RET                     ; return - zero flag will be set if so.\n                                ;                       e.g. PRINT a :\n\n; --------------\n; Print position\n; --------------\n; This routine considers a single positional character ';', ',', '''\n\n;; PR-POSN-1\nL204E:  RST     18H             ; GET-CHAR\n        CP      $3B             ; is it ';' ?\n                                ; i.e. print from last position.\n        JR      Z,L2067         ; forward to PR-POSN-3 if so.\n                                ; i.e. do nothing.\n\n        CP      $2C             ; is it ',' ?\n                                ; i.e. print at next tabstop.\n        JR      NZ,L2061        ; forward to PR-POSN-2 if anything else.\n\n        CALL    L2530           ; routine SYNTAX-Z\n        JR      Z,L2067         ; forward to PR-POSN-3 if checking syntax.\n\n        LD      A,$06           ; prepare the 'comma' control character.\n\n        RST     10H             ; PRINT-A  outputs to current channel in\n                                ; run-time.\n\n        JR      L2067           ; skip to PR-POSN-3.\n\n; ---\n\n; check for newline.\n\n;; PR-POSN-2\nL2061:  CP      $27             ; is character a \"'\" ? (newline)\n        RET     NZ              ; return if no match              >>>\n\n        CALL    L1FF5           ; routine PRINT-CR outputs a carriage return\n                                ; in runtime only.\n\n;; PR-POSN-3\nL2067:  RST     20H             ; NEXT-CHAR to A.\n        CALL    L2045           ; routine PR-END-Z checks if at end.\n        JR      NZ,L206E        ; to PR-POSN-4 if not.\n\n        POP     BC              ; drop return address if at end.\n\n;; PR-POSN-4\nL206E:  CP      A               ; reset the zero flag.\n        RET                     ; and return to loop or quit.\n\n; ------------\n; Alter stream\n; ------------\n; This routine is called from PRINT ITEMS above, and also LIST as in\n; LIST #15\n\n;; STR-ALTER\nL2070:  CP      $23             ; is character '#' ?\n        SCF                     ; set carry flag.\n        RET     NZ              ; return if no match.\n\n\n        RST      20H            ; NEXT-CHAR\n        CALL    L1C82           ; routine EXPT-1NUM gets stream number\n        AND     A               ; prepare to exit early with carry reset\n        CALL    L1FC3           ; routine UNSTACK-Z exits early if parsing\n        CALL    L1E94           ; routine FIND-INT1 gets number off stack\n        CP      $10             ; must be range 0 - 15 decimal.\n        JP      NC,L160E        ; jump back to REPORT-Oa if not\n                                ; 'Invalid stream'.\n\n        CALL    L1601           ; routine CHAN-OPEN\n        AND     A               ; clear carry - signal item dealt with.\n        RET                     ; return\n\n; -------------------\n; THE 'INPUT' COMMAND\n; -------------------\n; This command is mysterious.\n;\n\n;; INPUT\nL2089:  CALL    L2530           ; routine SYNTAX-Z to check if in runtime.\n\n        JR      Z,L2096         ; forward to INPUT-1 if checking syntax.\n\n        LD      A,$01           ; select channel 'K' the keyboard for input.\n        CALL    L1601           ; routine CHAN-OPEN opens the channel and sets\n                                ; bit 0 of TV_FLAG.\n\n;   Note. As a consequence of clearing the lower screen channel 0 is made\n;   the current channel so the above two instructions are superfluous.\n\n        CALL    L0D6E           ; routine CLS-LOWER clears the lower screen\n                                ; and sets DF_SZ to two and TV_FLAG to $01.\n\n;; INPUT-1\nL2096:  LD      (IY+$02),$01    ; update TV_FLAG - signal lower screen in use\n                                ; ensuring that the correct set of system\n                                ; variables are updated and that the border\n                                ; colour is used.\n\n;   Note. The Complete Spectrum ROM Disassembly incorrectly names DF-SZ as the\n;   system variable that is updated above and if, as some have done, you make\n;   this unnecessary alteration then there will be two blank lines between the\n;   lower screen and the upper screen areas which will also scroll wrongly.\n\n        CALL    L20C1           ; routine IN-ITEM-1 to handle the input.\n\n        CALL    L1BEE           ; routine CHECK-END will make an early exit\n                                ; if checking syntax. >>>\n\n;   Keyboard input has been made and it remains to adjust the upper\n;   screen in case the lower two lines have been extended upwards.\n\n        LD      BC,($5C88)      ; fetch S_POSN current line/column of\n                                ; the upper screen.\n        LD      A,($5C6B)       ; fetch DF_SZ the display file size of\n                                ; the lower screen.\n        CP      B               ; test that lower screen does not overlap\n        JR      C,L20AD         ; forward to INPUT-2 if not.\n\n; the two screens overlap so adjust upper screen.\n\n        LD      C,$21           ; set column of upper screen to leftmost.\n        LD      B,A             ; and line to one above lower screen.\n                                ; continue forward to update upper screen\n                                ; print position.\n\n;; INPUT-2\nL20AD:  LD      ($5C88),BC      ; set S_POSN update upper screen line/column.\n        LD      A,$19           ; subtract from twenty five\n        SUB     B               ; the new line number.\n        LD      ($5C8C),A       ; and place result in SCR_CT - scroll count.\n        RES     0,(IY+$02)      ; update TV_FLAG - signal main screen in use.\n\n        CALL    L0DD9           ; routine CL-SET sets the print position\n                                ; system variables for the upper screen.\n\n        JP      L0D6E           ; jump back to CLS-LOWER and make\n                                ; an indirect exit >>.\n\n; ---------------------\n; INPUT ITEM subroutine\n; ---------------------\n;   This subroutine deals with the input items and print items.\n;   from  the current input channel.\n;   It is only called from the above INPUT routine but was obviously\n;   once called from somewhere else in another context.\n\n;; IN-ITEM-1\nL20C1:  CALL    L204E           ; routine PR-POSN-1 deals with a single\n                                ; position item at each call.\n        JR      Z,L20C1         ; back to IN-ITEM-1 until no more in a\n                                ; sequence.\n\n        CP      $28             ; is character '(' ?\n        JR      NZ,L20D8        ; forward to IN-ITEM-2 if not.\n\n;   any variables within braces will be treated as part, or all, of the prompt\n;   instead of being used as destination variables.\n\n        RST     20H             ; NEXT-CHAR\n        CALL    L1FDF           ; routine PRINT-2 to output the dynamic\n                                ; prompt.\n\n        RST     18H             ; GET-CHAR\n        CP      $29             ; is character a matching ')' ?\n        JP      NZ,L1C8A        ; jump back to REPORT-C if not.\n                                ; 'Nonsense in BASIC'.\n\n        RST     20H             ; NEXT-CHAR\n        JP      L21B2           ; forward to IN-NEXT-2\n\n; ---\n\n;; IN-ITEM-2\nL20D8:  CP      $CA             ; is the character the token 'LINE' ?\n        JR      NZ,L20ED        ; forward to IN-ITEM-3 if not.\n\n        RST     20H             ; NEXT-CHAR - variable must come next.\n        CALL    L1C1F           ; routine CLASS-01 returns destination\n                                ; address of variable to be assigned.\n                                ; or generates an error if no variable\n                                ; at this position.\n\n        SET     7,(IY+$37)      ; update FLAGX  - signal handling INPUT LINE\n        BIT     6,(IY+$01)      ; test FLAGS  - numeric or string result ?\n        JP      NZ,L1C8A        ; jump back to REPORT-C if not string\n                                ; 'Nonsense in BASIC'.\n\n        JR      L20FA           ; forward to IN-PROMPT to set up workspace.\n\n; ---\n\n;   the jump was here for other variables.\n\n;; IN-ITEM-3\nL20ED:  CALL     L2C8D          ; routine ALPHA checks if character is\n                                ; a suitable variable name.\n        JP      NC,L21AF        ; forward to IN-NEXT-1 if not\n\n        CALL    L1C1F           ; routine CLASS-01 returns destination\n                                ; address of variable to be assigned.\n        RES     7,(IY+$37)      ; update FLAGX  - signal not INPUT LINE.\n\n;; IN-PROMPT\nL20FA:  CALL    L2530           ; routine SYNTAX-Z\n        JP      Z,L21B2         ; forward to IN-NEXT-2 if checking syntax.\n\n        CALL    L16BF           ; routine SET-WORK clears workspace.\n        LD      HL,$5C71        ; point to system variable FLAGX\n        RES     6,(HL)          ; signal string result.\n        SET     5,(HL)          ; signal in Input Mode for editor.\n        LD      BC,$0001        ; initialize space required to one for\n                                ; the carriage return.\n        BIT     7,(HL)          ; test FLAGX - INPUT LINE in use ?\n        JR      NZ,L211C        ; forward to IN-PR-2 if so as that is\n                                ; all the space that is required.\n\n        LD      A,($5C3B)       ; load accumulator from FLAGS\n        AND     $40             ; mask to test BIT 6 of FLAGS and clear\n                                ; the other bits in A.\n                                ; numeric result expected ?\n        JR      NZ,L211A        ; forward to IN-PR-1 if so\n\n        LD      C,$03           ; increase space to three bytes for the\n                                ; pair of surrounding quotes.\n\n;; IN-PR-1\nL211A:  OR      (HL)            ; if numeric result, set bit 6 of FLAGX.\n        LD      (HL),A          ; and update system variable\n\n;; IN-PR-2\nL211C:  RST     30H             ; BC-SPACES opens 1 or 3 bytes in workspace\n        LD      (HL),$0D        ; insert carriage return at last new location.\n        LD      A,C             ; fetch the length, one or three.\n        RRCA                    ; lose bit 0.\n        RRCA                    ; test if quotes required.\n        JR      NC,L2129        ; forward to IN-PR-3 if not.\n\n        LD      A,$22           ; load the '\"' character\n        LD      (DE),A          ; place quote in first new location at DE.\n        DEC     HL              ; decrease HL - from carriage return.\n        LD      (HL),A          ; and place a quote in second location.\n\n;; IN-PR-3\nL2129:  LD      ($5C5B),HL      ; set keyboard cursor K_CUR to HL\n        BIT     7,(IY+$37)      ; test FLAGX  - is this INPUT LINE ??\n        JR      NZ,L215E        ; forward to IN-VAR-3 if so as input will\n                                ; be accepted without checking its syntax.\n\n        LD      HL,($5C5D)      ; fetch CH_ADD\n        PUSH    HL              ; and save on stack.\n        LD      HL,($5C3D)      ; fetch ERR_SP\n        PUSH    HL              ; and save on stack\n\n;; IN-VAR-1\nL213A:  LD      HL,L213A        ; address: IN-VAR-1 - this address\n        PUSH    HL              ; is saved on stack to handle errors.\n        BIT     4,(IY+$30)      ; test FLAGS2  - is K channel in use ?\n        JR      Z,L2148         ; forward to IN-VAR-2 if not using the\n                                ; keyboard for input. (??)\n\n        LD      ($5C3D),SP      ; set ERR_SP to point to IN-VAR-1 on stack.\n\n;; IN-VAR-2\nL2148:  LD      HL,($5C61)      ; set HL to WORKSP - start of workspace.\n        CALL    L11A7           ; routine REMOVE-FP removes floating point\n                                ; forms when looping in error condition.\n        LD      (IY+$00),$FF    ; set ERR_NR to 'OK' cancelling the error.\n                                ; but X_PTR causes flashing error marker\n                                ; to be displayed at each call to the editor.\n        CALL    L0F2C           ; routine EDITOR allows input to be entered\n                                ; or corrected if this is second time around.\n\n; if we pass to next then there are no system errors\n\n        RES     7,(IY+$01)      ; update FLAGS  - signal checking syntax\n        CALL    L21B9           ; routine IN-ASSIGN checks syntax using\n                                ; the VAL-FET-2 and powerful SCANNING routines.\n                                ; any syntax error and its back to IN-VAR-1.\n                                ; but with the flashing error marker showing\n                                ; where the error is.\n                                ; Note. the syntax of string input has to be\n                                ; checked as the user may have removed the\n                                ; bounding quotes or escaped them as with\n                                ; \"hat\" + \"stand\" for example.\n; proceed if syntax passed.\n\n        JR      L2161           ; jump forward to IN-VAR-4\n\n; ---\n\n; the jump was to here when using INPUT LINE.\n\n;; IN-VAR-3\nL215E:  CALL    L0F2C           ; routine EDITOR is called for input\n\n; when ENTER received rejoin other route but with no syntax check.\n\n; INPUT and INPUT LINE converge here.\n\n;; IN-VAR-4\nL2161:  LD      (IY+$22),$00    ; set K_CUR_hi to a low value so that the cursor\n                                ; no longer appears in the input line.\n\n        CALL    L21D6           ; routine IN-CHAN-K tests if the keyboard\n                                ; is being used for input.\n        JR      NZ,L2174        ; forward to IN-VAR-5 if using another input\n                                ; channel.\n\n; continue here if using the keyboard.\n\n        CALL    L111D           ; routine ED-COPY overprints the edit line\n                                ; to the lower screen. The only visible\n                                ; affect is that the cursor disappears.\n                                ; if you're inputting more than one item in\n                                ; a statement then that becomes apparent.\n\n        LD      BC,($5C82)      ; fetch line and column from ECHO_E\n        CALL    L0DD9           ; routine CL-SET sets S-POSNL to those\n                                ; values.\n\n; if using another input channel rejoin here.\n\n;; IN-VAR-5\nL2174:  LD      HL,$5C71        ; point HL to FLAGX\n        RES     5,(HL)          ; signal not in input mode\n        BIT     7,(HL)          ; is this INPUT LINE ?\n        RES     7,(HL)          ; cancel the bit anyway.\n        JR      NZ,L219B        ; forward to IN-VAR-6 if INPUT LINE.\n\n        POP     HL              ; drop the looping address\n        POP     HL              ; drop the address of previous\n                                ; error handler.\n        LD      ($5C3D),HL      ; set ERR_SP to point to it.\n        POP     HL              ; drop original CH_ADD which points to\n                                ; INPUT command in BASIC line.\n        LD      ($5C5F),HL      ; save in X_PTR while input is assigned.\n        SET     7,(IY+$01)      ; update FLAGS - Signal running program\n        CALL    L21B9           ; routine IN-ASSIGN is called again\n                                ; this time the variable will be assigned\n                                ; the input value without error.\n                                ; Note. the previous example now\n                                ; becomes \"hatstand\"\n\n        LD      HL,($5C5F)      ; fetch stored CH_ADD value from X_PTR.\n        LD      (IY+$26),$00    ; set X_PTR_hi so that iy is no longer relevant.\n        LD      ($5C5D),HL      ; put restored value back in CH_ADD\n        JR      L21B2           ; forward to IN-NEXT-2 to see if anything\n                                ; more in the INPUT list.\n\n; ---\n\n; the jump was to here with INPUT LINE only\n\n;; IN-VAR-6\nL219B:  LD      HL,($5C63)      ; STKBOT points to the end of the input.\n        LD      DE,($5C61)      ; WORKSP points to the beginning.\n        SCF                     ; prepare for true subtraction.\n        SBC     HL,DE           ; subtract to get length\n        LD      B,H             ; transfer it to\n        LD      C,L             ; the BC register pair.\n        CALL    L2AB2           ; routine STK-STO-$ stores parameters on\n                                ; the calculator stack.\n        CALL    L2AFF           ; routine LET assigns it to destination.\n        JR      L21B2           ; forward to IN-NEXT-2 as print items\n                                ; not allowed with INPUT LINE.\n                                ; Note. that \"hat\" + \"stand\" will, for\n                                ; example, be unchanged as also would\n                                ; 'PRINT \"Iris was here\"'.\n\n; ---\n\n; the jump was to here when ALPHA found more items while looking for\n; a variable name.\n\n;; IN-NEXT-1\nL21AF:  CALL    L1FFC           ; routine PR-ITEM-1 considers further items.\n\n;; IN-NEXT-2\nL21B2:  CALL    L204E           ; routine PR-POSN-1 handles a position item.\n        JP      Z,L20C1         ; jump back to IN-ITEM-1 if the zero flag\n                                ; indicates more items are present.\n\n        RET                     ; return.\n\n; ---------------------------\n; INPUT ASSIGNMENT Subroutine\n; ---------------------------\n; This subroutine is called twice from the INPUT command when normal\n; keyboard input is assigned. On the first occasion syntax is checked\n; using SCANNING. The final call with the syntax flag reset is to make\n; the assignment.\n\n;; IN-ASSIGN\nL21B9:  LD      HL,($5C61)      ; fetch WORKSP start of input\n        LD      ($5C5D),HL      ; set CH_ADD to first character\n\n        RST     18H             ; GET-CHAR ignoring leading white-space.\n        CP      $E2             ; is it 'STOP'\n        JR      Z,L21D0         ; forward to IN-STOP if so.\n\n        LD      A,($5C71)       ; load accumulator from FLAGX\n        CALL    L1C59           ; routine VAL-FET-2 makes assignment\n                                ; or goes through the motions if checking\n                                ; syntax. SCANNING is used.\n\n        RST     18H             ; GET-CHAR\n        CP      $0D             ; is it carriage return ?\n        RET     Z               ; return if so\n                                ; either syntax is OK\n                                ; or assignment has been made.\n\n; if another character was found then raise an error.\n; User doesn't see report but the flashing error marker\n; appears in the lower screen.\n\n;; REPORT-Cb\nL21CE:  RST     08H             ; ERROR-1\n        DEFB    $0B             ; Error Report: Nonsense in BASIC\n\n;; IN-STOP\nL21D0:  CALL    L2530           ; routine SYNTAX-Z (UNSTACK-Z?)\n        RET     Z               ; return if checking syntax\n                                ; as user wouldn't see error report.\n                                ; but generate visible error report\n                                ; on second invocation.\n\n;; REPORT-H\nL21D4:  RST     08H             ; ERROR-1\n        DEFB    $10             ; Error Report: STOP in INPUT\n\n; -----------------------------------\n; THE 'TEST FOR CHANNEL K' SUBROUTINE\n; -----------------------------------\n;   This subroutine is called once from the keyboard INPUT command to check if\n;   the input routine in use is the one for the keyboard.\n\n;; IN-CHAN-K\nL21D6:  LD      HL,($5C51)      ; fetch address of current channel CURCHL\n        INC     HL              ;\n        INC     HL              ; advance past\n        INC     HL              ; input and\n        INC     HL              ; output streams\n        LD      A,(HL)          ; fetch the channel identifier.\n        CP      $4B             ; test for 'K'\n        RET                     ; return with zero set if keyboard is use.\n\n; --------------------\n; Colour Item Routines\n; --------------------\n;\n; These routines have 3 entry points -\n; 1) CO-TEMP-2 to handle a series of embedded Graphic colour items.\n; 2) CO-TEMP-3 to handle a single embedded print colour item.\n; 3) CO TEMP-4 to handle a colour command such as FLASH 1\n;\n; \"Due to a bug, if you bring in a peripheral channel and later use a colour\n;  statement, colour controls will be sent to it by mistake.\" - Steven Vickers\n;  Pitman Pocket Guide, 1984.\n;\n; To be fair, this only applies if the last channel was other than 'K', 'S'\n; or 'P', which are all that are supported by this ROM, but if that last\n; channel was a microdrive file, network channel etc. then\n; PAPER 6; CLS will not turn the screen yellow and\n; CIRCLE INK 2; 128,88,50 will not draw a red circle.\n;\n; This bug does not apply to embedded PRINT items as it is quite permissible\n; to mix stream altering commands and colour items.\n; The fix therefore would be to ensure that CLASS-07 and CLASS-09 make\n; channel 'S' the current channel when not checking syntax.\n; -----------------------------------------------------------------\n\n;; CO-TEMP-1\nL21E1:  RST     20H             ; NEXT-CHAR\n\n; -> Entry point from CLASS-09. Embedded Graphic colour items.\n; e.g. PLOT INK 2; PAPER 8; 128,88\n; Loops till all colour items output, finally addressing the coordinates.\n\n;; CO-TEMP-2\nL21E2:  CALL    L21F2           ; routine CO-TEMP-3 to output colour control.\n        RET     C               ; return if nothing more to output. ->\n\n\n        RST     18H             ; GET-CHAR\n        CP      $2C             ; is it ',' separator ?\n        JR      Z,L21E1         ; back if so to CO-TEMP-1\n\n        CP      $3B             ; is it ';' separator ?\n        JR      Z,L21E1         ; back to CO-TEMP-1 for more.\n\n        JP      L1C8A           ; to REPORT-C (REPORT-Cb is within range)\n                                ; 'Nonsense in BASIC'\n\n; -------------------\n; CO-TEMP-3\n; -------------------\n; -> this routine evaluates and outputs a colour control and parameter.\n; It is called from above and also from PR-ITEM-3 to handle a single embedded\n; print item e.g. PRINT PAPER 6; \"Hi\". In the latter case, the looping for\n; multiple items is within the PR-ITEM routine.\n; It is quite permissible to send these to any stream.\n\n;; CO-TEMP-3\nL21F2:  CP      $D9             ; is it 'INK' ?\n        RET     C               ; return if less.\n\n        CP      $DF             ; compare with 'OUT'\n        CCF                     ; Complement Carry Flag\n        RET     C               ; return if greater than 'OVER', $DE.\n\n        PUSH    AF              ; save the colour token.\n\n        RST     20H             ; address NEXT-CHAR\n        POP     AF              ; restore token and continue.\n\n; -> this entry point used by CLASS-07. e.g. the command PAPER 6.\n\n;; CO-TEMP-4\nL21FC:  SUB     $C9             ; reduce to control character $10 (INK)\n                                ; thru $15 (OVER).\n        PUSH    AF              ; save control.\n        CALL    L1C82           ; routine EXPT-1NUM stacks addressed\n                                ; parameter on calculator stack.\n        POP     AF              ; restore control.\n        AND     A               ; clear carry\n\n        CALL    L1FC3           ; routine UNSTACK-Z returns if checking syntax.\n\n        PUSH    AF              ; save again\n        CALL    L1E94           ; routine FIND-INT1 fetches parameter to A.\n        LD      D,A             ; transfer now to D\n        POP     AF              ; restore control.\n\n        RST     10H             ; PRINT-A outputs the control to current\n                                ; channel.\n        LD      A,D             ; transfer parameter to A.\n\n        RST     10H             ; PRINT-A outputs parameter.\n        RET                     ; return. ->\n\n; -------------------------------------------------------------------------\n;\n;         {fl}{br}{   paper   }{  ink    }    The temporary colour attributes\n;          ___ ___ ___ ___ ___ ___ ___ ___    system variable.\n; ATTR_T  |   |   |   |   |   |   |   |   |\n;         |   |   |   |   |   |   |   |   |\n; 23695   |___|___|___|___|___|___|___|___|\n;           7   6   5   4   3   2   1   0\n;\n;\n;         {fl}{br}{   paper   }{  ink    }    The temporary mask used for\n;          ___ ___ ___ ___ ___ ___ ___ ___    transparent colours. Any bit\n; MASK_T  |   |   |   |   |   |   |   |   |   that is 1 shows that the\n;         |   |   |   |   |   |   |   |   |   corresponding attribute is\n; 23696   |___|___|___|___|___|___|___|___|   taken not from ATTR-T but from\n;           7   6   5   4   3   2   1   0     what is already on the screen.\n;\n;\n;         {paper9 }{ ink9 }{ inv1 }{ over1}   The print flags. Even bits are\n;          ___ ___ ___ ___ ___ ___ ___ ___    temporary flags. The odd bits\n; P_FLAG  |   |   |   |   |   |   |   |   |   are the permanent flags.\n;         | p | t | p | t | p | t | p | t |\n; 23697   |___|___|___|___|___|___|___|___|\n;           7   6   5   4   3   2   1   0\n;\n; -----------------------------------------------------------------------\n\n; ------------------------------------\n;  The colour system variable handler.\n; ------------------------------------\n; This is an exit branch from PO-1-OPER, PO-2-OPER\n; A holds control $10 (INK) to $15 (OVER)\n; D holds parameter 0-9 for ink/paper 0,1 or 8 for bright/flash,\n; 0 or 1 for over/inverse.\n\n;; CO-TEMP-5\nL2211:  SUB     $11             ; reduce range $FF-$04\n        ADC     A,$00           ; add in carry if INK\n        JR      Z,L2234         ; forward to CO-TEMP-7 with INK and PAPER.\n\n        SUB     $02             ; reduce range $FF-$02\n        ADC     A,$00           ; add carry if FLASH\n        JR      Z,L2273         ; forward to CO-TEMP-C with FLASH and BRIGHT.\n\n        CP      $01             ; is it 'INVERSE' ?\n        LD      A,D             ; fetch parameter for INVERSE/OVER\n        LD      B,$01           ; prepare OVER mask setting bit 0.\n        JR      NZ,L2228        ; forward to CO-TEMP-6 if OVER\n\n        RLCA                    ; shift bit 0\n        RLCA                    ; to bit 2\n        LD      B,$04           ; set bit 2 of mask for inverse.\n\n;; CO-TEMP-6\nL2228:  LD      C,A             ; save the A\n        LD      A,D             ; re-fetch parameter\n        CP      $02             ; is it less than 2\n        JR      NC,L2244        ; to REPORT-K if not 0 or 1.\n                                ; 'Invalid colour'.\n\n        LD      A,C             ; restore A\n        LD      HL,$5C91        ; address system variable P_FLAG\n        JR      L226C           ; forward to exit via routine CO-CHANGE\n\n; ---\n\n; the branch was here with INK/PAPER and carry set for INK.\n\n;; CO-TEMP-7\nL2234:  LD      A,D             ; fetch parameter\n        LD      B,$07           ; set ink mask 00000111\n        JR      C,L223E         ; forward to CO-TEMP-8 with INK\n\n        RLCA                    ; shift bits 0-2\n        RLCA                    ; to\n        RLCA                    ; bits 3-5\n        LD      B,$38           ; set paper mask 00111000\n\n; both paper and ink rejoin here\n\n;; CO-TEMP-8\nL223E:  LD      C,A             ; value to C\n        LD      A,D             ; fetch parameter\n        CP      $0A             ; is it less than 10d ?\n        JR      C,L2246         ; forward to CO-TEMP-9 if so.\n\n; ink 10 etc. is not allowed.\n\n;; REPORT-K\nL2244:  RST     08H             ; ERROR-1\n        DEFB    $13             ; Error Report: Invalid colour\n\n;; CO-TEMP-9\nL2246:  LD      HL,$5C8F        ; address system variable ATTR_T initially.\n        CP      $08             ; compare with 8\n        JR      C,L2258         ; forward to CO-TEMP-B with 0-7.\n\n        LD      A,(HL)          ; fetch temporary attribute as no change.\n        JR      Z,L2257         ; forward to CO-TEMP-A with INK/PAPER 8\n\n; it is either ink 9 or paper 9 (contrasting)\n\n        OR      B               ; or with mask to make white\n        CPL                     ; make black and change other to dark\n        AND     $24             ; 00100100\n        JR      Z,L2257         ; forward to CO-TEMP-A if black and\n                                ; originally light.\n\n        LD      A,B             ; else just use the mask (white)\n\n;; CO-TEMP-A\nL2257:  LD      C,A             ; save A in C\n\n;; CO-TEMP-B\nL2258:  LD      A,C             ; load colour to A\n        CALL    L226C           ; routine CO-CHANGE addressing ATTR-T\n\n        LD      A,$07           ; put 7 in accumulator\n        CP      D               ; compare with parameter\n        SBC     A,A             ; $00 if 0-7, $FF if 8\n        CALL    L226C           ; routine CO-CHANGE addressing MASK-T\n                                ; mask returned in A.\n\n; now consider P-FLAG.\n\n        RLCA                    ; 01110000 or 00001110\n        RLCA                    ; 11100000 or 00011100\n        AND     $50             ; 01000000 or 00010000  (AND 01010000)\n        LD      B,A             ; transfer to mask\n        LD      A,$08           ; load A with 8\n        CP      D               ; compare with parameter\n        SBC     A,A             ; $FF if was 9,  $00 if 0-8\n                                ; continue while addressing P-FLAG\n                                ; setting bit 4 if ink 9\n                                ; setting bit 6 if paper 9\n\n; -----------------------\n; Handle change of colour\n; -----------------------\n; This routine addresses a system variable ATTR_T, MASK_T or P-FLAG in HL.\n; colour value in A, mask in B.\n\n;; CO-CHANGE\nL226C:  XOR     (HL)            ; impress bits specified\n        AND     B               ; by mask\n        XOR     (HL)            ; on system variable.\n        LD      (HL),A          ; update system variable.\n        INC     HL              ; address next location.\n        LD      A,B             ; put current value of mask in A\n        RET                     ; return.\n\n; ---\n\n; the branch was here with flash and bright\n\n;; CO-TEMP-C\nL2273:  SBC     A,A             ; set zero flag for bright.\n        LD      A,D             ; fetch original parameter 0,1 or 8\n        RRCA                    ; rotate bit 0 to bit 7\n        LD      B,$80           ; mask for flash 10000000\n        JR      NZ,L227D        ; forward to CO-TEMP-D if flash\n\n        RRCA                    ; rotate bit 7 to bit 6\n        LD      B,$40           ; mask for bright 01000000\n\n;; CO-TEMP-D\nL227D:  LD      C,A             ; store value in C\n        LD      A,D             ; fetch parameter\n        CP      $08             ; compare with 8\n        JR      Z,L2287         ; forward to CO-TEMP-E if 8\n\n        CP      $02             ; test if 0 or 1\n        JR      NC,L2244        ; back to REPORT-K if not\n                                ; 'Invalid colour'\n\n;; CO-TEMP-E\nL2287:  LD      A,C             ; value to A\n        LD      HL,$5C8F        ; address ATTR_T\n        CALL    L226C           ; routine CO-CHANGE addressing ATTR_T\n        LD      A,C             ; fetch value\n        RRCA                    ; for flash8/bright8 complete\n        RRCA                    ; rotations to put set bit in\n        RRCA                    ; bit 7 (flash) bit 6 (bright)\n        JR      L226C           ; back to CO-CHANGE addressing MASK_T\n                                ; and indirect return.\n\n; ---------------------\n; Handle BORDER command\n; ---------------------\n; Command syntax example: BORDER 7\n; This command routine sets the border to one of the eight colours.\n; The colours used for the lower screen are based on this.\n\n;; BORDER\nL2294:  CALL    L1E94           ; routine FIND-INT1\n        CP      $08             ; must be in range 0 (black) to 7 (white)\n        JR      NC,L2244        ; back to REPORT-K if not\n                                ; 'Invalid colour'.\n\n        OUT     ($FE),A         ; outputting to port effects an immediate\n                                ; change.\n        RLCA                    ; shift the colour to\n        RLCA                    ; the paper bits setting the\n        RLCA                    ; ink colour black.\n        BIT     5,A             ; is the number light coloured ?\n                                ; i.e. in the range green to white.\n        JR      NZ,L22A6        ; skip to BORDER-1 if so\n\n        XOR     $07             ; make the ink white.\n\n;; BORDER-1\nL22A6:  LD      ($5C48),A       ; update BORDCR with new paper/ink\n        RET                     ; return.\n\n; -----------------\n; Get pixel address\n; -----------------\n;\n;\n\n;; PIXEL-ADD\nL22AA:  LD      A,$AF           ; load with 175 decimal.\n        SUB     B               ; subtract the y value.\n        JP      C,L24F9         ; jump forward to REPORT-Bc if greater.\n                                ; 'Integer out of range'\n\n; the high byte is derived from Y only.\n; the first 3 bits are always 010\n; the next 2 bits denote in which third of the screen the byte is.\n; the last 3 bits denote in which of the 8 scan lines within a third\n; the byte is located. There are 24 discrete values.\n\n\n        LD      B,A             ; the line number from top of screen to B.\n        AND     A               ; clear carry (already clear)\n        RRA                     ;                     0xxxxxxx\n        SCF                     ; set carry flag\n        RRA                     ;                     10xxxxxx\n        AND     A               ; clear carry flag\n        RRA                     ;                     010xxxxx\n\n        XOR     B               ;\n        AND     $F8             ; keep the top 5 bits 11111000\n        XOR     B               ;                     010xxbbb\n        LD      H,A             ; transfer high byte to H.\n\n; the low byte is derived from both X and Y.\n\n        LD      A,C             ; the x value 0-255.\n        RLCA                    ;\n        RLCA                    ;\n        RLCA                    ;\n        XOR     B               ; the y value\n        AND     $C7             ; apply mask             11000111\n        XOR     B               ; restore unmasked bits  xxyyyxxx\n        RLCA                    ; rotate to              xyyyxxxx\n        RLCA                    ; required position.     yyyxxxxx\n        LD      L,A             ; low byte to L.\n\n; finally form the pixel position in A.\n\n        LD      A,C             ; x value to A\n        AND     $07             ; mod 8\n        RET                     ; return\n\n; ----------------\n; Point Subroutine\n; ----------------\n; The point subroutine is called from s-point via the scanning functions\n; table.\n\n;; POINT-SUB\nL22CB:  CALL    L2307           ; routine STK-TO-BC\n        CALL    L22AA           ; routine PIXEL-ADD finds address of pixel.\n        LD      B,A             ; pixel position to B, 0-7.\n        INC     B               ; increment to give rotation count 1-8.\n        LD      A,(HL)          ; fetch byte from screen.\n\n;; POINT-LP\nL22D4:  RLCA                    ; rotate and loop back\n        DJNZ    L22D4           ; to POINT-LP until pixel at right.\n\n        AND      $01            ; test to give zero or one.\n        JP      L2D28           ; jump forward to STACK-A to save result.\n\n; -------------------\n; Handle PLOT command\n; -------------------\n; Command Syntax example: PLOT 128,88\n;\n\n;; PLOT\nL22DC:  CALL    L2307           ; routine STK-TO-BC\n        CALL    L22E5           ; routine PLOT-SUB\n        JP      L0D4D           ; to TEMPS\n\n; -------------------\n; The Plot subroutine\n; -------------------\n; A screen byte holds 8 pixels so it is necessary to rotate a mask\n; into the correct position to leave the other 7 pixels unaffected.\n; However all 64 pixels in the character cell take any embedded colour\n; items.\n; A pixel can be reset (inverse 1), toggled (over 1), or set ( with inverse\n; and over switches off). With both switches on, the byte is simply put\n; back on the screen though the colours may change.\n\n;; PLOT-SUB\nL22E5:  LD      ($5C7D),BC      ; store new x/y values in COORDS\n        CALL    L22AA           ; routine PIXEL-ADD gets address in HL,\n                                ; count from left 0-7 in B.\n        LD      B,A             ; transfer count to B.\n        INC     B               ; increase 1-8.\n        LD      A,$FE           ; 11111110 in A.\n\n;; PLOT-LOOP\nL22F0:  RRCA                    ; rotate mask.\n        DJNZ    L22F0           ; to PLOT-LOOP until B circular rotations.\n\n        LD      B,A             ; load mask to B\n        LD      A,(HL)          ; fetch screen byte to A\n\n        LD      C,(IY+$57)      ; P_FLAG to C\n        BIT     0,C             ; is it to be OVER 1 ?\n        JR      NZ,L22FD        ; forward to PL-TST-IN if so.\n\n; was over 0\n\n        AND     B               ; combine with mask to blank pixel.\n\n;; PL-TST-IN\nL22FD:  BIT     2,C             ; is it inverse 1 ?\n        JR      NZ,L2303        ; to PLOT-END if so.\n\n        XOR     B               ; switch the pixel\n        CPL                     ; restore other 7 bits\n\n;; PLOT-END\nL2303:  LD      (HL),A          ; load byte to the screen.\n        JP      L0BDB           ; exit to PO-ATTR to set colours for cell.\n\n; ------------------------------\n; Put two numbers in BC register\n; ------------------------------\n;\n;\n\n;; STK-TO-BC\nL2307:  CALL    L2314           ; routine STK-TO-A\n        LD      B,A             ;\n        PUSH    BC              ;\n        CALL    L2314           ; routine STK-TO-A\n        LD      E,C             ;\n        POP     BC              ;\n        LD      D,C             ;\n        LD      C,A             ;\n        RET                     ;\n\n; -----------------------\n; Put stack in A register\n; -----------------------\n; This routine puts the last value on the calculator stack into the accumulator\n; deleting the last value.\n\n;; STK-TO-A\nL2314:  CALL    L2DD5           ; routine FP-TO-A compresses last value into\n                                ; accumulator. e.g. PI would become 3.\n                                ; zero flag set if positive.\n        JP      C,L24F9         ; jump forward to REPORT-Bc if >= 255.5.\n\n        LD      C,$01           ; prepare a positive sign byte.\n        RET     Z               ; return if FP-TO-BC indicated positive.\n\n        LD      C,$FF           ; prepare negative sign byte and\n        RET                     ; return.\n\n\n; --------------------\n; THE 'CIRCLE' COMMAND\n; --------------------\n;   \"Goe not Thou about to Square eyther circle\" -\n;   - John Donne, Cambridge educated theologian, 1624\n;\n;   The CIRCLE command draws a circle as a series of straight lines.\n;   In some ways it can be regarded as a polygon, but the first line is drawn\n;   as a tangent, taking the radius as its distance from the centre.\n;\n;   Both the CIRCLE algorithm and the ARC drawing algorithm make use of the\n;   'ROTATION FORMULA' (see later).  It is only necessary to work out where\n;   the first line will be drawn and how long it is and then the rotation\n;   formula takes over and calculates all other rotated points.\n;\n;   All Spectrum circles consist of two vertical lines at each side and two\n;   horizontal lines at the top and bottom. The number of lines is calculated\n;   from the radius of the circle and is always divisible by 4. For complete\n;   circles it will range from 4 for a square circle to 32 for a circle of\n;   radius 87. The Spectrum can attempt larger circles e.g. CIRCLE 0,14,255\n;   but these will error as they go off-screen after four lines are drawn.\n;   At the opposite end, CIRCLE 128,88,1.23 will draw a circle as a perfect 3x3\n;   square using 4 straight lines although very small circles are just drawn as\n;   a dot on the screen.\n;\n;   The first chord drawn is the vertical chord on the right of the circle.\n;   The starting point is at the base of this chord which is drawn upwards and\n;   the circle continues in an anti-clockwise direction. As noted earlier the\n;   x-coordinate of this point measured from the centre of the circle is the\n;   radius.\n;\n;   The CIRCLE command makes extensive use of the calculator and as part of\n;   process of drawing a large circle, free memory is checked 1315 times.\n;   When drawing a large arc, free memory is checked 928 times.\n;   A single call to 'sin' involves 63 memory checks and so values of sine\n;   and cosine are pre-calculated and held in the mem locations. As a\n;   clever trick 'cos' is derived from 'sin' using simple arithmetic operations\n;   instead of the more expensive 'cos' function.\n;\n;   Initially, the syntax has been partly checked using the class for the DRAW\n;   command which stacks the origin of the circle (X,Y).\n\n;; CIRCLE\nL2320:  RST     18H             ; GET-CHAR              x, y.\n        CP      $2C             ; Is character the required comma ?\n        JP      NZ,L1C8A        ; Jump, if not, to REPORT-C\n                                ; 'Nonsense in basic'\n\n        RST     20H             ; NEXT-CHAR advances the parsed character address.\n        CALL    L1C82           ; routine EXPT-1NUM stacks radius in runtime.\n        CALL    L1BEE           ; routine CHECK-END will return here in runtime\n                                ; if nothing follows the command.\n\n;   Now make the radius positive and ensure that it is in floating point form\n;   so that the exponent byte can be accessed for quick testing.\n\n        RST     28H             ;; FP-CALC              x, y, r.\n        DEFB    $2A             ;;abs                   x, y, r.\n        DEFB    $3D             ;;re-stack              x, y, r.\n        DEFB    $38             ;;end-calc              x, y, r.\n\n        LD      A,(HL)          ; Fetch first, floating-point, exponent byte.\n        CP      $81             ; Compare to one.\n        JR      NC,L233B        ; Forward to C-R-GRE-1\n                                ; if circle radius is greater than one.\n\n;    The circle is no larger than a single pixel so delete the radius from the\n;    calculator stack and plot a point at the centre.\n\n        RST     28H             ;; FP-CALC              x, y, r.\n        DEFB    $02             ;;delete                x, y.\n        DEFB    $38             ;;end-calc              x, y.\n\n        JR      L22DC           ; back to PLOT routine to just plot x,y.\n\n; ---\n\n;   Continue when the circle's radius measures greater than one by forming\n;   the angle 2 * PI radians which is 360 degrees.\n\n;; C-R-GRE-1\nL233B:  RST     28H             ;; FP-CALC      x, y, r\n        DEFB    $A3             ;;stk-pi/2      x, y, r, pi/2.\n        DEFB    $38             ;;end-calc      x, y, r, pi/2.\n\n;   Change the exponent of pi/2 from $81 to $83 giving 2*PI the central angle.\n;   This is quicker than multiplying by four.\n\n        LD      (HL),$83        ;               x, y, r, 2*PI.\n\n;   Now store this important constant in mem-5 and delete so that other\n;   parameters can be derived from it, by a routine shared with DRAW.\n\n        RST     28H             ;; FP-CALC      x, y, r, 2*PI.\n        DEFB    $C5             ;;st-mem-5      store 2*PI in mem-5\n        DEFB    $02             ;;delete        x, y, r.\n        DEFB    $38             ;;end-calc      x, y, r.\n\n;   The parameters derived from mem-5 (A) and from the radius are set up in\n;   four of the other mem locations by the CIRCLE DRAW PARAMETERS routine which\n;   also returns the number of straight lines in the B register.\n\n        CALL    L247D           ; routine CD-PRMS1\n\n                                ; mem-0 ; A/No of lines (=a)            unused\n                                ; mem-1 ; sin(a/2)  will be moving x    var\n                                ; mem-2 ; -         will be moving y    var\n                                ; mem-3 ; cos(a)                        const\n                                ; mem-4 ; sin(a)                        const\n                                ; mem-5 ; Angle of rotation (A) (2*PI)  const\n                                ; B     ; Number of straight lines.\n\n        PUSH    BC              ; Preserve the number of lines in B.\n\n;   Next calculate the length of half a chord by multiplying the sine of half\n;   the central angle by the radius of the circle.\n\n        RST     28H             ;; FP-CALC      x, y, r.\n        DEFB    $31             ;;duplicate     x, y, r, r.\n        DEFB    $E1             ;;get-mem-1     x, y, r, r, sin(a/2).\n        DEFB    $04             ;;multiply      x, y, r, half-chord.\n        DEFB    $38             ;;end-calc      x, y, r, half-chord.\n\n        LD      A,(HL)          ; fetch exponent  of the half arc to A.\n        CP      $80             ; compare to a half pixel\n        JR      NC,L235A        ; forward, if greater than .5, to C-ARC-GE1\n\n;   If the first line is less than .5 then 4 'lines' would be drawn on the same\n;   spot so tidy the calculator stack and machine stack and plot the centre.\n\n        RST     28H             ;; FP-CALC      x, y, r, hc.\n        DEFB    $02             ;;delete        x, y, r.\n        DEFB    $02             ;;delete        x, y.\n        DEFB    $38             ;;end-calc      x, y.\n\n        POP     BC              ; Balance machine stack by taking chord-count.\n\n        JP      L22DC           ; JUMP to PLOT\n\n; ---\n\n;   The arc is greater than 0.5 so the circle can be drawn.\n\n;; C-ARC-GE1\nL235A:  RST     28H             ;; FP-CALC      x, y, r, hc.\n        DEFB    $C2             ;;st-mem-2      x, y, r, half chord to mem-2.\n        DEFB    $01             ;;exchange      x, y, hc, r.\n        DEFB    $C0             ;;st-mem-0      x, y, hc, r.\n        DEFB    $02             ;;delete        x, y, hc.\n\n;   Subtract the length of the half-chord from the absolute y coordinate to\n;   give the starting y coordinate sy.\n;   Note that for a circle this is also the end coordinate.\n\n        DEFB    $03             ;;subtract      x, y-hc.  (The start y-coord)\n        DEFB    $01             ;;exchange      sy, x.\n\n;   Next simply add the radius to the x coordinate to give a fuzzy x-coordinate.\n;   Strictly speaking, the radius should be multiplied by cos(a/2) first but\n;   doing it this way makes the circle slightly larger.\n\n        DEFB    $E0             ;;get-mem-0     sy, x, r.\n        DEFB    $0F             ;;addition      sy, x+r.  (The start x-coord)\n\n;   We now want three copies of this pair of values on the calculator stack.\n;   The first pair remain on the stack throughout the circle routine and are\n;   the end points. The next pair will be the moving absolute values of x and y\n;   that are updated after each line is drawn. The final pair will be loaded\n;   into the COORDS system variable so that the first vertical line starts at\n;   the right place.\n\n        DEFB    $C0             ;;st-mem-0      sy, sx.\n        DEFB    $01             ;;exchange      sx, sy.\n        DEFB    $31             ;;duplicate     sx, sy, sy.\n        DEFB    $E0             ;;get-mem-0     sx, sy, sy, sx.\n        DEFB    $01             ;;exchange      sx, sy, sx, sy.\n        DEFB    $31             ;;duplicate     sx, sy, sx, sy, sy.\n        DEFB    $E0             ;;get-mem-0     sx, sy, sx, sy, sy, sx.\n\n;   Locations mem-1 and mem-2 are the relative x and y values which are updated\n;   after each line is drawn. Since we are drawing a vertical line then the rx\n;   value in mem-1 is zero and the ry value in mem-2 is the full chord.\n\n        DEFB    $A0             ;;stk-zero      sx, sy, sx, sy, sy, sx, 0.\n        DEFB    $C1             ;;st-mem-1      sx, sy, sx, sy, sy, sx, 0.\n        DEFB    $02             ;;delete        sx, sy, sx, sy, sy, sx.\n\n;   Although the three pairs of x/y values are the same for a circle, they\n;   will be labelled terminating, absolute and start coordinates.\n\n        DEFB    $38             ;;end-calc      tx, ty, ax, ay, sy, sx.\n\n;   Use the exponent manipulating trick again to double the value of mem-2.\n\n        INC     (IY+$62)        ; Increment MEM-2-1st doubling half chord.\n\n;   Note. this first vertical chord is drawn at the radius so circles are\n;   slightly displaced to the right.\n;   It is only necessary to place the values (sx) and (sy) in the system\n;   variable COORDS to ensure that drawing commences at the correct pixel.\n;   Note. a couple of LD (COORDS),A instructions would have been quicker, and\n;   simpler, than using LD (COORDS),HL.\n\n        CALL    L1E94           ; routine FIND-INT1 fetches sx from stack to A.\n\n        LD      L,A             ; place X value in L.\n        PUSH    HL              ; save the holding register.\n\n        CALL    L1E94           ; routine FIND-INT1 fetches sy to A\n\n        POP     HL              ; restore the holding register.\n        LD      H,A             ; and place y value in high byte.\n\n        LD      ($5C7D),HL      ; Update the COORDS system variable.\n                                ;\n                                ;               tx, ty, ax, ay.\n\n        POP     BC              ; restore the chord count\n                                ; values 4,8,12,16,20,24,28 or 32.\n\n        JP      L2420           ; forward to DRW-STEPS\n                                ;               tx, ty, ax, ay.\n\n;   Note. the jump to DRW-STEPS is just to decrement B and jump into the\n;   middle of the arc-drawing loop. The arc count which includes the first\n;   vertical arc draws one less than the perceived number of arcs.\n;   The final arc offsets are obtained by subtracting the final COORDS value\n;   from the initial sx and sy values which are kept at the base of the\n;   calculator stack throughout the arc loop.\n;   This ensures that the final line finishes exactly at the starting pixel\n;   removing the possibility of any inaccuracy.\n;   Since the initial sx and sy values are not required until the final arc\n;   is drawn, they are not shown until then.\n;   As the calculator stack is quite busy, only the active parts are shown in\n;   each section.\n\n\n; ------------------\n; THE 'DRAW' COMMAND\n; ------------------\n;   The Spectrum's DRAW command is overloaded and can take two parameters sets.\n;\n;   With two parameters, it simply draws an approximation to a straight line\n;   at offset x,y using the LINE-DRAW routine.\n;\n;   With three parameters, an arc is drawn to the point at offset x,y turning\n;   through an angle, in radians, supplied by the third parameter.\n;   The arc will consist of 4 to 252 straight lines each one of which is drawn\n;   by calls to the DRAW-LINE routine.\n\n;; DRAW\nL2382:  RST     18H             ; GET-CHAR\n        CP      $2C             ; is it the comma character ?\n        JR      Z,L238D         ; forward, if so, to DR-3-PRMS\n\n;   There are two parameters e.g. DRAW 255,175\n\n        CALL    L1BEE           ; routine CHECK-END\n\n        JP      L2477           ; jump forward to LINE-DRAW\n\n; ---\n\n;    There are three parameters e.g. DRAW 255, 175, .5\n;    The first two are relative coordinates and the third is the angle of\n;    rotation in radians (A).\n\n;; DR-3-PRMS\nL238D:  RST     20H             ; NEXT-CHAR skips over the 'comma'.\n\n        CALL    L1C82           ; routine EXPT-1NUM stacks the rotation angle.\n\n        CALL    L1BEE           ; routine CHECK-END\n\n;   Now enter the calculator and store the complete rotation angle in mem-5\n\n        RST     28H             ;; FP-CALC      x, y, A.\n        DEFB    $C5             ;;st-mem-5      x, y, A.\n\n;   Test the angle for the special case of 360 degrees.\n\n        DEFB    $A2             ;;stk-half      x, y, A, 1/2.\n        DEFB    $04             ;;multiply      x, y, A/2.\n        DEFB    $1F             ;;sin           x, y, sin(A/2).\n        DEFB    $31             ;;duplicate     x, y, sin(A/2),sin(A/2)\n        DEFB    $30             ;;not           x, y, sin(A/2), (0/1).\n        DEFB    $30             ;;not           x, y, sin(A/2), (1/0).\n        DEFB    $00             ;;jump-true     x, y, sin(A/2).\n\n        DEFB    $06             ;;forward to L23A3, DR-SIN-NZ\n                                ; if sin(r/2) is not zero.\n\n;   The third parameter is 2*PI (or a multiple of 2*PI) so a 360 degrees turn\n;   would just be a straight line.  Eliminating this case here prevents\n;   division by zero at later stage.\n\n        DEFB    $02             ;;delete        x, y.\n        DEFB    $38             ;;end-calc      x, y.\n\n        JP      L2477           ; forward to LINE-DRAW\n\n; ---\n\n;   An arc can be drawn.\n\n;; DR-SIN-NZ\nL23A3:  DEFB    $C0             ;;st-mem-0      x, y, sin(A/2).   store mem-0\n        DEFB    $02             ;;delete        x, y.\n\n;   The next step calculates (roughly) the diameter of the circle of which the\n;   arc will form part.  This value does not have to be too accurate as it is\n;   only used to evaluate the number of straight lines and then discarded.\n;   After all for a circle, the radius is used. Consequently, a circle of\n;   radius 50 will have 24 straight lines but an arc of radius 50 will have 20\n;   straight lines - when drawn in any direction.\n;   So that simple arithmetic can be used, the length of the chord can be\n;   calculated as X+Y rather than by Pythagoras Theorem and the sine of the\n;   nearest angle within reach is used.\n\n        DEFB    $C1             ;;st-mem-1      x, y.             store mem-1\n        DEFB    $02             ;;delete        x.\n\n        DEFB    $31             ;;duplicate     x, x.\n        DEFB    $2A             ;;abs           x, x (+ve).\n        DEFB    $E1             ;;get-mem-1     x, X, y.\n        DEFB    $01             ;;exchange      x, y, X.\n        DEFB    $E1             ;;get-mem-1     x, y, X, y.\n        DEFB    $2A             ;;abs           x, y, X, Y (+ve).\n        DEFB    $0F             ;;addition      x, y, X+Y.\n        DEFB    $E0             ;;get-mem-0     x, y, X+Y, sin(A/2).\n        DEFB    $05             ;;division      x, y, X+Y/sin(A/2).\n        DEFB    $2A             ;;abs           x, y, X+Y/sin(A/2) = D.\n\n;    Bring back sin(A/2) from mem-0 which will shortly get trashed.\n;    Then bring D to the top of the stack again.\n\n        DEFB    $E0             ;;get-mem-0     x, y, D, sin(A/2).\n        DEFB    $01             ;;exchange      x, y, sin(A/2), D.\n\n;   Note. that since the value at the top of the stack has arisen as a result\n;   of division then it can no longer be in integer form and the next re-stack\n;   is unnecessary. Only the Sinclair ZX80 had integer division.\n\n        DEFB    $3D             ;;re-stack      (unnecessary)\n\n        DEFB    $38             ;;end-calc      x, y, sin(A/2), D.\n\n;   The next test avoids drawing 4 straight lines when the start and end pixels\n;   are adjacent (or the same) but is probably best dispensed with.\n\n        LD      A,(HL)          ; fetch exponent byte of D.\n        CP      $81             ; compare to 1\n        JR      NC,L23C1        ; forward, if > 1,  to DR-PRMS\n\n;   else delete the top two stack values and draw a simple straight line.\n\n        RST     28H             ;; FP-CALC\n        DEFB    $02             ;;delete\n        DEFB    $02             ;;delete\n        DEFB    $38             ;;end-calc      x, y.\n\n        JP      L2477           ; to LINE-DRAW\n\n; ---\n\n;   The ARC will consist of multiple straight lines so call the CIRCLE-DRAW\n;   PARAMETERS ROUTINE to pre-calculate sine values from the angle (in mem-5)\n;   and determine also the number of straight lines from that value and the\n;   'diameter' which is at the top of the calculator stack.\n\n;; DR-PRMS\nL23C1:  CALL    L247D           ; routine CD-PRMS1\n\n                                ; mem-0 ; (A)/No. of lines (=a) (step angle)\n                                ; mem-1 ; sin(a/2)\n                                ; mem-2 ; -\n                                ; mem-3 ; cos(a)                        const\n                                ; mem-4 ; sin(a)                        const\n                                ; mem-5 ; Angle of rotation (A)         in\n                                ; B     ; Count of straight lines - max 252.\n\n        PUSH    BC              ; Save the line count on the machine stack.\n\n;   Remove the now redundant diameter value D.\n\n        RST     28H             ;; FP-CALC      x, y, sin(A/2), D.\n        DEFB    $02             ;;delete        x, y, sin(A/2).\n\n;   Dividing the sine of the step angle by the sine of the total angle gives\n;   the length of the initial chord on a unary circle. This factor f is used\n;   to scale the coordinates of the first line which still points in the\n;   direction of the end point and may be larger.\n\n        DEFB    $E1             ;;get-mem-1     x, y, sin(A/2), sin(a/2)\n        DEFB    $01             ;;exchange      x, y, sin(a/2), sin(A/2)\n        DEFB    $05             ;;division      x, y, sin(a/2)/sin(A/2)\n        DEFB    $C1             ;;st-mem-1      x, y. f.\n        DEFB    $02             ;;delete        x, y.\n\n;   With the factor stored, scale the x coordinate first.\n\n        DEFB    $01             ;;exchange      y, x.\n        DEFB    $31             ;;duplicate     y, x, x.\n        DEFB    $E1             ;;get-mem-1     y, x, x, f.\n        DEFB    $04             ;;multiply      y, x, x*f    (=xx)\n        DEFB    $C2             ;;st-mem-2      y, x, xx.\n        DEFB    $02             ;;delete        y. x.\n\n;   Now scale the y coordinate.\n\n        DEFB    $01             ;;exchange      x, y.\n        DEFB    $31             ;;duplicate     x, y, y.\n        DEFB    $E1             ;;get-mem-1     x, y, y, f\n        DEFB    $04             ;;multiply      x, y, y*f    (=yy)\n\n;   Note. 'sin' and 'cos' trash locations mem-0 to mem-2 so fetch mem-2 to the\n;   calculator stack for safe keeping.\n\n        DEFB    $E2             ;;get-mem-2     x, y, yy, xx.\n\n;   Once we get the coordinates of the first straight line then the 'ROTATION\n;   FORMULA' used in the arc loop will take care of all other points, but we\n;   now use a variation of that formula to rotate the first arc through (A-a)/2\n;   radians.\n;\n;       xRotated = y * sin(angle) + x * cos(angle)\n;       yRotated = y * cos(angle) - x * sin(angle)\n;\n\n        DEFB    $E5             ;;get-mem-5     x, y, yy, xx, A.\n        DEFB    $E0             ;;get-mem-0     x, y, yy, xx, A, a.\n        DEFB    $03             ;;subtract      x, y, yy, xx, A-a.\n        DEFB    $A2             ;;stk-half      x, y, yy, xx, A-a, 1/2.\n        DEFB    $04             ;;multiply      x, y, yy, xx, (A-a)/2. (=angle)\n        DEFB    $31             ;;duplicate     x, y, yy, xx, angle, angle.\n        DEFB    $1F             ;;sin           x, y, yy, xx, angle, sin(angle)\n        DEFB    $C5             ;;st-mem-5      x, y, yy, xx, angle, sin(angle)\n        DEFB    $02             ;;delete        x, y, yy, xx, angle\n\n        DEFB    $20             ;;cos           x, y, yy, xx, cos(angle).\n\n;   Note. mem-0, mem-1 and mem-2 can be used again now...\n\n        DEFB    $C0             ;;st-mem-0      x, y, yy, xx, cos(angle).\n        DEFB    $02             ;;delete        x, y, yy, xx.\n\n        DEFB    $C2             ;;st-mem-2      x, y, yy, xx.\n        DEFB    $02             ;;delete        x, y, yy.\n\n        DEFB    $C1             ;;st-mem-1      x, y, yy.\n        DEFB    $E5             ;;get-mem-5     x, y, yy, sin(angle)\n        DEFB    $04             ;;multiply      x, y, yy*sin(angle).\n        DEFB    $E0             ;;get-mem-0     x, y, yy*sin(angle), cos(angle)\n        DEFB    $E2             ;;get-mem-2     x, y, yy*sin(angle), cos(angle), xx.\n        DEFB    $04             ;;multiply      x, y, yy*sin(angle), xx*cos(angle).\n        DEFB    $0F             ;;addition      x, y, xRotated.\n        DEFB    $E1             ;;get-mem-1     x, y, xRotated, yy.\n        DEFB    $01             ;;exchange      x, y, yy, xRotated.\n        DEFB    $C1             ;;st-mem-1      x, y, yy, xRotated.\n        DEFB    $02             ;;delete        x, y, yy.\n\n        DEFB    $E0             ;;get-mem-0     x, y, yy, cos(angle).\n        DEFB    $04             ;;multiply      x, y, yy*cos(angle).\n        DEFB    $E2             ;;get-mem-2     x, y, yy*cos(angle), xx.\n        DEFB    $E5             ;;get-mem-5     x, y, yy*cos(angle), xx, sin(angle).\n        DEFB    $04             ;;multiply      x, y, yy*cos(angle), xx*sin(angle).\n        DEFB    $03             ;;subtract      x, y, yRotated.\n        DEFB    $C2             ;;st-mem-2      x, y, yRotated.\n\n;   Now the initial x and y coordinates are made positive and summed to see\n;   if they measure up to anything significant.\n\n        DEFB    $2A             ;;abs           x, y, yRotated'.\n        DEFB    $E1             ;;get-mem-1     x, y, yRotated', xRotated.\n        DEFB    $2A             ;;abs           x, y, yRotated', xRotated'.\n        DEFB    $0F             ;;addition      x, y, yRotated+xRotated.\n        DEFB    $02             ;;delete        x, y.\n\n        DEFB    $38             ;;end-calc      x, y.\n\n;   Although the test value has been deleted it is still above the calculator\n;   stack in memory and conveniently DE which points to the first free byte\n;   addresses the exponent of the test value.\n\n        LD      A,(DE)          ; Fetch exponent of the length indicator.\n        CP      $81             ; Compare to that for 1\n\n        POP     BC              ; Balance the machine stack\n\n        JP      C,L2477         ; forward, if the coordinates of first line\n                                ; don't add up to more than 1, to LINE-DRAW\n\n;   Continue when the arc will have a discernable shape.\n\n        PUSH    BC              ; Restore line counter to the machine stack.\n\n;   The parameters of the DRAW command were relative and they are now converted\n;   to absolute coordinates by adding to the coordinates of the last point\n;   plotted. The first two values on the stack are the terminal tx and ty\n;   coordinates.  The x-coordinate is converted first but first the last point\n;   plotted is saved as it will initialize the moving ax, value.\n\n        RST     28H             ;; FP-CALC      x, y.\n        DEFB    $01             ;;exchange      y, x.\n        DEFB    $38             ;;end-calc      y, x.\n\n        LD      A,($5C7D)       ; Fetch System Variable COORDS-x\n        CALL    L2D28           ; routine STACK-A\n\n        RST     28H             ;; FP-CALC      y, x, last-x.\n\n;   Store the last point plotted to initialize the moving ax value.\n\n        DEFB    $C0             ;;st-mem-0      y, x, last-x.\n        DEFB    $0F             ;;addition      y, absolute x.\n        DEFB    $01             ;;exchange      tx, y.\n        DEFB    $38             ;;end-calc      tx, y.\n\n        LD      A,($5C7E)       ; Fetch System Variable COORDS-y\n        CALL    L2D28           ; routine STACK-A\n\n        RST     28H             ;; FP-CALC      tx, y, last-y.\n\n;   Store the last point plotted to initialize the moving ay value.\n\n        DEFB    $C5             ;;st-mem-5      tx, y, last-y.\n        DEFB    $0F             ;;addition      tx, ty.\n\n;   Fetch the moving ax and ay to the calculator stack.\n\n        DEFB    $E0             ;;get-mem-0     tx, ty, ax.\n        DEFB    $E5             ;;get-mem-5     tx, ty, ax, ay.\n        DEFB    $38             ;;end-calc      tx, ty, ax, ay.\n\n        POP     BC              ; Restore the straight line count.\n\n; -----------------------------------\n; THE 'CIRCLE/DRAW CONVERGENCE POINT'\n; -----------------------------------\n;   The CIRCLE and ARC-DRAW commands converge here.\n;\n;   Note. for both the CIRCLE and ARC commands the minimum initial line count\n;   is 4 (as set up by the CD_PARAMS routine) and so the zero flag will never\n;   be set and the loop is always entered.  The first test is superfluous and\n;   the jump will always be made to ARC-START.\n\n;; DRW-STEPS\nL2420:  DEC     B               ; decrement the arc count (4,8,12,16...).\n\n        JR      Z,L245F         ; forward, if zero (not possible), to ARC-END\n\n        JR      L2439           ; forward to ARC-START\n\n; --------------\n; THE 'ARC LOOP'\n; --------------\n;\n;   The arc drawing loop will draw up to 31 straight lines for a circle and up\n;   251 straight lines for an arc between two points. In both cases the final\n;   closing straight line is drawn at ARC_END, but it otherwise loops back to\n;   here to calculate the next coordinate using the ROTATION FORMULA where (a)\n;   is the previously calculated, constant CENTRAL ANGLE of the arcs.\n;\n;       Xrotated = x * cos(a) - y * sin(a)\n;       Yrotated = x * sin(a) + y * cos(a)\n;\n;   The values cos(a) and sin(a) are pre-calculated and held in mem-3 and mem-4\n;   for the duration of the routine.\n;   Memory location mem-1 holds the last relative x value (rx) and mem-2 holds\n;   the last relative y value (ry) used by DRAW.\n;\n;   Note. that this is a very clever twist on what is after all a very clever,\n;   well-used formula.  Normally the rotation formula is used with the x and y\n;   coordinates from the centre of the circle (or arc) and a supplied angle to\n;   produce two new x and y coordinates in an anticlockwise direction on the\n;   circumference of the circle.\n;   What is being used here, instead, is the relative X and Y parameters from\n;   the last point plotted that are required to get to the current point and\n;   the formula returns the next relative coordinates to use.\n\n;; ARC-LOOP\nL2425:  RST     28H             ;; FP-CALC\n        DEFB    $E1             ;;get-mem-1     rx.\n        DEFB    $31             ;;duplicate     rx, rx.\n        DEFB    $E3             ;;get-mem-3     cos(a)\n        DEFB    $04             ;;multiply      rx, rx*cos(a).\n        DEFB    $E2             ;;get-mem-2     rx, rx*cos(a), ry.\n        DEFB    $E4             ;;get-mem-4     rx, rx*cos(a), ry, sin(a).\n        DEFB    $04             ;;multiply      rx, rx*cos(a), ry*sin(a).\n        DEFB    $03             ;;subtract      rx, rx*cos(a) - ry*sin(a)\n        DEFB    $C1             ;;st-mem-1      rx, new relative x rotated.\n        DEFB    $02             ;;delete        rx.\n\n        DEFB    $E4             ;;get-mem-4     rx, sin(a).\n        DEFB    $04             ;;multiply      rx*sin(a)\n        DEFB    $E2             ;;get-mem-2     rx*sin(a), ry.\n        DEFB    $E3             ;;get-mem-3     rx*sin(a), ry, cos(a).\n        DEFB    $04             ;;multiply      rx*sin(a), ry*cos(a).\n        DEFB    $0F             ;;addition      rx*sin(a) + ry*cos(a).\n        DEFB    $C2             ;;st-mem-2      new relative y rotated.\n        DEFB    $02             ;;delete        .\n        DEFB    $38             ;;end-calc      .\n\n;   Note. the calculator stack actually holds   tx, ty, ax, ay\n;   and the last absolute values of x and y\n;   are now brought into play.\n;\n;   Magically, the two new rotated coordinates rx and ry are all that we would\n;   require to draw a circle or arc - on paper!\n;   The Spectrum DRAW routine draws to the rounded x and y coordinate and so\n;   repetitions of values like 3.49 would mean that the fractional parts\n;   would be lost until eventually the draw coordinates might differ from the\n;   floating point values used above by several pixels.\n;   For this reason the accurate offsets calculated above are added to the\n;   accurate, absolute coordinates maintained in ax and ay and these new\n;   coordinates have the integer coordinates of the last plot position\n;   ( from System Variable COORDS ) subtracted from them to give the relative\n;   coordinates required by the DRAW routine.\n\n;   The mid entry point.\n\n;; ARC-START\nL2439:  PUSH    BC              ; Preserve the arc counter on the machine stack.\n\n;   Store the absolute ay in temporary variable mem-0 for the moment.\n\n        RST     28H             ;; FP-CALC      ax, ay.\n        DEFB    $C0             ;;st-mem-0      ax, ay.\n        DEFB    $02             ;;delete        ax.\n\n;   Now add the fractional relative x coordinate to the fractional absolute\n;   x coordinate to obtain a new fractional x-coordinate.\n\n        DEFB    $E1             ;;get-mem-1     ax, xr.\n        DEFB    $0F             ;;addition      ax+xr (= new ax).\n        DEFB    $31             ;;duplicate     ax, ax.\n        DEFB    $38             ;;end-calc      ax, ax.\n\n        LD      A,($5C7D)       ; COORDS-x      last x    (integer ix 0-255)\n        CALL    L2D28           ; routine STACK-A\n\n        RST     28H             ;; FP-CALC      ax, ax, ix.\n        DEFB    $03             ;;subtract      ax, ax-ix  = relative DRAW Dx.\n\n;   Having calculated the x value for DRAW do the same for the y value.\n\n        DEFB    $E0             ;;get-mem-0     ax, Dx, ay.\n        DEFB    $E2             ;;get-mem-2     ax, Dx, ay, ry.\n        DEFB    $0F             ;;addition      ax, Dx, ay+ry (= new ay).\n        DEFB    $C0             ;;st-mem-0      ax, Dx, ay.\n        DEFB    $01             ;;exchange      ax, ay, Dx,\n        DEFB    $E0             ;;get-mem-0     ax, ay, Dx, ay.\n        DEFB    $38             ;;end-calc      ax, ay, Dx, ay.\n\n        LD      A,($5C7E)       ; COORDS-y      last y (integer iy 0-175)\n        CALL    L2D28           ; routine STACK-A\n\n        RST     28H             ;; FP-CALC      ax, ay, Dx, ay, iy.\n        DEFB    $03             ;;subtract      ax, ay, Dx, ay-iy ( = Dy).\n        DEFB    $38             ;;end-calc      ax, ay, Dx, Dy.\n\n        CALL    L24B7           ; Routine DRAW-LINE draws (Dx,Dy) relative to\n                                ; the last pixel plotted leaving absolute x\n                                ; and y on the calculator stack.\n                                ;               ax, ay.\n\n        POP     BC              ; Restore the arc counter from the machine stack.\n\n        DJNZ    L2425           ; Decrement and loop while > 0 to ARC-LOOP\n\n; -------------\n; THE 'ARC END'\n; -------------\n\n;   To recap the full calculator stack is       tx, ty, ax, ay.\n\n;   Just as one would do if drawing the curve on paper, the final line would\n;   be drawn by joining the last point plotted to the initial start point\n;   in the case of a CIRCLE or to the calculated end point in the case of\n;   an ARC.\n;   The moving absolute values of x and y are no longer required and they\n;   can be deleted to expose the closing coordinates.\n\n;; ARC-END\nL245F:  RST     28H             ;; FP-CALC      tx, ty, ax, ay.\n        DEFB    $02             ;;delete        tx, ty, ax.\n        DEFB    $02             ;;delete        tx, ty.\n        DEFB    $01             ;;exchange      ty, tx.\n        DEFB    $38             ;;end-calc      ty, tx.\n\n;   First calculate the relative x coordinate to the end-point.\n\n        LD      A,($5C7D)       ; COORDS-x\n        CALL    L2D28           ; routine STACK-A\n\n        RST     28H             ;; FP-CALC      ty, tx, coords_x.\n        DEFB    $03             ;;subtract      ty, rx.\n\n;   Next calculate the relative y coordinate to the end-point.\n\n        DEFB    $01             ;;exchange      rx, ty.\n        DEFB    $38             ;;end-calc      rx, ty.\n\n        LD      A,($5C7E)       ; COORDS-y\n        CALL    L2D28           ; routine STACK-A\n\n        RST     28H             ;; FP-CALC      rx, ty, coords_y\n        DEFB    $03             ;;subtract      rx, ry.\n        DEFB    $38             ;;end-calc      rx, ry.\n\n;   Finally draw the last straight line.\n\n;; LINE-DRAW\nL2477:  CALL    L24B7           ; routine DRAW-LINE draws to the relative\n                                ; coordinates (rx, ry).\n\n        JP      L0D4D           ; jump back and exit via TEMPS          >>>\n\n\n; --------------------------------------------\n; THE 'INITIAL CIRCLE/DRAW PARAMETERS' ROUTINE\n; --------------------------------------------\n;   Begin by calculating the number of chords which will be returned in B.\n;   A rule of thumb is employed that uses a value z which for a circle is the\n;   radius and for an arc is the diameter with, as it happens, a pinch more if\n;   the arc is on a slope.\n;\n;   NUMBER OF STRAIGHT LINES = ANGLE OF ROTATION * SQUARE ROOT ( Z ) / 2\n\n;; CD-PRMS1\nL247D:  RST     28H             ;; FP-CALC      z.\n        DEFB    $31             ;;duplicate     z, z.\n        DEFB    $28             ;;sqr           z, sqr(z).\n        DEFB    $34             ;;stk-data      z, sqr(z), 2.\n        DEFB    $32             ;;Exponent: $82, Bytes: 1\n        DEFB    $00             ;;(+00,+00,+00)\n        DEFB    $01             ;;exchange      z, 2, sqr(z).\n        DEFB    $05             ;;division      z, 2/sqr(z).\n        DEFB    $E5             ;;get-mem-5     z, 2/sqr(z), ANGLE.\n        DEFB    $01             ;;exchange      z, ANGLE, 2/sqr (z)\n        DEFB    $05             ;;division      z, ANGLE*sqr(z)/2 (= No. of lines)\n        DEFB    $2A             ;;abs           (for arc only)\n        DEFB    $38             ;;end-calc      z, number of lines.\n\n;    As an example for a circle of radius 87 the number of lines will be 29.\n\n        CALL    L2DD5           ; routine FP-TO-A\n\n;    The value is compressed into A register, no carry with valid circle.\n\n        JR      C,L2495         ; forward, if over 256, to USE-252\n\n;    now make a multiple of 4 e.g. 29 becomes 28\n\n        AND     $FC             ; AND 252\n\n;    Adding 4 could set carry for arc, for the circle example, 28 becomes 32.\n\n        ADD     A,$04           ; adding 4 could set carry if result is 256.\n\n        JR      NC,L2497        ; forward if less than 256 to DRAW-SAVE\n\n;    For an arc, a limit of 252 is imposed.\n\n;; USE-252\nL2495:  LD      A,$FC           ; Use a value of 252 (for arc).\n\n\n;   For both arcs and circles, constants derived from the central angle are\n;   stored in the 'mem' locations.  Some are not relevant for the circle.\n\n;; DRAW-SAVE\nL2497:  PUSH    AF              ; Save the line count (A) on the machine stack.\n\n        CALL    L2D28           ; Routine STACK-A stacks the modified count(A).\n\n        RST     28H             ;; FP-CALC      z, A.\n        DEFB    $E5             ;;get-mem-5     z, A, ANGLE.\n        DEFB    $01             ;;exchange      z, ANGLE, A.\n        DEFB    $05             ;;division      z, ANGLE/A. (Angle/count = a)\n        DEFB    $31             ;;duplicate     z, a, a.\n\n;  Note. that cos (a) could be formed here directly using 'cos' and stored in\n;  mem-3 but that would spoil a good story and be slightly slower, as also\n;  would using square roots to form cos (a) from sin (a).\n\n        DEFB    $1F             ;;sin           z, a, sin(a)\n        DEFB    $C4             ;;st-mem-4      z, a, sin(a)\n        DEFB    $02             ;;delete        z, a.\n        DEFB    $31             ;;duplicate     z, a, a.\n        DEFB    $A2             ;;stk-half      z, a, a, 1/2.\n        DEFB    $04             ;;multiply      z, a, a/2.\n        DEFB    $1F             ;;sin           z, a, sin(a/2).\n\n;   Note. after second sin, mem-0 and mem-1 become free.\n\n        DEFB    $C1             ;;st-mem-1      z, a, sin(a/2).\n        DEFB    $01             ;;exchange      z, sin(a/2), a.\n        DEFB    $C0             ;;st-mem-0      z, sin(a/2), a.  (for arc only)\n\n;   Now form cos(a) from sin(a/2) using the 'DOUBLE ANGLE FORMULA'.\n\n        DEFB    $02             ;;delete        z, sin(a/2).\n        DEFB    $31             ;;duplicate     z, sin(a/2), sin(a/2).\n        DEFB    $04             ;;multiply      z, sin(a/2)*sin(a/2).\n        DEFB    $31             ;;duplicate     z, sin(a/2)*sin(a/2),\n                                ;;                           sin(a/2)*sin(a/2).\n        DEFB    $0F             ;;addition      z, 2*sin(a/2)*sin(a/2).\n        DEFB    $A1             ;;stk-one       z, 2*sin(a/2)*sin(a/2), 1.\n        DEFB    $03             ;;subtract      z, 2*sin(a/2)*sin(a/2)-1.\n\n        DEFB    $1B             ;;negate        z, 1-2*sin(a/2)*sin(a/2).\n\n        DEFB    $C3             ;;st-mem-3      z, cos(a).\n        DEFB    $02             ;;delete        z.\n        DEFB    $38             ;;end-calc      z.\n\n;   The radius/diameter is left on the calculator stack.\n\n        POP     BC              ; Restore the line count to the B register.\n\n        RET                     ; Return.\n\n; --------------------------\n; THE 'DOUBLE ANGLE FORMULA'\n; --------------------------\n;   This formula forms cos(a) from sin(a/2) using simple arithmetic.\n;\n;   THE GEOMETRIC PROOF OF FORMULA   cos (a) = 1 - 2 * sin(a/2) * sin(a/2)\n;\n;\n;                                            A\n;\n;                                         . /|\\\n;                                     .    / | \\\n;                                  .      /  |  \\\n;                               .        /   |a/2\\\n;                            .          /    |    \\\n;                         .          1 /     |     \\\n;                      .              /      |      \\\n;                   .                /       |       \\\n;                .                  /        |        \\\n;             .  a/2             D / a      E|-+       \\\n;          B ---------------------/----------+-+--------\\ C\n;            <-         1       -><-       1           ->\n;\n;   cos a = 1 - 2 * sin(a/2) * sin(a/2)\n;\n;   The figure shows a right triangle that inscribes a circle of radius 1 with\n;   centre, or origin, D.  Line BC is the diameter of length 2 and A is a point\n;   on the circle. The periphery angle BAC is therefore a right angle by the\n;   Rule of Thales.\n;   Line AC is a chord touching two points on the circle and the angle at the\n;   centre is (a).\n;   Since the vertex of the largest triangle B touches the circle, the\n;   inscribed angle (a/2) is half the central angle (a).\n;   The cosine of (a) is the length DE as the hypotenuse is of length 1.\n;   This can also be expressed as 1-length CE.  Examining the triangle at the\n;   right, the top angle is also (a/2) as angle BAE and EBA add to give a right\n;   angle as do BAE and EAC.\n;   So cos (a) = 1 - AC * sin(a/2)\n;   Looking at the largest triangle, side AC can be expressed as\n;   AC = 2 * sin(a/2)   and so combining these we get\n;   cos (a) = 1 - 2 * sin(a/2) * sin(a/2).\n;\n;   \"I will be sufficiently rewarded if when telling it to others, you will\n;    not claim the discovery as your own, but will say it is mine.\"\n;   - Thales, 640 - 546 B.C.\n;\n; --------------------------\n; THE 'LINE DRAWING' ROUTINE\n; --------------------------\n;\n;\n\n;; DRAW-LINE\nL24B7:  CALL    L2307           ; routine STK-TO-BC\n        LD      A,C             ;\n        CP      B               ;\n        JR      NC,L24C4        ; to DL-X-GE-Y\n\n        LD      L,C             ;\n        PUSH    DE              ;\n        XOR     A               ;\n        LD      E,A             ;\n        JR      L24CB           ; to DL-LARGER\n\n; ---\n\n;; DL-X-GE-Y\nL24C4:  OR      C               ;\n        RET     Z               ;\n\n        LD      L,B             ;\n        LD      B,C             ;\n        PUSH    DE              ;\n        LD      D,$00           ;\n\n;; DL-LARGER\nL24CB:  LD      H,B             ;\n        LD      A,B             ;\n        RRA                     ;\n\n;; D-L-LOOP\nL24CE:  ADD     A,L             ;\n        JR      C,L24D4         ; to D-L-DIAG\n\n        CP      H               ;\n        JR      C,L24DB         ; to D-L-HR-VT\n\n;; D-L-DIAG\nL24D4:  SUB     H               ;\n        LD      C,A             ;\n        EXX                     ;\n        POP     BC              ;\n        PUSH    BC              ;\n        JR      L24DF           ; to D-L-STEP\n\n; ---\n\n;; D-L-HR-VT\nL24DB:  LD      C,A             ;\n        PUSH    DE              ;\n        EXX                     ;\n        POP     BC              ;\n\n;; D-L-STEP\nL24DF:  LD      HL,($5C7D)      ; COORDS\n        LD      A,B             ;\n        ADD     A,H             ;\n        LD      B,A             ;\n        LD      A,C             ;\n        INC     A               ;\n        ADD     A,L             ;\n        JR      C,L24F7         ; to D-L-RANGE\n\n        JR      Z,L24F9         ; to REPORT-Bc\n\n;; D-L-PLOT\nL24EC:  DEC     A               ;\n        LD      C,A             ;\n        CALL    L22E5           ; routine PLOT-SUB\n        EXX                     ;\n        LD      A,C             ;\n        DJNZ    L24CE           ; to D-L-LOOP\n\n        POP     DE              ;\n        RET                     ;\n\n; ---\n\n;; D-L-RANGE\nL24F7:  JR      Z,L24EC         ; to D-L-PLOT\n\n\n;; REPORT-Bc\nL24F9:  RST     08H             ; ERROR-1\n        DEFB    $0A             ; Error Report: Integer out of range\n\n\n\n;***********************************\n;** Part 8. EXPRESSION EVALUATION **\n;***********************************\n;\n; It is a this stage of the ROM that the Spectrum ceases altogether to be\n; just a colourful novelty. One remarkable feature is that in all previous\n; commands when the Spectrum is expecting a number or a string then an\n; expression of the same type can be substituted ad infinitum.\n; This is the routine that evaluates that expression.\n; This is what causes 2 + 2 to give the answer 4.\n; That is quite easy to understand. However you don't have to make it much\n; more complex to start a remarkable juggling act.\n; e.g. PRINT 2 * (VAL \"2+2\" + TAN 3)\n; In fact, provided there is enough free RAM, the Spectrum can evaluate\n; an expression of unlimited complexity.\n; Apart from a couple of minor glitches, which you can now correct, the\n; system is remarkably robust.\n\n\n; ---------------------------------\n; Scan expression or sub-expression\n; ---------------------------------\n;\n;\n\n;; SCANNING\nL24FB:  RST     18H             ; GET-CHAR\n        LD      B,$00           ; priority marker zero is pushed on stack\n                                ; to signify end of expression when it is\n                                ; popped off again.\n        PUSH    BC              ; put in on stack.\n                                ; and proceed to consider the first character\n                                ; of the expression.\n\n;; S-LOOP-1\nL24FF:  LD      C,A             ; store the character while a look up is done.\n        LD      HL,L2596        ; Address: scan-func\n        CALL    L16DC           ; routine INDEXER is called to see if it is\n                                ; part of a limited range '+', '(', 'ATTR' etc.\n\n        LD      A,C             ; fetch the character back\n        JP      NC,L2684        ; jump forward to S-ALPHNUM if not in primary\n                                ; operators and functions to consider in the\n                                ; first instance a digit or a variable and\n                                ; then anything else.                >>>\n\n        LD      B,$00           ; but here if it was found in table so\n        LD      C,(HL)          ; fetch offset from table and make B zero.\n        ADD     HL,BC           ; add the offset to position found\n        JP      (HL)            ; and jump to the routine e.g. S-BIN\n                                ; making an indirect exit from there.\n\n; -------------------------------------------------------------------------\n; The four service subroutines for routines in the scanning function table\n; -------------------------------------------------------------------------\n\n; PRINT \"\"\"Hooray!\"\" he cried.\"\n\n;; S-QUOTE-S\nL250F:  CALL    L0074           ; routine CH-ADD+1 points to next character\n                                ; and fetches that character.\n        INC     BC              ; increase length counter.\n        CP      $0D             ; is it carriage return ?\n                                ; inside a quote.\n        JP      Z,L1C8A         ; jump back to REPORT-C if so.\n                                ; 'Nonsense in BASIC'.\n\n        CP      $22             ; is it a quote '\"' ?\n        JR      NZ,L250F        ; back to S-QUOTE-S if not for more.\n\n        CALL    L0074           ; routine CH-ADD+1\n        CP      $22             ; compare with possible adjacent quote\n        RET                     ; return. with zero set if two together.\n\n; ---\n\n; This subroutine is used to get two coordinate expressions for the three\n; functions SCREEN$, ATTR and POINT that have two fixed parameters and\n; therefore require surrounding braces.\n\n;; S-2-COORD\nL2522:  RST     20H             ; NEXT-CHAR\n        CP      $28             ; is it the opening '(' ?\n        JR      NZ,L252D        ; forward to S-RPORT-C if not\n                                ; 'Nonsense in BASIC'.\n\n        CALL    L1C79           ; routine NEXT-2NUM gets two comma-separated\n                                ; numeric expressions. Note. this could cause\n                                ; many more recursive calls to SCANNING but\n                                ; the parent function will be evaluated fully\n                                ; before rejoining the main juggling act.\n\n        RST     18H             ; GET-CHAR\n        CP      $29             ; is it the closing ')' ?\n\n;; S-RPORT-C\nL252D:  JP      NZ,L1C8A        ; jump back to REPORT-C if not.\n                                ; 'Nonsense in BASIC'.\n\n; ------------\n; Check syntax\n; ------------\n; This routine is called on a number of occasions to check if syntax is being\n; checked or if the program is being run. To test the flag inline would use\n; four bytes of code, but a call instruction only uses 3 bytes of code.\n\n;; SYNTAX-Z\nL2530:  BIT     7,(IY+$01)      ; test FLAGS  - checking syntax only ?\n        RET                     ; return.\n\n; ----------------\n; Scanning SCREEN$\n; ----------------\n; This function returns the code of a bit-mapped character at screen\n; position at line C, column B. It is unable to detect the mosaic characters\n; which are not bit-mapped but detects the ASCII 32 - 127 range.\n; The bit-mapped UDGs are ignored which is curious as it requires only a\n; few extra bytes of code. As usual, anything to do with CHARS is weird.\n; If no match is found a null string is returned.\n; No actual check on ranges is performed - that's up to the BASIC programmer.\n; No real harm can come from SCREEN$(255,255) although the BASIC manual\n; says that invalid values will be trapped.\n; Interestingly, in the Pitman pocket guide, 1984, Vickers says that the\n; range checking will be performed.\n\n;; S-SCRN$-S\nL2535:  CALL    L2307           ; routine STK-TO-BC.\n        LD      HL,($5C36)      ; fetch address of CHARS.\n        LD      DE,$0100        ; fetch offset to chr$ 32\n        ADD     HL,DE           ; and find start of bitmaps.\n                                ; Note. not inc h. ??\n        LD      A,C             ; transfer line to A.\n        RRCA                    ; multiply\n        RRCA                    ; by\n        RRCA                    ; thirty-two.\n        AND     $E0             ; and with 11100000\n        XOR     B               ; combine with column $00 - $1F\n        LD      E,A             ; to give the low byte of top line\n        LD      A,C             ; column to A range 00000000 to 00011111\n        AND     $18             ; and with 00011000\n        XOR     $40             ; xor with 01000000 (high byte screen start)\n        LD      D,A             ; register DE now holds start address of cell.\n        LD      B,$60           ; there are 96 characters in ASCII set.\n\n;; S-SCRN-LP\nL254F:  PUSH    BC              ; save count\n        PUSH    DE              ; save screen start address\n        PUSH    HL              ; save bitmap start\n        LD      A,(DE)          ; first byte of screen to A\n        XOR     (HL)            ; xor with corresponding character byte\n        JR      Z,L255A         ; forward to S-SC-MTCH if they match\n                                ; if inverse result would be $FF\n                                ; if any other then mismatch\n\n        INC     A               ; set to $00 if inverse\n        JR      NZ,L2573        ; forward to S-SCR-NXT if a mismatch\n\n        DEC     A               ; restore $FF\n\n; a match has been found so seven more to test.\n\n;; S-SC-MTCH\nL255A:  LD      C,A             ; load C with inverse mask $00 or $FF\n        LD      B,$07           ; count seven more bytes\n\n;; S-SC-ROWS\nL255D:  INC     D               ; increment screen address.\n        INC     HL              ; increment bitmap address.\n        LD      A,(DE)          ; byte to A\n        XOR     (HL)            ; will give $00 or $FF (inverse)\n        XOR     C               ; xor with inverse mask\n        JR      NZ,L2573        ; forward to S-SCR-NXT if no match.\n\n        DJNZ    L255D           ; back to S-SC-ROWS until all eight matched.\n\n; continue if a match of all eight bytes was found\n\n        POP     BC              ; discard the\n        POP     BC              ; saved\n        POP     BC              ; pointers\n        LD      A,$80           ; the endpoint of character set\n        SUB     B               ; subtract the counter\n                                ; to give the code 32-127\n        LD      BC,$0001        ; make one space in workspace.\n\n        RST     30H             ; BC-SPACES creates the space sliding\n                                ; the calculator stack upwards.\n        LD      (DE),A          ; start is addressed by DE, so insert code\n        JR      L257D           ; forward to S-SCR-STO\n\n; ---\n\n; the jump was here if no match and more bitmaps to test.\n\n;; S-SCR-NXT\nL2573:  POP     HL              ; restore the last bitmap start\n        LD      DE,$0008        ; and prepare to add 8.\n        ADD     HL,DE           ; now addresses next character bitmap.\n        POP     DE              ; restore screen address\n        POP     BC              ; and character counter in B\n        DJNZ    L254F           ; back to S-SCRN-LP if more characters.\n\n        LD      C,B             ; B is now zero, so BC now zero.\n\n;; S-SCR-STO\nL257D:  JP      L2AB2           ; to STK-STO-$ to store the string in\n                                ; workspace or a string with zero length.\n                                ; (value of DE doesn't matter in last case)\n\n; Note. this exit seems correct but the general-purpose routine S-STRING\n; that calls this one will also stack any of its string results so this\n; leads to a double storing of the result in this case.\n; The instruction at L257D should just be a RET.\n; credit Stephen Kelly and others, 1982.\n\n; -------------\n; Scanning ATTR\n; -------------\n; This function subroutine returns the attributes of a screen location -\n; a numeric result.\n; Again it's up to the BASIC programmer to supply valid values of line/column.\n\n;; S-ATTR-S\nL2580:  CALL    L2307           ; routine STK-TO-BC fetches line to C,\n                                ; and column to B.\n        LD      A,C             ; line to A $00 - $17   (max 00010111)\n        RRCA                    ; rotate\n        RRCA                    ; bits\n        RRCA                    ; left.\n        LD      C,A             ; store in C as an intermediate value.\n\n        AND     $E0             ; pick up bits 11100000 ( was 00011100 )\n        XOR     B               ; combine with column $00 - $1F\n        LD      L,A             ; low byte now correct.\n\n        LD      A,C             ; bring back intermediate result from C\n        AND     $03             ; mask to give correct third of\n                                ; screen $00 - $02\n        XOR     $58             ; combine with base address.\n        LD      H,A             ; high byte correct.\n        LD      A,(HL)          ; pick up the colour attribute.\n        JP      L2D28           ; forward to STACK-A to store result\n                                ; and make an indirect exit.\n\n; -----------------------\n; Scanning function table\n; -----------------------\n; This table is used by INDEXER routine to find the offsets to\n; four operators and eight functions. e.g. $A8 is the token 'FN'.\n; This table is used in the first instance for the first character of an\n; expression or by a recursive call to SCANNING for the first character of\n; any sub-expression. It eliminates functions that have no argument or\n; functions that can have more than one argument and therefore require\n; braces. By eliminating and dealing with these now it can later take a\n; simplistic approach to all other functions and assume that they have\n; one argument.\n; Similarly by eliminating BIN and '.' now it is later able to assume that\n; all numbers begin with a digit and that the presence of a number or\n; variable can be detected by a call to ALPHANUM.\n; By default all expressions are positive and the spurious '+' is eliminated\n; now as in print +2. This should not be confused with the operator '+'.\n; Note. this does allow a degree of nonsense to be accepted as in\n; PRINT +\"3 is the greatest.\".\n; An acquired programming skill is the ability to include brackets where\n; they are not necessary.\n; A bracket at the start of a sub-expression may be spurious or necessary\n; to denote that the contained expression is to be evaluated as an entity.\n; In either case this is dealt with by recursive calls to SCANNING.\n; An expression that begins with a quote requires special treatment.\n\n;; scan-func\nL2596:  DEFB    $22, L25B3-$-1  ; $1C offset to S-QUOTE\n        DEFB    '(', L25E8-$-1  ; $4F offset to S-BRACKET\n        DEFB    '.', L268D-$-1  ; $F2 offset to S-DECIMAL\n        DEFB    '+', L25AF-$-1  ; $12 offset to S-U-PLUS\n\n        DEFB    $A8, L25F5-$-1  ; $56 offset to S-FN\n        DEFB    $A5, L25F8-$-1  ; $57 offset to S-RND\n        DEFB    $A7, L2627-$-1  ; $84 offset to S-PI\n        DEFB    $A6, L2634-$-1  ; $8F offset to S-INKEY$\n        DEFB    $C4, L268D-$-1  ; $E6 offset to S-BIN\n        DEFB    $AA, L2668-$-1  ; $BF offset to S-SCREEN$\n        DEFB    $AB, L2672-$-1  ; $C7 offset to S-ATTR\n        DEFB    $A9, L267B-$-1  ; $CE offset to S-POINT\n\n        DEFB    $00             ; zero end marker\n\n; --------------------------\n; Scanning function routines\n; --------------------------\n; These are the 11 subroutines accessed by the above table.\n; S-BIN and S-DECIMAL are the same\n; The 1-byte offset limits their location to within 255 bytes of their\n; entry in the table.\n\n; ->\n;; S-U-PLUS\nL25AF:  RST     20H             ; NEXT-CHAR just ignore\n        JP      L24FF           ; to S-LOOP-1\n\n; ---\n\n; ->\n;; S-QUOTE\nL25B3:  RST     18H             ; GET-CHAR\n        INC     HL              ; address next character (first in quotes)\n        PUSH    HL              ; save start of quoted text.\n        LD      BC,$0000        ; initialize length of string to zero.\n        CALL    L250F           ; routine S-QUOTE-S\n        JR      NZ,L25D9        ; forward to S-Q-PRMS if\n\n;; S-Q-AGAIN\nL25BE:  CALL    L250F           ; routine S-QUOTE-S copies string until a\n                                ; quote is encountered\n        JR      Z,L25BE         ; back to S-Q-AGAIN if two quotes WERE\n                                ; together.\n\n; but if just an isolated quote then that terminates the string.\n\n        CALL    L2530           ; routine SYNTAX-Z\n        JR      Z,L25D9         ; forward to S-Q-PRMS if checking syntax.\n\n\n        RST     30H             ; BC-SPACES creates the space for true\n                                ; copy of string in workspace.\n        POP     HL              ; re-fetch start of quoted text.\n        PUSH    DE              ; save start in workspace.\n\n;; S-Q-COPY\nL25CB:  LD      A,(HL)          ; fetch a character from source.\n        INC     HL              ; advance source address.\n        LD      (DE),A          ; place in destination.\n        INC     DE              ; advance destination address.\n        CP      $22             ; was it a '\"' just copied ?\n        JR      NZ,L25CB        ; back to S-Q-COPY to copy more if not\n\n        LD      A,(HL)          ; fetch adjacent character from source.\n        INC     HL              ; advance source address.\n        CP      $22             ; is this '\"' ? - i.e. two quotes together ?\n        JR      Z,L25CB         ; to S-Q-COPY if so including just one of the\n                                ; pair of quotes.\n\n; proceed when terminating quote encountered.\n\n;; S-Q-PRMS\nL25D9:  DEC     BC              ; decrease count by 1.\n        POP     DE              ; restore start of string in workspace.\n\n;; S-STRING\nL25DB:  LD      HL,$5C3B        ; Address FLAGS system variable.\n        RES     6,(HL)          ; signal string result.\n        BIT     7,(HL)          ; is syntax being checked.\n        CALL    NZ,L2AB2        ; routine STK-STO-$ is called in runtime.\n        JP      L2712           ; jump forward to S-CONT-2          ===>\n\n; ---\n\n; ->\n;; S-BRACKET\nL25E8:  RST     20H             ; NEXT-CHAR\n        CALL    L24FB           ; routine SCANNING is called recursively.\n        CP      $29             ; is it the closing ')' ?\n        JP      NZ,L1C8A        ; jump back to REPORT-C if not\n                                ; 'Nonsense in BASIC'\n\n        RST     20H             ; NEXT-CHAR\n        JP      L2712           ; jump forward to S-CONT-2          ===>\n\n; ---\n\n; ->\n;; S-FN\nL25F5:  JP      L27BD           ; jump forward to S-FN-SBRN.\n\n; --------------------------------------------------------------------\n;\n;   RANDOM THEORY from the ZX81 manual by Steven Vickers\n;\n;   (same algorithm as the ZX Spectrum).\n;\n;   Chapter 5. Exercise 6. (For mathematicians only.)\n;\n;   Let p be a [large] prime, & let a be a primitive root modulo p.\n;   Then if b_i is the residue of a^i modulo p (1<=b_i<p-1), the\n;   sequence\n;\n;                           (b_i-1)/(p-1)\n;\n;   is a cyclical sequence of p-1 distinct numbers in the range 0 to 1\n;   (excluding 1). By choosing a suitably, these can be made to look\n;   fairly random.\n;\n;     65537 is a Mersenne prime 2^16-1. Note.\n;\n;   Use this, & Gauss' law of quadratic reciprocity, to show that 75\n;   is a primitive root modulo 65537.\n;\n;     The ZX81 uses p=65537 & a=75, & stores some b_i-1 in memory.\n;   The function RND involves replacing b_i-1 in memory by b_(i+1)-1,\n;   & yielding the result (b_(i+1)-1)/(p-1). RAND n (with 1<=n<=65535)\n;   makes b_i equal to n+1.\n;\n; --------------------------------------------------------------------\n;\n; Steven Vickers writing in comp.sys.sinclair on 20-DEC-1993\n;\n;   Note. (Of course, 65537 is 2^16 + 1, not -1.)\n;\n;   Consider arithmetic modulo a prime p. There are p residue classes, and the\n;   non-zero ones are all invertible. Hence under multiplication they form a\n;   group (Fp*, say) of order p-1; moreover (and not so obvious) Fp* is cyclic.\n;   Its generators are the \"primitive roots\". The \"quadratic residues modulo p\"\n;   are the squares in Fp*, and the \"Legendre symbol\" (d/p) is defined (when p\n;   does not divide d) as +1 or -1, according as d is or is not a quadratic\n;   residue mod p.\n;\n;   In the case when p = 65537, we can show that d is a primitive root if and\n;   only if it's not a quadratic residue. For let w be a primitive root, d\n;   congruent to w^r (mod p). If d is not primitive, then its order is a proper\n;   factor of 65536: hence w^{32768*r} = 1 (mod p), so 65536 divides 32768*r,\n;   and hence r is even and d is a square (mod p). Conversely, the squares in\n;   Fp* form a subgroup of (Fp*)^2 of index 2, and so cannot be generators.\n;\n;   Hence to check whether 75 is primitive mod 65537, we want to calculate that\n;   (75/65537) = -1. There is a multiplicative formula (ab/p) = (a/p)(b/p) (mod\n;   p), so (75/65537) = (5/65537)^2 * (3/65537) = (3/65537). Now the law of\n;   quadratic reciprocity says that if p and q are distinct odd primes, then\n;\n;    (p/q)(q/p) = (-1)^{(p-1)(q-1)/4}\n;\n;   Hence (3/65537) = (65537/3) * (-1)^{65536*2/4} = (65537/3)\n;            = (2/3)  (because 65537 = 2 mod 3)\n;            = -1\n;\n;   (I referred to Pierre Samuel's \"Algebraic Theory of Numbers\".)\n;\n; ->\n\n;; S-RND\nL25F8:  CALL    L2530           ; routine SYNTAX-Z\n        JR      Z,L2625         ; forward to S-RND-END if checking syntax.\n\n        LD      BC,($5C76)      ; fetch system variable SEED\n        CALL    L2D2B           ; routine STACK-BC places on calculator stack\n\n        RST     28H             ;; FP-CALC           ;s.\n        DEFB    $A1             ;;stk-one            ;s,1.\n        DEFB    $0F             ;;addition           ;s+1.\n        DEFB    $34             ;;stk-data           ;\n        DEFB    $37             ;;Exponent: $87,\n                                ;;Bytes: 1\n        DEFB    $16             ;;(+00,+00,+00)      ;s+1,75.\n        DEFB    $04             ;;multiply           ;(s+1)*75 = v\n        DEFB    $34             ;;stk-data           ;v.\n        DEFB    $80             ;;Bytes: 3\n        DEFB    $41             ;;Exponent $91\n        DEFB    $00,$00,$80     ;;(+00)              ;v,65537.\n        DEFB    $32             ;;n-mod-m            ;remainder, result.\n        DEFB    $02             ;;delete             ;remainder.\n        DEFB    $A1             ;;stk-one            ;remainder, 1.\n        DEFB    $03             ;;subtract           ;remainder - 1. = rnd\n        DEFB    $31             ;;duplicate          ;rnd,rnd.\n        DEFB    $38             ;;end-calc\n\n        CALL    L2DA2           ; routine FP-TO-BC\n        LD      ($5C76),BC      ; store in SEED for next starting point.\n        LD      A,(HL)          ; fetch exponent\n        AND     A               ; is it zero ?\n        JR      Z,L2625         ; forward if so to S-RND-END\n\n        SUB     $10             ; reduce exponent by 2^16\n        LD      (HL),A          ; place back\n\n;; S-RND-END\nL2625:  JR      L2630           ; forward to S-PI-END\n\n; ---\n\n; the number PI 3.14159...\n\n; ->\n;; S-PI\nL2627:  CALL    L2530           ; routine SYNTAX-Z\n        JR      Z,L2630         ; to S-PI-END if checking syntax.\n\n        RST     28H             ;; FP-CALC\n        DEFB    $A3             ;;stk-pi/2                          pi/2.\n        DEFB    $38             ;;end-calc\n\n        INC     (HL)            ; increment the exponent leaving pi\n                                ; on the calculator stack.\n\n;; S-PI-END\nL2630:  RST     20H             ; NEXT-CHAR\n        JP      L26C3           ; jump forward to S-NUMERIC\n\n; ---\n\n; ->\n;; S-INKEY$\nL2634:  LD      BC,$105A        ; priority $10, operation code $1A ('read-in')\n                                ; +$40 for string result, numeric operand.\n                                ; set this up now in case we need to use the\n                                ; calculator.\n        RST     20H             ; NEXT-CHAR\n        CP      $23             ; '#' ?\n        JP      Z,L270D         ; to S-PUSH-PO if so to use the calculator\n                                ; single operation\n                                ; to read from network/RS232 etc. .\n\n; else read a key from the keyboard.\n\n        LD      HL,$5C3B        ; fetch FLAGS\n        RES     6,(HL)          ; signal string result.\n        BIT     7,(HL)          ; checking syntax ?\n        JR      Z,L2665         ; forward to S-INK$-EN if so\n\n        CALL    L028E           ; routine KEY-SCAN key in E, shift in D.\n        LD      C,$00           ; the length of an empty string\n        JR      NZ,L2660        ; to S-IK$-STK to store empty string if\n                                ; no key returned.\n\n        CALL    L031E           ; routine K-TEST get main code in A\n        JR      NC,L2660        ; to S-IK$-STK to stack null string if\n                                ; invalid\n\n        DEC     D               ; D is expected to be FLAGS so set bit 3 $FF\n                                ; 'L' Mode so no keywords.\n        LD      E,A             ; main key to A\n                                ; C is MODE 0 'KLC' from above still.\n        CALL    L0333           ; routine K-DECODE\n        PUSH    AF              ; save the code\n        LD      BC,$0001        ; make room for one character\n\n        RST     30H             ; BC-SPACES\n        POP     AF              ; bring the code back\n        LD      (DE),A          ; put the key in workspace\n        LD      C,$01           ; set C length to one\n\n;; S-IK$-STK\nL2660:  LD      B,$00           ; set high byte of length to zero\n        CALL    L2AB2           ; routine STK-STO-$\n\n;; S-INK$-EN\nL2665:  JP      L2712           ; to S-CONT-2            ===>\n\n; ---\n\n; ->\n;; S-SCREEN$\nL2668:  CALL    L2522           ; routine S-2-COORD\n        CALL    NZ,L2535        ; routine S-SCRN$-S\n\n        RST     20H             ; NEXT-CHAR\n        JP      L25DB           ; forward to S-STRING to stack result\n\n; ---\n\n; ->\n;; S-ATTR\nL2672:  CALL    L2522           ; routine S-2-COORD\n        CALL    NZ,L2580        ; routine S-ATTR-S\n\n        RST     20H             ; NEXT-CHAR\n        JR      L26C3           ; forward to S-NUMERIC\n\n; ---\n\n; ->\n;; S-POINT\nL267B:  CALL    L2522           ; routine S-2-COORD\n        CALL    NZ,L22CB        ; routine POINT-SUB\n\n        RST     20H             ; NEXT-CHAR\n        JR      L26C3           ; forward to S-NUMERIC\n\n; -----------------------------\n\n; ==> The branch was here if not in table.\n\n;; S-ALPHNUM\nL2684:  CALL    L2C88           ; routine ALPHANUM checks if variable or\n                                ; a digit.\n        JR      NC,L26DF        ; forward to S-NEGATE if not to consider\n                                ; a '-' character then functions.\n\n        CP      $41             ; compare 'A'\n        JR      NC,L26C9        ; forward to S-LETTER if alpha       ->\n                                ; else must have been numeric so continue\n                                ; into that routine.\n\n; This important routine is called during runtime and from LINE-SCAN\n; when a BASIC line is checked for syntax. It is this routine that\n; inserts, during syntax checking, the invisible floating point numbers\n; after the numeric expression. During runtime it just picks these\n; numbers up. It also handles BIN format numbers.\n\n; ->\n;; S-BIN\n;; S-DECIMAL\nL268D:  CALL    L2530           ; routine SYNTAX-Z\n        JR      NZ,L26B5        ; to S-STK-DEC in runtime\n\n; this route is taken when checking syntax.\n\n        CALL    L2C9B           ; routine DEC-TO-FP to evaluate number\n\n        RST     18H             ; GET-CHAR to fetch HL\n        LD      BC,$0006        ; six locations required\n        CALL    L1655           ; routine MAKE-ROOM\n        INC     HL              ; to first new location\n        LD      (HL),$0E        ; insert number marker\n        INC     HL              ; address next\n        EX      DE,HL           ; make DE destination.\n        LD      HL,($5C65)      ; STKEND points to end of stack.\n        LD      C,$05           ; result is five locations lower\n        AND     A               ; prepare for true subtraction\n        SBC     HL,BC           ; point to start of value.\n        LD      ($5C65),HL      ; update STKEND as we are taking number.\n        LDIR                    ; Copy five bytes to program location\n        EX      DE,HL           ; transfer pointer to HL\n        DEC     HL              ; adjust\n        CALL    L0077           ; routine TEMP-PTR1 sets CH-ADD\n        JR      L26C3           ; to S-NUMERIC to record nature of result\n\n; ---\n\n; branch here in runtime.\n\n;; S-STK-DEC\nL26B5:  RST     18H             ; GET-CHAR positions HL at digit.\n\n;; S-SD-SKIP\nL26B6:  INC     HL              ; advance pointer\n        LD      A,(HL)          ; until we find\n        CP      $0E             ; chr 14d - the number indicator\n        JR      NZ,L26B6        ; to S-SD-SKIP until a match\n                                ; it has to be here.\n\n        INC     HL              ; point to first byte of number\n        CALL    L33B4           ; routine STACK-NUM stacks it\n        LD      ($5C5D),HL      ; update system variable CH_ADD\n\n;; S-NUMERIC\nL26C3:  SET     6,(IY+$01)      ; update FLAGS  - Signal numeric result\n        JR      L26DD           ; forward to S-CONT-1               ===>\n                                ; actually S-CONT-2 is destination but why\n                                ; waste a byte on a jump when a JR will do.\n                                ; Actually a JR L2712 can be used. Rats.\n\n; end of functions accessed from scanning functions table.\n\n; --------------------------\n; Scanning variable routines\n; --------------------------\n;\n;\n\n;; S-LETTER\nL26C9:  CALL    L28B2           ; routine LOOK-VARS\n\n        JP      C,L1C2E         ; jump back to REPORT-2 if variable not found\n                                ; 'Variable not found'\n                                ; but a variable is always 'found' if syntax\n                                ; is being checked.\n\n        CALL    Z,L2996         ; routine STK-VAR considers a subscript/slice\n        LD      A,($5C3B)       ; fetch FLAGS value\n        CP      $C0             ; compare 11000000\n        JR      C,L26DD         ; step forward to S-CONT-1 if string  ===>\n\n        INC     HL              ; advance pointer\n        CALL    L33B4           ; routine STACK-NUM\n\n;; S-CONT-1\nL26DD:  JR      L2712           ; forward to S-CONT-2                 ===>\n\n; ----------------------------------------\n; -> the scanning branch was here if not alphanumeric.\n; All the remaining functions will be evaluated by a single call to the\n; calculator. The correct priority for the operation has to be placed in\n; the B register and the operation code, calculator literal in the C register.\n; the operation code has bit 7 set if result is numeric and bit 6 is\n; set if operand is numeric. so\n; $C0 = numeric result, numeric operand.            e.g. 'sin'\n; $80 = numeric result, string operand.             e.g. 'code'\n; $40 = string result, numeric operand.             e.g. 'str$'\n; $00 = string result, string operand.              e.g. 'val$'\n\n;; S-NEGATE\nL26DF:  LD      BC,$09DB        ; prepare priority 09, operation code $C0 +\n                                ; 'negate' ($1B) - bits 6 and 7 set for numeric\n                                ; result and numeric operand.\n\n        CP      $2D             ; is it '-' ?\n        JR      Z,L270D         ; forward if so to S-PUSH-PO\n\n        LD      BC,$1018        ; prepare priority $10, operation code 'val$' -\n                                ; bits 6 and 7 reset for string result and\n                                ; string operand.\n\n        CP      $AE             ; is it 'VAL$' ?\n        JR      Z,L270D         ; forward if so to S-PUSH-PO\n\n        SUB     $AF             ; subtract token 'CODE' value to reduce\n                                ; functions 'CODE' to 'NOT' although the\n                                ; upper range is, as yet, unchecked.\n                                ; valid range would be $00 - $14.\n\n        JP      C,L1C8A         ; jump back to REPORT-C with anything else\n                                ; 'Nonsense in BASIC'\n\n        LD      BC,$04F0        ; prepare priority $04, operation $C0 +\n                                ; 'not' ($30)\n\n        CP      $14             ; is it 'NOT'\n        JR      Z,L270D         ; forward to S-PUSH-PO if so\n\n        JP      NC,L1C8A        ; to REPORT-C if higher\n                                ; 'Nonsense in BASIC'\n\n        LD      B,$10           ; priority $10 for all the rest\n        ADD     A,$DC           ; make range $DC - $EF\n                                ; $C0 + 'code'($1C) thru 'chr$' ($2F)\n\n        LD      C,A             ; transfer 'function' to C\n        CP      $DF             ; is it 'sin' ?\n        JR      NC,L2707        ; forward to S-NO-TO-$  with 'sin' through\n                                ; 'chr$' as operand is numeric.\n\n; all the rest 'cos' through 'chr$' give a numeric result except 'str$'\n; and 'chr$'.\n\n        RES     6,C             ; signal string operand for 'code', 'val' and\n                                ; 'len'.\n\n;; S-NO-TO-$\nL2707:  CP      $EE             ; compare 'str$'\n        JR      C,L270D         ; forward to S-PUSH-PO if lower as result\n                                ; is numeric.\n\n        RES     7,C             ; reset bit 7 of op code for 'str$', 'chr$'\n                                ; as result is string.\n\n; >> This is where they were all headed for.\n\n;; S-PUSH-PO\nL270D:  PUSH    BC              ; push the priority and calculator operation\n                                ; code.\n\n        RST     20H             ; NEXT-CHAR\n        JP      L24FF           ; jump back to S-LOOP-1 to go round the loop\n                                ; again with the next character.\n\n; --------------------------------\n\n; ===>  there were many branches forward to here\n\n;   An important step after the evaluation of an expression is to test for\n;   a string expression and allow it to be sliced.  If a numeric expression is\n;   followed by a '(' then the numeric expression is complete.\n;   Since a string slice can itself be sliced then loop repeatedly\n;   e.g. (STR$ PI) (3 TO) (TO 2)    or \"nonsense\" (4 TO )\n\n;; S-CONT-2\nL2712:  RST     18H             ; GET-CHAR\n\n;; S-CONT-3\nL2713:  CP      $28             ; is it '(' ?\n        JR      NZ,L2723        ; forward, if not, to S-OPERTR\n\n        BIT     6,(IY+$01)      ; test FLAGS - numeric or string result ?\n        JR      NZ,L2734        ; forward, if numeric, to S-LOOP\n\n;   if a string expression preceded the '(' then slice it.\n\n        CALL    L2A52           ; routine SLICING\n\n        RST     20H             ; NEXT-CHAR\n        JR      L2713           ; loop back to S-CONT-3\n\n; ---------------------------\n\n;   the branch was here when possibility of a '(' has been excluded.\n\n;; S-OPERTR\nL2723:  LD      B,$00           ; prepare to add\n        LD      C,A             ; possible operator to C\n        LD      HL,L2795        ; Address: $2795 - tbl-of-ops\n        CALL    L16DC           ; routine INDEXER\n        JR      NC,L2734        ; forward to S-LOOP if not in table\n\n;   but if found in table the priority has to be looked up.\n\n        LD      C,(HL)          ; operation code to C ( B is still zero )\n        LD      HL,L27B0 - $C3  ; $26ED is base of table\n        ADD     HL,BC           ; index into table.\n        LD      B,(HL)          ; priority to B.\n\n; ------------------\n; Scanning main loop\n; ------------------\n; the juggling act\n\n;; S-LOOP\nL2734:  POP     DE              ; fetch last priority and operation\n        LD      A,D             ; priority to A\n        CP      B               ; compare with this one\n        JR      C,L2773         ; forward to S-TIGHTER to execute the\n                                ; last operation before this one as it has\n                                ; higher priority.\n\n; the last priority was greater or equal this one.\n\n        AND     A               ; if it is zero then so is this\n        JP      Z,L0018         ; jump to exit via get-char pointing at\n                                ; next character.\n                                ; This may be the character after the\n                                ; expression or, if exiting a recursive call,\n                                ; the next part of the expression to be\n                                ; evaluated.\n\n        PUSH    BC              ; save current priority/operation\n                                ; as it has lower precedence than the one\n                                ; now in DE.\n\n; the 'USR' function is special in that it is overloaded to give two types\n; of result.\n\n        LD      HL,$5C3B        ; address FLAGS\n        LD      A,E             ; new operation to A register\n        CP      $ED             ; is it $C0 + 'usr-no' ($2D)  ?\n        JR      NZ,L274C        ; forward to S-STK-LST if not\n\n        BIT     6,(HL)          ; string result expected ?\n                                ; (from the lower priority operand we've\n                                ; just pushed on stack )\n        JR      NZ,L274C        ; forward to S-STK-LST if numeric\n                                ; as operand bits match.\n\n        LD      E,$99           ; reset bit 6 and substitute $19 'usr-$'\n                                ; for string operand.\n\n;; S-STK-LST\nL274C:  PUSH    DE              ; now stack this priority/operation\n        CALL    L2530           ; routine SYNTAX-Z\n        JR      Z,L275B         ; forward to S-SYNTEST if checking syntax.\n\n        LD      A,E             ; fetch the operation code\n        AND     $3F             ; mask off the result/operand bits to leave\n                                ; a calculator literal.\n        LD      B,A             ; transfer to B register\n\n; now use the calculator to perform the single operation - operand is on\n; the calculator stack.\n; Note. although the calculator is performing a single operation most\n; functions e.g. TAN are written using other functions and literals and\n; these in turn are written using further strings of calculator literals so\n; another level of magical recursion joins the juggling act for a while\n; as the calculator too is calling itself.\n\n        RST     28H             ;; FP-CALC\n        DEFB    $3B             ;;fp-calc-2\nL2758:  DEFB    $38             ;;end-calc\n\n        JR      L2764           ; forward to S-RUNTEST\n\n; ---\n\n; the branch was here if checking syntax only.\n\n;; S-SYNTEST\nL275B:  LD      A,E             ; fetch the operation code to accumulator\n        XOR     (IY+$01)        ; compare with bits of FLAGS\n        AND     $40             ; bit 6 will be zero now if operand\n                                ; matched expected result.\n\n;; S-RPORT-C2\nL2761:  JP      NZ,L1C8A        ; to REPORT-C if mismatch\n                                ; 'Nonsense in BASIC'\n                                ; else continue to set flags for next\n\n; the branch is to here in runtime after a successful operation.\n\n;; S-RUNTEST\nL2764:  POP     DE              ; fetch the last operation from stack\n        LD      HL,$5C3B        ; address FLAGS\n        SET     6,(HL)          ; set default to numeric result in FLAGS\n        BIT     7,E             ; test the operational result\n        JR      NZ,L2770        ; forward to S-LOOPEND if numeric\n\n        RES     6,(HL)          ; reset bit 6 of FLAGS to show string result.\n\n;; S-LOOPEND\nL2770:  POP     BC              ; fetch the previous priority/operation\n        JR      L2734           ; back to S-LOOP to perform these\n\n; ---\n\n; the branch was here when a stacked priority/operator had higher priority\n; than the current one.\n\n;; S-TIGHTER\nL2773:  PUSH    DE              ; save high priority op on stack again\n        LD      A,C             ; fetch lower priority operation code\n        BIT     6,(IY+$01)      ; test FLAGS - Numeric or string result ?\n        JR      NZ,L2790        ; forward to S-NEXT if numeric result\n\n; if this is lower priority yet has string then must be a comparison.\n; Since these can only be evaluated in context and were defaulted to\n; numeric in operator look up they must be changed to string equivalents.\n\n        AND     $3F             ; mask to give true calculator literal\n        ADD     A,$08           ; augment numeric literals to string\n                                ; equivalents.\n                                ; 'no-&-no'  => 'str-&-no'\n                                ; 'no-l-eql' => 'str-l-eql'\n                                ; 'no-gr-eq' => 'str-gr-eq'\n                                ; 'nos-neql' => 'strs-neql'\n                                ; 'no-grtr'  => 'str-grtr'\n                                ; 'no-less'  => 'str-less'\n                                ; 'nos-eql'  => 'strs-eql'\n                                ; 'addition' => 'strs-add'\n        LD      C,A             ; put modified comparison operator back\n        CP      $10             ; is it now 'str-&-no' ?\n        JR      NZ,L2788        ; forward to S-NOT-AND  if not.\n\n        SET     6,C             ; set numeric operand bit\n        JR      L2790           ; forward to S-NEXT\n\n; ---\n\n;; S-NOT-AND\nL2788:  JR      C,L2761         ; back to S-RPORT-C2 if less\n                                ; 'Nonsense in BASIC'.\n                                ; e.g. a$ * b$\n\n        CP      $17             ; is it 'strs-add' ?\n        JR      Z,L2790         ; forward to S-NEXT if so\n                                ; (bit 6 and 7 are reset)\n\n        SET     7,C             ; set numeric (Boolean) result for all others\n\n;; S-NEXT\nL2790:  PUSH    BC              ; now save this priority/operation on stack\n\n        RST     20H             ; NEXT-CHAR\n        JP      L24FF           ; jump back to S-LOOP-1\n\n; ------------------\n; Table of operators\n; ------------------\n; This table is used to look up the calculator literals associated with\n; the operator character. The thirteen calculator operations $03 - $0F\n; have bits 6 and 7 set to signify a numeric result.\n; Some of these codes and bits may be altered later if the context suggests\n; a string comparison or operation.\n; that is '+', '=', '>', '<', '<=', '>=' or '<>'.\n\n;; tbl-of-ops\nL2795:  DEFB    '+', $CF        ;        $C0 + 'addition'\n        DEFB    '-', $C3        ;        $C0 + 'subtract'\n        DEFB    '*', $C4        ;        $C0 + 'multiply'\n        DEFB    '/', $C5        ;        $C0 + 'division'\n        DEFB    '^', $C6        ;        $C0 + 'to-power'\n        DEFB    '=', $CE        ;        $C0 + 'nos-eql'\n        DEFB    '>', $CC        ;        $C0 + 'no-grtr'\n        DEFB    '<', $CD        ;        $C0 + 'no-less'\n\n        DEFB    $C7, $C9        ; '<='   $C0 + 'no-l-eql'\n        DEFB    $C8, $CA        ; '>='   $C0 + 'no-gr-eql'\n        DEFB    $C9, $CB        ; '<>'   $C0 + 'nos-neql'\n        DEFB    $C5, $C7        ; 'OR'   $C0 + 'or'\n        DEFB    $C6, $C8        ; 'AND'  $C0 + 'no-&-no'\n\n        DEFB    $00             ; zero end-marker.\n\n\n; -------------------\n; Table of priorities\n; -------------------\n; This table is indexed with the operation code obtained from the above\n; table $C3 - $CF to obtain the priority for the respective operation.\n\n;; tbl-priors\nL27B0:  DEFB    $06             ; '-'   opcode $C3\n        DEFB    $08             ; '*'   opcode $C4\n        DEFB    $08             ; '/'   opcode $C5\n        DEFB    $0A             ; '^'   opcode $C6\n        DEFB    $02             ; 'OR'  opcode $C7\n        DEFB    $03             ; 'AND' opcode $C8\n        DEFB    $05             ; '<='  opcode $C9\n        DEFB    $05             ; '>='  opcode $CA\n        DEFB    $05             ; '<>'  opcode $CB\n        DEFB    $05             ; '>'   opcode $CC\n        DEFB    $05             ; '<'   opcode $CD\n        DEFB    $05             ; '='   opcode $CE\n        DEFB    $06             ; '+'   opcode $CF\n\n; ----------------------\n; Scanning function (FN)\n; ----------------------\n; This routine deals with user-defined functions.\n; The definition can be anywhere in the program area but these are best\n; placed near the start of the program as we shall see.\n; The evaluation process is quite complex as the Spectrum has to parse two\n; statements at the same time. Syntax of both has been checked previously\n; and hidden locations have been created immediately after each argument\n; of the DEF FN statement. Each of the arguments of the FN function is\n; evaluated by SCANNING and placed in the hidden locations. Then the\n; expression to the right of the DEF FN '=' is evaluated by SCANNING and for\n; any variables encountered, a search is made in the DEF FN variable list\n; in the program area before searching in the normal variables area.\n;\n; Recursion is not allowed: i.e. the definition of a function should not use\n; the same function, either directly or indirectly ( through another function).\n; You'll normally get error 4, ('Out of memory'), although sometimes the system\n; will crash. - Vickers, Pitman 1984.\n;\n; As the definition is just an expression, there would seem to be no means\n; of breaking out of such recursion.\n; However, by the clever use of string expressions and VAL, such recursion is\n; possible.\n; e.g. DEF FN a(n) = VAL \"n+FN a(n-1)+0\" ((n<1) * 10 + 1 TO )\n; will evaluate the full 11-character expression for all values where n is\n; greater than zero but just the 11th character, \"0\", when n drops to zero\n; thereby ending the recursion producing the correct result.\n; Recursive string functions are possible using VAL$ instead of VAL and the\n; null string as the final addend.\n; - from a turn of the century newsgroup discussion initiated by Mike Wynne.\n\n;; S-FN-SBRN\nL27BD:  CALL    L2530           ; routine SYNTAX-Z\n        JR      NZ,L27F7        ; forward to SF-RUN in runtime\n\n\n        RST     20H             ; NEXT-CHAR\n        CALL    L2C8D           ; routine ALPHA check for letters A-Z a-z\n        JP      NC,L1C8A        ; jump back to REPORT-C if not\n                                ; 'Nonsense in BASIC'\n\n\n        RST     20H             ; NEXT-CHAR\n        CP      $24             ; is it '$' ?\n        PUSH    AF              ; save character and flags\n        JR      NZ,L27D0        ; forward to SF-BRKT-1 with numeric function\n\n\n        RST     20H             ; NEXT-CHAR\n\n;; SF-BRKT-1\nL27D0:  CP      $28             ; is '(' ?\n        JR      NZ,L27E6        ; forward to SF-RPRT-C if not\n                                ; 'Nonsense in BASIC'\n\n\n        RST     20H             ; NEXT-CHAR\n        CP      $29             ; is it ')' ?\n        JR      Z,L27E9         ; forward to SF-FLAG-6 if no arguments.\n\n;; SF-ARGMTS\nL27D9:  CALL    L24FB           ; routine SCANNING checks each argument\n                                ; which may be an expression.\n\n        RST     18H             ; GET-CHAR\n        CP      $2C             ; is it a ',' ?\n        JR      NZ,L27E4        ; forward if not to SF-BRKT-2 to test bracket\n\n\n        RST     20H             ; NEXT-CHAR if a comma was found\n        JR      L27D9           ; back to SF-ARGMTS to parse all arguments.\n\n; ---\n\n;; SF-BRKT-2\nL27E4:  CP      $29             ; is character the closing ')' ?\n\n;; SF-RPRT-C\nL27E6:  JP      NZ,L1C8A        ; jump to REPORT-C\n                                ; 'Nonsense in BASIC'\n\n; at this point any optional arguments have had their syntax checked.\n\n;; SF-FLAG-6\nL27E9:  RST     20H             ; NEXT-CHAR\n        LD      HL,$5C3B        ; address system variable FLAGS\n        RES     6,(HL)          ; signal string result\n        POP     AF              ; restore test against '$'.\n        JR      Z,L27F4         ; forward to SF-SYN-EN if string function.\n\n        SET     6,(HL)          ; signal numeric result\n\n;; SF-SYN-EN\nL27F4:  JP      L2712           ; jump back to S-CONT-2 to continue scanning.\n\n; ---\n\n; the branch was here in runtime.\n\n;; SF-RUN\nL27F7:  RST     20H             ; NEXT-CHAR fetches name\n        AND     $DF             ; AND 11101111 - reset bit 5 - upper-case.\n        LD      B,A             ; save in B\n\n        RST     20H             ; NEXT-CHAR\n        SUB     $24             ; subtract '$'\n        LD      C,A             ; save result in C\n        JR      NZ,L2802        ; forward if not '$' to SF-ARGMT1\n\n        RST     20H             ; NEXT-CHAR advances to bracket\n\n;; SF-ARGMT1\nL2802:  RST     20H             ; NEXT-CHAR advances to start of argument\n        PUSH    HL              ; save address\n        LD      HL,($5C53)      ; fetch start of program area from PROG\n        DEC     HL              ; the search starting point is the previous\n                                ; location.\n\n;; SF-FND-DF\nL2808:  LD      DE,$00CE        ; search is for token 'DEF FN' in E,\n                                ; statement count in D.\n        PUSH    BC              ; save C the string test, and B the letter.\n        CALL    L1D86           ; routine LOOK-PROG will search for token.\n        POP     BC              ; restore BC.\n        JR      NC,L2814        ; forward to SF-CP-DEF if a match was found.\n\n\n;; REPORT-P\nL2812:  RST     08H             ; ERROR-1\n        DEFB    $18             ; Error Report: FN without DEF\n\n;; SF-CP-DEF\nL2814:  PUSH    HL              ; save address of DEF FN\n        CALL    L28AB           ; routine FN-SKPOVR skips over white-space etc.\n                                ; without disturbing CH-ADD.\n        AND     $DF             ; make fetched character upper-case.\n        CP      B               ; compare with FN name\n        JR      NZ,L2825        ; forward to SF-NOT-FD if no match.\n\n; the letters match so test the type.\n\n        CALL    L28AB           ; routine FN-SKPOVR skips white-space\n        SUB     $24             ; subtract '$' from fetched character\n        CP      C               ; compare with saved result of same operation\n                                ; on FN name.\n        JR      Z,L2831         ; forward to SF-VALUES with a match.\n\n; the letters matched but one was string and the other numeric.\n\n;; SF-NOT-FD\nL2825:  POP     HL              ; restore search point.\n        DEC     HL              ; make location before\n        LD      DE,$0200        ; the search is to be for the end of the\n                                ; current definition - 2 statements forward.\n        PUSH    BC              ; save the letter/type\n        CALL    L198B           ; routine EACH-STMT steps past rejected\n                                ; definition.\n        POP     BC              ; restore letter/type\n        JR      L2808           ; back to SF-FND-DF to continue search\n\n; ---\n\n; Success!\n; the branch was here with matching letter and numeric/string type.\n\n;; SF-VALUES\nL2831:  AND     A               ; test A ( will be zero if string '$' - '$' )\n\n        CALL    Z,L28AB         ; routine FN-SKPOVR advances HL past '$'.\n\n        POP     DE              ; discard pointer to 'DEF FN'.\n        POP     DE              ; restore pointer to first FN argument.\n        LD      ($5C5D),DE      ; save in CH_ADD\n\n        CALL    L28AB           ; routine FN-SKPOVR advances HL past '('\n        PUSH    HL              ; save start address in DEF FN  ***\n        CP      $29             ; is character a ')' ?\n        JR      Z,L2885         ; forward to SF-R-BR-2 if no arguments.\n\n;; SF-ARG-LP\nL2843:  INC     HL              ; point to next character.\n        LD      A,(HL)          ; fetch it.\n        CP      $0E             ; is it the number marker\n        LD      D,$40           ; signal numeric in D.\n        JR      Z,L2852         ; forward to SF-ARG-VL if numeric.\n\n        DEC     HL              ; back to letter\n        CALL    L28AB           ; routine FN-SKPOVR skips any white-space\n        INC     HL              ; advance past the expected '$' to\n                                ; the 'hidden' marker.\n        LD      D,$00           ; signal string.\n\n;; SF-ARG-VL\nL2852:  INC     HL              ; now address first of 5-byte location.\n        PUSH    HL              ; save address in DEF FN statement\n        PUSH    DE              ; save D - result type\n\n        CALL    L24FB           ; routine SCANNING evaluates expression in\n                                ; the FN statement setting FLAGS and leaving\n                                ; result as last value on calculator stack.\n\n        POP     AF              ; restore saved result type to A\n\n        XOR     (IY+$01)        ; xor with FLAGS\n        AND     $40             ; and with 01000000 to test bit 6\n        JR      NZ,L288B        ; forward to REPORT-Q if type mismatch.\n                                ; 'Parameter error'\n\n        POP     HL              ; pop the start address in DEF FN statement\n        EX      DE,HL           ; transfer to DE ?? pop straight into de ?\n\n        LD      HL,($5C65)      ; set HL to STKEND location after value\n        LD      BC,$0005        ; five bytes to move\n        SBC     HL,BC           ; decrease HL by 5 to point to start.\n        LD      ($5C65),HL      ; set STKEND 'removing' value from stack.\n\n        LDIR                    ; copy value into DEF FN statement\n        EX      DE,HL           ; set HL to location after value in DEF FN\n        DEC     HL              ; step back one\n        CALL    L28AB           ; routine FN-SKPOVR gets next valid character\n        CP      $29             ; is it ')' end of arguments ?\n        JR      Z,L2885         ; forward to SF-R-BR-2 if so.\n\n; a comma separator has been encountered in the DEF FN argument list.\n\n        PUSH    HL              ; save position in DEF FN statement\n\n        RST     18H             ; GET-CHAR from FN statement\n        CP      $2C             ; is it ',' ?\n        JR      NZ,L288B        ; forward to REPORT-Q if not\n                                ; 'Parameter error'\n\n        RST     20H             ; NEXT-CHAR in FN statement advances to next\n                                ; argument.\n\n        POP     HL              ; restore DEF FN pointer\n        CALL    L28AB           ; routine FN-SKPOVR advances to corresponding\n                                ; argument.\n\n        JR      L2843           ; back to SF-ARG-LP looping until all\n                                ; arguments are passed into the DEF FN\n                                ; hidden locations.\n\n; ---\n\n; the branch was here when all arguments passed.\n\n;; SF-R-BR-2\nL2885:  PUSH    HL              ; save location of ')' in DEF FN\n\n        RST     18H             ; GET-CHAR gets next character in FN\n        CP      $29             ; is it a ')' also ?\n        JR      Z,L288D         ; forward to SF-VALUE if so.\n\n\n;; REPORT-Q\nL288B:  RST     08H             ; ERROR-1\n        DEFB    $19             ; Error Report: Parameter error\n\n;; SF-VALUE\nL288D:  POP     DE              ; location of ')' in DEF FN to DE.\n        EX      DE,HL           ; now to HL, FN ')' pointer to DE.\n        LD      ($5C5D),HL      ; initialize CH_ADD to this value.\n\n; At this point the start of the DEF FN argument list is on the machine stack.\n; We also have to consider that this defined function may form part of the\n; definition of another defined function (though not itself).\n; As this defined function may be part of a hierarchy of defined functions\n; currently being evaluated by recursive calls to SCANNING, then we have to\n; preserve the original value of DEFADD and not assume that it is zero.\n\n        LD      HL,($5C0B)      ; get original DEFADD address\n        EX      (SP),HL         ; swap with DEF FN address on stack ***\n        LD      ($5C0B),HL      ; set DEFADD to point to this argument list\n                                ; during scanning.\n\n        PUSH    DE              ; save FN ')' pointer.\n\n        RST     20H             ; NEXT-CHAR advances past ')' in define\n\n        RST     20H             ; NEXT-CHAR advances past '=' to expression\n\n        CALL    L24FB           ; routine SCANNING evaluates but searches\n                                ; initially for variables at DEFADD\n\n        POP     HL              ; pop the FN ')' pointer\n        LD      ($5C5D),HL      ; set CH_ADD to this\n        POP     HL              ; pop the original DEFADD value\n        LD      ($5C0B),HL      ; and re-insert into DEFADD system variable.\n\n        RST     20H             ; NEXT-CHAR advances to character after ')'\n        JP      L2712           ; to S-CONT-2 - to continue current\n                                ; invocation of scanning\n\n; --------------------\n; Used to parse DEF FN\n; --------------------\n; e.g. DEF FN     s $ ( x )     =  b     $ (  TO  x  ) : REM exaggerated\n;\n; This routine is used 10 times to advance along a DEF FN statement\n; skipping spaces and colour control codes. It is similar to NEXT-CHAR\n; which is, at the same time, used to skip along the corresponding FN function\n; except the latter has to deal with AT and TAB characters in string\n; expressions. These cannot occur in a program area so this routine is\n; simpler as both colour controls and their parameters are less than space.\n\n;; FN-SKPOVR\nL28AB:  INC     HL              ; increase pointer\n        LD      A,(HL)          ; fetch addressed character\n        CP      $21             ; compare with space + 1\n        JR      C,L28AB         ; back to FN-SKPOVR if less\n\n        RET                     ; return pointing to a valid character.\n\n; ---------\n; LOOK-VARS\n; ---------\n;\n;\n\n;; LOOK-VARS\nL28B2:  SET     6,(IY+$01)      ; update FLAGS - presume numeric result\n\n        RST     18H             ; GET-CHAR\n        CALL    L2C8D           ; routine ALPHA tests for A-Za-z\n        JP      NC,L1C8A        ; jump to REPORT-C if not.\n                                ; 'Nonsense in BASIC'\n\n        PUSH    HL              ; save pointer to first letter       ^1\n        AND     $1F             ; mask lower bits, 1 - 26 decimal     000xxxxx\n        LD      C,A             ; store in C.\n\n        RST     20H             ; NEXT-CHAR\n        PUSH    HL              ; save pointer to second character   ^2\n        CP      $28             ; is it '(' - an array ?\n        JR      Z,L28EF         ; forward to V-RUN/SYN if so.\n\n        SET     6,C             ; set 6 signaling string if solitary  010\n        CP      $24             ; is character a '$' ?\n        JR      Z,L28DE         ; forward to V-STR-VAR\n\n        SET     5,C             ; signal numeric                       011\n        CALL    L2C88           ; routine ALPHANUM sets carry if second\n                                ; character is alphanumeric.\n        JR      NC,L28E3        ; forward to V-TEST-FN if just one character\n\n; It is more than one character but re-test current character so that 6 reset\n; This loop renders the similar loop at V-PASS redundant.\n\n;; V-CHAR\nL28D4:  CALL    L2C88           ; routine ALPHANUM\n        JR      NC,L28EF        ; to V-RUN/SYN when no more\n\n        RES     6,C             ; make long named type                 001\n\n        RST     20H             ; NEXT-CHAR\n        JR      L28D4           ; loop back to V-CHAR\n\n; ---\n\n\n;; V-STR-VAR\nL28DE:  RST     20H             ; NEXT-CHAR advances past '$'\n        RES     6,(IY+$01)      ; update FLAGS - signal string result.\n\n;; V-TEST-FN\nL28E3:  LD      A,($5C0C)       ; load A with DEFADD_hi\n        AND     A               ; and test for zero.\n        JR      Z,L28EF         ; forward to V-RUN/SYN if a defined function\n                                ; is not being evaluated.\n\n; Note.\n\n        CALL    L2530           ; routine SYNTAX-Z\n        JP      NZ,L2951        ; JUMP to STK-F-ARG in runtime and then\n                                ; back to this point if no variable found.\n\n;; V-RUN/SYN\nL28EF:  LD      B,C             ; save flags in B\n        CALL    L2530           ; routine SYNTAX-Z\n        JR      NZ,L28FD        ; to V-RUN to look for the variable in runtime\n\n; if checking syntax the letter is not returned\n\n        LD      A,C             ; copy letter/flags to A\n        AND     $E0             ; and with 11100000 to get rid of the letter\n        SET     7,A             ; use spare bit to signal checking syntax.\n        LD      C,A             ; and transfer to C.\n        JR      L2934           ; forward to V-SYNTAX\n\n; ---\n\n; but in runtime search for the variable.\n\n;; V-RUN\nL28FD:  LD      HL,($5C4B)      ; set HL to start of variables from VARS\n\n;; V-EACH\nL2900:  LD      A,(HL)          ; get first character\n        AND     $7F             ; and with 01111111\n                                ; ignoring bit 7 which distinguishes\n                                ; arrays or for/next variables.\n\n        JR      Z,L2932         ; to V-80-BYTE if zero as must be 10000000\n                                ; the variables end-marker.\n\n        CP      C               ; compare with supplied value.\n        JR      NZ,L292A        ; forward to V-NEXT if no match.\n\n        RLA                     ; destructively test\n        ADD     A,A             ; bits 5 and 6 of A\n                                ; jumping if bit 5 reset or 6 set\n\n        JP      P,L293F         ; to V-FOUND-2  strings and arrays\n\n        JR      C,L293F         ; to V-FOUND-2  simple and for next\n\n; leaving long name variables.\n\n        POP     DE              ; pop pointer to 2nd. char\n        PUSH    DE              ; save it again\n        PUSH    HL              ; save variable first character pointer\n\n;; V-MATCHES\nL2912:  INC     HL              ; address next character in vars area\n\n;; V-SPACES\nL2913:  LD      A,(DE)          ; pick up letter from prog area\n        INC     DE              ; and advance address\n        CP      $20             ; is it a space\n        JR      Z,L2913         ; back to V-SPACES until non-space\n\n        OR      $20             ; convert to range 1 - 26.\n        CP      (HL)            ; compare with addressed variables character\n        JR      Z,L2912         ; loop back to V-MATCHES if a match on an\n                                ; intermediate letter.\n\n        OR      $80             ; now set bit 7 as last character of long\n                                ; names are inverted.\n        CP      (HL)            ; compare again\n        JR      NZ,L2929        ; forward to V-GET-PTR if no match\n\n; but if they match check that this is also last letter in prog area\n\n        LD      A,(DE)          ; fetch next character\n        CALL    L2C88           ; routine ALPHANUM sets carry if not alphanum\n        JR      NC,L293E        ; forward to V-FOUND-1 with a full match.\n\n;; V-GET-PTR\nL2929:  POP     HL              ; pop saved pointer to char 1\n\n;; V-NEXT\nL292A:  PUSH    BC              ; save flags\n        CALL    L19B8           ; routine NEXT-ONE gets next variable in DE\n        EX      DE,HL           ; transfer to HL.\n        POP     BC              ; restore the flags\n        JR      L2900           ; loop back to V-EACH\n                                ; to compare each variable\n\n; ---\n\n;; V-80-BYTE\nL2932:  SET     7,B             ; will signal not found\n\n; the branch was here when checking syntax\n\n;; V-SYNTAX\nL2934:  POP     DE              ; discard the pointer to 2nd. character  v2\n                                ; in BASIC line/workspace.\n\n        RST     18H             ; GET-CHAR gets character after variable name.\n        CP      $28             ; is it '(' ?\n        JR      Z,L2943         ; forward to V-PASS\n                                ; Note. could go straight to V-END ?\n\n        SET     5,B             ; signal not an array\n        JR      L294B           ; forward to V-END\n\n; ---------------------------\n\n; the jump was here when a long name matched and HL pointing to last character\n; in variables area.\n\n;; V-FOUND-1\nL293E:  POP     DE              ; discard pointer to first var letter\n\n; the jump was here with all other matches HL points to first var char.\n\n;; V-FOUND-2\nL293F:  POP     DE              ; discard pointer to 2nd prog char       v2\n        POP     DE              ; drop pointer to 1st prog char          v1\n        PUSH    HL              ; save pointer to last char in vars\n\n        RST     18H             ; GET-CHAR\n\n;; V-PASS\nL2943:  CALL    L2C88           ; routine ALPHANUM\n        JR      NC,L294B        ; forward to V-END if not\n\n; but it never will be as we advanced past long-named variables earlier.\n\n        RST     20H             ; NEXT-CHAR\n        JR      L2943           ; back to V-PASS\n\n; ---\n\n;; V-END\nL294B:  POP     HL              ; pop the pointer to first character in\n                                ; BASIC line/workspace.\n        RL      B               ; rotate the B register left\n                                ; bit 7 to carry\n        BIT     6,B             ; test the array indicator bit.\n        RET                     ; return\n\n; -----------------------\n; Stack function argument\n; -----------------------\n; This branch is taken from LOOK-VARS when a defined function is currently\n; being evaluated.\n; Scanning is evaluating the expression after the '=' and the variable\n; found could be in the argument list to the left of the '=' or in the\n; normal place after the program. Preference will be given to the former.\n; The variable name to be matched is in C.\n\n;; STK-F-ARG\nL2951:  LD      HL,($5C0B)      ; set HL to DEFADD\n        LD      A,(HL)          ; load the first character\n        CP      $29             ; is it ')' ?\n        JP      Z,L28EF         ; JUMP back to V-RUN/SYN, if so, as there are\n                                ; no arguments.\n\n; but proceed to search argument list of defined function first if not empty.\n\n;; SFA-LOOP\nL295A:  LD      A,(HL)          ; fetch character again.\n        OR      $60             ; or with 01100000 presume a simple variable.\n        LD      B,A             ; save result in B.\n        INC     HL              ; address next location.\n        LD      A,(HL)          ; pick up byte.\n        CP      $0E             ; is it the number marker ?\n        JR      Z,L296B         ; forward to SFA-CP-VR if so.\n\n; it was a string. White-space may be present but syntax has been checked.\n\n        DEC     HL              ; point back to letter.\n        CALL    L28AB           ; routine FN-SKPOVR skips to the '$'\n        INC     HL              ; now address the hidden marker.\n        RES     5,B             ; signal a string variable.\n\n;; SFA-CP-VR\nL296B:  LD      A,B             ; transfer found variable letter to A.\n        CP      C               ; compare with expected.\n        JR      Z,L2981         ; forward to SFA-MATCH with a match.\n\n        INC     HL              ; step\n        INC     HL              ; past\n        INC     HL              ; the\n        INC     HL              ; five\n        INC     HL              ; bytes.\n\n        CALL    L28AB           ; routine FN-SKPOVR skips to next character\n        CP      $29             ; is it ')' ?\n        JP      Z,L28EF         ; jump back if so to V-RUN/SYN to look in\n                                ; normal variables area.\n\n        CALL    L28AB           ; routine FN-SKPOVR skips past the ','\n                                ; all syntax has been checked and these\n                                ; things can be taken as read.\n        JR      L295A           ; back to SFA-LOOP while there are more\n                                ; arguments.\n\n; ---\n\n;; SFA-MATCH\nL2981:  BIT     5,C             ; test if numeric\n        JR      NZ,L2991        ; to SFA-END if so as will be stacked\n                                ; by scanning\n\n        INC     HL              ; point to start of string descriptor\n        LD      DE,($5C65)      ; set DE to STKEND\n        CALL    L33C0           ; routine MOVE-FP puts parameters on stack.\n        EX      DE,HL           ; new free location to HL.\n        LD      ($5C65),HL      ; use it to set STKEND system variable.\n\n;; SFA-END\nL2991:  POP     DE              ; discard\n        POP     DE              ; pointers.\n        XOR     A               ; clear carry flag.\n        INC     A               ; and zero flag.\n        RET                     ; return.\n\n; ------------------------\n; Stack variable component\n; ------------------------\n; This is called to evaluate a complex structure that has been found, in\n; runtime, by LOOK-VARS in the variables area.\n; In this case HL points to the initial letter, bits 7-5\n; of which indicate the type of variable.\n; 010 - simple string, 110 - string array, 100 - array of numbers.\n;\n; It is called from CLASS-01 when assigning to a string or array including\n; a slice.\n; It is called from SCANNING to isolate the required part of the structure.\n;\n; An important part of the runtime process is to check that the number of\n; dimensions of the variable match the number of subscripts supplied in the\n; BASIC line.\n;\n; If checking syntax,\n; the B register, which counts dimensions is set to zero (256) to allow\n; the loop to continue till all subscripts are checked. While doing this it\n; is reading dimension sizes from some arbitrary area of memory. Although\n; these are meaningless it is of no concern as the limit is never checked by\n; int-exp during syntax checking.\n;\n; The routine is also called from the syntax path of DIM command to check the\n; syntax of both string and numeric arrays definitions except that bit 6 of C\n; is reset so both are checked as numeric arrays. This ruse avoids a terminal\n; slice being accepted as part of the DIM command.\n; All that is being checked is that there are a valid set of comma-separated\n; expressions before a terminal ')', although, as above, it will still go\n; through the motions of checking dummy dimension sizes.\n\n;; STK-VAR\nL2996:  XOR     A               ; clear A\n        LD      B,A             ; and B, the syntax dimension counter (256)\n        BIT     7,C             ; checking syntax ?\n        JR      NZ,L29E7        ; forward to SV-COUNT if so.\n\n; runtime evaluation.\n\n        BIT     7,(HL)          ; will be reset if a simple string.\n        JR      NZ,L29AE        ; forward to SV-ARRAYS otherwise\n\n        INC     A               ; set A to 1, simple string.\n\n;; SV-SIMPLE$\nL29A1:  INC     HL              ; address length low\n        LD      C,(HL)          ; place in C\n        INC     HL              ; address length high\n        LD      B,(HL)          ; place in B\n        INC     HL              ; address start of string\n        EX      DE,HL           ; DE = start now.\n        CALL    L2AB2           ; routine STK-STO-$ stacks string parameters\n                                ; DE start in variables area,\n                                ; BC length, A=1 simple string\n\n; the only thing now is to consider if a slice is required.\n\n        RST     18H             ; GET-CHAR puts character at CH_ADD in A\n        JP      L2A49           ; jump forward to SV-SLICE? to test for '('\n\n; --------------------------------------------------------\n\n; the branch was here with string and numeric arrays in runtime.\n\n;; SV-ARRAYS\nL29AE:  INC     HL              ; step past\n        INC     HL              ; the total length\n        INC     HL              ; to address Number of dimensions.\n        LD      B,(HL)          ; transfer to B overwriting zero.\n        BIT     6,C             ; a numeric array ?\n        JR      Z,L29C0         ; forward to SV-PTR with numeric arrays\n\n        DEC     B               ; ignore the final element of a string array\n                                ; the fixed string size.\n\n        JR      Z,L29A1         ; back to SV-SIMPLE$ if result is zero as has\n                                ; been created with DIM a$(10) for instance\n                                ; and can be treated as a simple string.\n\n; proceed with multi-dimensioned string arrays in runtime.\n\n        EX      DE,HL           ; save pointer to dimensions in DE\n\n        RST     18H             ; GET-CHAR looks at the BASIC line\n        CP      $28             ; is character '(' ?\n        JR      NZ,L2A20        ; to REPORT-3 if not\n                                ; 'Subscript wrong'\n\n        EX      DE,HL           ; dimensions pointer to HL to synchronize\n                                ; with next instruction.\n\n; runtime numeric arrays path rejoins here.\n\n;; SV-PTR\nL29C0:  EX      DE,HL           ; save dimension pointer in DE\n        JR      L29E7           ; forward to SV-COUNT with true no of dims\n                                ; in B. As there is no initial comma the\n                                ; loop is entered at the midpoint.\n\n; ----------------------------------------------------------\n; the dimension counting loop which is entered at mid-point.\n\n;; SV-COMMA\nL29C3:  PUSH    HL              ; save counter\n\n        RST     18H             ; GET-CHAR\n\n        POP     HL              ; pop counter\n        CP      $2C             ; is character ',' ?\n        JR      Z,L29EA         ; forward to SV-LOOP if so\n\n; in runtime the variable definition indicates a comma should appear here\n\n        BIT     7,C             ; checking syntax ?\n        JR      Z,L2A20         ; forward to REPORT-3 if not\n                                ; 'Subscript error'\n\n; proceed if checking syntax of an array?\n\n        BIT     6,C             ; array of strings\n        JR      NZ,L29D8        ; forward to SV-CLOSE if so\n\n; an array of numbers.\n\n        CP      $29             ; is character ')' ?\n        JR      NZ,L2A12        ; forward to SV-RPT-C if not\n                                ; 'Nonsense in BASIC'\n\n        RST     20H             ; NEXT-CHAR moves CH-ADD past the statement\n        RET                     ; return ->\n\n; ---\n\n; the branch was here with an array of strings.\n\n;; SV-CLOSE\nL29D8:  CP      $29             ; as above ')' could follow the expression\n        JR      Z,L2A48         ; forward to SV-DIM if so\n\n        CP      $CC             ; is it 'TO' ?\n        JR      NZ,L2A12        ; to SV-RPT-C with anything else\n                                ; 'Nonsense in BASIC'\n\n; now backtrack CH_ADD to set up for slicing routine.\n; Note. in a BASIC line we can safely backtrack to a colour parameter.\n\n;; SV-CH-ADD\nL29E0:  RST     18H             ; GET-CHAR\n        DEC     HL              ; backtrack HL\n        LD      ($5C5D),HL      ; to set CH_ADD up for slicing routine\n        JR      L2A45           ; forward to SV-SLICE and make a return\n                                ; when all slicing complete.\n\n; ----------------------------------------\n; -> the mid-point entry point of the loop\n\n;; SV-COUNT\nL29E7:  LD      HL,$0000        ; initialize data pointer to zero.\n\n;; SV-LOOP\nL29EA:  PUSH    HL              ; save the data pointer.\n\n        RST     20H             ; NEXT-CHAR in BASIC area points to an\n                                ; expression.\n\n        POP     HL              ; restore the data pointer.\n        LD      A,C             ; transfer name/type to A.\n        CP      $C0             ; is it 11000000 ?\n                                ; Note. the letter component is absent if\n                                ; syntax checking.\n        JR      NZ,L29FB        ; forward to SV-MULT if not an array of\n                                ; strings.\n\n; proceed to check string arrays during syntax.\n\n        RST     18H             ; GET-CHAR\n        CP      $29             ; ')'  end of subscripts ?\n        JR      Z,L2A48         ; forward to SV-DIM to consider further slice\n\n        CP      $CC             ; is it 'TO' ?\n        JR      Z,L29E0         ; back to SV-CH-ADD to consider a slice.\n                                ; (no need to repeat get-char at L29E0)\n\n; if neither, then an expression is required so rejoin runtime loop ??\n; registers HL and DE only point to somewhere meaningful in runtime so\n; comments apply to that situation.\n\n;; SV-MULT\nL29FB:  PUSH    BC              ; save dimension number.\n        PUSH    HL              ; push data pointer/rubbish.\n                                ; DE points to current dimension.\n        CALL    L2AEE           ; routine DE,(DE+1) gets next dimension in DE\n                                ; and HL points to it.\n        EX      (SP),HL         ; dim pointer to stack, data pointer to HL (*)\n        EX      DE,HL           ; data pointer to DE, dim size to HL.\n\n        CALL    L2ACC           ; routine INT-EXP1 checks integer expression\n                                ; and gets result in BC in runtime.\n        JR      C,L2A20         ; to REPORT-3 if > HL\n                                ; 'Subscript out of range'\n\n        DEC     BC              ; adjust returned result from 1-x to 0-x\n        CALL    L2AF4           ; routine GET-HL*DE multiplies data pointer by\n                                ; dimension size.\n        ADD     HL,BC           ; add the integer returned by expression.\n        POP     DE              ; pop the dimension pointer.                              ***\n        POP     BC              ; pop dimension counter.\n        DJNZ    L29C3           ; back to SV-COMMA if more dimensions\n                                ; Note. during syntax checking, unless there\n                                ; are more than 256 subscripts, the branch\n                                ; back to SV-COMMA is always taken.\n\n        BIT     7,C             ; are we checking syntax ?\n                                ; then we've got a joker here.\n\n;; SV-RPT-C\nL2A12:  JR      NZ,L2A7A        ; forward to SL-RPT-C if so\n                                ; 'Nonsense in BASIC'\n                                ; more than 256 subscripts in BASIC line.\n\n; but in runtime the number of subscripts are at least the same as dims\n\n        PUSH    HL              ; save data pointer.\n        BIT     6,C             ; is it a string array ?\n        JR      NZ,L2A2C        ; forward to SV-ELEM$ if so.\n\n; a runtime numeric array subscript.\n\n        LD      B,D             ; register DE has advanced past all dimensions\n        LD      C,E             ; and points to start of data in variable.\n                                ; transfer it to BC.\n\n        RST     18H             ; GET-CHAR checks BASIC line\n        CP      $29             ; must be a ')' ?\n        JR      Z,L2A22         ; skip to SV-NUMBER if so\n\n; else more subscripts in BASIC line than the variable definition.\n\n;; REPORT-3\nL2A20:  RST     08H             ; ERROR-1\n        DEFB    $02             ; Error Report: Subscript wrong\n\n; continue if subscripts matched the numeric array.\n\n;; SV-NUMBER\nL2A22:  RST     20H             ; NEXT-CHAR moves CH_ADD to next statement\n                                ; - finished parsing.\n\n        POP     HL              ; pop the data pointer.\n        LD      DE,$0005        ; each numeric element is 5 bytes.\n        CALL    L2AF4           ; routine GET-HL*DE multiplies.\n        ADD     HL,BC           ; now add to start of data in the variable.\n\n        RET                     ; return with HL pointing at the numeric\n                                ; array subscript.                       ->\n\n; ---------------------------------------------------------------\n\n; the branch was here for string subscripts when the number of subscripts\n; in the BASIC line was one less than in variable definition.\n\n;; SV-ELEM$\nL2A2C:  CALL    L2AEE           ; routine DE,(DE+1) gets final dimension\n                                ; the length of strings in this array.\n        EX      (SP),HL         ; start pointer to stack, data pointer to HL.\n        CALL    L2AF4           ; routine GET-HL*DE multiplies by element\n                                ; size.\n        POP     BC              ; the start of data pointer is added\n        ADD     HL,BC           ; in - now points to location before.\n        INC     HL              ; point to start of required string.\n        LD      B,D             ; transfer the length (final dimension size)\n        LD      C,E             ; from DE to BC.\n        EX      DE,HL           ; put start in DE.\n        CALL    L2AB1           ; routine STK-ST-0 stores the string parameters\n                                ; with A=0 - a slice or subscript.\n\n; now check that there were no more subscripts in the BASIC line.\n\n        RST     18H             ; GET-CHAR\n        CP      $29             ; is it ')' ?\n        JR      Z,L2A48         ; forward to SV-DIM to consider a separate\n                                ; subscript or/and a slice.\n\n        CP      $2C             ; a comma is allowed if the final subscript\n                                ; is to be sliced e.g. a$(2,3,4 TO 6).\n        JR      NZ,L2A20        ; to REPORT-3 with anything else\n                                ; 'Subscript error'\n\n;; SV-SLICE\nL2A45:  CALL    L2A52           ; routine SLICING slices the string.\n\n; but a slice of a simple string can itself be sliced.\n\n;; SV-DIM\nL2A48:  RST     20H             ; NEXT-CHAR\n\n;; SV-SLICE?\nL2A49:  CP      $28             ; is character '(' ?\n        JR      Z,L2A45         ; loop back if so to SV-SLICE\n\n        RES     6,(IY+$01)      ; update FLAGS  - Signal string result\n        RET                     ; and return.\n\n; ---\n\n; The above section deals with the flexible syntax allowed.\n; DIM a$(3,3,10) can be considered as two dimensional array of ten-character\n; strings or a 3-dimensional array of characters.\n; a$(1,1) will return a 10-character string as will a$(1,1,1 TO 10)\n; a$(1,1,1) will return a single character.\n; a$(1,1) (1 TO 6) is the same as a$(1,1,1 TO 6)\n; A slice can itself be sliced ad infinitum\n; b$ () () () () () () (2 TO 10) (2 TO 9) (3) is the same as b$(5)\n\n\n\n; -------------------------\n; Handle slicing of strings\n; -------------------------\n; The syntax of string slicing is very natural and it is as well to reflect\n; on the permutations possible.\n; a$() and a$( TO ) indicate the entire string although just a$ would do\n; and would avoid coming here.\n; h$(16) indicates the single character at position 16.\n; a$( TO 32) indicates the first 32 characters.\n; a$(257 TO) indicates all except the first 256 characters.\n; a$(19000 TO 19999) indicates the thousand characters at position 19000.\n; Also a$(9 TO 5) returns a null string not an error.\n; This enables a$(2 TO) to return a null string if the passed string is\n; of length zero or 1.\n; A string expression in brackets can be sliced. e.g. (STR$ PI) (3 TO )\n; We arrived here from SCANNING with CH-ADD pointing to the initial '('\n; or from above.\n\n;; SLICING\nL2A52:  CALL    L2530           ; routine SYNTAX-Z\n        CALL    NZ,L2BF1        ; routine STK-FETCH fetches parameters of\n                                ; string at runtime, start in DE, length\n                                ; in BC. This could be an array subscript.\n\n        RST     20H             ; NEXT-CHAR\n        CP      $29             ; is it ')' ?     e.g. a$()\n        JR      Z,L2AAD         ; forward to SL-STORE to store entire string.\n\n        PUSH    DE              ; else save start address of string\n\n        XOR     A               ; clear accumulator to use as a running flag.\n        PUSH    AF              ; and save on stack before any branching.\n\n        PUSH    BC              ; save length of string to be sliced.\n        LD      DE,$0001        ; default the start point to position 1.\n\n        RST     18H             ; GET-CHAR\n\n        POP     HL              ; pop length to HL as default end point\n                                ; and limit.\n\n        CP      $CC             ; is it 'TO' ?    e.g. a$( TO 10000)\n        JR      Z,L2A81         ; to SL-SECOND to evaluate second parameter.\n\n        POP     AF              ; pop the running flag.\n\n        CALL    L2ACD           ; routine INT-EXP2 fetches first parameter.\n\n        PUSH    AF              ; save flag (will be $FF if parameter>limit)\n\n        LD      D,B             ; transfer the start\n        LD      E,C             ; to DE overwriting 0001.\n        PUSH    HL              ; save original length.\n\n        RST     18H             ; GET-CHAR\n        POP     HL              ; pop the limit length.\n        CP      $CC             ; is it 'TO' after a start ?\n        JR      Z,L2A81         ; to SL-SECOND to evaluate second parameter\n\n        CP      $29             ; is it ')' ?       e.g. a$(365)\n\n;; SL-RPT-C\nL2A7A:  JP      NZ,L1C8A        ; jump to REPORT-C with anything else\n                                ; 'Nonsense in BASIC'\n\n        LD      H,D             ; copy start\n        LD      L,E             ; to end - just a one character slice.\n        JR      L2A94           ; forward to SL-DEFINE.\n\n; ---------------------\n\n;; SL-SECOND\nL2A81:  PUSH    HL              ; save limit length.\n\n        RST     20H             ; NEXT-CHAR\n\n        POP     HL              ; pop the length.\n\n        CP      $29             ; is character ')' ?        e.g. a$(7 TO )\n        JR      Z,L2A94         ; to SL-DEFINE using length as end point.\n\n        POP     AF              ; else restore flag.\n        CALL    L2ACD           ; routine INT-EXP2 gets second expression.\n\n        PUSH    AF              ; save the running flag.\n\n        RST     18H             ; GET-CHAR\n\n        LD      H,B             ; transfer second parameter\n        LD      L,C             ; to HL.              e.g. a$(42 to 99)\n        CP      $29             ; is character a ')' ?\n        JR      NZ,L2A7A        ; to SL-RPT-C if not\n                                ; 'Nonsense in BASIC'\n\n; we now have start in DE and an end in HL.\n\n;; SL-DEFINE\nL2A94:  POP     AF              ; pop the running flag.\n        EX      (SP),HL         ; put end point on stack, start address to HL\n        ADD     HL,DE           ; add address of string to the start point.\n        DEC     HL              ; point to first character of slice.\n        EX      (SP),HL         ; start address to stack, end point to HL (*)\n        AND     A               ; prepare to subtract.\n        SBC     HL,DE           ; subtract start point from end point.\n        LD      BC,$0000        ; default the length result to zero.\n        JR      C,L2AA8         ; forward to SL-OVER if start > end.\n\n        INC     HL              ; increment the length for inclusive byte.\n\n        AND     A               ; now test the running flag.\n        JP      M,L2A20         ; jump back to REPORT-3 if $FF.\n                                ; 'Subscript out of range'\n\n        LD      B,H             ; transfer the length\n        LD      C,L             ; to BC.\n\n;; SL-OVER\nL2AA8:  POP     DE              ; restore start address from machine stack ***\n        RES     6,(IY+$01)      ; update FLAGS - signal string result for\n                                ; syntax.\n\n;; SL-STORE\nL2AAD:  CALL    L2530           ; routine SYNTAX-Z  (UNSTACK-Z?)\n        RET     Z               ; return if checking syntax.\n                                ; but continue to store the string in runtime.\n\n; ------------------------------------\n; other than from above, this routine is called from STK-VAR to stack\n; a known string array element.\n; ------------------------------------\n\n;; STK-ST-0\nL2AB1:  XOR     A               ; clear to signal a sliced string or element.\n\n; -------------------------\n; this routine is called from chr$, scrn$ etc. to store a simple string result.\n; --------------------------\n\n;; STK-STO-$\nL2AB2:  RES     6,(IY+$01)      ; update FLAGS - signal string result.\n                                ; and continue to store parameters of string.\n\n; ---------------------------------------\n; Pass five registers to calculator stack\n; ---------------------------------------\n; This subroutine puts five registers on the calculator stack.\n\n;; STK-STORE\nL2AB6:  PUSH    BC              ; save two registers\n        CALL    L33A9           ; routine TEST-5-SP checks room and puts 5\n                                ; in BC.\n        POP     BC              ; fetch the saved registers.\n        LD      HL,($5C65)      ; make HL point to first empty location STKEND\n        LD      (HL),A          ; place the 5 registers.\n        INC     HL              ;\n        LD      (HL),E          ;\n        INC     HL              ;\n        LD      (HL),D          ;\n        INC     HL              ;\n        LD      (HL),C          ;\n        INC     HL              ;\n        LD      (HL),B          ;\n        INC     HL              ;\n        LD      ($5C65),HL      ; update system variable STKEND.\n        RET                     ; and return.\n\n; -------------------------------------------\n; Return result of evaluating next expression\n; -------------------------------------------\n; This clever routine is used to check and evaluate an integer expression\n; which is returned in BC, setting A to $FF, if greater than a limit supplied\n; in HL. It is used to check array subscripts, parameters of a string slice\n; and the arguments of the DIM command. In the latter case, the limit check\n; is not required and H is set to $FF. When checking optional string slice\n; parameters, it is entered at the second entry point so as not to disturb\n; the running flag A, which may be $00 or $FF from a previous invocation.\n\n;; INT-EXP1\nL2ACC:  XOR     A               ; set result flag to zero.\n\n; -> The entry point is here if A is used as a running flag.\n\n;; INT-EXP2\nL2ACD:  PUSH    DE              ; preserve DE register throughout.\n        PUSH    HL              ; save the supplied limit.\n        PUSH    AF              ; save the flag.\n\n        CALL    L1C82           ; routine EXPT-1NUM evaluates expression\n                                ; at CH_ADD returning if numeric result,\n                                ; with value on calculator stack.\n\n        POP     AF              ; pop the flag.\n        CALL    L2530           ; routine SYNTAX-Z\n        JR      Z,L2AEB         ; forward to I-RESTORE if checking syntax so\n                                ; avoiding a comparison with supplied limit.\n\n        PUSH    AF              ; save the flag.\n\n        CALL    L1E99           ; routine FIND-INT2 fetches value from\n                                ; calculator stack to BC producing an error\n                                ; if too high.\n\n        POP     DE              ; pop the flag to D.\n        LD      A,B             ; test value for zero and reject\n        OR      C               ; as arrays and strings begin at 1.\n        SCF                     ; set carry flag.\n        JR      Z,L2AE8         ; forward to I-CARRY if zero.\n\n        POP     HL              ; restore the limit.\n        PUSH    HL              ; and save.\n        AND     A               ; prepare to subtract.\n        SBC     HL,BC           ; subtract value from limit.\n\n;; I-CARRY\nL2AE8:  LD      A,D             ; move flag to accumulator $00 or $FF.\n        SBC     A,$00           ; will set to $FF if carry set.\n\n;; I-RESTORE\nL2AEB:  POP     HL              ; restore the limit.\n        POP     DE              ; and DE register.\n        RET                     ; return.\n\n\n; -----------------------\n; LD DE,(DE+1) Subroutine\n; -----------------------\n; This routine just loads the DE register with the contents of the two\n; locations following the location addressed by DE.\n; It is used to step along the 16-bit dimension sizes in array definitions.\n; Note. Such code is made into subroutines to make programs easier to\n; write and it would use less space to include the five instructions in-line.\n; However, there are so many exchanges going on at the places this is invoked\n; that to implement it in-line would make the code hard to follow.\n; It probably had a zippier label though as the intention is to simplify the\n; program.\n\n;; DE,(DE+1)\nL2AEE:  EX      DE,HL           ;\n        INC     HL              ;\n        LD      E,(HL)          ;\n        INC     HL              ;\n        LD      D,(HL)          ;\n        RET                     ;\n\n; -------------------\n; HL=HL*DE Subroutine\n; -------------------\n; This routine calls the mathematical routine to multiply HL by DE in runtime.\n; It is called from STK-VAR and from DIM. In the latter case syntax is not\n; being checked so the entry point could have been at the second CALL\n; instruction to save a few clock-cycles.\n\n;; GET-HL*DE\nL2AF4:  CALL    L2530           ; routine SYNTAX-Z.\n        RET     Z               ; return if checking syntax.\n\n        CALL    L30A9           ; routine HL-HL*DE.\n        JP      C,L1F15         ; jump back to REPORT-4 if over 65535.\n\n        RET                     ; else return with 16-bit result in HL.\n\n; -----------------\n; THE 'LET' COMMAND\n; -----------------\n; Sinclair BASIC adheres to the ANSI-78 standard and a LET is required in\n; assignments e.g. LET a = 1  :   LET h$ = \"hat\".\n;\n; Long names may contain spaces but not colour controls (when assigned).\n; a substring can appear to the left of the equals sign.\n\n; An earlier mathematician Lewis Carroll may have been pleased that\n; 10 LET Babies cannot manage crocodiles = Babies are illogical AND\n;    Nobody is despised who can manage a crocodile AND Illogical persons\n;    are despised\n; does not give the 'Nonsense..' error if the three variables exist.\n; I digress.\n\n;; LET\nL2AFF:  LD      HL,($5C4D)      ; fetch system variable DEST to HL.\n        BIT     1,(IY+$37)      ; test FLAGX - handling a new variable ?\n        JR      Z,L2B66         ; forward to L-EXISTS if not.\n\n; continue for a new variable. DEST points to start in BASIC line.\n; from the CLASS routines.\n\n        LD      BC,$0005        ; assume numeric and assign an initial 5 bytes\n\n;; L-EACH-CH\nL2B0B:  INC     BC              ; increase byte count for each relevant\n                                ; character\n\n;; L-NO-SP\nL2B0C:  INC     HL              ; increase pointer.\n        LD      A,(HL)          ; fetch character.\n        CP      $20             ; is it a space ?\n        JR      Z,L2B0C         ; back to L-NO-SP is so.\n\n        JR      NC,L2B1F        ; forward to L-TEST-CH if higher.\n\n        CP      $10             ; is it $00 - $0F ?\n        JR      C,L2B29         ; forward to L-SPACES if so.\n\n        CP      $16             ; is it $16 - $1F ?\n        JR      NC,L2B29        ; forward to L-SPACES if so.\n\n; it was $10 - $15  so step over a colour code.\n\n        INC     HL              ; increase pointer.\n        JR      L2B0C           ; loop back to L-NO-SP.\n\n; ---\n\n; the branch was to here if higher than space.\n\n;; L-TEST-CH\nL2B1F:  CALL    L2C88           ; routine ALPHANUM sets carry if alphanumeric\n        JR      C,L2B0B         ; loop back to L-EACH-CH for more if so.\n\n        CP      $24             ; is it '$' ?\n        JP      Z,L2BC0         ; jump forward if so, to L-NEW$\n                                ; with a new string.\n\n;; L-SPACES\nL2B29:  LD      A,C             ; save length lo in A.\n        LD      HL,($5C59)      ; fetch E_LINE to HL.\n        DEC     HL              ; point to location before, the variables\n                                ; end-marker.\n        CALL    L1655           ; routine MAKE-ROOM creates BC spaces\n                                ; for name and numeric value.\n        INC     HL              ; advance to first new location.\n        INC     HL              ; then to second.\n        EX      DE,HL           ; set DE to second location.\n        PUSH    DE              ; save this pointer.\n        LD      HL,($5C4D)      ; reload HL with DEST.\n        DEC     DE              ; point to first.\n        SUB     $06             ; subtract six from length_lo.\n        LD      B,A             ; save count in B.\n        JR      Z,L2B4F         ; forward to L-SINGLE if it was just\n                                ; one character.\n\n; HL points to start of variable name after 'LET' in BASIC line.\n\n;; L-CHAR\nL2B3E:  INC     HL              ; increase pointer.\n        LD      A,(HL)          ; pick up character.\n        CP      $21             ; is it space or higher ?\n        JR      C,L2B3E         ; back to L-CHAR with space and less.\n\n        OR      $20             ; make variable lower-case.\n        INC     DE              ; increase destination pointer.\n        LD      (DE),A          ; and load to edit line.\n        DJNZ    L2B3E           ; loop back to L-CHAR until B is zero.\n\n        OR      $80             ; invert the last character.\n        LD      (DE),A          ; and overwrite that in edit line.\n\n; now consider first character which has bit 6 set\n\n        LD      A,$C0           ; set A 11000000 is xor mask for a long name.\n                                ; %101      is xor/or  result\n\n; single character numerics rejoin here with %00000000 in mask.\n;                                            %011      will be xor/or result\n\n;; L-SINGLE\nL2B4F:  LD      HL,($5C4D)      ; fetch DEST - HL addresses first character.\n        XOR     (HL)            ; apply variable type indicator mask (above).\n        OR      $20             ; make lowercase - set bit 5.\n        POP     HL              ; restore pointer to 2nd character.\n        CALL    L2BEA           ; routine L-FIRST puts A in first character.\n                                ; and returns with HL holding\n                                ; new E_LINE-1  the $80 vars end-marker.\n\n;; L-NUMERIC\nL2B59:  PUSH    HL              ; save the pointer.\n\n; the value of variable is deleted but remains after calculator stack.\n\n        RST     28H             ;; FP-CALC\n        DEFB    $02             ;;delete      ; delete variable value\n        DEFB    $38             ;;end-calc\n\n; DE (STKEND) points to start of value.\n\n        POP     HL              ; restore the pointer.\n        LD      BC,$0005        ; start of number is five bytes before.\n        AND     A               ; prepare for true subtraction.\n        SBC     HL,BC           ; HL points to start of value.\n        JR      L2BA6           ; forward to L-ENTER  ==>\n\n; ---\n\n\n; the jump was to here if the variable already existed.\n\n;; L-EXISTS\nL2B66:  BIT     6,(IY+$01)      ; test FLAGS - numeric or string result ?\n        JR      Z,L2B72         ; skip forward to L-DELETE$   -*->\n                                ; if string result.\n\n; A numeric variable could be simple or an array element.\n; They are treated the same and the old value is overwritten.\n\n        LD      DE,$0006        ; six bytes forward points to loc past value.\n        ADD     HL,DE           ; add to start of number.\n        JR      L2B59           ; back to L-NUMERIC to overwrite value.\n\n; ---\n\n; -*-> the branch was here if a string existed.\n\n;; L-DELETE$\nL2B72:  LD      HL,($5C4D)      ; fetch DEST to HL.\n                                ; (still set from first instruction)\n        LD      BC,($5C72)      ; fetch STRLEN to BC.\n        BIT     0,(IY+$37)      ; test FLAGX - handling a complete simple\n                                ; string ?\n        JR      NZ,L2BAF        ; forward to L-ADD$ if so.\n\n; must be a string array or a slice in workspace.\n; Note. LET a$(3 TO 6) = h$   will assign \"hat \" if h$ = \"hat\"\n;                                  and    \"hats\" if h$ = \"hatstand\".\n;\n; This is known as Procrustean lengthening and shortening after a\n; character Procrustes in Greek legend who made travellers sleep in his bed,\n; cutting off their feet or stretching them so they fitted the bed perfectly.\n; The bloke was hatstand and slain by Theseus.\n\n        LD      A,B             ; test if length\n        OR      C               ; is zero and\n        RET     Z               ; return if so.\n\n        PUSH    HL              ; save pointer to start.\n\n        RST     30H             ; BC-SPACES creates room.\n        PUSH    DE              ; save pointer to first new location.\n        PUSH    BC              ; and length            (*)\n        LD      D,H             ; set DE to point to last location.\n        LD      E,L             ;\n        INC     HL              ; set HL to next location.\n        LD      (HL),$20        ; place a space there.\n        LDDR                    ; copy bytes filling with spaces.\n\n        PUSH    HL              ; save pointer to start.\n        CALL    L2BF1           ; routine STK-FETCH start to DE,\n                                ; length to BC.\n        POP     HL              ; restore the pointer.\n        EX      (SP),HL         ; (*) length to HL, pointer to stack.\n        AND     A               ; prepare for true subtraction.\n        SBC     HL,BC           ; subtract old length from new.\n        ADD     HL,BC           ; and add back.\n        JR      NC,L2B9B        ; forward if it fits to L-LENGTH.\n\n        LD      B,H             ; otherwise set\n        LD      C,L             ; length to old length.\n                                ; \"hatstand\" becomes \"hats\"\n\n;; L-LENGTH\nL2B9B:  EX      (SP),HL         ; (*) length to stack, pointer to HL.\n        EX      DE,HL           ; pointer to DE, start of string to HL.\n        LD      A,B             ; is the length zero ?\n        OR      C               ;\n        JR      Z,L2BA3         ; forward to L-IN-W/S if so\n                                ; leaving prepared spaces.\n\n        LDIR                    ; else copy bytes overwriting some spaces.\n\n;; L-IN-W/S\nL2BA3:  POP     BC              ; pop the new length.  (*)\n        POP     DE              ; pop pointer to new area.\n        POP     HL              ; pop pointer to variable in assignment.\n                                ; and continue copying from workspace\n                                ; to variables area.\n\n; ==> branch here from  L-NUMERIC\n\n;; L-ENTER\nL2BA6:  EX      DE,HL           ; exchange pointers HL=STKEND DE=end of vars.\n        LD      A,B             ; test the length\n        OR      C               ; and make a\n        RET     Z               ; return if zero (strings only).\n\n        PUSH    DE              ; save start of destination.\n        LDIR                    ; copy bytes.\n        POP     HL              ; address the start.\n        RET                     ; and return.\n\n; ---\n\n; the branch was here from L-DELETE$ if an existing simple string.\n; register HL addresses start of string in variables area.\n\n;; L-ADD$\nL2BAF:  DEC     HL              ; point to high byte of length.\n        DEC     HL              ; to low byte.\n        DEC     HL              ; to letter.\n        LD      A,(HL)          ; fetch masked letter to A.\n        PUSH    HL              ; save the pointer on stack.\n        PUSH    BC              ; save new length.\n        CALL    L2BC6           ; routine L-STRING adds new string at end\n                                ; of variables area.\n                                ; if no room we still have old one.\n        POP     BC              ; restore length.\n        POP     HL              ; restore start.\n        INC     BC              ; increase\n        INC     BC              ; length by three\n        INC     BC              ; to include character and length bytes.\n        JP      L19E8           ; jump to indirect exit via RECLAIM-2\n                                ; deleting old version and adjusting pointers.\n\n; ---\n\n; the jump was here with a new string variable.\n\n;; L-NEW$\nL2BC0:  LD      A,$DF           ; indicator mask %11011111 for\n                                ;                %010xxxxx will be result\n        LD      HL,($5C4D)      ; address DEST first character.\n        AND     (HL)            ; combine mask with character.\n\n;; L-STRING\nL2BC6:  PUSH    AF              ; save first character and mask.\n        CALL    L2BF1           ; routine STK-FETCH fetches parameters of\n                                ; the string.\n        EX      DE,HL           ; transfer start to HL.\n        ADD     HL,BC           ; add to length.\n        PUSH    BC              ; save the length.\n        DEC     HL              ; point to end of string.\n        LD      ($5C4D),HL      ; save pointer in DEST.\n                                ; (updated by POINTERS if in workspace)\n        INC     BC              ; extra byte for letter.\n        INC     BC              ; two bytes\n        INC     BC              ; for the length of string.\n        LD      HL,($5C59)      ; address E_LINE.\n        DEC     HL              ; now end of VARS area.\n        CALL    L1655           ; routine MAKE-ROOM makes room for string.\n                                ; updating pointers including DEST.\n        LD      HL,($5C4D)      ; pick up pointer to end of string from DEST.\n        POP     BC              ; restore length from stack.\n        PUSH    BC              ; and save again on stack.\n        INC     BC              ; add a byte.\n        LDDR                    ; copy bytes from end to start.\n        EX      DE,HL           ; HL addresses length low\n        INC     HL              ; increase to address high byte\n        POP     BC              ; restore length to BC\n        LD      (HL),B          ; insert high byte\n        DEC     HL              ; address low byte location\n        LD      (HL),C          ; insert that byte\n        POP     AF              ; restore character and mask\n\n;; L-FIRST\nL2BEA:  DEC     HL              ; address variable name\n        LD      (HL),A          ; and insert character.\n        LD      HL,($5C59)      ; load HL with E_LINE.\n        DEC     HL              ; now end of VARS area.\n        RET                     ; return\n\n; ------------------------------------\n; Get last value from calculator stack\n; ------------------------------------\n;\n;\n\n;; STK-FETCH\nL2BF1:  LD      HL,($5C65)      ; STKEND\n        DEC     HL              ;\n        LD      B,(HL)          ;\n        DEC     HL              ;\n        LD      C,(HL)          ;\n        DEC     HL              ;\n        LD      D,(HL)          ;\n        DEC     HL              ;\n        LD      E,(HL)          ;\n        DEC     HL              ;\n        LD      A,(HL)          ;\n        LD      ($5C65),HL      ; STKEND\n        RET                     ;\n\n; ------------------\n; Handle DIM command\n; ------------------\n; e.g. DIM a(2,3,4,7): DIM a$(32) : DIM b$(20,2,768) : DIM c$(20000)\n; the only limit to dimensions is memory so, for example,\n; DIM a(2,2,2,2,2,2,2,2,2,2,2,2,2) is possible and creates a multi-\n; dimensional array of zeros. String arrays are initialized to spaces.\n; It is not possible to erase an array, but it can be re-dimensioned to\n; a minimal size of 1, after use, to free up memory.\n\n;; DIM\nL2C02:  CALL    L28B2           ; routine LOOK-VARS\n\n;; D-RPORT-C\nL2C05:  JP      NZ,L1C8A        ; jump to REPORT-C if a long-name variable.\n                                ; DIM lottery numbers(49) doesn't work.\n\n        CALL    L2530           ; routine SYNTAX-Z\n        JR      NZ,L2C15        ; forward to D-RUN in runtime.\n\n        RES     6,C             ; signal 'numeric' array even if string as\n                                ; this simplifies the syntax checking.\n\n        CALL    L2996           ; routine STK-VAR checks syntax.\n        CALL    L1BEE           ; routine CHECK-END performs early exit ->\n\n; the branch was here in runtime.\n\n;; D-RUN\nL2C15:  JR      C,L2C1F         ; skip to D-LETTER if variable did not exist.\n                                ; else reclaim the old one.\n\n        PUSH    BC              ; save type in C.\n        CALL    L19B8           ; routine NEXT-ONE find following variable\n                                ; or position of $80 end-marker.\n        CALL    L19E8           ; routine RECLAIM-2 reclaims the\n                                ; space between.\n        POP     BC              ; pop the type.\n\n;; D-LETTER\nL2C1F:  SET     7,C             ; signal array.\n        LD      B,$00           ; initialize dimensions to zero and\n        PUSH    BC              ; save with the type.\n        LD      HL,$0001        ; make elements one character presuming string\n        BIT     6,C             ; is it a string ?\n        JR      NZ,L2C2D        ; forward to D-SIZE if so.\n\n        LD      L,$05           ; make elements 5 bytes as is numeric.\n\n;; D-SIZE\nL2C2D:  EX      DE,HL           ; save the element size in DE.\n\n; now enter a loop to parse each of the integers in the list.\n\n;; D-NO-LOOP\nL2C2E:  RST     20H             ; NEXT-CHAR\n        LD      H,$FF           ; disable limit check by setting HL high\n        CALL    L2ACC           ; routine INT-EXP1\n        JP      C,L2A20         ; to REPORT-3 if > 65280 and then some\n                                ; 'Subscript out of range'\n\n        POP     HL              ; pop dimension counter, array type\n        PUSH    BC              ; save dimension size                     ***\n        INC     H               ; increment the dimension counter\n        PUSH    HL              ; save the dimension counter\n        LD      H,B             ; transfer size\n        LD      L,C             ; to HL\n        CALL    L2AF4           ; routine GET-HL*DE multiplies dimension by\n                                ; running total of size required initially\n                                ; 1 or 5.\n        EX      DE,HL           ; save running total in DE\n\n        RST     18H             ; GET-CHAR\n        CP      $2C             ; is it ',' ?\n        JR      Z,L2C2E         ; loop back to D-NO-LOOP until all dimensions\n                                ; have been considered\n\n; when loop complete continue.\n\n        CP      $29             ; is it ')' ?\n        JR      NZ,L2C05        ; to D-RPORT-C with anything else\n                                ; 'Nonsense in BASIC'\n\n\n        RST     20H             ; NEXT-CHAR advances to next statement/CR\n\n        POP     BC              ; pop dimension counter/type\n        LD      A,C             ; type to A\n\n; now calculate space required for array variable\n\n        LD      L,B             ; dimensions to L since these require 16 bits\n                                ; then this value will be doubled\n        LD      H,$00           ; set high byte to zero\n\n; another four bytes are required for letter(1), total length(2), number of\n; dimensions(1) but since we have yet to double allow for two\n\n        INC     HL              ; increment\n        INC     HL              ; increment\n\n        ADD     HL,HL           ; now double giving 4 + dimensions * 2\n\n        ADD     HL,DE           ; add to space required for array contents\n\n        JP      C,L1F15         ; to REPORT-4 if > 65535\n                                ; 'Out of memory'\n\n        PUSH    DE              ; save data space\n        PUSH    BC              ; save dimensions/type\n        PUSH    HL              ; save total space\n        LD      B,H             ; total space\n        LD      C,L             ; to BC\n        LD      HL,($5C59)      ; address E_LINE - first location after\n                                ; variables area\n        DEC     HL              ; point to location before - the $80 end-marker\n        CALL    L1655           ; routine MAKE-ROOM creates the space if\n                                ; memory is available.\n\n        INC     HL              ; point to first new location and\n        LD      (HL),A          ; store letter/type\n\n        POP     BC              ; pop total space\n        DEC     BC              ; exclude name\n        DEC     BC              ; exclude the 16-bit\n        DEC     BC              ; counter itself\n        INC     HL              ; point to next location the 16-bit counter\n        LD      (HL),C          ; insert low byte\n        INC     HL              ; address next\n        LD      (HL),B          ; insert high byte\n\n        POP     BC              ; pop the number of dimensions.\n        LD      A,B             ; dimensions to A\n        INC     HL              ; address next\n        LD      (HL),A          ; and insert \"No. of dims\"\n\n        LD      H,D             ; transfer DE space + 1 from make-room\n        LD      L,E             ; to HL\n        DEC     DE              ; set DE to next location down.\n        LD      (HL),$00        ; presume numeric and insert a zero\n        BIT     6,C             ; test bit 6 of C. numeric or string ?\n        JR      Z,L2C7C         ; skip to DIM-CLEAR if numeric\n\n        LD      (HL),$20        ; place a space character in HL\n\n;; DIM-CLEAR\nL2C7C:  POP     BC              ; pop the data length\n\n        LDDR                    ; LDDR sets to zeros or spaces\n\n; The number of dimensions is still in A.\n; A loop is now entered to insert the size of each dimension that was pushed\n; during the D-NO-LOOP working downwards from position before start of data.\n\n;; DIM-SIZES\nL2C7F:  POP     BC              ; pop a dimension size                    ***\n        LD      (HL),B          ; insert high byte at position\n        DEC     HL              ; next location down\n        LD      (HL),C          ; insert low byte\n        DEC     HL              ; next location down\n        DEC     A               ; decrement dimension counter\n        JR      NZ,L2C7F        ; back to DIM-SIZES until all done.\n\n        RET                     ; return.\n\n; -----------------------------\n; Check whether digit or letter\n; -----------------------------\n; This routine checks that the character in A is alphanumeric\n; returning with carry set if so.\n\n;; ALPHANUM\nL2C88:  CALL    L2D1B           ; routine NUMERIC will reset carry if so.\n        CCF                     ; Complement Carry Flag\n        RET     C               ; Return if numeric else continue into\n                                ; next routine.\n\n; This routine checks that the character in A is alphabetic\n\n;; ALPHA\nL2C8D:  CP      $41             ; less than 'A' ?\n        CCF                     ; Complement Carry Flag\n        RET     NC              ; return if so\n\n        CP      $5B             ; less than 'Z'+1 ?\n        RET     C               ; is within first range\n\n        CP      $61             ; less than 'a' ?\n        CCF                     ; Complement Carry Flag\n        RET     NC              ; return if so.\n\n        CP      $7B             ; less than 'z'+1 ?\n        RET                     ; carry set if within a-z.\n\n; -------------------------\n; Decimal to floating point\n; -------------------------\n; This routine finds the floating point number represented by an expression\n; beginning with BIN, '.' or a digit.\n; Note that BIN need not have any '0's or '1's after it.\n; BIN is really just a notational symbol and not a function.\n\n;; DEC-TO-FP\nL2C9B:  CP      $C4             ; 'BIN' token ?\n        JR      NZ,L2CB8        ; to NOT-BIN if not\n\n        LD      DE,$0000        ; initialize 16 bit buffer register.\n\n;; BIN-DIGIT\nL2CA2:  RST     20H             ; NEXT-CHAR\n        SUB     $31             ; '1'\n        ADC     A,$00           ; will be zero if '1' or '0'\n                                ; carry will be set if was '0'\n        JR      NZ,L2CB3        ; forward to BIN-END if result not zero\n\n        EX      DE,HL           ; buffer to HL\n        CCF                     ; Carry now set if originally '1'\n        ADC     HL,HL           ; shift the carry into HL\n        JP      C,L31AD         ; to REPORT-6 if overflow - too many digits\n                                ; after first '1'. There can be an unlimited\n                                ; number of leading zeros.\n                                ; 'Number too big' - raise an error\n\n        EX      DE,HL           ; save the buffer\n        JR      L2CA2           ; back to BIN-DIGIT for more digits\n\n; ---\n\n;; BIN-END\nL2CB3:  LD      B,D             ; transfer 16 bit buffer\n        LD      C,E             ; to BC register pair.\n        JP      L2D2B           ; JUMP to STACK-BC to put on calculator stack\n\n; ---\n\n; continue here with .1,  42, 3.14, 5., 2.3 E -4\n\n;; NOT-BIN\nL2CB8:  CP      $2E             ; '.' - leading decimal point ?\n        JR      Z,L2CCB         ; skip to DECIMAL if so.\n\n        CALL    L2D3B           ; routine INT-TO-FP to evaluate all digits\n                                ; This number 'x' is placed on stack.\n        CP      $2E             ; '.' - mid decimal point ?\n\n        JR      NZ,L2CEB        ; to E-FORMAT if not to consider that format\n\n        RST     20H             ; NEXT-CHAR\n        CALL    L2D1B           ; routine NUMERIC returns carry reset if 0-9\n\n        JR      C,L2CEB         ; to E-FORMAT if not a digit e.g. '1.'\n\n        JR      L2CD5           ; to DEC-STO-1 to add the decimal part to 'x'\n\n; ---\n\n; a leading decimal point has been found in a number.\n\n;; DECIMAL\nL2CCB:  RST     20H             ; NEXT-CHAR\n        CALL    L2D1B           ; routine NUMERIC will reset carry if digit\n\n;; DEC-RPT-C\nL2CCF:  JP      C,L1C8A         ; to REPORT-C if just a '.'\n                                ; raise 'Nonsense in BASIC'\n\n; since there is no leading zero put one on the calculator stack.\n\n        RST     28H             ;; FP-CALC\n        DEFB    $A0             ;;stk-zero  ; 0.\n        DEFB    $38             ;;end-calc\n\n; If rejoining from earlier there will be a value 'x' on stack.\n; If continuing from above the value zero.\n; Now store 1 in mem-0.\n; Note. At each pass of the digit loop this will be divided by ten.\n\n;; DEC-STO-1\nL2CD5:  RST     28H             ;; FP-CALC\n        DEFB    $A1             ;;stk-one   ;x or 0,1.\n        DEFB    $C0             ;;st-mem-0  ;x or 0,1.\n        DEFB    $02             ;;delete    ;x or 0.\n        DEFB    $38             ;;end-calc\n\n\n;; NXT-DGT-1\nL2CDA:  RST     18H             ; GET-CHAR\n        CALL    L2D22           ; routine STK-DIGIT stacks single digit 'd'\n        JR      C,L2CEB         ; exit to E-FORMAT when digits exhausted  >\n\n\n        RST     28H             ;; FP-CALC   ;x or 0,d.           first pass.\n        DEFB    $E0             ;;get-mem-0  ;x or 0,d,1.\n        DEFB    $A4             ;;stk-ten    ;x or 0,d,1,10.\n        DEFB    $05             ;;division   ;x or 0,d,1/10.\n        DEFB    $C0             ;;st-mem-0   ;x or 0,d,1/10.\n        DEFB    $04             ;;multiply   ;x or 0,d/10.\n        DEFB    $0F             ;;addition   ;x or 0 + d/10.\n        DEFB    $38             ;;end-calc   last value.\n\n        RST     20H             ; NEXT-CHAR  moves to next character\n        JR      L2CDA           ; back to NXT-DGT-1\n\n; ---\n\n; although only the first pass is shown it can be seen that at each pass\n; the new less significant digit is multiplied by an increasingly smaller\n; factor (1/100, 1/1000, 1/10000 ... ) before being added to the previous\n; last value to form a new last value.\n\n; Finally see if an exponent has been input.\n\n;; E-FORMAT\nL2CEB:  CP      $45             ; is character 'E' ?\n        JR      Z,L2CF2         ; to SIGN-FLAG if so\n\n        CP      $65             ; 'e' is acceptable as well.\n        RET     NZ              ; return as no exponent.\n\n;; SIGN-FLAG\nL2CF2:  LD      B,$FF           ; initialize temporary sign byte to $FF\n\n        RST     20H             ; NEXT-CHAR\n        CP      $2B             ; is character '+' ?\n        JR      Z,L2CFE         ; to SIGN-DONE\n\n        CP      $2D             ; is character '-' ?\n        JR      NZ,L2CFF        ; to ST-E-PART as no sign\n\n        INC     B               ; set sign to zero\n\n; now consider digits of exponent.\n; Note. incidentally this is the only occasion in Spectrum BASIC when an\n; expression may not be used when a number is expected.\n\n;; SIGN-DONE\nL2CFE:  RST     20H             ; NEXT-CHAR\n\n;; ST-E-PART\nL2CFF:  CALL    L2D1B           ; routine NUMERIC\n        JR      C,L2CCF         ; to DEC-RPT-C if not\n                                ; raise 'Nonsense in BASIC'.\n\n        PUSH    BC              ; save sign (in B)\n        CALL    L2D3B           ; routine INT-TO-FP places exponent on stack\n        CALL    L2DD5           ; routine FP-TO-A  transfers it to A\n        POP     BC              ; restore sign\n        JP      C,L31AD         ; to REPORT-6 if overflow (over 255)\n                                ; raise 'Number too big'.\n\n        AND     A               ; set flags\n        JP      M,L31AD         ; to REPORT-6 if over '127'.\n                                ; raise 'Number too big'.\n                                ; 127 is still way too high and it is\n                                ; impossible to enter an exponent greater\n                                ; than 39 from the keyboard. The error gets\n                                ; raised later in E-TO-FP so two different\n                                ; error messages depending how high A is.\n\n        INC     B               ; $FF to $00 or $00 to $01 - expendable now.\n        JR      Z,L2D18         ; forward to E-FP-JUMP if exponent positive\n\n        NEG                     ; Negate the exponent.\n\n;; E-FP-JUMP\nL2D18:  JP      L2D4F           ; JUMP forward to E-TO-FP to assign to\n                                ; last value x on stack x * 10 to power A\n                                ; a relative jump would have done.\n\n; ---------------------\n; Check for valid digit\n; ---------------------\n; This routine checks that the ASCII character in A is numeric\n; returning with carry reset if so.\n\n;; NUMERIC\nL2D1B:  CP      $30             ; '0'\n        RET     C               ; return if less than zero character.\n\n        CP      $3A             ; The upper test is '9'\n        CCF                     ; Complement Carry Flag\n        RET                     ; Return - carry clear if character '0' - '9'\n\n; -----------\n; Stack Digit\n; -----------\n; This subroutine is called from INT-TO-FP and DEC-TO-FP to stack a digit\n; on the calculator stack.\n\n;; STK-DIGIT\nL2D22:  CALL    L2D1B           ; routine NUMERIC\n        RET     C               ; return if not numeric character\n\n        SUB     $30             ; convert from ASCII to digit\n\n; -----------------\n; Stack accumulator\n; -----------------\n;\n;\n\n;; STACK-A\nL2D28:  LD      C,A             ; transfer to C\n        LD      B,$00           ; and make B zero\n\n; ----------------------\n; Stack BC register pair\n; ----------------------\n;\n\n;; STACK-BC\nL2D2B:  LD      IY,$5C3A        ; re-initialize ERR_NR\n\n        XOR     A               ; clear to signal small integer\n        LD      E,A             ; place in E for sign\n        LD      D,C             ; LSB to D\n        LD      C,B             ; MSB to C\n        LD      B,A             ; last byte not used\n        CALL    L2AB6           ; routine STK-STORE\n\n        RST     28H             ;; FP-CALC\n        DEFB    $38             ;;end-calc  make HL = STKEND-5\n\n        AND     A               ; clear carry\n        RET                     ; before returning\n\n; -------------------------\n; Integer to floating point\n; -------------------------\n; This routine places one or more digits found in a BASIC line\n; on the calculator stack multiplying the previous value by ten each time\n; before adding in the new digit to form a last value on calculator stack.\n\n;; INT-TO-FP\nL2D3B:  PUSH    AF              ; save first character\n\n        RST     28H             ;; FP-CALC\n        DEFB    $A0             ;;stk-zero    ; v=0. initial value\n        DEFB    $38             ;;end-calc\n\n        POP     AF              ; fetch first character back.\n\n;; NXT-DGT-2\nL2D40:  CALL    L2D22           ; routine STK-DIGIT puts 0-9 on stack\n        RET     C               ; will return when character is not numeric >\n\n        RST     28H             ;; FP-CALC    ; v, d.\n        DEFB    $01             ;;exchange    ; d, v.\n        DEFB    $A4             ;;stk-ten     ; d, v, 10.\n        DEFB    $04             ;;multiply    ; d, v*10.\n        DEFB    $0F             ;;addition    ; d + v*10 = newvalue\n        DEFB    $38             ;;end-calc    ; v.\n\n        CALL    L0074           ; routine CH-ADD+1 get next character\n        JR      L2D40           ; back to NXT-DGT-2 to process as a digit\n\n\n;*********************************\n;** Part 9. ARITHMETIC ROUTINES **\n;*********************************\n\n; --------------------------\n; E-format to floating point\n; --------------------------\n; This subroutine is used by the PRINT-FP routine and the decimal to FP\n; routines to stack a number expressed in exponent format.\n; Note. Though not used by the ROM as such, it has also been set up as\n; a unary calculator literal but this will not work as the accumulator\n; is not available from within the calculator.\n\n; on entry there is a value x on the calculator stack and an exponent of ten\n; in A.    The required value is x + 10 ^ A\n\n;; e-to-fp\n;; E-TO-FP\nL2D4F:  RLCA                    ; this will set the          x.\n        RRCA                    ; carry if bit 7 is set\n\n        JR      NC,L2D55        ; to E-SAVE  if positive.\n\n        CPL                     ; make negative positive\n        INC     A               ; without altering carry.\n\n;; E-SAVE\nL2D55:  PUSH    AF              ; save positive exp and sign in carry\n\n        LD      HL,$5C92        ; address MEM-0\n\n        CALL    L350B           ; routine FP-0/1\n                                ; places an integer zero, if no carry,\n                                ; else a one in mem-0 as a sign flag\n\n        RST     28H             ;; FP-CALC\n        DEFB    $A4             ;;stk-ten                    x, 10.\n        DEFB    $38             ;;end-calc\n\n        POP     AF              ; pop the exponent.\n\n; now enter a loop\n\n;; E-LOOP\nL2D60:  SRL     A               ; 0>76543210>C\n\n        JR      NC,L2D71        ; forward to E-TST-END if no bit\n\n        PUSH    AF              ; save shifted exponent.\n\n        RST     28H             ;; FP-CALC\n        DEFB    $C1             ;;st-mem-1                   x, 10.\n        DEFB    $E0             ;;get-mem-0                  x, 10, (0/1).\n        DEFB    $00             ;;jump-true\n\n        DEFB    $04             ;;to L2D6D, E-DIVSN\n\n        DEFB    $04             ;;multiply                   x*10.\n        DEFB    $33             ;;jump\n\n        DEFB    $02             ;;to L2D6E, E-FETCH\n\n;; E-DIVSN\nL2D6D:  DEFB    $05             ;;division                   x/10.\n\n;; E-FETCH\nL2D6E:  DEFB    $E1             ;;get-mem-1                  x/10 or x*10, 10.\n        DEFB    $38             ;;end-calc                   new x, 10.\n\n        POP     AF              ; restore shifted exponent\n\n; the loop branched to here with no carry\n\n;; E-TST-END\nL2D71:  JR      Z,L2D7B         ; forward to E-END  if A emptied of bits\n\n        PUSH    AF              ; re-save shifted exponent\n\n        RST     28H             ;; FP-CALC\n        DEFB    $31             ;;duplicate                  new x, 10, 10.\n        DEFB    $04             ;;multiply                   new x, 100.\n        DEFB    $38             ;;end-calc\n\n        POP     AF              ; restore shifted exponent\n        JR      L2D60           ; back to E-LOOP  until all bits done.\n\n; ---\n\n; although only the first pass is shown it can be seen that for each set bit\n; representing a power of two, x is multiplied or divided by the\n; corresponding power of ten.\n\n;; E-END\nL2D7B:  RST     28H             ;; FP-CALC                   final x, factor.\n        DEFB    $02             ;;delete                     final x.\n        DEFB    $38             ;;end-calc                   x.\n\n        RET                     ; return\n\n\n\n\n; -------------\n; Fetch integer\n; -------------\n; This routine is called by the mathematical routines - FP-TO-BC, PRINT-FP,\n; mult, re-stack and negate to fetch an integer from address HL.\n; HL points to the stack or a location in MEM and no deletion occurs.\n; If the number is negative then a similar process to that used in INT-STORE\n; is used to restore the twos complement number to normal in DE and a sign\n; in C.\n\n;; INT-FETCH\nL2D7F:  INC     HL              ; skip zero indicator.\n        LD      C,(HL)          ; fetch sign to C\n        INC     HL              ; address low byte\n        LD      A,(HL)          ; fetch to A\n        XOR     C               ; two's complement\n        SUB     C               ;\n        LD      E,A             ; place in E\n        INC     HL              ; address high byte\n        LD      A,(HL)          ; fetch to A\n        ADC     A,C             ; two's complement\n        XOR     C               ;\n        LD      D,A             ; place in D\n        RET                     ; return\n\n; ------------------------\n; Store a positive integer\n; ------------------------\n; This entry point is not used in this ROM but would\n; store any integer as positive.\n\n;; p-int-sto\nL2D8C:  LD      C,$00           ; make sign byte positive and continue\n\n; -------------\n; Store integer\n; -------------\n; this routine stores an integer in DE at address HL.\n; It is called from mult, truncate, negate and sgn.\n; The sign byte $00 +ve or $FF -ve is in C.\n; If negative, the number is stored in 2's complement form so that it is\n; ready to be added.\n\n;; INT-STORE\nL2D8E:  PUSH    HL              ; preserve HL\n\n        LD      (HL),$00        ; first byte zero shows integer not exponent\n        INC     HL              ;\n        LD      (HL),C          ; then store the sign byte\n        INC     HL              ;\n                                ; e.g.             +1             -1\n        LD      A,E             ; fetch low byte   00000001       00000001\n        XOR     C               ; xor sign         00000000   or  11111111\n                                ; gives            00000001   or  11111110\n        SUB     C               ; sub sign         00000000   or  11111111\n                                ; gives            00000001>0 or  11111111>C\n        LD      (HL),A          ; store 2's complement.\n        INC     HL              ;\n        LD      A,D             ; high byte        00000000       00000000\n        ADC     A,C             ; sign             00000000<0     11111111<C\n                                ; gives            00000000   or  00000000\n        XOR     C               ; xor sign         00000000       11111111\n        LD      (HL),A          ; store 2's complement.\n        INC     HL              ;\n        LD      (HL),$00        ; last byte always zero for integers.\n                                ; is not used and need not be looked at when\n                                ; testing for zero but comes into play should\n                                ; an integer be converted to fp.\n        POP     HL              ; restore HL\n        RET                     ; return.\n\n\n; -----------------------------\n; Floating point to BC register\n; -----------------------------\n; This routine gets a floating point number e.g. 127.4 from the calculator\n; stack to the BC register.\n\n;; FP-TO-BC\nL2DA2:  RST     28H             ;; FP-CALC            set HL to\n        DEFB    $38             ;;end-calc            point to last value.\n\n        LD      A,(HL)          ; get first of 5 bytes\n        AND     A               ; and test\n        JR      Z,L2DAD         ; forward to FP-DELETE if an integer\n\n; The value is first rounded up and then converted to integer.\n\n        RST     28H             ;; FP-CALC           x.\n        DEFB    $A2             ;;stk-half           x. 1/2.\n        DEFB    $0F             ;;addition           x + 1/2.\n        DEFB    $27             ;;int                int(x + .5)\n        DEFB    $38             ;;end-calc\n\n; now delete but leave HL pointing at integer\n\n;; FP-DELETE\nL2DAD:  RST     28H             ;; FP-CALC\n        DEFB    $02             ;;delete\n        DEFB    $38             ;;end-calc\n\n        PUSH    HL              ; save pointer.\n        PUSH    DE              ; and STKEND.\n        EX      DE,HL           ; make HL point to exponent/zero indicator\n        LD      B,(HL)          ; indicator to B\n        CALL    L2D7F           ; routine INT-FETCH\n                                ; gets int in DE sign byte to C\n                                ; but meaningless values if a large integer\n\n        XOR     A               ; clear A\n        SUB     B               ; subtract indicator byte setting carry\n                                ; if not a small integer.\n\n        BIT     7,C             ; test a bit of the sign byte setting zero\n                                ; if positive.\n\n        LD      B,D             ; transfer int\n        LD      C,E             ; to BC\n        LD      A,E             ; low byte to A as a useful return value.\n\n        POP     DE              ; pop STKEND\n        POP     HL              ; and pointer to last value\n        RET                     ; return\n                                ; if carry is set then the number was too big.\n\n; ------------\n; LOG(2^A)\n; ------------\n; This routine is used when printing floating point numbers to calculate\n; the number of digits before the decimal point.\n\n; first convert a one-byte signed integer to its five byte form.\n\n;; LOG(2^A)\nL2DC1:  LD      D,A             ; store a copy of A in D.\n        RLA                     ; test sign bit of A.\n        SBC     A,A             ; now $FF if negative or $00\n        LD      E,A             ; sign byte to E.\n        LD      C,A             ; and to C\n        XOR     A               ; clear A\n        LD      B,A             ; and B.\n        CALL    L2AB6           ; routine STK-STORE stacks number AEDCB\n\n;  so 00 00 XX 00 00 (positive) or 00 FF XX FF 00 (negative).\n;  i.e. integer indicator, sign byte, low, high, unused.\n\n; now multiply exponent by log to the base 10 of two.\n\n        RST      28H            ;; FP-CALC\n\n        DEFB    $34             ;;stk-data                      .30103 (log 2)\n        DEFB    $EF             ;;Exponent: $7F, Bytes: 4\n        DEFB    $1A,$20,$9A,$85 ;;\n        DEFB    $04             ;;multiply\n\n        DEFB    $27             ;;int\n\n        DEFB    $38             ;;end-calc\n\n; -------------------\n; Floating point to A\n; -------------------\n; this routine collects a floating point number from the stack into the\n; accumulator returning carry set if not in range 0 - 255.\n; Not all the calling routines raise an error with overflow so no attempt\n; is made to produce an error report here.\n\n;; FP-TO-A\nL2DD5:  CALL    L2DA2           ; routine FP-TO-BC returns with C in A also.\n        RET     C               ; return with carry set if > 65535, overflow\n\n        PUSH    AF              ; save the value and flags\n        DEC     B               ; and test that\n        INC     B               ; the high byte is zero.\n        JR      Z,L2DE1         ; forward  FP-A-END if zero\n\n; else there has been 8-bit overflow\n\n        POP     AF              ; retrieve the value\n        SCF                     ; set carry flag to show overflow\n        RET                     ; and return.\n\n; ---\n\n;; FP-A-END\nL2DE1:  POP     AF              ; restore value and success flag and\n        RET                     ; return.\n\n\n; -----------------------------\n; Print a floating point number\n; -----------------------------\n; Not a trivial task.\n; Begin by considering whether to print a leading sign for negative numbers.\n\n;; PRINT-FP\nL2DE3:  RST     28H             ;; FP-CALC\n        DEFB    $31             ;;duplicate\n        DEFB    $36             ;;less-0\n        DEFB    $00             ;;jump-true\n\n        DEFB    $0B             ;;to L2DF2, PF-NEGTVE\n\n        DEFB    $31             ;;duplicate\n        DEFB    $37             ;;greater-0\n        DEFB    $00             ;;jump-true\n\n        DEFB    $0D             ;;to L2DF8, PF-POSTVE\n\n; must be zero itself\n\n        DEFB    $02             ;;delete\n        DEFB    $38             ;;end-calc\n\n        LD      A,$30           ; prepare the character '0'\n\n        RST     10H             ; PRINT-A\n        RET                     ; return.                 ->\n; ---\n\n;; PF-NEGTVE\nL2DF2:  DEFB    $2A             ;;abs\n        DEFB    $38             ;;end-calc\n\n        LD      A,$2D           ; the character '-'\n\n        RST     10H             ; PRINT-A\n\n; and continue to print the now positive number.\n\n        RST     28H             ;; FP-CALC\n\n;; PF-POSTVE\nL2DF8:  DEFB    $A0             ;;stk-zero     x,0.     begin by\n        DEFB    $C3             ;;st-mem-3     x,0.     clearing a temporary\n        DEFB    $C4             ;;st-mem-4     x,0.     output buffer to\n        DEFB    $C5             ;;st-mem-5     x,0.     fifteen zeros.\n        DEFB    $02             ;;delete       x.\n        DEFB    $38             ;;end-calc     x.\n\n        EXX                     ; in case called from 'str$' then save the\n        PUSH    HL              ; pointer to whatever comes after\n        EXX                     ; str$ as H'L' will be used.\n\n; now enter a loop?\n\n;; PF-LOOP\nL2E01:  RST     28H             ;; FP-CALC\n        DEFB    $31             ;;duplicate    x,x.\n        DEFB    $27             ;;int          x,int x.\n        DEFB    $C2             ;;st-mem-2     x,int x.\n        DEFB    $03             ;;subtract     x-int x.     fractional part.\n        DEFB    $E2             ;;get-mem-2    x-int x, int x.\n        DEFB    $01             ;;exchange     int x, x-int x.\n        DEFB    $C2             ;;st-mem-2     int x, x-int x.\n        DEFB    $02             ;;delete       int x.\n        DEFB    $38             ;;end-calc     int x.\n                                ;\n                                ; mem-2 holds the fractional part.\n\n; HL points to last value int x\n\n        LD      A,(HL)          ; fetch exponent of int x.\n        AND     A               ; test\n        JR      NZ,L2E56        ; forward to PF-LARGE if a large integer\n                                ; > 65535\n\n; continue with small positive integer components in range 0 - 65535\n; if original number was say .999 then this integer component is zero.\n\n        CALL    L2D7F           ; routine INT-FETCH gets x in DE\n                                ; (but x is not deleted)\n\n        LD      B,$10           ; set B, bit counter, to 16d\n\n        LD      A,D             ; test if\n        AND     A               ; high byte is zero\n        JR      NZ,L2E1E        ; forward to PF-SAVE if 16-bit integer.\n\n; and continue with integer in range 0 - 255.\n\n        OR      E               ; test the low byte for zero\n                                ; i.e. originally just point something or other.\n        JR      Z,L2E24         ; forward if so to PF-SMALL\n\n;\n\n        LD      D,E             ; transfer E to D\n        LD      B,$08           ; and reduce the bit counter to 8.\n\n;; PF-SAVE\nL2E1E:  PUSH    DE              ; save the part before decimal point.\n        EXX                     ;\n        POP     DE              ; and pop in into D'E'\n        EXX                     ;\n        JR      L2E7B           ; forward to PF-BITS\n\n; ---------------------\n\n; the branch was here when 'int x' was found to be zero as in say 0.5.\n; The zero has been fetched from the calculator stack but not deleted and\n; this should occur now. This omission leaves the stack unbalanced and while\n; that causes no problems with a simple PRINT statement, it will if str$ is\n; being used in an expression e.g. \"2\" + STR$ 0.5 gives the result \"0.5\"\n; instead of the expected result \"20.5\".\n; credit Tony Stratton, 1982.\n; A DEFB 02 delete is required immediately on using the calculator.\n\n;; PF-SMALL\nL2E24:  RST     28H             ;; FP-CALC       int x = 0.\nL2E25:  DEFB    $E2             ;;get-mem-2      int x = 0, x-int x.\n        DEFB    $38             ;;end-calc\n\n        LD      A,(HL)          ; fetch exponent of positive fractional number\n        SUB     $7E             ; subtract\n\n        CALL    L2DC1           ; routine LOG(2^A) calculates leading digits.\n\n        LD      D,A             ; transfer count to D\n        LD      A,($5CAC)       ; fetch total MEM-5-1\n        SUB     D               ;\n        LD      ($5CAC),A       ; MEM-5-1\n        LD      A,D             ;\n        CALL    L2D4F           ; routine E-TO-FP\n\n        RST     28H             ;; FP-CALC\n        DEFB    $31             ;;duplicate\n        DEFB    $27             ;;int\n        DEFB    $C1             ;;st-mem-1\n        DEFB    $03             ;;subtract\n        DEFB    $E1             ;;get-mem-1\n        DEFB    $38             ;;end-calc\n\n        CALL    L2DD5           ; routine FP-TO-A\n\n        PUSH    HL              ; save HL\n        LD      ($5CA1),A       ; MEM-3-1\n        DEC     A               ;\n        RLA                     ;\n        SBC     A,A             ;\n        INC     A               ;\n\n        LD      HL,$5CAB        ; address MEM-5-1 leading digit counter\n        LD      (HL),A          ; store counter\n        INC     HL              ; address MEM-5-2 total digits\n        ADD     A,(HL)          ; add counter to contents\n        LD      (HL),A          ; and store updated value\n        POP     HL              ; restore HL\n\n        JP      L2ECF           ; JUMP forward to PF-FRACTN\n\n; ---\n\n; Note. while it would be pedantic to comment on every occasion a JP\n; instruction could be replaced with a JR instruction, this applies to the\n; above, which is useful if you wish to correct the unbalanced stack error\n; by inserting a 'DEFB 02 delete' at L2E25, and maintain main addresses.\n\n; the branch was here with a large positive integer > 65535 e.g. 123456789\n; the accumulator holds the exponent.\n\n;; PF-LARGE\nL2E56:  SUB     $80             ; make exponent positive\n        CP      $1C             ; compare to 28\n        JR      C,L2E6F         ; to PF-MEDIUM if integer <= 2^27\n\n        CALL    L2DC1           ; routine LOG(2^A)\n        SUB     $07             ;\n        LD      B,A             ;\n        LD      HL,$5CAC        ; address MEM-5-1 the leading digits counter.\n        ADD     A,(HL)          ; add A to contents\n        LD      (HL),A          ; store updated value.\n        LD      A,B             ;\n        NEG                     ; negate\n        CALL    L2D4F           ; routine E-TO-FP\n        JR      L2E01           ; back to PF-LOOP\n\n; ----------------------------\n\n;; PF-MEDIUM\nL2E6F:  EX      DE,HL           ;\n        CALL    L2FBA           ; routine FETCH-TWO\n        EXX                     ;\n        SET     7,D             ;\n        LD      A,L             ;\n        EXX                     ;\n        SUB     $80             ;\n        LD      B,A             ;\n\n; the branch was here to handle bits in DE with 8 or 16 in B  if small int\n; and integer in D'E', 6 nibbles will accommodate 065535 but routine does\n; 32-bit numbers as well from above\n\n;; PF-BITS\nL2E7B:  SLA     E               ;  C<xxxxxxxx<0\n        RL      D               ;  C<xxxxxxxx<C\n        EXX                     ;\n        RL      E               ;  C<xxxxxxxx<C\n        RL      D               ;  C<xxxxxxxx<C\n        EXX                     ;\n\n        LD      HL,$5CAA        ; set HL to mem-4-5th last byte of buffer\n        LD      C,$05           ; set byte count to 5 -  10 nibbles\n\n;; PF-BYTES\nL2E8A:  LD      A,(HL)          ; fetch 0 or prev value\n        ADC     A,A             ; shift left add in carry    C<xxxxxxxx<C\n\n        DAA                     ; Decimal Adjust Accumulator.\n                                ; if greater than 9 then the left hand\n                                ; nibble is incremented. If greater than\n                                ; 99 then adjusted and carry set.\n                                ; so if we'd built up 7 and a carry came in\n                                ;      0000 0111 < C\n                                ;      0000 1111\n                                ; daa     1 0101  which is 15 in BCD\n\n        LD      (HL),A          ; put back\n        DEC     HL              ; work down thru mem 4\n        DEC     C               ; decrease the 5 counter.\n        JR      NZ,L2E8A        ; back to PF-BYTES until the ten nibbles rolled\n\n        DJNZ    L2E7B           ; back to PF-BITS until 8 or 16 (or 32) done\n\n; at most 9 digits for 32-bit number will have been loaded with digits\n; each of the 9 nibbles in mem 4 is placed into ten bytes in mem-3 and mem 4\n; unless the nibble is zero as the buffer is already zero.\n; ( or in the case of mem-5 will become zero as a result of RLD instruction )\n\n        XOR     A               ; clear to accept\n        LD      HL,$5CA6        ; address MEM-4-0 byte destination.\n        LD      DE,$5CA1        ; address MEM-3-0 nibble source.\n        LD      B,$09           ; the count is 9 (not ten) as the first\n                                ; nibble is known to be blank.\n\n        RLD                     ; shift RH nibble to left in (HL)\n                                ;    A           (HL)\n                                ; 0000 0000 < 0000 3210\n                                ; 0000 0000   3210 0000\n                                ; A picks up the blank nibble\n\n\n        LD      C,$FF           ; set a flag to indicate when a significant\n                                ; digit has been encountered.\n\n;; PF-DIGITS\nL2EA1:  RLD                     ; pick up leftmost nibble from (HL)\n                                ;    A           (HL)\n                                ; 0000 0000 < 7654 3210\n                                ; 0000 7654   3210 0000\n\n\n        JR      NZ,L2EA9        ; to PF-INSERT if non-zero value picked up.\n\n        DEC     C               ; test\n        INC     C               ; flag\n        JR      NZ,L2EB3        ; skip forward to PF-TEST-2 if flag still $FF\n                                ; indicating this is a leading zero.\n\n; but if the zero is a significant digit e.g. 10 then include in digit totals.\n; the path for non-zero digits rejoins here.\n\n;; PF-INSERT\nL2EA9:  LD      (DE),A          ; insert digit at destination\n        INC     DE              ; increase the destination pointer\n        INC     (IY+$71)        ; increment MEM-5-1st  digit counter\n        INC     (IY+$72)        ; increment MEM-5-2nd  leading digit counter\n        LD      C,$00           ; set flag to zero indicating that any\n                                ; subsequent zeros are significant and not\n                                ; leading.\n\n;; PF-TEST-2\nL2EB3:  BIT     0,B             ; test if the nibble count is even\n        JR      Z,L2EB8         ; skip to PF-ALL-9 if so to deal with the\n                                ; other nibble in the same byte\n\n        INC     HL              ; point to next source byte if not\n\n;; PF-ALL-9\nL2EB8:  DJNZ    L2EA1           ; decrement the nibble count, back to PF-DIGITS\n                                ; if all nine not done.\n\n; For 8-bit integers there will be at most 3 digits.\n; For 16-bit integers there will be at most 5 digits.\n; but for larger integers there could be nine leading digits.\n; if nine digits complete then the last one is rounded up as the number will\n; be printed using E-format notation\n\n        LD      A,($5CAB)       ; fetch digit count from MEM-5-1st\n        SUB     $09             ; subtract 9 - max possible\n        JR      C,L2ECB         ; forward if less to PF-MORE\n\n        DEC     (IY+$71)        ; decrement digit counter MEM-5-1st to 8\n        LD      A,$04           ; load A with the value 4.\n        CP      (IY+$6F)        ; compare with MEM-4-4th - the ninth digit\n        JR      L2F0C           ; forward to PF-ROUND\n                                ; to consider rounding.\n\n; ---------------------------------------\n\n; now delete int x from calculator stack and fetch fractional part.\n\n;; PF-MORE\nL2ECB:  RST     28H             ;; FP-CALC        int x.\n        DEFB    $02             ;;delete          .\n        DEFB    $E2             ;;get-mem-2       x - int x = f.\n        DEFB    $38             ;;end-calc        f.\n\n;; PF-FRACTN\nL2ECF:  EX      DE,HL           ;\n        CALL    L2FBA           ; routine FETCH-TWO\n        EXX                     ;\n        LD      A,$80           ;\n        SUB     L               ;\n        LD      L,$00           ;\n        SET     7,D             ;\n        EXX                     ;\n        CALL    L2FDD           ; routine SHIFT-FP\n\n;; PF-FRN-LP\nL2EDF:  LD      A,(IY+$71)      ; MEM-5-1st\n        CP      $08             ;\n        JR      C,L2EEC         ; to PF-FR-DGT\n\n        EXX                     ;\n        RL      D               ;\n        EXX                     ;\n        JR      L2F0C           ; to PF-ROUND\n\n; ---\n\n;; PF-FR-DGT\nL2EEC:  LD      BC,$0200        ;\n\n;; PF-FR-EXX\nL2EEF:  LD      A,E             ;\n        CALL    L2F8B           ; routine CA-10*A+C\n        LD      E,A             ;\n        LD      A,D             ;\n        CALL    L2F8B           ; routine CA-10*A+C\n        LD      D,A             ;\n        PUSH    BC              ;\n        EXX                     ;\n        POP     BC              ;\n        DJNZ    L2EEF           ; to PF-FR-EXX\n\n        LD      HL,$5CA1        ; MEM-3\n        LD      A,C             ;\n        LD      C,(IY+$71)      ; MEM-5-1st\n        ADD     HL,BC           ;\n        LD      (HL),A          ;\n        INC     (IY+$71)        ; MEM-5-1st\n        JR      L2EDF           ; to PF-FRN-LP\n\n; ----------------\n\n; 1) with 9 digits but 8 in mem-5-1 and A holding 4, carry set if rounding up.\n; e.g.\n;      999999999 is printed as 1E+9\n;      100000001 is printed as 1E+8\n;      100000009 is printed as 1.0000001E+8\n\n;; PF-ROUND\nL2F0C:  PUSH    AF              ; save A and flags\n        LD      HL,$5CA1        ; address MEM-3 start of digits\n        LD      C,(IY+$71)      ; MEM-5-1st No. of digits to C\n        LD      B,$00           ; prepare to add\n        ADD     HL,BC           ; address last digit + 1\n        LD      B,C             ; No. of digits to B counter\n        POP     AF              ; restore A and carry flag from comparison.\n\n;; PF-RND-LP\nL2F18:  DEC     HL              ; address digit at rounding position.\n        LD      A,(HL)          ; fetch it\n        ADC     A,$00           ; add carry from the comparison\n        LD      (HL),A          ; put back result even if $0A.\n        AND     A               ; test A\n        JR      Z,L2F25         ; skip to PF-R-BACK if ZERO?\n\n        CP      $0A             ; compare to 'ten' - overflow\n        CCF                     ; complement carry flag so that set if ten.\n        JR      NC,L2F2D        ; forward to PF-COUNT with 1 - 9.\n\n;; PF-R-BACK\nL2F25:  DJNZ    L2F18           ; loop back to PF-RND-LP\n\n; if B counts down to zero then we've rounded right back as in 999999995.\n; and the first 8 locations all hold $0A.\n\n\n        LD      (HL),$01        ; load first location with digit 1.\n        INC     B               ; make B hold 1 also.\n                                ; could save an instruction byte here.\n        INC     (IY+$72)        ; make MEM-5-2nd hold 1.\n                                ; and proceed to initialize total digits to 1.\n\n;; PF-COUNT\nL2F2D:  LD      (IY+$71),B      ; MEM-5-1st\n\n; now balance the calculator stack by deleting  it\n\n        RST     28H             ;; FP-CALC\n        DEFB    $02             ;;delete\n        DEFB    $38             ;;end-calc\n\n; note if used from str$ then other values may be on the calculator stack.\n; we can also restore the next literal pointer from its position on the\n; machine stack.\n\n        EXX                     ;\n        POP     HL              ; restore next literal pointer.\n        EXX                     ;\n\n        LD      BC,($5CAB)      ; set C to MEM-5-1st digit counter.\n                                ; set B to MEM-5-2nd leading digit counter.\n        LD      HL,$5CA1        ; set HL to start of digits at MEM-3-1\n        LD      A,B             ;\n        CP      $09             ;\n        JR      C,L2F46         ; to PF-NOT-E\n\n        CP      $FC             ;\n        JR      C,L2F6C         ; to PF-E-FRMT\n\n;; PF-NOT-E\nL2F46:  AND     A               ; test for zero leading digits as in .123\n\n        CALL    Z,L15EF         ; routine OUT-CODE prints a zero e.g. 0.123\n\n;; PF-E-SBRN\nL2F4A:  XOR     A               ;\n        SUB     B               ;\n        JP      M,L2F52         ; skip forward to PF-OUT-LP if originally +ve\n\n        LD      B,A             ; else negative count now +ve\n        JR      L2F5E           ; forward to PF-DC-OUT       ->\n\n; ---\n\n;; PF-OUT-LP\nL2F52:  LD      A,C             ; fetch total digit count\n        AND     A               ; test for zero\n        JR      Z,L2F59         ; forward to PF-OUT-DT if so\n\n        LD      A,(HL)          ; fetch digit\n        INC     HL              ; address next digit\n        DEC     C               ; decrease total digit counter\n\n;; PF-OUT-DT\nL2F59:  CALL    L15EF           ; routine OUT-CODE outputs it.\n        DJNZ    L2F52           ; loop back to PF-OUT-LP until B leading\n                                ; digits output.\n\n;; PF-DC-OUT\nL2F5E:  LD      A,C             ; fetch total digits and\n        AND     A               ; test if also zero\n        RET     Z               ; return if so              -->\n\n;\n\n        INC     B               ; increment B\n        LD      A,$2E           ; prepare the character '.'\n\n;; PF-DEC-0S\nL2F64:  RST     10H             ; PRINT-A outputs the character '.' or '0'\n\n        LD      A,$30           ; prepare the character '0'\n                                ; (for cases like .000012345678)\n        DJNZ    L2F64           ; loop back to PF-DEC-0S for B times.\n\n        LD      B,C             ; load B with now trailing digit counter.\n        JR      L2F52           ; back to PF-OUT-LP\n\n; ---------------------------------\n\n; the branch was here for E-format printing e.g. 123456789 => 1.2345679e+8\n\n;; PF-E-FRMT\nL2F6C:  LD      D,B             ; counter to D\n        DEC     D               ; decrement\n        LD      B,$01           ; load B with 1.\n\n        CALL    L2F4A           ; routine PF-E-SBRN above\n\n        LD      A,$45           ; prepare character 'e'\n        RST     10H             ; PRINT-A\n\n        LD      C,D             ; exponent to C\n        LD      A,C             ; and to A\n        AND     A               ; test exponent\n        JP      P,L2F83         ; to PF-E-POS if positive\n\n        NEG                     ; negate\n        LD      C,A             ; positive exponent to C\n        LD      A,$2D           ; prepare character '-'\n        JR      L2F85           ; skip to PF-E-SIGN\n\n; ---\n\n;; PF-E-POS\nL2F83:  LD      A,$2B           ; prepare character '+'\n\n;; PF-E-SIGN\nL2F85:  RST     10H             ; PRINT-A outputs the sign\n\n        LD      B,$00           ; make the high byte zero.\n        JP      L1A1B           ; exit via OUT-NUM-1 to print exponent in BC\n\n; ------------------------------\n; Handle printing floating point\n; ------------------------------\n; This subroutine is called twice from above when printing floating-point\n; numbers. It returns 10*A +C in registers C and A\n\n;; CA-10*A+C\nL2F8B:  PUSH    DE              ; preserve DE.\n        LD      L,A             ; transfer A to L\n        LD      H,$00           ; zero high byte.\n        LD      E,L             ; copy HL\n        LD      D,H             ; to DE.\n        ADD     HL,HL           ; double (*2)\n        ADD     HL,HL           ; double (*4)\n        ADD     HL,DE           ; add DE (*5)\n        ADD     HL,HL           ; double (*10)\n        LD      E,C             ; copy C to E    (D is 0)\n        ADD     HL,DE           ; and add to give required result.\n        LD      C,H             ; transfer to\n        LD      A,L             ; destination registers.\n        POP     DE              ; restore DE\n        RET                     ; return with result.\n\n; --------------\n; Prepare to add\n; --------------\n; This routine is called twice by addition to prepare the two numbers. The\n; exponent is picked up in A and the location made zero. Then the sign bit\n; is tested before being set to the implied state. Negative numbers are twos\n; complemented.\n\n;; PREP-ADD\nL2F9B:  LD      A,(HL)          ; pick up exponent\n        LD      (HL),$00        ; make location zero\n        AND     A               ; test if number is zero\n        RET     Z               ; return if so\n\n        INC     HL              ; address mantissa\n        BIT     7,(HL)          ; test the sign bit\n        SET     7,(HL)          ; set it to implied state\n        DEC     HL              ; point to exponent\n        RET     Z               ; return if positive number.\n\n        PUSH    BC              ; preserve BC\n        LD      BC,$0005        ; length of number\n        ADD     HL,BC           ; point HL past end\n        LD      B,C             ; set B to 5 counter\n        LD      C,A             ; store exponent in C\n        SCF                     ; set carry flag\n\n;; NEG-BYTE\nL2FAF:  DEC     HL              ; work from LSB to MSB\n        LD      A,(HL)          ; fetch byte\n        CPL                     ; complement\n        ADC     A,$00           ; add in initial carry or from prev operation\n        LD      (HL),A          ; put back\n        DJNZ    L2FAF           ; loop to NEG-BYTE till all 5 done\n\n        LD      A,C             ; stored exponent to A\n        POP     BC              ; restore original BC\n        RET                     ; return\n\n; -----------------\n; Fetch two numbers\n; -----------------\n; This routine is called twice when printing floating point numbers and also\n; to fetch two numbers by the addition, multiply and division routines.\n; HL addresses the first number, DE addresses the second number.\n; For arithmetic only, A holds the sign of the result which is stored in\n; the second location.\n\n;; FETCH-TWO\nL2FBA:  PUSH    HL              ; save pointer to first number, result if math.\n        PUSH    AF              ; save result sign.\n\n        LD      C,(HL)          ;\n        INC     HL              ;\n\n        LD      B,(HL)          ;\n        LD      (HL),A          ; store the sign at correct location in\n                                ; destination 5 bytes for arithmetic only.\n        INC     HL              ;\n\n        LD      A,C             ;\n        LD      C,(HL)          ;\n        PUSH    BC              ;\n        INC     HL              ;\n        LD      C,(HL)          ;\n        INC     HL              ;\n        LD      B,(HL)          ;\n        EX      DE,HL           ;\n        LD      D,A             ;\n        LD      E,(HL)          ;\n        PUSH    DE              ;\n        INC     HL              ;\n        LD      D,(HL)          ;\n        INC     HL              ;\n        LD      E,(HL)          ;\n        PUSH    DE              ;\n        EXX                     ;\n        POP     DE              ;\n        POP     HL              ;\n        POP     BC              ;\n        EXX                     ;\n        INC     HL              ;\n        LD      D,(HL)          ;\n        INC     HL              ;\n        LD      E,(HL)          ;\n\n        POP     AF              ; restore possible result sign.\n        POP     HL              ; and pointer to possible result.\n        RET                     ; return.\n\n; ---------------------------------\n; Shift floating point number right\n; ---------------------------------\n;\n;\n\n;; SHIFT-FP\nL2FDD:  AND     A               ;\n        RET     Z               ;\n\n        CP      $21             ;\n        JR      NC,L2FF9        ; to ADDEND-0\n\n        PUSH    BC              ;\n        LD      B,A             ;\n\n;; ONE-SHIFT\nL2FE5:  EXX                     ;\n        SRA     L               ;\n        RR      D               ;\n        RR      E               ;\n        EXX                     ;\n        RR      D               ;\n        RR      E               ;\n        DJNZ    L2FE5           ; to ONE-SHIFT\n\n        POP     BC              ;\n        RET     NC              ;\n\n        CALL    L3004           ; routine ADD-BACK\n        RET     NZ              ;\n\n;; ADDEND-0\nL2FF9:  EXX                     ;\n        XOR     A               ;\n\n;; ZEROS-4/5\nL2FFB:  LD      L,$00           ;\n        LD      D,A             ;\n        LD      E,L             ;\n        EXX                     ;\n        LD      DE,$0000        ;\n        RET                     ;\n\n; ------------------\n; Add back any carry\n; ------------------\n;\n;\n\n;; ADD-BACK\nL3004:  INC     E               ;\n        RET     NZ              ;\n\n        INC      D              ;\n        RET     NZ              ;\n\n        EXX                     ;\n        INC     E               ;\n        JR      NZ,L300D        ; to ALL-ADDED\n\n        INC     D               ;\n\n;; ALL-ADDED\nL300D:  EXX                     ;\n        RET                     ;\n\n; -----------------------\n; Handle subtraction (03)\n; -----------------------\n; Subtraction is done by switching the sign byte/bit of the second number\n; which may be integer of floating point and continuing into addition.\n\n;; subtract\nL300F:  EX      DE,HL           ; address second number with HL\n\n        CALL    L346E           ; routine NEGATE switches sign\n\n        EX      DE,HL           ; address first number again\n                                ; and continue.\n\n; --------------------\n; Handle addition (0F)\n; --------------------\n; HL points to first number, DE to second.\n; If they are both integers, then go for the easy route.\n\n;; addition\nL3014:  LD      A,(DE)          ; fetch first byte of second\n        OR      (HL)            ; combine with first byte of first\n        JR      NZ,L303E        ; forward to FULL-ADDN if at least one was\n                                ; in floating point form.\n\n; continue if both were small integers.\n\n        PUSH    DE              ; save pointer to lowest number for result.\n\n        INC     HL              ; address sign byte and\n        PUSH    HL              ; push the pointer.\n\n        INC     HL              ; address low byte\n        LD      E,(HL)          ; to E\n        INC     HL              ; address high byte\n        LD      D,(HL)          ; to D\n        INC     HL              ; address unused byte\n\n        INC     HL              ; address known zero indicator of 1st number\n        INC     HL              ; address sign byte\n\n        LD      A,(HL)          ; sign to A, $00 or $FF\n\n        INC     HL              ; address low byte\n        LD      C,(HL)          ; to C\n        INC     HL              ; address high byte\n        LD      B,(HL)          ; to B\n\n        POP     HL              ; pop result sign pointer\n        EX      DE,HL           ; integer to HL\n\n        ADD     HL,BC           ; add to the other one in BC\n                                ; setting carry if overflow.\n\n        EX      DE,HL           ; save result in DE bringing back sign pointer\n\n        ADC     A,(HL)          ; if pos/pos A=01 with overflow else 00\n                                ; if neg/neg A=FF with overflow else FE\n                                ; if mixture A=00 with overflow else FF\n\n        RRCA                    ; bit 0 to (C)\n\n        ADC     A,$00           ; both acceptable signs now zero\n\n        JR      NZ,L303C        ; forward to ADDN-OFLW if not\n\n        SBC     A,A             ; restore a negative result sign\n\n        LD      (HL),A          ;\n        INC     HL              ;\n        LD      (HL),E          ;\n        INC     HL              ;\n        LD      (HL),D          ;\n        DEC     HL              ;\n        DEC     HL              ;\n        DEC     HL              ;\n\n        POP     DE              ; STKEND\n        RET                     ;\n\n; ---\n\n;; ADDN-OFLW\nL303C:  DEC     HL              ;\n        POP     DE              ;\n\n;; FULL-ADDN\nL303E:  CALL    L3293           ; routine RE-ST-TWO\n        EXX                     ;\n        PUSH    HL              ;\n        EXX                     ;\n        PUSH    DE              ;\n        PUSH    HL              ;\n        CALL    L2F9B           ; routine PREP-ADD\n        LD      B,A             ;\n        EX      DE,HL           ;\n        CALL    L2F9B           ; routine PREP-ADD\n        LD       C,A            ;\n        CP      B               ;\n        JR      NC,L3055        ; to SHIFT-LEN\n\n        LD      A,B             ;\n        LD      B,C             ;\n        EX      DE,HL           ;\n\n;; SHIFT-LEN\nL3055:  PUSH    AF              ;\n        SUB     B               ;\n        CALL    L2FBA           ; routine FETCH-TWO\n        CALL    L2FDD           ; routine SHIFT-FP\n        POP     AF              ;\n        POP     HL              ;\n        LD      (HL),A          ;\n        PUSH    HL              ;\n        LD      L,B             ;\n        LD      H,C             ;\n        ADD     HL,DE           ;\n        EXX                     ;\n        EX      DE,HL           ;\n        ADC     HL,BC           ;\n        EX      DE,HL           ;\n        LD      A,H             ;\n        ADC     A,L             ;\n        LD      L,A             ;\n        RRA                     ;\n        XOR     L               ;\n        EXX                     ;\n        EX      DE,HL           ;\n        POP     HL              ;\n        RRA                     ;\n        JR      NC,L307C        ; to TEST-NEG\n\n        LD      A,$01           ;\n        CALL    L2FDD           ; routine SHIFT-FP\n        INC     (HL)            ;\n        JR      Z,L309F         ; to ADD-REP-6\n\n;; TEST-NEG\nL307C:  EXX                     ;\n        LD      A,L             ;\n        AND     $80             ;\n        EXX                     ;\n        INC     HL              ;\n        LD      (HL),A          ;\n        DEC     HL              ;\n        JR      Z,L30A5         ; to GO-NC-MLT\n\n        LD      A,E             ;\n        NEG                     ; Negate\n        CCF                     ; Complement Carry Flag\n        LD      E,A             ;\n        LD      A,D             ;\n        CPL                     ;\n        ADC     A,$00           ;\n        LD      D,A             ;\n        EXX                     ;\n        LD      A,E             ;\n        CPL                     ;\n        ADC     A,$00           ;\n        LD      E,A             ;\n        LD      A,D             ;\n        CPL                     ;\n        ADC     A,$00           ;\n        JR      NC,L30A3        ; to END-COMPL\n\n        RRA                     ;\n        EXX                     ;\n        INC     (HL)            ;\n\n;; ADD-REP-6\nL309F:  JP      Z,L31AD         ; to REPORT-6\n\n        EXX                     ;\n\n;; END-COMPL\nL30A3:  LD      D,A             ;\n        EXX                     ;\n\n;; GO-NC-MLT\nL30A5:  XOR     A               ;\n        JP      L3155           ; to TEST-NORM\n\n; -----------------------------\n; Used in 16 bit multiplication\n; -----------------------------\n; This routine is used, in the first instance, by the multiply calculator\n; literal to perform an integer multiplication in preference to\n; 32-bit multiplication to which it will resort if this overflows.\n;\n; It is also used by STK-VAR to calculate array subscripts and by DIM to\n; calculate the space required for multi-dimensional arrays.\n\n;; HL-HL*DE\nL30A9:  PUSH    BC              ; preserve BC throughout\n        LD      B,$10           ; set B to 16\n        LD      A,H             ; save H in A high byte\n        LD      C,L             ; save L in C low byte\n        LD      HL,$0000        ; initialize result to zero\n\n; now enter a loop.\n\n;; HL-LOOP\nL30B1:  ADD     HL,HL           ; double result\n        JR      C,L30BE         ; to HL-END if overflow\n\n        RL      C               ; shift AC left into carry\n        RLA                     ;\n        JR      NC,L30BC        ; to HL-AGAIN to skip addition if no carry\n\n        ADD     HL,DE           ; add in DE\n        JR      C,L30BE         ; to HL-END if overflow\n\n;; HL-AGAIN\nL30BC:  DJNZ    L30B1           ; back to HL-LOOP for all 16 bits\n\n;; HL-END\nL30BE:  POP     BC              ; restore preserved BC\n        RET                     ; return with carry reset if successful\n                                ; and result in HL.\n\n; ----------------------------------------------\n; THE 'PREPARE TO MULTIPLY OR DIVIDE' SUBROUTINE\n; ----------------------------------------------\n;   This routine is called in succession from multiply and divide to prepare\n;   two mantissas by setting the leftmost bit that is used for the sign.\n;   On the first call A holds zero and picks up the sign bit. On the second\n;   call the two bits are XORed to form the result sign - minus * minus giving\n;   plus etc. If either number is zero then this is flagged.\n;   HL addresses the exponent.\n\n;; PREP-M/D\nL30C0:  CALL    L34E9           ; routine TEST-ZERO  preserves accumulator.\n        RET     C               ; return carry set if zero\n\n        INC     HL              ; address first byte of mantissa\n        XOR     (HL)            ; pick up the first or xor with first.\n        SET     7,(HL)          ; now set to give true 32-bit mantissa\n        DEC     HL              ; point to exponent\n        RET                     ; return with carry reset\n\n; ----------------------\n; THE 'MULTIPLY' ROUTINE\n; ----------------------\n; (offset: $04 'multiply')\n;\n;\n;   \"He said go forth and something about mathematics, I wasn't really\n;    listening\" - overheard conversation between two unicorns.\n;    [ The Odd Streak ].\n\n;; multiply\nL30CA:  LD      A,(DE)          ;\n        OR      (HL)            ;\n        JR      NZ,L30F0        ; to MULT-LONG\n\n        PUSH    DE              ;\n        PUSH    HL              ;\n        PUSH    DE              ;\n        CALL    L2D7F           ; routine INT-FETCH\n        EX      DE,HL           ;\n        EX      (SP),HL         ;\n        LD      B,C             ;\n        CALL    L2D7F           ; routine INT-FETCH\n        LD      A,B             ;\n        XOR     C               ;\n        LD      C,A             ;\n        POP     HL              ;\n        CALL    L30A9           ; routine HL-HL*DE\n        EX      DE,HL           ;\n        POP     HL              ;\n        JR      C,L30EF         ; to MULT-OFLW\n\n        LD      A,D             ;\n        OR      E               ;\n        JR      NZ,L30EA        ; to MULT-RSLT\n\n        LD      C,A             ;\n\n;; MULT-RSLT\nL30EA:  CALL    L2D8E           ; routine INT-STORE\n        POP      DE             ;\n        RET                     ;\n\n; ---\n\n;; MULT-OFLW\nL30EF:  POP     DE              ;\n\n;; MULT-LONG\nL30F0:  CALL    L3293           ; routine RE-ST-TWO\n        XOR     A               ;\n        CALL    L30C0           ; routine PREP-M/D\n        RET     C               ;\n\n        EXX                     ;\n        PUSH    HL              ;\n        EXX                     ;\n        PUSH    DE              ;\n        EX      DE,HL           ;\n        CALL    L30C0           ; routine PREP-M/D\n        EX      DE,HL           ;\n        JR      C,L315D         ; to ZERO-RSLT\n\n        PUSH    HL              ;\n        CALL    L2FBA           ; routine FETCH-TWO\n        LD      A,B             ;\n        AND     A               ;\n        SBC     HL,HL           ;\n        EXX                     ;\n        PUSH    HL              ;\n        SBC     HL,HL           ;\n        EXX                     ;\n        LD      B,$21           ;\n        JR      L3125           ; to STRT-MLT\n\n; ---\n\n;; MLT-LOOP\nL3114:  JR      NC,L311B        ; to NO-ADD\n\n        ADD     HL,DE           ;\n        EXX                     ;\n        ADC     HL,DE           ;\n        EXX                     ;\n\n;; NO-ADD\nL311B:  EXX                     ;\n        RR      H               ;\n        RR      L               ;\n        EXX                     ;\n        RR      H               ;\n        RR      L               ;\n\n;; STRT-MLT\nL3125:  EXX                     ;\n        RR      B               ;\n        RR      C               ;\n        EXX                     ;\n        RR      C               ;\n        RRA                     ;\n        DJNZ    L3114           ; to MLT-LOOP\n\n        EX      DE,HL           ;\n        EXX                     ;\n        EX      DE,HL           ;\n        EXX                     ;\n        POP     BC              ;\n        POP     HL              ;\n        LD      A,B             ;\n        ADD     A,C             ;\n        JR      NZ,L313B        ; to MAKE-EXPT\n\n        AND     A               ;\n\n;; MAKE-EXPT\nL313B:  DEC     A               ;\n        CCF                     ; Complement Carry Flag\n\n;; DIVN-EXPT\nL313D:  RLA                     ;\n        CCF                     ; Complement Carry Flag\n        RRA                     ;\n        JP      P,L3146         ; to OFLW1-CLR\n\n        JR      NC,L31AD        ; to REPORT-6\n\n        AND     A               ;\n\n;; OFLW1-CLR\nL3146:  INC     A               ;\n        JR      NZ,L3151        ; to OFLW2-CLR\n\n        JR      C,L3151         ; to OFLW2-CLR\n\n        EXX                     ;\n        BIT     7,D             ;\n        EXX                     ;\n        JR      NZ,L31AD        ; to REPORT-6\n\n;; OFLW2-CLR\nL3151:  LD      (HL),A          ;\n        EXX                     ;\n        LD      A,B             ;\n        EXX                     ;\n\n;; TEST-NORM\nL3155:  JR      NC,L316C        ; to NORMALISE\n\n        LD      A,(HL)          ;\n        AND     A               ;\n\n;; NEAR-ZERO\nL3159:  LD      A,$80           ;\n        JR      Z,L315E         ; to SKIP-ZERO\n\n;; ZERO-RSLT\nL315D:  XOR     A               ;\n\n;; SKIP-ZERO\nL315E:  EXX                     ;\n        AND     D               ;\n        CALL    L2FFB           ; routine ZEROS-4/5\n        RLCA                    ;\n        LD      (HL),A          ;\n        JR      C,L3195         ; to OFLOW-CLR\n\n        INC     HL              ;\n        LD      (HL),A          ;\n        DEC     HL              ;\n        JR      L3195           ; to OFLOW-CLR\n\n; ---\n\n;; NORMALISE\nL316C:  LD      B,$20           ;\n\n;; SHIFT-ONE\nL316E:  EXX                     ;\n        BIT     7,D             ;\n        EXX                     ;\n        JR      NZ,L3186        ; to NORML-NOW\n\n        RLCA                    ;\n        RL      E               ;\n        RL      D               ;\n        EXX                     ;\n        RL      E               ;\n        RL      D               ;\n        EXX                     ;\n        DEC     (HL)            ;\n        JR      Z,L3159         ; to NEAR-ZERO\n\n        DJNZ    L316E           ; to SHIFT-ONE\n\n        JR      L315D           ; to ZERO-RSLT\n\n; ---\n\n;; NORML-NOW\nL3186:  RLA                     ;\n        JR      NC,L3195        ; to OFLOW-CLR\n\n        CALL    L3004           ; routine ADD-BACK\n        JR      NZ,L3195        ; to OFLOW-CLR\n\n        EXX                     ;\n        LD       D,$80          ;\n        EXX                     ;\n        INC     (HL)            ;\n        JR      Z,L31AD         ; to REPORT-6\n\n;; OFLOW-CLR\nL3195:  PUSH    HL              ;\n        INC     HL              ;\n        EXX                     ;\n        PUSH    DE              ;\n        EXX                     ;\n        POP     BC              ;\n        LD      A,B             ;\n        RLA                     ;\n        RL      (HL)            ;\n        RRA                     ;\n        LD      (HL),A          ;\n        INC     HL              ;\n        LD      (HL),C          ;\n        INC     HL              ;\n        LD      (HL),D          ;\n        INC     HL              ;\n        LD      (HL),E          ;\n        POP     HL              ;\n        POP     DE              ;\n        EXX                     ;\n        POP     HL              ;\n        EXX                     ;\n        RET                     ;\n\n; ---\n\n;; REPORT-6\nL31AD:  RST     08H             ; ERROR-1\n        DEFB    $05             ; Error Report: Number too big\n\n; ----------------------\n; THE 'DIVISION' ROUTINE\n; ----------------------\n; (offset: $05 'division')\n;\n;   \"He who can properly define and divide is to be considered a god\"\n;   - Plato,  429 - 347 B.C.\n\n;; division\nL31AF:  CALL    L3293           ; routine RE-ST-TWO\n        EX      DE,HL           ;\n        XOR     A               ;\n        CALL    L30C0           ; routine PREP-M/D\n        JR      C,L31AD         ; to REPORT-6\n\n        EX      DE,HL           ;\n        CALL    L30C0           ; routine PREP-M/D\n        RET     C               ;\n\n        EXX                     ;\n        PUSH    HL              ;\n        EXX                     ;\n        PUSH    DE              ;\n        PUSH    HL              ;\n        CALL    L2FBA           ; routine FETCH-TWO\n        EXX                     ;\n        PUSH    HL              ;\n        LD      H,B             ;\n        LD      L,C             ;\n        EXX                     ;\n        LD      H,C             ;\n        LD      L,B             ;\n        XOR     A               ;\n        LD      B,$DF           ;\n        JR      L31E2           ; to DIV-START\n\n; ---\n\n;; DIV-LOOP\nL31D2:  RLA                     ;\n        RL      C               ;\n        EXX                     ;\n        RL      C               ;\n        RL      B               ;\n        EXX                     ;\n\n;; div-34th\nL31DB:  ADD     HL,HL           ;\n        EXX                     ;\n        ADC     HL,HL           ;\n        EXX                     ;\n        JR      C,L31F2         ; to SUBN-ONLY\n\n;; DIV-START\nL31E2:  SBC     HL,DE           ;\n        EXX                     ;\n        SBC     HL,DE           ;\n        EXX                     ;\n        JR      NC,L31F9        ; to NO-RSTORE\n\n        ADD     HL,DE           ;\n        EXX                     ;\n        ADC     HL,DE           ;\n        EXX                     ;\n        AND     A               ;\n        JR      L31FA           ; to COUNT-ONE\n\n; ---\n\n;; SUBN-ONLY\nL31F2:  AND     A               ;\n        SBC     HL,DE           ;\n        EXX                     ;\n        SBC     HL,DE           ;\n        EXX                     ;\n\n;; NO-RSTORE\nL31F9:  SCF                     ; Set Carry Flag\n\n;; COUNT-ONE\nL31FA:  INC     B               ;\n        JP      M,L31D2         ; to DIV-LOOP\n\n        PUSH    AF              ;\n        JR      Z,L31E2         ; to DIV-START\n\n;\n;\n;\n;\n\n        LD      E,A             ;\n        LD      D,C             ;\n        EXX                     ;\n        LD      E,C             ;\n        LD      D,B             ;\n        POP     AF              ;\n        RR      B               ;\n        POP     AF              ;\n        RR      B               ;\n        EXX                     ;\n        POP     BC              ;\n        POP     HL              ;\n        LD      A,B             ;\n        SUB     C               ;\n        JP      L313D           ; jump back to DIVN-EXPT\n\n; ------------------------------------\n; Integer truncation towards zero ($3A)\n; ------------------------------------\n;\n;\n\n;; truncate\nL3214:  LD      A,(HL)          ;\n        AND     A               ;\n        RET     Z               ;\n\n        CP      $81             ;\n        JR      NC,L3221        ; to T-GR-ZERO\n\n        LD      (HL),$00        ;\n        LD      A,$20           ;\n        JR      L3272           ; to NIL-BYTES\n\n; ---\n\n;; T-GR-ZERO\nL3221:  CP      $91             ;\n        JR      NZ,L323F        ; to T-SMALL\n\n        INC     HL              ;\n        INC     HL              ;\n        INC     HL              ;\n        LD      A,$80           ;\n        AND     (HL)            ;\n        DEC     HL              ;\n        OR      (HL)            ;\n        DEC     HL              ;\n        JR      NZ,L3233        ; to T-FIRST\n\n        LD      A,$80           ;\n        XOR     (HL)            ;\n\n;; T-FIRST\nL3233:  DEC     HL              ;\n        JR      NZ,L326C        ; to T-EXPNENT\n\n        LD      (HL),A          ;\n        INC     HL              ;\n        LD      (HL),$FF        ;\n        DEC     HL              ;\n        LD      A,$18           ;\n        JR      L3272           ; to NIL-BYTES\n\n; ---\n\n;; T-SMALL\nL323F:  JR      NC,L326D        ; to X-LARGE\n\n        PUSH    DE              ;\n        CPL                     ;\n        ADD     A,$91           ;\n        INC     HL              ;\n        LD      D,(HL)          ;\n        INC     HL              ;\n        LD      E,(HL)          ;\n        DEC     HL              ;\n        DEC     HL              ;\n        LD      C,$00           ;\n        BIT     7,D             ;\n        JR      Z,L3252         ; to T-NUMERIC\n\n        DEC     C               ;\n\n;; T-NUMERIC\nL3252:  SET     7,D             ;\n        LD      B,$08           ;\n        SUB     B               ;\n        ADD     A,B             ;\n        JR      C,L325E         ; to T-TEST\n\n        LD      E,D             ;\n        LD      D,$00           ;\n        SUB     B               ;\n\n;; T-TEST\nL325E:  JR      Z,L3267         ; to T-STORE\n\n        LD      B,A             ;\n\n;; T-SHIFT\nL3261:  SRL     D               ;\n        RR      E               ;\n        DJNZ    L3261           ; to T-SHIFT\n\n;; T-STORE\nL3267:  CALL    L2D8E           ; routine INT-STORE\n        POP     DE              ;\n        RET                     ;\n\n; ---\n\n;; T-EXPNENT\nL326C:  LD      A,(HL)          ;\n\n;; X-LARGE\nL326D:  SUB     $A0             ;\n        RET     P               ;\n\n        NEG                     ; Negate\n\n;; NIL-BYTES\nL3272:  PUSH    DE              ;\n        EX      DE,HL           ;\n        DEC     HL              ;\n        LD      B,A             ;\n        SRL     B               ;\n        SRL     B               ;\n        SRL     B               ;\n        JR      Z,L3283         ; to BITS-ZERO\n\n;; BYTE-ZERO\nL327E:  LD      (HL),$00        ;\n        DEC     HL              ;\n        DJNZ    L327E           ; to BYTE-ZERO\n\n;; BITS-ZERO\nL3283:  AND     $07             ;\n        JR      Z,L3290         ; to IX-END\n\n        LD      B,A             ;\n        LD      A,$FF           ;\n\n;; LESS-MASK\nL328A:  SLA     A               ;\n        DJNZ    L328A           ; to LESS-MASK\n\n        AND     (HL)            ;\n        LD      (HL),A          ;\n\n;; IX-END\nL3290:  EX      DE,HL           ;\n        POP     DE              ;\n        RET                     ;\n\n; ----------------------------------\n; Storage of numbers in 5 byte form.\n; ==================================\n; Both integers and floating-point numbers can be stored in five bytes.\n; Zero is a special case stored as 5 zeros.\n; For integers the form is\n; Byte 1 - zero,\n; Byte 2 - sign byte, $00 +ve, $FF -ve.\n; Byte 3 - Low byte of integer.\n; Byte 4 - High byte\n; Byte 5 - unused but always zero.\n;\n; it seems unusual to store the low byte first but it is just as easy either\n; way. Statistically it just increases the chances of trailing zeros which\n; is an advantage elsewhere in saving ROM code.\n;\n;             zero     sign     low      high    unused\n; So +1 is  00000000 00000000 00000001 00000000 00000000\n;\n; and -1 is 00000000 11111111 11111111 11111111 00000000\n;\n; much of the arithmetic found in BASIC lines can be done using numbers\n; in this form using the Z80's 16 bit register operation ADD.\n; (multiplication is done by a sequence of additions).\n;\n; Storing -ve integers in two's complement form, means that they are ready for\n; addition and you might like to add the numbers above to prove that the\n; answer is zero. If, as in this case, the carry is set then that denotes that\n; the result is positive. This only applies when the signs don't match.\n; With positive numbers a carry denotes the result is out of integer range.\n; With negative numbers a carry denotes the result is within range.\n; The exception to the last rule is when the result is -65536\n;\n; Floating point form is an alternative method of storing numbers which can\n; be used for integers and larger (or fractional) numbers.\n;\n; In this form 1 is stored as\n;           10000001 00000000 00000000 00000000 00000000\n;\n; When a small integer is converted to a floating point number the last two\n; bytes are always blank so they are omitted in the following steps\n;\n; first make exponent +1 +16d  (bit 7 of the exponent is set if positive)\n\n; 10010001 00000000 00000001\n; 10010000 00000000 00000010 <-  now shift left and decrement exponent\n; ...\n; 10000010 01000000 00000000 <-  until a 1 abuts the imaginary point\n; 10000001 10000000 00000000     to the left of the mantissa.\n;\n; however since the leftmost bit of the mantissa is always set then it can\n; be used to denote the sign of the mantissa and put back when needed by the\n; PREP routines which gives\n;\n; 10000001 00000000 00000000\n\n; ----------------------------------------------\n; THE 'RE-STACK TWO \"SMALL\" INTEGERS' SUBROUTINE\n; ----------------------------------------------\n;   This routine is called to re-stack two numbers in full floating point form\n;   e.g. from mult when integer multiplication has overflowed.\n\n;; RE-ST-TWO\nL3293:  CALL    L3296           ; routine RESTK-SUB  below and continue\n                                ; into the routine to do the other one.\n\n;; RESTK-SUB\nL3296:  EX      DE,HL           ; swap pointers\n\n; ---------------------------------------------\n; THE 'RE-STACK ONE \"SMALL\" INTEGER' SUBROUTINE\n; ---------------------------------------------\n; (offset: $3D 're-stack')\n;   This routine re-stacks an integer, usually on the calculator stack, in full\n;   floating point form.  HL points to first byte.\n\n;; re-stack\nL3297:  LD      A,(HL)          ; Fetch Exponent byte to A\n        AND     A               ; test it\n        RET     NZ              ; return if not zero as already in full\n                                ; floating-point form.\n\n        PUSH    DE              ; preserve DE.\n        CALL    L2D7F           ; routine INT-FETCH\n                                ; integer to DE, sign to C.\n\n; HL points to 4th byte.\n\n        XOR     A               ; clear accumulator.\n        INC     HL              ; point to 5th.\n        LD      (HL),A          ; and blank.\n        DEC     HL              ; point to 4th.\n        LD      (HL),A          ; and blank.\n\n        LD      B,$91           ; set exponent byte +ve $81\n                                ; and imaginary dec point 16 bits to right\n                                ; of first bit.\n\n;   we could skip to normalize now but it's quicker to avoid normalizing\n;   through an empty D.\n\n        LD      A,D             ; fetch the high byte D\n        AND     A               ; is it zero ?\n        JR      NZ,L32B1        ; skip to RS-NRMLSE if not.\n\n        OR      E               ; low byte E to A and test for zero\n        LD      B,D             ; set B exponent to 0\n        JR      Z,L32BD         ; forward to RS-STORE if value is zero.\n\n        LD      D,E             ; transfer E to D\n        LD      E,B             ; set E to 0\n        LD      B,$89           ; reduce the initial exponent by eight.\n\n\n;; RS-NRMLSE\nL32B1:  EX      DE,HL           ; integer to HL, addr of 4th byte to DE.\n\n;; RSTK-LOOP\nL32B2:  DEC     B               ; decrease exponent\n        ADD     HL,HL           ; shift DE left\n        JR      NC,L32B2        ; loop back to RSTK-LOOP\n                                ; until a set bit pops into carry\n\n        RRC     C               ; now rotate the sign byte $00 or $FF\n                                ; into carry to give a sign bit\n\n        RR      H               ; rotate the sign bit to left of H\n        RR      L               ; rotate any carry into L\n\n        EX      DE,HL           ; address 4th byte, normalized int to DE\n\n;; RS-STORE\nL32BD:  DEC     HL              ; address 3rd byte\n        LD      (HL),E          ; place E\n        DEC     HL              ; address 2nd byte\n        LD      (HL),D          ; place D\n        DEC     HL              ; address 1st byte\n        LD      (HL),B          ; store the exponent\n\n        POP     DE              ; restore initial DE.\n        RET                     ; return.\n\n;****************************************\n;** Part 10. FLOATING-POINT CALCULATOR **\n;****************************************\n\n; As a general rule the calculator avoids using the IY register.\n; exceptions are val, val$ and str$.\n; So an assembly language programmer who has disabled interrupts to use\n; IY for other purposes can still use the calculator for mathematical\n; purposes.\n\n\n; ------------------------\n; THE 'TABLE OF CONSTANTS'\n; ------------------------\n;\n;\n\n; used 11 times\n;; stk-zero                                                 00 00 00 00 00\nL32C5:  DEFB    $00             ;;Bytes: 1\n        DEFB    $B0             ;;Exponent $00\n        DEFB    $00             ;;(+00,+00,+00)\n\n; used 19 times\n;; stk-one                                                  00 00 01 00 00\nL32C8:  DEFB    $40             ;;Bytes: 2\n        DEFB    $B0             ;;Exponent $00\n        DEFB    $00,$01         ;;(+00,+00)\n\n; used 9 times\n;; stk-half                                                 80 00 00 00 00\nL32CC:  DEFB    $30             ;;Exponent: $80, Bytes: 1\n        DEFB    $00             ;;(+00,+00,+00)\n\n; used 4 times.\n;; stk-pi/2                                                 81 49 0F DA A2\nL32CE:  DEFB    $F1             ;;Exponent: $81, Bytes: 4\n        DEFB    $49,$0F,$DA,$A2 ;;\n\n; used 3 times.\n;; stk-ten                                                  00 00 0A 00 00\nL32D3:  DEFB    $40             ;;Bytes: 2\n        DEFB    $B0             ;;Exponent $00\n        DEFB    $00,$0A         ;;(+00,+00)\n\n\n; ------------------------\n; THE 'TABLE OF ADDRESSES'\n; ------------------------\n;  \"Each problem that I solved became a rule which served afterwards to solve\n;   other problems\" - Rene Descartes 1596 - 1650.\n;\n;   Starts with binary operations which have two operands and one result.\n;   Three pseudo binary operations first.\n\n;; tbl-addrs\nL32D7:  DEFW    L368F           ; $00 Address: $368F - jump-true\n        DEFW    L343C           ; $01 Address: $343C - exchange\n        DEFW    L33A1           ; $02 Address: $33A1 - delete\n\n;   True binary operations.\n\n        DEFW    L300F           ; $03 Address: $300F - subtract\n        DEFW    L30CA           ; $04 Address: $30CA - multiply\n        DEFW    L31AF           ; $05 Address: $31AF - division\n        DEFW    L3851           ; $06 Address: $3851 - to-power\n        DEFW    L351B           ; $07 Address: $351B - or\n\n        DEFW    L3524           ; $08 Address: $3524 - no-&-no\n        DEFW    L353B           ; $09 Address: $353B - no-l-eql\n        DEFW    L353B           ; $0A Address: $353B - no-gr-eql\n        DEFW    L353B           ; $0B Address: $353B - nos-neql\n        DEFW    L353B           ; $0C Address: $353B - no-grtr\n        DEFW    L353B           ; $0D Address: $353B - no-less\n        DEFW    L353B           ; $0E Address: $353B - nos-eql\n        DEFW    L3014           ; $0F Address: $3014 - addition\n\n        DEFW    L352D           ; $10 Address: $352D - str-&-no\n        DEFW    L353B           ; $11 Address: $353B - str-l-eql\n        DEFW    L353B           ; $12 Address: $353B - str-gr-eql\n        DEFW    L353B           ; $13 Address: $353B - strs-neql\n        DEFW    L353B           ; $14 Address: $353B - str-grtr\n        DEFW    L353B           ; $15 Address: $353B - str-less\n        DEFW    L353B           ; $16 Address: $353B - strs-eql\n        DEFW    L359C           ; $17 Address: $359C - strs-add\n\n;   Unary follow.\n\n        DEFW    L35DE           ; $18 Address: $35DE - val$\n        DEFW    L34BC           ; $19 Address: $34BC - usr-$\n        DEFW    L3645           ; $1A Address: $3645 - read-in\n        DEFW    L346E           ; $1B Address: $346E - negate\n\n        DEFW    L3669           ; $1C Address: $3669 - code\n        DEFW    L35DE           ; $1D Address: $35DE - val\n        DEFW    L3674           ; $1E Address: $3674 - len\n        DEFW    L37B5           ; $1F Address: $37B5 - sin\n        DEFW    L37AA           ; $20 Address: $37AA - cos\n        DEFW    L37DA           ; $21 Address: $37DA - tan\n        DEFW    L3833           ; $22 Address: $3833 - asn\n        DEFW    L3843           ; $23 Address: $3843 - acs\n        DEFW    L37E2           ; $24 Address: $37E2 - atn\n        DEFW    L3713           ; $25 Address: $3713 - ln\n        DEFW    L36C4           ; $26 Address: $36C4 - exp\n        DEFW    L36AF           ; $27 Address: $36AF - int\n        DEFW    L384A           ; $28 Address: $384A - sqr\n        DEFW    L3492           ; $29 Address: $3492 - sgn\n        DEFW    L346A           ; $2A Address: $346A - abs\n        DEFW    L34AC           ; $2B Address: $34AC - peek\n        DEFW    L34A5           ; $2C Address: $34A5 - in\n        DEFW    L34B3           ; $2D Address: $34B3 - usr-no\n        DEFW    L361F           ; $2E Address: $361F - str$\n        DEFW    L35C9           ; $2F Address: $35C9 - chrs\n        DEFW    L3501           ; $30 Address: $3501 - not\n\n;   End of true unary.\n\n        DEFW    L33C0           ; $31 Address: $33C0 - duplicate\n        DEFW    L36A0           ; $32 Address: $36A0 - n-mod-m\n        DEFW    L3686           ; $33 Address: $3686 - jump\n        DEFW    L33C6           ; $34 Address: $33C6 - stk-data\n        DEFW    L367A           ; $35 Address: $367A - dec-jr-nz\n        DEFW    L3506           ; $36 Address: $3506 - less-0\n        DEFW    L34F9           ; $37 Address: $34F9 - greater-0\n        DEFW    L369B           ; $38 Address: $369B - end-calc\n        DEFW    L3783           ; $39 Address: $3783 - get-argt\n        DEFW    L3214           ; $3A Address: $3214 - truncate\n        DEFW    L33A2           ; $3B Address: $33A2 - fp-calc-2\n        DEFW    L2D4F           ; $3C Address: $2D4F - e-to-fp\n        DEFW    L3297           ; $3D Address: $3297 - re-stack\n\n;   The following are just the next available slots for the 128 compound\n;   literals which are in range $80 - $FF.\n\n        DEFW    L3449           ;     Address: $3449 - series-xx    $80 - $9F.\n        DEFW    L341B           ;     Address: $341B - stk-const-xx $A0 - $BF.\n        DEFW    L342D           ;     Address: $342D - st-mem-xx    $C0 - $DF.\n        DEFW    L340F           ;     Address: $340F - get-mem-xx   $E0 - $FF.\n\n;   Aside: 3E - 3F are therefore unused calculator literals.\n;   If the literal has to be also usable as a function then bits 6 and 7 are\n;   used to show type of arguments and result.\n\n; --------------\n; The Calculator\n; --------------\n;  \"A good calculator does not need artificial aids\"\n;  Lao Tze 604 - 531 B.C.\n\n;; CALCULATE\nL335B:  CALL    L35BF           ; routine STK-PNTRS is called to set up the\n                                ; calculator stack pointers for a default\n                                ; unary operation. HL = last value on stack.\n                                ; DE = STKEND first location after stack.\n\n; the calculate routine is called at this point by the series generator...\n\n;; GEN-ENT-1\nL335E:  LD      A,B             ; fetch the Z80 B register to A\n        LD      ($5C67),A       ; and store value in system variable BREG.\n                                ; this will be the counter for dec-jr-nz\n                                ; or if used from fp-calc2 the calculator\n                                ; instruction.\n\n; ... and again later at this point\n\n;; GEN-ENT-2\nL3362:  EXX                     ; switch sets\n        EX      (SP),HL         ; and store the address of next instruction,\n                                ; the return address, in H'L'.\n                                ; If this is a recursive call the H'L'\n                                ; of the previous invocation goes on stack.\n                                ; c.f. end-calc.\n        EXX                     ; switch back to main set\n\n; this is the re-entry looping point when handling a string of literals.\n\n;; RE-ENTRY\nL3365:  LD      ($5C65),DE      ; save end of stack in system variable STKEND\n        EXX                     ; switch to alt\n        LD      A,(HL)          ; get next literal\n        INC     HL              ; increase pointer'\n\n; single operation jumps back to here\n\n;; SCAN-ENT\nL336C:  PUSH    HL              ; save pointer on stack\n        AND     A               ; now test the literal\n        JP      P,L3380         ; forward to FIRST-3D if in range $00 - $3D\n                                ; anything with bit 7 set will be one of\n                                ; 128 compound literals.\n\n; compound literals have the following format.\n; bit 7 set indicates compound.\n; bits 6-5 the subgroup 0-3.\n; bits 4-0 the embedded parameter $00 - $1F.\n; The subgroup 0-3 needs to be manipulated to form the next available four\n; address places after the simple literals in the address table.\n\n        LD      D,A             ; save literal in D\n        AND     $60             ; and with 01100000 to isolate subgroup\n        RRCA                    ; rotate bits\n        RRCA                    ; 4 places to right\n        RRCA                    ; not five as we need offset * 2\n        RRCA                    ; 00000xx0\n        ADD     A,$7C           ; add ($3E * 2) to give correct offset.\n                                ; alter above if you add more literals.\n        LD      L,A             ; store in L for later indexing.\n        LD      A,D             ; bring back compound literal\n        AND     $1F             ; use mask to isolate parameter bits\n        JR      L338E           ; forward to ENT-TABLE\n\n; ---\n\n; the branch was here with simple literals.\n\n;; FIRST-3D\nL3380:  CP      $18             ; compare with first unary operations.\n        JR      NC,L338C        ; to DOUBLE-A with unary operations\n\n; it is binary so adjust pointers.\n\n        EXX                     ;\n        LD      BC,$FFFB        ; the value -5\n        LD      D,H             ; transfer HL, the last value, to DE.\n        LD      E,L             ;\n        ADD     HL,BC           ; subtract 5 making HL point to second\n                                ; value.\n        EXX                     ;\n\n;; DOUBLE-A\nL338C:  RLCA                    ; double the literal\n        LD      L,A             ; and store in L for indexing\n\n;; ENT-TABLE\nL338E:  LD      DE,L32D7        ; Address: tbl-addrs\n        LD      H,$00           ; prepare to index\n        ADD     HL,DE           ; add to get address of routine\n        LD      E,(HL)          ; low byte to E\n        INC     HL              ;\n        LD      D,(HL)          ; high byte to D\n        LD      HL,L3365        ; Address: RE-ENTRY\n        EX      (SP),HL         ; goes to stack\n        PUSH    DE              ; now address of routine\n        EXX                     ; main set\n                                ; avoid using IY register.\n        LD      BC,($5C66)      ; STKEND_hi\n                                ; nothing much goes to C but BREG to B\n                                ; and continue into next ret instruction\n                                ; which has a dual identity\n\n\n; ------------------\n; Handle delete (02)\n; ------------------\n; A simple return but when used as a calculator literal this\n; deletes the last value from the calculator stack.\n; On entry, as always with binary operations,\n; HL=first number, DE=second number\n; On exit, HL=result, DE=stkend.\n; So nothing to do\n\n;; delete\nL33A1:  RET                     ; return - indirect jump if from above.\n\n; ---------------------\n; Single operation (3B)\n; ---------------------\n;   This single operation is used, in the first instance, to evaluate most\n;   of the mathematical and string functions found in BASIC expressions.\n\n;; fp-calc-2\nL33A2:  POP     AF              ; drop return address.\n        LD      A,($5C67)       ; load accumulator from system variable BREG\n                                ; value will be literal e.g. 'tan'\n        EXX                     ; switch to alt\n        JR      L336C           ; back to SCAN-ENT\n                                ; next literal will be end-calc at L2758\n\n; ---------------------------------\n; THE 'TEST FIVE SPACES' SUBROUTINE\n; ---------------------------------\n;   This routine is called from MOVE-FP, STK-CONST and STK-STORE to test that\n;   there is enough space between the calculator stack and the machine stack\n;   for another five-byte value.  It returns with BC holding the value 5 ready\n;   for any subsequent LDIR.\n\n;; TEST-5-SP\nL33A9:  PUSH    DE              ; save\n        PUSH    HL              ; registers\n        LD      BC,$0005        ; an overhead of five bytes\n        CALL    L1F05           ; routine TEST-ROOM tests free RAM raising\n                                ; an error if not.\n        POP     HL              ; else restore\n        POP     DE              ; registers.\n        RET                     ; return with BC set at 5.\n\n; -----------------------------\n; THE 'STACK NUMBER' SUBROUTINE\n; -----------------------------\n;   This routine is called to stack a hidden floating point number found in\n;   a BASIC line.  It is also called to stack a numeric variable value, and\n;   from BEEP, to stack an entry in the semi-tone table.  It is not part of the\n;   calculator suite of routines.  On entry, HL points to the number to be\n;   stacked.\n\n;; STACK-NUM\nL33B4:  LD      DE,($5C65)      ; Load destination from STKEND system variable.\n\n        CALL    L33C0           ; Routine MOVE-FP puts on calculator stack\n                                ; with a memory check.\n        LD      ($5C65),DE      ; Set STKEND to next free location.\n\n        RET                     ; Return.\n\n; ---------------------------------\n; Move a floating point number (31)\n; ---------------------------------\n\n; This simple routine is a 5-byte LDIR instruction\n; that incorporates a memory check.\n; When used as a calculator literal it duplicates the last value on the\n; calculator stack.\n; Unary so on entry HL points to last value, DE to stkend\n\n;; duplicate\n;; MOVE-FP\nL33C0:  CALL    L33A9           ; routine TEST-5-SP test free memory\n                                ; and sets BC to 5.\n        LDIR                    ; copy the five bytes.\n        RET                     ; return with DE addressing new STKEND\n                                ; and HL addressing new last value.\n\n; -------------------\n; Stack literals ($34)\n; -------------------\n; When a calculator subroutine needs to put a value on the calculator\n; stack that is not a regular constant this routine is called with a\n; variable number of following data bytes that convey to the routine\n; the integer or floating point form as succinctly as is possible.\n\n;; stk-data\nL33C6:  LD      H,D             ; transfer STKEND\n        LD      L,E             ; to HL for result.\n\n;; STK-CONST\nL33C8:  CALL    L33A9           ; routine TEST-5-SP tests that room exists\n                                ; and sets BC to $05.\n\n        EXX                     ; switch to alternate set\n        PUSH    HL              ; save the pointer to next literal on stack\n        EXX                     ; switch back to main set\n\n        EX      (SP),HL         ; pointer to HL, destination to stack.\n\n        PUSH    BC              ; save BC - value 5 from test room ??.\n\n        LD      A,(HL)          ; fetch the byte following 'stk-data'\n        AND     $C0             ; isolate bits 7 and 6\n        RLCA                    ; rotate\n        RLCA                    ; to bits 1 and 0  range $00 - $03.\n        LD      C,A             ; transfer to C\n        INC     C               ; and increment to give number of bytes\n                                ; to read. $01 - $04\n        LD      A,(HL)          ; reload the first byte\n        AND     $3F             ; mask off to give possible exponent.\n        JR      NZ,L33DE        ; forward to FORM-EXP if it was possible to\n                                ; include the exponent.\n\n; else byte is just a byte count and exponent comes next.\n\n        INC     HL              ; address next byte and\n        LD      A,(HL)          ; pick up the exponent ( - $50).\n\n;; FORM-EXP\nL33DE:  ADD     A,$50           ; now add $50 to form actual exponent\n        LD      (DE),A          ; and load into first destination byte.\n        LD      A,$05           ; load accumulator with $05 and\n        SUB     C               ; subtract C to give count of trailing\n                                ; zeros plus one.\n        INC     HL              ; increment source\n        INC     DE              ; increment destination\n        LD      B,$00           ; prepare to copy\n        LDIR                    ; copy C bytes\n\n        POP     BC              ; restore 5 counter to BC ??.\n\n        EX      (SP),HL         ; put HL on stack as next literal pointer\n                                ; and the stack value - result pointer -\n                                ; to HL.\n\n        EXX                     ; switch to alternate set.\n        POP     HL              ; restore next literal pointer from stack\n                                ; to H'L'.\n        EXX                     ; switch back to main set.\n\n        LD      B,A             ; zero count to B\n        XOR     A               ; clear accumulator\n\n;; STK-ZEROS\nL33F1:  DEC     B               ; decrement B counter\n        RET     Z               ; return if zero.          >>\n                                ; DE points to new STKEND\n                                ; HL to new number.\n\n        LD      (DE),A          ; else load zero to destination\n        INC     DE              ; increase destination\n        JR      L33F1           ; loop back to STK-ZEROS until done.\n\n; -------------------------------\n; THE 'SKIP CONSTANTS' SUBROUTINE\n; -------------------------------\n;   This routine traverses variable-length entries in the table of constants,\n;   stacking intermediate, unwanted constants onto a dummy calculator stack,\n;   in the first five bytes of ROM.  The destination DE normally points to the\n;   end of the calculator stack which might be in the normal place or in the\n;   system variables area during E-LINE-NO; INT-TO-FP; stk-ten.  In any case,\n;   it would be simpler all round if the routine just shoved unwanted values\n;   where it is going to stick the wanted value.  The instruction LD DE, $0000\n;   can be removed.\n\n;; SKIP-CONS\nL33F7:  AND     A               ; test if initially zero.\n\n;; SKIP-NEXT\nL33F8:  RET     Z               ; return if zero.          >>\n\n        PUSH    AF              ; save count.\n        PUSH    DE              ; and normal STKEND\n\n        LD      DE,$0000        ; dummy value for STKEND at start of ROM\n                                ; Note. not a fault but this has to be\n                                ; moved elsewhere when running in RAM.\n                                ; e.g. with Expandor Systems 'Soft ROM'.\n                                ; Better still, write to the normal place.\n        CALL    L33C8           ; routine STK-CONST works through variable\n                                ; length records.\n\n        POP     DE              ; restore real STKEND\n        POP     AF              ; restore count\n        DEC     A               ; decrease\n        JR      L33F8           ; loop back to SKIP-NEXT\n\n; ------------------------------\n; THE 'LOCATE MEMORY' SUBROUTINE\n; ------------------------------\n;   This routine, when supplied with a base address in HL and an index in A,\n;   will calculate the address of the A'th entry, where each entry occupies\n;   five bytes.  It is used for reading the semi-tone table and addressing\n;   floating-point numbers in the calculator's memory area.\n;   It is not possible to use this routine for the table of constants as these\n;   six values are held in compressed format.\n\n;; LOC-MEM\nL3406:  LD      C,A             ; store the original number $00-$1F.\n        RLCA                    ; X2 - double.\n        RLCA                    ; X4 - quadruple.\n        ADD     A,C             ; X5 - now add original to multiply by five.\n\n        LD      C,A             ; place the result in the low byte.\n        LD      B,$00           ; set high byte to zero.\n        ADD     HL,BC           ; add to form address of start of number in HL.\n\n        RET                     ; return.\n\n; ------------------------------\n; Get from memory area ($E0 etc.)\n; ------------------------------\n; Literals $E0 to $FF\n; A holds $00-$1F offset.\n; The calculator stack increases by 5 bytes.\n\n;; get-mem-xx\nL340F:  PUSH    DE              ; save STKEND\n        LD      HL,($5C68)      ; MEM is base address of the memory cells.\n        CALL    L3406           ; routine LOC-MEM so that HL = first byte\n        CALL    L33C0           ; routine MOVE-FP moves 5 bytes with memory\n                                ; check.\n                                ; DE now points to new STKEND.\n        POP     HL              ; original STKEND is now RESULT pointer.\n        RET                     ; return.\n\n; --------------------------\n; Stack a constant (A0 etc.)\n; --------------------------\n; This routine allows a one-byte instruction to stack up to 32 constants\n; held in short form in a table of constants. In fact only 5 constants are\n; required. On entry the A register holds the literal ANDed with 1F.\n; It isn't very efficient and it would have been better to hold the\n; numbers in full, five byte form and stack them in a similar manner\n; to that used for semi-tone table values.\n\n;; stk-const-xx\nL341B:  LD      H,D             ; save STKEND - required for result\n        LD      L,E             ;\n        EXX                     ; swap\n        PUSH    HL              ; save pointer to next literal\n        LD      HL,L32C5        ; Address: stk-zero - start of table of\n                                ; constants\n        EXX                     ;\n        CALL    L33F7           ; routine SKIP-CONS\n        CALL    L33C8           ; routine STK-CONST\n        EXX                     ;\n        POP     HL              ; restore pointer to next literal.\n        EXX                     ;\n        RET                     ; return.\n\n; --------------------------------\n; Store in a memory area ($C0 etc.)\n; --------------------------------\n; Offsets $C0 to $DF\n; Although 32 memory storage locations can be addressed, only six\n; $C0 to $C5 are required by the ROM and only the thirty bytes (6*5)\n; required for these are allocated. Spectrum programmers who wish to\n; use the floating point routines from assembly language may wish to\n; alter the system variable MEM to point to 160 bytes of RAM to have\n; use the full range available.\n; A holds the derived offset $00-$1F.\n; This is a unary operation, so on entry HL points to the last value and DE\n; points to STKEND.\n\n;; st-mem-xx\nL342D:  PUSH    HL              ; save the result pointer.\n        EX      DE,HL           ; transfer to DE.\n        LD      HL,($5C68)      ; fetch MEM the base of memory area.\n        CALL    L3406           ; routine LOC-MEM sets HL to the destination.\n        EX      DE,HL           ; swap - HL is start, DE is destination.\n        CALL    L33C0           ; routine MOVE-FP.\n                                ; note. a short ld bc,5; ldir\n                                ; the embedded memory check is not required\n                                ; so these instructions would be faster.\n        EX      DE,HL           ; DE = STKEND\n        POP     HL              ; restore original result pointer\n        RET                     ; return.\n\n; -------------------------\n; THE 'EXCHANGE' SUBROUTINE\n; -------------------------\n; (offset: $01 'exchange')\n;   This routine swaps the last two values on the calculator stack.\n;   On entry, as always with binary operations,\n;   HL=first number, DE=second number\n;   On exit, HL=result, DE=stkend.\n\n;; exchange\nL343C:  LD      B,$05           ; there are five bytes to be swapped\n\n; start of loop.\n\n;; SWAP-BYTE\nL343E:  LD      A,(DE)          ; each byte of second\n        LD      C,(HL)          ; each byte of first\n        EX      DE,HL           ; swap pointers\n        LD      (DE),A          ; store each byte of first\n        LD      (HL),C          ; store each byte of second\n        INC     HL              ; advance both\n        INC     DE              ; pointers.\n        DJNZ    L343E           ; loop back to SWAP-BYTE until all 5 done.\n\n        EX      DE,HL           ; even up the exchanges so that DE addresses\n                                ; STKEND.\n\n        RET                     ; return.\n\n; ------------------------------\n; THE 'SERIES GENERATOR' ROUTINE\n; ------------------------------\n; (offset: $86 'series-06')\n; (offset: $88 'series-08')\n; (offset: $8C 'series-0C')\n;   The Spectrum uses Chebyshev polynomials to generate approximations for\n;   SIN, ATN, LN and EXP.  These are named after the Russian mathematician\n;   Pafnuty Chebyshev, born in 1821, who did much pioneering work on numerical\n;   series.  As far as calculators are concerned, Chebyshev polynomials have an\n;   advantage over other series, for example the Taylor series, as they can\n;   reach an approximation in just six iterations for SIN, eight for EXP and\n;   twelve for LN and ATN.  The mechanics of the routine are interesting but\n;   for full treatment of how these are generated with demonstrations in\n;   Sinclair BASIC see \"The Complete Spectrum ROM Disassembly\" by Dr Ian Logan\n;   and Dr Frank O'Hara, published 1983 by Melbourne House.\n\n;; series-xx\nL3449:  LD      B,A             ; parameter $00 - $1F to B counter\n        CALL    L335E           ; routine GEN-ENT-1 is called.\n                                ; A recursive call to a special entry point\n                                ; in the calculator that puts the B register\n                                ; in the system variable BREG. The return\n                                ; address is the next location and where\n                                ; the calculator will expect its first\n                                ; instruction - now pointed to by HL'.\n                                ; The previous pointer to the series of\n                                ; five-byte numbers goes on the machine stack.\n\n; The initialization phase.\n\n        DEFB    $31             ;;duplicate       x,x\n        DEFB    $0F             ;;addition        x+x\n        DEFB    $C0             ;;st-mem-0        x+x\n        DEFB    $02             ;;delete          .\n        DEFB    $A0             ;;stk-zero        0\n        DEFB    $C2             ;;st-mem-2        0\n\n; a loop is now entered to perform the algebraic calculation for each of\n; the numbers in the series\n\n;; G-LOOP\nL3453:  DEFB    $31             ;;duplicate       v,v.\n        DEFB    $E0             ;;get-mem-0       v,v,x+2\n        DEFB    $04             ;;multiply        v,v*x+2\n        DEFB    $E2             ;;get-mem-2       v,v*x+2,v\n        DEFB    $C1             ;;st-mem-1\n        DEFB    $03             ;;subtract\n        DEFB    $38             ;;end-calc\n\n; the previous pointer is fetched from the machine stack to H'L' where it\n; addresses one of the numbers of the series following the series literal.\n\n        CALL    L33C6           ; routine STK-DATA is called directly to\n                                ; push a value and advance H'L'.\n        CALL    L3362           ; routine GEN-ENT-2 recursively re-enters\n                                ; the calculator without disturbing\n                                ; system variable BREG\n                                ; H'L' value goes on the machine stack and is\n                                ; then loaded as usual with the next address.\n\n        DEFB    $0F             ;;addition\n        DEFB    $01             ;;exchange\n        DEFB    $C2             ;;st-mem-2\n        DEFB    $02             ;;delete\n\n        DEFB    $35             ;;dec-jr-nz\n        DEFB    $EE             ;;back to L3453, G-LOOP\n\n; when the counted loop is complete the final subtraction yields the result\n; for example SIN X.\n\n        DEFB    $E1             ;;get-mem-1\n        DEFB    $03             ;;subtract\n        DEFB    $38             ;;end-calc\n\n        RET                     ; return with H'L' pointing to location\n                                ; after last number in series.\n\n; ---------------------------------\n; THE 'ABSOLUTE MAGNITUDE' FUNCTION\n; ---------------------------------\n; (offset: $2A 'abs')\n;   This calculator literal finds the absolute value of the last value,\n;   integer or floating point, on calculator stack.\n\n;; abs\nL346A:  LD      B,$FF           ; signal abs\n        JR      L3474           ; forward to NEG-TEST\n\n; ---------------------------\n; THE 'UNARY MINUS' OPERATION\n; ---------------------------\n; (offset: $1B 'negate')\n;   Unary so on entry HL points to last value, DE to STKEND.\n\n;; NEGATE\n;; negate\nL346E:  CALL    L34E9           ; call routine TEST-ZERO and\n        RET     C               ; return if so leaving zero unchanged.\n\n        LD      B,$00           ; signal negate required before joining\n                                ; common code.\n\n;; NEG-TEST\nL3474:  LD      A,(HL)          ; load first byte and\n        AND     A               ; test for zero\n        JR      Z,L3483         ; forward to INT-CASE if a small integer\n\n; for floating point numbers a single bit denotes the sign.\n\n        INC     HL              ; address the first byte of mantissa.\n        LD      A,B             ; action flag $FF=abs, $00=neg.\n        AND     $80             ; now         $80      $00\n        OR      (HL)            ; sets bit 7 for abs\n        RLA                     ; sets carry for abs and if number negative\n        CCF                     ; complement carry flag\n        RRA                     ; and rotate back in altering sign\n        LD      (HL),A          ; put the altered adjusted number back\n        DEC     HL              ; HL points to result\n        RET                     ; return with DE unchanged\n\n; ---\n\n; for integer numbers an entire byte denotes the sign.\n\n;; INT-CASE\nL3483:  PUSH    DE              ; save STKEND.\n\n        PUSH    HL              ; save pointer to the last value/result.\n\n        CALL    L2D7F           ; routine INT-FETCH puts integer in DE\n                                ; and the sign in C.\n\n        POP     HL              ; restore the result pointer.\n\n        LD      A,B             ; $FF=abs, $00=neg\n        OR      C               ; $FF for abs, no change neg\n        CPL                     ; $00 for abs, switched for neg\n        LD      C,A             ; transfer result to sign byte.\n\n        CALL    L2D8E           ; routine INT-STORE to re-write the integer.\n\n        POP     DE              ; restore STKEND.\n        RET                     ; return.\n\n; ---------------------\n; THE 'SIGNUM' FUNCTION\n; ---------------------\n; (offset: $29 'sgn')\n;   This routine replaces the last value on the calculator stack,\n;   which may be in floating point or integer form, with the integer values\n;   zero if zero, with one if positive and  with -minus one if negative.\n\n;; sgn\nL3492:  CALL    L34E9           ; call routine TEST-ZERO and\n        RET     C               ; exit if so as no change is required.\n\n        PUSH    DE              ; save pointer to STKEND.\n\n        LD      DE,$0001        ; the result will be 1.\n        INC     HL              ; skip over the exponent.\n        RL      (HL)            ; rotate the sign bit into the carry flag.\n        DEC     HL              ; step back to point to the result.\n        SBC     A,A             ; byte will be $FF if negative, $00 if positive.\n        LD      C,A             ; store the sign byte in the C register.\n        CALL    L2D8E           ; routine INT-STORE to overwrite the last\n                                ; value with 0001 and sign.\n\n        POP     DE              ; restore STKEND.\n        RET                     ; return.\n\n; -----------------\n; THE 'IN' FUNCTION\n; -----------------\n; (offset: $2C 'in')\n;   This function reads a byte from an input port.\n\n;; in\nL34A5:  CALL    L1E99           ; Routine FIND-INT2 puts port address in BC.\n                                ; All 16 bits are put on the address line.\n\n        IN      A,(C)           ; Read the port.\n\n        JR      L34B0           ; exit to STACK-A (via IN-PK-STK to save a byte\n                                ; of instruction code).\n\n; -------------------\n; THE 'PEEK' FUNCTION\n; -------------------\n; (offset: $2B 'peek')\n;   This function returns the contents of a memory address.\n;   The entire address space can be peeked including the ROM.\n\n;; peek\nL34AC:  CALL    L1E99           ; routine FIND-INT2 puts address in BC.\n        LD      A,(BC)          ; load contents into A register.\n\n;; IN-PK-STK\nL34B0:  JP      L2D28           ; exit via STACK-A to put the value on the\n                                ; calculator stack.\n\n; ------------------\n; THE 'USR' FUNCTION\n; ------------------\n; (offset: $2d 'usr-no')\n;   The USR function followed by a number 0-65535 is the method by which\n;   the Spectrum invokes machine code programs. This function returns the\n;   contents of the BC register pair.\n;   Note. that STACK-BC re-initializes the IY register if a user-written\n;   program has altered it.\n\n;; usr-no\nL34B3:  CALL    L1E99           ; routine FIND-INT2 to fetch the\n                                ; supplied address into BC.\n\n        LD      HL,L2D2B        ; address: STACK-BC is\n        PUSH    HL              ; pushed onto the machine stack.\n        PUSH    BC              ; then the address of the machine code\n                                ; routine.\n\n        RET                     ; make an indirect jump to the routine\n                                ; and, hopefully, to STACK-BC also.\n\n; -------------------------\n; THE 'USR STRING' FUNCTION\n; -------------------------\n; (offset: $19 'usr-$')\n;   The user function with a one-character string argument, calculates the\n;   address of the User Defined Graphic character that is in the string.\n;   As an alternative, the ASCII equivalent, upper or lower case,\n;   may be supplied. This provides a user-friendly method of redefining\n;   the 21 User Definable Graphics e.g.\n;   POKE USR \"a\", BIN 10000000 will put a dot in the top left corner of the\n;   character 144.\n;   Note. the curious double check on the range. With 26 UDGs the first check\n;   only is necessary. With anything less the second check only is required.\n;   It is highly likely that the first check was written by Steven Vickers.\n\n;; usr-$\nL34BC:  CALL    L2BF1           ; routine STK-FETCH fetches the string\n                                ; parameters.\n        DEC     BC              ; decrease BC by\n        LD      A,B             ; one to test\n        OR      C               ; the length.\n        JR      NZ,L34E7        ; to REPORT-A if not a single character.\n\n        LD      A,(DE)          ; fetch the character\n        CALL    L2C8D           ; routine ALPHA sets carry if 'A-Z' or 'a-z'.\n        JR      C,L34D3         ; forward to USR-RANGE if ASCII.\n\n        SUB     $90             ; make UDGs range 0-20d\n        JR      C,L34E7         ; to REPORT-A if too low. e.g. usr \" \".\n\n        CP      $15             ; Note. this test is not necessary.\n        JR      NC,L34E7        ; to REPORT-A if higher than 20.\n\n        INC     A               ; make range 1-21d to match LSBs of ASCII\n\n;; USR-RANGE\nL34D3:  DEC     A               ; make range of bits 0-4 start at zero\n        ADD     A,A             ; multiply by eight\n        ADD     A,A             ; and lose any set bits\n        ADD     A,A             ; range now 0 - 25*8\n        CP      $A8             ; compare to 21*8\n        JR      NC,L34E7        ; to REPORT-A if originally higher\n                                ; than 'U','u' or graphics U.\n\n        LD      BC,($5C7B)      ; fetch the UDG system variable value.\n        ADD     A,C             ; add the offset to character\n        LD      C,A             ; and store back in register C.\n        JR      NC,L34E4        ; forward to USR-STACK if no overflow.\n\n        INC     B               ; increment high byte.\n\n;; USR-STACK\nL34E4:  JP      L2D2B           ; jump back and exit via STACK-BC to store\n\n; ---\n\n;; REPORT-A\nL34E7:  RST     08H             ; ERROR-1\n        DEFB    $09             ; Error Report: Invalid argument\n\n; ------------------------------\n; THE 'TEST FOR ZERO' SUBROUTINE\n; ------------------------------\n;   Test if top value on calculator stack is zero.  The carry flag is set if\n;   the last value is zero but no registers are altered.\n;   All five bytes will be zero but first four only need be tested.\n;   On entry, HL points to the exponent the first byte of the value.\n\n;; TEST-ZERO\nL34E9:  PUSH    HL              ; preserve HL which is used to address.\n        PUSH    BC              ; preserve BC which is used as a store.\n        LD      B,A             ; preserve A in B.\n\n        LD      A,(HL)          ; load first byte to accumulator\n        INC     HL              ; advance.\n        OR      (HL)            ; OR with second byte and clear carry.\n        INC     HL              ; advance.\n        OR      (HL)            ; OR with third byte.\n        INC     HL              ; advance.\n        OR      (HL)            ; OR with fourth byte.\n\n        LD      A,B             ; restore A without affecting flags.\n        POP     BC              ; restore the saved\n        POP     HL              ; registers.\n\n        RET     NZ              ; return if not zero and with carry reset.\n\n        SCF                     ; set the carry flag.\n        RET                     ; return with carry set if zero.\n\n; --------------------------------\n; THE 'GREATER THAN ZERO' OPERATOR\n; --------------------------------\n; (offset: $37 'greater-0' )\n;   Test if the last value on the calculator stack is greater than zero.\n;   This routine is also called directly from the end-tests of the comparison\n;   routine.\n\n;; GREATER-0\n;; greater-0\nL34F9:  CALL    L34E9           ; routine TEST-ZERO\n        RET     C               ; return if was zero as this\n                                ; is also the Boolean 'false' value.\n\n        LD      A,$FF           ; prepare XOR mask for sign bit\n        JR      L3507           ; forward to SIGN-TO-C\n                                ; to put sign in carry\n                                ; (carry will become set if sign is positive)\n                                ; and then overwrite location with 1 or 0\n                                ; as appropriate.\n\n; ------------------\n; THE 'NOT' FUNCTION\n; ------------------\n; (offset: $30 'not')\n;   This overwrites the last value with 1 if it was zero else with zero\n;   if it was any other value.\n;\n;   e.g. NOT 0 returns 1, NOT 1 returns 0, NOT -3 returns 0.\n;\n;   The subroutine is also called directly from the end-tests of the comparison\n;   operator.\n\n;; NOT\n;; not\nL3501:  CALL    L34E9           ; routine TEST-ZERO sets carry if zero\n\n        JR      L350B           ; to FP-0/1 to overwrite operand with\n                                ; 1 if carry is set else to overwrite with zero.\n\n; ------------------------------\n; THE 'LESS THAN ZERO' OPERATION\n; ------------------------------\n; (offset: $36 'less-0' )\n;   Destructively test if last value on calculator stack is less than zero.\n;   Bit 7 of second byte will be set if so.\n\n;; less-0\nL3506:  XOR     A               ; set XOR mask to zero\n                                ; (carry will become set if sign is negative).\n\n;   transfer sign of mantissa to Carry Flag.\n\n;; SIGN-TO-C\nL3507:  INC     HL              ; address 2nd byte.\n        XOR     (HL)            ; bit 7 of HL will be set if number is negative.\n        DEC     HL              ; address 1st byte again.\n        RLCA                    ; rotate bit 7 of A to carry.\n\n; ----------------------------\n; THE 'ZERO OR ONE' SUBROUTINE\n; ----------------------------\n;   This routine places an integer value of zero or one at the addressed\n;   location of the calculator stack or MEM area.  The value one is written if\n;   carry is set on entry else zero.\n\n;; FP-0/1\nL350B:  PUSH    HL              ; save pointer to the first byte\n        LD      A,$00           ; load accumulator with zero - without\n                                ; disturbing flags.\n        LD      (HL),A          ; zero to first byte\n        INC     HL              ; address next\n        LD      (HL),A          ; zero to 2nd byte\n        INC     HL              ; address low byte of integer\n        RLA                     ; carry to bit 0 of A\n        LD      (HL),A          ; load one or zero to low byte.\n        RRA                     ; restore zero to accumulator.\n        INC     HL              ; address high byte of integer.\n        LD      (HL),A          ; put a zero there.\n        INC     HL              ; address fifth byte.\n        LD      (HL),A          ; put a zero there.\n        POP     HL              ; restore pointer to the first byte.\n        RET                     ; return.\n\n; -----------------\n; THE 'OR' OPERATOR\n; -----------------\n; (offset: $07 'or' )\n; The Boolean OR operator. e.g. X OR Y\n; The result is zero if both values are zero else a non-zero value.\n;\n; e.g.    0 OR 0  returns 0.\n;        -3 OR 0  returns -3.\n;         0 OR -3 returns 1.\n;        -3 OR 2  returns 1.\n;\n; A binary operation.\n; On entry HL points to first operand (X) and DE to second operand (Y).\n\n;; or\nL351B:  EX      DE,HL           ; make HL point to second number\n        CALL    L34E9           ; routine TEST-ZERO\n        EX      DE,HL           ; restore pointers\n        RET     C               ; return if result was zero - first operand,\n                                ; now the last value, is the result.\n\n        SCF                     ; set carry flag\n        JR      L350B           ; back to FP-0/1 to overwrite the first operand\n                                ; with the value 1.\n\n\n; ---------------------------------\n; THE 'NUMBER AND NUMBER' OPERATION\n; ---------------------------------\n; (offset: $08 'no-&-no')\n;   The Boolean AND operator.\n;\n;   e.g.    -3 AND 2  returns -3.\n;           -3 AND 0  returns 0.\n;            0 and -2 returns 0.\n;            0 and 0  returns 0.\n;\n;   Compare with OR routine above.\n\n;; no-&-no\nL3524:  EX      DE,HL           ; make HL address second operand.\n\n        CALL    L34E9           ; routine TEST-ZERO sets carry if zero.\n\n        EX      DE,HL           ; restore pointers.\n        RET     NC              ; return if second non-zero, first is result.\n\n;\n\n        AND     A               ; else clear carry.\n        JR      L350B           ; back to FP-0/1 to overwrite first operand\n                                ; with zero for return value.\n\n; ---------------------------------\n; THE 'STRING AND NUMBER' OPERATION\n; ---------------------------------\n; (offset: $10 'str-&-no')\n;   e.g. \"You Win\" AND score>99 will return the string if condition is true\n;   or the null string if false.\n\n;; str-&-no\nL352D:  EX      DE,HL           ; make HL point to the number.\n        CALL    L34E9           ; routine TEST-ZERO.\n        EX      DE,HL           ; restore pointers.\n        RET     NC              ; return if number was not zero - the string\n                                ; is the result.\n\n;   if the number was zero (false) then the null string must be returned by\n;   altering the length of the string on the calculator stack to zero.\n\n        PUSH    DE              ; save pointer to the now obsolete number\n                                ; (which will become the new STKEND)\n\n        DEC     DE              ; point to the 5th byte of string descriptor.\n        XOR     A               ; clear the accumulator.\n        LD      (DE),A          ; place zero in high byte of length.\n        DEC     DE              ; address low byte of length.\n        LD      (DE),A          ; place zero there - now the null string.\n\n        POP     DE              ; restore pointer - new STKEND.\n        RET                     ; return.\n\n; ---------------------------\n; THE 'COMPARISON' OPERATIONS\n; ---------------------------\n; (offset: $0A 'no-gr-eql')\n; (offset: $0B 'nos-neql')\n; (offset: $0C 'no-grtr')\n; (offset: $0D 'no-less')\n; (offset: $0E 'nos-eql')\n; (offset: $11 'str-l-eql')\n; (offset: $12 'str-gr-eql')\n; (offset: $13 'strs-neql')\n; (offset: $14 'str-grtr')\n; (offset: $15 'str-less')\n; (offset: $16 'strs-eql')\n\n;   True binary operations.\n;   A single entry point is used to evaluate six numeric and six string\n;   comparisons. On entry, the calculator literal is in the B register and\n;   the two numeric values, or the two string parameters, are on the\n;   calculator stack.\n;   The individual bits of the literal are manipulated to group similar\n;   operations although the SUB 8 instruction does nothing useful and merely\n;   alters the string test bit.\n;   Numbers are compared by subtracting one from the other, strings are\n;   compared by comparing every character until a mismatch, or the end of one\n;   or both, is reached.\n;\n;   Numeric Comparisons.\n;   --------------------\n;   The 'x>y' example is the easiest as it employs straight-thru logic.\n;   Number y is subtracted from x and the result tested for greater-0 yielding\n;   a final value 1 (true) or 0 (false).\n;   For 'x<y' the same logic is used but the two values are first swapped on the\n;   calculator stack.\n;   For 'x=y' NOT is applied to the subtraction result yielding true if the\n;   difference was zero and false with anything else.\n;   The first three numeric comparisons are just the opposite of the last three\n;   so the same processing steps are used and then a final NOT is applied.\n;\n; literal    Test   No  sub 8       ExOrNot  1st RRCA  exch sub  ?   End-Tests\n; =========  ====   == ======== === ======== ========  ==== ===  =  === === ===\n; no-l-eql   x<=y   09 00000001 dec 00000000 00000000  ---- x-y  ?  --- >0? NOT\n; no-gr-eql  x>=y   0A 00000010 dec 00000001 10000000c swap y-x  ?  --- >0? NOT\n; nos-neql   x<>y   0B 00000011 dec 00000010 00000001  ---- x-y  ?  NOT --- NOT\n; no-grtr    x>y    0C 00000100  -  00000100 00000010  ---- x-y  ?  --- >0? ---\n; no-less    x<y    0D 00000101  -  00000101 10000010c swap y-x  ?  --- >0? ---\n; nos-eql    x=y    0E 00000110  -  00000110 00000011  ---- x-y  ?  NOT --- ---\n;\n;                                                           comp -> C/F\n;                                                           ====    ===\n; str-l-eql  x$<=y$ 11 00001001 dec 00001000 00000100  ---- x$y$ 0  !or >0? NOT\n; str-gr-eql x$>=y$ 12 00001010 dec 00001001 10000100c swap y$x$ 0  !or >0? NOT\n; strs-neql  x$<>y$ 13 00001011 dec 00001010 00000101  ---- x$y$ 0  !or >0? NOT\n; str-grtr   x$>y$  14 00001100  -  00001100 00000110  ---- x$y$ 0  !or >0? ---\n; str-less   x$<y$  15 00001101  -  00001101 10000110c swap y$x$ 0  !or >0? ---\n; strs-eql   x$=y$  16 00001110  -  00001110 00000111  ---- x$y$ 0  !or >0? ---\n;\n;   String comparisons are a little different in that the eql/neql carry flag\n;   from the 2nd RRCA is, as before, fed into the first of the end tests but\n;   along the way it gets modified by the comparison process. The result on the\n;   stack always starts off as zero and the carry fed in determines if NOT is\n;   applied to it. So the only time the greater-0 test is applied is if the\n;   stack holds zero which is not very efficient as the test will always yield\n;   zero. The most likely explanation is that there were once separate end tests\n;   for numbers and strings.\n\n;; no-l-eql,etc.\nL353B:  LD      A,B             ; transfer literal to accumulator.\n        SUB     $08             ; subtract eight - which is not useful.\n\n        BIT     2,A             ; isolate '>', '<', '='.\n\n        JR      NZ,L3543        ; skip to EX-OR-NOT with these.\n\n        DEC     A               ; else make $00-$02, $08-$0A to match bits 0-2.\n\n;; EX-OR-NOT\nL3543:  RRCA                    ; the first RRCA sets carry for a swap.\n        JR      NC,L354E        ; forward to NU-OR-STR with other 8 cases\n\n; for the other 4 cases the two values on the calculator stack are exchanged.\n\n        PUSH    AF              ; save A and carry.\n        PUSH    HL              ; save HL - pointer to first operand.\n                                ; (DE points to second operand).\n\n        CALL    L343C           ; routine exchange swaps the two values.\n                                ; (HL = second operand, DE = STKEND)\n\n        POP     DE              ; DE = first operand\n        EX      DE,HL           ; as we were.\n        POP     AF              ; restore A and carry.\n\n; Note. it would be better if the 2nd RRCA preceded the string test.\n; It would save two duplicate bytes and if we also got rid of that sub 8\n; at the beginning we wouldn't have to alter which bit we test.\n\n;; NU-OR-STR\nL354E:  BIT     2,A             ; test if a string comparison.\n        JR      NZ,L3559        ; forward to STRINGS if so.\n\n; continue with numeric comparisons.\n\n        RRCA                    ; 2nd RRCA causes eql/neql to set carry.\n        PUSH    AF              ; save A and carry\n\n        CALL    L300F           ; routine subtract leaves result on stack.\n        JR      L358C           ; forward to END-TESTS\n\n; ---\n\n;; STRINGS\nL3559:  RRCA                    ; 2nd RRCA causes eql/neql to set carry.\n        PUSH    AF              ; save A and carry.\n\n        CALL    L2BF1           ; routine STK-FETCH gets 2nd string params\n        PUSH    DE              ; save start2 *.\n        PUSH    BC              ; and the length.\n\n        CALL    L2BF1           ; routine STK-FETCH gets 1st string\n                                ; parameters - start in DE, length in BC.\n        POP     HL              ; restore length of second to HL.\n\n; A loop is now entered to compare, by subtraction, each corresponding character\n; of the strings. For each successful match, the pointers are incremented and\n; the lengths decreased and the branch taken back to here. If both string\n; remainders become null at the same time, then an exact match exists.\n\n;; BYTE-COMP\nL3564:  LD      A,H             ; test if the second string\n        OR      L               ; is the null string and hold flags.\n\n        EX      (SP),HL         ; put length2 on stack, bring start2 to HL *.\n        LD      A,B             ; hi byte of length1 to A\n\n        JR      NZ,L3575        ; forward to SEC-PLUS if second not null.\n\n        OR      C               ; test length of first string.\n\n;; SECND-LOW\nL356B:  POP     BC              ; pop the second length off stack.\n        JR      Z,L3572         ; forward to BOTH-NULL if first string is also\n                                ; of zero length.\n\n; the true condition - first is longer than second (SECND-LESS)\n\n        POP     AF              ; restore carry (set if eql/neql)\n        CCF                     ; complement carry flag.\n                                ; Note. equality becomes false.\n                                ; Inequality is true. By swapping or applying\n                                ; a terminal 'not', all comparisons have been\n                                ; manipulated so that this is success path.\n        JR      L3588           ; forward to leave via STR-TEST\n\n; ---\n; the branch was here with a match\n\n;; BOTH-NULL\nL3572:  POP     AF              ; restore carry - set for eql/neql\n        JR      L3588           ; forward to STR-TEST\n\n; ---\n; the branch was here when 2nd string not null and low byte of first is yet\n; to be tested.\n\n\n;; SEC-PLUS\nL3575:  OR      C               ; test the length of first string.\n        JR      Z,L3585         ; forward to FRST-LESS if length is zero.\n\n; both strings have at least one character left.\n\n        LD      A,(DE)          ; fetch character of first string.\n        SUB     (HL)            ; subtract with that of 2nd string.\n        JR      C,L3585         ; forward to FRST-LESS if carry set\n\n        JR      NZ,L356B        ; back to SECND-LOW and then STR-TEST\n                                ; if not exact match.\n\n        DEC     BC              ; decrease length of 1st string.\n        INC     DE              ; increment 1st string pointer.\n\n        INC     HL              ; increment 2nd string pointer.\n        EX      (SP),HL         ; swap with length on stack\n        DEC     HL              ; decrement 2nd string length\n        JR      L3564           ; back to BYTE-COMP\n\n; ---\n; the false condition.\n\n;; FRST-LESS\nL3585:  POP     BC              ; discard length\n        POP     AF              ; pop A\n        AND     A               ; clear the carry for false result.\n\n; ---\n; exact match and x$>y$ rejoin here\n\n;; STR-TEST\nL3588:  PUSH    AF              ; save A and carry\n\n        RST     28H             ;; FP-CALC\n        DEFB    $A0             ;;stk-zero      an initial false value.\n        DEFB    $38             ;;end-calc\n\n; both numeric and string paths converge here.\n\n;; END-TESTS\nL358C:  POP     AF              ; pop carry  - will be set if eql/neql\n        PUSH    AF              ; save it again.\n\n        CALL    C,L3501         ; routine NOT sets true(1) if equal(0)\n                                ; or, for strings, applies true result.\n\n        POP     AF              ; pop carry and\n        PUSH    AF              ; save A\n\n        CALL    NC,L34F9        ; routine GREATER-0 tests numeric subtraction\n                                ; result but also needlessly tests the string\n                                ; value for zero - it must be.\n\n        POP     AF              ; pop A\n        RRCA                    ; the third RRCA - test for '<=', '>=' or '<>'.\n        CALL    NC,L3501        ; apply a terminal NOT if so.\n        RET                     ; return.\n\n; ------------------------------------\n; THE 'STRING CONCATENATION' OPERATION\n; ------------------------------------\n; (offset: $17 'strs-add')\n;   This literal combines two strings into one e.g. LET a$ = b$ + c$\n;   The two parameters of the two strings to be combined are on the stack.\n\n;; strs-add\nL359C:  CALL    L2BF1           ; routine STK-FETCH fetches string parameters\n                                ; and deletes calculator stack entry.\n        PUSH    DE              ; save start address.\n        PUSH    BC              ; and length.\n\n        CALL    L2BF1           ; routine STK-FETCH for first string\n        POP     HL              ; re-fetch first length\n        PUSH    HL              ; and save again\n        PUSH    DE              ; save start of second string\n        PUSH    BC              ; and its length.\n\n        ADD     HL,BC           ; add the two lengths.\n        LD      B,H             ; transfer to BC\n        LD      C,L             ; and create\n        RST     30H             ; BC-SPACES in workspace.\n                                ; DE points to start of space.\n\n        CALL    L2AB2           ; routine STK-STO-$ stores parameters\n                                ; of new string updating STKEND.\n\n        POP     BC              ; length of first\n        POP     HL              ; address of start\n        LD      A,B             ; test for\n        OR      C               ; zero length.\n        JR      Z,L35B7         ; to OTHER-STR if null string\n\n        LDIR                    ; copy string to workspace.\n\n;; OTHER-STR\nL35B7:  POP     BC              ; now second length\n        POP     HL              ; and start of string\n        LD      A,B             ; test this one\n        OR      C               ; for zero length\n        JR      Z,L35BF         ; skip forward to STK-PNTRS if so as complete.\n\n        LDIR                    ; else copy the bytes.\n                                ; and continue into next routine which\n                                ; sets the calculator stack pointers.\n\n; -----------------------------------\n; THE 'SET STACK POINTERS' SUBROUTINE\n; -----------------------------------\n;   Register DE is set to STKEND and HL, the result pointer, is set to five\n;   locations below this.\n;   This routine is used when it is inconvenient to save these values at the\n;   time the calculator stack is manipulated due to other activity on the\n;   machine stack.\n;   This routine is also used to terminate the VAL and READ-IN  routines for\n;   the same reason and to initialize the calculator stack at the start of\n;   the CALCULATE routine.\n\n;; STK-PNTRS\nL35BF:  LD      HL,($5C65)      ; fetch STKEND value from system variable.\n        LD      DE,$FFFB        ; the value -5\n        PUSH    HL              ; push STKEND value.\n\n        ADD     HL,DE           ; subtract 5 from HL.\n\n        POP     DE              ; pop STKEND to DE.\n        RET                     ; return.\n\n; -------------------\n; THE 'CHR$' FUNCTION\n; -------------------\n; (offset: $2f 'chr$')\n;   This function returns a single character string that is a result of\n;   converting a number in the range 0-255 to a string e.g. CHR$ 65 = \"A\".\n\n;; chrs\nL35C9:  CALL    L2DD5           ; routine FP-TO-A puts the number in A.\n\n        JR      C,L35DC         ; forward to REPORT-Bd if overflow\n        JR      NZ,L35DC        ; forward to REPORT-Bd if negative\n\n        PUSH    AF              ; save the argument.\n\n        LD      BC,$0001        ; one space required.\n        RST     30H             ; BC-SPACES makes DE point to start\n\n        POP     AF              ; restore the number.\n\n        LD      (DE),A          ; and store in workspace\n\n        CALL    L2AB2           ; routine STK-STO-$ stacks descriptor.\n\n        EX      DE,HL           ; make HL point to result and DE to STKEND.\n        RET                     ; return.\n\n; ---\n\n;; REPORT-Bd\nL35DC:  RST     08H             ; ERROR-1\n        DEFB    $0A             ; Error Report: Integer out of range\n\n; ----------------------------\n; THE 'VAL and VAL$' FUNCTIONS\n; ----------------------------\n; (offset: $1d 'val')\n; (offset: $18 'val$')\n;   VAL treats the characters in a string as a numeric expression.\n;   e.g. VAL \"2.3\" = 2.3, VAL \"2+4\" = 6, VAL (\"2\" + \"4\") = 24.\n;   VAL$ treats the characters in a string as a string expression.\n;   e.g. VAL$ (z$+\"(2)\") = a$(2) if z$ happens to be \"a$\".\n\n;; val\n;; val$\nL35DE:  LD      HL,($5C5D)      ; fetch value of system variable CH_ADD\n        PUSH    HL              ; and save on the machine stack.\n        LD      A,B             ; fetch the literal (either $1D or $18).\n        ADD     A,$E3           ; add $E3 to form $00 (setting carry) or $FB.\n        SBC     A,A             ; now form $FF bit 6 = numeric result\n                                ; or $00 bit 6 = string result.\n        PUSH    AF              ; save this mask on the stack\n\n        CALL    L2BF1           ; routine STK-FETCH fetches the string operand\n                                ; from calculator stack.\n\n        PUSH    DE              ; save the address of the start of the string.\n        INC     BC              ; increment the length for a carriage return.\n\n        RST     30H             ; BC-SPACES creates the space in workspace.\n        POP     HL              ; restore start of string to HL.\n        LD      ($5C5D),DE      ; load CH_ADD with start DE in workspace.\n\n        PUSH    DE              ; save the start in workspace\n        LDIR                    ; copy string from program or variables or\n                                ; workspace to the workspace area.\n        EX      DE,HL           ; end of string + 1 to HL\n        DEC     HL              ; decrement HL to point to end of new area.\n        LD      (HL),$0D        ; insert a carriage return at end.\n        RES     7,(IY+$01)      ; update FLAGS  - signal checking syntax.\n        CALL    L24FB           ; routine SCANNING evaluates string\n                                ; expression and result.\n\n        RST     18H             ; GET-CHAR fetches next character.\n        CP      $0D             ; is it the expected carriage return ?\n        JR      NZ,L360C        ; forward to V-RPORT-C if not\n                                ; 'Nonsense in BASIC'.\n\n        POP     HL              ; restore start of string in workspace.\n        POP     AF              ; restore expected result flag (bit 6).\n        XOR     (IY+$01)        ; xor with FLAGS now updated by SCANNING.\n        AND     $40             ; test bit 6 - should be zero if result types\n                                ; match.\n\n;; V-RPORT-C\nL360C:  JP      NZ,L1C8A        ; jump back to REPORT-C with a result mismatch.\n\n        LD      ($5C5D),HL      ; set CH_ADD to the start of the string again.\n        SET     7,(IY+$01)      ; update FLAGS  - signal running program.\n        CALL    L24FB           ; routine SCANNING evaluates the string\n                                ; in full leaving result on calculator stack.\n\n        POP     HL              ; restore saved character address in program.\n        LD      ($5C5D),HL      ; and reset the system variable CH_ADD.\n\n        JR      L35BF           ; back to exit via STK-PNTRS.\n                                ; resetting the calculator stack pointers\n                                ; HL and DE from STKEND as it wasn't possible\n                                ; to preserve them during this routine.\n\n; -------------------\n; THE 'STR$' FUNCTION\n; -------------------\n; (offset: $2e 'str$')\n;   This function produces a string comprising the characters that would appear\n;   if the numeric argument were printed.\n;   e.g. STR$ (1/10) produces \"0.1\".\n\n;; str$\nL361F:  LD      BC,$0001        ; create an initial byte in workspace\n        RST     30H             ; using BC-SPACES restart.\n\n        LD      ($5C5B),HL      ; set system variable K_CUR to new location.\n        PUSH    HL              ; and save start on machine stack also.\n\n        LD      HL,($5C51)      ; fetch value of system variable CURCHL\n        PUSH    HL              ; and save that too.\n\n        LD      A,$FF           ; select system channel 'R'.\n        CALL    L1601           ; routine CHAN-OPEN opens it.\n        CALL    L2DE3           ; routine PRINT-FP outputs the number to\n                                ; workspace updating K-CUR.\n\n        POP     HL              ; restore current channel.\n        CALL    L1615           ; routine CHAN-FLAG resets flags.\n\n        POP     DE              ; fetch saved start of string to DE.\n        LD      HL,($5C5B)      ; load HL with end of string from K_CUR.\n\n        AND     A               ; prepare for true subtraction.\n        SBC     HL,DE           ; subtract start from end to give length.\n        LD      B,H             ; transfer the length to\n        LD      C,L             ; the BC register pair.\n\n        CALL    L2AB2           ; routine STK-STO-$ stores string parameters\n                                ; on the calculator stack.\n\n        EX      DE,HL           ; HL = last value, DE = STKEND.\n        RET                     ; return.\n\n; ------------------------\n; THE 'READ-IN' SUBROUTINE\n; ------------------------\n; (offset: $1a 'read-in')\n;   This is the calculator literal used by the INKEY$ function when a '#'\n;   is encountered after the keyword.\n;   INKEY$ # does not interact correctly with the keyboard, #0 or #1, and\n;   its uses are for other channels.\n\n;; read-in\nL3645:  CALL    L1E94           ; routine FIND-INT1 fetches stream to A\n        CP      $10             ; compare with 16 decimal.\n        JP      NC,L1E9F        ; JUMP to REPORT-Bb if not in range 0 - 15.\n                                ; 'Integer out of range'\n                                ; (REPORT-Bd is within range)\n\n        LD      HL,($5C51)      ; fetch current channel CURCHL\n        PUSH    HL              ; save it\n\n        CALL    L1601           ; routine CHAN-OPEN opens channel\n\n        CALL    L15E6           ; routine INPUT-AD - the channel must have an\n                                ; input stream or else error here from stream\n                                ; stub.\n        LD      BC,$0000        ; initialize length of string to zero\n        JR      NC,L365F        ; forward to R-I-STORE if no key detected.\n\n        INC     C               ; increase length to one.\n\n        RST     30H             ; BC-SPACES creates space for one character\n                                ; in workspace.\n        LD      (DE),A          ; the character is inserted.\n\n;; R-I-STORE\nL365F:  CALL    L2AB2           ; routine STK-STO-$ stacks the string\n                                ; parameters.\n        POP     HL              ; restore current channel address\n\n        CALL    L1615           ; routine CHAN-FLAG resets current channel\n                                ; system variable and flags.\n\n        JP      L35BF           ; jump back to STK-PNTRS\n\n; -------------------\n; THE 'CODE' FUNCTION\n; -------------------\n; (offset: $1c 'code')\n;   Returns the ASCII code of a character or first character of a string\n;   e.g. CODE \"Aardvark\" = 65, CODE \"\" = 0.\n\n;; code\nL3669:  CALL    L2BF1           ; routine STK-FETCH to fetch and delete the\n                                ; string parameters.\n                                ; DE points to the start, BC holds the length.\n\n        LD      A,B             ; test length\n        OR      C               ; of the string.\n        JR      Z,L3671         ; skip to STK-CODE with zero if the null string.\n\n        LD      A,(DE)          ; else fetch the first character.\n\n;; STK-CODE\nL3671:  JP      L2D28           ; jump back to STACK-A (with memory check)\n\n; ------------------\n; THE 'LEN' FUNCTION\n; ------------------\n; (offset: $1e 'len')\n;   Returns the length of a string.\n;   In Sinclair BASIC strings can be more than twenty thousand characters long\n;   so a sixteen-bit register is required to store the length\n\n;; len\nL3674:  CALL    L2BF1           ; Routine STK-FETCH to fetch and delete the\n                                ; string parameters from the calculator stack.\n                                ; Register BC now holds the length of string.\n\n        JP      L2D2B           ; Jump back to STACK-BC to save result on the\n                                ; calculator stack (with memory check).\n\n; -------------------------------------\n; THE 'DECREASE THE COUNTER' SUBROUTINE\n; -------------------------------------\n; (offset: $35 'dec-jr-nz')\n;   The calculator has an instruction that decrements a single-byte\n;   pseudo-register and makes consequential relative jumps just like\n;   the Z80's DJNZ instruction.\n\n;; dec-jr-nz\nL367A:  EXX                     ; switch in set that addresses code\n\n        PUSH    HL              ; save pointer to offset byte\n        LD      HL,$5C67        ; address BREG in system variables\n        DEC     (HL)            ; decrement it\n        POP     HL              ; restore pointer\n\n        JR      NZ,L3687        ; to JUMP-2 if not zero\n\n        INC     HL              ; step past the jump length.\n        EXX                     ; switch in the main set.\n        RET                     ; return.\n\n; Note. as a general rule the calculator avoids using the IY register\n; otherwise the cumbersome 4 instructions in the middle could be replaced by\n; dec (iy+$2d) - three bytes instead of six.\n\n\n; ---------------------\n; THE 'JUMP' SUBROUTINE\n; ---------------------\n; (offset: $33 'jump')\n;   This enables the calculator to perform relative jumps just like the Z80\n;   chip's JR instruction.\n\n;; jump\n;; JUMP\nL3686:  EXX                     ; switch in pointer set\n\n;; JUMP-2\nL3687:  LD      E,(HL)          ; the jump byte 0-127 forward, 128-255 back.\n        LD      A,E             ; transfer to accumulator.\n        RLA                     ; if backward jump, carry is set.\n        SBC     A,A             ; will be $FF if backward or $00 if forward.\n        LD      D,A             ; transfer to high byte.\n        ADD     HL,DE           ; advance calculator pointer forward or back.\n\n        EXX                     ; switch back.\n        RET                     ; return.\n\n; --------------------------\n; THE 'JUMP-TRUE' SUBROUTINE\n; --------------------------\n; (offset: $00 'jump-true')\n;   This enables the calculator to perform conditional relative jumps dependent\n;   on whether the last test gave a true result.\n\n;; jump-true\nL368F:  INC     DE              ; Collect the\n        INC     DE              ; third byte\n        LD      A,(DE)          ; of the test\n        DEC     DE              ; result and\n        DEC     DE              ; backtrack.\n\n        AND     A               ; Is result 0 or 1 ?\n        JR      NZ,L3686        ; Back to JUMP if true (1).\n\n        EXX                     ; Else switch in the pointer set.\n        INC     HL              ; Step past the jump length.\n        EXX                     ; Switch in the main set.\n        RET                     ; Return.\n\n; -------------------------\n; THE 'END-CALC' SUBROUTINE\n; -------------------------\n; (offset: $38 'end-calc')\n;   The end-calc literal terminates a mini-program written in the Spectrum's\n;   internal language.\n\n;; end-calc\nL369B:  POP     AF              ; Drop the calculator return address RE-ENTRY\n        EXX                     ; Switch to the other set.\n\n        EX      (SP),HL         ; Transfer H'L' to machine stack for the\n                                ; return address.\n                                ; When exiting recursion, then the previous\n                                ; pointer is transferred to H'L'.\n\n        EXX                     ; Switch back to main set.\n        RET                     ; Return.\n\n\n; ------------------------\n; THE 'MODULUS' SUBROUTINE\n; ------------------------\n; (offset: $32 'n-mod-m')\n; (n1,n2 -- r,q)\n;   Similar to FORTH's 'divide mod' /MOD\n;   On the Spectrum, this is only used internally by the RND function and could\n;   have been implemented inline.  On the ZX81, this calculator routine was also\n;   used by PRINT-FP.\n\n;; n-mod-m\nL36A0:  RST     28H             ;; FP-CALC          17, 3.\n        DEFB    $C0             ;;st-mem-0          17, 3.\n        DEFB    $02             ;;delete            17.\n        DEFB    $31             ;;duplicate         17, 17.\n        DEFB    $E0             ;;get-mem-0         17, 17, 3.\n        DEFB    $05             ;;division          17, 17/3.\n        DEFB    $27             ;;int               17, 5.\n        DEFB    $E0             ;;get-mem-0         17, 5, 3.\n        DEFB    $01             ;;exchange          17, 3, 5.\n        DEFB    $C0             ;;st-mem-0          17, 3, 5.\n        DEFB    $04             ;;multiply          17, 15.\n        DEFB    $03             ;;subtract          2.\n        DEFB    $E0             ;;get-mem-0         2, 5.\n        DEFB    $38             ;;end-calc          2, 5.\n\n        RET                     ; return.\n\n\n; ------------------\n; THE 'INT' FUNCTION\n; ------------------\n; (offset $27: 'int' )\n; This function returns the integer of x, which is just the same as truncate\n; for positive numbers. The truncate literal truncates negative numbers\n; upwards so that -3.4 gives -3 whereas the BASIC INT function has to\n; truncate negative numbers down so that INT -3.4 is -4.\n; It is best to work through using, say, +-3.4 as examples.\n\n;; int\nL36AF:  RST     28H             ;; FP-CALC              x.    (= 3.4 or -3.4).\n        DEFB    $31             ;;duplicate             x, x.\n        DEFB    $36             ;;less-0                x, (1/0)\n        DEFB    $00             ;;jump-true             x, (1/0)\n        DEFB    $04             ;;to L36B7, X-NEG\n\n        DEFB    $3A             ;;truncate              trunc 3.4 = 3.\n        DEFB    $38             ;;end-calc              3.\n\n        RET                     ; return with + int x on stack.\n\n; ---\n\n\n;; X-NEG\nL36B7:  DEFB    $31             ;;duplicate             -3.4, -3.4.\n        DEFB    $3A             ;;truncate              -3.4, -3.\n        DEFB    $C0             ;;st-mem-0              -3.4, -3.\n        DEFB    $03             ;;subtract              -.4\n        DEFB    $E0             ;;get-mem-0             -.4, -3.\n        DEFB    $01             ;;exchange              -3, -.4.\n        DEFB    $30             ;;not                   -3, (0).\n        DEFB    $00             ;;jump-true             -3.\n        DEFB    $03             ;;to L36C2, EXIT        -3.\n\n        DEFB    $A1             ;;stk-one               -3, 1.\n        DEFB    $03             ;;subtract              -4.\n\n;; EXIT\nL36C2:  DEFB    $38             ;;end-calc              -4.\n\n        RET                     ; return.\n\n\n; ------------------\n; THE 'EXP' FUNCTION\n; ------------------\n; (offset $26: 'exp')\n;   The exponential function EXP x is equal to e^x, where e is the mathematical\n;   name for a number approximated to 2.718281828.\n;   ERROR 6 if argument is more than about 88.\n\n;; EXP\n;; exp\nL36C4:  RST     28H             ;; FP-CALC\n        DEFB    $3D             ;;re-stack      (not required - mult will do)\n        DEFB    $34             ;;stk-data\n        DEFB    $F1             ;;Exponent: $81, Bytes: 4\n        DEFB    $38,$AA,$3B,$29 ;;\n        DEFB    $04             ;;multiply\n        DEFB    $31             ;;duplicate\n        DEFB    $27             ;;int\n        DEFB    $C3             ;;st-mem-3\n        DEFB    $03             ;;subtract\n        DEFB    $31             ;;duplicate\n        DEFB    $0F             ;;addition\n        DEFB    $A1             ;;stk-one\n        DEFB    $03             ;;subtract\n        DEFB    $88             ;;series-08\n        DEFB    $13             ;;Exponent: $63, Bytes: 1\n        DEFB    $36             ;;(+00,+00,+00)\n        DEFB    $58             ;;Exponent: $68, Bytes: 2\n        DEFB    $65,$66         ;;(+00,+00)\n        DEFB    $9D             ;;Exponent: $6D, Bytes: 3\n        DEFB    $78,$65,$40     ;;(+00)\n        DEFB    $A2             ;;Exponent: $72, Bytes: 3\n        DEFB    $60,$32,$C9     ;;(+00)\n        DEFB    $E7             ;;Exponent: $77, Bytes: 4\n        DEFB    $21,$F7,$AF,$24 ;;\n        DEFB    $EB             ;;Exponent: $7B, Bytes: 4\n        DEFB    $2F,$B0,$B0,$14 ;;\n        DEFB    $EE             ;;Exponent: $7E, Bytes: 4\n        DEFB    $7E,$BB,$94,$58 ;;\n        DEFB    $F1             ;;Exponent: $81, Bytes: 4\n        DEFB    $3A,$7E,$F8,$CF ;;\n        DEFB    $E3             ;;get-mem-3\n        DEFB    $38             ;;end-calc\n\n        CALL    L2DD5           ; routine FP-TO-A\n        JR      NZ,L3705        ; to N-NEGTV\n\n        JR      C,L3703         ; to REPORT-6b\n                                ; 'Number too big'\n\n        ADD     A,(HL)          ;\n        JR      NC,L370C        ; to RESULT-OK\n\n\n;; REPORT-6b\nL3703:  RST     08H             ; ERROR-1\n        DEFB    $05             ; Error Report: Number too big\n\n; ---\n\n;; N-NEGTV\nL3705:  JR      C,L370E         ; to RSLT-ZERO\n\n        SUB     (HL)            ;\n        JR      NC,L370E        ; to RSLT-ZERO\n\n        NEG                     ; Negate\n\n;; RESULT-OK\nL370C:  LD      (HL),A          ;\n        RET                     ; return.\n\n; ---\n\n\n;; RSLT-ZERO\nL370E:  RST     28H             ;; FP-CALC\n        DEFB    $02             ;;delete\n        DEFB    $A0             ;;stk-zero\n        DEFB    $38             ;;end-calc\n\n        RET                     ; return.\n\n\n; --------------------------------\n; THE 'NATURAL LOGARITHM' FUNCTION\n; --------------------------------\n; (offset $25: 'ln')\n;   Function to calculate the natural logarithm (to the base e ).\n;   Natural logarithms were devised in 1614 by well-traveled Scotsman John\n;   Napier who noted\n;   \"Nothing doth more molest and hinder calculators than the multiplications,\n;    divisions, square and cubical extractions of great numbers\".\n;\n;   Napier's logarithms enabled the above operations to be accomplished by\n;   simple addition and subtraction simplifying the navigational and\n;   astronomical calculations which beset his age.\n;   Napier's logarithms were quickly overtaken by logarithms to the base 10\n;   devised, in conjunction with Napier, by Henry Briggs a Cambridge-educated\n;   professor of Geometry at Oxford University. These simplified the layout\n;   of the tables enabling humans to easily scale calculations.\n;\n;   It is only recently with the introduction of pocket calculators and machines\n;   like the ZX Spectrum that natural logarithms are once more at the fore,\n;   although some computers retain logarithms to the base ten.\n;\n;   'Natural' logarithms are powers to the base 'e', which like 'pi' is a\n;   naturally occurring number in branches of mathematics.\n;   Like 'pi' also, 'e' is an irrational number and starts 2.718281828...\n;\n;   The tabular use of logarithms was that to multiply two numbers one looked\n;   up their two logarithms in the tables, added them together and then looked\n;   for the result in a table of antilogarithms to give the desired product.\n;\n;   The EXP function is the BASIC equivalent of a calculator's 'antiln' function\n;   and by picking any two numbers, 1.72 and 6.89 say,\n;     10 PRINT EXP ( LN 1.72 + LN 6.89 )\n;   will give just the same result as\n;     20 PRINT 1.72 * 6.89.\n;   Division is accomplished by subtracting the two logs.\n;\n;   Napier also mentioned \"square and cubicle extractions\".\n;   To raise a number to the power 3, find its 'ln', multiply by 3 and find the\n;   'antiln'.  e.g. PRINT EXP( LN 4 * 3 )  gives 64.\n;   Similarly to find the n'th root divide the logarithm by 'n'.\n;   The ZX81 ROM used PRINT EXP ( LN 9 / 2 ) to find the square root of the\n;   number 9. The Napieran square root function is just a special case of\n;   the 'to_power' function. A cube root or indeed any root/power would be just\n;   as simple.\n\n;   First test that the argument to LN is a positive, non-zero number.\n;   Error A if the argument is 0 or negative.\n\n;; ln\nL3713:  RST     28H             ;; FP-CALC\n        DEFB    $3D             ;;re-stack\n        DEFB    $31             ;;duplicate\n        DEFB    $37             ;;greater-0\n        DEFB    $00             ;;jump-true\n        DEFB    $04             ;;to L371C, VALID\n\n        DEFB    $38             ;;end-calc\n\n\n;; REPORT-Ab\nL371A:  RST     08H             ; ERROR-1\n        DEFB    $09             ; Error Report: Invalid argument\n\n;; VALID\nL371C:  DEFB    $A0             ;;stk-zero              Note. not\n        DEFB    $02             ;;delete                necessary.\n        DEFB    $38             ;;end-calc\n        LD      A,(HL)          ;\n\n        LD      (HL),$80        ;\n        CALL    L2D28           ; routine STACK-A\n\n        RST     28H             ;; FP-CALC\n        DEFB    $34             ;;stk-data\n        DEFB    $38             ;;Exponent: $88, Bytes: 1\n        DEFB    $00             ;;(+00,+00,+00)\n        DEFB    $03             ;;subtract\n        DEFB    $01             ;;exchange\n        DEFB    $31             ;;duplicate\n        DEFB    $34             ;;stk-data\n        DEFB    $F0             ;;Exponent: $80, Bytes: 4\n        DEFB    $4C,$CC,$CC,$CD ;;\n        DEFB    $03             ;;subtract\n        DEFB    $37             ;;greater-0\n        DEFB    $00             ;;jump-true\n        DEFB    $08             ;;to L373D, GRE.8\n\n        DEFB    $01             ;;exchange\n        DEFB    $A1             ;;stk-one\n        DEFB    $03             ;;subtract\n        DEFB    $01             ;;exchange\n        DEFB    $38             ;;end-calc\n\n        INC     (HL)            ;\n\n        RST     28H             ;; FP-CALC\n\n;; GRE.8\nL373D:  DEFB    $01             ;;exchange\n        DEFB    $34             ;;stk-data\n        DEFB    $F0             ;;Exponent: $80, Bytes: 4\n        DEFB    $31,$72,$17,$F8 ;;\n        DEFB    $04             ;;multiply\n        DEFB    $01             ;;exchange\n        DEFB    $A2             ;;stk-half\n        DEFB    $03             ;;subtract\n        DEFB    $A2             ;;stk-half\n        DEFB    $03             ;;subtract\n        DEFB    $31             ;;duplicate\n        DEFB    $34             ;;stk-data\n        DEFB    $32             ;;Exponent: $82, Bytes: 1\n        DEFB    $20             ;;(+00,+00,+00)\n        DEFB    $04             ;;multiply\n        DEFB    $A2             ;;stk-half\n        DEFB    $03             ;;subtract\n        DEFB    $8C             ;;series-0C\n        DEFB    $11             ;;Exponent: $61, Bytes: 1\n        DEFB    $AC             ;;(+00,+00,+00)\n        DEFB    $14             ;;Exponent: $64, Bytes: 1\n        DEFB    $09             ;;(+00,+00,+00)\n        DEFB    $56             ;;Exponent: $66, Bytes: 2\n        DEFB    $DA,$A5         ;;(+00,+00)\n        DEFB    $59             ;;Exponent: $69, Bytes: 2\n        DEFB    $30,$C5         ;;(+00,+00)\n        DEFB    $5C             ;;Exponent: $6C, Bytes: 2\n        DEFB    $90,$AA         ;;(+00,+00)\n        DEFB    $9E             ;;Exponent: $6E, Bytes: 3\n        DEFB    $70,$6F,$61     ;;(+00)\n        DEFB    $A1             ;;Exponent: $71, Bytes: 3\n        DEFB    $CB,$DA,$96     ;;(+00)\n        DEFB    $A4             ;;Exponent: $74, Bytes: 3\n        DEFB    $31,$9F,$B4     ;;(+00)\n        DEFB    $E7             ;;Exponent: $77, Bytes: 4\n        DEFB    $A0,$FE,$5C,$FC ;;\n        DEFB    $EA             ;;Exponent: $7A, Bytes: 4\n        DEFB    $1B,$43,$CA,$36 ;;\n        DEFB    $ED             ;;Exponent: $7D, Bytes: 4\n        DEFB    $A7,$9C,$7E,$5E ;;\n        DEFB    $F0             ;;Exponent: $80, Bytes: 4\n        DEFB    $6E,$23,$80,$93 ;;\n        DEFB    $04             ;;multiply\n        DEFB    $0F             ;;addition\n        DEFB    $38             ;;end-calc\n\n        RET                     ; return.\n\n\n; -----------------------------\n; THE 'TRIGONOMETRIC' FUNCTIONS\n; -----------------------------\n; Trigonometry is rocket science. It is also used by carpenters and pyramid\n; builders.\n; Some uses can be quite abstract but the principles can be seen in simple\n; right-angled triangles. Triangles have some special properties -\n;\n; 1) The sum of the three angles is always PI radians (180 degrees).\n;    Very helpful if you know two angles and wish to find the third.\n; 2) In any right-angled triangle the sum of the squares of the two shorter\n;    sides is equal to the square of the longest side opposite the right-angle.\n;    Very useful if you know the length of two sides and wish to know the\n;    length of the third side.\n; 3) Functions sine, cosine and tangent enable one to calculate the length\n;    of an unknown side when the length of one other side and an angle is\n;    known.\n; 4) Functions arcsin, arccosine and arctan enable one to calculate an unknown\n;    angle when the length of two of the sides is known.\n\n; --------------------------------\n; THE 'REDUCE ARGUMENT' SUBROUTINE\n; --------------------------------\n; (offset $39: 'get-argt')\n;\n; This routine performs two functions on the angle, in radians, that forms\n; the argument to the sine and cosine functions.\n; First it ensures that the angle 'wraps round'. That if a ship turns through\n; an angle of, say, 3*PI radians (540 degrees) then the net effect is to turn\n; through an angle of PI radians (180 degrees).\n; Secondly it converts the angle in radians to a fraction of a right angle,\n; depending within which quadrant the angle lies, with the periodicity\n; resembling that of the desired sine value.\n; The result lies in the range -1 to +1.\n;\n;                     90 deg.\n;\n;                     (pi/2)\n;              II       +1        I\n;                       |\n;        sin+      |\\   |   /|    sin+\n;        cos-      | \\  |  / |    cos+\n;        tan-      |  \\ | /  |    tan+\n;                  |   \\|/)  |\n; 180 deg. (pi) 0 -|----+----|-- 0  (0)   0 degrees\n;                  |   /|\\   |\n;        sin-      |  / | \\  |    sin-\n;        cos-      | /  |  \\ |    cos+\n;        tan+      |/   |   \\|    tan-\n;                       |\n;              III      -1       IV\n;                     (3pi/2)\n;\n;                     270 deg.\n;\n\n;; get-argt\nL3783:  RST     28H             ;; FP-CALC      X.\n        DEFB    $3D             ;;re-stack      (not rquired done by mult)\n        DEFB    $34             ;;stk-data\n        DEFB    $EE             ;;Exponent: $7E,\n                                ;;Bytes: 4\n        DEFB    $22,$F9,$83,$6E ;;              X, 1/(2*PI)\n        DEFB    $04             ;;multiply      X/(2*PI) = fraction\n        DEFB    $31             ;;duplicate\n        DEFB    $A2             ;;stk-half\n        DEFB    $0F             ;;addition\n        DEFB    $27             ;;int\n\n        DEFB    $03             ;;subtract      now range -.5 to .5\n\n        DEFB    $31             ;;duplicate\n        DEFB    $0F             ;;addition      now range -1 to 1.\n        DEFB    $31             ;;duplicate\n        DEFB    $0F             ;;addition      now range -2 to +2.\n\n; quadrant I (0 to +1) and quadrant IV (-1 to 0) are now correct.\n; quadrant II ranges +1 to +2.\n; quadrant III ranges -2 to -1.\n\n        DEFB    $31             ;;duplicate     Y, Y.\n        DEFB    $2A             ;;abs           Y, abs(Y).    range 1 to 2\n        DEFB    $A1             ;;stk-one       Y, abs(Y), 1.\n        DEFB    $03             ;;subtract      Y, abs(Y)-1.  range 0 to 1\n        DEFB    $31             ;;duplicate     Y, Z, Z.\n        DEFB    $37             ;;greater-0     Y, Z, (1/0).\n\n        DEFB    $C0             ;;st-mem-0         store as possible sign\n                                ;;                 for cosine function.\n\n        DEFB    $00             ;;jump-true\n        DEFB    $04             ;;to L37A1, ZPLUS  with quadrants II and III.\n\n; else the angle lies in quadrant I or IV and value Y is already correct.\n\n        DEFB    $02             ;;delete        Y.   delete the test value.\n        DEFB    $38             ;;end-calc      Y.\n\n        RET                     ; return.       with Q1 and Q4           >>>\n\n; ---\n\n; the branch was here with quadrants II (0 to 1) and III (1 to 0).\n; Y will hold -2 to -1 if this is quadrant III.\n\n;; ZPLUS\nL37A1:  DEFB    $A1             ;;stk-one         Y, Z, 1.\n        DEFB    $03             ;;subtract        Y, Z-1.       Q3 = 0 to -1\n        DEFB    $01             ;;exchange        Z-1, Y.\n        DEFB    $36             ;;less-0          Z-1, (1/0).\n        DEFB    $00             ;;jump-true       Z-1.\n        DEFB    $02             ;;to L37A8, YNEG\n                                ;;if angle in quadrant III\n\n; else angle is within quadrant II (-1 to 0)\n\n        DEFB    $1B             ;;negate          range +1 to 0.\n\n;; YNEG\nL37A8:  DEFB    $38             ;;end-calc        quadrants II and III correct.\n\n        RET                     ; return.\n\n\n; ---------------------\n; THE 'COSINE' FUNCTION\n; ---------------------\n; (offset $20: 'cos')\n; Cosines are calculated as the sine of the opposite angle rectifying the\n; sign depending on the quadrant rules.\n;\n;\n;           /|\n;        h /y|\n;         /  |o\n;        /x  |\n;       /----|\n;         a\n;\n; The cosine of angle x is the adjacent side (a) divided by the hypotenuse 1.\n; However if we examine angle y then a/h is the sine of that angle.\n; Since angle x plus angle y equals a right-angle, we can find angle y by\n; subtracting angle x from pi/2.\n; However it's just as easy to reduce the argument first and subtract the\n; reduced argument from the value 1 (a reduced right-angle).\n; It's even easier to subtract 1 from the angle and rectify the sign.\n; In fact, after reducing the argument, the absolute value of the argument\n; is used and rectified using the test result stored in mem-0 by 'get-argt'\n; for that purpose.\n;\n\n;; cos\nL37AA:  RST     28H             ;; FP-CALC              angle in radians.\n        DEFB    $39             ;;get-argt              X     reduce -1 to +1\n\n        DEFB    $2A             ;;abs                   ABS X.   0 to 1\n        DEFB    $A1             ;;stk-one               ABS X, 1.\n        DEFB    $03             ;;subtract              now opposite angle\n                                ;;                      although sign is -ve.\n\n        DEFB    $E0             ;;get-mem-0             fetch the sign indicator\n        DEFB    $00             ;;jump-true\n        DEFB    $06             ;;fwd to L37B7, C-ENT\n                                ;;forward to common code if in QII or QIII.\n\n        DEFB    $1B             ;;negate                else make sign +ve.\n        DEFB    $33             ;;jump\n        DEFB    $03             ;;fwd to L37B7, C-ENT\n                                ;; with quadrants I and IV.\n\n; -------------------\n; THE 'SINE' FUNCTION\n; -------------------\n; (offset $1F: 'sin')\n; This is a fundamental transcendental function from which others such as cos\n; and tan are directly, or indirectly, derived.\n; It uses the series generator to produce Chebyshev polynomials.\n;\n;\n;           /|\n;        1 / |\n;         /  |x\n;        /a  |\n;       /----|\n;         y\n;\n; The 'get-argt' function is designed to modify the angle and its sign\n; in line with the desired sine value and afterwards it can launch straight\n; into common code.\n\n;; sin\nL37B5:  RST     28H             ;; FP-CALC      angle in radians\n        DEFB    $39             ;;get-argt      reduce - sign now correct.\n\n;; C-ENT\nL37B7:  DEFB    $31             ;;duplicate\n        DEFB    $31             ;;duplicate\n        DEFB    $04             ;;multiply\n        DEFB    $31             ;;duplicate\n        DEFB    $0F             ;;addition\n        DEFB    $A1             ;;stk-one\n        DEFB    $03             ;;subtract\n\n        DEFB    $86             ;;series-06\n        DEFB    $14             ;;Exponent: $64, Bytes: 1\n        DEFB    $E6             ;;(+00,+00,+00)\n        DEFB    $5C             ;;Exponent: $6C, Bytes: 2\n        DEFB    $1F,$0B         ;;(+00,+00)\n        DEFB    $A3             ;;Exponent: $73, Bytes: 3\n        DEFB    $8F,$38,$EE     ;;(+00)\n        DEFB    $E9             ;;Exponent: $79, Bytes: 4\n        DEFB    $15,$63,$BB,$23 ;;\n        DEFB    $EE             ;;Exponent: $7E, Bytes: 4\n        DEFB    $92,$0D,$CD,$ED ;;\n        DEFB    $F1             ;;Exponent: $81, Bytes: 4\n        DEFB    $23,$5D,$1B,$EA ;;\n        DEFB    $04             ;;multiply\n        DEFB    $38             ;;end-calc\n\n        RET                     ; return.\n\n; ----------------------\n; THE 'TANGENT' FUNCTION\n; ----------------------\n; (offset $21: 'tan')\n;\n; Evaluates tangent x as    sin(x) / cos(x).\n;\n;\n;           /|\n;        h / |\n;         /  |o\n;        /x  |\n;       /----|\n;         a\n;\n; the tangent of angle x is the ratio of the length of the opposite side\n; divided by the length of the adjacent side. As the opposite length can\n; be calculates using sin(x) and the adjacent length using cos(x) then\n; the tangent can be defined in terms of the previous two functions.\n\n; Error 6 if the argument, in radians, is too close to one like pi/2\n; which has an infinite tangent. e.g. PRINT TAN (PI/2)  evaluates as 1/0.\n; Similarly PRINT TAN (3*PI/2), TAN (5*PI/2) etc.\n\n;; tan\nL37DA:  RST     28H             ;; FP-CALC          x.\n        DEFB    $31             ;;duplicate         x, x.\n        DEFB    $1F             ;;sin               x, sin x.\n        DEFB    $01             ;;exchange          sin x, x.\n        DEFB    $20             ;;cos               sin x, cos x.\n        DEFB    $05             ;;division          sin x/cos x (= tan x).\n        DEFB    $38             ;;end-calc          tan x.\n\n        RET                     ; return.\n\n; ---------------------\n; THE 'ARCTAN' FUNCTION\n; ---------------------\n; (Offset $24: 'atn')\n; the inverse tangent function with the result in radians.\n; This is a fundamental transcendental function from which others such as asn\n; and acs are directly, or indirectly, derived.\n; It uses the series generator to produce Chebyshev polynomials.\n\n;; atn\nL37E2:  CALL    L3297           ; routine re-stack\n        LD      A,(HL)          ; fetch exponent byte.\n        CP      $81             ; compare to that for 'one'\n        JR      C,L37F8         ; forward, if less, to SMALL\n\n        RST     28H             ;; FP-CALC\n        DEFB    $A1             ;;stk-one\n        DEFB    $1B             ;;negate\n        DEFB    $01             ;;exchange\n        DEFB    $05             ;;division\n        DEFB    $31             ;;duplicate\n        DEFB    $36             ;;less-0\n        DEFB    $A3             ;;stk-pi/2\n        DEFB    $01             ;;exchange\n        DEFB    $00             ;;jump-true\n        DEFB    $06             ;;to L37FA, CASES\n\n        DEFB    $1B             ;;negate\n        DEFB    $33             ;;jump\n        DEFB    $03             ;;to L37FA, CASES\n\n;; SMALL\nL37F8:  RST     28H             ;; FP-CALC\n        DEFB    $A0             ;;stk-zero\n\n;; CASES\nL37FA:  DEFB    $01             ;;exchange\n        DEFB    $31             ;;duplicate\n        DEFB    $31             ;;duplicate\n        DEFB    $04             ;;multiply\n        DEFB    $31             ;;duplicate\n        DEFB    $0F             ;;addition\n        DEFB    $A1             ;;stk-one\n        DEFB    $03             ;;subtract\n        DEFB    $8C             ;;series-0C\n        DEFB    $10             ;;Exponent: $60, Bytes: 1\n        DEFB    $B2             ;;(+00,+00,+00)\n        DEFB    $13             ;;Exponent: $63, Bytes: 1\n        DEFB    $0E             ;;(+00,+00,+00)\n        DEFB    $55             ;;Exponent: $65, Bytes: 2\n        DEFB    $E4,$8D         ;;(+00,+00)\n        DEFB    $58             ;;Exponent: $68, Bytes: 2\n        DEFB    $39,$BC         ;;(+00,+00)\n        DEFB    $5B             ;;Exponent: $6B, Bytes: 2\n        DEFB    $98,$FD         ;;(+00,+00)\n        DEFB    $9E             ;;Exponent: $6E, Bytes: 3\n        DEFB    $00,$36,$75     ;;(+00)\n        DEFB    $A0             ;;Exponent: $70, Bytes: 3\n        DEFB    $DB,$E8,$B4     ;;(+00)\n        DEFB    $63             ;;Exponent: $73, Bytes: 2\n        DEFB    $42,$C4         ;;(+00,+00)\n        DEFB    $E6             ;;Exponent: $76, Bytes: 4\n        DEFB    $B5,$09,$36,$BE ;;\n        DEFB    $E9             ;;Exponent: $79, Bytes: 4\n        DEFB    $36,$73,$1B,$5D ;;\n        DEFB    $EC             ;;Exponent: $7C, Bytes: 4\n        DEFB    $D8,$DE,$63,$BE ;;\n        DEFB    $F0             ;;Exponent: $80, Bytes: 4\n        DEFB    $61,$A1,$B3,$0C ;;\n        DEFB    $04             ;;multiply\n        DEFB    $0F             ;;addition\n        DEFB    $38             ;;end-calc\n\n        RET                     ; return.\n\n\n; ---------------------\n; THE 'ARCSIN' FUNCTION\n; ---------------------\n; (Offset $22: 'asn')\n;   The inverse sine function with result in radians.\n;   Derived from arctan function above.\n;   Error A unless the argument is between -1 and +1 inclusive.\n;   Uses an adaptation of the formula asn(x) = atn(x/sqr(1-x*x))\n;\n;\n;                 /|\n;                / |\n;              1/  |x\n;              /a  |\n;             /----|\n;               y\n;\n;   e.g. We know the opposite side (x) and hypotenuse (1)\n;   and we wish to find angle a in radians.\n;   We can derive length y by Pythagoras and then use ATN instead.\n;   Since y*y + x*x = 1*1 (Pythagoras Theorem) then\n;   y=sqr(1-x*x)                         - no need to multiply 1 by itself.\n;   So, asn(a) = atn(x/y)\n;   or more fully,\n;   asn(a) = atn(x/sqr(1-x*x))\n\n;   Close but no cigar.\n\n;   While PRINT ATN (x/SQR (1-x*x)) gives the same results as PRINT ASN x,\n;   it leads to division by zero when x is 1 or -1.\n;   To overcome this, 1 is added to y giving half the required angle and the\n;   result is then doubled.\n;   That is, PRINT ATN (x/(SQR (1-x*x) +1)) *2\n;\n;   GEOMETRIC PROOF.\n;\n;\n;               . /|\n;            .  c/ |\n;         .     /1 |x\n;      . c   b /a  |\n;    ---------/----|\n;      1      y\n;\n;   By creating an isosceles triangle with two equal sides of 1, angles c and\n;   c are also equal. If b+c+c = 180 degrees and b+a = 180 degrees then c=a/2.\n;\n;   A value higher than 1 gives the required error as attempting to find  the\n;   square root of a negative number generates an error in Sinclair BASIC.\n\n;; asn\nL3833:  RST     28H             ;; FP-CALC      x.\n        DEFB    $31             ;;duplicate     x, x.\n        DEFB    $31             ;;duplicate     x, x, x.\n        DEFB    $04             ;;multiply      x, x*x.\n        DEFB    $A1             ;;stk-one       x, x*x, 1.\n        DEFB    $03             ;;subtract      x, x*x-1.\n        DEFB    $1B             ;;negate        x, 1-x*x.\n        DEFB    $28             ;;sqr           x, sqr(1-x*x) = y\n        DEFB    $A1             ;;stk-one       x, y, 1.\n        DEFB    $0F             ;;addition      x, y+1.\n        DEFB    $05             ;;division      x/y+1.\n        DEFB    $24             ;;atn           a/2       (half the angle)\n        DEFB    $31             ;;duplicate     a/2, a/2.\n        DEFB    $0F             ;;addition      a.\n        DEFB    $38             ;;end-calc      a.\n\n        RET                     ; return.\n\n\n; ---------------------\n; THE 'ARCCOS' FUNCTION\n; ---------------------\n; (Offset $23: 'acs')\n; the inverse cosine function with the result in radians.\n; Error A unless the argument is between -1 and +1.\n; Result in range 0 to pi.\n; Derived from asn above which is in turn derived from the preceding atn.\n; It could have been derived directly from atn using acs(x) = atn(sqr(1-x*x)/x).\n; However, as sine and cosine are horizontal translations of each other,\n; uses acs(x) = pi/2 - asn(x)\n\n; e.g. the arccosine of a known x value will give the required angle b in\n; radians.\n; We know, from above, how to calculate the angle a using asn(x).\n; Since the three angles of any triangle add up to 180 degrees, or pi radians,\n; and the largest angle in this case is a right-angle (pi/2 radians), then\n; we can calculate angle b as pi/2 (both angles) minus asn(x) (angle a).\n;\n;\n;           /|\n;        1 /b|\n;         /  |x\n;        /a  |\n;       /----|\n;         y\n;\n\n;; acs\nL3843:  RST     28H             ;; FP-CALC      x.\n        DEFB    $22             ;;asn           asn(x).\n        DEFB    $A3             ;;stk-pi/2      asn(x), pi/2.\n        DEFB    $03             ;;subtract      asn(x) - pi/2.\n        DEFB    $1B             ;;negate        pi/2 -asn(x)  =  acs(x).\n        DEFB    $38             ;;end-calc      acs(x).\n\n        RET                     ; return.\n\n\n; --------------------------\n; THE 'SQUARE ROOT' FUNCTION\n; --------------------------\n; (Offset $28: 'sqr')\n; This routine is remarkable for its brevity - 7 bytes.\n; It wasn't written here but in the ZX81 where the programmers had to squeeze\n; a bulky operating system into an 8K ROM. It simply calculates\n; the square root by stacking the value .5 and continuing into the 'to-power'\n; routine. With more space available the much faster Newton-Raphson method\n; could have been used as on the Jupiter Ace.\n\n;; sqr\nL384A:  RST     28H             ;; FP-CALC\n        DEFB    $31             ;;duplicate\n        DEFB    $30             ;;not\n        DEFB    $00             ;;jump-true\n        DEFB    $1E             ;;to L386C, LAST\n\n        DEFB    $A2             ;;stk-half\n        DEFB    $38             ;;end-calc\n\n\n; ------------------------------\n; THE 'EXPONENTIATION' OPERATION\n; ------------------------------\n; (Offset $06: 'to-power')\n; This raises the first number X to the power of the second number Y.\n; As with the ZX80,\n; 0 ^ 0 = 1.\n; 0 ^ +n = 0.\n; 0 ^ -n = arithmetic overflow.\n;\n\n;; to-power\nL3851:  RST     28H             ;; FP-CALC              X, Y.\n        DEFB    $01             ;;exchange              Y, X.\n        DEFB    $31             ;;duplicate             Y, X, X.\n        DEFB    $30             ;;not                   Y, X, (1/0).\n        DEFB    $00             ;;jump-true\n        DEFB    $07             ;;to L385D, XIS0   if X is zero.\n\n;   else X is non-zero. Function 'ln' will catch a negative value of X.\n\n        DEFB    $25             ;;ln                    Y, LN X.\n        DEFB    $04             ;;multiply              Y * LN X.\n        DEFB    $38             ;;end-calc\n\n        JP      L36C4           ; jump back to EXP routine   ->\n\n; ---\n\n;   these routines form the three simple results when the number is zero.\n;   begin by deleting the known zero to leave Y the power factor.\n\n;; XIS0\nL385D:  DEFB    $02             ;;delete                Y.\n        DEFB    $31             ;;duplicate             Y, Y.\n        DEFB    $30             ;;not                   Y, (1/0).\n        DEFB    $00             ;;jump-true\n        DEFB    $09             ;;to L386A, ONE         if Y is zero.\n\n        DEFB    $A0             ;;stk-zero              Y, 0.\n        DEFB    $01             ;;exchange              0, Y.\n        DEFB    $37             ;;greater-0             0, (1/0).\n        DEFB    $00             ;;jump-true             0.\n        DEFB    $06             ;;to L386C, LAST        if Y was any positive\n                                ;;                      number.\n\n;   else force division by zero thereby raising an Arithmetic overflow error.\n;   There are some one and two-byte alternatives but perhaps the most formal\n;   might have been to use end-calc; rst 08; defb 05.\n\n        DEFB    $A1             ;;stk-one               0, 1.\n        DEFB    $01             ;;exchange              1, 0.\n        DEFB    $05             ;;division              1/0        ouch!\n\n; ---\n\n;; ONE\nL386A:  DEFB    $02             ;;delete                .\n        DEFB    $A1             ;;stk-one               1.\n\n;; LAST\nL386C:  DEFB    $38             ;;end-calc              last value is 1 or 0.\n\n        RET                     ; return.\n\n;   \"Everything should be made as simple as possible, but not simpler\"\n;   - Albert Einstein, 1879-1955.\n\n; ---------------------\n; THE 'SPARE' LOCATIONS\n; ---------------------\n\n;; spare\nL386E:  DEFB    $FF, $FF        ;\n\n; ----------------------------------------------------------------------------\n; This custom NMI handler provides a way to enter a POKE for a game by typing in\n; the address (5 decimal digits) followed by the value (3 decimal digits)\n; after which the value will be stored to the selected location.\n; ----------------------------------------------------------------------------\nnmi_handler:                    ; NMI handler\n        push    bc\n        push    de\n        push    ix\n        ld      hl,$04000       ; Use the screen memory as a temp storage\n        ld      e,$08           ; Will load 8 characters (numbers)\nnext_key:\n        ld      bc,$f7fe        ; Number row 1..5\n        in      a,(c)\n        ld      c,a\n        ld      a,$01           ; Preload \"1\"\n        bit     0,c             ; If the key has been pressed\n        jr      z,accept_key    ; Accept it\n        inc     a               ; Preload \"2\"\n        bit     1,c             ; and continue for every key up to \"5\"\n        jr      z,accept_key\n        inc     a\n        bit     2,c\n        jr      z,accept_key\n        inc     a\n        bit     3,c\n        jr      z,accept_key\n        inc     a\n        bit     4,c\n        jr      z,accept_key\n        ld      bc,$effe        ; Number row 6...0\n        in      a,(c)\n        ld      c,a\n        ld      a,$06\n        bit     4,c\n        jr      z,accept_key\n        inc     a\n        bit     3,c\n        jr      z,accept_key\n        inc     a\n        bit     2,c\n        jr      z,accept_key\n        inc     a\n        bit     1,c\n        jr      z,accept_key\n        xor     a\n        bit     0,c\n        jr      z,accept_key\n        jp      next_key\naccept_key:\n        ld      (hl),a          ; Store current key value into the buffer\n        inc     hl\npoll_key_release:               ; Poll for any pressed key to be released\n        ld      bc,$f7fe\n        in      a,(c)\n        cpl\n        and     $1f\n        jr      nz,poll_key_release\n        ld      bc,$effe\n        in      a,(c)\n        cpl\n        and     $1f\n        jr      nz,poll_key_release\n        dec     e               ; Decrement the number of keys expected\n        jr      nz,next_key     ; Jump back to accept next key if not yet done\n        ld      ix,$4000\n        ld      b,$05           ; First 5 numbers represent the address to POKE to\n        call    decimal_to_hl\n        push    hl              ; Address is in HL, store it\n        ld      b,$03           ; Next 3 numbers represent the value to POKE\n        call    decimal_to_hl\n        ld      a,l             ; Value is in L\n        pop     hl              ; Get the address\n        ld      (hl),a          ; POKE a value\n        pop     ix\n        pop     de\n        pop     bc\n        pop     hl\n        pop     af\n        retn\n; Read a decimal value pointed to by IX register\n; The number of digits is given in B register\n; Return the value in HL register\ndecimal_to_hl:\n        ld      hl,$0000        ; Start with value of 0\nlp2:\n        push    bc\n        ld      b,$09           ; Multiply the current value by 10\n        push    hl\n        pop     de\nlp1:\n        add     hl,de\n        djnz    lp1\n        pop     bc\n        ld      e,(ix+0)        ; Read in the next digit\n        ld      d,$00\n        add     hl,de           ; Add in the new value\n        inc     ix\n        djnz    lp2             ; Loop for the requested number of digits\n        ret\n\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n        DEFB    $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF;\n\nORG $3D00\n\n; -------------------------------\n; THE 'ZX SPECTRUM CHARACTER SET'\n; -------------------------------\n\n;; char-set\n\n; $20 - Character: ' '          CHR$(32)\n\nL3D00:  DEFB    %00000000\n        DEFB    %00000000\n        DEFB    %00000000\n        DEFB    %00000000\n        DEFB    %00000000\n        DEFB    %00000000\n        DEFB    %00000000\n        DEFB    %00000000\n\n; $21 - Character: '!'          CHR$(33)\n\n        DEFB    %00000000\n        DEFB    %00010000\n        DEFB    %00010000\n        DEFB    %00010000\n        DEFB    %00010000\n        DEFB    %00000000\n        DEFB    %00010000\n        DEFB    %00000000\n\n; $22 - Character: '\"'          CHR$(34)\n\n        DEFB    %00000000\n        DEFB    %00100100\n        DEFB    %00100100\n        DEFB    %00000000\n        DEFB    %00000000\n        DEFB    %00000000\n        DEFB    %00000000\n        DEFB    %00000000\n\n; $23 - Character: '#'          CHR$(35)\n\n        DEFB    %00000000\n        DEFB    %00100100\n        DEFB    %01111110\n        DEFB    %00100100\n        DEFB    %00100100\n        DEFB    %01111110\n        DEFB    %00100100\n        DEFB    %00000000\n\n; $24 - Character: '$'          CHR$(36)\n\n        DEFB    %00000000\n        DEFB    %00001000\n        DEFB    %00111110\n        DEFB    %00101000\n        DEFB    %00111110\n        DEFB    %00001010\n        DEFB    %00111110\n        DEFB    %00001000\n\n; $25 - Character: '%'          CHR$(37)\n\n        DEFB    %00000000\n        DEFB    %01100010\n        DEFB    %01100100\n        DEFB    %00001000\n        DEFB    %00010000\n        DEFB    %00100110\n        DEFB    %01000110\n        DEFB    %00000000\n\n; $26 - Character: '&'          CHR$(38)\n\n        DEFB    %00000000\n        DEFB    %00010000\n        DEFB    %00101000\n        DEFB    %00010000\n        DEFB    %00101010\n        DEFB    %01000100\n        DEFB    %00111010\n        DEFB    %00000000\n\n; $27 - Character: '''          CHR$(39)\n\n        DEFB    %00000000\n        DEFB    %00001000\n        DEFB    %00010000\n        DEFB    %00000000\n        DEFB    %00000000\n        DEFB    %00000000\n        DEFB    %00000000\n        DEFB    %00000000\n\n; $28 - Character: '('          CHR$(40)\n\n        DEFB    %00000000\n        DEFB    %00000100\n        DEFB    %00001000\n        DEFB    %00001000\n        DEFB    %00001000\n        DEFB    %00001000\n        DEFB    %00000100\n        DEFB    %00000000\n\n; $29 - Character: ')'          CHR$(41)\n\n        DEFB    %00000000\n        DEFB    %00100000\n        DEFB    %00010000\n        DEFB    %00010000\n        DEFB    %00010000\n        DEFB    %00010000\n        DEFB    %00100000\n        DEFB    %00000000\n\n; $2A - Character: '*'          CHR$(42)\n\n        DEFB    %00000000\n        DEFB    %00000000\n        DEFB    %00010100\n        DEFB    %00001000\n        DEFB    %00111110\n        DEFB    %00001000\n        DEFB    %00010100\n        DEFB    %00000000\n\n; $2B - Character: '+'          CHR$(43)\n\n        DEFB    %00000000\n        DEFB    %00000000\n        DEFB    %00001000\n        DEFB    %00001000\n        DEFB    %00111110\n        DEFB    %00001000\n        DEFB    %00001000\n        DEFB    %00000000\n\n; $2C - Character: ','          CHR$(44)\n\n        DEFB    %00000000\n        DEFB    %00000000\n        DEFB    %00000000\n        DEFB    %00000000\n        DEFB    %00000000\n        DEFB    %00001000\n        DEFB    %00001000\n        DEFB    %00010000\n\n; $2D - Character: '-'          CHR$(45)\n\n        DEFB    %00000000\n        DEFB    %00000000\n        DEFB    %00000000\n        DEFB    %00000000\n        DEFB    %00111110\n        DEFB    %00000000\n        DEFB    %00000000\n        DEFB    %00000000\n\n; $2E - Character: '.'          CHR$(46)\n\n        DEFB    %00000000\n        DEFB    %00000000\n        DEFB    %00000000\n        DEFB    %00000000\n        DEFB    %00000000\n        DEFB    %00011000\n        DEFB    %00011000\n        DEFB    %00000000\n\n; $2F - Character: '/'          CHR$(47)\n\n        DEFB    %00000000\n        DEFB    %00000000\n        DEFB    %00000010\n        DEFB    %00000100\n        DEFB    %00001000\n        DEFB    %00010000\n        DEFB    %00100000\n        DEFB    %00000000\n\n; $30 - Character: '0'          CHR$(48)\n\n        DEFB    %00000000\n        DEFB    %00111100\n        DEFB    %01000110\n        DEFB    %01001010\n        DEFB    %01010010\n        DEFB    %01100010\n        DEFB    %00111100\n        DEFB    %00000000\n\n; $31 - Character: '1'          CHR$(49)\n\n        DEFB    %00000000\n        DEFB    %00011000\n        DEFB    %00101000\n        DEFB    %00001000\n        DEFB    %00001000\n        DEFB    %00001000\n        DEFB    %00111110\n        DEFB    %00000000\n\n; $32 - Character: '2'          CHR$(50)\n\n        DEFB    %00000000\n        DEFB    %00111100\n        DEFB    %01000010\n        DEFB    %00000010\n        DEFB    %00111100\n        DEFB    %01000000\n        DEFB    %01111110\n        DEFB    %00000000\n\n; $33 - Character: '3'          CHR$(51)\n\n        DEFB    %00000000\n        DEFB    %00111100\n        DEFB    %01000010\n        DEFB    %00001100\n        DEFB    %00000010\n        DEFB    %01000010\n        DEFB    %00111100\n        DEFB    %00000000\n\n; $34 - Character: '4'          CHR$(52)\n\n        DEFB    %00000000\n        DEFB    %00001000\n        DEFB    %00011000\n        DEFB    %00101000\n        DEFB    %01001000\n        DEFB    %01111110\n        DEFB    %00001000\n        DEFB    %00000000\n\n; $35 - Character: '5'          CHR$(53)\n\n        DEFB    %00000000\n        DEFB    %01111110\n        DEFB    %01000000\n        DEFB    %01111100\n        DEFB    %00000010\n        DEFB    %01000010\n        DEFB    %00111100\n        DEFB    %00000000\n\n; $36 - Character: '6'          CHR$(54)\n\n        DEFB    %00000000\n        DEFB    %00111100\n        DEFB    %01000000\n        DEFB    %01111100\n        DEFB    %01000010\n        DEFB    %01000010\n        DEFB    %00111100\n        DEFB    %00000000\n\n; $37 - Character: '7'          CHR$(55)\n\n        DEFB    %00000000\n        DEFB    %01111110\n        DEFB    %00000010\n        DEFB    %00000100\n        DEFB    %00001000\n        DEFB    %00010000\n        DEFB    %00010000\n        DEFB    %00000000\n\n; $38 - Character: '8'          CHR$(56)\n\n        DEFB    %00000000\n        DEFB    %00111100\n        DEFB    %01000010\n        DEFB    %00111100\n        DEFB    %01000010\n        DEFB    %01000010\n        DEFB    %00111100\n        DEFB    %00000000\n\n; $39 - Character: '9'          CHR$(57)\n\n        DEFB    %00000000\n        DEFB    %00111100\n        DEFB    %01000010\n        DEFB    %01000010\n        DEFB    %00111110\n        DEFB    %00000010\n        DEFB    %00111100\n        DEFB    %00000000\n\n; $3A - Character: ':'          CHR$(58)\n\n        DEFB    %00000000\n        DEFB    %00000000\n        DEFB    %00000000\n        DEFB    %00010000\n        DEFB    %00000000\n        DEFB    %00000000\n        DEFB    %00010000\n        DEFB    %00000000\n\n; $3B - Character: ';'          CHR$(59)\n\n        DEFB    %00000000\n        DEFB    %00000000\n        DEFB    %00010000\n        DEFB    %00000000\n        DEFB    %00000000\n        DEFB    %00010000\n        DEFB    %00010000\n        DEFB    %00100000\n\n; $3C - Character: '<'          CHR$(60)\n\n        DEFB    %00000000\n        DEFB    %00000000\n        DEFB    %00000100\n        DEFB    %00001000\n        DEFB    %00010000\n        DEFB    %00001000\n        DEFB    %00000100\n        DEFB    %00000000\n\n; $3D - Character: '='          CHR$(61)\n\n        DEFB    %00000000\n        DEFB    %00000000\n        DEFB    %00000000\n        DEFB    %00111110\n        DEFB    %00000000\n        DEFB    %00111110\n        DEFB    %00000000\n        DEFB    %00000000\n\n; $3E - Character: '>'          CHR$(62)\n\n        DEFB    %00000000\n        DEFB    %00000000\n        DEFB    %00010000\n        DEFB    %00001000\n        DEFB    %00000100\n        DEFB    %00001000\n        DEFB    %00010000\n        DEFB    %00000000\n\n; $3F - Character: '?'          CHR$(63)\n\n        DEFB    %00000000\n        DEFB    %00111100\n        DEFB    %01000010\n        DEFB    %00000100\n        DEFB    %00001000\n        DEFB    %00000000\n        DEFB    %00001000\n        DEFB    %00000000\n\n; $40 - Character: '@'          CHR$(64)\n\n        DEFB    %00000000\n        DEFB    %00111100\n        DEFB    %01001010\n        DEFB    %01010110\n        DEFB    %01011110\n        DEFB    %01000000\n        DEFB    %00111100\n        DEFB    %00000000\n\n; $41 - Character: 'A'          CHR$(65)\n\n        DEFB    %00000000\n        DEFB    %00111100\n        DEFB    %01000010\n        DEFB    %01000010\n        DEFB    %01111110\n        DEFB    %01000010\n        DEFB    %01000010\n        DEFB    %00000000\n\n; $42 - Character: 'B'          CHR$(66)\n\n        DEFB    %00000000\n        DEFB    %01111100\n        DEFB    %01000010\n        DEFB    %01111100\n        DEFB    %01000010\n        DEFB    %01000010\n        DEFB    %01111100\n        DEFB    %00000000\n\n; $43 - Character: 'C'          CHR$(67)\n\n        DEFB    %00000000\n        DEFB    %00111100\n        DEFB    %01000010\n        DEFB    %01000000\n        DEFB    %01000000\n        DEFB    %01000010\n        DEFB    %00111100\n        DEFB    %00000000\n\n; $44 - Character: 'D'          CHR$(68)\n\n        DEFB    %00000000\n        DEFB    %01111000\n        DEFB    %01000100\n        DEFB    %01000010\n        DEFB    %01000010\n        DEFB    %01000100\n        DEFB    %01111000\n        DEFB    %00000000\n\n; $45 - Character: 'E'          CHR$(69)\n\n        DEFB    %00000000\n        DEFB    %01111110\n        DEFB    %01000000\n        DEFB    %01111100\n        DEFB    %01000000\n        DEFB    %01000000\n        DEFB    %01111110\n        DEFB    %00000000\n\n; $46 - Character: 'F'          CHR$(70)\n\n        DEFB    %00000000\n        DEFB    %01111110\n        DEFB    %01000000\n        DEFB    %01111100\n        DEFB    %01000000\n        DEFB    %01000000\n        DEFB    %01000000\n        DEFB    %00000000\n\n; $47 - Character: 'G'          CHR$(71)\n\n        DEFB    %00000000\n        DEFB    %00111100\n        DEFB    %01000010\n        DEFB    %01000000\n        DEFB    %01001110\n        DEFB    %01000010\n        DEFB    %00111100\n        DEFB    %00000000\n\n; $48 - Character: 'H'          CHR$(72)\n\n        DEFB    %00000000\n        DEFB    %01000010\n        DEFB    %01000010\n        DEFB    %01111110\n        DEFB    %01000010\n        DEFB    %01000010\n        DEFB    %01000010\n        DEFB    %00000000\n\n; $49 - Character: 'I'          CHR$(73)\n\n        DEFB    %00000000\n        DEFB    %00111110\n        DEFB    %00001000\n        DEFB    %00001000\n        DEFB    %00001000\n        DEFB    %00001000\n        DEFB    %00111110\n        DEFB    %00000000\n\n; $4A - Character: 'J'          CHR$(74)\n\n        DEFB    %00000000\n        DEFB    %00000010\n        DEFB    %00000010\n        DEFB    %00000010\n        DEFB    %01000010\n        DEFB    %01000010\n        DEFB    %00111100\n        DEFB    %00000000\n\n; $4B - Character: 'K'          CHR$(75)\n\n        DEFB    %00000000\n        DEFB    %01000100\n        DEFB    %01001000\n        DEFB    %01110000\n        DEFB    %01001000\n        DEFB    %01000100\n        DEFB    %01000010\n        DEFB    %00000000\n\n; $4C - Character: 'L'          CHR$(76)\n\n        DEFB    %00000000\n        DEFB    %01000000\n        DEFB    %01000000\n        DEFB    %01000000\n        DEFB    %01000000\n        DEFB    %01000000\n        DEFB    %01111110\n        DEFB    %00000000\n\n; $4D - Character: 'M'          CHR$(77)\n\n        DEFB    %00000000\n        DEFB    %01000010\n        DEFB    %01100110\n        DEFB    %01011010\n        DEFB    %01000010\n        DEFB    %01000010\n        DEFB    %01000010\n        DEFB    %00000000\n\n; $4E - Character: 'N'          CHR$(78)\n\n        DEFB    %00000000\n        DEFB    %01000010\n        DEFB    %01100010\n        DEFB    %01010010\n        DEFB    %01001010\n        DEFB    %01000110\n        DEFB    %01000010\n        DEFB    %00000000\n\n; $4F - Character: 'O'          CHR$(79)\n\n        DEFB    %00000000\n        DEFB    %00111100\n        DEFB    %01000010\n        DEFB    %01000010\n        DEFB    %01000010\n        DEFB    %01000010\n        DEFB    %00111100\n        DEFB    %00000000\n\n; $50 - Character: 'P'          CHR$(80)\n\n        DEFB    %00000000\n        DEFB    %01111100\n        DEFB    %01000010\n        DEFB    %01000010\n        DEFB    %01111100\n        DEFB    %01000000\n        DEFB    %01000000\n        DEFB    %00000000\n\n; $51 - Character: 'Q'          CHR$(81)\n\n        DEFB    %00000000\n        DEFB    %00111100\n        DEFB    %01000010\n        DEFB    %01000010\n        DEFB    %01010010\n        DEFB    %01001010\n        DEFB    %00111100\n        DEFB    %00000000\n\n; $52 - Character: 'R'          CHR$(82)\n\n        DEFB    %00000000\n        DEFB    %01111100\n        DEFB    %01000010\n        DEFB    %01000010\n        DEFB    %01111100\n        DEFB    %01000100\n        DEFB    %01000010\n        DEFB    %00000000\n\n; $53 - Character: 'S'          CHR$(83)\n\n        DEFB    %00000000\n        DEFB    %00111100\n        DEFB    %01000000\n        DEFB    %00111100\n        DEFB    %00000010\n        DEFB    %01000010\n        DEFB    %00111100\n        DEFB    %00000000\n\n; $54 - Character: 'T'          CHR$(84)\n\n        DEFB    %00000000\n        DEFB    %11111110\n        DEFB    %00010000\n        DEFB    %00010000\n        DEFB    %00010000\n        DEFB    %00010000\n        DEFB    %00010000\n        DEFB    %00000000\n\n; $55 - Character: 'U'          CHR$(85)\n\n        DEFB    %00000000\n        DEFB    %01000010\n        DEFB    %01000010\n        DEFB    %01000010\n        DEFB    %01000010\n        DEFB    %01000010\n        DEFB    %00111100\n        DEFB    %00000000\n\n; $56 - Character: 'V'          CHR$(86)\n\n        DEFB    %00000000\n        DEFB    %01000010\n        DEFB    %01000010\n        DEFB    %01000010\n        DEFB    %01000010\n        DEFB    %00100100\n        DEFB    %00011000\n        DEFB    %00000000\n\n; $57 - Character: 'W'          CHR$(87)\n\n        DEFB    %00000000\n        DEFB    %01000010\n        DEFB    %01000010\n        DEFB    %01000010\n        DEFB    %01000010\n        DEFB    %01011010\n        DEFB    %00100100\n        DEFB    %00000000\n\n; $58 - Character: 'X'          CHR$(88)\n\n        DEFB    %00000000\n        DEFB    %01000010\n        DEFB    %00100100\n        DEFB    %00011000\n        DEFB    %00011000\n        DEFB    %00100100\n        DEFB    %01000010\n        DEFB    %00000000\n\n; $59 - Character: 'Y'          CHR$(89)\n\n        DEFB    %00000000\n        DEFB    %10000010\n        DEFB    %01000100\n        DEFB    %00101000\n        DEFB    %00010000\n        DEFB    %00010000\n        DEFB    %00010000\n        DEFB    %00000000\n\n; $5A - Character: 'Z'          CHR$(90)\n\n        DEFB    %00000000\n        DEFB    %01111110\n        DEFB    %00000100\n        DEFB    %00001000\n        DEFB    %00010000\n        DEFB    %00100000\n        DEFB    %01111110\n        DEFB    %00000000\n\n; $5B - Character: '['          CHR$(91)\n\n        DEFB    %00000000\n        DEFB    %00001110\n        DEFB    %00001000\n        DEFB    %00001000\n        DEFB    %00001000\n        DEFB    %00001000\n        DEFB    %00001110\n        DEFB    %00000000\n\n; $5C - Character: '\\'          CHR$(92)\n\n        DEFB    %00000000\n        DEFB    %00000000\n        DEFB    %01000000\n        DEFB    %00100000\n        DEFB    %00010000\n        DEFB    %00001000\n        DEFB    %00000100\n        DEFB    %00000000\n\n; $5D - Character: ']'          CHR$(93)\n\n        DEFB    %00000000\n        DEFB    %01110000\n        DEFB    %00010000\n        DEFB    %00010000\n        DEFB    %00010000\n        DEFB    %00010000\n        DEFB    %01110000\n        DEFB    %00000000\n\n; $5E - Character: '^'          CHR$(94)\n\n        DEFB    %00000000\n        DEFB    %00010000\n        DEFB    %00111000\n        DEFB    %01010100\n        DEFB    %00010000\n        DEFB    %00010000\n        DEFB    %00010000\n        DEFB    %00000000\n\n; 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$7F - Character: ' © '        CHR$(127)\n\n        DEFB    %00111100\n        DEFB    %01000010\n        DEFB    %10011001\n        DEFB    %10100001\n        DEFB    %10100001\n        DEFB    %10011001\n        DEFB    %01000010\n        DEFB    %00111100\n\n\n#end                            ; generic cross-assembler directive\n\n; Acknowledgements\n; -----------------\n; Sean Irvine               for default list of section headings\n; Dr. Ian Logan             for labels and functional disassembly.\n; Dr. Frank O'Hara          for labels and functional disassembly.\n;\n; Credits\n; -------\n; Alex Pallero Gonzales     for corrections.\n; Mike Dailly               for comments.\n; Alvin Albrecht            for comments.\n; Andy Styles               for full relocatability implementation and testing.                    testing.\n; Andrew Owen               for ZASM compatibility and format improvements.\n\n;   For other assemblers you may have to add directives like these near the\n;   beginning - see accompanying documentation.\n;   ZASM (MacOs) cross-assembler directives. (uncomment by removing ';' )\n;   #target rom           ; declare target file format as binary.\n;   #code   0,$4000       ; declare code segment.\n;   Also see notes at Address Labels 0609 and 1CA5 if your assembler has\n;   trouble with expressions.\n;\n;   Note. The Sinclair Interface 1 ROM written by Dr. Ian Logan and Martin\n;   Brennan calls numerous routines in this ROM.\n;   Non-standard entry points have a label beginning with X.\n"
  },
  {
    "path": "host/zxspectrum_de1/ula/clocks.sv",
    "content": "//============================================================================\n// Implementation of the Sinclair ZX Spectrum ULA\n//\n// This module contains the clocks section.\n//\n// TODO: Video RAM contention would cause a clock gating which would be\n// implemented in this module. RAM contention is not implemented since we are\n// using FPGA RAM cells configured in dual-port mode.\n//\n//  Copyright (C) 2014-2016  Goran Devic\n//\n//  This program is free software; you can redistribute it and/or modify it\n//  under the terms of the GNU General Public License as published by the Free\n//  Software Foundation; either version 2 of the License, or (at your option)\n//  any later version.\n//\n//  This program is distributed in the hope that it will be useful, but WITHOUT\n//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n//  more details.\n//\n//  You should have received a copy of the GNU General Public License along\n//  with this program; if not, write to the Free Software Foundation, Inc.,\n//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n//============================================================================\nmodule clocks\n(\n    input wire clk_ula,         // Input ULA clock of 14 MHz\n    input wire turbo,           // Turbo speed (3.5 MHz x 2 = 7.0 MHz)\n    output reg clk_cpu          // Output 3.5 MHz CPU clock\n);\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// Generate 3.5 MHz Z80 CPU clock by dividing input clock of 14 MHz by 4\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nreg [0:0] counter;\n\n// Note: In order to get to 3.5 MHz, the PLL needs to be set to generate 14 MHz\n// and then this divider-by-4 brings the effective clock down to 3.5 MHz\n// 1. always block at positive edge of clk_ula divides by 2\n// 2. counter flop further divides it by 2 unless the turbo mode is set\nalways @(posedge clk_ula)\nbegin\n    if (counter=='0 | turbo)\n        clk_cpu <= ~clk_cpu;\n    counter <= counter - 1'b1;\nend\n\nendmodule\n"
  },
  {
    "path": "host/zxspectrum_de1/ula/i2c_loader.vhd",
    "content": "-- ZX Spectrum for Altera DE1\n--\n-- Copyright (c) 2009-2010 Mike Stirling\n--\n-- All rights reserved\n--\n-- Redistribution and use in source and synthezised forms, with or without\n-- modification, are permitted provided that the following conditions are met:\n--\n-- * Redistributions of source code must retain the above copyright notice,\n--   this list of conditions and the following disclaimer.\n--\n-- * Redistributions in synthesized form must reproduce the above copyright\n--   notice, this list of conditions and the following disclaimer in the\n--   documentation and/or other materials provided with the distribution.\n--\n-- * Neither the name of the author nor the names of other contributors may\n--   be used to endorse or promote products derived from this software without\n--   specific prior written permission.\n--\n-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\n-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE\n-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n-- POSSIBILITY OF SUCH DAMAGE.\n--\n\nlibrary IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\nuse IEEE.STD_LOGIC_ARITH.ALL;\nuse IEEE.STD_LOGIC_UNSIGNED.ALL;\nuse IEEE.STD_LOGIC_MISC.ALL; -- for AND_REDUCE\nuse IEEE.NUMERIC_STD.ALL;\n\nentity i2c_loader is\ngeneric (\n    -- Address of slave to be loaded\n    device_address : integer := 16#1a#;\n    -- Number of retries to allow before stopping\n    num_retries : integer := 0;\n    -- Length of clock divider in bits.  Resulting bus frequency is\n    -- CLK/2^(log2_divider + 2)\n    log2_divider : integer := 6\n);\n\nport (\n    CLK         :   in  std_logic;\n    nRESET      :   in  std_logic;\n\n    I2C_SCL     :   inout   std_logic;\n    I2C_SDA     :   inout   std_logic;\n\n    IS_DONE     :   out std_logic;\n    IS_ERROR    :   out std_logic\n    );\nend i2c_loader;\n\narchitecture i2c_loader_arch of i2c_loader is\ntype regs is array(0 to 19) of std_logic_vector(7 downto 0);\nconstant init_regs : regs := (\n    -- Left line in, 0dB, unmute\n    X\"00\", X\"17\",\n    -- Right line in, 0dB, unmute\n    X\"02\", X\"17\",\n    -- Left headphone out, 0dB\n    X\"04\", X\"79\",\n    -- Right headphone out, 0dB\n    X\"06\", X\"79\",\n    -- Audio path, DAC enabled, Line in, Bypass off, mic unmuted\n    X\"08\", X\"10\",\n    -- Digital path, Unmute, HP filter enabled\n    X\"0A\", X\"00\",\n    -- Power down mic, clkout and xtal osc\n    X\"0C\", X\"62\",\n    -- Format 16-bit I2S, no bit inversion or phase changes\n    X\"0E\", X\"02\",\n    -- Sampling control, 8 kHz USB mode (MCLK = 250fs * 6)\n    X\"10\", X\"0D\",\n    -- Activate\n    X\"12\", X\"01\"\n    );\n-- Number of bursts (i.e. total number of registers)\nconstant burst_length : positive := 2;\n-- Number of bytes to transfer per burst\nconstant num_bursts : positive := (init_regs'length / burst_length);\n\ntype state_t is (Idle, Start, Data, Ack, Stop, Pause, Done);\nsignal state : state_t;\nsignal phase : std_logic_vector(1 downto 0);\nsubtype nbit_t is integer range 0 to 7;\nsignal nbit : nbit_t;\nsubtype nbyte_t is integer range 0 to burst_length; -- +1 for address byte\nsignal nbyte : nbyte_t;\nsubtype thisbyte_t is integer range 0 to init_regs'length; -- +1 for \"done\"\nsignal thisbyte : thisbyte_t;\nsubtype retries_t is integer range 0 to num_retries;\nsignal retries : retries_t;\n\nsignal clken : std_logic;\nsignal divider : std_logic_vector(log2_divider-1 downto 0);\nsignal shiftreg : std_logic_vector(7 downto 0);\nsignal scl_out : std_logic;\nsignal sda_out : std_logic;\nsignal nak : std_logic;\nbegin\n    -- Create open-drain outputs for I2C bus\n    I2C_SCL <= '0' when scl_out = '0' else 'Z';\n    I2C_SDA <= '0' when sda_out = '0' else 'Z';\n    -- Status outputs are driven both ways\n    IS_DONE <= '1' when state = Done else '0';\n    IS_ERROR <= nak;\n\n    -- Generate clock enable for desired bus speed\n    clken <= AND_REDUCE(divider);\n    process(nRESET,CLK)\n    begin\n        if nRESET = '0' then\n            divider <= (others => '0');\n        elsif falling_edge(CLK) then\n            divider <= divider + '1';\n        end if;\n    end process;\n\n    -- The I2C loader process\n    process(nRESET,CLK,clken)\n    begin\n        if nRESET = '0' then\n            scl_out <= '1';\n            sda_out <= '1';\n            state <= Idle;\n            phase <= \"00\";\n            nbit <= 0;\n            nbyte <= 0;\n            thisbyte <= 0;\n            shiftreg <= (others => '0');\n            nak <= '0'; -- No error\n            retries <= num_retries;\n        elsif rising_edge(CLK) and clken = '1' then\n            -- Next phase by default\n            phase <= phase + 1;\n\n            -- STATE: IDLE\n            if state = Idle then\n                -- Start loading the device registers straight away\n                -- A 'GO' bit could be polled here if required\n                state <= Start;\n                phase <= \"00\";\n                scl_out <= '1';\n                sda_out <= '1';\n\n            -- STATE: START\n            elsif state = Start then\n                -- Generate START condition\n                case phase is\n                when \"00\" =>\n                    -- Drop SDA first\n                    sda_out <= '0';\n                when \"10\" =>\n                    -- Then drop SCL\n                    scl_out <= '0';\n                when \"11\" =>\n                    -- Advance to next state\n                    -- Shift register loaded with device slave address\n                    state <= Data;\n                    nbit <= 7;\n                    shiftreg <= std_logic_vector(to_unsigned(device_address,7)) & '0'; -- writing\n                    nbyte <= burst_length;\n                when others =>\n                    null;\n                end case;\n\n            -- STATE: DATA\n            elsif state = Data then\n                -- Generate data\n                case phase is\n                when \"00\" =>\n                    -- Drop SCL\n                    scl_out <= '0';\n                when \"01\" =>\n                    -- Output data and shift (MSb first)\n                    sda_out <= shiftreg(7);\n                    shiftreg <= shiftreg(6 downto 0) & '0';\n                when \"10\" =>\n                    -- Raise SCL\n                    scl_out <= '1';\n                when \"11\" =>\n                    -- Next bit or advance to next state when done\n                    if nbit = 0 then\n                        state <= Ack;\n                    else\n                        nbit <= nbit - 1;\n                    end if;\n                when others =>\n                  null;\n                end case;\n\n            -- STATE: ACK\n            elsif state = Ack then\n                -- Generate ACK clock and check for error condition\n                case phase is\n                when \"00\" =>\n                    -- Drop SCL\n                    scl_out <= '0';\n                when \"01\" =>\n                    -- Float data\n                    sda_out <= '1';\n                when \"10\" =>\n                    -- Sample ack bit\n                    nak <= I2C_SDA;\n                    if I2C_SDA = '1' then\n                        -- Error\n                        nbyte <= 0; -- Close this burst and skip remaining registers\n                        thisbyte <= init_regs'length;\n                    else\n                        -- Hold ACK to avoid spurious stops - this seems to fix a\n                        -- problem with the Wolfson codec which releases the ACK\n                        -- right on the falling edge of the clock pulse.  It looks like\n                        -- the device interprets this is a STOP condition and then fails\n                        -- to acknowledge the next byte.  We can avoid this by holding the\n                        -- ACK condition for a little longer.\n                        sda_out <= '0';\n                    end if;\n                    -- Raise SCL\n                    scl_out <= '1';\n                when \"11\" =>\n                    -- Advance to next state\n                    if nbyte = 0 then\n                        -- No more bytes in this burst - generate a STOP\n                        state <= Stop;\n                    else\n                        -- Generate next byte\n                        state <= Data;\n                        nbit <= 7;\n                        shiftreg <= init_regs(thisbyte);\n                        nbyte <= nbyte - 1;\n                        thisbyte <= thisbyte + 1;\n                    end if;\n                when others =>\n                    null;\n                end case;\n\n            -- STATE: STOP\n            elsif state = Stop then\n                -- Generate STOP condition\n                case phase is\n                when \"00\" =>\n                    -- Drop SCL first\n                    scl_out <= '0';\n                when \"01\" =>\n                    -- Drop SDA\n                    sda_out <= '0';\n                when \"10\" =>\n                    -- Raise SCL\n                    scl_out <= '1';\n                when \"11\" =>\n                    if thisbyte = init_regs'length then\n                        -- All registers done, advance to finished state.  This will\n                        -- bring SDA high while SCL is still high, completing the STOP\n                        -- condition\n                        state <= Done;\n                    else\n                        -- Load the next register after a short delay\n                        state <= Pause;\n                    end if;\n                when others =>\n                    null;\n                end case;\n\n            -- STATE: PAUSE\n            elsif state = Pause then\n                -- Delay for one cycle of 'phase' then start the next burst\n                scl_out <= '1';\n                sda_out <= '1';\n                if phase = \"11\" then\n                    state <= Start;\n                end if;\n\n            -- STATE: DONE\n            else\n                -- Finished\n                scl_out <= '1';\n                sda_out <= '1';\n\n                if nak = '1' and retries > 0 then\n                    -- We can retry in the event of a NAK in case the\n                    -- slave got out of sync for some reason\n                    retries <= retries - 1;\n                    state <= Idle;\n                end if;\n            end if;\n        end if;\n    end process;\nend i2c_loader_arch;\n\n"
  },
  {
    "path": "host/zxspectrum_de1/ula/i2s_intf.vhd",
    "content": "-- ZX Spectrum for Altera DE1\n--\n-- Copyright (c) 2009-2010 Mike Stirling\n--\n-- All rights reserved\n--\n-- Redistribution and use in source and synthezised forms, with or without\n-- modification, are permitted provided that the following conditions are met:\n--\n-- * Redistributions of source code must retain the above copyright notice,\n--   this list of conditions and the following disclaimer.\n--\n-- * Redistributions in synthesized form must reproduce the above copyright\n--   notice, this list of conditions and the following disclaimer in the\n--   documentation and/or other materials provided with the distribution.\n--\n-- * Neither the name of the author nor the names of other contributors may\n--   be used to endorse or promote products derived from this software without\n--   specific prior written permission.\n--\n-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\n-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE\n-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n-- POSSIBILITY OF SUCH DAMAGE.\n--\n\nlibrary IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\nuse IEEE.STD_LOGIC_ARITH.ALL;\nuse IEEE.STD_LOGIC_UNSIGNED.ALL;\n\nentity i2s_intf is\ngeneric(\n    mclk_rate : positive := 12000000;\n    sample_rate : positive := 8000;\n    preamble : positive := 1; -- I2S\n    word_length : positive := 16\n    );\n\nport (\n    -- 2x MCLK in (e.g. 24 MHz for WM8731 USB mode)\n    CLK         :   in  std_logic;\n    nRESET      :   in  std_logic;\n\n    -- Parallel IO\n    PCM_INL     :   out std_logic_vector(word_length - 1 downto 0);\n    PCM_INR     :   out std_logic_vector(word_length - 1 downto 0);\n    PCM_OUTL    :   in  std_logic_vector(word_length - 1 downto 0);\n    PCM_OUTR    :   in  std_logic_vector(word_length - 1 downto 0);\n\n    -- Codec interface (right justified mode)\n    -- MCLK is generated at half of the CLK input\n    I2S_MCLK    :   out std_logic;\n    -- LRCLK is equal to the sample rate and is synchronous to\n    -- MCLK.  It must be related to MCLK by the oversampling ratio\n    -- given in the codec datasheet.\n    I2S_LRCLK   :   out std_logic;\n\n    -- Data is shifted out on the falling edge of BCLK, sampled\n    -- on the rising edge.  The bit rate is determined such that\n    -- it is fast enough to fit preamble + word_length bits into\n    -- each LRCLK half cycle.  The last cycle of each word may be\n    -- stretched to fit to LRCLK.  This is OK at least for the\n    -- WM8731 codec.\n    -- The first falling edge of each timeslot is always synchronised\n    -- with the LRCLK edge.\n    I2S_BCLK    :   out std_logic;\n    -- Output bitstream\n    I2S_DOUT    :   out std_logic;\n    -- Input bitstream\n    I2S_DIN     :   in  std_logic\n    );\nend i2s_intf;\n\narchitecture i2s_intf_arch of i2s_intf is\nconstant ratio_mclk_fs : positive := (mclk_rate / sample_rate);\nconstant lrdivider_top : positive := (ratio_mclk_fs / 2) - 1;\nconstant bdivider_top : positive := (ratio_mclk_fs / 8 / (preamble + word_length) * 2) - 1;\nconstant nbits : positive := preamble + word_length;\n\nsubtype lrdivider_t is integer range 0 to lrdivider_top;\nsubtype bdivider_t is integer range 0 to bdivider_top;\nsubtype bitcount_t is integer range 0 to nbits;\n\nsignal lrdivider : lrdivider_t := lrdivider_top;\nsignal bdivider : bdivider_t := bdivider_top;\nsignal bitcount : bitcount_t := nbits;\n\nsignal mclk_r : std_logic;\nsignal lrclk_r : std_logic;\nsignal bclk_r : std_logic;\n\n-- Shift register is long enough for the number of data bits\n-- plus the preamble, plus an extra bit on the right to register\n-- the incoming data\nsignal shiftreg : std_logic_vector(nbits downto 0);\nbegin\n    I2S_MCLK <= mclk_r;\n    I2S_LRCLK <= lrclk_r;\n    I2S_BCLK <= bclk_r;\n    I2S_DOUT <= shiftreg(nbits); -- data goes out MSb first\n\n    process(nRESET,CLK)\n    begin\n        if nRESET = '0' then\n            PCM_INL <= (others => '0');\n            PCM_INR <= (others => '0');\n\n            -- Preload down-counters for clock generation\n            lrdivider <= lrdivider_top;\n            bdivider <= bdivider_top;\n            bitcount <= nbits;\n\n            mclk_r <= '0';\n            lrclk_r <= '0';\n            bclk_r <= '0';\n            shiftreg <= (others => '0');\n        elsif rising_edge(CLK) then\n            -- Generate MCLK at half input clock rate\n            mclk_r <= not mclk_r;\n\n            -- Generate LRCLK at rate specified by codec configuration\n            if lrdivider = 0 then\n                -- LRCLK divider has reached 0 - start again from the top\n                lrdivider <= lrdivider_top;\n\n                -- Generate LRCLK edge and sync the BCLK counter\n                lrclk_r <= not lrclk_r;\n                bclk_r <= '0';\n                bitcount <= nbits; -- 1 extra required for setup\n                bdivider <= bdivider_top;\n\n                -- Load shift register with output data padding preamble\n                -- with 0s.  Load output buses with input word from the\n                -- previous timeslot.\n                shiftreg(nbits downto nbits - preamble + 1) <= (others => '0');\n                if lrclk_r = '0' then\n                    -- Previous channel input is LEFT.  This is available in the\n                    -- shift register at the end of a cycle, right justified\n                    PCM_INL <= shiftreg(word_length - 1 downto 0);\n                    -- Next channel to output is RIGHT.  Load this into the\n                    -- shift register at the start of a cycle, left justified\n                    shiftreg(word_length downto 1) <= PCM_OUTR;\n                else\n                    -- Previous channel input is RIGHT\n                    PCM_INR <= shiftreg(word_length - 1 downto 0);\n                    -- Next channel is LEFT\n                    shiftreg(word_length downto 1) <= PCM_OUTL;\n                end if;\n            else\n                -- Decrement the LRCLK counter\n                lrdivider <= lrdivider - 1;\n\n                -- Generate BCLK at a suitable rate to fit the required number\n                -- of bits into each timeslot.  Data is changed on the falling edge,\n                -- sampled on the rising edge\n                if bdivider = 0 then\n                    -- If all bits have been output for this phase then\n                    -- stop and wait to sync back up with LRCLK\n                    if bitcount > 0 then\n                        -- Reset\n                        bdivider <= bdivider_top;\n\n                        -- Toggle BCLK\n                        bclk_r <= not bclk_r;\n                        if bclk_r = '0' then\n                            -- Rising edge - shift in current bit and decrement bit counter\n                            bitcount <= bitcount - 1;\n                            shiftreg(0) <= I2S_DIN;\n                        else\n                            -- Falling edge - shift out next bit\n                            shiftreg(nbits downto 1) <= shiftreg(nbits - 1 downto 0);\n                        end if;\n                    end if;\n                else\n                    -- Decrement the BCLK counter\n                    bdivider <= bdivider - 1;\n                end if;\n            end if;\n\n        end if;\n    end process;\nend i2s_intf_arch;\n\n"
  },
  {
    "path": "host/zxspectrum_de1/ula/pll.ppf",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\" ?>\n<!DOCTYPE pinplan>\n<pinplan intended_family=\"Cyclone II\" variation_name=\"pll\" megafunction_name=\"ALTPLL\" specifies=\"all_ports\">\n<global>\n<pin name=\"inclk0\" direction=\"input\" scope=\"external\" source=\"clock\"  />\n<pin name=\"c0\" direction=\"output\" scope=\"external\" source=\"clock\"  />\n<pin name=\"c1\" direction=\"output\" scope=\"external\" source=\"clock\"  />\n\n</global>\n</pinplan>\n"
  },
  {
    "path": "host/zxspectrum_de1/ula/pll.qip",
    "content": "set_global_assignment -name IP_TOOL_NAME \"ALTPLL\"\nset_global_assignment -name IP_TOOL_VERSION \"13.0\"\nset_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) \"pll.v\"]\nset_global_assignment -name MISC_FILE [file join $::quartus(qip_path) \"pll_inst.v\"]\nset_global_assignment -name MISC_FILE [file join $::quartus(qip_path) \"pll.ppf\"]\n"
  },
  {
    "path": "host/zxspectrum_de1/ula/pll.v",
    "content": "// megafunction wizard: %ALTPLL%\n// GENERATION: STANDARD\n// VERSION: WM1.0\n// MODULE: altpll \n\n// ============================================================\n// File Name: pll.v\n// Megafunction Name(s):\n// \t\t\taltpll\n//\n// Simulation Library Files(s):\n// \t\t\taltera_mf\n// ============================================================\n// ************************************************************\n// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!\n//\n// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition\n// ************************************************************\n\n\n//Copyright (C) 1991-2013 Altera Corporation\n//Your use of Altera Corporation's design tools, logic functions \n//and other software and tools, and its AMPP partner logic \n//functions, and any output files from any of the foregoing \n//(including device programming or simulation files), and any \n//associated documentation or information are expressly subject \n//to the terms and conditions of the Altera Program License \n//Subscription Agreement, Altera MegaCore Function License \n//Agreement, or other applicable license agreement, including, \n//without limitation, that your use is for the sole purpose of \n//programming logic devices manufactured by Altera and sold by \n//Altera or its authorized distributors.  Please refer to the \n//applicable agreement for further details.\n\n\n// synopsys translate_off\n`timescale 1 ps / 1 ps\n// synopsys translate_on\nmodule pll (\n\tinclk0,\n\tc0,\n\tc1);\n\n\tinput\t  inclk0;\n\toutput\t  c0;\n\toutput\t  c1;\n\n\twire [5:0] sub_wire0;\n\twire [0:0] sub_wire5 = 1'h0;\n\twire [1:1] sub_wire2 = sub_wire0[1:1];\n\twire [0:0] sub_wire1 = sub_wire0[0:0];\n\twire  c0 = sub_wire1;\n\twire  c1 = sub_wire2;\n\twire  sub_wire3 = inclk0;\n\twire [1:0] sub_wire4 = {sub_wire5, sub_wire3};\n\n\taltpll\taltpll_component (\n\t\t\t\t.inclk (sub_wire4),\n\t\t\t\t.clk (sub_wire0),\n\t\t\t\t.activeclock (),\n\t\t\t\t.areset (1'b0),\n\t\t\t\t.clkbad (),\n\t\t\t\t.clkena ({6{1'b1}}),\n\t\t\t\t.clkloss (),\n\t\t\t\t.clkswitch (1'b0),\n\t\t\t\t.configupdate (1'b0),\n\t\t\t\t.enable0 (),\n\t\t\t\t.enable1 (),\n\t\t\t\t.extclk (),\n\t\t\t\t.extclkena ({4{1'b1}}),\n\t\t\t\t.fbin (1'b1),\n\t\t\t\t.fbmimicbidir (),\n\t\t\t\t.fbout (),\n\t\t\t\t.fref (),\n\t\t\t\t.icdrclk (),\n\t\t\t\t.locked (),\n\t\t\t\t.pfdena (1'b1),\n\t\t\t\t.phasecounterselect ({4{1'b1}}),\n\t\t\t\t.phasedone (),\n\t\t\t\t.phasestep (1'b1),\n\t\t\t\t.phaseupdown (1'b1),\n\t\t\t\t.pllena (1'b1),\n\t\t\t\t.scanaclr (1'b0),\n\t\t\t\t.scanclk (1'b0),\n\t\t\t\t.scanclkena (1'b1),\n\t\t\t\t.scandata (1'b0),\n\t\t\t\t.scandataout (),\n\t\t\t\t.scandone (),\n\t\t\t\t.scanread (1'b0),\n\t\t\t\t.scanwrite (1'b0),\n\t\t\t\t.sclkout0 (),\n\t\t\t\t.sclkout1 (),\n\t\t\t\t.vcooverrange (),\n\t\t\t\t.vcounderrange ());\n\tdefparam\n\t\taltpll_component.clk0_divide_by = 1080,\n\t\taltpll_component.clk0_duty_cycle = 50,\n\t\taltpll_component.clk0_multiply_by = 1007,\n\t\taltpll_component.clk0_phase_shift = \"0\",\n\t\taltpll_component.clk1_divide_by = 27,\n\t\taltpll_component.clk1_duty_cycle = 50,\n\t\taltpll_component.clk1_multiply_by = 14,\n\t\taltpll_component.clk1_phase_shift = \"0\",\n\t\taltpll_component.compensate_clock = \"CLK0\",\n\t\taltpll_component.inclk0_input_frequency = 37037,\n\t\taltpll_component.intended_device_family = \"Cyclone II\",\n\t\taltpll_component.lpm_hint = \"CBX_MODULE_PREFIX=pll\",\n\t\taltpll_component.lpm_type = \"altpll\",\n\t\taltpll_component.operation_mode = \"NORMAL\",\n\t\taltpll_component.port_activeclock = \"PORT_UNUSED\",\n\t\taltpll_component.port_areset = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkbad0 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkbad1 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkloss = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkswitch = \"PORT_UNUSED\",\n\t\taltpll_component.port_configupdate = \"PORT_UNUSED\",\n\t\taltpll_component.port_fbin = \"PORT_UNUSED\",\n\t\taltpll_component.port_inclk0 = \"PORT_USED\",\n\t\taltpll_component.port_inclk1 = \"PORT_UNUSED\",\n\t\taltpll_component.port_locked = \"PORT_UNUSED\",\n\t\taltpll_component.port_pfdena = \"PORT_UNUSED\",\n\t\taltpll_component.port_phasecounterselect = \"PORT_UNUSED\",\n\t\taltpll_component.port_phasedone = \"PORT_UNUSED\",\n\t\taltpll_component.port_phasestep = \"PORT_UNUSED\",\n\t\taltpll_component.port_phaseupdown = \"PORT_UNUSED\",\n\t\taltpll_component.port_pllena = \"PORT_UNUSED\",\n\t\taltpll_component.port_scanaclr = \"PORT_UNUSED\",\n\t\taltpll_component.port_scanclk = \"PORT_UNUSED\",\n\t\taltpll_component.port_scanclkena = \"PORT_UNUSED\",\n\t\taltpll_component.port_scandata = \"PORT_UNUSED\",\n\t\taltpll_component.port_scandataout = \"PORT_UNUSED\",\n\t\taltpll_component.port_scandone = \"PORT_UNUSED\",\n\t\taltpll_component.port_scanread = \"PORT_UNUSED\",\n\t\taltpll_component.port_scanwrite = \"PORT_UNUSED\",\n\t\taltpll_component.port_clk0 = \"PORT_USED\",\n\t\taltpll_component.port_clk1 = \"PORT_USED\",\n\t\taltpll_component.port_clk2 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clk3 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clk4 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clk5 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkena0 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkena1 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkena2 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkena3 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkena4 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkena5 = \"PORT_UNUSED\",\n\t\taltpll_component.port_extclk0 = \"PORT_UNUSED\",\n\t\taltpll_component.port_extclk1 = \"PORT_UNUSED\",\n\t\taltpll_component.port_extclk2 = \"PORT_UNUSED\",\n\t\taltpll_component.port_extclk3 = \"PORT_UNUSED\";\n\n\nendmodule\n\n// ============================================================\n// CNX file retrieval info\n// ============================================================\n// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: BANDWIDTH STRING \"1.000\"\n// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING \"0\"\n// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING \"MHz\"\n// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING \"Low\"\n// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING \"1\"\n// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING \"0\"\n// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING \"0\"\n// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING \"0\"\n// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING \"c0\"\n// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING \"c0\"\n// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING \"7\"\n// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC \"1\"\n// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC \"1\"\n// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING \"50.00000000\"\n// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING \"50.00000000\"\n// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING \"25.174999\"\n// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING \"14.000000\"\n// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING \"0\"\n// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING \"0\"\n// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING \"1\"\n// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING \"1\"\n// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC \"1048575\"\n// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING \"0\"\n// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING \"27.000\"\n// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING \"MHz\"\n// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING \"50.000\"\n// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING \"1\"\n// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING \"1\"\n// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING \"MHz\"\n// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING \"Cyclone II\"\n// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING \"1\"\n// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING \"1\"\n// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING \"Not Available\"\n// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC \"0\"\n// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING \"deg\"\n// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING \"deg\"\n// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING \"Any\"\n// Retrieval info: PRIVATE: MIRROR_CLK0 STRING \"0\"\n// Retrieval info: PRIVATE: MIRROR_CLK1 STRING \"0\"\n// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC \"1\"\n// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC \"1\"\n// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING \"1\"\n// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING \"25.17500000\"\n// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING \"14.00000000\"\n// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING \"1\"\n// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING \"1\"\n// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING \"MHz\"\n// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING \"MHz\"\n// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING \"0\"\n// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING \"0.00000000\"\n// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING \"0.00000000\"\n// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING \"deg\"\n// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING \"deg\"\n// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC \"1\"\n// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC \"0\"\n// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC \"0\"\n// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC \"0\"\n// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC \"0\"\n// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING \"inclk0\"\n// Retrieval info: PRIVATE: RECONFIG_FILE STRING \"pll.mif\"\n// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING \"0\"\n// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING \"0\"\n// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING \"0\"\n// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING \"0\"\n// Retrieval info: PRIVATE: SPREAD_FREQ STRING \"50.000\"\n// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING \"KHz\"\n// Retrieval info: PRIVATE: SPREAD_PERCENT STRING \"0.500\"\n// Retrieval info: PRIVATE: SPREAD_USE STRING \"0\"\n// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING \"0\"\n// Retrieval info: PRIVATE: STICKY_CLK0 STRING \"1\"\n// Retrieval info: PRIVATE: STICKY_CLK1 STRING \"1\"\n// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC \"1\"\n// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING \"1\"\n// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING \"0\"\n// Retrieval info: PRIVATE: USE_CLK0 STRING \"1\"\n// Retrieval info: PRIVATE: USE_CLK1 STRING \"1\"\n// Retrieval info: PRIVATE: USE_CLKENA0 STRING \"0\"\n// Retrieval info: PRIVATE: USE_CLKENA1 STRING \"0\"\n// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC \"0\"\n// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING \"0\"\n// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all\n// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC \"1080\"\n// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC \"50\"\n// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC \"1007\"\n// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING \"0\"\n// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC \"27\"\n// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC \"50\"\n// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC \"14\"\n// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING \"0\"\n// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING \"CLK0\"\n// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC \"37037\"\n// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING \"Cyclone II\"\n// Retrieval info: CONSTANT: LPM_TYPE STRING \"altpll\"\n// Retrieval info: CONSTANT: OPERATION_MODE STRING \"NORMAL\"\n// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_ARESET STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_CLKLOSS STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_FBIN STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_INCLK0 STRING \"PORT_USED\"\n// Retrieval info: CONSTANT: PORT_INCLK1 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_LOCKED STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_PFDENA STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_PHASEDONE STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_PHASESTEP STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_PLLENA STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_SCANACLR STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_SCANCLK STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_SCANDATA STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_SCANDONE STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_SCANREAD STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_SCANWRITE STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clk0 STRING \"PORT_USED\"\n// Retrieval info: CONSTANT: PORT_clk1 STRING \"PORT_USED\"\n// Retrieval info: CONSTANT: PORT_clk2 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clk3 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clk4 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clk5 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clkena0 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clkena1 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clkena2 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clkena3 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clkena4 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clkena5 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_extclk0 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_extclk1 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_extclk2 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_extclk3 STRING \"PORT_UNUSED\"\n// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC \"@clk[5..0]\"\n// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC \"@extclk[3..0]\"\n// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC \"c0\"\n// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC \"c1\"\n// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND \"inclk0\"\n// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0\n// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0\n// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0\n// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1\n// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE\n// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE\n// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE\n// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE\n// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE\n// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v TRUE\n// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE\n// Retrieval info: LIB_FILE: altera_mf\n// Retrieval info: CBX_MODULE_PREFIX: ON\n"
  },
  {
    "path": "host/zxspectrum_de1/ula/ps2_kbd.sv",
    "content": "//============================================================================\n// PS/2 keyboard scan-code reader\n//\n//  Copyright (C) 2014-2016  Goran Devic\n//\n//  This program is free software; you can redistribute it and/or modify it\n//  under the terms of the GNU General Public License as published by the Free\n//  Software Foundation; either version 2 of the License, or (at your option)\n//  any later version.\n//\n//  This program is distributed in the hope that it will be useful, but WITHOUT\n//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n//  more details.\n//\n//  You should have received a copy of the GNU General Public License along\n//  with this program; if not, write to the Free Software Foundation, Inc.,\n//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n//============================================================================\nmodule ps2_keyboard\n(\n    input wire clk,\n    input wire nreset,          // Active low reset\n    input wire PS2_CLK,         // PS/2 keyboard clock line\n    input wire PS2_DAT,         // PS/2 keyboard data line\n\n    output wire [7:0] scan_code,// Completed keyboard scan code\n    output reg scan_code_ready, // Active for 1 clock: scan code is ready\n    output reg scan_code_error  // Error receiving keyboard data\n);\n\nreg [7:0] clk_filter;\nreg ps2_clk_in;\n\nreg clk_edge;\nreg [3:0] bit_count;\n\n// Shift register contains all the bits that are read so far; scan_code simply\n// mirrors it and becomes valid only when \"scan_code_ready\" is set\nreg [8:0] shiftreg;\nassign scan_code = shiftreg[7:0];\n\n// Compute parity on the fly; we only need it after the last bit is stored\nwire parity;\nassign parity = ^shiftreg[8:0];\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// Filter the PS/2 clock signal since it might have a noise (false '1')\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nalways @(posedge clk or negedge nreset)\nbegin\n    if (!nreset) begin\n        ps2_clk_in <= 1;\n        clk_filter <= 8'b1;\n        clk_edge <= 0;\n        end\n    else begin\n        // Filter in a new keyboard clock sample\n        clk_filter <= { PS2_CLK, clk_filter[7:1] };\n        clk_edge <= 0;\n\n        if (clk_filter==8'b1)\n            ps2_clk_in <= 1;\n        else if (clk_filter==8'b0) begin\n            // Filter clock is low, check for edge\n            if (ps2_clk_in==1)\n                clk_edge <= 1;\n            ps2_clk_in <= 0;\n        end\n    end\nend\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// State machine to process bits of PS/2 data\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nalways @(posedge clk or negedge nreset)\nbegin\n    if (!nreset) begin\n        bit_count <= '0;\n        shiftreg <= '0;\n        scan_code_ready <= 0;\n        scan_code_error <= 0;\n        end\n    else begin\n        scan_code_ready <= 0;\n        scan_code_error <= 0;\n        // We have a new valid clocked bit from the keyboard\n        if (clk_edge==1) begin\n            // Start condition, the bit count is 0\n            if (bit_count==0 && PS2_DAT==0)\n                    bit_count <= bit_count + 4'h1;\n            else begin\n                // Collecting up to 8 data bits and a parity bit\n                if (bit_count < 10) begin\n                    bit_count <= bit_count + 4'h1;\n                    shiftreg <= { PS2_DAT, shiftreg[8:1] };\n                    end\n                else\n                // Finalize: both the calculated parity and the stop bits should be '1'\n                begin\n                    bit_count <= '0;\n                    scan_code_ready <= { PS2_DAT, parity} == 2'b11;\n                    scan_code_error <= { PS2_DAT, parity} != 2'b11;\n                end\n            end\n        end\n    end\nend\n\nendmodule\n"
  },
  {
    "path": "host/zxspectrum_de1/ula/ram8.qip",
    "content": "set_global_assignment -name IP_TOOL_NAME \"RAM: 1-PORT\"\nset_global_assignment -name IP_TOOL_VERSION \"13.0\"\nset_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) \"ram8.v\"]\n"
  },
  {
    "path": "host/zxspectrum_de1/ula/ram8.v",
    "content": "// megafunction wizard: %RAM: 1-PORT%\n// GENERATION: STANDARD\n// VERSION: WM1.0\n// MODULE: altsyncram \n\n// ============================================================\n// File Name: ram8.v\n// Megafunction Name(s):\n// \t\t\taltsyncram\n//\n// Simulation Library Files(s):\n// \t\t\taltera_mf\n// ============================================================\n// ************************************************************\n// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!\n//\n// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition\n// ************************************************************\n\n\n//Copyright (C) 1991-2013 Altera Corporation\n//Your use of Altera Corporation's design tools, logic functions \n//and other software and tools, and its AMPP partner logic \n//functions, and any output files from any of the foregoing \n//(including device programming or simulation files), and any \n//associated documentation or information are expressly subject \n//to the terms and conditions of the Altera Program License \n//Subscription Agreement, Altera MegaCore Function License \n//Agreement, or other applicable license agreement, including, \n//without limitation, that your use is for the sole purpose of \n//programming logic devices manufactured by Altera and sold by \n//Altera or its authorized distributors.  Please refer to the \n//applicable agreement for further details.\n\n\n// synopsys translate_off\n`timescale 1 ps / 1 ps\n// synopsys translate_on\nmodule ram8 (\n\taddress,\n\tclock,\n\tdata,\n\twren,\n\tq);\n\n\tinput\t[12:0]  address;\n\tinput\t  clock;\n\tinput\t[7:0]  data;\n\tinput\t  wren;\n\toutput\t[7:0]  q;\n`ifndef ALTERA_RESERVED_QIS\n// synopsys translate_off\n`endif\n\ttri1\t  clock;\n`ifndef ALTERA_RESERVED_QIS\n// synopsys translate_on\n`endif\n\n\twire [7:0] sub_wire0;\n\twire [7:0] q = sub_wire0[7:0];\n\n\taltsyncram\taltsyncram_component (\n\t\t\t\t.address_a (address),\n\t\t\t\t.clock0 (clock),\n\t\t\t\t.data_a (data),\n\t\t\t\t.wren_a (wren),\n\t\t\t\t.q_a (sub_wire0),\n\t\t\t\t.aclr0 (1'b0),\n\t\t\t\t.aclr1 (1'b0),\n\t\t\t\t.address_b (1'b1),\n\t\t\t\t.addressstall_a (1'b0),\n\t\t\t\t.addressstall_b (1'b0),\n\t\t\t\t.byteena_a (1'b1),\n\t\t\t\t.byteena_b (1'b1),\n\t\t\t\t.clock1 (1'b1),\n\t\t\t\t.clocken0 (1'b1),\n\t\t\t\t.clocken1 (1'b1),\n\t\t\t\t.clocken2 (1'b1),\n\t\t\t\t.clocken3 (1'b1),\n\t\t\t\t.data_b (1'b1),\n\t\t\t\t.eccstatus (),\n\t\t\t\t.q_b (),\n\t\t\t\t.rden_a (1'b1),\n\t\t\t\t.rden_b (1'b1),\n\t\t\t\t.wren_b (1'b0));\n\tdefparam\n\t\taltsyncram_component.clock_enable_input_a = \"BYPASS\",\n\t\taltsyncram_component.clock_enable_output_a = \"BYPASS\",\n`ifdef NO_PLI\n\t\taltsyncram_component.init_file = \"test_scr.rif\"\n`else\n\t\taltsyncram_component.init_file = \"test_scr.hex\"\n`endif\n,\n\t\taltsyncram_component.intended_device_family = \"Cyclone II\",\n\t\taltsyncram_component.lpm_hint = \"ENABLE_RUNTIME_MOD=NO\",\n\t\taltsyncram_component.lpm_type = \"altsyncram\",\n\t\taltsyncram_component.numwords_a = 8192,\n\t\taltsyncram_component.operation_mode = \"SINGLE_PORT\",\n\t\taltsyncram_component.outdata_aclr_a = \"NONE\",\n\t\taltsyncram_component.outdata_reg_a = \"UNREGISTERED\",\n\t\taltsyncram_component.power_up_uninitialized = \"FALSE\",\n\t\taltsyncram_component.widthad_a = 13,\n\t\taltsyncram_component.width_a = 8,\n\t\taltsyncram_component.width_byteena_a = 1;\n\n\nendmodule\n\n// ============================================================\n// CNX file retrieval info\n// ============================================================\n// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC \"0\"\n// Retrieval info: PRIVATE: AclrAddr NUMERIC \"0\"\n// Retrieval info: PRIVATE: AclrByte NUMERIC \"0\"\n// Retrieval info: PRIVATE: AclrData NUMERIC \"0\"\n// Retrieval info: PRIVATE: AclrOutput NUMERIC \"0\"\n// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC \"0\"\n// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC \"8\"\n// Retrieval info: PRIVATE: BlankMemory NUMERIC \"0\"\n// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC \"0\"\n// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC \"0\"\n// Retrieval info: PRIVATE: Clken NUMERIC \"0\"\n// Retrieval info: PRIVATE: DataBusSeparated NUMERIC \"1\"\n// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC \"0\"\n// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING \"PORT_A\"\n// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC \"0\"\n// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING \"Cyclone II\"\n// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC \"0\"\n// Retrieval info: PRIVATE: JTAG_ID STRING \"NONE\"\n// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC \"0\"\n// Retrieval info: PRIVATE: MIFfilename STRING \"test_scr.hex\"\n// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC \"8192\"\n// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC \"0\"\n// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC \"3\"\n// Retrieval info: PRIVATE: RegAddr NUMERIC \"1\"\n// Retrieval info: PRIVATE: RegData NUMERIC \"1\"\n// Retrieval info: PRIVATE: RegOutput NUMERIC \"0\"\n// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING \"0\"\n// Retrieval info: PRIVATE: SingleClock NUMERIC \"1\"\n// Retrieval info: PRIVATE: UseDQRAM NUMERIC \"1\"\n// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC \"0\"\n// Retrieval info: PRIVATE: WidthAddr NUMERIC \"13\"\n// Retrieval info: PRIVATE: WidthData NUMERIC \"8\"\n// Retrieval info: PRIVATE: rden NUMERIC \"0\"\n// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all\n// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING \"BYPASS\"\n// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING \"BYPASS\"\n// Retrieval info: CONSTANT: INIT_FILE STRING \"test_scr.hex\"\n// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING \"Cyclone II\"\n// Retrieval info: CONSTANT: LPM_HINT STRING \"ENABLE_RUNTIME_MOD=NO\"\n// Retrieval info: CONSTANT: LPM_TYPE STRING \"altsyncram\"\n// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC \"8192\"\n// Retrieval info: CONSTANT: OPERATION_MODE STRING \"SINGLE_PORT\"\n// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING \"NONE\"\n// Retrieval info: CONSTANT: OUTDATA_REG_A STRING \"UNREGISTERED\"\n// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING \"FALSE\"\n// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC \"13\"\n// Retrieval info: CONSTANT: WIDTH_A NUMERIC \"8\"\n// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC \"1\"\n// Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL \"address[12..0]\"\n// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC \"clock\"\n// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL \"data[7..0]\"\n// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL \"q[7..0]\"\n// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL \"wren\"\n// Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0\n// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0\n// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0\n// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0\n// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0\n// Retrieval info: GEN_FILE: TYPE_NORMAL ram8.v TRUE\n// Retrieval info: GEN_FILE: TYPE_NORMAL ram8.inc FALSE\n// Retrieval info: GEN_FILE: TYPE_NORMAL ram8.cmp FALSE\n// Retrieval info: GEN_FILE: TYPE_NORMAL ram8.bsf FALSE\n// Retrieval info: GEN_FILE: TYPE_NORMAL ram8_inst.v FALSE\n// Retrieval info: GEN_FILE: TYPE_NORMAL ram8_bb.v FALSE\n// Retrieval info: LIB_FILE: altera_mf\n"
  },
  {
    "path": "host/zxspectrum_de1/ula/test_scr.hex",
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  },
  {
    "path": "host/zxspectrum_de1/ula/test_ula.qpf",
    "content": "# -------------------------------------------------------------------------- #\n#\n# Copyright (C) 1991-2013 Altera Corporation\n# Your use of Altera Corporation's design tools, logic functions \n# and other software and tools, and its AMPP partner logic \n# functions, and any output files from any of the foregoing \n# (including device programming or simulation files), and any \n# associated documentation or information are expressly subject \n# to the terms and conditions of the Altera Program License \n# Subscription Agreement, Altera MegaCore Function License \n# Agreement, or other applicable license agreement, including, \n# without limitation, that your use is for the sole purpose of \n# programming logic devices manufactured by Altera and sold by \n# Altera or its authorized distributors.  Please refer to the \n# applicable agreement for further details.\n#\n# -------------------------------------------------------------------------- #\n#\n# Quartus II 64-Bit\n# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\n# Date created = 18:31:55  October 13, 2014\n#\n# -------------------------------------------------------------------------- #\n\nQUARTUS_VERSION = \"13.0\"\nDATE = \"18:31:55  October 13, 2014\"\n\n# Revisions\n\nPROJECT_REVISION = \"test_ula\"\n"
  },
  {
    "path": "host/zxspectrum_de1/ula/test_ula.qsf",
    "content": "# -------------------------------------------------------------------------- #\n#\n# Copyright (C) 1991-2013 Altera Corporation\n# Your use of Altera Corporation's design tools, logic functions \n# and other software and tools, and its AMPP partner logic \n# functions, and any output files from any of the foregoing \n# (including device programming or simulation files), and any \n# associated documentation or information are expressly subject \n# to the terms and conditions of the Altera Program License \n# Subscription Agreement, Altera MegaCore Function License \n# Agreement, or other applicable license agreement, including, \n# without limitation, that your use is for the sole purpose of \n# programming logic devices manufactured by Altera and sold by \n# Altera or its authorized distributors.  Please refer to the \n# applicable agreement for further details.\n#\n# -------------------------------------------------------------------------- #\n#\n# Quartus II 64-Bit\n# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\n# Date created = 18:31:55  October 13, 2014\n#\n# -------------------------------------------------------------------------- #\n#\n# Notes:\n#\n# 1) The default values for assignments are stored in the file:\n#\t\tula_assignment_defaults.qdf\n#    If this file doesn't exist, see file:\n#\t\tassignment_defaults.qdf\n#\n# 2) Altera recommends that you do not modify this file. This\n#    file is updated automatically by the Quartus II software\n#    and any changes you make may be lost or overwritten.\n#\n# -------------------------------------------------------------------------- #\nset_global_assignment -name FAMILY \"Cyclone II\"\nset_global_assignment -name DEVICE EP2C20F484C7\nset_global_assignment -name TOP_LEVEL_ENTITY test_ula\nset_global_assignment -name ORIGINAL_QUARTUS_VERSION \"13.0 SP1\"\nset_global_assignment -name PROJECT_CREATION_TIME_DATE \"18:31:55  OCTOBER 13, 2014\"\nset_global_assignment -name LAST_QUARTUS_VERSION \"13.0 SP1\"\nset_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files\nset_global_assignment -name MIN_CORE_JUNCTION_TEMP 0\nset_global_assignment -name MAX_CORE_JUNCTION_TEMP 85\nset_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1\nset_global_assignment -name STRATIX_DEVICE_IO_STANDARD \"3.3-V LVTTL\"\n\n###########################################################################\n# System Clocks\n###########################################################################\nset_location_assignment PIN_D12 -to CLOCK_27\nset_location_assignment PIN_E12 -to CLOCK_27_1\nset_location_assignment PIN_B12 -to CLOCK_24\nset_location_assignment PIN_A12 -to CLOCK_24_1\nset_location_assignment PIN_L1 -to CLOCK_50\nset_location_assignment PIN_M21 -to EXT_CLOCK\nset_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_27\nset_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_27_1\nset_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_24\nset_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_24_1\nset_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_50\nset_instance_assignment -name IO_STANDARD LVTTL -to EXT_CLOCK\n\n###########################################################################\n# Pushbuttons\n###########################################################################\nset_location_assignment PIN_R22 -to KEY0\nset_location_assignment PIN_R21 -to KEY1\nset_location_assignment PIN_T22 -to KEY2\nset_location_assignment PIN_T21 -to KEY3\nset_instance_assignment -name IO_STANDARD LVTTL -to KEY0\nset_instance_assignment -name IO_STANDARD LVTTL -to KEY1\nset_instance_assignment -name IO_STANDARD LVTTL -to KEY2\nset_instance_assignment -name IO_STANDARD LVTTL -to KEY3\n\n###########################################################################\n# Toggle switches\n###########################################################################\nset_location_assignment PIN_L22 -to SW0\nset_location_assignment PIN_L21 -to SW1\nset_location_assignment PIN_M22 -to SW2\nset_location_assignment PIN_V12 -to SW3\nset_location_assignment PIN_W12 -to SW4\nset_location_assignment PIN_U12 -to SW5\nset_location_assignment PIN_U11 -to SW6\nset_location_assignment PIN_M2 -to SW7\nset_location_assignment PIN_M1 -to SW8\nset_location_assignment PIN_L2 -to SW9\nset_instance_assignment -name IO_STANDARD LVTTL -to SW0\nset_instance_assignment -name IO_STANDARD LVTTL -to SW1\nset_instance_assignment -name IO_STANDARD LVTTL -to SW2\nset_instance_assignment -name IO_STANDARD LVTTL -to SW3\nset_instance_assignment -name IO_STANDARD LVTTL -to SW4\nset_instance_assignment -name IO_STANDARD LVTTL -to SW5\nset_instance_assignment -name IO_STANDARD LVTTL -to SW6\nset_instance_assignment -name IO_STANDARD LVTTL -to SW7\nset_instance_assignment -name IO_STANDARD LVTTL -to SW8\nset_instance_assignment -name IO_STANDARD LVTTL -to SW9\n\n###########################################################################\n# LEDs\n###########################################################################\nset_location_assignment PIN_R20 -to LEDR[0]\nset_location_assignment PIN_R19 -to LEDR[1]\nset_location_assignment PIN_U19 -to LEDR[2]\nset_location_assignment PIN_Y19 -to LEDR[3]\nset_location_assignment PIN_T18 -to LEDR[4]\nset_location_assignment PIN_V19 -to LEDR[5]\nset_location_assignment PIN_Y18 -to LEDR[6]\nset_location_assignment PIN_U18 -to LEDR[7]\nset_location_assignment PIN_R18 -to LEDR[8]\nset_location_assignment PIN_R17 -to LEDR[9]\nset_location_assignment PIN_U22 -to LEDG[0]\nset_location_assignment PIN_U21 -to LEDG[1]\nset_location_assignment PIN_V22 -to LEDG[2]\nset_location_assignment PIN_V21 -to LEDG[3]\nset_location_assignment PIN_W22 -to LEDG[4]\nset_location_assignment PIN_W21 -to LEDG[5]\nset_location_assignment PIN_Y22 -to LEDG[6]\nset_location_assignment PIN_Y21 -to LEDG[7]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDR[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDR[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDR[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDR[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDR[4]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDR[5]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDR[6]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDR[7]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDR[8]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDR[9]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDG[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDG[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDG[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDG[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDG[4]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDG[5]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDG[6]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDG[7]\n\n###########################################################################\n# 7-Segment displays\n###########################################################################\nset_location_assignment PIN_J2 -to HEX0[0]\nset_location_assignment PIN_J1 -to HEX0[1]\nset_location_assignment PIN_H2 -to HEX0[2]\nset_location_assignment PIN_H1 -to HEX0[3]\nset_location_assignment PIN_F2 -to HEX0[4]\nset_location_assignment PIN_F1 -to HEX0[5]\nset_location_assignment PIN_E2 -to HEX0[6]\nset_location_assignment PIN_E1 -to HEX1[0]\nset_location_assignment PIN_H6 -to HEX1[1]\nset_location_assignment PIN_H5 -to HEX1[2]\nset_location_assignment PIN_H4 -to HEX1[3]\nset_location_assignment PIN_G3 -to HEX1[4]\nset_location_assignment PIN_D2 -to HEX1[5]\nset_location_assignment PIN_D1 -to HEX1[6]\nset_location_assignment PIN_G5 -to HEX2[0]\nset_location_assignment PIN_G6 -to HEX2[1]\nset_location_assignment PIN_C2 -to HEX2[2]\nset_location_assignment PIN_C1 -to HEX2[3]\nset_location_assignment PIN_E3 -to HEX2[4]\nset_location_assignment PIN_E4 -to HEX2[5]\nset_location_assignment PIN_D3 -to HEX2[6]\nset_location_assignment PIN_F4 -to HEX3[0]\nset_location_assignment PIN_D5 -to HEX3[1]\nset_location_assignment PIN_D6 -to HEX3[2]\nset_location_assignment PIN_J4 -to HEX3[3]\nset_location_assignment PIN_L8 -to HEX3[4]\nset_location_assignment PIN_F3 -to HEX3[5]\nset_location_assignment PIN_D4 -to HEX3[6]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX0[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX0[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX0[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX0[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX0[4]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX0[5]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX0[6]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX1[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX1[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX1[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX1[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX1[4]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX1[5]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX1[6]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX2[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX2[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX2[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX2[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX2[4]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX2[5]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX2[6]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX3[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX3[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX3[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX3[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX3[4]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX3[5]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX3[6]\n\n###########################################################################\n# VGA\n###########################################################################\nset_location_assignment PIN_D9 -to VGA_R[0]\nset_location_assignment PIN_C9 -to VGA_R[1]\nset_location_assignment PIN_A7 -to VGA_R[2]\nset_location_assignment PIN_B7 -to VGA_R[3]\nset_location_assignment PIN_B8 -to VGA_G[0]\nset_location_assignment PIN_C10 -to VGA_G[1]\nset_location_assignment PIN_B9 -to VGA_G[2]\nset_location_assignment PIN_A8 -to VGA_G[3]\nset_location_assignment PIN_A9 -to VGA_B[0]\nset_location_assignment PIN_D11 -to VGA_B[1]\nset_location_assignment PIN_A10 -to VGA_B[2]\nset_location_assignment PIN_B10 -to VGA_B[3]\nset_location_assignment PIN_A11 -to VGA_HS\nset_location_assignment PIN_B11 -to VGA_VS\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_HS\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_VS\n\n###########################################################################\n# Audio Codec\n###########################################################################\nset_location_assignment PIN_A3 -to I2C_SCLK\nset_location_assignment PIN_B3 -to I2C_SDAT\nset_location_assignment PIN_A6 -to AUD_ADCLRCK\nset_location_assignment PIN_B6 -to AUD_ADCDAT\nset_location_assignment PIN_A5 -to AUD_DACLRCK\nset_location_assignment PIN_B5 -to AUD_DACDAT\nset_location_assignment PIN_B4 -to AUD_XCK\nset_location_assignment PIN_A4 -to AUD_BCLK\nset_instance_assignment -name IO_STANDARD LVTTL -to I2C_SCLK\nset_instance_assignment -name IO_STANDARD LVTTL -to I2C_SDAT\nset_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCLRCK\nset_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCDAT\nset_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACLRCK\nset_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACDAT\nset_instance_assignment -name IO_STANDARD LVTTL -to AUD_XCK\nset_instance_assignment -name IO_STANDARD LVTTL -to AUD_BCLK\n\n###########################################################################\n# Serial (UART)\n###########################################################################\nset_location_assignment PIN_F14 -to UART_RXD\nset_location_assignment PIN_G12 -to UART_TXD\nset_instance_assignment -name IO_STANDARD LVTTL -to UART_RXD\nset_instance_assignment -name IO_STANDARD LVTTL -to UART_TXD\n\n###########################################################################\n# PS/2\n###########################################################################\nset_location_assignment PIN_H15 -to PS2_CLK\nset_location_assignment PIN_J14 -to PS2_DAT\nset_instance_assignment -name IO_STANDARD LVTTL -to PS2_CLK\nset_instance_assignment -name IO_STANDARD LVTTL -to PS2_DAT\n\n###########################################################################\n# SD Card\n###########################################################################\nset_location_assignment PIN_E8 -to TDI\nset_location_assignment PIN_D8 -to TCS\nset_location_assignment PIN_C7 -to TCK\nset_location_assignment PIN_D7 -to TDO\nset_instance_assignment -name IO_STANDARD LVTTL -to TDI\nset_instance_assignment -name IO_STANDARD LVTTL -to TCS\nset_instance_assignment -name IO_STANDARD LVTTL -to TCK\nset_instance_assignment -name IO_STANDARD LVTTL -to TDO\n\n###########################################################################\n# SDRAM\n###########################################################################\nset_location_assignment PIN_W4 -to DRAM_ADDR[0]\nset_location_assignment PIN_W5 -to DRAM_ADDR[1]\nset_location_assignment PIN_Y3 -to DRAM_ADDR[2]\nset_location_assignment PIN_Y4 -to DRAM_ADDR[3]\nset_location_assignment PIN_R6 -to DRAM_ADDR[4]\nset_location_assignment PIN_R5 -to DRAM_ADDR[5]\nset_location_assignment PIN_P6 -to DRAM_ADDR[6]\nset_location_assignment PIN_P5 -to DRAM_ADDR[7]\nset_location_assignment PIN_P3 -to DRAM_ADDR[8]\nset_location_assignment PIN_N4 -to DRAM_ADDR[9]\nset_location_assignment PIN_W3 -to DRAM_ADDR[10]\nset_location_assignment PIN_N6 -to DRAM_ADDR[11]\nset_location_assignment PIN_U1 -to DRAM_DQ[0]\nset_location_assignment PIN_U2 -to DRAM_DQ[1]\nset_location_assignment PIN_V1 -to DRAM_DQ[2]\nset_location_assignment PIN_V2 -to DRAM_DQ[3]\nset_location_assignment PIN_W1 -to DRAM_DQ[4]\nset_location_assignment PIN_W2 -to DRAM_DQ[5]\nset_location_assignment PIN_Y1 -to DRAM_DQ[6]\nset_location_assignment PIN_Y2 -to DRAM_DQ[7]\nset_location_assignment PIN_N1 -to DRAM_DQ[8]\nset_location_assignment PIN_N2 -to DRAM_DQ[9]\nset_location_assignment PIN_P1 -to DRAM_DQ[10]\nset_location_assignment PIN_P2 -to DRAM_DQ[11]\nset_location_assignment PIN_R1 -to DRAM_DQ[12]\nset_location_assignment PIN_R2 -to DRAM_DQ[13]\nset_location_assignment PIN_T1 -to DRAM_DQ[14]\nset_location_assignment PIN_T2 -to DRAM_DQ[15]\nset_location_assignment PIN_U3 -to DRAM_BA_0\nset_location_assignment PIN_V4 -to DRAM_BA_1\nset_location_assignment PIN_R7 -to DRAM_LDQM\nset_location_assignment PIN_M5 -to DRAM_UDQM\nset_location_assignment PIN_T5 -to DRAM_RAS_N\nset_location_assignment PIN_T3 -to DRAM_CAS_N\nset_location_assignment PIN_N3 -to DRAM_CKE\nset_location_assignment PIN_U4 -to DRAM_CLK\nset_location_assignment PIN_R8 -to DRAM_WE_N\nset_location_assignment PIN_T6 -to DRAM_CS_N\n\n###########################################################################\n# SRAM\n###########################################################################\nset_location_assignment PIN_AA3 -to SRAM_ADDR[0]\nset_location_assignment PIN_AB3 -to SRAM_ADDR[1]\nset_location_assignment PIN_AA4 -to SRAM_ADDR[2]\nset_location_assignment PIN_AB4 -to SRAM_ADDR[3]\nset_location_assignment PIN_AA5 -to SRAM_ADDR[4]\nset_location_assignment PIN_AB10 -to SRAM_ADDR[5]\nset_location_assignment PIN_AA11 -to SRAM_ADDR[6]\nset_location_assignment PIN_AB11 -to SRAM_ADDR[7]\nset_location_assignment PIN_V11 -to SRAM_ADDR[8]\nset_location_assignment PIN_W11 -to SRAM_ADDR[9]\nset_location_assignment PIN_R11 -to SRAM_ADDR[10]\nset_location_assignment PIN_T11 -to SRAM_ADDR[11]\nset_location_assignment PIN_Y10 -to SRAM_ADDR[12]\nset_location_assignment PIN_U10 -to SRAM_ADDR[13]\nset_location_assignment PIN_R10 -to SRAM_ADDR[14]\nset_location_assignment PIN_T7 -to SRAM_ADDR[15]\nset_location_assignment PIN_Y6 -to SRAM_ADDR[16]\nset_location_assignment PIN_Y5 -to SRAM_ADDR[17]\nset_location_assignment PIN_AA6 -to SRAM_DQ[0]\nset_location_assignment PIN_AB6 -to SRAM_DQ[1]\nset_location_assignment PIN_AA7 -to SRAM_DQ[2]\nset_location_assignment PIN_AB7 -to SRAM_DQ[3]\nset_location_assignment PIN_AA8 -to SRAM_DQ[4]\nset_location_assignment PIN_AB8 -to SRAM_DQ[5]\nset_location_assignment PIN_AA9 -to SRAM_DQ[6]\nset_location_assignment PIN_AB9 -to SRAM_DQ[7]\nset_location_assignment PIN_Y9 -to SRAM_DQ[8]\nset_location_assignment PIN_W9 -to SRAM_DQ[9]\nset_location_assignment PIN_V9 -to SRAM_DQ[10]\nset_location_assignment PIN_U9 -to SRAM_DQ[11]\nset_location_assignment PIN_R9 -to SRAM_DQ[12]\nset_location_assignment PIN_W8 -to SRAM_DQ[13]\nset_location_assignment PIN_V8 -to SRAM_DQ[14]\nset_location_assignment PIN_U8 -to SRAM_DQ[15]\nset_location_assignment PIN_AA10 -to SRAM_WE_N\nset_location_assignment PIN_T8 -to SRAM_OE_N\nset_location_assignment PIN_W7 -to SRAM_UB_N\nset_location_assignment PIN_Y7 -to SRAM_LB_N\nset_location_assignment PIN_AB5 -to SRAM_CE_N\n\n###########################################################################\n# FLASH\n###########################################################################\nset_location_assignment PIN_AB20 -to FL_ADDR[0]\nset_location_assignment PIN_AA14 -to FL_ADDR[1]\nset_location_assignment PIN_Y16 -to FL_ADDR[2]\nset_location_assignment PIN_R15 -to FL_ADDR[3]\nset_location_assignment PIN_T15 -to FL_ADDR[4]\nset_location_assignment PIN_U15 -to FL_ADDR[5]\nset_location_assignment PIN_V15 -to FL_ADDR[6]\nset_location_assignment PIN_W15 -to FL_ADDR[7]\nset_location_assignment PIN_R14 -to FL_ADDR[8]\nset_location_assignment PIN_Y13 -to FL_ADDR[9]\nset_location_assignment PIN_R12 -to FL_ADDR[10]\nset_location_assignment PIN_T12 -to FL_ADDR[11]\nset_location_assignment PIN_AB14 -to FL_ADDR[12]\nset_location_assignment PIN_AA13 -to FL_ADDR[13]\nset_location_assignment PIN_AB13 -to FL_ADDR[14]\nset_location_assignment PIN_AA12 -to FL_ADDR[15]\nset_location_assignment PIN_AB12 -to FL_ADDR[16]\nset_location_assignment PIN_AA20 -to FL_ADDR[17]\nset_location_assignment PIN_U14 -to FL_ADDR[18]\nset_location_assignment PIN_V14 -to FL_ADDR[19]\nset_location_assignment PIN_U13 -to FL_ADDR[20]\nset_location_assignment PIN_R13 -to FL_ADDR[21]\nset_location_assignment PIN_AB16 -to FL_DQ[0]\nset_location_assignment PIN_AA16 -to FL_DQ[1]\nset_location_assignment PIN_AB17 -to FL_DQ[2]\nset_location_assignment PIN_AA17 -to FL_DQ[3]\nset_location_assignment PIN_AB18 -to FL_DQ[4]\nset_location_assignment PIN_AA18 -to FL_DQ[5]\nset_location_assignment PIN_AB19 -to FL_DQ[6]\nset_location_assignment PIN_AA19 -to FL_DQ[7]\nset_location_assignment PIN_AB15 -to FL_CE_N\nset_location_assignment PIN_AA15 -to FL_OE_N\nset_location_assignment PIN_W14 -to FL_RST_N\nset_location_assignment PIN_Y14 -to FL_WE_N\n\n###########################################################################\n# GPIO-0 Expansion Header 1\n###########################################################################\nset_location_assignment PIN_A13 -to GPIO_0[0]\nset_location_assignment PIN_B13 -to GPIO_0[1]\nset_location_assignment PIN_A14 -to GPIO_0[2]\nset_location_assignment PIN_B14 -to GPIO_0[3]\nset_location_assignment PIN_A15 -to GPIO_0[4]\nset_location_assignment PIN_B15 -to GPIO_0[5]\nset_location_assignment PIN_A16 -to GPIO_0[6]\nset_location_assignment PIN_B16 -to GPIO_0[7]\nset_location_assignment PIN_A17 -to GPIO_0[8]\nset_location_assignment PIN_B17 -to GPIO_0[9]\nset_location_assignment PIN_A18 -to GPIO_0[10]\nset_location_assignment PIN_B18 -to GPIO_0[11]\nset_location_assignment PIN_A19 -to GPIO_0[12]\nset_location_assignment PIN_B19 -to GPIO_0[13]\nset_location_assignment PIN_A20 -to GPIO_0[14]\nset_location_assignment PIN_B20 -to GPIO_0[15]\nset_location_assignment PIN_C21 -to GPIO_0[16]\nset_location_assignment PIN_C22 -to GPIO_0[17]\nset_location_assignment PIN_D21 -to GPIO_0[18]\nset_location_assignment PIN_D22 -to GPIO_0[19]\nset_location_assignment PIN_E21 -to GPIO_0[20]\nset_location_assignment PIN_E22 -to GPIO_0[21]\nset_location_assignment PIN_F21 -to GPIO_0[22]\nset_location_assignment PIN_F22 -to GPIO_0[23]\nset_location_assignment PIN_G21 -to GPIO_0[24]\nset_location_assignment PIN_G22 -to GPIO_0[25]\nset_location_assignment PIN_J21 -to GPIO_0[26]\nset_location_assignment PIN_J22 -to GPIO_0[27]\nset_location_assignment PIN_K21 -to GPIO_0[28]\nset_location_assignment PIN_K22 -to GPIO_0[29]\nset_location_assignment PIN_J19 -to GPIO_0[30]\nset_location_assignment PIN_J20 -to GPIO_0[31]\nset_location_assignment PIN_J18 -to GPIO_0[32]\nset_location_assignment PIN_K20 -to GPIO_0[33]\nset_location_assignment PIN_L19 -to GPIO_0[34]\nset_location_assignment PIN_L18 -to GPIO_0[35]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[4]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[5]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[6]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[7]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[8]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[9]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[10]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[11]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[12]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[13]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[14]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[15]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[16]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[17]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[18]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[19]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[20]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[21]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[22]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[23]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[24]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[25]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[26]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[27]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[28]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[29]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[30]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[31]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[32]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[33]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[34]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[35]\n\n###########################################################################\n# GPIO-1 Expansion Header 2\n###########################################################################\nset_location_assignment PIN_H12 -to GPIO_1[0]\nset_location_assignment PIN_H13 -to GPIO_1[1]\nset_location_assignment PIN_H14 -to GPIO_1[2]\nset_location_assignment PIN_G15 -to GPIO_1[3]\nset_location_assignment PIN_E14 -to GPIO_1[4]\nset_location_assignment PIN_E15 -to GPIO_1[5]\nset_location_assignment PIN_F15 -to GPIO_1[6]\nset_location_assignment PIN_G16 -to GPIO_1[7]\nset_location_assignment PIN_F12 -to GPIO_1[8]\nset_location_assignment PIN_F13 -to GPIO_1[9]\nset_location_assignment PIN_C14 -to GPIO_1[10]\nset_location_assignment PIN_D14 -to GPIO_1[11]\nset_location_assignment PIN_D15 -to GPIO_1[12]\nset_location_assignment PIN_D16 -to GPIO_1[13]\nset_location_assignment PIN_C17 -to GPIO_1[14]\nset_location_assignment PIN_C18 -to GPIO_1[15]\nset_location_assignment PIN_C19 -to GPIO_1[16]\nset_location_assignment PIN_C20 -to GPIO_1[17]\nset_location_assignment PIN_D19 -to GPIO_1[18]\nset_location_assignment PIN_D20 -to GPIO_1[19]\nset_location_assignment PIN_E20 -to GPIO_1[20]\nset_location_assignment PIN_F20 -to GPIO_1[21]\nset_location_assignment PIN_E19 -to GPIO_1[22]\nset_location_assignment PIN_E18 -to GPIO_1[23]\nset_location_assignment PIN_G20 -to GPIO_1[24]\nset_location_assignment PIN_G18 -to GPIO_1[25]\nset_location_assignment PIN_G17 -to GPIO_1[26]\nset_location_assignment PIN_H17 -to GPIO_1[27]\nset_location_assignment PIN_J15 -to GPIO_1[28]\nset_location_assignment PIN_H18 -to GPIO_1[29]\nset_location_assignment PIN_N22 -to GPIO_1[30]\nset_location_assignment PIN_N21 -to GPIO_1[31]\nset_location_assignment PIN_P15 -to GPIO_1[32]\nset_location_assignment PIN_N15 -to GPIO_1[33]\nset_location_assignment PIN_P17 -to GPIO_1[34]\nset_location_assignment PIN_P18 -to GPIO_1[35]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[4]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[5]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[6]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[7]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[8]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[9]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[10]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[11]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[12]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[13]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[14]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[15]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[16]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[17]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[18]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[19]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[20]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[21]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[22]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[23]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[24]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[25]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[26]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[27]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[28]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[29]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[30]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[31]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[32]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[33]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[34]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[35]\n\nset_global_assignment -name USE_CONFIGURATION_DEVICE ON\nset_global_assignment -name RESERVE_ALL_UNUSED_PINS \"AS INPUT TRI-STATED WITH WEAK PULL-UP\"\nset_global_assignment -name POWER_PRESET_COOLING_SOLUTION \"23 MM HEAT SINK WITH 200 LFPM AIRFLOW\"\nset_global_assignment -name POWER_BOARD_THERMAL_MODEL \"NONE (CONSERVATIVE)\"\nset_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top\nset_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top\nset_global_assignment -name PARTITION_COLOR 16764057 -section_id Top\nset_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4\nset_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005\nset_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF\nset_global_assignment -name SMART_RECOMPILE ON\nset_global_assignment -name OPTIMIZE_HOLD_TIMING \"IO PATHS AND MINIMUM TPD PATHS\"\nset_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON\nset_global_assignment -name FITTER_EFFORT \"FAST FIT\"\nset_global_assignment -name QIP_FILE ram8.qip\nset_global_assignment -name QIP_FILE pll.qip\nset_global_assignment -name SYSTEMVERILOG_FILE test_ula.sv\nset_global_assignment -name SYSTEMVERILOG_FILE clocks.sv\nset_global_assignment -name SYSTEMVERILOG_FILE video.sv\nset_global_assignment -name SYSTEMVERILOG_FILE zx_kbd.sv\nset_global_assignment -name SYSTEMVERILOG_FILE ps2_kbd.sv\nset_global_assignment -name SYSTEMVERILOG_FILE uart_core.sv\nset_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top"
  },
  {
    "path": "host/zxspectrum_de1/ula/test_ula.sv",
    "content": "//============================================================================\n// Test Sinclair ZX Spectrum ULA\n//\n//  Copyright (C) 2014-2016  Goran Devic\n//\n//  This program is free software; you can redistribute it and/or modify it\n//  under the terms of the GNU General Public License as published by the Free\n//  Software Foundation; either version 2 of the License, or (at your option)\n//  any later version.\n//\n//  This program is distributed in the hope that it will be useful, but WITHOUT\n//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n//  more details.\n//\n//  You should have received a copy of the GNU General Public License along\n//  with this program; if not, write to the Free Software Foundation, Inc.,\n//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n//============================================================================\nmodule test_ula\n(\n    input wire CLOCK_50,        // Input clock 50 MHz\n    input wire CLOCK_27,        // Input clock 27 MHz\n    input wire KEY0,            // Button 0 is reset\n\n    output wire [3:0] VGA_R,\n    output wire [3:0] VGA_G,\n    output wire [3:0] VGA_B,\n    output reg VGA_HS,\n    output reg VGA_VS,\n\n    output wire [21:0] FL_ADDR,\n    input wire [7:0] FL_DQ,\n    output wire FL_CE_N,\n    output wire FL_OE_N,\n    output wire FL_RST_N,\n    output wire FL_WE_N,\n\n    input wire PS2_CLK,\n    input wire PS2_DAT,\n    output wire UART_TXD,\n\n    output wire [6:0] GPIO_0,   // Scope test points\n    input wire SW0,\n    input wire SW1,\n    input wire SW2\n);\n`default_nettype none\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// Instantiate PLL and clocks block\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nwire clk_pix;                   // VGA pixel clock (25.175 MHz)\nwire clk_ula;                   // ULA master clock (14 MHz)\npll pll_( .inclk0(CLOCK_27), .c0(clk_pix), .c1(clk_ula) );\n\nwire clk_cpu;                   // Clocks generates CPU clocks of 3.5 MHz\nclocks clocks_( .* );\n\n// Various scope test points, connect as needed:\n//assign GPIO_0[0] = CLOCK_27;\n//assign GPIO_0[1] = clk_pix;\n//assign GPIO_0[2] = clk_ula;\n//assign GPIO_0[3] = clk_cpu;\nassign GPIO_0[4] = VGA_VS;\nassign GPIO_0[5] = VGA_HS;\nassign GPIO_0[6] = VGA_B[0];\n\nassign GPIO_0[0] = PS2_CLK;\nassign GPIO_0[1] = PS2_DAT;\nassign GPIO_0[2] = UART_TXD;\nassign GPIO_0[3] = vs_nintr;\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// Instantiate RAM that contains a sample screen image\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nreg [12:0] vram_address;\nreg [7:0] vram_data;\nram8 ram8_( .address(vram_address), .clock(clk_pix), .data(0), .wren(0), .q(vram_data));\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// State register containing the border color index\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nreg [7:0] state;\n\n// Testing: assign the border color index based on the board switches\nwire [2:0] border;              // Border color index value\nassign border = { SW2, SW1, SW0 };\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// Instantiate ULA's video subsystem\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nwire vs_nintr;                  // Vertical retrace interrupt\n\nvideo video_( .*, .vram_address(vram_address), .vram_data(vram_data) );\n\n// Use flash interface instead of the internal RAM\nassign FL_CE_N = 0;\nassign FL_OE_N = 0;\nassign FL_RST_N = KEY0;\nassign FL_WE_N = 1;\nassign FL_ADDR[21:13] = 'b10;\n//video video_( .*, .vram_address(FL_ADDR[12:0]), .vram_data(FL_DQ) );\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// Instantiate keyboard support\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nwire [7:0] scan_code;\nwire scan_code_ready;\nwire scan_code_error;\n\nps2_keyboard ps2_keyboard_( .*, .clk(CLOCK_50), .reset(KEY0) );\n\nreg [15:0] A = 16'hFEFE;\nwire [4:0] key_row;\nzx_keyboard zx_keyboard_( .*, .clk(CLOCK_50), .reset(KEY0)  );\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// Add UART so we can echo keyboard through the serial port out\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nwire busy_tx;\nuart_core uart_core_( .*, .reset(!KEY0), .clk(CLOCK_50), .uart_tx(UART_TXD), .data_in(scan_code), .data_in_wr(scan_code_ready) );\n\nendmodule\n"
  },
  {
    "path": "host/zxspectrum_de1/ula/ula.sv",
    "content": "//============================================================================\n// Sinclair ZX Spectrum ULA\n//\n//  Copyright (C) 2014-2016  Goran Devic\n//\n//  This program is free software; you can redistribute it and/or modify it\n//  under the terms of the GNU General Public License as published by the Free\n//  Software Foundation; either version 2 of the License, or (at your option)\n//  any later version.\n//\n//  This program is distributed in the hope that it will be useful, but WITHOUT\n//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n//  more details.\n//\n//  You should have received a copy of the GNU General Public License along\n//  with this program; if not, write to the Free Software Foundation, Inc.,\n//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n//============================================================================\nmodule ula\n(\n    //-------- Clocks and reset -----------------\n    input wire CLOCK_27,            // Input clock 27 MHz\n    input wire CLOCK_24,            // Input clock 24 MHz\n    input wire turbo,               // Turbo speed (3.5 MHz x 2 = 7.0 MHz)\n    output wire clk_vram,\n    input wire nreset,              // Active low reset\n    output wire locked,             // PLL is locked signal\n\n    //-------- CPU control ----------------------\n    output wire clk_cpu,            // Generates CPU clock of 3.5 MHz\n    output wire vs_nintr,           // Generates a vertical retrace interrupt\n\n    //-------- Address and data buses -----------\n    input wire [15:0] A,            // Input address bus\n    input wire [7:0] D,             // Input data bus\n    output wire [7:0] ula_data,     // Output data\n    input wire io_we,               // Write enable to data register through IO\n\n    output wire [12:0] vram_address,// ULA video block requests a byte from the video RAM\n    input wire [7:0] vram_data,     // ULA video block reads a byte from the video RAM\n\n    //-------- PS/2 Keyboard --------------------\n    input wire PS2_CLK,\n    input wire PS2_DAT,\n    output wire pressed,\n\n    //-------- Audio (Tape player) --------------\n    inout wire I2C_SCLK,\n    inout wire I2C_SDAT,\n    output wire AUD_XCK,\n    output wire AUD_ADCLRCK,\n    output wire AUD_DACLRCK,\n    output wire AUD_BCLK,\n    output wire AUD_DACDAT,\n    input wire AUD_ADCDAT,\n    output reg beeper,\n\n    //-------- VGA connector --------------------\n    output wire [3:0] VGA_R,\n    output wire [3:0] VGA_G,\n    output wire [3:0] VGA_B,\n    output reg VGA_HS,\n    output reg VGA_VS\n);\n`default_nettype none\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// Instantiate PLL and clocks block\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nwire clk_pix;                       // VGA pixel clock (25.175 MHz)\nwire clk_ula;                       // ULA master clock (14 MHz)\nassign clk_vram = clk_pix;\npll pll_( .locked(locked), .inclk0(CLOCK_27), .c0(clk_pix), .c1(clk_ula) );\n\nclocks clocks_( .* );\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// The border color index\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nreg [2:0] border;                   // Border color index value\n\nalways @(posedge clk_cpu)\nbegin\n    if (A[0]==0 && io_we==1) begin\n        border <= D[2:0];\n        // EAR output (produces a louder sound)\n        pcm_outl[14] <= D[4];       // Why [14] and not [15]? Less loud.\n        pcm_outr[14] <= D[4];\n        // MIC (echoes the input)\n        pcm_outl[13] <= D[3];\n        pcm_outr[13] <= D[3];\n        // Let us hear the tape loading!\n        pcm_outl[12] <= pcm_inl[14] | pcm_inr[14];\n        pcm_outr[12] <= pcm_inl[14] | pcm_inr[14];\n        // Let us see the tape loading!\n        beep <= (pcm_inl[14] | pcm_inr[14]) ^ D[4] ^ D[3];\n    end\nend\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// Instantiate audio interface\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nwire audio_done;\nwire audio_error;\n\ni2c_loader i2c_loader_( .CLK(CLOCK_24), .nRESET(nreset), .I2C_SCL(I2C_SCLK), .I2C_SDA(I2C_SDAT), .IS_DONE(audio_done), .IS_ERROR(audio_error) );\n\nassign AUD_DACLRCK = AUD_ADCLRCK;\nwire [15:0] pcm_inl;\nwire [15:0] pcm_inr;\nreg  [15:0] pcm_outl;\nreg  [15:0] pcm_outr;\n\ni2s_intf i2s_intf_( .CLK(CLOCK_24), .nRESET(nreset),\n    .PCM_INL(pcm_inl[15:0]), .PCM_INR(pcm_inr[15:0]), .PCM_OUTL(pcm_outl[15:0]), .PCM_OUTR(pcm_outr[15:0]),\n    .I2S_MCLK(AUD_XCK), .I2S_LRCLK(AUD_ADCLRCK), .I2S_BCLK(AUD_BCLK), .I2S_DOUT(AUD_DACDAT), .I2S_DIN(AUD_ADCDAT) );\n\n// Show the beeper visually by dividing the frequency with some factor to generate LED blinks\nreg beep;                           // Beeper latch\nreg [6:0] beepcnt;                  // Beeper counter\nalways @(posedge beep)\nbegin\n    beepcnt <= beepcnt - '1;\n    if (beepcnt==0) beeper <= ~beeper;\nend\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// Instantiate ULA's video subsystem\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nvideo video_( .* );\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// Instantiate keyboard support\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nwire [7:0] scan_code;\nwire scan_code_ready;\nwire scan_code_error;\n\nps2_keyboard ps2_keyboard_( .*, .clk(clk_cpu) );\n\nwire [4:0] key_row;\nzx_keyboard zx_keyboard_( .*, .clk(clk_cpu) );\n\nalways_comb\nbegin\n    ula_data = 8'hFF;\n    // Regular IO at every odd address: line-in and keyboard\n    if (A[0]==0) begin\n        ula_data = { 1'b1, pcm_inl[14] | pcm_inr[14], 1'b1, key_row[4:0] };\n    end\nend\n\nendmodule\n"
  },
  {
    "path": "host/zxspectrum_de1/ula/video.sv",
    "content": "//============================================================================\n// Sinclair ZX Spectrum ULA\n//\n// This module contains video support.\n//\n// Note: There is no reset signal in this VGA design since all relevant\n//       counters will reset themselves within one display frame as the\n//       pixel clock keeps ticking.\n//\n//  Copyright (C) 2014-2016  Goran Devic\n//\n//  This program is free software; you can redistribute it and/or modify it\n//  under the terms of the GNU General Public License as published by the Free\n//  Software Foundation; either version 2 of the License, or (at your option)\n//  any later version.\n//\n//  This program is distributed in the hope that it will be useful, but WITHOUT\n//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n//  more details.\n//\n//  You should have received a copy of the GNU General Public License along\n//  with this program; if not, write to the Free Software Foundation, Inc.,\n//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n//============================================================================\nmodule video\n(\n    input wire clk_pix,         // Input VGA pixel clock of 25.175 MHz\n\n    output wire [3:0] VGA_R,    // Output VGA R component\n    output wire [3:0] VGA_G,    // Output VGA G component\n    output wire [3:0] VGA_B,    // Output VGA B component\n    output reg VGA_HS,          // Output VGA horizontal sync\n    output reg VGA_VS,          // Output VGA vertical sync\n    output wire vs_nintr,       // Vertical retrace interrupt\n\n    output wire [12:0] vram_address,// Address request to the video RAM\n    input wire [7:0] vram_data, // Data read from the video RAM\n\n    input wire [2:0] border     // Border color index value\n);\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// VGA 640x480 Sync pulses generator\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nreg [9:0] vga_hc;               // Horizontal counter\nreg [9:0] vga_vc;               // Vertical counter\nreg [4:0] frame;                // Frame counter, used for the flash attribute\n\nalways @(posedge clk_pix)\nbegin\n    vga_hc <= vga_hc + 10'b1;   // With each pixel clock, advance the horizontal counter\n    //---------------------------------------------------------------\n    // Horizontal sync and line end timings\n    //---------------------------------------------------------------\n    case (vga_hc)\n        96:     VGA_HS <= 1;\n        800: begin\n                VGA_HS <= 0;\n                vga_hc <= 0;\n                vga_vc <= vga_vc + 10'b1;\n             end\n    endcase\n    //---------------------------------------------------------------\n    // Vertical sync and display end timings\n    //---------------------------------------------------------------\n    case (vga_vc)\n        2:      VGA_VS <= 1;\n        525: begin\n                VGA_VS <= 0;\n                vga_vc <= 0;\n                frame  <= frame + 5'b1;\n             end\n    endcase\nend\n\n// Generate interrupt at around the time of the vertical retrace start\nassign vs_nintr = (vga_vc=='0 && vga_hc[9:7]=='0)? '0 : '1;\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// VGA active display area 640x480\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nwire disp_enable;\nassign disp_enable = vga_hc>=144 && vga_hc<784 && vga_vc>=35 && vga_vc<515;\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// Fetch screen data from RAM based on the current video counters\n// Spectrum resolution of 256x192 is line-doubled to 512x384 sub-frame\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nwire screen_en;\nassign screen_en = vga_hc>=208 && vga_hc<720 && vga_vc>=83 && vga_vc<467;\n\nreg [7:0] bits_prefetch;        // Line bitmap data prefetch register\nreg [7:0] attr_prefetch;        // Attribute data prefetch register\n\n// At the first clock of each new character, prefetch values are latched into these:\nreg [7:0] bits;                 // Current line bitmap data register\nreg [7:0] attr;                 // Current attribute data register\n\nwire [4:0] pix_x;               // Column 0-31\nwire [7:0] pix_y;               // Active display pixel Y coordinate\n// We use 16 clocks for 1 byte of display; also prefetch 1 byte (+16)\nwire [9:0] xd = vga_hc-10'd192; // =vga_hc-208+16\nassign pix_x = xd[8:4];         // Effectively divide by 16\nwire [9:0] yd = vga_vc-10'd83;  // Lines are (also) doubled vertically\nassign pix_y = yd[8:1];         // Effectively divide by 2\n\nalways @(posedge clk_pix)\nbegin\n    case (vga_hc[3:0])\n                // Format the address into the bitmap which is a swizzle of coordinate parts\n        10:     vram_address <= {pix_y[7:6], pix_y[2:0], pix_y[5:3], pix_x};\n        12:     begin\n                    bits_prefetch <= vram_data;\n                    // Format the address into the attribute map\n                    vram_address <= {3'b110, pix_y[7:3], pix_x};\n                end\n        14:     attr_prefetch <= vram_data;\n        // Last tick before a new character: load working bitmap and attribute registers\n        15:     begin\n                    attr <= attr_prefetch;\n                    bits <= bits_prefetch;\n                end\n    endcase\nend\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// Pixel data generator\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nwire [2:0] ink;                 // INK color (index into the palette)\nwire [2:0] paper;               // PAPER color\nwire bright;                    // BRIGHT attribute bit\nwire flash;                     // FLASH attribute bit\nwire pixbit;                    // Current pixel to render\nwire inverted;                  // Are the pixel's attributes inverted?\n\n// Output a pixel bit based on the VGA horizontal counter. This could have been\n// a shift register but a mux works as well since we are writing out each pixel\n// twice (required by this VGA clock rate)\nalways @(*) // always_comb\nbegin\n    case (vga_hc[3:1])\n        0:      pixbit = bits[7];\n        1:      pixbit = bits[6];\n        2:      pixbit = bits[5];\n        3:      pixbit = bits[4];\n        4:      pixbit = bits[3];\n        5:      pixbit = bits[2];\n        6:      pixbit = bits[1];\n        7:      pixbit = bits[0];\n    endcase\nend\n\nassign flash  = attr[7];\nassign bright = attr[6];\nassign inverted = flash & frame[4];\nassign ink    = inverted? attr[5:3] : attr[2:0];\nassign paper  = inverted? attr[2:0] : attr[5:3];\n\n// The final color index depends on where we are (active display area, border) and\n// whether we are rendering INK or PAPER color, including the brightness bit\nassign cindex = screen_en? pixbit? {bright,ink} : {bright,paper} : {1'b0,border[2:0]};\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// Color lookup table\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nwire [3:0] cindex;\nwire [11:0] pix_rgb;\n\nalways @(*) // always_comb\nbegin\n    case (cindex[3:0])\n        // Normal color\n        0:   pix_rgb = 12'h000; // BLACK\n        1:   pix_rgb = 12'h00D; // BLUE\n        2:   pix_rgb = 12'hD00; // RED\n        3:   pix_rgb = 12'hD0D; // MAGENTA\n        4:   pix_rgb = 12'h0D0; // GREEN\n        5:   pix_rgb = 12'h0DD; // CYAN\n        6:   pix_rgb = 12'hDD0; // YELLOW\n        7:   pix_rgb = 12'hDDD; // WHITE\n        // \"Bright\" bit is set\n        8:   pix_rgb = 12'h000; // BLACK remains black\n        9:   pix_rgb = 12'h00F;\n        10:  pix_rgb = 12'hF00;\n        11:  pix_rgb = 12'hF0F;\n        12:  pix_rgb = 12'h0F0;\n        13:  pix_rgb = 12'h0FF;\n        14:  pix_rgb = 12'hFF0;\n        15:  pix_rgb = 12'hFFF;\n    endcase\nend\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// VGA RGB output drivers\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nassign VGA_R[3:0] = disp_enable? pix_rgb[11:8] : '0;\nassign VGA_G[3:0] = disp_enable? pix_rgb[7:4]  : '0;\nassign VGA_B[3:0] = disp_enable? pix_rgb[3:0]  : '0;\n\nendmodule\n"
  },
  {
    "path": "host/zxspectrum_de1/ula/zx_kbd.sv",
    "content": "//============================================================================\n// ZX Spectrum keyboard input\n//\n// This module takes scan-codes from the attached PS/2 keyboard and sets\n// corresponding ZX key bitfields which are read by the 'IN' instructions.\n//\n// PS/2      |  ZX Spectrum\n// ----------+-----------------\n// CTRL      |  CAPS SHIFT\n// ALT       |  SYMBOL SHIFT\n//\n// For convenience, in addition to regular alpha-numeric keys, this code\n// simulates several other standard symbols on the PS/2 keyboard.\n//\n// PS/2      |  ZX Spectrum\n// ----------+-----------------\n// BACKSPACE |  DELETE\n// Arrows Left, Right, Up, Down\n// ESC       |  BREAK (CAPS+SPACE)\n// SHIFT => PS/2 shift for additional keys: -_ += ;: \"' <, >. ?/\n//\n//  Copyright (C) 2014-2016  Goran Devic\n//\n//  This program is free software; you can redistribute it and/or modify it\n//  under the terms of the GNU General Public License as published by the Free\n//  Software Foundation; either version 2 of the License, or (at your option)\n//  any later version.\n//\n//  This program is distributed in the hope that it will be useful, but WITHOUT\n//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n//  more details.\n//\n//  You should have received a copy of the GNU General Public License along\n//  with this program; if not, write to the Free Software Foundation, Inc.,\n//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n//============================================================================\nmodule zx_keyboard\n(\n    input wire clk,\n    input wire nreset,          // Active low reset\n\n    // Output ZX-specific keyboard codes when requested by the ULA access\n    input wire [15:0] A,        // Address bus\n    output wire [4:0] key_row,  // Output the state of a requested row of keys\n\n    // Input key scan codes from the PS/2 keyboard\n    input wire [7:0] scan_code, // PS/2 scan-code\n    input wire scan_code_ready, // Active for 1 clock: a scan code is ready\n    input wire scan_code_error, // Error receiving PS/2 keyboard data\n    output wire pressed         // Signal that a key is pressed\n);\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n//\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nreg [4:0] keys [0:7];       // 8 rows of 5 bits each: contains 0 for a pressed key at a specific location, 1 otherwise\n\nreg released;               // Tracks \"released\" scan code (F0): contains 0 when a key is pressed, 1 otherwise\nreg extended;               // Tracks \"extended\" scan code (E0)\nreg shifted;                // Tracks local \"shifted\" state\n\n// Calculate a \"key is pressed\" signal\nassign pressed = ~(&keys[7] & &keys[6] & &keys[5] & &keys[4] & &keys[3] & &keys[2] & &keys[1] & &keys[0]);\n\n// Output requested row of keys continously\nassign key_row =\n    (~A[8]  ? keys[0] : 5'b11111) &\n    (~A[9]  ? keys[1] : 5'b11111) &\n    (~A[10] ? keys[2] : 5'b11111) &\n    (~A[11] ? keys[3] : 5'b11111) &\n    (~A[12] ? keys[4] : 5'b11111) &\n    (~A[13] ? keys[5] : 5'b11111) &\n    (~A[14] ? keys[6] : 5'b11111) &\n    (~A[15] ? keys[7] : 5'b11111);\n\nalways @(posedge clk or negedge nreset)\nbegin\n    if (!nreset) begin\n        released <= 0;\n        extended <= 0;\n        shifted  <= 0;\n\n        keys[0] <= '1;\n        keys[1] <= '1;\n        keys[2] <= '1;\n        keys[3] <= '1;\n        keys[4] <= '1;\n        keys[5] <= '1;\n        keys[6] <= '1;\n        keys[7] <= '1;\n    end else\n    if (scan_code_ready) begin\n        if (scan_code==8'hE0) // Extended code prefix byte\n            extended <= 1;\n        else if (scan_code==8'hF0) // Break code prefix byte\n            released <= 1;\n        else begin\n            // Cancel release/extended flags for the next clock\n            extended <= 0;\n            released <= 0;\n\n            if (extended) begin\n                // Extended keys\n                case (scan_code)\n                    8'h6B:  begin                       // LEFT\n                            keys[0][0] <= released;     // CAPS SHIFT\n                            keys[3][4] <= released;     // 5\n                            end\n                    8'h72:  begin                       // DOWN\n                            keys[0][0] <= released;     // CAPS SHIFT\n                            keys[4][4] <= released;     // 6\n                            end\n                    8'h75:  begin                       // UP\n                            keys[0][0] <= released;     // CAPS SHIFT\n                            keys[4][3] <= released;     // 7\n                            end\n                    8'h74:  begin                       // RIGHT\n                            keys[0][0] <= released;     // CAPS SHIFT\n                            keys[4][2] <= released;     // 8\n                            end\n                endcase\n            end\n            else begin\n                // For each PS/2 scan-code, set the ZX keyboard matrix state\n                case (scan_code)\n                    8'h12:  shifted <= !released;       // Local SHIFT key (left)\n                    8'h59:  shifted <= !released;       // Local SHIFT key (right)\n\n                    8'h14:  keys[0][0] <= released;     // CAPS SHIFT = Left or right Ctrl\n\n                    8'h1A:  keys[0][1] <= released;     // Z\n                    8'h22:  keys[0][2] <= released;     // X\n                    8'h21:  keys[0][3] <= released;     // C\n                    8'h2A:  keys[0][4] <= released;     // V\n\n                    8'h1C:  keys[1][0] <= released;     // A\n                    8'h1B:  keys[1][1] <= released;     // S\n                    8'h23:  keys[1][2] <= released;     // D\n                    8'h2B:  keys[1][3] <= released;     // F\n                    8'h34:  keys[1][4] <= released;     // G\n\n                    8'h15:  keys[2][0] <= released;     // Q\n                    8'h1D:  keys[2][1] <= released;     // W\n                    8'h24:  keys[2][2] <= released;     // E\n                    8'h2D:  keys[2][3] <= released;     // R\n                    8'h2C:  keys[2][4] <= released;     // T\n\n                    8'h16:  keys[3][0] <= released;     // 1\n                    8'h1E:  keys[3][1] <= released;     // 2\n                    8'h26:  keys[3][2] <= released;     // 3\n                    8'h25:  keys[3][3] <= released;     // 4\n                    8'h2E:  keys[3][4] <= released;     // 5\n\n                    8'h45:  keys[4][0] <= released;     // 0\n                    8'h46:  keys[4][1] <= released;     // 9\n                    8'h3E:  keys[4][2] <= released;     // 8\n                    8'h3D:  keys[4][3] <= released;     // 7\n                    8'h36:  keys[4][4] <= released;     // 6\n\n                    8'h4D:  keys[5][0] <= released;     // P\n                    8'h44:  keys[5][1] <= released;     // O\n                    8'h43:  keys[5][2] <= released;     // I\n                    8'h3C:  keys[5][3] <= released;     // U\n                    8'h35:  keys[5][4] <= released;     // Y\n\n                    8'h5A:  keys[6][0] <= released;     // ENTER\n                    8'h4B:  keys[6][1] <= released;     // L\n                    8'h42:  keys[6][2] <= released;     // K\n                    8'h3B:  keys[6][3] <= released;     // J\n                    8'h33:  keys[6][4] <= released;     // H\n\n                    8'h29:  keys[7][0] <= released;     // SPACE\n                    8'h11:  keys[7][1] <= released;     // SYMBOL SHIFT (Red) = Left and right Alt\n                    8'h3A:  keys[7][2] <= released;     // M\n                    8'h31:  keys[7][3] <= released;     // N\n                    8'h32:  keys[7][4] <= released;     // B\n\n                    8'h66:  begin                       // BACKSPACE\n                            keys[0][0] <= released;\n                            keys[4][0] <= released;\n                            end\n                    8'h76:  begin                       // ESC -> BREAK\n                            keys[0][0] <= released;     // CAPS SHIFT\n                            keys[7][0] <= released;     // SPACE\n                            end\n                    // With shifted keys, we need to make inactive (set to 1) other corresponding key\n                    // Otherwise, it will stay active if the shift was released first\n                    8'h4E:  begin                       // - or (shifted) _\n                            keys[7][1] <= released;     // SYMBOL SHIFT (Red)\n                            keys[4][0] <= shifted ? released : 1'b1;     // 0\n                            keys[6][3] <= shifted ? 1'b1 : released;     // J\n                            end\n                    8'h55:  begin                       // = or (shifted) +\n                            keys[7][1] <= released;     // SYMBOL SHIFT (Red)\n                            keys[6][2] <= shifted ? released : 1'b1;     // K\n                            keys[6][1] <= shifted ? 1'b1 : released;     // L\n                            end\n                    8'h52:  begin                       // ' or (shifted) \"\n                            keys[7][1] <= released;     // SYMBOL SHIFT (Red)\n                            keys[5][0] <= shifted ? released : 1'b1;     // P\n                            keys[4][3] <= shifted ? 1'b1 : released;     // 7\n                            end\n                    8'h4C:  begin                       // ; or (shifted) :\n                            keys[7][1] <= released;     // SYMBOL SHIFT (Red)\n                            keys[0][1] <= shifted ? released : 1'b1;     // Z\n                            keys[5][1] <= shifted ? 1'b1 : released;     // O\n                            end\n                    8'h41:  begin                       // , or (shifted) <\n                            keys[7][1] <= released;     // SYMBOL SHIFT (Red)\n                            keys[2][3] <= shifted ? released : 1'b1;     // R\n                            keys[7][3] <= shifted ? 1'b1 : released;     // N\n                            end\n                    8'h49:  begin                       // . or (shifted) >\n                            keys[7][1] <= released;     // SYMBOL SHIFT (Red)\n                            keys[2][4] <= shifted ? released : 1'b1;     // T\n                            keys[7][2] <= shifted ? 1'b1 : released;     // M\n                            end\n                    8'h4A:  begin                       // / or (shifted) ?\n                            keys[7][1] <= released;     // SYMBOL SHIFT (Red)\n                            keys[0][3] <= shifted ? released : 1'b1;     // C\n                            keys[0][4] <= shifted ? 1'b1 : released;     // V\n                            end\n                endcase\n            end\n        end\n    end\nend\n\nendmodule\n"
  },
  {
    "path": "host/zxspectrum_de1/zxspectrum_de1.qpf",
    "content": "# -------------------------------------------------------------------------- #\n#\n# Copyright (C) 1991-2013 Altera Corporation\n# Your use of Altera Corporation's design tools, logic functions\n# and other software and tools, and its AMPP partner logic\n# functions, and any output files from any of the foregoing\n# (including device programming or simulation files), and any\n# associated documentation or information are expressly subject\n# to the terms and conditions of the Altera Program License\n# Subscription Agreement, Altera MegaCore Function License\n# Agreement, or other applicable license agreement, including,\n# without limitation, that your use is for the sole purpose of\n# programming logic devices manufactured by Altera and sold by\n# Altera or its authorized distributors.  Please refer to the\n# applicable agreement for further details.\n#\n# -------------------------------------------------------------------------- #\n#\n# Quartus II 64-Bit\n# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\n# Date created = 23:30:28  October 14, 2014\n#\n# -------------------------------------------------------------------------- #\n\nQUARTUS_VERSION = \"13.0\"\nDATE = \"23:30:28  October 14, 2014\"\n\n# Revisions\n\nPROJECT_REVISION = \"zxspectrum_de1\"\n"
  },
  {
    "path": "host/zxspectrum_de1/zxspectrum_de1.qsf",
    "content": "# -------------------------------------------------------------------------- #\n#\n# Copyright (C) 1991-2013 Altera Corporation\n# Your use of Altera Corporation's design tools, logic functions\n# and other software and tools, and its AMPP partner logic\n# functions, and any output files from any of the foregoing\n# (including device programming or simulation files), and any\n# associated documentation or information are expressly subject\n# to the terms and conditions of the Altera Program License\n# Subscription Agreement, Altera MegaCore Function License\n# Agreement, or other applicable license agreement, including,\n# without limitation, that your use is for the sole purpose of\n# programming logic devices manufactured by Altera and sold by\n# Altera or its authorized distributors.  Please refer to the\n# applicable agreement for further details.\n#\n# -------------------------------------------------------------------------- #\n#\n# Quartus II 64-Bit\n# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\n# Date created = 23:30:28  October 14, 2014\n#\n# -------------------------------------------------------------------------- #\n#\n# Notes:\n#\n# 1) The default values for assignments are stored in the file:\n#       zxspectrum_board_assignment_defaults.qdf\n#    If this file doesn't exist, see file:\n#       assignment_defaults.qdf\n#\n# 2) Altera recommends that you do not modify this file. This\n#    file is updated automatically by the Quartus II software\n#    and any changes you make may be lost or overwritten.\n#\n# -------------------------------------------------------------------------- #\n\n###########################################################################\n# System Clocks\n###########################################################################\nset_location_assignment PIN_D12 -to CLOCK_27\nset_location_assignment PIN_E12 -to CLOCK_27_1\nset_location_assignment PIN_B12 -to CLOCK_24\nset_location_assignment PIN_A12 -to CLOCK_24_1\nset_location_assignment PIN_L1 -to CLOCK_50\nset_location_assignment PIN_M21 -to EXT_CLOCK\nset_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_27\nset_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_27_1\nset_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_24\nset_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_24_1\nset_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_50\nset_instance_assignment -name IO_STANDARD LVTTL -to EXT_CLOCK\n\n###########################################################################\n# Pushbuttons\n###########################################################################\nset_location_assignment PIN_R22 -to KEY0\nset_location_assignment PIN_R21 -to KEY1\nset_location_assignment PIN_T22 -to KEY2\nset_location_assignment PIN_T21 -to KEY3\nset_instance_assignment -name IO_STANDARD LVTTL -to KEY0\nset_instance_assignment -name IO_STANDARD LVTTL -to KEY1\nset_instance_assignment -name IO_STANDARD LVTTL -to KEY2\nset_instance_assignment -name IO_STANDARD LVTTL -to KEY3\n\n###########################################################################\n# Toggle switches\n###########################################################################\nset_location_assignment PIN_L22 -to SW0\nset_location_assignment PIN_L21 -to SW1\nset_location_assignment PIN_M22 -to SW2\nset_location_assignment PIN_V12 -to SW3\nset_location_assignment PIN_W12 -to SW4\nset_location_assignment PIN_U12 -to SW5\nset_location_assignment PIN_U11 -to SW6\nset_location_assignment PIN_M2 -to SW7\nset_location_assignment PIN_M1 -to SW8\nset_location_assignment PIN_L2 -to SW9\nset_instance_assignment -name IO_STANDARD LVTTL -to SW0\nset_instance_assignment -name IO_STANDARD LVTTL -to SW1\nset_instance_assignment -name IO_STANDARD LVTTL -to SW2\nset_instance_assignment -name IO_STANDARD LVTTL -to SW3\nset_instance_assignment -name IO_STANDARD LVTTL -to SW4\nset_instance_assignment -name IO_STANDARD LVTTL -to SW5\nset_instance_assignment -name IO_STANDARD LVTTL -to SW6\nset_instance_assignment -name IO_STANDARD LVTTL -to SW7\nset_instance_assignment -name IO_STANDARD LVTTL -to SW8\nset_instance_assignment -name IO_STANDARD LVTTL -to SW9\n\n###########################################################################\n# LEDs\n###########################################################################\nset_location_assignment PIN_R20 -to LEDR[0]\nset_location_assignment PIN_R19 -to LEDR[1]\nset_location_assignment PIN_U19 -to LEDR[2]\nset_location_assignment PIN_Y19 -to LEDR[3]\nset_location_assignment PIN_T18 -to LEDR[4]\nset_location_assignment PIN_V19 -to LEDR[5]\nset_location_assignment PIN_Y18 -to LEDR[6]\nset_location_assignment PIN_U18 -to LEDR[7]\nset_location_assignment PIN_R18 -to LEDR[8]\nset_location_assignment PIN_R17 -to LEDR[9]\nset_location_assignment PIN_U22 -to LEDG[0]\nset_location_assignment PIN_U21 -to LEDG[1]\nset_location_assignment PIN_V22 -to LEDG[2]\nset_location_assignment PIN_V21 -to LEDG[3]\nset_location_assignment PIN_W22 -to LEDG[4]\nset_location_assignment PIN_W21 -to LEDGTOP[0]\nset_location_assignment PIN_Y22 -to LEDGTOP[1]\nset_location_assignment PIN_Y21 -to LEDGTOP[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDR[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDR[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDR[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDR[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDR[4]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDR[5]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDR[6]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDR[7]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDR[8]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDR[9]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDG[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDG[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDG[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDG[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDG[4]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDGTOP[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDGTOP[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to LEDGTOP[2]\n\n###########################################################################\n# 7-Segment displays\n###########################################################################\nset_location_assignment PIN_J2 -to HEX0[0]\nset_location_assignment PIN_J1 -to HEX0[1]\nset_location_assignment PIN_H2 -to HEX0[2]\nset_location_assignment PIN_H1 -to HEX0[3]\nset_location_assignment PIN_F2 -to HEX0[4]\nset_location_assignment PIN_F1 -to HEX0[5]\nset_location_assignment PIN_E2 -to HEX0[6]\nset_location_assignment PIN_E1 -to HEX1[0]\nset_location_assignment PIN_H6 -to HEX1[1]\nset_location_assignment PIN_H5 -to HEX1[2]\nset_location_assignment PIN_H4 -to HEX1[3]\nset_location_assignment PIN_G3 -to HEX1[4]\nset_location_assignment PIN_D2 -to HEX1[5]\nset_location_assignment PIN_D1 -to HEX1[6]\nset_location_assignment PIN_G5 -to HEX2[0]\nset_location_assignment PIN_G6 -to HEX2[1]\nset_location_assignment PIN_C2 -to HEX2[2]\nset_location_assignment PIN_C1 -to HEX2[3]\nset_location_assignment PIN_E3 -to HEX2[4]\nset_location_assignment PIN_E4 -to HEX2[5]\nset_location_assignment PIN_D3 -to HEX2[6]\nset_location_assignment PIN_F4 -to HEX3[0]\nset_location_assignment PIN_D5 -to HEX3[1]\nset_location_assignment PIN_D6 -to HEX3[2]\nset_location_assignment PIN_J4 -to HEX3[3]\nset_location_assignment PIN_L8 -to HEX3[4]\nset_location_assignment PIN_F3 -to HEX3[5]\nset_location_assignment PIN_D4 -to HEX3[6]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX0[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX0[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX0[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX0[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX0[4]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX0[5]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX0[6]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX1[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX1[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX1[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX1[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX1[4]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX1[5]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX1[6]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX2[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX2[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX2[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX2[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX2[4]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX2[5]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX2[6]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX3[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX3[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX3[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX3[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX3[4]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX3[5]\nset_instance_assignment -name IO_STANDARD LVTTL -to HEX3[6]\n\n###########################################################################\n# VGA\n###########################################################################\nset_location_assignment PIN_D9 -to VGA_R[0]\nset_location_assignment PIN_C9 -to VGA_R[1]\nset_location_assignment PIN_A7 -to VGA_R[2]\nset_location_assignment PIN_B7 -to VGA_R[3]\nset_location_assignment PIN_B8 -to VGA_G[0]\nset_location_assignment PIN_C10 -to VGA_G[1]\nset_location_assignment PIN_B9 -to VGA_G[2]\nset_location_assignment PIN_A8 -to VGA_G[3]\nset_location_assignment PIN_A9 -to VGA_B[0]\nset_location_assignment PIN_D11 -to VGA_B[1]\nset_location_assignment PIN_A10 -to VGA_B[2]\nset_location_assignment PIN_B10 -to VGA_B[3]\nset_location_assignment PIN_A11 -to VGA_HS\nset_location_assignment PIN_B11 -to VGA_VS\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_HS\nset_instance_assignment -name IO_STANDARD LVTTL -to VGA_VS\n\n###########################################################################\n# Audio Codec\n###########################################################################\nset_location_assignment PIN_A3 -to I2C_SCLK\nset_location_assignment PIN_B3 -to I2C_SDAT\nset_location_assignment PIN_A6 -to AUD_ADCLRCK\nset_location_assignment PIN_B6 -to AUD_ADCDAT\nset_location_assignment PIN_A5 -to AUD_DACLRCK\nset_location_assignment PIN_B5 -to AUD_DACDAT\nset_location_assignment PIN_B4 -to AUD_XCK\nset_location_assignment PIN_A4 -to AUD_BCLK\nset_instance_assignment -name IO_STANDARD LVTTL -to I2C_SCLK\nset_instance_assignment -name IO_STANDARD LVTTL -to I2C_SDAT\nset_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCLRCK\nset_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCDAT\nset_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACLRCK\nset_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACDAT\nset_instance_assignment -name IO_STANDARD LVTTL -to AUD_XCK\nset_instance_assignment -name IO_STANDARD LVTTL -to AUD_BCLK\n\n###########################################################################\n# Serial (UART)\n###########################################################################\nset_location_assignment PIN_F14 -to UART_RXD\nset_location_assignment PIN_G12 -to UART_TXD\nset_instance_assignment -name IO_STANDARD LVTTL -to UART_RXD\nset_instance_assignment -name IO_STANDARD LVTTL -to UART_TXD\n\n###########################################################################\n# PS/2\n###########################################################################\nset_location_assignment PIN_H15 -to PS2_CLK\nset_location_assignment PIN_J14 -to PS2_DAT\nset_instance_assignment -name IO_STANDARD LVTTL -to PS2_CLK\nset_instance_assignment -name IO_STANDARD LVTTL -to PS2_DAT\n\n###########################################################################\n# SD Card\n###########################################################################\nset_location_assignment PIN_E8 -to TDI\nset_location_assignment PIN_D8 -to TCS\nset_location_assignment PIN_C7 -to TCK\nset_location_assignment PIN_D7 -to TDO\nset_instance_assignment -name IO_STANDARD LVTTL -to TDI\nset_instance_assignment -name IO_STANDARD LVTTL -to TCS\nset_instance_assignment -name IO_STANDARD LVTTL -to TCK\nset_instance_assignment -name IO_STANDARD LVTTL -to TDO\n\n###########################################################################\n# SDRAM\n###########################################################################\nset_location_assignment PIN_W4 -to DRAM_ADDR[0]\nset_location_assignment PIN_W5 -to DRAM_ADDR[1]\nset_location_assignment PIN_Y3 -to DRAM_ADDR[2]\nset_location_assignment PIN_Y4 -to DRAM_ADDR[3]\nset_location_assignment PIN_R6 -to DRAM_ADDR[4]\nset_location_assignment PIN_R5 -to DRAM_ADDR[5]\nset_location_assignment PIN_P6 -to DRAM_ADDR[6]\nset_location_assignment PIN_P5 -to DRAM_ADDR[7]\nset_location_assignment PIN_P3 -to DRAM_ADDR[8]\nset_location_assignment PIN_N4 -to DRAM_ADDR[9]\nset_location_assignment PIN_W3 -to DRAM_ADDR[10]\nset_location_assignment PIN_N6 -to DRAM_ADDR[11]\nset_location_assignment PIN_U1 -to DRAM_DQ[0]\nset_location_assignment PIN_U2 -to DRAM_DQ[1]\nset_location_assignment PIN_V1 -to DRAM_DQ[2]\nset_location_assignment PIN_V2 -to DRAM_DQ[3]\nset_location_assignment PIN_W1 -to DRAM_DQ[4]\nset_location_assignment PIN_W2 -to DRAM_DQ[5]\nset_location_assignment PIN_Y1 -to DRAM_DQ[6]\nset_location_assignment PIN_Y2 -to DRAM_DQ[7]\nset_location_assignment PIN_N1 -to DRAM_DQ[8]\nset_location_assignment PIN_N2 -to DRAM_DQ[9]\nset_location_assignment PIN_P1 -to DRAM_DQ[10]\nset_location_assignment PIN_P2 -to DRAM_DQ[11]\nset_location_assignment PIN_R1 -to DRAM_DQ[12]\nset_location_assignment PIN_R2 -to DRAM_DQ[13]\nset_location_assignment PIN_T1 -to DRAM_DQ[14]\nset_location_assignment PIN_T2 -to DRAM_DQ[15]\nset_location_assignment PIN_U3 -to DRAM_BA_0\nset_location_assignment PIN_V4 -to DRAM_BA_1\nset_location_assignment PIN_R7 -to DRAM_LDQM\nset_location_assignment PIN_M5 -to DRAM_UDQM\nset_location_assignment PIN_T5 -to DRAM_RAS_N\nset_location_assignment PIN_T3 -to DRAM_CAS_N\nset_location_assignment PIN_N3 -to DRAM_CKE\nset_location_assignment PIN_U4 -to DRAM_CLK\nset_location_assignment PIN_R8 -to DRAM_WE_N\nset_location_assignment PIN_T6 -to DRAM_CS_N\n\n###########################################################################\n# SRAM\n###########################################################################\nset_location_assignment PIN_AA3 -to SRAM_ADDR[0]\nset_location_assignment PIN_AB3 -to SRAM_ADDR[1]\nset_location_assignment PIN_AA4 -to SRAM_ADDR[2]\nset_location_assignment PIN_AB4 -to SRAM_ADDR[3]\nset_location_assignment PIN_AA5 -to SRAM_ADDR[4]\nset_location_assignment PIN_AB10 -to SRAM_ADDR[5]\nset_location_assignment PIN_AA11 -to SRAM_ADDR[6]\nset_location_assignment PIN_AB11 -to SRAM_ADDR[7]\nset_location_assignment PIN_V11 -to SRAM_ADDR[8]\nset_location_assignment PIN_W11 -to SRAM_ADDR[9]\nset_location_assignment PIN_R11 -to SRAM_ADDR[10]\nset_location_assignment PIN_T11 -to SRAM_ADDR[11]\nset_location_assignment PIN_Y10 -to SRAM_ADDR[12]\nset_location_assignment PIN_U10 -to SRAM_ADDR[13]\nset_location_assignment PIN_R10 -to SRAM_ADDR[14]\nset_location_assignment PIN_T7 -to SRAM_ADDR[15]\nset_location_assignment PIN_Y6 -to SRAM_ADDR[16]\nset_location_assignment PIN_Y5 -to SRAM_ADDR[17]\nset_location_assignment PIN_AA6 -to SRAM_DQ[0]\nset_location_assignment PIN_AB6 -to SRAM_DQ[1]\nset_location_assignment PIN_AA7 -to SRAM_DQ[2]\nset_location_assignment PIN_AB7 -to SRAM_DQ[3]\nset_location_assignment PIN_AA8 -to SRAM_DQ[4]\nset_location_assignment PIN_AB8 -to SRAM_DQ[5]\nset_location_assignment PIN_AA9 -to SRAM_DQ[6]\nset_location_assignment PIN_AB9 -to SRAM_DQ[7]\nset_location_assignment PIN_Y9 -to SRAM_DQ[8]\nset_location_assignment PIN_W9 -to SRAM_DQ[9]\nset_location_assignment PIN_V9 -to SRAM_DQ[10]\nset_location_assignment PIN_U9 -to SRAM_DQ[11]\nset_location_assignment PIN_R9 -to SRAM_DQ[12]\nset_location_assignment PIN_W8 -to SRAM_DQ[13]\nset_location_assignment PIN_V8 -to SRAM_DQ[14]\nset_location_assignment PIN_U8 -to SRAM_DQ[15]\nset_location_assignment PIN_AB5 -to SRAM_CE_N\nset_location_assignment PIN_T8 -to SRAM_OE_N\nset_location_assignment PIN_AA10 -to SRAM_WE_N\nset_location_assignment PIN_W7 -to SRAM_UB_N\nset_location_assignment PIN_Y7 -to SRAM_LB_N\n\n###########################################################################\n# FLASH\n###########################################################################\nset_location_assignment PIN_AB20 -to FL_ADDR[0]\nset_location_assignment PIN_AA14 -to FL_ADDR[1]\nset_location_assignment PIN_Y16 -to FL_ADDR[2]\nset_location_assignment PIN_R15 -to FL_ADDR[3]\nset_location_assignment PIN_T15 -to FL_ADDR[4]\nset_location_assignment PIN_U15 -to FL_ADDR[5]\nset_location_assignment PIN_V15 -to FL_ADDR[6]\nset_location_assignment PIN_W15 -to FL_ADDR[7]\nset_location_assignment PIN_R14 -to FL_ADDR[8]\nset_location_assignment PIN_Y13 -to FL_ADDR[9]\nset_location_assignment PIN_R12 -to FL_ADDR[10]\nset_location_assignment PIN_T12 -to FL_ADDR[11]\nset_location_assignment PIN_AB14 -to FL_ADDR[12]\nset_location_assignment PIN_AA13 -to FL_ADDR[13]\nset_location_assignment PIN_AB13 -to FL_ADDR[14]\nset_location_assignment PIN_AA12 -to FL_ADDR[15]\nset_location_assignment PIN_AB12 -to FL_ADDR[16]\nset_location_assignment PIN_AA20 -to FL_ADDR[17]\nset_location_assignment PIN_U14 -to FL_ADDR[18]\nset_location_assignment PIN_V14 -to FL_ADDR[19]\nset_location_assignment PIN_U13 -to FL_ADDR[20]\nset_location_assignment PIN_R13 -to FL_ADDR[21]\nset_location_assignment PIN_AB16 -to FL_DQ[0]\nset_location_assignment PIN_AA16 -to FL_DQ[1]\nset_location_assignment PIN_AB17 -to FL_DQ[2]\nset_location_assignment PIN_AA17 -to FL_DQ[3]\nset_location_assignment PIN_AB18 -to FL_DQ[4]\nset_location_assignment PIN_AA18 -to FL_DQ[5]\nset_location_assignment PIN_AB19 -to FL_DQ[6]\nset_location_assignment PIN_AA19 -to FL_DQ[7]\nset_location_assignment PIN_AB15 -to FL_CE_N\nset_location_assignment PIN_AA15 -to FL_OE_N\nset_location_assignment PIN_Y14 -to FL_WE_N\nset_location_assignment PIN_W14 -to FL_RST_N\n\n###########################################################################\n# GPIO-0 Expansion Header 1\n###########################################################################\nset_location_assignment PIN_A13 -to kempston_gnd\nset_location_assignment PIN_B13 -to GPIO_0[1]\nset_location_assignment PIN_A14 -to kempston[4]\nset_location_assignment PIN_B14 -to GPIO_0[3]\nset_location_assignment PIN_A15 -to kempston[3]\nset_location_assignment PIN_B15 -to kempston[2]\nset_location_assignment PIN_A16 -to kempston[1]\nset_location_assignment PIN_B16 -to kempston[0]\nset_location_assignment PIN_B17 -to GPIO_0[9]\nset_location_assignment PIN_A18 -to GPIO_0[10]\nset_location_assignment PIN_B18 -to GPIO_0[11]\nset_location_assignment PIN_A19 -to GPIO_0[12]\nset_location_assignment PIN_B19 -to GPIO_0[13]\nset_location_assignment PIN_A20 -to GPIO_0[14]\nset_location_assignment PIN_B20 -to GPIO_0[15]\nset_location_assignment PIN_C21 -to GPIO_0[16]\nset_location_assignment PIN_C22 -to GPIO_0[17]\nset_location_assignment PIN_D21 -to GPIO_0[18]\nset_location_assignment PIN_D22 -to GPIO_0[19]\nset_location_assignment PIN_E21 -to GPIO_0[20]\nset_location_assignment PIN_E22 -to GPIO_0[21]\nset_location_assignment PIN_F21 -to GPIO_0[22]\nset_location_assignment PIN_F22 -to GPIO_0[23]\nset_location_assignment PIN_G21 -to GPIO_0[24]\nset_location_assignment PIN_G22 -to GPIO_0[25]\nset_location_assignment PIN_J21 -to GPIO_0[26]\nset_location_assignment PIN_J22 -to GPIO_0[27]\nset_location_assignment PIN_K21 -to GPIO_0[28]\nset_location_assignment PIN_K22 -to GPIO_0[29]\nset_location_assignment PIN_J19 -to GPIO_0[30]\nset_location_assignment PIN_J20 -to GPIO_0[31]\nset_instance_assignment -name IO_STANDARD LVTTL -to kempston_gnd\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[1]\nset_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to kempston[4]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[3]\nset_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to kempston[3]\nset_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to kempston[2]\nset_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to kempston[1]\nset_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to kempston[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[8]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[9]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[10]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[11]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[12]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[13]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[14]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[15]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[16]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[17]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[18]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[19]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[20]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[21]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[22]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[23]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[24]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[25]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[26]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[27]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[28]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[29]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[30]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[31]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[32]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[33]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[34]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[35]\n\n###########################################################################\n# GPIO-1 Expansion Header 2\n###########################################################################\nset_location_assignment PIN_H12 -to GPIO_1[0]\nset_location_assignment PIN_H13 -to GPIO_1[1]\nset_location_assignment PIN_H14 -to GPIO_1[2]\nset_location_assignment PIN_G15 -to GPIO_1[3]\nset_location_assignment PIN_E14 -to GPIO_1[4]\nset_location_assignment PIN_E15 -to GPIO_1[5]\nset_location_assignment PIN_F15 -to GPIO_1[6]\nset_location_assignment PIN_G16 -to GPIO_1[7]\nset_location_assignment PIN_F12 -to GPIO_1[8]\nset_location_assignment PIN_F13 -to GPIO_1[9]\nset_location_assignment PIN_C14 -to GPIO_1[10]\nset_location_assignment PIN_D14 -to GPIO_1[11]\nset_location_assignment PIN_D15 -to GPIO_1[12]\nset_location_assignment PIN_D16 -to GPIO_1[13]\nset_location_assignment PIN_C17 -to GPIO_1[14]\nset_location_assignment PIN_C18 -to GPIO_1[15]\nset_location_assignment PIN_C19 -to GPIO_1[16]\nset_location_assignment PIN_C20 -to GPIO_1[17]\nset_location_assignment PIN_D19 -to GPIO_1[18]\nset_location_assignment PIN_D20 -to GPIO_1[19]\nset_location_assignment PIN_E20 -to GPIO_1[20]\nset_location_assignment PIN_F20 -to GPIO_1[21]\nset_location_assignment PIN_E19 -to GPIO_1[22]\nset_location_assignment PIN_E18 -to GPIO_1[23]\nset_location_assignment PIN_G20 -to GPIO_1[24]\nset_location_assignment PIN_G18 -to GPIO_1[25]\nset_location_assignment PIN_G17 -to GPIO_1[26]\nset_location_assignment PIN_H17 -to GPIO_1[27]\nset_location_assignment PIN_J15 -to GPIO_1[28]\nset_location_assignment PIN_H18 -to GPIO_1[29]\nset_location_assignment PIN_N22 -to GPIO_1[30]\nset_location_assignment PIN_N21 -to GPIO_1[31]\nset_location_assignment PIN_P15 -to GPIO_1[32]\nset_location_assignment PIN_N15 -to GPIO_1[33]\nset_location_assignment PIN_P17 -to GPIO_1[34]\nset_location_assignment PIN_P18 -to GPIO_1[35]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[0]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[1]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[2]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[3]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[4]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[5]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[6]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[7]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[8]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[9]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[10]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[11]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[12]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[13]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[14]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[15]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[16]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[17]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[18]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[19]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[20]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[21]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[22]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[23]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[24]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[25]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[26]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[27]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[28]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[29]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[30]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[31]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[32]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[33]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[34]\nset_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[35]\n\n#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n# These are some common settings that all DE1 boards might want to have\n# without having to be manually set each time\n#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n\nset_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files\nset_global_assignment -name MIN_CORE_JUNCTION_TEMP 0\nset_global_assignment -name MAX_CORE_JUNCTION_TEMP 85\nset_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1\nset_global_assignment -name USE_CONFIGURATION_DEVICE ON\nset_global_assignment -name RESERVE_ALL_UNUSED_PINS \"AS INPUT TRI-STATED WITH WEAK PULL-UP\"\nset_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON\nset_global_assignment -name SMART_RECOMPILE ON\nset_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON\nset_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4\nset_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS \"NORMAL COMPILATION\"\nset_global_assignment -name OPTIMIZE_POWER_DURING_FITTING \"NORMAL COMPILATION\"\nset_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005\nset_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF\nset_global_assignment -name POWER_PRESET_COOLING_SOLUTION \"23 MM HEAT SINK WITH 200 LFPM AIRFLOW\"\nset_global_assignment -name POWER_BOARD_THERMAL_MODEL \"NONE (CONSERVATIVE)\"\nset_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON\nset_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON\n\n#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n# Quartus managed\n#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n\nset_global_assignment -name FAMILY \"Cyclone II\"\nset_global_assignment -name DEVICE EP2C20F484C7\nset_global_assignment -name TOP_LEVEL_ENTITY zxspectrum_board\nset_global_assignment -name ORIGINAL_QUARTUS_VERSION \"13.0 SP1\"\nset_global_assignment -name PROJECT_CREATION_TIME_DATE \"23:30:28  OCTOBER 14, 2014\"\nset_global_assignment -name LAST_QUARTUS_VERSION \"13.0 SP1\"\nset_global_assignment -name FITTER_EFFORT \"AUTO FIT\"\nset_global_assignment -name STRATIX_DEVICE_IO_STANDARD \"3.3-V LVTTL\"\n\nset_global_assignment -name OPTIMIZE_HOLD_TIMING \"IO PATHS AND MINIMUM TPD PATHS\"\nset_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top\nset_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top\nset_global_assignment -name PARTITION_COLOR 16764057 -section_id Top\nset_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED\nset_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF\nset_global_assignment -name NUM_PARALLEL_PROCESSORS ALL\nset_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE OPTIMISTIC\nset_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF\nset_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON\nset_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF\nset_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON\nset_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF\nset_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF\nset_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL\nset_global_assignment -name VERILOG_FILE ../../cpu/bus/bus_switch.v\nset_global_assignment -name VERILOG_FILE ../../cpu/control/execute.v\nset_global_assignment -name VERILOG_FILE ../../cpu/control/pla_decode.v\nset_global_assignment -name VERILOG_FILE ../../cpu/toplevel/z80_top_direct_n.v\nset_global_assignment -name VERILOG_FILE ../../cpu/alu/alu.v\nset_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_bit_select.v\nset_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_control.v\nset_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_core.v\nset_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_flags.v\nset_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_mux_2.v\nset_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_mux_2z.v\nset_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_mux_3z.v\nset_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_mux_4.v\nset_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_mux_8.v\nset_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_prep_daa.v\nset_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_select.v\nset_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_shifter_core.v\nset_global_assignment -name VERILOG_FILE ../../cpu/alu/alu_slice.v\nset_global_assignment -name VERILOG_FILE ../../cpu/bus/address_latch.v\nset_global_assignment -name VERILOG_FILE ../../cpu/bus/address_mux.v\nset_global_assignment -name VERILOG_FILE ../../cpu/bus/address_pins.v\nset_global_assignment -name VERILOG_FILE ../../cpu/bus/bus_control.v\nset_global_assignment -name VERILOG_FILE ../../cpu/bus/control_pins_n.v\nset_global_assignment -name VERILOG_FILE ../../cpu/bus/data_pins.v\nset_global_assignment -name VERILOG_FILE ../../cpu/bus/data_switch.v\nset_global_assignment -name VERILOG_FILE ../../cpu/bus/data_switch_mask.v\nset_global_assignment -name VERILOG_FILE ../../cpu/bus/inc_dec.v\nset_global_assignment -name VERILOG_FILE ../../cpu/bus/inc_dec_2bit.v\nset_global_assignment -name VERILOG_FILE ../../cpu/control/clk_delay.v\nset_global_assignment -name VERILOG_FILE ../../cpu/control/decode_state.v\nset_global_assignment -name VERILOG_FILE ../../cpu/control/interrupts.v\nset_global_assignment -name VERILOG_FILE ../../cpu/control/ir.v\nset_global_assignment -name VERILOG_FILE ../../cpu/control/memory_ifc.v\nset_global_assignment -name VERILOG_FILE ../../cpu/control/pin_control.v\nset_global_assignment -name VERILOG_FILE ../../cpu/control/resets.v\nset_global_assignment -name VERILOG_FILE ../../cpu/control/sequencer.v\nset_global_assignment -name VERILOG_FILE ../../cpu/registers/reg_control.v\nset_global_assignment -name VERILOG_FILE ../../cpu/registers/reg_file.v\nset_global_assignment -name VERILOG_FILE ../../cpu/registers/reg_latch.v\nset_global_assignment -name SYSTEMVERILOG_FILE ula/zx_kbd.sv\nset_global_assignment -name SYSTEMVERILOG_FILE ula/video.sv\nset_global_assignment -name SYSTEMVERILOG_FILE ula/ula.sv\nset_global_assignment -name SYSTEMVERILOG_FILE ula/ps2_kbd.sv\nset_global_assignment -name VHDL_FILE ula/i2s_intf.vhd\nset_global_assignment -name VHDL_FILE ula/i2c_loader.vhd\nset_global_assignment -name SYSTEMVERILOG_FILE ula/clocks.sv\nset_global_assignment -name SYSTEMVERILOG_FILE zxspectrum_de1.sv\nset_global_assignment -name QIP_FILE pll.qip\nset_global_assignment -name QIP_FILE ram16.qip\nset_global_assignment -name SDC_FILE zxspectrum_de1.sdc\nset_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top"
  },
  {
    "path": "host/zxspectrum_de1/zxspectrum_de1.sdc",
    "content": "#**************************************************************\n## VENDOR  \"Altera\"\n## PROGRAM \"Quartus II\"\n## VERSION \"Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition\"\n##\n## DEVICE  \"EP2C20F484C7\"\n##\n#**************************************************************\n# Time Information\n#**************************************************************\n\nset_time_format -unit ns -decimal_places 3\n\n#**************************************************************\n# Create Clock\n#**************************************************************\n\ncreate_clock -name \"CLOCK_27\" -period 27MHz [get_ports {CLOCK_27}]\ncreate_clock -name \"CLOCK_24\" -period 24MHz [get_ports {CLOCK_24}]\ncreate_clock -name KEY1 -period 10.000 [get_ports {KEY1}]\ncreate_clock -name beep -period 10.000 [get_registers {ula:ula_|beep}]\n\nderive_pll_clocks -create_base_clocks\n\n#**************************************************************\n# Create Generated Clock\n#**************************************************************\n\ncreate_generated_clock -name clk_cpu -source [get_pins {ula_|clocks_|clk_cpu|clk}] -divide_by 4 [get_pins {ula_|clocks_|clk_cpu|regout}]\n\n#**************************************************************\n# Set Clock Latency\n#**************************************************************\n\n\n#**************************************************************\n# Set Clock Uncertainty\n#**************************************************************\n\nderive_clock_uncertainty\n\n#**************************************************************\n# Set Input Delay\n#**************************************************************\n\nset_input_delay -clock CLOCK_27 -max 2 [all_inputs]\nset_input_delay -clock CLOCK_27 -min 1 [all_inputs]\n\nset_input_delay -add_delay -max -clock [get_clocks {CLOCK_24}]  2.000 [get_ports {CLOCK_24}]\nset_input_delay -add_delay -min -clock [get_clocks {CLOCK_24}]  1.000 [get_ports {CLOCK_24}]\n\nset_input_delay -add_delay -max -clock [get_clocks {CLOCK_27}]  2.000 [get_ports {CLOCK_27}]\nset_input_delay -add_delay -min -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {CLOCK_27}]\n\n#**************************************************************\n# Set Output Delay\n#**************************************************************\n\nset_output_delay -clock CLOCK_24 10 [all_outputs]\n\n#**************************************************************\n# Set Clock Groups\n#**************************************************************\n\nset_clock_groups -asynchronous \\\n -group [get_clocks {CLOCK_24}] \\\n -group [get_clocks {CLOCK_27}] \\\n -group [get_clocks {clk_cpu}] \\\n -group [get_clocks {KEY1}] \\\n -group [get_clocks {beep}] \\\n -group ula_|pll_|altpll_component|pll|clk[0] \\\n -group ula_|pll_|altpll_component|pll|clk[1]\n\n#**************************************************************\n# Set False Path\n#**************************************************************\n\n\n#**************************************************************\n# Set Multicycle Path\n#**************************************************************\n\n\n#**************************************************************\n# Set Maximum Delay\n#**************************************************************\n\n\n#**************************************************************\n# Set Minimum Delay\n#**************************************************************\n\n\n#**************************************************************\n# Set Input Transition\n#**************************************************************\n\n"
  },
  {
    "path": "host/zxspectrum_de1/zxspectrum_de1.sv",
    "content": "//============================================================================\n// Sinclair ZX Spectrum host board\n//\n//  Copyright (C) 2014-2016  Goran Devic\n//\n//  This program is free software; you can redistribute it and/or modify it\n//  under the terms of the GNU General Public License as published by the Free\n//  Software Foundation; either version 2 of the License, or (at your option)\n//  any later version.\n//\n//  This program is distributed in the hope that it will be useful, but WITHOUT\n//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n//  more details.\n//\n//  You should have received a copy of the GNU General Public License along\n//  with this program; if not, write to the Free Software Foundation, Inc.,\n//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n//============================================================================\nmodule zxspectrum_board\n(\n    //-------- Clocks and reset -----------------\n    input wire CLOCK_27,            // Input clock 27 MHz\n    input wire CLOCK_24,            // Input clock 24 MHz\n    input wire KEY0,                // RESET button; on DE1, keys are active low!\n    input wire KEY1,                // NMI button\n\n    //-------- PS/2 Keyboard --------------------\n    input wire PS2_CLK,\n    input wire PS2_DAT,\n\n    //-------- Audio (Tape player) --------------\n    inout wire I2C_SCLK,\n    inout wire I2C_SDAT,\n    output wire AUD_XCK,\n    output wire AUD_ADCLRCK,\n    output wire AUD_DACLRCK,\n    output wire AUD_BCLK,\n    output wire AUD_DACDAT,\n    input wire AUD_ADCDAT,\n\n    //-------- VGA connector --------------------\n    output wire [3:0] VGA_R,\n    output wire [3:0] VGA_G,\n    output wire [3:0] VGA_B,\n    output reg VGA_HS,\n    output reg VGA_VS,\n\n    //-------- Flash memory interface -----------\n    output wire [21:0] FL_ADDR,\n    input wire [7:0] FL_DQ,\n    output wire FL_CE_N,\n    output wire FL_OE_N,\n    output wire FL_WE_N,\n    output wire FL_RST_N,\n\n    //-------- SRAM memory interface ------------\n    output wire [17:0] SRAM_ADDR,\n    inout reg [15:0] SRAM_DQ,\n    output wire SRAM_CE_N,\n    output wire SRAM_OE_N,\n    output wire SRAM_WE_N,\n    output wire SRAM_UB_N,\n    output wire SRAM_LB_N,\n\n    //-------- Atari joystick mapped as Kempston\n    input wire [4:0] kempston,      // Input with weak pull-up\n    output wire kempston_gnd,       // Helps mapping to DB9 cable\n    output wire [4:0] LEDG,         // Show the joystick state\n\n    //-------- Misc and debug -------------------\n    input wire SW0,                 // ROM selection\n    input wire SW1,                 // Enable/disable interrupts\n    input wire SW2,                 // Turbo speed (3.5 MHz x 2 = 7.0 MHz)\n    output wire [2:0] LEDR,         // Shows the switch selection\n    output wire [31:0] GPIO_1,      // Exports CPU chip pins\n    output wire [2:0] LEDGTOP       // Show additional information visually\n);\n`default_nettype none\n\nwire reset;\nwire locked;\nassign reset = locked & KEY0;\n\n// Export selected pins to the extension connector\nassign GPIO_1[15:0] = A[15:0];\nassign GPIO_1[23:16] = D[7:0];\nassign GPIO_1[31:24] = {nM1,nMREQ,nIORQ,nRD,nWR,nRFSH,nHALT,nBUSACK};\nassign kempston_gnd = 0;\n\n// Top 3 green LEDs show various states:\nassign LEDGTOP[2] = 0;              // Reserved for future use\nassign LEDGTOP[1] = beeper;         // Show the beeper state\nassign LEDGTOP[0] = pressed;        // Show when a key is being pressed\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// Internal buses and address map selection logic\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nwire [15:0] A;                  // Global address bus\nwire [7:0] D;                   // CPU data bus\n\nwire [7:0] ram_data;            // Internal 16K RAM data\nwire RamWE;\nassign RamWE = A[15:14]==2'b01 && nIORQ==1 && nRD==1 && nWR==0;\n\nwire ExtRamWE;                  // Extended (and external) 32K RAM\nassign ExtRamWE = A[15]==1 && nIORQ==1 && nRD==1 && nWR==0;\nassign SRAM_DQ[15:0] = ExtRamWE? {8'b0,D[7:0]} : {16{1'bz}};\n\nwire [7:0] ula_data;            // ULA\nwire io_we;\nassign io_we = nIORQ==0 && nRD==1 && nWR==0;\n\n// Memory map:\n//   0000 - 3FFF  16K ROM (mapped to the external Flash memory)\n//   4000 - 7FFF  16K dual-port RAM\n//   8000 - FFFF  32K RAM (mapped to the external SRAM memory)\nalways @(*) // always_comb\nbegin\n    case ({nIORQ,nRD,nWR})\n        // -------------------------------- Memory read --------------------------------\n        3'b101: begin\n                casez (A[15:14])\n                    2'b00:  D[7:0] = FL_DQ;\n                    2'b01:  D[7:0] = ram_data;\n                    2'b1?:  D[7:0] = SRAM_DQ[7:0];\n                endcase\n            end\n        // ---------------------------------- IO read ----------------------------------\n        3'b001: begin\n                // Normally data supplied by the ULA\n                D[7:0] = ula_data;\n\n                // Kempston joystick at the IO address 0x1F; active bits are high:\n                //                   FIRE         UP           DOWN         LEFT         RIGHT\n                if (A[7:0]==8'h1F) begin\n                    D[7:0] = { 3'b0, !kempston[4],!kempston[0],!kempston[1],!kempston[2],!kempston[3] };\n                end\n            end\n    default:\n        D[7:0] = {8{1'bz}};\n    endcase\nend\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// 16K of the original ZX Spectrum ROM is in the flash at the address 0\n// 16K of The GOSH WONDERFUL ZX Spectrum ROM is in the flash following it\n//    http://www.wearmouth.demon.co.uk/gw03/gw03info.htm\n// SW0 selectes which ROM is going to be used by feeding the address bit 14\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nassign FL_ADDR[13:0] = A[13:0];\nassign FL_ADDR[14] = SW0;\nassign LEDR[0] = SW0;           // Glow red when using alternate ROM\nassign FL_ADDR[21:15] = 0;\nassign FL_RST_N = KEY0;\nassign FL_CE_N = 0;\nassign FL_OE_N = 0;\nassign FL_WE_N = 1;\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// Instantiate 16K dual-port RAM\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nwire clk_vram;\n// \"A\" port is the CPU side, \"B\" port is the VGA image generator in the ULA\nram16 ram16_(\n    .clock      (clk_vram),     // RAM connects to the higher, pixel clock rate\n\n    .address_a  (A[13:0]),      // Address in to the RAM from the CPU side\n    .data_a     (D),            // Data in to the RAM from the CPU side\n    .q_a        (ram_data),     // Data out from the RAM into the data bus selector\n    .wren_a     (RamWE),\n\n    .address_b  ({1'b0, vram_address}),\n    .data_b     (8'b0),\n    .q_b        (vram_data),\n    .wren_b     ('0));\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// 32K of ZX Spectrum extended RAM is using the external SRAM memory\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nassign SRAM_ADDR[14:0] = A[14:0];\nassign SRAM_ADDR[17:15] = 0;\nassign SRAM_CE_N = 0;\nassign SRAM_OE_N = 0;\nassign SRAM_WE_N = !ExtRamWE;\nassign SRAM_UB_N = 1;\nassign SRAM_LB_N = 0;\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// Instantiate ULA\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nwire clk_cpu;                   // Global CPU clock of 3.5 MHz\nassign LEDR[2] = SW2;           // Glow red when in turbo mode (7.0 MHz)\nwire [12:0] vram_address;       // ULA video block requests a byte from the video RAM\nwire [7:0] vram_data;           // ULA video block reads a byte from the video RAM\nwire vs_nintr;                  // Generates a vertical retrace interrupt\nwire pressed;                   // Show that a key is being pressed\nwire beeper;                    // Show the beeper state\n\nula ula_(\n    //-------- Clocks and reset -----------------\n    .CLOCK_27 (CLOCK_27),       // Input clock 27 MHz\n    .CLOCK_24 (CLOCK_24),       // Input clock 24 MHz\n    .turbo (SW2),               // Turbo speed (3.5 MHz x 2 = 7.0 MHz)\n    .clk_vram (clk_vram),\n    .nreset (reset),            // KEY0 is reset; on DE1, keys are active low!\n    .locked (locked),           // PLL is locked signal\n\n    //-------- CPU control ----------------------\n    .clk_cpu (clk_cpu),         // Generates CPU clock of 3.5 MHz\n    .vs_nintr (vs_nintr),       // Generates a vertical retrace interrupt\n\n    //-------- Address and data buses -----------\n    .A (A),                     // Input address bus\n    .D (D),                     // Input data bus\n    .ula_data (ula_data),       // Output data\n    .io_we (io_we),             // Write enable to data register through IO\n\n    .vram_address (vram_address),// ULA video block requests a byte from the video RAM\n    .vram_data (vram_data),     // ULA video block reads a byte from the video RAM\n\n    //-------- PS/2 Keyboard --------------------\n    .PS2_CLK (PS2_CLK),\n    .PS2_DAT (PS2_DAT),\n    .pressed (pressed),\n\n    //-------- Audio (Tape player) --------------\n    .I2C_SCLK (I2C_SCLK),\n    .I2C_SDAT (I2C_SDAT),\n    .AUD_XCK (AUD_XCK),\n    .AUD_ADCLRCK (AUD_ADCLRCK),\n    .AUD_DACLRCK (AUD_DACLRCK),\n    .AUD_BCLK (AUD_BCLK),\n    .AUD_DACDAT (AUD_DACDAT),\n    .AUD_ADCDAT (AUD_ADCDAT),\n    .beeper (beeper),\n\n    //-------- VGA connector --------------------\n    .VGA_R (VGA_R),\n    .VGA_G (VGA_G),\n    .VGA_B (VGA_B),\n    .VGA_HS (VGA_HS),\n    .VGA_VS (VGA_VS)\n);\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// Instantiate A-Z80 CPU\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nwire nM1;\nwire nMREQ;\nwire nIORQ;\nwire nRD;\nwire nWR;\nwire nRFSH;\nwire nHALT;\nwire nBUSACK;\n\nwire nWAIT = 1;\nwire nINT = (SW1==0)? vs_nintr : '1;// SW1 disables interrupts and, hence, keyboard\nassign LEDR[1] = SW1;               // Glow red when interrupts are *disabled*\nwire nNMI = KEY1;                   // Pressing KEY1 issues a NMI\nwire nBUSRQ = 1;\n\nz80_top_direct_n z80_(\n    .nM1 (nM1),\n    .nMREQ (nMREQ),\n    .nIORQ (nIORQ),\n    .nRD (nRD),\n    .nWR (nWR),\n    .nRFSH (nRFSH),\n    .nHALT (nHALT),\n    .nBUSACK (nBUSACK),\n\n    .nWAIT (nWAIT),\n    .nINT (nINT),\n    .nNMI (nNMI),\n    .nRESET (reset),\n    .nBUSRQ (nBUSRQ),\n\n    .CLK (clk_cpu),\n    .A (A),\n    .D (D)\n);\n\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n// Lit green LEDs to show activity on a Kempston compatible joystick\n//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nassign LEDG[0] = !kempston[0]; // UP\nassign LEDG[1] = !kempston[1]; // DOWN\nassign LEDG[2] = !kempston[2]; // LEFT\nassign LEDG[3] = !kempston[3]; // RIGHT\nassign LEDG[4] = !kempston[4]; // FIRE\n\nendmodule\n"
  },
  {
    "path": "license.txt",
    "content": "                    GNU GENERAL PUBLIC LICENSE\n                       Version 2, June 1991\n\n Copyright (C) 1989, 1991 Free Software Foundation, Inc., <http://fsf.org/>\n 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA\n Everyone is permitted to copy and distribute verbatim copies\n of this license document, but changing it is not allowed.\n\n                            Preamble\n\n  The licenses for most software are designed to take away your\nfreedom to share and change it.  By contrast, the GNU General Public\nLicense is intended to guarantee your freedom to share and change free\nsoftware--to make sure the software is free for all its users.  This\nGeneral Public License applies to most of the Free Software\nFoundation's software and to any other program whose authors commit to\nusing it.  (Some other Free Software Foundation software is covered by\nthe GNU Lesser General Public License instead.)  You can apply it to\nyour programs, too.\n\n  When we speak of free software, we are referring to freedom, not\nprice.  Our General Public Licenses are designed to make sure that you\nhave the freedom to distribute copies of free software (and charge for\nthis service if you wish), that you receive source code or can get it\nif you want it, that you can change the software or use pieces of it\nin new free programs; and that you know you can do these things.\n\n  To protect your rights, we need to make restrictions that forbid\nanyone to deny you these rights or to ask you to surrender the rights.\nThese restrictions translate to certain responsibilities for you if you\ndistribute copies of the software, or if you modify it.\n\n  For example, if you distribute copies of such a program, whether\ngratis or for a fee, you must give the recipients all the rights that\nyou have.  You must make sure that they, too, receive or can get the\nsource code.  And you must show them these terms so they know their\nrights.\n\n  We protect your rights with two steps: (1) copyright the software, and\n(2) offer you this license which gives you legal permission to copy,\ndistribute and/or modify the software.\n\n  Also, for each author's protection and ours, we want to make certain\nthat everyone understands that there is no warranty for this free\nsoftware.  If the software is modified by someone else and passed on, we\nwant its recipients to know that what they have is not the original, so\nthat any problems introduced by others will not reflect on the original\nauthors' reputations.\n\n  Finally, any free program is threatened constantly by software\npatents.  We wish to avoid the danger that redistributors of a free\nprogram will individually obtain patent licenses, in effect making the\nprogram proprietary.  To prevent this, we have made it clear that any\npatent must be licensed for everyone's free use or not licensed at all.\n\n  The precise terms and conditions for copying, distribution and\nmodification follow.\n\n                    GNU GENERAL PUBLIC LICENSE\n   TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION\n\n  0. This License applies to any program or other work which contains\na notice placed by the copyright holder saying it may be distributed\nunder the terms of this General Public License.  The \"Program\", below,\nrefers to any such program or work, and a \"work based on the Program\"\nmeans either the Program or any derivative work under copyright law:\nthat is to say, a work containing the Program or a portion of it,\neither verbatim or with modifications and/or translated into another\nlanguage.  (Hereinafter, translation is included without limitation in\nthe term \"modification\".)  Each licensee is addressed as \"you\".\n\nActivities other than copying, distribution and modification are not\ncovered by this License; they are outside its scope.  The act of\nrunning the Program is not restricted, and the output from the Program\nis covered only if its contents constitute a work based on the\nProgram (independent of having been made by running the Program).\nWhether that is true depends on what the Program does.\n\n  1. You may copy and distribute verbatim copies of the Program's\nsource code as you receive it, in any medium, provided that you\nconspicuously and appropriately publish on each copy an appropriate\ncopyright notice and disclaimer of warranty; keep intact all the\nnotices that refer to this License and to the absence of any warranty;\nand give any other recipients of the Program a copy of this License\nalong with the Program.\n\nYou may charge a fee for the physical act of transferring a copy, and\nyou may at your option offer warranty protection in exchange for a fee.\n\n  2. You may modify your copy or copies of the Program or any portion\nof it, thus forming a work based on the Program, and copy and\ndistribute such modifications or work under the terms of Section 1\nabove, provided that you also meet all of these conditions:\n\n    a) You must cause the modified files to carry prominent notices\n    stating that you changed the files and the date of any change.\n\n    b) You must cause any work that you distribute or publish, that in\n    whole or in part contains or is derived from the Program or any\n    part thereof, to be licensed as a whole at no charge to all third\n    parties under the terms of this License.\n\n    c) If the modified program normally reads commands interactively\n    when run, you must cause it, when started running for such\n    interactive use in the most ordinary way, to print or display an\n    announcement including an appropriate copyright notice and a\n    notice that there is no warranty (or else, saying that you provide\n    a warranty) and that users may redistribute the program under\n    these conditions, and telling the user how to view a copy of this\n    License.  (Exception: if the Program itself is interactive but\n    does not normally print such an announcement, your work based on\n    the Program is not required to print an announcement.)\n\nThese requirements apply to the modified work as a whole.  If\nidentifiable sections of that work are not derived from the Program,\nand can be reasonably considered independent and separate works in\nthemselves, then this License, and its terms, do not apply to those\nsections when you distribute them as separate works.  But when you\ndistribute the same sections as part of a whole which is a work based\non the Program, the distribution of the whole must be on the terms of\nthis License, whose permissions for other licensees extend to the\nentire whole, and thus to each and every part regardless of who wrote it.\n\nThus, it is not the intent of this section to claim rights or contest\nyour rights to work written entirely by you; rather, the intent is to\nexercise the right to control the distribution of derivative or\ncollective works based on the Program.\n\nIn addition, mere aggregation of another work not based on the Program\nwith the Program (or with a work based on the Program) on a volume of\na storage or distribution medium does not bring the other work under\nthe scope of this License.\n\n  3. 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Many people have made\ngenerous contributions to the wide range of software distributed\nthrough that system in reliance on consistent application of that\nsystem; it is up to the author/donor to decide if he or she is willing\nto distribute software through any other system and a licensee cannot\nimpose that choice.\n\nThis section is intended to make thoroughly clear what is believed to\nbe a consequence of the rest of this License.\n\n  8. If the distribution and/or use of the Program is restricted in\ncertain countries either by patents or by copyrighted interfaces, the\noriginal copyright holder who places the Program under this License\nmay add an explicit geographical distribution limitation excluding\nthose countries, so that distribution is permitted only in or among\ncountries not thus excluded.  In such case, this License incorporates\nthe limitation as if written in the body of this License.\n\n  9. The Free Software Foundation may publish revised and/or new versions\nof the General Public License from time to time.  Such new versions will\nbe similar in spirit to the present version, but may differ in detail to\naddress new problems or concerns.\n\nEach version is given a distinguishing version number.  If the Program\nspecifies a version number of this License which applies to it and \"any\nlater version\", you have the option of following the terms and conditions\neither of that version or of any later version published by the Free\nSoftware Foundation.  If the Program does not specify a version number of\nthis License, you may choose any version ever published by the Free Software\nFoundation.\n\n  10. If you wish to incorporate parts of the Program into other free\nprograms whose distribution conditions are different, write to the author\nto ask for permission.  For software which is copyrighted by the Free\nSoftware Foundation, write to the Free Software Foundation; we sometimes\nmake exceptions for this.  Our decision will be guided by the two goals\nof preserving the free status of all derivatives of our free software and\nof promoting the sharing and reuse of software generally.\n\n                            NO WARRANTY\n\n  11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY\nFOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW.  EXCEPT WHEN\nOTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES\nPROVIDE THE PROGRAM \"AS IS\" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED\nOR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\nMERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.  THE ENTIRE RISK AS\nTO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU.  SHOULD THE\nPROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,\nREPAIR OR CORRECTION.\n\n  12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING\nWILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR\nREDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,\nINCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING\nOUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED\nTO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY\nYOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER\nPROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGES.\n\n                     END OF TERMS AND CONDITIONS\n"
  },
  {
    "path": "modelsim_pre_commit.py",
    "content": "#!/usr/bin/env python3\n#\n# This script prepares ModelSim *.mpf files for committing to git\n#\n# Why is this necessary?\n#\n# ModelSim notoriously shuffles the list of project files that are stored in its\n# configuration file (*.mpf) even if no files were added or removed. That results\n# in a version system (git, in this case) to always report mpf files as changed\n# and needed to be committed even if there has been no _effective_ change to it.\n#\n# This script sorts the list of project files in a consistent way so no change\n# will result in files looking the same way. In addition, the same is done with\n# (key value) pairs within each file's line containing properties.\n#\n# Run this script before committing changes to git and bogus modifications will\n# magically dissapear!\n#\n#-------------------------------------------------------------------------------\n#  Copyright (C) 2014  Goran Devic\n#\n#  This program is free software; you can redistribute it and/or modify it\n#  under the terms of the GNU General Public License as published by the Free\n#  Software Foundation; either version 2 of the License, or (at your option)\n#  any later version.\n#\n#  This program is distributed in the hope that it will be useful, but WITHOUT\n#  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n#  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n#  more details.\n#-------------------------------------------------------------------------------\nimport os\nimport glob\n\ndef fixup():\n    # Open and read any ModelSim project file (we normally have one per project)\n    for file in glob.glob(\"*.mpf\"):\n        in_file_section = 0\n        # We use the fact that a file property line immediately follows the file name\n        current_name = \"\"\n        pf = {}\n        with open(file, \"r\") as f, open(file+\".new\", \"w\") as g:\n            for line in f:\n                if \"Project_File_P_\" in line:\n                    # In addition, sort the \"key value\" pairs in the property line\n                    # since ModelSim randomly shuffles them as well\n                    pp = {}\n                    prop = line.partition(\" = \")[2].split(\" \")\n                    i = 0\n                    while(i<len(prop)):\n                        key = prop[i]\n                        value = prop[i+1]\n                        # A property value that has a space is enclosed in { .. }\n                        if \"{}\" not in value and \"{\" in value:\n                            i = i + 1\n                            value = value + \" \" + prop[i+1]\n                        # Another hack: ignore property \"last_compile\" since it always changes\n                        if \"last_compile\" in key:\n                            value = \"1\"\n                        # Another hack: ignore property \"ood\"\n                        if \"ood\" in key:\n                            value = \"0\"\n                        pp[key] = value.strip()\n                        i = i + 2\n                    sorted_prop = \"\"\n                    for k,v in sorted(pp.items()):\n                        sorted_prop = sorted_prop + \" {0} {1}\".format(k,v)\n                    pf[current_name] = sorted_prop.lstrip() + \"\\n\"\n                    in_file_section = 1\n                    continue\n                if \"Project_File_\" in line:\n                    current_name = line.partition(\" = \")[2]\n                    in_file_section = 1\n                    # When we are already at it, make sure project files are relative to the $ROOT\n                    if \"$ROOT\" not in line:\n                        g.write(\"; Warning: Path {0} is not relative to the $ROOT!\\n\".format(current_name.strip()))\n                    continue\n                # We are not in the file section any more since we are here\n                if in_file_section:\n                    # Flush out our file list in a predictable order\n                    i = 0\n                    for k,v in sorted(pf.items()):\n                        g.write(\"Project_File_{0} = {1}\".format(i, k))\n                        g.write(\"Project_File_P_{0} = {1}\".format(i, v))\n                        i = i + 1\n                    in_file_section = 0\n                g.write(line.strip() + \"\\n\") # Trim whitespaces that ModelSim sometimes adds randomly\n        # Lastly, replace old mpf file with the new one\n        os.remove(file)\n        os.rename(file+\".new\", file)\n\n# Return to our current directory after each module has been visited\nabspath = os.path.abspath(__file__)\ndname = os.path.dirname(abspath)\n\n# Visit each ModelSim project directory...\nos.chdir(\"cpu/alu/simulation/modelsim\")\nfixup()\nos.chdir(dname)\n\nos.chdir(\"cpu/bus/simulation/modelsim\")\nfixup()\nos.chdir(dname)\n\nos.chdir(\"cpu/control/simulation/modelsim\")\nfixup()\nos.chdir(dname)\n\nos.chdir(\"cpu/registers/simulation/modelsim\")\nfixup()\nos.chdir(dname)\n\nos.chdir(\"cpu/toplevel/simulation/modelsim\")\nfixup()\nos.chdir(dname)\n\nos.chdir(\"host/basic_de1/simulation/modelsim\")\nfixup()\nos.chdir(dname)\n"
  },
  {
    "path": "modelsim_setup.py",
    "content": "#!/usr/bin/env python3\n#\n# This script sets up the environment to run ModelSim on each module.\n#\n# It sets up a relative path to your specific directory mapping by creating\n# a file \"mgc_location_map\". We use the loction mapping so all paths to source\n# files are relative.\n#\n#-------------------------------------------------------------------------------\n#  Copyright (C) 2014  Goran Devic\n#\n#  This program is free software; you can redistribute it and/or modify it\n#  under the terms of the GNU General Public License as published by the Free\n#  Software Foundation; either version 2 of the License, or (at your option)\n#  any later version.\n#\n#  This program is distributed in the hope that it will be useful, but WITHOUT\n#  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n#  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n#  more details.\n#-------------------------------------------------------------------------------\nimport os\n\ndef setup():\n    # Create mgc_location_map with relative path mapping\n    # Assumes this directory hierarchy:\n    # $ROOT/<block>/<module>/simulation/modelsim/work/<this script>.py\n    with open(\"mgc_location_map\", \"w\") as f:\n        f.write(\"$ROOT\\n\")\n        path = os.path.abspath(\"../../../.\")\n        f.write(os.path.dirname(path))\n        print (\"Setting up\", os.getcwd())\n\n# Return to our current directory after each module has been visited\nabspath = os.path.abspath(__file__)\ndname = os.path.dirname(abspath)\n\n# Visit each ModelSim project directory...\nos.chdir(\"cpu/alu/simulation/modelsim\")\nsetup()\nos.chdir(dname)\n\nos.chdir(\"cpu/bus/simulation/modelsim\")\nsetup()\nos.chdir(dname)\n\nos.chdir(\"cpu/control/simulation/modelsim\")\nsetup()\nos.chdir(dname)\n\nos.chdir(\"cpu/registers/simulation/modelsim\")\nsetup()\nos.chdir(dname)\n\nos.chdir(\"cpu/toplevel/simulation/modelsim\")\nsetup()\nos.chdir(dname)\n\nos.chdir(\"host/basic_de1/simulation/modelsim\")\nsetup()\nos.chdir(dname)\n"
  },
  {
    "path": "readme.txt",
    "content": "                               A-Z80\n             A conceptual implementation of the Z80 CPU\n             ------------------------------------------\n                for Altera, Xilinx and Lattice FPGAs\n\nThis project is described in more details at https://baltazarstudios.com\n\nFor additional information, read 'Quick Start' and 'Users Guide' documents\nin the 'docs' folder. Also read a 'readme.txt' file in each of the folders.\n\nPrerequisites\n=============\n* Altera Quartus and Modelsim (free web editions) OR\n* Xilinx ISE (free Webpack edition) OR\n* Lattice ICECube toolchain from Synopsis (Lattice tested by JuanS)\n* Python 3.5 or newer\n\nImporting A-Z80 into your project\n=================================\nIf you want to use A-Z80 in your own project, run \"export.py\" script which\nwill copy only the files that are needed. Do not manually pick and copy files.\n\nFolder layout\n=============\n\"cpu\" folder contains CPU functional blocks and all top-level modules:\n  alu         ALU block, ALU control and flags logic\n  bus         data bus switches, pin logic, address latch and incrementer\n  control     PLA decoder, the sequencer and other control blocks\n  registers   CPU register file and the register control logic\n  toplevel    top level core, interfaces and test code\n\n\"host\" folder integrates the A-Z80 CPU into several fully functional designs:\n  \"basic_de1\" contains a simplified board consisting of A-Z80 CPU, memory\n          and UART modules that can run small Z80 programs on Altera DE1\n  \"basic_nexys3\" contains the same example project but for Xilinx Nexys3 board\n  \"zxspectrum_de1\" contains a simple implementation of the Sinclair ZX Spectrum\n          for Altera DE1 board\n\n\"tools\", \"resources\" contain various tools related to the project; reverse\n  engineering of the real Z80, design verification and testing.\n\nEmail me if you have any questions, issues or you want to use A-Z80 or any of\nthe files within this project. I'd like to hear from you,\n\nGoran Devic\ngdevic@yahoo.com\n\n----------------------------------------------------------------------------------\nThis project and each file therein is covered under the GNU GPL2.0 license.\nIt basically states that anyone is free to use it and distribute it, but the full\nsource needs to be available under the same terms.\n"
  },
  {
    "path": "resources/connotate-fuse.bat",
    "content": "Rem Fuse tests are read from the fuse directory and modified versions\nRem are stored in the same folder, but with the .out extension\n\npython connotate-fuse.py ..\\cpu\\toplevel\\fuse\\regress.in\npython connotate-fuse.py ..\\cpu\\toplevel\\fuse\\regress.expected\npython connotate-fuse.py ..\\cpu\\toplevel\\fuse\\tests.in\npython connotate-fuse.py ..\\cpu\\toplevel\\fuse\\tests.expected\n"
  },
  {
    "path": "resources/connotate-fuse.py",
    "content": "#!/usr/bin/env python3\n#\n# This script connotates fuse test files with Z80 opcode strings.\n# Run it once to convert original fuse files to a new, connotated format.\n#\n#-------------------------------------------------------------------------------\n#  Copyright (C) 2014  Goran Devic\n#\n#  This program is free software; you can redistribute it and/or modify it\n#  under the terms of the GNU General Public License as published by the Free\n#  Software Foundation; either version 2 of the License, or (at your option)\n#  any later version.\n#\n#  This program is distributed in the hope that it will be useful, but WITHOUT\n#  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n#  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n#  more details.\n#-------------------------------------------------------------------------------\nimport string\nimport os\nimport sys\n\nop = {}\n\n# Read all available Z80 opcode strings that we have, hash them by the opcode\ndef load(opcodeFile):\n    global op\n    with open(opcodeFile) as fIn:\n        for line in fIn:\n            (opcode, mnemonic) = (line.split()[0], line[12:])\n            # Special case with ddcb and fdcb where our two formats slightly differ\n            if opcode==\"DDCB\" or opcode==\"FDCB\":\n                (opcode, mnemonic) = (line.split()[0]+line.split()[2], line[12:])\n            op[opcode] = mnemonic.rstrip()\n\nload(\"opcodes-xx.txt\")\nload(\"opcodes-cb-xx.txt\")\nload(\"opcodes-dd-cb.txt\")\nload(\"opcodes-dd-xx.txt\")\nload(\"opcodes-ed-xx.txt\")\nload(\"opcodes-fd-cb.txt\")\nload(\"opcodes-fd-xx.txt\")\n\nif len(sys.argv)!=2:\n    print (\"Usage:\", sys.argv[0], \"<fuse-test-file>\")\n    exit(0)\nfile = sys.argv[1]\n\nwith open(file) as f, open(file+\".out\", \"wt\") as f2:\n    for line in f:\n        line = line.rstrip()\n        if line is None: break\n        parts = line.split()\n        note = \"\"\n        if len(parts)==1 and parts[0]!=\"-1\":\n            index = parts[0].split(\"_\")[0].upper()\n            if index in op:\n                note = \" \" + \" \"*(7-len(parts[0])) + op[index.upper()]\n        f2.write(line + note + \"\\n\")\n        print (line + note)\n"
  },
  {
    "path": "resources/opcodes-cb-xx.txt",
    "content": "CB00        RLC B\nCB01        RLC C\nCB02        RLC D\nCB03        RLC E\nCB04        RLC H\nCB05        RLC L\nCB06        RLC (HL)\nCB07        RLC A\nCB08        RRC B\nCB09        RRC C\nCB0A        RRC D\nCB0B        RRC E\nCB0C        RRC H\nCB0D        RRC L\nCB0E        RRC (HL)\nCB0F        RRC A\nCB10        RL B\nCB11        RL C\nCB12        RL D\nCB13        RL E\nCB14        RL H\nCB15        RL L\nCB16        RL (HL)\nCB17        RL A\nCB18        RR B\nCB19        RR C\nCB1A        RR D\nCB1B        RR E\nCB1C        RR H\nCB1D        RR L\nCB1E        RR (HL)\nCB1F        RR A\nCB20        SLA B\nCB21        SLA C\nCB22        SLA D\nCB23        SLA E\nCB24        SLA H\nCB25        SLA L\nCB26        SLA (HL)\nCB27        SLA A\nCB28        SRA B\nCB29        SRA C\nCB2A        SRA D\nCB2B        SRA E\nCB2C        SRA H\nCB2D        SRA L\nCB2E        SRA (HL)\nCB2F        SRA A\nCB30        SLL B*\nCB31        SLL C*\nCB32        SLL D*\nCB33        SLL E*\nCB34        SLL H*\nCB35        SLL L*\nCB36        SLL (HL)*\nCB37        SLL A*\nCB38        SRL B\nCB39        SRL C\nCB3A        SRL D\nCB3B        SRL E\nCB3C        SRL H\nCB3D        SRL L\nCB3E        SRL (HL)\nCB3F        SRL A\nCB40        BIT 0,B\nCB41        BIT 0,C\nCB42        BIT 0,D\nCB43        BIT 0,E\nCB44        BIT 0,H\nCB45        BIT 0,L\nCB46        BIT 0,(HL)\nCB47        BIT 0,A\nCB48        BIT 1,B\nCB49        BIT 1,C\nCB4A        BIT 1,D\nCB4B        BIT 1,E\nCB4C        BIT 1,H\nCB4D        BIT 1,L\nCB4E        BIT 1,(HL)\nCB4F        BIT 1,A\nCB50        BIT 2,B\nCB51        BIT 2,C\nCB52        BIT 2,D\nCB53        BIT 2,E\nCB54        BIT 2,H\nCB55        BIT 2,L\nCB56        BIT 2,(HL)\nCB57        BIT 2,A\nCB58        BIT 3,B\nCB59        BIT 3,C\nCB5A        BIT 3,D\nCB5B        BIT 3,E\nCB5C        BIT 3,H\nCB5D        BIT 3,L\nCB5E        BIT 3,(HL)\nCB5F        BIT 3,A\nCB60        BIT 4,B\nCB61        BIT 4,C\nCB62        BIT 4,D\nCB63        BIT 4,E\nCB64        BIT 4,H\nCB65        BIT 4,L\nCB66        BIT 4,(HL)\nCB67        BIT 4,A\nCB68        BIT 5,B\nCB69        BIT 5,C\nCB6A        BIT 5,D\nCB6B        BIT 5,E\nCB6C        BIT 5,H\nCB6D        BIT 5,L\nCB6E        BIT 5,(HL)\nCB6F        BIT 5,A\nCB70        BIT 6,B\nCB71        BIT 6,C\nCB72        BIT 6,D\nCB73        BIT 6,E\nCB74        BIT 6,H\nCB75        BIT 6,L\nCB76        BIT 6,(HL)\nCB77        BIT 6,A\nCB78        BIT 7,B\nCB79        BIT 7,C\nCB7A        BIT 7,D\nCB7B        BIT 7,E\nCB7C        BIT 7,H\nCB7D        BIT 7,L\nCB7E        BIT 7,(HL)\nCB7F        BIT 7,A\nCB80        RES 0,B\nCB81        RES 0,C\nCB82        RES 0,D\nCB83        RES 0,E\nCB84        RES 0,H\nCB85        RES 0,L\nCB86        RES 0,(HL)\nCB87        RES 0,A\nCB88        RES 1,B\nCB89        RES 1,C\nCB8A        RES 1,D\nCB8B        RES 1,E\nCB8C        RES 1,H\nCB8D        RES 1,L\nCB8E        RES 1,(HL)\nCB8F        RES 1,A\nCB90        RES 2,B\nCB91        RES 2,C\nCB92        RES 2,D\nCB93        RES 2,E\nCB94        RES 2,H\nCB95        RES 2,L\nCB96        RES 2,(HL)\nCB97        RES 2,A\nCB98        RES 3,B\nCB99        RES 3,C\nCB9A        RES 3,D\nCB9B        RES 3,E\nCB9C        RES 3,H\nCB9D        RES 3,L\nCB9E        RES 3,(HL)\nCB9F        RES 3,A\nCBA0        RES 4,B\nCBA1        RES 4,C\nCBA2        RES 4,D\nCBA3        RES 4,E\nCBA4        RES 4,H\nCBA5        RES 4,L\nCBA6        RES 4,(HL)\nCBA7        RES 4,A\nCBA8        RES 5,B\nCBA9        RES 5,C\nCBAA        RES 5,D\nCBAB        RES 5,E\nCBAC        RES 5,H\nCBAD        RES 5,L\nCBAE        RES 5,(HL)\nCBAF        RES 5,A\nCBB0        RES 6,B\nCBB1        RES 6,C\nCBB2        RES 6,D\nCBB3        RES 6,E\nCBB4        RES 6,H\nCBB5        RES 6,L\nCBB6        RES 6,(HL)\nCBB7        RES 6,A\nCBB8        RES 7,B\nCBB9        RES 7,C\nCBBA        RES 7,D\nCBBB        RES 7,E\nCBBC        RES 7,H\nCBBD        RES 7,L\nCBBE        RES 7,(HL)\nCBBF        RES 7,A\nCBC0        SET 0,B\nCBC1        SET 0,C\nCBC2        SET 0,D\nCBC3        SET 0,E\nCBC4        SET 0,H\nCBC5        SET 0,L\nCBC6        SET 0,(HL)\nCBC7        SET 0,A\nCBC8        SET 1,B\nCBC9        SET 1,C\nCBCA        SET 1,D\nCBCB        SET 1,E\nCBCC        SET 1,H\nCBCD        SET 1,L\nCBCE        SET 1,(HL)\nCBCF        SET 1,A\nCBD0        SET 2,B\nCBD1        SET 2,C\nCBD2        SET 2,D\nCBD3        SET 2,E\nCBD4        SET 2,H\nCBD5        SET 2,L\nCBD6        SET 2,(HL)\nCBD7        SET 2,A\nCBD8        SET 3,B\nCBD9        SET 3,C\nCBDA        SET 3,D\nCBDB        SET 3,E\nCBDC        SET 3,H\nCBDD        SET 3,L\nCBDE        SET 3,(HL)\nCBDF        SET 3,A\nCBE0        SET 4,B\nCBE1        SET 4,C\nCBE2        SET 4,D\nCBE3        SET 4,E\nCBE4        SET 4,H\nCBE5        SET 4,L\nCBE6        SET 4,(HL)\nCBE7        SET 4,A\nCBE8        SET 5,B\nCBE9        SET 5,C\nCBEA        SET 5,D\nCBEB        SET 5,E\nCBEC        SET 5,H\nCBED        SET 5,L\nCBEE        SET 5,(HL)\nCBEF        SET 5,A\nCBF0        SET 6,B\nCBF1        SET 6,C\nCBF2        SET 6,D\nCBF3        SET 6,E\nCBF4        SET 6,H\nCBF5        SET 6,L\nCBF6        SET 6,(HL)\nCBF7        SET 6,A\nCBF8        SET 7,B\nCBF9        SET 7,C\nCBFA        SET 7,D\nCBFB        SET 7,E\nCBFC        SET 7,H\nCBFD        SET 7,L\nCBFE        SET 7,(HL)\nCBFF        SET 7,A"
  },
  {
    "path": "resources/opcodes-dd-cb.txt",
    "content": "DDCB d 00   RLC (IX+d),B*\nDDCB d 01   RLC (IX+d),C*\nDDCB d 02   RLC (IX+d),D*\nDDCB d 03   RLC (IX+d),E*\nDDCB d 04   RLC (IX+d),H*\nDDCB d 05   RLC (IX+d),L*\nDDCB d 06   RLC (IX+d)\nDDCB d 07   RLC (IX+d),A*\nDDCB d 08   RRC (IX+d),B*\nDDCB d 09   RRC (IX+d),C*\nDDCB d 0A   RRC (IX+d),D*\nDDCB d 0B   RRC (IX+d),E*\nDDCB d 0C   RRC (IX+d),H*\nDDCB d 0D   RRC (IX+d),L*\nDDCB d 0E   RRC (IX+d)\nDDCB d 0F   RRC (IX+d),A*\nDDCB d 10   RL (IX+d),B*\nDDCB d 11   RL (IX+d),C*\nDDCB d 12   RL (IX+d),D*\nDDCB d 13   RL (IX+d),E*\nDDCB d 14   RL (IX+d),H*\nDDCB d 15   RL (IX+d),L*\nDDCB d 16   RL (IX+d)\nDDCB d 17   RL (IX+d),A*\nDDCB d 18   RR (IX+d),B*\nDDCB d 19   RR (IX+d),C*\nDDCB d 1A   RR (IX+d),D*\nDDCB d 1B   RR (IX+d),E*\nDDCB d 1C   RR (IX+d),H*\nDDCB d 1D   RR (IX+d),L*\nDDCB d 1E   RR (IX+d)\nDDCB d 1F   RR (IX+d),A*\nDDCB d 20   SLA (IX+d),B*\nDDCB d 21   SLA (IX+d),C*\nDDCB d 22   SLA (IX+d),D*\nDDCB d 23   SLA (IX+d),E*\nDDCB d 24   SLA (IX+d),H*\nDDCB d 25   SLA (IX+d),L*\nDDCB d 26   SLA (IX+d)\nDDCB d 27   SLA (IX+d),A*\nDDCB d 28   SRA (IX+d),B*\nDDCB d 29   SRA (IX+d),C*\nDDCB d 2A   SRA (IX+d),D*\nDDCB d 2B   SRA (IX+d),E*\nDDCB d 2C   SRA (IX+d),H*\nDDCB d 2D   SRA (IX+d),L*\nDDCB d 2E   SRA (IX+d)\nDDCB d 2F   SRA (IX+d),A*\nDDCB d 30   SLL (IX+d),B*\nDDCB d 31   SLL (IX+d),C*\nDDCB d 32   SLL (IX+d),D*\nDDCB d 33   SLL (IX+d),E*\nDDCB d 34   SLL (IX+d),H*\nDDCB d 35   SLL (IX+d),L*\nDDCB d 36   SLL (IX+d)*\nDDCB d 37   SLL (IX+d),A*\nDDCB d 38   SRL (IX+d),B*\nDDCB d 39   SRL (IX+d),C*\nDDCB d 3A   SRL (IX+d),D*\nDDCB d 3B   SRL (IX+d),E*\nDDCB d 3C   SRL (IX+d),H*\nDDCB d 3D   SRL (IX+d),L*\nDDCB d 3E   SRL (IX+d)\nDDCB d 3F   SRL (IX+d),A*\nDDCB d 40   BIT 0,(IX+d)*\nDDCB d 41   BIT 0,(IX+d)*\nDDCB d 42   BIT 0,(IX+d)*\nDDCB d 43   BIT 0,(IX+d)*\nDDCB d 44   BIT 0,(IX+d)*\nDDCB d 45   BIT 0,(IX+d)*\nDDCB d 46   BIT 0,(IX+d)\nDDCB d 47   BIT 0,(IX+d)*\nDDCB d 48   BIT 1,(IX+d)*\nDDCB d 49   BIT 1,(IX+d)*\nDDCB d 4A   BIT 1,(IX+d)*\nDDCB d 4B   BIT 1,(IX+d)*\nDDCB d 4C   BIT 1,(IX+d)*\nDDCB d 4D   BIT 1,(IX+d)*\nDDCB d 4E   BIT 1,(IX+d)\nDDCB d 4F   BIT 1,(IX+d)*\nDDCB d 50   BIT 2,(IX+d)*\nDDCB d 51   BIT 2,(IX+d)*\nDDCB d 52   BIT 2,(IX+d)*\nDDCB d 53   BIT 2,(IX+d)*\nDDCB d 54   BIT 2,(IX+d)*\nDDCB d 55   BIT 2,(IX+d)*\nDDCB d 56   BIT 2,(IX+d)\nDDCB d 57   BIT 2,(IX+d)*\nDDCB d 58   BIT 3,(IX+d)*\nDDCB d 59   BIT 3,(IX+d)*\nDDCB d 5A   BIT 3,(IX+d)*\nDDCB d 5B   BIT 3,(IX+d)*\nDDCB d 5C   BIT 3,(IX+d)*\nDDCB d 5D   BIT 3,(IX+d)*\nDDCB d 5E   BIT 3,(IX+d)\nDDCB d 5F   BIT 3,(IX+d)*\nDDCB d 60   BIT 4,(IX+d)*\nDDCB d 61   BIT 4,(IX+d)*\nDDCB d 62   BIT 4,(IX+d)*\nDDCB d 63   BIT 4,(IX+d)*\nDDCB d 64   BIT 4,(IX+d)*\nDDCB d 65   BIT 4,(IX+d)*\nDDCB d 66   BIT 4,(IX+d)\nDDCB d 67   BIT 4,(IX+d)*\nDDCB d 68   BIT 5,(IX+d)*\nDDCB d 69   BIT 5,(IX+d)*\nDDCB d 6A   BIT 5,(IX+d)*\nDDCB d 6B   BIT 5,(IX+d)*\nDDCB d 6C   BIT 5,(IX+d)*\nDDCB d 6D   BIT 5,(IX+d)*\nDDCB d 6E   BIT 5,(IX+d)\nDDCB d 6F   BIT 5,(IX+d)*\nDDCB d 70   BIT 6,(IX+d)*\nDDCB d 71   BIT 6,(IX+d)*\nDDCB d 72   BIT 6,(IX+d)*\nDDCB d 73   BIT 6,(IX+d)*\nDDCB d 74   BIT 6,(IX+d)*\nDDCB d 75   BIT 6,(IX+d)*\nDDCB d 76   BIT 6,(IX+d)\nDDCB d 77   BIT 6,(IX+d)*\nDDCB d 78   BIT 7,(IX+d)*\nDDCB d 79   BIT 7,(IX+d)*\nDDCB d 7A   BIT 7,(IX+d)*\nDDCB d 7B   BIT 7,(IX+d)*\nDDCB d 7C   BIT 7,(IX+d)*\nDDCB d 7D   BIT 7,(IX+d)*\nDDCB d 7E   BIT 7,(IX+d)\nDDCB d 7F   BIT 7,(IX+d)*\nDDCB d 80   RES 0,(IX+d),B*\nDDCB d 81   RES 0,(IX+d),C*\nDDCB d 82   RES 0,(IX+d),D*\nDDCB d 83   RES 0,(IX+d),E*\nDDCB d 84   RES 0,(IX+d),H*\nDDCB d 85   RES 0,(IX+d),L*\nDDCB d 86   RES 0,(IX+d)\nDDCB d 87   RES 0,(IX+d),A*\nDDCB d 88   RES 1,(IX+d),B*\nDDCB d 89   RES 1,(IX+d),C*\nDDCB d 8A   RES 1,(IX+d),D*\nDDCB d 8B   RES 1,(IX+d),E*\nDDCB d 8C   RES 1,(IX+d),H*\nDDCB d 8D   RES 1,(IX+d),L*\nDDCB d 8E   RES 1,(IX+d)\nDDCB d 8F   RES 1,(IX+d),A*\nDDCB d 90   RES 2,(IX+d),B*\nDDCB d 91   RES 2,(IX+d),C*\nDDCB d 92   RES 2,(IX+d),D*\nDDCB d 93   RES 2,(IX+d),E*\nDDCB d 94   RES 2,(IX+d),H*\nDDCB d 95   RES 2,(IX+d),L*\nDDCB d 96   RES 2,(IX+d)\nDDCB d 97   RES 2,(IX+d),A*\nDDCB d 98   RES 3,(IX+d),B*\nDDCB d 99   RES 3,(IX+d),C*\nDDCB d 9A   RES 3,(IX+d),D*\nDDCB d 9B   RES 3,(IX+d),E*\nDDCB d 9C   RES 3,(IX+d),H*\nDDCB d 9D   RES 3,(IX+d),L*\nDDCB d 9E   RES 3,(IX+d)\nDDCB d 9F   RES 3,(IX+d),A*\nDDCB d A0   RES 4,(IX+d),B*\nDDCB d A1   RES 4,(IX+d),C*\nDDCB d A2   RES 4,(IX+d),D*\nDDCB d A3   RES 4,(IX+d),E*\nDDCB d A4   RES 4,(IX+d),H*\nDDCB d A5   RES 4,(IX+d),L*\nDDCB d A6   RES 4,(IX+d)\nDDCB d A7   RES 4,(IX+d),A*\nDDCB d A8   RES 5,(IX+d),B*\nDDCB d A9   RES 5,(IX+d),C*\nDDCB d AA   RES 5,(IX+d),D*\nDDCB d AB   RES 5,(IX+d),E*\nDDCB d AC   RES 5,(IX+d),H*\nDDCB d AD   RES 5,(IX+d),L*\nDDCB d AE   RES 5,(IX+d)\nDDCB d AF   RES 5,(IX+d),A*\nDDCB d B0   RES 6,(IX+d),B*\nDDCB d B1   RES 6,(IX+d),C*\nDDCB d B2   RES 6,(IX+d),D*\nDDCB d B3   RES 6,(IX+d),E*\nDDCB d B4   RES 6,(IX+d),H*\nDDCB d B5   RES 6,(IX+d),L*\nDDCB d B6   RES 6,(IX+d)\nDDCB d B7   RES 6,(IX+d),A*\nDDCB d B8   RES 7,(IX+d),B*\nDDCB d B9   RES 7,(IX+d),C*\nDDCB d BA   RES 7,(IX+d),D*\nDDCB d BB   RES 7,(IX+d),E*\nDDCB d BC   RES 7,(IX+d),H*\nDDCB d BD   RES 7,(IX+d),L*\nDDCB d BE   RES 7,(IX+d)\nDDCB d BF   RES 7,(IX+d),A*\nDDCB d C0   SET 0,(IX+d),B*\nDDCB d C1   SET 0,(IX+d),C*\nDDCB d C2   SET 0,(IX+d),D*\nDDCB d C3   SET 0,(IX+d),E*\nDDCB d C4   SET 0,(IX+d),H*\nDDCB d C5   SET 0,(IX+d),L*\nDDCB d C6   SET 0,(IX+d)\nDDCB d C7   SET 0,(IX+d),A*\nDDCB d C8   SET 1,(IX+d),B*\nDDCB d C9   SET 1,(IX+d),C*\nDDCB d CA   SET 1,(IX+d),D*\nDDCB d CB   SET 1,(IX+d),E*\nDDCB d CC   SET 1,(IX+d),H*\nDDCB d CD   SET 1,(IX+d),L*\nDDCB d CE   SET 1,(IX+d)\nDDCB d CF   SET 1,(IX+d),A*\nDDCB d D0   SET 2,(IX+d),B*\nDDCB d D1   SET 2,(IX+d),C*\nDDCB d D2   SET 2,(IX+d),D*\nDDCB d D3   SET 2,(IX+d),E*\nDDCB d D4   SET 2,(IX+d),H*\nDDCB d D5   SET 2,(IX+d),L*\nDDCB d D6   SET 2,(IX+d)\nDDCB d D7   SET 2,(IX+d),A*\nDDCB d D8   SET 3,(IX+d),B*\nDDCB d D9   SET 3,(IX+d),C*\nDDCB d DA   SET 3,(IX+d),D*\nDDCB d DB   SET 3,(IX+d),E*\nDDCB d DC   SET 3,(IX+d),H*\nDDCB d DD   SET 3,(IX+d),L*\nDDCB d DE   SET 3,(IX+d)\nDDCB d DF   SET 3,(IX+d),A*\nDDCB d E0   SET 4,(IX+d),B*\nDDCB d E1   SET 4,(IX+d),C*\nDDCB d E2   SET 4,(IX+d),D*\nDDCB d E3   SET 4,(IX+d),E*\nDDCB d E4   SET 4,(IX+d),H*\nDDCB d E5   SET 4,(IX+d),L*\nDDCB d E6   SET 4,(IX+d)\nDDCB d E7   SET 4,(IX+d),A*\nDDCB d E8   SET 5,(IX+d),B*\nDDCB d E9   SET 5,(IX+d),C*\nDDCB d EA   SET 5,(IX+d),D*\nDDCB d EB   SET 5,(IX+d),E*\nDDCB d EC   SET 5,(IX+d),H*\nDDCB d ED   SET 5,(IX+d),L*\nDDCB d EE   SET 5,(IX+d)\nDDCB d EF   SET 5,(IX+d),A*\nDDCB d F0   SET 6,(IX+d),B*\nDDCB d F1   SET 6,(IX+d),C*\nDDCB d F2   SET 6,(IX+d),D*\nDDCB d F3   SET 6,(IX+d),E*\nDDCB d F4   SET 6,(IX+d),H*\nDDCB d F5   SET 6,(IX+d),L*\nDDCB d F6   SET 6,(IX+d)\nDDCB d F7   SET 6,(IX+d),A*\nDDCB d F8   SET 7,(IX+d),B*\nDDCB d F9   SET 7,(IX+d),C*\nDDCB d FA   SET 7,(IX+d),D*\nDDCB d FB   SET 7,(IX+d),E*\nDDCB d FC   SET 7,(IX+d),H*\nDDCB d FD   SET 7,(IX+d),L*\nDDCB d FE   SET 7,(IX+d)\nDDCB d FF   SET 7,(IX+d),A*"
  },
  {
    "path": "resources/opcodes-dd-xx.txt",
    "content": "DD09        ADD IX,BC\nDD19        ADD IX,DE\nDD21 n n    LD IX,nn\nDD22 n n    LD (nn),IX\nDD23        INC IX\nDD24        INC IXh*\nDD25        DEC IXh*\nDD26 n      LD IXh,n*\nDD29        ADD IX,IX\nDD2A n n    LD IX,(nn)\nDD2B        DEC IX\nDD2C        INC IXl*\nDD2D        DEC IXl*\nDD2E n      LD IXl,n*\nDD34 d      INC (IX+d)\nDD35 d      DEC (IX+d)\nDD36 d n    LD (IX+d),n\nDD39        ADD IX,SP\nDD44        LD B,IXh*\nDD45        LD B,IXl*\nDD46 d      LD B,(IX+d)\nDD4C        LD C,IXh*\nDD4D        LD C,IXl*\nDD4E d      LD C,(IX+d)\nDD54        LD D,IXh*\nDD55        LD D,IXl*\nDD56 d      LD D,(IX+d)\nDD5C        LD E,IXh*\nDD5D        LD E,IXl*\nDD5E d      LD E,(IX+d)\nDD60        LD IXh,B*\nDD61        LD IXh,C*\nDD62        LD IXh,D*\nDD63        LD IXh,E*\nDD64        LD IXh,IXh*\nDD65        LD IXh,IXl*\nDD66 d      LD H,(IX+d)\nDD67        LD IXh,A*\nDD68        LD IXl,B*\nDD69        LD IXl,C*\nDD6A        LD IXl,D*\nDD6B        LD IXl,E*\nDD6C        LD IXl,IXh*\nDD6D        LD IXl,IXl*\nDD6E d      LD L,(IX+d)\nDD6F        LD IXl,A*\nDD70 d      LD (IX+d),B\nDD71 d      LD (IX+d),C\nDD72 d      LD (IX+d),D\nDD73 d      LD (IX+d),E\nDD74 d      LD (IX+d),H\nDD75 d      LD (IX+d),L\nDD77 d      LD (IX+d),A\nDD7C        LD A,IXh*\nDD7D        LD A,IXl*\nDD7E d      LD A,(IX+d)\nDD84        ADD A,IXh*\nDD85        ADD A,IXl*\nDD86 d      ADD A,(IX+d)\nDD8C        ADC A,IXh*\nDD8D        ADC A,IXl*\nDD8E d      ADC A,(IX+d)\nDD94        SUB IXh*\nDD95        SUB IXl*\nDD96 d      SUB (IX+d)\nDD9C        SBC A,IXh*\nDD9D        SBC A,IXl*\nDD9E d      SBC A,(IX+d)\nDDA4        AND IXh*\nDDA5        AND IXl*\nDDA6 d      AND (IX+d)\nDDAC        XOR IXh*\nDDAD        XOR IXl*\nDDAE d      XOR (IX+d)\nDDB4        OR IXh*\nDDB5        OR IXl*\nDDB6 d      OR (IX+d)\nDDBC        CP IXh*\nDDBD        CP IXl*\nDDBE d      CP (IX+d)\nDDE1        POP IX\nDDE3        EX (SP),IX\nDDE5        PUSH IX\nDDE9        JP (IX)\nDDF9        LD SP,IX"
  },
  {
    "path": "resources/opcodes-ed-xx.txt",
    "content": "ED40        IN B,(C)\nED41        OUT (C),B\nED42        SBC HL,BC\nED43 n n    LD (nn),BC\nED44        NEG\nED45        RETN\nED46        IM 0\nED47        LD I,A\nED48        IN C,(C)\nED49        OUT (C),C\nED4A        ADC HL,BC\nED4B n n    LD BC,(nn)\nED4C        NEG*\nED4D        RETI\nED4E        IM 0*\nED4F        LD R,A\nED50        IN D,(C)\nED51        OUT (C),D\nED52        SBC HL,DE\nED53 n n    LD (nn),DE\nED54        NEG*\nED55        RETN*\nED56        IM 1\nED57        LD A,I\nED58        IN E,(C)\nED59        OUT (C),E\nED5A        ADC HL,DE\nED5B n n    LD DE,(nn)\nED5C        NEG*\nED5D        RETN*\nED5E        IM 2\nED5F        LD A,R\nED60        IN H,(C)\nED61        OUT (C),H\nED62        SBC HL,HL\nED63 n n    LD (nn),HL\nED64        NEG*\nED65        RETN*\nED66        IM 0*\nED67        RRD\nED68        IN L,(C)\nED69        OUT (C),L\nED6A        ADC HL,HL\nED6B n n    LD HL,(nn)\nED6C        NEG*\nED6D        RETN*\nED6E        IM 0*\nED6F        RLD\nED70        IN F,(C)*\nED71        OUT (C),0*\nED72        SBC HL,SP\nED73 n n    LD (nn),SP\nED74        NEG*\nED75        RETN*\nED76        IM 1*\nED78        IN A,(C)\nED79        OUT (C),A\nED7A        ADC HL,SP\nED7B n n    LD SP,(nn)\nED7C        NEG*\nED7D        RETN*\nED7E        IM 2*\nEDA0        LDI\nEDA1        CPI\nEDA2        INI\nEDA3        OUTI\nEDA8        LDD\nEDA9        CPD\nEDAA        IND\nEDAB        OUTD\nEDB0        LDIR\nEDB1        CPIR\nEDB2        INIR\nEDB3        OTIR\nEDB8        LDDR\nEDB9        CPDR\nEDBA        INDR\nEDBB        OTDR"
  },
  {
    "path": "resources/opcodes-fd-cb.txt",
    "content": "FDCB d 00   RLC (IY+d),B*\nFDCB d 01   RLC (IY+d),C*\nFDCB d 02   RLC (IY+d),D*\nFDCB d 03   RLC (IY+d),E*\nFDCB d 04   RLC (IY+d),H*\nFDCB d 05   RLC (IY+d),L*\nFDCB d 06   RLC (IY+d)\nFDCB d 07   RLC (IY+d),A*\nFDCB d 08   RRC (IY+d),B*\nFDCB d 09   RRC (IY+d),C*\nFDCB d 0A   RRC (IY+d),D*\nFDCB d 0B   RRC (IY+d),E*\nFDCB d 0C   RRC (IY+d),H*\nFDCB d 0D   RRC (IY+d),L*\nFDCB d 0E   RRC (IY+d)\nFDCB d 0F   RRC (IY+d),A*\nFDCB d 10   RL (IY+d),B*\nFDCB d 11   RL (IY+d),C*\nFDCB d 12   RL (IY+d),D*\nFDCB d 13   RL (IY+d),E*\nFDCB d 14   RL (IY+d),H*\nFDCB d 15   RL (IY+d),L*\nFDCB d 16   RL (IY+d)\nFDCB d 17   RL (IY+d),A*\nFDCB d 18   RR (IY+d),B*\nFDCB d 19   RR (IY+d),C*\nFDCB d 1A   RR (IY+d),D*\nFDCB d 1B   RR (IY+d),E*\nFDCB d 1C   RR (IY+d),H*\nFDCB d 1D   RR (IY+d),L*\nFDCB d 1E   RR (IY+d)\nFDCB d 1F   RR (IY+d),A*\nFDCB d 20   SLA (IY+d),B*\nFDCB d 21   SLA (IY+d),C*\nFDCB d 22   SLA (IY+d),D*\nFDCB d 23   SLA (IY+d),E*\nFDCB d 24   SLA (IY+d),H*\nFDCB d 25   SLA (IY+d),L*\nFDCB d 26   SLA (IY+d)\nFDCB d 27   SLA (IY+d),A*\nFDCB d 28   SRA (IY+d),B*\nFDCB d 29   SRA (IY+d),C*\nFDCB d 2A   SRA (IY+d),D*\nFDCB d 2B   SRA (IY+d),E*\nFDCB d 2C   SRA (IY+d),H*\nFDCB d 2D   SRA (IY+d),L*\nFDCB d 2E   SRA (IY+d)\nFDCB d 2F   SRA (IY+d),A*\nFDCB d 30   SLL (IY+d),B*\nFDCB d 31   SLL (IY+d),C*\nFDCB d 32   SLL (IY+d),D*\nFDCB d 33   SLL (IY+d),E*\nFDCB d 34   SLL (IY+d),H*\nFDCB d 35   SLL (IY+d),L*\nFDCB d 36   SLL (IY+d)*\nFDCB d 37   SLL (IY+d),A*\nFDCB d 38   SRL (IY+d),B*\nFDCB d 39   SRL (IY+d),C*\nFDCB d 3A   SRL (IY+d),D*\nFDCB d 3B   SRL (IY+d),E*\nFDCB d 3C   SRL (IY+d),H*\nFDCB d 3D   SRL (IY+d),L*\nFDCB d 3E   SRL (IY+d)\nFDCB d 3F   SRL (IY+d),A*\nFDCB d 40   BIT 0,(IY+d)*\nFDCB d 41   BIT 0,(IY+d)*\nFDCB d 42   BIT 0,(IY+d)*\nFDCB d 43   BIT 0,(IY+d)*\nFDCB d 44   BIT 0,(IY+d)*\nFDCB d 45   BIT 0,(IY+d)*\nFDCB d 46   BIT 0,(IY+d)\nFDCB d 47   BIT 0,(IY+d)*\nFDCB d 48   BIT 1,(IY+d)*\nFDCB d 49   BIT 1,(IY+d)*\nFDCB d 4A   BIT 1,(IY+d)*\nFDCB d 4B   BIT 1,(IY+d)*\nFDCB d 4C   BIT 1,(IY+d)*\nFDCB d 4D   BIT 1,(IY+d)*\nFDCB d 4E   BIT 1,(IY+d)\nFDCB d 4F   BIT 1,(IY+d)*\nFDCB d 50   BIT 2,(IY+d)*\nFDCB d 51   BIT 2,(IY+d)*\nFDCB d 52   BIT 2,(IY+d)*\nFDCB d 53   BIT 2,(IY+d)*\nFDCB d 54   BIT 2,(IY+d)*\nFDCB d 55   BIT 2,(IY+d)*\nFDCB d 56   BIT 2,(IY+d)\nFDCB d 57   BIT 2,(IY+d)*\nFDCB d 58   BIT 3,(IY+d)*\nFDCB d 59   BIT 3,(IY+d)*\nFDCB d 5A   BIT 3,(IY+d)*\nFDCB d 5B   BIT 3,(IY+d)*\nFDCB d 5C   BIT 3,(IY+d)*\nFDCB d 5D   BIT 3,(IY+d)*\nFDCB d 5E   BIT 3,(IY+d)\nFDCB d 5F   BIT 3,(IY+d)*\nFDCB d 60   BIT 4,(IY+d)*\nFDCB d 61   BIT 4,(IY+d)*\nFDCB d 62   BIT 4,(IY+d)*\nFDCB d 63   BIT 4,(IY+d)*\nFDCB d 64   BIT 4,(IY+d)*\nFDCB d 65   BIT 4,(IY+d)*\nFDCB d 66   BIT 4,(IY+d)\nFDCB d 67   BIT 4,(IY+d)*\nFDCB d 68   BIT 5,(IY+d)*\nFDCB d 69   BIT 5,(IY+d)*\nFDCB d 6A   BIT 5,(IY+d)*\nFDCB d 6B   BIT 5,(IY+d)*\nFDCB d 6C   BIT 5,(IY+d)*\nFDCB d 6D   BIT 5,(IY+d)*\nFDCB d 6E   BIT 5,(IY+d)\nFDCB d 6F   BIT 5,(IY+d)*\nFDCB d 70   BIT 6,(IY+d)*\nFDCB d 71   BIT 6,(IY+d)*\nFDCB d 72   BIT 6,(IY+d)*\nFDCB d 73   BIT 6,(IY+d)*\nFDCB d 74   BIT 6,(IY+d)*\nFDCB d 75   BIT 6,(IY+d)*\nFDCB d 76   BIT 6,(IY+d)\nFDCB d 77   BIT 6,(IY+d)*\nFDCB d 78   BIT 7,(IY+d)*\nFDCB d 79   BIT 7,(IY+d)*\nFDCB d 7A   BIT 7,(IY+d)*\nFDCB d 7B   BIT 7,(IY+d)*\nFDCB d 7C   BIT 7,(IY+d)*\nFDCB d 7D   BIT 7,(IY+d)*\nFDCB d 7E   BIT 7,(IY+d)\nFDCB d 7F   BIT 7,(IY+d)*\nFDCB d 80   RES 0,(IY+d),B*\nFDCB d 81   RES 0,(IY+d),C*\nFDCB d 82   RES 0,(IY+d),D*\nFDCB d 83   RES 0,(IY+d),E*\nFDCB d 84   RES 0,(IY+d),H*\nFDCB d 85   RES 0,(IY+d),L*\nFDCB d 86   RES 0,(IY+d)\nFDCB d 87   RES 0,(IY+d),A*\nFDCB d 88   RES 1,(IY+d),B*\nFDCB d 89   RES 1,(IY+d),C*\nFDCB d 8A   RES 1,(IY+d),D*\nFDCB d 8B   RES 1,(IY+d),E*\nFDCB d 8C   RES 1,(IY+d),H*\nFDCB d 8D   RES 1,(IY+d),L*\nFDCB d 8E   RES 1,(IY+d)\nFDCB d 8F   RES 1,(IY+d),A*\nFDCB d 90   RES 2,(IY+d),B*\nFDCB d 91   RES 2,(IY+d),C*\nFDCB d 92   RES 2,(IY+d),D*\nFDCB d 93   RES 2,(IY+d),E*\nFDCB d 94   RES 2,(IY+d),H*\nFDCB d 95   RES 2,(IY+d),L*\nFDCB d 96   RES 2,(IY+d)\nFDCB d 97   RES 2,(IY+d),A*\nFDCB d 98   RES 3,(IY+d),B*\nFDCB d 99   RES 3,(IY+d),C*\nFDCB d 9A   RES 3,(IY+d),D*\nFDCB d 9B   RES 3,(IY+d),E*\nFDCB d 9C   RES 3,(IY+d),H*\nFDCB d 9D   RES 3,(IY+d),L*\nFDCB d 9E   RES 3,(IY+d)\nFDCB d 9F   RES 3,(IY+d),A*\nFDCB d A0   RES 4,(IY+d),B*\nFDCB d A1   RES 4,(IY+d),C*\nFDCB d A2   RES 4,(IY+d),D*\nFDCB d A3   RES 4,(IY+d),E*\nFDCB d A4   RES 4,(IY+d),H*\nFDCB d A5   RES 4,(IY+d),L*\nFDCB d A6   RES 4,(IY+d)\nFDCB d A7   RES 4,(IY+d),A*\nFDCB d A8   RES 5,(IY+d),B*\nFDCB d A9   RES 5,(IY+d),C*\nFDCB d AA   RES 5,(IY+d),D*\nFDCB d AB   RES 5,(IY+d),E*\nFDCB d AC   RES 5,(IY+d),H*\nFDCB d AD   RES 5,(IY+d),L*\nFDCB d AE   RES 5,(IY+d)\nFDCB d AF   RES 5,(IY+d),A*\nFDCB d B0   RES 6,(IY+d),B*\nFDCB d B1   RES 6,(IY+d),C*\nFDCB d B2   RES 6,(IY+d),D*\nFDCB d B3   RES 6,(IY+d),E*\nFDCB d B4   RES 6,(IY+d),H*\nFDCB d B5   RES 6,(IY+d),L*\nFDCB d B6   RES 6,(IY+d)\nFDCB d B7   RES 6,(IY+d),A*\nFDCB d B8   RES 7,(IY+d),B*\nFDCB d B9   RES 7,(IY+d),C*\nFDCB d BA   RES 7,(IY+d),D*\nFDCB d BB   RES 7,(IY+d),E*\nFDCB d BC   RES 7,(IY+d),H*\nFDCB d BD   RES 7,(IY+d),L*\nFDCB d BE   RES 7,(IY+d)\nFDCB d BF   RES 7,(IY+d),A*\nFDCB d C0   SET 0,(IY+d),B*\nFDCB d C1   SET 0,(IY+d),C*\nFDCB d C2   SET 0,(IY+d),D*\nFDCB d C3   SET 0,(IY+d),E*\nFDCB d C4   SET 0,(IY+d),H*\nFDCB d C5   SET 0,(IY+d),L*\nFDCB d C6   SET 0,(IY+d)\nFDCB d C7   SET 0,(IY+d),A*\nFDCB d C8   SET 1,(IY+d),B*\nFDCB d C9   SET 1,(IY+d),C*\nFDCB d CA   SET 1,(IY+d),D*\nFDCB d CB   SET 1,(IY+d),E*\nFDCB d CC   SET 1,(IY+d),H*\nFDCB d CD   SET 1,(IY+d),L*\nFDCB d CE   SET 1,(IY+d)\nFDCB d CF   SET 1,(IY+d),A*\nFDCB d D0   SET 2,(IY+d),B*\nFDCB d D1   SET 2,(IY+d),C*\nFDCB d D2   SET 2,(IY+d),D*\nFDCB d D3   SET 2,(IY+d),E*\nFDCB d D4   SET 2,(IY+d),H*\nFDCB d D5   SET 2,(IY+d),L*\nFDCB d D6   SET 2,(IY+d)\nFDCB d D7   SET 2,(IY+d),A*\nFDCB d D8   SET 3,(IY+d),B*\nFDCB d D9   SET 3,(IY+d),C*\nFDCB d DA   SET 3,(IY+d),D*\nFDCB d DB   SET 3,(IY+d),E*\nFDCB d DC   SET 3,(IY+d),H*\nFDCB d DD   SET 3,(IY+d),L*\nFDCB d DE   SET 3,(IY+d)\nFDCB d DF   SET 3,(IY+d),A*\nFDCB d E0   SET 4,(IY+d),B*\nFDCB d E1   SET 4,(IY+d),C*\nFDCB d E2   SET 4,(IY+d),D*\nFDCB d E3   SET 4,(IY+d),E*\nFDCB d E4   SET 4,(IY+d),H*\nFDCB d E5   SET 4,(IY+d),L*\nFDCB d E6   SET 4,(IY+d)\nFDCB d E7   SET 4,(IY+d),A*\nFDCB d E8   SET 5,(IY+d),B*\nFDCB d E9   SET 5,(IY+d),C*\nFDCB d EA   SET 5,(IY+d),D*\nFDCB d EB   SET 5,(IY+d),E*\nFDCB d EC   SET 5,(IY+d),H*\nFDCB d ED   SET 5,(IY+d),L*\nFDCB d EE   SET 5,(IY+d)\nFDCB d EF   SET 5,(IY+d),A*\nFDCB d F0   SET 6,(IY+d),B*\nFDCB d F1   SET 6,(IY+d),C*\nFDCB d F2   SET 6,(IY+d),D*\nFDCB d F3   SET 6,(IY+d),E*\nFDCB d F4   SET 6,(IY+d),H*\nFDCB d F5   SET 6,(IY+d),L*\nFDCB d F6   SET 6,(IY+d)\nFDCB d F7   SET 6,(IY+d),A*\nFDCB d F8   SET 7,(IY+d),B*\nFDCB d F9   SET 7,(IY+d),C*\nFDCB d FA   SET 7,(IY+d),D*\nFDCB d FB   SET 7,(IY+d),E*\nFDCB d FC   SET 7,(IY+d),H*\nFDCB d FD   SET 7,(IY+d),L*\nFDCB d FE   SET 7,(IY+d)\nFDCB d FF   SET 7,(IY+d),A*"
  },
  {
    "path": "resources/opcodes-fd-xx.txt",
    "content": "FD09        ADD IY,BC\nFD19        ADD IY,DE\nFD21 n n    LD IY,nn\nFD22 n n    LD (nn),IY\nFD23        INC IY\nFD24        INC IYh*\nFD25        DEC IYh*\nFD26 n      LD IYh,n*\nFD29        ADD IY,IY\nFD2A n n    LD IY,(nn)\nFD2B        DEC IY\nFD2C        INC IYl*\nFD2D        DEC IYl*\nFD2E n      LD IYl,n*\nFD34 d      INC (IY+d)\nFD35 d      DEC (IY+d)\nFD36 d n    LD (IY+d),n\nFD39        ADD IY,SP\nFD44        LD B,IYh*\nFD45        LD B,IYl*\nFD46 d      LD B,(IY+d)\nFD4C        LD C,IYh*\nFD4D        LD C,IYl*\nFD4E d      LD C,(IY+d)\nFD54        LD D,IYh*\nFD55        LD D,IYl*\nFD56 d      LD D,(IY+d)\nFD5C        LD E,IYh*\nFD5D        LD E,IYl*\nFD5E d      LD E,(IY+d)\nFD60        LD IYh,B*\nFD61        LD IYh,C*\nFD62        LD IYh,D*\nFD63        LD IYh,E*\nFD64        LD IYh,IYh*\nFD65        LD IYh,IYl*\nFD66 d      LD H,(IY+d)\nFD67        LD IYh,A*\nFD68        LD IYl,B*\nFD69        LD IYl,C*\nFD6A        LD IYl,D*\nFD6B        LD IYl,E*\nFD6C        LD IYl,IYh*\nFD6D        LD IYl,IYl*\nFD6E d      LD L,(IY+d)\nFD6F        LD IYl,A*\nFD70 d      LD (IY+d),B\nFD71 d      LD (IY+d),C\nFD72 d      LD (IY+d),D\nFD73 d      LD (IY+d),E\nFD74 d      LD (IY+d),H\nFD75 d      LD (IY+d),L\nFD77 d      LD (IY+d),A\nFD7C        LD A,IYh*\nFD7D        LD A,IYl*\nFD7E d      LD A,(IY+d)\nFD84        ADD A,IYh*\nFD85        ADD A,IYl*\nFD86 d      ADD A,(IY+d)\nFD8C        ADC A,IYh*\nFD8D        ADC A,IYl*\nFD8E d      ADC A,(IY+d)\nFD94        SUB IYh*\nFD95        SUB IYl*\nFD96 d      SUB (IY+d)\nFD9C        SBC A,IYh*\nFD9D        SBC A,IYl*\nFD9E d      SBC A,(IY+d)\nFDA4        AND IYh*\nFDA5        AND IYl*\nFDA6 d      AND (IY+d)\nFDAC        XOR IYh*\nFDAD        XOR IYl*\nFDAE d      XOR (IY+d)\nFDB4        OR IYh*\nFDB5        OR IYl*\nFDB6 d      OR (IY+d)\nFDBC        CP IYh*\nFDBD        CP IYl*\nFDBE d      CP (IY+d)\nFDE1        POP IY\nFDE3        EX (SP),IY\nFDE5        PUSH IY\nFDE9        JP (IY)\nFDF9        LD SP,IY"
  },
  {
    "path": "resources/opcodes-xx.txt",
    "content": "00          NOP\n01 n n      LD BC,nn\n02          LD (BC),A\n03          INC BC\n04          INC B\n05          DEC B\n06 n        LD B,n\n07          RLCA\n08          EX AF,AF'\n09          ADD HL,BC\n0A          LD A,(BC)\n0B          DEC BC\n0C          INC C\n0D          DEC C\n0E n        LD C,n\n0F          RRCA\n10 e        DJNZ (PC+e)\n11 n n      LD DE,nn\n12          LD (DE),A\n13          INC DE\n14          INC D\n15          DEC D\n16 n        LD D,n\n17          RLA\n18 e        JR e\n19          ADD HL,DE\n1A          LD A,(DE)\n1B          DEC DE\n1C          INC E\n1D          DEC E\n1E n        LD E,n\n1F          RRA\n20 e        JR NZ,e\n21 n n      LD HL,nn\n22 n n      LD (nn),HL\n23          INC HL\n24          INC H\n25          DEC H\n26 n        LD H,n\n27          DAA\n28 e        JR Z,e\n29          ADD HL,HL\n2A n n      LD HL,(nn)\n2B          DEC HL\n2C          INC L\n2D          DEC L\n2E n        LD L,n\n2F          CPL\n30 e        JR NC,e\n31 n n      LD SP,nn\n32 n n      LD (nn),A\n33          INC SP\n34          INC (HL)\n35          DEC (HL)\n36 n        LD (HL),n\n37          SCF\n38 e        JR C,e\n39          ADD HL,SP\n3A n n      LD A,(nn)\n3B          DEC SP\n3C          INC A\n3D          DEC A\n3E n        LD A,n\n3F          CCF\n40          LD B,B\n41          LD B,C\n42          LD B,D\n43          LD B,E\n44          LD B,H\n45          LD B,L\n46          LD B,(HL)\n47          LD B,A\n48          LD C,B\n49          LD C,C\n4A          LD C,D\n4B          LD C,E\n4C          LD C,H\n4D          LD C,L\n4E          LD C,(HL)\n4F          LD C,A\n50          LD D,B\n51          LD D,C\n52          LD D,D\n53          LD D,E\n54          LD D,H\n55          LD D,L\n56          LD D,(HL)\n57          LD D,A\n58          LD E,B\n59          LD E,C\n5A          LD E,D\n5B          LD E,E\n5C          LD E,H\n5D          LD E,L\n5E          LD E,(HL)\n5F          LD E,A\n60          LD H,B\n61          LD H,C\n62          LD H,D\n63          LD H,E\n64          LD H,H\n65          LD H,L\n66          LD H,(HL)\n67          LD H,A\n68          LD L,B\n69          LD L,C\n6A          LD L,D\n6B          LD L,E\n6C          LD L,H\n6D          LD L,L\n6E          LD L,(HL)\n6F          LD L,A\n70          LD (HL),B\n71          LD (HL),C\n72          LD (HL),D\n73          LD (HL),E\n74          LD (HL),H\n75          LD (HL),L\n76          HALT\n77          LD (HL),A\n78          LD A,B\n79          LD A,C\n7A          LD A,D\n7B          LD A,E\n7C          LD A,H\n7D          LD A,L\n7E          LD A,(HL)\n7F          LD A,A\n80          ADD A,B\n81          ADD A,C\n82          ADD A,D\n83          ADD A,E\n84          ADD A,H\n85          ADD A,L\n86          ADD A,(HL)\n87          ADD A,A\n88          ADC A,B\n89          ADC A,C\n8A          ADC A,D\n8B          ADC A,E\n8C          ADC A,H\n8D          ADC A,L\n8E          ADC A,(HL)\n8F          ADC A,A\n90          SUB B\n91          SUB C\n92          SUB D\n93          SUB E\n94          SUB H\n95          SUB L\n96          SUB (HL)\n97          SUB A\n98          SBC A,B\n99          SBC A,C\n9A          SBC A,D\n9B          SBC A,E\n9C          SBC A,H\n9D          SBC A,L\n9E          SBC A,(HL)\n9F          SBC A,A\nA0          AND B\nA1          AND C\nA2          AND D\nA3          AND E\nA4          AND H\nA5          AND L\nA6          AND (HL)\nA7          AND A\nA8          XOR B\nA9          XOR C\nAA          XOR D\nAB          XOR E\nAC          XOR H\nAD          XOR L\nAE          XOR (HL)\nAF          XOR A\nB0          OR B\nB1          OR C\nB2          OR D\nB3          OR E\nB4          OR H\nB5          OR L\nB6          OR (HL)\nB7          OR A\nB8          CP B\nB9          CP C\nBA          CP D\nBB          CP E\nBC          CP H\nBD          CP L\nBE          CP (HL)\nBF          CP A\nC0          RET NZ\nC1          POP BC\nC2 n n      JP NZ,nn\nC3 n n      JP nn\nC4 n n      CALL NZ,nn\nC5          PUSH BC\nC6 n        ADD A,n\nC7          RST 0H\nC8          RET Z\nC9          RET\nCA n n      JP Z,nn\nCB          CB\nCC n n      CALL Z,nn\nCD n n      CALL nn\nCE n        ADC A,n\nCF          RST 8H\nD0          RET NC\nD1          POP DE\nD2 n n      JP NC,nn\nD3 n        OUT (n),A\nD4 n n      CALL NC,nn\nD5          PUSH DE\nD6 n        SUB n\nD7          RST 10H\nD8          RET C\nD9          EXX\nDA n n      JP C,nn\nDB n        IN A,(n)\nDC n n      CALL C,nn\nDD          DD\nDE n        SBC A,n\nDF          RST 18H\nE0          RET PO\nE1          POP HL\nE2 n n      JP PO,nn\nE3          EX (SP),HL\nE4 n n      CALL PO,nn\nE5          PUSH HL\nE6 n        AND n\nE7          RST 20H\nE8          RET PE\nE9          JP (HL)\nEA n n      JP PE,nn\nEB          EX DE,HL\nEC n n      CALL PE,nn\nED          ED\nEE n        XOR n\nEF          RST 28H\nF0          RET P\nF1          POP AF\nF2 n n      JP P,nn\nF3          DI\nF4 n n      CALL P,nn\nF5          PUSH AF\nF6 n        OR n\nF7          RST 30H\nF8          RET M\nF9          LD SP,HL\nFA n n      JP M,nn\nFB          EI\nFC n n      CALL M,nn\nFD          FD\nFE n        CP n\nFF          RST 38H"
  },
  {
    "path": "resources/process-pla.py",
    "content": "#!/usr/bin/env python3\n#\n# This script reads the original Z80 PLA table and processes it to get the list of PLA\n# entries in the form suitable to load into the PLA checker program.\n#\n# Format of the output PLA table:\n# 7 bits of modifiers:\n#  loc 0  If \"1\", IX or IY flag is reset        |\\\n#      1  If \"1\", IX or IY flag is set          | Only 1 of these 2 can be set\n#      2  If \"1\", in HALT state\n#      3  If \"1\", ALU operation\n#      4  If \"1\", XX regular instruction        |\\\n#      5  If \"1\", CB instruction table modifier | Only 1 of these 3 can be set\n#      6  If \"1\", ED instruction table modifier |/\n#\n#  Following 16 bits of opcode test in pairs, from bit7 to bit0\n#    For each pair, if the left bit is \"1\", the opcode bit has to be 0\n#                   if the right bit is \"1\", the opcode bit has to be 1\n#                   otherwise the bit is ignored\n#\n#-------------------------------------------------------------------------------\n#  Copyright (C) 2014  Goran Devic\n#\n#  This program is free software; you can redistribute it and/or modify it\n#  under the terms of the GNU General Public License as published by the Free\n#  Software Foundation; either version 2 of the License, or (at your option)\n#  any later version.\n#\n#  This program is distributed in the hope that it will be useful, but WITHOUT\n#  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n#  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n#  more details.\n#-------------------------------------------------------------------------------\nimport string\nimport os\n\n# Input PLA table: a text file representing the original (Z80 reverse-engineered)\n# table at http://arcfn.com/files/z80-pla-table.html\ninFile = \"z80-pla-original.txt\"\n\n# Output processed PLA table\noutFile = \"z80-pla.txt\"\n\ntable = []\n\ndef xtostr ( condition ):\n    if condition:\n        return \"1\"\n    return \".\"\n\n# Read the content of the input PLA table and add all valid lines (starting with a number)\nwith open(inFile, 'r') as fIn:\n    for line in fIn:\n        seg = line.split()\n        if len(seg)>1 and seg[0].isdigit():\n            table.append(line)\n\n# In the original PLA table, entries are listed in reverse order -\ntable.reverse()\n\n# Control ID to detect errors\ncontrolID = 0\n\nwith open(outFile, 'w') as fOut:\n    fOut.write(\"# Automatically generated by process-pla.py\\n\")\n    pla = []\n    for entry in table:\n        # This is an example of an input PLA entry containing different segments:\n        # ID   ALU  XX  CB  ED  0  /0   1  /1   2  /2   6  /6   7  /7   3  /3   4  /4   5  /5   Instruction Ex  Description\n        # 59    1   1   .   .   .   .   .   .   .   .   .   1   1   .   1   .   .   1   .   1   01110xxx    ce  ld (hl),r (and hlt)\n        # 0     1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17  18  19  20   21          22  23\n        seg = entry.split()\n        if len(seg)>22:\n            # Sanity check\n            if controlID!=int(seg[0]):\n                fOut.write(\"Unexpected entry \" + seg[0])\n                exit(-1)\n            controlID = controlID + 1\n\n            # Decipher [22] into actual PLA entry lines IXY0, IXY1 and HALT (a, b, c)\n            entry = \"\"\n            entry += xtostr(\"a\" in seg[22])\n            entry += xtostr(\"b\" in seg[22])\n            entry += xtostr(\"c\" in seg[22])\n            # Append the rest of the PLA modifiers: ALU, XX, CB and ED\n            entry += seg[1] + seg[2] + seg[3] + seg[4] + ' '\n            # Add the instruction decoder bit7 through bit0 in that order\n            #         7      /7        6      /6        5      /5       4       /4        3      /3        2     /2        1     /1       0     /0\n            entry += seg[13]+seg[14] +seg[11]+seg[12] +seg[19]+seg[20] +seg[17]+seg[18] +seg[15]+seg[16] +seg[9]+seg[10] +seg[7]+seg[8] +seg[5]+seg[6]\n\n            # Check if the new PLA entry is a duplicate (already stored to PLA)\n            # Append \"D\" for duplicate entries so they can be skipped easily\n            if entry in pla:\n                fOut.write(entry + \"\\tD\\t\")\n            else:\n            # Store the new PLA line in the PLA list and write it out\n                pla.append(entry)\n                fOut.write(entry + \"\\t-\\t\")\n\n            # Write the ID number, text decode and description\n            fOut.write(seg[0] + \"\\t\" + seg[21] + \"\\t\" + ' '.join(seg[23:len(seg)]) +  \"\\n\")\n\n    # The original PLA table passes individual opcode bits that are needed to decode many\n    # instructions but it does not contain concrete single-bit entries\n    # We append those bits to the end of our PLA table\n    fOut.write(\"....... ...............1\\t-\\t99\\txxxxxxx1\\topcode[0]\\n\")\n    fOut.write(\"....... .............1..\\t-\\t100\\txxxxxx1x\\topcode[1]\\n\")\n    fOut.write(\"....... ...........1....\\t-\\t101\\txxxxx1xx\\topcode[2]\\n\")\n    fOut.write(\"....... .........1......\\t-\\t102\\txxxx1xxx\\topcode[3]\\n\")\n    fOut.write(\"....... .......1........\\t-\\t103\\txxx1xxxx\\topcode[4]\\n\")\n    fOut.write(\"....... .....1..........\\t-\\t104\\txx1xxxxx\\topcode[5]\\n\")\n"
  },
  {
    "path": "resources/title-custom-medium.bsf",
    "content": "/*\n* Custom title schematic defintion file\n*\n* To install and use, copy this file to:\n* <install>/quartus/libraries/primitives/other\n*\n* The frame has a 3D look. To revert to 2D, change \"0\" into \"1\" in initial \"rect\" sections.\n*/\n(header \"symbol\" (version \"1.2\"))\n(title_block\n\t(rect 64 64 385 125)\n\t(name \"title-custom-medium\")\n\t(section (rect 0   0  320 20)(text \"PROJECT\" (rect 2 0 30 12)(font \"Arial\" ))(text \"(project)\" (rect 56 2 185 20)(font \"Arial\" (font_size 12)(bold)))(border))\n\t(section (rect 130 0  320 20)(text \"MODULE\" (rect 2 1 25 13)(font \"Arial\" ))(text \"(module)\" (rect 43 2 53 17)(font \"Arial\" (font_size 12)(bold)))(border))\n\t(section (rect 0   21 320 40)(text \"DESIGNER\" (rect 2 0 59 12)(font \"Arial\" ))(text \"Goran Devic\" (rect 56 2 165 20)(font \"Arial\" (font_size 11)))(border))\n\t(section (rect 0   41 240 60)(text \"DATE\" (rect 2 0 30 12)(font \"Arial\" ))(text \"(date)\" (rect 56 3 225 19)(font \"Arial\" (font_size 10)))(border))\n\t(section (rect 241 41 320 60)(text \"REV\" (rect 2 1 25 13)(font \"Arial\" ))(text \"1.0\" (rect 43 3 53 17)(font \"Arial\" (font_size 10)))(border))\n\t(drawing\n\t)\n)\n"
  },
  {
    "path": "resources/title-custom-small.bsf",
    "content": "/*\n* Custom title schematic defintion file\n*\n* To install and use, copy this file to:\n* <install>/quartus/libraries/primitives/other\n*\n* The frame has a 3D look. To revert to 2D, change \"0\" into \"1\" in initial \"rect\" sections.\n*/\n(header \"symbol\" (version \"1.2\"))\n(title_block\n\t(rect 64 64 321 116)\n\t(name \"title-custom-small\")\n\t(section (rect 0   0  256 17)(text \"PROJECT\" (rect 2 0 30 12)(font \"Arial\" ))(text \"(project)\" (rect 56 2 185 20)(font \"Arial\" (font_size 9)(bold)))(border))\n\t(section (rect 104 0  256 17)(text \"MODULE\" (rect 2 1 25 13)(font \"Arial\" ))(text \"(module)\" (rect 43 2 53 17)(font \"Arial\" (font_size 9)(bold)))(border))\n\t(section (rect 0   18 256 34)(text \"DESIGNER\" (rect 2 0 59 12)(font \"Arial\" ))(text \"Goran Devic\" (rect 56 2 165 20)(font \"Arial\" (font_size 9)))(border))\n\t(section (rect 0   35 256 51)(text \"DATE\" (rect 2 0 30 12)(font \"Arial\" ))(text \"(date)\" (rect 56 3 225 19)(font \"Arial\" (font_size 8)))(border))\n\t(section (rect 192 35 256 51)(text \"REV\" (rect 2 1 25 13)(font \"Arial\" ))(text \"1.0\" (rect 43 3 53 17)(font \"Arial\" (font_size 8)))(border))\n\t(drawing\n\t)\n)\n"
  },
  {
    "path": "resources/z80-pla-original.txt",
    "content": "Source: http://arcfn.com/files/z80-pla-table.html\n98\t.\t1\t.\t.\t.\t1\t.\t1\t1\t.\t.\t1\t.\t1\t.\t.\t.\t1\t1\t.\t1101x011\te\tout (*),a/in a,(*)\n97\t.\t1\t.\t.\t.\t1\t.\t1\t1\t.\t.\t1\t.\t1\t.\t.\t.\t1\t.\t1\t1111x011\te\tdi/ei\n96\t.\t.\t.\t1\t1\t.\t.\t1\t.\t1\t.\t1\t1\t.\t.\t.\t.\t.\t.\t.\t01xxx110\tg\tim n\n95\t.\t1\t.\t.\t1\t.\t.\t1\t.\t1\t.\t1\t1\t.\t1\t.\t.\t1\t.\t1\t01110110\te\thalt\nGND\n94\t.\t.\t.\t1\t1\t.\t1\t.\t1\t.\t1\t.\t.\t1\t.\t.\t.\t.\t.\t1\t101xx000\tg\tldi/ldir/ldd/lddr\n93\t.\t.\t.\t1\t.\t1\t1\t.\t1\t.\t1\t.\t.\t1\t.\t.\t.\t.\t.\t1\t101xx001\tg\tcpi/cpir/cpd/cpdr\n92\t.\t1\t.\t.\t.\t1\t.\t1\t.\t1\t1\t.\t1\t.\t1\t.\t.\t1\t.\t1\t00110111\te\tscf\n91\t.\t.\t.\t1\t.\t.\t.\t1\t1\t.\t1\t.\t.\t1\t.\t.\t.\t.\t.\t1\t101xx01x\tg\tinx/outx/inxr/otxr\n90\t.\t1\t.\t.\t1\t.\t1\t.\t1\t.\t1\t.\t1\t.\t1\t.\t.\t1\t1\t.\t00010000\te\tdjnz *\n89\t.\t1\t.\t.\t.\t1\t.\t1\t.\t1\t1\t.\t1\t.\t.\t1\t.\t1\t.\t1\t00111111\te\tccf\n88\t1\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t1\t1\t.\t.\t1\txx101xxx\td\t101 (XOR)\n87\t.\t.\t.\t1\t.\t1\t.\t1\t.\t1\t.\t1\t1\t.\t.\t.\t.\t1\t1\t.\t0101x111\tg\tld a,i / ld a,r\nGND\n86\t1\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t1\t.\t.\t1\t.\t1\txx110xxx\td\t110 (OR)\n85\t1\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t1\t.\t1\t.\t.\t1\txx100xxx\td\t100 (AND)\n--- bit 3\n84\t1\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t1\t.\t1\t.\t1\t.\txx000xxx\td\t000 (ADD)\n83\t.\t.\t.\t1\t.\t1\t.\t1\t.\t1\t.\t1\t1\t.\t.\t.\t.\t1\t1\t.\t0101x111\tg\tld a,i/a,r\n82\t.\t.\t.\t1\t1\t.\t1\t.\t.\t1\t.\t1\t1\t.\t.\t.\t.\t.\t.\t.\t01xxx100\tg\tneg\n81\t.\t1\t.\t.\t.\t1\t.\t1\t.\t1\t1\t.\t1\t.\t.\t1\t1\t.\t.\t1\t00101111\te\tcpl\n80\t1\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t1\t1\t.\t1\t.\txx001xxx\td\t001 (ADC)\nGND\n79\t1\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t1\t.\t1\t1\t.\txx011xxx\td\t011 (SBC)\n78\t1\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t1\t.\t.\t1\t1\t.\txx010xxx\td\t010 (SUB)\n--- bit 4\n77\t.\t1\t.\t.\t.\t1\t.\t1\t.\t1\t1\t.\t1\t.\t1\t.\t1\t.\t.\t1\t00100111\te\tdaa\n76\t1\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t1\t.\t1\t.\t1\txx111xxx\td\t111 (CP)\n75\t.\t1\t.\t.\t.\t1\t1\t.\t.\t1\t1\t.\t1\t.\t.\t.\t.\t.\t.\t.\t00xxx101\te\tdec r\n74\t.\t.\t1\t.\t.\t.\t.\t.\t.\t.\t.\t1\t.\t1\t.\t.\t.\t.\t.\t.\t11xxxxxx\tf\tset b,r\n73\t.\t.\t1\t.\t.\t.\t.\t.\t.\t.\t1\t.\t.\t1\t.\t.\t.\t.\t.\t.\t10xxxxxx\tf\tres b,r\n72\t.\t.\t1\t.\t.\t.\t.\t.\t.\t.\t.\t1\t1\t.\t.\t.\t.\t.\t.\t.\t01xxxxxx\tf\tbit b,r\nGND\n71\t.\t1\t.\t.\t.\t1\t.\t1\t.\t1\t1\t.\t1\t.\t.\t.\t.\t.\t1\t.\t000xx111\te\trlca/rla/rrca/rra\n70\t.\t.\t1\t.\t.\t.\t.\t.\t.\t.\t1\t.\t1\t.\t.\t.\t.\t.\t.\t.\t00xxxxxx\tf\trlc r\n69\t.\t1\t.\t.\t.\t1\t1\t.\t1\t.\t1\t.\t1\t.\t.\t1\t.\t.\t.\t.\t00xx1001\te\tadd hl,rr\n68\t.\t.\t.\t1\t1\t.\t.\t1\t1\t.\t.\t1\t1\t.\t.\t.\t.\t.\t.\t.\t01xxx010\tg\tadc/sbc hl,rr\n67\t.\t.\t.\t1\t1\t.\t1\t.\t1\t.\t.\t1\t1\t.\t.\t.\t.\t.\t.\t.\t01xxx000\tg\tin\n66\t.\t1\t.\t.\t.\t.\t1\t.\t.\t1\t1\t.\t1\t.\t.\t.\t.\t.\t.\t.\t00xxx10x\te\tinc/dec r\n65\t.\t1\t.\t.\t.\t.\t.\t.\t.\t.\t1\t.\t.\t1\t.\t.\t.\t.\t.\t.\t10xxxxxx\te\tadd/sub/and/or/xor/cmp a,r\n64\t.\t1\t.\t.\t1\t.\t.\t1\t.\t1\t.\t1\t.\t1\t.\t.\t.\t.\t.\t.\t11xxx110\te\tadd/sub/and/or/xor/cmp a,imm\n---\nGND\n63\t.\t1\t.\t.\t1\t.\t.\t1\t.\t1\t1\t.\t1\t.\t.\t.\t.\t.\t.\t.\t00xxx110\te\tld r,*\n62\t.\t.\t1\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\txxxxxxxx\tf\tFor all CB opcodes\n---\n61\t.\t1\t.\t.\t.\t.\t.\t.\t.\t.\t.\t1\t1\t.\t.\t.\t.\t.\t.\t.\t01xxxxxx\te\tld r,r'\n60\t.\t.\t.\t1\t.\t1\t.\t1\t.\t1\t.\t1\t1\t.\t.\t.\t1\t.\t.\t1\t0110x111\tg\trrd/rld\n---\n---\n---\nGND\n59\t.\t1\t.\t.\t.\t.\t.\t.\t.\t.\t.\t1\t1\t.\t1\t.\t.\t1\t.\t1\t01110xxx\tce\tld (hl),r\n58\t.\t1\t.\t.\t1\t.\t.\t1\t.\t1\t.\t1\t1\t.\t.\t.\t.\t.\t.\t.\t01xxx110\tce\tld r,(hl)\n---\n57\t.\t.\t.\t1\t.\t1\t.\t1\t.\t1\t.\t1\t1\t.\t.\t.\t1\t.\t1\t.\t0100x111\tg\tld i,a/r,a\n56\t.\t1\t.\t.\t.\t1\t.\t1\t.\t1\t.\t1\t.\t1\t.\t.\t.\t.\t.\t.\t11xxx111\te\trst p\n55\t.\t.\t1\t.\t1\t.\t.\t1\t.\t1\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\txxxxx110\tf\tEvery CB op (hl)\n54\t.\t.\t1\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\t.\txxxxxxxx\tbf\tEvery CB with IX/IY\n--- bit /0\n53\t.\t1\t.\t.\t.\t.\t1\t.\t.\t1\t1\t.\t1\t.\t1\t.\t.\t1\t.\t1\t0011010x\te\tinc/dec (hl)\nGND\n52\t.\t1\t.\t.\t1\t.\t.\t1\t.\t1\t1\t.\t.\t1\t.\t.\t.\t.\t.\t.\t10xxx110\te\tadd/sub/and/or/xor/cp (hl)\n--- bit 4\n51\t.\t1\t.\t.\t.\t1\t1\t.\t.\t1\t.\t1\t.\t1\t.\t1\t1\t.\t.\t1\t11101101\te\tED prefix\n--- bit /1\n--- bit /2\n50\t.\t1\t.\t.\t1\t.\t.\t1\t.\t1\t1\t.\t1\t.\t1\t.\t.\t1\t.\t1\t00110110\te\tld (hl),n\n49\t.\t.\t.\t.\t.\t1\t.\t1\t1\t.\t.\t1\t.\t1\t.\t1\t1\t.\t1\t.\t11001011\tb\tCB prefix with IX/IY\n48\t.\t1\t.\t.\t1\t.\t1\t.\t1\t.\t1\t.\t1\t.\t.\t.\t.\t.\t.\t1\t001xx000\te\tjr ss,e\nGND\n47\t.\t1\t.\t.\t1\t.\t1\t.\t1\t.\t1\t.\t1\t.\t.\t1\t.\t1\t1\t.\t00011000\te\tjr e\n46\t.\t.\t.\t1\t.\t1\t1\t.\t.\t1\t.\t1\t1\t.\t.\t.\t.\t.\t.\t.\t01xxx101\tg\treti/retn\n45\t.\t1\t.\t.\t1\t.\t1\t.\t1\t.\t.\t1\t.\t1\t.\t.\t.\t.\t.\t.\t11xxx000\te\tret cc\n44\t.\t1\t.\t.\t.\t1\t.\t1\t1\t.\t.\t1\t.\t1\t.\t1\t1\t.\t1\t.\t11001011\te\tCB prefix\n43\t.\t1\t.\t.\t1\t.\t.\t1\t1\t.\t.\t1\t.\t1\t.\t.\t.\t.\t.\t.\t11xxx010\te\tjp cc,nn\n42\t.\t1\t.\t.\t1\t.\t1\t.\t.\t1\t.\t1\t.\t1\t.\t.\t.\t.\t.\t.\t11xxx100\te\tcall cc,nn\n41\t.\t1\t.\t.\t.\t1\t1\t.\t.\t1\t.\t1\t.\t1\t.\t1\t.\t1\t.\t.\t11x11101\te\tIX/IY\n40\t.\t1\t.\t.\t1\t.\t.\t1\t.\t1\t1\t.\t1\t.\t1\t.\t.\t1\t.\t1\t00110110\tbe\tld (ix+d),n\nGND\n39\t.\t1\t.\t.\t1\t.\t1\t.\t1\t.\t1\t.\t1\t.\t.\t1\t1\t.\t1\t.\t00001000\te\tex af,af'\n38\t.\t1\t.\t.\t1\t.\t.\t1\t1\t.\t1\t.\t1\t.\t.\t.\t.\t1\t.\t1\t0011x010\te\tld (nn),a/a,(nn)\n37\t.\t1\t.\t.\t.\t1\t.\t1\t1\t.\t.\t1\t.\t1\t.\t.\t.\t1\t1\t.\t1101x011\te\tout (n),a/a,(n)\n36\t.\t1\t.\t.\t1\t.\t.\t1\t1\t.\t1\t.\t1\t.\t.\t.\t.\t.\t1\t.\t000xx010\te\tld(rr),a/a,(rr)\n35\t.\t1\t.\t.\t.\t1\t1\t.\t1\t.\t.\t1\t.\t1\t.\t1\t1\t.\t1\t.\t11001001\te\tret\n34\t.\t.\t.\t1\t.\t1\t1\t.\t1\t.\t.\t1\t1\t.\t.\t.\t.\t.\t.\t.\t01xxx001\tg\tout (c),r\n33\t.\t.\t.\t1\t.\t1\t.\t1\t1\t.\t.\t1\t1\t.\t1\t.\t.\t.\t.\t.\t01xx0011\tg\tld direction\n32\t.\t.\t.\t1\t.\t1\t.\t1\t.\t1\t.\t1\t1\t.\t.\t.\t.\t.\t1\t.\t010xx111\tg\tld i,a/a,i/r,a/a,r\nGND\n---\n31\t.\t.\t.\t1\t.\t1\t.\t1\t1\t.\t.\t1\t1\t.\t.\t.\t.\t.\t.\t.\t01xxx011\tg\tld rr,(nn)/(nn),rr\n30\t.\t1\t.\t.\t1\t.\t.\t1\t1\t.\t1\t.\t1\t.\t.\t.\t1\t.\t.\t1\t0010x010\te\tld hl,(nn)/(nn),hl\n29\t.\t1\t.\t.\t.\t1\t.\t1\t1\t.\t.\t1\t.\t1\t1\t.\t1\t.\t1\t.\t11000011\te\tjp nn\n28\t.\t1\t.\t.\t.\t1\t.\t1\t1\t.\t.\t1\t.\t1\t1\t.\t.\t1\t1\t.\t11010011\te\tout (n),a\n--- bit 3\n27\t.\t.\t.\t1\t.\t.\t1\t.\t1\t.\t.\t1\t1\t.\t.\t.\t.\t.\t.\t.\t01xxx00x\tg\tin/out r,(c)\n26\t.\t1\t.\t.\t1\t.\t1\t.\t1\t.\t1\t.\t1\t.\t1\t.\t.\t1\t1\t.\t00010000\te\tdjnz e\nGND\n25\t.\t1\t.\t.\t.\t1\t.\t1\t.\t1\t1\t.\t1\t.\t.\t.\t.\t.\t1\t.\t000xx111\te\trlca/rla/rrca/rra\n24\t.\t1\t.\t.\t.\t1\t1\t.\t.\t1\t.\t1\t.\t1\t.\t1\t1\t.\t1\t.\t11001101\te\tcall nn\n---\n23\t.\t1\t.\t.\t.\t1\t1\t.\t.\t.\t.\t1\t.\t1\t1\t.\t.\t.\t.\t.\t11xx0x01\te\tpush/pop\n---\n22\t.\t.\t.\t.\t.\t1\t.\t1\t1\t.\t.\t1\t.\t1\t.\t1\t1\t.\t1\t.\t11001011\ta\tCB prefix w/o IX/IY\n21\t.\t.\t.\t1\t1\t.\t.\t1\t1\t.\t1\t.\t.\t1\t.\t.\t.\t.\t.\t1\t101xx010\tg\tinx/inxr\nGND\n20\t.\t.\t.\t1\t.\t1\t.\t1\t1\t.\t1\t.\t.\t1\t.\t.\t.\t.\t.\t1\t101xx011\tg\toutx/otxr\n---\n19\t.\t.\t.\t1\t.\t1\t1\t.\t1\t.\t1\t.\t.\t1\t.\t.\t.\t.\t.\t1\t101xx001\tg\tcpi/cpir/cpd/cpdr\n18\t.\t.\t.\t1\t1\t.\t1\t.\t1\t.\t1\t.\t.\t1\t.\t.\t.\t.\t.\t1\t101xx000\tg\tldi/ldir/ldd/lddr\n17\t.\t1\t.\t.\t1\t.\t.\t1\t.\t1\t1\t.\t1\t.\t.\t.\t.\t.\t.\t.\t00xxx110\te\tld r,n\nGND\n16\t.\t1\t.\t.\t.\t1\t1\t.\t.\t1\t.\t1\t.\t1\t1\t.\t.\t.\t.\t.\t11xx0101\te\tpush rr\n15\t.\t.\t.\t1\t.\t1\t.\t1\t.\t1\t.\t1\t1\t.\t.\t.\t1\t.\t.\t1\t0110x111\tg\trrd/rld\n---\n14\t.\t1\t.\t.\t.\t1\t.\t1\t1\t.\t1\t.\t1\t.\t.\t1\t.\t.\t.\t.\t00xx1011\te\tdec rr\n13\t.\t1\t.\t.\t1\t.\t.\t1\t1\t.\t1\t.\t1\t.\t1\t.\t.\t.\t.\t.\t00xx0010\te\tld direction\n12\t.\t.\t.\t1\t1\t.\t1\t.\t1\t.\t1\t.\t.\t1\t.\t.\t.\t.\t.\t1\t101xx000\tg\tldi/ldir/ldd/lddr\n11\t.\t.\t.\t1\t.\t1\t1\t.\t1\t.\t1\t.\t.\t1\t.\t.\t.\t.\t.\t1\t101xx001\tg\tcpi/cpir/cpd/cpdr\n10\t.\t1\t.\t.\t.\t1\t.\t1\t1\t.\t.\t1\t.\t1\t1\t.\t1\t.\t.\t1\t11100011\te\tex (sp),hl\nGND\n9\t.\t1\t.\t.\t.\t1\t.\t1\t1\t.\t1\t.\t1\t.\t.\t.\t.\t.\t.\t.\t00xxx011\te\tinc/dec rr\n8\t.\t1\t.\t.\t1\t.\t.\t1\t1\t.\t1\t.\t1\t.\t.\t.\t.\t.\t1\t.\t000xx010\te\tld (rr),a/a,(rr)\n7\t.\t1\t.\t.\t.\t1\t1\t.\t1\t.\t1\t.\t1\t.\t1\t.\t.\t.\t.\t.\t00xx0001\te\tld rr,nn\n6\t.\t1\t.\t.\t.\t1\t1\t.\t1\t.\t.\t1\t.\t1\t.\t1\t1\t.\t.\t1\t11101001\te\tjp hl\n5\t.\t1\t.\t.\t.\t1\t1\t.\t1\t.\t.\t1\t.\t1\t.\t1\t.\t1\t.\t1\t11111001\te\tld sp,hl\n4\t.\t.\t.\t1\t.\t1\t.\t1\t.\t1\t.\t1\t1\t.\t.\t.\t.\t.\t1\t.\t010xx111\tg\tld x,a/a,x\nGND\n3\t.\t1\t.\t.\t.\t1\t1\t.\t.\t1\t.\t1\t.\t1\t.\t1\t.\t1\t.\t.\t11x11101\te\tIX/IY prefix\n2\t.\t1\t.\t.\t.\t1\t.\t1\t1\t.\t.\t1\t.\t1\t.\t1\t1\t.\t.\t1\t11101011\te\tex de,hl\n1\t.\t1\t.\t.\t.\t1\t1\t.\t1\t.\t.\t1\t.\t1\t.\t1\t.\t1\t1\t.\t11011001\te\texx\n0\t.\t.\t.\t1\t.\t.\t.\t.\t1\t.\t1\t.\t.\t1\t.\t.\t1\t.\t.\t1\t1010x0xx\tg\tldx/cpx/inx/outx brk\n"
  },
  {
    "path": "resources/z80-pla.txt",
    "content": "# Automatically generated by process-pla.py\n......1 .11..11...1.....\t-\t0\t1010x0xx\tldx/cpx/inx/outx brk\n....1.. .1.11..1.11.1..1\t-\t1\t11011001\texx\n....1.. .1.1.11..11..1.1\t-\t2\t11101011\tex de,hl\n....1.. .1.1...1.1.11..1\t-\t3\t11x11101\tIX/IY prefix\n......1 1..11......1.1.1\t-\t4\t010xx111\tld x,a/a,x\n....1.. .1.1.1.1.11.1..1\t-\t5\t11111001\tld sp,hl\n....1.. .1.1.11..11.1..1\t-\t6\t11101001\tjp hl\n....1.. 1.1.....1.1.1..1\t-\t7\t00xx0001\tld rr,nn\n....1.. 1.1.1.....1..11.\t-\t8\t000xx010\tld (rr),a/a,(rr)\n....1.. 1.1.......1..1.1\t-\t9\t00xxx011\tinc/dec rr\n....1.. .1.1.11.1.1..1.1\t-\t10\t11100011\tex (sp),hl\n......1 .11..1....1.1..1\t-\t11\t101xx001\tcpi/cpir/cpd/cpdr\n......1 .11..1....1.1.1.\t-\t12\t101xx000\tldi/ldir/ldd/lddr\n....1.. 1.1.....1.1..11.\t-\t13\t00xx0010\tld direction\n....1.. 1.1......11..1.1\t-\t14\t00xx1011\tdec rr\n......1 1..1.11....1.1.1\t-\t15\t0110x111\trrd/rld\n....1.. .1.1....1..11..1\t-\t16\t11xx0101\tpush rr\n....1.. 1.1........1.11.\t-\t17\t00xxx110\tld r,n\n......1 .11..1....1.1.1.\tD\t18\t101xx000\tldi/ldir/ldd/lddr\n......1 .11..1....1.1..1\tD\t19\t101xx001\tcpi/cpir/cpd/cpdr\n......1 .11..1....1..1.1\t-\t20\t101xx011\toutx/otxr\n......1 .11..1....1..11.\t-\t21\t101xx010\tinx/inxr\n1...... .1.11.1..11..1.1\t-\t22\t11001011\tCB prefix w/o IX/IY\n....1.. .1.1....1...1..1\t-\t23\t11xx0x01\tpush/pop\n....1.. .1.11.1..1.11..1\t-\t24\t11001101\tcall nn\n....1.. 1.1.1......1.1.1\t-\t25\t000xx111\trlca/rla/rrca/rra\n....1.. 1.1.1..11.1.1.1.\t-\t26\t00010000\tdjnz e\n......1 1..1......1.1...\t-\t27\t01xxx00x\tin/out r,(c)\n....1.. .1.11..11.1..1.1\t-\t28\t11010011\tout (n),a\n....1.. .1.11.1.1.1..1.1\t-\t29\t11000011\tjp nn\n....1.. 1.1..11...1..11.\t-\t30\t0010x010\tld hl,(nn)/(nn),hl\n......1 1..1......1..1.1\t-\t31\t01xxx011\tld rr,(nn)/(nn),rr\n......1 1..11......1.1.1\tD\t32\t010xx111\tld i,a/a,i/r,a/a,r\n......1 1..1....1.1..1.1\t-\t33\t01xx0011\tld direction\n......1 1..1......1.1..1\t-\t34\t01xxx001\tout (c),r\n....1.. .1.11.1..11.1..1\t-\t35\t11001001\tret\n....1.. 1.1.1.....1..11.\tD\t36\t000xx010\tld(rr),a/a,(rr)\n....1.. .1.11..1..1..1.1\t-\t37\t1101x011\tout (n),a/a,(n)\n....1.. 1.1..1.1..1..11.\t-\t38\t0011x010\tld (nn),a/a,(nn)\n....1.. 1.1.1.1..11.1.1.\t-\t39\t00001000\tex af,af'\n.1..1.. 1.1..1.11..1.11.\t-\t40\t00110110\tld (ix+d),n\n....1.. .1.1...1.1.11..1\tD\t41\t11x11101\tIX/IY\n....1.. .1.1.......11.1.\t-\t42\t11xxx100\tcall cc,nn\n....1.. .1.1......1..11.\t-\t43\t11xxx010\tjp cc,nn\n....1.. .1.11.1..11..1.1\t-\t44\t11001011\tCB prefix\n....1.. .1.1......1.1.1.\t-\t45\t11xxx000\tret cc\n......1 1..1.......11..1\t-\t46\t01xxx101\treti/retn\n....1.. 1.1.1..1.11.1.1.\t-\t47\t00011000\tjr e\n....1.. 1.1..1....1.1.1.\t-\t48\t001xx000\tjr ss,e\n.1..... .1.11.1..11..1.1\t-\t49\t11001011\tCB prefix with IX/IY\n....1.. 1.1..1.11..1.11.\t-\t50\t00110110\tld (hl),n\n....1.. .1.1.11..1.11..1\t-\t51\t11101101\tED prefix\n....1.. .11........1.11.\t-\t52\t10xxx110\tadd/sub/and/or/xor/cp (hl)\n....1.. 1.1..1.11..11...\t-\t53\t0011010x\tinc/dec (hl)\n.1...1. ................\t-\t54\txxxxxxxx\tEvery CB with IX/IY\n.....1. ...........1.11.\t-\t55\txxxxx110\tEvery CB op (hl)\n....1.. .1.1.......1.1.1\t-\t56\t11xxx111\trst p\n......1 1..11.1....1.1.1\t-\t57\t0100x111\tld i,a/r,a\n..1.1.. 1..1.......1.11.\t-\t58\t01xxx110\tld r,(hl)\n..1.1.. 1..1.1.11.......\t-\t59\t01110xxx\tld (hl),r\n......1 1..1.11....1.1.1\tD\t60\t0110x111\trrd/rld\n....1.. 1..1............\t-\t61\t01xxxxxx\tld r,r'\n.....1. ................\t-\t62\txxxxxxxx\tFor all CB opcodes\n....1.. 1.1........1.11.\tD\t63\t00xxx110\tld r,*\n....1.. .1.1.......1.11.\t-\t64\t11xxx110\tadd/sub/and/or/xor/cmp a,imm\n....1.. .11.............\t-\t65\t10xxxxxx\tadd/sub/and/or/xor/cmp a,r\n....1.. 1.1........11...\t-\t66\t00xxx10x\tinc/dec r\n......1 1..1......1.1.1.\t-\t67\t01xxx000\tin\n......1 1..1......1..11.\t-\t68\t01xxx010\tadc/sbc hl,rr\n....1.. 1.1......11.1..1\t-\t69\t00xx1001\tadd hl,rr\n.....1. 1.1.............\t-\t70\t00xxxxxx\trlc r\n....1.. 1.1.1......1.1.1\tD\t71\t000xx111\trlca/rla/rrca/rra\n.....1. 1..1............\t-\t72\t01xxxxxx\tbit b,r\n.....1. .11.............\t-\t73\t10xxxxxx\tres b,r\n.....1. .1.1............\t-\t74\t11xxxxxx\tset b,r\n....1.. 1.1........11..1\t-\t75\t00xxx101\tdec r\n...1... .....1.1.1......\t-\t76\txx111xxx\t111 (CP)\n....1.. 1.1..11.1..1.1.1\t-\t77\t00100111\tdaa\n...1... ....1..11.......\t-\t78\txx010xxx\t010 (SUB)\n...1... ....1..1.1......\t-\t79\txx011xxx\t011 (SBC)\n...1... ....1.1..1......\t-\t80\txx001xxx\t001 (ADC)\n....1.. 1.1..11..1.1.1.1\t-\t81\t00101111\tcpl\n......1 1..1.......11.1.\t-\t82\t01xxx100\tneg\n......1 1..11..1...1.1.1\t-\t83\t0101x111\tld a,i/a,r\n...1... ....1.1.1.......\t-\t84\txx000xxx\t000 (ADD)\n...1... .....11.1.......\t-\t85\txx100xxx\t100 (AND)\n...1... .....1.11.......\t-\t86\txx110xxx\t110 (OR)\n......1 1..11..1...1.1.1\tD\t87\t0101x111\tld a,i / ld a,r\n...1... .....11..1......\t-\t88\txx101xxx\t101 (XOR)\n....1.. 1.1..1.1.1.1.1.1\t-\t89\t00111111\tccf\n....1.. 1.1.1..11.1.1.1.\tD\t90\t00010000\tdjnz *\n......1 .11..1....1..1..\t-\t91\t101xx01x\tinx/outx/inxr/otxr\n....1.. 1.1..1.11..1.1.1\t-\t92\t00110111\tscf\n......1 .11..1....1.1..1\tD\t93\t101xx001\tcpi/cpir/cpd/cpdr\n......1 .11..1....1.1.1.\tD\t94\t101xx000\tldi/ldir/ldd/lddr\n....1.. 1..1.1.11..1.11.\t-\t95\t01110110\thalt\n......1 1..1.......1.11.\t-\t96\t01xxx110\tim n\n....1.. .1.1.1.1..1..1.1\t-\t97\t1111x011\tdi/ei\n....1.. .1.11..1..1..1.1\tD\t98\t1101x011\tout (*),a/in a,(*)\n....... ...............1\t-\t99\txxxxxxx1\topcode[0]\n....... .............1..\t-\t100\txxxxxx1x\topcode[1]\n....... ...........1....\t-\t101\txxxxx1xx\topcode[2]\n....... .........1......\t-\t102\txxxx1xxx\topcode[3]\n....... .......1........\t-\t103\txxx1xxxx\topcode[4]\n....... .....1..........\t-\t104\txx1xxxxx\topcode[5]\n"
  },
  {
    "path": "tools/Arduino/Z80_dongle/Z80_dongle.ino",
    "content": "//------------------------------------------------------------------------\n// This Arduino sketch should be used with a Mega board connected to a\n// dongle hosting a Z80 CPU. The Arduino fully controls and senses all\n// Z80 CPU pins. This software runs physical Z80 CPU by providing clock\n// ticks and setting various control pins.\n//\n// There is a limited RAM buffer simulated by this sketch. All Z80 memory\n// accesses are directed to use that buffer.\n//\n// Address and data buses from Z80 are connected to analog Arduino pins.\n// Along with a resistor network on the dongle, this allows the software\n// to sense when Z80 tri-states those two buses.\n//\n// Notes:\n//      - Use serial set to 115200\n//      - In the Arduino serial monitor window, set line ending to \"CR\"\n//      - Memory access is simulated using a 256-byte pseudo-RAM memory\n//      - I/O map is _not_ implemented. Reads will return whatever happens\n//        to be on the data bus\n//\n// Copyright 2014 by Goran Devic\n// This source code is released under the GPL v2 software license.\n//------------------------------------------------------------------------\n#include <stdarg.h>\n#include \"WString.h\"\n\n// Define Arduino Mega pins that are connected to a Z80 dongle board.\n// Pin numbers appear out-of-order, but they cleanly connect in complete\n// blocks to sets of pins on Arduino Mega! This will become obvious once\n// you start connecting them...\n#define DB0         A9      // DB pin line-up on a Z80 is a bit swizzled...\n#define DB1         A8\n#define DB2         A11\n#define DB3         A14\n#define DB4         A15\n#define DB5         A13\n#define DB6         A12\n#define DB7         A10\n// Address bus pins from Z80 are connected to A0..A7 on Arduino.\n\n#define INT         52      // This is a block of control signals from the\n#define NMI         50      // bottom-left corner of Z80\n#define HALT        48\n#define MREQ        46\n#define IORQ        44\n\n#define RFSH        53      // This is a block of control signals from the\n#define M1          51      // bottom-right corner of Z80\n#define RESET       49\n#define BUSRQ       47\n#define WAIT        45\n#define BUSAK       43\n#define WR          41\n#define RD          39\n\n#define CLK         13      // Clock is also toggling Arduino LED (fast, though)\n\n// Tri-state detection values: the values that are read on analog pins\n// sensing the \"high-Z\" will differ based on the resistor values that make\n// up your voltage divider. Print your particular readings and adjust these:\n#define HI_Z_LOW    50      // Upper \"0\" value; low tri-state boundary\n#define HI_Z_HIGH   600     // Low \"1\" value; upper tri-state boundary\n\n// Control *output* pins of Z80, we read them into these variables\nint  halt;\nint  mreq;\nint  iorq;\nint  rfsh;\nint  m1;\nint  busak;\nint  wr;\nint  rd;\n\n// Control *input* pins of Z80, we write them into the dongle\nint zint = 1;\nint nmi = 1;\nint reset = 1;\nint busrq = 1;\nint wait = 1;\n\n// Content of address and data wires\nint ab;\nbyte db;\n\n// Clock counter after reset\nint clkCount;\nint clkCountHi;\n\n// T-cycle counter\nint T;\nint Mlast;\n\n// M1-cycle counter\nint m1Count;\n\n// Detection if the address or data bus is tri-stated\nbool abTristated = false;\nbool dbTristated = false;\n\n// Simulation control variables\nbool running = 1;           // Simulation is running or is stopped\nint traceShowBothPhases;    // Show both phases of a clock cycle\nint traceRefresh;           // Trace refresh cycles\nint tracePause;             // Pause for a key press every so many clocks\nint tracePauseCount;        // Current clock count for tracePause\nint stopAtClk;              // Stop the simulation after this many clocks\nint stopAtM1;               // Stop at a specific M1 cycle number\nint stopAtHalt;             // Stop when HALT signal gets active\nint intAtClk;               // Issue INT signal at that clock number\nint nmiAtClk;               // Issue NMI signal at that clock number\nint busrqAtClk;             // Issue BUSRQ signal at that clock number\nint resetAtClk;             // Issue RESET signal at that clock number\nint waitAtClk;              // Issue WAIT signal at that clock number\nint clearAtClk;             // Clear all control signals at that clock number\nbyte iorqVector;            // Push IORQ vector (default is FF)\n\n// Buffer containing RAM memory for Z80 to access\nbyte ram[256];\n\n// Temp buffer to store input line\n#define TEMP_SIZE   512\nchar temp[TEMP_SIZE];\n\n// Temp buffer to store extra dump information\nchar extraInfo[64] = { \"\" };\n\n// Utility function to provide a meaningful printf to a serial port\nvoid p(char *fmt, ... ){\n    char tmp[256];          // resulting string limited to 256 chars\n    va_list args;\n    va_start (args, fmt );\n    vsnprintf(tmp, 256, fmt, args);\n    va_end (args);\n    Serial.print(tmp);\n}\n\n// Read and return one ASCII hex value from a string\nbyte hex(char *s){\n    byte nibbleH = (*s - '0') & ~(1<<5);\n    byte nibbleL = (*(s+1) - '0') & ~(1<<5);\n    if (nibbleH>9) nibbleH -= 7;\n    if (nibbleL>9) nibbleL -= 7;\n    return (nibbleH << 4) | nibbleL;\n}\n\n// Read and return one ASCII hex value from a temp buffer given the index\n// of that hex number. This is used only to read Intel HEX format buffer.\nbyte hexFromTemp(char *pTemp, int index)\n{\n    int start = (index*2)+1;\n    return hex(pTemp + start);\n}\n\n// -----------------------------------------------------------\n// Arduino initialization entry point\n// -----------------------------------------------------------\nvoid setup()\n{\n    Serial.begin(115200);\n    Serial.flush();\n    Serial.setTimeout(1000*60*60);\n\n    ResetSimulationVars();\n\n    // By default, all Arduino pins are set as inputs\n    // Configure all output pins, *inputs* into Z80\n    pinMode(CLK, OUTPUT);\n    digitalWrite(CLK, HIGH);\n    pinMode(INT, OUTPUT);\n    pinMode(NMI, OUTPUT);\n    pinMode(RESET, OUTPUT);\n    pinMode(BUSRQ, OUTPUT);\n    pinMode(WAIT, OUTPUT);\n    WriteControlPins();\n\n    // Perform a Z80 CPU reset\n    DoReset();\n}\n\n// Resets all simulation variables to their defaults\nvoid ResetSimulationVars()\n{\n    traceShowBothPhases = 0;// Show both phases of a clock cycle\n    traceRefresh = 1;       // Trace refresh cycles\n    tracePause = -1;        // Pause for a keypress every so many clocks\n    stopAtClk = 40;         // Stop the simulation after this many clocks\n    stopAtM1 = -1;          // Stop at a specific M1 cycle number\n    stopAtHalt = 1;         // Stop when HALT signal gets active\n    intAtClk = -1;          // Issue INT signal at that clock number\n    nmiAtClk = -1;          // Issue NMI signal at that clock number\n    busrqAtClk = -1;        // Issue BUSRQ signal at that clock number\n    resetAtClk = -1;        // Issue RESET signal at that clock number\n    waitAtClk = -1;         // Issue WAIT signal at that clock number\n    clearAtClk = -1;        // Clear all control signals at that clock number\n    iorqVector = 0xFF;      // Push IORQ vector\n}\n\n// Issue a RESET sequence to Z80 and reset internal counters\nvoid DoReset()\n{\n    p(\"\\r\\n:Starting the clock\\r\\n\");\n    digitalWrite(RESET, LOW);    delay(1);\n    // Reset should be kept low for 3 full clock cycles\n    for(int i=0; i<3; i++)\n    {\n        digitalWrite(CLK, HIGH); delay(1);\n        digitalWrite(CLK, LOW);  delay(1);\n    }\n    p(\":Releasing RESET\\r\\n\");\n    digitalWrite(RESET, HIGH);   delay(1);\n    // Do not count initial 2 clocks after the reset\n    clkCount = -2;\n    T = 0;\n    Mlast = 1;\n    tracePauseCount = 0;\n    m1Count = 0;\n}\n\n// Write all control pins into the Z80 dongle\nvoid WriteControlPins()\n{\n    digitalWrite(INT, zint ? HIGH : LOW);\n    digitalWrite(NMI, nmi ? HIGH : LOW);\n    digitalWrite(RESET, reset ? HIGH : LOW);\n    digitalWrite(BUSRQ, busrq ? HIGH : LOW);\n    digitalWrite(WAIT,  wait ? HIGH : LOW);\n}\n\n// Set new data value into the Z80 data bus\nvoid SetDataToDB(byte data)\n{\n    pinMode(DB0, OUTPUT);\n    pinMode(DB1, OUTPUT);\n    pinMode(DB2, OUTPUT);\n    pinMode(DB3, OUTPUT);\n    pinMode(DB4, OUTPUT);\n    pinMode(DB5, OUTPUT);\n    pinMode(DB6, OUTPUT);\n    pinMode(DB7, OUTPUT);\n\n    digitalWrite(DB0, (data & (1<<0)) ? HIGH : LOW);\n    digitalWrite(DB1, (data & (1<<1)) ? HIGH : LOW);\n    digitalWrite(DB2, (data & (1<<2)) ? HIGH : LOW);\n    digitalWrite(DB3, (data & (1<<3)) ? HIGH : LOW);\n    digitalWrite(DB4, (data & (1<<4)) ? HIGH : LOW);\n    digitalWrite(DB5, (data & (1<<5)) ? HIGH : LOW);\n    digitalWrite(DB6, (data & (1<<6)) ? HIGH : LOW);\n    digitalWrite(DB7, (data & (1<<7)) ? HIGH : LOW);\n    db = data;\n    dbTristated = false;\n}\n\n// Read Z80 data bus and store into db variable\nvoid GetDataFromDB()\n{\n    pinMode(DB0, INPUT);\n    pinMode(DB1, INPUT);\n    pinMode(DB2, INPUT);\n    pinMode(DB3, INPUT);\n    pinMode(DB4, INPUT);\n    pinMode(DB5, INPUT);\n    pinMode(DB6, INPUT);\n    pinMode(DB7, INPUT);\n\n    digitalWrite(DB0, LOW);\n    digitalWrite(DB1, LOW);\n    digitalWrite(DB2, LOW);\n    digitalWrite(DB3, LOW);\n    digitalWrite(DB4, LOW);\n    digitalWrite(DB5, LOW);\n    digitalWrite(DB6, LOW);\n    digitalWrite(DB7, LOW);\n\n    // Detect if the data bus is tri-stated\n    delay(1);\n    int test0 = analogRead(DB0);\n    // These numbers might need to be adjusted for each Arduino board\n    dbTristated = test0>HI_Z_LOW && test0<HI_Z_HIGH;\n\n    byte d0 = digitalRead(DB0);\n    byte d1 = digitalRead(DB1);\n    byte d2 = digitalRead(DB2);\n    byte d3 = digitalRead(DB3);\n    byte d4 = digitalRead(DB4);\n    byte d5 = digitalRead(DB5);\n    byte d6 = digitalRead(DB6);\n    byte d7 = digitalRead(DB7);\n    db = (d7<<7)|(d6<<6)|(d5<<5)|(d4<<4)|(d3<<3)|(d2<<2)|(d1<<1)|d0;\n}\n\n// Read a value of Z80 address bus and store it into the ab variable.\n// In addition, try to detect when a bus is tri-stated and write 0xFFF if so.\nvoid GetAddressFromAB()\n{\n    // Detect if the address bus is tri-stated\n    int test0 = analogRead(A0);\n    // These numbers might need to be adjusted for each Arduino board\n    abTristated = test0>HI_Z_LOW && test0<HI_Z_HIGH;\n\n    int a0 = digitalRead(A0);\n    int a1 = digitalRead(A1);\n    int a2 = digitalRead(A2);\n    int a3 = digitalRead(A3);\n    int a4 = digitalRead(A4);\n    int a5 = digitalRead(A5);\n    int a6 = digitalRead(A6);\n    int a7 = digitalRead(A7);\n    ab = (a7<<7)|(a6<<6)|(a5<<5)|(a4<<4)|(a3<<3)|(a2<<2)|(a1<<1)|a0;\n}\n\n// Read all control pins on the Z80 and store them into internal variables\nvoid ReadControlState()\n{\n    halt  = digitalRead(HALT);\n    mreq  = digitalRead(MREQ);\n    iorq  = digitalRead(IORQ);\n    rfsh  = digitalRead(RFSH);\n    m1    = digitalRead(M1);\n    busak = digitalRead(BUSAK);\n    wr    = digitalRead(WR);\n    rd    = digitalRead(RD);\n}\n\n// Dump the Z80 state as stored in internal variables\nvoid DumpState(bool suppress)\n{\n    if (!suppress)\n    {\n        // Select your character for tri-stated bus\n        char abStr[4] = { \"---\" };\n        char dbStr[3] = { \"--\" };\n        if (!abTristated) sprintf(abStr, \"%03X\", ab);\n        if (!dbTristated) sprintf(dbStr, \"%02X\", db);\n        if (T==1 && clkCountHi)\n            p(\"-----------------------------------------------------------+\\r\\n\");\n        p(\"#%03d%c T%-2d AB:%s DB:%s  %s %s %s %s %s %s %s %s |%s%s%s%s %s\\r\\n\",\n        clkCount<0? 0 : clkCount, clkCountHi ? 'H' : 'L', T,\n        abStr, dbStr,\n        m1?\"  \":\"M1\", rfsh?\"    \":\"RFSH\", mreq?\"    \":\"MREQ\", rd?\"  \":\"RD\", wr?\"  \":\"WR\", iorq?\"    \":\"IORQ\", busak?\"     \":\"BUSAK\",halt?\"    \":\"HALT\",\n        zint?\"\":\"[INT]\", nmi?\"\":\"[NMI]\", busrq?\"\":\"[BUSRQ]\", wait?\"\":\"[WAIT]\",\n        extraInfo);\n    }\n    extraInfo[0] = 0;\n}\n\n// -----------------------------------------------------------\n// Main loop routine runs over and over again forever\n// -----------------------------------------------------------\nvoid loop()\n{\n    //--------------------------------------------------------\n    // Clock goes high\n    //--------------------------------------------------------\n    delay(1); digitalWrite(CLK, HIGH); delay(1);\n\n    clkCountHi = 1;\n    clkCount++;\n    T++;\n    tracePauseCount++;\n    ReadControlState();\n    GetAddressFromAB();\n    if (Mlast==1 && m1==0)\n        T = 1, m1Count++;\n    Mlast = m1;\n    bool suppressDump = false;\n    if (!traceRefresh & !rfsh) suppressDump = true;\n\n    // If the number of M1 cycles has been reached, skip the rest since we dont\n    // want to execute this M1 phase\n    if (m1Count==stopAtM1)\n    {\n        sprintf(extraInfo, \"Number of M1 cycles reached\"), running = false;\n        p(\"-----------------------------------------------------------+\\r\\n\");\n        goto control;\n    }\n\n    // If the address is tri-stated, skip checking various combinations of\n    // control signals since they may also be floating and we can't detect that\n    if (!abTristated)\n    {\n        // Simulate read from RAM\n        if (!mreq && !rd)\n        {\n            SetDataToDB(ram[ab & 0xFF]);\n            if (!m1)\n                sprintf(extraInfo, \"Opcode read from %03X -> %02X\", ab, ram[ab & 0xFF]);\n            else\n                sprintf(extraInfo, \"Memory read from %03X -> %02X\", ab, ram[ab & 0xFF]);\n        }\n        else\n        // Simulate interrupt requesting a vector\n        if (!m1 && !iorq)\n        {\n            SetDataToDB(iorqVector);\n            sprintf(extraInfo, \"Pushing vector %02X\", iorqVector);\n        }\n        else\n            GetDataFromDB();\n\n        // Simulate write to RAM\n        if (!mreq && !wr)\n        {\n            ram[ab & 0xFF] = db;\n            sprintf(extraInfo, \"Memory write to  %03X <- %02X\", ab, db);\n        }\n\n        // Detect I/O read: We don't place anything on the bus\n        if (!iorq && !rd)\n        {\n            sprintf(extraInfo, \"I/O read from %03X\", ab);\n        }\n\n        // Detect I/O write\n        if (!iorq && !wr)\n        {\n            sprintf(extraInfo, \"I/O write to %03X <- %02X\", ab, db);\n        }\n\n        // Capture memory refresh cycle\n        if (!mreq && !rfsh)\n        {\n            sprintf(extraInfo, \"Refresh address  %03X\", ab);\n        }\n    }\n    else\n        GetDataFromDB();\n\n    DumpState(suppressDump);\n\n    // If the user wanted to pause simulation after a certain number of\n    // clocks, handle it here. If the key pressed to continue was not Enter,\n    // stop the simulation to issue that command\n    if (tracePause==tracePauseCount)\n    {\n        while(Serial.available()==0) ;\n        if (Serial.peek()!='\\r')\n            sprintf(extraInfo, \"Continue keypress was not Enter\"), running = false;\n        else\n            Serial.read();\n        tracePauseCount = 0;\n    }\n\n    //--------------------------------------------------------\n    // Clock goes low\n    //--------------------------------------------------------\n    delay(1); digitalWrite(CLK, LOW); delay(1);\n\n    clkCountHi = 0;\n    if (traceShowBothPhases)\n    {\n        ReadControlState();\n        GetAddressFromAB();\n        DumpState(suppressDump);\n    }\n\n    // Perform various actions at the requested clock number\n    // if the count is positive (we start it at -2 to skip initial 2T)\n    if (clkCount>=0)\n    {\n        if (clkCount==intAtClk) zint = 0;\n        if (clkCount==nmiAtClk) nmi = 0;\n        if (clkCount==busrqAtClk) busrq = 0;\n        if (clkCount==resetAtClk) reset = 0;\n        if (clkCount==waitAtClk) wait = 0;\n        // De-assert all control pins at this clock number\n        if (clkCount==clearAtClk)\n            zint = nmi = busrq = reset = wait = 1;\n        WriteControlPins();\n\n        // Stop the simulation under some conditions\n        if (clkCount==stopAtClk)\n            sprintf(extraInfo, \"Number of clocks reached\"), running = false;\n        if (stopAtHalt&!halt)\n            sprintf(extraInfo, \"HALT instruction\"), running = false;\n    }\n\n    //--------------------------------------------------------\n    // Trace/simulation control handler\n    //--------------------------------------------------------\ncontrol:\n    if (!running)\n    {\n        p(\":Simulation stopped: %s\\r\\n\", extraInfo);\n        extraInfo[0] = 0;\n        digitalWrite(CLK, HIGH);\n        zint = nmi = busrq = wait = 1;\n        WriteControlPins();\n\n        while(!running)\n        {\n            // Expect a command from the serial port\n            if (Serial.available()>0)\n            {\n                memset(temp, 0, TEMP_SIZE);\n                Serial.readBytesUntil('\\r', temp, TEMP_SIZE-1);\n\n                // Option \":\"  : this is not really a user option. This is used to\n                //               Intel HEX format values into the RAM buffer\n                // Multiple lines may be pasted. They are separated by a space character.\n                char *pTemp = temp;\n                while (*pTemp==':')\n                {\n                    byte bytes = hexFromTemp(pTemp, 0);\n                    if (bytes>0)\n                    {\n                        int address = (hexFromTemp(pTemp, 1)<<8) + hexFromTemp(pTemp, 2);\n                        byte recordType = hexFromTemp(pTemp, 3);\n                        p(\"%04X:\", address);\n                        for (int i=0; i<bytes; i++)\n                        {\n                            ram[(address + i) & 0xFF] = hexFromTemp(pTemp, 4+i);\n                            p(\" %02X\", hexFromTemp(pTemp, 4+i));\n                        }\n                        p(\"\\r\\n\");\n                    }\n                    pTemp += bytes*2 + 12;  // Skip to the next possible line of hex entry\n                }\n                // Option \"r\"  : reset and run the simulation\n                if (temp[0]=='r')\n                {\n                    // If the variable 9 (Issue RESET) is not set, perform a RESET and run the simulation.\n                    // If the variable was set, skip reset sequence since we might be testing it.\n                    if (resetAtClk<0)\n                        DoReset();\n                    running = true;\n                }\n                // Option \"sc\" : clear simulation variables to their default values\n                if (temp[0]=='s' && temp[1]=='c')\n                {\n                    ResetSimulationVars();\n                    temp[1] = 0;            // Proceed to dump all variables...\n                }\n                // Option \"s\"  : show and set internal control variables\n                if (temp[0]=='s' && temp[1]!='c')\n                {\n                    // Show or set the simulation parameters\n                    int var = 0, value;\n                    int args = sscanf(&temp[1], \"%d %d\\r\\n\", &var, &value);\n                    // Parameter for the option #12 is read in as a hex; others are decimal by default\n                    if (var==12)\n                        args = sscanf(&temp[1], \"%d %x\\r\\n\", &var, &value);\n                    if (args==2)\n                    {\n                        if (var==0) traceShowBothPhases = value;\n                        if (var==1) traceRefresh = value;\n                        if (var==2) tracePause = value;\n                        if (var==3) stopAtClk = value;\n                        if (var==4) stopAtM1 = value;\n                        if (var==5) stopAtHalt = value;\n                        if (var==6) intAtClk = value;\n                        if (var==7) nmiAtClk = value;\n                        if (var==8) busrqAtClk = value;\n                        if (var==9) resetAtClk = value;\n                        if (var==10) waitAtClk = value;\n                        if (var==11) clearAtClk = value;\n                        if (var==12) iorqVector = value & 0xFF;\n                    }\n                    p(\"------ Simulation variables ------\\r\\n\");\n                    p(\"#0  Trace both clock phases  = %d\\r\\n\", traceShowBothPhases);\n                    p(\"#1  Trace refresh cycles     = %d\\r\\n\", traceRefresh);\n                    p(\"#2  Pause for keypress every = %d\\r\\n\", tracePause);\n                    p(\"#3  Stop after clock #       = %d\\r\\n\", stopAtClk);\n                    p(\"#4  Stop after # M1 cycles   = %d\\r\\n\", stopAtM1);\n                    p(\"#5  Stop at HALT             = %d\\r\\n\", stopAtHalt);\n                    p(\"#6  Issue INT at clock #     = %d\\r\\n\", intAtClk);\n                    p(\"#7  Issue NMI at clock #     = %d\\r\\n\", nmiAtClk);\n                    p(\"#8  Issue BUSRQ at clock #   = %d\\r\\n\", busrqAtClk);\n                    p(\"#9  Issue RESET at clock #   = %d\\r\\n\", resetAtClk);\n                    p(\"#10 Issue WAIT at clock #    = %d\\r\\n\", waitAtClk);\n                    p(\"#11 Clear all at clock #     = %d\\r\\n\", clearAtClk);\n                    p(\"#12 Push IORQ vector #(hex)  = %2X\\r\\n\", iorqVector);\n                }\n                // Option \"m\"  : dump RAM memory\n                if (temp[0]=='m' && temp[1]!='c')\n                {\n                    // Dump the content of a RAM buffer\n                    p(\"    00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F\\r\\n\");\n                    p(\"   +-----------------------------------------------\\r\\n\");\n                    for(int i=0; i<16; i++)\n                    {\n                        p(\"%02X |\", i);\n                        for(int j=0; j<16; j++)\n                        {\n                            p(\"%02X \", ram[i*16+j]);\n                        }\n                        p(\"\\r\\n\");\n                    }\n                }\n                // Option \"mc\"  : clear RAM memory\n                if (temp[0]=='m' && temp[1]=='c')\n                {\n                    memset(ram, 0, sizeof(ram));\n                    p(\"RAM cleared\\r\\n\");\n                }\n                // Option \"?\"  : print help\n                if (temp[0]=='?' || temp[0]=='h')\n                {\n                    p(\"s            - show simulation variables\\r\\n\");\n                    p(\"s #var value - set simulation variable number to a value\\r\\n\");\n                    p(\"sc           - clear simulation variables to their default values\\r\\n\");\n                    p(\"r            - restart the simulation\\r\\n\");\n                    p(\":INTEL-HEX   - reload RAM buffer with a given data stream\\r\\n\");\n                    p(\"m            - dump the content of the RAM buffer\\r\\n\");\n                    p(\"mc           - clear the RAM buffer\\r\\n\");\n                }\n            }\n        }\n    }\n}\n"
  },
  {
    "path": "tools/dongle/cb.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD HTML 4.01//EN\">\n<HTML><HEAD><TITLE>Z80 Instructions Timing</TITLE></HEAD><BODY>\n<H1>Opcodes with CB prefix</H1>\nCB 00 .. <A href=\"#00\">RLC B</A><BR>\nCB 01 .. <A href=\"#01\">RLC C</A><BR>\nCB 02 .. <A href=\"#02\">RLC D</A><BR>\nCB 03 .. <A href=\"#03\">RLC E</A><BR>\nCB 04 .. <A href=\"#04\">RLC H</A><BR>\nCB 05 .. <A href=\"#05\">RLC L</A><BR>\nCB 06 .. <A href=\"#06\">RLC (HL)</A><BR>\nCB 07 .. <A href=\"#07\">RLC A</A><BR>\nCB 08 .. <A href=\"#08\">RRC B</A><BR>\nCB 09 .. <A href=\"#09\">RRC C</A><BR>\nCB 0A .. <A href=\"#0A\">RRC D</A><BR>\nCB 0B .. <A href=\"#0B\">RRC E</A><BR>\nCB 0C .. <A href=\"#0C\">RRC H</A><BR>\nCB 0D .. <A href=\"#0D\">RRC L</A><BR>\nCB 0E .. <A href=\"#0E\">RRC (HL)</A><BR>\nCB 0F .. <A href=\"#0F\">RRC A</A><BR>\nCB 10 .. <A href=\"#10\">RL B</A><BR>\nCB 11 .. <A href=\"#11\">RL C</A><BR>\nCB 12 .. <A href=\"#12\">RL D</A><BR>\nCB 13 .. <A href=\"#13\">RL E</A><BR>\nCB 14 .. <A href=\"#14\">RL H</A><BR>\nCB 15 .. <A href=\"#15\">RL L</A><BR>\nCB 16 .. <A href=\"#16\">RL (HL)</A><BR>\nCB 17 .. <A href=\"#17\">RL A</A><BR>\nCB 18 .. <A href=\"#18\">RR B</A><BR>\nCB 19 .. <A href=\"#19\">RR C</A><BR>\nCB 1A .. <A href=\"#1A\">RR D</A><BR>\nCB 1B .. <A href=\"#1B\">RR E</A><BR>\nCB 1C .. <A href=\"#1C\">RR H</A><BR>\nCB 1D .. <A href=\"#1D\">RR L</A><BR>\nCB 1E .. <A href=\"#1E\">RR (HL)</A><BR>\nCB 1F .. <A href=\"#1F\">RR A</A><BR>\nCB 20 .. <A href=\"#20\">SLA B</A><BR>\nCB 21 .. <A href=\"#21\">SLA C</A><BR>\nCB 22 .. <A href=\"#22\">SLA D</A><BR>\nCB 23 .. <A href=\"#23\">SLA E</A><BR>\nCB 24 .. <A href=\"#24\">SLA H</A><BR>\nCB 25 .. <A href=\"#25\">SLA L</A><BR>\nCB 26 .. <A href=\"#26\">SLA (HL)</A><BR>\nCB 27 .. <A href=\"#27\">SLA A</A><BR>\nCB 28 .. <A href=\"#28\">SRA B</A><BR>\nCB 29 .. <A href=\"#29\">SRA C</A><BR>\nCB 2A .. <A href=\"#2A\">SRA D</A><BR>\nCB 2B .. <A href=\"#2B\">SRA E</A><BR>\nCB 2C .. <A href=\"#2C\">SRA H</A><BR>\nCB 2D .. <A href=\"#2D\">SRA L</A><BR>\nCB 2E .. <A href=\"#2E\">SRA (HL)</A><BR>\nCB 2F .. <A href=\"#2F\">SRA A</A><BR>\nCB 30 .. <A href=\"#30\">SLL B*</A><BR>\nCB 31 .. <A href=\"#31\">SLL C*</A><BR>\nCB 32 .. <A href=\"#32\">SLL D*</A><BR>\nCB 33 .. <A href=\"#33\">SLL E*</A><BR>\nCB 34 .. <A href=\"#34\">SLL H*</A><BR>\nCB 35 .. <A href=\"#35\">SLL L*</A><BR>\nCB 36 .. <A href=\"#36\">SLL (HL)*</A><BR>\nCB 37 .. <A href=\"#37\">SLL A*</A><BR>\nCB 38 .. <A href=\"#38\">SRL B</A><BR>\nCB 39 .. <A href=\"#39\">SRL C</A><BR>\nCB 3A .. <A href=\"#3A\">SRL D</A><BR>\nCB 3B .. <A href=\"#3B\">SRL E</A><BR>\nCB 3C .. <A href=\"#3C\">SRL H</A><BR>\nCB 3D .. <A href=\"#3D\">SRL L</A><BR>\nCB 3E .. <A href=\"#3E\">SRL (HL)</A><BR>\nCB 3F .. <A href=\"#3F\">SRL A</A><BR>\nCB 40 .. <A href=\"#40\">BIT 0,B</A><BR>\nCB 41 .. <A href=\"#41\">BIT 0,C</A><BR>\nCB 42 .. <A href=\"#42\">BIT 0,D</A><BR>\nCB 43 .. <A href=\"#43\">BIT 0,E</A><BR>\nCB 44 .. <A href=\"#44\">BIT 0,H</A><BR>\nCB 45 .. <A href=\"#45\">BIT 0,L</A><BR>\nCB 46 .. <A href=\"#46\">BIT 0,(HL)</A><BR>\nCB 47 .. <A href=\"#47\">BIT 0,A</A><BR>\nCB 48 .. <A href=\"#48\">BIT 1,B</A><BR>\nCB 49 .. <A href=\"#49\">BIT 1,C</A><BR>\nCB 4A .. <A href=\"#4A\">BIT 1,D</A><BR>\nCB 4B .. <A href=\"#4B\">BIT 1,E</A><BR>\nCB 4C .. <A href=\"#4C\">BIT 1,H</A><BR>\nCB 4D .. <A href=\"#4D\">BIT 1,L</A><BR>\nCB 4E .. <A href=\"#4E\">BIT 1,(HL)</A><BR>\nCB 4F .. <A href=\"#4F\">BIT 1,A</A><BR>\nCB 50 .. <A href=\"#50\">BIT 2,B</A><BR>\nCB 51 .. <A href=\"#51\">BIT 2,C</A><BR>\nCB 52 .. <A href=\"#52\">BIT 2,D</A><BR>\nCB 53 .. <A href=\"#53\">BIT 2,E</A><BR>\nCB 54 .. <A href=\"#54\">BIT 2,H</A><BR>\nCB 55 .. <A href=\"#55\">BIT 2,L</A><BR>\nCB 56 .. <A href=\"#56\">BIT 2,(HL)</A><BR>\nCB 57 .. <A href=\"#57\">BIT 2,A</A><BR>\nCB 58 .. <A href=\"#58\">BIT 3,B</A><BR>\nCB 59 .. <A href=\"#59\">BIT 3,C</A><BR>\nCB 5A .. <A href=\"#5A\">BIT 3,D</A><BR>\nCB 5B .. <A href=\"#5B\">BIT 3,E</A><BR>\nCB 5C .. <A href=\"#5C\">BIT 3,H</A><BR>\nCB 5D .. <A href=\"#5D\">BIT 3,L</A><BR>\nCB 5E .. <A href=\"#5E\">BIT 3,(HL)</A><BR>\nCB 5F .. <A href=\"#5F\">BIT 3,A</A><BR>\nCB 60 .. <A href=\"#60\">BIT 4,B</A><BR>\nCB 61 .. <A href=\"#61\">BIT 4,C</A><BR>\nCB 62 .. <A href=\"#62\">BIT 4,D</A><BR>\nCB 63 .. <A href=\"#63\">BIT 4,E</A><BR>\nCB 64 .. <A href=\"#64\">BIT 4,H</A><BR>\nCB 65 .. <A href=\"#65\">BIT 4,L</A><BR>\nCB 66 .. <A href=\"#66\">BIT 4,(HL)</A><BR>\nCB 67 .. <A href=\"#67\">BIT 4,A</A><BR>\nCB 68 .. <A href=\"#68\">BIT 5,B</A><BR>\nCB 69 .. <A href=\"#69\">BIT 5,C</A><BR>\nCB 6A .. <A href=\"#6A\">BIT 5,D</A><BR>\nCB 6B .. <A href=\"#6B\">BIT 5,E</A><BR>\nCB 6C .. <A href=\"#6C\">BIT 5,H</A><BR>\nCB 6D .. <A href=\"#6D\">BIT 5,L</A><BR>\nCB 6E .. <A href=\"#6E\">BIT 5,(HL)</A><BR>\nCB 6F .. <A href=\"#6F\">BIT 5,A</A><BR>\nCB 70 .. <A href=\"#70\">BIT 6,B</A><BR>\nCB 71 .. <A href=\"#71\">BIT 6,C</A><BR>\nCB 72 .. <A href=\"#72\">BIT 6,D</A><BR>\nCB 73 .. <A href=\"#73\">BIT 6,E</A><BR>\nCB 74 .. <A href=\"#74\">BIT 6,H</A><BR>\nCB 75 .. <A href=\"#75\">BIT 6,L</A><BR>\nCB 76 .. <A href=\"#76\">BIT 6,(HL)</A><BR>\nCB 77 .. <A href=\"#77\">BIT 6,A</A><BR>\nCB 78 .. <A href=\"#78\">BIT 7,B</A><BR>\nCB 79 .. <A href=\"#79\">BIT 7,C</A><BR>\nCB 7A .. <A href=\"#7A\">BIT 7,D</A><BR>\nCB 7B .. <A href=\"#7B\">BIT 7,E</A><BR>\nCB 7C .. <A href=\"#7C\">BIT 7,H</A><BR>\nCB 7D .. <A href=\"#7D\">BIT 7,L</A><BR>\nCB 7E .. <A href=\"#7E\">BIT 7,(HL)</A><BR>\nCB 7F .. <A href=\"#7F\">BIT 7,A</A><BR>\nCB 80 .. <A href=\"#80\">RES 0,B</A><BR>\nCB 81 .. <A href=\"#81\">RES 0,C</A><BR>\nCB 82 .. <A href=\"#82\">RES 0,D</A><BR>\nCB 83 .. <A href=\"#83\">RES 0,E</A><BR>\nCB 84 .. <A href=\"#84\">RES 0,H</A><BR>\nCB 85 .. <A href=\"#85\">RES 0,L</A><BR>\nCB 86 .. <A href=\"#86\">RES 0,(HL)</A><BR>\nCB 87 .. <A href=\"#87\">RES 0,A</A><BR>\nCB 88 .. <A href=\"#88\">RES 1,B</A><BR>\nCB 89 .. <A href=\"#89\">RES 1,C</A><BR>\nCB 8A .. <A href=\"#8A\">RES 1,D</A><BR>\nCB 8B .. <A href=\"#8B\">RES 1,E</A><BR>\nCB 8C .. <A href=\"#8C\">RES 1,H</A><BR>\nCB 8D .. <A href=\"#8D\">RES 1,L</A><BR>\nCB 8E .. <A href=\"#8E\">RES 1,(HL)</A><BR>\nCB 8F .. <A href=\"#8F\">RES 1,A</A><BR>\nCB 90 .. <A href=\"#90\">RES 2,B</A><BR>\nCB 91 .. <A href=\"#91\">RES 2,C</A><BR>\nCB 92 .. <A href=\"#92\">RES 2,D</A><BR>\nCB 93 .. <A href=\"#93\">RES 2,E</A><BR>\nCB 94 .. <A href=\"#94\">RES 2,H</A><BR>\nCB 95 .. <A href=\"#95\">RES 2,L</A><BR>\nCB 96 .. <A href=\"#96\">RES 2,(HL)</A><BR>\nCB 97 .. <A href=\"#97\">RES 2,A</A><BR>\nCB 98 .. <A href=\"#98\">RES 3,B</A><BR>\nCB 99 .. <A href=\"#99\">RES 3,C</A><BR>\nCB 9A .. <A href=\"#9A\">RES 3,D</A><BR>\nCB 9B .. <A href=\"#9B\">RES 3,E</A><BR>\nCB 9C .. <A href=\"#9C\">RES 3,H</A><BR>\nCB 9D .. <A href=\"#9D\">RES 3,L</A><BR>\nCB 9E .. <A href=\"#9E\">RES 3,(HL)</A><BR>\nCB 9F .. <A href=\"#9F\">RES 3,A</A><BR>\nCB A0 .. <A href=\"#A0\">RES 4,B</A><BR>\nCB A1 .. <A href=\"#A1\">RES 4,C</A><BR>\nCB A2 .. <A href=\"#A2\">RES 4,D</A><BR>\nCB A3 .. <A href=\"#A3\">RES 4,E</A><BR>\nCB A4 .. <A href=\"#A4\">RES 4,H</A><BR>\nCB A5 .. <A href=\"#A5\">RES 4,L</A><BR>\nCB A6 .. <A href=\"#A6\">RES 4,(HL)</A><BR>\nCB A7 .. <A href=\"#A7\">RES 4,A</A><BR>\nCB A8 .. <A href=\"#A8\">RES 5,B</A><BR>\nCB A9 .. <A href=\"#A9\">RES 5,C</A><BR>\nCB AA .. <A href=\"#AA\">RES 5,D</A><BR>\nCB AB .. <A href=\"#AB\">RES 5,E</A><BR>\nCB AC .. <A href=\"#AC\">RES 5,H</A><BR>\nCB AD .. <A href=\"#AD\">RES 5,L</A><BR>\nCB AE .. <A href=\"#AE\">RES 5,(HL)</A><BR>\nCB AF .. <A href=\"#AF\">RES 5,A</A><BR>\nCB B0 .. <A href=\"#B0\">RES 6,B</A><BR>\nCB B1 .. <A href=\"#B1\">RES 6,C</A><BR>\nCB B2 .. <A href=\"#B2\">RES 6,D</A><BR>\nCB B3 .. <A href=\"#B3\">RES 6,E</A><BR>\nCB B4 .. <A href=\"#B4\">RES 6,H</A><BR>\nCB B5 .. <A href=\"#B5\">RES 6,L</A><BR>\nCB B6 .. <A href=\"#B6\">RES 6,(HL)</A><BR>\nCB B7 .. <A href=\"#B7\">RES 6,A</A><BR>\nCB B8 .. <A href=\"#B8\">RES 7,B</A><BR>\nCB B9 .. <A href=\"#B9\">RES 7,C</A><BR>\nCB BA .. <A href=\"#BA\">RES 7,D</A><BR>\nCB BB .. <A href=\"#BB\">RES 7,E</A><BR>\nCB BC .. <A href=\"#BC\">RES 7,H</A><BR>\nCB BD .. <A href=\"#BD\">RES 7,L</A><BR>\nCB BE .. <A href=\"#BE\">RES 7,(HL)</A><BR>\nCB BF .. <A href=\"#BF\">RES 7,A</A><BR>\nCB C0 .. <A href=\"#C0\">SET 0,B</A><BR>\nCB C1 .. <A href=\"#C1\">SET 0,C</A><BR>\nCB C2 .. <A href=\"#C2\">SET 0,D</A><BR>\nCB C3 .. <A href=\"#C3\">SET 0,E</A><BR>\nCB C4 .. <A href=\"#C4\">SET 0,H</A><BR>\nCB C5 .. <A href=\"#C5\">SET 0,L</A><BR>\nCB C6 .. <A href=\"#C6\">SET 0,(HL)</A><BR>\nCB C7 .. <A href=\"#C7\">SET 0,A</A><BR>\nCB C8 .. <A href=\"#C8\">SET 1,B</A><BR>\nCB C9 .. <A href=\"#C9\">SET 1,C</A><BR>\nCB CA .. <A href=\"#CA\">SET 1,D</A><BR>\nCB CB .. <A href=\"#CB\">SET 1,E</A><BR>\nCB CC .. <A href=\"#CC\">SET 1,H</A><BR>\nCB CD .. <A href=\"#CD\">SET 1,L</A><BR>\nCB CE .. <A href=\"#CE\">SET 1,(HL)</A><BR>\nCB CF .. <A href=\"#CF\">SET 1,A</A><BR>\nCB D0 .. <A href=\"#D0\">SET 2,B</A><BR>\nCB D1 .. <A href=\"#D1\">SET 2,C</A><BR>\nCB D2 .. <A href=\"#D2\">SET 2,D</A><BR>\nCB D3 .. <A href=\"#D3\">SET 2,E</A><BR>\nCB D4 .. <A href=\"#D4\">SET 2,H</A><BR>\nCB D5 .. <A href=\"#D5\">SET 2,L</A><BR>\nCB D6 .. <A href=\"#D6\">SET 2,(HL)</A><BR>\nCB D7 .. <A href=\"#D7\">SET 2,A</A><BR>\nCB D8 .. <A href=\"#D8\">SET 3,B</A><BR>\nCB D9 .. <A href=\"#D9\">SET 3,C</A><BR>\nCB DA .. <A href=\"#DA\">SET 3,D</A><BR>\nCB DB .. <A href=\"#DB\">SET 3,E</A><BR>\nCB DC .. <A href=\"#DC\">SET 3,H</A><BR>\nCB DD .. <A href=\"#DD\">SET 3,L</A><BR>\nCB DE .. <A href=\"#DE\">SET 3,(HL)</A><BR>\nCB DF .. <A href=\"#DF\">SET 3,A</A><BR>\nCB E0 .. <A href=\"#E0\">SET 4,B</A><BR>\nCB E1 .. <A href=\"#E1\">SET 4,C</A><BR>\nCB E2 .. <A href=\"#E2\">SET 4,D</A><BR>\nCB E3 .. <A href=\"#E3\">SET 4,E</A><BR>\nCB E4 .. <A href=\"#E4\">SET 4,H</A><BR>\nCB E5 .. <A href=\"#E5\">SET 4,L</A><BR>\nCB E6 .. <A href=\"#E6\">SET 4,(HL)</A><BR>\nCB E7 .. <A href=\"#E7\">SET 4,A</A><BR>\nCB E8 .. <A href=\"#E8\">SET 5,B</A><BR>\nCB E9 .. <A href=\"#E9\">SET 5,C</A><BR>\nCB EA .. <A href=\"#EA\">SET 5,D</A><BR>\nCB EB .. <A href=\"#EB\">SET 5,E</A><BR>\nCB EC .. <A href=\"#EC\">SET 5,H</A><BR>\nCB ED .. <A href=\"#ED\">SET 5,L</A><BR>\nCB EE .. <A href=\"#EE\">SET 5,(HL)</A><BR>\nCB EF .. <A href=\"#EF\">SET 5,A</A><BR>\nCB F0 .. <A href=\"#F0\">SET 6,B</A><BR>\nCB F1 .. <A href=\"#F1\">SET 6,C</A><BR>\nCB F2 .. <A href=\"#F2\">SET 6,D</A><BR>\nCB F3 .. <A href=\"#F3\">SET 6,E</A><BR>\nCB F4 .. <A href=\"#F4\">SET 6,H</A><BR>\nCB F5 .. <A href=\"#F5\">SET 6,L</A><BR>\nCB F6 .. <A href=\"#F6\">SET 6,(HL)</A><BR>\nCB F7 .. <A href=\"#F7\">SET 6,A</A><BR>\nCB F8 .. <A href=\"#F8\">SET 7,B</A><BR>\nCB F9 .. <A href=\"#F9\">SET 7,C</A><BR>\nCB FA .. <A href=\"#FA\">SET 7,D</A><BR>\nCB FB .. <A href=\"#FB\">SET 7,E</A><BR>\nCB FC .. <A href=\"#FC\">SET 7,H</A><BR>\nCB FD .. <A href=\"#FD\">SET 7,L</A><BR>\nCB FE .. <A href=\"#FE\">SET 7,(HL)</A><BR>\nCB FF .. <A href=\"#FF\">SET 7,A</A><BR>\n<H1>Instructions Timing</H1>\n<H3 id=\"00\">Opcode: CB 00 => RLC B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:00  M1      MREQ RD                    | Opcode read from 001 -> 00\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"01\">Opcode: CB 01 => RLC C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:01  M1      MREQ RD                    | Opcode read from 001 -> 01\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"02\">Opcode: CB 02 => RLC D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:02  M1      MREQ RD                    | Opcode read from 001 -> 02\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"03\">Opcode: CB 03 => RLC E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:03  M1      MREQ RD                    | Opcode read from 001 -> 03\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"04\">Opcode: CB 04 => RLC H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:04  M1      MREQ RD                    | Opcode read from 001 -> 04\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"05\">Opcode: CB 05 => RLC L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:05  M1      MREQ RD                    | Opcode read from 001 -> 05\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"06\">Opcode: CB 06 => RLC (HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:06  M1      MREQ RD                    | Opcode read from 001 -> 06\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:006 DB:--                                     | \n#010H T6  AB:006 DB:05          MREQ RD                    | Memory read from 006 -> 05\n#011H T7  AB:006 DB:05          MREQ RD                    | Memory read from 006 -> 05\n#012H T8  AB:006 DB:--                                     | \n#013H T9  AB:006 DB:--                                     | \n#014H T10 AB:006 DB:0A          MREQ                       | \n#015H T11 AB:006 DB:0A          MREQ    WR                 | Memory write to  006 <- 0A\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"07\">Opcode: CB 07 => RLC A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:07  M1      MREQ RD                    | Opcode read from 001 -> 07\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"08\">Opcode: CB 08 => RRC B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:08  M1      MREQ RD                    | Opcode read from 001 -> 08\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"09\">Opcode: CB 09 => RRC C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:09  M1      MREQ RD                    | Opcode read from 001 -> 09\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"0A\">Opcode: CB 0A => RRC D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:0A  M1      MREQ RD                    | Opcode read from 001 -> 0A\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"0B\">Opcode: CB 0B => RRC E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:0B  M1      MREQ RD                    | Opcode read from 001 -> 0B\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"0C\">Opcode: CB 0C => RRC H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:0C  M1      MREQ RD                    | Opcode read from 001 -> 0C\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"0D\">Opcode: CB 0D => RRC L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:0D  M1      MREQ RD                    | Opcode read from 001 -> 0D\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"0E\">Opcode: CB 0E => RRC (HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:0E  M1      MREQ RD                    | Opcode read from 001 -> 0E\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:003 DB:--                                     | \n#010H T6  AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#011H T7  AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:--                                     | \n#014H T10 AB:003 DB:01          MREQ                       | \n#015H T11 AB:003 DB:01          MREQ    WR                 | Memory write to  003 <- 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"0F\">Opcode: CB 0F => RRC A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:0F  M1      MREQ RD                    | Opcode read from 001 -> 0F\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"10\">Opcode: CB 10 => RL B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:10  M1      MREQ RD                    | Opcode read from 001 -> 10\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"11\">Opcode: CB 11 => RL C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:11  M1      MREQ RD                    | Opcode read from 001 -> 11\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"12\">Opcode: CB 12 => RL D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:12  M1      MREQ RD                    | Opcode read from 001 -> 12\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"13\">Opcode: CB 13 => RL E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:13  M1      MREQ RD                    | Opcode read from 001 -> 13\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"14\">Opcode: CB 14 => RL H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:14  M1      MREQ RD                    | Opcode read from 001 -> 14\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"15\">Opcode: CB 15 => RL L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:15  M1      MREQ RD                    | Opcode read from 001 -> 15\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"16\">Opcode: CB 16 => RL (HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:16  M1      MREQ RD                    | Opcode read from 001 -> 16\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:007 DB:--                                     | \n#010H T6  AB:007 DB:06          MREQ RD                    | Memory read from 007 -> 06\n#011H T7  AB:007 DB:06          MREQ RD                    | Memory read from 007 -> 06\n#012H T8  AB:007 DB:--                                     | \n#013H T9  AB:007 DB:--                                     | \n#014H T10 AB:007 DB:0C          MREQ                       | \n#015H T11 AB:007 DB:0C          MREQ    WR                 | Memory write to  007 <- 0C\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"17\">Opcode: CB 17 => RL A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:17  M1      MREQ RD                    | Opcode read from 001 -> 17\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"18\">Opcode: CB 18 => RR B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:18  M1      MREQ RD                    | Opcode read from 001 -> 18\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"19\">Opcode: CB 19 => RR C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:19  M1      MREQ RD                    | Opcode read from 001 -> 19\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"1A\">Opcode: CB 1A => RR D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:1A  M1      MREQ RD                    | Opcode read from 001 -> 1A\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"1B\">Opcode: CB 1B => RR E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:1B  M1      MREQ RD                    | Opcode read from 001 -> 1B\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"1C\">Opcode: CB 1C => RR H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:1C  M1      MREQ RD                    | Opcode read from 001 -> 1C\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"1D\">Opcode: CB 1D => RR L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:1D  M1      MREQ RD                    | Opcode read from 001 -> 1D\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"1E\">Opcode: CB 1E => RR (HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:1E  M1      MREQ RD                    | Opcode read from 001 -> 1E\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:003 DB:--                                     | \n#010H T6  AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#011H T7  AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:--                                     | \n#014H T10 AB:003 DB:81          MREQ                       | \n#015H T11 AB:003 DB:81          MREQ    WR                 | Memory write to  003 <- 81\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"1F\">Opcode: CB 1F => RR A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:1F  M1      MREQ RD                    | Opcode read from 001 -> 1F\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"20\">Opcode: CB 20 => SLA B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:20  M1      MREQ RD                    | Opcode read from 001 -> 20\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"21\">Opcode: CB 21 => SLA C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:21  M1      MREQ RD                    | Opcode read from 001 -> 21\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"22\">Opcode: CB 22 => SLA D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:22  M1      MREQ RD                    | Opcode read from 001 -> 22\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"23\">Opcode: CB 23 => SLA E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:23  M1      MREQ RD                    | Opcode read from 001 -> 23\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"24\">Opcode: CB 24 => SLA H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:24  M1      MREQ RD                    | Opcode read from 001 -> 24\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"25\">Opcode: CB 25 => SLA L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:25  M1      MREQ RD                    | Opcode read from 001 -> 25\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"26\">Opcode: CB 26 => SLA (HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:26  M1      MREQ RD                    | Opcode read from 001 -> 26\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:006 DB:--                                     | \n#010H T6  AB:006 DB:05          MREQ RD                    | Memory read from 006 -> 05\n#011H T7  AB:006 DB:05          MREQ RD                    | Memory read from 006 -> 05\n#012H T8  AB:006 DB:--                                     | \n#013H T9  AB:006 DB:--                                     | \n#014H T10 AB:006 DB:0A          MREQ                       | \n#015H T11 AB:006 DB:0A          MREQ    WR                 | Memory write to  006 <- 0A\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"27\">Opcode: CB 27 => SLA A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:27  M1      MREQ RD                    | Opcode read from 001 -> 27\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"28\">Opcode: CB 28 => SRA B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:28  M1      MREQ RD                    | Opcode read from 001 -> 28\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"29\">Opcode: CB 29 => SRA C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:29  M1      MREQ RD                    | Opcode read from 001 -> 29\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"2A\">Opcode: CB 2A => SRA D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:2A  M1      MREQ RD                    | Opcode read from 001 -> 2A\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"2B\">Opcode: CB 2B => SRA E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:2B  M1      MREQ RD                    | Opcode read from 001 -> 2B\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"2C\">Opcode: CB 2C => SRA H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:2C  M1      MREQ RD                    | Opcode read from 001 -> 2C\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"2D\">Opcode: CB 2D => SRA L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:2D  M1      MREQ RD                    | Opcode read from 001 -> 2D\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"2E\">Opcode: CB 2E => SRA (HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:2E  M1      MREQ RD                    | Opcode read from 001 -> 2E\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:003 DB:--                                     | \n#010H T6  AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#011H T7  AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:--                                     | \n#014H T10 AB:003 DB:01          MREQ                       | \n#015H T11 AB:003 DB:01          MREQ    WR                 | Memory write to  003 <- 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"2F\">Opcode: CB 2F => SRA A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:2F  M1      MREQ RD                    | Opcode read from 001 -> 2F\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"30\">Opcode: CB 30 => SLL B*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:30  M1      MREQ RD                    | Opcode read from 001 -> 30\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"31\">Opcode: CB 31 => SLL C*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:31  M1      MREQ RD                    | Opcode read from 001 -> 31\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"32\">Opcode: CB 32 => SLL D*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:32  M1      MREQ RD                    | Opcode read from 001 -> 32\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"33\">Opcode: CB 33 => SLL E*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:33  M1      MREQ RD                    | Opcode read from 001 -> 33\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"34\">Opcode: CB 34 => SLL H*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:34  M1      MREQ RD                    | Opcode read from 001 -> 34\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"35\">Opcode: CB 35 => SLL L*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:35  M1      MREQ RD                    | Opcode read from 001 -> 35\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"36\">Opcode: CB 36 => SLL (HL)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:36  M1      MREQ RD                    | Opcode read from 001 -> 36\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:007 DB:--                                     | \n#010H T6  AB:007 DB:06          MREQ RD                    | Memory read from 007 -> 06\n#011H T7  AB:007 DB:06          MREQ RD                    | Memory read from 007 -> 06\n#012H T8  AB:007 DB:--                                     | \n#013H T9  AB:007 DB:--                                     | \n#014H T10 AB:007 DB:0D          MREQ                       | \n#015H T11 AB:007 DB:0D          MREQ    WR                 | Memory write to  007 <- 0D\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"37\">Opcode: CB 37 => SLL A*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:37  M1      MREQ RD                    | Opcode read from 001 -> 37\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"38\">Opcode: CB 38 => SRL B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:38  M1      MREQ RD                    | Opcode read from 001 -> 38\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"39\">Opcode: CB 39 => SRL C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:39  M1      MREQ RD                    | Opcode read from 001 -> 39\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"3A\">Opcode: CB 3A => SRL D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:3A  M1      MREQ RD                    | Opcode read from 001 -> 3A\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"3B\">Opcode: CB 3B => SRL E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:3B  M1      MREQ RD                    | Opcode read from 001 -> 3B\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"3C\">Opcode: CB 3C => SRL H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:3C  M1      MREQ RD                    | Opcode read from 001 -> 3C\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"3D\">Opcode: CB 3D => SRL L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:3D  M1      MREQ RD                    | Opcode read from 001 -> 3D\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"3E\">Opcode: CB 3E => SRL (HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:3E  M1      MREQ RD                    | Opcode read from 001 -> 3E\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:003 DB:--                                     | \n#010H T6  AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#011H T7  AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:--                                     | \n#014H T10 AB:003 DB:01          MREQ                       | \n#015H T11 AB:003 DB:01          MREQ    WR                 | Memory write to  003 <- 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"3F\">Opcode: CB 3F => SRL A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:3F  M1      MREQ RD                    | Opcode read from 001 -> 3F\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"40\">Opcode: CB 40 => BIT 0,B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:40  M1      MREQ RD                    | Opcode read from 001 -> 40\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"41\">Opcode: CB 41 => BIT 0,C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:41  M1      MREQ RD                    | Opcode read from 001 -> 41\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"42\">Opcode: CB 42 => BIT 0,D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:42  M1      MREQ RD                    | Opcode read from 001 -> 42\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"43\">Opcode: CB 43 => BIT 0,E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:43  M1      MREQ RD                    | Opcode read from 001 -> 43\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"44\">Opcode: CB 44 => BIT 0,H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:44  M1      MREQ RD                    | Opcode read from 001 -> 44\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"45\">Opcode: CB 45 => BIT 0,L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:45  M1      MREQ RD                    | Opcode read from 001 -> 45\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"46\">Opcode: CB 46 => BIT 0,(HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:46  M1      MREQ RD                    | Opcode read from 001 -> 46\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:003 DB:--                                     | \n#010H T6  AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#011H T7  AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#012H T8  AB:003 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"47\">Opcode: CB 47 => BIT 0,A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:47  M1      MREQ RD                    | Opcode read from 001 -> 47\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"48\">Opcode: CB 48 => BIT 1,B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:48  M1      MREQ RD                    | Opcode read from 001 -> 48\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"49\">Opcode: CB 49 => BIT 1,C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:49  M1      MREQ RD                    | Opcode read from 001 -> 49\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"4A\">Opcode: CB 4A => BIT 1,D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:4A  M1      MREQ RD                    | Opcode read from 001 -> 4A\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"4B\">Opcode: CB 4B => BIT 1,E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:4B  M1      MREQ RD                    | Opcode read from 001 -> 4B\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"4C\">Opcode: CB 4C => BIT 1,H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:4C  M1      MREQ RD                    | Opcode read from 001 -> 4C\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"4D\">Opcode: CB 4D => BIT 1,L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:4D  M1      MREQ RD                    | Opcode read from 001 -> 4D\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"4E\">Opcode: CB 4E => BIT 1,(HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:4E  M1      MREQ RD                    | Opcode read from 001 -> 4E\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:003 DB:--                                     | \n#010H T6  AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#011H T7  AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#012H T8  AB:003 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"4F\">Opcode: CB 4F => BIT 1,A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:4F  M1      MREQ RD                    | Opcode read from 001 -> 4F\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"50\">Opcode: CB 50 => BIT 2,B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:50  M1      MREQ RD                    | Opcode read from 001 -> 50\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"51\">Opcode: CB 51 => BIT 2,C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:51  M1      MREQ RD                    | Opcode read from 001 -> 51\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"52\">Opcode: CB 52 => BIT 2,D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:52  M1      MREQ RD                    | Opcode read from 001 -> 52\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"53\">Opcode: CB 53 => BIT 2,E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:53  M1      MREQ RD                    | Opcode read from 001 -> 53\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"54\">Opcode: CB 54 => BIT 2,H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:54  M1      MREQ RD                    | Opcode read from 001 -> 54\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"55\">Opcode: CB 55 => BIT 2,L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:55  M1      MREQ RD                    | Opcode read from 001 -> 55\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"56\">Opcode: CB 56 => BIT 2,(HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:56  M1      MREQ RD                    | Opcode read from 001 -> 56\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:003 DB:--                                     | \n#010H T6  AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#011H T7  AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#012H T8  AB:003 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"57\">Opcode: CB 57 => BIT 2,A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:57  M1      MREQ RD                    | Opcode read from 001 -> 57\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"58\">Opcode: CB 58 => BIT 3,B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:58  M1      MREQ RD                    | Opcode read from 001 -> 58\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"59\">Opcode: CB 59 => BIT 3,C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:59  M1      MREQ RD                    | Opcode read from 001 -> 59\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"5A\">Opcode: CB 5A => BIT 3,D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:5A  M1      MREQ RD                    | Opcode read from 001 -> 5A\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"5B\">Opcode: CB 5B => BIT 3,E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:5B  M1      MREQ RD                    | Opcode read from 001 -> 5B\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"5C\">Opcode: CB 5C => BIT 3,H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:5C  M1      MREQ RD                    | Opcode read from 001 -> 5C\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"5D\">Opcode: CB 5D => BIT 3,L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:5D  M1      MREQ RD                    | Opcode read from 001 -> 5D\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"5E\">Opcode: CB 5E => BIT 3,(HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:5E  M1      MREQ RD                    | Opcode read from 001 -> 5E\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:003 DB:--                                     | \n#010H T6  AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#011H T7  AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#012H T8  AB:003 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"5F\">Opcode: CB 5F => BIT 3,A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:5F  M1      MREQ RD                    | Opcode read from 001 -> 5F\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"60\">Opcode: CB 60 => BIT 4,B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:60  M1      MREQ RD                    | Opcode read from 001 -> 60\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"61\">Opcode: CB 61 => BIT 4,C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:61  M1      MREQ RD                    | Opcode read from 001 -> 61\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"62\">Opcode: CB 62 => BIT 4,D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:62  M1      MREQ RD                    | Opcode read from 001 -> 62\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"63\">Opcode: CB 63 => BIT 4,E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:63  M1      MREQ RD                    | Opcode read from 001 -> 63\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"64\">Opcode: CB 64 => BIT 4,H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:64  M1      MREQ RD                    | Opcode read from 001 -> 64\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"65\">Opcode: CB 65 => BIT 4,L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:65  M1      MREQ RD                    | Opcode read from 001 -> 65\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"66\">Opcode: CB 66 => BIT 4,(HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:66  M1      MREQ RD                    | Opcode read from 001 -> 66\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:003 DB:--                                     | \n#010H T6  AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#011H T7  AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#012H T8  AB:003 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"67\">Opcode: CB 67 => BIT 4,A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:67  M1      MREQ RD                    | Opcode read from 001 -> 67\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"68\">Opcode: CB 68 => BIT 5,B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:68  M1      MREQ RD                    | Opcode read from 001 -> 68\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"69\">Opcode: CB 69 => BIT 5,C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:69  M1      MREQ RD                    | Opcode read from 001 -> 69\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"6A\">Opcode: CB 6A => BIT 5,D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:6A  M1      MREQ RD                    | Opcode read from 001 -> 6A\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"6B\">Opcode: CB 6B => BIT 5,E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:6B  M1      MREQ RD                    | Opcode read from 001 -> 6B\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"6C\">Opcode: CB 6C => BIT 5,H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:6C  M1      MREQ RD                    | Opcode read from 001 -> 6C\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"6D\">Opcode: CB 6D => BIT 5,L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:6D  M1      MREQ RD                    | Opcode read from 001 -> 6D\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"6E\">Opcode: CB 6E => BIT 5,(HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:6E  M1      MREQ RD                    | Opcode read from 001 -> 6E\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:003 DB:--                                     | \n#010H T6  AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#011H T7  AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#012H T8  AB:003 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"6F\">Opcode: CB 6F => BIT 5,A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:6F  M1      MREQ RD                    | Opcode read from 001 -> 6F\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"70\">Opcode: CB 70 => BIT 6,B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:70  M1      MREQ RD                    | Opcode read from 001 -> 70\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"71\">Opcode: CB 71 => BIT 6,C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:71  M1      MREQ RD                    | Opcode read from 001 -> 71\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"72\">Opcode: CB 72 => BIT 6,D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:72  M1      MREQ RD                    | Opcode read from 001 -> 72\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"73\">Opcode: CB 73 => BIT 6,E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:73  M1      MREQ RD                    | Opcode read from 001 -> 73\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"74\">Opcode: CB 74 => BIT 6,H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:74  M1      MREQ RD                    | Opcode read from 001 -> 74\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"75\">Opcode: CB 75 => BIT 6,L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:75  M1      MREQ RD                    | Opcode read from 001 -> 75\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"76\">Opcode: CB 76 => BIT 6,(HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:76  M1      MREQ RD                    | Opcode read from 001 -> 76\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:003 DB:--                                     | \n#010H T6  AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#011H T7  AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#012H T8  AB:003 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"77\">Opcode: CB 77 => BIT 6,A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:77  M1      MREQ RD                    | Opcode read from 001 -> 77\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"78\">Opcode: CB 78 => BIT 7,B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:78  M1      MREQ RD                    | Opcode read from 001 -> 78\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"79\">Opcode: CB 79 => BIT 7,C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:79  M1      MREQ RD                    | Opcode read from 001 -> 79\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"7A\">Opcode: CB 7A => BIT 7,D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:7A  M1      MREQ RD                    | Opcode read from 001 -> 7A\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"7B\">Opcode: CB 7B => BIT 7,E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:7B  M1      MREQ RD                    | Opcode read from 001 -> 7B\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"7C\">Opcode: CB 7C => BIT 7,H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:7C  M1      MREQ RD                    | Opcode read from 001 -> 7C\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"7D\">Opcode: CB 7D => BIT 7,L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:7D  M1      MREQ RD                    | Opcode read from 001 -> 7D\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"7E\">Opcode: CB 7E => BIT 7,(HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:7E  M1      MREQ RD                    | Opcode read from 001 -> 7E\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:003 DB:--                                     | \n#010H T6  AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#011H T7  AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#012H T8  AB:003 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"7F\">Opcode: CB 7F => BIT 7,A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:7F  M1      MREQ RD                    | Opcode read from 001 -> 7F\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"80\">Opcode: CB 80 => RES 0,B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:80  M1      MREQ RD                    | Opcode read from 001 -> 80\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"81\">Opcode: CB 81 => RES 0,C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:81  M1      MREQ RD                    | Opcode read from 001 -> 81\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"82\">Opcode: CB 82 => RES 0,D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:82  M1      MREQ RD                    | Opcode read from 001 -> 82\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"83\">Opcode: CB 83 => RES 0,E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:83  M1      MREQ RD                    | Opcode read from 001 -> 83\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"84\">Opcode: CB 84 => RES 0,H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:84  M1      MREQ RD                    | Opcode read from 001 -> 84\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"85\">Opcode: CB 85 => RES 0,L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:85  M1      MREQ RD                    | Opcode read from 001 -> 85\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"86\">Opcode: CB 86 => RES 0,(HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:86  M1      MREQ RD                    | Opcode read from 001 -> 86\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:002 DB:--                                     | \n#013H T9  AB:002 DB:--                                     | \n#014H T10 AB:002 DB:00          MREQ                       | \n#015H T11 AB:002 DB:00          MREQ    WR                 | Memory write to  002 <- 00\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"87\">Opcode: CB 87 => RES 0,A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:87  M1      MREQ RD                    | Opcode read from 001 -> 87\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"88\">Opcode: CB 88 => RES 1,B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:88  M1      MREQ RD                    | Opcode read from 001 -> 88\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"89\">Opcode: CB 89 => RES 1,C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:89  M1      MREQ RD                    | Opcode read from 001 -> 89\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"8A\">Opcode: CB 8A => RES 1,D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:8A  M1      MREQ RD                    | Opcode read from 001 -> 8A\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"8B\">Opcode: CB 8B => RES 1,E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:8B  M1      MREQ RD                    | Opcode read from 001 -> 8B\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"8C\">Opcode: CB 8C => RES 1,H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:8C  M1      MREQ RD                    | Opcode read from 001 -> 8C\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"8D\">Opcode: CB 8D => RES 1,L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:8D  M1      MREQ RD                    | Opcode read from 001 -> 8D\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"8E\">Opcode: CB 8E => RES 1,(HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:8E  M1      MREQ RD                    | Opcode read from 001 -> 8E\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:000 DB:--                                     | \n#010H T6  AB:000 DB:CB          MREQ RD                    | Memory read from 000 -> CB\n#011H T7  AB:000 DB:CB          MREQ RD                    | Memory read from 000 -> CB\n#012H T8  AB:000 DB:--                                     | \n#013H T9  AB:000 DB:--                                     | \n#014H T10 AB:000 DB:C9          MREQ                       | \n#015H T11 AB:000 DB:C9          MREQ    WR                 | Memory write to  000 <- C9\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"8F\">Opcode: CB 8F => RES 1,A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:8F  M1      MREQ RD                    | Opcode read from 001 -> 8F\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"90\">Opcode: CB 90 => RES 2,B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:90  M1      MREQ RD                    | Opcode read from 001 -> 90\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"91\">Opcode: CB 91 => RES 2,C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:91  M1      MREQ RD                    | Opcode read from 001 -> 91\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"92\">Opcode: CB 92 => RES 2,D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:92  M1      MREQ RD                    | Opcode read from 001 -> 92\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"93\">Opcode: CB 93 => RES 2,E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:93  M1      MREQ RD                    | Opcode read from 001 -> 93\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"94\">Opcode: CB 94 => RES 2,H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:94  M1      MREQ RD                    | Opcode read from 001 -> 94\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"95\">Opcode: CB 95 => RES 2,L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:95  M1      MREQ RD                    | Opcode read from 001 -> 95\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"96\">Opcode: CB 96 => RES 2,(HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:96  M1      MREQ RD                    | Opcode read from 001 -> 96\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:000 DB:--                                     | \n#010H T6  AB:000 DB:CB          MREQ RD                    | Memory read from 000 -> CB\n#011H T7  AB:000 DB:CB          MREQ RD                    | Memory read from 000 -> CB\n#012H T8  AB:000 DB:--                                     | \n#013H T9  AB:000 DB:--                                     | \n#014H T10 AB:000 DB:CB          MREQ                       | \n#015H T11 AB:000 DB:CB          MREQ    WR                 | Memory write to  000 <- CB\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"97\">Opcode: CB 97 => RES 2,A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:97  M1      MREQ RD                    | Opcode read from 001 -> 97\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"98\">Opcode: CB 98 => RES 3,B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:98  M1      MREQ RD                    | Opcode read from 001 -> 98\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"99\">Opcode: CB 99 => RES 3,C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:99  M1      MREQ RD                    | Opcode read from 001 -> 99\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"9A\">Opcode: CB 9A => RES 3,D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:9A  M1      MREQ RD                    | Opcode read from 001 -> 9A\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"9B\">Opcode: CB 9B => RES 3,E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:9B  M1      MREQ RD                    | Opcode read from 001 -> 9B\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"9C\">Opcode: CB 9C => RES 3,H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:9C  M1      MREQ RD                    | Opcode read from 001 -> 9C\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"9D\">Opcode: CB 9D => RES 3,L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:9D  M1      MREQ RD                    | Opcode read from 001 -> 9D\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"9E\">Opcode: CB 9E => RES 3,(HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:9E  M1      MREQ RD                    | Opcode read from 001 -> 9E\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:000 DB:--                                     | \n#010H T6  AB:000 DB:CB          MREQ RD                    | Memory read from 000 -> CB\n#011H T7  AB:000 DB:CB          MREQ RD                    | Memory read from 000 -> CB\n#012H T8  AB:000 DB:--                                     | \n#013H T9  AB:000 DB:--                                     | \n#014H T10 AB:000 DB:C3          MREQ                       | \n#015H T11 AB:000 DB:C3          MREQ    WR                 | Memory write to  000 <- C3\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"9F\">Opcode: CB 9F => RES 3,A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:9F  M1      MREQ RD                    | Opcode read from 001 -> 9F\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"A0\">Opcode: CB A0 => RES 4,B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:A0  M1      MREQ RD                    | Opcode read from 001 -> A0\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"A1\">Opcode: CB A1 => RES 4,C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:A1  M1      MREQ RD                    | Opcode read from 001 -> A1\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"A2\">Opcode: CB A2 => RES 4,D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:A2  M1      MREQ RD                    | Opcode read from 001 -> A2\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"A3\">Opcode: CB A3 => RES 4,E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:A3  M1      MREQ RD                    | Opcode read from 001 -> A3\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"A4\">Opcode: CB A4 => RES 4,H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:A4  M1      MREQ RD                    | Opcode read from 001 -> A4\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"A5\">Opcode: CB A5 => RES 4,L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:A5  M1      MREQ RD                    | Opcode read from 001 -> A5\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"A6\">Opcode: CB A6 => RES 4,(HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:A6  M1      MREQ RD                    | Opcode read from 001 -> A6\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:000 DB:--                                     | \n#010H T6  AB:000 DB:CB          MREQ RD                    | Memory read from 000 -> CB\n#011H T7  AB:000 DB:CB          MREQ RD                    | Memory read from 000 -> CB\n#012H T8  AB:000 DB:--                                     | \n#013H T9  AB:000 DB:--                                     | \n#014H T10 AB:000 DB:CB          MREQ                       | \n#015H T11 AB:000 DB:CB          MREQ    WR                 | Memory write to  000 <- CB\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"A7\">Opcode: CB A7 => RES 4,A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:A7  M1      MREQ RD                    | Opcode read from 001 -> A7\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"A8\">Opcode: CB A8 => RES 5,B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:A8  M1      MREQ RD                    | Opcode read from 001 -> A8\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"A9\">Opcode: CB A9 => RES 5,C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:A9  M1      MREQ RD                    | Opcode read from 001 -> A9\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"AA\">Opcode: CB AA => RES 5,D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:AA  M1      MREQ RD                    | Opcode read from 001 -> AA\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"AB\">Opcode: CB AB => RES 5,E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:AB  M1      MREQ RD                    | Opcode read from 001 -> AB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"AC\">Opcode: CB AC => RES 5,H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:AC  M1      MREQ RD                    | Opcode read from 001 -> AC\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"AD\">Opcode: CB AD => RES 5,L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:AD  M1      MREQ RD                    | Opcode read from 001 -> AD\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"AE\">Opcode: CB AE => RES 5,(HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:AE  M1      MREQ RD                    | Opcode read from 001 -> AE\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:000 DB:--                                     | \n#010H T6  AB:000 DB:CB          MREQ RD                    | Memory read from 000 -> CB\n#011H T7  AB:000 DB:CB          MREQ RD                    | Memory read from 000 -> CB\n#012H T8  AB:000 DB:--                                     | \n#013H T9  AB:000 DB:--                                     | \n#014H T10 AB:000 DB:CB          MREQ                       | \n#015H T11 AB:000 DB:CB          MREQ    WR                 | Memory write to  000 <- CB\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"AF\">Opcode: CB AF => RES 5,A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:AF  M1      MREQ RD                    | Opcode read from 001 -> AF\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"B0\">Opcode: CB B0 => RES 6,B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:B0  M1      MREQ RD                    | Opcode read from 001 -> B0\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"B1\">Opcode: CB B1 => RES 6,C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:B1  M1      MREQ RD                    | Opcode read from 001 -> B1\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"B2\">Opcode: CB B2 => RES 6,D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:B2  M1      MREQ RD                    | Opcode read from 001 -> B2\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"B3\">Opcode: CB B3 => RES 6,E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:B3  M1      MREQ RD                    | Opcode read from 001 -> B3\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"B4\">Opcode: CB B4 => RES 6,H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:B4  M1      MREQ RD                    | Opcode read from 001 -> B4\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"B5\">Opcode: CB B5 => RES 6,L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:B5  M1      MREQ RD                    | Opcode read from 001 -> B5\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"B6\">Opcode: CB B6 => RES 6,(HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:B6  M1      MREQ RD                    | Opcode read from 001 -> B6\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:000 DB:--                                     | \n#010H T6  AB:000 DB:CB          MREQ RD                    | Memory read from 000 -> CB\n#011H T7  AB:000 DB:CB          MREQ RD                    | Memory read from 000 -> CB\n#012H T8  AB:000 DB:--                                     | \n#013H T9  AB:000 DB:--                                     | \n#014H T10 AB:000 DB:8B          MREQ                       | \n#015H T11 AB:000 DB:8B          MREQ    WR                 | Memory write to  000 <- 8B\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"B7\">Opcode: CB B7 => RES 6,A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:B7  M1      MREQ RD                    | Opcode read from 001 -> B7\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"B8\">Opcode: CB B8 => RES 7,B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:B8  M1      MREQ RD                    | Opcode read from 001 -> B8\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"B9\">Opcode: CB B9 => RES 7,C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:B9  M1      MREQ RD                    | Opcode read from 001 -> B9\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"BA\">Opcode: CB BA => RES 7,D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:BA  M1      MREQ RD                    | Opcode read from 001 -> BA\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"BB\">Opcode: CB BB => RES 7,E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:BB  M1      MREQ RD                    | Opcode read from 001 -> BB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"BC\">Opcode: CB BC => RES 7,H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:BC  M1      MREQ RD                    | Opcode read from 001 -> BC\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"BD\">Opcode: CB BD => RES 7,L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:BD  M1      MREQ RD                    | Opcode read from 001 -> BD\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"BE\">Opcode: CB BE => RES 7,(HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:BE  M1      MREQ RD                    | Opcode read from 001 -> BE\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:000 DB:--                                     | \n#010H T6  AB:000 DB:CB          MREQ RD                    | Memory read from 000 -> CB\n#011H T7  AB:000 DB:CB          MREQ RD                    | Memory read from 000 -> CB\n#012H T8  AB:000 DB:--                                     | \n#013H T9  AB:000 DB:--                                     | \n#014H T10 AB:000 DB:4B          MREQ                       | \n#015H T11 AB:000 DB:4B          MREQ    WR                 | Memory write to  000 <- 4B\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"BF\">Opcode: CB BF => RES 7,A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:BF  M1      MREQ RD                    | Opcode read from 001 -> BF\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"C0\">Opcode: CB C0 => SET 0,B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:C0  M1      MREQ RD                    | Opcode read from 001 -> C0\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"C1\">Opcode: CB C1 => SET 0,C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:C1  M1      MREQ RD                    | Opcode read from 001 -> C1\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"C2\">Opcode: CB C2 => SET 0,D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:C2  M1      MREQ RD                    | Opcode read from 001 -> C2\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"C3\">Opcode: CB C3 => SET 0,E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:C3  M1      MREQ RD                    | Opcode read from 001 -> C3\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"C4\">Opcode: CB C4 => SET 0,H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:C4  M1      MREQ RD                    | Opcode read from 001 -> C4\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"C5\">Opcode: CB C5 => SET 0,L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:C5  M1      MREQ RD                    | Opcode read from 001 -> C5\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"C6\">Opcode: CB C6 => SET 0,(HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:C6  M1      MREQ RD                    | Opcode read from 001 -> C6\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:001 DB:--                                     | \n#010H T6  AB:001 DB:C6          MREQ RD                    | Memory read from 001 -> C6\n#011H T7  AB:001 DB:C6          MREQ RD                    | Memory read from 001 -> C6\n#012H T8  AB:001 DB:--                                     | \n#013H T9  AB:001 DB:--                                     | \n#014H T10 AB:001 DB:C7          MREQ                       | \n#015H T11 AB:001 DB:C7          MREQ    WR                 | Memory write to  001 <- C7\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"C7\">Opcode: CB C7 => SET 0,A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:C7  M1      MREQ RD                    | Opcode read from 001 -> C7\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"C8\">Opcode: CB C8 => SET 1,B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:C8  M1      MREQ RD                    | Opcode read from 001 -> C8\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"C9\">Opcode: CB C9 => SET 1,C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:C9  M1      MREQ RD                    | Opcode read from 001 -> C9\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"CA\">Opcode: CB CA => SET 1,D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CA  M1      MREQ RD                    | Opcode read from 001 -> CA\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"CB\">Opcode: CB CB => SET 1,E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"CC\">Opcode: CB CC => SET 1,H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CC  M1      MREQ RD                    | Opcode read from 001 -> CC\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"CD\">Opcode: CB CD => SET 1,L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CD  M1      MREQ RD                    | Opcode read from 001 -> CD\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"CE\">Opcode: CB CE => SET 1,(HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CE  M1      MREQ RD                    | Opcode read from 001 -> CE\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:003 DB:--                                     | \n#010H T6  AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#011H T7  AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:--                                     | \n#014H T10 AB:003 DB:02          MREQ                       | \n#015H T11 AB:003 DB:02          MREQ    WR                 | Memory write to  003 <- 02\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"CF\">Opcode: CB CF => SET 1,A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CF  M1      MREQ RD                    | Opcode read from 001 -> CF\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"D0\">Opcode: CB D0 => SET 2,B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:D0  M1      MREQ RD                    | Opcode read from 001 -> D0\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"D1\">Opcode: CB D1 => SET 2,C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:D1  M1      MREQ RD                    | Opcode read from 001 -> D1\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"D2\">Opcode: CB D2 => SET 2,D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:D2  M1      MREQ RD                    | Opcode read from 001 -> D2\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"D3\">Opcode: CB D3 => SET 2,E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:D3  M1      MREQ RD                    | Opcode read from 001 -> D3\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"D4\">Opcode: CB D4 => SET 2,H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:D4  M1      MREQ RD                    | Opcode read from 001 -> D4\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"D5\">Opcode: CB D5 => SET 2,L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:D5  M1      MREQ RD                    | Opcode read from 001 -> D5\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"D6\">Opcode: CB D6 => SET 2,(HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:D6  M1      MREQ RD                    | Opcode read from 001 -> D6\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:007 DB:--                                     | \n#010H T6  AB:007 DB:06          MREQ RD                    | Memory read from 007 -> 06\n#011H T7  AB:007 DB:06          MREQ RD                    | Memory read from 007 -> 06\n#012H T8  AB:007 DB:--                                     | \n#013H T9  AB:007 DB:--                                     | \n#014H T10 AB:007 DB:06          MREQ                       | \n#015H T11 AB:007 DB:06          MREQ    WR                 | Memory write to  007 <- 06\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"D7\">Opcode: CB D7 => SET 2,A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:D7  M1      MREQ RD                    | Opcode read from 001 -> D7\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"D8\">Opcode: CB D8 => SET 3,B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:D8  M1      MREQ RD                    | Opcode read from 001 -> D8\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"D9\">Opcode: CB D9 => SET 3,C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:D9  M1      MREQ RD                    | Opcode read from 001 -> D9\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"DA\">Opcode: CB DA => SET 3,D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:DA  M1      MREQ RD                    | Opcode read from 001 -> DA\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"DB\">Opcode: CB DB => SET 3,E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:DB  M1      MREQ RD                    | Opcode read from 001 -> DB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"DC\">Opcode: CB DC => SET 3,H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:DC  M1      MREQ RD                    | Opcode read from 001 -> DC\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"DD\">Opcode: CB DD => SET 3,L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:DD  M1      MREQ RD                    | Opcode read from 001 -> DD\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"DE\">Opcode: CB DE => SET 3,(HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:DE  M1      MREQ RD                    | Opcode read from 001 -> DE\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:00F DB:--                                     | \n#010H T6  AB:00F DB:00          MREQ RD                    | Memory read from 00F -> 00\n#011H T7  AB:00F DB:00          MREQ RD                    | Memory read from 00F -> 00\n#012H T8  AB:00F DB:--                                     | \n#013H T9  AB:00F DB:--                                     | \n#014H T10 AB:00F DB:08          MREQ                       | \n#015H T11 AB:00F DB:08          MREQ    WR                 | Memory write to  00F <- 08\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"DF\">Opcode: CB DF => SET 3,A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:DF  M1      MREQ RD                    | Opcode read from 001 -> DF\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"E0\">Opcode: CB E0 => SET 4,B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:E0  M1      MREQ RD                    | Opcode read from 001 -> E0\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"E1\">Opcode: CB E1 => SET 4,C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:E1  M1      MREQ RD                    | Opcode read from 001 -> E1\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"E2\">Opcode: CB E2 => SET 4,D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:E2  M1      MREQ RD                    | Opcode read from 001 -> E2\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"E3\">Opcode: CB E3 => SET 4,E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:E3  M1      MREQ RD                    | Opcode read from 001 -> E3\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"E4\">Opcode: CB E4 => SET 4,H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:E4  M1      MREQ RD                    | Opcode read from 001 -> E4\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"E5\">Opcode: CB E5 => SET 4,L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:E5  M1      MREQ RD                    | Opcode read from 001 -> E5\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"E6\">Opcode: CB E6 => SET 4,(HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:E6  M1      MREQ RD                    | Opcode read from 001 -> E6\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:01F DB:--                                     | \n#010H T6  AB:01F DB:00          MREQ RD                    | Memory read from 01F -> 00\n#011H T7  AB:01F DB:00          MREQ RD                    | Memory read from 01F -> 00\n#012H T8  AB:01F DB:--                                     | \n#013H T9  AB:01F DB:--                                     | \n#014H T10 AB:01F DB:10          MREQ                       | \n#015H T11 AB:01F DB:10          MREQ    WR                 | Memory write to  01F <- 10\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"E7\">Opcode: CB E7 => SET 4,A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:E7  M1      MREQ RD                    | Opcode read from 001 -> E7\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"E8\">Opcode: CB E8 => SET 5,B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:E8  M1      MREQ RD                    | Opcode read from 001 -> E8\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"E9\">Opcode: CB E9 => SET 5,C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:E9  M1      MREQ RD                    | Opcode read from 001 -> E9\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"EA\">Opcode: CB EA => SET 5,D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:EA  M1      MREQ RD                    | Opcode read from 001 -> EA\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"EB\">Opcode: CB EB => SET 5,E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:EB  M1      MREQ RD                    | Opcode read from 001 -> EB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"EC\">Opcode: CB EC => SET 5,H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:EC  M1      MREQ RD                    | Opcode read from 001 -> EC\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"ED\">Opcode: CB ED => SET 5,L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:ED  M1      MREQ RD                    | Opcode read from 001 -> ED\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"EE\">Opcode: CB EE => SET 5,(HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:EE  M1      MREQ RD                    | Opcode read from 001 -> EE\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:03F DB:--                                     | \n#010H T6  AB:03F DB:00          MREQ RD                    | Memory read from 03F -> 00\n#011H T7  AB:03F DB:00          MREQ RD                    | Memory read from 03F -> 00\n#012H T8  AB:03F DB:--                                     | \n#013H T9  AB:03F DB:--                                     | \n#014H T10 AB:03F DB:20          MREQ                       | \n#015H T11 AB:03F DB:20          MREQ    WR                 | Memory write to  03F <- 20\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"EF\">Opcode: CB EF => SET 5,A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:EF  M1      MREQ RD                    | Opcode read from 001 -> EF\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"F0\">Opcode: CB F0 => SET 6,B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:F0  M1      MREQ RD                    | Opcode read from 001 -> F0\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"F1\">Opcode: CB F1 => SET 6,C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:F1  M1      MREQ RD                    | Opcode read from 001 -> F1\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"F2\">Opcode: CB F2 => SET 6,D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:F2  M1      MREQ RD                    | Opcode read from 001 -> F2\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"F3\">Opcode: CB F3 => SET 6,E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:F3  M1      MREQ RD                    | Opcode read from 001 -> F3\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"F4\">Opcode: CB F4 => SET 6,H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:F4  M1      MREQ RD                    | Opcode read from 001 -> F4\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"F5\">Opcode: CB F5 => SET 6,L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:F5  M1      MREQ RD                    | Opcode read from 001 -> F5\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"F6\">Opcode: CB F6 => SET 6,(HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:F6  M1      MREQ RD                    | Opcode read from 001 -> F6\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:07F DB:--                                     | \n#010H T6  AB:07F DB:00          MREQ RD                    | Memory read from 07F -> 00\n#011H T7  AB:07F DB:00          MREQ RD                    | Memory read from 07F -> 00\n#012H T8  AB:07F DB:--                                     | \n#013H T9  AB:07F DB:--                                     | \n#014H T10 AB:07F DB:40          MREQ                       | \n#015H T11 AB:07F DB:40          MREQ    WR                 | Memory write to  07F <- 40\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"F7\">Opcode: CB F7 => SET 6,A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:F7  M1      MREQ RD                    | Opcode read from 001 -> F7\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"F8\">Opcode: CB F8 => SET 7,B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:F8  M1      MREQ RD                    | Opcode read from 001 -> F8\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"F9\">Opcode: CB F9 => SET 7,C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:F9  M1      MREQ RD                    | Opcode read from 001 -> F9\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"FA\">Opcode: CB FA => SET 7,D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:FA  M1      MREQ RD                    | Opcode read from 001 -> FA\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"FB\">Opcode: CB FB => SET 7,E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:FB  M1      MREQ RD                    | Opcode read from 001 -> FB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"FC\">Opcode: CB FC => SET 7,H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:FC  M1      MREQ RD                    | Opcode read from 001 -> FC\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"FD\">Opcode: CB FD => SET 7,L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:FD  M1      MREQ RD                    | Opcode read from 001 -> FD\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"FE\">Opcode: CB FE => SET 7,(HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:FE  M1      MREQ RD                    | Opcode read from 001 -> FE\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:0FF DB:--                                     | \n#010H T6  AB:0FF DB:00          MREQ RD                    | Memory read from 0FF -> 00\n#011H T7  AB:0FF DB:00          MREQ RD                    | Memory read from 0FF -> 00\n#012H T8  AB:0FF DB:--                                     | \n#013H T9  AB:0FF DB:--                                     | \n#014H T10 AB:0FF DB:80          MREQ                       | \n#015H T11 AB:0FF DB:80          MREQ    WR                 | Memory write to  0FF <- 80\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"FF\">Opcode: CB FF => SET 7,A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:FF  M1      MREQ RD                    | Opcode read from 001 -> FF\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n</BODY></HTML>\n"
  },
  {
    "path": "tools/dongle/daa/daa-concise.txt",
    "content": "F:00 A:00 -> 00 F:44\nF:00 A:01 -> 01 F:00\nF:00 A:02 -> 02 F:00\nF:00 A:03 -> 03 F:04\nF:00 A:04 -> 04 F:00\nF:00 A:05 -> 05 F:04\nF:00 A:06 -> 06 F:04\nF:00 A:07 -> 07 F:00\nF:00 A:08 -> 08 F:08\nF:00 A:09 -> 09 F:0C\nF:00 A:0A -> 10 F:10\nF:00 A:0B -> 11 F:14\nF:00 A:0C -> 12 F:14\nF:00 A:0D -> 13 F:10\nF:00 A:0E -> 14 F:14\nF:00 A:0F -> 15 F:10\nF:00 A:10 -> 10 F:00\nF:00 A:11 -> 11 F:04\nF:00 A:12 -> 12 F:04\nF:00 A:13 -> 13 F:00\nF:00 A:14 -> 14 F:04\nF:00 A:15 -> 15 F:00\nF:00 A:16 -> 16 F:00\nF:00 A:17 -> 17 F:04\nF:00 A:18 -> 18 F:0C\nF:00 A:19 -> 19 F:08\nF:00 A:1A -> 20 F:30\nF:00 A:1B -> 21 F:34\nF:00 A:1C -> 22 F:34\nF:00 A:1D -> 23 F:30\nF:00 A:1E -> 24 F:34\nF:00 A:1F -> 25 F:30\nF:00 A:20 -> 20 F:20\nF:00 A:21 -> 21 F:24\nF:00 A:22 -> 22 F:24\nF:00 A:23 -> 23 F:20\nF:00 A:24 -> 24 F:24\nF:00 A:25 -> 25 F:20\nF:00 A:26 -> 26 F:20\nF:00 A:27 -> 27 F:24\nF:00 A:28 -> 28 F:2C\nF:00 A:29 -> 29 F:28\nF:00 A:2A -> 30 F:34\nF:00 A:2B -> 31 F:30\nF:00 A:2C -> 32 F:30\nF:00 A:2D -> 33 F:34\nF:00 A:2E -> 34 F:30\nF:00 A:2F -> 35 F:34\nF:00 A:30 -> 30 F:24\nF:00 A:31 -> 31 F:20\nF:00 A:32 -> 32 F:20\nF:00 A:33 -> 33 F:24\nF:00 A:34 -> 34 F:20\nF:00 A:35 -> 35 F:24\nF:00 A:36 -> 36 F:24\nF:00 A:37 -> 37 F:20\nF:00 A:38 -> 38 F:28\nF:00 A:39 -> 39 F:2C\nF:00 A:3A -> 40 F:10\nF:00 A:3B -> 41 F:14\nF:00 A:3C -> 42 F:14\nF:00 A:3D -> 43 F:10\nF:00 A:3E -> 44 F:14\nF:00 A:3F -> 45 F:10\nF:00 A:40 -> 40 F:00\nF:00 A:41 -> 41 F:04\nF:00 A:42 -> 42 F:04\nF:00 A:43 -> 43 F:00\nF:00 A:44 -> 44 F:04\nF:00 A:45 -> 45 F:00\nF:00 A:46 -> 46 F:00\nF:00 A:47 -> 47 F:04\nF:00 A:48 -> 48 F:0C\nF:00 A:49 -> 49 F:08\nF:00 A:4A -> 50 F:14\nF:00 A:4B -> 51 F:10\nF:00 A:4C -> 52 F:10\nF:00 A:4D -> 53 F:14\nF:00 A:4E -> 54 F:10\nF:00 A:4F -> 55 F:14\nF:00 A:50 -> 50 F:04\nF:00 A:51 -> 51 F:00\nF:00 A:52 -> 52 F:00\nF:00 A:53 -> 53 F:04\nF:00 A:54 -> 54 F:00\nF:00 A:55 -> 55 F:04\nF:00 A:56 -> 56 F:04\nF:00 A:57 -> 57 F:00\nF:00 A:58 -> 58 F:08\nF:00 A:59 -> 59 F:0C\nF:00 A:5A -> 60 F:34\nF:00 A:5B -> 61 F:30\nF:00 A:5C -> 62 F:30\nF:00 A:5D -> 63 F:34\nF:00 A:5E -> 64 F:30\nF:00 A:5F -> 65 F:34\nF:00 A:60 -> 60 F:24\nF:00 A:61 -> 61 F:20\nF:00 A:62 -> 62 F:20\nF:00 A:63 -> 63 F:24\nF:00 A:64 -> 64 F:20\nF:00 A:65 -> 65 F:24\nF:00 A:66 -> 66 F:24\nF:00 A:67 -> 67 F:20\nF:00 A:68 -> 68 F:28\nF:00 A:69 -> 69 F:2C\nF:00 A:6A -> 70 F:30\nF:00 A:6B -> 71 F:34\nF:00 A:6C -> 72 F:34\nF:00 A:6D -> 73 F:30\nF:00 A:6E -> 74 F:34\nF:00 A:6F -> 75 F:30\nF:00 A:70 -> 70 F:20\nF:00 A:71 -> 71 F:24\nF:00 A:72 -> 72 F:24\nF:00 A:73 -> 73 F:20\nF:00 A:74 -> 74 F:24\nF:00 A:75 -> 75 F:20\nF:00 A:76 -> 76 F:20\nF:00 A:77 -> 77 F:24\nF:00 A:78 -> 78 F:2C\nF:00 A:79 -> 79 F:28\nF:00 A:7A -> 80 F:90\nF:00 A:7B -> 81 F:94\nF:00 A:7C -> 82 F:94\nF:00 A:7D -> 83 F:90\nF:00 A:7E -> 84 F:94\nF:00 A:7F -> 85 F:90\nF:00 A:80 -> 80 F:80\nF:00 A:81 -> 81 F:84\nF:00 A:82 -> 82 F:84\nF:00 A:83 -> 83 F:80\nF:00 A:84 -> 84 F:84\nF:00 A:85 -> 85 F:80\nF:00 A:86 -> 86 F:80\nF:00 A:87 -> 87 F:84\nF:00 A:88 -> 88 F:8C\nF:00 A:89 -> 89 F:88\nF:00 A:8A -> 90 F:94\nF:00 A:8B -> 91 F:90\nF:00 A:8C -> 92 F:90\nF:00 A:8D -> 93 F:94\nF:00 A:8E -> 94 F:90\nF:00 A:8F -> 95 F:94\nF:00 A:90 -> 90 F:84\nF:00 A:91 -> 91 F:80\nF:00 A:92 -> 92 F:80\nF:00 A:93 -> 93 F:84\nF:00 A:94 -> 94 F:80\nF:00 A:95 -> 95 F:84\nF:00 A:96 -> 96 F:84\nF:00 A:97 -> 97 F:80\nF:00 A:98 -> 98 F:88\nF:00 A:99 -> 99 F:8C\nF:00 A:9A -> 00 F:55\nF:00 A:9B -> 01 F:11\nF:00 A:9C -> 02 F:11\nF:00 A:9D -> 03 F:15\nF:00 A:9E -> 04 F:11\nF:00 A:9F -> 05 F:15\nF:00 A:A0 -> 00 F:45\nF:00 A:A1 -> 01 F:01\nF:00 A:A2 -> 02 F:01\nF:00 A:A3 -> 03 F:05\nF:00 A:A4 -> 04 F:01\nF:00 A:A5 -> 05 F:05\nF:00 A:A6 -> 06 F:05\nF:00 A:A7 -> 07 F:01\nF:00 A:A8 -> 08 F:09\nF:00 A:A9 -> 09 F:0D\nF:00 A:AA -> 10 F:11\nF:00 A:AB -> 11 F:15\nF:00 A:AC -> 12 F:15\nF:00 A:AD -> 13 F:11\nF:00 A:AE -> 14 F:15\nF:00 A:AF -> 15 F:11\nF:00 A:B0 -> 10 F:01\nF:00 A:B1 -> 11 F:05\nF:00 A:B2 -> 12 F:05\nF:00 A:B3 -> 13 F:01\nF:00 A:B4 -> 14 F:05\nF:00 A:B5 -> 15 F:01\nF:00 A:B6 -> 16 F:01\nF:00 A:B7 -> 17 F:05\nF:00 A:B8 -> 18 F:0D\nF:00 A:B9 -> 19 F:09\nF:00 A:BA -> 20 F:31\nF:00 A:BB -> 21 F:35\nF:00 A:BC -> 22 F:35\nF:00 A:BD -> 23 F:31\nF:00 A:BE -> 24 F:35\nF:00 A:BF -> 25 F:31\nF:00 A:C0 -> 20 F:21\nF:00 A:C1 -> 21 F:25\nF:00 A:C2 -> 22 F:25\nF:00 A:C3 -> 23 F:21\nF:00 A:C4 -> 24 F:25\nF:00 A:C5 -> 25 F:21\nF:00 A:C6 -> 26 F:21\nF:00 A:C7 -> 27 F:25\nF:00 A:C8 -> 28 F:2D\nF:00 A:C9 -> 29 F:29\nF:00 A:CA -> 30 F:35\nF:00 A:CB -> 31 F:31\nF:00 A:CC -> 32 F:31\nF:00 A:CD -> 33 F:35\nF:00 A:CE -> 34 F:31\nF:00 A:CF -> 35 F:35\nF:00 A:D0 -> 30 F:25\nF:00 A:D1 -> 31 F:21\nF:00 A:D2 -> 32 F:21\nF:00 A:D3 -> 33 F:25\nF:00 A:D4 -> 34 F:21\nF:00 A:D5 -> 35 F:25\nF:00 A:D6 -> 36 F:25\nF:00 A:D7 -> 37 F:21\nF:00 A:D8 -> 38 F:29\nF:00 A:D9 -> 39 F:2D\nF:00 A:DA -> 40 F:11\nF:00 A:DB -> 41 F:15\nF:00 A:DC -> 42 F:15\nF:00 A:DD -> 43 F:11\nF:00 A:DE -> 44 F:15\nF:00 A:DF -> 45 F:11\nF:00 A:E0 -> 40 F:01\nF:00 A:E1 -> 41 F:05\nF:00 A:E2 -> 42 F:05\nF:00 A:E3 -> 43 F:01\nF:00 A:E4 -> 44 F:05\nF:00 A:E5 -> 45 F:01\nF:00 A:E6 -> 46 F:01\nF:00 A:E7 -> 47 F:05\nF:00 A:E8 -> 48 F:0D\nF:00 A:E9 -> 49 F:09\nF:00 A:EA -> 50 F:15\nF:00 A:EB -> 51 F:11\nF:00 A:EC -> 52 F:11\nF:00 A:ED -> 53 F:15\nF:00 A:EE -> 54 F:11\nF:00 A:EF -> 55 F:15\nF:00 A:F0 -> 50 F:05\nF:00 A:F1 -> 51 F:01\nF:00 A:F2 -> 52 F:01\nF:00 A:F3 -> 53 F:05\nF:00 A:F4 -> 54 F:01\nF:00 A:F5 -> 55 F:05\nF:00 A:F6 -> 56 F:05\nF:00 A:F7 -> 57 F:01\nF:00 A:F8 -> 58 F:09\nF:00 A:F9 -> 59 F:0D\nF:00 A:FA -> 60 F:35\nF:00 A:FB -> 61 F:31\nF:00 A:FC -> 62 F:31\nF:00 A:FD -> 63 F:35\nF:00 A:FE -> 64 F:31\nF:00 A:FF -> 65 F:35\nF:01 A:00 -> 60 F:25\nF:01 A:01 -> 61 F:21\nF:01 A:02 -> 62 F:21\nF:01 A:03 -> 63 F:25\nF:01 A:04 -> 64 F:21\nF:01 A:05 -> 65 F:25\nF:01 A:06 -> 66 F:25\nF:01 A:07 -> 67 F:21\nF:01 A:08 -> 68 F:29\nF:01 A:09 -> 69 F:2D\nF:01 A:0A -> 70 F:31\nF:01 A:0B -> 71 F:35\nF:01 A:0C -> 72 F:35\nF:01 A:0D -> 73 F:31\nF:01 A:0E -> 74 F:35\nF:01 A:0F -> 75 F:31\nF:01 A:10 -> 70 F:21\nF:01 A:11 -> 71 F:25\nF:01 A:12 -> 72 F:25\nF:01 A:13 -> 73 F:21\nF:01 A:14 -> 74 F:25\nF:01 A:15 -> 75 F:21\nF:01 A:16 -> 76 F:21\nF:01 A:17 -> 77 F:25\nF:01 A:18 -> 78 F:2D\nF:01 A:19 -> 79 F:29\nF:01 A:1A -> 80 F:91\nF:01 A:1B -> 81 F:95\nF:01 A:1C -> 82 F:95\nF:01 A:1D -> 83 F:91\nF:01 A:1E -> 84 F:95\nF:01 A:1F -> 85 F:91\nF:01 A:20 -> 80 F:81\nF:01 A:21 -> 81 F:85\nF:01 A:22 -> 82 F:85\nF:01 A:23 -> 83 F:81\nF:01 A:24 -> 84 F:85\nF:01 A:25 -> 85 F:81\nF:01 A:26 -> 86 F:81\nF:01 A:27 -> 87 F:85\nF:01 A:28 -> 88 F:8D\nF:01 A:29 -> 89 F:89\nF:01 A:2A -> 90 F:95\nF:01 A:2B -> 91 F:91\nF:01 A:2C -> 92 F:91\nF:01 A:2D -> 93 F:95\nF:01 A:2E -> 94 F:91\nF:01 A:2F -> 95 F:95\nF:01 A:30 -> 90 F:85\nF:01 A:31 -> 91 F:81\nF:01 A:32 -> 92 F:81\nF:01 A:33 -> 93 F:85\nF:01 A:34 -> 94 F:81\nF:01 A:35 -> 95 F:85\nF:01 A:36 -> 96 F:85\nF:01 A:37 -> 97 F:81\nF:01 A:38 -> 98 F:89\nF:01 A:39 -> 99 F:8D\nF:01 A:3A -> A0 F:B5\nF:01 A:3B -> A1 F:B1\nF:01 A:3C -> A2 F:B1\nF:01 A:3D -> A3 F:B5\nF:01 A:3E -> A4 F:B1\nF:01 A:3F -> A5 F:B5\nF:01 A:40 -> A0 F:A5\nF:01 A:41 -> A1 F:A1\nF:01 A:42 -> A2 F:A1\nF:01 A:43 -> A3 F:A5\nF:01 A:44 -> A4 F:A1\nF:01 A:45 -> A5 F:A5\nF:01 A:46 -> A6 F:A5\nF:01 A:47 -> A7 F:A1\nF:01 A:48 -> A8 F:A9\nF:01 A:49 -> A9 F:AD\nF:01 A:4A -> B0 F:B1\nF:01 A:4B -> B1 F:B5\nF:01 A:4C -> B2 F:B5\nF:01 A:4D -> B3 F:B1\nF:01 A:4E -> B4 F:B5\nF:01 A:4F -> B5 F:B1\nF:01 A:50 -> B0 F:A1\nF:01 A:51 -> B1 F:A5\nF:01 A:52 -> B2 F:A5\nF:01 A:53 -> B3 F:A1\nF:01 A:54 -> B4 F:A5\nF:01 A:55 -> B5 F:A1\nF:01 A:56 -> B6 F:A1\nF:01 A:57 -> B7 F:A5\nF:01 A:58 -> B8 F:AD\nF:01 A:59 -> B9 F:A9\nF:01 A:5A -> C0 F:95\nF:01 A:5B -> C1 F:91\nF:01 A:5C -> C2 F:91\nF:01 A:5D -> C3 F:95\nF:01 A:5E -> C4 F:91\nF:01 A:5F -> C5 F:95\nF:01 A:60 -> C0 F:85\nF:01 A:61 -> C1 F:81\nF:01 A:62 -> C2 F:81\nF:01 A:63 -> C3 F:85\nF:01 A:64 -> C4 F:81\nF:01 A:65 -> C5 F:85\nF:01 A:66 -> C6 F:85\nF:01 A:67 -> C7 F:81\nF:01 A:68 -> C8 F:89\nF:01 A:69 -> C9 F:8D\nF:01 A:6A -> D0 F:91\nF:01 A:6B -> D1 F:95\nF:01 A:6C -> D2 F:95\nF:01 A:6D -> D3 F:91\nF:01 A:6E -> D4 F:95\nF:01 A:6F -> D5 F:91\nF:01 A:70 -> D0 F:81\nF:01 A:71 -> D1 F:85\nF:01 A:72 -> D2 F:85\nF:01 A:73 -> D3 F:81\nF:01 A:74 -> D4 F:85\nF:01 A:75 -> D5 F:81\nF:01 A:76 -> D6 F:81\nF:01 A:77 -> D7 F:85\nF:01 A:78 -> D8 F:8D\nF:01 A:79 -> D9 F:89\nF:01 A:7A -> E0 F:B1\nF:01 A:7B -> E1 F:B5\nF:01 A:7C -> E2 F:B5\nF:01 A:7D -> E3 F:B1\nF:01 A:7E -> E4 F:B5\nF:01 A:7F -> E5 F:B1\nF:01 A:80 -> E0 F:A1\nF:01 A:81 -> E1 F:A5\nF:01 A:82 -> E2 F:A5\nF:01 A:83 -> E3 F:A1\nF:01 A:84 -> E4 F:A5\nF:01 A:85 -> E5 F:A1\nF:01 A:86 -> E6 F:A1\nF:01 A:87 -> E7 F:A5\nF:01 A:88 -> E8 F:AD\nF:01 A:89 -> E9 F:A9\nF:01 A:8A -> F0 F:B5\nF:01 A:8B -> F1 F:B1\nF:01 A:8C -> F2 F:B1\nF:01 A:8D -> F3 F:B5\nF:01 A:8E -> F4 F:B1\nF:01 A:8F -> F5 F:B5\nF:01 A:90 -> F0 F:A5\nF:01 A:91 -> F1 F:A1\nF:01 A:92 -> F2 F:A1\nF:01 A:93 -> F3 F:A5\nF:01 A:94 -> F4 F:A1\nF:01 A:95 -> F5 F:A5\nF:01 A:96 -> F6 F:A5\nF:01 A:97 -> F7 F:A1\nF:01 A:98 -> F8 F:A9\nF:01 A:99 -> F9 F:AD\nF:01 A:9A -> 00 F:55\nF:01 A:9B -> 01 F:11\nF:01 A:9C -> 02 F:11\nF:01 A:9D -> 03 F:15\nF:01 A:9E -> 04 F:11\nF:01 A:9F -> 05 F:15\nF:01 A:A0 -> 00 F:45\nF:01 A:A1 -> 01 F:01\nF:01 A:A2 -> 02 F:01\nF:01 A:A3 -> 03 F:05\nF:01 A:A4 -> 04 F:01\nF:01 A:A5 -> 05 F:05\nF:01 A:A6 -> 06 F:05\nF:01 A:A7 -> 07 F:01\nF:01 A:A8 -> 08 F:09\nF:01 A:A9 -> 09 F:0D\nF:01 A:AA -> 10 F:11\nF:01 A:AB -> 11 F:15\nF:01 A:AC -> 12 F:15\nF:01 A:AD -> 13 F:11\nF:01 A:AE -> 14 F:15\nF:01 A:AF -> 15 F:11\nF:01 A:B0 -> 10 F:01\nF:01 A:B1 -> 11 F:05\nF:01 A:B2 -> 12 F:05\nF:01 A:B3 -> 13 F:01\nF:01 A:B4 -> 14 F:05\nF:01 A:B5 -> 15 F:01\nF:01 A:B6 -> 16 F:01\nF:01 A:B7 -> 17 F:05\nF:01 A:B8 -> 18 F:0D\nF:01 A:B9 -> 19 F:09\nF:01 A:BA -> 20 F:31\nF:01 A:BB -> 21 F:35\nF:01 A:BC -> 22 F:35\nF:01 A:BD -> 23 F:31\nF:01 A:BE -> 24 F:35\nF:01 A:BF -> 25 F:31\nF:01 A:C0 -> 20 F:21\nF:01 A:C1 -> 21 F:25\nF:01 A:C2 -> 22 F:25\nF:01 A:C3 -> 23 F:21\nF:01 A:C4 -> 24 F:25\nF:01 A:C5 -> 25 F:21\nF:01 A:C6 -> 26 F:21\nF:01 A:C7 -> 27 F:25\nF:01 A:C8 -> 28 F:2D\nF:01 A:C9 -> 29 F:29\nF:01 A:CA -> 30 F:35\nF:01 A:CB -> 31 F:31\nF:01 A:CC -> 32 F:31\nF:01 A:CD -> 33 F:35\nF:01 A:CE -> 34 F:31\nF:01 A:CF -> 35 F:35\nF:01 A:D0 -> 30 F:25\nF:01 A:D1 -> 31 F:21\nF:01 A:D2 -> 32 F:21\nF:01 A:D3 -> 33 F:25\nF:01 A:D4 -> 34 F:21\nF:01 A:D5 -> 35 F:25\nF:01 A:D6 -> 36 F:25\nF:01 A:D7 -> 37 F:21\nF:01 A:D8 -> 38 F:29\nF:01 A:D9 -> 39 F:2D\nF:01 A:DA -> 40 F:11\nF:01 A:DB -> 41 F:15\nF:01 A:DC -> 42 F:15\nF:01 A:DD -> 43 F:11\nF:01 A:DE -> 44 F:15\nF:01 A:DF -> 45 F:11\nF:01 A:E0 -> 40 F:01\nF:01 A:E1 -> 41 F:05\nF:01 A:E2 -> 42 F:05\nF:01 A:E3 -> 43 F:01\nF:01 A:E4 -> 44 F:05\nF:01 A:E5 -> 45 F:01\nF:01 A:E6 -> 46 F:01\nF:01 A:E7 -> 47 F:05\nF:01 A:E8 -> 48 F:0D\nF:01 A:E9 -> 49 F:09\nF:01 A:EA -> 50 F:15\nF:01 A:EB -> 51 F:11\nF:01 A:EC -> 52 F:11\nF:01 A:ED -> 53 F:15\nF:01 A:EE -> 54 F:11\nF:01 A:EF -> 55 F:15\nF:01 A:F0 -> 50 F:05\nF:01 A:F1 -> 51 F:01\nF:01 A:F2 -> 52 F:01\nF:01 A:F3 -> 53 F:05\nF:01 A:F4 -> 54 F:01\nF:01 A:F5 -> 55 F:05\nF:01 A:F6 -> 56 F:05\nF:01 A:F7 -> 57 F:01\nF:01 A:F8 -> 58 F:09\nF:01 A:F9 -> 59 F:0D\nF:01 A:FA -> 60 F:35\nF:01 A:FB -> 61 F:31\nF:01 A:FC -> 62 F:31\nF:01 A:FD -> 63 F:35\nF:01 A:FE -> 64 F:31\nF:01 A:FF -> 65 F:35\nF:10 A:00 -> 06 F:04\nF:10 A:01 -> 07 F:00\nF:10 A:02 -> 08 F:08\nF:10 A:03 -> 09 F:0C\nF:10 A:04 -> 0A F:0C\nF:10 A:05 -> 0B F:08\nF:10 A:06 -> 0C F:0C\nF:10 A:07 -> 0D F:08\nF:10 A:08 -> 0E F:08\nF:10 A:09 -> 0F F:0C\nF:10 A:0A -> 10 F:10\nF:10 A:0B -> 11 F:14\nF:10 A:0C -> 12 F:14\nF:10 A:0D -> 13 F:10\nF:10 A:0E -> 14 F:14\nF:10 A:0F -> 15 F:10\nF:10 A:10 -> 16 F:00\nF:10 A:11 -> 17 F:04\nF:10 A:12 -> 18 F:0C\nF:10 A:13 -> 19 F:08\nF:10 A:14 -> 1A F:08\nF:10 A:15 -> 1B F:0C\nF:10 A:16 -> 1C F:08\nF:10 A:17 -> 1D F:0C\nF:10 A:18 -> 1E F:0C\nF:10 A:19 -> 1F F:08\nF:10 A:1A -> 20 F:30\nF:10 A:1B -> 21 F:34\nF:10 A:1C -> 22 F:34\nF:10 A:1D -> 23 F:30\nF:10 A:1E -> 24 F:34\nF:10 A:1F -> 25 F:30\nF:10 A:20 -> 26 F:20\nF:10 A:21 -> 27 F:24\nF:10 A:22 -> 28 F:2C\nF:10 A:23 -> 29 F:28\nF:10 A:24 -> 2A F:28\nF:10 A:25 -> 2B F:2C\nF:10 A:26 -> 2C F:28\nF:10 A:27 -> 2D F:2C\nF:10 A:28 -> 2E F:2C\nF:10 A:29 -> 2F F:28\nF:10 A:2A -> 30 F:34\nF:10 A:2B -> 31 F:30\nF:10 A:2C -> 32 F:30\nF:10 A:2D -> 33 F:34\nF:10 A:2E -> 34 F:30\nF:10 A:2F -> 35 F:34\nF:10 A:30 -> 36 F:24\nF:10 A:31 -> 37 F:20\nF:10 A:32 -> 38 F:28\nF:10 A:33 -> 39 F:2C\nF:10 A:34 -> 3A F:2C\nF:10 A:35 -> 3B F:28\nF:10 A:36 -> 3C F:2C\nF:10 A:37 -> 3D F:28\nF:10 A:38 -> 3E F:28\nF:10 A:39 -> 3F F:2C\nF:10 A:3A -> 40 F:10\nF:10 A:3B -> 41 F:14\nF:10 A:3C -> 42 F:14\nF:10 A:3D -> 43 F:10\nF:10 A:3E -> 44 F:14\nF:10 A:3F -> 45 F:10\nF:10 A:40 -> 46 F:00\nF:10 A:41 -> 47 F:04\nF:10 A:42 -> 48 F:0C\nF:10 A:43 -> 49 F:08\nF:10 A:44 -> 4A F:08\nF:10 A:45 -> 4B F:0C\nF:10 A:46 -> 4C F:08\nF:10 A:47 -> 4D F:0C\nF:10 A:48 -> 4E F:0C\nF:10 A:49 -> 4F F:08\nF:10 A:4A -> 50 F:14\nF:10 A:4B -> 51 F:10\nF:10 A:4C -> 52 F:10\nF:10 A:4D -> 53 F:14\nF:10 A:4E -> 54 F:10\nF:10 A:4F -> 55 F:14\nF:10 A:50 -> 56 F:04\nF:10 A:51 -> 57 F:00\nF:10 A:52 -> 58 F:08\nF:10 A:53 -> 59 F:0C\nF:10 A:54 -> 5A F:0C\nF:10 A:55 -> 5B F:08\nF:10 A:56 -> 5C F:0C\nF:10 A:57 -> 5D F:08\nF:10 A:58 -> 5E F:08\nF:10 A:59 -> 5F F:0C\nF:10 A:5A -> 60 F:34\nF:10 A:5B -> 61 F:30\nF:10 A:5C -> 62 F:30\nF:10 A:5D -> 63 F:34\nF:10 A:5E -> 64 F:30\nF:10 A:5F -> 65 F:34\nF:10 A:60 -> 66 F:24\nF:10 A:61 -> 67 F:20\nF:10 A:62 -> 68 F:28\nF:10 A:63 -> 69 F:2C\nF:10 A:64 -> 6A F:2C\nF:10 A:65 -> 6B F:28\nF:10 A:66 -> 6C F:2C\nF:10 A:67 -> 6D F:28\nF:10 A:68 -> 6E F:28\nF:10 A:69 -> 6F F:2C\nF:10 A:6A -> 70 F:30\nF:10 A:6B -> 71 F:34\nF:10 A:6C -> 72 F:34\nF:10 A:6D -> 73 F:30\nF:10 A:6E -> 74 F:34\nF:10 A:6F -> 75 F:30\nF:10 A:70 -> 76 F:20\nF:10 A:71 -> 77 F:24\nF:10 A:72 -> 78 F:2C\nF:10 A:73 -> 79 F:28\nF:10 A:74 -> 7A F:28\nF:10 A:75 -> 7B F:2C\nF:10 A:76 -> 7C F:28\nF:10 A:77 -> 7D F:2C\nF:10 A:78 -> 7E F:2C\nF:10 A:79 -> 7F F:28\nF:10 A:7A -> 80 F:90\nF:10 A:7B -> 81 F:94\nF:10 A:7C -> 82 F:94\nF:10 A:7D -> 83 F:90\nF:10 A:7E -> 84 F:94\nF:10 A:7F -> 85 F:90\nF:10 A:80 -> 86 F:80\nF:10 A:81 -> 87 F:84\nF:10 A:82 -> 88 F:8C\nF:10 A:83 -> 89 F:88\nF:10 A:84 -> 8A F:88\nF:10 A:85 -> 8B F:8C\nF:10 A:86 -> 8C F:88\nF:10 A:87 -> 8D F:8C\nF:10 A:88 -> 8E F:8C\nF:10 A:89 -> 8F F:88\nF:10 A:8A -> 90 F:94\nF:10 A:8B -> 91 F:90\nF:10 A:8C -> 92 F:90\nF:10 A:8D -> 93 F:94\nF:10 A:8E -> 94 F:90\nF:10 A:8F -> 95 F:94\nF:10 A:90 -> 96 F:84\nF:10 A:91 -> 97 F:80\nF:10 A:92 -> 98 F:88\nF:10 A:93 -> 99 F:8C\nF:10 A:94 -> 9A F:8C\nF:10 A:95 -> 9B F:88\nF:10 A:96 -> 9C F:8C\nF:10 A:97 -> 9D F:88\nF:10 A:98 -> 9E F:88\nF:10 A:99 -> 9F F:8C\nF:10 A:9A -> 00 F:55\nF:10 A:9B -> 01 F:11\nF:10 A:9C -> 02 F:11\nF:10 A:9D -> 03 F:15\nF:10 A:9E -> 04 F:11\nF:10 A:9F -> 05 F:15\nF:10 A:A0 -> 06 F:05\nF:10 A:A1 -> 07 F:01\nF:10 A:A2 -> 08 F:09\nF:10 A:A3 -> 09 F:0D\nF:10 A:A4 -> 0A F:0D\nF:10 A:A5 -> 0B F:09\nF:10 A:A6 -> 0C F:0D\nF:10 A:A7 -> 0D F:09\nF:10 A:A8 -> 0E F:09\nF:10 A:A9 -> 0F F:0D\nF:10 A:AA -> 10 F:11\nF:10 A:AB -> 11 F:15\nF:10 A:AC -> 12 F:15\nF:10 A:AD -> 13 F:11\nF:10 A:AE -> 14 F:15\nF:10 A:AF -> 15 F:11\nF:10 A:B0 -> 16 F:01\nF:10 A:B1 -> 17 F:05\nF:10 A:B2 -> 18 F:0D\nF:10 A:B3 -> 19 F:09\nF:10 A:B4 -> 1A F:09\nF:10 A:B5 -> 1B F:0D\nF:10 A:B6 -> 1C F:09\nF:10 A:B7 -> 1D F:0D\nF:10 A:B8 -> 1E F:0D\nF:10 A:B9 -> 1F F:09\nF:10 A:BA -> 20 F:31\nF:10 A:BB -> 21 F:35\nF:10 A:BC -> 22 F:35\nF:10 A:BD -> 23 F:31\nF:10 A:BE -> 24 F:35\nF:10 A:BF -> 25 F:31\nF:10 A:C0 -> 26 F:21\nF:10 A:C1 -> 27 F:25\nF:10 A:C2 -> 28 F:2D\nF:10 A:C3 -> 29 F:29\nF:10 A:C4 -> 2A F:29\nF:10 A:C5 -> 2B F:2D\nF:10 A:C6 -> 2C F:29\nF:10 A:C7 -> 2D F:2D\nF:10 A:C8 -> 2E F:2D\nF:10 A:C9 -> 2F F:29\nF:10 A:CA -> 30 F:35\nF:10 A:CB -> 31 F:31\nF:10 A:CC -> 32 F:31\nF:10 A:CD -> 33 F:35\nF:10 A:CE -> 34 F:31\nF:10 A:CF -> 35 F:35\nF:10 A:D0 -> 36 F:25\nF:10 A:D1 -> 37 F:21\nF:10 A:D2 -> 38 F:29\nF:10 A:D3 -> 39 F:2D\nF:10 A:D4 -> 3A F:2D\nF:10 A:D5 -> 3B F:29\nF:10 A:D6 -> 3C F:2D\nF:10 A:D7 -> 3D F:29\nF:10 A:D8 -> 3E F:29\nF:10 A:D9 -> 3F F:2D\nF:10 A:DA -> 40 F:11\nF:10 A:DB -> 41 F:15\nF:10 A:DC -> 42 F:15\nF:10 A:DD -> 43 F:11\nF:10 A:DE -> 44 F:15\nF:10 A:DF -> 45 F:11\nF:10 A:E0 -> 46 F:01\nF:10 A:E1 -> 47 F:05\nF:10 A:E2 -> 48 F:0D\nF:10 A:E3 -> 49 F:09\nF:10 A:E4 -> 4A F:09\nF:10 A:E5 -> 4B F:0D\nF:10 A:E6 -> 4C F:09\nF:10 A:E7 -> 4D F:0D\nF:10 A:E8 -> 4E F:0D\nF:10 A:E9 -> 4F F:09\nF:10 A:EA -> 50 F:15\nF:10 A:EB -> 51 F:11\nF:10 A:EC -> 52 F:11\nF:10 A:ED -> 53 F:15\nF:10 A:EE -> 54 F:11\nF:10 A:EF -> 55 F:15\nF:10 A:F0 -> 56 F:05\nF:10 A:F1 -> 57 F:01\nF:10 A:F2 -> 58 F:09\nF:10 A:F3 -> 59 F:0D\nF:10 A:F4 -> 5A F:0D\nF:10 A:F5 -> 5B F:09\nF:10 A:F6 -> 5C F:0D\nF:10 A:F7 -> 5D F:09\nF:10 A:F8 -> 5E F:09\nF:10 A:F9 -> 5F F:0D\nF:10 A:FA -> 60 F:35\nF:10 A:FB -> 61 F:31\nF:10 A:FC -> 62 F:31\nF:10 A:FD -> 63 F:35\nF:10 A:FE -> 64 F:31\nF:10 A:FF -> 65 F:35\nF:11 A:00 -> 66 F:25\nF:11 A:01 -> 67 F:21\nF:11 A:02 -> 68 F:29\nF:11 A:03 -> 69 F:2D\nF:11 A:04 -> 6A F:2D\nF:11 A:05 -> 6B F:29\nF:11 A:06 -> 6C F:2D\nF:11 A:07 -> 6D F:29\nF:11 A:08 -> 6E F:29\nF:11 A:09 -> 6F F:2D\nF:11 A:0A -> 70 F:31\nF:11 A:0B -> 71 F:35\nF:11 A:0C -> 72 F:35\nF:11 A:0D -> 73 F:31\nF:11 A:0E -> 74 F:35\nF:11 A:0F -> 75 F:31\nF:11 A:10 -> 76 F:21\nF:11 A:11 -> 77 F:25\nF:11 A:12 -> 78 F:2D\nF:11 A:13 -> 79 F:29\nF:11 A:14 -> 7A F:29\nF:11 A:15 -> 7B F:2D\nF:11 A:16 -> 7C F:29\nF:11 A:17 -> 7D F:2D\nF:11 A:18 -> 7E F:2D\nF:11 A:19 -> 7F F:29\nF:11 A:1A -> 80 F:91\nF:11 A:1B -> 81 F:95\nF:11 A:1C -> 82 F:95\nF:11 A:1D -> 83 F:91\nF:11 A:1E -> 84 F:95\nF:11 A:1F -> 85 F:91\nF:11 A:20 -> 86 F:81\nF:11 A:21 -> 87 F:85\nF:11 A:22 -> 88 F:8D\nF:11 A:23 -> 89 F:89\nF:11 A:24 -> 8A F:89\nF:11 A:25 -> 8B F:8D\nF:11 A:26 -> 8C F:89\nF:11 A:27 -> 8D F:8D\nF:11 A:28 -> 8E F:8D\nF:11 A:29 -> 8F F:89\nF:11 A:2A -> 90 F:95\nF:11 A:2B -> 91 F:91\nF:11 A:2C -> 92 F:91\nF:11 A:2D -> 93 F:95\nF:11 A:2E -> 94 F:91\nF:11 A:2F -> 95 F:95\nF:11 A:30 -> 96 F:85\nF:11 A:31 -> 97 F:81\nF:11 A:32 -> 98 F:89\nF:11 A:33 -> 99 F:8D\nF:11 A:34 -> 9A F:8D\nF:11 A:35 -> 9B F:89\nF:11 A:36 -> 9C F:8D\nF:11 A:37 -> 9D F:89\nF:11 A:38 -> 9E F:89\nF:11 A:39 -> 9F F:8D\nF:11 A:3A -> A0 F:B5\nF:11 A:3B -> A1 F:B1\nF:11 A:3C -> A2 F:B1\nF:11 A:3D -> A3 F:B5\nF:11 A:3E -> A4 F:B1\nF:11 A:3F -> A5 F:B5\nF:11 A:40 -> A6 F:A5\nF:11 A:41 -> A7 F:A1\nF:11 A:42 -> A8 F:A9\nF:11 A:43 -> A9 F:AD\nF:11 A:44 -> AA F:AD\nF:11 A:45 -> AB F:A9\nF:11 A:46 -> AC F:AD\nF:11 A:47 -> AD F:A9\nF:11 A:48 -> AE F:A9\nF:11 A:49 -> AF F:AD\nF:11 A:4A -> B0 F:B1\nF:11 A:4B -> B1 F:B5\nF:11 A:4C -> B2 F:B5\nF:11 A:4D -> B3 F:B1\nF:11 A:4E -> B4 F:B5\nF:11 A:4F -> B5 F:B1\nF:11 A:50 -> B6 F:A1\nF:11 A:51 -> B7 F:A5\nF:11 A:52 -> B8 F:AD\nF:11 A:53 -> B9 F:A9\nF:11 A:54 -> BA F:A9\nF:11 A:55 -> BB F:AD\nF:11 A:56 -> BC F:A9\nF:11 A:57 -> BD F:AD\nF:11 A:58 -> BE F:AD\nF:11 A:59 -> BF F:A9\nF:11 A:5A -> C0 F:95\nF:11 A:5B -> C1 F:91\nF:11 A:5C -> C2 F:91\nF:11 A:5D -> C3 F:95\nF:11 A:5E -> C4 F:91\nF:11 A:5F -> C5 F:95\nF:11 A:60 -> C6 F:85\nF:11 A:61 -> C7 F:81\nF:11 A:62 -> C8 F:89\nF:11 A:63 -> C9 F:8D\nF:11 A:64 -> CA F:8D\nF:11 A:65 -> CB F:89\nF:11 A:66 -> CC F:8D\nF:11 A:67 -> CD F:89\nF:11 A:68 -> CE F:89\nF:11 A:69 -> CF F:8D\nF:11 A:6A -> D0 F:91\nF:11 A:6B -> D1 F:95\nF:11 A:6C -> D2 F:95\nF:11 A:6D -> D3 F:91\nF:11 A:6E -> D4 F:95\nF:11 A:6F -> D5 F:91\nF:11 A:70 -> D6 F:81\nF:11 A:71 -> D7 F:85\nF:11 A:72 -> D8 F:8D\nF:11 A:73 -> D9 F:89\nF:11 A:74 -> DA F:89\nF:11 A:75 -> DB F:8D\nF:11 A:76 -> DC F:89\nF:11 A:77 -> DD F:8D\nF:11 A:78 -> DE F:8D\nF:11 A:79 -> DF F:89\nF:11 A:7A -> E0 F:B1\nF:11 A:7B -> E1 F:B5\nF:11 A:7C -> E2 F:B5\nF:11 A:7D -> E3 F:B1\nF:11 A:7E -> E4 F:B5\nF:11 A:7F -> E5 F:B1\nF:11 A:80 -> E6 F:A1\nF:11 A:81 -> E7 F:A5\nF:11 A:82 -> E8 F:AD\nF:11 A:83 -> E9 F:A9\nF:11 A:84 -> EA F:A9\nF:11 A:85 -> EB F:AD\nF:11 A:86 -> EC F:A9\nF:11 A:87 -> ED F:AD\nF:11 A:88 -> EE F:AD\nF:11 A:89 -> EF F:A9\nF:11 A:8A -> F0 F:B5\nF:11 A:8B -> F1 F:B1\nF:11 A:8C -> F2 F:B1\nF:11 A:8D -> F3 F:B5\nF:11 A:8E -> F4 F:B1\nF:11 A:8F -> F5 F:B5\nF:11 A:90 -> F6 F:A5\nF:11 A:91 -> F7 F:A1\nF:11 A:92 -> F8 F:A9\nF:11 A:93 -> F9 F:AD\nF:11 A:94 -> FA F:AD\nF:11 A:95 -> FB F:A9\nF:11 A:96 -> FC F:AD\nF:11 A:97 -> FD F:A9\nF:11 A:98 -> FE F:A9\nF:11 A:99 -> FF F:AD\nF:11 A:9A -> 00 F:55\nF:11 A:9B -> 01 F:11\nF:11 A:9C -> 02 F:11\nF:11 A:9D -> 03 F:15\nF:11 A:9E -> 04 F:11\nF:11 A:9F -> 05 F:15\nF:11 A:A0 -> 06 F:05\nF:11 A:A1 -> 07 F:01\nF:11 A:A2 -> 08 F:09\nF:11 A:A3 -> 09 F:0D\nF:11 A:A4 -> 0A F:0D\nF:11 A:A5 -> 0B F:09\nF:11 A:A6 -> 0C F:0D\nF:11 A:A7 -> 0D F:09\nF:11 A:A8 -> 0E F:09\nF:11 A:A9 -> 0F F:0D\nF:11 A:AA -> 10 F:11\nF:11 A:AB -> 11 F:15\nF:11 A:AC -> 12 F:15\nF:11 A:AD -> 13 F:11\nF:11 A:AE -> 14 F:15\nF:11 A:AF -> 15 F:11\nF:11 A:B0 -> 16 F:01\nF:11 A:B1 -> 17 F:05\nF:11 A:B2 -> 18 F:0D\nF:11 A:B3 -> 19 F:09\nF:11 A:B4 -> 1A F:09\nF:11 A:B5 -> 1B F:0D\nF:11 A:B6 -> 1C F:09\nF:11 A:B7 -> 1D F:0D\nF:11 A:B8 -> 1E F:0D\nF:11 A:B9 -> 1F F:09\nF:11 A:BA -> 20 F:31\nF:11 A:BB -> 21 F:35\nF:11 A:BC -> 22 F:35\nF:11 A:BD -> 23 F:31\nF:11 A:BE -> 24 F:35\nF:11 A:BF -> 25 F:31\nF:11 A:C0 -> 26 F:21\nF:11 A:C1 -> 27 F:25\nF:11 A:C2 -> 28 F:2D\nF:11 A:C3 -> 29 F:29\nF:11 A:C4 -> 2A F:29\nF:11 A:C5 -> 2B F:2D\nF:11 A:C6 -> 2C F:29\nF:11 A:C7 -> 2D F:2D\nF:11 A:C8 -> 2E F:2D\nF:11 A:C9 -> 2F F:29\nF:11 A:CA -> 30 F:35\nF:11 A:CB -> 31 F:31\nF:11 A:CC -> 32 F:31\nF:11 A:CD -> 33 F:35\nF:11 A:CE -> 34 F:31\nF:11 A:CF -> 35 F:35\nF:11 A:D0 -> 36 F:25\nF:11 A:D1 -> 37 F:21\nF:11 A:D2 -> 38 F:29\nF:11 A:D3 -> 39 F:2D\nF:11 A:D4 -> 3A F:2D\nF:11 A:D5 -> 3B F:29\nF:11 A:D6 -> 3C F:2D\nF:11 A:D7 -> 3D F:29\nF:11 A:D8 -> 3E F:29\nF:11 A:D9 -> 3F F:2D\nF:11 A:DA -> 40 F:11\nF:11 A:DB -> 41 F:15\nF:11 A:DC -> 42 F:15\nF:11 A:DD -> 43 F:11\nF:11 A:DE -> 44 F:15\nF:11 A:DF -> 45 F:11\nF:11 A:E0 -> 46 F:01\nF:11 A:E1 -> 47 F:05\nF:11 A:E2 -> 48 F:0D\nF:11 A:E3 -> 49 F:09\nF:11 A:E4 -> 4A F:09\nF:11 A:E5 -> 4B F:0D\nF:11 A:E6 -> 4C F:09\nF:11 A:E7 -> 4D F:0D\nF:11 A:E8 -> 4E F:0D\nF:11 A:E9 -> 4F F:09\nF:11 A:EA -> 50 F:15\nF:11 A:EB -> 51 F:11\nF:11 A:EC -> 52 F:11\nF:11 A:ED -> 53 F:15\nF:11 A:EE -> 54 F:11\nF:11 A:EF -> 55 F:15\nF:11 A:F0 -> 56 F:05\nF:11 A:F1 -> 57 F:01\nF:11 A:F2 -> 58 F:09\nF:11 A:F3 -> 59 F:0D\nF:11 A:F4 -> 5A F:0D\nF:11 A:F5 -> 5B F:09\nF:11 A:F6 -> 5C F:0D\nF:11 A:F7 -> 5D F:09\nF:11 A:F8 -> 5E F:09\nF:11 A:F9 -> 5F F:0D\nF:11 A:FA -> 60 F:35\nF:11 A:FB -> 61 F:31\nF:11 A:FC -> 62 F:31\nF:11 A:FD -> 63 F:35\nF:11 A:FE -> 64 F:31\nF:11 A:FF -> 65 F:35\nF:02 A:00 -> 00 F:46\nF:02 A:01 -> 01 F:02\nF:02 A:02 -> 02 F:02\nF:02 A:03 -> 03 F:06\nF:02 A:04 -> 04 F:02\nF:02 A:05 -> 05 F:06\nF:02 A:06 -> 06 F:06\nF:02 A:07 -> 07 F:02\nF:02 A:08 -> 08 F:0A\nF:02 A:09 -> 09 F:0E\nF:02 A:0A -> 04 F:02\nF:02 A:0B -> 05 F:06\nF:02 A:0C -> 06 F:06\nF:02 A:0D -> 07 F:02\nF:02 A:0E -> 08 F:0A\nF:02 A:0F -> 09 F:0E\nF:02 A:10 -> 10 F:02\nF:02 A:11 -> 11 F:06\nF:02 A:12 -> 12 F:06\nF:02 A:13 -> 13 F:02\nF:02 A:14 -> 14 F:06\nF:02 A:15 -> 15 F:02\nF:02 A:16 -> 16 F:02\nF:02 A:17 -> 17 F:06\nF:02 A:18 -> 18 F:0E\nF:02 A:19 -> 19 F:0A\nF:02 A:1A -> 14 F:06\nF:02 A:1B -> 15 F:02\nF:02 A:1C -> 16 F:02\nF:02 A:1D -> 17 F:06\nF:02 A:1E -> 18 F:0E\nF:02 A:1F -> 19 F:0A\nF:02 A:20 -> 20 F:22\nF:02 A:21 -> 21 F:26\nF:02 A:22 -> 22 F:26\nF:02 A:23 -> 23 F:22\nF:02 A:24 -> 24 F:26\nF:02 A:25 -> 25 F:22\nF:02 A:26 -> 26 F:22\nF:02 A:27 -> 27 F:26\nF:02 A:28 -> 28 F:2E\nF:02 A:29 -> 29 F:2A\nF:02 A:2A -> 24 F:26\nF:02 A:2B -> 25 F:22\nF:02 A:2C -> 26 F:22\nF:02 A:2D -> 27 F:26\nF:02 A:2E -> 28 F:2E\nF:02 A:2F -> 29 F:2A\nF:02 A:30 -> 30 F:26\nF:02 A:31 -> 31 F:22\nF:02 A:32 -> 32 F:22\nF:02 A:33 -> 33 F:26\nF:02 A:34 -> 34 F:22\nF:02 A:35 -> 35 F:26\nF:02 A:36 -> 36 F:26\nF:02 A:37 -> 37 F:22\nF:02 A:38 -> 38 F:2A\nF:02 A:39 -> 39 F:2E\nF:02 A:3A -> 34 F:22\nF:02 A:3B -> 35 F:26\nF:02 A:3C -> 36 F:26\nF:02 A:3D -> 37 F:22\nF:02 A:3E -> 38 F:2A\nF:02 A:3F -> 39 F:2E\nF:02 A:40 -> 40 F:02\nF:02 A:41 -> 41 F:06\nF:02 A:42 -> 42 F:06\nF:02 A:43 -> 43 F:02\nF:02 A:44 -> 44 F:06\nF:02 A:45 -> 45 F:02\nF:02 A:46 -> 46 F:02\nF:02 A:47 -> 47 F:06\nF:02 A:48 -> 48 F:0E\nF:02 A:49 -> 49 F:0A\nF:02 A:4A -> 44 F:06\nF:02 A:4B -> 45 F:02\nF:02 A:4C -> 46 F:02\nF:02 A:4D -> 47 F:06\nF:02 A:4E -> 48 F:0E\nF:02 A:4F -> 49 F:0A\nF:02 A:50 -> 50 F:06\nF:02 A:51 -> 51 F:02\nF:02 A:52 -> 52 F:02\nF:02 A:53 -> 53 F:06\nF:02 A:54 -> 54 F:02\nF:02 A:55 -> 55 F:06\nF:02 A:56 -> 56 F:06\nF:02 A:57 -> 57 F:02\nF:02 A:58 -> 58 F:0A\nF:02 A:59 -> 59 F:0E\nF:02 A:5A -> 54 F:02\nF:02 A:5B -> 55 F:06\nF:02 A:5C -> 56 F:06\nF:02 A:5D -> 57 F:02\nF:02 A:5E -> 58 F:0A\nF:02 A:5F -> 59 F:0E\nF:02 A:60 -> 60 F:26\nF:02 A:61 -> 61 F:22\nF:02 A:62 -> 62 F:22\nF:02 A:63 -> 63 F:26\nF:02 A:64 -> 64 F:22\nF:02 A:65 -> 65 F:26\nF:02 A:66 -> 66 F:26\nF:02 A:67 -> 67 F:22\nF:02 A:68 -> 68 F:2A\nF:02 A:69 -> 69 F:2E\nF:02 A:6A -> 64 F:22\nF:02 A:6B -> 65 F:26\nF:02 A:6C -> 66 F:26\nF:02 A:6D -> 67 F:22\nF:02 A:6E -> 68 F:2A\nF:02 A:6F -> 69 F:2E\nF:02 A:70 -> 70 F:22\nF:02 A:71 -> 71 F:26\nF:02 A:72 -> 72 F:26\nF:02 A:73 -> 73 F:22\nF:02 A:74 -> 74 F:26\nF:02 A:75 -> 75 F:22\nF:02 A:76 -> 76 F:22\nF:02 A:77 -> 77 F:26\nF:02 A:78 -> 78 F:2E\nF:02 A:79 -> 79 F:2A\nF:02 A:7A -> 74 F:26\nF:02 A:7B -> 75 F:22\nF:02 A:7C -> 76 F:22\nF:02 A:7D -> 77 F:26\nF:02 A:7E -> 78 F:2E\nF:02 A:7F -> 79 F:2A\nF:02 A:80 -> 80 F:82\nF:02 A:81 -> 81 F:86\nF:02 A:82 -> 82 F:86\nF:02 A:83 -> 83 F:82\nF:02 A:84 -> 84 F:86\nF:02 A:85 -> 85 F:82\nF:02 A:86 -> 86 F:82\nF:02 A:87 -> 87 F:86\nF:02 A:88 -> 88 F:8E\nF:02 A:89 -> 89 F:8A\nF:02 A:8A -> 84 F:86\nF:02 A:8B -> 85 F:82\nF:02 A:8C -> 86 F:82\nF:02 A:8D -> 87 F:86\nF:02 A:8E -> 88 F:8E\nF:02 A:8F -> 89 F:8A\nF:02 A:90 -> 90 F:86\nF:02 A:91 -> 91 F:82\nF:02 A:92 -> 92 F:82\nF:02 A:93 -> 93 F:86\nF:02 A:94 -> 94 F:82\nF:02 A:95 -> 95 F:86\nF:02 A:96 -> 96 F:86\nF:02 A:97 -> 97 F:82\nF:02 A:98 -> 98 F:8A\nF:02 A:99 -> 99 F:8E\nF:02 A:9A -> 34 F:23\nF:02 A:9B -> 35 F:27\nF:02 A:9C -> 36 F:27\nF:02 A:9D -> 37 F:23\nF:02 A:9E -> 38 F:2B\nF:02 A:9F -> 39 F:2F\nF:02 A:A0 -> 40 F:03\nF:02 A:A1 -> 41 F:07\nF:02 A:A2 -> 42 F:07\nF:02 A:A3 -> 43 F:03\nF:02 A:A4 -> 44 F:07\nF:02 A:A5 -> 45 F:03\nF:02 A:A6 -> 46 F:03\nF:02 A:A7 -> 47 F:07\nF:02 A:A8 -> 48 F:0F\nF:02 A:A9 -> 49 F:0B\nF:02 A:AA -> 44 F:07\nF:02 A:AB -> 45 F:03\nF:02 A:AC -> 46 F:03\nF:02 A:AD -> 47 F:07\nF:02 A:AE -> 48 F:0F\nF:02 A:AF -> 49 F:0B\nF:02 A:B0 -> 50 F:07\nF:02 A:B1 -> 51 F:03\nF:02 A:B2 -> 52 F:03\nF:02 A:B3 -> 53 F:07\nF:02 A:B4 -> 54 F:03\nF:02 A:B5 -> 55 F:07\nF:02 A:B6 -> 56 F:07\nF:02 A:B7 -> 57 F:03\nF:02 A:B8 -> 58 F:0B\nF:02 A:B9 -> 59 F:0F\nF:02 A:BA -> 54 F:03\nF:02 A:BB -> 55 F:07\nF:02 A:BC -> 56 F:07\nF:02 A:BD -> 57 F:03\nF:02 A:BE -> 58 F:0B\nF:02 A:BF -> 59 F:0F\nF:02 A:C0 -> 60 F:27\nF:02 A:C1 -> 61 F:23\nF:02 A:C2 -> 62 F:23\nF:02 A:C3 -> 63 F:27\nF:02 A:C4 -> 64 F:23\nF:02 A:C5 -> 65 F:27\nF:02 A:C6 -> 66 F:27\nF:02 A:C7 -> 67 F:23\nF:02 A:C8 -> 68 F:2B\nF:02 A:C9 -> 69 F:2F\nF:02 A:CA -> 64 F:23\nF:02 A:CB -> 65 F:27\nF:02 A:CC -> 66 F:27\nF:02 A:CD -> 67 F:23\nF:02 A:CE -> 68 F:2B\nF:02 A:CF -> 69 F:2F\nF:02 A:D0 -> 70 F:23\nF:02 A:D1 -> 71 F:27\nF:02 A:D2 -> 72 F:27\nF:02 A:D3 -> 73 F:23\nF:02 A:D4 -> 74 F:27\nF:02 A:D5 -> 75 F:23\nF:02 A:D6 -> 76 F:23\nF:02 A:D7 -> 77 F:27\nF:02 A:D8 -> 78 F:2F\nF:02 A:D9 -> 79 F:2B\nF:02 A:DA -> 74 F:27\nF:02 A:DB -> 75 F:23\nF:02 A:DC -> 76 F:23\nF:02 A:DD -> 77 F:27\nF:02 A:DE -> 78 F:2F\nF:02 A:DF -> 79 F:2B\nF:02 A:E0 -> 80 F:83\nF:02 A:E1 -> 81 F:87\nF:02 A:E2 -> 82 F:87\nF:02 A:E3 -> 83 F:83\nF:02 A:E4 -> 84 F:87\nF:02 A:E5 -> 85 F:83\nF:02 A:E6 -> 86 F:83\nF:02 A:E7 -> 87 F:87\nF:02 A:E8 -> 88 F:8F\nF:02 A:E9 -> 89 F:8B\nF:02 A:EA -> 84 F:87\nF:02 A:EB -> 85 F:83\nF:02 A:EC -> 86 F:83\nF:02 A:ED -> 87 F:87\nF:02 A:EE -> 88 F:8F\nF:02 A:EF -> 89 F:8B\nF:02 A:F0 -> 90 F:87\nF:02 A:F1 -> 91 F:83\nF:02 A:F2 -> 92 F:83\nF:02 A:F3 -> 93 F:87\nF:02 A:F4 -> 94 F:83\nF:02 A:F5 -> 95 F:87\nF:02 A:F6 -> 96 F:87\nF:02 A:F7 -> 97 F:83\nF:02 A:F8 -> 98 F:8B\nF:02 A:F9 -> 99 F:8F\nF:02 A:FA -> 94 F:83\nF:02 A:FB -> 95 F:87\nF:02 A:FC -> 96 F:87\nF:02 A:FD -> 97 F:83\nF:02 A:FE -> 98 F:8B\nF:02 A:FF -> 99 F:8F\nF:03 A:00 -> A0 F:A7\nF:03 A:01 -> A1 F:A3\nF:03 A:02 -> A2 F:A3\nF:03 A:03 -> A3 F:A7\nF:03 A:04 -> A4 F:A3\nF:03 A:05 -> A5 F:A7\nF:03 A:06 -> A6 F:A7\nF:03 A:07 -> A7 F:A3\nF:03 A:08 -> A8 F:AB\nF:03 A:09 -> A9 F:AF\nF:03 A:0A -> A4 F:A3\nF:03 A:0B -> A5 F:A7\nF:03 A:0C -> A6 F:A7\nF:03 A:0D -> A7 F:A3\nF:03 A:0E -> A8 F:AB\nF:03 A:0F -> A9 F:AF\nF:03 A:10 -> B0 F:A3\nF:03 A:11 -> B1 F:A7\nF:03 A:12 -> B2 F:A7\nF:03 A:13 -> B3 F:A3\nF:03 A:14 -> B4 F:A7\nF:03 A:15 -> B5 F:A3\nF:03 A:16 -> B6 F:A3\nF:03 A:17 -> B7 F:A7\nF:03 A:18 -> B8 F:AF\nF:03 A:19 -> B9 F:AB\nF:03 A:1A -> B4 F:A7\nF:03 A:1B -> B5 F:A3\nF:03 A:1C -> B6 F:A3\nF:03 A:1D -> B7 F:A7\nF:03 A:1E -> B8 F:AF\nF:03 A:1F -> B9 F:AB\nF:03 A:20 -> C0 F:87\nF:03 A:21 -> C1 F:83\nF:03 A:22 -> C2 F:83\nF:03 A:23 -> C3 F:87\nF:03 A:24 -> C4 F:83\nF:03 A:25 -> C5 F:87\nF:03 A:26 -> C6 F:87\nF:03 A:27 -> C7 F:83\nF:03 A:28 -> C8 F:8B\nF:03 A:29 -> C9 F:8F\nF:03 A:2A -> C4 F:83\nF:03 A:2B -> C5 F:87\nF:03 A:2C -> C6 F:87\nF:03 A:2D -> C7 F:83\nF:03 A:2E -> C8 F:8B\nF:03 A:2F -> C9 F:8F\nF:03 A:30 -> D0 F:83\nF:03 A:31 -> D1 F:87\nF:03 A:32 -> D2 F:87\nF:03 A:33 -> D3 F:83\nF:03 A:34 -> D4 F:87\nF:03 A:35 -> D5 F:83\nF:03 A:36 -> D6 F:83\nF:03 A:37 -> D7 F:87\nF:03 A:38 -> D8 F:8F\nF:03 A:39 -> D9 F:8B\nF:03 A:3A -> D4 F:87\nF:03 A:3B -> D5 F:83\nF:03 A:3C -> D6 F:83\nF:03 A:3D -> D7 F:87\nF:03 A:3E -> D8 F:8F\nF:03 A:3F -> D9 F:8B\nF:03 A:40 -> E0 F:A3\nF:03 A:41 -> E1 F:A7\nF:03 A:42 -> E2 F:A7\nF:03 A:43 -> E3 F:A3\nF:03 A:44 -> E4 F:A7\nF:03 A:45 -> E5 F:A3\nF:03 A:46 -> E6 F:A3\nF:03 A:47 -> E7 F:A7\nF:03 A:48 -> E8 F:AF\nF:03 A:49 -> E9 F:AB\nF:03 A:4A -> E4 F:A7\nF:03 A:4B -> E5 F:A3\nF:03 A:4C -> E6 F:A3\nF:03 A:4D -> E7 F:A7\nF:03 A:4E -> E8 F:AF\nF:03 A:4F -> E9 F:AB\nF:03 A:50 -> F0 F:A7\nF:03 A:51 -> F1 F:A3\nF:03 A:52 -> F2 F:A3\nF:03 A:53 -> F3 F:A7\nF:03 A:54 -> F4 F:A3\nF:03 A:55 -> F5 F:A7\nF:03 A:56 -> F6 F:A7\nF:03 A:57 -> F7 F:A3\nF:03 A:58 -> F8 F:AB\nF:03 A:59 -> F9 F:AF\nF:03 A:5A -> F4 F:A3\nF:03 A:5B -> F5 F:A7\nF:03 A:5C -> F6 F:A7\nF:03 A:5D -> F7 F:A3\nF:03 A:5E -> F8 F:AB\nF:03 A:5F -> F9 F:AF\nF:03 A:60 -> 00 F:47\nF:03 A:61 -> 01 F:03\nF:03 A:62 -> 02 F:03\nF:03 A:63 -> 03 F:07\nF:03 A:64 -> 04 F:03\nF:03 A:65 -> 05 F:07\nF:03 A:66 -> 06 F:07\nF:03 A:67 -> 07 F:03\nF:03 A:68 -> 08 F:0B\nF:03 A:69 -> 09 F:0F\nF:03 A:6A -> 04 F:03\nF:03 A:6B -> 05 F:07\nF:03 A:6C -> 06 F:07\nF:03 A:6D -> 07 F:03\nF:03 A:6E -> 08 F:0B\nF:03 A:6F -> 09 F:0F\nF:03 A:70 -> 10 F:03\nF:03 A:71 -> 11 F:07\nF:03 A:72 -> 12 F:07\nF:03 A:73 -> 13 F:03\nF:03 A:74 -> 14 F:07\nF:03 A:75 -> 15 F:03\nF:03 A:76 -> 16 F:03\nF:03 A:77 -> 17 F:07\nF:03 A:78 -> 18 F:0F\nF:03 A:79 -> 19 F:0B\nF:03 A:7A -> 14 F:07\nF:03 A:7B -> 15 F:03\nF:03 A:7C -> 16 F:03\nF:03 A:7D -> 17 F:07\nF:03 A:7E -> 18 F:0F\nF:03 A:7F -> 19 F:0B\nF:03 A:80 -> 20 F:23\nF:03 A:81 -> 21 F:27\nF:03 A:82 -> 22 F:27\nF:03 A:83 -> 23 F:23\nF:03 A:84 -> 24 F:27\nF:03 A:85 -> 25 F:23\nF:03 A:86 -> 26 F:23\nF:03 A:87 -> 27 F:27\nF:03 A:88 -> 28 F:2F\nF:03 A:89 -> 29 F:2B\nF:03 A:8A -> 24 F:27\nF:03 A:8B -> 25 F:23\nF:03 A:8C -> 26 F:23\nF:03 A:8D -> 27 F:27\nF:03 A:8E -> 28 F:2F\nF:03 A:8F -> 29 F:2B\nF:03 A:90 -> 30 F:27\nF:03 A:91 -> 31 F:23\nF:03 A:92 -> 32 F:23\nF:03 A:93 -> 33 F:27\nF:03 A:94 -> 34 F:23\nF:03 A:95 -> 35 F:27\nF:03 A:96 -> 36 F:27\nF:03 A:97 -> 37 F:23\nF:03 A:98 -> 38 F:2B\nF:03 A:99 -> 39 F:2F\nF:03 A:9A -> 34 F:23\nF:03 A:9B -> 35 F:27\nF:03 A:9C -> 36 F:27\nF:03 A:9D -> 37 F:23\nF:03 A:9E -> 38 F:2B\nF:03 A:9F -> 39 F:2F\nF:03 A:A0 -> 40 F:03\nF:03 A:A1 -> 41 F:07\nF:03 A:A2 -> 42 F:07\nF:03 A:A3 -> 43 F:03\nF:03 A:A4 -> 44 F:07\nF:03 A:A5 -> 45 F:03\nF:03 A:A6 -> 46 F:03\nF:03 A:A7 -> 47 F:07\nF:03 A:A8 -> 48 F:0F\nF:03 A:A9 -> 49 F:0B\nF:03 A:AA -> 44 F:07\nF:03 A:AB -> 45 F:03\nF:03 A:AC -> 46 F:03\nF:03 A:AD -> 47 F:07\nF:03 A:AE -> 48 F:0F\nF:03 A:AF -> 49 F:0B\nF:03 A:B0 -> 50 F:07\nF:03 A:B1 -> 51 F:03\nF:03 A:B2 -> 52 F:03\nF:03 A:B3 -> 53 F:07\nF:03 A:B4 -> 54 F:03\nF:03 A:B5 -> 55 F:07\nF:03 A:B6 -> 56 F:07\nF:03 A:B7 -> 57 F:03\nF:03 A:B8 -> 58 F:0B\nF:03 A:B9 -> 59 F:0F\nF:03 A:BA -> 54 F:03\nF:03 A:BB -> 55 F:07\nF:03 A:BC -> 56 F:07\nF:03 A:BD -> 57 F:03\nF:03 A:BE -> 58 F:0B\nF:03 A:BF -> 59 F:0F\nF:03 A:C0 -> 60 F:27\nF:03 A:C1 -> 61 F:23\nF:03 A:C2 -> 62 F:23\nF:03 A:C3 -> 63 F:27\nF:03 A:C4 -> 64 F:23\nF:03 A:C5 -> 65 F:27\nF:03 A:C6 -> 66 F:27\nF:03 A:C7 -> 67 F:23\nF:03 A:C8 -> 68 F:2B\nF:03 A:C9 -> 69 F:2F\nF:03 A:CA -> 64 F:23\nF:03 A:CB -> 65 F:27\nF:03 A:CC -> 66 F:27\nF:03 A:CD -> 67 F:23\nF:03 A:CE -> 68 F:2B\nF:03 A:CF -> 69 F:2F\nF:03 A:D0 -> 70 F:23\nF:03 A:D1 -> 71 F:27\nF:03 A:D2 -> 72 F:27\nF:03 A:D3 -> 73 F:23\nF:03 A:D4 -> 74 F:27\nF:03 A:D5 -> 75 F:23\nF:03 A:D6 -> 76 F:23\nF:03 A:D7 -> 77 F:27\nF:03 A:D8 -> 78 F:2F\nF:03 A:D9 -> 79 F:2B\nF:03 A:DA -> 74 F:27\nF:03 A:DB -> 75 F:23\nF:03 A:DC -> 76 F:23\nF:03 A:DD -> 77 F:27\nF:03 A:DE -> 78 F:2F\nF:03 A:DF -> 79 F:2B\nF:03 A:E0 -> 80 F:83\nF:03 A:E1 -> 81 F:87\nF:03 A:E2 -> 82 F:87\nF:03 A:E3 -> 83 F:83\nF:03 A:E4 -> 84 F:87\nF:03 A:E5 -> 85 F:83\nF:03 A:E6 -> 86 F:83\nF:03 A:E7 -> 87 F:87\nF:03 A:E8 -> 88 F:8F\nF:03 A:E9 -> 89 F:8B\nF:03 A:EA -> 84 F:87\nF:03 A:EB -> 85 F:83\nF:03 A:EC -> 86 F:83\nF:03 A:ED -> 87 F:87\nF:03 A:EE -> 88 F:8F\nF:03 A:EF -> 89 F:8B\nF:03 A:F0 -> 90 F:87\nF:03 A:F1 -> 91 F:83\nF:03 A:F2 -> 92 F:83\nF:03 A:F3 -> 93 F:87\nF:03 A:F4 -> 94 F:83\nF:03 A:F5 -> 95 F:87\nF:03 A:F6 -> 96 F:87\nF:03 A:F7 -> 97 F:83\nF:03 A:F8 -> 98 F:8B\nF:03 A:F9 -> 99 F:8F\nF:03 A:FA -> 94 F:83\nF:03 A:FB -> 95 F:87\nF:03 A:FC -> 96 F:87\nF:03 A:FD -> 97 F:83\nF:03 A:FE -> 98 F:8B\nF:03 A:FF -> 99 F:8F\nF:12 A:00 -> FA F:BE\nF:12 A:01 -> FB F:BA\nF:12 A:02 -> FC F:BE\nF:12 A:03 -> FD F:BA\nF:12 A:04 -> FE F:BA\nF:12 A:05 -> FF F:BE\nF:12 A:06 -> 00 F:46\nF:12 A:07 -> 01 F:02\nF:12 A:08 -> 02 F:02\nF:12 A:09 -> 03 F:06\nF:12 A:0A -> 04 F:02\nF:12 A:0B -> 05 F:06\nF:12 A:0C -> 06 F:06\nF:12 A:0D -> 07 F:02\nF:12 A:0E -> 08 F:0A\nF:12 A:0F -> 09 F:0E\nF:12 A:10 -> 0A F:1E\nF:12 A:11 -> 0B F:1A\nF:12 A:12 -> 0C F:1E\nF:12 A:13 -> 0D F:1A\nF:12 A:14 -> 0E F:1A\nF:12 A:15 -> 0F F:1E\nF:12 A:16 -> 10 F:02\nF:12 A:17 -> 11 F:06\nF:12 A:18 -> 12 F:06\nF:12 A:19 -> 13 F:02\nF:12 A:1A -> 14 F:06\nF:12 A:1B -> 15 F:02\nF:12 A:1C -> 16 F:02\nF:12 A:1D -> 17 F:06\nF:12 A:1E -> 18 F:0E\nF:12 A:1F -> 19 F:0A\nF:12 A:20 -> 1A F:1A\nF:12 A:21 -> 1B F:1E\nF:12 A:22 -> 1C F:1A\nF:12 A:23 -> 1D F:1E\nF:12 A:24 -> 1E F:1E\nF:12 A:25 -> 1F F:1A\nF:12 A:26 -> 20 F:22\nF:12 A:27 -> 21 F:26\nF:12 A:28 -> 22 F:26\nF:12 A:29 -> 23 F:22\nF:12 A:2A -> 24 F:26\nF:12 A:2B -> 25 F:22\nF:12 A:2C -> 26 F:22\nF:12 A:2D -> 27 F:26\nF:12 A:2E -> 28 F:2E\nF:12 A:2F -> 29 F:2A\nF:12 A:30 -> 2A F:3A\nF:12 A:31 -> 2B F:3E\nF:12 A:32 -> 2C F:3A\nF:12 A:33 -> 2D F:3E\nF:12 A:34 -> 2E F:3E\nF:12 A:35 -> 2F F:3A\nF:12 A:36 -> 30 F:26\nF:12 A:37 -> 31 F:22\nF:12 A:38 -> 32 F:22\nF:12 A:39 -> 33 F:26\nF:12 A:3A -> 34 F:22\nF:12 A:3B -> 35 F:26\nF:12 A:3C -> 36 F:26\nF:12 A:3D -> 37 F:22\nF:12 A:3E -> 38 F:2A\nF:12 A:3F -> 39 F:2E\nF:12 A:40 -> 3A F:3E\nF:12 A:41 -> 3B F:3A\nF:12 A:42 -> 3C F:3E\nF:12 A:43 -> 3D F:3A\nF:12 A:44 -> 3E F:3A\nF:12 A:45 -> 3F F:3E\nF:12 A:46 -> 40 F:02\nF:12 A:47 -> 41 F:06\nF:12 A:48 -> 42 F:06\nF:12 A:49 -> 43 F:02\nF:12 A:4A -> 44 F:06\nF:12 A:4B -> 45 F:02\nF:12 A:4C -> 46 F:02\nF:12 A:4D -> 47 F:06\nF:12 A:4E -> 48 F:0E\nF:12 A:4F -> 49 F:0A\nF:12 A:50 -> 4A F:1A\nF:12 A:51 -> 4B F:1E\nF:12 A:52 -> 4C F:1A\nF:12 A:53 -> 4D F:1E\nF:12 A:54 -> 4E F:1E\nF:12 A:55 -> 4F F:1A\nF:12 A:56 -> 50 F:06\nF:12 A:57 -> 51 F:02\nF:12 A:58 -> 52 F:02\nF:12 A:59 -> 53 F:06\nF:12 A:5A -> 54 F:02\nF:12 A:5B -> 55 F:06\nF:12 A:5C -> 56 F:06\nF:12 A:5D -> 57 F:02\nF:12 A:5E -> 58 F:0A\nF:12 A:5F -> 59 F:0E\nF:12 A:60 -> 5A F:1E\nF:12 A:61 -> 5B F:1A\nF:12 A:62 -> 5C F:1E\nF:12 A:63 -> 5D F:1A\nF:12 A:64 -> 5E F:1A\nF:12 A:65 -> 5F F:1E\nF:12 A:66 -> 60 F:26\nF:12 A:67 -> 61 F:22\nF:12 A:68 -> 62 F:22\nF:12 A:69 -> 63 F:26\nF:12 A:6A -> 64 F:22\nF:12 A:6B -> 65 F:26\nF:12 A:6C -> 66 F:26\nF:12 A:6D -> 67 F:22\nF:12 A:6E -> 68 F:2A\nF:12 A:6F -> 69 F:2E\nF:12 A:70 -> 6A F:3E\nF:12 A:71 -> 6B F:3A\nF:12 A:72 -> 6C F:3E\nF:12 A:73 -> 6D F:3A\nF:12 A:74 -> 6E F:3A\nF:12 A:75 -> 6F F:3E\nF:12 A:76 -> 70 F:22\nF:12 A:77 -> 71 F:26\nF:12 A:78 -> 72 F:26\nF:12 A:79 -> 73 F:22\nF:12 A:7A -> 74 F:26\nF:12 A:7B -> 75 F:22\nF:12 A:7C -> 76 F:22\nF:12 A:7D -> 77 F:26\nF:12 A:7E -> 78 F:2E\nF:12 A:7F -> 79 F:2A\nF:12 A:80 -> 7A F:3A\nF:12 A:81 -> 7B F:3E\nF:12 A:82 -> 7C F:3A\nF:12 A:83 -> 7D F:3E\nF:12 A:84 -> 7E F:3E\nF:12 A:85 -> 7F F:3A\nF:12 A:86 -> 80 F:82\nF:12 A:87 -> 81 F:86\nF:12 A:88 -> 82 F:86\nF:12 A:89 -> 83 F:82\nF:12 A:8A -> 84 F:86\nF:12 A:8B -> 85 F:82\nF:12 A:8C -> 86 F:82\nF:12 A:8D -> 87 F:86\nF:12 A:8E -> 88 F:8E\nF:12 A:8F -> 89 F:8A\nF:12 A:90 -> 8A F:9A\nF:12 A:91 -> 8B F:9E\nF:12 A:92 -> 8C F:9A\nF:12 A:93 -> 8D F:9E\nF:12 A:94 -> 8E F:9E\nF:12 A:95 -> 8F F:9A\nF:12 A:96 -> 90 F:86\nF:12 A:97 -> 91 F:82\nF:12 A:98 -> 92 F:82\nF:12 A:99 -> 93 F:86\nF:12 A:9A -> 34 F:23\nF:12 A:9B -> 35 F:27\nF:12 A:9C -> 36 F:27\nF:12 A:9D -> 37 F:23\nF:12 A:9E -> 38 F:2B\nF:12 A:9F -> 39 F:2F\nF:12 A:A0 -> 3A F:3F\nF:12 A:A1 -> 3B F:3B\nF:12 A:A2 -> 3C F:3F\nF:12 A:A3 -> 3D F:3B\nF:12 A:A4 -> 3E F:3B\nF:12 A:A5 -> 3F F:3F\nF:12 A:A6 -> 40 F:03\nF:12 A:A7 -> 41 F:07\nF:12 A:A8 -> 42 F:07\nF:12 A:A9 -> 43 F:03\nF:12 A:AA -> 44 F:07\nF:12 A:AB -> 45 F:03\nF:12 A:AC -> 46 F:03\nF:12 A:AD -> 47 F:07\nF:12 A:AE -> 48 F:0F\nF:12 A:AF -> 49 F:0B\nF:12 A:B0 -> 4A F:1B\nF:12 A:B1 -> 4B F:1F\nF:12 A:B2 -> 4C F:1B\nF:12 A:B3 -> 4D F:1F\nF:12 A:B4 -> 4E F:1F\nF:12 A:B5 -> 4F F:1B\nF:12 A:B6 -> 50 F:07\nF:12 A:B7 -> 51 F:03\nF:12 A:B8 -> 52 F:03\nF:12 A:B9 -> 53 F:07\nF:12 A:BA -> 54 F:03\nF:12 A:BB -> 55 F:07\nF:12 A:BC -> 56 F:07\nF:12 A:BD -> 57 F:03\nF:12 A:BE -> 58 F:0B\nF:12 A:BF -> 59 F:0F\nF:12 A:C0 -> 5A F:1F\nF:12 A:C1 -> 5B F:1B\nF:12 A:C2 -> 5C F:1F\nF:12 A:C3 -> 5D F:1B\nF:12 A:C4 -> 5E F:1B\nF:12 A:C5 -> 5F F:1F\nF:12 A:C6 -> 60 F:27\nF:12 A:C7 -> 61 F:23\nF:12 A:C8 -> 62 F:23\nF:12 A:C9 -> 63 F:27\nF:12 A:CA -> 64 F:23\nF:12 A:CB -> 65 F:27\nF:12 A:CC -> 66 F:27\nF:12 A:CD -> 67 F:23\nF:12 A:CE -> 68 F:2B\nF:12 A:CF -> 69 F:2F\nF:12 A:D0 -> 6A F:3F\nF:12 A:D1 -> 6B F:3B\nF:12 A:D2 -> 6C F:3F\nF:12 A:D3 -> 6D F:3B\nF:12 A:D4 -> 6E F:3B\nF:12 A:D5 -> 6F F:3F\nF:12 A:D6 -> 70 F:23\nF:12 A:D7 -> 71 F:27\nF:12 A:D8 -> 72 F:27\nF:12 A:D9 -> 73 F:23\nF:12 A:DA -> 74 F:27\nF:12 A:DB -> 75 F:23\nF:12 A:DC -> 76 F:23\nF:12 A:DD -> 77 F:27\nF:12 A:DE -> 78 F:2F\nF:12 A:DF -> 79 F:2B\nF:12 A:E0 -> 7A F:3B\nF:12 A:E1 -> 7B F:3F\nF:12 A:E2 -> 7C F:3B\nF:12 A:E3 -> 7D F:3F\nF:12 A:E4 -> 7E F:3F\nF:12 A:E5 -> 7F F:3B\nF:12 A:E6 -> 80 F:83\nF:12 A:E7 -> 81 F:87\nF:12 A:E8 -> 82 F:87\nF:12 A:E9 -> 83 F:83\nF:12 A:EA -> 84 F:87\nF:12 A:EB -> 85 F:83\nF:12 A:EC -> 86 F:83\nF:12 A:ED -> 87 F:87\nF:12 A:EE -> 88 F:8F\nF:12 A:EF -> 89 F:8B\nF:12 A:F0 -> 8A F:9B\nF:12 A:F1 -> 8B F:9F\nF:12 A:F2 -> 8C F:9B\nF:12 A:F3 -> 8D F:9F\nF:12 A:F4 -> 8E F:9F\nF:12 A:F5 -> 8F F:9B\nF:12 A:F6 -> 90 F:87\nF:12 A:F7 -> 91 F:83\nF:12 A:F8 -> 92 F:83\nF:12 A:F9 -> 93 F:87\nF:12 A:FA -> 94 F:83\nF:12 A:FB -> 95 F:87\nF:12 A:FC -> 96 F:87\nF:12 A:FD -> 97 F:83\nF:12 A:FE -> 98 F:8B\nF:12 A:FF -> 99 F:8F\nF:13 A:00 -> 9A F:9F\nF:13 A:01 -> 9B F:9B\nF:13 A:02 -> 9C F:9F\nF:13 A:03 -> 9D F:9B\nF:13 A:04 -> 9E F:9B\nF:13 A:05 -> 9F F:9F\nF:13 A:06 -> A0 F:A7\nF:13 A:07 -> A1 F:A3\nF:13 A:08 -> A2 F:A3\nF:13 A:09 -> A3 F:A7\nF:13 A:0A -> A4 F:A3\nF:13 A:0B -> A5 F:A7\nF:13 A:0C -> A6 F:A7\nF:13 A:0D -> A7 F:A3\nF:13 A:0E -> A8 F:AB\nF:13 A:0F -> A9 F:AF\nF:13 A:10 -> AA F:BF\nF:13 A:11 -> AB F:BB\nF:13 A:12 -> AC F:BF\nF:13 A:13 -> AD F:BB\nF:13 A:14 -> AE F:BB\nF:13 A:15 -> AF F:BF\nF:13 A:16 -> B0 F:A3\nF:13 A:17 -> B1 F:A7\nF:13 A:18 -> B2 F:A7\nF:13 A:19 -> B3 F:A3\nF:13 A:1A -> B4 F:A7\nF:13 A:1B -> B5 F:A3\nF:13 A:1C -> B6 F:A3\nF:13 A:1D -> B7 F:A7\nF:13 A:1E -> B8 F:AF\nF:13 A:1F -> B9 F:AB\nF:13 A:20 -> BA F:BB\nF:13 A:21 -> BB F:BF\nF:13 A:22 -> BC F:BB\nF:13 A:23 -> BD F:BF\nF:13 A:24 -> BE F:BF\nF:13 A:25 -> BF F:BB\nF:13 A:26 -> C0 F:87\nF:13 A:27 -> C1 F:83\nF:13 A:28 -> C2 F:83\nF:13 A:29 -> C3 F:87\nF:13 A:2A -> C4 F:83\nF:13 A:2B -> C5 F:87\nF:13 A:2C -> C6 F:87\nF:13 A:2D -> C7 F:83\nF:13 A:2E -> C8 F:8B\nF:13 A:2F -> C9 F:8F\nF:13 A:30 -> CA F:9F\nF:13 A:31 -> CB F:9B\nF:13 A:32 -> CC F:9F\nF:13 A:33 -> CD F:9B\nF:13 A:34 -> CE F:9B\nF:13 A:35 -> CF F:9F\nF:13 A:36 -> D0 F:83\nF:13 A:37 -> D1 F:87\nF:13 A:38 -> D2 F:87\nF:13 A:39 -> D3 F:83\nF:13 A:3A -> D4 F:87\nF:13 A:3B -> D5 F:83\nF:13 A:3C -> D6 F:83\nF:13 A:3D -> D7 F:87\nF:13 A:3E -> D8 F:8F\nF:13 A:3F -> D9 F:8B\nF:13 A:40 -> DA F:9B\nF:13 A:41 -> DB F:9F\nF:13 A:42 -> DC F:9B\nF:13 A:43 -> DD F:9F\nF:13 A:44 -> DE F:9F\nF:13 A:45 -> DF F:9B\nF:13 A:46 -> E0 F:A3\nF:13 A:47 -> E1 F:A7\nF:13 A:48 -> E2 F:A7\nF:13 A:49 -> E3 F:A3\nF:13 A:4A -> E4 F:A7\nF:13 A:4B -> E5 F:A3\nF:13 A:4C -> E6 F:A3\nF:13 A:4D -> E7 F:A7\nF:13 A:4E -> E8 F:AF\nF:13 A:4F -> E9 F:AB\nF:13 A:50 -> EA F:BB\nF:13 A:51 -> EB F:BF\nF:13 A:52 -> EC F:BB\nF:13 A:53 -> ED F:BF\nF:13 A:54 -> EE F:BF\nF:13 A:55 -> EF F:BB\nF:13 A:56 -> F0 F:A7\nF:13 A:57 -> F1 F:A3\nF:13 A:58 -> F2 F:A3\nF:13 A:59 -> F3 F:A7\nF:13 A:5A -> F4 F:A3\nF:13 A:5B -> F5 F:A7\nF:13 A:5C -> F6 F:A7\nF:13 A:5D -> F7 F:A3\nF:13 A:5E -> F8 F:AB\nF:13 A:5F -> F9 F:AF\nF:13 A:60 -> FA F:BF\nF:13 A:61 -> FB F:BB\nF:13 A:62 -> FC F:BF\nF:13 A:63 -> FD F:BB\nF:13 A:64 -> FE F:BB\nF:13 A:65 -> FF F:BF\nF:13 A:66 -> 00 F:47\nF:13 A:67 -> 01 F:03\nF:13 A:68 -> 02 F:03\nF:13 A:69 -> 03 F:07\nF:13 A:6A -> 04 F:03\nF:13 A:6B -> 05 F:07\nF:13 A:6C -> 06 F:07\nF:13 A:6D -> 07 F:03\nF:13 A:6E -> 08 F:0B\nF:13 A:6F -> 09 F:0F\nF:13 A:70 -> 0A F:1F\nF:13 A:71 -> 0B F:1B\nF:13 A:72 -> 0C F:1F\nF:13 A:73 -> 0D F:1B\nF:13 A:74 -> 0E F:1B\nF:13 A:75 -> 0F F:1F\nF:13 A:76 -> 10 F:03\nF:13 A:77 -> 11 F:07\nF:13 A:78 -> 12 F:07\nF:13 A:79 -> 13 F:03\nF:13 A:7A -> 14 F:07\nF:13 A:7B -> 15 F:03\nF:13 A:7C -> 16 F:03\nF:13 A:7D -> 17 F:07\nF:13 A:7E -> 18 F:0F\nF:13 A:7F -> 19 F:0B\nF:13 A:80 -> 1A F:1B\nF:13 A:81 -> 1B F:1F\nF:13 A:82 -> 1C F:1B\nF:13 A:83 -> 1D F:1F\nF:13 A:84 -> 1E F:1F\nF:13 A:85 -> 1F F:1B\nF:13 A:86 -> 20 F:23\nF:13 A:87 -> 21 F:27\nF:13 A:88 -> 22 F:27\nF:13 A:89 -> 23 F:23\nF:13 A:8A -> 24 F:27\nF:13 A:8B -> 25 F:23\nF:13 A:8C -> 26 F:23\nF:13 A:8D -> 27 F:27\nF:13 A:8E -> 28 F:2F\nF:13 A:8F -> 29 F:2B\nF:13 A:90 -> 2A F:3B\nF:13 A:91 -> 2B F:3F\nF:13 A:92 -> 2C F:3B\nF:13 A:93 -> 2D F:3F\nF:13 A:94 -> 2E F:3F\nF:13 A:95 -> 2F F:3B\nF:13 A:96 -> 30 F:27\nF:13 A:97 -> 31 F:23\nF:13 A:98 -> 32 F:23\nF:13 A:99 -> 33 F:27\nF:13 A:9A -> 34 F:23\nF:13 A:9B -> 35 F:27\nF:13 A:9C -> 36 F:27\nF:13 A:9D -> 37 F:23\nF:13 A:9E -> 38 F:2B\nF:13 A:9F -> 39 F:2F\nF:13 A:A0 -> 3A F:3F\nF:13 A:A1 -> 3B F:3B\nF:13 A:A2 -> 3C F:3F\nF:13 A:A3 -> 3D F:3B\nF:13 A:A4 -> 3E F:3B\nF:13 A:A5 -> 3F F:3F\nF:13 A:A6 -> 40 F:03\nF:13 A:A7 -> 41 F:07\nF:13 A:A8 -> 42 F:07\nF:13 A:A9 -> 43 F:03\nF:13 A:AA -> 44 F:07\nF:13 A:AB -> 45 F:03\nF:13 A:AC -> 46 F:03\nF:13 A:AD -> 47 F:07\nF:13 A:AE -> 48 F:0F\nF:13 A:AF -> 49 F:0B\nF:13 A:B0 -> 4A F:1B\nF:13 A:B1 -> 4B F:1F\nF:13 A:B2 -> 4C F:1B\nF:13 A:B3 -> 4D F:1F\nF:13 A:B4 -> 4E F:1F\nF:13 A:B5 -> 4F F:1B\nF:13 A:B6 -> 50 F:07\nF:13 A:B7 -> 51 F:03\nF:13 A:B8 -> 52 F:03\nF:13 A:B9 -> 53 F:07\nF:13 A:BA -> 54 F:03\nF:13 A:BB -> 55 F:07\nF:13 A:BC -> 56 F:07\nF:13 A:BD -> 57 F:03\nF:13 A:BE -> 58 F:0B\nF:13 A:BF -> 59 F:0F\nF:13 A:C0 -> 5A F:1F\nF:13 A:C1 -> 5B F:1B\nF:13 A:C2 -> 5C F:1F\nF:13 A:C3 -> 5D F:1B\nF:13 A:C4 -> 5E F:1B\nF:13 A:C5 -> 5F F:1F\nF:13 A:C6 -> 60 F:27\nF:13 A:C7 -> 61 F:23\nF:13 A:C8 -> 62 F:23\nF:13 A:C9 -> 63 F:27\nF:13 A:CA -> 64 F:23\nF:13 A:CB -> 65 F:27\nF:13 A:CC -> 66 F:27\nF:13 A:CD -> 67 F:23\nF:13 A:CE -> 68 F:2B\nF:13 A:CF -> 69 F:2F\nF:13 A:D0 -> 6A F:3F\nF:13 A:D1 -> 6B F:3B\nF:13 A:D2 -> 6C F:3F\nF:13 A:D3 -> 6D F:3B\nF:13 A:D4 -> 6E F:3B\nF:13 A:D5 -> 6F F:3F\nF:13 A:D6 -> 70 F:23\nF:13 A:D7 -> 71 F:27\nF:13 A:D8 -> 72 F:27\nF:13 A:D9 -> 73 F:23\nF:13 A:DA -> 74 F:27\nF:13 A:DB -> 75 F:23\nF:13 A:DC -> 76 F:23\nF:13 A:DD -> 77 F:27\nF:13 A:DE -> 78 F:2F\nF:13 A:DF -> 79 F:2B\nF:13 A:E0 -> 7A F:3B\nF:13 A:E1 -> 7B F:3F\nF:13 A:E2 -> 7C F:3B\nF:13 A:E3 -> 7D F:3F\nF:13 A:E4 -> 7E F:3F\nF:13 A:E5 -> 7F F:3B\nF:13 A:E6 -> 80 F:83\nF:13 A:E7 -> 81 F:87\nF:13 A:E8 -> 82 F:87\nF:13 A:E9 -> 83 F:83\nF:13 A:EA -> 84 F:87\nF:13 A:EB -> 85 F:83\nF:13 A:EC -> 86 F:83\nF:13 A:ED -> 87 F:87\nF:13 A:EE -> 88 F:8F\nF:13 A:EF -> 89 F:8B\nF:13 A:F0 -> 8A F:9B\nF:13 A:F1 -> 8B F:9F\nF:13 A:F2 -> 8C F:9B\nF:13 A:F3 -> 8D F:9F\nF:13 A:F4 -> 8E F:9F\nF:13 A:F5 -> 8F F:9B\nF:13 A:F6 -> 90 F:87\nF:13 A:F7 -> 91 F:83\nF:13 A:F8 -> 92 F:83\nF:13 A:F9 -> 93 F:87\nF:13 A:FA -> 94 F:83\nF:13 A:FB -> 95 F:87\nF:13 A:FC -> 96 F:87\nF:13 A:FD -> 97 F:83\nF:13 A:FE -> 98 F:8B\nF:13 A:FF -> 99 F:8F"
  },
  {
    "path": "tools/dongle/daa/daa_a-00.out",
    "content": "#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:00          MREQ RD                    | Memory read from 005 -> 00\n#053H T8  AB:0FF DB:00          MREQ    WR                 | Memory write to  0FF <- 00\n#056H T11 AB:0FE DB:44          MREQ    WR                 | Memory write to  0FE <- 44\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:01          MREQ RD                    | Memory read from 005 -> 01\n#053H T8  AB:0FF DB:01          MREQ    WR                 | Memory write to  0FF <- 01\n#056H T11 AB:0FE DB:00          MREQ    WR                 | Memory write to  0FE <- 00\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:02          MREQ RD                    | Memory read from 005 -> 02\n#053H T8  AB:0FF DB:02          MREQ    WR                 | Memory write to  0FF <- 02\n#056H T11 AB:0FE DB:00          MREQ    WR                 | Memory write to  0FE <- 00\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:03          MREQ RD                    | Memory read from 005 -> 03\n#053H T8  AB:0FF DB:03          MREQ    WR                 | Memory write to  0FF <- 03\n#056H T11 AB:0FE DB:04          MREQ    WR                 | Memory write to  0FE <- 04\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:04          MREQ RD                    | Memory read from 005 -> 04\n#053H T8  AB:0FF DB:04          MREQ    WR                 | Memory write to  0FF <- 04\n#056H T11 AB:0FE DB:00          MREQ    WR                 | Memory write to  0FE <- 00\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:05          MREQ RD                    | Memory read from 005 -> 05\n#053H T8  AB:0FF DB:05          MREQ    WR                 | Memory write to  0FF <- 05\n#056H T11 AB:0FE DB:04          MREQ    WR                 | Memory write to  0FE <- 04\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:06          MREQ RD                    | Memory read from 005 -> 06\n#053H T8  AB:0FF DB:06          MREQ    WR                 | Memory write to  0FF <- 06\n#056H T11 AB:0FE DB:04          MREQ    WR                 | Memory write to  0FE <- 04\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:07          MREQ RD                    | Memory read from 005 -> 07\n#053H T8  AB:0FF DB:07          MREQ    WR                 | Memory write to  0FF <- 07\n#056H T11 AB:0FE DB:00          MREQ    WR                 | Memory write to  0FE <- 00\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:08          MREQ RD                    | Memory read from 005 -> 08\n#053H T8  AB:0FF DB:08          MREQ    WR                 | Memory write to  0FF <- 08\n#056H T11 AB:0FE DB:08          MREQ    WR                 | Memory write to  0FE <- 08\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:09          MREQ RD                    | Memory read from 005 -> 09\n#053H T8  AB:0FF DB:09          MREQ    WR                 | Memory write to  0FF <- 09\n#056H T11 AB:0FE DB:0C          MREQ    WR                 | Memory write to  0FE <- 0C\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:0A          MREQ RD                    | Memory read from 005 -> 0A\n#053H T8  AB:0FF DB:10          MREQ    WR                 | Memory write to  0FF <- 10\n#056H T11 AB:0FE DB:10          MREQ    WR                 | Memory write to  0FE <- 10\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:0B          MREQ RD                    | Memory read from 005 -> 0B\n#053H T8  AB:0FF DB:11          MREQ    WR                 | Memory write to  0FF <- 11\n#056H T11 AB:0FE DB:14          MREQ    WR                 | Memory write to  0FE <- 14\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:0C          MREQ RD                    | Memory read from 005 -> 0C\n#053H T8  AB:0FF DB:12          MREQ    WR                 | Memory write to  0FF <- 12\n#056H T11 AB:0FE DB:14          MREQ    WR                 | Memory write to  0FE <- 14\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:0D          MREQ RD                    | Memory read from 005 -> 0D\n#053H T8  AB:0FF DB:13          MREQ    WR                 | Memory write to  0FF <- 13\n#056H T11 AB:0FE DB:10          MREQ    WR                 | Memory write to  0FE <- 10\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:0E          MREQ RD                    | Memory read from 005 -> 0E\n#053H T8  AB:0FF DB:14          MREQ    WR                 | Memory write to  0FF <- 14\n#056H T11 AB:0FE DB:14          MREQ    WR                 | Memory write to  0FE <- 14\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:0F          MREQ RD                    | Memory read from 005 -> 0F\n#053H T8  AB:0FF DB:15          MREQ    WR                 | Memory write to  0FF <- 15\n#056H T11 AB:0FE DB:10          MREQ    WR                 | Memory write to  0FE <- 10\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:10          MREQ RD                    | Memory read from 005 -> 10\n#053H T8  AB:0FF DB:10          MREQ    WR                 | Memory write to  0FF <- 10\n#056H T11 AB:0FE DB:00          MREQ    WR                 | Memory write to  0FE <- 00\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:11          MREQ RD                    | Memory read from 005 -> 11\n#053H T8  AB:0FF DB:11          MREQ    WR                 | Memory write to  0FF <- 11\n#056H T11 AB:0FE DB:04          MREQ    WR                 | Memory write to  0FE <- 04\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:12          MREQ RD                    | Memory read from 005 -> 12\n#053H T8  AB:0FF DB:12          MREQ    WR                 | Memory write to  0FF <- 12\n#056H T11 AB:0FE DB:04          MREQ    WR                 | Memory write to  0FE <- 04\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:13          MREQ RD                    | Memory read from 005 -> 13\n#053H T8  AB:0FF DB:13          MREQ    WR                 | Memory write to  0FF <- 13\n#056H T11 AB:0FE DB:00          MREQ    WR                 | Memory write to  0FE <- 00\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:14          MREQ RD                    | Memory read from 005 -> 14\n#053H T8  AB:0FF DB:14          MREQ    WR                 | Memory write to  0FF <- 14\n#056H T11 AB:0FE DB:04          MREQ    WR                 | Memory write to  0FE <- 04\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:15          MREQ RD                    | Memory read from 005 -> 15\n#053H T8  AB:0FF DB:15          MREQ    WR                 | Memory write to  0FF <- 15\n#056H T11 AB:0FE DB:00          MREQ    WR                 | Memory write to  0FE <- 00\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:16          MREQ RD                    | Memory read from 005 -> 16\n#053H T8  AB:0FF DB:16          MREQ    WR                 | Memory write to  0FF <- 16\n#056H T11 AB:0FE DB:00          MREQ    WR                 | Memory write to  0FE <- 00\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:17          MREQ RD                    | Memory read from 005 -> 17\n#053H T8  AB:0FF DB:17          MREQ    WR                 | Memory write to  0FF <- 17\n#056H T11 AB:0FE DB:04          MREQ    WR                 | Memory write to  0FE <- 04\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:18          MREQ RD                    | Memory read from 005 -> 18\n#053H T8  AB:0FF DB:18          MREQ    WR                 | Memory write to  0FF <- 18\n#056H T11 AB:0FE DB:0C          MREQ    WR                 | Memory write to  0FE <- 0C\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:19          MREQ RD                    | Memory read from 005 -> 19\n#053H T8  AB:0FF DB:19          MREQ    WR                 | Memory write to  0FF <- 19\n#056H T11 AB:0FE DB:08          MREQ    WR                 | Memory write to  0FE <- 08\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:1A          MREQ RD                    | Memory read from 005 -> 1A\n#053H T8  AB:0FF DB:20          MREQ    WR                 | Memory write to  0FF <- 20\n#056H T11 AB:0FE DB:30          MREQ    WR                 | Memory write to  0FE <- 30\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:1B          MREQ RD                    | Memory read from 005 -> 1B\n#053H T8  AB:0FF DB:21          MREQ    WR                 | Memory write to  0FF <- 21\n#056H T11 AB:0FE DB:34          MREQ    WR                 | Memory write to  0FE <- 34\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:1C          MREQ RD                    | Memory read from 005 -> 1C\n#053H T8  AB:0FF DB:22          MREQ    WR                 | Memory write to  0FF <- 22\n#056H T11 AB:0FE DB:34          MREQ    WR                 | Memory write to  0FE <- 34\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:1D          MREQ RD                    | Memory read from 005 -> 1D\n#053H T8  AB:0FF DB:23          MREQ    WR                 | Memory write to  0FF <- 23\n#056H T11 AB:0FE DB:30          MREQ    WR                 | Memory write to  0FE <- 30\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:1E          MREQ RD                    | Memory read from 005 -> 1E\n#053H T8  AB:0FF DB:24          MREQ    WR                 | Memory write to  0FF <- 24\n#056H T11 AB:0FE DB:34          MREQ    WR                 | Memory write to  0FE <- 34\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:1F          MREQ RD                    | Memory read from 005 -> 1F\n#053H T8  AB:0FF DB:25          MREQ    WR                 | Memory write to  0FF <- 25\n#056H T11 AB:0FE DB:30          MREQ    WR                 | Memory write to  0FE <- 30\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:20          MREQ RD                    | Memory read from 005 -> 20\n#053H T8  AB:0FF DB:20          MREQ    WR                 | Memory write to  0FF <- 20\n#056H T11 AB:0FE DB:20          MREQ    WR                 | Memory write to  0FE <- 20\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:21          MREQ RD                    | Memory read from 005 -> 21\n#053H T8  AB:0FF DB:21          MREQ    WR                 | Memory write to  0FF <- 21\n#056H T11 AB:0FE DB:24          MREQ    WR                 | Memory write to  0FE <- 24\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:22          MREQ RD                    | Memory read from 005 -> 22\n#053H T8  AB:0FF DB:22          MREQ    WR                 | Memory write to  0FF <- 22\n#056H T11 AB:0FE DB:24          MREQ    WR                 | Memory write to  0FE <- 24\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:23          MREQ RD                    | Memory read from 005 -> 23\n#053H T8  AB:0FF DB:23          MREQ    WR                 | Memory write to  0FF <- 23\n#056H T11 AB:0FE DB:20          MREQ    WR                 | Memory write to  0FE <- 20\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:24          MREQ RD                    | Memory read from 005 -> 24\n#053H T8  AB:0FF DB:24          MREQ    WR                 | Memory write to  0FF <- 24\n#056H T11 AB:0FE DB:24          MREQ    WR                 | Memory write to  0FE <- 24\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:25          MREQ RD                    | Memory read from 005 -> 25\n#053H T8  AB:0FF DB:25          MREQ    WR                 | Memory write to  0FF <- 25\n#056H T11 AB:0FE DB:20          MREQ    WR                 | Memory write to  0FE <- 20\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:26          MREQ RD                    | Memory read from 005 -> 26\n#053H T8  AB:0FF DB:26          MREQ    WR                 | Memory write to  0FF <- 26\n#056H T11 AB:0FE DB:20          MREQ    WR                 | Memory write to  0FE <- 20\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:27          MREQ RD                    | Memory read from 005 -> 27\n#053H T8  AB:0FF DB:27          MREQ    WR                 | Memory write to  0FF <- 27\n#056H T11 AB:0FE DB:24          MREQ    WR                 | Memory write to  0FE <- 24\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:28          MREQ RD                    | Memory read from 005 -> 28\n#053H T8  AB:0FF DB:28          MREQ    WR                 | Memory write to  0FF <- 28\n#056H T11 AB:0FE DB:2C          MREQ    WR                 | Memory write to  0FE <- 2C\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:29          MREQ RD                    | Memory read from 005 -> 29\n#053H T8  AB:0FF DB:29          MREQ    WR                 | Memory write to  0FF <- 29\n#056H T11 AB:0FE DB:28          MREQ    WR                 | Memory write to  0FE <- 28\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:2A          MREQ RD                    | Memory read from 005 -> 2A\n#053H T8  AB:0FF DB:30          MREQ    WR                 | Memory write to  0FF <- 30\n#056H T11 AB:0FE DB:34          MREQ    WR                 | Memory write to  0FE <- 34\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:2B          MREQ RD                    | Memory read from 005 -> 2B\n#053H T8  AB:0FF DB:31          MREQ    WR                 | Memory write to  0FF <- 31\n#056H T11 AB:0FE DB:30          MREQ    WR                 | Memory write to  0FE <- 30\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:2C          MREQ RD                    | Memory read from 005 -> 2C\n#053H T8  AB:0FF DB:32          MREQ    WR                 | Memory write to  0FF <- 32\n#056H T11 AB:0FE DB:30          MREQ    WR                 | Memory write to  0FE <- 30\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:2D          MREQ RD                    | Memory read from 005 -> 2D\n#053H T8  AB:0FF DB:33          MREQ    WR                 | Memory write to  0FF <- 33\n#056H T11 AB:0FE DB:34          MREQ    WR                 | Memory write to  0FE <- 34\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:2E          MREQ RD                    | Memory read from 005 -> 2E\n#053H T8  AB:0FF DB:34          MREQ    WR                 | Memory write to  0FF <- 34\n#056H T11 AB:0FE DB:30          MREQ    WR                 | Memory write to  0FE <- 30\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:2F          MREQ RD                    | Memory read from 005 -> 2F\n#053H T8  AB:0FF DB:35          MREQ    WR                 | Memory write to  0FF <- 35\n#056H T11 AB:0FE DB:34          MREQ    WR                 | Memory write to  0FE <- 34\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:30          MREQ RD                    | Memory read from 005 -> 30\n#053H T8  AB:0FF DB:30          MREQ    WR                 | Memory write to  0FF <- 30\n#056H T11 AB:0FE DB:24          MREQ    WR                 | Memory write to  0FE <- 24\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:31          MREQ RD                    | Memory read from 005 -> 31\n#053H T8  AB:0FF DB:31          MREQ    WR                 | Memory write to  0FF <- 31\n#056H T11 AB:0FE DB:20          MREQ    WR                 | Memory write to  0FE <- 20\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:32          MREQ RD                    | Memory read from 005 -> 32\n#053H T8  AB:0FF DB:32          MREQ    WR                 | Memory write to  0FF <- 32\n#056H T11 AB:0FE DB:20          MREQ    WR                 | Memory write to  0FE <- 20\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:33          MREQ RD                    | Memory read from 005 -> 33\n#053H T8  AB:0FF DB:33          MREQ    WR                 | Memory write to  0FF <- 33\n#056H T11 AB:0FE DB:24          MREQ    WR                 | Memory write to  0FE <- 24\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:34          MREQ RD                    | Memory read from 005 -> 34\n#053H T8  AB:0FF DB:34          MREQ    WR                 | Memory write to  0FF <- 34\n#056H T11 AB:0FE DB:20          MREQ    WR                 | Memory write to  0FE <- 20\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:35          MREQ RD                    | Memory read from 005 -> 35\n#053H T8  AB:0FF DB:35          MREQ    WR                 | Memory write to  0FF <- 35\n#056H T11 AB:0FE DB:24          MREQ    WR                 | Memory write to  0FE <- 24\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:36          MREQ RD                    | Memory read from 005 -> 36\n#053H T8  AB:0FF DB:36          MREQ    WR                 | Memory write to  0FF <- 36\n#056H T11 AB:0FE DB:24          MREQ    WR                 | Memory write to  0FE <- 24\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:37          MREQ RD                    | Memory read from 005 -> 37\n#053H T8  AB:0FF DB:37          MREQ    WR                 | Memory write to  0FF <- 37\n#056H T11 AB:0FE DB:20          MREQ    WR                 | Memory write to  0FE <- 20\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:38          MREQ RD                    | Memory read from 005 -> 38\n#053H T8  AB:0FF DB:38          MREQ    WR                 | Memory write to  0FF <- 38\n#056H T11 AB:0FE DB:28          MREQ    WR                 | Memory write to  0FE <- 28\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:39          MREQ RD                    | Memory read from 005 -> 39\n#053H T8  AB:0FF DB:39          MREQ    WR                 | Memory write to  0FF <- 39\n#056H T11 AB:0FE DB:2C          MREQ    WR                 | Memory write to  0FE <- 2C\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:3A          MREQ RD                    | Memory read from 005 -> 3A\n#053H T8  AB:0FF DB:40          MREQ    WR                 | Memory write to  0FF <- 40\n#056H T11 AB:0FE DB:10          MREQ    WR                 | Memory write to  0FE <- 10\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:3B          MREQ RD                    | Memory read from 005 -> 3B\n#053H T8  AB:0FF DB:41          MREQ    WR                 | Memory write to  0FF <- 41\n#056H T11 AB:0FE DB:14          MREQ    WR                 | Memory write to  0FE <- 14\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:3C          MREQ RD                    | Memory read from 005 -> 3C\n#053H T8  AB:0FF DB:42          MREQ    WR                 | Memory write to  0FF <- 42\n#056H T11 AB:0FE DB:14          MREQ    WR                 | Memory write to  0FE <- 14\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:3D          MREQ RD                    | Memory read from 005 -> 3D\n#053H T8  AB:0FF DB:43          MREQ    WR                 | Memory write to  0FF <- 43\n#056H T11 AB:0FE DB:10          MREQ    WR                 | Memory write to  0FE <- 10\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:3E          MREQ RD                    | Memory read from 005 -> 3E\n#053H T8  AB:0FF DB:44          MREQ    WR                 | Memory write to  0FF <- 44\n#056H T11 AB:0FE DB:14          MREQ    WR                 | Memory write to  0FE <- 14\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:3F          MREQ RD                    | Memory read from 005 -> 3F\n#053H T8  AB:0FF DB:45          MREQ    WR                 | Memory write to  0FF <- 45\n#056H T11 AB:0FE DB:10          MREQ    WR                 | Memory write to  0FE <- 10\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:40          MREQ RD                    | Memory read from 005 -> 40\n#053H T8  AB:0FF DB:40          MREQ    WR                 | Memory write to  0FF <- 40\n#056H T11 AB:0FE DB:00          MREQ    WR                 | Memory write to  0FE <- 00\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:41          MREQ RD                    | Memory read from 005 -> 41\n#053H T8  AB:0FF DB:41          MREQ    WR                 | Memory write to  0FF <- 41\n#056H T11 AB:0FE DB:04          MREQ    WR                 | Memory write to  0FE <- 04\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:42          MREQ RD                    | Memory read from 005 -> 42\n#053H T8  AB:0FF DB:42          MREQ    WR                 | Memory write to  0FF <- 42\n#056H T11 AB:0FE DB:04          MREQ    WR                 | Memory write to  0FE <- 04\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:43          MREQ RD                    | Memory read from 005 -> 43\n#053H T8  AB:0FF DB:43          MREQ    WR                 | Memory write to  0FF <- 43\n#056H T11 AB:0FE DB:00          MREQ    WR                 | Memory write to  0FE <- 00\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:44          MREQ RD                    | Memory read from 005 -> 44\n#053H T8  AB:0FF DB:44          MREQ    WR                 | Memory write to  0FF <- 44\n#056H T11 AB:0FE DB:04          MREQ    WR                 | Memory write to  0FE <- 04\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:45          MREQ RD                    | Memory read from 005 -> 45\n#053H T8  AB:0FF DB:45          MREQ    WR                 | Memory write to  0FF <- 45\n#056H T11 AB:0FE DB:00          MREQ    WR                 | Memory write to  0FE <- 00\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:46          MREQ RD                    | Memory read from 005 -> 46\n#053H T8  AB:0FF DB:46          MREQ    WR                 | Memory write to  0FF <- 46\n#056H T11 AB:0FE DB:00          MREQ    WR                 | Memory write to  0FE <- 00\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:47          MREQ RD                    | Memory read from 005 -> 47\n#053H T8  AB:0FF DB:47          MREQ    WR                 | Memory write to  0FF <- 47\n#056H T11 AB:0FE DB:04          MREQ    WR                 | Memory write to  0FE <- 04\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:48          MREQ RD                    | Memory read from 005 -> 48\n#053H T8  AB:0FF DB:48          MREQ    WR                 | Memory write to  0FF <- 48\n#056H T11 AB:0FE DB:0C          MREQ    WR                 | Memory write to  0FE <- 0C\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:49          MREQ RD                    | Memory read from 005 -> 49\n#053H T8  AB:0FF DB:49          MREQ    WR                 | Memory write to  0FF <- 49\n#056H T11 AB:0FE DB:08          MREQ    WR                 | Memory write to  0FE <- 08\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:4A          MREQ RD                    | Memory read from 005 -> 4A\n#053H T8  AB:0FF DB:50          MREQ    WR                 | Memory write to  0FF <- 50\n#056H T11 AB:0FE DB:14          MREQ    WR                 | Memory write to  0FE <- 14\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:4B          MREQ RD                    | Memory read from 005 -> 4B\n#053H T8  AB:0FF DB:51          MREQ    WR                 | Memory write to  0FF <- 51\n#056H T11 AB:0FE DB:10          MREQ    WR                 | Memory write to  0FE <- 10\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:4C          MREQ RD                    | Memory read from 005 -> 4C\n#053H T8  AB:0FF DB:52          MREQ    WR                 | Memory write to  0FF <- 52\n#056H T11 AB:0FE DB:10          MREQ    WR                 | Memory write to  0FE <- 10\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:4D          MREQ RD                    | Memory read from 005 -> 4D\n#053H T8  AB:0FF DB:53          MREQ    WR                 | Memory write to  0FF <- 53\n#056H T11 AB:0FE DB:14          MREQ    WR                 | Memory write to  0FE <- 14\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:4E          MREQ RD                    | Memory read from 005 -> 4E\n#053H T8  AB:0FF DB:54          MREQ    WR                 | Memory write to  0FF <- 54\n#056H T11 AB:0FE DB:10          MREQ    WR                 | Memory write to  0FE <- 10\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:4F          MREQ RD                    | Memory read from 005 -> 4F\n#053H T8  AB:0FF DB:55          MREQ    WR                 | Memory write to  0FF <- 55\n#056H T11 AB:0FE DB:14          MREQ    WR                 | Memory write to  0FE <- 14\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:50          MREQ RD                    | Memory read from 005 -> 50\n#053H T8  AB:0FF DB:50          MREQ    WR                 | Memory write to  0FF <- 50\n#056H T11 AB:0FE DB:04          MREQ    WR                 | Memory write to  0FE <- 04\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:51          MREQ RD                    | Memory read from 005 -> 51\n#053H T8  AB:0FF DB:51          MREQ    WR                 | Memory write to  0FF <- 51\n#056H T11 AB:0FE DB:00          MREQ    WR                 | Memory write to  0FE <- 00\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:52          MREQ RD                    | Memory read from 005 -> 52\n#053H T8  AB:0FF DB:52          MREQ    WR                 | Memory write to  0FF <- 52\n#056H T11 AB:0FE DB:00          MREQ    WR                 | Memory write to  0FE <- 00\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:53          MREQ RD                    | Memory read from 005 -> 53\n#053H T8  AB:0FF DB:53          MREQ    WR                 | Memory write to  0FF <- 53\n#056H T11 AB:0FE DB:04          MREQ    WR                 | Memory write to  0FE <- 04\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:54          MREQ RD                    | Memory read from 005 -> 54\n#053H T8  AB:0FF DB:54          MREQ    WR                 | Memory write to  0FF <- 54\n#056H T11 AB:0FE DB:00          MREQ    WR                 | Memory write to  0FE <- 00\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:55          MREQ RD                    | Memory read from 005 -> 55\n#053H T8  AB:0FF DB:55          MREQ    WR                 | Memory write to  0FF <- 55\n#056H T11 AB:0FE DB:04          MREQ    WR                 | Memory write to  0FE <- 04\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:56          MREQ RD                    | Memory read from 005 -> 56\n#053H T8  AB:0FF DB:56          MREQ    WR                 | Memory write to  0FF <- 56\n#056H T11 AB:0FE DB:04          MREQ    WR                 | Memory write to  0FE <- 04\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:57          MREQ RD                    | Memory read from 005 -> 57\n#053H T8  AB:0FF DB:57          MREQ    WR                 | Memory write to  0FF <- 57\n#056H T11 AB:0FE DB:00          MREQ    WR                 | Memory write to  0FE <- 00\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:58          MREQ RD                    | Memory read from 005 -> 58\n#053H T8  AB:0FF DB:58          MREQ    WR                 | Memory write to  0FF <- 58\n#056H T11 AB:0FE DB:08          MREQ    WR                 | Memory write to  0FE <- 08\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:59          MREQ RD                    | Memory read from 005 -> 59\n#053H T8  AB:0FF DB:59          MREQ    WR                 | Memory write to  0FF <- 59\n#056H T11 AB:0FE DB:0C          MREQ    WR                 | Memory write to  0FE <- 0C\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:5A          MREQ RD                    | Memory read from 005 -> 5A\n#053H T8  AB:0FF DB:60          MREQ    WR                 | Memory write to  0FF <- 60\n#056H T11 AB:0FE DB:34          MREQ    WR                 | Memory write to  0FE <- 34\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:5B          MREQ RD                    | Memory read from 005 -> 5B\n#053H T8  AB:0FF DB:61          MREQ    WR                 | Memory write to  0FF <- 61\n#056H T11 AB:0FE DB:30          MREQ    WR                 | Memory write to  0FE <- 30\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:5C          MREQ RD                    | Memory read from 005 -> 5C\n#053H T8  AB:0FF DB:62          MREQ    WR                 | Memory write to  0FF <- 62\n#056H T11 AB:0FE DB:30          MREQ    WR                 | Memory write to  0FE <- 30\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:5D          MREQ RD                    | Memory read from 005 -> 5D\n#053H T8  AB:0FF DB:63          MREQ    WR                 | Memory write to  0FF <- 63\n#056H T11 AB:0FE DB:34          MREQ    WR                 | Memory write to  0FE <- 34\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:5E          MREQ RD                    | Memory read from 005 -> 5E\n#053H T8  AB:0FF DB:64          MREQ    WR                 | Memory write to  0FF <- 64\n#056H T11 AB:0FE DB:30          MREQ    WR                 | Memory write to  0FE <- 30\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:5F          MREQ RD                    | Memory read from 005 -> 5F\n#053H T8  AB:0FF DB:65          MREQ    WR                 | Memory write to  0FF <- 65\n#056H T11 AB:0FE DB:34          MREQ    WR                 | Memory write to  0FE <- 34\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:60          MREQ RD                    | Memory read from 005 -> 60\n#053H T8  AB:0FF DB:60          MREQ    WR                 | Memory write to  0FF <- 60\n#056H T11 AB:0FE DB:24          MREQ    WR                 | Memory write to  0FE <- 24\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:61          MREQ RD                    | Memory read from 005 -> 61\n#053H T8  AB:0FF DB:61          MREQ    WR                 | Memory write to  0FF <- 61\n#056H T11 AB:0FE DB:20          MREQ    WR                 | Memory write to  0FE <- 20\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:62          MREQ RD                    | Memory read from 005 -> 62\n#053H T8  AB:0FF DB:62          MREQ    WR                 | Memory write to  0FF <- 62\n#056H T11 AB:0FE DB:20          MREQ    WR                 | Memory write to  0FE <- 20\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:63          MREQ RD                    | Memory read from 005 -> 63\n#053H T8  AB:0FF DB:63          MREQ    WR                 | Memory write to  0FF <- 63\n#056H T11 AB:0FE DB:24          MREQ    WR                 | Memory write to  0FE <- 24\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:64          MREQ RD                    | Memory read from 005 -> 64\n#053H T8  AB:0FF DB:64          MREQ    WR                 | Memory write to  0FF <- 64\n#056H T11 AB:0FE DB:20          MREQ    WR                 | Memory write to  0FE <- 20\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:65          MREQ RD                    | Memory read from 005 -> 65\n#053H T8  AB:0FF DB:65          MREQ    WR                 | Memory write to  0FF <- 65\n#056H T11 AB:0FE DB:24          MREQ    WR                 | Memory write to  0FE <- 24\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:66          MREQ RD                    | Memory read from 005 -> 66\n#053H T8  AB:0FF DB:66          MREQ    WR                 | Memory write to  0FF <- 66\n#056H T11 AB:0FE DB:24          MREQ    WR                 | Memory write to  0FE <- 24\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:67          MREQ RD                    | Memory read from 005 -> 67\n#053H T8  AB:0FF DB:67          MREQ    WR                 | Memory write to  0FF <- 67\n#056H T11 AB:0FE DB:20          MREQ    WR                 | Memory write to  0FE <- 20\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:68          MREQ RD                    | Memory read from 005 -> 68\n#053H T8  AB:0FF DB:68          MREQ    WR                 | Memory write to  0FF <- 68\n#056H T11 AB:0FE DB:28          MREQ    WR                 | Memory write to  0FE <- 28\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:69          MREQ RD                    | Memory read from 005 -> 69\n#053H T8  AB:0FF DB:69          MREQ    WR                 | Memory write to  0FF <- 69\n#056H T11 AB:0FE DB:2C          MREQ    WR                 | Memory write to  0FE <- 2C\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:6A          MREQ RD                    | Memory read from 005 -> 6A\n#053H T8  AB:0FF DB:70          MREQ    WR                 | Memory write to  0FF <- 70\n#056H T11 AB:0FE DB:30          MREQ    WR                 | Memory write to  0FE <- 30\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:6B          MREQ RD                    | Memory read from 005 -> 6B\n#053H T8  AB:0FF DB:71          MREQ    WR                 | Memory write to  0FF <- 71\n#056H T11 AB:0FE DB:34          MREQ    WR                 | Memory write to  0FE <- 34\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:6C          MREQ RD                    | Memory read from 005 -> 6C\n#053H T8  AB:0FF DB:72          MREQ    WR                 | Memory write to  0FF <- 72\n#056H T11 AB:0FE DB:34          MREQ    WR                 | Memory write to  0FE <- 34\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:6D          MREQ RD                    | Memory read from 005 -> 6D\n#053H T8  AB:0FF DB:73          MREQ    WR                 | Memory write to  0FF <- 73\n#056H T11 AB:0FE DB:30          MREQ    WR                 | Memory write to  0FE <- 30\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:6E          MREQ RD                    | Memory read from 005 -> 6E\n#053H T8  AB:0FF DB:74          MREQ    WR                 | Memory write to  0FF <- 74\n#056H T11 AB:0FE DB:34          MREQ    WR                 | Memory write to  0FE <- 34\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:6F          MREQ RD                    | Memory read from 005 -> 6F\n#053H T8  AB:0FF DB:75          MREQ    WR                 | Memory write to  0FF <- 75\n#056H T11 AB:0FE DB:30          MREQ    WR                 | Memory write to  0FE <- 30\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:70          MREQ RD                    | Memory read from 005 -> 70\n#053H T8  AB:0FF DB:70          MREQ    WR                 | Memory write to  0FF <- 70\n#056H T11 AB:0FE DB:20          MREQ    WR                 | Memory write to  0FE <- 20\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:71          MREQ RD                    | Memory read from 005 -> 71\n#053H T8  AB:0FF DB:71          MREQ    WR                 | Memory write to  0FF <- 71\n#056H T11 AB:0FE DB:24          MREQ    WR                 | Memory write to  0FE <- 24\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:72          MREQ RD                    | Memory read from 005 -> 72\n#053H T8  AB:0FF DB:72          MREQ    WR                 | Memory write to  0FF <- 72\n#056H T11 AB:0FE DB:24          MREQ    WR                 | Memory write to  0FE <- 24\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:73          MREQ RD                    | Memory read from 005 -> 73\n#053H T8  AB:0FF DB:73          MREQ    WR                 | Memory write to  0FF <- 73\n#056H T11 AB:0FE DB:20          MREQ    WR                 | Memory write to  0FE <- 20\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:74          MREQ RD                    | Memory read from 005 -> 74\n#053H T8  AB:0FF DB:74          MREQ    WR                 | Memory write to  0FF <- 74\n#056H T11 AB:0FE DB:24          MREQ    WR                 | Memory write to  0FE <- 24\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:75          MREQ RD                    | Memory read from 005 -> 75\n#053H T8  AB:0FF DB:75          MREQ    WR                 | Memory write to  0FF <- 75\n#056H T11 AB:0FE DB:20          MREQ    WR                 | Memory write to  0FE <- 20\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:76          MREQ RD                    | Memory read from 005 -> 76\n#053H T8  AB:0FF DB:76          MREQ    WR                 | Memory write to  0FF <- 76\n#056H T11 AB:0FE DB:20          MREQ    WR                 | Memory write to  0FE <- 20\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:77          MREQ RD                    | Memory read from 005 -> 77\n#053H T8  AB:0FF DB:77          MREQ    WR                 | Memory write to  0FF <- 77\n#056H T11 AB:0FE DB:24          MREQ    WR                 | Memory write to  0FE <- 24\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:78          MREQ RD                    | Memory read from 005 -> 78\n#053H T8  AB:0FF DB:78          MREQ    WR                 | Memory write to  0FF <- 78\n#056H T11 AB:0FE DB:2C          MREQ    WR                 | Memory write to  0FE <- 2C\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:79          MREQ RD                    | Memory read from 005 -> 79\n#053H T8  AB:0FF DB:79          MREQ    WR                 | Memory write to  0FF <- 79\n#056H T11 AB:0FE DB:28          MREQ    WR                 | Memory write to  0FE <- 28\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:7A          MREQ RD                    | Memory read from 005 -> 7A\n#053H T8  AB:0FF DB:80          MREQ    WR                 | Memory write to  0FF <- 80\n#056H T11 AB:0FE DB:90          MREQ    WR                 | Memory write to  0FE <- 90\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:7B          MREQ RD                    | Memory read from 005 -> 7B\n#053H T8  AB:0FF DB:81          MREQ    WR                 | Memory write to  0FF <- 81\n#056H T11 AB:0FE DB:94          MREQ    WR                 | Memory write to  0FE <- 94\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:7C          MREQ RD                    | Memory read from 005 -> 7C\n#053H T8  AB:0FF DB:82          MREQ    WR                 | Memory write to  0FF <- 82\n#056H T11 AB:0FE DB:94          MREQ    WR                 | Memory write to  0FE <- 94\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:7D          MREQ RD                    | Memory read from 005 -> 7D\n#053H T8  AB:0FF DB:83          MREQ    WR                 | Memory write to  0FF <- 83\n#056H T11 AB:0FE DB:90          MREQ    WR                 | Memory write to  0FE <- 90\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:7E          MREQ RD                    | Memory read from 005 -> 7E\n#053H T8  AB:0FF DB:84          MREQ    WR                 | Memory write to  0FF <- 84\n#056H T11 AB:0FE DB:94          MREQ    WR                 | Memory write to  0FE <- 94\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:7F          MREQ RD                    | Memory read from 005 -> 7F\n#053H T8  AB:0FF DB:85          MREQ    WR                 | Memory write to  0FF <- 85\n#056H T11 AB:0FE DB:90          MREQ    WR                 | Memory write to  0FE <- 90\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:80          MREQ RD                    | Memory read from 005 -> 80\n#053H T8  AB:0FF DB:80          MREQ    WR                 | Memory write to  0FF <- 80\n#056H T11 AB:0FE DB:80          MREQ    WR                 | Memory write to  0FE <- 80\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:81          MREQ RD                    | Memory read from 005 -> 81\n#053H T8  AB:0FF DB:81          MREQ    WR                 | Memory write to  0FF <- 81\n#056H T11 AB:0FE DB:84          MREQ    WR                 | Memory write to  0FE <- 84\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:82          MREQ RD                    | Memory read from 005 -> 82\n#053H T8  AB:0FF DB:82          MREQ    WR                 | Memory write to  0FF <- 82\n#056H T11 AB:0FE DB:84          MREQ    WR                 | Memory write to  0FE <- 84\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:83          MREQ RD                    | Memory read from 005 -> 83\n#053H T8  AB:0FF DB:83          MREQ    WR                 | Memory write to  0FF <- 83\n#056H T11 AB:0FE DB:80          MREQ    WR                 | Memory write to  0FE <- 80\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:84          MREQ RD                    | Memory read from 005 -> 84\n#053H T8  AB:0FF DB:84          MREQ    WR                 | Memory write to  0FF <- 84\n#056H T11 AB:0FE DB:84          MREQ    WR                 | Memory write to  0FE <- 84\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:85          MREQ RD                    | Memory read from 005 -> 85\n#053H T8  AB:0FF DB:85          MREQ    WR                 | Memory write to  0FF <- 85\n#056H T11 AB:0FE DB:80          MREQ    WR                 | Memory write to  0FE <- 80\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:86          MREQ RD                    | Memory read from 005 -> 86\n#053H T8  AB:0FF DB:86          MREQ    WR                 | Memory write to  0FF <- 86\n#056H T11 AB:0FE DB:80          MREQ    WR                 | Memory write to  0FE <- 80\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:87          MREQ RD                    | Memory read from 005 -> 87\n#053H T8  AB:0FF DB:87          MREQ    WR                 | Memory write to  0FF <- 87\n#056H T11 AB:0FE DB:84          MREQ    WR                 | Memory write to  0FE <- 84\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:88          MREQ RD                    | Memory read from 005 -> 88\n#053H T8  AB:0FF DB:88          MREQ    WR                 | Memory write to  0FF <- 88\n#056H T11 AB:0FE DB:8C          MREQ    WR                 | Memory write to  0FE <- 8C\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:89          MREQ RD                    | Memory read from 005 -> 89\n#053H T8  AB:0FF DB:89          MREQ    WR                 | Memory write to  0FF <- 89\n#056H T11 AB:0FE DB:88          MREQ    WR                 | Memory write to  0FE <- 88\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:8A          MREQ RD                    | Memory read from 005 -> 8A\n#053H T8  AB:0FF DB:90          MREQ    WR                 | Memory write to  0FF <- 90\n#056H T11 AB:0FE DB:94          MREQ    WR                 | Memory write to  0FE <- 94\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:8B          MREQ RD                    | Memory read from 005 -> 8B\n#053H T8  AB:0FF DB:91          MREQ    WR                 | Memory write to  0FF <- 91\n#056H T11 AB:0FE DB:90          MREQ    WR                 | Memory write to  0FE <- 90\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:8C          MREQ RD                    | Memory read from 005 -> 8C\n#053H T8  AB:0FF DB:92          MREQ    WR                 | Memory write to  0FF <- 92\n#056H T11 AB:0FE DB:90          MREQ    WR                 | Memory write to  0FE <- 90\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:8D          MREQ RD                    | Memory read from 005 -> 8D\n#053H T8  AB:0FF DB:93          MREQ    WR                 | Memory write to  0FF <- 93\n#056H T11 AB:0FE DB:94          MREQ    WR                 | Memory write to  0FE <- 94\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:8E          MREQ RD                    | Memory read from 005 -> 8E\n#053H T8  AB:0FF DB:94          MREQ    WR                 | Memory write to  0FF <- 94\n#056H T11 AB:0FE DB:90          MREQ    WR                 | Memory write to  0FE <- 90\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:8F          MREQ RD                    | Memory read from 005 -> 8F\n#053H T8  AB:0FF DB:95          MREQ    WR                 | Memory write to  0FF <- 95\n#056H T11 AB:0FE DB:94          MREQ    WR                 | Memory write to  0FE <- 94\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:90          MREQ RD                    | Memory read from 005 -> 90\n#053H T8  AB:0FF DB:90          MREQ    WR                 | Memory write to  0FF <- 90\n#056H T11 AB:0FE DB:84          MREQ    WR                 | Memory write to  0FE <- 84\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:91          MREQ RD                    | Memory read from 005 -> 91\n#053H T8  AB:0FF DB:91          MREQ    WR                 | Memory write to  0FF <- 91\n#056H T11 AB:0FE DB:80          MREQ    WR                 | Memory write to  0FE <- 80\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:92          MREQ RD                    | Memory read from 005 -> 92\n#053H T8  AB:0FF DB:92          MREQ    WR                 | Memory write to  0FF <- 92\n#056H T11 AB:0FE DB:80          MREQ    WR                 | Memory write to  0FE <- 80\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:93          MREQ RD                    | Memory read from 005 -> 93\n#053H T8  AB:0FF DB:93          MREQ    WR                 | Memory write to  0FF <- 93\n#056H T11 AB:0FE DB:84          MREQ    WR                 | Memory write to  0FE <- 84\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:94          MREQ RD                    | Memory read from 005 -> 94\n#053H T8  AB:0FF DB:94          MREQ    WR                 | Memory write to  0FF <- 94\n#056H T11 AB:0FE DB:80          MREQ    WR                 | Memory write to  0FE <- 80\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:95          MREQ RD                    | Memory read from 005 -> 95\n#053H T8  AB:0FF DB:95          MREQ    WR                 | Memory write to  0FF <- 95\n#056H T11 AB:0FE DB:84          MREQ    WR                 | Memory write to  0FE <- 84\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:96          MREQ RD                    | Memory read from 005 -> 96\n#053H T8  AB:0FF DB:96          MREQ    WR                 | Memory write to  0FF <- 96\n#056H T11 AB:0FE DB:84          MREQ    WR                 | Memory write to  0FE <- 84\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:97          MREQ RD                    | Memory read from 005 -> 97\n#053H T8  AB:0FF DB:97          MREQ    WR                 | Memory write to  0FF <- 97\n#056H T11 AB:0FE DB:80          MREQ    WR                 | Memory write to  0FE <- 80\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:98          MREQ RD                    | Memory read from 005 -> 98\n#053H T8  AB:0FF DB:98          MREQ    WR                 | Memory write to  0FF <- 98\n#056H T11 AB:0FE DB:88          MREQ    WR                 | Memory write to  0FE <- 88\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:99          MREQ RD                    | Memory read from 005 -> 99\n#053H T8  AB:0FF DB:99          MREQ    WR                 | Memory write to  0FF <- 99\n#056H T11 AB:0FE DB:8C          MREQ    WR                 | Memory write to  0FE <- 8C\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:9A          MREQ RD                    | Memory read from 005 -> 9A\n#053H T8  AB:0FF DB:00          MREQ    WR                 | Memory write to  0FF <- 00\n#056H T11 AB:0FE DB:55          MREQ    WR                 | Memory write to  0FE <- 55\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:9B          MREQ RD                    | Memory read from 005 -> 9B\n#053H T8  AB:0FF DB:01          MREQ    WR                 | Memory write to  0FF <- 01\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:9C          MREQ RD                    | Memory read from 005 -> 9C\n#053H T8  AB:0FF DB:02          MREQ    WR                 | Memory write to  0FF <- 02\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:9D          MREQ RD                    | Memory read from 005 -> 9D\n#053H T8  AB:0FF DB:03          MREQ    WR                 | Memory write to  0FF <- 03\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:9E          MREQ RD                    | Memory read from 005 -> 9E\n#053H T8  AB:0FF DB:04          MREQ    WR                 | Memory write to  0FF <- 04\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:9F          MREQ RD                    | Memory read from 005 -> 9F\n#053H T8  AB:0FF DB:05          MREQ    WR                 | Memory write to  0FF <- 05\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:A0          MREQ RD                    | Memory read from 005 -> A0\n#053H T8  AB:0FF DB:00          MREQ    WR                 | Memory write to  0FF <- 00\n#056H T11 AB:0FE DB:45          MREQ    WR                 | Memory write to  0FE <- 45\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:A1          MREQ RD                    | Memory read from 005 -> A1\n#053H T8  AB:0FF DB:01          MREQ    WR                 | Memory write to  0FF <- 01\n#056H T11 AB:0FE DB:01          MREQ    WR                 | Memory write to  0FE <- 01\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:A2          MREQ RD                    | Memory read from 005 -> A2\n#053H T8  AB:0FF DB:02          MREQ    WR                 | Memory write to  0FF <- 02\n#056H T11 AB:0FE DB:01          MREQ    WR                 | Memory write to  0FE <- 01\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:A3          MREQ RD                    | Memory read from 005 -> A3\n#053H T8  AB:0FF DB:03          MREQ    WR                 | Memory write to  0FF <- 03\n#056H T11 AB:0FE DB:05          MREQ    WR                 | Memory write to  0FE <- 05\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:A4          MREQ RD                    | Memory read from 005 -> A4\n#053H T8  AB:0FF DB:04          MREQ    WR                 | Memory write to  0FF <- 04\n#056H T11 AB:0FE DB:01          MREQ    WR                 | Memory write to  0FE <- 01\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:A5          MREQ RD                    | Memory read from 005 -> A5\n#053H T8  AB:0FF DB:05          MREQ    WR                 | Memory write to  0FF <- 05\n#056H T11 AB:0FE DB:05          MREQ    WR                 | Memory write to  0FE <- 05\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:A6          MREQ RD                    | Memory read from 005 -> A6\n#053H T8  AB:0FF DB:06          MREQ    WR                 | Memory write to  0FF <- 06\n#056H T11 AB:0FE DB:05          MREQ    WR                 | Memory write to  0FE <- 05\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:A7          MREQ RD                    | Memory read from 005 -> A7\n#053H T8  AB:0FF DB:07          MREQ    WR                 | Memory write to  0FF <- 07\n#056H T11 AB:0FE DB:01          MREQ    WR                 | Memory write to  0FE <- 01\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:A8          MREQ RD                    | Memory read from 005 -> A8\n#053H T8  AB:0FF DB:08          MREQ    WR                 | Memory write to  0FF <- 08\n#056H T11 AB:0FE DB:09          MREQ    WR                 | Memory write to  0FE <- 09\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:A9          MREQ RD                    | Memory read from 005 -> A9\n#053H T8  AB:0FF DB:09          MREQ    WR                 | Memory write to  0FF <- 09\n#056H T11 AB:0FE DB:0D          MREQ    WR                 | Memory write to  0FE <- 0D\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:AA          MREQ RD                    | Memory read from 005 -> AA\n#053H T8  AB:0FF DB:10          MREQ    WR                 | Memory write to  0FF <- 10\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:AB          MREQ RD                    | Memory read from 005 -> AB\n#053H T8  AB:0FF DB:11          MREQ    WR                 | Memory write to  0FF <- 11\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:AC          MREQ RD                    | Memory read from 005 -> AC\n#053H T8  AB:0FF DB:12          MREQ    WR                 | Memory write to  0FF <- 12\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:AD          MREQ RD                    | Memory read from 005 -> AD\n#053H T8  AB:0FF DB:13          MREQ    WR                 | Memory write to  0FF <- 13\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:AE          MREQ RD                    | Memory read from 005 -> AE\n#053H T8  AB:0FF DB:14          MREQ    WR                 | Memory write to  0FF <- 14\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:AF          MREQ RD                    | Memory read from 005 -> AF\n#053H T8  AB:0FF DB:15          MREQ    WR                 | Memory write to  0FF <- 15\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:B0          MREQ RD                    | Memory read from 005 -> B0\n#053H T8  AB:0FF DB:10          MREQ    WR                 | Memory write to  0FF <- 10\n#056H T11 AB:0FE DB:01          MREQ    WR                 | Memory write to  0FE <- 01\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:B1          MREQ RD                    | Memory read from 005 -> B1\n#053H T8  AB:0FF DB:11          MREQ    WR                 | Memory write to  0FF <- 11\n#056H T11 AB:0FE DB:05          MREQ    WR                 | Memory write to  0FE <- 05\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:B2          MREQ RD                    | Memory read from 005 -> B2\n#053H T8  AB:0FF DB:12          MREQ    WR                 | Memory write to  0FF <- 12\n#056H T11 AB:0FE DB:05          MREQ    WR                 | Memory write to  0FE <- 05\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:B3          MREQ RD                    | Memory read from 005 -> B3\n#053H T8  AB:0FF DB:13          MREQ    WR                 | Memory write to  0FF <- 13\n#056H T11 AB:0FE DB:01          MREQ    WR                 | Memory write to  0FE <- 01\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:B4          MREQ RD                    | Memory read from 005 -> B4\n#053H T8  AB:0FF DB:14          MREQ    WR                 | Memory write to  0FF <- 14\n#056H T11 AB:0FE DB:05          MREQ    WR                 | Memory write to  0FE <- 05\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:B5          MREQ RD                    | Memory read from 005 -> B5\n#053H T8  AB:0FF DB:15          MREQ    WR                 | Memory write to  0FF <- 15\n#056H T11 AB:0FE DB:01          MREQ    WR                 | Memory write to  0FE <- 01\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:B6          MREQ RD                    | Memory read from 005 -> B6\n#053H T8  AB:0FF DB:16          MREQ    WR                 | Memory write to  0FF <- 16\n#056H T11 AB:0FE DB:01          MREQ    WR                 | Memory write to  0FE <- 01\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:B7          MREQ RD                    | Memory read from 005 -> B7\n#053H T8  AB:0FF DB:17          MREQ    WR                 | Memory write to  0FF <- 17\n#056H T11 AB:0FE DB:05          MREQ    WR                 | Memory write to  0FE <- 05\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:B8          MREQ RD                    | Memory read from 005 -> B8\n#053H T8  AB:0FF DB:18          MREQ    WR                 | Memory write to  0FF <- 18\n#056H T11 AB:0FE DB:0D          MREQ    WR                 | Memory write to  0FE <- 0D\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:B9          MREQ RD                    | Memory read from 005 -> B9\n#053H T8  AB:0FF DB:19          MREQ    WR                 | Memory write to  0FF <- 19\n#056H T11 AB:0FE DB:09          MREQ    WR                 | Memory write to  0FE <- 09\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:BA          MREQ RD                    | Memory read from 005 -> BA\n#053H T8  AB:0FF DB:20          MREQ    WR                 | Memory write to  0FF <- 20\n#056H T11 AB:0FE DB:31          MREQ    WR                 | Memory write to  0FE <- 31\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:BB          MREQ RD                    | Memory read from 005 -> BB\n#053H T8  AB:0FF DB:21          MREQ    WR                 | Memory write to  0FF <- 21\n#056H T11 AB:0FE DB:35          MREQ    WR                 | Memory write to  0FE <- 35\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:BC          MREQ RD                    | Memory read from 005 -> BC\n#053H T8  AB:0FF DB:22          MREQ    WR                 | Memory write to  0FF <- 22\n#056H T11 AB:0FE DB:35          MREQ    WR                 | Memory write to  0FE <- 35\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:BD          MREQ RD                    | Memory read from 005 -> BD\n#053H T8  AB:0FF DB:23          MREQ    WR                 | Memory write to  0FF <- 23\n#056H T11 AB:0FE DB:31          MREQ    WR                 | Memory write to  0FE <- 31\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:BE          MREQ RD                    | Memory read from 005 -> BE\n#053H T8  AB:0FF DB:24          MREQ    WR                 | Memory write to  0FF <- 24\n#056H T11 AB:0FE DB:35          MREQ    WR                 | Memory write to  0FE <- 35\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:BF          MREQ RD                    | Memory read from 005 -> BF\n#053H T8  AB:0FF DB:25          MREQ    WR                 | Memory write to  0FF <- 25\n#056H T11 AB:0FE DB:31          MREQ    WR                 | Memory write to  0FE <- 31\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:C0          MREQ RD                    | Memory read from 005 -> C0\n#053H T8  AB:0FF DB:20          MREQ    WR                 | Memory write to  0FF <- 20\n#056H T11 AB:0FE DB:21          MREQ    WR                 | Memory write to  0FE <- 21\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:C1          MREQ RD                    | Memory read from 005 -> C1\n#053H T8  AB:0FF DB:21          MREQ    WR                 | Memory write to  0FF <- 21\n#056H T11 AB:0FE DB:25          MREQ    WR                 | Memory write to  0FE <- 25\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:C2          MREQ RD                    | Memory read from 005 -> C2\n#053H T8  AB:0FF DB:22          MREQ    WR                 | Memory write to  0FF <- 22\n#056H T11 AB:0FE DB:25          MREQ    WR                 | Memory write to  0FE <- 25\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:C3          MREQ RD                    | Memory read from 005 -> C3\n#053H T8  AB:0FF DB:23          MREQ    WR                 | Memory write to  0FF <- 23\n#056H T11 AB:0FE DB:21          MREQ    WR                 | Memory write to  0FE <- 21\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:C4          MREQ RD                    | Memory read from 005 -> C4\n#053H T8  AB:0FF DB:24          MREQ    WR                 | Memory write to  0FF <- 24\n#056H T11 AB:0FE DB:25          MREQ    WR                 | Memory write to  0FE <- 25\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:C5          MREQ RD                    | Memory read from 005 -> C5\n#053H T8  AB:0FF DB:25          MREQ    WR                 | Memory write to  0FF <- 25\n#056H T11 AB:0FE DB:21          MREQ    WR                 | Memory write to  0FE <- 21\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:C6          MREQ RD                    | Memory read from 005 -> C6\n#053H T8  AB:0FF DB:26          MREQ    WR                 | Memory write to  0FF <- 26\n#056H T11 AB:0FE DB:21          MREQ    WR                 | Memory write to  0FE <- 21\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:C7          MREQ RD                    | Memory read from 005 -> C7\n#053H T8  AB:0FF DB:27          MREQ    WR                 | Memory write to  0FF <- 27\n#056H T11 AB:0FE DB:25          MREQ    WR                 | Memory write to  0FE <- 25\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:C8          MREQ RD                    | Memory read from 005 -> C8\n#053H T8  AB:0FF DB:28          MREQ    WR                 | Memory write to  0FF <- 28\n#056H T11 AB:0FE DB:2D          MREQ    WR                 | Memory write to  0FE <- 2D\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:C9          MREQ RD                    | Memory read from 005 -> C9\n#053H T8  AB:0FF DB:29          MREQ    WR                 | Memory write to  0FF <- 29\n#056H T11 AB:0FE DB:29          MREQ    WR                 | Memory write to  0FE <- 29\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:CA          MREQ RD                    | Memory read from 005 -> CA\n#053H T8  AB:0FF DB:30          MREQ    WR                 | Memory write to  0FF <- 30\n#056H T11 AB:0FE DB:35          MREQ    WR                 | Memory write to  0FE <- 35\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:CB          MREQ RD                    | Memory read from 005 -> CB\n#053H T8  AB:0FF DB:31          MREQ    WR                 | Memory write to  0FF <- 31\n#056H T11 AB:0FE DB:31          MREQ    WR                 | Memory write to  0FE <- 31\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:CC          MREQ RD                    | Memory read from 005 -> CC\n#053H T8  AB:0FF DB:32          MREQ    WR                 | Memory write to  0FF <- 32\n#056H T11 AB:0FE DB:31          MREQ    WR                 | Memory write to  0FE <- 31\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:CD          MREQ RD                    | Memory read from 005 -> CD\n#053H T8  AB:0FF DB:33          MREQ    WR                 | Memory write to  0FF <- 33\n#056H T11 AB:0FE DB:35          MREQ    WR                 | Memory write to  0FE <- 35\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:CE          MREQ RD                    | Memory read from 005 -> CE\n#053H T8  AB:0FF DB:34          MREQ    WR                 | Memory write to  0FF <- 34\n#056H T11 AB:0FE DB:31          MREQ    WR                 | Memory write to  0FE <- 31\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:CF          MREQ RD                    | Memory read from 005 -> CF\n#053H T8  AB:0FF DB:35          MREQ    WR                 | Memory write to  0FF <- 35\n#056H T11 AB:0FE DB:35          MREQ    WR                 | Memory write to  0FE <- 35\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:D0          MREQ RD                    | Memory read from 005 -> D0\n#053H T8  AB:0FF DB:30          MREQ    WR                 | Memory write to  0FF <- 30\n#056H T11 AB:0FE DB:25          MREQ    WR                 | Memory write to  0FE <- 25\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:D1          MREQ RD                    | Memory read from 005 -> D1\n#053H T8  AB:0FF DB:31          MREQ    WR                 | Memory write to  0FF <- 31\n#056H T11 AB:0FE DB:21          MREQ    WR                 | Memory write to  0FE <- 21\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:D2          MREQ RD                    | Memory read from 005 -> D2\n#053H T8  AB:0FF DB:32          MREQ    WR                 | Memory write to  0FF <- 32\n#056H T11 AB:0FE DB:21          MREQ    WR                 | Memory write to  0FE <- 21\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:D3          MREQ RD                    | Memory read from 005 -> D3\n#053H T8  AB:0FF DB:33          MREQ    WR                 | Memory write to  0FF <- 33\n#056H T11 AB:0FE DB:25          MREQ    WR                 | Memory write to  0FE <- 25\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:D4          MREQ RD                    | Memory read from 005 -> D4\n#053H T8  AB:0FF DB:34          MREQ    WR                 | Memory write to  0FF <- 34\n#056H T11 AB:0FE DB:21          MREQ    WR                 | Memory write to  0FE <- 21\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:D5          MREQ RD                    | Memory read from 005 -> D5\n#053H T8  AB:0FF DB:35          MREQ    WR                 | Memory write to  0FF <- 35\n#056H T11 AB:0FE DB:25          MREQ    WR                 | Memory write to  0FE <- 25\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:D6          MREQ RD                    | Memory read from 005 -> D6\n#053H T8  AB:0FF DB:36          MREQ    WR                 | Memory write to  0FF <- 36\n#056H T11 AB:0FE DB:25          MREQ    WR                 | Memory write to  0FE <- 25\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:D7          MREQ RD                    | Memory read from 005 -> D7\n#053H T8  AB:0FF DB:37          MREQ    WR                 | Memory write to  0FF <- 37\n#056H T11 AB:0FE DB:21          MREQ    WR                 | Memory write to  0FE <- 21\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:D8          MREQ RD                    | Memory read from 005 -> D8\n#053H T8  AB:0FF DB:38          MREQ    WR                 | Memory write to  0FF <- 38\n#056H T11 AB:0FE DB:29          MREQ    WR                 | Memory write to  0FE <- 29\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:D9          MREQ RD                    | Memory read from 005 -> D9\n#053H T8  AB:0FF DB:39          MREQ    WR                 | Memory write to  0FF <- 39\n#056H T11 AB:0FE DB:2D          MREQ    WR                 | Memory write to  0FE <- 2D\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:DA          MREQ RD                    | Memory read from 005 -> DA\n#053H T8  AB:0FF DB:40          MREQ    WR                 | Memory write to  0FF <- 40\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:DB          MREQ RD                    | Memory read from 005 -> DB\n#053H T8  AB:0FF DB:41          MREQ    WR                 | Memory write to  0FF <- 41\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:DC          MREQ RD                    | Memory read from 005 -> DC\n#053H T8  AB:0FF DB:42          MREQ    WR                 | Memory write to  0FF <- 42\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:DD          MREQ RD                    | Memory read from 005 -> DD\n#053H T8  AB:0FF DB:43          MREQ    WR                 | Memory write to  0FF <- 43\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:DE          MREQ RD                    | Memory read from 005 -> DE\n#053H T8  AB:0FF DB:44          MREQ    WR                 | Memory write to  0FF <- 44\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:DF          MREQ RD                    | Memory read from 005 -> DF\n#053H T8  AB:0FF DB:45          MREQ    WR                 | Memory write to  0FF <- 45\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:E0          MREQ RD                    | Memory read from 005 -> E0\n#053H T8  AB:0FF DB:40          MREQ    WR                 | Memory write to  0FF <- 40\n#056H T11 AB:0FE DB:01          MREQ    WR                 | Memory write to  0FE <- 01\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:E1          MREQ RD                    | Memory read from 005 -> E1\n#053H T8  AB:0FF DB:41          MREQ    WR                 | Memory write to  0FF <- 41\n#056H T11 AB:0FE DB:05          MREQ    WR                 | Memory write to  0FE <- 05\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:E2          MREQ RD                    | Memory read from 005 -> E2\n#053H T8  AB:0FF DB:42          MREQ    WR                 | Memory write to  0FF <- 42\n#056H T11 AB:0FE DB:05          MREQ    WR                 | Memory write to  0FE <- 05\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:E3          MREQ RD                    | Memory read from 005 -> E3\n#053H T8  AB:0FF DB:43          MREQ    WR                 | Memory write to  0FF <- 43\n#056H T11 AB:0FE DB:01          MREQ    WR                 | Memory write to  0FE <- 01\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:E4          MREQ RD                    | Memory read from 005 -> E4\n#053H T8  AB:0FF DB:44          MREQ    WR                 | Memory write to  0FF <- 44\n#056H T11 AB:0FE DB:05          MREQ    WR                 | Memory write to  0FE <- 05\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:E5          MREQ RD                    | Memory read from 005 -> E5\n#053H T8  AB:0FF DB:45          MREQ    WR                 | Memory write to  0FF <- 45\n#056H T11 AB:0FE DB:01          MREQ    WR                 | Memory write to  0FE <- 01\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:E6          MREQ RD                    | Memory read from 005 -> E6\n#053H T8  AB:0FF DB:46          MREQ    WR                 | Memory write to  0FF <- 46\n#056H T11 AB:0FE DB:01          MREQ    WR                 | Memory write to  0FE <- 01\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:E7          MREQ RD                    | Memory read from 005 -> E7\n#053H T8  AB:0FF DB:47          MREQ    WR                 | Memory write to  0FF <- 47\n#056H T11 AB:0FE DB:05          MREQ    WR                 | Memory write to  0FE <- 05\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:E8          MREQ RD                    | Memory read from 005 -> E8\n#053H T8  AB:0FF DB:48          MREQ    WR                 | Memory write to  0FF <- 48\n#056H T11 AB:0FE DB:0D          MREQ    WR                 | Memory write to  0FE <- 0D\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:E9          MREQ RD                    | Memory read from 005 -> E9\n#053H T8  AB:0FF DB:49          MREQ    WR                 | Memory write to  0FF <- 49\n#056H T11 AB:0FE DB:09          MREQ    WR                 | Memory write to  0FE <- 09\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:EA          MREQ RD                    | Memory read from 005 -> EA\n#053H T8  AB:0FF DB:50          MREQ    WR                 | Memory write to  0FF <- 50\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:EB          MREQ RD                    | Memory read from 005 -> EB\n#053H T8  AB:0FF DB:51          MREQ    WR                 | Memory write to  0FF <- 51\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:EC          MREQ RD                    | Memory read from 005 -> EC\n#053H T8  AB:0FF DB:52          MREQ    WR                 | Memory write to  0FF <- 52\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:ED          MREQ RD                    | Memory read from 005 -> ED\n#053H T8  AB:0FF DB:53          MREQ    WR                 | Memory write to  0FF <- 53\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:EE          MREQ RD                    | Memory read from 005 -> EE\n#053H T8  AB:0FF DB:54          MREQ    WR                 | Memory write to  0FF <- 54\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:EF          MREQ RD                    | Memory read from 005 -> EF\n#053H T8  AB:0FF DB:55          MREQ    WR                 | Memory write to  0FF <- 55\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:F0          MREQ RD                    | Memory read from 005 -> F0\n#053H T8  AB:0FF DB:50          MREQ    WR                 | Memory write to  0FF <- 50\n#056H T11 AB:0FE DB:05          MREQ    WR                 | Memory write to  0FE <- 05\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:F1          MREQ RD                    | Memory read from 005 -> F1\n#053H T8  AB:0FF DB:51          MREQ    WR                 | Memory write to  0FF <- 51\n#056H T11 AB:0FE DB:01          MREQ    WR                 | Memory write to  0FE <- 01\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:F2          MREQ RD                    | Memory read from 005 -> F2\n#053H T8  AB:0FF DB:52          MREQ    WR                 | Memory write to  0FF <- 52\n#056H T11 AB:0FE DB:01          MREQ    WR                 | Memory write to  0FE <- 01\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:F3          MREQ RD                    | Memory read from 005 -> F3\n#053H T8  AB:0FF DB:53          MREQ    WR                 | Memory write to  0FF <- 53\n#056H T11 AB:0FE DB:05          MREQ    WR                 | Memory write to  0FE <- 05\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:F4          MREQ RD                    | Memory read from 005 -> F4\n#053H T8  AB:0FF DB:54          MREQ    WR                 | Memory write to  0FF <- 54\n#056H T11 AB:0FE DB:01          MREQ    WR                 | Memory write to  0FE <- 01\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:F5          MREQ RD                    | Memory read from 005 -> F5\n#053H T8  AB:0FF DB:55          MREQ    WR                 | Memory write to  0FF <- 55\n#056H T11 AB:0FE DB:05          MREQ    WR                 | Memory write to  0FE <- 05\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:F6          MREQ RD                    | Memory read from 005 -> F6\n#053H T8  AB:0FF DB:56          MREQ    WR                 | Memory write to  0FF <- 56\n#056H T11 AB:0FE DB:05          MREQ    WR                 | Memory write to  0FE <- 05\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:F7          MREQ RD                    | Memory read from 005 -> F7\n#053H T8  AB:0FF DB:57          MREQ    WR                 | Memory write to  0FF <- 57\n#056H T11 AB:0FE DB:01          MREQ    WR                 | Memory write to  0FE <- 01\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:F8          MREQ RD                    | Memory read from 005 -> F8\n#053H T8  AB:0FF DB:58          MREQ    WR                 | Memory write to  0FF <- 58\n#056H T11 AB:0FE DB:09          MREQ    WR                 | Memory write to  0FE <- 09\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:F9          MREQ RD                    | Memory read from 005 -> F9\n#053H T8  AB:0FF DB:59          MREQ    WR                 | Memory write to  0FF <- 59\n#056H T11 AB:0FE DB:0D          MREQ    WR                 | Memory write to  0FE <- 0D\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:FA          MREQ RD                    | Memory read from 005 -> FA\n#053H T8  AB:0FF DB:60          MREQ    WR                 | Memory write to  0FF <- 60\n#056H T11 AB:0FE DB:35          MREQ    WR                 | Memory write to  0FE <- 35\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:FB          MREQ RD                    | Memory read from 005 -> FB\n#053H T8  AB:0FF DB:61          MREQ    WR                 | Memory write to  0FF <- 61\n#056H T11 AB:0FE DB:31          MREQ    WR                 | Memory write to  0FE <- 31\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:FC          MREQ RD                    | Memory read from 005 -> FC\n#053H T8  AB:0FF DB:62          MREQ    WR                 | Memory write to  0FF <- 62\n#056H T11 AB:0FE DB:31          MREQ    WR                 | Memory write to  0FE <- 31\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:FD          MREQ RD                    | Memory read from 005 -> FD\n#053H T8  AB:0FF DB:63          MREQ    WR                 | Memory write to  0FF <- 63\n#056H T11 AB:0FE DB:35          MREQ    WR                 | Memory write to  0FE <- 35\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:FE          MREQ RD                    | Memory read from 005 -> FE\n#053H T8  AB:0FF DB:64          MREQ    WR                 | Memory write to  0FF <- 64\n#056H T11 AB:0FE DB:31          MREQ    WR                 | Memory write to  0FE <- 31\n#017H T7  AB:004 DB:00          MREQ RD                    | Memory read from 004 -> 00\n#020H T10 AB:005 DB:FF          MREQ RD                    | Memory read from 005 -> FF\n#053H T8  AB:0FF DB:65          MREQ    WR                 | Memory write to  0FF <- 65\n#056H T11 AB:0FE DB:35          MREQ    WR                 | Memory write to  0FE <- 35\n"
  },
  {
    "path": "tools/dongle/daa/daa_a-0c.out",
    "content": "#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:00          MREQ RD                    | Memory read from 005 -> 00\n#053H T8  AB:0FF DB:60          MREQ    WR                 | Memory write to  0FF <- 60\n#056H T11 AB:0FE DB:25          MREQ    WR                 | Memory write to  0FE <- 25\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:01          MREQ RD                    | Memory read from 005 -> 01\n#053H T8  AB:0FF DB:61          MREQ    WR                 | Memory write to  0FF <- 61\n#056H T11 AB:0FE DB:21          MREQ    WR                 | Memory write to  0FE <- 21\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:02          MREQ RD                    | Memory read from 005 -> 02\n#053H T8  AB:0FF DB:62          MREQ    WR                 | Memory write to  0FF <- 62\n#056H T11 AB:0FE DB:21          MREQ    WR                 | Memory write to  0FE <- 21\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:03          MREQ RD                    | Memory read from 005 -> 03\n#053H T8  AB:0FF DB:63          MREQ    WR                 | Memory write to  0FF <- 63\n#056H T11 AB:0FE DB:25          MREQ    WR                 | Memory write to  0FE <- 25\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:04          MREQ RD                    | Memory read from 005 -> 04\n#053H T8  AB:0FF DB:64          MREQ    WR                 | Memory write to  0FF <- 64\n#056H T11 AB:0FE DB:21          MREQ    WR                 | Memory write to  0FE <- 21\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:05          MREQ RD                    | Memory read from 005 -> 05\n#053H T8  AB:0FF DB:65          MREQ    WR                 | Memory write to  0FF <- 65\n#056H T11 AB:0FE DB:25          MREQ    WR                 | Memory write to  0FE <- 25\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:06          MREQ RD                    | Memory read from 005 -> 06\n#053H T8  AB:0FF DB:66          MREQ    WR                 | Memory write to  0FF <- 66\n#056H T11 AB:0FE DB:25          MREQ    WR                 | Memory write to  0FE <- 25\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:07          MREQ RD                    | Memory read from 005 -> 07\n#053H T8  AB:0FF DB:67          MREQ    WR                 | Memory write to  0FF <- 67\n#056H T11 AB:0FE DB:21          MREQ    WR                 | Memory write to  0FE <- 21\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:08          MREQ RD                    | Memory read from 005 -> 08\n#053H T8  AB:0FF DB:68          MREQ    WR                 | Memory write to  0FF <- 68\n#056H T11 AB:0FE DB:29          MREQ    WR                 | Memory write to  0FE <- 29\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:09          MREQ RD                    | Memory read from 005 -> 09\n#053H T8  AB:0FF DB:69          MREQ    WR                 | Memory write to  0FF <- 69\n#056H T11 AB:0FE DB:2D          MREQ    WR                 | Memory write to  0FE <- 2D\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:0A          MREQ RD                    | Memory read from 005 -> 0A\n#053H T8  AB:0FF DB:70          MREQ    WR                 | Memory write to  0FF <- 70\n#056H T11 AB:0FE DB:31          MREQ    WR                 | Memory write to  0FE <- 31\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:0B          MREQ RD                    | Memory read from 005 -> 0B\n#053H T8  AB:0FF DB:71          MREQ    WR                 | Memory write to  0FF <- 71\n#056H T11 AB:0FE DB:35          MREQ    WR                 | Memory write to  0FE <- 35\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:0C          MREQ RD                    | Memory read from 005 -> 0C\n#053H T8  AB:0FF DB:72          MREQ    WR                 | Memory write to  0FF <- 72\n#056H T11 AB:0FE DB:35          MREQ    WR                 | Memory write to  0FE <- 35\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:0D          MREQ RD                    | Memory read from 005 -> 0D\n#053H T8  AB:0FF DB:73          MREQ    WR                 | Memory write to  0FF <- 73\n#056H T11 AB:0FE DB:31          MREQ    WR                 | Memory write to  0FE <- 31\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:0E          MREQ RD                    | Memory read from 005 -> 0E\n#053H T8  AB:0FF DB:74          MREQ    WR                 | Memory write to  0FF <- 74\n#056H T11 AB:0FE DB:35          MREQ    WR                 | Memory write to  0FE <- 35\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:0F          MREQ RD                    | Memory read from 005 -> 0F\n#053H T8  AB:0FF DB:75          MREQ    WR                 | Memory write to  0FF <- 75\n#056H T11 AB:0FE DB:31          MREQ    WR                 | Memory write to  0FE <- 31\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:10          MREQ RD                    | Memory read from 005 -> 10\n#053H T8  AB:0FF DB:70          MREQ    WR                 | Memory write to  0FF <- 70\n#056H T11 AB:0FE DB:21          MREQ    WR                 | Memory write to  0FE <- 21\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:11          MREQ RD                    | Memory read from 005 -> 11\n#053H T8  AB:0FF DB:71          MREQ    WR                 | Memory write to  0FF <- 71\n#056H T11 AB:0FE DB:25          MREQ    WR                 | Memory write to  0FE <- 25\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:12          MREQ RD                    | Memory read from 005 -> 12\n#053H T8  AB:0FF DB:72          MREQ    WR                 | Memory write to  0FF <- 72\n#056H T11 AB:0FE DB:25          MREQ    WR                 | Memory write to  0FE <- 25\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:13          MREQ RD                    | Memory read from 005 -> 13\n#053H T8  AB:0FF DB:73          MREQ    WR                 | Memory write to  0FF <- 73\n#056H T11 AB:0FE DB:21          MREQ    WR                 | Memory write to  0FE <- 21\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:14          MREQ RD                    | Memory read from 005 -> 14\n#053H T8  AB:0FF DB:74          MREQ    WR                 | Memory write to  0FF <- 74\n#056H T11 AB:0FE DB:25          MREQ    WR                 | Memory write to  0FE <- 25\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:15          MREQ RD                    | Memory read from 005 -> 15\n#053H T8  AB:0FF DB:75          MREQ    WR                 | Memory write to  0FF <- 75\n#056H T11 AB:0FE DB:21          MREQ    WR                 | Memory write to  0FE <- 21\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:16          MREQ RD                    | Memory read from 005 -> 16\n#053H T8  AB:0FF DB:76          MREQ    WR                 | Memory write to  0FF <- 76\n#056H T11 AB:0FE DB:21          MREQ    WR                 | Memory write to  0FE <- 21\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:17          MREQ RD                    | Memory read from 005 -> 17\n#053H T8  AB:0FF DB:77          MREQ    WR                 | Memory write to  0FF <- 77\n#056H T11 AB:0FE DB:25          MREQ    WR                 | Memory write to  0FE <- 25\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:18          MREQ RD                    | Memory read from 005 -> 18\n#053H T8  AB:0FF DB:78          MREQ    WR                 | Memory write to  0FF <- 78\n#056H T11 AB:0FE DB:2D          MREQ    WR                 | Memory write to  0FE <- 2D\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:19          MREQ RD                    | Memory read from 005 -> 19\n#053H T8  AB:0FF DB:79          MREQ    WR                 | Memory write to  0FF <- 79\n#056H T11 AB:0FE DB:29          MREQ    WR                 | Memory write to  0FE <- 29\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:1A          MREQ RD                    | Memory read from 005 -> 1A\n#053H T8  AB:0FF DB:80          MREQ    WR                 | Memory write to  0FF <- 80\n#056H T11 AB:0FE DB:91          MREQ    WR                 | Memory write to  0FE <- 91\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:1B          MREQ RD                    | Memory read from 005 -> 1B\n#053H T8  AB:0FF DB:81          MREQ    WR                 | Memory write to  0FF <- 81\n#056H T11 AB:0FE DB:95          MREQ    WR                 | Memory write to  0FE <- 95\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:1C          MREQ RD                    | Memory read from 005 -> 1C\n#053H T8  AB:0FF DB:82          MREQ    WR                 | Memory write to  0FF <- 82\n#056H T11 AB:0FE DB:95          MREQ    WR                 | Memory write to  0FE <- 95\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:1D          MREQ RD                    | Memory read from 005 -> 1D\n#053H T8  AB:0FF DB:83          MREQ    WR                 | Memory write to  0FF <- 83\n#056H T11 AB:0FE DB:91          MREQ    WR                 | Memory write to  0FE <- 91\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:1E          MREQ RD                    | Memory read from 005 -> 1E\n#053H T8  AB:0FF DB:84          MREQ    WR                 | Memory write to  0FF <- 84\n#056H T11 AB:0FE DB:95          MREQ    WR                 | Memory write to  0FE <- 95\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:1F          MREQ RD                    | Memory read from 005 -> 1F\n#053H T8  AB:0FF DB:85          MREQ    WR                 | Memory write to  0FF <- 85\n#056H T11 AB:0FE DB:91          MREQ    WR                 | Memory write to  0FE <- 91\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:20          MREQ RD                    | Memory read from 005 -> 20\n#053H T8  AB:0FF DB:80          MREQ    WR                 | Memory write to  0FF <- 80\n#056H T11 AB:0FE DB:81          MREQ    WR                 | Memory write to  0FE <- 81\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:21          MREQ RD                    | Memory read from 005 -> 21\n#053H T8  AB:0FF DB:81          MREQ    WR                 | Memory write to  0FF <- 81\n#056H T11 AB:0FE DB:85          MREQ    WR                 | Memory write to  0FE <- 85\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:22          MREQ RD                    | Memory read from 005 -> 22\n#053H T8  AB:0FF DB:82          MREQ    WR                 | Memory write to  0FF <- 82\n#056H T11 AB:0FE DB:85          MREQ    WR                 | Memory write to  0FE <- 85\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:23          MREQ RD                    | Memory read from 005 -> 23\n#053H T8  AB:0FF DB:83          MREQ    WR                 | Memory write to  0FF <- 83\n#056H T11 AB:0FE DB:81          MREQ    WR                 | Memory write to  0FE <- 81\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:24          MREQ RD                    | Memory read from 005 -> 24\n#053H T8  AB:0FF DB:84          MREQ    WR                 | Memory write to  0FF <- 84\n#056H T11 AB:0FE DB:85          MREQ    WR                 | Memory write to  0FE <- 85\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:25          MREQ RD                    | Memory read from 005 -> 25\n#053H T8  AB:0FF DB:85          MREQ    WR                 | Memory write to  0FF <- 85\n#056H T11 AB:0FE DB:81          MREQ    WR                 | Memory write to  0FE <- 81\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:26          MREQ RD                    | Memory read from 005 -> 26\n#053H T8  AB:0FF DB:86          MREQ    WR                 | Memory write to  0FF <- 86\n#056H T11 AB:0FE DB:81          MREQ    WR                 | Memory write to  0FE <- 81\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:27          MREQ RD                    | Memory read from 005 -> 27\n#053H T8  AB:0FF DB:87          MREQ    WR                 | Memory write to  0FF <- 87\n#056H T11 AB:0FE DB:85          MREQ    WR                 | Memory write to  0FE <- 85\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:28          MREQ RD                    | Memory read from 005 -> 28\n#053H T8  AB:0FF DB:88          MREQ    WR                 | Memory write to  0FF <- 88\n#056H T11 AB:0FE DB:8D          MREQ    WR                 | Memory write to  0FE <- 8D\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:29          MREQ RD                    | Memory read from 005 -> 29\n#053H T8  AB:0FF DB:89          MREQ    WR                 | Memory write to  0FF <- 89\n#056H T11 AB:0FE DB:89          MREQ    WR                 | Memory write to  0FE <- 89\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:2A          MREQ RD                    | Memory read from 005 -> 2A\n#053H T8  AB:0FF DB:90          MREQ    WR                 | Memory write to  0FF <- 90\n#056H T11 AB:0FE DB:95          MREQ    WR                 | Memory write to  0FE <- 95\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:2B          MREQ RD                    | Memory read from 005 -> 2B\n#053H T8  AB:0FF DB:91          MREQ    WR                 | Memory write to  0FF <- 91\n#056H T11 AB:0FE DB:91          MREQ    WR                 | Memory write to  0FE <- 91\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:2C          MREQ RD                    | Memory read from 005 -> 2C\n#053H T8  AB:0FF DB:92          MREQ    WR                 | Memory write to  0FF <- 92\n#056H T11 AB:0FE DB:91          MREQ    WR                 | Memory write to  0FE <- 91\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:2D          MREQ RD                    | Memory read from 005 -> 2D\n#053H T8  AB:0FF DB:93          MREQ    WR                 | Memory write to  0FF <- 93\n#056H T11 AB:0FE DB:95          MREQ    WR                 | Memory write to  0FE <- 95\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:2E          MREQ RD                    | Memory read from 005 -> 2E\n#053H T8  AB:0FF DB:94          MREQ    WR                 | Memory write to  0FF <- 94\n#056H T11 AB:0FE DB:91          MREQ    WR                 | Memory write to  0FE <- 91\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:2F          MREQ RD                    | Memory read from 005 -> 2F\n#053H T8  AB:0FF DB:95          MREQ    WR                 | Memory write to  0FF <- 95\n#056H T11 AB:0FE DB:95          MREQ    WR                 | Memory write to  0FE <- 95\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:30          MREQ RD                    | Memory read from 005 -> 30\n#053H T8  AB:0FF DB:90          MREQ    WR                 | Memory write to  0FF <- 90\n#056H T11 AB:0FE DB:85          MREQ    WR                 | Memory write to  0FE <- 85\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:31          MREQ RD                    | Memory read from 005 -> 31\n#053H T8  AB:0FF DB:91          MREQ    WR                 | Memory write to  0FF <- 91\n#056H T11 AB:0FE DB:81          MREQ    WR                 | Memory write to  0FE <- 81\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:32          MREQ RD                    | Memory read from 005 -> 32\n#053H T8  AB:0FF DB:92          MREQ    WR                 | Memory write to  0FF <- 92\n#056H T11 AB:0FE DB:81          MREQ    WR                 | Memory write to  0FE <- 81\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:33          MREQ RD                    | Memory read from 005 -> 33\n#053H T8  AB:0FF DB:93          MREQ    WR                 | Memory write to  0FF <- 93\n#056H T11 AB:0FE DB:85          MREQ    WR                 | Memory write to  0FE <- 85\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:34          MREQ RD                    | Memory read from 005 -> 34\n#053H T8  AB:0FF DB:94          MREQ    WR                 | Memory write to  0FF <- 94\n#056H T11 AB:0FE DB:81          MREQ    WR                 | Memory write to  0FE <- 81\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:35          MREQ RD                    | Memory read from 005 -> 35\n#053H T8  AB:0FF DB:95          MREQ    WR                 | Memory write to  0FF <- 95\n#056H T11 AB:0FE DB:85          MREQ    WR                 | Memory write to  0FE <- 85\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:36          MREQ RD                    | Memory read from 005 -> 36\n#053H T8  AB:0FF DB:96          MREQ    WR                 | Memory write to  0FF <- 96\n#056H T11 AB:0FE DB:85          MREQ    WR                 | Memory write to  0FE <- 85\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:37          MREQ RD                    | Memory read from 005 -> 37\n#053H T8  AB:0FF DB:97          MREQ    WR                 | Memory write to  0FF <- 97\n#056H T11 AB:0FE DB:81          MREQ    WR                 | Memory write to  0FE <- 81\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:38          MREQ RD                    | Memory read from 005 -> 38\n#053H T8  AB:0FF DB:98          MREQ    WR                 | Memory write to  0FF <- 98\n#056H T11 AB:0FE DB:89          MREQ    WR                 | Memory write to  0FE <- 89\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:39          MREQ RD                    | Memory read from 005 -> 39\n#053H T8  AB:0FF DB:99          MREQ    WR                 | Memory write to  0FF <- 99\n#056H T11 AB:0FE DB:8D          MREQ    WR                 | Memory write to  0FE <- 8D\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:3A          MREQ RD                    | Memory read from 005 -> 3A\n#053H T8  AB:0FF DB:A0          MREQ    WR                 | Memory write to  0FF <- A0\n#056H T11 AB:0FE DB:B5          MREQ    WR                 | Memory write to  0FE <- B5\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:3B          MREQ RD                    | Memory read from 005 -> 3B\n#053H T8  AB:0FF DB:A1          MREQ    WR                 | Memory write to  0FF <- A1\n#056H T11 AB:0FE DB:B1          MREQ    WR                 | Memory write to  0FE <- B1\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:3C          MREQ RD                    | Memory read from 005 -> 3C\n#053H T8  AB:0FF DB:A2          MREQ    WR                 | Memory write to  0FF <- A2\n#056H T11 AB:0FE DB:B1          MREQ    WR                 | Memory write to  0FE <- B1\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:3D          MREQ RD                    | Memory read from 005 -> 3D\n#053H T8  AB:0FF DB:A3          MREQ    WR                 | Memory write to  0FF <- A3\n#056H T11 AB:0FE DB:B5          MREQ    WR                 | Memory write to  0FE <- B5\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:3E          MREQ RD                    | Memory read from 005 -> 3E\n#053H T8  AB:0FF DB:A4          MREQ    WR                 | Memory write to  0FF <- A4\n#056H T11 AB:0FE DB:B1          MREQ    WR                 | Memory write to  0FE <- B1\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:3F          MREQ RD                    | Memory read from 005 -> 3F\n#053H T8  AB:0FF DB:A5          MREQ    WR                 | Memory write to  0FF <- A5\n#056H T11 AB:0FE DB:B5          MREQ    WR                 | Memory write to  0FE <- B5\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:40          MREQ RD                    | Memory read from 005 -> 40\n#053H T8  AB:0FF DB:A0          MREQ    WR                 | Memory write to  0FF <- A0\n#056H T11 AB:0FE DB:A5          MREQ    WR                 | Memory write to  0FE <- A5\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:41          MREQ RD                    | Memory read from 005 -> 41\n#053H T8  AB:0FF DB:A1          MREQ    WR                 | Memory write to  0FF <- A1\n#056H T11 AB:0FE DB:A1          MREQ    WR                 | Memory write to  0FE <- A1\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:42          MREQ RD                    | Memory read from 005 -> 42\n#053H T8  AB:0FF DB:A2          MREQ    WR                 | Memory write to  0FF <- A2\n#056H T11 AB:0FE DB:A1          MREQ    WR                 | Memory write to  0FE <- A1\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:43          MREQ RD                    | Memory read from 005 -> 43\n#053H T8  AB:0FF DB:A3          MREQ    WR                 | Memory write to  0FF <- A3\n#056H T11 AB:0FE DB:A5          MREQ    WR                 | Memory write to  0FE <- A5\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:44          MREQ RD                    | Memory read from 005 -> 44\n#053H T8  AB:0FF DB:A4          MREQ    WR                 | Memory write to  0FF <- A4\n#056H T11 AB:0FE DB:A1          MREQ    WR                 | Memory write to  0FE <- A1\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:45          MREQ RD                    | Memory read from 005 -> 45\n#053H T8  AB:0FF DB:A5          MREQ    WR                 | Memory write to  0FF <- A5\n#056H T11 AB:0FE DB:A5          MREQ    WR                 | Memory write to  0FE <- A5\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:46          MREQ RD                    | Memory read from 005 -> 46\n#053H T8  AB:0FF DB:A6          MREQ    WR                 | Memory write to  0FF <- A6\n#056H T11 AB:0FE DB:A5          MREQ    WR                 | Memory write to  0FE <- A5\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:47          MREQ RD                    | Memory read from 005 -> 47\n#053H T8  AB:0FF DB:A7          MREQ    WR                 | Memory write to  0FF <- A7\n#056H T11 AB:0FE DB:A1          MREQ    WR                 | Memory write to  0FE <- A1\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:48          MREQ RD                    | Memory read from 005 -> 48\n#053H T8  AB:0FF DB:A8          MREQ    WR                 | Memory write to  0FF <- A8\n#056H T11 AB:0FE DB:A9          MREQ    WR                 | Memory write to  0FE <- A9\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:49          MREQ RD                    | Memory read from 005 -> 49\n#053H T8  AB:0FF DB:A9          MREQ    WR                 | Memory write to  0FF <- A9\n#056H T11 AB:0FE DB:AD          MREQ    WR                 | Memory write to  0FE <- AD\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:4A          MREQ RD                    | Memory read from 005 -> 4A\n#053H T8  AB:0FF DB:B0          MREQ    WR                 | Memory write to  0FF <- B0\n#056H T11 AB:0FE DB:B1          MREQ    WR                 | Memory write to  0FE <- B1\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:4B          MREQ RD                    | Memory read from 005 -> 4B\n#053H T8  AB:0FF DB:B1          MREQ    WR                 | Memory write to  0FF <- B1\n#056H T11 AB:0FE DB:B5          MREQ    WR                 | Memory write to  0FE <- B5\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:4C          MREQ RD                    | Memory read from 005 -> 4C\n#053H T8  AB:0FF DB:B2          MREQ    WR                 | Memory write to  0FF <- B2\n#056H T11 AB:0FE DB:B5          MREQ    WR                 | Memory write to  0FE <- B5\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:4D          MREQ RD                    | Memory read from 005 -> 4D\n#053H T8  AB:0FF DB:B3          MREQ    WR                 | Memory write to  0FF <- B3\n#056H T11 AB:0FE DB:B1          MREQ    WR                 | Memory write to  0FE <- B1\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:4E          MREQ RD                    | Memory read from 005 -> 4E\n#053H T8  AB:0FF DB:B4          MREQ    WR                 | Memory write to  0FF <- B4\n#056H T11 AB:0FE DB:B5          MREQ    WR                 | Memory write to  0FE <- B5\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:4F          MREQ RD                    | Memory read from 005 -> 4F\n#053H T8  AB:0FF DB:B5          MREQ    WR                 | Memory write to  0FF <- B5\n#056H T11 AB:0FE DB:B1          MREQ    WR                 | Memory write to  0FE <- B1\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:50          MREQ RD                    | Memory read from 005 -> 50\n#053H T8  AB:0FF DB:B0          MREQ    WR                 | Memory write to  0FF <- B0\n#056H T11 AB:0FE DB:A1          MREQ    WR                 | Memory write to  0FE <- A1\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:51          MREQ RD                    | Memory read from 005 -> 51\n#053H T8  AB:0FF DB:B1          MREQ    WR                 | Memory write to  0FF <- B1\n#056H T11 AB:0FE DB:A5          MREQ    WR                 | Memory write to  0FE <- A5\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:52          MREQ RD                    | Memory read from 005 -> 52\n#053H T8  AB:0FF DB:B2          MREQ    WR                 | Memory write to  0FF <- B2\n#056H T11 AB:0FE DB:A5          MREQ    WR                 | Memory write to  0FE <- A5\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:53          MREQ RD                    | Memory read from 005 -> 53\n#053H T8  AB:0FF DB:B3          MREQ    WR                 | Memory write to  0FF <- B3\n#056H T11 AB:0FE DB:A1          MREQ    WR                 | Memory write to  0FE <- A1\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:54          MREQ RD                    | Memory read from 005 -> 54\n#053H T8  AB:0FF DB:B4          MREQ    WR                 | Memory write to  0FF <- B4\n#056H T11 AB:0FE DB:A5          MREQ    WR                 | Memory write to  0FE <- A5\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:55          MREQ RD                    | Memory read from 005 -> 55\n#053H T8  AB:0FF DB:B5          MREQ    WR                 | Memory write to  0FF <- B5\n#056H T11 AB:0FE DB:A1          MREQ    WR                 | Memory write to  0FE <- A1\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:56          MREQ RD                    | Memory read from 005 -> 56\n#053H T8  AB:0FF DB:B6          MREQ    WR                 | Memory write to  0FF <- B6\n#056H T11 AB:0FE DB:A1          MREQ    WR                 | Memory write to  0FE <- A1\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:57          MREQ RD                    | Memory read from 005 -> 57\n#053H T8  AB:0FF DB:B7          MREQ    WR                 | Memory write to  0FF <- B7\n#056H T11 AB:0FE DB:A5          MREQ    WR                 | Memory write to  0FE <- A5\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:58          MREQ RD                    | Memory read from 005 -> 58\n#053H T8  AB:0FF DB:B8          MREQ    WR                 | Memory write to  0FF <- B8\n#056H T11 AB:0FE DB:AD          MREQ    WR                 | Memory write to  0FE <- AD\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:59          MREQ RD                    | Memory read from 005 -> 59\n#053H T8  AB:0FF DB:B9          MREQ    WR                 | Memory write to  0FF <- B9\n#056H T11 AB:0FE DB:A9          MREQ    WR                 | Memory write to  0FE <- A9\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:5A          MREQ RD                    | Memory read from 005 -> 5A\n#053H T8  AB:0FF DB:C0          MREQ    WR                 | Memory write to  0FF <- C0\n#056H T11 AB:0FE DB:95          MREQ    WR                 | Memory write to  0FE <- 95\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:5B          MREQ RD                    | Memory read from 005 -> 5B\n#053H T8  AB:0FF DB:C1          MREQ    WR                 | Memory write to  0FF <- C1\n#056H T11 AB:0FE DB:91          MREQ    WR                 | Memory write to  0FE <- 91\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:5C          MREQ RD                    | Memory read from 005 -> 5C\n#053H T8  AB:0FF DB:C2          MREQ    WR                 | Memory write to  0FF <- C2\n#056H T11 AB:0FE DB:91          MREQ    WR                 | Memory write to  0FE <- 91\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:5D          MREQ RD                    | Memory read from 005 -> 5D\n#053H T8  AB:0FF DB:C3          MREQ    WR                 | Memory write to  0FF <- C3\n#056H T11 AB:0FE DB:95          MREQ    WR                 | Memory write to  0FE <- 95\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:5E          MREQ RD                    | Memory read from 005 -> 5E\n#053H T8  AB:0FF DB:C4          MREQ    WR                 | Memory write to  0FF <- C4\n#056H T11 AB:0FE DB:91          MREQ    WR                 | Memory write to  0FE <- 91\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:5F          MREQ RD                    | Memory read from 005 -> 5F\n#053H T8  AB:0FF DB:C5          MREQ    WR                 | Memory write to  0FF <- C5\n#056H T11 AB:0FE DB:95          MREQ    WR                 | Memory write to  0FE <- 95\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:60          MREQ RD                    | Memory read from 005 -> 60\n#053H T8  AB:0FF DB:C0          MREQ    WR                 | Memory write to  0FF <- C0\n#056H T11 AB:0FE DB:85          MREQ    WR                 | Memory write to  0FE <- 85\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:61          MREQ RD                    | Memory read from 005 -> 61\n#053H T8  AB:0FF DB:C1          MREQ    WR                 | Memory write to  0FF <- C1\n#056H T11 AB:0FE DB:81          MREQ    WR                 | Memory write to  0FE <- 81\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:62          MREQ RD                    | Memory read from 005 -> 62\n#053H T8  AB:0FF DB:C2          MREQ    WR                 | Memory write to  0FF <- C2\n#056H T11 AB:0FE DB:81          MREQ    WR                 | Memory write to  0FE <- 81\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:63          MREQ RD                    | Memory read from 005 -> 63\n#053H T8  AB:0FF DB:C3          MREQ    WR                 | Memory write to  0FF <- C3\n#056H T11 AB:0FE DB:85          MREQ    WR                 | Memory write to  0FE <- 85\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:64          MREQ RD                    | Memory read from 005 -> 64\n#053H T8  AB:0FF DB:C4          MREQ    WR                 | Memory write to  0FF <- C4\n#056H T11 AB:0FE DB:81          MREQ    WR                 | Memory write to  0FE <- 81\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:65          MREQ RD                    | Memory read from 005 -> 65\n#053H T8  AB:0FF DB:C5          MREQ    WR                 | Memory write to  0FF <- C5\n#056H T11 AB:0FE DB:85          MREQ    WR                 | Memory write to  0FE <- 85\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:66          MREQ RD                    | Memory read from 005 -> 66\n#053H T8  AB:0FF DB:C6          MREQ    WR                 | Memory write to  0FF <- C6\n#056H T11 AB:0FE DB:85          MREQ    WR                 | Memory write to  0FE <- 85\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:67          MREQ RD                    | Memory read from 005 -> 67\n#053H T8  AB:0FF DB:C7          MREQ    WR                 | Memory write to  0FF <- C7\n#056H T11 AB:0FE DB:81          MREQ    WR                 | Memory write to  0FE <- 81\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:68          MREQ RD                    | Memory read from 005 -> 68\n#053H T8  AB:0FF DB:C8          MREQ    WR                 | Memory write to  0FF <- C8\n#056H T11 AB:0FE DB:89          MREQ    WR                 | Memory write to  0FE <- 89\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:69          MREQ RD                    | Memory read from 005 -> 69\n#053H T8  AB:0FF DB:C9          MREQ    WR                 | Memory write to  0FF <- C9\n#056H T11 AB:0FE DB:8D          MREQ    WR                 | Memory write to  0FE <- 8D\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:6A          MREQ RD                    | Memory read from 005 -> 6A\n#053H T8  AB:0FF DB:D0          MREQ    WR                 | Memory write to  0FF <- D0\n#056H T11 AB:0FE DB:91          MREQ    WR                 | Memory write to  0FE <- 91\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:6B          MREQ RD                    | Memory read from 005 -> 6B\n#053H T8  AB:0FF DB:D1          MREQ    WR                 | Memory write to  0FF <- D1\n#056H T11 AB:0FE DB:95          MREQ    WR                 | Memory write to  0FE <- 95\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:6C          MREQ RD                    | Memory read from 005 -> 6C\n#053H T8  AB:0FF DB:D2          MREQ    WR                 | Memory write to  0FF <- D2\n#056H T11 AB:0FE DB:95          MREQ    WR                 | Memory write to  0FE <- 95\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:6D          MREQ RD                    | Memory read from 005 -> 6D\n#053H T8  AB:0FF DB:D3          MREQ    WR                 | Memory write to  0FF <- D3\n#056H T11 AB:0FE DB:91          MREQ    WR                 | Memory write to  0FE <- 91\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:6E          MREQ RD                    | Memory read from 005 -> 6E\n#053H T8  AB:0FF DB:D4          MREQ    WR                 | Memory write to  0FF <- D4\n#056H T11 AB:0FE DB:95          MREQ    WR                 | Memory write to  0FE <- 95\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:6F          MREQ RD                    | Memory read from 005 -> 6F\n#053H T8  AB:0FF DB:D5          MREQ    WR                 | Memory write to  0FF <- D5\n#056H T11 AB:0FE DB:91          MREQ    WR                 | Memory write to  0FE <- 91\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:70          MREQ RD                    | Memory read from 005 -> 70\n#053H T8  AB:0FF DB:D0          MREQ    WR                 | Memory write to  0FF <- D0\n#056H T11 AB:0FE DB:81          MREQ    WR                 | Memory write to  0FE <- 81\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:71          MREQ RD                    | Memory read from 005 -> 71\n#053H T8  AB:0FF DB:D1          MREQ    WR                 | Memory write to  0FF <- D1\n#056H T11 AB:0FE DB:85          MREQ    WR                 | Memory write to  0FE <- 85\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:72          MREQ RD                    | Memory read from 005 -> 72\n#053H T8  AB:0FF DB:D2          MREQ    WR                 | Memory write to  0FF <- D2\n#056H T11 AB:0FE DB:85          MREQ    WR                 | Memory write to  0FE <- 85\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:73          MREQ RD                    | Memory read from 005 -> 73\n#053H T8  AB:0FF DB:D3          MREQ    WR                 | Memory write to  0FF <- D3\n#056H T11 AB:0FE DB:81          MREQ    WR                 | Memory write to  0FE <- 81\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:74          MREQ RD                    | Memory read from 005 -> 74\n#053H T8  AB:0FF DB:D4          MREQ    WR                 | Memory write to  0FF <- D4\n#056H T11 AB:0FE DB:85          MREQ    WR                 | Memory write to  0FE <- 85\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:75          MREQ RD                    | Memory read from 005 -> 75\n#053H T8  AB:0FF DB:D5          MREQ    WR                 | Memory write to  0FF <- D5\n#056H T11 AB:0FE DB:81          MREQ    WR                 | Memory write to  0FE <- 81\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:76          MREQ RD                    | Memory read from 005 -> 76\n#053H T8  AB:0FF DB:D6          MREQ    WR                 | Memory write to  0FF <- D6\n#056H T11 AB:0FE DB:81          MREQ    WR                 | Memory write to  0FE <- 81\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:77          MREQ RD                    | Memory read from 005 -> 77\n#053H T8  AB:0FF DB:D7          MREQ    WR                 | Memory write to  0FF <- D7\n#056H T11 AB:0FE DB:85          MREQ    WR                 | Memory write to  0FE <- 85\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:78          MREQ RD                    | Memory read from 005 -> 78\n#053H T8  AB:0FF DB:D8          MREQ    WR                 | Memory write to  0FF <- D8\n#056H T11 AB:0FE DB:8D          MREQ    WR                 | Memory write to  0FE <- 8D\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:79          MREQ RD                    | Memory read from 005 -> 79\n#053H T8  AB:0FF DB:D9          MREQ    WR                 | Memory write to  0FF <- D9\n#056H T11 AB:0FE DB:89          MREQ    WR                 | Memory write to  0FE <- 89\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:7A          MREQ RD                    | Memory read from 005 -> 7A\n#053H T8  AB:0FF DB:E0          MREQ    WR                 | Memory write to  0FF <- E0\n#056H T11 AB:0FE DB:B1          MREQ    WR                 | Memory write to  0FE <- B1\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:7B          MREQ RD                    | Memory read from 005 -> 7B\n#053H T8  AB:0FF DB:E1          MREQ    WR                 | Memory write to  0FF <- E1\n#056H T11 AB:0FE DB:B5          MREQ    WR                 | Memory write to  0FE <- B5\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:7C          MREQ RD                    | Memory read from 005 -> 7C\n#053H T8  AB:0FF DB:E2          MREQ    WR                 | Memory write to  0FF <- E2\n#056H T11 AB:0FE DB:B5          MREQ    WR                 | Memory write to  0FE <- B5\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:7D          MREQ RD                    | Memory read from 005 -> 7D\n#053H T8  AB:0FF DB:E3          MREQ    WR                 | Memory write to  0FF <- E3\n#056H T11 AB:0FE DB:B1          MREQ    WR                 | Memory write to  0FE <- B1\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:7E          MREQ RD                    | Memory read from 005 -> 7E\n#053H T8  AB:0FF DB:E4          MREQ    WR                 | Memory write to  0FF <- E4\n#056H T11 AB:0FE DB:B5          MREQ    WR                 | Memory write to  0FE <- B5\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:7F          MREQ RD                    | Memory read from 005 -> 7F\n#053H T8  AB:0FF DB:E5          MREQ    WR                 | Memory write to  0FF <- E5\n#056H T11 AB:0FE DB:B1          MREQ    WR                 | Memory write to  0FE <- B1\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:80          MREQ RD                    | Memory read from 005 -> 80\n#053H T8  AB:0FF DB:E0          MREQ    WR                 | Memory write to  0FF <- E0\n#056H T11 AB:0FE DB:A1          MREQ    WR                 | Memory write to  0FE <- A1\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:81          MREQ RD                    | Memory read from 005 -> 81\n#053H T8  AB:0FF DB:E1          MREQ    WR                 | Memory write to  0FF <- E1\n#056H T11 AB:0FE DB:A5          MREQ    WR                 | Memory write to  0FE <- A5\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:82          MREQ RD                    | Memory read from 005 -> 82\n#053H T8  AB:0FF DB:E2          MREQ    WR                 | Memory write to  0FF <- E2\n#056H T11 AB:0FE DB:A5          MREQ    WR                 | Memory write to  0FE <- A5\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:83          MREQ RD                    | Memory read from 005 -> 83\n#053H T8  AB:0FF DB:E3          MREQ    WR                 | Memory write to  0FF <- E3\n#056H T11 AB:0FE DB:A1          MREQ    WR                 | Memory write to  0FE <- A1\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:84          MREQ RD                    | Memory read from 005 -> 84\n#053H T8  AB:0FF DB:E4          MREQ    WR                 | Memory write to  0FF <- E4\n#056H T11 AB:0FE DB:A5          MREQ    WR                 | Memory write to  0FE <- A5\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:85          MREQ RD                    | Memory read from 005 -> 85\n#053H T8  AB:0FF DB:E5          MREQ    WR                 | Memory write to  0FF <- E5\n#056H T11 AB:0FE DB:A1          MREQ    WR                 | Memory write to  0FE <- A1\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:86          MREQ RD                    | Memory read from 005 -> 86\n#053H T8  AB:0FF DB:E6          MREQ    WR                 | Memory write to  0FF <- E6\n#056H T11 AB:0FE DB:A1          MREQ    WR                 | Memory write to  0FE <- A1\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:87          MREQ RD                    | Memory read from 005 -> 87\n#053H T8  AB:0FF DB:E7          MREQ    WR                 | Memory write to  0FF <- E7\n#056H T11 AB:0FE DB:A5          MREQ    WR                 | Memory write to  0FE <- A5\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:88          MREQ RD                    | Memory read from 005 -> 88\n#053H T8  AB:0FF DB:E8          MREQ    WR                 | Memory write to  0FF <- E8\n#056H T11 AB:0FE DB:AD          MREQ    WR                 | Memory write to  0FE <- AD\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:89          MREQ RD                    | Memory read from 005 -> 89\n#053H T8  AB:0FF DB:E9          MREQ    WR                 | Memory write to  0FF <- E9\n#056H T11 AB:0FE DB:A9          MREQ    WR                 | Memory write to  0FE <- A9\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:8A          MREQ RD                    | Memory read from 005 -> 8A\n#053H T8  AB:0FF DB:F0          MREQ    WR                 | Memory write to  0FF <- F0\n#056H T11 AB:0FE DB:B5          MREQ    WR                 | Memory write to  0FE <- B5\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:8B          MREQ RD                    | Memory read from 005 -> 8B\n#053H T8  AB:0FF DB:F1          MREQ    WR                 | Memory write to  0FF <- F1\n#056H T11 AB:0FE DB:B1          MREQ    WR                 | Memory write to  0FE <- B1\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:8C          MREQ RD                    | Memory read from 005 -> 8C\n#053H T8  AB:0FF DB:F2          MREQ    WR                 | Memory write to  0FF <- F2\n#056H T11 AB:0FE DB:B1          MREQ    WR                 | Memory write to  0FE <- B1\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:8D          MREQ RD                    | Memory read from 005 -> 8D\n#053H T8  AB:0FF DB:F3          MREQ    WR                 | Memory write to  0FF <- F3\n#056H T11 AB:0FE DB:B5          MREQ    WR                 | Memory write to  0FE <- B5\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:8E          MREQ RD                    | Memory read from 005 -> 8E\n#053H T8  AB:0FF DB:F4          MREQ    WR                 | Memory write to  0FF <- F4\n#056H T11 AB:0FE DB:B1          MREQ    WR                 | Memory write to  0FE <- B1\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:8F          MREQ RD                    | Memory read from 005 -> 8F\n#053H T8  AB:0FF DB:F5          MREQ    WR                 | Memory write to  0FF <- F5\n#056H T11 AB:0FE DB:B5          MREQ    WR                 | Memory write to  0FE <- B5\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:90          MREQ RD                    | Memory read from 005 -> 90\n#053H T8  AB:0FF DB:F0          MREQ    WR                 | Memory write to  0FF <- F0\n#056H T11 AB:0FE DB:A5          MREQ    WR                 | Memory write to  0FE <- A5\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:91          MREQ RD                    | Memory read from 005 -> 91\n#053H T8  AB:0FF DB:F1          MREQ    WR                 | Memory write to  0FF <- F1\n#056H T11 AB:0FE DB:A1          MREQ    WR                 | Memory write to  0FE <- A1\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:92          MREQ RD                    | Memory read from 005 -> 92\n#053H T8  AB:0FF DB:F2          MREQ    WR                 | Memory write to  0FF <- F2\n#056H T11 AB:0FE DB:A1          MREQ    WR                 | Memory write to  0FE <- A1\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:93          MREQ RD                    | Memory read from 005 -> 93\n#053H T8  AB:0FF DB:F3          MREQ    WR                 | Memory write to  0FF <- F3\n#056H T11 AB:0FE DB:A5          MREQ    WR                 | Memory write to  0FE <- A5\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:94          MREQ RD                    | Memory read from 005 -> 94\n#053H T8  AB:0FF DB:F4          MREQ    WR                 | Memory write to  0FF <- F4\n#056H T11 AB:0FE DB:A1          MREQ    WR                 | Memory write to  0FE <- A1\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:95          MREQ RD                    | Memory read from 005 -> 95\n#053H T8  AB:0FF DB:F5          MREQ    WR                 | Memory write to  0FF <- F5\n#056H T11 AB:0FE DB:A5          MREQ    WR                 | Memory write to  0FE <- A5\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:96          MREQ RD                    | Memory read from 005 -> 96\n#053H T8  AB:0FF DB:F6          MREQ    WR                 | Memory write to  0FF <- F6\n#056H T11 AB:0FE DB:A5          MREQ    WR                 | Memory write to  0FE <- A5\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:97          MREQ RD                    | Memory read from 005 -> 97\n#053H T8  AB:0FF DB:F7          MREQ    WR                 | Memory write to  0FF <- F7\n#056H T11 AB:0FE DB:A1          MREQ    WR                 | Memory write to  0FE <- A1\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:98          MREQ RD                    | Memory read from 005 -> 98\n#053H T8  AB:0FF DB:F8          MREQ    WR                 | Memory write to  0FF <- F8\n#056H T11 AB:0FE DB:A9          MREQ    WR                 | Memory write to  0FE <- A9\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:99          MREQ RD                    | Memory read from 005 -> 99\n#053H T8  AB:0FF DB:F9          MREQ    WR                 | Memory write to  0FF <- F9\n#056H T11 AB:0FE DB:AD          MREQ    WR                 | Memory write to  0FE <- AD\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:9A          MREQ RD                    | Memory read from 005 -> 9A\n#053H T8  AB:0FF DB:00          MREQ    WR                 | Memory write to  0FF <- 00\n#056H T11 AB:0FE DB:55          MREQ    WR                 | Memory write to  0FE <- 55\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:9B          MREQ RD                    | Memory read from 005 -> 9B\n#053H T8  AB:0FF DB:01          MREQ    WR                 | Memory write to  0FF <- 01\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:9C          MREQ RD                    | Memory read from 005 -> 9C\n#053H T8  AB:0FF DB:02          MREQ    WR                 | Memory write to  0FF <- 02\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:9D          MREQ RD                    | Memory read from 005 -> 9D\n#053H T8  AB:0FF DB:03          MREQ    WR                 | Memory write to  0FF <- 03\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:9E          MREQ RD                    | Memory read from 005 -> 9E\n#053H T8  AB:0FF DB:04          MREQ    WR                 | Memory write to  0FF <- 04\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:9F          MREQ RD                    | Memory read from 005 -> 9F\n#053H T8  AB:0FF DB:05          MREQ    WR                 | Memory write to  0FF <- 05\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:A0          MREQ RD                    | Memory read from 005 -> A0\n#053H T8  AB:0FF DB:00          MREQ    WR                 | Memory write to  0FF <- 00\n#056H T11 AB:0FE DB:45          MREQ    WR                 | Memory write to  0FE <- 45\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:A1          MREQ RD                    | Memory read from 005 -> A1\n#053H T8  AB:0FF DB:01          MREQ    WR                 | Memory write to  0FF <- 01\n#056H T11 AB:0FE DB:01          MREQ    WR                 | Memory write to  0FE <- 01\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:A2          MREQ RD                    | Memory read from 005 -> A2\n#053H T8  AB:0FF DB:02          MREQ    WR                 | Memory write to  0FF <- 02\n#056H T11 AB:0FE DB:01          MREQ    WR                 | Memory write to  0FE <- 01\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:A3          MREQ RD                    | Memory read from 005 -> A3\n#053H T8  AB:0FF DB:03          MREQ    WR                 | Memory write to  0FF <- 03\n#056H T11 AB:0FE DB:05          MREQ    WR                 | Memory write to  0FE <- 05\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:A4          MREQ RD                    | Memory read from 005 -> A4\n#053H T8  AB:0FF DB:04          MREQ    WR                 | Memory write to  0FF <- 04\n#056H T11 AB:0FE DB:01          MREQ    WR                 | Memory write to  0FE <- 01\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:A5          MREQ RD                    | Memory read from 005 -> A5\n#053H T8  AB:0FF DB:05          MREQ    WR                 | Memory write to  0FF <- 05\n#056H T11 AB:0FE DB:05          MREQ    WR                 | Memory write to  0FE <- 05\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:A6          MREQ RD                    | Memory read from 005 -> A6\n#053H T8  AB:0FF DB:06          MREQ    WR                 | Memory write to  0FF <- 06\n#056H T11 AB:0FE DB:05          MREQ    WR                 | Memory write to  0FE <- 05\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:A7          MREQ RD                    | Memory read from 005 -> A7\n#053H T8  AB:0FF DB:07          MREQ    WR                 | Memory write to  0FF <- 07\n#056H T11 AB:0FE DB:01          MREQ    WR                 | Memory write to  0FE <- 01\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:A8          MREQ RD                    | Memory read from 005 -> A8\n#053H T8  AB:0FF DB:08          MREQ    WR                 | Memory write to  0FF <- 08\n#056H T11 AB:0FE DB:09          MREQ    WR                 | Memory write to  0FE <- 09\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:A9          MREQ RD                    | Memory read from 005 -> A9\n#053H T8  AB:0FF DB:09          MREQ    WR                 | Memory write to  0FF <- 09\n#056H T11 AB:0FE DB:0D          MREQ    WR                 | Memory write to  0FE <- 0D\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:AA          MREQ RD                    | Memory read from 005 -> AA\n#053H T8  AB:0FF DB:10          MREQ    WR                 | Memory write to  0FF <- 10\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:AB          MREQ RD                    | Memory read from 005 -> AB\n#053H T8  AB:0FF DB:11          MREQ    WR                 | Memory write to  0FF <- 11\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:AC          MREQ RD                    | Memory read from 005 -> AC\n#053H T8  AB:0FF DB:12          MREQ    WR                 | Memory write to  0FF <- 12\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:AD          MREQ RD                    | Memory read from 005 -> AD\n#053H T8  AB:0FF DB:13          MREQ    WR                 | Memory write to  0FF <- 13\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:AE          MREQ RD                    | Memory read from 005 -> AE\n#053H T8  AB:0FF DB:14          MREQ    WR                 | Memory write to  0FF <- 14\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:AF          MREQ RD                    | Memory read from 005 -> AF\n#053H T8  AB:0FF DB:15          MREQ    WR                 | Memory write to  0FF <- 15\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:B0          MREQ RD                    | Memory read from 005 -> B0\n#053H T8  AB:0FF DB:10          MREQ    WR                 | Memory write to  0FF <- 10\n#056H T11 AB:0FE DB:01          MREQ    WR                 | Memory write to  0FE <- 01\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:B1          MREQ RD                    | Memory read from 005 -> B1\n#053H T8  AB:0FF DB:11          MREQ    WR                 | Memory write to  0FF <- 11\n#056H T11 AB:0FE DB:05          MREQ    WR                 | Memory write to  0FE <- 05\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:B2          MREQ RD                    | Memory read from 005 -> B2\n#053H T8  AB:0FF DB:12          MREQ    WR                 | Memory write to  0FF <- 12\n#056H T11 AB:0FE DB:05          MREQ    WR                 | Memory write to  0FE <- 05\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:B3          MREQ RD                    | Memory read from 005 -> B3\n#053H T8  AB:0FF DB:13          MREQ    WR                 | Memory write to  0FF <- 13\n#056H T11 AB:0FE DB:01          MREQ    WR                 | Memory write to  0FE <- 01\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:B4          MREQ RD                    | Memory read from 005 -> B4\n#053H T8  AB:0FF DB:14          MREQ    WR                 | Memory write to  0FF <- 14\n#056H T11 AB:0FE DB:05          MREQ    WR                 | Memory write to  0FE <- 05\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:B5          MREQ RD                    | Memory read from 005 -> B5\n#053H T8  AB:0FF DB:15          MREQ    WR                 | Memory write to  0FF <- 15\n#056H T11 AB:0FE DB:01          MREQ    WR                 | Memory write to  0FE <- 01\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:B6          MREQ RD                    | Memory read from 005 -> B6\n#053H T8  AB:0FF DB:16          MREQ    WR                 | Memory write to  0FF <- 16\n#056H T11 AB:0FE DB:01          MREQ    WR                 | Memory write to  0FE <- 01\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:B7          MREQ RD                    | Memory read from 005 -> B7\n#053H T8  AB:0FF DB:17          MREQ    WR                 | Memory write to  0FF <- 17\n#056H T11 AB:0FE DB:05          MREQ    WR                 | Memory write to  0FE <- 05\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:B8          MREQ RD                    | Memory read from 005 -> B8\n#053H T8  AB:0FF DB:18          MREQ    WR                 | Memory write to  0FF <- 18\n#056H T11 AB:0FE DB:0D          MREQ    WR                 | Memory write to  0FE <- 0D\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:B9          MREQ RD                    | Memory read from 005 -> B9\n#053H T8  AB:0FF DB:19          MREQ    WR                 | Memory write to  0FF <- 19\n#056H T11 AB:0FE DB:09          MREQ    WR                 | Memory write to  0FE <- 09\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:BA          MREQ RD                    | Memory read from 005 -> BA\n#053H T8  AB:0FF DB:20          MREQ    WR                 | Memory write to  0FF <- 20\n#056H T11 AB:0FE DB:31          MREQ    WR                 | Memory write to  0FE <- 31\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:BB          MREQ RD                    | Memory read from 005 -> BB\n#053H T8  AB:0FF DB:21          MREQ    WR                 | Memory write to  0FF <- 21\n#056H T11 AB:0FE DB:35          MREQ    WR                 | Memory write to  0FE <- 35\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:BC          MREQ RD                    | Memory read from 005 -> BC\n#053H T8  AB:0FF DB:22          MREQ    WR                 | Memory write to  0FF <- 22\n#056H T11 AB:0FE DB:35          MREQ    WR                 | Memory write to  0FE <- 35\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:BD          MREQ RD                    | Memory read from 005 -> BD\n#053H T8  AB:0FF DB:23          MREQ    WR                 | Memory write to  0FF <- 23\n#056H T11 AB:0FE DB:31          MREQ    WR                 | Memory write to  0FE <- 31\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:BE          MREQ RD                    | Memory read from 005 -> BE\n#053H T8  AB:0FF DB:24          MREQ    WR                 | Memory write to  0FF <- 24\n#056H T11 AB:0FE DB:35          MREQ    WR                 | Memory write to  0FE <- 35\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:BF          MREQ RD                    | Memory read from 005 -> BF\n#053H T8  AB:0FF DB:25          MREQ    WR                 | Memory write to  0FF <- 25\n#056H T11 AB:0FE DB:31          MREQ    WR                 | Memory write to  0FE <- 31\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:C0          MREQ RD                    | Memory read from 005 -> C0\n#053H T8  AB:0FF DB:20          MREQ    WR                 | Memory write to  0FF <- 20\n#056H T11 AB:0FE DB:21          MREQ    WR                 | Memory write to  0FE <- 21\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:C1          MREQ RD                    | Memory read from 005 -> C1\n#053H T8  AB:0FF DB:21          MREQ    WR                 | Memory write to  0FF <- 21\n#056H T11 AB:0FE DB:25          MREQ    WR                 | Memory write to  0FE <- 25\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:C2          MREQ RD                    | Memory read from 005 -> C2\n#053H T8  AB:0FF DB:22          MREQ    WR                 | Memory write to  0FF <- 22\n#056H T11 AB:0FE DB:25          MREQ    WR                 | Memory write to  0FE <- 25\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:C3          MREQ RD                    | Memory read from 005 -> C3\n#053H T8  AB:0FF DB:23          MREQ    WR                 | Memory write to  0FF <- 23\n#056H T11 AB:0FE DB:21          MREQ    WR                 | Memory write to  0FE <- 21\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:C4          MREQ RD                    | Memory read from 005 -> C4\n#053H T8  AB:0FF DB:24          MREQ    WR                 | Memory write to  0FF <- 24\n#056H T11 AB:0FE DB:25          MREQ    WR                 | Memory write to  0FE <- 25\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:C5          MREQ RD                    | Memory read from 005 -> C5\n#053H T8  AB:0FF DB:25          MREQ    WR                 | Memory write to  0FF <- 25\n#056H T11 AB:0FE DB:21          MREQ    WR                 | Memory write to  0FE <- 21\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:C6          MREQ RD                    | Memory read from 005 -> C6\n#053H T8  AB:0FF DB:26          MREQ    WR                 | Memory write to  0FF <- 26\n#056H T11 AB:0FE DB:21          MREQ    WR                 | Memory write to  0FE <- 21\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:C7          MREQ RD                    | Memory read from 005 -> C7\n#053H T8  AB:0FF DB:27          MREQ    WR                 | Memory write to  0FF <- 27\n#056H T11 AB:0FE DB:25          MREQ    WR                 | Memory write to  0FE <- 25\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:C8          MREQ RD                    | Memory read from 005 -> C8\n#053H T8  AB:0FF DB:28          MREQ    WR                 | Memory write to  0FF <- 28\n#056H T11 AB:0FE DB:2D          MREQ    WR                 | Memory write to  0FE <- 2D\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:C9          MREQ RD                    | Memory read from 005 -> C9\n#053H T8  AB:0FF DB:29          MREQ    WR                 | Memory write to  0FF <- 29\n#056H T11 AB:0FE DB:29          MREQ    WR                 | Memory write to  0FE <- 29\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:CA          MREQ RD                    | Memory read from 005 -> CA\n#053H T8  AB:0FF DB:30          MREQ    WR                 | Memory write to  0FF <- 30\n#056H T11 AB:0FE DB:35          MREQ    WR                 | Memory write to  0FE <- 35\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:CB          MREQ RD                    | Memory read from 005 -> CB\n#053H T8  AB:0FF DB:31          MREQ    WR                 | Memory write to  0FF <- 31\n#056H T11 AB:0FE DB:31          MREQ    WR                 | Memory write to  0FE <- 31\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:CC          MREQ RD                    | Memory read from 005 -> CC\n#053H T8  AB:0FF DB:32          MREQ    WR                 | Memory write to  0FF <- 32\n#056H T11 AB:0FE DB:31          MREQ    WR                 | Memory write to  0FE <- 31\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:CD          MREQ RD                    | Memory read from 005 -> CD\n#053H T8  AB:0FF DB:33          MREQ    WR                 | Memory write to  0FF <- 33\n#056H T11 AB:0FE DB:35          MREQ    WR                 | Memory write to  0FE <- 35\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:CE          MREQ RD                    | Memory read from 005 -> CE\n#053H T8  AB:0FF DB:34          MREQ    WR                 | Memory write to  0FF <- 34\n#056H T11 AB:0FE DB:31          MREQ    WR                 | Memory write to  0FE <- 31\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:CF          MREQ RD                    | Memory read from 005 -> CF\n#053H T8  AB:0FF DB:35          MREQ    WR                 | Memory write to  0FF <- 35\n#056H T11 AB:0FE DB:35          MREQ    WR                 | Memory write to  0FE <- 35\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:D0          MREQ RD                    | Memory read from 005 -> D0\n#053H T8  AB:0FF DB:30          MREQ    WR                 | Memory write to  0FF <- 30\n#056H T11 AB:0FE DB:25          MREQ    WR                 | Memory write to  0FE <- 25\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:D1          MREQ RD                    | Memory read from 005 -> D1\n#053H T8  AB:0FF DB:31          MREQ    WR                 | Memory write to  0FF <- 31\n#056H T11 AB:0FE DB:21          MREQ    WR                 | Memory write to  0FE <- 21\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:D2          MREQ RD                    | Memory read from 005 -> D2\n#053H T8  AB:0FF DB:32          MREQ    WR                 | Memory write to  0FF <- 32\n#056H T11 AB:0FE DB:21          MREQ    WR                 | Memory write to  0FE <- 21\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:D3          MREQ RD                    | Memory read from 005 -> D3\n#053H T8  AB:0FF DB:33          MREQ    WR                 | Memory write to  0FF <- 33\n#056H T11 AB:0FE DB:25          MREQ    WR                 | Memory write to  0FE <- 25\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:D4          MREQ RD                    | Memory read from 005 -> D4\n#053H T8  AB:0FF DB:34          MREQ    WR                 | Memory write to  0FF <- 34\n#056H T11 AB:0FE DB:21          MREQ    WR                 | Memory write to  0FE <- 21\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:D5          MREQ RD                    | Memory read from 005 -> D5\n#053H T8  AB:0FF DB:35          MREQ    WR                 | Memory write to  0FF <- 35\n#056H T11 AB:0FE DB:25          MREQ    WR                 | Memory write to  0FE <- 25\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:D6          MREQ RD                    | Memory read from 005 -> D6\n#053H T8  AB:0FF DB:36          MREQ    WR                 | Memory write to  0FF <- 36\n#056H T11 AB:0FE DB:25          MREQ    WR                 | Memory write to  0FE <- 25\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:D7          MREQ RD                    | Memory read from 005 -> D7\n#053H T8  AB:0FF DB:37          MREQ    WR                 | Memory write to  0FF <- 37\n#056H T11 AB:0FE DB:21          MREQ    WR                 | Memory write to  0FE <- 21\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:D8          MREQ RD                    | Memory read from 005 -> D8\n#053H T8  AB:0FF DB:38          MREQ    WR                 | Memory write to  0FF <- 38\n#056H T11 AB:0FE DB:29          MREQ    WR                 | Memory write to  0FE <- 29\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:D9          MREQ RD                    | Memory read from 005 -> D9\n#053H T8  AB:0FF DB:39          MREQ    WR                 | Memory write to  0FF <- 39\n#056H T11 AB:0FE DB:2D          MREQ    WR                 | Memory write to  0FE <- 2D\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:DA          MREQ RD                    | Memory read from 005 -> DA\n#053H T8  AB:0FF DB:40          MREQ    WR                 | Memory write to  0FF <- 40\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:DB          MREQ RD                    | Memory read from 005 -> DB\n#053H T8  AB:0FF DB:41          MREQ    WR                 | Memory write to  0FF <- 41\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:DC          MREQ RD                    | Memory read from 005 -> DC\n#053H T8  AB:0FF DB:42          MREQ    WR                 | Memory write to  0FF <- 42\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:DD          MREQ RD                    | Memory read from 005 -> DD\n#053H T8  AB:0FF DB:43          MREQ    WR                 | Memory write to  0FF <- 43\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:DE          MREQ RD                    | Memory read from 005 -> DE\n#053H T8  AB:0FF DB:44          MREQ    WR                 | Memory write to  0FF <- 44\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:DF          MREQ RD                    | Memory read from 005 -> DF\n#053H T8  AB:0FF DB:45          MREQ    WR                 | Memory write to  0FF <- 45\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:E0          MREQ RD                    | Memory read from 005 -> E0\n#053H T8  AB:0FF DB:40          MREQ    WR                 | Memory write to  0FF <- 40\n#056H T11 AB:0FE DB:01          MREQ    WR                 | Memory write to  0FE <- 01\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:E1          MREQ RD                    | Memory read from 005 -> E1\n#053H T8  AB:0FF DB:41          MREQ    WR                 | Memory write to  0FF <- 41\n#056H T11 AB:0FE DB:05          MREQ    WR                 | Memory write to  0FE <- 05\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:E2          MREQ RD                    | Memory read from 005 -> E2\n#053H T8  AB:0FF DB:42          MREQ    WR                 | Memory write to  0FF <- 42\n#056H T11 AB:0FE DB:05          MREQ    WR                 | Memory write to  0FE <- 05\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:E3          MREQ RD                    | Memory read from 005 -> E3\n#053H T8  AB:0FF DB:43          MREQ    WR                 | Memory write to  0FF <- 43\n#056H T11 AB:0FE DB:01          MREQ    WR                 | Memory write to  0FE <- 01\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:E4          MREQ RD                    | Memory read from 005 -> E4\n#053H T8  AB:0FF DB:44          MREQ    WR                 | Memory write to  0FF <- 44\n#056H T11 AB:0FE DB:05          MREQ    WR                 | Memory write to  0FE <- 05\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:E5          MREQ RD                    | Memory read from 005 -> E5\n#053H T8  AB:0FF DB:45          MREQ    WR                 | Memory write to  0FF <- 45\n#056H T11 AB:0FE DB:01          MREQ    WR                 | Memory write to  0FE <- 01\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:E6          MREQ RD                    | Memory read from 005 -> E6\n#053H T8  AB:0FF DB:46          MREQ    WR                 | Memory write to  0FF <- 46\n#056H T11 AB:0FE DB:01          MREQ    WR                 | Memory write to  0FE <- 01\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:E7          MREQ RD                    | Memory read from 005 -> E7\n#053H T8  AB:0FF DB:47          MREQ    WR                 | Memory write to  0FF <- 47\n#056H T11 AB:0FE DB:05          MREQ    WR                 | Memory write to  0FE <- 05\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:E8          MREQ RD                    | Memory read from 005 -> E8\n#053H T8  AB:0FF DB:48          MREQ    WR                 | Memory write to  0FF <- 48\n#056H T11 AB:0FE DB:0D          MREQ    WR                 | Memory write to  0FE <- 0D\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:E9          MREQ RD                    | Memory read from 005 -> E9\n#053H T8  AB:0FF DB:49          MREQ    WR                 | Memory write to  0FF <- 49\n#056H T11 AB:0FE DB:09          MREQ    WR                 | Memory write to  0FE <- 09\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:EA          MREQ RD                    | Memory read from 005 -> EA\n#053H T8  AB:0FF DB:50          MREQ    WR                 | Memory write to  0FF <- 50\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:EB          MREQ RD                    | Memory read from 005 -> EB\n#053H T8  AB:0FF DB:51          MREQ    WR                 | Memory write to  0FF <- 51\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:EC          MREQ RD                    | Memory read from 005 -> EC\n#053H T8  AB:0FF DB:52          MREQ    WR                 | Memory write to  0FF <- 52\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:ED          MREQ RD                    | Memory read from 005 -> ED\n#053H T8  AB:0FF DB:53          MREQ    WR                 | Memory write to  0FF <- 53\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:EE          MREQ RD                    | Memory read from 005 -> EE\n#053H T8  AB:0FF DB:54          MREQ    WR                 | Memory write to  0FF <- 54\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:EF          MREQ RD                    | Memory read from 005 -> EF\n#053H T8  AB:0FF DB:55          MREQ    WR                 | Memory write to  0FF <- 55\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:F0          MREQ RD                    | Memory read from 005 -> F0\n#053H T8  AB:0FF DB:50          MREQ    WR                 | Memory write to  0FF <- 50\n#056H T11 AB:0FE DB:05          MREQ    WR                 | Memory write to  0FE <- 05\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:F1          MREQ RD                    | Memory read from 005 -> F1\n#053H T8  AB:0FF DB:51          MREQ    WR                 | Memory write to  0FF <- 51\n#056H T11 AB:0FE DB:01          MREQ    WR                 | Memory write to  0FE <- 01\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:F2          MREQ RD                    | Memory read from 005 -> F2\n#053H T8  AB:0FF DB:52          MREQ    WR                 | Memory write to  0FF <- 52\n#056H T11 AB:0FE DB:01          MREQ    WR                 | Memory write to  0FE <- 01\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:F3          MREQ RD                    | Memory read from 005 -> F3\n#053H T8  AB:0FF DB:53          MREQ    WR                 | Memory write to  0FF <- 53\n#056H T11 AB:0FE DB:05          MREQ    WR                 | Memory write to  0FE <- 05\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:F4          MREQ RD                    | Memory read from 005 -> F4\n#053H T8  AB:0FF DB:54          MREQ    WR                 | Memory write to  0FF <- 54\n#056H T11 AB:0FE DB:01          MREQ    WR                 | Memory write to  0FE <- 01\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:F5          MREQ RD                    | Memory read from 005 -> F5\n#053H T8  AB:0FF DB:55          MREQ    WR                 | Memory write to  0FF <- 55\n#056H T11 AB:0FE DB:05          MREQ    WR                 | Memory write to  0FE <- 05\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:F6          MREQ RD                    | Memory read from 005 -> F6\n#053H T8  AB:0FF DB:56          MREQ    WR                 | Memory write to  0FF <- 56\n#056H T11 AB:0FE DB:05          MREQ    WR                 | Memory write to  0FE <- 05\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:F7          MREQ RD                    | Memory read from 005 -> F7\n#053H T8  AB:0FF DB:57          MREQ    WR                 | Memory write to  0FF <- 57\n#056H T11 AB:0FE DB:01          MREQ    WR                 | Memory write to  0FE <- 01\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:F8          MREQ RD                    | Memory read from 005 -> F8\n#053H T8  AB:0FF DB:58          MREQ    WR                 | Memory write to  0FF <- 58\n#056H T11 AB:0FE DB:09          MREQ    WR                 | Memory write to  0FE <- 09\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:F9          MREQ RD                    | Memory read from 005 -> F9\n#053H T8  AB:0FF DB:59          MREQ    WR                 | Memory write to  0FF <- 59\n#056H T11 AB:0FE DB:0D          MREQ    WR                 | Memory write to  0FE <- 0D\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:FA          MREQ RD                    | Memory read from 005 -> FA\n#053H T8  AB:0FF DB:60          MREQ    WR                 | Memory write to  0FF <- 60\n#056H T11 AB:0FE DB:35          MREQ    WR                 | Memory write to  0FE <- 35\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:FB          MREQ RD                    | Memory read from 005 -> FB\n#053H T8  AB:0FF DB:61          MREQ    WR                 | Memory write to  0FF <- 61\n#056H T11 AB:0FE DB:31          MREQ    WR                 | Memory write to  0FE <- 31\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:FC          MREQ RD                    | Memory read from 005 -> FC\n#053H T8  AB:0FF DB:62          MREQ    WR                 | Memory write to  0FF <- 62\n#056H T11 AB:0FE DB:31          MREQ    WR                 | Memory write to  0FE <- 31\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:FD          MREQ RD                    | Memory read from 005 -> FD\n#053H T8  AB:0FF DB:63          MREQ    WR                 | Memory write to  0FF <- 63\n#056H T11 AB:0FE DB:35          MREQ    WR                 | Memory write to  0FE <- 35\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:FE          MREQ RD                    | Memory read from 005 -> FE\n#053H T8  AB:0FF DB:64          MREQ    WR                 | Memory write to  0FF <- 64\n#056H T11 AB:0FE DB:31          MREQ    WR                 | Memory write to  0FE <- 31\n#017H T7  AB:004 DB:01          MREQ RD                    | Memory read from 004 -> 01\n#020H T10 AB:005 DB:FF          MREQ RD                    | Memory read from 005 -> FF\n#053H T8  AB:0FF DB:65          MREQ    WR                 | Memory write to  0FF <- 65\n#056H T11 AB:0FE DB:35          MREQ    WR                 | Memory write to  0FE <- 35\n"
  },
  {
    "path": "tools/dongle/daa/daa_a-h0.out",
    "content": "#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:00          MREQ RD                    | Memory read from 005 -> 00\n#053H T8  AB:0FF DB:06          MREQ    WR                 | Memory write to  0FF <- 06\n#056H T11 AB:0FE DB:04          MREQ    WR                 | Memory write to  0FE <- 04\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:01          MREQ RD                    | Memory read from 005 -> 01\n#053H T8  AB:0FF DB:07          MREQ    WR                 | Memory write to  0FF <- 07\n#056H T11 AB:0FE DB:00          MREQ    WR                 | Memory write to  0FE <- 00\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:02          MREQ RD                    | Memory read from 005 -> 02\n#053H T8  AB:0FF DB:08          MREQ    WR                 | Memory write to  0FF <- 08\n#056H T11 AB:0FE DB:08          MREQ    WR                 | Memory write to  0FE <- 08\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:03          MREQ RD                    | Memory read from 005 -> 03\n#053H T8  AB:0FF DB:09          MREQ    WR                 | Memory write to  0FF <- 09\n#056H T11 AB:0FE DB:0C          MREQ    WR                 | Memory write to  0FE <- 0C\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:04          MREQ RD                    | Memory read from 005 -> 04\n#053H T8  AB:0FF DB:0A          MREQ    WR                 | Memory write to  0FF <- 0A\n#056H T11 AB:0FE DB:0C          MREQ    WR                 | Memory write to  0FE <- 0C\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:05          MREQ RD                    | Memory read from 005 -> 05\n#053H T8  AB:0FF DB:0B          MREQ    WR                 | Memory write to  0FF <- 0B\n#056H T11 AB:0FE DB:08          MREQ    WR                 | Memory write to  0FE <- 08\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:06          MREQ RD                    | Memory read from 005 -> 06\n#053H T8  AB:0FF DB:0C          MREQ    WR                 | Memory write to  0FF <- 0C\n#056H T11 AB:0FE DB:0C          MREQ    WR                 | Memory write to  0FE <- 0C\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:07          MREQ RD                    | Memory read from 005 -> 07\n#053H T8  AB:0FF DB:0D          MREQ    WR                 | Memory write to  0FF <- 0D\n#056H T11 AB:0FE DB:08          MREQ    WR                 | Memory write to  0FE <- 08\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:08          MREQ RD                    | Memory read from 005 -> 08\n#053H T8  AB:0FF DB:0E          MREQ    WR                 | Memory write to  0FF <- 0E\n#056H T11 AB:0FE DB:08          MREQ    WR                 | Memory write to  0FE <- 08\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:09          MREQ RD                    | Memory read from 005 -> 09\n#053H T8  AB:0FF DB:0F          MREQ    WR                 | Memory write to  0FF <- 0F\n#056H T11 AB:0FE DB:0C          MREQ    WR                 | Memory write to  0FE <- 0C\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:0A          MREQ RD                    | Memory read from 005 -> 0A\n#053H T8  AB:0FF DB:10          MREQ    WR                 | Memory write to  0FF <- 10\n#056H T11 AB:0FE DB:10          MREQ    WR                 | Memory write to  0FE <- 10\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:0B          MREQ RD                    | Memory read from 005 -> 0B\n#053H T8  AB:0FF DB:11          MREQ    WR                 | Memory write to  0FF <- 11\n#056H T11 AB:0FE DB:14          MREQ    WR                 | Memory write to  0FE <- 14\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:0C          MREQ RD                    | Memory read from 005 -> 0C\n#053H T8  AB:0FF DB:12          MREQ    WR                 | Memory write to  0FF <- 12\n#056H T11 AB:0FE DB:14          MREQ    WR                 | Memory write to  0FE <- 14\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:0D          MREQ RD                    | Memory read from 005 -> 0D\n#053H T8  AB:0FF DB:13          MREQ    WR                 | Memory write to  0FF <- 13\n#056H T11 AB:0FE DB:10          MREQ    WR                 | Memory write to  0FE <- 10\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:0E          MREQ RD                    | Memory read from 005 -> 0E\n#053H T8  AB:0FF DB:14          MREQ    WR                 | Memory write to  0FF <- 14\n#056H T11 AB:0FE DB:14          MREQ    WR                 | Memory write to  0FE <- 14\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:0F          MREQ RD                    | Memory read from 005 -> 0F\n#053H T8  AB:0FF DB:15          MREQ    WR                 | Memory write to  0FF <- 15\n#056H T11 AB:0FE DB:10          MREQ    WR                 | Memory write to  0FE <- 10\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:10          MREQ RD                    | Memory read from 005 -> 10\n#053H T8  AB:0FF DB:16          MREQ    WR                 | Memory write to  0FF <- 16\n#056H T11 AB:0FE DB:00          MREQ    WR                 | Memory write to  0FE <- 00\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:11          MREQ RD                    | Memory read from 005 -> 11\n#053H T8  AB:0FF DB:17          MREQ    WR                 | Memory write to  0FF <- 17\n#056H T11 AB:0FE DB:04          MREQ    WR                 | Memory write to  0FE <- 04\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:12          MREQ RD                    | Memory read from 005 -> 12\n#053H T8  AB:0FF DB:18          MREQ    WR                 | Memory write to  0FF <- 18\n#056H T11 AB:0FE DB:0C          MREQ    WR                 | Memory write to  0FE <- 0C\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:13          MREQ RD                    | Memory read from 005 -> 13\n#053H T8  AB:0FF DB:19          MREQ    WR                 | Memory write to  0FF <- 19\n#056H T11 AB:0FE DB:08          MREQ    WR                 | Memory write to  0FE <- 08\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:14          MREQ RD                    | Memory read from 005 -> 14\n#053H T8  AB:0FF DB:1A          MREQ    WR                 | Memory write to  0FF <- 1A\n#056H T11 AB:0FE DB:08          MREQ    WR                 | Memory write to  0FE <- 08\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:15          MREQ RD                    | Memory read from 005 -> 15\n#053H T8  AB:0FF DB:1B          MREQ    WR                 | Memory write to  0FF <- 1B\n#056H T11 AB:0FE DB:0C          MREQ    WR                 | Memory write to  0FE <- 0C\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:16          MREQ RD                    | Memory read from 005 -> 16\n#053H T8  AB:0FF DB:1C          MREQ    WR                 | Memory write to  0FF <- 1C\n#056H T11 AB:0FE DB:08          MREQ    WR                 | Memory write to  0FE <- 08\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:17          MREQ RD                    | Memory read from 005 -> 17\n#053H T8  AB:0FF DB:1D          MREQ    WR                 | Memory write to  0FF <- 1D\n#056H T11 AB:0FE DB:0C          MREQ    WR                 | Memory write to  0FE <- 0C\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:18          MREQ RD                    | Memory read from 005 -> 18\n#053H T8  AB:0FF DB:1E          MREQ    WR                 | Memory write to  0FF <- 1E\n#056H T11 AB:0FE DB:0C          MREQ    WR                 | Memory write to  0FE <- 0C\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:19          MREQ RD                    | Memory read from 005 -> 19\n#053H T8  AB:0FF DB:1F          MREQ    WR                 | Memory write to  0FF <- 1F\n#056H T11 AB:0FE DB:08          MREQ    WR                 | Memory write to  0FE <- 08\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:1A          MREQ RD                    | Memory read from 005 -> 1A\n#053H T8  AB:0FF DB:20          MREQ    WR                 | Memory write to  0FF <- 20\n#056H T11 AB:0FE DB:30          MREQ    WR                 | Memory write to  0FE <- 30\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:1B          MREQ RD                    | Memory read from 005 -> 1B\n#053H T8  AB:0FF DB:21          MREQ    WR                 | Memory write to  0FF <- 21\n#056H T11 AB:0FE DB:34          MREQ    WR                 | Memory write to  0FE <- 34\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:1C          MREQ RD                    | Memory read from 005 -> 1C\n#053H T8  AB:0FF DB:22          MREQ    WR                 | Memory write to  0FF <- 22\n#056H T11 AB:0FE DB:34          MREQ    WR                 | Memory write to  0FE <- 34\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:1D          MREQ RD                    | Memory read from 005 -> 1D\n#053H T8  AB:0FF DB:23          MREQ    WR                 | Memory write to  0FF <- 23\n#056H T11 AB:0FE DB:30          MREQ    WR                 | Memory write to  0FE <- 30\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:1E          MREQ RD                    | Memory read from 005 -> 1E\n#053H T8  AB:0FF DB:24          MREQ    WR                 | Memory write to  0FF <- 24\n#056H T11 AB:0FE DB:34          MREQ    WR                 | Memory write to  0FE <- 34\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:1F          MREQ RD                    | Memory read from 005 -> 1F\n#053H T8  AB:0FF DB:25          MREQ    WR                 | Memory write to  0FF <- 25\n#056H T11 AB:0FE DB:30          MREQ    WR                 | Memory write to  0FE <- 30\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:20          MREQ RD                    | Memory read from 005 -> 20\n#053H T8  AB:0FF DB:26          MREQ    WR                 | Memory write to  0FF <- 26\n#056H T11 AB:0FE DB:20          MREQ    WR                 | Memory write to  0FE <- 20\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:21          MREQ RD                    | Memory read from 005 -> 21\n#053H T8  AB:0FF DB:27          MREQ    WR                 | Memory write to  0FF <- 27\n#056H T11 AB:0FE DB:24          MREQ    WR                 | Memory write to  0FE <- 24\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:22          MREQ RD                    | Memory read from 005 -> 22\n#053H T8  AB:0FF DB:28          MREQ    WR                 | Memory write to  0FF <- 28\n#056H T11 AB:0FE DB:2C          MREQ    WR                 | Memory write to  0FE <- 2C\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:23          MREQ RD                    | Memory read from 005 -> 23\n#053H T8  AB:0FF DB:29          MREQ    WR                 | Memory write to  0FF <- 29\n#056H T11 AB:0FE DB:28          MREQ    WR                 | Memory write to  0FE <- 28\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:24          MREQ RD                    | Memory read from 005 -> 24\n#053H T8  AB:0FF DB:2A          MREQ    WR                 | Memory write to  0FF <- 2A\n#056H T11 AB:0FE DB:28          MREQ    WR                 | Memory write to  0FE <- 28\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:25          MREQ RD                    | Memory read from 005 -> 25\n#053H T8  AB:0FF DB:2B          MREQ    WR                 | Memory write to  0FF <- 2B\n#056H T11 AB:0FE DB:2C          MREQ    WR                 | Memory write to  0FE <- 2C\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:26          MREQ RD                    | Memory read from 005 -> 26\n#053H T8  AB:0FF DB:2C          MREQ    WR                 | Memory write to  0FF <- 2C\n#056H T11 AB:0FE DB:28          MREQ    WR                 | Memory write to  0FE <- 28\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:27          MREQ RD                    | Memory read from 005 -> 27\n#053H T8  AB:0FF DB:2D          MREQ    WR                 | Memory write to  0FF <- 2D\n#056H T11 AB:0FE DB:2C          MREQ    WR                 | Memory write to  0FE <- 2C\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:28          MREQ RD                    | Memory read from 005 -> 28\n#053H T8  AB:0FF DB:2E          MREQ    WR                 | Memory write to  0FF <- 2E\n#056H T11 AB:0FE DB:2C          MREQ    WR                 | Memory write to  0FE <- 2C\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:29          MREQ RD                    | Memory read from 005 -> 29\n#053H T8  AB:0FF DB:2F          MREQ    WR                 | Memory write to  0FF <- 2F\n#056H T11 AB:0FE DB:28          MREQ    WR                 | Memory write to  0FE <- 28\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:2A          MREQ RD                    | Memory read from 005 -> 2A\n#053H T8  AB:0FF DB:30          MREQ    WR                 | Memory write to  0FF <- 30\n#056H T11 AB:0FE DB:34          MREQ    WR                 | Memory write to  0FE <- 34\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:2B          MREQ RD                    | Memory read from 005 -> 2B\n#053H T8  AB:0FF DB:31          MREQ    WR                 | Memory write to  0FF <- 31\n#056H T11 AB:0FE DB:30          MREQ    WR                 | Memory write to  0FE <- 30\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:2C          MREQ RD                    | Memory read from 005 -> 2C\n#053H T8  AB:0FF DB:32          MREQ    WR                 | Memory write to  0FF <- 32\n#056H T11 AB:0FE DB:30          MREQ    WR                 | Memory write to  0FE <- 30\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:2D          MREQ RD                    | Memory read from 005 -> 2D\n#053H T8  AB:0FF DB:33          MREQ    WR                 | Memory write to  0FF <- 33\n#056H T11 AB:0FE DB:34          MREQ    WR                 | Memory write to  0FE <- 34\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:2E          MREQ RD                    | Memory read from 005 -> 2E\n#053H T8  AB:0FF DB:34          MREQ    WR                 | Memory write to  0FF <- 34\n#056H T11 AB:0FE DB:30          MREQ    WR                 | Memory write to  0FE <- 30\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:2F          MREQ RD                    | Memory read from 005 -> 2F\n#053H T8  AB:0FF DB:35          MREQ    WR                 | Memory write to  0FF <- 35\n#056H T11 AB:0FE DB:34          MREQ    WR                 | Memory write to  0FE <- 34\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:30          MREQ RD                    | Memory read from 005 -> 30\n#053H T8  AB:0FF DB:36          MREQ    WR                 | Memory write to  0FF <- 36\n#056H T11 AB:0FE DB:24          MREQ    WR                 | Memory write to  0FE <- 24\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:31          MREQ RD                    | Memory read from 005 -> 31\n#053H T8  AB:0FF DB:37          MREQ    WR                 | Memory write to  0FF <- 37\n#056H T11 AB:0FE DB:20          MREQ    WR                 | Memory write to  0FE <- 20\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:32          MREQ RD                    | Memory read from 005 -> 32\n#053H T8  AB:0FF DB:38          MREQ    WR                 | Memory write to  0FF <- 38\n#056H T11 AB:0FE DB:28          MREQ    WR                 | Memory write to  0FE <- 28\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:33          MREQ RD                    | Memory read from 005 -> 33\n#053H T8  AB:0FF DB:39          MREQ    WR                 | Memory write to  0FF <- 39\n#056H T11 AB:0FE DB:2C          MREQ    WR                 | Memory write to  0FE <- 2C\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:34          MREQ RD                    | Memory read from 005 -> 34\n#053H T8  AB:0FF DB:3A          MREQ    WR                 | Memory write to  0FF <- 3A\n#056H T11 AB:0FE DB:2C          MREQ    WR                 | Memory write to  0FE <- 2C\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:35          MREQ RD                    | Memory read from 005 -> 35\n#053H T8  AB:0FF DB:3B          MREQ    WR                 | Memory write to  0FF <- 3B\n#056H T11 AB:0FE DB:28          MREQ    WR                 | Memory write to  0FE <- 28\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:36          MREQ RD                    | Memory read from 005 -> 36\n#053H T8  AB:0FF DB:3C          MREQ    WR                 | Memory write to  0FF <- 3C\n#056H T11 AB:0FE DB:2C          MREQ    WR                 | Memory write to  0FE <- 2C\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:37          MREQ RD                    | Memory read from 005 -> 37\n#053H T8  AB:0FF DB:3D          MREQ    WR                 | Memory write to  0FF <- 3D\n#056H T11 AB:0FE DB:28          MREQ    WR                 | Memory write to  0FE <- 28\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:38          MREQ RD                    | Memory read from 005 -> 38\n#053H T8  AB:0FF DB:3E          MREQ    WR                 | Memory write to  0FF <- 3E\n#056H T11 AB:0FE DB:28          MREQ    WR                 | Memory write to  0FE <- 28\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:39          MREQ RD                    | Memory read from 005 -> 39\n#053H T8  AB:0FF DB:3F          MREQ    WR                 | Memory write to  0FF <- 3F\n#056H T11 AB:0FE DB:2C          MREQ    WR                 | Memory write to  0FE <- 2C\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:3A          MREQ RD                    | Memory read from 005 -> 3A\n#053H T8  AB:0FF DB:40          MREQ    WR                 | Memory write to  0FF <- 40\n#056H T11 AB:0FE DB:10          MREQ    WR                 | Memory write to  0FE <- 10\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:3B          MREQ RD                    | Memory read from 005 -> 3B\n#053H T8  AB:0FF DB:41          MREQ    WR                 | Memory write to  0FF <- 41\n#056H T11 AB:0FE DB:14          MREQ    WR                 | Memory write to  0FE <- 14\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:3C          MREQ RD                    | Memory read from 005 -> 3C\n#053H T8  AB:0FF DB:42          MREQ    WR                 | Memory write to  0FF <- 42\n#056H T11 AB:0FE DB:14          MREQ    WR                 | Memory write to  0FE <- 14\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:3D          MREQ RD                    | Memory read from 005 -> 3D\n#053H T8  AB:0FF DB:43          MREQ    WR                 | Memory write to  0FF <- 43\n#056H T11 AB:0FE DB:10          MREQ    WR                 | Memory write to  0FE <- 10\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:3E          MREQ RD                    | Memory read from 005 -> 3E\n#053H T8  AB:0FF DB:44          MREQ    WR                 | Memory write to  0FF <- 44\n#056H T11 AB:0FE DB:14          MREQ    WR                 | Memory write to  0FE <- 14\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:3F          MREQ RD                    | Memory read from 005 -> 3F\n#053H T8  AB:0FF DB:45          MREQ    WR                 | Memory write to  0FF <- 45\n#056H T11 AB:0FE DB:10          MREQ    WR                 | Memory write to  0FE <- 10\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:40          MREQ RD                    | Memory read from 005 -> 40\n#053H T8  AB:0FF DB:46          MREQ    WR                 | Memory write to  0FF <- 46\n#056H T11 AB:0FE DB:00          MREQ    WR                 | Memory write to  0FE <- 00\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:41          MREQ RD                    | Memory read from 005 -> 41\n#053H T8  AB:0FF DB:47          MREQ    WR                 | Memory write to  0FF <- 47\n#056H T11 AB:0FE DB:04          MREQ    WR                 | Memory write to  0FE <- 04\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:42          MREQ RD                    | Memory read from 005 -> 42\n#053H T8  AB:0FF DB:48          MREQ    WR                 | Memory write to  0FF <- 48\n#056H T11 AB:0FE DB:0C          MREQ    WR                 | Memory write to  0FE <- 0C\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:43          MREQ RD                    | Memory read from 005 -> 43\n#053H T8  AB:0FF DB:49          MREQ    WR                 | Memory write to  0FF <- 49\n#056H T11 AB:0FE DB:08          MREQ    WR                 | Memory write to  0FE <- 08\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:44          MREQ RD                    | Memory read from 005 -> 44\n#053H T8  AB:0FF DB:4A          MREQ    WR                 | Memory write to  0FF <- 4A\n#056H T11 AB:0FE DB:08          MREQ    WR                 | Memory write to  0FE <- 08\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:45          MREQ RD                    | Memory read from 005 -> 45\n#053H T8  AB:0FF DB:4B          MREQ    WR                 | Memory write to  0FF <- 4B\n#056H T11 AB:0FE DB:0C          MREQ    WR                 | Memory write to  0FE <- 0C\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:46          MREQ RD                    | Memory read from 005 -> 46\n#053H T8  AB:0FF DB:4C          MREQ    WR                 | Memory write to  0FF <- 4C\n#056H T11 AB:0FE DB:08          MREQ    WR                 | Memory write to  0FE <- 08\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:47          MREQ RD                    | Memory read from 005 -> 47\n#053H T8  AB:0FF DB:4D          MREQ    WR                 | Memory write to  0FF <- 4D\n#056H T11 AB:0FE DB:0C          MREQ    WR                 | Memory write to  0FE <- 0C\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:48          MREQ RD                    | Memory read from 005 -> 48\n#053H T8  AB:0FF DB:4E          MREQ    WR                 | Memory write to  0FF <- 4E\n#056H T11 AB:0FE DB:0C          MREQ    WR                 | Memory write to  0FE <- 0C\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:49          MREQ RD                    | Memory read from 005 -> 49\n#053H T8  AB:0FF DB:4F          MREQ    WR                 | Memory write to  0FF <- 4F\n#056H T11 AB:0FE DB:08          MREQ    WR                 | Memory write to  0FE <- 08\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:4A          MREQ RD                    | Memory read from 005 -> 4A\n#053H T8  AB:0FF DB:50          MREQ    WR                 | Memory write to  0FF <- 50\n#056H T11 AB:0FE DB:14          MREQ    WR                 | Memory write to  0FE <- 14\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:4B          MREQ RD                    | Memory read from 005 -> 4B\n#053H T8  AB:0FF DB:51          MREQ    WR                 | Memory write to  0FF <- 51\n#056H T11 AB:0FE DB:10          MREQ    WR                 | Memory write to  0FE <- 10\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:4C          MREQ RD                    | Memory read from 005 -> 4C\n#053H T8  AB:0FF DB:52          MREQ    WR                 | Memory write to  0FF <- 52\n#056H T11 AB:0FE DB:10          MREQ    WR                 | Memory write to  0FE <- 10\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:4D          MREQ RD                    | Memory read from 005 -> 4D\n#053H T8  AB:0FF DB:53          MREQ    WR                 | Memory write to  0FF <- 53\n#056H T11 AB:0FE DB:14          MREQ    WR                 | Memory write to  0FE <- 14\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:4E          MREQ RD                    | Memory read from 005 -> 4E\n#053H T8  AB:0FF DB:54          MREQ    WR                 | Memory write to  0FF <- 54\n#056H T11 AB:0FE DB:10          MREQ    WR                 | Memory write to  0FE <- 10\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:4F          MREQ RD                    | Memory read from 005 -> 4F\n#053H T8  AB:0FF DB:55          MREQ    WR                 | Memory write to  0FF <- 55\n#056H T11 AB:0FE DB:14          MREQ    WR                 | Memory write to  0FE <- 14\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:50          MREQ RD                    | Memory read from 005 -> 50\n#053H T8  AB:0FF DB:56          MREQ    WR                 | Memory write to  0FF <- 56\n#056H T11 AB:0FE DB:04          MREQ    WR                 | Memory write to  0FE <- 04\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:51          MREQ RD                    | Memory read from 005 -> 51\n#053H T8  AB:0FF DB:57          MREQ    WR                 | Memory write to  0FF <- 57\n#056H T11 AB:0FE DB:00          MREQ    WR                 | Memory write to  0FE <- 00\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:52          MREQ RD                    | Memory read from 005 -> 52\n#053H T8  AB:0FF DB:58          MREQ    WR                 | Memory write to  0FF <- 58\n#056H T11 AB:0FE DB:08          MREQ    WR                 | Memory write to  0FE <- 08\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:53          MREQ RD                    | Memory read from 005 -> 53\n#053H T8  AB:0FF DB:59          MREQ    WR                 | Memory write to  0FF <- 59\n#056H T11 AB:0FE DB:0C          MREQ    WR                 | Memory write to  0FE <- 0C\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:54          MREQ RD                    | Memory read from 005 -> 54\n#053H T8  AB:0FF DB:5A          MREQ    WR                 | Memory write to  0FF <- 5A\n#056H T11 AB:0FE DB:0C          MREQ    WR                 | Memory write to  0FE <- 0C\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:55          MREQ RD                    | Memory read from 005 -> 55\n#053H T8  AB:0FF DB:5B          MREQ    WR                 | Memory write to  0FF <- 5B\n#056H T11 AB:0FE DB:08          MREQ    WR                 | Memory write to  0FE <- 08\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:56          MREQ RD                    | Memory read from 005 -> 56\n#053H T8  AB:0FF DB:5C          MREQ    WR                 | Memory write to  0FF <- 5C\n#056H T11 AB:0FE DB:0C          MREQ    WR                 | Memory write to  0FE <- 0C\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:57          MREQ RD                    | Memory read from 005 -> 57\n#053H T8  AB:0FF DB:5D          MREQ    WR                 | Memory write to  0FF <- 5D\n#056H T11 AB:0FE DB:08          MREQ    WR                 | Memory write to  0FE <- 08\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:58          MREQ RD                    | Memory read from 005 -> 58\n#053H T8  AB:0FF DB:5E          MREQ    WR                 | Memory write to  0FF <- 5E\n#056H T11 AB:0FE DB:08          MREQ    WR                 | Memory write to  0FE <- 08\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:59          MREQ RD                    | Memory read from 005 -> 59\n#053H T8  AB:0FF DB:5F          MREQ    WR                 | Memory write to  0FF <- 5F\n#056H T11 AB:0FE DB:0C          MREQ    WR                 | Memory write to  0FE <- 0C\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:5A          MREQ RD                    | Memory read from 005 -> 5A\n#053H T8  AB:0FF DB:60          MREQ    WR                 | Memory write to  0FF <- 60\n#056H T11 AB:0FE DB:34          MREQ    WR                 | Memory write to  0FE <- 34\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:5B          MREQ RD                    | Memory read from 005 -> 5B\n#053H T8  AB:0FF DB:61          MREQ    WR                 | Memory write to  0FF <- 61\n#056H T11 AB:0FE DB:30          MREQ    WR                 | Memory write to  0FE <- 30\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:5C          MREQ RD                    | Memory read from 005 -> 5C\n#053H T8  AB:0FF DB:62          MREQ    WR                 | Memory write to  0FF <- 62\n#056H T11 AB:0FE DB:30          MREQ    WR                 | Memory write to  0FE <- 30\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:5D          MREQ RD                    | Memory read from 005 -> 5D\n#053H T8  AB:0FF DB:63          MREQ    WR                 | Memory write to  0FF <- 63\n#056H T11 AB:0FE DB:34          MREQ    WR                 | Memory write to  0FE <- 34\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:5E          MREQ RD                    | Memory read from 005 -> 5E\n#053H T8  AB:0FF DB:64          MREQ    WR                 | Memory write to  0FF <- 64\n#056H T11 AB:0FE DB:30          MREQ    WR                 | Memory write to  0FE <- 30\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:5F          MREQ RD                    | Memory read from 005 -> 5F\n#053H T8  AB:0FF DB:65          MREQ    WR                 | Memory write to  0FF <- 65\n#056H T11 AB:0FE DB:34          MREQ    WR                 | Memory write to  0FE <- 34\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:60          MREQ RD                    | Memory read from 005 -> 60\n#053H T8  AB:0FF DB:66          MREQ    WR                 | Memory write to  0FF <- 66\n#056H T11 AB:0FE DB:24          MREQ    WR                 | Memory write to  0FE <- 24\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:61          MREQ RD                    | Memory read from 005 -> 61\n#053H T8  AB:0FF DB:67          MREQ    WR                 | Memory write to  0FF <- 67\n#056H T11 AB:0FE DB:20          MREQ    WR                 | Memory write to  0FE <- 20\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:62          MREQ RD                    | Memory read from 005 -> 62\n#053H T8  AB:0FF DB:68          MREQ    WR                 | Memory write to  0FF <- 68\n#056H T11 AB:0FE DB:28          MREQ    WR                 | Memory write to  0FE <- 28\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:63          MREQ RD                    | Memory read from 005 -> 63\n#053H T8  AB:0FF DB:69          MREQ    WR                 | Memory write to  0FF <- 69\n#056H T11 AB:0FE DB:2C          MREQ    WR                 | Memory write to  0FE <- 2C\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:64          MREQ RD                    | Memory read from 005 -> 64\n#053H T8  AB:0FF DB:6A          MREQ    WR                 | Memory write to  0FF <- 6A\n#056H T11 AB:0FE DB:2C          MREQ    WR                 | Memory write to  0FE <- 2C\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:65          MREQ RD                    | Memory read from 005 -> 65\n#053H T8  AB:0FF DB:6B          MREQ    WR                 | Memory write to  0FF <- 6B\n#056H T11 AB:0FE DB:28          MREQ    WR                 | Memory write to  0FE <- 28\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:66          MREQ RD                    | Memory read from 005 -> 66\n#053H T8  AB:0FF DB:6C          MREQ    WR                 | Memory write to  0FF <- 6C\n#056H T11 AB:0FE DB:2C          MREQ    WR                 | Memory write to  0FE <- 2C\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:67          MREQ RD                    | Memory read from 005 -> 67\n#053H T8  AB:0FF DB:6D          MREQ    WR                 | Memory write to  0FF <- 6D\n#056H T11 AB:0FE DB:28          MREQ    WR                 | Memory write to  0FE <- 28\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:68          MREQ RD                    | Memory read from 005 -> 68\n#053H T8  AB:0FF DB:6E          MREQ    WR                 | Memory write to  0FF <- 6E\n#056H T11 AB:0FE DB:28          MREQ    WR                 | Memory write to  0FE <- 28\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:69          MREQ RD                    | Memory read from 005 -> 69\n#053H T8  AB:0FF DB:6F          MREQ    WR                 | Memory write to  0FF <- 6F\n#056H T11 AB:0FE DB:2C          MREQ    WR                 | Memory write to  0FE <- 2C\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:6A          MREQ RD                    | Memory read from 005 -> 6A\n#053H T8  AB:0FF DB:70          MREQ    WR                 | Memory write to  0FF <- 70\n#056H T11 AB:0FE DB:30          MREQ    WR                 | Memory write to  0FE <- 30\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:6B          MREQ RD                    | Memory read from 005 -> 6B\n#053H T8  AB:0FF DB:71          MREQ    WR                 | Memory write to  0FF <- 71\n#056H T11 AB:0FE DB:34          MREQ    WR                 | Memory write to  0FE <- 34\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:6C          MREQ RD                    | Memory read from 005 -> 6C\n#053H T8  AB:0FF DB:72          MREQ    WR                 | Memory write to  0FF <- 72\n#056H T11 AB:0FE DB:34          MREQ    WR                 | Memory write to  0FE <- 34\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:6D          MREQ RD                    | Memory read from 005 -> 6D\n#053H T8  AB:0FF DB:73          MREQ    WR                 | Memory write to  0FF <- 73\n#056H T11 AB:0FE DB:30          MREQ    WR                 | Memory write to  0FE <- 30\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:6E          MREQ RD                    | Memory read from 005 -> 6E\n#053H T8  AB:0FF DB:74          MREQ    WR                 | Memory write to  0FF <- 74\n#056H T11 AB:0FE DB:34          MREQ    WR                 | Memory write to  0FE <- 34\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:6F          MREQ RD                    | Memory read from 005 -> 6F\n#053H T8  AB:0FF DB:75          MREQ    WR                 | Memory write to  0FF <- 75\n#056H T11 AB:0FE DB:30          MREQ    WR                 | Memory write to  0FE <- 30\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:70          MREQ RD                    | Memory read from 005 -> 70\n#053H T8  AB:0FF DB:76          MREQ    WR                 | Memory write to  0FF <- 76\n#056H T11 AB:0FE DB:20          MREQ    WR                 | Memory write to  0FE <- 20\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:71          MREQ RD                    | Memory read from 005 -> 71\n#053H T8  AB:0FF DB:77          MREQ    WR                 | Memory write to  0FF <- 77\n#056H T11 AB:0FE DB:24          MREQ    WR                 | Memory write to  0FE <- 24\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:72          MREQ RD                    | Memory read from 005 -> 72\n#053H T8  AB:0FF DB:78          MREQ    WR                 | Memory write to  0FF <- 78\n#056H T11 AB:0FE DB:2C          MREQ    WR                 | Memory write to  0FE <- 2C\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:73          MREQ RD                    | Memory read from 005 -> 73\n#053H T8  AB:0FF DB:79          MREQ    WR                 | Memory write to  0FF <- 79\n#056H T11 AB:0FE DB:28          MREQ    WR                 | Memory write to  0FE <- 28\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:74          MREQ RD                    | Memory read from 005 -> 74\n#053H T8  AB:0FF DB:7A          MREQ    WR                 | Memory write to  0FF <- 7A\n#056H T11 AB:0FE DB:28          MREQ    WR                 | Memory write to  0FE <- 28\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:75          MREQ RD                    | Memory read from 005 -> 75\n#053H T8  AB:0FF DB:7B          MREQ    WR                 | Memory write to  0FF <- 7B\n#056H T11 AB:0FE DB:2C          MREQ    WR                 | Memory write to  0FE <- 2C\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:76          MREQ RD                    | Memory read from 005 -> 76\n#053H T8  AB:0FF DB:7C          MREQ    WR                 | Memory write to  0FF <- 7C\n#056H T11 AB:0FE DB:28          MREQ    WR                 | Memory write to  0FE <- 28\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:77          MREQ RD                    | Memory read from 005 -> 77\n#053H T8  AB:0FF DB:7D          MREQ    WR                 | Memory write to  0FF <- 7D\n#056H T11 AB:0FE DB:2C          MREQ    WR                 | Memory write to  0FE <- 2C\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:78          MREQ RD                    | Memory read from 005 -> 78\n#053H T8  AB:0FF DB:7E          MREQ    WR                 | Memory write to  0FF <- 7E\n#056H T11 AB:0FE DB:2C          MREQ    WR                 | Memory write to  0FE <- 2C\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:79          MREQ RD                    | Memory read from 005 -> 79\n#053H T8  AB:0FF DB:7F          MREQ    WR                 | Memory write to  0FF <- 7F\n#056H T11 AB:0FE DB:28          MREQ    WR                 | Memory write to  0FE <- 28\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:7A          MREQ RD                    | Memory read from 005 -> 7A\n#053H T8  AB:0FF DB:80          MREQ    WR                 | Memory write to  0FF <- 80\n#056H T11 AB:0FE DB:90          MREQ    WR                 | Memory write to  0FE <- 90\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:7B          MREQ RD                    | Memory read from 005 -> 7B\n#053H T8  AB:0FF DB:81          MREQ    WR                 | Memory write to  0FF <- 81\n#056H T11 AB:0FE DB:94          MREQ    WR                 | Memory write to  0FE <- 94\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:7C          MREQ RD                    | Memory read from 005 -> 7C\n#053H T8  AB:0FF DB:82          MREQ    WR                 | Memory write to  0FF <- 82\n#056H T11 AB:0FE DB:94          MREQ    WR                 | Memory write to  0FE <- 94\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:7D          MREQ RD                    | Memory read from 005 -> 7D\n#053H T8  AB:0FF DB:83          MREQ    WR                 | Memory write to  0FF <- 83\n#056H T11 AB:0FE DB:90          MREQ    WR                 | Memory write to  0FE <- 90\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:7E          MREQ RD                    | Memory read from 005 -> 7E\n#053H T8  AB:0FF DB:84          MREQ    WR                 | Memory write to  0FF <- 84\n#056H T11 AB:0FE DB:94          MREQ    WR                 | Memory write to  0FE <- 94\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:7F          MREQ RD                    | Memory read from 005 -> 7F\n#053H T8  AB:0FF DB:85          MREQ    WR                 | Memory write to  0FF <- 85\n#056H T11 AB:0FE DB:90          MREQ    WR                 | Memory write to  0FE <- 90\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:80          MREQ RD                    | Memory read from 005 -> 80\n#053H T8  AB:0FF DB:86          MREQ    WR                 | Memory write to  0FF <- 86\n#056H T11 AB:0FE DB:80          MREQ    WR                 | Memory write to  0FE <- 80\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:81          MREQ RD                    | Memory read from 005 -> 81\n#053H T8  AB:0FF DB:87          MREQ    WR                 | Memory write to  0FF <- 87\n#056H T11 AB:0FE DB:84          MREQ    WR                 | Memory write to  0FE <- 84\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:82          MREQ RD                    | Memory read from 005 -> 82\n#053H T8  AB:0FF DB:88          MREQ    WR                 | Memory write to  0FF <- 88\n#056H T11 AB:0FE DB:8C          MREQ    WR                 | Memory write to  0FE <- 8C\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:83          MREQ RD                    | Memory read from 005 -> 83\n#053H T8  AB:0FF DB:89          MREQ    WR                 | Memory write to  0FF <- 89\n#056H T11 AB:0FE DB:88          MREQ    WR                 | Memory write to  0FE <- 88\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:84          MREQ RD                    | Memory read from 005 -> 84\n#053H T8  AB:0FF DB:8A          MREQ    WR                 | Memory write to  0FF <- 8A\n#056H T11 AB:0FE DB:88          MREQ    WR                 | Memory write to  0FE <- 88\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:85          MREQ RD                    | Memory read from 005 -> 85\n#053H T8  AB:0FF DB:8B          MREQ    WR                 | Memory write to  0FF <- 8B\n#056H T11 AB:0FE DB:8C          MREQ    WR                 | Memory write to  0FE <- 8C\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:86          MREQ RD                    | Memory read from 005 -> 86\n#053H T8  AB:0FF DB:8C          MREQ    WR                 | Memory write to  0FF <- 8C\n#056H T11 AB:0FE DB:88          MREQ    WR                 | Memory write to  0FE <- 88\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:87          MREQ RD                    | Memory read from 005 -> 87\n#053H T8  AB:0FF DB:8D          MREQ    WR                 | Memory write to  0FF <- 8D\n#056H T11 AB:0FE DB:8C          MREQ    WR                 | Memory write to  0FE <- 8C\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:88          MREQ RD                    | Memory read from 005 -> 88\n#053H T8  AB:0FF DB:8E          MREQ    WR                 | Memory write to  0FF <- 8E\n#056H T11 AB:0FE DB:8C          MREQ    WR                 | Memory write to  0FE <- 8C\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:89          MREQ RD                    | Memory read from 005 -> 89\n#053H T8  AB:0FF DB:8F          MREQ    WR                 | Memory write to  0FF <- 8F\n#056H T11 AB:0FE DB:88          MREQ    WR                 | Memory write to  0FE <- 88\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:8A          MREQ RD                    | Memory read from 005 -> 8A\n#053H T8  AB:0FF DB:90          MREQ    WR                 | Memory write to  0FF <- 90\n#056H T11 AB:0FE DB:94          MREQ    WR                 | Memory write to  0FE <- 94\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:8B          MREQ RD                    | Memory read from 005 -> 8B\n#053H T8  AB:0FF DB:91          MREQ    WR                 | Memory write to  0FF <- 91\n#056H T11 AB:0FE DB:90          MREQ    WR                 | Memory write to  0FE <- 90\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:8C          MREQ RD                    | Memory read from 005 -> 8C\n#053H T8  AB:0FF DB:92          MREQ    WR                 | Memory write to  0FF <- 92\n#056H T11 AB:0FE DB:90          MREQ    WR                 | Memory write to  0FE <- 90\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:8D          MREQ RD                    | Memory read from 005 -> 8D\n#053H T8  AB:0FF DB:93          MREQ    WR                 | Memory write to  0FF <- 93\n#056H T11 AB:0FE DB:94          MREQ    WR                 | Memory write to  0FE <- 94\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:8E          MREQ RD                    | Memory read from 005 -> 8E\n#053H T8  AB:0FF DB:94          MREQ    WR                 | Memory write to  0FF <- 94\n#056H T11 AB:0FE DB:90          MREQ    WR                 | Memory write to  0FE <- 90\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:8F          MREQ RD                    | Memory read from 005 -> 8F\n#053H T8  AB:0FF DB:95          MREQ    WR                 | Memory write to  0FF <- 95\n#056H T11 AB:0FE DB:94          MREQ    WR                 | Memory write to  0FE <- 94\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:90          MREQ RD                    | Memory read from 005 -> 90\n#053H T8  AB:0FF DB:96          MREQ    WR                 | Memory write to  0FF <- 96\n#056H T11 AB:0FE DB:84          MREQ    WR                 | Memory write to  0FE <- 84\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:91          MREQ RD                    | Memory read from 005 -> 91\n#053H T8  AB:0FF DB:97          MREQ    WR                 | Memory write to  0FF <- 97\n#056H T11 AB:0FE DB:80          MREQ    WR                 | Memory write to  0FE <- 80\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:92          MREQ RD                    | Memory read from 005 -> 92\n#053H T8  AB:0FF DB:98          MREQ    WR                 | Memory write to  0FF <- 98\n#056H T11 AB:0FE DB:88          MREQ    WR                 | Memory write to  0FE <- 88\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:93          MREQ RD                    | Memory read from 005 -> 93\n#053H T8  AB:0FF DB:99          MREQ    WR                 | Memory write to  0FF <- 99\n#056H T11 AB:0FE DB:8C          MREQ    WR                 | Memory write to  0FE <- 8C\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:94          MREQ RD                    | Memory read from 005 -> 94\n#053H T8  AB:0FF DB:9A          MREQ    WR                 | Memory write to  0FF <- 9A\n#056H T11 AB:0FE DB:8C          MREQ    WR                 | Memory write to  0FE <- 8C\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:95          MREQ RD                    | Memory read from 005 -> 95\n#053H T8  AB:0FF DB:9B          MREQ    WR                 | Memory write to  0FF <- 9B\n#056H T11 AB:0FE DB:88          MREQ    WR                 | Memory write to  0FE <- 88\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:96          MREQ RD                    | Memory read from 005 -> 96\n#053H T8  AB:0FF DB:9C          MREQ    WR                 | Memory write to  0FF <- 9C\n#056H T11 AB:0FE DB:8C          MREQ    WR                 | Memory write to  0FE <- 8C\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:97          MREQ RD                    | Memory read from 005 -> 97\n#053H T8  AB:0FF DB:9D          MREQ    WR                 | Memory write to  0FF <- 9D\n#056H T11 AB:0FE DB:88          MREQ    WR                 | Memory write to  0FE <- 88\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:98          MREQ RD                    | Memory read from 005 -> 98\n#053H T8  AB:0FF DB:9E          MREQ    WR                 | Memory write to  0FF <- 9E\n#056H T11 AB:0FE DB:88          MREQ    WR                 | Memory write to  0FE <- 88\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:99          MREQ RD                    | Memory read from 005 -> 99\n#053H T8  AB:0FF DB:9F          MREQ    WR                 | Memory write to  0FF <- 9F\n#056H T11 AB:0FE DB:8C          MREQ    WR                 | Memory write to  0FE <- 8C\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:9A          MREQ RD                    | Memory read from 005 -> 9A\n#053H T8  AB:0FF DB:00          MREQ    WR                 | Memory write to  0FF <- 00\n#056H T11 AB:0FE DB:55          MREQ    WR                 | Memory write to  0FE <- 55\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:9B          MREQ RD                    | Memory read from 005 -> 9B\n#053H T8  AB:0FF DB:01          MREQ    WR                 | Memory write to  0FF <- 01\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:9C          MREQ RD                    | Memory read from 005 -> 9C\n#053H T8  AB:0FF DB:02          MREQ    WR                 | Memory write to  0FF <- 02\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:9D          MREQ RD                    | Memory read from 005 -> 9D\n#053H T8  AB:0FF DB:03          MREQ    WR                 | Memory write to  0FF <- 03\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:9E          MREQ RD                    | Memory read from 005 -> 9E\n#053H T8  AB:0FF DB:04          MREQ    WR                 | Memory write to  0FF <- 04\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:9F          MREQ RD                    | Memory read from 005 -> 9F\n#053H T8  AB:0FF DB:05          MREQ    WR                 | Memory write to  0FF <- 05\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:A0          MREQ RD                    | Memory read from 005 -> A0\n#053H T8  AB:0FF DB:06          MREQ    WR                 | Memory write to  0FF <- 06\n#056H T11 AB:0FE DB:05          MREQ    WR                 | Memory write to  0FE <- 05\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:A1          MREQ RD                    | Memory read from 005 -> A1\n#053H T8  AB:0FF DB:07          MREQ    WR                 | Memory write to  0FF <- 07\n#056H T11 AB:0FE DB:01          MREQ    WR                 | Memory write to  0FE <- 01\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:A2          MREQ RD                    | Memory read from 005 -> A2\n#053H T8  AB:0FF DB:08          MREQ    WR                 | Memory write to  0FF <- 08\n#056H T11 AB:0FE DB:09          MREQ    WR                 | Memory write to  0FE <- 09\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:A3          MREQ RD                    | Memory read from 005 -> A3\n#053H T8  AB:0FF DB:09          MREQ    WR                 | Memory write to  0FF <- 09\n#056H T11 AB:0FE DB:0D          MREQ    WR                 | Memory write to  0FE <- 0D\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:A4          MREQ RD                    | Memory read from 005 -> A4\n#053H T8  AB:0FF DB:0A          MREQ    WR                 | Memory write to  0FF <- 0A\n#056H T11 AB:0FE DB:0D          MREQ    WR                 | Memory write to  0FE <- 0D\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:A5          MREQ RD                    | Memory read from 005 -> A5\n#053H T8  AB:0FF DB:0B          MREQ    WR                 | Memory write to  0FF <- 0B\n#056H T11 AB:0FE DB:09          MREQ    WR                 | Memory write to  0FE <- 09\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:A6          MREQ RD                    | Memory read from 005 -> A6\n#053H T8  AB:0FF DB:0C          MREQ    WR                 | Memory write to  0FF <- 0C\n#056H T11 AB:0FE DB:0D          MREQ    WR                 | Memory write to  0FE <- 0D\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:A7          MREQ RD                    | Memory read from 005 -> A7\n#053H T8  AB:0FF DB:0D          MREQ    WR                 | Memory write to  0FF <- 0D\n#056H T11 AB:0FE DB:09          MREQ    WR                 | Memory write to  0FE <- 09\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:A8          MREQ RD                    | Memory read from 005 -> A8\n#053H T8  AB:0FF DB:0E          MREQ    WR                 | Memory write to  0FF <- 0E\n#056H T11 AB:0FE DB:09          MREQ    WR                 | Memory write to  0FE <- 09\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:A9          MREQ RD                    | Memory read from 005 -> A9\n#053H T8  AB:0FF DB:0F          MREQ    WR                 | Memory write to  0FF <- 0F\n#056H T11 AB:0FE DB:0D          MREQ    WR                 | Memory write to  0FE <- 0D\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:AA          MREQ RD                    | Memory read from 005 -> AA\n#053H T8  AB:0FF DB:10          MREQ    WR                 | Memory write to  0FF <- 10\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:AB          MREQ RD                    | Memory read from 005 -> AB\n#053H T8  AB:0FF DB:11          MREQ    WR                 | Memory write to  0FF <- 11\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:AC          MREQ RD                    | Memory read from 005 -> AC\n#053H T8  AB:0FF DB:12          MREQ    WR                 | Memory write to  0FF <- 12\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:AD          MREQ RD                    | Memory read from 005 -> AD\n#053H T8  AB:0FF DB:13          MREQ    WR                 | Memory write to  0FF <- 13\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:AE          MREQ RD                    | Memory read from 005 -> AE\n#053H T8  AB:0FF DB:14          MREQ    WR                 | Memory write to  0FF <- 14\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:AF          MREQ RD                    | Memory read from 005 -> AF\n#053H T8  AB:0FF DB:15          MREQ    WR                 | Memory write to  0FF <- 15\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:B0          MREQ RD                    | Memory read from 005 -> B0\n#053H T8  AB:0FF DB:16          MREQ    WR                 | Memory write to  0FF <- 16\n#056H T11 AB:0FE DB:01          MREQ    WR                 | Memory write to  0FE <- 01\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:B1          MREQ RD                    | Memory read from 005 -> B1\n#053H T8  AB:0FF DB:17          MREQ    WR                 | Memory write to  0FF <- 17\n#056H T11 AB:0FE DB:05          MREQ    WR                 | Memory write to  0FE <- 05\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:B2          MREQ RD                    | Memory read from 005 -> B2\n#053H T8  AB:0FF DB:18          MREQ    WR                 | Memory write to  0FF <- 18\n#056H T11 AB:0FE DB:0D          MREQ    WR                 | Memory write to  0FE <- 0D\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:B3          MREQ RD                    | Memory read from 005 -> B3\n#053H T8  AB:0FF DB:19          MREQ    WR                 | Memory write to  0FF <- 19\n#056H T11 AB:0FE DB:09          MREQ    WR                 | Memory write to  0FE <- 09\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:B4          MREQ RD                    | Memory read from 005 -> B4\n#053H T8  AB:0FF DB:1A          MREQ    WR                 | Memory write to  0FF <- 1A\n#056H T11 AB:0FE DB:09          MREQ    WR                 | Memory write to  0FE <- 09\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:B5          MREQ RD                    | Memory read from 005 -> B5\n#053H T8  AB:0FF DB:1B          MREQ    WR                 | Memory write to  0FF <- 1B\n#056H T11 AB:0FE DB:0D          MREQ    WR                 | Memory write to  0FE <- 0D\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:B6          MREQ RD                    | Memory read from 005 -> B6\n#053H T8  AB:0FF DB:1C          MREQ    WR                 | Memory write to  0FF <- 1C\n#056H T11 AB:0FE DB:09          MREQ    WR                 | Memory write to  0FE <- 09\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:B7          MREQ RD                    | Memory read from 005 -> B7\n#053H T8  AB:0FF DB:1D          MREQ    WR                 | Memory write to  0FF <- 1D\n#056H T11 AB:0FE DB:0D          MREQ    WR                 | Memory write to  0FE <- 0D\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:B8          MREQ RD                    | Memory read from 005 -> B8\n#053H T8  AB:0FF DB:1E          MREQ    WR                 | Memory write to  0FF <- 1E\n#056H T11 AB:0FE DB:0D          MREQ    WR                 | Memory write to  0FE <- 0D\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:B9          MREQ RD                    | Memory read from 005 -> B9\n#053H T8  AB:0FF DB:1F          MREQ    WR                 | Memory write to  0FF <- 1F\n#056H T11 AB:0FE DB:09          MREQ    WR                 | Memory write to  0FE <- 09\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:BA          MREQ RD                    | Memory read from 005 -> BA\n#053H T8  AB:0FF DB:20          MREQ    WR                 | Memory write to  0FF <- 20\n#056H T11 AB:0FE DB:31          MREQ    WR                 | Memory write to  0FE <- 31\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:BB          MREQ RD                    | Memory read from 005 -> BB\n#053H T8  AB:0FF DB:21          MREQ    WR                 | Memory write to  0FF <- 21\n#056H T11 AB:0FE DB:35          MREQ    WR                 | Memory write to  0FE <- 35\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:BC          MREQ RD                    | Memory read from 005 -> BC\n#053H T8  AB:0FF DB:22          MREQ    WR                 | Memory write to  0FF <- 22\n#056H T11 AB:0FE DB:35          MREQ    WR                 | Memory write to  0FE <- 35\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:BD          MREQ RD                    | Memory read from 005 -> BD\n#053H T8  AB:0FF DB:23          MREQ    WR                 | Memory write to  0FF <- 23\n#056H T11 AB:0FE DB:31          MREQ    WR                 | Memory write to  0FE <- 31\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:BE          MREQ RD                    | Memory read from 005 -> BE\n#053H T8  AB:0FF DB:24          MREQ    WR                 | Memory write to  0FF <- 24\n#056H T11 AB:0FE DB:35          MREQ    WR                 | Memory write to  0FE <- 35\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:BF          MREQ RD                    | Memory read from 005 -> BF\n#053H T8  AB:0FF DB:25          MREQ    WR                 | Memory write to  0FF <- 25\n#056H T11 AB:0FE DB:31          MREQ    WR                 | Memory write to  0FE <- 31\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:C0          MREQ RD                    | Memory read from 005 -> C0\n#053H T8  AB:0FF DB:26          MREQ    WR                 | Memory write to  0FF <- 26\n#056H T11 AB:0FE DB:21          MREQ    WR                 | Memory write to  0FE <- 21\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:C1          MREQ RD                    | Memory read from 005 -> C1\n#053H T8  AB:0FF DB:27          MREQ    WR                 | Memory write to  0FF <- 27\n#056H T11 AB:0FE DB:25          MREQ    WR                 | Memory write to  0FE <- 25\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:C2          MREQ RD                    | Memory read from 005 -> C2\n#053H T8  AB:0FF DB:28          MREQ    WR                 | Memory write to  0FF <- 28\n#056H T11 AB:0FE DB:2D          MREQ    WR                 | Memory write to  0FE <- 2D\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:C3          MREQ RD                    | Memory read from 005 -> C3\n#053H T8  AB:0FF DB:29          MREQ    WR                 | Memory write to  0FF <- 29\n#056H T11 AB:0FE DB:29          MREQ    WR                 | Memory write to  0FE <- 29\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:C4          MREQ RD                    | Memory read from 005 -> C4\n#053H T8  AB:0FF DB:2A          MREQ    WR                 | Memory write to  0FF <- 2A\n#056H T11 AB:0FE DB:29          MREQ    WR                 | Memory write to  0FE <- 29\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:C5          MREQ RD                    | Memory read from 005 -> C5\n#053H T8  AB:0FF DB:2B          MREQ    WR                 | Memory write to  0FF <- 2B\n#056H T11 AB:0FE DB:2D          MREQ    WR                 | Memory write to  0FE <- 2D\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:C6          MREQ RD                    | Memory read from 005 -> C6\n#053H T8  AB:0FF DB:2C          MREQ    WR                 | Memory write to  0FF <- 2C\n#056H T11 AB:0FE DB:29          MREQ    WR                 | Memory write to  0FE <- 29\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:C7          MREQ RD                    | Memory read from 005 -> C7\n#053H T8  AB:0FF DB:2D          MREQ    WR                 | Memory write to  0FF <- 2D\n#056H T11 AB:0FE DB:2D          MREQ    WR                 | Memory write to  0FE <- 2D\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:C8          MREQ RD                    | Memory read from 005 -> C8\n#053H T8  AB:0FF DB:2E          MREQ    WR                 | Memory write to  0FF <- 2E\n#056H T11 AB:0FE DB:2D          MREQ    WR                 | Memory write to  0FE <- 2D\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:C9          MREQ RD                    | Memory read from 005 -> C9\n#053H T8  AB:0FF DB:2F          MREQ    WR                 | Memory write to  0FF <- 2F\n#056H T11 AB:0FE DB:29          MREQ    WR                 | Memory write to  0FE <- 29\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:CA          MREQ RD                    | Memory read from 005 -> CA\n#053H T8  AB:0FF DB:30          MREQ    WR                 | Memory write to  0FF <- 30\n#056H T11 AB:0FE DB:35          MREQ    WR                 | Memory write to  0FE <- 35\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:CB          MREQ RD                    | Memory read from 005 -> CB\n#053H T8  AB:0FF DB:31          MREQ    WR                 | Memory write to  0FF <- 31\n#056H T11 AB:0FE DB:31          MREQ    WR                 | Memory write to  0FE <- 31\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:CC          MREQ RD                    | Memory read from 005 -> CC\n#053H T8  AB:0FF DB:32          MREQ    WR                 | Memory write to  0FF <- 32\n#056H T11 AB:0FE DB:31          MREQ    WR                 | Memory write to  0FE <- 31\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:CD          MREQ RD                    | Memory read from 005 -> CD\n#053H T8  AB:0FF DB:33          MREQ    WR                 | Memory write to  0FF <- 33\n#056H T11 AB:0FE DB:35          MREQ    WR                 | Memory write to  0FE <- 35\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:CE          MREQ RD                    | Memory read from 005 -> CE\n#053H T8  AB:0FF DB:34          MREQ    WR                 | Memory write to  0FF <- 34\n#056H T11 AB:0FE DB:31          MREQ    WR                 | Memory write to  0FE <- 31\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:CF          MREQ RD                    | Memory read from 005 -> CF\n#053H T8  AB:0FF DB:35          MREQ    WR                 | Memory write to  0FF <- 35\n#056H T11 AB:0FE DB:35          MREQ    WR                 | Memory write to  0FE <- 35\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:D0          MREQ RD                    | Memory read from 005 -> D0\n#053H T8  AB:0FF DB:36          MREQ    WR                 | Memory write to  0FF <- 36\n#056H T11 AB:0FE DB:25          MREQ    WR                 | Memory write to  0FE <- 25\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:D1          MREQ RD                    | Memory read from 005 -> D1\n#053H T8  AB:0FF DB:37          MREQ    WR                 | Memory write to  0FF <- 37\n#056H T11 AB:0FE DB:21          MREQ    WR                 | Memory write to  0FE <- 21\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:D2          MREQ RD                    | Memory read from 005 -> D2\n#053H T8  AB:0FF DB:38          MREQ    WR                 | Memory write to  0FF <- 38\n#056H T11 AB:0FE DB:29          MREQ    WR                 | Memory write to  0FE <- 29\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:D3          MREQ RD                    | Memory read from 005 -> D3\n#053H T8  AB:0FF DB:39          MREQ    WR                 | Memory write to  0FF <- 39\n#056H T11 AB:0FE DB:2D          MREQ    WR                 | Memory write to  0FE <- 2D\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:D4          MREQ RD                    | Memory read from 005 -> D4\n#053H T8  AB:0FF DB:3A          MREQ    WR                 | Memory write to  0FF <- 3A\n#056H T11 AB:0FE DB:2D          MREQ    WR                 | Memory write to  0FE <- 2D\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:D5          MREQ RD                    | Memory read from 005 -> D5\n#053H T8  AB:0FF DB:3B          MREQ    WR                 | Memory write to  0FF <- 3B\n#056H T11 AB:0FE DB:29          MREQ    WR                 | Memory write to  0FE <- 29\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:D6          MREQ RD                    | Memory read from 005 -> D6\n#053H T8  AB:0FF DB:3C          MREQ    WR                 | Memory write to  0FF <- 3C\n#056H T11 AB:0FE DB:2D          MREQ    WR                 | Memory write to  0FE <- 2D\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:D7          MREQ RD                    | Memory read from 005 -> D7\n#053H T8  AB:0FF DB:3D          MREQ    WR                 | Memory write to  0FF <- 3D\n#056H T11 AB:0FE DB:29          MREQ    WR                 | Memory write to  0FE <- 29\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:D8          MREQ RD                    | Memory read from 005 -> D8\n#053H T8  AB:0FF DB:3E          MREQ    WR                 | Memory write to  0FF <- 3E\n#056H T11 AB:0FE DB:29          MREQ    WR                 | Memory write to  0FE <- 29\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:D9          MREQ RD                    | Memory read from 005 -> D9\n#053H T8  AB:0FF DB:3F          MREQ    WR                 | Memory write to  0FF <- 3F\n#056H T11 AB:0FE DB:2D          MREQ    WR                 | Memory write to  0FE <- 2D\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:DA          MREQ RD                    | Memory read from 005 -> DA\n#053H T8  AB:0FF DB:40          MREQ    WR                 | Memory write to  0FF <- 40\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:DB          MREQ RD                    | Memory read from 005 -> DB\n#053H T8  AB:0FF DB:41          MREQ    WR                 | Memory write to  0FF <- 41\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:DC          MREQ RD                    | Memory read from 005 -> DC\n#053H T8  AB:0FF DB:42          MREQ    WR                 | Memory write to  0FF <- 42\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:DD          MREQ RD                    | Memory read from 005 -> DD\n#053H T8  AB:0FF DB:43          MREQ    WR                 | Memory write to  0FF <- 43\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:DE          MREQ RD                    | Memory read from 005 -> DE\n#053H T8  AB:0FF DB:44          MREQ    WR                 | Memory write to  0FF <- 44\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:DF          MREQ RD                    | Memory read from 005 -> DF\n#053H T8  AB:0FF DB:45          MREQ    WR                 | Memory write to  0FF <- 45\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:E0          MREQ RD                    | Memory read from 005 -> E0\n#053H T8  AB:0FF DB:46          MREQ    WR                 | Memory write to  0FF <- 46\n#056H T11 AB:0FE DB:01          MREQ    WR                 | Memory write to  0FE <- 01\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:E1          MREQ RD                    | Memory read from 005 -> E1\n#053H T8  AB:0FF DB:47          MREQ    WR                 | Memory write to  0FF <- 47\n#056H T11 AB:0FE DB:05          MREQ    WR                 | Memory write to  0FE <- 05\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:E2          MREQ RD                    | Memory read from 005 -> E2\n#053H T8  AB:0FF DB:48          MREQ    WR                 | Memory write to  0FF <- 48\n#056H T11 AB:0FE DB:0D          MREQ    WR                 | Memory write to  0FE <- 0D\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:E3          MREQ RD                    | Memory read from 005 -> E3\n#053H T8  AB:0FF DB:49          MREQ    WR                 | Memory write to  0FF <- 49\n#056H T11 AB:0FE DB:09          MREQ    WR                 | Memory write to  0FE <- 09\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:E4          MREQ RD                    | Memory read from 005 -> E4\n#053H T8  AB:0FF DB:4A          MREQ    WR                 | Memory write to  0FF <- 4A\n#056H T11 AB:0FE DB:09          MREQ    WR                 | Memory write to  0FE <- 09\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:E5          MREQ RD                    | Memory read from 005 -> E5\n#053H T8  AB:0FF DB:4B          MREQ    WR                 | Memory write to  0FF <- 4B\n#056H T11 AB:0FE DB:0D          MREQ    WR                 | Memory write to  0FE <- 0D\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:E6          MREQ RD                    | Memory read from 005 -> E6\n#053H T8  AB:0FF DB:4C          MREQ    WR                 | Memory write to  0FF <- 4C\n#056H T11 AB:0FE DB:09          MREQ    WR                 | Memory write to  0FE <- 09\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:E7          MREQ RD                    | Memory read from 005 -> E7\n#053H T8  AB:0FF DB:4D          MREQ    WR                 | Memory write to  0FF <- 4D\n#056H T11 AB:0FE DB:0D          MREQ    WR                 | Memory write to  0FE <- 0D\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:E8          MREQ RD                    | Memory read from 005 -> E8\n#053H T8  AB:0FF DB:4E          MREQ    WR                 | Memory write to  0FF <- 4E\n#056H T11 AB:0FE DB:0D          MREQ    WR                 | Memory write to  0FE <- 0D\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:E9          MREQ RD                    | Memory read from 005 -> E9\n#053H T8  AB:0FF DB:4F          MREQ    WR                 | Memory write to  0FF <- 4F\n#056H T11 AB:0FE DB:09          MREQ    WR                 | Memory write to  0FE <- 09\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:EA          MREQ RD                    | Memory read from 005 -> EA\n#053H T8  AB:0FF DB:50          MREQ    WR                 | Memory write to  0FF <- 50\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:EB          MREQ RD                    | Memory read from 005 -> EB\n#053H T8  AB:0FF DB:51          MREQ    WR                 | Memory write to  0FF <- 51\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:EC          MREQ RD                    | Memory read from 005 -> EC\n#053H T8  AB:0FF DB:52          MREQ    WR                 | Memory write to  0FF <- 52\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:ED          MREQ RD                    | Memory read from 005 -> ED\n#053H T8  AB:0FF DB:53          MREQ    WR                 | Memory write to  0FF <- 53\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:EE          MREQ RD                    | Memory read from 005 -> EE\n#053H T8  AB:0FF DB:54          MREQ    WR                 | Memory write to  0FF <- 54\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:EF          MREQ RD                    | Memory read from 005 -> EF\n#053H T8  AB:0FF DB:55          MREQ    WR                 | Memory write to  0FF <- 55\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:F0          MREQ RD                    | Memory read from 005 -> F0\n#053H T8  AB:0FF DB:56          MREQ    WR                 | Memory write to  0FF <- 56\n#056H T11 AB:0FE DB:05          MREQ    WR                 | Memory write to  0FE <- 05\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:F1          MREQ RD                    | Memory read from 005 -> F1\n#053H T8  AB:0FF DB:57          MREQ    WR                 | Memory write to  0FF <- 57\n#056H T11 AB:0FE DB:01          MREQ    WR                 | Memory write to  0FE <- 01\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:F2          MREQ RD                    | Memory read from 005 -> F2\n#053H T8  AB:0FF DB:58          MREQ    WR                 | Memory write to  0FF <- 58\n#056H T11 AB:0FE DB:09          MREQ    WR                 | Memory write to  0FE <- 09\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:F3          MREQ RD                    | Memory read from 005 -> F3\n#053H T8  AB:0FF DB:59          MREQ    WR                 | Memory write to  0FF <- 59\n#056H T11 AB:0FE DB:0D          MREQ    WR                 | Memory write to  0FE <- 0D\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:F4          MREQ RD                    | Memory read from 005 -> F4\n#053H T8  AB:0FF DB:5A          MREQ    WR                 | Memory write to  0FF <- 5A\n#056H T11 AB:0FE DB:0D          MREQ    WR                 | Memory write to  0FE <- 0D\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:F5          MREQ RD                    | Memory read from 005 -> F5\n#053H T8  AB:0FF DB:5B          MREQ    WR                 | Memory write to  0FF <- 5B\n#056H T11 AB:0FE DB:09          MREQ    WR                 | Memory write to  0FE <- 09\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:F6          MREQ RD                    | Memory read from 005 -> F6\n#053H T8  AB:0FF DB:5C          MREQ    WR                 | Memory write to  0FF <- 5C\n#056H T11 AB:0FE DB:0D          MREQ    WR                 | Memory write to  0FE <- 0D\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:F7          MREQ RD                    | Memory read from 005 -> F7\n#053H T8  AB:0FF DB:5D          MREQ    WR                 | Memory write to  0FF <- 5D\n#056H T11 AB:0FE DB:09          MREQ    WR                 | Memory write to  0FE <- 09\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:F8          MREQ RD                    | Memory read from 005 -> F8\n#053H T8  AB:0FF DB:5E          MREQ    WR                 | Memory write to  0FF <- 5E\n#056H T11 AB:0FE DB:09          MREQ    WR                 | Memory write to  0FE <- 09\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:F9          MREQ RD                    | Memory read from 005 -> F9\n#053H T8  AB:0FF DB:5F          MREQ    WR                 | Memory write to  0FF <- 5F\n#056H T11 AB:0FE DB:0D          MREQ    WR                 | Memory write to  0FE <- 0D\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:FA          MREQ RD                    | Memory read from 005 -> FA\n#053H T8  AB:0FF DB:60          MREQ    WR                 | Memory write to  0FF <- 60\n#056H T11 AB:0FE DB:35          MREQ    WR                 | Memory write to  0FE <- 35\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:FB          MREQ RD                    | Memory read from 005 -> FB\n#053H T8  AB:0FF DB:61          MREQ    WR                 | Memory write to  0FF <- 61\n#056H T11 AB:0FE DB:31          MREQ    WR                 | Memory write to  0FE <- 31\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:FC          MREQ RD                    | Memory read from 005 -> FC\n#053H T8  AB:0FF DB:62          MREQ    WR                 | Memory write to  0FF <- 62\n#056H T11 AB:0FE DB:31          MREQ    WR                 | Memory write to  0FE <- 31\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:FD          MREQ RD                    | Memory read from 005 -> FD\n#053H T8  AB:0FF DB:63          MREQ    WR                 | Memory write to  0FF <- 63\n#056H T11 AB:0FE DB:35          MREQ    WR                 | Memory write to  0FE <- 35\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:FE          MREQ RD                    | Memory read from 005 -> FE\n#053H T8  AB:0FF DB:64          MREQ    WR                 | Memory write to  0FF <- 64\n#056H T11 AB:0FE DB:31          MREQ    WR                 | Memory write to  0FE <- 31\n#017H T7  AB:004 DB:10          MREQ RD                    | Memory read from 004 -> 10\n#020H T10 AB:005 DB:FF          MREQ RD                    | Memory read from 005 -> FF\n#053H T8  AB:0FF DB:65          MREQ    WR                 | Memory write to  0FF <- 65\n#056H T11 AB:0FE DB:35          MREQ    WR                 | Memory write to  0FE <- 35\n"
  },
  {
    "path": "tools/dongle/daa/daa_a-hc.out",
    "content": "#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:00          MREQ RD                    | Memory read from 005 -> 00\n#053H T8  AB:0FF DB:66          MREQ    WR                 | Memory write to  0FF <- 66\n#056H T11 AB:0FE DB:25          MREQ    WR                 | Memory write to  0FE <- 25\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:01          MREQ RD                    | Memory read from 005 -> 01\n#053H T8  AB:0FF DB:67          MREQ    WR                 | Memory write to  0FF <- 67\n#056H T11 AB:0FE DB:21          MREQ    WR                 | Memory write to  0FE <- 21\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:02          MREQ RD                    | Memory read from 005 -> 02\n#053H T8  AB:0FF DB:68          MREQ    WR                 | Memory write to  0FF <- 68\n#056H T11 AB:0FE DB:29          MREQ    WR                 | Memory write to  0FE <- 29\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:03          MREQ RD                    | Memory read from 005 -> 03\n#053H T8  AB:0FF DB:69          MREQ    WR                 | Memory write to  0FF <- 69\n#056H T11 AB:0FE DB:2D          MREQ    WR                 | Memory write to  0FE <- 2D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:04          MREQ RD                    | Memory read from 005 -> 04\n#053H T8  AB:0FF DB:6A          MREQ    WR                 | Memory write to  0FF <- 6A\n#056H T11 AB:0FE DB:2D          MREQ    WR                 | Memory write to  0FE <- 2D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:05          MREQ RD                    | Memory read from 005 -> 05\n#053H T8  AB:0FF DB:6B          MREQ    WR                 | Memory write to  0FF <- 6B\n#056H T11 AB:0FE DB:29          MREQ    WR                 | Memory write to  0FE <- 29\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:06          MREQ RD                    | Memory read from 005 -> 06\n#053H T8  AB:0FF DB:6C          MREQ    WR                 | Memory write to  0FF <- 6C\n#056H T11 AB:0FE DB:2D          MREQ    WR                 | Memory write to  0FE <- 2D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:07          MREQ RD                    | Memory read from 005 -> 07\n#053H T8  AB:0FF DB:6D          MREQ    WR                 | Memory write to  0FF <- 6D\n#056H T11 AB:0FE DB:29          MREQ    WR                 | Memory write to  0FE <- 29\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:08          MREQ RD                    | Memory read from 005 -> 08\n#053H T8  AB:0FF DB:6E          MREQ    WR                 | Memory write to  0FF <- 6E\n#056H T11 AB:0FE DB:29          MREQ    WR                 | Memory write to  0FE <- 29\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:09          MREQ RD                    | Memory read from 005 -> 09\n#053H T8  AB:0FF DB:6F          MREQ    WR                 | Memory write to  0FF <- 6F\n#056H T11 AB:0FE DB:2D          MREQ    WR                 | Memory write to  0FE <- 2D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:0A          MREQ RD                    | Memory read from 005 -> 0A\n#053H T8  AB:0FF DB:70          MREQ    WR                 | Memory write to  0FF <- 70\n#056H T11 AB:0FE DB:31          MREQ    WR                 | Memory write to  0FE <- 31\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:0B          MREQ RD                    | Memory read from 005 -> 0B\n#053H T8  AB:0FF DB:71          MREQ    WR                 | Memory write to  0FF <- 71\n#056H T11 AB:0FE DB:35          MREQ    WR                 | Memory write to  0FE <- 35\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:0C          MREQ RD                    | Memory read from 005 -> 0C\n#053H T8  AB:0FF DB:72          MREQ    WR                 | Memory write to  0FF <- 72\n#056H T11 AB:0FE DB:35          MREQ    WR                 | Memory write to  0FE <- 35\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:0D          MREQ RD                    | Memory read from 005 -> 0D\n#053H T8  AB:0FF DB:73          MREQ    WR                 | Memory write to  0FF <- 73\n#056H T11 AB:0FE DB:31          MREQ    WR                 | Memory write to  0FE <- 31\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:0E          MREQ RD                    | Memory read from 005 -> 0E\n#053H T8  AB:0FF DB:74          MREQ    WR                 | Memory write to  0FF <- 74\n#056H T11 AB:0FE DB:35          MREQ    WR                 | Memory write to  0FE <- 35\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:0F          MREQ RD                    | Memory read from 005 -> 0F\n#053H T8  AB:0FF DB:75          MREQ    WR                 | Memory write to  0FF <- 75\n#056H T11 AB:0FE DB:31          MREQ    WR                 | Memory write to  0FE <- 31\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:10          MREQ RD                    | Memory read from 005 -> 10\n#053H T8  AB:0FF DB:76          MREQ    WR                 | Memory write to  0FF <- 76\n#056H T11 AB:0FE DB:21          MREQ    WR                 | Memory write to  0FE <- 21\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:11          MREQ RD                    | Memory read from 005 -> 11\n#053H T8  AB:0FF DB:77          MREQ    WR                 | Memory write to  0FF <- 77\n#056H T11 AB:0FE DB:25          MREQ    WR                 | Memory write to  0FE <- 25\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:12          MREQ RD                    | Memory read from 005 -> 12\n#053H T8  AB:0FF DB:78          MREQ    WR                 | Memory write to  0FF <- 78\n#056H T11 AB:0FE DB:2D          MREQ    WR                 | Memory write to  0FE <- 2D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:13          MREQ RD                    | Memory read from 005 -> 13\n#053H T8  AB:0FF DB:79          MREQ    WR                 | Memory write to  0FF <- 79\n#056H T11 AB:0FE DB:29          MREQ    WR                 | Memory write to  0FE <- 29\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:14          MREQ RD                    | Memory read from 005 -> 14\n#053H T8  AB:0FF DB:7A          MREQ    WR                 | Memory write to  0FF <- 7A\n#056H T11 AB:0FE DB:29          MREQ    WR                 | Memory write to  0FE <- 29\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:15          MREQ RD                    | Memory read from 005 -> 15\n#053H T8  AB:0FF DB:7B          MREQ    WR                 | Memory write to  0FF <- 7B\n#056H T11 AB:0FE DB:2D          MREQ    WR                 | Memory write to  0FE <- 2D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:16          MREQ RD                    | Memory read from 005 -> 16\n#053H T8  AB:0FF DB:7C          MREQ    WR                 | Memory write to  0FF <- 7C\n#056H T11 AB:0FE DB:29          MREQ    WR                 | Memory write to  0FE <- 29\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:17          MREQ RD                    | Memory read from 005 -> 17\n#053H T8  AB:0FF DB:7D          MREQ    WR                 | Memory write to  0FF <- 7D\n#056H T11 AB:0FE DB:2D          MREQ    WR                 | Memory write to  0FE <- 2D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:18          MREQ RD                    | Memory read from 005 -> 18\n#053H T8  AB:0FF DB:7E          MREQ    WR                 | Memory write to  0FF <- 7E\n#056H T11 AB:0FE DB:2D          MREQ    WR                 | Memory write to  0FE <- 2D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:19          MREQ RD                    | Memory read from 005 -> 19\n#053H T8  AB:0FF DB:7F          MREQ    WR                 | Memory write to  0FF <- 7F\n#056H T11 AB:0FE DB:29          MREQ    WR                 | Memory write to  0FE <- 29\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:1A          MREQ RD                    | Memory read from 005 -> 1A\n#053H T8  AB:0FF DB:80          MREQ    WR                 | Memory write to  0FF <- 80\n#056H T11 AB:0FE DB:91          MREQ    WR                 | Memory write to  0FE <- 91\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:1B          MREQ RD                    | Memory read from 005 -> 1B\n#053H T8  AB:0FF DB:81          MREQ    WR                 | Memory write to  0FF <- 81\n#056H T11 AB:0FE DB:95          MREQ    WR                 | Memory write to  0FE <- 95\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:1C          MREQ RD                    | Memory read from 005 -> 1C\n#053H T8  AB:0FF DB:82          MREQ    WR                 | Memory write to  0FF <- 82\n#056H T11 AB:0FE DB:95          MREQ    WR                 | Memory write to  0FE <- 95\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:1D          MREQ RD                    | Memory read from 005 -> 1D\n#053H T8  AB:0FF DB:83          MREQ    WR                 | Memory write to  0FF <- 83\n#056H T11 AB:0FE DB:91          MREQ    WR                 | Memory write to  0FE <- 91\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:1E          MREQ RD                    | Memory read from 005 -> 1E\n#053H T8  AB:0FF DB:84          MREQ    WR                 | Memory write to  0FF <- 84\n#056H T11 AB:0FE DB:95          MREQ    WR                 | Memory write to  0FE <- 95\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:1F          MREQ RD                    | Memory read from 005 -> 1F\n#053H T8  AB:0FF DB:85          MREQ    WR                 | Memory write to  0FF <- 85\n#056H T11 AB:0FE DB:91          MREQ    WR                 | Memory write to  0FE <- 91\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:20          MREQ RD                    | Memory read from 005 -> 20\n#053H T8  AB:0FF DB:86          MREQ    WR                 | Memory write to  0FF <- 86\n#056H T11 AB:0FE DB:81          MREQ    WR                 | Memory write to  0FE <- 81\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:21          MREQ RD                    | Memory read from 005 -> 21\n#053H T8  AB:0FF DB:87          MREQ    WR                 | Memory write to  0FF <- 87\n#056H T11 AB:0FE DB:85          MREQ    WR                 | Memory write to  0FE <- 85\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:22          MREQ RD                    | Memory read from 005 -> 22\n#053H T8  AB:0FF DB:88          MREQ    WR                 | Memory write to  0FF <- 88\n#056H T11 AB:0FE DB:8D          MREQ    WR                 | Memory write to  0FE <- 8D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:23          MREQ RD                    | Memory read from 005 -> 23\n#053H T8  AB:0FF DB:89          MREQ    WR                 | Memory write to  0FF <- 89\n#056H T11 AB:0FE DB:89          MREQ    WR                 | Memory write to  0FE <- 89\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:24          MREQ RD                    | Memory read from 005 -> 24\n#053H T8  AB:0FF DB:8A          MREQ    WR                 | Memory write to  0FF <- 8A\n#056H T11 AB:0FE DB:89          MREQ    WR                 | Memory write to  0FE <- 89\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:25          MREQ RD                    | Memory read from 005 -> 25\n#053H T8  AB:0FF DB:8B          MREQ    WR                 | Memory write to  0FF <- 8B\n#056H T11 AB:0FE DB:8D          MREQ    WR                 | Memory write to  0FE <- 8D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:26          MREQ RD                    | Memory read from 005 -> 26\n#053H T8  AB:0FF DB:8C          MREQ    WR                 | Memory write to  0FF <- 8C\n#056H T11 AB:0FE DB:89          MREQ    WR                 | Memory write to  0FE <- 89\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:27          MREQ RD                    | Memory read from 005 -> 27\n#053H T8  AB:0FF DB:8D          MREQ    WR                 | Memory write to  0FF <- 8D\n#056H T11 AB:0FE DB:8D          MREQ    WR                 | Memory write to  0FE <- 8D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:28          MREQ RD                    | Memory read from 005 -> 28\n#053H T8  AB:0FF DB:8E          MREQ    WR                 | Memory write to  0FF <- 8E\n#056H T11 AB:0FE DB:8D          MREQ    WR                 | Memory write to  0FE <- 8D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:29          MREQ RD                    | Memory read from 005 -> 29\n#053H T8  AB:0FF DB:8F          MREQ    WR                 | Memory write to  0FF <- 8F\n#056H T11 AB:0FE DB:89          MREQ    WR                 | Memory write to  0FE <- 89\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:2A          MREQ RD                    | Memory read from 005 -> 2A\n#053H T8  AB:0FF DB:90          MREQ    WR                 | Memory write to  0FF <- 90\n#056H T11 AB:0FE DB:95          MREQ    WR                 | Memory write to  0FE <- 95\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:2B          MREQ RD                    | Memory read from 005 -> 2B\n#053H T8  AB:0FF DB:91          MREQ    WR                 | Memory write to  0FF <- 91\n#056H T11 AB:0FE DB:91          MREQ    WR                 | Memory write to  0FE <- 91\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:2C          MREQ RD                    | Memory read from 005 -> 2C\n#053H T8  AB:0FF DB:92          MREQ    WR                 | Memory write to  0FF <- 92\n#056H T11 AB:0FE DB:91          MREQ    WR                 | Memory write to  0FE <- 91\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:2D          MREQ RD                    | Memory read from 005 -> 2D\n#053H T8  AB:0FF DB:93          MREQ    WR                 | Memory write to  0FF <- 93\n#056H T11 AB:0FE DB:95          MREQ    WR                 | Memory write to  0FE <- 95\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:2E          MREQ RD                    | Memory read from 005 -> 2E\n#053H T8  AB:0FF DB:94          MREQ    WR                 | Memory write to  0FF <- 94\n#056H T11 AB:0FE DB:91          MREQ    WR                 | Memory write to  0FE <- 91\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:2F          MREQ RD                    | Memory read from 005 -> 2F\n#053H T8  AB:0FF DB:95          MREQ    WR                 | Memory write to  0FF <- 95\n#056H T11 AB:0FE DB:95          MREQ    WR                 | Memory write to  0FE <- 95\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:30          MREQ RD                    | Memory read from 005 -> 30\n#053H T8  AB:0FF DB:96          MREQ    WR                 | Memory write to  0FF <- 96\n#056H T11 AB:0FE DB:85          MREQ    WR                 | Memory write to  0FE <- 85\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:31          MREQ RD                    | Memory read from 005 -> 31\n#053H T8  AB:0FF DB:97          MREQ    WR                 | Memory write to  0FF <- 97\n#056H T11 AB:0FE DB:81          MREQ    WR                 | Memory write to  0FE <- 81\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:32          MREQ RD                    | Memory read from 005 -> 32\n#053H T8  AB:0FF DB:98          MREQ    WR                 | Memory write to  0FF <- 98\n#056H T11 AB:0FE DB:89          MREQ    WR                 | Memory write to  0FE <- 89\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:33          MREQ RD                    | Memory read from 005 -> 33\n#053H T8  AB:0FF DB:99          MREQ    WR                 | Memory write to  0FF <- 99\n#056H T11 AB:0FE DB:8D          MREQ    WR                 | Memory write to  0FE <- 8D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:34          MREQ RD                    | Memory read from 005 -> 34\n#053H T8  AB:0FF DB:9A          MREQ    WR                 | Memory write to  0FF <- 9A\n#056H T11 AB:0FE DB:8D          MREQ    WR                 | Memory write to  0FE <- 8D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:35          MREQ RD                    | Memory read from 005 -> 35\n#053H T8  AB:0FF DB:9B          MREQ    WR                 | Memory write to  0FF <- 9B\n#056H T11 AB:0FE DB:89          MREQ    WR                 | Memory write to  0FE <- 89\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:36          MREQ RD                    | Memory read from 005 -> 36\n#053H T8  AB:0FF DB:9C          MREQ    WR                 | Memory write to  0FF <- 9C\n#056H T11 AB:0FE DB:8D          MREQ    WR                 | Memory write to  0FE <- 8D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:37          MREQ RD                    | Memory read from 005 -> 37\n#053H T8  AB:0FF DB:9D          MREQ    WR                 | Memory write to  0FF <- 9D\n#056H T11 AB:0FE DB:89          MREQ    WR                 | Memory write to  0FE <- 89\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:38          MREQ RD                    | Memory read from 005 -> 38\n#053H T8  AB:0FF DB:9E          MREQ    WR                 | Memory write to  0FF <- 9E\n#056H T11 AB:0FE DB:89          MREQ    WR                 | Memory write to  0FE <- 89\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:39          MREQ RD                    | Memory read from 005 -> 39\n#053H T8  AB:0FF DB:9F          MREQ    WR                 | Memory write to  0FF <- 9F\n#056H T11 AB:0FE DB:8D          MREQ    WR                 | Memory write to  0FE <- 8D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:3A          MREQ RD                    | Memory read from 005 -> 3A\n#053H T8  AB:0FF DB:A0          MREQ    WR                 | Memory write to  0FF <- A0\n#056H T11 AB:0FE DB:B5          MREQ    WR                 | Memory write to  0FE <- B5\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:3B          MREQ RD                    | Memory read from 005 -> 3B\n#053H T8  AB:0FF DB:A1          MREQ    WR                 | Memory write to  0FF <- A1\n#056H T11 AB:0FE DB:B1          MREQ    WR                 | Memory write to  0FE <- B1\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:3C          MREQ RD                    | Memory read from 005 -> 3C\n#053H T8  AB:0FF DB:A2          MREQ    WR                 | Memory write to  0FF <- A2\n#056H T11 AB:0FE DB:B1          MREQ    WR                 | Memory write to  0FE <- B1\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:3D          MREQ RD                    | Memory read from 005 -> 3D\n#053H T8  AB:0FF DB:A3          MREQ    WR                 | Memory write to  0FF <- A3\n#056H T11 AB:0FE DB:B5          MREQ    WR                 | Memory write to  0FE <- B5\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:3E          MREQ RD                    | Memory read from 005 -> 3E\n#053H T8  AB:0FF DB:A4          MREQ    WR                 | Memory write to  0FF <- A4\n#056H T11 AB:0FE DB:B1          MREQ    WR                 | Memory write to  0FE <- B1\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:3F          MREQ RD                    | Memory read from 005 -> 3F\n#053H T8  AB:0FF DB:A5          MREQ    WR                 | Memory write to  0FF <- A5\n#056H T11 AB:0FE DB:B5          MREQ    WR                 | Memory write to  0FE <- B5\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:40          MREQ RD                    | Memory read from 005 -> 40\n#053H T8  AB:0FF DB:A6          MREQ    WR                 | Memory write to  0FF <- A6\n#056H T11 AB:0FE DB:A5          MREQ    WR                 | Memory write to  0FE <- A5\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:41          MREQ RD                    | Memory read from 005 -> 41\n#053H T8  AB:0FF DB:A7          MREQ    WR                 | Memory write to  0FF <- A7\n#056H T11 AB:0FE DB:A1          MREQ    WR                 | Memory write to  0FE <- A1\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:42          MREQ RD                    | Memory read from 005 -> 42\n#053H T8  AB:0FF DB:A8          MREQ    WR                 | Memory write to  0FF <- A8\n#056H T11 AB:0FE DB:A9          MREQ    WR                 | Memory write to  0FE <- A9\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:43          MREQ RD                    | Memory read from 005 -> 43\n#053H T8  AB:0FF DB:A9          MREQ    WR                 | Memory write to  0FF <- A9\n#056H T11 AB:0FE DB:AD          MREQ    WR                 | Memory write to  0FE <- AD\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:44          MREQ RD                    | Memory read from 005 -> 44\n#053H T8  AB:0FF DB:AA          MREQ    WR                 | Memory write to  0FF <- AA\n#056H T11 AB:0FE DB:AD          MREQ    WR                 | Memory write to  0FE <- AD\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:45          MREQ RD                    | Memory read from 005 -> 45\n#053H T8  AB:0FF DB:AB          MREQ    WR                 | Memory write to  0FF <- AB\n#056H T11 AB:0FE DB:A9          MREQ    WR                 | Memory write to  0FE <- A9\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:46          MREQ RD                    | Memory read from 005 -> 46\n#053H T8  AB:0FF DB:AC          MREQ    WR                 | Memory write to  0FF <- AC\n#056H T11 AB:0FE DB:AD          MREQ    WR                 | Memory write to  0FE <- AD\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:47          MREQ RD                    | Memory read from 005 -> 47\n#053H T8  AB:0FF DB:AD          MREQ    WR                 | Memory write to  0FF <- AD\n#056H T11 AB:0FE DB:A9          MREQ    WR                 | Memory write to  0FE <- A9\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:48          MREQ RD                    | Memory read from 005 -> 48\n#053H T8  AB:0FF DB:AE          MREQ    WR                 | Memory write to  0FF <- AE\n#056H T11 AB:0FE DB:A9          MREQ    WR                 | Memory write to  0FE <- A9\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:49          MREQ RD                    | Memory read from 005 -> 49\n#053H T8  AB:0FF DB:AF          MREQ    WR                 | Memory write to  0FF <- AF\n#056H T11 AB:0FE DB:AD          MREQ    WR                 | Memory write to  0FE <- AD\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:4A          MREQ RD                    | Memory read from 005 -> 4A\n#053H T8  AB:0FF DB:B0          MREQ    WR                 | Memory write to  0FF <- B0\n#056H T11 AB:0FE DB:B1          MREQ    WR                 | Memory write to  0FE <- B1\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:4B          MREQ RD                    | Memory read from 005 -> 4B\n#053H T8  AB:0FF DB:B1          MREQ    WR                 | Memory write to  0FF <- B1\n#056H T11 AB:0FE DB:B5          MREQ    WR                 | Memory write to  0FE <- B5\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:4C          MREQ RD                    | Memory read from 005 -> 4C\n#053H T8  AB:0FF DB:B2          MREQ    WR                 | Memory write to  0FF <- B2\n#056H T11 AB:0FE DB:B5          MREQ    WR                 | Memory write to  0FE <- B5\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:4D          MREQ RD                    | Memory read from 005 -> 4D\n#053H T8  AB:0FF DB:B3          MREQ    WR                 | Memory write to  0FF <- B3\n#056H T11 AB:0FE DB:B1          MREQ    WR                 | Memory write to  0FE <- B1\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:4E          MREQ RD                    | Memory read from 005 -> 4E\n#053H T8  AB:0FF DB:B4          MREQ    WR                 | Memory write to  0FF <- B4\n#056H T11 AB:0FE DB:B5          MREQ    WR                 | Memory write to  0FE <- B5\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:4F          MREQ RD                    | Memory read from 005 -> 4F\n#053H T8  AB:0FF DB:B5          MREQ    WR                 | Memory write to  0FF <- B5\n#056H T11 AB:0FE DB:B1          MREQ    WR                 | Memory write to  0FE <- B1\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:50          MREQ RD                    | Memory read from 005 -> 50\n#053H T8  AB:0FF DB:B6          MREQ    WR                 | Memory write to  0FF <- B6\n#056H T11 AB:0FE DB:A1          MREQ    WR                 | Memory write to  0FE <- A1\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:51          MREQ RD                    | Memory read from 005 -> 51\n#053H T8  AB:0FF DB:B7          MREQ    WR                 | Memory write to  0FF <- B7\n#056H T11 AB:0FE DB:A5          MREQ    WR                 | Memory write to  0FE <- A5\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:52          MREQ RD                    | Memory read from 005 -> 52\n#053H T8  AB:0FF DB:B8          MREQ    WR                 | Memory write to  0FF <- B8\n#056H T11 AB:0FE DB:AD          MREQ    WR                 | Memory write to  0FE <- AD\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:53          MREQ RD                    | Memory read from 005 -> 53\n#053H T8  AB:0FF DB:B9          MREQ    WR                 | Memory write to  0FF <- B9\n#056H T11 AB:0FE DB:A9          MREQ    WR                 | Memory write to  0FE <- A9\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:54          MREQ RD                    | Memory read from 005 -> 54\n#053H T8  AB:0FF DB:BA          MREQ    WR                 | Memory write to  0FF <- BA\n#056H T11 AB:0FE DB:A9          MREQ    WR                 | Memory write to  0FE <- A9\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:55          MREQ RD                    | Memory read from 005 -> 55\n#053H T8  AB:0FF DB:BB          MREQ    WR                 | Memory write to  0FF <- BB\n#056H T11 AB:0FE DB:AD          MREQ    WR                 | Memory write to  0FE <- AD\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:56          MREQ RD                    | Memory read from 005 -> 56\n#053H T8  AB:0FF DB:BC          MREQ    WR                 | Memory write to  0FF <- BC\n#056H T11 AB:0FE DB:A9          MREQ    WR                 | Memory write to  0FE <- A9\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:57          MREQ RD                    | Memory read from 005 -> 57\n#053H T8  AB:0FF DB:BD          MREQ    WR                 | Memory write to  0FF <- BD\n#056H T11 AB:0FE DB:AD          MREQ    WR                 | Memory write to  0FE <- AD\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:58          MREQ RD                    | Memory read from 005 -> 58\n#053H T8  AB:0FF DB:BE          MREQ    WR                 | Memory write to  0FF <- BE\n#056H T11 AB:0FE DB:AD          MREQ    WR                 | Memory write to  0FE <- AD\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:59          MREQ RD                    | Memory read from 005 -> 59\n#053H T8  AB:0FF DB:BF          MREQ    WR                 | Memory write to  0FF <- BF\n#056H T11 AB:0FE DB:A9          MREQ    WR                 | Memory write to  0FE <- A9\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:5A          MREQ RD                    | Memory read from 005 -> 5A\n#053H T8  AB:0FF DB:C0          MREQ    WR                 | Memory write to  0FF <- C0\n#056H T11 AB:0FE DB:95          MREQ    WR                 | Memory write to  0FE <- 95\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:5B          MREQ RD                    | Memory read from 005 -> 5B\n#053H T8  AB:0FF DB:C1          MREQ    WR                 | Memory write to  0FF <- C1\n#056H T11 AB:0FE DB:91          MREQ    WR                 | Memory write to  0FE <- 91\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:5C          MREQ RD                    | Memory read from 005 -> 5C\n#053H T8  AB:0FF DB:C2          MREQ    WR                 | Memory write to  0FF <- C2\n#056H T11 AB:0FE DB:91          MREQ    WR                 | Memory write to  0FE <- 91\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:5D          MREQ RD                    | Memory read from 005 -> 5D\n#053H T8  AB:0FF DB:C3          MREQ    WR                 | Memory write to  0FF <- C3\n#056H T11 AB:0FE DB:95          MREQ    WR                 | Memory write to  0FE <- 95\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:5E          MREQ RD                    | Memory read from 005 -> 5E\n#053H T8  AB:0FF DB:C4          MREQ    WR                 | Memory write to  0FF <- C4\n#056H T11 AB:0FE DB:91          MREQ    WR                 | Memory write to  0FE <- 91\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:5F          MREQ RD                    | Memory read from 005 -> 5F\n#053H T8  AB:0FF DB:C5          MREQ    WR                 | Memory write to  0FF <- C5\n#056H T11 AB:0FE DB:95          MREQ    WR                 | Memory write to  0FE <- 95\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:60          MREQ RD                    | Memory read from 005 -> 60\n#053H T8  AB:0FF DB:C6          MREQ    WR                 | Memory write to  0FF <- C6\n#056H T11 AB:0FE DB:85          MREQ    WR                 | Memory write to  0FE <- 85\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:61          MREQ RD                    | Memory read from 005 -> 61\n#053H T8  AB:0FF DB:C7          MREQ    WR                 | Memory write to  0FF <- C7\n#056H T11 AB:0FE DB:81          MREQ    WR                 | Memory write to  0FE <- 81\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:62          MREQ RD                    | Memory read from 005 -> 62\n#053H T8  AB:0FF DB:C8          MREQ    WR                 | Memory write to  0FF <- C8\n#056H T11 AB:0FE DB:89          MREQ    WR                 | Memory write to  0FE <- 89\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:63          MREQ RD                    | Memory read from 005 -> 63\n#053H T8  AB:0FF DB:C9          MREQ    WR                 | Memory write to  0FF <- C9\n#056H T11 AB:0FE DB:8D          MREQ    WR                 | Memory write to  0FE <- 8D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:64          MREQ RD                    | Memory read from 005 -> 64\n#053H T8  AB:0FF DB:CA          MREQ    WR                 | Memory write to  0FF <- CA\n#056H T11 AB:0FE DB:8D          MREQ    WR                 | Memory write to  0FE <- 8D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:65          MREQ RD                    | Memory read from 005 -> 65\n#053H T8  AB:0FF DB:CB          MREQ    WR                 | Memory write to  0FF <- CB\n#056H T11 AB:0FE DB:89          MREQ    WR                 | Memory write to  0FE <- 89\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:66          MREQ RD                    | Memory read from 005 -> 66\n#053H T8  AB:0FF DB:CC          MREQ    WR                 | Memory write to  0FF <- CC\n#056H T11 AB:0FE DB:8D          MREQ    WR                 | Memory write to  0FE <- 8D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:67          MREQ RD                    | Memory read from 005 -> 67\n#053H T8  AB:0FF DB:CD          MREQ    WR                 | Memory write to  0FF <- CD\n#056H T11 AB:0FE DB:89          MREQ    WR                 | Memory write to  0FE <- 89\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:68          MREQ RD                    | Memory read from 005 -> 68\n#053H T8  AB:0FF DB:CE          MREQ    WR                 | Memory write to  0FF <- CE\n#056H T11 AB:0FE DB:89          MREQ    WR                 | Memory write to  0FE <- 89\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:69          MREQ RD                    | Memory read from 005 -> 69\n#053H T8  AB:0FF DB:CF          MREQ    WR                 | Memory write to  0FF <- CF\n#056H T11 AB:0FE DB:8D          MREQ    WR                 | Memory write to  0FE <- 8D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:6A          MREQ RD                    | Memory read from 005 -> 6A\n#053H T8  AB:0FF DB:D0          MREQ    WR                 | Memory write to  0FF <- D0\n#056H T11 AB:0FE DB:91          MREQ    WR                 | Memory write to  0FE <- 91\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:6B          MREQ RD                    | Memory read from 005 -> 6B\n#053H T8  AB:0FF DB:D1          MREQ    WR                 | Memory write to  0FF <- D1\n#056H T11 AB:0FE DB:95          MREQ    WR                 | Memory write to  0FE <- 95\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:6C          MREQ RD                    | Memory read from 005 -> 6C\n#053H T8  AB:0FF DB:D2          MREQ    WR                 | Memory write to  0FF <- D2\n#056H T11 AB:0FE DB:95          MREQ    WR                 | Memory write to  0FE <- 95\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:6D          MREQ RD                    | Memory read from 005 -> 6D\n#053H T8  AB:0FF DB:D3          MREQ    WR                 | Memory write to  0FF <- D3\n#056H T11 AB:0FE DB:91          MREQ    WR                 | Memory write to  0FE <- 91\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:6E          MREQ RD                    | Memory read from 005 -> 6E\n#053H T8  AB:0FF DB:D4          MREQ    WR                 | Memory write to  0FF <- D4\n#056H T11 AB:0FE DB:95          MREQ    WR                 | Memory write to  0FE <- 95\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:6F          MREQ RD                    | Memory read from 005 -> 6F\n#053H T8  AB:0FF DB:D5          MREQ    WR                 | Memory write to  0FF <- D5\n#056H T11 AB:0FE DB:91          MREQ    WR                 | Memory write to  0FE <- 91\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:70          MREQ RD                    | Memory read from 005 -> 70\n#053H T8  AB:0FF DB:D6          MREQ    WR                 | Memory write to  0FF <- D6\n#056H T11 AB:0FE DB:81          MREQ    WR                 | Memory write to  0FE <- 81\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:71          MREQ RD                    | Memory read from 005 -> 71\n#053H T8  AB:0FF DB:D7          MREQ    WR                 | Memory write to  0FF <- D7\n#056H T11 AB:0FE DB:85          MREQ    WR                 | Memory write to  0FE <- 85\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:72          MREQ RD                    | Memory read from 005 -> 72\n#053H T8  AB:0FF DB:D8          MREQ    WR                 | Memory write to  0FF <- D8\n#056H T11 AB:0FE DB:8D          MREQ    WR                 | Memory write to  0FE <- 8D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:73          MREQ RD                    | Memory read from 005 -> 73\n#053H T8  AB:0FF DB:D9          MREQ    WR                 | Memory write to  0FF <- D9\n#056H T11 AB:0FE DB:89          MREQ    WR                 | Memory write to  0FE <- 89\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:74          MREQ RD                    | Memory read from 005 -> 74\n#053H T8  AB:0FF DB:DA          MREQ    WR                 | Memory write to  0FF <- DA\n#056H T11 AB:0FE DB:89          MREQ    WR                 | Memory write to  0FE <- 89\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:75          MREQ RD                    | Memory read from 005 -> 75\n#053H T8  AB:0FF DB:DB          MREQ    WR                 | Memory write to  0FF <- DB\n#056H T11 AB:0FE DB:8D          MREQ    WR                 | Memory write to  0FE <- 8D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:76          MREQ RD                    | Memory read from 005 -> 76\n#053H T8  AB:0FF DB:DC          MREQ    WR                 | Memory write to  0FF <- DC\n#056H T11 AB:0FE DB:89          MREQ    WR                 | Memory write to  0FE <- 89\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:77          MREQ RD                    | Memory read from 005 -> 77\n#053H T8  AB:0FF DB:DD          MREQ    WR                 | Memory write to  0FF <- DD\n#056H T11 AB:0FE DB:8D          MREQ    WR                 | Memory write to  0FE <- 8D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:78          MREQ RD                    | Memory read from 005 -> 78\n#053H T8  AB:0FF DB:DE          MREQ    WR                 | Memory write to  0FF <- DE\n#056H T11 AB:0FE DB:8D          MREQ    WR                 | Memory write to  0FE <- 8D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:79          MREQ RD                    | Memory read from 005 -> 79\n#053H T8  AB:0FF DB:DF          MREQ    WR                 | Memory write to  0FF <- DF\n#056H T11 AB:0FE DB:89          MREQ    WR                 | Memory write to  0FE <- 89\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:7A          MREQ RD                    | Memory read from 005 -> 7A\n#053H T8  AB:0FF DB:E0          MREQ    WR                 | Memory write to  0FF <- E0\n#056H T11 AB:0FE DB:B1          MREQ    WR                 | Memory write to  0FE <- B1\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:7B          MREQ RD                    | Memory read from 005 -> 7B\n#053H T8  AB:0FF DB:E1          MREQ    WR                 | Memory write to  0FF <- E1\n#056H T11 AB:0FE DB:B5          MREQ    WR                 | Memory write to  0FE <- B5\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:7C          MREQ RD                    | Memory read from 005 -> 7C\n#053H T8  AB:0FF DB:E2          MREQ    WR                 | Memory write to  0FF <- E2\n#056H T11 AB:0FE DB:B5          MREQ    WR                 | Memory write to  0FE <- B5\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:7D          MREQ RD                    | Memory read from 005 -> 7D\n#053H T8  AB:0FF DB:E3          MREQ    WR                 | Memory write to  0FF <- E3\n#056H T11 AB:0FE DB:B1          MREQ    WR                 | Memory write to  0FE <- B1\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:7E          MREQ RD                    | Memory read from 005 -> 7E\n#053H T8  AB:0FF DB:E4          MREQ    WR                 | Memory write to  0FF <- E4\n#056H T11 AB:0FE DB:B5          MREQ    WR                 | Memory write to  0FE <- B5\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:7F          MREQ RD                    | Memory read from 005 -> 7F\n#053H T8  AB:0FF DB:E5          MREQ    WR                 | Memory write to  0FF <- E5\n#056H T11 AB:0FE DB:B1          MREQ    WR                 | Memory write to  0FE <- B1\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:80          MREQ RD                    | Memory read from 005 -> 80\n#053H T8  AB:0FF DB:E6          MREQ    WR                 | Memory write to  0FF <- E6\n#056H T11 AB:0FE DB:A1          MREQ    WR                 | Memory write to  0FE <- A1\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:81          MREQ RD                    | Memory read from 005 -> 81\n#053H T8  AB:0FF DB:E7          MREQ    WR                 | Memory write to  0FF <- E7\n#056H T11 AB:0FE DB:A5          MREQ    WR                 | Memory write to  0FE <- A5\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:82          MREQ RD                    | Memory read from 005 -> 82\n#053H T8  AB:0FF DB:E8          MREQ    WR                 | Memory write to  0FF <- E8\n#056H T11 AB:0FE DB:AD          MREQ    WR                 | Memory write to  0FE <- AD\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:83          MREQ RD                    | Memory read from 005 -> 83\n#053H T8  AB:0FF DB:E9          MREQ    WR                 | Memory write to  0FF <- E9\n#056H T11 AB:0FE DB:A9          MREQ    WR                 | Memory write to  0FE <- A9\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:84          MREQ RD                    | Memory read from 005 -> 84\n#053H T8  AB:0FF DB:EA          MREQ    WR                 | Memory write to  0FF <- EA\n#056H T11 AB:0FE DB:A9          MREQ    WR                 | Memory write to  0FE <- A9\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:85          MREQ RD                    | Memory read from 005 -> 85\n#053H T8  AB:0FF DB:EB          MREQ    WR                 | Memory write to  0FF <- EB\n#056H T11 AB:0FE DB:AD          MREQ    WR                 | Memory write to  0FE <- AD\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:86          MREQ RD                    | Memory read from 005 -> 86\n#053H T8  AB:0FF DB:EC          MREQ    WR                 | Memory write to  0FF <- EC\n#056H T11 AB:0FE DB:A9          MREQ    WR                 | Memory write to  0FE <- A9\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:87          MREQ RD                    | Memory read from 005 -> 87\n#053H T8  AB:0FF DB:ED          MREQ    WR                 | Memory write to  0FF <- ED\n#056H T11 AB:0FE DB:AD          MREQ    WR                 | Memory write to  0FE <- AD\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:88          MREQ RD                    | Memory read from 005 -> 88\n#053H T8  AB:0FF DB:EE          MREQ    WR                 | Memory write to  0FF <- EE\n#056H T11 AB:0FE DB:AD          MREQ    WR                 | Memory write to  0FE <- AD\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:89          MREQ RD                    | Memory read from 005 -> 89\n#053H T8  AB:0FF DB:EF          MREQ    WR                 | Memory write to  0FF <- EF\n#056H T11 AB:0FE DB:A9          MREQ    WR                 | Memory write to  0FE <- A9\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:8A          MREQ RD                    | Memory read from 005 -> 8A\n#053H T8  AB:0FF DB:F0          MREQ    WR                 | Memory write to  0FF <- F0\n#056H T11 AB:0FE DB:B5          MREQ    WR                 | Memory write to  0FE <- B5\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:8B          MREQ RD                    | Memory read from 005 -> 8B\n#053H T8  AB:0FF DB:F1          MREQ    WR                 | Memory write to  0FF <- F1\n#056H T11 AB:0FE DB:B1          MREQ    WR                 | Memory write to  0FE <- B1\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:8C          MREQ RD                    | Memory read from 005 -> 8C\n#053H T8  AB:0FF DB:F2          MREQ    WR                 | Memory write to  0FF <- F2\n#056H T11 AB:0FE DB:B1          MREQ    WR                 | Memory write to  0FE <- B1\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:8D          MREQ RD                    | Memory read from 005 -> 8D\n#053H T8  AB:0FF DB:F3          MREQ    WR                 | Memory write to  0FF <- F3\n#056H T11 AB:0FE DB:B5          MREQ    WR                 | Memory write to  0FE <- B5\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:8E          MREQ RD                    | Memory read from 005 -> 8E\n#053H T8  AB:0FF DB:F4          MREQ    WR                 | Memory write to  0FF <- F4\n#056H T11 AB:0FE DB:B1          MREQ    WR                 | Memory write to  0FE <- B1\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:8F          MREQ RD                    | Memory read from 005 -> 8F\n#053H T8  AB:0FF DB:F5          MREQ    WR                 | Memory write to  0FF <- F5\n#056H T11 AB:0FE DB:B5          MREQ    WR                 | Memory write to  0FE <- B5\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:90          MREQ RD                    | Memory read from 005 -> 90\n#053H T8  AB:0FF DB:F6          MREQ    WR                 | Memory write to  0FF <- F6\n#056H T11 AB:0FE DB:A5          MREQ    WR                 | Memory write to  0FE <- A5\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:91          MREQ RD                    | Memory read from 005 -> 91\n#053H T8  AB:0FF DB:F7          MREQ    WR                 | Memory write to  0FF <- F7\n#056H T11 AB:0FE DB:A1          MREQ    WR                 | Memory write to  0FE <- A1\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:92          MREQ RD                    | Memory read from 005 -> 92\n#053H T8  AB:0FF DB:F8          MREQ    WR                 | Memory write to  0FF <- F8\n#056H T11 AB:0FE DB:A9          MREQ    WR                 | Memory write to  0FE <- A9\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:93          MREQ RD                    | Memory read from 005 -> 93\n#053H T8  AB:0FF DB:F9          MREQ    WR                 | Memory write to  0FF <- F9\n#056H T11 AB:0FE DB:AD          MREQ    WR                 | Memory write to  0FE <- AD\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:94          MREQ RD                    | Memory read from 005 -> 94\n#053H T8  AB:0FF DB:FA          MREQ    WR                 | Memory write to  0FF <- FA\n#056H T11 AB:0FE DB:AD          MREQ    WR                 | Memory write to  0FE <- AD\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:95          MREQ RD                    | Memory read from 005 -> 95\n#053H T8  AB:0FF DB:FB          MREQ    WR                 | Memory write to  0FF <- FB\n#056H T11 AB:0FE DB:A9          MREQ    WR                 | Memory write to  0FE <- A9\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:96          MREQ RD                    | Memory read from 005 -> 96\n#053H T8  AB:0FF DB:FC          MREQ    WR                 | Memory write to  0FF <- FC\n#056H T11 AB:0FE DB:AD          MREQ    WR                 | Memory write to  0FE <- AD\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:97          MREQ RD                    | Memory read from 005 -> 97\n#053H T8  AB:0FF DB:FD          MREQ    WR                 | Memory write to  0FF <- FD\n#056H T11 AB:0FE DB:A9          MREQ    WR                 | Memory write to  0FE <- A9\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:98          MREQ RD                    | Memory read from 005 -> 98\n#053H T8  AB:0FF DB:FE          MREQ    WR                 | Memory write to  0FF <- FE\n#056H T11 AB:0FE DB:A9          MREQ    WR                 | Memory write to  0FE <- A9\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:99          MREQ RD                    | Memory read from 005 -> 99\n#053H T8  AB:0FF DB:FF          MREQ    WR                 | Memory write to  0FF <- FF\n#056H T11 AB:0FE DB:AD          MREQ    WR                 | Memory write to  0FE <- AD\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:9A          MREQ RD                    | Memory read from 005 -> 9A\n#053H T8  AB:0FF DB:00          MREQ    WR                 | Memory write to  0FF <- 00\n#056H T11 AB:0FE DB:55          MREQ    WR                 | Memory write to  0FE <- 55\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:9B          MREQ RD                    | Memory read from 005 -> 9B\n#053H T8  AB:0FF DB:01          MREQ    WR                 | Memory write to  0FF <- 01\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:9C          MREQ RD                    | Memory read from 005 -> 9C\n#053H T8  AB:0FF DB:02          MREQ    WR                 | Memory write to  0FF <- 02\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:9D          MREQ RD                    | Memory read from 005 -> 9D\n#053H T8  AB:0FF DB:03          MREQ    WR                 | Memory write to  0FF <- 03\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:9E          MREQ RD                    | Memory read from 005 -> 9E\n#053H T8  AB:0FF DB:04          MREQ    WR                 | Memory write to  0FF <- 04\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:9F          MREQ RD                    | Memory read from 005 -> 9F\n#053H T8  AB:0FF DB:05          MREQ    WR                 | Memory write to  0FF <- 05\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:A0          MREQ RD                    | Memory read from 005 -> A0\n#053H T8  AB:0FF DB:06          MREQ    WR                 | Memory write to  0FF <- 06\n#056H T11 AB:0FE DB:05          MREQ    WR                 | Memory write to  0FE <- 05\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:A1          MREQ RD                    | Memory read from 005 -> A1\n#053H T8  AB:0FF DB:07          MREQ    WR                 | Memory write to  0FF <- 07\n#056H T11 AB:0FE DB:01          MREQ    WR                 | Memory write to  0FE <- 01\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:A2          MREQ RD                    | Memory read from 005 -> A2\n#053H T8  AB:0FF DB:08          MREQ    WR                 | Memory write to  0FF <- 08\n#056H T11 AB:0FE DB:09          MREQ    WR                 | Memory write to  0FE <- 09\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:A3          MREQ RD                    | Memory read from 005 -> A3\n#053H T8  AB:0FF DB:09          MREQ    WR                 | Memory write to  0FF <- 09\n#056H T11 AB:0FE DB:0D          MREQ    WR                 | Memory write to  0FE <- 0D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:A4          MREQ RD                    | Memory read from 005 -> A4\n#053H T8  AB:0FF DB:0A          MREQ    WR                 | Memory write to  0FF <- 0A\n#056H T11 AB:0FE DB:0D          MREQ    WR                 | Memory write to  0FE <- 0D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:A5          MREQ RD                    | Memory read from 005 -> A5\n#053H T8  AB:0FF DB:0B          MREQ    WR                 | Memory write to  0FF <- 0B\n#056H T11 AB:0FE DB:09          MREQ    WR                 | Memory write to  0FE <- 09\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:A6          MREQ RD                    | Memory read from 005 -> A6\n#053H T8  AB:0FF DB:0C          MREQ    WR                 | Memory write to  0FF <- 0C\n#056H T11 AB:0FE DB:0D          MREQ    WR                 | Memory write to  0FE <- 0D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:A7          MREQ RD                    | Memory read from 005 -> A7\n#053H T8  AB:0FF DB:0D          MREQ    WR                 | Memory write to  0FF <- 0D\n#056H T11 AB:0FE DB:09          MREQ    WR                 | Memory write to  0FE <- 09\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:A8          MREQ RD                    | Memory read from 005 -> A8\n#053H T8  AB:0FF DB:0E          MREQ    WR                 | Memory write to  0FF <- 0E\n#056H T11 AB:0FE DB:09          MREQ    WR                 | Memory write to  0FE <- 09\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:A9          MREQ RD                    | Memory read from 005 -> A9\n#053H T8  AB:0FF DB:0F          MREQ    WR                 | Memory write to  0FF <- 0F\n#056H T11 AB:0FE DB:0D          MREQ    WR                 | Memory write to  0FE <- 0D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:AA          MREQ RD                    | Memory read from 005 -> AA\n#053H T8  AB:0FF DB:10          MREQ    WR                 | Memory write to  0FF <- 10\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:AB          MREQ RD                    | Memory read from 005 -> AB\n#053H T8  AB:0FF DB:11          MREQ    WR                 | Memory write to  0FF <- 11\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:AC          MREQ RD                    | Memory read from 005 -> AC\n#053H T8  AB:0FF DB:12          MREQ    WR                 | Memory write to  0FF <- 12\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:AD          MREQ RD                    | Memory read from 005 -> AD\n#053H T8  AB:0FF DB:13          MREQ    WR                 | Memory write to  0FF <- 13\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:AE          MREQ RD                    | Memory read from 005 -> AE\n#053H T8  AB:0FF DB:14          MREQ    WR                 | Memory write to  0FF <- 14\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:AF          MREQ RD                    | Memory read from 005 -> AF\n#053H T8  AB:0FF DB:15          MREQ    WR                 | Memory write to  0FF <- 15\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:B0          MREQ RD                    | Memory read from 005 -> B0\n#053H T8  AB:0FF DB:16          MREQ    WR                 | Memory write to  0FF <- 16\n#056H T11 AB:0FE DB:01          MREQ    WR                 | Memory write to  0FE <- 01\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:B1          MREQ RD                    | Memory read from 005 -> B1\n#053H T8  AB:0FF DB:17          MREQ    WR                 | Memory write to  0FF <- 17\n#056H T11 AB:0FE DB:05          MREQ    WR                 | Memory write to  0FE <- 05\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:B2          MREQ RD                    | Memory read from 005 -> B2\n#053H T8  AB:0FF DB:18          MREQ    WR                 | Memory write to  0FF <- 18\n#056H T11 AB:0FE DB:0D          MREQ    WR                 | Memory write to  0FE <- 0D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:B3          MREQ RD                    | Memory read from 005 -> B3\n#053H T8  AB:0FF DB:19          MREQ    WR                 | Memory write to  0FF <- 19\n#056H T11 AB:0FE DB:09          MREQ    WR                 | Memory write to  0FE <- 09\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:B4          MREQ RD                    | Memory read from 005 -> B4\n#053H T8  AB:0FF DB:1A          MREQ    WR                 | Memory write to  0FF <- 1A\n#056H T11 AB:0FE DB:09          MREQ    WR                 | Memory write to  0FE <- 09\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:B5          MREQ RD                    | Memory read from 005 -> B5\n#053H T8  AB:0FF DB:1B          MREQ    WR                 | Memory write to  0FF <- 1B\n#056H T11 AB:0FE DB:0D          MREQ    WR                 | Memory write to  0FE <- 0D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:B6          MREQ RD                    | Memory read from 005 -> B6\n#053H T8  AB:0FF DB:1C          MREQ    WR                 | Memory write to  0FF <- 1C\n#056H T11 AB:0FE DB:09          MREQ    WR                 | Memory write to  0FE <- 09\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:B7          MREQ RD                    | Memory read from 005 -> B7\n#053H T8  AB:0FF DB:1D          MREQ    WR                 | Memory write to  0FF <- 1D\n#056H T11 AB:0FE DB:0D          MREQ    WR                 | Memory write to  0FE <- 0D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:B8          MREQ RD                    | Memory read from 005 -> B8\n#053H T8  AB:0FF DB:1E          MREQ    WR                 | Memory write to  0FF <- 1E\n#056H T11 AB:0FE DB:0D          MREQ    WR                 | Memory write to  0FE <- 0D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:B9          MREQ RD                    | Memory read from 005 -> B9\n#053H T8  AB:0FF DB:1F          MREQ    WR                 | Memory write to  0FF <- 1F\n#056H T11 AB:0FE DB:09          MREQ    WR                 | Memory write to  0FE <- 09\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:BA          MREQ RD                    | Memory read from 005 -> BA\n#053H T8  AB:0FF DB:20          MREQ    WR                 | Memory write to  0FF <- 20\n#056H T11 AB:0FE DB:31          MREQ    WR                 | Memory write to  0FE <- 31\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:BB          MREQ RD                    | Memory read from 005 -> BB\n#053H T8  AB:0FF DB:21          MREQ    WR                 | Memory write to  0FF <- 21\n#056H T11 AB:0FE DB:35          MREQ    WR                 | Memory write to  0FE <- 35\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:BC          MREQ RD                    | Memory read from 005 -> BC\n#053H T8  AB:0FF DB:22          MREQ    WR                 | Memory write to  0FF <- 22\n#056H T11 AB:0FE DB:35          MREQ    WR                 | Memory write to  0FE <- 35\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:BD          MREQ RD                    | Memory read from 005 -> BD\n#053H T8  AB:0FF DB:23          MREQ    WR                 | Memory write to  0FF <- 23\n#056H T11 AB:0FE DB:31          MREQ    WR                 | Memory write to  0FE <- 31\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:BE          MREQ RD                    | Memory read from 005 -> BE\n#053H T8  AB:0FF DB:24          MREQ    WR                 | Memory write to  0FF <- 24\n#056H T11 AB:0FE DB:35          MREQ    WR                 | Memory write to  0FE <- 35\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:BF          MREQ RD                    | Memory read from 005 -> BF\n#053H T8  AB:0FF DB:25          MREQ    WR                 | Memory write to  0FF <- 25\n#056H T11 AB:0FE DB:31          MREQ    WR                 | Memory write to  0FE <- 31\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:C0          MREQ RD                    | Memory read from 005 -> C0\n#053H T8  AB:0FF DB:26          MREQ    WR                 | Memory write to  0FF <- 26\n#056H T11 AB:0FE DB:21          MREQ    WR                 | Memory write to  0FE <- 21\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:C1          MREQ RD                    | Memory read from 005 -> C1\n#053H T8  AB:0FF DB:27          MREQ    WR                 | Memory write to  0FF <- 27\n#056H T11 AB:0FE DB:25          MREQ    WR                 | Memory write to  0FE <- 25\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:C2          MREQ RD                    | Memory read from 005 -> C2\n#053H T8  AB:0FF DB:28          MREQ    WR                 | Memory write to  0FF <- 28\n#056H T11 AB:0FE DB:2D          MREQ    WR                 | Memory write to  0FE <- 2D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:C3          MREQ RD                    | Memory read from 005 -> C3\n#053H T8  AB:0FF DB:29          MREQ    WR                 | Memory write to  0FF <- 29\n#056H T11 AB:0FE DB:29          MREQ    WR                 | Memory write to  0FE <- 29\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:C4          MREQ RD                    | Memory read from 005 -> C4\n#053H T8  AB:0FF DB:2A          MREQ    WR                 | Memory write to  0FF <- 2A\n#056H T11 AB:0FE DB:29          MREQ    WR                 | Memory write to  0FE <- 29\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:C5          MREQ RD                    | Memory read from 005 -> C5\n#053H T8  AB:0FF DB:2B          MREQ    WR                 | Memory write to  0FF <- 2B\n#056H T11 AB:0FE DB:2D          MREQ    WR                 | Memory write to  0FE <- 2D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:C6          MREQ RD                    | Memory read from 005 -> C6\n#053H T8  AB:0FF DB:2C          MREQ    WR                 | Memory write to  0FF <- 2C\n#056H T11 AB:0FE DB:29          MREQ    WR                 | Memory write to  0FE <- 29\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:C7          MREQ RD                    | Memory read from 005 -> C7\n#053H T8  AB:0FF DB:2D          MREQ    WR                 | Memory write to  0FF <- 2D\n#056H T11 AB:0FE DB:2D          MREQ    WR                 | Memory write to  0FE <- 2D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:C8          MREQ RD                    | Memory read from 005 -> C8\n#053H T8  AB:0FF DB:2E          MREQ    WR                 | Memory write to  0FF <- 2E\n#056H T11 AB:0FE DB:2D          MREQ    WR                 | Memory write to  0FE <- 2D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:C9          MREQ RD                    | Memory read from 005 -> C9\n#053H T8  AB:0FF DB:2F          MREQ    WR                 | Memory write to  0FF <- 2F\n#056H T11 AB:0FE DB:29          MREQ    WR                 | Memory write to  0FE <- 29\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:CA          MREQ RD                    | Memory read from 005 -> CA\n#053H T8  AB:0FF DB:30          MREQ    WR                 | Memory write to  0FF <- 30\n#056H T11 AB:0FE DB:35          MREQ    WR                 | Memory write to  0FE <- 35\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:CB          MREQ RD                    | Memory read from 005 -> CB\n#053H T8  AB:0FF DB:31          MREQ    WR                 | Memory write to  0FF <- 31\n#056H T11 AB:0FE DB:31          MREQ    WR                 | Memory write to  0FE <- 31\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:CC          MREQ RD                    | Memory read from 005 -> CC\n#053H T8  AB:0FF DB:32          MREQ    WR                 | Memory write to  0FF <- 32\n#056H T11 AB:0FE DB:31          MREQ    WR                 | Memory write to  0FE <- 31\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:CD          MREQ RD                    | Memory read from 005 -> CD\n#053H T8  AB:0FF DB:33          MREQ    WR                 | Memory write to  0FF <- 33\n#056H T11 AB:0FE DB:35          MREQ    WR                 | Memory write to  0FE <- 35\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:CE          MREQ RD                    | Memory read from 005 -> CE\n#053H T8  AB:0FF DB:34          MREQ    WR                 | Memory write to  0FF <- 34\n#056H T11 AB:0FE DB:31          MREQ    WR                 | Memory write to  0FE <- 31\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:CF          MREQ RD                    | Memory read from 005 -> CF\n#053H T8  AB:0FF DB:35          MREQ    WR                 | Memory write to  0FF <- 35\n#056H T11 AB:0FE DB:35          MREQ    WR                 | Memory write to  0FE <- 35\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:D0          MREQ RD                    | Memory read from 005 -> D0\n#053H T8  AB:0FF DB:36          MREQ    WR                 | Memory write to  0FF <- 36\n#056H T11 AB:0FE DB:25          MREQ    WR                 | Memory write to  0FE <- 25\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:D1          MREQ RD                    | Memory read from 005 -> D1\n#053H T8  AB:0FF DB:37          MREQ    WR                 | Memory write to  0FF <- 37\n#056H T11 AB:0FE DB:21          MREQ    WR                 | Memory write to  0FE <- 21\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:D2          MREQ RD                    | Memory read from 005 -> D2\n#053H T8  AB:0FF DB:38          MREQ    WR                 | Memory write to  0FF <- 38\n#056H T11 AB:0FE DB:29          MREQ    WR                 | Memory write to  0FE <- 29\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:D3          MREQ RD                    | Memory read from 005 -> D3\n#053H T8  AB:0FF DB:39          MREQ    WR                 | Memory write to  0FF <- 39\n#056H T11 AB:0FE DB:2D          MREQ    WR                 | Memory write to  0FE <- 2D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:D4          MREQ RD                    | Memory read from 005 -> D4\n#053H T8  AB:0FF DB:3A          MREQ    WR                 | Memory write to  0FF <- 3A\n#056H T11 AB:0FE DB:2D          MREQ    WR                 | Memory write to  0FE <- 2D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:D5          MREQ RD                    | Memory read from 005 -> D5\n#053H T8  AB:0FF DB:3B          MREQ    WR                 | Memory write to  0FF <- 3B\n#056H T11 AB:0FE DB:29          MREQ    WR                 | Memory write to  0FE <- 29\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:D6          MREQ RD                    | Memory read from 005 -> D6\n#053H T8  AB:0FF DB:3C          MREQ    WR                 | Memory write to  0FF <- 3C\n#056H T11 AB:0FE DB:2D          MREQ    WR                 | Memory write to  0FE <- 2D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:D7          MREQ RD                    | Memory read from 005 -> D7\n#053H T8  AB:0FF DB:3D          MREQ    WR                 | Memory write to  0FF <- 3D\n#056H T11 AB:0FE DB:29          MREQ    WR                 | Memory write to  0FE <- 29\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:D8          MREQ RD                    | Memory read from 005 -> D8\n#053H T8  AB:0FF DB:3E          MREQ    WR                 | Memory write to  0FF <- 3E\n#056H T11 AB:0FE DB:29          MREQ    WR                 | Memory write to  0FE <- 29\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:D9          MREQ RD                    | Memory read from 005 -> D9\n#053H T8  AB:0FF DB:3F          MREQ    WR                 | Memory write to  0FF <- 3F\n#056H T11 AB:0FE DB:2D          MREQ    WR                 | Memory write to  0FE <- 2D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:DA          MREQ RD                    | Memory read from 005 -> DA\n#053H T8  AB:0FF DB:40          MREQ    WR                 | Memory write to  0FF <- 40\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:DB          MREQ RD                    | Memory read from 005 -> DB\n#053H T8  AB:0FF DB:41          MREQ    WR                 | Memory write to  0FF <- 41\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:DC          MREQ RD                    | Memory read from 005 -> DC\n#053H T8  AB:0FF DB:42          MREQ    WR                 | Memory write to  0FF <- 42\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:DD          MREQ RD                    | Memory read from 005 -> DD\n#053H T8  AB:0FF DB:43          MREQ    WR                 | Memory write to  0FF <- 43\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:DE          MREQ RD                    | Memory read from 005 -> DE\n#053H T8  AB:0FF DB:44          MREQ    WR                 | Memory write to  0FF <- 44\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:DF          MREQ RD                    | Memory read from 005 -> DF\n#053H T8  AB:0FF DB:45          MREQ    WR                 | Memory write to  0FF <- 45\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:E0          MREQ RD                    | Memory read from 005 -> E0\n#053H T8  AB:0FF DB:46          MREQ    WR                 | Memory write to  0FF <- 46\n#056H T11 AB:0FE DB:01          MREQ    WR                 | Memory write to  0FE <- 01\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:E1          MREQ RD                    | Memory read from 005 -> E1\n#053H T8  AB:0FF DB:47          MREQ    WR                 | Memory write to  0FF <- 47\n#056H T11 AB:0FE DB:05          MREQ    WR                 | Memory write to  0FE <- 05\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:E2          MREQ RD                    | Memory read from 005 -> E2\n#053H T8  AB:0FF DB:48          MREQ    WR                 | Memory write to  0FF <- 48\n#056H T11 AB:0FE DB:0D          MREQ    WR                 | Memory write to  0FE <- 0D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:E3          MREQ RD                    | Memory read from 005 -> E3\n#053H T8  AB:0FF DB:49          MREQ    WR                 | Memory write to  0FF <- 49\n#056H T11 AB:0FE DB:09          MREQ    WR                 | Memory write to  0FE <- 09\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:E4          MREQ RD                    | Memory read from 005 -> E4\n#053H T8  AB:0FF DB:4A          MREQ    WR                 | Memory write to  0FF <- 4A\n#056H T11 AB:0FE DB:09          MREQ    WR                 | Memory write to  0FE <- 09\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:E5          MREQ RD                    | Memory read from 005 -> E5\n#053H T8  AB:0FF DB:4B          MREQ    WR                 | Memory write to  0FF <- 4B\n#056H T11 AB:0FE DB:0D          MREQ    WR                 | Memory write to  0FE <- 0D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:E6          MREQ RD                    | Memory read from 005 -> E6\n#053H T8  AB:0FF DB:4C          MREQ    WR                 | Memory write to  0FF <- 4C\n#056H T11 AB:0FE DB:09          MREQ    WR                 | Memory write to  0FE <- 09\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:E7          MREQ RD                    | Memory read from 005 -> E7\n#053H T8  AB:0FF DB:4D          MREQ    WR                 | Memory write to  0FF <- 4D\n#056H T11 AB:0FE DB:0D          MREQ    WR                 | Memory write to  0FE <- 0D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:E8          MREQ RD                    | Memory read from 005 -> E8\n#053H T8  AB:0FF DB:4E          MREQ    WR                 | Memory write to  0FF <- 4E\n#056H T11 AB:0FE DB:0D          MREQ    WR                 | Memory write to  0FE <- 0D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:E9          MREQ RD                    | Memory read from 005 -> E9\n#053H T8  AB:0FF DB:4F          MREQ    WR                 | Memory write to  0FF <- 4F\n#056H T11 AB:0FE DB:09          MREQ    WR                 | Memory write to  0FE <- 09\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:EA          MREQ RD                    | Memory read from 005 -> EA\n#053H T8  AB:0FF DB:50          MREQ    WR                 | Memory write to  0FF <- 50\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:EB          MREQ RD                    | Memory read from 005 -> EB\n#053H T8  AB:0FF DB:51          MREQ    WR                 | Memory write to  0FF <- 51\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:EC          MREQ RD                    | Memory read from 005 -> EC\n#053H T8  AB:0FF DB:52          MREQ    WR                 | Memory write to  0FF <- 52\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:ED          MREQ RD                    | Memory read from 005 -> ED\n#053H T8  AB:0FF DB:53          MREQ    WR                 | Memory write to  0FF <- 53\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:EE          MREQ RD                    | Memory read from 005 -> EE\n#053H T8  AB:0FF DB:54          MREQ    WR                 | Memory write to  0FF <- 54\n#056H T11 AB:0FE DB:11          MREQ    WR                 | Memory write to  0FE <- 11\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:EF          MREQ RD                    | Memory read from 005 -> EF\n#053H T8  AB:0FF DB:55          MREQ    WR                 | Memory write to  0FF <- 55\n#056H T11 AB:0FE DB:15          MREQ    WR                 | Memory write to  0FE <- 15\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:F0          MREQ RD                    | Memory read from 005 -> F0\n#053H T8  AB:0FF DB:56          MREQ    WR                 | Memory write to  0FF <- 56\n#056H T11 AB:0FE DB:05          MREQ    WR                 | Memory write to  0FE <- 05\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:F1          MREQ RD                    | Memory read from 005 -> F1\n#053H T8  AB:0FF DB:57          MREQ    WR                 | Memory write to  0FF <- 57\n#056H T11 AB:0FE DB:01          MREQ    WR                 | Memory write to  0FE <- 01\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:F2          MREQ RD                    | Memory read from 005 -> F2\n#053H T8  AB:0FF DB:58          MREQ    WR                 | Memory write to  0FF <- 58\n#056H T11 AB:0FE DB:09          MREQ    WR                 | Memory write to  0FE <- 09\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:F3          MREQ RD                    | Memory read from 005 -> F3\n#053H T8  AB:0FF DB:59          MREQ    WR                 | Memory write to  0FF <- 59\n#056H T11 AB:0FE DB:0D          MREQ    WR                 | Memory write to  0FE <- 0D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:F4          MREQ RD                    | Memory read from 005 -> F4\n#053H T8  AB:0FF DB:5A          MREQ    WR                 | Memory write to  0FF <- 5A\n#056H T11 AB:0FE DB:0D          MREQ    WR                 | Memory write to  0FE <- 0D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:F5          MREQ RD                    | Memory read from 005 -> F5\n#053H T8  AB:0FF DB:5B          MREQ    WR                 | Memory write to  0FF <- 5B\n#056H T11 AB:0FE DB:09          MREQ    WR                 | Memory write to  0FE <- 09\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:F6          MREQ RD                    | Memory read from 005 -> F6\n#053H T8  AB:0FF DB:5C          MREQ    WR                 | Memory write to  0FF <- 5C\n#056H T11 AB:0FE DB:0D          MREQ    WR                 | Memory write to  0FE <- 0D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:F7          MREQ RD                    | Memory read from 005 -> F7\n#053H T8  AB:0FF DB:5D          MREQ    WR                 | Memory write to  0FF <- 5D\n#056H T11 AB:0FE DB:09          MREQ    WR                 | Memory write to  0FE <- 09\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:F8          MREQ RD                    | Memory read from 005 -> F8\n#053H T8  AB:0FF DB:5E          MREQ    WR                 | Memory write to  0FF <- 5E\n#056H T11 AB:0FE DB:09          MREQ    WR                 | Memory write to  0FE <- 09\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:F9          MREQ RD                    | Memory read from 005 -> F9\n#053H T8  AB:0FF DB:5F          MREQ    WR                 | Memory write to  0FF <- 5F\n#056H T11 AB:0FE DB:0D          MREQ    WR                 | Memory write to  0FE <- 0D\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:FA          MREQ RD                    | Memory read from 005 -> FA\n#053H T8  AB:0FF DB:60          MREQ    WR                 | Memory write to  0FF <- 60\n#056H T11 AB:0FE DB:35          MREQ    WR                 | Memory write to  0FE <- 35\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:FB          MREQ RD                    | Memory read from 005 -> FB\n#053H T8  AB:0FF DB:61          MREQ    WR                 | Memory write to  0FF <- 61\n#056H T11 AB:0FE DB:31          MREQ    WR                 | Memory write to  0FE <- 31\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:FC          MREQ RD                    | Memory read from 005 -> FC\n#053H T8  AB:0FF DB:62          MREQ    WR                 | Memory write to  0FF <- 62\n#056H T11 AB:0FE DB:31          MREQ    WR                 | Memory write to  0FE <- 31\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:FD          MREQ RD                    | Memory read from 005 -> FD\n#053H T8  AB:0FF DB:63          MREQ    WR                 | Memory write to  0FF <- 63\n#056H T11 AB:0FE DB:35          MREQ    WR                 | Memory write to  0FE <- 35\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:FE          MREQ RD                    | Memory read from 005 -> FE\n#053H T8  AB:0FF DB:64          MREQ    WR                 | Memory write to  0FF <- 64\n#056H T11 AB:0FE DB:31          MREQ    WR                 | Memory write to  0FE <- 31\n#017H T7  AB:004 DB:11          MREQ RD                    | Memory read from 004 -> 11\n#020H T10 AB:005 DB:FF          MREQ RD                    | Memory read from 005 -> FF\n#053H T8  AB:0FF DB:65          MREQ    WR                 | Memory write to  0FF <- 65\n#056H T11 AB:0FE DB:35          MREQ    WR                 | Memory write to  0FE <- 35\n"
  },
  {
    "path": "tools/dongle/daa/daa_s-00.out",
    "content": "#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:00          MREQ RD                    | Memory read from 005 -> 00\n#053H T8  AB:0FF DB:00          MREQ    WR                 | Memory write to  0FF <- 00\n#056H T11 AB:0FE DB:46          MREQ    WR                 | Memory write to  0FE <- 46\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:01          MREQ RD                    | Memory read from 005 -> 01\n#053H T8  AB:0FF DB:01          MREQ    WR                 | Memory write to  0FF <- 01\n#056H T11 AB:0FE DB:02          MREQ    WR                 | Memory write to  0FE <- 02\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:02          MREQ RD                    | Memory read from 005 -> 02\n#053H T8  AB:0FF DB:02          MREQ    WR                 | Memory write to  0FF <- 02\n#056H T11 AB:0FE DB:02          MREQ    WR                 | Memory write to  0FE <- 02\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:03          MREQ RD                    | Memory read from 005 -> 03\n#053H T8  AB:0FF DB:03          MREQ    WR                 | Memory write to  0FF <- 03\n#056H T11 AB:0FE DB:06          MREQ    WR                 | Memory write to  0FE <- 06\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:04          MREQ RD                    | Memory read from 005 -> 04\n#053H T8  AB:0FF DB:04          MREQ    WR                 | Memory write to  0FF <- 04\n#056H T11 AB:0FE DB:02          MREQ    WR                 | Memory write to  0FE <- 02\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:05          MREQ RD                    | Memory read from 005 -> 05\n#053H T8  AB:0FF DB:05          MREQ    WR                 | Memory write to  0FF <- 05\n#056H T11 AB:0FE DB:06          MREQ    WR                 | Memory write to  0FE <- 06\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:06          MREQ RD                    | Memory read from 005 -> 06\n#053H T8  AB:0FF DB:06          MREQ    WR                 | Memory write to  0FF <- 06\n#056H T11 AB:0FE DB:06          MREQ    WR                 | Memory write to  0FE <- 06\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:07          MREQ RD                    | Memory read from 005 -> 07\n#053H T8  AB:0FF DB:07          MREQ    WR                 | Memory write to  0FF <- 07\n#056H T11 AB:0FE DB:02          MREQ    WR                 | Memory write to  0FE <- 02\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:08          MREQ RD                    | Memory read from 005 -> 08\n#053H T8  AB:0FF DB:08          MREQ    WR                 | Memory write to  0FF <- 08\n#056H T11 AB:0FE DB:0A          MREQ    WR                 | Memory write to  0FE <- 0A\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:09          MREQ RD                    | Memory read from 005 -> 09\n#053H T8  AB:0FF DB:09          MREQ    WR                 | Memory write to  0FF <- 09\n#056H T11 AB:0FE DB:0E          MREQ    WR                 | Memory write to  0FE <- 0E\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:0A          MREQ RD                    | Memory read from 005 -> 0A\n#053H T8  AB:0FF DB:04          MREQ    WR                 | Memory write to  0FF <- 04\n#056H T11 AB:0FE DB:02          MREQ    WR                 | Memory write to  0FE <- 02\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:0B          MREQ RD                    | Memory read from 005 -> 0B\n#053H T8  AB:0FF DB:05          MREQ    WR                 | Memory write to  0FF <- 05\n#056H T11 AB:0FE DB:06          MREQ    WR                 | Memory write to  0FE <- 06\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:0C          MREQ RD                    | Memory read from 005 -> 0C\n#053H T8  AB:0FF DB:06          MREQ    WR                 | Memory write to  0FF <- 06\n#056H T11 AB:0FE DB:06          MREQ    WR                 | Memory write to  0FE <- 06\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:0D          MREQ RD                    | Memory read from 005 -> 0D\n#053H T8  AB:0FF DB:07          MREQ    WR                 | Memory write to  0FF <- 07\n#056H T11 AB:0FE DB:02          MREQ    WR                 | Memory write to  0FE <- 02\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:0E          MREQ RD                    | Memory read from 005 -> 0E\n#053H T8  AB:0FF DB:08          MREQ    WR                 | Memory write to  0FF <- 08\n#056H T11 AB:0FE DB:0A          MREQ    WR                 | Memory write to  0FE <- 0A\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:0F          MREQ RD                    | Memory read from 005 -> 0F\n#053H T8  AB:0FF DB:09          MREQ    WR                 | Memory write to  0FF <- 09\n#056H T11 AB:0FE DB:0E          MREQ    WR                 | Memory write to  0FE <- 0E\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:10          MREQ RD                    | Memory read from 005 -> 10\n#053H T8  AB:0FF DB:10          MREQ    WR                 | Memory write to  0FF <- 10\n#056H T11 AB:0FE DB:02          MREQ    WR                 | Memory write to  0FE <- 02\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:11          MREQ RD                    | Memory read from 005 -> 11\n#053H T8  AB:0FF DB:11          MREQ    WR                 | Memory write to  0FF <- 11\n#056H T11 AB:0FE DB:06          MREQ    WR                 | Memory write to  0FE <- 06\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:12          MREQ RD                    | Memory read from 005 -> 12\n#053H T8  AB:0FF DB:12          MREQ    WR                 | Memory write to  0FF <- 12\n#056H T11 AB:0FE DB:06          MREQ    WR                 | Memory write to  0FE <- 06\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:13          MREQ RD                    | Memory read from 005 -> 13\n#053H T8  AB:0FF DB:13          MREQ    WR                 | Memory write to  0FF <- 13\n#056H T11 AB:0FE DB:02          MREQ    WR                 | Memory write to  0FE <- 02\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:14          MREQ RD                    | Memory read from 005 -> 14\n#053H T8  AB:0FF DB:14          MREQ    WR                 | Memory write to  0FF <- 14\n#056H T11 AB:0FE DB:06          MREQ    WR                 | Memory write to  0FE <- 06\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:15          MREQ RD                    | Memory read from 005 -> 15\n#053H T8  AB:0FF DB:15          MREQ    WR                 | Memory write to  0FF <- 15\n#056H T11 AB:0FE DB:02          MREQ    WR                 | Memory write to  0FE <- 02\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:16          MREQ RD                    | Memory read from 005 -> 16\n#053H T8  AB:0FF DB:16          MREQ    WR                 | Memory write to  0FF <- 16\n#056H T11 AB:0FE DB:02          MREQ    WR                 | Memory write to  0FE <- 02\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:17          MREQ RD                    | Memory read from 005 -> 17\n#053H T8  AB:0FF DB:17          MREQ    WR                 | Memory write to  0FF <- 17\n#056H T11 AB:0FE DB:06          MREQ    WR                 | Memory write to  0FE <- 06\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:18          MREQ RD                    | Memory read from 005 -> 18\n#053H T8  AB:0FF DB:18          MREQ    WR                 | Memory write to  0FF <- 18\n#056H T11 AB:0FE DB:0E          MREQ    WR                 | Memory write to  0FE <- 0E\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:19          MREQ RD                    | Memory read from 005 -> 19\n#053H T8  AB:0FF DB:19          MREQ    WR                 | Memory write to  0FF <- 19\n#056H T11 AB:0FE DB:0A          MREQ    WR                 | Memory write to  0FE <- 0A\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:1A          MREQ RD                    | Memory read from 005 -> 1A\n#053H T8  AB:0FF DB:14          MREQ    WR                 | Memory write to  0FF <- 14\n#056H T11 AB:0FE DB:06          MREQ    WR                 | Memory write to  0FE <- 06\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:1B          MREQ RD                    | Memory read from 005 -> 1B\n#053H T8  AB:0FF DB:15          MREQ    WR                 | Memory write to  0FF <- 15\n#056H T11 AB:0FE DB:02          MREQ    WR                 | Memory write to  0FE <- 02\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:1C          MREQ RD                    | Memory read from 005 -> 1C\n#053H T8  AB:0FF DB:16          MREQ    WR                 | Memory write to  0FF <- 16\n#056H T11 AB:0FE DB:02          MREQ    WR                 | Memory write to  0FE <- 02\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:1D          MREQ RD                    | Memory read from 005 -> 1D\n#053H T8  AB:0FF DB:17          MREQ    WR                 | Memory write to  0FF <- 17\n#056H T11 AB:0FE DB:06          MREQ    WR                 | Memory write to  0FE <- 06\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:1E          MREQ RD                    | Memory read from 005 -> 1E\n#053H T8  AB:0FF DB:18          MREQ    WR                 | Memory write to  0FF <- 18\n#056H T11 AB:0FE DB:0E          MREQ    WR                 | Memory write to  0FE <- 0E\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:1F          MREQ RD                    | Memory read from 005 -> 1F\n#053H T8  AB:0FF DB:19          MREQ    WR                 | Memory write to  0FF <- 19\n#056H T11 AB:0FE DB:0A          MREQ    WR                 | Memory write to  0FE <- 0A\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:20          MREQ RD                    | Memory read from 005 -> 20\n#053H T8  AB:0FF DB:20          MREQ    WR                 | Memory write to  0FF <- 20\n#056H T11 AB:0FE DB:22          MREQ    WR                 | Memory write to  0FE <- 22\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:21          MREQ RD                    | Memory read from 005 -> 21\n#053H T8  AB:0FF DB:21          MREQ    WR                 | Memory write to  0FF <- 21\n#056H T11 AB:0FE DB:26          MREQ    WR                 | Memory write to  0FE <- 26\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:22          MREQ RD                    | Memory read from 005 -> 22\n#053H T8  AB:0FF DB:22          MREQ    WR                 | Memory write to  0FF <- 22\n#056H T11 AB:0FE DB:26          MREQ    WR                 | Memory write to  0FE <- 26\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:23          MREQ RD                    | Memory read from 005 -> 23\n#053H T8  AB:0FF DB:23          MREQ    WR                 | Memory write to  0FF <- 23\n#056H T11 AB:0FE DB:22          MREQ    WR                 | Memory write to  0FE <- 22\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:24          MREQ RD                    | Memory read from 005 -> 24\n#053H T8  AB:0FF DB:24          MREQ    WR                 | Memory write to  0FF <- 24\n#056H T11 AB:0FE DB:26          MREQ    WR                 | Memory write to  0FE <- 26\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:25          MREQ RD                    | Memory read from 005 -> 25\n#053H T8  AB:0FF DB:25          MREQ    WR                 | Memory write to  0FF <- 25\n#056H T11 AB:0FE DB:22          MREQ    WR                 | Memory write to  0FE <- 22\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:26          MREQ RD                    | Memory read from 005 -> 26\n#053H T8  AB:0FF DB:26          MREQ    WR                 | Memory write to  0FF <- 26\n#056H T11 AB:0FE DB:22          MREQ    WR                 | Memory write to  0FE <- 22\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:27          MREQ RD                    | Memory read from 005 -> 27\n#053H T8  AB:0FF DB:27          MREQ    WR                 | Memory write to  0FF <- 27\n#056H T11 AB:0FE DB:26          MREQ    WR                 | Memory write to  0FE <- 26\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:28          MREQ RD                    | Memory read from 005 -> 28\n#053H T8  AB:0FF DB:28          MREQ    WR                 | Memory write to  0FF <- 28\n#056H T11 AB:0FE DB:2E          MREQ    WR                 | Memory write to  0FE <- 2E\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:29          MREQ RD                    | Memory read from 005 -> 29\n#053H T8  AB:0FF DB:29          MREQ    WR                 | Memory write to  0FF <- 29\n#056H T11 AB:0FE DB:2A          MREQ    WR                 | Memory write to  0FE <- 2A\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:2A          MREQ RD                    | Memory read from 005 -> 2A\n#053H T8  AB:0FF DB:24          MREQ    WR                 | Memory write to  0FF <- 24\n#056H T11 AB:0FE DB:26          MREQ    WR                 | Memory write to  0FE <- 26\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:2B          MREQ RD                    | Memory read from 005 -> 2B\n#053H T8  AB:0FF DB:25          MREQ    WR                 | Memory write to  0FF <- 25\n#056H T11 AB:0FE DB:22          MREQ    WR                 | Memory write to  0FE <- 22\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:2C          MREQ RD                    | Memory read from 005 -> 2C\n#053H T8  AB:0FF DB:26          MREQ    WR                 | Memory write to  0FF <- 26\n#056H T11 AB:0FE DB:22          MREQ    WR                 | Memory write to  0FE <- 22\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:2D          MREQ RD                    | Memory read from 005 -> 2D\n#053H T8  AB:0FF DB:27          MREQ    WR                 | Memory write to  0FF <- 27\n#056H T11 AB:0FE DB:26          MREQ    WR                 | Memory write to  0FE <- 26\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:2E          MREQ RD                    | Memory read from 005 -> 2E\n#053H T8  AB:0FF DB:28          MREQ    WR                 | Memory write to  0FF <- 28\n#056H T11 AB:0FE DB:2E          MREQ    WR                 | Memory write to  0FE <- 2E\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:2F          MREQ RD                    | Memory read from 005 -> 2F\n#053H T8  AB:0FF DB:29          MREQ    WR                 | Memory write to  0FF <- 29\n#056H T11 AB:0FE DB:2A          MREQ    WR                 | Memory write to  0FE <- 2A\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:30          MREQ RD                    | Memory read from 005 -> 30\n#053H T8  AB:0FF DB:30          MREQ    WR                 | Memory write to  0FF <- 30\n#056H T11 AB:0FE DB:26          MREQ    WR                 | Memory write to  0FE <- 26\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:31          MREQ RD                    | Memory read from 005 -> 31\n#053H T8  AB:0FF DB:31          MREQ    WR                 | Memory write to  0FF <- 31\n#056H T11 AB:0FE DB:22          MREQ    WR                 | Memory write to  0FE <- 22\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:32          MREQ RD                    | Memory read from 005 -> 32\n#053H T8  AB:0FF DB:32          MREQ    WR                 | Memory write to  0FF <- 32\n#056H T11 AB:0FE DB:22          MREQ    WR                 | Memory write to  0FE <- 22\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:33          MREQ RD                    | Memory read from 005 -> 33\n#053H T8  AB:0FF DB:33          MREQ    WR                 | Memory write to  0FF <- 33\n#056H T11 AB:0FE DB:26          MREQ    WR                 | Memory write to  0FE <- 26\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:34          MREQ RD                    | Memory read from 005 -> 34\n#053H T8  AB:0FF DB:34          MREQ    WR                 | Memory write to  0FF <- 34\n#056H T11 AB:0FE DB:22          MREQ    WR                 | Memory write to  0FE <- 22\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:35          MREQ RD                    | Memory read from 005 -> 35\n#053H T8  AB:0FF DB:35          MREQ    WR                 | Memory write to  0FF <- 35\n#056H T11 AB:0FE DB:26          MREQ    WR                 | Memory write to  0FE <- 26\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:36          MREQ RD                    | Memory read from 005 -> 36\n#053H T8  AB:0FF DB:36          MREQ    WR                 | Memory write to  0FF <- 36\n#056H T11 AB:0FE DB:26          MREQ    WR                 | Memory write to  0FE <- 26\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:37          MREQ RD                    | Memory read from 005 -> 37\n#053H T8  AB:0FF DB:37          MREQ    WR                 | Memory write to  0FF <- 37\n#056H T11 AB:0FE DB:22          MREQ    WR                 | Memory write to  0FE <- 22\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:38          MREQ RD                    | Memory read from 005 -> 38\n#053H T8  AB:0FF DB:38          MREQ    WR                 | Memory write to  0FF <- 38\n#056H T11 AB:0FE DB:2A          MREQ    WR                 | Memory write to  0FE <- 2A\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:39          MREQ RD                    | Memory read from 005 -> 39\n#053H T8  AB:0FF DB:39          MREQ    WR                 | Memory write to  0FF <- 39\n#056H T11 AB:0FE DB:2E          MREQ    WR                 | Memory write to  0FE <- 2E\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:3A          MREQ RD                    | Memory read from 005 -> 3A\n#053H T8  AB:0FF DB:34          MREQ    WR                 | Memory write to  0FF <- 34\n#056H T11 AB:0FE DB:22          MREQ    WR                 | Memory write to  0FE <- 22\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:3B          MREQ RD                    | Memory read from 005 -> 3B\n#053H T8  AB:0FF DB:35          MREQ    WR                 | Memory write to  0FF <- 35\n#056H T11 AB:0FE DB:26          MREQ    WR                 | Memory write to  0FE <- 26\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:3C          MREQ RD                    | Memory read from 005 -> 3C\n#053H T8  AB:0FF DB:36          MREQ    WR                 | Memory write to  0FF <- 36\n#056H T11 AB:0FE DB:26          MREQ    WR                 | Memory write to  0FE <- 26\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:3D          MREQ RD                    | Memory read from 005 -> 3D\n#053H T8  AB:0FF DB:37          MREQ    WR                 | Memory write to  0FF <- 37\n#056H T11 AB:0FE DB:22          MREQ    WR                 | Memory write to  0FE <- 22\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:3E          MREQ RD                    | Memory read from 005 -> 3E\n#053H T8  AB:0FF DB:38          MREQ    WR                 | Memory write to  0FF <- 38\n#056H T11 AB:0FE DB:2A          MREQ    WR                 | Memory write to  0FE <- 2A\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:3F          MREQ RD                    | Memory read from 005 -> 3F\n#053H T8  AB:0FF DB:39          MREQ    WR                 | Memory write to  0FF <- 39\n#056H T11 AB:0FE DB:2E          MREQ    WR                 | Memory write to  0FE <- 2E\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:40          MREQ RD                    | Memory read from 005 -> 40\n#053H T8  AB:0FF DB:40          MREQ    WR                 | Memory write to  0FF <- 40\n#056H T11 AB:0FE DB:02          MREQ    WR                 | Memory write to  0FE <- 02\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:41          MREQ RD                    | Memory read from 005 -> 41\n#053H T8  AB:0FF DB:41          MREQ    WR                 | Memory write to  0FF <- 41\n#056H T11 AB:0FE DB:06          MREQ    WR                 | Memory write to  0FE <- 06\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:42          MREQ RD                    | Memory read from 005 -> 42\n#053H T8  AB:0FF DB:42          MREQ    WR                 | Memory write to  0FF <- 42\n#056H T11 AB:0FE DB:06          MREQ    WR                 | Memory write to  0FE <- 06\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:43          MREQ RD                    | Memory read from 005 -> 43\n#053H T8  AB:0FF DB:43          MREQ    WR                 | Memory write to  0FF <- 43\n#056H T11 AB:0FE DB:02          MREQ    WR                 | Memory write to  0FE <- 02\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:44          MREQ RD                    | Memory read from 005 -> 44\n#053H T8  AB:0FF DB:44          MREQ    WR                 | Memory write to  0FF <- 44\n#056H T11 AB:0FE DB:06          MREQ    WR                 | Memory write to  0FE <- 06\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:45          MREQ RD                    | Memory read from 005 -> 45\n#053H T8  AB:0FF DB:45          MREQ    WR                 | Memory write to  0FF <- 45\n#056H T11 AB:0FE DB:02          MREQ    WR                 | Memory write to  0FE <- 02\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:46          MREQ RD                    | Memory read from 005 -> 46\n#053H T8  AB:0FF DB:46          MREQ    WR                 | Memory write to  0FF <- 46\n#056H T11 AB:0FE DB:02          MREQ    WR                 | Memory write to  0FE <- 02\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:47          MREQ RD                    | Memory read from 005 -> 47\n#053H T8  AB:0FF DB:47          MREQ    WR                 | Memory write to  0FF <- 47\n#056H T11 AB:0FE DB:06          MREQ    WR                 | Memory write to  0FE <- 06\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:48          MREQ RD                    | Memory read from 005 -> 48\n#053H T8  AB:0FF DB:48          MREQ    WR                 | Memory write to  0FF <- 48\n#056H T11 AB:0FE DB:0E          MREQ    WR                 | Memory write to  0FE <- 0E\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:49          MREQ RD                    | Memory read from 005 -> 49\n#053H T8  AB:0FF DB:49          MREQ    WR                 | Memory write to  0FF <- 49\n#056H T11 AB:0FE DB:0A          MREQ    WR                 | Memory write to  0FE <- 0A\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:4A          MREQ RD                    | Memory read from 005 -> 4A\n#053H T8  AB:0FF DB:44          MREQ    WR                 | Memory write to  0FF <- 44\n#056H T11 AB:0FE DB:06          MREQ    WR                 | Memory write to  0FE <- 06\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:4B          MREQ RD                    | Memory read from 005 -> 4B\n#053H T8  AB:0FF DB:45          MREQ    WR                 | Memory write to  0FF <- 45\n#056H T11 AB:0FE DB:02          MREQ    WR                 | Memory write to  0FE <- 02\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:4C          MREQ RD                    | Memory read from 005 -> 4C\n#053H T8  AB:0FF DB:46          MREQ    WR                 | Memory write to  0FF <- 46\n#056H T11 AB:0FE DB:02          MREQ    WR                 | Memory write to  0FE <- 02\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:4D          MREQ RD                    | Memory read from 005 -> 4D\n#053H T8  AB:0FF DB:47          MREQ    WR                 | Memory write to  0FF <- 47\n#056H T11 AB:0FE DB:06          MREQ    WR                 | Memory write to  0FE <- 06\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:4E          MREQ RD                    | Memory read from 005 -> 4E\n#053H T8  AB:0FF DB:48          MREQ    WR                 | Memory write to  0FF <- 48\n#056H T11 AB:0FE DB:0E          MREQ    WR                 | Memory write to  0FE <- 0E\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:4F          MREQ RD                    | Memory read from 005 -> 4F\n#053H T8  AB:0FF DB:49          MREQ    WR                 | Memory write to  0FF <- 49\n#056H T11 AB:0FE DB:0A          MREQ    WR                 | Memory write to  0FE <- 0A\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:50          MREQ RD                    | Memory read from 005 -> 50\n#053H T8  AB:0FF DB:50          MREQ    WR                 | Memory write to  0FF <- 50\n#056H T11 AB:0FE DB:06          MREQ    WR                 | Memory write to  0FE <- 06\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:51          MREQ RD                    | Memory read from 005 -> 51\n#053H T8  AB:0FF DB:51          MREQ    WR                 | Memory write to  0FF <- 51\n#056H T11 AB:0FE DB:02          MREQ    WR                 | Memory write to  0FE <- 02\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:52          MREQ RD                    | Memory read from 005 -> 52\n#053H T8  AB:0FF DB:52          MREQ    WR                 | Memory write to  0FF <- 52\n#056H T11 AB:0FE DB:02          MREQ    WR                 | Memory write to  0FE <- 02\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:53          MREQ RD                    | Memory read from 005 -> 53\n#053H T8  AB:0FF DB:53          MREQ    WR                 | Memory write to  0FF <- 53\n#056H T11 AB:0FE DB:06          MREQ    WR                 | Memory write to  0FE <- 06\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:54          MREQ RD                    | Memory read from 005 -> 54\n#053H T8  AB:0FF DB:54          MREQ    WR                 | Memory write to  0FF <- 54\n#056H T11 AB:0FE DB:02          MREQ    WR                 | Memory write to  0FE <- 02\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:55          MREQ RD                    | Memory read from 005 -> 55\n#053H T8  AB:0FF DB:55          MREQ    WR                 | Memory write to  0FF <- 55\n#056H T11 AB:0FE DB:06          MREQ    WR                 | Memory write to  0FE <- 06\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:56          MREQ RD                    | Memory read from 005 -> 56\n#053H T8  AB:0FF DB:56          MREQ    WR                 | Memory write to  0FF <- 56\n#056H T11 AB:0FE DB:06          MREQ    WR                 | Memory write to  0FE <- 06\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:57          MREQ RD                    | Memory read from 005 -> 57\n#053H T8  AB:0FF DB:57          MREQ    WR                 | Memory write to  0FF <- 57\n#056H T11 AB:0FE DB:02          MREQ    WR                 | Memory write to  0FE <- 02\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:58          MREQ RD                    | Memory read from 005 -> 58\n#053H T8  AB:0FF DB:58          MREQ    WR                 | Memory write to  0FF <- 58\n#056H T11 AB:0FE DB:0A          MREQ    WR                 | Memory write to  0FE <- 0A\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:59          MREQ RD                    | Memory read from 005 -> 59\n#053H T8  AB:0FF DB:59          MREQ    WR                 | Memory write to  0FF <- 59\n#056H T11 AB:0FE DB:0E          MREQ    WR                 | Memory write to  0FE <- 0E\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:5A          MREQ RD                    | Memory read from 005 -> 5A\n#053H T8  AB:0FF DB:54          MREQ    WR                 | Memory write to  0FF <- 54\n#056H T11 AB:0FE DB:02          MREQ    WR                 | Memory write to  0FE <- 02\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:5B          MREQ RD                    | Memory read from 005 -> 5B\n#053H T8  AB:0FF DB:55          MREQ    WR                 | Memory write to  0FF <- 55\n#056H T11 AB:0FE DB:06          MREQ    WR                 | Memory write to  0FE <- 06\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:5C          MREQ RD                    | Memory read from 005 -> 5C\n#053H T8  AB:0FF DB:56          MREQ    WR                 | Memory write to  0FF <- 56\n#056H T11 AB:0FE DB:06          MREQ    WR                 | Memory write to  0FE <- 06\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:5D          MREQ RD                    | Memory read from 005 -> 5D\n#053H T8  AB:0FF DB:57          MREQ    WR                 | Memory write to  0FF <- 57\n#056H T11 AB:0FE DB:02          MREQ    WR                 | Memory write to  0FE <- 02\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:5E          MREQ RD                    | Memory read from 005 -> 5E\n#053H T8  AB:0FF DB:58          MREQ    WR                 | Memory write to  0FF <- 58\n#056H T11 AB:0FE DB:0A          MREQ    WR                 | Memory write to  0FE <- 0A\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:5F          MREQ RD                    | Memory read from 005 -> 5F\n#053H T8  AB:0FF DB:59          MREQ    WR                 | Memory write to  0FF <- 59\n#056H T11 AB:0FE DB:0E          MREQ    WR                 | Memory write to  0FE <- 0E\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:60          MREQ RD                    | Memory read from 005 -> 60\n#053H T8  AB:0FF DB:60          MREQ    WR                 | Memory write to  0FF <- 60\n#056H T11 AB:0FE DB:26          MREQ    WR                 | Memory write to  0FE <- 26\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:61          MREQ RD                    | Memory read from 005 -> 61\n#053H T8  AB:0FF DB:61          MREQ    WR                 | Memory write to  0FF <- 61\n#056H T11 AB:0FE DB:22          MREQ    WR                 | Memory write to  0FE <- 22\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:62          MREQ RD                    | Memory read from 005 -> 62\n#053H T8  AB:0FF DB:62          MREQ    WR                 | Memory write to  0FF <- 62\n#056H T11 AB:0FE DB:22          MREQ    WR                 | Memory write to  0FE <- 22\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:63          MREQ RD                    | Memory read from 005 -> 63\n#053H T8  AB:0FF DB:63          MREQ    WR                 | Memory write to  0FF <- 63\n#056H T11 AB:0FE DB:26          MREQ    WR                 | Memory write to  0FE <- 26\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:64          MREQ RD                    | Memory read from 005 -> 64\n#053H T8  AB:0FF DB:64          MREQ    WR                 | Memory write to  0FF <- 64\n#056H T11 AB:0FE DB:22          MREQ    WR                 | Memory write to  0FE <- 22\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:65          MREQ RD                    | Memory read from 005 -> 65\n#053H T8  AB:0FF DB:65          MREQ    WR                 | Memory write to  0FF <- 65\n#056H T11 AB:0FE DB:26          MREQ    WR                 | Memory write to  0FE <- 26\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:66          MREQ RD                    | Memory read from 005 -> 66\n#053H T8  AB:0FF DB:66          MREQ    WR                 | Memory write to  0FF <- 66\n#056H T11 AB:0FE DB:26          MREQ    WR                 | Memory write to  0FE <- 26\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:67          MREQ RD                    | Memory read from 005 -> 67\n#053H T8  AB:0FF DB:67          MREQ    WR                 | Memory write to  0FF <- 67\n#056H T11 AB:0FE DB:22          MREQ    WR                 | Memory write to  0FE <- 22\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:68          MREQ RD                    | Memory read from 005 -> 68\n#053H T8  AB:0FF DB:68          MREQ    WR                 | Memory write to  0FF <- 68\n#056H T11 AB:0FE DB:2A          MREQ    WR                 | Memory write to  0FE <- 2A\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:69          MREQ RD                    | Memory read from 005 -> 69\n#053H T8  AB:0FF DB:69          MREQ    WR                 | Memory write to  0FF <- 69\n#056H T11 AB:0FE DB:2E          MREQ    WR                 | Memory write to  0FE <- 2E\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:6A          MREQ RD                    | Memory read from 005 -> 6A\n#053H T8  AB:0FF DB:64          MREQ    WR                 | Memory write to  0FF <- 64\n#056H T11 AB:0FE DB:22          MREQ    WR                 | Memory write to  0FE <- 22\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:6B          MREQ RD                    | Memory read from 005 -> 6B\n#053H T8  AB:0FF DB:65          MREQ    WR                 | Memory write to  0FF <- 65\n#056H T11 AB:0FE DB:26          MREQ    WR                 | Memory write to  0FE <- 26\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:6C          MREQ RD                    | Memory read from 005 -> 6C\n#053H T8  AB:0FF DB:66          MREQ    WR                 | Memory write to  0FF <- 66\n#056H T11 AB:0FE DB:26          MREQ    WR                 | Memory write to  0FE <- 26\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:6D          MREQ RD                    | Memory read from 005 -> 6D\n#053H T8  AB:0FF DB:67          MREQ    WR                 | Memory write to  0FF <- 67\n#056H T11 AB:0FE DB:22          MREQ    WR                 | Memory write to  0FE <- 22\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:6E          MREQ RD                    | Memory read from 005 -> 6E\n#053H T8  AB:0FF DB:68          MREQ    WR                 | Memory write to  0FF <- 68\n#056H T11 AB:0FE DB:2A          MREQ    WR                 | Memory write to  0FE <- 2A\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:6F          MREQ RD                    | Memory read from 005 -> 6F\n#053H T8  AB:0FF DB:69          MREQ    WR                 | Memory write to  0FF <- 69\n#056H T11 AB:0FE DB:2E          MREQ    WR                 | Memory write to  0FE <- 2E\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:70          MREQ RD                    | Memory read from 005 -> 70\n#053H T8  AB:0FF DB:70          MREQ    WR                 | Memory write to  0FF <- 70\n#056H T11 AB:0FE DB:22          MREQ    WR                 | Memory write to  0FE <- 22\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:71          MREQ RD                    | Memory read from 005 -> 71\n#053H T8  AB:0FF DB:71          MREQ    WR                 | Memory write to  0FF <- 71\n#056H T11 AB:0FE DB:26          MREQ    WR                 | Memory write to  0FE <- 26\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:72          MREQ RD                    | Memory read from 005 -> 72\n#053H T8  AB:0FF DB:72          MREQ    WR                 | Memory write to  0FF <- 72\n#056H T11 AB:0FE DB:26          MREQ    WR                 | Memory write to  0FE <- 26\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:73          MREQ RD                    | Memory read from 005 -> 73\n#053H T8  AB:0FF DB:73          MREQ    WR                 | Memory write to  0FF <- 73\n#056H T11 AB:0FE DB:22          MREQ    WR                 | Memory write to  0FE <- 22\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:74          MREQ RD                    | Memory read from 005 -> 74\n#053H T8  AB:0FF DB:74          MREQ    WR                 | Memory write to  0FF <- 74\n#056H T11 AB:0FE DB:26          MREQ    WR                 | Memory write to  0FE <- 26\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:75          MREQ RD                    | Memory read from 005 -> 75\n#053H T8  AB:0FF DB:75          MREQ    WR                 | Memory write to  0FF <- 75\n#056H T11 AB:0FE DB:22          MREQ    WR                 | Memory write to  0FE <- 22\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:76          MREQ RD                    | Memory read from 005 -> 76\n#053H T8  AB:0FF DB:76          MREQ    WR                 | Memory write to  0FF <- 76\n#056H T11 AB:0FE DB:22          MREQ    WR                 | Memory write to  0FE <- 22\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:77          MREQ RD                    | Memory read from 005 -> 77\n#053H T8  AB:0FF DB:77          MREQ    WR                 | Memory write to  0FF <- 77\n#056H T11 AB:0FE DB:26          MREQ    WR                 | Memory write to  0FE <- 26\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:78          MREQ RD                    | Memory read from 005 -> 78\n#053H T8  AB:0FF DB:78          MREQ    WR                 | Memory write to  0FF <- 78\n#056H T11 AB:0FE DB:2E          MREQ    WR                 | Memory write to  0FE <- 2E\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:79          MREQ RD                    | Memory read from 005 -> 79\n#053H T8  AB:0FF DB:79          MREQ    WR                 | Memory write to  0FF <- 79\n#056H T11 AB:0FE DB:2A          MREQ    WR                 | Memory write to  0FE <- 2A\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:7A          MREQ RD                    | Memory read from 005 -> 7A\n#053H T8  AB:0FF DB:74          MREQ    WR                 | Memory write to  0FF <- 74\n#056H T11 AB:0FE DB:26          MREQ    WR                 | Memory write to  0FE <- 26\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:7B          MREQ RD                    | Memory read from 005 -> 7B\n#053H T8  AB:0FF DB:75          MREQ    WR                 | Memory write to  0FF <- 75\n#056H T11 AB:0FE DB:22          MREQ    WR                 | Memory write to  0FE <- 22\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:7C          MREQ RD                    | Memory read from 005 -> 7C\n#053H T8  AB:0FF DB:76          MREQ    WR                 | Memory write to  0FF <- 76\n#056H T11 AB:0FE DB:22          MREQ    WR                 | Memory write to  0FE <- 22\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:7D          MREQ RD                    | Memory read from 005 -> 7D\n#053H T8  AB:0FF DB:77          MREQ    WR                 | Memory write to  0FF <- 77\n#056H T11 AB:0FE DB:26          MREQ    WR                 | Memory write to  0FE <- 26\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:7E          MREQ RD                    | Memory read from 005 -> 7E\n#053H T8  AB:0FF DB:78          MREQ    WR                 | Memory write to  0FF <- 78\n#056H T11 AB:0FE DB:2E          MREQ    WR                 | Memory write to  0FE <- 2E\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:7F          MREQ RD                    | Memory read from 005 -> 7F\n#053H T8  AB:0FF DB:79          MREQ    WR                 | Memory write to  0FF <- 79\n#056H T11 AB:0FE DB:2A          MREQ    WR                 | Memory write to  0FE <- 2A\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:80          MREQ RD                    | Memory read from 005 -> 80\n#053H T8  AB:0FF DB:80          MREQ    WR                 | Memory write to  0FF <- 80\n#056H T11 AB:0FE DB:82          MREQ    WR                 | Memory write to  0FE <- 82\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:81          MREQ RD                    | Memory read from 005 -> 81\n#053H T8  AB:0FF DB:81          MREQ    WR                 | Memory write to  0FF <- 81\n#056H T11 AB:0FE DB:86          MREQ    WR                 | Memory write to  0FE <- 86\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:82          MREQ RD                    | Memory read from 005 -> 82\n#053H T8  AB:0FF DB:82          MREQ    WR                 | Memory write to  0FF <- 82\n#056H T11 AB:0FE DB:86          MREQ    WR                 | Memory write to  0FE <- 86\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:83          MREQ RD                    | Memory read from 005 -> 83\n#053H T8  AB:0FF DB:83          MREQ    WR                 | Memory write to  0FF <- 83\n#056H T11 AB:0FE DB:82          MREQ    WR                 | Memory write to  0FE <- 82\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:84          MREQ RD                    | Memory read from 005 -> 84\n#053H T8  AB:0FF DB:84          MREQ    WR                 | Memory write to  0FF <- 84\n#056H T11 AB:0FE DB:86          MREQ    WR                 | Memory write to  0FE <- 86\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:85          MREQ RD                    | Memory read from 005 -> 85\n#053H T8  AB:0FF DB:85          MREQ    WR                 | Memory write to  0FF <- 85\n#056H T11 AB:0FE DB:82          MREQ    WR                 | Memory write to  0FE <- 82\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:86          MREQ RD                    | Memory read from 005 -> 86\n#053H T8  AB:0FF DB:86          MREQ    WR                 | Memory write to  0FF <- 86\n#056H T11 AB:0FE DB:82          MREQ    WR                 | Memory write to  0FE <- 82\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:87          MREQ RD                    | Memory read from 005 -> 87\n#053H T8  AB:0FF DB:87          MREQ    WR                 | Memory write to  0FF <- 87\n#056H T11 AB:0FE DB:86          MREQ    WR                 | Memory write to  0FE <- 86\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:88          MREQ RD                    | Memory read from 005 -> 88\n#053H T8  AB:0FF DB:88          MREQ    WR                 | Memory write to  0FF <- 88\n#056H T11 AB:0FE DB:8E          MREQ    WR                 | Memory write to  0FE <- 8E\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:89          MREQ RD                    | Memory read from 005 -> 89\n#053H T8  AB:0FF DB:89          MREQ    WR                 | Memory write to  0FF <- 89\n#056H T11 AB:0FE DB:8A          MREQ    WR                 | Memory write to  0FE <- 8A\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:8A          MREQ RD                    | Memory read from 005 -> 8A\n#053H T8  AB:0FF DB:84          MREQ    WR                 | Memory write to  0FF <- 84\n#056H T11 AB:0FE DB:86          MREQ    WR                 | Memory write to  0FE <- 86\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:8B          MREQ RD                    | Memory read from 005 -> 8B\n#053H T8  AB:0FF DB:85          MREQ    WR                 | Memory write to  0FF <- 85\n#056H T11 AB:0FE DB:82          MREQ    WR                 | Memory write to  0FE <- 82\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:8C          MREQ RD                    | Memory read from 005 -> 8C\n#053H T8  AB:0FF DB:86          MREQ    WR                 | Memory write to  0FF <- 86\n#056H T11 AB:0FE DB:82          MREQ    WR                 | Memory write to  0FE <- 82\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:8D          MREQ RD                    | Memory read from 005 -> 8D\n#053H T8  AB:0FF DB:87          MREQ    WR                 | Memory write to  0FF <- 87\n#056H T11 AB:0FE DB:86          MREQ    WR                 | Memory write to  0FE <- 86\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:8E          MREQ RD                    | Memory read from 005 -> 8E\n#053H T8  AB:0FF DB:88          MREQ    WR                 | Memory write to  0FF <- 88\n#056H T11 AB:0FE DB:8E          MREQ    WR                 | Memory write to  0FE <- 8E\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:8F          MREQ RD                    | Memory read from 005 -> 8F\n#053H T8  AB:0FF DB:89          MREQ    WR                 | Memory write to  0FF <- 89\n#056H T11 AB:0FE DB:8A          MREQ    WR                 | Memory write to  0FE <- 8A\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:90          MREQ RD                    | Memory read from 005 -> 90\n#053H T8  AB:0FF DB:90          MREQ    WR                 | Memory write to  0FF <- 90\n#056H T11 AB:0FE DB:86          MREQ    WR                 | Memory write to  0FE <- 86\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:91          MREQ RD                    | Memory read from 005 -> 91\n#053H T8  AB:0FF DB:91          MREQ    WR                 | Memory write to  0FF <- 91\n#056H T11 AB:0FE DB:82          MREQ    WR                 | Memory write to  0FE <- 82\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:92          MREQ RD                    | Memory read from 005 -> 92\n#053H T8  AB:0FF DB:92          MREQ    WR                 | Memory write to  0FF <- 92\n#056H T11 AB:0FE DB:82          MREQ    WR                 | Memory write to  0FE <- 82\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:93          MREQ RD                    | Memory read from 005 -> 93\n#053H T8  AB:0FF DB:93          MREQ    WR                 | Memory write to  0FF <- 93\n#056H T11 AB:0FE DB:86          MREQ    WR                 | Memory write to  0FE <- 86\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:94          MREQ RD                    | Memory read from 005 -> 94\n#053H T8  AB:0FF DB:94          MREQ    WR                 | Memory write to  0FF <- 94\n#056H T11 AB:0FE DB:82          MREQ    WR                 | Memory write to  0FE <- 82\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:95          MREQ RD                    | Memory read from 005 -> 95\n#053H T8  AB:0FF DB:95          MREQ    WR                 | Memory write to  0FF <- 95\n#056H T11 AB:0FE DB:86          MREQ    WR                 | Memory write to  0FE <- 86\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:96          MREQ RD                    | Memory read from 005 -> 96\n#053H T8  AB:0FF DB:96          MREQ    WR                 | Memory write to  0FF <- 96\n#056H T11 AB:0FE DB:86          MREQ    WR                 | Memory write to  0FE <- 86\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:97          MREQ RD                    | Memory read from 005 -> 97\n#053H T8  AB:0FF DB:97          MREQ    WR                 | Memory write to  0FF <- 97\n#056H T11 AB:0FE DB:82          MREQ    WR                 | Memory write to  0FE <- 82\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:98          MREQ RD                    | Memory read from 005 -> 98\n#053H T8  AB:0FF DB:98          MREQ    WR                 | Memory write to  0FF <- 98\n#056H T11 AB:0FE DB:8A          MREQ    WR                 | Memory write to  0FE <- 8A\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:99          MREQ RD                    | Memory read from 005 -> 99\n#053H T8  AB:0FF DB:99          MREQ    WR                 | Memory write to  0FF <- 99\n#056H T11 AB:0FE DB:8E          MREQ    WR                 | Memory write to  0FE <- 8E\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:9A          MREQ RD                    | Memory read from 005 -> 9A\n#053H T8  AB:0FF DB:34          MREQ    WR                 | Memory write to  0FF <- 34\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:9B          MREQ RD                    | Memory read from 005 -> 9B\n#053H T8  AB:0FF DB:35          MREQ    WR                 | Memory write to  0FF <- 35\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:9C          MREQ RD                    | Memory read from 005 -> 9C\n#053H T8  AB:0FF DB:36          MREQ    WR                 | Memory write to  0FF <- 36\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:9D          MREQ RD                    | Memory read from 005 -> 9D\n#053H T8  AB:0FF DB:37          MREQ    WR                 | Memory write to  0FF <- 37\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:9E          MREQ RD                    | Memory read from 005 -> 9E\n#053H T8  AB:0FF DB:38          MREQ    WR                 | Memory write to  0FF <- 38\n#056H T11 AB:0FE DB:2B          MREQ    WR                 | Memory write to  0FE <- 2B\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:9F          MREQ RD                    | Memory read from 005 -> 9F\n#053H T8  AB:0FF DB:39          MREQ    WR                 | Memory write to  0FF <- 39\n#056H T11 AB:0FE DB:2F          MREQ    WR                 | Memory write to  0FE <- 2F\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:A0          MREQ RD                    | Memory read from 005 -> A0\n#053H T8  AB:0FF DB:40          MREQ    WR                 | Memory write to  0FF <- 40\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:A1          MREQ RD                    | Memory read from 005 -> A1\n#053H T8  AB:0FF DB:41          MREQ    WR                 | Memory write to  0FF <- 41\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:A2          MREQ RD                    | Memory read from 005 -> A2\n#053H T8  AB:0FF DB:42          MREQ    WR                 | Memory write to  0FF <- 42\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:A3          MREQ RD                    | Memory read from 005 -> A3\n#053H T8  AB:0FF DB:43          MREQ    WR                 | Memory write to  0FF <- 43\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:A4          MREQ RD                    | Memory read from 005 -> A4\n#053H T8  AB:0FF DB:44          MREQ    WR                 | Memory write to  0FF <- 44\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:A5          MREQ RD                    | Memory read from 005 -> A5\n#053H T8  AB:0FF DB:45          MREQ    WR                 | Memory write to  0FF <- 45\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:A6          MREQ RD                    | Memory read from 005 -> A6\n#053H T8  AB:0FF DB:46          MREQ    WR                 | Memory write to  0FF <- 46\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:A7          MREQ RD                    | Memory read from 005 -> A7\n#053H T8  AB:0FF DB:47          MREQ    WR                 | Memory write to  0FF <- 47\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:A8          MREQ RD                    | Memory read from 005 -> A8\n#053H T8  AB:0FF DB:48          MREQ    WR                 | Memory write to  0FF <- 48\n#056H T11 AB:0FE DB:0F          MREQ    WR                 | Memory write to  0FE <- 0F\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:A9          MREQ RD                    | Memory read from 005 -> A9\n#053H T8  AB:0FF DB:49          MREQ    WR                 | Memory write to  0FF <- 49\n#056H T11 AB:0FE DB:0B          MREQ    WR                 | Memory write to  0FE <- 0B\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:AA          MREQ RD                    | Memory read from 005 -> AA\n#053H T8  AB:0FF DB:44          MREQ    WR                 | Memory write to  0FF <- 44\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:AB          MREQ RD                    | Memory read from 005 -> AB\n#053H T8  AB:0FF DB:45          MREQ    WR                 | Memory write to  0FF <- 45\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:AC          MREQ RD                    | Memory read from 005 -> AC\n#053H T8  AB:0FF DB:46          MREQ    WR                 | Memory write to  0FF <- 46\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:AD          MREQ RD                    | Memory read from 005 -> AD\n#053H T8  AB:0FF DB:47          MREQ    WR                 | Memory write to  0FF <- 47\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:AE          MREQ RD                    | Memory read from 005 -> AE\n#053H T8  AB:0FF DB:48          MREQ    WR                 | Memory write to  0FF <- 48\n#056H T11 AB:0FE DB:0F          MREQ    WR                 | Memory write to  0FE <- 0F\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:AF          MREQ RD                    | Memory read from 005 -> AF\n#053H T8  AB:0FF DB:49          MREQ    WR                 | Memory write to  0FF <- 49\n#056H T11 AB:0FE DB:0B          MREQ    WR                 | Memory write to  0FE <- 0B\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:B0          MREQ RD                    | Memory read from 005 -> B0\n#053H T8  AB:0FF DB:50          MREQ    WR                 | Memory write to  0FF <- 50\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:B1          MREQ RD                    | Memory read from 005 -> B1\n#053H T8  AB:0FF DB:51          MREQ    WR                 | Memory write to  0FF <- 51\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:B2          MREQ RD                    | Memory read from 005 -> B2\n#053H T8  AB:0FF DB:52          MREQ    WR                 | Memory write to  0FF <- 52\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:B3          MREQ RD                    | Memory read from 005 -> B3\n#053H T8  AB:0FF DB:53          MREQ    WR                 | Memory write to  0FF <- 53\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:B4          MREQ RD                    | Memory read from 005 -> B4\n#053H T8  AB:0FF DB:54          MREQ    WR                 | Memory write to  0FF <- 54\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:B5          MREQ RD                    | Memory read from 005 -> B5\n#053H T8  AB:0FF DB:55          MREQ    WR                 | Memory write to  0FF <- 55\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:B6          MREQ RD                    | Memory read from 005 -> B6\n#053H T8  AB:0FF DB:56          MREQ    WR                 | Memory write to  0FF <- 56\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:B7          MREQ RD                    | Memory read from 005 -> B7\n#053H T8  AB:0FF DB:57          MREQ    WR                 | Memory write to  0FF <- 57\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:B8          MREQ RD                    | Memory read from 005 -> B8\n#053H T8  AB:0FF DB:58          MREQ    WR                 | Memory write to  0FF <- 58\n#056H T11 AB:0FE DB:0B          MREQ    WR                 | Memory write to  0FE <- 0B\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:B9          MREQ RD                    | Memory read from 005 -> B9\n#053H T8  AB:0FF DB:59          MREQ    WR                 | Memory write to  0FF <- 59\n#056H T11 AB:0FE DB:0F          MREQ    WR                 | Memory write to  0FE <- 0F\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:BA          MREQ RD                    | Memory read from 005 -> BA\n#053H T8  AB:0FF DB:54          MREQ    WR                 | Memory write to  0FF <- 54\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:BB          MREQ RD                    | Memory read from 005 -> BB\n#053H T8  AB:0FF DB:55          MREQ    WR                 | Memory write to  0FF <- 55\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:BC          MREQ RD                    | Memory read from 005 -> BC\n#053H T8  AB:0FF DB:56          MREQ    WR                 | Memory write to  0FF <- 56\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:BD          MREQ RD                    | Memory read from 005 -> BD\n#053H T8  AB:0FF DB:57          MREQ    WR                 | Memory write to  0FF <- 57\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:BE          MREQ RD                    | Memory read from 005 -> BE\n#053H T8  AB:0FF DB:58          MREQ    WR                 | Memory write to  0FF <- 58\n#056H T11 AB:0FE DB:0B          MREQ    WR                 | Memory write to  0FE <- 0B\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:BF          MREQ RD                    | Memory read from 005 -> BF\n#053H T8  AB:0FF DB:59          MREQ    WR                 | Memory write to  0FF <- 59\n#056H T11 AB:0FE DB:0F          MREQ    WR                 | Memory write to  0FE <- 0F\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:C0          MREQ RD                    | Memory read from 005 -> C0\n#053H T8  AB:0FF DB:60          MREQ    WR                 | Memory write to  0FF <- 60\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:C1          MREQ RD                    | Memory read from 005 -> C1\n#053H T8  AB:0FF DB:61          MREQ    WR                 | Memory write to  0FF <- 61\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:C2          MREQ RD                    | Memory read from 005 -> C2\n#053H T8  AB:0FF DB:62          MREQ    WR                 | Memory write to  0FF <- 62\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:C3          MREQ RD                    | Memory read from 005 -> C3\n#053H T8  AB:0FF DB:63          MREQ    WR                 | Memory write to  0FF <- 63\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:C4          MREQ RD                    | Memory read from 005 -> C4\n#053H T8  AB:0FF DB:64          MREQ    WR                 | Memory write to  0FF <- 64\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:C5          MREQ RD                    | Memory read from 005 -> C5\n#053H T8  AB:0FF DB:65          MREQ    WR                 | Memory write to  0FF <- 65\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:C6          MREQ RD                    | Memory read from 005 -> C6\n#053H T8  AB:0FF DB:66          MREQ    WR                 | Memory write to  0FF <- 66\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:C7          MREQ RD                    | Memory read from 005 -> C7\n#053H T8  AB:0FF DB:67          MREQ    WR                 | Memory write to  0FF <- 67\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:C8          MREQ RD                    | Memory read from 005 -> C8\n#053H T8  AB:0FF DB:68          MREQ    WR                 | Memory write to  0FF <- 68\n#056H T11 AB:0FE DB:2B          MREQ    WR                 | Memory write to  0FE <- 2B\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:C9          MREQ RD                    | Memory read from 005 -> C9\n#053H T8  AB:0FF DB:69          MREQ    WR                 | Memory write to  0FF <- 69\n#056H T11 AB:0FE DB:2F          MREQ    WR                 | Memory write to  0FE <- 2F\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:CA          MREQ RD                    | Memory read from 005 -> CA\n#053H T8  AB:0FF DB:64          MREQ    WR                 | Memory write to  0FF <- 64\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:CB          MREQ RD                    | Memory read from 005 -> CB\n#053H T8  AB:0FF DB:65          MREQ    WR                 | Memory write to  0FF <- 65\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:CC          MREQ RD                    | Memory read from 005 -> CC\n#053H T8  AB:0FF DB:66          MREQ    WR                 | Memory write to  0FF <- 66\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:CD          MREQ RD                    | Memory read from 005 -> CD\n#053H T8  AB:0FF DB:67          MREQ    WR                 | Memory write to  0FF <- 67\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:CE          MREQ RD                    | Memory read from 005 -> CE\n#053H T8  AB:0FF DB:68          MREQ    WR                 | Memory write to  0FF <- 68\n#056H T11 AB:0FE DB:2B          MREQ    WR                 | Memory write to  0FE <- 2B\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:CF          MREQ RD                    | Memory read from 005 -> CF\n#053H T8  AB:0FF DB:69          MREQ    WR                 | Memory write to  0FF <- 69\n#056H T11 AB:0FE DB:2F          MREQ    WR                 | Memory write to  0FE <- 2F\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:D0          MREQ RD                    | Memory read from 005 -> D0\n#053H T8  AB:0FF DB:70          MREQ    WR                 | Memory write to  0FF <- 70\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:D1          MREQ RD                    | Memory read from 005 -> D1\n#053H T8  AB:0FF DB:71          MREQ    WR                 | Memory write to  0FF <- 71\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:D2          MREQ RD                    | Memory read from 005 -> D2\n#053H T8  AB:0FF DB:72          MREQ    WR                 | Memory write to  0FF <- 72\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:D3          MREQ RD                    | Memory read from 005 -> D3\n#053H T8  AB:0FF DB:73          MREQ    WR                 | Memory write to  0FF <- 73\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:D4          MREQ RD                    | Memory read from 005 -> D4\n#053H T8  AB:0FF DB:74          MREQ    WR                 | Memory write to  0FF <- 74\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:D5          MREQ RD                    | Memory read from 005 -> D5\n#053H T8  AB:0FF DB:75          MREQ    WR                 | Memory write to  0FF <- 75\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:D6          MREQ RD                    | Memory read from 005 -> D6\n#053H T8  AB:0FF DB:76          MREQ    WR                 | Memory write to  0FF <- 76\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:D7          MREQ RD                    | Memory read from 005 -> D7\n#053H T8  AB:0FF DB:77          MREQ    WR                 | Memory write to  0FF <- 77\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:D8          MREQ RD                    | Memory read from 005 -> D8\n#053H T8  AB:0FF DB:78          MREQ    WR                 | Memory write to  0FF <- 78\n#056H T11 AB:0FE DB:2F          MREQ    WR                 | Memory write to  0FE <- 2F\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:D9          MREQ RD                    | Memory read from 005 -> D9\n#053H T8  AB:0FF DB:79          MREQ    WR                 | Memory write to  0FF <- 79\n#056H T11 AB:0FE DB:2B          MREQ    WR                 | Memory write to  0FE <- 2B\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:DA          MREQ RD                    | Memory read from 005 -> DA\n#053H T8  AB:0FF DB:74          MREQ    WR                 | Memory write to  0FF <- 74\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:DB          MREQ RD                    | Memory read from 005 -> DB\n#053H T8  AB:0FF DB:75          MREQ    WR                 | Memory write to  0FF <- 75\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:DC          MREQ RD                    | Memory read from 005 -> DC\n#053H T8  AB:0FF DB:76          MREQ    WR                 | Memory write to  0FF <- 76\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:DD          MREQ RD                    | Memory read from 005 -> DD\n#053H T8  AB:0FF DB:77          MREQ    WR                 | Memory write to  0FF <- 77\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:DE          MREQ RD                    | Memory read from 005 -> DE\n#053H T8  AB:0FF DB:78          MREQ    WR                 | Memory write to  0FF <- 78\n#056H T11 AB:0FE DB:2F          MREQ    WR                 | Memory write to  0FE <- 2F\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:DF          MREQ RD                    | Memory read from 005 -> DF\n#053H T8  AB:0FF DB:79          MREQ    WR                 | Memory write to  0FF <- 79\n#056H T11 AB:0FE DB:2B          MREQ    WR                 | Memory write to  0FE <- 2B\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:E0          MREQ RD                    | Memory read from 005 -> E0\n#053H T8  AB:0FF DB:80          MREQ    WR                 | Memory write to  0FF <- 80\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:E1          MREQ RD                    | Memory read from 005 -> E1\n#053H T8  AB:0FF DB:81          MREQ    WR                 | Memory write to  0FF <- 81\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:E2          MREQ RD                    | Memory read from 005 -> E2\n#053H T8  AB:0FF DB:82          MREQ    WR                 | Memory write to  0FF <- 82\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:E3          MREQ RD                    | Memory read from 005 -> E3\n#053H T8  AB:0FF DB:83          MREQ    WR                 | Memory write to  0FF <- 83\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:E4          MREQ RD                    | Memory read from 005 -> E4\n#053H T8  AB:0FF DB:84          MREQ    WR                 | Memory write to  0FF <- 84\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:E5          MREQ RD                    | Memory read from 005 -> E5\n#053H T8  AB:0FF DB:85          MREQ    WR                 | Memory write to  0FF <- 85\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:E6          MREQ RD                    | Memory read from 005 -> E6\n#053H T8  AB:0FF DB:86          MREQ    WR                 | Memory write to  0FF <- 86\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:E7          MREQ RD                    | Memory read from 005 -> E7\n#053H T8  AB:0FF DB:87          MREQ    WR                 | Memory write to  0FF <- 87\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:E8          MREQ RD                    | Memory read from 005 -> E8\n#053H T8  AB:0FF DB:88          MREQ    WR                 | Memory write to  0FF <- 88\n#056H T11 AB:0FE DB:8F          MREQ    WR                 | Memory write to  0FE <- 8F\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:E9          MREQ RD                    | Memory read from 005 -> E9\n#053H T8  AB:0FF DB:89          MREQ    WR                 | Memory write to  0FF <- 89\n#056H T11 AB:0FE DB:8B          MREQ    WR                 | Memory write to  0FE <- 8B\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:EA          MREQ RD                    | Memory read from 005 -> EA\n#053H T8  AB:0FF DB:84          MREQ    WR                 | Memory write to  0FF <- 84\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:EB          MREQ RD                    | Memory read from 005 -> EB\n#053H T8  AB:0FF DB:85          MREQ    WR                 | Memory write to  0FF <- 85\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:EC          MREQ RD                    | Memory read from 005 -> EC\n#053H T8  AB:0FF DB:86          MREQ    WR                 | Memory write to  0FF <- 86\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:ED          MREQ RD                    | Memory read from 005 -> ED\n#053H T8  AB:0FF DB:87          MREQ    WR                 | Memory write to  0FF <- 87\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:EE          MREQ RD                    | Memory read from 005 -> EE\n#053H T8  AB:0FF DB:88          MREQ    WR                 | Memory write to  0FF <- 88\n#056H T11 AB:0FE DB:8F          MREQ    WR                 | Memory write to  0FE <- 8F\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:EF          MREQ RD                    | Memory read from 005 -> EF\n#053H T8  AB:0FF DB:89          MREQ    WR                 | Memory write to  0FF <- 89\n#056H T11 AB:0FE DB:8B          MREQ    WR                 | Memory write to  0FE <- 8B\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:F0          MREQ RD                    | Memory read from 005 -> F0\n#053H T8  AB:0FF DB:90          MREQ    WR                 | Memory write to  0FF <- 90\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:F1          MREQ RD                    | Memory read from 005 -> F1\n#053H T8  AB:0FF DB:91          MREQ    WR                 | Memory write to  0FF <- 91\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:F2          MREQ RD                    | Memory read from 005 -> F2\n#053H T8  AB:0FF DB:92          MREQ    WR                 | Memory write to  0FF <- 92\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:F3          MREQ RD                    | Memory read from 005 -> F3\n#053H T8  AB:0FF DB:93          MREQ    WR                 | Memory write to  0FF <- 93\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:F4          MREQ RD                    | Memory read from 005 -> F4\n#053H T8  AB:0FF DB:94          MREQ    WR                 | Memory write to  0FF <- 94\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:F5          MREQ RD                    | Memory read from 005 -> F5\n#053H T8  AB:0FF DB:95          MREQ    WR                 | Memory write to  0FF <- 95\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:F6          MREQ RD                    | Memory read from 005 -> F6\n#053H T8  AB:0FF DB:96          MREQ    WR                 | Memory write to  0FF <- 96\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:F7          MREQ RD                    | Memory read from 005 -> F7\n#053H T8  AB:0FF DB:97          MREQ    WR                 | Memory write to  0FF <- 97\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:F8          MREQ RD                    | Memory read from 005 -> F8\n#053H T8  AB:0FF DB:98          MREQ    WR                 | Memory write to  0FF <- 98\n#056H T11 AB:0FE DB:8B          MREQ    WR                 | Memory write to  0FE <- 8B\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:F9          MREQ RD                    | Memory read from 005 -> F9\n#053H T8  AB:0FF DB:99          MREQ    WR                 | Memory write to  0FF <- 99\n#056H T11 AB:0FE DB:8F          MREQ    WR                 | Memory write to  0FE <- 8F\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:FA          MREQ RD                    | Memory read from 005 -> FA\n#053H T8  AB:0FF DB:94          MREQ    WR                 | Memory write to  0FF <- 94\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:FB          MREQ RD                    | Memory read from 005 -> FB\n#053H T8  AB:0FF DB:95          MREQ    WR                 | Memory write to  0FF <- 95\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:FC          MREQ RD                    | Memory read from 005 -> FC\n#053H T8  AB:0FF DB:96          MREQ    WR                 | Memory write to  0FF <- 96\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:FD          MREQ RD                    | Memory read from 005 -> FD\n#053H T8  AB:0FF DB:97          MREQ    WR                 | Memory write to  0FF <- 97\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:FE          MREQ RD                    | Memory read from 005 -> FE\n#053H T8  AB:0FF DB:98          MREQ    WR                 | Memory write to  0FF <- 98\n#056H T11 AB:0FE DB:8B          MREQ    WR                 | Memory write to  0FE <- 8B\n#017H T7  AB:004 DB:02          MREQ RD                    | Memory read from 004 -> 02\n#020H T10 AB:005 DB:FF          MREQ RD                    | Memory read from 005 -> FF\n#053H T8  AB:0FF DB:99          MREQ    WR                 | Memory write to  0FF <- 99\n#056H T11 AB:0FE DB:8F          MREQ    WR                 | Memory write to  0FE <- 8F\n"
  },
  {
    "path": "tools/dongle/daa/daa_s-0c.out",
    "content": "#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:00          MREQ RD                    | Memory read from 005 -> 00\n#053H T8  AB:0FF DB:A0          MREQ    WR                 | Memory write to  0FF <- A0\n#056H T11 AB:0FE DB:A7          MREQ    WR                 | Memory write to  0FE <- A7\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:01          MREQ RD                    | Memory read from 005 -> 01\n#053H T8  AB:0FF DB:A1          MREQ    WR                 | Memory write to  0FF <- A1\n#056H T11 AB:0FE DB:A3          MREQ    WR                 | Memory write to  0FE <- A3\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:02          MREQ RD                    | Memory read from 005 -> 02\n#053H T8  AB:0FF DB:A2          MREQ    WR                 | Memory write to  0FF <- A2\n#056H T11 AB:0FE DB:A3          MREQ    WR                 | Memory write to  0FE <- A3\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:03          MREQ RD                    | Memory read from 005 -> 03\n#053H T8  AB:0FF DB:A3          MREQ    WR                 | Memory write to  0FF <- A3\n#056H T11 AB:0FE DB:A7          MREQ    WR                 | Memory write to  0FE <- A7\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:04          MREQ RD                    | Memory read from 005 -> 04\n#053H T8  AB:0FF DB:A4          MREQ    WR                 | Memory write to  0FF <- A4\n#056H T11 AB:0FE DB:A3          MREQ    WR                 | Memory write to  0FE <- A3\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:05          MREQ RD                    | Memory read from 005 -> 05\n#053H T8  AB:0FF DB:A5          MREQ    WR                 | Memory write to  0FF <- A5\n#056H T11 AB:0FE DB:A7          MREQ    WR                 | Memory write to  0FE <- A7\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:06          MREQ RD                    | Memory read from 005 -> 06\n#053H T8  AB:0FF DB:A6          MREQ    WR                 | Memory write to  0FF <- A6\n#056H T11 AB:0FE DB:A7          MREQ    WR                 | Memory write to  0FE <- A7\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:07          MREQ RD                    | Memory read from 005 -> 07\n#053H T8  AB:0FF DB:A7          MREQ    WR                 | Memory write to  0FF <- A7\n#056H T11 AB:0FE DB:A3          MREQ    WR                 | Memory write to  0FE <- A3\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:08          MREQ RD                    | Memory read from 005 -> 08\n#053H T8  AB:0FF DB:A8          MREQ    WR                 | Memory write to  0FF <- A8\n#056H T11 AB:0FE DB:AB          MREQ    WR                 | Memory write to  0FE <- AB\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:09          MREQ RD                    | Memory read from 005 -> 09\n#053H T8  AB:0FF DB:A9          MREQ    WR                 | Memory write to  0FF <- A9\n#056H T11 AB:0FE DB:AF          MREQ    WR                 | Memory write to  0FE <- AF\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:0A          MREQ RD                    | Memory read from 005 -> 0A\n#053H T8  AB:0FF DB:A4          MREQ    WR                 | Memory write to  0FF <- A4\n#056H T11 AB:0FE DB:A3          MREQ    WR                 | Memory write to  0FE <- A3\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:0B          MREQ RD                    | Memory read from 005 -> 0B\n#053H T8  AB:0FF DB:A5          MREQ    WR                 | Memory write to  0FF <- A5\n#056H T11 AB:0FE DB:A7          MREQ    WR                 | Memory write to  0FE <- A7\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:0C          MREQ RD                    | Memory read from 005 -> 0C\n#053H T8  AB:0FF DB:A6          MREQ    WR                 | Memory write to  0FF <- A6\n#056H T11 AB:0FE DB:A7          MREQ    WR                 | Memory write to  0FE <- A7\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:0D          MREQ RD                    | Memory read from 005 -> 0D\n#053H T8  AB:0FF DB:A7          MREQ    WR                 | Memory write to  0FF <- A7\n#056H T11 AB:0FE DB:A3          MREQ    WR                 | Memory write to  0FE <- A3\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:0E          MREQ RD                    | Memory read from 005 -> 0E\n#053H T8  AB:0FF DB:A8          MREQ    WR                 | Memory write to  0FF <- A8\n#056H T11 AB:0FE DB:AB          MREQ    WR                 | Memory write to  0FE <- AB\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:0F          MREQ RD                    | Memory read from 005 -> 0F\n#053H T8  AB:0FF DB:A9          MREQ    WR                 | Memory write to  0FF <- A9\n#056H T11 AB:0FE DB:AF          MREQ    WR                 | Memory write to  0FE <- AF\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:10          MREQ RD                    | Memory read from 005 -> 10\n#053H T8  AB:0FF DB:B0          MREQ    WR                 | Memory write to  0FF <- B0\n#056H T11 AB:0FE DB:A3          MREQ    WR                 | Memory write to  0FE <- A3\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:11          MREQ RD                    | Memory read from 005 -> 11\n#053H T8  AB:0FF DB:B1          MREQ    WR                 | Memory write to  0FF <- B1\n#056H T11 AB:0FE DB:A7          MREQ    WR                 | Memory write to  0FE <- A7\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:12          MREQ RD                    | Memory read from 005 -> 12\n#053H T8  AB:0FF DB:B2          MREQ    WR                 | Memory write to  0FF <- B2\n#056H T11 AB:0FE DB:A7          MREQ    WR                 | Memory write to  0FE <- A7\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:13          MREQ RD                    | Memory read from 005 -> 13\n#053H T8  AB:0FF DB:B3          MREQ    WR                 | Memory write to  0FF <- B3\n#056H T11 AB:0FE DB:A3          MREQ    WR                 | Memory write to  0FE <- A3\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:14          MREQ RD                    | Memory read from 005 -> 14\n#053H T8  AB:0FF DB:B4          MREQ    WR                 | Memory write to  0FF <- B4\n#056H T11 AB:0FE DB:A7          MREQ    WR                 | Memory write to  0FE <- A7\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:15          MREQ RD                    | Memory read from 005 -> 15\n#053H T8  AB:0FF DB:B5          MREQ    WR                 | Memory write to  0FF <- B5\n#056H T11 AB:0FE DB:A3          MREQ    WR                 | Memory write to  0FE <- A3\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:16          MREQ RD                    | Memory read from 005 -> 16\n#053H T8  AB:0FF DB:B6          MREQ    WR                 | Memory write to  0FF <- B6\n#056H T11 AB:0FE DB:A3          MREQ    WR                 | Memory write to  0FE <- A3\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:17          MREQ RD                    | Memory read from 005 -> 17\n#053H T8  AB:0FF DB:B7          MREQ    WR                 | Memory write to  0FF <- B7\n#056H T11 AB:0FE DB:A7          MREQ    WR                 | Memory write to  0FE <- A7\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:18          MREQ RD                    | Memory read from 005 -> 18\n#053H T8  AB:0FF DB:B8          MREQ    WR                 | Memory write to  0FF <- B8\n#056H T11 AB:0FE DB:AF          MREQ    WR                 | Memory write to  0FE <- AF\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:19          MREQ RD                    | Memory read from 005 -> 19\n#053H T8  AB:0FF DB:B9          MREQ    WR                 | Memory write to  0FF <- B9\n#056H T11 AB:0FE DB:AB          MREQ    WR                 | Memory write to  0FE <- AB\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:1A          MREQ RD                    | Memory read from 005 -> 1A\n#053H T8  AB:0FF DB:B4          MREQ    WR                 | Memory write to  0FF <- B4\n#056H T11 AB:0FE DB:A7          MREQ    WR                 | Memory write to  0FE <- A7\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:1B          MREQ RD                    | Memory read from 005 -> 1B\n#053H T8  AB:0FF DB:B5          MREQ    WR                 | Memory write to  0FF <- B5\n#056H T11 AB:0FE DB:A3          MREQ    WR                 | Memory write to  0FE <- A3\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:1C          MREQ RD                    | Memory read from 005 -> 1C\n#053H T8  AB:0FF DB:B6          MREQ    WR                 | Memory write to  0FF <- B6\n#056H T11 AB:0FE DB:A3          MREQ    WR                 | Memory write to  0FE <- A3\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:1D          MREQ RD                    | Memory read from 005 -> 1D\n#053H T8  AB:0FF DB:B7          MREQ    WR                 | Memory write to  0FF <- B7\n#056H T11 AB:0FE DB:A7          MREQ    WR                 | Memory write to  0FE <- A7\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:1E          MREQ RD                    | Memory read from 005 -> 1E\n#053H T8  AB:0FF DB:B8          MREQ    WR                 | Memory write to  0FF <- B8\n#056H T11 AB:0FE DB:AF          MREQ    WR                 | Memory write to  0FE <- AF\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:1F          MREQ RD                    | Memory read from 005 -> 1F\n#053H T8  AB:0FF DB:B9          MREQ    WR                 | Memory write to  0FF <- B9\n#056H T11 AB:0FE DB:AB          MREQ    WR                 | Memory write to  0FE <- AB\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:20          MREQ RD                    | Memory read from 005 -> 20\n#053H T8  AB:0FF DB:C0          MREQ    WR                 | Memory write to  0FF <- C0\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:21          MREQ RD                    | Memory read from 005 -> 21\n#053H T8  AB:0FF DB:C1          MREQ    WR                 | Memory write to  0FF <- C1\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:22          MREQ RD                    | Memory read from 005 -> 22\n#053H T8  AB:0FF DB:C2          MREQ    WR                 | Memory write to  0FF <- C2\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:23          MREQ RD                    | Memory read from 005 -> 23\n#053H T8  AB:0FF DB:C3          MREQ    WR                 | Memory write to  0FF <- C3\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:24          MREQ RD                    | Memory read from 005 -> 24\n#053H T8  AB:0FF DB:C4          MREQ    WR                 | Memory write to  0FF <- C4\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:25          MREQ RD                    | Memory read from 005 -> 25\n#053H T8  AB:0FF DB:C5          MREQ    WR                 | Memory write to  0FF <- C5\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:26          MREQ RD                    | Memory read from 005 -> 26\n#053H T8  AB:0FF DB:C6          MREQ    WR                 | Memory write to  0FF <- C6\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:27          MREQ RD                    | Memory read from 005 -> 27\n#053H T8  AB:0FF DB:C7          MREQ    WR                 | Memory write to  0FF <- C7\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:28          MREQ RD                    | Memory read from 005 -> 28\n#053H T8  AB:0FF DB:C8          MREQ    WR                 | Memory write to  0FF <- C8\n#056H T11 AB:0FE DB:8B          MREQ    WR                 | Memory write to  0FE <- 8B\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:29          MREQ RD                    | Memory read from 005 -> 29\n#053H T8  AB:0FF DB:C9          MREQ    WR                 | Memory write to  0FF <- C9\n#056H T11 AB:0FE DB:8F          MREQ    WR                 | Memory write to  0FE <- 8F\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:2A          MREQ RD                    | Memory read from 005 -> 2A\n#053H T8  AB:0FF DB:C4          MREQ    WR                 | Memory write to  0FF <- C4\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:2B          MREQ RD                    | Memory read from 005 -> 2B\n#053H T8  AB:0FF DB:C5          MREQ    WR                 | Memory write to  0FF <- C5\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:2C          MREQ RD                    | Memory read from 005 -> 2C\n#053H T8  AB:0FF DB:C6          MREQ    WR                 | Memory write to  0FF <- C6\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:2D          MREQ RD                    | Memory read from 005 -> 2D\n#053H T8  AB:0FF DB:C7          MREQ    WR                 | Memory write to  0FF <- C7\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:2E          MREQ RD                    | Memory read from 005 -> 2E\n#053H T8  AB:0FF DB:C8          MREQ    WR                 | Memory write to  0FF <- C8\n#056H T11 AB:0FE DB:8B          MREQ    WR                 | Memory write to  0FE <- 8B\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:2F          MREQ RD                    | Memory read from 005 -> 2F\n#053H T8  AB:0FF DB:C9          MREQ    WR                 | Memory write to  0FF <- C9\n#056H T11 AB:0FE DB:8F          MREQ    WR                 | Memory write to  0FE <- 8F\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:30          MREQ RD                    | Memory read from 005 -> 30\n#053H T8  AB:0FF DB:D0          MREQ    WR                 | Memory write to  0FF <- D0\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:31          MREQ RD                    | Memory read from 005 -> 31\n#053H T8  AB:0FF DB:D1          MREQ    WR                 | Memory write to  0FF <- D1\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:32          MREQ RD                    | Memory read from 005 -> 32\n#053H T8  AB:0FF DB:D2          MREQ    WR                 | Memory write to  0FF <- D2\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:33          MREQ RD                    | Memory read from 005 -> 33\n#053H T8  AB:0FF DB:D3          MREQ    WR                 | Memory write to  0FF <- D3\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:34          MREQ RD                    | Memory read from 005 -> 34\n#053H T8  AB:0FF DB:D4          MREQ    WR                 | Memory write to  0FF <- D4\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:35          MREQ RD                    | Memory read from 005 -> 35\n#053H T8  AB:0FF DB:D5          MREQ    WR                 | Memory write to  0FF <- D5\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:36          MREQ RD                    | Memory read from 005 -> 36\n#053H T8  AB:0FF DB:D6          MREQ    WR                 | Memory write to  0FF <- D6\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:37          MREQ RD                    | Memory read from 005 -> 37\n#053H T8  AB:0FF DB:D7          MREQ    WR                 | Memory write to  0FF <- D7\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:38          MREQ RD                    | Memory read from 005 -> 38\n#053H T8  AB:0FF DB:D8          MREQ    WR                 | Memory write to  0FF <- D8\n#056H T11 AB:0FE DB:8F          MREQ    WR                 | Memory write to  0FE <- 8F\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:39          MREQ RD                    | Memory read from 005 -> 39\n#053H T8  AB:0FF DB:D9          MREQ    WR                 | Memory write to  0FF <- D9\n#056H T11 AB:0FE DB:8B          MREQ    WR                 | Memory write to  0FE <- 8B\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:3A          MREQ RD                    | Memory read from 005 -> 3A\n#053H T8  AB:0FF DB:D4          MREQ    WR                 | Memory write to  0FF <- D4\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:3B          MREQ RD                    | Memory read from 005 -> 3B\n#053H T8  AB:0FF DB:D5          MREQ    WR                 | Memory write to  0FF <- D5\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:3C          MREQ RD                    | Memory read from 005 -> 3C\n#053H T8  AB:0FF DB:D6          MREQ    WR                 | Memory write to  0FF <- D6\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:3D          MREQ RD                    | Memory read from 005 -> 3D\n#053H T8  AB:0FF DB:D7          MREQ    WR                 | Memory write to  0FF <- D7\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:3E          MREQ RD                    | Memory read from 005 -> 3E\n#053H T8  AB:0FF DB:D8          MREQ    WR                 | Memory write to  0FF <- D8\n#056H T11 AB:0FE DB:8F          MREQ    WR                 | Memory write to  0FE <- 8F\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:3F          MREQ RD                    | Memory read from 005 -> 3F\n#053H T8  AB:0FF DB:D9          MREQ    WR                 | Memory write to  0FF <- D9\n#056H T11 AB:0FE DB:8B          MREQ    WR                 | Memory write to  0FE <- 8B\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:40          MREQ RD                    | Memory read from 005 -> 40\n#053H T8  AB:0FF DB:E0          MREQ    WR                 | Memory write to  0FF <- E0\n#056H T11 AB:0FE DB:A3          MREQ    WR                 | Memory write to  0FE <- A3\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:41          MREQ RD                    | Memory read from 005 -> 41\n#053H T8  AB:0FF DB:E1          MREQ    WR                 | Memory write to  0FF <- E1\n#056H T11 AB:0FE DB:A7          MREQ    WR                 | Memory write to  0FE <- A7\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:42          MREQ RD                    | Memory read from 005 -> 42\n#053H T8  AB:0FF DB:E2          MREQ    WR                 | Memory write to  0FF <- E2\n#056H T11 AB:0FE DB:A7          MREQ    WR                 | Memory write to  0FE <- A7\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:43          MREQ RD                    | Memory read from 005 -> 43\n#053H T8  AB:0FF DB:E3          MREQ    WR                 | Memory write to  0FF <- E3\n#056H T11 AB:0FE DB:A3          MREQ    WR                 | Memory write to  0FE <- A3\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:44          MREQ RD                    | Memory read from 005 -> 44\n#053H T8  AB:0FF DB:E4          MREQ    WR                 | Memory write to  0FF <- E4\n#056H T11 AB:0FE DB:A7          MREQ    WR                 | Memory write to  0FE <- A7\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:45          MREQ RD                    | Memory read from 005 -> 45\n#053H T8  AB:0FF DB:E5          MREQ    WR                 | Memory write to  0FF <- E5\n#056H T11 AB:0FE DB:A3          MREQ    WR                 | Memory write to  0FE <- A3\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:46          MREQ RD                    | Memory read from 005 -> 46\n#053H T8  AB:0FF DB:E6          MREQ    WR                 | Memory write to  0FF <- E6\n#056H T11 AB:0FE DB:A3          MREQ    WR                 | Memory write to  0FE <- A3\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:47          MREQ RD                    | Memory read from 005 -> 47\n#053H T8  AB:0FF DB:E7          MREQ    WR                 | Memory write to  0FF <- E7\n#056H T11 AB:0FE DB:A7          MREQ    WR                 | Memory write to  0FE <- A7\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:48          MREQ RD                    | Memory read from 005 -> 48\n#053H T8  AB:0FF DB:E8          MREQ    WR                 | Memory write to  0FF <- E8\n#056H T11 AB:0FE DB:AF          MREQ    WR                 | Memory write to  0FE <- AF\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:49          MREQ RD                    | Memory read from 005 -> 49\n#053H T8  AB:0FF DB:E9          MREQ    WR                 | Memory write to  0FF <- E9\n#056H T11 AB:0FE DB:AB          MREQ    WR                 | Memory write to  0FE <- AB\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:4A          MREQ RD                    | Memory read from 005 -> 4A\n#053H T8  AB:0FF DB:E4          MREQ    WR                 | Memory write to  0FF <- E4\n#056H T11 AB:0FE DB:A7          MREQ    WR                 | Memory write to  0FE <- A7\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:4B          MREQ RD                    | Memory read from 005 -> 4B\n#053H T8  AB:0FF DB:E5          MREQ    WR                 | Memory write to  0FF <- E5\n#056H T11 AB:0FE DB:A3          MREQ    WR                 | Memory write to  0FE <- A3\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:4C          MREQ RD                    | Memory read from 005 -> 4C\n#053H T8  AB:0FF DB:E6          MREQ    WR                 | Memory write to  0FF <- E6\n#056H T11 AB:0FE DB:A3          MREQ    WR                 | Memory write to  0FE <- A3\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:4D          MREQ RD                    | Memory read from 005 -> 4D\n#053H T8  AB:0FF DB:E7          MREQ    WR                 | Memory write to  0FF <- E7\n#056H T11 AB:0FE DB:A7          MREQ    WR                 | Memory write to  0FE <- A7\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:4E          MREQ RD                    | Memory read from 005 -> 4E\n#053H T8  AB:0FF DB:E8          MREQ    WR                 | Memory write to  0FF <- E8\n#056H T11 AB:0FE DB:AF          MREQ    WR                 | Memory write to  0FE <- AF\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:4F          MREQ RD                    | Memory read from 005 -> 4F\n#053H T8  AB:0FF DB:E9          MREQ    WR                 | Memory write to  0FF <- E9\n#056H T11 AB:0FE DB:AB          MREQ    WR                 | Memory write to  0FE <- AB\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:50          MREQ RD                    | Memory read from 005 -> 50\n#053H T8  AB:0FF DB:F0          MREQ    WR                 | Memory write to  0FF <- F0\n#056H T11 AB:0FE DB:A7          MREQ    WR                 | Memory write to  0FE <- A7\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:51          MREQ RD                    | Memory read from 005 -> 51\n#053H T8  AB:0FF DB:F1          MREQ    WR                 | Memory write to  0FF <- F1\n#056H T11 AB:0FE DB:A3          MREQ    WR                 | Memory write to  0FE <- A3\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:52          MREQ RD                    | Memory read from 005 -> 52\n#053H T8  AB:0FF DB:F2          MREQ    WR                 | Memory write to  0FF <- F2\n#056H T11 AB:0FE DB:A3          MREQ    WR                 | Memory write to  0FE <- A3\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:53          MREQ RD                    | Memory read from 005 -> 53\n#053H T8  AB:0FF DB:F3          MREQ    WR                 | Memory write to  0FF <- F3\n#056H T11 AB:0FE DB:A7          MREQ    WR                 | Memory write to  0FE <- A7\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:54          MREQ RD                    | Memory read from 005 -> 54\n#053H T8  AB:0FF DB:F4          MREQ    WR                 | Memory write to  0FF <- F4\n#056H T11 AB:0FE DB:A3          MREQ    WR                 | Memory write to  0FE <- A3\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:55          MREQ RD                    | Memory read from 005 -> 55\n#053H T8  AB:0FF DB:F5          MREQ    WR                 | Memory write to  0FF <- F5\n#056H T11 AB:0FE DB:A7          MREQ    WR                 | Memory write to  0FE <- A7\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:56          MREQ RD                    | Memory read from 005 -> 56\n#053H T8  AB:0FF DB:F6          MREQ    WR                 | Memory write to  0FF <- F6\n#056H T11 AB:0FE DB:A7          MREQ    WR                 | Memory write to  0FE <- A7\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:57          MREQ RD                    | Memory read from 005 -> 57\n#053H T8  AB:0FF DB:F7          MREQ    WR                 | Memory write to  0FF <- F7\n#056H T11 AB:0FE DB:A3          MREQ    WR                 | Memory write to  0FE <- A3\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:58          MREQ RD                    | Memory read from 005 -> 58\n#053H T8  AB:0FF DB:F8          MREQ    WR                 | Memory write to  0FF <- F8\n#056H T11 AB:0FE DB:AB          MREQ    WR                 | Memory write to  0FE <- AB\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:59          MREQ RD                    | Memory read from 005 -> 59\n#053H T8  AB:0FF DB:F9          MREQ    WR                 | Memory write to  0FF <- F9\n#056H T11 AB:0FE DB:AF          MREQ    WR                 | Memory write to  0FE <- AF\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:5A          MREQ RD                    | Memory read from 005 -> 5A\n#053H T8  AB:0FF DB:F4          MREQ    WR                 | Memory write to  0FF <- F4\n#056H T11 AB:0FE DB:A3          MREQ    WR                 | Memory write to  0FE <- A3\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:5B          MREQ RD                    | Memory read from 005 -> 5B\n#053H T8  AB:0FF DB:F5          MREQ    WR                 | Memory write to  0FF <- F5\n#056H T11 AB:0FE DB:A7          MREQ    WR                 | Memory write to  0FE <- A7\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:5C          MREQ RD                    | Memory read from 005 -> 5C\n#053H T8  AB:0FF DB:F6          MREQ    WR                 | Memory write to  0FF <- F6\n#056H T11 AB:0FE DB:A7          MREQ    WR                 | Memory write to  0FE <- A7\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:5D          MREQ RD                    | Memory read from 005 -> 5D\n#053H T8  AB:0FF DB:F7          MREQ    WR                 | Memory write to  0FF <- F7\n#056H T11 AB:0FE DB:A3          MREQ    WR                 | Memory write to  0FE <- A3\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:5E          MREQ RD                    | Memory read from 005 -> 5E\n#053H T8  AB:0FF DB:F8          MREQ    WR                 | Memory write to  0FF <- F8\n#056H T11 AB:0FE DB:AB          MREQ    WR                 | Memory write to  0FE <- AB\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:5F          MREQ RD                    | Memory read from 005 -> 5F\n#053H T8  AB:0FF DB:F9          MREQ    WR                 | Memory write to  0FF <- F9\n#056H T11 AB:0FE DB:AF          MREQ    WR                 | Memory write to  0FE <- AF\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:60          MREQ RD                    | Memory read from 005 -> 60\n#053H T8  AB:0FF DB:00          MREQ    WR                 | Memory write to  0FF <- 00\n#056H T11 AB:0FE DB:47          MREQ    WR                 | Memory write to  0FE <- 47\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:61          MREQ RD                    | Memory read from 005 -> 61\n#053H T8  AB:0FF DB:01          MREQ    WR                 | Memory write to  0FF <- 01\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:62          MREQ RD                    | Memory read from 005 -> 62\n#053H T8  AB:0FF DB:02          MREQ    WR                 | Memory write to  0FF <- 02\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:63          MREQ RD                    | Memory read from 005 -> 63\n#053H T8  AB:0FF DB:03          MREQ    WR                 | Memory write to  0FF <- 03\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:64          MREQ RD                    | Memory read from 005 -> 64\n#053H T8  AB:0FF DB:04          MREQ    WR                 | Memory write to  0FF <- 04\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:65          MREQ RD                    | Memory read from 005 -> 65\n#053H T8  AB:0FF DB:05          MREQ    WR                 | Memory write to  0FF <- 05\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:66          MREQ RD                    | Memory read from 005 -> 66\n#053H T8  AB:0FF DB:06          MREQ    WR                 | Memory write to  0FF <- 06\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:67          MREQ RD                    | Memory read from 005 -> 67\n#053H T8  AB:0FF DB:07          MREQ    WR                 | Memory write to  0FF <- 07\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:68          MREQ RD                    | Memory read from 005 -> 68\n#053H T8  AB:0FF DB:08          MREQ    WR                 | Memory write to  0FF <- 08\n#056H T11 AB:0FE DB:0B          MREQ    WR                 | Memory write to  0FE <- 0B\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:69          MREQ RD                    | Memory read from 005 -> 69\n#053H T8  AB:0FF DB:09          MREQ    WR                 | Memory write to  0FF <- 09\n#056H T11 AB:0FE DB:0F          MREQ    WR                 | Memory write to  0FE <- 0F\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:6A          MREQ RD                    | Memory read from 005 -> 6A\n#053H T8  AB:0FF DB:04          MREQ    WR                 | Memory write to  0FF <- 04\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:6B          MREQ RD                    | Memory read from 005 -> 6B\n#053H T8  AB:0FF DB:05          MREQ    WR                 | Memory write to  0FF <- 05\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:6C          MREQ RD                    | Memory read from 005 -> 6C\n#053H T8  AB:0FF DB:06          MREQ    WR                 | Memory write to  0FF <- 06\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:6D          MREQ RD                    | Memory read from 005 -> 6D\n#053H T8  AB:0FF DB:07          MREQ    WR                 | Memory write to  0FF <- 07\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:6E          MREQ RD                    | Memory read from 005 -> 6E\n#053H T8  AB:0FF DB:08          MREQ    WR                 | Memory write to  0FF <- 08\n#056H T11 AB:0FE DB:0B          MREQ    WR                 | Memory write to  0FE <- 0B\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:6F          MREQ RD                    | Memory read from 005 -> 6F\n#053H T8  AB:0FF DB:09          MREQ    WR                 | Memory write to  0FF <- 09\n#056H T11 AB:0FE DB:0F          MREQ    WR                 | Memory write to  0FE <- 0F\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:70          MREQ RD                    | Memory read from 005 -> 70\n#053H T8  AB:0FF DB:10          MREQ    WR                 | Memory write to  0FF <- 10\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:71          MREQ RD                    | Memory read from 005 -> 71\n#053H T8  AB:0FF DB:11          MREQ    WR                 | Memory write to  0FF <- 11\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:72          MREQ RD                    | Memory read from 005 -> 72\n#053H T8  AB:0FF DB:12          MREQ    WR                 | Memory write to  0FF <- 12\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:73          MREQ RD                    | Memory read from 005 -> 73\n#053H T8  AB:0FF DB:13          MREQ    WR                 | Memory write to  0FF <- 13\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:74          MREQ RD                    | Memory read from 005 -> 74\n#053H T8  AB:0FF DB:14          MREQ    WR                 | Memory write to  0FF <- 14\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:75          MREQ RD                    | Memory read from 005 -> 75\n#053H T8  AB:0FF DB:15          MREQ    WR                 | Memory write to  0FF <- 15\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:76          MREQ RD                    | Memory read from 005 -> 76\n#053H T8  AB:0FF DB:16          MREQ    WR                 | Memory write to  0FF <- 16\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:77          MREQ RD                    | Memory read from 005 -> 77\n#053H T8  AB:0FF DB:17          MREQ    WR                 | Memory write to  0FF <- 17\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:78          MREQ RD                    | Memory read from 005 -> 78\n#053H T8  AB:0FF DB:18          MREQ    WR                 | Memory write to  0FF <- 18\n#056H T11 AB:0FE DB:0F          MREQ    WR                 | Memory write to  0FE <- 0F\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:79          MREQ RD                    | Memory read from 005 -> 79\n#053H T8  AB:0FF DB:19          MREQ    WR                 | Memory write to  0FF <- 19\n#056H T11 AB:0FE DB:0B          MREQ    WR                 | Memory write to  0FE <- 0B\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:7A          MREQ RD                    | Memory read from 005 -> 7A\n#053H T8  AB:0FF DB:14          MREQ    WR                 | Memory write to  0FF <- 14\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:7B          MREQ RD                    | Memory read from 005 -> 7B\n#053H T8  AB:0FF DB:15          MREQ    WR                 | Memory write to  0FF <- 15\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:7C          MREQ RD                    | Memory read from 005 -> 7C\n#053H T8  AB:0FF DB:16          MREQ    WR                 | Memory write to  0FF <- 16\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:7D          MREQ RD                    | Memory read from 005 -> 7D\n#053H T8  AB:0FF DB:17          MREQ    WR                 | Memory write to  0FF <- 17\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:7E          MREQ RD                    | Memory read from 005 -> 7E\n#053H T8  AB:0FF DB:18          MREQ    WR                 | Memory write to  0FF <- 18\n#056H T11 AB:0FE DB:0F          MREQ    WR                 | Memory write to  0FE <- 0F\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:7F          MREQ RD                    | Memory read from 005 -> 7F\n#053H T8  AB:0FF DB:19          MREQ    WR                 | Memory write to  0FF <- 19\n#056H T11 AB:0FE DB:0B          MREQ    WR                 | Memory write to  0FE <- 0B\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:80          MREQ RD                    | Memory read from 005 -> 80\n#053H T8  AB:0FF DB:20          MREQ    WR                 | Memory write to  0FF <- 20\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:81          MREQ RD                    | Memory read from 005 -> 81\n#053H T8  AB:0FF DB:21          MREQ    WR                 | Memory write to  0FF <- 21\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:82          MREQ RD                    | Memory read from 005 -> 82\n#053H T8  AB:0FF DB:22          MREQ    WR                 | Memory write to  0FF <- 22\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:83          MREQ RD                    | Memory read from 005 -> 83\n#053H T8  AB:0FF DB:23          MREQ    WR                 | Memory write to  0FF <- 23\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:84          MREQ RD                    | Memory read from 005 -> 84\n#053H T8  AB:0FF DB:24          MREQ    WR                 | Memory write to  0FF <- 24\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:85          MREQ RD                    | Memory read from 005 -> 85\n#053H T8  AB:0FF DB:25          MREQ    WR                 | Memory write to  0FF <- 25\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:86          MREQ RD                    | Memory read from 005 -> 86\n#053H T8  AB:0FF DB:26          MREQ    WR                 | Memory write to  0FF <- 26\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:87          MREQ RD                    | Memory read from 005 -> 87\n#053H T8  AB:0FF DB:27          MREQ    WR                 | Memory write to  0FF <- 27\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:88          MREQ RD                    | Memory read from 005 -> 88\n#053H T8  AB:0FF DB:28          MREQ    WR                 | Memory write to  0FF <- 28\n#056H T11 AB:0FE DB:2F          MREQ    WR                 | Memory write to  0FE <- 2F\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:89          MREQ RD                    | Memory read from 005 -> 89\n#053H T8  AB:0FF DB:29          MREQ    WR                 | Memory write to  0FF <- 29\n#056H T11 AB:0FE DB:2B          MREQ    WR                 | Memory write to  0FE <- 2B\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:8A          MREQ RD                    | Memory read from 005 -> 8A\n#053H T8  AB:0FF DB:24          MREQ    WR                 | Memory write to  0FF <- 24\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:8B          MREQ RD                    | Memory read from 005 -> 8B\n#053H T8  AB:0FF DB:25          MREQ    WR                 | Memory write to  0FF <- 25\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:8C          MREQ RD                    | Memory read from 005 -> 8C\n#053H T8  AB:0FF DB:26          MREQ    WR                 | Memory write to  0FF <- 26\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:8D          MREQ RD                    | Memory read from 005 -> 8D\n#053H T8  AB:0FF DB:27          MREQ    WR                 | Memory write to  0FF <- 27\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:8E          MREQ RD                    | Memory read from 005 -> 8E\n#053H T8  AB:0FF DB:28          MREQ    WR                 | Memory write to  0FF <- 28\n#056H T11 AB:0FE DB:2F          MREQ    WR                 | Memory write to  0FE <- 2F\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:8F          MREQ RD                    | Memory read from 005 -> 8F\n#053H T8  AB:0FF DB:29          MREQ    WR                 | Memory write to  0FF <- 29\n#056H T11 AB:0FE DB:2B          MREQ    WR                 | Memory write to  0FE <- 2B\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:90          MREQ RD                    | Memory read from 005 -> 90\n#053H T8  AB:0FF DB:30          MREQ    WR                 | Memory write to  0FF <- 30\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:91          MREQ RD                    | Memory read from 005 -> 91\n#053H T8  AB:0FF DB:31          MREQ    WR                 | Memory write to  0FF <- 31\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:92          MREQ RD                    | Memory read from 005 -> 92\n#053H T8  AB:0FF DB:32          MREQ    WR                 | Memory write to  0FF <- 32\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:93          MREQ RD                    | Memory read from 005 -> 93\n#053H T8  AB:0FF DB:33          MREQ    WR                 | Memory write to  0FF <- 33\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:94          MREQ RD                    | Memory read from 005 -> 94\n#053H T8  AB:0FF DB:34          MREQ    WR                 | Memory write to  0FF <- 34\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:95          MREQ RD                    | Memory read from 005 -> 95\n#053H T8  AB:0FF DB:35          MREQ    WR                 | Memory write to  0FF <- 35\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:96          MREQ RD                    | Memory read from 005 -> 96\n#053H T8  AB:0FF DB:36          MREQ    WR                 | Memory write to  0FF <- 36\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:97          MREQ RD                    | Memory read from 005 -> 97\n#053H T8  AB:0FF DB:37          MREQ    WR                 | Memory write to  0FF <- 37\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:98          MREQ RD                    | Memory read from 005 -> 98\n#053H T8  AB:0FF DB:38          MREQ    WR                 | Memory write to  0FF <- 38\n#056H T11 AB:0FE DB:2B          MREQ    WR                 | Memory write to  0FE <- 2B\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:99          MREQ RD                    | Memory read from 005 -> 99\n#053H T8  AB:0FF DB:39          MREQ    WR                 | Memory write to  0FF <- 39\n#056H T11 AB:0FE DB:2F          MREQ    WR                 | Memory write to  0FE <- 2F\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:9A          MREQ RD                    | Memory read from 005 -> 9A\n#053H T8  AB:0FF DB:34          MREQ    WR                 | Memory write to  0FF <- 34\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:9B          MREQ RD                    | Memory read from 005 -> 9B\n#053H T8  AB:0FF DB:35          MREQ    WR                 | Memory write to  0FF <- 35\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:9C          MREQ RD                    | Memory read from 005 -> 9C\n#053H T8  AB:0FF DB:36          MREQ    WR                 | Memory write to  0FF <- 36\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:9D          MREQ RD                    | Memory read from 005 -> 9D\n#053H T8  AB:0FF DB:37          MREQ    WR                 | Memory write to  0FF <- 37\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:9E          MREQ RD                    | Memory read from 005 -> 9E\n#053H T8  AB:0FF DB:38          MREQ    WR                 | Memory write to  0FF <- 38\n#056H T11 AB:0FE DB:2B          MREQ    WR                 | Memory write to  0FE <- 2B\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:9F          MREQ RD                    | Memory read from 005 -> 9F\n#053H T8  AB:0FF DB:39          MREQ    WR                 | Memory write to  0FF <- 39\n#056H T11 AB:0FE DB:2F          MREQ    WR                 | Memory write to  0FE <- 2F\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:A0          MREQ RD                    | Memory read from 005 -> A0\n#053H T8  AB:0FF DB:40          MREQ    WR                 | Memory write to  0FF <- 40\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:A1          MREQ RD                    | Memory read from 005 -> A1\n#053H T8  AB:0FF DB:41          MREQ    WR                 | Memory write to  0FF <- 41\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:A2          MREQ RD                    | Memory read from 005 -> A2\n#053H T8  AB:0FF DB:42          MREQ    WR                 | Memory write to  0FF <- 42\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:A3          MREQ RD                    | Memory read from 005 -> A3\n#053H T8  AB:0FF DB:43          MREQ    WR                 | Memory write to  0FF <- 43\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:A4          MREQ RD                    | Memory read from 005 -> A4\n#053H T8  AB:0FF DB:44          MREQ    WR                 | Memory write to  0FF <- 44\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:A5          MREQ RD                    | Memory read from 005 -> A5\n#053H T8  AB:0FF DB:45          MREQ    WR                 | Memory write to  0FF <- 45\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:A6          MREQ RD                    | Memory read from 005 -> A6\n#053H T8  AB:0FF DB:46          MREQ    WR                 | Memory write to  0FF <- 46\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:A7          MREQ RD                    | Memory read from 005 -> A7\n#053H T8  AB:0FF DB:47          MREQ    WR                 | Memory write to  0FF <- 47\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:A8          MREQ RD                    | Memory read from 005 -> A8\n#053H T8  AB:0FF DB:48          MREQ    WR                 | Memory write to  0FF <- 48\n#056H T11 AB:0FE DB:0F          MREQ    WR                 | Memory write to  0FE <- 0F\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:A9          MREQ RD                    | Memory read from 005 -> A9\n#053H T8  AB:0FF DB:49          MREQ    WR                 | Memory write to  0FF <- 49\n#056H T11 AB:0FE DB:0B          MREQ    WR                 | Memory write to  0FE <- 0B\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:AA          MREQ RD                    | Memory read from 005 -> AA\n#053H T8  AB:0FF DB:44          MREQ    WR                 | Memory write to  0FF <- 44\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:AB          MREQ RD                    | Memory read from 005 -> AB\n#053H T8  AB:0FF DB:45          MREQ    WR                 | Memory write to  0FF <- 45\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:AC          MREQ RD                    | Memory read from 005 -> AC\n#053H T8  AB:0FF DB:46          MREQ    WR                 | Memory write to  0FF <- 46\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:AD          MREQ RD                    | Memory read from 005 -> AD\n#053H T8  AB:0FF DB:47          MREQ    WR                 | Memory write to  0FF <- 47\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:AE          MREQ RD                    | Memory read from 005 -> AE\n#053H T8  AB:0FF DB:48          MREQ    WR                 | Memory write to  0FF <- 48\n#056H T11 AB:0FE DB:0F          MREQ    WR                 | Memory write to  0FE <- 0F\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:AF          MREQ RD                    | Memory read from 005 -> AF\n#053H T8  AB:0FF DB:49          MREQ    WR                 | Memory write to  0FF <- 49\n#056H T11 AB:0FE DB:0B          MREQ    WR                 | Memory write to  0FE <- 0B\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:B0          MREQ RD                    | Memory read from 005 -> B0\n#053H T8  AB:0FF DB:50          MREQ    WR                 | Memory write to  0FF <- 50\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:B1          MREQ RD                    | Memory read from 005 -> B1\n#053H T8  AB:0FF DB:51          MREQ    WR                 | Memory write to  0FF <- 51\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:B2          MREQ RD                    | Memory read from 005 -> B2\n#053H T8  AB:0FF DB:52          MREQ    WR                 | Memory write to  0FF <- 52\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:B3          MREQ RD                    | Memory read from 005 -> B3\n#053H T8  AB:0FF DB:53          MREQ    WR                 | Memory write to  0FF <- 53\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:B4          MREQ RD                    | Memory read from 005 -> B4\n#053H T8  AB:0FF DB:54          MREQ    WR                 | Memory write to  0FF <- 54\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:B5          MREQ RD                    | Memory read from 005 -> B5\n#053H T8  AB:0FF DB:55          MREQ    WR                 | Memory write to  0FF <- 55\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:B6          MREQ RD                    | Memory read from 005 -> B6\n#053H T8  AB:0FF DB:56          MREQ    WR                 | Memory write to  0FF <- 56\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:B7          MREQ RD                    | Memory read from 005 -> B7\n#053H T8  AB:0FF DB:57          MREQ    WR                 | Memory write to  0FF <- 57\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:B8          MREQ RD                    | Memory read from 005 -> B8\n#053H T8  AB:0FF DB:58          MREQ    WR                 | Memory write to  0FF <- 58\n#056H T11 AB:0FE DB:0B          MREQ    WR                 | Memory write to  0FE <- 0B\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:B9          MREQ RD                    | Memory read from 005 -> B9\n#053H T8  AB:0FF DB:59          MREQ    WR                 | Memory write to  0FF <- 59\n#056H T11 AB:0FE DB:0F          MREQ    WR                 | Memory write to  0FE <- 0F\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:BA          MREQ RD                    | Memory read from 005 -> BA\n#053H T8  AB:0FF DB:54          MREQ    WR                 | Memory write to  0FF <- 54\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:BB          MREQ RD                    | Memory read from 005 -> BB\n#053H T8  AB:0FF DB:55          MREQ    WR                 | Memory write to  0FF <- 55\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:BC          MREQ RD                    | Memory read from 005 -> BC\n#053H T8  AB:0FF DB:56          MREQ    WR                 | Memory write to  0FF <- 56\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:BD          MREQ RD                    | Memory read from 005 -> BD\n#053H T8  AB:0FF DB:57          MREQ    WR                 | Memory write to  0FF <- 57\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:BE          MREQ RD                    | Memory read from 005 -> BE\n#053H T8  AB:0FF DB:58          MREQ    WR                 | Memory write to  0FF <- 58\n#056H T11 AB:0FE DB:0B          MREQ    WR                 | Memory write to  0FE <- 0B\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:BF          MREQ RD                    | Memory read from 005 -> BF\n#053H T8  AB:0FF DB:59          MREQ    WR                 | Memory write to  0FF <- 59\n#056H T11 AB:0FE DB:0F          MREQ    WR                 | Memory write to  0FE <- 0F\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:C0          MREQ RD                    | Memory read from 005 -> C0\n#053H T8  AB:0FF DB:60          MREQ    WR                 | Memory write to  0FF <- 60\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:C1          MREQ RD                    | Memory read from 005 -> C1\n#053H T8  AB:0FF DB:61          MREQ    WR                 | Memory write to  0FF <- 61\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:C2          MREQ RD                    | Memory read from 005 -> C2\n#053H T8  AB:0FF DB:62          MREQ    WR                 | Memory write to  0FF <- 62\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:C3          MREQ RD                    | Memory read from 005 -> C3\n#053H T8  AB:0FF DB:63          MREQ    WR                 | Memory write to  0FF <- 63\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:C4          MREQ RD                    | Memory read from 005 -> C4\n#053H T8  AB:0FF DB:64          MREQ    WR                 | Memory write to  0FF <- 64\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:C5          MREQ RD                    | Memory read from 005 -> C5\n#053H T8  AB:0FF DB:65          MREQ    WR                 | Memory write to  0FF <- 65\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:C6          MREQ RD                    | Memory read from 005 -> C6\n#053H T8  AB:0FF DB:66          MREQ    WR                 | Memory write to  0FF <- 66\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:C7          MREQ RD                    | Memory read from 005 -> C7\n#053H T8  AB:0FF DB:67          MREQ    WR                 | Memory write to  0FF <- 67\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:C8          MREQ RD                    | Memory read from 005 -> C8\n#053H T8  AB:0FF DB:68          MREQ    WR                 | Memory write to  0FF <- 68\n#056H T11 AB:0FE DB:2B          MREQ    WR                 | Memory write to  0FE <- 2B\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:C9          MREQ RD                    | Memory read from 005 -> C9\n#053H T8  AB:0FF DB:69          MREQ    WR                 | Memory write to  0FF <- 69\n#056H T11 AB:0FE DB:2F          MREQ    WR                 | Memory write to  0FE <- 2F\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:CA          MREQ RD                    | Memory read from 005 -> CA\n#053H T8  AB:0FF DB:64          MREQ    WR                 | Memory write to  0FF <- 64\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:CB          MREQ RD                    | Memory read from 005 -> CB\n#053H T8  AB:0FF DB:65          MREQ    WR                 | Memory write to  0FF <- 65\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:CC          MREQ RD                    | Memory read from 005 -> CC\n#053H T8  AB:0FF DB:66          MREQ    WR                 | Memory write to  0FF <- 66\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:CD          MREQ RD                    | Memory read from 005 -> CD\n#053H T8  AB:0FF DB:67          MREQ    WR                 | Memory write to  0FF <- 67\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:CE          MREQ RD                    | Memory read from 005 -> CE\n#053H T8  AB:0FF DB:68          MREQ    WR                 | Memory write to  0FF <- 68\n#056H T11 AB:0FE DB:2B          MREQ    WR                 | Memory write to  0FE <- 2B\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:CF          MREQ RD                    | Memory read from 005 -> CF\n#053H T8  AB:0FF DB:69          MREQ    WR                 | Memory write to  0FF <- 69\n#056H T11 AB:0FE DB:2F          MREQ    WR                 | Memory write to  0FE <- 2F\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:D0          MREQ RD                    | Memory read from 005 -> D0\n#053H T8  AB:0FF DB:70          MREQ    WR                 | Memory write to  0FF <- 70\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:D1          MREQ RD                    | Memory read from 005 -> D1\n#053H T8  AB:0FF DB:71          MREQ    WR                 | Memory write to  0FF <- 71\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:D2          MREQ RD                    | Memory read from 005 -> D2\n#053H T8  AB:0FF DB:72          MREQ    WR                 | Memory write to  0FF <- 72\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:D3          MREQ RD                    | Memory read from 005 -> D3\n#053H T8  AB:0FF DB:73          MREQ    WR                 | Memory write to  0FF <- 73\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:D4          MREQ RD                    | Memory read from 005 -> D4\n#053H T8  AB:0FF DB:74          MREQ    WR                 | Memory write to  0FF <- 74\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:D5          MREQ RD                    | Memory read from 005 -> D5\n#053H T8  AB:0FF DB:75          MREQ    WR                 | Memory write to  0FF <- 75\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:D6          MREQ RD                    | Memory read from 005 -> D6\n#053H T8  AB:0FF DB:76          MREQ    WR                 | Memory write to  0FF <- 76\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:D7          MREQ RD                    | Memory read from 005 -> D7\n#053H T8  AB:0FF DB:77          MREQ    WR                 | Memory write to  0FF <- 77\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:D8          MREQ RD                    | Memory read from 005 -> D8\n#053H T8  AB:0FF DB:78          MREQ    WR                 | Memory write to  0FF <- 78\n#056H T11 AB:0FE DB:2F          MREQ    WR                 | Memory write to  0FE <- 2F\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:D9          MREQ RD                    | Memory read from 005 -> D9\n#053H T8  AB:0FF DB:79          MREQ    WR                 | Memory write to  0FF <- 79\n#056H T11 AB:0FE DB:2B          MREQ    WR                 | Memory write to  0FE <- 2B\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:DA          MREQ RD                    | Memory read from 005 -> DA\n#053H T8  AB:0FF DB:74          MREQ    WR                 | Memory write to  0FF <- 74\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:DB          MREQ RD                    | Memory read from 005 -> DB\n#053H T8  AB:0FF DB:75          MREQ    WR                 | Memory write to  0FF <- 75\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:DC          MREQ RD                    | Memory read from 005 -> DC\n#053H T8  AB:0FF DB:76          MREQ    WR                 | Memory write to  0FF <- 76\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:DD          MREQ RD                    | Memory read from 005 -> DD\n#053H T8  AB:0FF DB:77          MREQ    WR                 | Memory write to  0FF <- 77\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:DE          MREQ RD                    | Memory read from 005 -> DE\n#053H T8  AB:0FF DB:78          MREQ    WR                 | Memory write to  0FF <- 78\n#056H T11 AB:0FE DB:2F          MREQ    WR                 | Memory write to  0FE <- 2F\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:DF          MREQ RD                    | Memory read from 005 -> DF\n#053H T8  AB:0FF DB:79          MREQ    WR                 | Memory write to  0FF <- 79\n#056H T11 AB:0FE DB:2B          MREQ    WR                 | Memory write to  0FE <- 2B\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:E0          MREQ RD                    | Memory read from 005 -> E0\n#053H T8  AB:0FF DB:80          MREQ    WR                 | Memory write to  0FF <- 80\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:E1          MREQ RD                    | Memory read from 005 -> E1\n#053H T8  AB:0FF DB:81          MREQ    WR                 | Memory write to  0FF <- 81\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:E2          MREQ RD                    | Memory read from 005 -> E2\n#053H T8  AB:0FF DB:82          MREQ    WR                 | Memory write to  0FF <- 82\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:E3          MREQ RD                    | Memory read from 005 -> E3\n#053H T8  AB:0FF DB:83          MREQ    WR                 | Memory write to  0FF <- 83\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:E4          MREQ RD                    | Memory read from 005 -> E4\n#053H T8  AB:0FF DB:84          MREQ    WR                 | Memory write to  0FF <- 84\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:E5          MREQ RD                    | Memory read from 005 -> E5\n#053H T8  AB:0FF DB:85          MREQ    WR                 | Memory write to  0FF <- 85\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:E6          MREQ RD                    | Memory read from 005 -> E6\n#053H T8  AB:0FF DB:86          MREQ    WR                 | Memory write to  0FF <- 86\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:E7          MREQ RD                    | Memory read from 005 -> E7\n#053H T8  AB:0FF DB:87          MREQ    WR                 | Memory write to  0FF <- 87\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:E8          MREQ RD                    | Memory read from 005 -> E8\n#053H T8  AB:0FF DB:88          MREQ    WR                 | Memory write to  0FF <- 88\n#056H T11 AB:0FE DB:8F          MREQ    WR                 | Memory write to  0FE <- 8F\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:E9          MREQ RD                    | Memory read from 005 -> E9\n#053H T8  AB:0FF DB:89          MREQ    WR                 | Memory write to  0FF <- 89\n#056H T11 AB:0FE DB:8B          MREQ    WR                 | Memory write to  0FE <- 8B\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:EA          MREQ RD                    | Memory read from 005 -> EA\n#053H T8  AB:0FF DB:84          MREQ    WR                 | Memory write to  0FF <- 84\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:EB          MREQ RD                    | Memory read from 005 -> EB\n#053H T8  AB:0FF DB:85          MREQ    WR                 | Memory write to  0FF <- 85\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:EC          MREQ RD                    | Memory read from 005 -> EC\n#053H T8  AB:0FF DB:86          MREQ    WR                 | Memory write to  0FF <- 86\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:ED          MREQ RD                    | Memory read from 005 -> ED\n#053H T8  AB:0FF DB:87          MREQ    WR                 | Memory write to  0FF <- 87\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:EE          MREQ RD                    | Memory read from 005 -> EE\n#053H T8  AB:0FF DB:88          MREQ    WR                 | Memory write to  0FF <- 88\n#056H T11 AB:0FE DB:8F          MREQ    WR                 | Memory write to  0FE <- 8F\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:EF          MREQ RD                    | Memory read from 005 -> EF\n#053H T8  AB:0FF DB:89          MREQ    WR                 | Memory write to  0FF <- 89\n#056H T11 AB:0FE DB:8B          MREQ    WR                 | Memory write to  0FE <- 8B\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:F0          MREQ RD                    | Memory read from 005 -> F0\n#053H T8  AB:0FF DB:90          MREQ    WR                 | Memory write to  0FF <- 90\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:F1          MREQ RD                    | Memory read from 005 -> F1\n#053H T8  AB:0FF DB:91          MREQ    WR                 | Memory write to  0FF <- 91\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:F2          MREQ RD                    | Memory read from 005 -> F2\n#053H T8  AB:0FF DB:92          MREQ    WR                 | Memory write to  0FF <- 92\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:F3          MREQ RD                    | Memory read from 005 -> F3\n#053H T8  AB:0FF DB:93          MREQ    WR                 | Memory write to  0FF <- 93\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:F4          MREQ RD                    | Memory read from 005 -> F4\n#053H T8  AB:0FF DB:94          MREQ    WR                 | Memory write to  0FF <- 94\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:F5          MREQ RD                    | Memory read from 005 -> F5\n#053H T8  AB:0FF DB:95          MREQ    WR                 | Memory write to  0FF <- 95\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:F6          MREQ RD                    | Memory read from 005 -> F6\n#053H T8  AB:0FF DB:96          MREQ    WR                 | Memory write to  0FF <- 96\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:F7          MREQ RD                    | Memory read from 005 -> F7\n#053H T8  AB:0FF DB:97          MREQ    WR                 | Memory write to  0FF <- 97\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:F8          MREQ RD                    | Memory read from 005 -> F8\n#053H T8  AB:0FF DB:98          MREQ    WR                 | Memory write to  0FF <- 98\n#056H T11 AB:0FE DB:8B          MREQ    WR                 | Memory write to  0FE <- 8B\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:F9          MREQ RD                    | Memory read from 005 -> F9\n#053H T8  AB:0FF DB:99          MREQ    WR                 | Memory write to  0FF <- 99\n#056H T11 AB:0FE DB:8F          MREQ    WR                 | Memory write to  0FE <- 8F\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:FA          MREQ RD                    | Memory read from 005 -> FA\n#053H T8  AB:0FF DB:94          MREQ    WR                 | Memory write to  0FF <- 94\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:FB          MREQ RD                    | Memory read from 005 -> FB\n#053H T8  AB:0FF DB:95          MREQ    WR                 | Memory write to  0FF <- 95\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:FC          MREQ RD                    | Memory read from 005 -> FC\n#053H T8  AB:0FF DB:96          MREQ    WR                 | Memory write to  0FF <- 96\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:FD          MREQ RD                    | Memory read from 005 -> FD\n#053H T8  AB:0FF DB:97          MREQ    WR                 | Memory write to  0FF <- 97\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:FE          MREQ RD                    | Memory read from 005 -> FE\n#053H T8  AB:0FF DB:98          MREQ    WR                 | Memory write to  0FF <- 98\n#056H T11 AB:0FE DB:8B          MREQ    WR                 | Memory write to  0FE <- 8B\n#017H T7  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#020H T10 AB:005 DB:FF          MREQ RD                    | Memory read from 005 -> FF\n#053H T8  AB:0FF DB:99          MREQ    WR                 | Memory write to  0FF <- 99\n#056H T11 AB:0FE DB:8F          MREQ    WR                 | Memory write to  0FE <- 8F\n"
  },
  {
    "path": "tools/dongle/daa/daa_s-h0.out",
    "content": "#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:00          MREQ RD                    | Memory read from 005 -> 00\n#053H T8  AB:0FF DB:FA          MREQ    WR                 | Memory write to  0FF <- FA\n#056H T11 AB:0FE DB:BE          MREQ    WR                 | Memory write to  0FE <- BE\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:01          MREQ RD                    | Memory read from 005 -> 01\n#053H T8  AB:0FF DB:FB          MREQ    WR                 | Memory write to  0FF <- FB\n#056H T11 AB:0FE DB:BA          MREQ    WR                 | Memory write to  0FE <- BA\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:02          MREQ RD                    | Memory read from 005 -> 02\n#053H T8  AB:0FF DB:FC          MREQ    WR                 | Memory write to  0FF <- FC\n#056H T11 AB:0FE DB:BE          MREQ    WR                 | Memory write to  0FE <- BE\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:03          MREQ RD                    | Memory read from 005 -> 03\n#053H T8  AB:0FF DB:FD          MREQ    WR                 | Memory write to  0FF <- FD\n#056H T11 AB:0FE DB:BA          MREQ    WR                 | Memory write to  0FE <- BA\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:04          MREQ RD                    | Memory read from 005 -> 04\n#053H T8  AB:0FF DB:FE          MREQ    WR                 | Memory write to  0FF <- FE\n#056H T11 AB:0FE DB:BA          MREQ    WR                 | Memory write to  0FE <- BA\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:05          MREQ RD                    | Memory read from 005 -> 05\n#053H T8  AB:0FF DB:FF          MREQ    WR                 | Memory write to  0FF <- FF\n#056H T11 AB:0FE DB:BE          MREQ    WR                 | Memory write to  0FE <- BE\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:06          MREQ RD                    | Memory read from 005 -> 06\n#053H T8  AB:0FF DB:00          MREQ    WR                 | Memory write to  0FF <- 00\n#056H T11 AB:0FE DB:46          MREQ    WR                 | Memory write to  0FE <- 46\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:07          MREQ RD                    | Memory read from 005 -> 07\n#053H T8  AB:0FF DB:01          MREQ    WR                 | Memory write to  0FF <- 01\n#056H T11 AB:0FE DB:02          MREQ    WR                 | Memory write to  0FE <- 02\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:08          MREQ RD                    | Memory read from 005 -> 08\n#053H T8  AB:0FF DB:02          MREQ    WR                 | Memory write to  0FF <- 02\n#056H T11 AB:0FE DB:02          MREQ    WR                 | Memory write to  0FE <- 02\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:09          MREQ RD                    | Memory read from 005 -> 09\n#053H T8  AB:0FF DB:03          MREQ    WR                 | Memory write to  0FF <- 03\n#056H T11 AB:0FE DB:06          MREQ    WR                 | Memory write to  0FE <- 06\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:0A          MREQ RD                    | Memory read from 005 -> 0A\n#053H T8  AB:0FF DB:04          MREQ    WR                 | Memory write to  0FF <- 04\n#056H T11 AB:0FE DB:02          MREQ    WR                 | Memory write to  0FE <- 02\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:0B          MREQ RD                    | Memory read from 005 -> 0B\n#053H T8  AB:0FF DB:05          MREQ    WR                 | Memory write to  0FF <- 05\n#056H T11 AB:0FE DB:06          MREQ    WR                 | Memory write to  0FE <- 06\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:0C          MREQ RD                    | Memory read from 005 -> 0C\n#053H T8  AB:0FF DB:06          MREQ    WR                 | Memory write to  0FF <- 06\n#056H T11 AB:0FE DB:06          MREQ    WR                 | Memory write to  0FE <- 06\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:0D          MREQ RD                    | Memory read from 005 -> 0D\n#053H T8  AB:0FF DB:07          MREQ    WR                 | Memory write to  0FF <- 07\n#056H T11 AB:0FE DB:02          MREQ    WR                 | Memory write to  0FE <- 02\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:0E          MREQ RD                    | Memory read from 005 -> 0E\n#053H T8  AB:0FF DB:08          MREQ    WR                 | Memory write to  0FF <- 08\n#056H T11 AB:0FE DB:0A          MREQ    WR                 | Memory write to  0FE <- 0A\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:0F          MREQ RD                    | Memory read from 005 -> 0F\n#053H T8  AB:0FF DB:09          MREQ    WR                 | Memory write to  0FF <- 09\n#056H T11 AB:0FE DB:0E          MREQ    WR                 | Memory write to  0FE <- 0E\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:10          MREQ RD                    | Memory read from 005 -> 10\n#053H T8  AB:0FF DB:0A          MREQ    WR                 | Memory write to  0FF <- 0A\n#056H T11 AB:0FE DB:1E          MREQ    WR                 | Memory write to  0FE <- 1E\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:11          MREQ RD                    | Memory read from 005 -> 11\n#053H T8  AB:0FF DB:0B          MREQ    WR                 | Memory write to  0FF <- 0B\n#056H T11 AB:0FE DB:1A          MREQ    WR                 | Memory write to  0FE <- 1A\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:12          MREQ RD                    | Memory read from 005 -> 12\n#053H T8  AB:0FF DB:0C          MREQ    WR                 | Memory write to  0FF <- 0C\n#056H T11 AB:0FE DB:1E          MREQ    WR                 | Memory write to  0FE <- 1E\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:13          MREQ RD                    | Memory read from 005 -> 13\n#053H T8  AB:0FF DB:0D          MREQ    WR                 | Memory write to  0FF <- 0D\n#056H T11 AB:0FE DB:1A          MREQ    WR                 | Memory write to  0FE <- 1A\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:14          MREQ RD                    | Memory read from 005 -> 14\n#053H T8  AB:0FF DB:0E          MREQ    WR                 | Memory write to  0FF <- 0E\n#056H T11 AB:0FE DB:1A          MREQ    WR                 | Memory write to  0FE <- 1A\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:15          MREQ RD                    | Memory read from 005 -> 15\n#053H T8  AB:0FF DB:0F          MREQ    WR                 | Memory write to  0FF <- 0F\n#056H T11 AB:0FE DB:1E          MREQ    WR                 | Memory write to  0FE <- 1E\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:16          MREQ RD                    | Memory read from 005 -> 16\n#053H T8  AB:0FF DB:10          MREQ    WR                 | Memory write to  0FF <- 10\n#056H T11 AB:0FE DB:02          MREQ    WR                 | Memory write to  0FE <- 02\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:17          MREQ RD                    | Memory read from 005 -> 17\n#053H T8  AB:0FF DB:11          MREQ    WR                 | Memory write to  0FF <- 11\n#056H T11 AB:0FE DB:06          MREQ    WR                 | Memory write to  0FE <- 06\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:18          MREQ RD                    | Memory read from 005 -> 18\n#053H T8  AB:0FF DB:12          MREQ    WR                 | Memory write to  0FF <- 12\n#056H T11 AB:0FE DB:06          MREQ    WR                 | Memory write to  0FE <- 06\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:19          MREQ RD                    | Memory read from 005 -> 19\n#053H T8  AB:0FF DB:13          MREQ    WR                 | Memory write to  0FF <- 13\n#056H T11 AB:0FE DB:02          MREQ    WR                 | Memory write to  0FE <- 02\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:1A          MREQ RD                    | Memory read from 005 -> 1A\n#053H T8  AB:0FF DB:14          MREQ    WR                 | Memory write to  0FF <- 14\n#056H T11 AB:0FE DB:06          MREQ    WR                 | Memory write to  0FE <- 06\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:1B          MREQ RD                    | Memory read from 005 -> 1B\n#053H T8  AB:0FF DB:15          MREQ    WR                 | Memory write to  0FF <- 15\n#056H T11 AB:0FE DB:02          MREQ    WR                 | Memory write to  0FE <- 02\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:1C          MREQ RD                    | Memory read from 005 -> 1C\n#053H T8  AB:0FF DB:16          MREQ    WR                 | Memory write to  0FF <- 16\n#056H T11 AB:0FE DB:02          MREQ    WR                 | Memory write to  0FE <- 02\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:1D          MREQ RD                    | Memory read from 005 -> 1D\n#053H T8  AB:0FF DB:17          MREQ    WR                 | Memory write to  0FF <- 17\n#056H T11 AB:0FE DB:06          MREQ    WR                 | Memory write to  0FE <- 06\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:1E          MREQ RD                    | Memory read from 005 -> 1E\n#053H T8  AB:0FF DB:18          MREQ    WR                 | Memory write to  0FF <- 18\n#056H T11 AB:0FE DB:0E          MREQ    WR                 | Memory write to  0FE <- 0E\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:1F          MREQ RD                    | Memory read from 005 -> 1F\n#053H T8  AB:0FF DB:19          MREQ    WR                 | Memory write to  0FF <- 19\n#056H T11 AB:0FE DB:0A          MREQ    WR                 | Memory write to  0FE <- 0A\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:20          MREQ RD                    | Memory read from 005 -> 20\n#053H T8  AB:0FF DB:1A          MREQ    WR                 | Memory write to  0FF <- 1A\n#056H T11 AB:0FE DB:1A          MREQ    WR                 | Memory write to  0FE <- 1A\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:21          MREQ RD                    | Memory read from 005 -> 21\n#053H T8  AB:0FF DB:1B          MREQ    WR                 | Memory write to  0FF <- 1B\n#056H T11 AB:0FE DB:1E          MREQ    WR                 | Memory write to  0FE <- 1E\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:22          MREQ RD                    | Memory read from 005 -> 22\n#053H T8  AB:0FF DB:1C          MREQ    WR                 | Memory write to  0FF <- 1C\n#056H T11 AB:0FE DB:1A          MREQ    WR                 | Memory write to  0FE <- 1A\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:23          MREQ RD                    | Memory read from 005 -> 23\n#053H T8  AB:0FF DB:1D          MREQ    WR                 | Memory write to  0FF <- 1D\n#056H T11 AB:0FE DB:1E          MREQ    WR                 | Memory write to  0FE <- 1E\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:24          MREQ RD                    | Memory read from 005 -> 24\n#053H T8  AB:0FF DB:1E          MREQ    WR                 | Memory write to  0FF <- 1E\n#056H T11 AB:0FE DB:1E          MREQ    WR                 | Memory write to  0FE <- 1E\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:25          MREQ RD                    | Memory read from 005 -> 25\n#053H T8  AB:0FF DB:1F          MREQ    WR                 | Memory write to  0FF <- 1F\n#056H T11 AB:0FE DB:1A          MREQ    WR                 | Memory write to  0FE <- 1A\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:26          MREQ RD                    | Memory read from 005 -> 26\n#053H T8  AB:0FF DB:20          MREQ    WR                 | Memory write to  0FF <- 20\n#056H T11 AB:0FE DB:22          MREQ    WR                 | Memory write to  0FE <- 22\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:27          MREQ RD                    | Memory read from 005 -> 27\n#053H T8  AB:0FF DB:21          MREQ    WR                 | Memory write to  0FF <- 21\n#056H T11 AB:0FE DB:26          MREQ    WR                 | Memory write to  0FE <- 26\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:28          MREQ RD                    | Memory read from 005 -> 28\n#053H T8  AB:0FF DB:22          MREQ    WR                 | Memory write to  0FF <- 22\n#056H T11 AB:0FE DB:26          MREQ    WR                 | Memory write to  0FE <- 26\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:29          MREQ RD                    | Memory read from 005 -> 29\n#053H T8  AB:0FF DB:23          MREQ    WR                 | Memory write to  0FF <- 23\n#056H T11 AB:0FE DB:22          MREQ    WR                 | Memory write to  0FE <- 22\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:2A          MREQ RD                    | Memory read from 005 -> 2A\n#053H T8  AB:0FF DB:24          MREQ    WR                 | Memory write to  0FF <- 24\n#056H T11 AB:0FE DB:26          MREQ    WR                 | Memory write to  0FE <- 26\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:2B          MREQ RD                    | Memory read from 005 -> 2B\n#053H T8  AB:0FF DB:25          MREQ    WR                 | Memory write to  0FF <- 25\n#056H T11 AB:0FE DB:22          MREQ    WR                 | Memory write to  0FE <- 22\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:2C          MREQ RD                    | Memory read from 005 -> 2C\n#053H T8  AB:0FF DB:26          MREQ    WR                 | Memory write to  0FF <- 26\n#056H T11 AB:0FE DB:22          MREQ    WR                 | Memory write to  0FE <- 22\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:2D          MREQ RD                    | Memory read from 005 -> 2D\n#053H T8  AB:0FF DB:27          MREQ    WR                 | Memory write to  0FF <- 27\n#056H T11 AB:0FE DB:26          MREQ    WR                 | Memory write to  0FE <- 26\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:2E          MREQ RD                    | Memory read from 005 -> 2E\n#053H T8  AB:0FF DB:28          MREQ    WR                 | Memory write to  0FF <- 28\n#056H T11 AB:0FE DB:2E          MREQ    WR                 | Memory write to  0FE <- 2E\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:2F          MREQ RD                    | Memory read from 005 -> 2F\n#053H T8  AB:0FF DB:29          MREQ    WR                 | Memory write to  0FF <- 29\n#056H T11 AB:0FE DB:2A          MREQ    WR                 | Memory write to  0FE <- 2A\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:30          MREQ RD                    | Memory read from 005 -> 30\n#053H T8  AB:0FF DB:2A          MREQ    WR                 | Memory write to  0FF <- 2A\n#056H T11 AB:0FE DB:3A          MREQ    WR                 | Memory write to  0FE <- 3A\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:31          MREQ RD                    | Memory read from 005 -> 31\n#053H T8  AB:0FF DB:2B          MREQ    WR                 | Memory write to  0FF <- 2B\n#056H T11 AB:0FE DB:3E          MREQ    WR                 | Memory write to  0FE <- 3E\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:32          MREQ RD                    | Memory read from 005 -> 32\n#053H T8  AB:0FF DB:2C          MREQ    WR                 | Memory write to  0FF <- 2C\n#056H T11 AB:0FE DB:3A          MREQ    WR                 | Memory write to  0FE <- 3A\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:33          MREQ RD                    | Memory read from 005 -> 33\n#053H T8  AB:0FF DB:2D          MREQ    WR                 | Memory write to  0FF <- 2D\n#056H T11 AB:0FE DB:3E          MREQ    WR                 | Memory write to  0FE <- 3E\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:34          MREQ RD                    | Memory read from 005 -> 34\n#053H T8  AB:0FF DB:2E          MREQ    WR                 | Memory write to  0FF <- 2E\n#056H T11 AB:0FE DB:3E          MREQ    WR                 | Memory write to  0FE <- 3E\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:35          MREQ RD                    | Memory read from 005 -> 35\n#053H T8  AB:0FF DB:2F          MREQ    WR                 | Memory write to  0FF <- 2F\n#056H T11 AB:0FE DB:3A          MREQ    WR                 | Memory write to  0FE <- 3A\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:36          MREQ RD                    | Memory read from 005 -> 36\n#053H T8  AB:0FF DB:30          MREQ    WR                 | Memory write to  0FF <- 30\n#056H T11 AB:0FE DB:26          MREQ    WR                 | Memory write to  0FE <- 26\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:37          MREQ RD                    | Memory read from 005 -> 37\n#053H T8  AB:0FF DB:31          MREQ    WR                 | Memory write to  0FF <- 31\n#056H T11 AB:0FE DB:22          MREQ    WR                 | Memory write to  0FE <- 22\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:38          MREQ RD                    | Memory read from 005 -> 38\n#053H T8  AB:0FF DB:32          MREQ    WR                 | Memory write to  0FF <- 32\n#056H T11 AB:0FE DB:22          MREQ    WR                 | Memory write to  0FE <- 22\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:39          MREQ RD                    | Memory read from 005 -> 39\n#053H T8  AB:0FF DB:33          MREQ    WR                 | Memory write to  0FF <- 33\n#056H T11 AB:0FE DB:26          MREQ    WR                 | Memory write to  0FE <- 26\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:3A          MREQ RD                    | Memory read from 005 -> 3A\n#053H T8  AB:0FF DB:34          MREQ    WR                 | Memory write to  0FF <- 34\n#056H T11 AB:0FE DB:22          MREQ    WR                 | Memory write to  0FE <- 22\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:3B          MREQ RD                    | Memory read from 005 -> 3B\n#053H T8  AB:0FF DB:35          MREQ    WR                 | Memory write to  0FF <- 35\n#056H T11 AB:0FE DB:26          MREQ    WR                 | Memory write to  0FE <- 26\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:3C          MREQ RD                    | Memory read from 005 -> 3C\n#053H T8  AB:0FF DB:36          MREQ    WR                 | Memory write to  0FF <- 36\n#056H T11 AB:0FE DB:26          MREQ    WR                 | Memory write to  0FE <- 26\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:3D          MREQ RD                    | Memory read from 005 -> 3D\n#053H T8  AB:0FF DB:37          MREQ    WR                 | Memory write to  0FF <- 37\n#056H T11 AB:0FE DB:22          MREQ    WR                 | Memory write to  0FE <- 22\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:3E          MREQ RD                    | Memory read from 005 -> 3E\n#053H T8  AB:0FF DB:38          MREQ    WR                 | Memory write to  0FF <- 38\n#056H T11 AB:0FE DB:2A          MREQ    WR                 | Memory write to  0FE <- 2A\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:3F          MREQ RD                    | Memory read from 005 -> 3F\n#053H T8  AB:0FF DB:39          MREQ    WR                 | Memory write to  0FF <- 39\n#056H T11 AB:0FE DB:2E          MREQ    WR                 | Memory write to  0FE <- 2E\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:40          MREQ RD                    | Memory read from 005 -> 40\n#053H T8  AB:0FF DB:3A          MREQ    WR                 | Memory write to  0FF <- 3A\n#056H T11 AB:0FE DB:3E          MREQ    WR                 | Memory write to  0FE <- 3E\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:41          MREQ RD                    | Memory read from 005 -> 41\n#053H T8  AB:0FF DB:3B          MREQ    WR                 | Memory write to  0FF <- 3B\n#056H T11 AB:0FE DB:3A          MREQ    WR                 | Memory write to  0FE <- 3A\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:42          MREQ RD                    | Memory read from 005 -> 42\n#053H T8  AB:0FF DB:3C          MREQ    WR                 | Memory write to  0FF <- 3C\n#056H T11 AB:0FE DB:3E          MREQ    WR                 | Memory write to  0FE <- 3E\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:43          MREQ RD                    | Memory read from 005 -> 43\n#053H T8  AB:0FF DB:3D          MREQ    WR                 | Memory write to  0FF <- 3D\n#056H T11 AB:0FE DB:3A          MREQ    WR                 | Memory write to  0FE <- 3A\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:44          MREQ RD                    | Memory read from 005 -> 44\n#053H T8  AB:0FF DB:3E          MREQ    WR                 | Memory write to  0FF <- 3E\n#056H T11 AB:0FE DB:3A          MREQ    WR                 | Memory write to  0FE <- 3A\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:45          MREQ RD                    | Memory read from 005 -> 45\n#053H T8  AB:0FF DB:3F          MREQ    WR                 | Memory write to  0FF <- 3F\n#056H T11 AB:0FE DB:3E          MREQ    WR                 | Memory write to  0FE <- 3E\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:46          MREQ RD                    | Memory read from 005 -> 46\n#053H T8  AB:0FF DB:40          MREQ    WR                 | Memory write to  0FF <- 40\n#056H T11 AB:0FE DB:02          MREQ    WR                 | Memory write to  0FE <- 02\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:47          MREQ RD                    | Memory read from 005 -> 47\n#053H T8  AB:0FF DB:41          MREQ    WR                 | Memory write to  0FF <- 41\n#056H T11 AB:0FE DB:06          MREQ    WR                 | Memory write to  0FE <- 06\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:48          MREQ RD                    | Memory read from 005 -> 48\n#053H T8  AB:0FF DB:42          MREQ    WR                 | Memory write to  0FF <- 42\n#056H T11 AB:0FE DB:06          MREQ    WR                 | Memory write to  0FE <- 06\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:49          MREQ RD                    | Memory read from 005 -> 49\n#053H T8  AB:0FF DB:43          MREQ    WR                 | Memory write to  0FF <- 43\n#056H T11 AB:0FE DB:02          MREQ    WR                 | Memory write to  0FE <- 02\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:4A          MREQ RD                    | Memory read from 005 -> 4A\n#053H T8  AB:0FF DB:44          MREQ    WR                 | Memory write to  0FF <- 44\n#056H T11 AB:0FE DB:06          MREQ    WR                 | Memory write to  0FE <- 06\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:4B          MREQ RD                    | Memory read from 005 -> 4B\n#053H T8  AB:0FF DB:45          MREQ    WR                 | Memory write to  0FF <- 45\n#056H T11 AB:0FE DB:02          MREQ    WR                 | Memory write to  0FE <- 02\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:4C          MREQ RD                    | Memory read from 005 -> 4C\n#053H T8  AB:0FF DB:46          MREQ    WR                 | Memory write to  0FF <- 46\n#056H T11 AB:0FE DB:02          MREQ    WR                 | Memory write to  0FE <- 02\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:4D          MREQ RD                    | Memory read from 005 -> 4D\n#053H T8  AB:0FF DB:47          MREQ    WR                 | Memory write to  0FF <- 47\n#056H T11 AB:0FE DB:06          MREQ    WR                 | Memory write to  0FE <- 06\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:4E          MREQ RD                    | Memory read from 005 -> 4E\n#053H T8  AB:0FF DB:48          MREQ    WR                 | Memory write to  0FF <- 48\n#056H T11 AB:0FE DB:0E          MREQ    WR                 | Memory write to  0FE <- 0E\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:4F          MREQ RD                    | Memory read from 005 -> 4F\n#053H T8  AB:0FF DB:49          MREQ    WR                 | Memory write to  0FF <- 49\n#056H T11 AB:0FE DB:0A          MREQ    WR                 | Memory write to  0FE <- 0A\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:50          MREQ RD                    | Memory read from 005 -> 50\n#053H T8  AB:0FF DB:4A          MREQ    WR                 | Memory write to  0FF <- 4A\n#056H T11 AB:0FE DB:1A          MREQ    WR                 | Memory write to  0FE <- 1A\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:51          MREQ RD                    | Memory read from 005 -> 51\n#053H T8  AB:0FF DB:4B          MREQ    WR                 | Memory write to  0FF <- 4B\n#056H T11 AB:0FE DB:1E          MREQ    WR                 | Memory write to  0FE <- 1E\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:52          MREQ RD                    | Memory read from 005 -> 52\n#053H T8  AB:0FF DB:4C          MREQ    WR                 | Memory write to  0FF <- 4C\n#056H T11 AB:0FE DB:1A          MREQ    WR                 | Memory write to  0FE <- 1A\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:53          MREQ RD                    | Memory read from 005 -> 53\n#053H T8  AB:0FF DB:4D          MREQ    WR                 | Memory write to  0FF <- 4D\n#056H T11 AB:0FE DB:1E          MREQ    WR                 | Memory write to  0FE <- 1E\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:54          MREQ RD                    | Memory read from 005 -> 54\n#053H T8  AB:0FF DB:4E          MREQ    WR                 | Memory write to  0FF <- 4E\n#056H T11 AB:0FE DB:1E          MREQ    WR                 | Memory write to  0FE <- 1E\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:55          MREQ RD                    | Memory read from 005 -> 55\n#053H T8  AB:0FF DB:4F          MREQ    WR                 | Memory write to  0FF <- 4F\n#056H T11 AB:0FE DB:1A          MREQ    WR                 | Memory write to  0FE <- 1A\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:56          MREQ RD                    | Memory read from 005 -> 56\n#053H T8  AB:0FF DB:50          MREQ    WR                 | Memory write to  0FF <- 50\n#056H T11 AB:0FE DB:06          MREQ    WR                 | Memory write to  0FE <- 06\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:57          MREQ RD                    | Memory read from 005 -> 57\n#053H T8  AB:0FF DB:51          MREQ    WR                 | Memory write to  0FF <- 51\n#056H T11 AB:0FE DB:02          MREQ    WR                 | Memory write to  0FE <- 02\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:58          MREQ RD                    | Memory read from 005 -> 58\n#053H T8  AB:0FF DB:52          MREQ    WR                 | Memory write to  0FF <- 52\n#056H T11 AB:0FE DB:02          MREQ    WR                 | Memory write to  0FE <- 02\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:59          MREQ RD                    | Memory read from 005 -> 59\n#053H T8  AB:0FF DB:53          MREQ    WR                 | Memory write to  0FF <- 53\n#056H T11 AB:0FE DB:06          MREQ    WR                 | Memory write to  0FE <- 06\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:5A          MREQ RD                    | Memory read from 005 -> 5A\n#053H T8  AB:0FF DB:54          MREQ    WR                 | Memory write to  0FF <- 54\n#056H T11 AB:0FE DB:02          MREQ    WR                 | Memory write to  0FE <- 02\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:5B          MREQ RD                    | Memory read from 005 -> 5B\n#053H T8  AB:0FF DB:55          MREQ    WR                 | Memory write to  0FF <- 55\n#056H T11 AB:0FE DB:06          MREQ    WR                 | Memory write to  0FE <- 06\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:5C          MREQ RD                    | Memory read from 005 -> 5C\n#053H T8  AB:0FF DB:56          MREQ    WR                 | Memory write to  0FF <- 56\n#056H T11 AB:0FE DB:06          MREQ    WR                 | Memory write to  0FE <- 06\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:5D          MREQ RD                    | Memory read from 005 -> 5D\n#053H T8  AB:0FF DB:57          MREQ    WR                 | Memory write to  0FF <- 57\n#056H T11 AB:0FE DB:02          MREQ    WR                 | Memory write to  0FE <- 02\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:5E          MREQ RD                    | Memory read from 005 -> 5E\n#053H T8  AB:0FF DB:58          MREQ    WR                 | Memory write to  0FF <- 58\n#056H T11 AB:0FE DB:0A          MREQ    WR                 | Memory write to  0FE <- 0A\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:5F          MREQ RD                    | Memory read from 005 -> 5F\n#053H T8  AB:0FF DB:59          MREQ    WR                 | Memory write to  0FF <- 59\n#056H T11 AB:0FE DB:0E          MREQ    WR                 | Memory write to  0FE <- 0E\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:60          MREQ RD                    | Memory read from 005 -> 60\n#053H T8  AB:0FF DB:5A          MREQ    WR                 | Memory write to  0FF <- 5A\n#056H T11 AB:0FE DB:1E          MREQ    WR                 | Memory write to  0FE <- 1E\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:61          MREQ RD                    | Memory read from 005 -> 61\n#053H T8  AB:0FF DB:5B          MREQ    WR                 | Memory write to  0FF <- 5B\n#056H T11 AB:0FE DB:1A          MREQ    WR                 | Memory write to  0FE <- 1A\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:62          MREQ RD                    | Memory read from 005 -> 62\n#053H T8  AB:0FF DB:5C          MREQ    WR                 | Memory write to  0FF <- 5C\n#056H T11 AB:0FE DB:1E          MREQ    WR                 | Memory write to  0FE <- 1E\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:63          MREQ RD                    | Memory read from 005 -> 63\n#053H T8  AB:0FF DB:5D          MREQ    WR                 | Memory write to  0FF <- 5D\n#056H T11 AB:0FE DB:1A          MREQ    WR                 | Memory write to  0FE <- 1A\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:64          MREQ RD                    | Memory read from 005 -> 64\n#053H T8  AB:0FF DB:5E          MREQ    WR                 | Memory write to  0FF <- 5E\n#056H T11 AB:0FE DB:1A          MREQ    WR                 | Memory write to  0FE <- 1A\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:65          MREQ RD                    | Memory read from 005 -> 65\n#053H T8  AB:0FF DB:5F          MREQ    WR                 | Memory write to  0FF <- 5F\n#056H T11 AB:0FE DB:1E          MREQ    WR                 | Memory write to  0FE <- 1E\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:66          MREQ RD                    | Memory read from 005 -> 66\n#053H T8  AB:0FF DB:60          MREQ    WR                 | Memory write to  0FF <- 60\n#056H T11 AB:0FE DB:26          MREQ    WR                 | Memory write to  0FE <- 26\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:67          MREQ RD                    | Memory read from 005 -> 67\n#053H T8  AB:0FF DB:61          MREQ    WR                 | Memory write to  0FF <- 61\n#056H T11 AB:0FE DB:22          MREQ    WR                 | Memory write to  0FE <- 22\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:68          MREQ RD                    | Memory read from 005 -> 68\n#053H T8  AB:0FF DB:62          MREQ    WR                 | Memory write to  0FF <- 62\n#056H T11 AB:0FE DB:22          MREQ    WR                 | Memory write to  0FE <- 22\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:69          MREQ RD                    | Memory read from 005 -> 69\n#053H T8  AB:0FF DB:63          MREQ    WR                 | Memory write to  0FF <- 63\n#056H T11 AB:0FE DB:26          MREQ    WR                 | Memory write to  0FE <- 26\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:6A          MREQ RD                    | Memory read from 005 -> 6A\n#053H T8  AB:0FF DB:64          MREQ    WR                 | Memory write to  0FF <- 64\n#056H T11 AB:0FE DB:22          MREQ    WR                 | Memory write to  0FE <- 22\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:6B          MREQ RD                    | Memory read from 005 -> 6B\n#053H T8  AB:0FF DB:65          MREQ    WR                 | Memory write to  0FF <- 65\n#056H T11 AB:0FE DB:26          MREQ    WR                 | Memory write to  0FE <- 26\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:6C          MREQ RD                    | Memory read from 005 -> 6C\n#053H T8  AB:0FF DB:66          MREQ    WR                 | Memory write to  0FF <- 66\n#056H T11 AB:0FE DB:26          MREQ    WR                 | Memory write to  0FE <- 26\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:6D          MREQ RD                    | Memory read from 005 -> 6D\n#053H T8  AB:0FF DB:67          MREQ    WR                 | Memory write to  0FF <- 67\n#056H T11 AB:0FE DB:22          MREQ    WR                 | Memory write to  0FE <- 22\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:6E          MREQ RD                    | Memory read from 005 -> 6E\n#053H T8  AB:0FF DB:68          MREQ    WR                 | Memory write to  0FF <- 68\n#056H T11 AB:0FE DB:2A          MREQ    WR                 | Memory write to  0FE <- 2A\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:6F          MREQ RD                    | Memory read from 005 -> 6F\n#053H T8  AB:0FF DB:69          MREQ    WR                 | Memory write to  0FF <- 69\n#056H T11 AB:0FE DB:2E          MREQ    WR                 | Memory write to  0FE <- 2E\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:70          MREQ RD                    | Memory read from 005 -> 70\n#053H T8  AB:0FF DB:6A          MREQ    WR                 | Memory write to  0FF <- 6A\n#056H T11 AB:0FE DB:3E          MREQ    WR                 | Memory write to  0FE <- 3E\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:71          MREQ RD                    | Memory read from 005 -> 71\n#053H T8  AB:0FF DB:6B          MREQ    WR                 | Memory write to  0FF <- 6B\n#056H T11 AB:0FE DB:3A          MREQ    WR                 | Memory write to  0FE <- 3A\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:72          MREQ RD                    | Memory read from 005 -> 72\n#053H T8  AB:0FF DB:6C          MREQ    WR                 | Memory write to  0FF <- 6C\n#056H T11 AB:0FE DB:3E          MREQ    WR                 | Memory write to  0FE <- 3E\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:73          MREQ RD                    | Memory read from 005 -> 73\n#053H T8  AB:0FF DB:6D          MREQ    WR                 | Memory write to  0FF <- 6D\n#056H T11 AB:0FE DB:3A          MREQ    WR                 | Memory write to  0FE <- 3A\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:74          MREQ RD                    | Memory read from 005 -> 74\n#053H T8  AB:0FF DB:6E          MREQ    WR                 | Memory write to  0FF <- 6E\n#056H T11 AB:0FE DB:3A          MREQ    WR                 | Memory write to  0FE <- 3A\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:75          MREQ RD                    | Memory read from 005 -> 75\n#053H T8  AB:0FF DB:6F          MREQ    WR                 | Memory write to  0FF <- 6F\n#056H T11 AB:0FE DB:3E          MREQ    WR                 | Memory write to  0FE <- 3E\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:76          MREQ RD                    | Memory read from 005 -> 76\n#053H T8  AB:0FF DB:70          MREQ    WR                 | Memory write to  0FF <- 70\n#056H T11 AB:0FE DB:22          MREQ    WR                 | Memory write to  0FE <- 22\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:77          MREQ RD                    | Memory read from 005 -> 77\n#053H T8  AB:0FF DB:71          MREQ    WR                 | Memory write to  0FF <- 71\n#056H T11 AB:0FE DB:26          MREQ    WR                 | Memory write to  0FE <- 26\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:78          MREQ RD                    | Memory read from 005 -> 78\n#053H T8  AB:0FF DB:72          MREQ    WR                 | Memory write to  0FF <- 72\n#056H T11 AB:0FE DB:26          MREQ    WR                 | Memory write to  0FE <- 26\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:79          MREQ RD                    | Memory read from 005 -> 79\n#053H T8  AB:0FF DB:73          MREQ    WR                 | Memory write to  0FF <- 73\n#056H T11 AB:0FE DB:22          MREQ    WR                 | Memory write to  0FE <- 22\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:7A          MREQ RD                    | Memory read from 005 -> 7A\n#053H T8  AB:0FF DB:74          MREQ    WR                 | Memory write to  0FF <- 74\n#056H T11 AB:0FE DB:26          MREQ    WR                 | Memory write to  0FE <- 26\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:7B          MREQ RD                    | Memory read from 005 -> 7B\n#053H T8  AB:0FF DB:75          MREQ    WR                 | Memory write to  0FF <- 75\n#056H T11 AB:0FE DB:22          MREQ    WR                 | Memory write to  0FE <- 22\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:7C          MREQ RD                    | Memory read from 005 -> 7C\n#053H T8  AB:0FF DB:76          MREQ    WR                 | Memory write to  0FF <- 76\n#056H T11 AB:0FE DB:22          MREQ    WR                 | Memory write to  0FE <- 22\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:7D          MREQ RD                    | Memory read from 005 -> 7D\n#053H T8  AB:0FF DB:77          MREQ    WR                 | Memory write to  0FF <- 77\n#056H T11 AB:0FE DB:26          MREQ    WR                 | Memory write to  0FE <- 26\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:7E          MREQ RD                    | Memory read from 005 -> 7E\n#053H T8  AB:0FF DB:78          MREQ    WR                 | Memory write to  0FF <- 78\n#056H T11 AB:0FE DB:2E          MREQ    WR                 | Memory write to  0FE <- 2E\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:7F          MREQ RD                    | Memory read from 005 -> 7F\n#053H T8  AB:0FF DB:79          MREQ    WR                 | Memory write to  0FF <- 79\n#056H T11 AB:0FE DB:2A          MREQ    WR                 | Memory write to  0FE <- 2A\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:80          MREQ RD                    | Memory read from 005 -> 80\n#053H T8  AB:0FF DB:7A          MREQ    WR                 | Memory write to  0FF <- 7A\n#056H T11 AB:0FE DB:3A          MREQ    WR                 | Memory write to  0FE <- 3A\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:81          MREQ RD                    | Memory read from 005 -> 81\n#053H T8  AB:0FF DB:7B          MREQ    WR                 | Memory write to  0FF <- 7B\n#056H T11 AB:0FE DB:3E          MREQ    WR                 | Memory write to  0FE <- 3E\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:82          MREQ RD                    | Memory read from 005 -> 82\n#053H T8  AB:0FF DB:7C          MREQ    WR                 | Memory write to  0FF <- 7C\n#056H T11 AB:0FE DB:3A          MREQ    WR                 | Memory write to  0FE <- 3A\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:83          MREQ RD                    | Memory read from 005 -> 83\n#053H T8  AB:0FF DB:7D          MREQ    WR                 | Memory write to  0FF <- 7D\n#056H T11 AB:0FE DB:3E          MREQ    WR                 | Memory write to  0FE <- 3E\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:84          MREQ RD                    | Memory read from 005 -> 84\n#053H T8  AB:0FF DB:7E          MREQ    WR                 | Memory write to  0FF <- 7E\n#056H T11 AB:0FE DB:3E          MREQ    WR                 | Memory write to  0FE <- 3E\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:85          MREQ RD                    | Memory read from 005 -> 85\n#053H T8  AB:0FF DB:7F          MREQ    WR                 | Memory write to  0FF <- 7F\n#056H T11 AB:0FE DB:3A          MREQ    WR                 | Memory write to  0FE <- 3A\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:86          MREQ RD                    | Memory read from 005 -> 86\n#053H T8  AB:0FF DB:80          MREQ    WR                 | Memory write to  0FF <- 80\n#056H T11 AB:0FE DB:82          MREQ    WR                 | Memory write to  0FE <- 82\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:87          MREQ RD                    | Memory read from 005 -> 87\n#053H T8  AB:0FF DB:81          MREQ    WR                 | Memory write to  0FF <- 81\n#056H T11 AB:0FE DB:86          MREQ    WR                 | Memory write to  0FE <- 86\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:88          MREQ RD                    | Memory read from 005 -> 88\n#053H T8  AB:0FF DB:82          MREQ    WR                 | Memory write to  0FF <- 82\n#056H T11 AB:0FE DB:86          MREQ    WR                 | Memory write to  0FE <- 86\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:89          MREQ RD                    | Memory read from 005 -> 89\n#053H T8  AB:0FF DB:83          MREQ    WR                 | Memory write to  0FF <- 83\n#056H T11 AB:0FE DB:82          MREQ    WR                 | Memory write to  0FE <- 82\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:8A          MREQ RD                    | Memory read from 005 -> 8A\n#053H T8  AB:0FF DB:84          MREQ    WR                 | Memory write to  0FF <- 84\n#056H T11 AB:0FE DB:86          MREQ    WR                 | Memory write to  0FE <- 86\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:8B          MREQ RD                    | Memory read from 005 -> 8B\n#053H T8  AB:0FF DB:85          MREQ    WR                 | Memory write to  0FF <- 85\n#056H T11 AB:0FE DB:82          MREQ    WR                 | Memory write to  0FE <- 82\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:8C          MREQ RD                    | Memory read from 005 -> 8C\n#053H T8  AB:0FF DB:86          MREQ    WR                 | Memory write to  0FF <- 86\n#056H T11 AB:0FE DB:82          MREQ    WR                 | Memory write to  0FE <- 82\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:8D          MREQ RD                    | Memory read from 005 -> 8D\n#053H T8  AB:0FF DB:87          MREQ    WR                 | Memory write to  0FF <- 87\n#056H T11 AB:0FE DB:86          MREQ    WR                 | Memory write to  0FE <- 86\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:8E          MREQ RD                    | Memory read from 005 -> 8E\n#053H T8  AB:0FF DB:88          MREQ    WR                 | Memory write to  0FF <- 88\n#056H T11 AB:0FE DB:8E          MREQ    WR                 | Memory write to  0FE <- 8E\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:8F          MREQ RD                    | Memory read from 005 -> 8F\n#053H T8  AB:0FF DB:89          MREQ    WR                 | Memory write to  0FF <- 89\n#056H T11 AB:0FE DB:8A          MREQ    WR                 | Memory write to  0FE <- 8A\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:90          MREQ RD                    | Memory read from 005 -> 90\n#053H T8  AB:0FF DB:8A          MREQ    WR                 | Memory write to  0FF <- 8A\n#056H T11 AB:0FE DB:9A          MREQ    WR                 | Memory write to  0FE <- 9A\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:91          MREQ RD                    | Memory read from 005 -> 91\n#053H T8  AB:0FF DB:8B          MREQ    WR                 | Memory write to  0FF <- 8B\n#056H T11 AB:0FE DB:9E          MREQ    WR                 | Memory write to  0FE <- 9E\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:92          MREQ RD                    | Memory read from 005 -> 92\n#053H T8  AB:0FF DB:8C          MREQ    WR                 | Memory write to  0FF <- 8C\n#056H T11 AB:0FE DB:9A          MREQ    WR                 | Memory write to  0FE <- 9A\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:93          MREQ RD                    | Memory read from 005 -> 93\n#053H T8  AB:0FF DB:8D          MREQ    WR                 | Memory write to  0FF <- 8D\n#056H T11 AB:0FE DB:9E          MREQ    WR                 | Memory write to  0FE <- 9E\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:94          MREQ RD                    | Memory read from 005 -> 94\n#053H T8  AB:0FF DB:8E          MREQ    WR                 | Memory write to  0FF <- 8E\n#056H T11 AB:0FE DB:9E          MREQ    WR                 | Memory write to  0FE <- 9E\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:95          MREQ RD                    | Memory read from 005 -> 95\n#053H T8  AB:0FF DB:8F          MREQ    WR                 | Memory write to  0FF <- 8F\n#056H T11 AB:0FE DB:9A          MREQ    WR                 | Memory write to  0FE <- 9A\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:96          MREQ RD                    | Memory read from 005 -> 96\n#053H T8  AB:0FF DB:90          MREQ    WR                 | Memory write to  0FF <- 90\n#056H T11 AB:0FE DB:86          MREQ    WR                 | Memory write to  0FE <- 86\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:97          MREQ RD                    | Memory read from 005 -> 97\n#053H T8  AB:0FF DB:91          MREQ    WR                 | Memory write to  0FF <- 91\n#056H T11 AB:0FE DB:82          MREQ    WR                 | Memory write to  0FE <- 82\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:98          MREQ RD                    | Memory read from 005 -> 98\n#053H T8  AB:0FF DB:92          MREQ    WR                 | Memory write to  0FF <- 92\n#056H T11 AB:0FE DB:82          MREQ    WR                 | Memory write to  0FE <- 82\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:99          MREQ RD                    | Memory read from 005 -> 99\n#053H T8  AB:0FF DB:93          MREQ    WR                 | Memory write to  0FF <- 93\n#056H T11 AB:0FE DB:86          MREQ    WR                 | Memory write to  0FE <- 86\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:9A          MREQ RD                    | Memory read from 005 -> 9A\n#053H T8  AB:0FF DB:34          MREQ    WR                 | Memory write to  0FF <- 34\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:9B          MREQ RD                    | Memory read from 005 -> 9B\n#053H T8  AB:0FF DB:35          MREQ    WR                 | Memory write to  0FF <- 35\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:9C          MREQ RD                    | Memory read from 005 -> 9C\n#053H T8  AB:0FF DB:36          MREQ    WR                 | Memory write to  0FF <- 36\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:9D          MREQ RD                    | Memory read from 005 -> 9D\n#053H T8  AB:0FF DB:37          MREQ    WR                 | Memory write to  0FF <- 37\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:9E          MREQ RD                    | Memory read from 005 -> 9E\n#053H T8  AB:0FF DB:38          MREQ    WR                 | Memory write to  0FF <- 38\n#056H T11 AB:0FE DB:2B          MREQ    WR                 | Memory write to  0FE <- 2B\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:9F          MREQ RD                    | Memory read from 005 -> 9F\n#053H T8  AB:0FF DB:39          MREQ    WR                 | Memory write to  0FF <- 39\n#056H T11 AB:0FE DB:2F          MREQ    WR                 | Memory write to  0FE <- 2F\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:A0          MREQ RD                    | Memory read from 005 -> A0\n#053H T8  AB:0FF DB:3A          MREQ    WR                 | Memory write to  0FF <- 3A\n#056H T11 AB:0FE DB:3F          MREQ    WR                 | Memory write to  0FE <- 3F\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:A1          MREQ RD                    | Memory read from 005 -> A1\n#053H T8  AB:0FF DB:3B          MREQ    WR                 | Memory write to  0FF <- 3B\n#056H T11 AB:0FE DB:3B          MREQ    WR                 | Memory write to  0FE <- 3B\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:A2          MREQ RD                    | Memory read from 005 -> A2\n#053H T8  AB:0FF DB:3C          MREQ    WR                 | Memory write to  0FF <- 3C\n#056H T11 AB:0FE DB:3F          MREQ    WR                 | Memory write to  0FE <- 3F\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:A3          MREQ RD                    | Memory read from 005 -> A3\n#053H T8  AB:0FF DB:3D          MREQ    WR                 | Memory write to  0FF <- 3D\n#056H T11 AB:0FE DB:3B          MREQ    WR                 | Memory write to  0FE <- 3B\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:A4          MREQ RD                    | Memory read from 005 -> A4\n#053H T8  AB:0FF DB:3E          MREQ    WR                 | Memory write to  0FF <- 3E\n#056H T11 AB:0FE DB:3B          MREQ    WR                 | Memory write to  0FE <- 3B\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:A5          MREQ RD                    | Memory read from 005 -> A5\n#053H T8  AB:0FF DB:3F          MREQ    WR                 | Memory write to  0FF <- 3F\n#056H T11 AB:0FE DB:3F          MREQ    WR                 | Memory write to  0FE <- 3F\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:A6          MREQ RD                    | Memory read from 005 -> A6\n#053H T8  AB:0FF DB:40          MREQ    WR                 | Memory write to  0FF <- 40\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:A7          MREQ RD                    | Memory read from 005 -> A7\n#053H T8  AB:0FF DB:41          MREQ    WR                 | Memory write to  0FF <- 41\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:A8          MREQ RD                    | Memory read from 005 -> A8\n#053H T8  AB:0FF DB:42          MREQ    WR                 | Memory write to  0FF <- 42\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:A9          MREQ RD                    | Memory read from 005 -> A9\n#053H T8  AB:0FF DB:43          MREQ    WR                 | Memory write to  0FF <- 43\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:AA          MREQ RD                    | Memory read from 005 -> AA\n#053H T8  AB:0FF DB:44          MREQ    WR                 | Memory write to  0FF <- 44\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:AB          MREQ RD                    | Memory read from 005 -> AB\n#053H T8  AB:0FF DB:45          MREQ    WR                 | Memory write to  0FF <- 45\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:AC          MREQ RD                    | Memory read from 005 -> AC\n#053H T8  AB:0FF DB:46          MREQ    WR                 | Memory write to  0FF <- 46\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:AD          MREQ RD                    | Memory read from 005 -> AD\n#053H T8  AB:0FF DB:47          MREQ    WR                 | Memory write to  0FF <- 47\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:AE          MREQ RD                    | Memory read from 005 -> AE\n#053H T8  AB:0FF DB:48          MREQ    WR                 | Memory write to  0FF <- 48\n#056H T11 AB:0FE DB:0F          MREQ    WR                 | Memory write to  0FE <- 0F\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:AF          MREQ RD                    | Memory read from 005 -> AF\n#053H T8  AB:0FF DB:49          MREQ    WR                 | Memory write to  0FF <- 49\n#056H T11 AB:0FE DB:0B          MREQ    WR                 | Memory write to  0FE <- 0B\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:B0          MREQ RD                    | Memory read from 005 -> B0\n#053H T8  AB:0FF DB:4A          MREQ    WR                 | Memory write to  0FF <- 4A\n#056H T11 AB:0FE DB:1B          MREQ    WR                 | Memory write to  0FE <- 1B\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:B1          MREQ RD                    | Memory read from 005 -> B1\n#053H T8  AB:0FF DB:4B          MREQ    WR                 | Memory write to  0FF <- 4B\n#056H T11 AB:0FE DB:1F          MREQ    WR                 | Memory write to  0FE <- 1F\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:B2          MREQ RD                    | Memory read from 005 -> B2\n#053H T8  AB:0FF DB:4C          MREQ    WR                 | Memory write to  0FF <- 4C\n#056H T11 AB:0FE DB:1B          MREQ    WR                 | Memory write to  0FE <- 1B\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:B3          MREQ RD                    | Memory read from 005 -> B3\n#053H T8  AB:0FF DB:4D          MREQ    WR                 | Memory write to  0FF <- 4D\n#056H T11 AB:0FE DB:1F          MREQ    WR                 | Memory write to  0FE <- 1F\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:B4          MREQ RD                    | Memory read from 005 -> B4\n#053H T8  AB:0FF DB:4E          MREQ    WR                 | Memory write to  0FF <- 4E\n#056H T11 AB:0FE DB:1F          MREQ    WR                 | Memory write to  0FE <- 1F\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:B5          MREQ RD                    | Memory read from 005 -> B5\n#053H T8  AB:0FF DB:4F          MREQ    WR                 | Memory write to  0FF <- 4F\n#056H T11 AB:0FE DB:1B          MREQ    WR                 | Memory write to  0FE <- 1B\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:B6          MREQ RD                    | Memory read from 005 -> B6\n#053H T8  AB:0FF DB:50          MREQ    WR                 | Memory write to  0FF <- 50\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:B7          MREQ RD                    | Memory read from 005 -> B7\n#053H T8  AB:0FF DB:51          MREQ    WR                 | Memory write to  0FF <- 51\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:B8          MREQ RD                    | Memory read from 005 -> B8\n#053H T8  AB:0FF DB:52          MREQ    WR                 | Memory write to  0FF <- 52\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:B9          MREQ RD                    | Memory read from 005 -> B9\n#053H T8  AB:0FF DB:53          MREQ    WR                 | Memory write to  0FF <- 53\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:BA          MREQ RD                    | Memory read from 005 -> BA\n#053H T8  AB:0FF DB:54          MREQ    WR                 | Memory write to  0FF <- 54\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:BB          MREQ RD                    | Memory read from 005 -> BB\n#053H T8  AB:0FF DB:55          MREQ    WR                 | Memory write to  0FF <- 55\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:BC          MREQ RD                    | Memory read from 005 -> BC\n#053H T8  AB:0FF DB:56          MREQ    WR                 | Memory write to  0FF <- 56\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:BD          MREQ RD                    | Memory read from 005 -> BD\n#053H T8  AB:0FF DB:57          MREQ    WR                 | Memory write to  0FF <- 57\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:BE          MREQ RD                    | Memory read from 005 -> BE\n#053H T8  AB:0FF DB:58          MREQ    WR                 | Memory write to  0FF <- 58\n#056H T11 AB:0FE DB:0B          MREQ    WR                 | Memory write to  0FE <- 0B\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:BF          MREQ RD                    | Memory read from 005 -> BF\n#053H T8  AB:0FF DB:59          MREQ    WR                 | Memory write to  0FF <- 59\n#056H T11 AB:0FE DB:0F          MREQ    WR                 | Memory write to  0FE <- 0F\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:C0          MREQ RD                    | Memory read from 005 -> C0\n#053H T8  AB:0FF DB:5A          MREQ    WR                 | Memory write to  0FF <- 5A\n#056H T11 AB:0FE DB:1F          MREQ    WR                 | Memory write to  0FE <- 1F\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:C1          MREQ RD                    | Memory read from 005 -> C1\n#053H T8  AB:0FF DB:5B          MREQ    WR                 | Memory write to  0FF <- 5B\n#056H T11 AB:0FE DB:1B          MREQ    WR                 | Memory write to  0FE <- 1B\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:C2          MREQ RD                    | Memory read from 005 -> C2\n#053H T8  AB:0FF DB:5C          MREQ    WR                 | Memory write to  0FF <- 5C\n#056H T11 AB:0FE DB:1F          MREQ    WR                 | Memory write to  0FE <- 1F\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:C3          MREQ RD                    | Memory read from 005 -> C3\n#053H T8  AB:0FF DB:5D          MREQ    WR                 | Memory write to  0FF <- 5D\n#056H T11 AB:0FE DB:1B          MREQ    WR                 | Memory write to  0FE <- 1B\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:C4          MREQ RD                    | Memory read from 005 -> C4\n#053H T8  AB:0FF DB:5E          MREQ    WR                 | Memory write to  0FF <- 5E\n#056H T11 AB:0FE DB:1B          MREQ    WR                 | Memory write to  0FE <- 1B\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:C5          MREQ RD                    | Memory read from 005 -> C5\n#053H T8  AB:0FF DB:5F          MREQ    WR                 | Memory write to  0FF <- 5F\n#056H T11 AB:0FE DB:1F          MREQ    WR                 | Memory write to  0FE <- 1F\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:C6          MREQ RD                    | Memory read from 005 -> C6\n#053H T8  AB:0FF DB:60          MREQ    WR                 | Memory write to  0FF <- 60\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:C7          MREQ RD                    | Memory read from 005 -> C7\n#053H T8  AB:0FF DB:61          MREQ    WR                 | Memory write to  0FF <- 61\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:C8          MREQ RD                    | Memory read from 005 -> C8\n#053H T8  AB:0FF DB:62          MREQ    WR                 | Memory write to  0FF <- 62\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:C9          MREQ RD                    | Memory read from 005 -> C9\n#053H T8  AB:0FF DB:63          MREQ    WR                 | Memory write to  0FF <- 63\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:CA          MREQ RD                    | Memory read from 005 -> CA\n#053H T8  AB:0FF DB:64          MREQ    WR                 | Memory write to  0FF <- 64\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:CB          MREQ RD                    | Memory read from 005 -> CB\n#053H T8  AB:0FF DB:65          MREQ    WR                 | Memory write to  0FF <- 65\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:CC          MREQ RD                    | Memory read from 005 -> CC\n#053H T8  AB:0FF DB:66          MREQ    WR                 | Memory write to  0FF <- 66\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:CD          MREQ RD                    | Memory read from 005 -> CD\n#053H T8  AB:0FF DB:67          MREQ    WR                 | Memory write to  0FF <- 67\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:CE          MREQ RD                    | Memory read from 005 -> CE\n#053H T8  AB:0FF DB:68          MREQ    WR                 | Memory write to  0FF <- 68\n#056H T11 AB:0FE DB:2B          MREQ    WR                 | Memory write to  0FE <- 2B\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:CF          MREQ RD                    | Memory read from 005 -> CF\n#053H T8  AB:0FF DB:69          MREQ    WR                 | Memory write to  0FF <- 69\n#056H T11 AB:0FE DB:2F          MREQ    WR                 | Memory write to  0FE <- 2F\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:D0          MREQ RD                    | Memory read from 005 -> D0\n#053H T8  AB:0FF DB:6A          MREQ    WR                 | Memory write to  0FF <- 6A\n#056H T11 AB:0FE DB:3F          MREQ    WR                 | Memory write to  0FE <- 3F\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:D1          MREQ RD                    | Memory read from 005 -> D1\n#053H T8  AB:0FF DB:6B          MREQ    WR                 | Memory write to  0FF <- 6B\n#056H T11 AB:0FE DB:3B          MREQ    WR                 | Memory write to  0FE <- 3B\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:D2          MREQ RD                    | Memory read from 005 -> D2\n#053H T8  AB:0FF DB:6C          MREQ    WR                 | Memory write to  0FF <- 6C\n#056H T11 AB:0FE DB:3F          MREQ    WR                 | Memory write to  0FE <- 3F\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:D3          MREQ RD                    | Memory read from 005 -> D3\n#053H T8  AB:0FF DB:6D          MREQ    WR                 | Memory write to  0FF <- 6D\n#056H T11 AB:0FE DB:3B          MREQ    WR                 | Memory write to  0FE <- 3B\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:D4          MREQ RD                    | Memory read from 005 -> D4\n#053H T8  AB:0FF DB:6E          MREQ    WR                 | Memory write to  0FF <- 6E\n#056H T11 AB:0FE DB:3B          MREQ    WR                 | Memory write to  0FE <- 3B\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:D5          MREQ RD                    | Memory read from 005 -> D5\n#053H T8  AB:0FF DB:6F          MREQ    WR                 | Memory write to  0FF <- 6F\n#056H T11 AB:0FE DB:3F          MREQ    WR                 | Memory write to  0FE <- 3F\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:D6          MREQ RD                    | Memory read from 005 -> D6\n#053H T8  AB:0FF DB:70          MREQ    WR                 | Memory write to  0FF <- 70\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:D7          MREQ RD                    | Memory read from 005 -> D7\n#053H T8  AB:0FF DB:71          MREQ    WR                 | Memory write to  0FF <- 71\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:D8          MREQ RD                    | Memory read from 005 -> D8\n#053H T8  AB:0FF DB:72          MREQ    WR                 | Memory write to  0FF <- 72\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:D9          MREQ RD                    | Memory read from 005 -> D9\n#053H T8  AB:0FF DB:73          MREQ    WR                 | Memory write to  0FF <- 73\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:DA          MREQ RD                    | Memory read from 005 -> DA\n#053H T8  AB:0FF DB:74          MREQ    WR                 | Memory write to  0FF <- 74\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:DB          MREQ RD                    | Memory read from 005 -> DB\n#053H T8  AB:0FF DB:75          MREQ    WR                 | Memory write to  0FF <- 75\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:DC          MREQ RD                    | Memory read from 005 -> DC\n#053H T8  AB:0FF DB:76          MREQ    WR                 | Memory write to  0FF <- 76\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:DD          MREQ RD                    | Memory read from 005 -> DD\n#053H T8  AB:0FF DB:77          MREQ    WR                 | Memory write to  0FF <- 77\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:DE          MREQ RD                    | Memory read from 005 -> DE\n#053H T8  AB:0FF DB:78          MREQ    WR                 | Memory write to  0FF <- 78\n#056H T11 AB:0FE DB:2F          MREQ    WR                 | Memory write to  0FE <- 2F\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:DF          MREQ RD                    | Memory read from 005 -> DF\n#053H T8  AB:0FF DB:79          MREQ    WR                 | Memory write to  0FF <- 79\n#056H T11 AB:0FE DB:2B          MREQ    WR                 | Memory write to  0FE <- 2B\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:E0          MREQ RD                    | Memory read from 005 -> E0\n#053H T8  AB:0FF DB:7A          MREQ    WR                 | Memory write to  0FF <- 7A\n#056H T11 AB:0FE DB:3B          MREQ    WR                 | Memory write to  0FE <- 3B\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:E1          MREQ RD                    | Memory read from 005 -> E1\n#053H T8  AB:0FF DB:7B          MREQ    WR                 | Memory write to  0FF <- 7B\n#056H T11 AB:0FE DB:3F          MREQ    WR                 | Memory write to  0FE <- 3F\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:E2          MREQ RD                    | Memory read from 005 -> E2\n#053H T8  AB:0FF DB:7C          MREQ    WR                 | Memory write to  0FF <- 7C\n#056H T11 AB:0FE DB:3B          MREQ    WR                 | Memory write to  0FE <- 3B\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:E3          MREQ RD                    | Memory read from 005 -> E3\n#053H T8  AB:0FF DB:7D          MREQ    WR                 | Memory write to  0FF <- 7D\n#056H T11 AB:0FE DB:3F          MREQ    WR                 | Memory write to  0FE <- 3F\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:E4          MREQ RD                    | Memory read from 005 -> E4\n#053H T8  AB:0FF DB:7E          MREQ    WR                 | Memory write to  0FF <- 7E\n#056H T11 AB:0FE DB:3F          MREQ    WR                 | Memory write to  0FE <- 3F\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:E5          MREQ RD                    | Memory read from 005 -> E5\n#053H T8  AB:0FF DB:7F          MREQ    WR                 | Memory write to  0FF <- 7F\n#056H T11 AB:0FE DB:3B          MREQ    WR                 | Memory write to  0FE <- 3B\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:E6          MREQ RD                    | Memory read from 005 -> E6\n#053H T8  AB:0FF DB:80          MREQ    WR                 | Memory write to  0FF <- 80\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:E7          MREQ RD                    | Memory read from 005 -> E7\n#053H T8  AB:0FF DB:81          MREQ    WR                 | Memory write to  0FF <- 81\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:E8          MREQ RD                    | Memory read from 005 -> E8\n#053H T8  AB:0FF DB:82          MREQ    WR                 | Memory write to  0FF <- 82\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:E9          MREQ RD                    | Memory read from 005 -> E9\n#053H T8  AB:0FF DB:83          MREQ    WR                 | Memory write to  0FF <- 83\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:EA          MREQ RD                    | Memory read from 005 -> EA\n#053H T8  AB:0FF DB:84          MREQ    WR                 | Memory write to  0FF <- 84\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:EB          MREQ RD                    | Memory read from 005 -> EB\n#053H T8  AB:0FF DB:85          MREQ    WR                 | Memory write to  0FF <- 85\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:EC          MREQ RD                    | Memory read from 005 -> EC\n#053H T8  AB:0FF DB:86          MREQ    WR                 | Memory write to  0FF <- 86\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:ED          MREQ RD                    | Memory read from 005 -> ED\n#053H T8  AB:0FF DB:87          MREQ    WR                 | Memory write to  0FF <- 87\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:EE          MREQ RD                    | Memory read from 005 -> EE\n#053H T8  AB:0FF DB:88          MREQ    WR                 | Memory write to  0FF <- 88\n#056H T11 AB:0FE DB:8F          MREQ    WR                 | Memory write to  0FE <- 8F\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:EF          MREQ RD                    | Memory read from 005 -> EF\n#053H T8  AB:0FF DB:89          MREQ    WR                 | Memory write to  0FF <- 89\n#056H T11 AB:0FE DB:8B          MREQ    WR                 | Memory write to  0FE <- 8B\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:F0          MREQ RD                    | Memory read from 005 -> F0\n#053H T8  AB:0FF DB:8A          MREQ    WR                 | Memory write to  0FF <- 8A\n#056H T11 AB:0FE DB:9B          MREQ    WR                 | Memory write to  0FE <- 9B\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:F1          MREQ RD                    | Memory read from 005 -> F1\n#053H T8  AB:0FF DB:8B          MREQ    WR                 | Memory write to  0FF <- 8B\n#056H T11 AB:0FE DB:9F          MREQ    WR                 | Memory write to  0FE <- 9F\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:F2          MREQ RD                    | Memory read from 005 -> F2\n#053H T8  AB:0FF DB:8C          MREQ    WR                 | Memory write to  0FF <- 8C\n#056H T11 AB:0FE DB:9B          MREQ    WR                 | Memory write to  0FE <- 9B\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:F3          MREQ RD                    | Memory read from 005 -> F3\n#053H T8  AB:0FF DB:8D          MREQ    WR                 | Memory write to  0FF <- 8D\n#056H T11 AB:0FE DB:9F          MREQ    WR                 | Memory write to  0FE <- 9F\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:F4          MREQ RD                    | Memory read from 005 -> F4\n#053H T8  AB:0FF DB:8E          MREQ    WR                 | Memory write to  0FF <- 8E\n#056H T11 AB:0FE DB:9F          MREQ    WR                 | Memory write to  0FE <- 9F\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:F5          MREQ RD                    | Memory read from 005 -> F5\n#053H T8  AB:0FF DB:8F          MREQ    WR                 | Memory write to  0FF <- 8F\n#056H T11 AB:0FE DB:9B          MREQ    WR                 | Memory write to  0FE <- 9B\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:F6          MREQ RD                    | Memory read from 005 -> F6\n#053H T8  AB:0FF DB:90          MREQ    WR                 | Memory write to  0FF <- 90\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:F7          MREQ RD                    | Memory read from 005 -> F7\n#053H T8  AB:0FF DB:91          MREQ    WR                 | Memory write to  0FF <- 91\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:F8          MREQ RD                    | Memory read from 005 -> F8\n#053H T8  AB:0FF DB:92          MREQ    WR                 | Memory write to  0FF <- 92\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:F9          MREQ RD                    | Memory read from 005 -> F9\n#053H T8  AB:0FF DB:93          MREQ    WR                 | Memory write to  0FF <- 93\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:FA          MREQ RD                    | Memory read from 005 -> FA\n#053H T8  AB:0FF DB:94          MREQ    WR                 | Memory write to  0FF <- 94\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:FB          MREQ RD                    | Memory read from 005 -> FB\n#053H T8  AB:0FF DB:95          MREQ    WR                 | Memory write to  0FF <- 95\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:FC          MREQ RD                    | Memory read from 005 -> FC\n#053H T8  AB:0FF DB:96          MREQ    WR                 | Memory write to  0FF <- 96\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:FD          MREQ RD                    | Memory read from 005 -> FD\n#053H T8  AB:0FF DB:97          MREQ    WR                 | Memory write to  0FF <- 97\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:FE          MREQ RD                    | Memory read from 005 -> FE\n#053H T8  AB:0FF DB:98          MREQ    WR                 | Memory write to  0FF <- 98\n#056H T11 AB:0FE DB:8B          MREQ    WR                 | Memory write to  0FE <- 8B\n#017H T7  AB:004 DB:12          MREQ RD                    | Memory read from 004 -> 12\n#020H T10 AB:005 DB:FF          MREQ RD                    | Memory read from 005 -> FF\n#053H T8  AB:0FF DB:99          MREQ    WR                 | Memory write to  0FF <- 99\n#056H T11 AB:0FE DB:8F          MREQ    WR                 | Memory write to  0FE <- 8F\n"
  },
  {
    "path": "tools/dongle/daa/daa_s-hc.out",
    "content": "#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:00          MREQ RD                    | Memory read from 005 -> 00\n#053H T8  AB:0FF DB:9A          MREQ    WR                 | Memory write to  0FF <- 9A\n#056H T11 AB:0FE DB:9F          MREQ    WR                 | Memory write to  0FE <- 9F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:01          MREQ RD                    | Memory read from 005 -> 01\n#053H T8  AB:0FF DB:9B          MREQ    WR                 | Memory write to  0FF <- 9B\n#056H T11 AB:0FE DB:9B          MREQ    WR                 | Memory write to  0FE <- 9B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:02          MREQ RD                    | Memory read from 005 -> 02\n#053H T8  AB:0FF DB:9C          MREQ    WR                 | Memory write to  0FF <- 9C\n#056H T11 AB:0FE DB:9F          MREQ    WR                 | Memory write to  0FE <- 9F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:03          MREQ RD                    | Memory read from 005 -> 03\n#053H T8  AB:0FF DB:9D          MREQ    WR                 | Memory write to  0FF <- 9D\n#056H T11 AB:0FE DB:9B          MREQ    WR                 | Memory write to  0FE <- 9B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:04          MREQ RD                    | Memory read from 005 -> 04\n#053H T8  AB:0FF DB:9E          MREQ    WR                 | Memory write to  0FF <- 9E\n#056H T11 AB:0FE DB:9B          MREQ    WR                 | Memory write to  0FE <- 9B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:05          MREQ RD                    | Memory read from 005 -> 05\n#053H T8  AB:0FF DB:9F          MREQ    WR                 | Memory write to  0FF <- 9F\n#056H T11 AB:0FE DB:9F          MREQ    WR                 | Memory write to  0FE <- 9F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:06          MREQ RD                    | Memory read from 005 -> 06\n#053H T8  AB:0FF DB:A0          MREQ    WR                 | Memory write to  0FF <- A0\n#056H T11 AB:0FE DB:A7          MREQ    WR                 | Memory write to  0FE <- A7\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:07          MREQ RD                    | Memory read from 005 -> 07\n#053H T8  AB:0FF DB:A1          MREQ    WR                 | Memory write to  0FF <- A1\n#056H T11 AB:0FE DB:A3          MREQ    WR                 | Memory write to  0FE <- A3\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:08          MREQ RD                    | Memory read from 005 -> 08\n#053H T8  AB:0FF DB:A2          MREQ    WR                 | Memory write to  0FF <- A2\n#056H T11 AB:0FE DB:A3          MREQ    WR                 | Memory write to  0FE <- A3\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:09          MREQ RD                    | Memory read from 005 -> 09\n#053H T8  AB:0FF DB:A3          MREQ    WR                 | Memory write to  0FF <- A3\n#056H T11 AB:0FE DB:A7          MREQ    WR                 | Memory write to  0FE <- A7\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:0A          MREQ RD                    | Memory read from 005 -> 0A\n#053H T8  AB:0FF DB:A4          MREQ    WR                 | Memory write to  0FF <- A4\n#056H T11 AB:0FE DB:A3          MREQ    WR                 | Memory write to  0FE <- A3\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:0B          MREQ RD                    | Memory read from 005 -> 0B\n#053H T8  AB:0FF DB:A5          MREQ    WR                 | Memory write to  0FF <- A5\n#056H T11 AB:0FE DB:A7          MREQ    WR                 | Memory write to  0FE <- A7\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:0C          MREQ RD                    | Memory read from 005 -> 0C\n#053H T8  AB:0FF DB:A6          MREQ    WR                 | Memory write to  0FF <- A6\n#056H T11 AB:0FE DB:A7          MREQ    WR                 | Memory write to  0FE <- A7\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:0D          MREQ RD                    | Memory read from 005 -> 0D\n#053H T8  AB:0FF DB:A7          MREQ    WR                 | Memory write to  0FF <- A7\n#056H T11 AB:0FE DB:A3          MREQ    WR                 | Memory write to  0FE <- A3\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:0E          MREQ RD                    | Memory read from 005 -> 0E\n#053H T8  AB:0FF DB:A8          MREQ    WR                 | Memory write to  0FF <- A8\n#056H T11 AB:0FE DB:AB          MREQ    WR                 | Memory write to  0FE <- AB\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:0F          MREQ RD                    | Memory read from 005 -> 0F\n#053H T8  AB:0FF DB:A9          MREQ    WR                 | Memory write to  0FF <- A9\n#056H T11 AB:0FE DB:AF          MREQ    WR                 | Memory write to  0FE <- AF\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:10          MREQ RD                    | Memory read from 005 -> 10\n#053H T8  AB:0FF DB:AA          MREQ    WR                 | Memory write to  0FF <- AA\n#056H T11 AB:0FE DB:BF          MREQ    WR                 | Memory write to  0FE <- BF\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:11          MREQ RD                    | Memory read from 005 -> 11\n#053H T8  AB:0FF DB:AB          MREQ    WR                 | Memory write to  0FF <- AB\n#056H T11 AB:0FE DB:BB          MREQ    WR                 | Memory write to  0FE <- BB\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:12          MREQ RD                    | Memory read from 005 -> 12\n#053H T8  AB:0FF DB:AC          MREQ    WR                 | Memory write to  0FF <- AC\n#056H T11 AB:0FE DB:BF          MREQ    WR                 | Memory write to  0FE <- BF\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:13          MREQ RD                    | Memory read from 005 -> 13\n#053H T8  AB:0FF DB:AD          MREQ    WR                 | Memory write to  0FF <- AD\n#056H T11 AB:0FE DB:BB          MREQ    WR                 | Memory write to  0FE <- BB\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:14          MREQ RD                    | Memory read from 005 -> 14\n#053H T8  AB:0FF DB:AE          MREQ    WR                 | Memory write to  0FF <- AE\n#056H T11 AB:0FE DB:BB          MREQ    WR                 | Memory write to  0FE <- BB\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:15          MREQ RD                    | Memory read from 005 -> 15\n#053H T8  AB:0FF DB:AF          MREQ    WR                 | Memory write to  0FF <- AF\n#056H T11 AB:0FE DB:BF          MREQ    WR                 | Memory write to  0FE <- BF\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:16          MREQ RD                    | Memory read from 005 -> 16\n#053H T8  AB:0FF DB:B0          MREQ    WR                 | Memory write to  0FF <- B0\n#056H T11 AB:0FE DB:A3          MREQ    WR                 | Memory write to  0FE <- A3\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:17          MREQ RD                    | Memory read from 005 -> 17\n#053H T8  AB:0FF DB:B1          MREQ    WR                 | Memory write to  0FF <- B1\n#056H T11 AB:0FE DB:A7          MREQ    WR                 | Memory write to  0FE <- A7\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:18          MREQ RD                    | Memory read from 005 -> 18\n#053H T8  AB:0FF DB:B2          MREQ    WR                 | Memory write to  0FF <- B2\n#056H T11 AB:0FE DB:A7          MREQ    WR                 | Memory write to  0FE <- A7\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:19          MREQ RD                    | Memory read from 005 -> 19\n#053H T8  AB:0FF DB:B3          MREQ    WR                 | Memory write to  0FF <- B3\n#056H T11 AB:0FE DB:A3          MREQ    WR                 | Memory write to  0FE <- A3\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:1A          MREQ RD                    | Memory read from 005 -> 1A\n#053H T8  AB:0FF DB:B4          MREQ    WR                 | Memory write to  0FF <- B4\n#056H T11 AB:0FE DB:A7          MREQ    WR                 | Memory write to  0FE <- A7\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:1B          MREQ RD                    | Memory read from 005 -> 1B\n#053H T8  AB:0FF DB:B5          MREQ    WR                 | Memory write to  0FF <- B5\n#056H T11 AB:0FE DB:A3          MREQ    WR                 | Memory write to  0FE <- A3\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:1C          MREQ RD                    | Memory read from 005 -> 1C\n#053H T8  AB:0FF DB:B6          MREQ    WR                 | Memory write to  0FF <- B6\n#056H T11 AB:0FE DB:A3          MREQ    WR                 | Memory write to  0FE <- A3\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:1D          MREQ RD                    | Memory read from 005 -> 1D\n#053H T8  AB:0FF DB:B7          MREQ    WR                 | Memory write to  0FF <- B7\n#056H T11 AB:0FE DB:A7          MREQ    WR                 | Memory write to  0FE <- A7\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:1E          MREQ RD                    | Memory read from 005 -> 1E\n#053H T8  AB:0FF DB:B8          MREQ    WR                 | Memory write to  0FF <- B8\n#056H T11 AB:0FE DB:AF          MREQ    WR                 | Memory write to  0FE <- AF\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:1F          MREQ RD                    | Memory read from 005 -> 1F\n#053H T8  AB:0FF DB:B9          MREQ    WR                 | Memory write to  0FF <- B9\n#056H T11 AB:0FE DB:AB          MREQ    WR                 | Memory write to  0FE <- AB\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:20          MREQ RD                    | Memory read from 005 -> 20\n#053H T8  AB:0FF DB:BA          MREQ    WR                 | Memory write to  0FF <- BA\n#056H T11 AB:0FE DB:BB          MREQ    WR                 | Memory write to  0FE <- BB\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:21          MREQ RD                    | Memory read from 005 -> 21\n#053H T8  AB:0FF DB:BB          MREQ    WR                 | Memory write to  0FF <- BB\n#056H T11 AB:0FE DB:BF          MREQ    WR                 | Memory write to  0FE <- BF\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:22          MREQ RD                    | Memory read from 005 -> 22\n#053H T8  AB:0FF DB:BC          MREQ    WR                 | Memory write to  0FF <- BC\n#056H T11 AB:0FE DB:BB          MREQ    WR                 | Memory write to  0FE <- BB\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:23          MREQ RD                    | Memory read from 005 -> 23\n#053H T8  AB:0FF DB:BD          MREQ    WR                 | Memory write to  0FF <- BD\n#056H T11 AB:0FE DB:BF          MREQ    WR                 | Memory write to  0FE <- BF\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:24          MREQ RD                    | Memory read from 005 -> 24\n#053H T8  AB:0FF DB:BE          MREQ    WR                 | Memory write to  0FF <- BE\n#056H T11 AB:0FE DB:BF          MREQ    WR                 | Memory write to  0FE <- BF\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:25          MREQ RD                    | Memory read from 005 -> 25\n#053H T8  AB:0FF DB:BF          MREQ    WR                 | Memory write to  0FF <- BF\n#056H T11 AB:0FE DB:BB          MREQ    WR                 | Memory write to  0FE <- BB\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:26          MREQ RD                    | Memory read from 005 -> 26\n#053H T8  AB:0FF DB:C0          MREQ    WR                 | Memory write to  0FF <- C0\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:27          MREQ RD                    | Memory read from 005 -> 27\n#053H T8  AB:0FF DB:C1          MREQ    WR                 | Memory write to  0FF <- C1\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:28          MREQ RD                    | Memory read from 005 -> 28\n#053H T8  AB:0FF DB:C2          MREQ    WR                 | Memory write to  0FF <- C2\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:29          MREQ RD                    | Memory read from 005 -> 29\n#053H T8  AB:0FF DB:C3          MREQ    WR                 | Memory write to  0FF <- C3\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:2A          MREQ RD                    | Memory read from 005 -> 2A\n#053H T8  AB:0FF DB:C4          MREQ    WR                 | Memory write to  0FF <- C4\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:2B          MREQ RD                    | Memory read from 005 -> 2B\n#053H T8  AB:0FF DB:C5          MREQ    WR                 | Memory write to  0FF <- C5\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:2C          MREQ RD                    | Memory read from 005 -> 2C\n#053H T8  AB:0FF DB:C6          MREQ    WR                 | Memory write to  0FF <- C6\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:2D          MREQ RD                    | Memory read from 005 -> 2D\n#053H T8  AB:0FF DB:C7          MREQ    WR                 | Memory write to  0FF <- C7\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:2E          MREQ RD                    | Memory read from 005 -> 2E\n#053H T8  AB:0FF DB:C8          MREQ    WR                 | Memory write to  0FF <- C8\n#056H T11 AB:0FE DB:8B          MREQ    WR                 | Memory write to  0FE <- 8B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:2F          MREQ RD                    | Memory read from 005 -> 2F\n#053H T8  AB:0FF DB:C9          MREQ    WR                 | Memory write to  0FF <- C9\n#056H T11 AB:0FE DB:8F          MREQ    WR                 | Memory write to  0FE <- 8F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:30          MREQ RD                    | Memory read from 005 -> 30\n#053H T8  AB:0FF DB:CA          MREQ    WR                 | Memory write to  0FF <- CA\n#056H T11 AB:0FE DB:9F          MREQ    WR                 | Memory write to  0FE <- 9F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:31          MREQ RD                    | Memory read from 005 -> 31\n#053H T8  AB:0FF DB:CB          MREQ    WR                 | Memory write to  0FF <- CB\n#056H T11 AB:0FE DB:9B          MREQ    WR                 | Memory write to  0FE <- 9B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:32          MREQ RD                    | Memory read from 005 -> 32\n#053H T8  AB:0FF DB:CC          MREQ    WR                 | Memory write to  0FF <- CC\n#056H T11 AB:0FE DB:9F          MREQ    WR                 | Memory write to  0FE <- 9F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:33          MREQ RD                    | Memory read from 005 -> 33\n#053H T8  AB:0FF DB:CD          MREQ    WR                 | Memory write to  0FF <- CD\n#056H T11 AB:0FE DB:9B          MREQ    WR                 | Memory write to  0FE <- 9B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:34          MREQ RD                    | Memory read from 005 -> 34\n#053H T8  AB:0FF DB:CE          MREQ    WR                 | Memory write to  0FF <- CE\n#056H T11 AB:0FE DB:9B          MREQ    WR                 | Memory write to  0FE <- 9B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:35          MREQ RD                    | Memory read from 005 -> 35\n#053H T8  AB:0FF DB:CF          MREQ    WR                 | Memory write to  0FF <- CF\n#056H T11 AB:0FE DB:9F          MREQ    WR                 | Memory write to  0FE <- 9F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:36          MREQ RD                    | Memory read from 005 -> 36\n#053H T8  AB:0FF DB:D0          MREQ    WR                 | Memory write to  0FF <- D0\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:37          MREQ RD                    | Memory read from 005 -> 37\n#053H T8  AB:0FF DB:D1          MREQ    WR                 | Memory write to  0FF <- D1\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:38          MREQ RD                    | Memory read from 005 -> 38\n#053H T8  AB:0FF DB:D2          MREQ    WR                 | Memory write to  0FF <- D2\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:39          MREQ RD                    | Memory read from 005 -> 39\n#053H T8  AB:0FF DB:D3          MREQ    WR                 | Memory write to  0FF <- D3\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:3A          MREQ RD                    | Memory read from 005 -> 3A\n#053H T8  AB:0FF DB:D4          MREQ    WR                 | Memory write to  0FF <- D4\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:3B          MREQ RD                    | Memory read from 005 -> 3B\n#053H T8  AB:0FF DB:D5          MREQ    WR                 | Memory write to  0FF <- D5\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:3C          MREQ RD                    | Memory read from 005 -> 3C\n#053H T8  AB:0FF DB:D6          MREQ    WR                 | Memory write to  0FF <- D6\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:3D          MREQ RD                    | Memory read from 005 -> 3D\n#053H T8  AB:0FF DB:D7          MREQ    WR                 | Memory write to  0FF <- D7\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:3E          MREQ RD                    | Memory read from 005 -> 3E\n#053H T8  AB:0FF DB:D8          MREQ    WR                 | Memory write to  0FF <- D8\n#056H T11 AB:0FE DB:8F          MREQ    WR                 | Memory write to  0FE <- 8F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:3F          MREQ RD                    | Memory read from 005 -> 3F\n#053H T8  AB:0FF DB:D9          MREQ    WR                 | Memory write to  0FF <- D9\n#056H T11 AB:0FE DB:8B          MREQ    WR                 | Memory write to  0FE <- 8B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:40          MREQ RD                    | Memory read from 005 -> 40\n#053H T8  AB:0FF DB:DA          MREQ    WR                 | Memory write to  0FF <- DA\n#056H T11 AB:0FE DB:9B          MREQ    WR                 | Memory write to  0FE <- 9B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:41          MREQ RD                    | Memory read from 005 -> 41\n#053H T8  AB:0FF DB:DB          MREQ    WR                 | Memory write to  0FF <- DB\n#056H T11 AB:0FE DB:9F          MREQ    WR                 | Memory write to  0FE <- 9F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:42          MREQ RD                    | Memory read from 005 -> 42\n#053H T8  AB:0FF DB:DC          MREQ    WR                 | Memory write to  0FF <- DC\n#056H T11 AB:0FE DB:9B          MREQ    WR                 | Memory write to  0FE <- 9B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:43          MREQ RD                    | Memory read from 005 -> 43\n#053H T8  AB:0FF DB:DD          MREQ    WR                 | Memory write to  0FF <- DD\n#056H T11 AB:0FE DB:9F          MREQ    WR                 | Memory write to  0FE <- 9F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:44          MREQ RD                    | Memory read from 005 -> 44\n#053H T8  AB:0FF DB:DE          MREQ    WR                 | Memory write to  0FF <- DE\n#056H T11 AB:0FE DB:9F          MREQ    WR                 | Memory write to  0FE <- 9F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:45          MREQ RD                    | Memory read from 005 -> 45\n#053H T8  AB:0FF DB:DF          MREQ    WR                 | Memory write to  0FF <- DF\n#056H T11 AB:0FE DB:9B          MREQ    WR                 | Memory write to  0FE <- 9B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:46          MREQ RD                    | Memory read from 005 -> 46\n#053H T8  AB:0FF DB:E0          MREQ    WR                 | Memory write to  0FF <- E0\n#056H T11 AB:0FE DB:A3          MREQ    WR                 | Memory write to  0FE <- A3\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:47          MREQ RD                    | Memory read from 005 -> 47\n#053H T8  AB:0FF DB:E1          MREQ    WR                 | Memory write to  0FF <- E1\n#056H T11 AB:0FE DB:A7          MREQ    WR                 | Memory write to  0FE <- A7\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:48          MREQ RD                    | Memory read from 005 -> 48\n#053H T8  AB:0FF DB:E2          MREQ    WR                 | Memory write to  0FF <- E2\n#056H T11 AB:0FE DB:A7          MREQ    WR                 | Memory write to  0FE <- A7\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:49          MREQ RD                    | Memory read from 005 -> 49\n#053H T8  AB:0FF DB:E3          MREQ    WR                 | Memory write to  0FF <- E3\n#056H T11 AB:0FE DB:A3          MREQ    WR                 | Memory write to  0FE <- A3\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:4A          MREQ RD                    | Memory read from 005 -> 4A\n#053H T8  AB:0FF DB:E4          MREQ    WR                 | Memory write to  0FF <- E4\n#056H T11 AB:0FE DB:A7          MREQ    WR                 | Memory write to  0FE <- A7\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:4B          MREQ RD                    | Memory read from 005 -> 4B\n#053H T8  AB:0FF DB:E5          MREQ    WR                 | Memory write to  0FF <- E5\n#056H T11 AB:0FE DB:A3          MREQ    WR                 | Memory write to  0FE <- A3\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:4C          MREQ RD                    | Memory read from 005 -> 4C\n#053H T8  AB:0FF DB:E6          MREQ    WR                 | Memory write to  0FF <- E6\n#056H T11 AB:0FE DB:A3          MREQ    WR                 | Memory write to  0FE <- A3\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:4D          MREQ RD                    | Memory read from 005 -> 4D\n#053H T8  AB:0FF DB:E7          MREQ    WR                 | Memory write to  0FF <- E7\n#056H T11 AB:0FE DB:A7          MREQ    WR                 | Memory write to  0FE <- A7\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:4E          MREQ RD                    | Memory read from 005 -> 4E\n#053H T8  AB:0FF DB:E8          MREQ    WR                 | Memory write to  0FF <- E8\n#056H T11 AB:0FE DB:AF          MREQ    WR                 | Memory write to  0FE <- AF\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:4F          MREQ RD                    | Memory read from 005 -> 4F\n#053H T8  AB:0FF DB:E9          MREQ    WR                 | Memory write to  0FF <- E9\n#056H T11 AB:0FE DB:AB          MREQ    WR                 | Memory write to  0FE <- AB\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:50          MREQ RD                    | Memory read from 005 -> 50\n#053H T8  AB:0FF DB:EA          MREQ    WR                 | Memory write to  0FF <- EA\n#056H T11 AB:0FE DB:BB          MREQ    WR                 | Memory write to  0FE <- BB\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:51          MREQ RD                    | Memory read from 005 -> 51\n#053H T8  AB:0FF DB:EB          MREQ    WR                 | Memory write to  0FF <- EB\n#056H T11 AB:0FE DB:BF          MREQ    WR                 | Memory write to  0FE <- BF\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:52          MREQ RD                    | Memory read from 005 -> 52\n#053H T8  AB:0FF DB:EC          MREQ    WR                 | Memory write to  0FF <- EC\n#056H T11 AB:0FE DB:BB          MREQ    WR                 | Memory write to  0FE <- BB\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:53          MREQ RD                    | Memory read from 005 -> 53\n#053H T8  AB:0FF DB:ED          MREQ    WR                 | Memory write to  0FF <- ED\n#056H T11 AB:0FE DB:BF          MREQ    WR                 | Memory write to  0FE <- BF\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:54          MREQ RD                    | Memory read from 005 -> 54\n#053H T8  AB:0FF DB:EE          MREQ    WR                 | Memory write to  0FF <- EE\n#056H T11 AB:0FE DB:BF          MREQ    WR                 | Memory write to  0FE <- BF\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:55          MREQ RD                    | Memory read from 005 -> 55\n#053H T8  AB:0FF DB:EF          MREQ    WR                 | Memory write to  0FF <- EF\n#056H T11 AB:0FE DB:BB          MREQ    WR                 | Memory write to  0FE <- BB\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:56          MREQ RD                    | Memory read from 005 -> 56\n#053H T8  AB:0FF DB:F0          MREQ    WR                 | Memory write to  0FF <- F0\n#056H T11 AB:0FE DB:A7          MREQ    WR                 | Memory write to  0FE <- A7\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:57          MREQ RD                    | Memory read from 005 -> 57\n#053H T8  AB:0FF DB:F1          MREQ    WR                 | Memory write to  0FF <- F1\n#056H T11 AB:0FE DB:A3          MREQ    WR                 | Memory write to  0FE <- A3\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:58          MREQ RD                    | Memory read from 005 -> 58\n#053H T8  AB:0FF DB:F2          MREQ    WR                 | Memory write to  0FF <- F2\n#056H T11 AB:0FE DB:A3          MREQ    WR                 | Memory write to  0FE <- A3\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:59          MREQ RD                    | Memory read from 005 -> 59\n#053H T8  AB:0FF DB:F3          MREQ    WR                 | Memory write to  0FF <- F3\n#056H T11 AB:0FE DB:A7          MREQ    WR                 | Memory write to  0FE <- A7\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:5A          MREQ RD                    | Memory read from 005 -> 5A\n#053H T8  AB:0FF DB:F4          MREQ    WR                 | Memory write to  0FF <- F4\n#056H T11 AB:0FE DB:A3          MREQ    WR                 | Memory write to  0FE <- A3\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:5B          MREQ RD                    | Memory read from 005 -> 5B\n#053H T8  AB:0FF DB:F5          MREQ    WR                 | Memory write to  0FF <- F5\n#056H T11 AB:0FE DB:A7          MREQ    WR                 | Memory write to  0FE <- A7\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:5C          MREQ RD                    | Memory read from 005 -> 5C\n#053H T8  AB:0FF DB:F6          MREQ    WR                 | Memory write to  0FF <- F6\n#056H T11 AB:0FE DB:A7          MREQ    WR                 | Memory write to  0FE <- A7\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:5D          MREQ RD                    | Memory read from 005 -> 5D\n#053H T8  AB:0FF DB:F7          MREQ    WR                 | Memory write to  0FF <- F7\n#056H T11 AB:0FE DB:A3          MREQ    WR                 | Memory write to  0FE <- A3\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:5E          MREQ RD                    | Memory read from 005 -> 5E\n#053H T8  AB:0FF DB:F8          MREQ    WR                 | Memory write to  0FF <- F8\n#056H T11 AB:0FE DB:AB          MREQ    WR                 | Memory write to  0FE <- AB\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:5F          MREQ RD                    | Memory read from 005 -> 5F\n#053H T8  AB:0FF DB:F9          MREQ    WR                 | Memory write to  0FF <- F9\n#056H T11 AB:0FE DB:AF          MREQ    WR                 | Memory write to  0FE <- AF\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:60          MREQ RD                    | Memory read from 005 -> 60\n#053H T8  AB:0FF DB:FA          MREQ    WR                 | Memory write to  0FF <- FA\n#056H T11 AB:0FE DB:BF          MREQ    WR                 | Memory write to  0FE <- BF\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:61          MREQ RD                    | Memory read from 005 -> 61\n#053H T8  AB:0FF DB:FB          MREQ    WR                 | Memory write to  0FF <- FB\n#056H T11 AB:0FE DB:BB          MREQ    WR                 | Memory write to  0FE <- BB\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:62          MREQ RD                    | Memory read from 005 -> 62\n#053H T8  AB:0FF DB:FC          MREQ    WR                 | Memory write to  0FF <- FC\n#056H T11 AB:0FE DB:BF          MREQ    WR                 | Memory write to  0FE <- BF\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:63          MREQ RD                    | Memory read from 005 -> 63\n#053H T8  AB:0FF DB:FD          MREQ    WR                 | Memory write to  0FF <- FD\n#056H T11 AB:0FE DB:BB          MREQ    WR                 | Memory write to  0FE <- BB\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:64          MREQ RD                    | Memory read from 005 -> 64\n#053H T8  AB:0FF DB:FE          MREQ    WR                 | Memory write to  0FF <- FE\n#056H T11 AB:0FE DB:BB          MREQ    WR                 | Memory write to  0FE <- BB\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:65          MREQ RD                    | Memory read from 005 -> 65\n#053H T8  AB:0FF DB:FF          MREQ    WR                 | Memory write to  0FF <- FF\n#056H T11 AB:0FE DB:BF          MREQ    WR                 | Memory write to  0FE <- BF\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:66          MREQ RD                    | Memory read from 005 -> 66\n#053H T8  AB:0FF DB:00          MREQ    WR                 | Memory write to  0FF <- 00\n#056H T11 AB:0FE DB:47          MREQ    WR                 | Memory write to  0FE <- 47\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:67          MREQ RD                    | Memory read from 005 -> 67\n#053H T8  AB:0FF DB:01          MREQ    WR                 | Memory write to  0FF <- 01\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:68          MREQ RD                    | Memory read from 005 -> 68\n#053H T8  AB:0FF DB:02          MREQ    WR                 | Memory write to  0FF <- 02\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:69          MREQ RD                    | Memory read from 005 -> 69\n#053H T8  AB:0FF DB:03          MREQ    WR                 | Memory write to  0FF <- 03\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:6A          MREQ RD                    | Memory read from 005 -> 6A\n#053H T8  AB:0FF DB:04          MREQ    WR                 | Memory write to  0FF <- 04\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:6B          MREQ RD                    | Memory read from 005 -> 6B\n#053H T8  AB:0FF DB:05          MREQ    WR                 | Memory write to  0FF <- 05\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:6C          MREQ RD                    | Memory read from 005 -> 6C\n#053H T8  AB:0FF DB:06          MREQ    WR                 | Memory write to  0FF <- 06\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:6D          MREQ RD                    | Memory read from 005 -> 6D\n#053H T8  AB:0FF DB:07          MREQ    WR                 | Memory write to  0FF <- 07\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:6E          MREQ RD                    | Memory read from 005 -> 6E\n#053H T8  AB:0FF DB:08          MREQ    WR                 | Memory write to  0FF <- 08\n#056H T11 AB:0FE DB:0B          MREQ    WR                 | Memory write to  0FE <- 0B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:6F          MREQ RD                    | Memory read from 005 -> 6F\n#053H T8  AB:0FF DB:09          MREQ    WR                 | Memory write to  0FF <- 09\n#056H T11 AB:0FE DB:0F          MREQ    WR                 | Memory write to  0FE <- 0F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:70          MREQ RD                    | Memory read from 005 -> 70\n#053H T8  AB:0FF DB:0A          MREQ    WR                 | Memory write to  0FF <- 0A\n#056H T11 AB:0FE DB:1F          MREQ    WR                 | Memory write to  0FE <- 1F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:71          MREQ RD                    | Memory read from 005 -> 71\n#053H T8  AB:0FF DB:0B          MREQ    WR                 | Memory write to  0FF <- 0B\n#056H T11 AB:0FE DB:1B          MREQ    WR                 | Memory write to  0FE <- 1B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:72          MREQ RD                    | Memory read from 005 -> 72\n#053H T8  AB:0FF DB:0C          MREQ    WR                 | Memory write to  0FF <- 0C\n#056H T11 AB:0FE DB:1F          MREQ    WR                 | Memory write to  0FE <- 1F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:73          MREQ RD                    | Memory read from 005 -> 73\n#053H T8  AB:0FF DB:0D          MREQ    WR                 | Memory write to  0FF <- 0D\n#056H T11 AB:0FE DB:1B          MREQ    WR                 | Memory write to  0FE <- 1B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:74          MREQ RD                    | Memory read from 005 -> 74\n#053H T8  AB:0FF DB:0E          MREQ    WR                 | Memory write to  0FF <- 0E\n#056H T11 AB:0FE DB:1B          MREQ    WR                 | Memory write to  0FE <- 1B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:75          MREQ RD                    | Memory read from 005 -> 75\n#053H T8  AB:0FF DB:0F          MREQ    WR                 | Memory write to  0FF <- 0F\n#056H T11 AB:0FE DB:1F          MREQ    WR                 | Memory write to  0FE <- 1F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:76          MREQ RD                    | Memory read from 005 -> 76\n#053H T8  AB:0FF DB:10          MREQ    WR                 | Memory write to  0FF <- 10\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:77          MREQ RD                    | Memory read from 005 -> 77\n#053H T8  AB:0FF DB:11          MREQ    WR                 | Memory write to  0FF <- 11\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:78          MREQ RD                    | Memory read from 005 -> 78\n#053H T8  AB:0FF DB:12          MREQ    WR                 | Memory write to  0FF <- 12\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:79          MREQ RD                    | Memory read from 005 -> 79\n#053H T8  AB:0FF DB:13          MREQ    WR                 | Memory write to  0FF <- 13\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:7A          MREQ RD                    | Memory read from 005 -> 7A\n#053H T8  AB:0FF DB:14          MREQ    WR                 | Memory write to  0FF <- 14\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:7B          MREQ RD                    | Memory read from 005 -> 7B\n#053H T8  AB:0FF DB:15          MREQ    WR                 | Memory write to  0FF <- 15\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:7C          MREQ RD                    | Memory read from 005 -> 7C\n#053H T8  AB:0FF DB:16          MREQ    WR                 | Memory write to  0FF <- 16\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:7D          MREQ RD                    | Memory read from 005 -> 7D\n#053H T8  AB:0FF DB:17          MREQ    WR                 | Memory write to  0FF <- 17\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:7E          MREQ RD                    | Memory read from 005 -> 7E\n#053H T8  AB:0FF DB:18          MREQ    WR                 | Memory write to  0FF <- 18\n#056H T11 AB:0FE DB:0F          MREQ    WR                 | Memory write to  0FE <- 0F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:7F          MREQ RD                    | Memory read from 005 -> 7F\n#053H T8  AB:0FF DB:19          MREQ    WR                 | Memory write to  0FF <- 19\n#056H T11 AB:0FE DB:0B          MREQ    WR                 | Memory write to  0FE <- 0B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:80          MREQ RD                    | Memory read from 005 -> 80\n#053H T8  AB:0FF DB:1A          MREQ    WR                 | Memory write to  0FF <- 1A\n#056H T11 AB:0FE DB:1B          MREQ    WR                 | Memory write to  0FE <- 1B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:81          MREQ RD                    | Memory read from 005 -> 81\n#053H T8  AB:0FF DB:1B          MREQ    WR                 | Memory write to  0FF <- 1B\n#056H T11 AB:0FE DB:1F          MREQ    WR                 | Memory write to  0FE <- 1F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:82          MREQ RD                    | Memory read from 005 -> 82\n#053H T8  AB:0FF DB:1C          MREQ    WR                 | Memory write to  0FF <- 1C\n#056H T11 AB:0FE DB:1B          MREQ    WR                 | Memory write to  0FE <- 1B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:83          MREQ RD                    | Memory read from 005 -> 83\n#053H T8  AB:0FF DB:1D          MREQ    WR                 | Memory write to  0FF <- 1D\n#056H T11 AB:0FE DB:1F          MREQ    WR                 | Memory write to  0FE <- 1F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:84          MREQ RD                    | Memory read from 005 -> 84\n#053H T8  AB:0FF DB:1E          MREQ    WR                 | Memory write to  0FF <- 1E\n#056H T11 AB:0FE DB:1F          MREQ    WR                 | Memory write to  0FE <- 1F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:85          MREQ RD                    | Memory read from 005 -> 85\n#053H T8  AB:0FF DB:1F          MREQ    WR                 | Memory write to  0FF <- 1F\n#056H T11 AB:0FE DB:1B          MREQ    WR                 | Memory write to  0FE <- 1B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:86          MREQ RD                    | Memory read from 005 -> 86\n#053H T8  AB:0FF DB:20          MREQ    WR                 | Memory write to  0FF <- 20\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:87          MREQ RD                    | Memory read from 005 -> 87\n#053H T8  AB:0FF DB:21          MREQ    WR                 | Memory write to  0FF <- 21\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:88          MREQ RD                    | Memory read from 005 -> 88\n#053H T8  AB:0FF DB:22          MREQ    WR                 | Memory write to  0FF <- 22\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:89          MREQ RD                    | Memory read from 005 -> 89\n#053H T8  AB:0FF DB:23          MREQ    WR                 | Memory write to  0FF <- 23\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:8A          MREQ RD                    | Memory read from 005 -> 8A\n#053H T8  AB:0FF DB:24          MREQ    WR                 | Memory write to  0FF <- 24\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:8B          MREQ RD                    | Memory read from 005 -> 8B\n#053H T8  AB:0FF DB:25          MREQ    WR                 | Memory write to  0FF <- 25\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:8C          MREQ RD                    | Memory read from 005 -> 8C\n#053H T8  AB:0FF DB:26          MREQ    WR                 | Memory write to  0FF <- 26\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:8D          MREQ RD                    | Memory read from 005 -> 8D\n#053H T8  AB:0FF DB:27          MREQ    WR                 | Memory write to  0FF <- 27\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:8E          MREQ RD                    | Memory read from 005 -> 8E\n#053H T8  AB:0FF DB:28          MREQ    WR                 | Memory write to  0FF <- 28\n#056H T11 AB:0FE DB:2F          MREQ    WR                 | Memory write to  0FE <- 2F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:8F          MREQ RD                    | Memory read from 005 -> 8F\n#053H T8  AB:0FF DB:29          MREQ    WR                 | Memory write to  0FF <- 29\n#056H T11 AB:0FE DB:2B          MREQ    WR                 | Memory write to  0FE <- 2B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:90          MREQ RD                    | Memory read from 005 -> 90\n#053H T8  AB:0FF DB:2A          MREQ    WR                 | Memory write to  0FF <- 2A\n#056H T11 AB:0FE DB:3B          MREQ    WR                 | Memory write to  0FE <- 3B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:91          MREQ RD                    | Memory read from 005 -> 91\n#053H T8  AB:0FF DB:2B          MREQ    WR                 | Memory write to  0FF <- 2B\n#056H T11 AB:0FE DB:3F          MREQ    WR                 | Memory write to  0FE <- 3F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:92          MREQ RD                    | Memory read from 005 -> 92\n#053H T8  AB:0FF DB:2C          MREQ    WR                 | Memory write to  0FF <- 2C\n#056H T11 AB:0FE DB:3B          MREQ    WR                 | Memory write to  0FE <- 3B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:93          MREQ RD                    | Memory read from 005 -> 93\n#053H T8  AB:0FF DB:2D          MREQ    WR                 | Memory write to  0FF <- 2D\n#056H T11 AB:0FE DB:3F          MREQ    WR                 | Memory write to  0FE <- 3F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:94          MREQ RD                    | Memory read from 005 -> 94\n#053H T8  AB:0FF DB:2E          MREQ    WR                 | Memory write to  0FF <- 2E\n#056H T11 AB:0FE DB:3F          MREQ    WR                 | Memory write to  0FE <- 3F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:95          MREQ RD                    | Memory read from 005 -> 95\n#053H T8  AB:0FF DB:2F          MREQ    WR                 | Memory write to  0FF <- 2F\n#056H T11 AB:0FE DB:3B          MREQ    WR                 | Memory write to  0FE <- 3B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:96          MREQ RD                    | Memory read from 005 -> 96\n#053H T8  AB:0FF DB:30          MREQ    WR                 | Memory write to  0FF <- 30\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:97          MREQ RD                    | Memory read from 005 -> 97\n#053H T8  AB:0FF DB:31          MREQ    WR                 | Memory write to  0FF <- 31\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:98          MREQ RD                    | Memory read from 005 -> 98\n#053H T8  AB:0FF DB:32          MREQ    WR                 | Memory write to  0FF <- 32\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:99          MREQ RD                    | Memory read from 005 -> 99\n#053H T8  AB:0FF DB:33          MREQ    WR                 | Memory write to  0FF <- 33\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:9A          MREQ RD                    | Memory read from 005 -> 9A\n#053H T8  AB:0FF DB:34          MREQ    WR                 | Memory write to  0FF <- 34\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:9B          MREQ RD                    | Memory read from 005 -> 9B\n#053H T8  AB:0FF DB:35          MREQ    WR                 | Memory write to  0FF <- 35\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:9C          MREQ RD                    | Memory read from 005 -> 9C\n#053H T8  AB:0FF DB:36          MREQ    WR                 | Memory write to  0FF <- 36\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:9D          MREQ RD                    | Memory read from 005 -> 9D\n#053H T8  AB:0FF DB:37          MREQ    WR                 | Memory write to  0FF <- 37\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:9E          MREQ RD                    | Memory read from 005 -> 9E\n#053H T8  AB:0FF DB:38          MREQ    WR                 | Memory write to  0FF <- 38\n#056H T11 AB:0FE DB:2B          MREQ    WR                 | Memory write to  0FE <- 2B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:9F          MREQ RD                    | Memory read from 005 -> 9F\n#053H T8  AB:0FF DB:39          MREQ    WR                 | Memory write to  0FF <- 39\n#056H T11 AB:0FE DB:2F          MREQ    WR                 | Memory write to  0FE <- 2F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:A0          MREQ RD                    | Memory read from 005 -> A0\n#053H T8  AB:0FF DB:3A          MREQ    WR                 | Memory write to  0FF <- 3A\n#056H T11 AB:0FE DB:3F          MREQ    WR                 | Memory write to  0FE <- 3F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:A1          MREQ RD                    | Memory read from 005 -> A1\n#053H T8  AB:0FF DB:3B          MREQ    WR                 | Memory write to  0FF <- 3B\n#056H T11 AB:0FE DB:3B          MREQ    WR                 | Memory write to  0FE <- 3B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:A2          MREQ RD                    | Memory read from 005 -> A2\n#053H T8  AB:0FF DB:3C          MREQ    WR                 | Memory write to  0FF <- 3C\n#056H T11 AB:0FE DB:3F          MREQ    WR                 | Memory write to  0FE <- 3F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:A3          MREQ RD                    | Memory read from 005 -> A3\n#053H T8  AB:0FF DB:3D          MREQ    WR                 | Memory write to  0FF <- 3D\n#056H T11 AB:0FE DB:3B          MREQ    WR                 | Memory write to  0FE <- 3B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:A4          MREQ RD                    | Memory read from 005 -> A4\n#053H T8  AB:0FF DB:3E          MREQ    WR                 | Memory write to  0FF <- 3E\n#056H T11 AB:0FE DB:3B          MREQ    WR                 | Memory write to  0FE <- 3B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:A5          MREQ RD                    | Memory read from 005 -> A5\n#053H T8  AB:0FF DB:3F          MREQ    WR                 | Memory write to  0FF <- 3F\n#056H T11 AB:0FE DB:3F          MREQ    WR                 | Memory write to  0FE <- 3F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:A6          MREQ RD                    | Memory read from 005 -> A6\n#053H T8  AB:0FF DB:40          MREQ    WR                 | Memory write to  0FF <- 40\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:A7          MREQ RD                    | Memory read from 005 -> A7\n#053H T8  AB:0FF DB:41          MREQ    WR                 | Memory write to  0FF <- 41\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:A8          MREQ RD                    | Memory read from 005 -> A8\n#053H T8  AB:0FF DB:42          MREQ    WR                 | Memory write to  0FF <- 42\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:A9          MREQ RD                    | Memory read from 005 -> A9\n#053H T8  AB:0FF DB:43          MREQ    WR                 | Memory write to  0FF <- 43\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:AA          MREQ RD                    | Memory read from 005 -> AA\n#053H T8  AB:0FF DB:44          MREQ    WR                 | Memory write to  0FF <- 44\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:AB          MREQ RD                    | Memory read from 005 -> AB\n#053H T8  AB:0FF DB:45          MREQ    WR                 | Memory write to  0FF <- 45\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:AC          MREQ RD                    | Memory read from 005 -> AC\n#053H T8  AB:0FF DB:46          MREQ    WR                 | Memory write to  0FF <- 46\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:AD          MREQ RD                    | Memory read from 005 -> AD\n#053H T8  AB:0FF DB:47          MREQ    WR                 | Memory write to  0FF <- 47\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:AE          MREQ RD                    | Memory read from 005 -> AE\n#053H T8  AB:0FF DB:48          MREQ    WR                 | Memory write to  0FF <- 48\n#056H T11 AB:0FE DB:0F          MREQ    WR                 | Memory write to  0FE <- 0F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:AF          MREQ RD                    | Memory read from 005 -> AF\n#053H T8  AB:0FF DB:49          MREQ    WR                 | Memory write to  0FF <- 49\n#056H T11 AB:0FE DB:0B          MREQ    WR                 | Memory write to  0FE <- 0B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:B0          MREQ RD                    | Memory read from 005 -> B0\n#053H T8  AB:0FF DB:4A          MREQ    WR                 | Memory write to  0FF <- 4A\n#056H T11 AB:0FE DB:1B          MREQ    WR                 | Memory write to  0FE <- 1B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:B1          MREQ RD                    | Memory read from 005 -> B1\n#053H T8  AB:0FF DB:4B          MREQ    WR                 | Memory write to  0FF <- 4B\n#056H T11 AB:0FE DB:1F          MREQ    WR                 | Memory write to  0FE <- 1F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:B2          MREQ RD                    | Memory read from 005 -> B2\n#053H T8  AB:0FF DB:4C          MREQ    WR                 | Memory write to  0FF <- 4C\n#056H T11 AB:0FE DB:1B          MREQ    WR                 | Memory write to  0FE <- 1B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:B3          MREQ RD                    | Memory read from 005 -> B3\n#053H T8  AB:0FF DB:4D          MREQ    WR                 | Memory write to  0FF <- 4D\n#056H T11 AB:0FE DB:1F          MREQ    WR                 | Memory write to  0FE <- 1F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:B4          MREQ RD                    | Memory read from 005 -> B4\n#053H T8  AB:0FF DB:4E          MREQ    WR                 | Memory write to  0FF <- 4E\n#056H T11 AB:0FE DB:1F          MREQ    WR                 | Memory write to  0FE <- 1F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:B5          MREQ RD                    | Memory read from 005 -> B5\n#053H T8  AB:0FF DB:4F          MREQ    WR                 | Memory write to  0FF <- 4F\n#056H T11 AB:0FE DB:1B          MREQ    WR                 | Memory write to  0FE <- 1B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:B6          MREQ RD                    | Memory read from 005 -> B6\n#053H T8  AB:0FF DB:50          MREQ    WR                 | Memory write to  0FF <- 50\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:B7          MREQ RD                    | Memory read from 005 -> B7\n#053H T8  AB:0FF DB:51          MREQ    WR                 | Memory write to  0FF <- 51\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:B8          MREQ RD                    | Memory read from 005 -> B8\n#053H T8  AB:0FF DB:52          MREQ    WR                 | Memory write to  0FF <- 52\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:B9          MREQ RD                    | Memory read from 005 -> B9\n#053H T8  AB:0FF DB:53          MREQ    WR                 | Memory write to  0FF <- 53\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:BA          MREQ RD                    | Memory read from 005 -> BA\n#053H T8  AB:0FF DB:54          MREQ    WR                 | Memory write to  0FF <- 54\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:BB          MREQ RD                    | Memory read from 005 -> BB\n#053H T8  AB:0FF DB:55          MREQ    WR                 | Memory write to  0FF <- 55\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:BC          MREQ RD                    | Memory read from 005 -> BC\n#053H T8  AB:0FF DB:56          MREQ    WR                 | Memory write to  0FF <- 56\n#056H T11 AB:0FE DB:07          MREQ    WR                 | Memory write to  0FE <- 07\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:BD          MREQ RD                    | Memory read from 005 -> BD\n#053H T8  AB:0FF DB:57          MREQ    WR                 | Memory write to  0FF <- 57\n#056H T11 AB:0FE DB:03          MREQ    WR                 | Memory write to  0FE <- 03\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:BE          MREQ RD                    | Memory read from 005 -> BE\n#053H T8  AB:0FF DB:58          MREQ    WR                 | Memory write to  0FF <- 58\n#056H T11 AB:0FE DB:0B          MREQ    WR                 | Memory write to  0FE <- 0B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:BF          MREQ RD                    | Memory read from 005 -> BF\n#053H T8  AB:0FF DB:59          MREQ    WR                 | Memory write to  0FF <- 59\n#056H T11 AB:0FE DB:0F          MREQ    WR                 | Memory write to  0FE <- 0F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:C0          MREQ RD                    | Memory read from 005 -> C0\n#053H T8  AB:0FF DB:5A          MREQ    WR                 | Memory write to  0FF <- 5A\n#056H T11 AB:0FE DB:1F          MREQ    WR                 | Memory write to  0FE <- 1F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:C1          MREQ RD                    | Memory read from 005 -> C1\n#053H T8  AB:0FF DB:5B          MREQ    WR                 | Memory write to  0FF <- 5B\n#056H T11 AB:0FE DB:1B          MREQ    WR                 | Memory write to  0FE <- 1B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:C2          MREQ RD                    | Memory read from 005 -> C2\n#053H T8  AB:0FF DB:5C          MREQ    WR                 | Memory write to  0FF <- 5C\n#056H T11 AB:0FE DB:1F          MREQ    WR                 | Memory write to  0FE <- 1F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:C3          MREQ RD                    | Memory read from 005 -> C3\n#053H T8  AB:0FF DB:5D          MREQ    WR                 | Memory write to  0FF <- 5D\n#056H T11 AB:0FE DB:1B          MREQ    WR                 | Memory write to  0FE <- 1B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:C4          MREQ RD                    | Memory read from 005 -> C4\n#053H T8  AB:0FF DB:5E          MREQ    WR                 | Memory write to  0FF <- 5E\n#056H T11 AB:0FE DB:1B          MREQ    WR                 | Memory write to  0FE <- 1B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:C5          MREQ RD                    | Memory read from 005 -> C5\n#053H T8  AB:0FF DB:5F          MREQ    WR                 | Memory write to  0FF <- 5F\n#056H T11 AB:0FE DB:1F          MREQ    WR                 | Memory write to  0FE <- 1F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:C6          MREQ RD                    | Memory read from 005 -> C6\n#053H T8  AB:0FF DB:60          MREQ    WR                 | Memory write to  0FF <- 60\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:C7          MREQ RD                    | Memory read from 005 -> C7\n#053H T8  AB:0FF DB:61          MREQ    WR                 | Memory write to  0FF <- 61\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:C8          MREQ RD                    | Memory read from 005 -> C8\n#053H T8  AB:0FF DB:62          MREQ    WR                 | Memory write to  0FF <- 62\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:C9          MREQ RD                    | Memory read from 005 -> C9\n#053H T8  AB:0FF DB:63          MREQ    WR                 | Memory write to  0FF <- 63\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:CA          MREQ RD                    | Memory read from 005 -> CA\n#053H T8  AB:0FF DB:64          MREQ    WR                 | Memory write to  0FF <- 64\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:CB          MREQ RD                    | Memory read from 005 -> CB\n#053H T8  AB:0FF DB:65          MREQ    WR                 | Memory write to  0FF <- 65\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:CC          MREQ RD                    | Memory read from 005 -> CC\n#053H T8  AB:0FF DB:66          MREQ    WR                 | Memory write to  0FF <- 66\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:CD          MREQ RD                    | Memory read from 005 -> CD\n#053H T8  AB:0FF DB:67          MREQ    WR                 | Memory write to  0FF <- 67\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:CE          MREQ RD                    | Memory read from 005 -> CE\n#053H T8  AB:0FF DB:68          MREQ    WR                 | Memory write to  0FF <- 68\n#056H T11 AB:0FE DB:2B          MREQ    WR                 | Memory write to  0FE <- 2B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:CF          MREQ RD                    | Memory read from 005 -> CF\n#053H T8  AB:0FF DB:69          MREQ    WR                 | Memory write to  0FF <- 69\n#056H T11 AB:0FE DB:2F          MREQ    WR                 | Memory write to  0FE <- 2F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:D0          MREQ RD                    | Memory read from 005 -> D0\n#053H T8  AB:0FF DB:6A          MREQ    WR                 | Memory write to  0FF <- 6A\n#056H T11 AB:0FE DB:3F          MREQ    WR                 | Memory write to  0FE <- 3F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:D1          MREQ RD                    | Memory read from 005 -> D1\n#053H T8  AB:0FF DB:6B          MREQ    WR                 | Memory write to  0FF <- 6B\n#056H T11 AB:0FE DB:3B          MREQ    WR                 | Memory write to  0FE <- 3B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:D2          MREQ RD                    | Memory read from 005 -> D2\n#053H T8  AB:0FF DB:6C          MREQ    WR                 | Memory write to  0FF <- 6C\n#056H T11 AB:0FE DB:3F          MREQ    WR                 | Memory write to  0FE <- 3F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:D3          MREQ RD                    | Memory read from 005 -> D3\n#053H T8  AB:0FF DB:6D          MREQ    WR                 | Memory write to  0FF <- 6D\n#056H T11 AB:0FE DB:3B          MREQ    WR                 | Memory write to  0FE <- 3B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:D4          MREQ RD                    | Memory read from 005 -> D4\n#053H T8  AB:0FF DB:6E          MREQ    WR                 | Memory write to  0FF <- 6E\n#056H T11 AB:0FE DB:3B          MREQ    WR                 | Memory write to  0FE <- 3B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:D5          MREQ RD                    | Memory read from 005 -> D5\n#053H T8  AB:0FF DB:6F          MREQ    WR                 | Memory write to  0FF <- 6F\n#056H T11 AB:0FE DB:3F          MREQ    WR                 | Memory write to  0FE <- 3F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:D6          MREQ RD                    | Memory read from 005 -> D6\n#053H T8  AB:0FF DB:70          MREQ    WR                 | Memory write to  0FF <- 70\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:D7          MREQ RD                    | Memory read from 005 -> D7\n#053H T8  AB:0FF DB:71          MREQ    WR                 | Memory write to  0FF <- 71\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:D8          MREQ RD                    | Memory read from 005 -> D8\n#053H T8  AB:0FF DB:72          MREQ    WR                 | Memory write to  0FF <- 72\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:D9          MREQ RD                    | Memory read from 005 -> D9\n#053H T8  AB:0FF DB:73          MREQ    WR                 | Memory write to  0FF <- 73\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:DA          MREQ RD                    | Memory read from 005 -> DA\n#053H T8  AB:0FF DB:74          MREQ    WR                 | Memory write to  0FF <- 74\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:DB          MREQ RD                    | Memory read from 005 -> DB\n#053H T8  AB:0FF DB:75          MREQ    WR                 | Memory write to  0FF <- 75\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:DC          MREQ RD                    | Memory read from 005 -> DC\n#053H T8  AB:0FF DB:76          MREQ    WR                 | Memory write to  0FF <- 76\n#056H T11 AB:0FE DB:23          MREQ    WR                 | Memory write to  0FE <- 23\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:DD          MREQ RD                    | Memory read from 005 -> DD\n#053H T8  AB:0FF DB:77          MREQ    WR                 | Memory write to  0FF <- 77\n#056H T11 AB:0FE DB:27          MREQ    WR                 | Memory write to  0FE <- 27\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:DE          MREQ RD                    | Memory read from 005 -> DE\n#053H T8  AB:0FF DB:78          MREQ    WR                 | Memory write to  0FF <- 78\n#056H T11 AB:0FE DB:2F          MREQ    WR                 | Memory write to  0FE <- 2F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:DF          MREQ RD                    | Memory read from 005 -> DF\n#053H T8  AB:0FF DB:79          MREQ    WR                 | Memory write to  0FF <- 79\n#056H T11 AB:0FE DB:2B          MREQ    WR                 | Memory write to  0FE <- 2B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:E0          MREQ RD                    | Memory read from 005 -> E0\n#053H T8  AB:0FF DB:7A          MREQ    WR                 | Memory write to  0FF <- 7A\n#056H T11 AB:0FE DB:3B          MREQ    WR                 | Memory write to  0FE <- 3B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:E1          MREQ RD                    | Memory read from 005 -> E1\n#053H T8  AB:0FF DB:7B          MREQ    WR                 | Memory write to  0FF <- 7B\n#056H T11 AB:0FE DB:3F          MREQ    WR                 | Memory write to  0FE <- 3F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:E2          MREQ RD                    | Memory read from 005 -> E2\n#053H T8  AB:0FF DB:7C          MREQ    WR                 | Memory write to  0FF <- 7C\n#056H T11 AB:0FE DB:3B          MREQ    WR                 | Memory write to  0FE <- 3B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:E3          MREQ RD                    | Memory read from 005 -> E3\n#053H T8  AB:0FF DB:7D          MREQ    WR                 | Memory write to  0FF <- 7D\n#056H T11 AB:0FE DB:3F          MREQ    WR                 | Memory write to  0FE <- 3F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:E4          MREQ RD                    | Memory read from 005 -> E4\n#053H T8  AB:0FF DB:7E          MREQ    WR                 | Memory write to  0FF <- 7E\n#056H T11 AB:0FE DB:3F          MREQ    WR                 | Memory write to  0FE <- 3F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:E5          MREQ RD                    | Memory read from 005 -> E5\n#053H T8  AB:0FF DB:7F          MREQ    WR                 | Memory write to  0FF <- 7F\n#056H T11 AB:0FE DB:3B          MREQ    WR                 | Memory write to  0FE <- 3B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:E6          MREQ RD                    | Memory read from 005 -> E6\n#053H T8  AB:0FF DB:80          MREQ    WR                 | Memory write to  0FF <- 80\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:E7          MREQ RD                    | Memory read from 005 -> E7\n#053H T8  AB:0FF DB:81          MREQ    WR                 | Memory write to  0FF <- 81\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:E8          MREQ RD                    | Memory read from 005 -> E8\n#053H T8  AB:0FF DB:82          MREQ    WR                 | Memory write to  0FF <- 82\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:E9          MREQ RD                    | Memory read from 005 -> E9\n#053H T8  AB:0FF DB:83          MREQ    WR                 | Memory write to  0FF <- 83\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:EA          MREQ RD                    | Memory read from 005 -> EA\n#053H T8  AB:0FF DB:84          MREQ    WR                 | Memory write to  0FF <- 84\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:EB          MREQ RD                    | Memory read from 005 -> EB\n#053H T8  AB:0FF DB:85          MREQ    WR                 | Memory write to  0FF <- 85\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:EC          MREQ RD                    | Memory read from 005 -> EC\n#053H T8  AB:0FF DB:86          MREQ    WR                 | Memory write to  0FF <- 86\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:ED          MREQ RD                    | Memory read from 005 -> ED\n#053H T8  AB:0FF DB:87          MREQ    WR                 | Memory write to  0FF <- 87\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:EE          MREQ RD                    | Memory read from 005 -> EE\n#053H T8  AB:0FF DB:88          MREQ    WR                 | Memory write to  0FF <- 88\n#056H T11 AB:0FE DB:8F          MREQ    WR                 | Memory write to  0FE <- 8F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:EF          MREQ RD                    | Memory read from 005 -> EF\n#053H T8  AB:0FF DB:89          MREQ    WR                 | Memory write to  0FF <- 89\n#056H T11 AB:0FE DB:8B          MREQ    WR                 | Memory write to  0FE <- 8B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:F0          MREQ RD                    | Memory read from 005 -> F0\n#053H T8  AB:0FF DB:8A          MREQ    WR                 | Memory write to  0FF <- 8A\n#056H T11 AB:0FE DB:9B          MREQ    WR                 | Memory write to  0FE <- 9B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:F1          MREQ RD                    | Memory read from 005 -> F1\n#053H T8  AB:0FF DB:8B          MREQ    WR                 | Memory write to  0FF <- 8B\n#056H T11 AB:0FE DB:9F          MREQ    WR                 | Memory write to  0FE <- 9F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:F2          MREQ RD                    | Memory read from 005 -> F2\n#053H T8  AB:0FF DB:8C          MREQ    WR                 | Memory write to  0FF <- 8C\n#056H T11 AB:0FE DB:9B          MREQ    WR                 | Memory write to  0FE <- 9B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:F3          MREQ RD                    | Memory read from 005 -> F3\n#053H T8  AB:0FF DB:8D          MREQ    WR                 | Memory write to  0FF <- 8D\n#056H T11 AB:0FE DB:9F          MREQ    WR                 | Memory write to  0FE <- 9F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:F4          MREQ RD                    | Memory read from 005 -> F4\n#053H T8  AB:0FF DB:8E          MREQ    WR                 | Memory write to  0FF <- 8E\n#056H T11 AB:0FE DB:9F          MREQ    WR                 | Memory write to  0FE <- 9F\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:F5          MREQ RD                    | Memory read from 005 -> F5\n#053H T8  AB:0FF DB:8F          MREQ    WR                 | Memory write to  0FF <- 8F\n#056H T11 AB:0FE DB:9B          MREQ    WR                 | Memory write to  0FE <- 9B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:F6          MREQ RD                    | Memory read from 005 -> F6\n#053H T8  AB:0FF DB:90          MREQ    WR                 | Memory write to  0FF <- 90\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:F7          MREQ RD                    | Memory read from 005 -> F7\n#053H T8  AB:0FF DB:91          MREQ    WR                 | Memory write to  0FF <- 91\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:F8          MREQ RD                    | Memory read from 005 -> F8\n#053H T8  AB:0FF DB:92          MREQ    WR                 | Memory write to  0FF <- 92\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:F9          MREQ RD                    | Memory read from 005 -> F9\n#053H T8  AB:0FF DB:93          MREQ    WR                 | Memory write to  0FF <- 93\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:FA          MREQ RD                    | Memory read from 005 -> FA\n#053H T8  AB:0FF DB:94          MREQ    WR                 | Memory write to  0FF <- 94\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:FB          MREQ RD                    | Memory read from 005 -> FB\n#053H T8  AB:0FF DB:95          MREQ    WR                 | Memory write to  0FF <- 95\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:FC          MREQ RD                    | Memory read from 005 -> FC\n#053H T8  AB:0FF DB:96          MREQ    WR                 | Memory write to  0FF <- 96\n#056H T11 AB:0FE DB:87          MREQ    WR                 | Memory write to  0FE <- 87\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:FD          MREQ RD                    | Memory read from 005 -> FD\n#053H T8  AB:0FF DB:97          MREQ    WR                 | Memory write to  0FF <- 97\n#056H T11 AB:0FE DB:83          MREQ    WR                 | Memory write to  0FE <- 83\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:FE          MREQ RD                    | Memory read from 005 -> FE\n#053H T8  AB:0FF DB:98          MREQ    WR                 | Memory write to  0FF <- 98\n#056H T11 AB:0FE DB:8B          MREQ    WR                 | Memory write to  0FE <- 8B\n#017H T7  AB:004 DB:13          MREQ RD                    | Memory read from 004 -> 13\n#020H T10 AB:005 DB:FF          MREQ RD                    | Memory read from 005 -> FF\n#053H T8  AB:0FF DB:99          MREQ    WR                 | Memory write to  0FF <- 99\n#056H T11 AB:0FE DB:8F          MREQ    WR                 | Memory write to  0FE <- 8F\n"
  },
  {
    "path": "tools/dongle/daa/simulate-daa.py",
    "content": "#!/usr/bin/env python3\n#\n# This script simulates 'daa' calculation and generates values for numbers 0-255.\n# These can be compared with a real Z80 run values.\n#\nimport sys\n\n# Open opcode file and read opcode + mnemonics\nwith open('daa-concise.txt') as tmpFile:\n    testVectors = [line.rstrip('\\n') for line in tmpFile]\n\nfor line in testVectors:\n    # F:00 A:00 -> 00 F:44\n    inF = int(line[2:4], 16)\n    inA = int(line[7:9], 16)\n    outA = int(line[13:15], 16)\n    outF = int(line[18:20], 16)\n    #print ('F:' + (\"%0.2X\" % inF) + ' A:' + (\"%0.2X\" % inA) + ' -> ' + (\"%0.2X\" % outA) + ' F:' + (\"%0.2X\" % outF))\n\n    # Get the flags that will determine daa operation\n    hf = (inF>>4) & 1\n    nf = (inF>>1) & 1\n    cf = (inF>>0) & 1\n\n    correction = 0x00               # Initial correction byte\n    low_nibble_flag = 0             # Flag to keep the compare state of the low nibble\n    if (inA & 0x0F) > 9:\n        low_nibble_flag = 1\n\n    if low_nibble_flag or hf:\n        correction |= 0x06          # Setup lower nibble\n\n    # if inA > 0x99 or cf:\n    upperA = (inA >> 4) & 0xF       # Simulate ALU: get the upper nibble\n    if (upperA == 9 and low_nibble_flag) or upperA > 9 or cf:\n        correction |= 0x60          # Setup upper nibble\n        cf = 1\n    else:\n        cf = 0\n\n    if nf:\n        finalA = inA - correction\n    else:\n        finalA = inA + correction\n    finalA &= 0xFF                  # Formality\n\n    #-------------------------------------------------------------------------------\n    # Flag calculation: SF, ZF, YF, HF, XF, VF/PF, NF, CF\n    #-------------------------------------------------------------------------------\n    sf = (finalA>>7) & 1            # Copy of [7]\n    zf = finalA==0                  # Set if the final value is zero\n    yf = (finalA>>5) & 1            # Copy of [5]\n    hf = 0                          # Standard way to compute HF\n    if (inA&0x10)!=(finalA&0x10):\n        hf = 1\n    xf = (finalA>>3) & 1            # Copy of [3]\n    pf = (((finalA>>7)^(finalA>>6)^(finalA>>5)^(finalA>>4)^(finalA>>3)^(finalA>>2)^(finalA>>1)^(finalA>>0))&1)^1\n    nf = (inF>>1) & 1               # Always unchanged\n\n    flags = (sf<<7) | (zf<<6) | (yf<<5) | (hf<<4) | (xf<<3) | (pf<<2) | (nf<<1) | (cf<<0)\n\n    print ('F:' + (\"%0.2X\" % inF) + ' A:' + (\"%0.2X\" % inA) + ' -> ' + (\"%0.2X\" % finalA) + ' F:' + (\"%0.2X\" % flags))\n"
  },
  {
    "path": "tools/dongle/daa/z80-instruction-test-daa.py",
    "content": "#!/usr/bin/env python\n#\n# This script runs Z80 command 'daa' for all 256 values and flag combinations\n# and prints out memory access log data. This data is used to feed the simulation\n# script and verify its algorithm correctness.\n# It needs:\n#   1. Arduino Z80 dongle: http://www.baltazarstudios.com\n# Needs pyserial from https://pypi.python.org/pypi/pyserial\n#\nimport serial\nimport sys\n\nser = serial.Serial(\"\\\\.\\COM9\", 115200, timeout=1)\n\n# Flush the serial buffer, removes any command response\ndef serialFlush(ser):\n    while 1:\n        indata = ser.readline().rstrip('\\n')\n        if not indata:\n            break\n\ntry:\n    serialFlush(ser)\n    # Stop after selected M1 cycle effectively running only that one sequence\n    ser.write(\"s 4 7\\r\")\n    ser.write(\"s 3 60\\r\")\n    serialFlush(ser)\n\n    # Loop for all 256 arguments\n    for x in range(0, 256):\n    #2:    0+10 0000  310000        ld  sp, 0000h\n    #3:   10+10 0003  010000        ld  bc, 0000h\n    #4:   20+11 0006  C5            push    bc\n    #5:   31+10 0007  F1            pop     af\n    #6:   41+4  0008  27            daa\n    #7:   45+11 0009  F5            push    af\n    #8:   56+4  000A  76            halt\n        ram = ':10000000' + '310000' + '01' + '13' + (\"%0.2X\" % x) + 'C5F127F5760000000000'\n\n        ser.write(ram + '\\r')\n        indata = ser.readline().rstrip('\\n')\n        ser.write('r\\r')\n\n        sys.stderr.write (ram + '\\n')\n\n        # Skip initial response from Arduino, includes two empty cycles after the reset\n        for x in range(1,7):\n            indata = ser.readline()\n\n        while 1:\n            indata = ser.readline()\n            if not indata:\n                break\n            if indata[0]!=':':\n                if (\"#017\" in indata) or (\"#020\" in indata) or (\"#053\" in indata) or (\"#056\" in indata):\n                    print (indata.rstrip('\\r\\n'))\n                    sys.stderr.write (indata)\n\nexcept KeyboardInterrupt:\n     ser.close()\n"
  },
  {
    "path": "tools/dongle/dd.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD HTML 4.01//EN\">\n<HTML><HEAD><TITLE>Z80 Instructions Timing</TITLE></HEAD><BODY>\n<H1>Opcodes with DD prefix</H1>\nDD 09 .. <A href=\"#09\">ADD IX,BC</A><BR>\nDD 19 .. <A href=\"#19\">ADD IX,DE</A><BR>\nDD 21 .. <A href=\"#21\">LD IX,nn</A><BR>\nDD 22 .. <A href=\"#22\">LD (nn),IX</A><BR>\nDD 23 .. <A href=\"#23\">INC IX</A><BR>\nDD 24 .. <A href=\"#24\">INC IXh*</A><BR>\nDD 25 .. <A href=\"#25\">DEC IXh*</A><BR>\nDD 26 .. <A href=\"#26\">LD IXh,n*</A><BR>\nDD 29 .. <A href=\"#29\">ADD IX,IX</A><BR>\nDD 2A .. <A href=\"#2A\">LD IX,(nn)</A><BR>\nDD 2B .. <A href=\"#2B\">DEC IX</A><BR>\nDD 2C .. <A href=\"#2C\">INC IXl*</A><BR>\nDD 2D .. <A href=\"#2D\">DEC IXl*</A><BR>\nDD 2E .. <A href=\"#2E\">LD IXl,n*</A><BR>\nDD 34 .. <A href=\"#34\">INC (IX+d)</A><BR>\nDD 35 .. <A href=\"#35\">DEC (IX+d)</A><BR>\nDD 36 .. <A href=\"#36\">LD (IX+d),n</A><BR>\nDD 39 .. <A href=\"#39\">ADD IX,SP</A><BR>\nDD 44 .. <A href=\"#44\">LD B,IXh*</A><BR>\nDD 45 .. <A href=\"#45\">LD B,IXl*</A><BR>\nDD 46 .. <A href=\"#46\">LD B,(IX+d)</A><BR>\nDD 4C .. <A href=\"#4C\">LD C,IXh*</A><BR>\nDD 4D .. <A href=\"#4D\">LD C,IXl*</A><BR>\nDD 4E .. <A href=\"#4E\">LD C,(IX+d)</A><BR>\nDD 54 .. <A href=\"#54\">LD D,IXh*</A><BR>\nDD 55 .. <A href=\"#55\">LD D,IXl*</A><BR>\nDD 56 .. <A href=\"#56\">LD D,(IX+d)</A><BR>\nDD 5C .. <A href=\"#5C\">LD E,IXh*</A><BR>\nDD 5D .. <A href=\"#5D\">LD E,IXl*</A><BR>\nDD 5E .. <A href=\"#5E\">LD E,(IX+d)</A><BR>\nDD 60 .. <A href=\"#60\">LD IXh,B*</A><BR>\nDD 61 .. <A href=\"#61\">LD IXh,C*</A><BR>\nDD 62 .. <A href=\"#62\">LD IXh,D*</A><BR>\nDD 63 .. <A href=\"#63\">LD IXh,E*</A><BR>\nDD 64 .. <A href=\"#64\">LD IXh,IXh*</A><BR>\nDD 65 .. <A href=\"#65\">LD IXh,IXl*</A><BR>\nDD 66 .. <A href=\"#66\">LD H,(IX+d)</A><BR>\nDD 67 .. <A href=\"#67\">LD IXh,A*</A><BR>\nDD 68 .. <A href=\"#68\">LD IXl,B*</A><BR>\nDD 69 .. <A href=\"#69\">LD IXl,C*</A><BR>\nDD 6A .. <A href=\"#6A\">LD IXl,D*</A><BR>\nDD 6B .. <A href=\"#6B\">LD IXl,E*</A><BR>\nDD 6C .. <A href=\"#6C\">LD IXl,IXh*</A><BR>\nDD 6D .. <A href=\"#6D\">LD IXl,IXl*</A><BR>\nDD 6E .. <A href=\"#6E\">LD L,(IX+d)</A><BR>\nDD 6F .. <A href=\"#6F\">LD IXl,A*</A><BR>\nDD 70 .. <A href=\"#70\">LD (IX+d),B</A><BR>\nDD 71 .. <A href=\"#71\">LD (IX+d),C</A><BR>\nDD 72 .. <A href=\"#72\">LD (IX+d),D</A><BR>\nDD 73 .. <A href=\"#73\">LD (IX+d),E</A><BR>\nDD 74 .. <A href=\"#74\">LD (IX+d),H</A><BR>\nDD 75 .. <A href=\"#75\">LD (IX+d),L</A><BR>\nDD 77 .. <A href=\"#77\">LD (IX+d),A</A><BR>\nDD 7C .. <A href=\"#7C\">LD A,IXh*</A><BR>\nDD 7D .. <A href=\"#7D\">LD A,IXl*</A><BR>\nDD 7E .. <A href=\"#7E\">LD A,(IX+d)</A><BR>\nDD 84 .. <A href=\"#84\">ADD A,IXh*</A><BR>\nDD 85 .. <A href=\"#85\">ADD A,IXl*</A><BR>\nDD 86 .. <A href=\"#86\">ADD A,(IX+d)</A><BR>\nDD 8C .. <A href=\"#8C\">ADC A,IXh*</A><BR>\nDD 8D .. <A href=\"#8D\">ADC A,IXl*</A><BR>\nDD 8E .. <A href=\"#8E\">ADC A,(IX+d)</A><BR>\nDD 94 .. <A href=\"#94\">SUB IXh*</A><BR>\nDD 95 .. <A href=\"#95\">SUB IXl*</A><BR>\nDD 96 .. <A href=\"#96\">SUB (IX+d)</A><BR>\nDD 9C .. <A href=\"#9C\">SBC A,IXh*</A><BR>\nDD 9D .. <A href=\"#9D\">SBC A,IXl*</A><BR>\nDD 9E .. <A href=\"#9E\">SBC A,(IX+d)</A><BR>\nDD A4 .. <A href=\"#A4\">AND IXh*</A><BR>\nDD A5 .. <A href=\"#A5\">AND IXl*</A><BR>\nDD A6 .. <A href=\"#A6\">AND (IX+d)</A><BR>\nDD AC .. <A href=\"#AC\">XOR IXh*</A><BR>\nDD AD .. <A href=\"#AD\">XOR IXl*</A><BR>\nDD AE .. <A href=\"#AE\">XOR (IX+d)</A><BR>\nDD B4 .. <A href=\"#B4\">OR IXh*</A><BR>\nDD B5 .. <A href=\"#B5\">OR IXl*</A><BR>\nDD B6 .. <A href=\"#B6\">OR (IX+d)</A><BR>\nDD BC .. <A href=\"#BC\">CP IXh*</A><BR>\nDD BD .. <A href=\"#BD\">CP IXl*</A><BR>\nDD BE .. <A href=\"#BE\">CP (IX+d)</A><BR>\nDD E1 .. <A href=\"#E1\">POP IX</A><BR>\nDD E3 .. <A href=\"#E3\">EX (SP),IX</A><BR>\nDD E5 .. <A href=\"#E5\">PUSH IX</A><BR>\nDD E9 .. <A href=\"#E9\">JP (IX)</A><BR>\nDD F9 .. <A href=\"#F9\">LD SP,IX</A><BR>\n<H1>Instructions Timing</H1>\n<H3 id=\"09\">Opcode: DD 09     => ADD IX,BC</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:09  M1      MREQ RD                    | Opcode read from 001 -> 09\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:001 DB:--                                     | \n#010H T6  AB:001 DB:--                                     | \n#011H T7  AB:001 DB:--                                     | \n#012H T8  AB:001 DB:--                                     | \n#013H T9  AB:001 DB:--                                     | \n#014H T10 AB:001 DB:--                                     | \n#015H T11 AB:001 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"19\">Opcode: DD 19     => ADD IX,DE</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:19  M1      MREQ RD                    | Opcode read from 001 -> 19\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:001 DB:--                                     | \n#010H T6  AB:001 DB:--                                     | \n#011H T7  AB:001 DB:--                                     | \n#012H T8  AB:001 DB:--                                     | \n#013H T9  AB:001 DB:--                                     | \n#014H T10 AB:001 DB:--                                     | \n#015H T11 AB:001 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"21\">Opcode: DD 21 n n => LD IX,nn</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:21  M1      MREQ RD                    | Opcode read from 001 -> 21\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#014H T10 AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"22\">Opcode: DD 22 n n => LD (nn),IX</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:22  M1      MREQ RD                    | Opcode read from 001 -> 22\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#014H T10 AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#015H T11 AB:001 DB:--                                     | \n#016H T12 AB:001 DB:01          MREQ                       | \n#017H T13 AB:001 DB:01          MREQ    WR                 | Memory write to  001 <- 01\n#018H T14 AB:002 DB:--                                     | \n#019H T15 AB:002 DB:02          MREQ                       | \n#020H T16 AB:002 DB:02          MREQ    WR                 | Memory write to  002 <- 02\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"23\">Opcode: DD 23     => INC IX</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:23  M1      MREQ RD                    | Opcode read from 001 -> 23\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:001 DB:--                                     | \n#010H T6  AB:001 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"24\">Opcode: DD 24     => INC IXh*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:24  M1      MREQ RD                    | Opcode read from 001 -> 24\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"25\">Opcode: DD 25     => DEC IXh*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:25  M1      MREQ RD                    | Opcode read from 001 -> 25\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"26\">Opcode: DD 26 n   => LD IXh,n*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:26  M1      MREQ RD                    | Opcode read from 001 -> 26\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"29\">Opcode: DD 29     => ADD IX,IX</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:29  M1      MREQ RD                    | Opcode read from 001 -> 29\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:001 DB:--                                     | \n#010H T6  AB:001 DB:--                                     | \n#011H T7  AB:001 DB:--                                     | \n#012H T8  AB:001 DB:--                                     | \n#013H T9  AB:001 DB:--                                     | \n#014H T10 AB:001 DB:--                                     | \n#015H T11 AB:001 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"2A\">Opcode: DD 2A n n => LD IX,(nn)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:2A  M1      MREQ RD                    | Opcode read from 001 -> 2A\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#014H T10 AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#015H T11 AB:001 DB:--                                     | \n#016H T12 AB:001 DB:2A          MREQ RD                    | Memory read from 001 -> 2A\n#017H T13 AB:001 DB:2A          MREQ RD                    | Memory read from 001 -> 2A\n#018H T14 AB:002 DB:--                                     | \n#019H T15 AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#020H T16 AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"2B\">Opcode: DD 2B     => DEC IX</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:2B  M1      MREQ RD                    | Opcode read from 001 -> 2B\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:001 DB:--                                     | \n#010H T6  AB:001 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"2C\">Opcode: DD 2C     => INC IXl*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:2C  M1      MREQ RD                    | Opcode read from 001 -> 2C\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"2D\">Opcode: DD 2D     => DEC IXl*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:2D  M1      MREQ RD                    | Opcode read from 001 -> 2D\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"2E\">Opcode: DD 2E n   => LD IXl,n*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:2E  M1      MREQ RD                    | Opcode read from 001 -> 2E\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"34\">Opcode: DD 34 d   => INC (IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:34  M1      MREQ RD                    | Opcode read from 001 -> 34\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:002 DB:--                                     | \n#013H T9  AB:002 DB:--                                     | \n#014H T10 AB:002 DB:--                                     | \n#015H T11 AB:002 DB:--                                     | \n#016H T12 AB:002 DB:--                                     | \n#017H T13 AB:002 DB:--                                     | \n#018H T14 AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#019H T15 AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#020H T16 AB:002 DB:--                                     | \n#021H T17 AB:002 DB:--                                     | \n#022H T18 AB:002 DB:02          MREQ                       | \n#023H T19 AB:002 DB:02          MREQ    WR                 | Memory write to  002 <- 02\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"35\">Opcode: DD 35 d   => DEC (IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:35  M1      MREQ RD                    | Opcode read from 001 -> 35\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:002 DB:--                                     | \n#013H T9  AB:002 DB:--                                     | \n#014H T10 AB:002 DB:--                                     | \n#015H T11 AB:002 DB:--                                     | \n#016H T12 AB:002 DB:--                                     | \n#017H T13 AB:002 DB:--                                     | \n#018H T14 AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#019H T15 AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#020H T16 AB:002 DB:--                                     | \n#021H T17 AB:002 DB:--                                     | \n#022H T18 AB:002 DB:00          MREQ                       | \n#023H T19 AB:002 DB:00          MREQ    WR                 | Memory write to  002 <- 00\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"36\">Opcode: DD 36 d n => LD (IX+d),n</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:36  M1      MREQ RD                    | Opcode read from 001 -> 36\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#014H T10 AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:002 DB:--                                     | \n#018H T14 AB:002 DB:02          MREQ                       | \n#019H T15 AB:002 DB:02          MREQ    WR                 | Memory write to  002 <- 02\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"39\">Opcode: DD 39     => ADD IX,SP</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:39  M1      MREQ RD                    | Opcode read from 001 -> 39\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:001 DB:--                                     | \n#010H T6  AB:001 DB:--                                     | \n#011H T7  AB:001 DB:--                                     | \n#012H T8  AB:001 DB:--                                     | \n#013H T9  AB:001 DB:--                                     | \n#014H T10 AB:001 DB:--                                     | \n#015H T11 AB:001 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"44\">Opcode: DD 44     => LD B,IXh*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:44  M1      MREQ RD                    | Opcode read from 001 -> 44\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"45\">Opcode: DD 45     => LD B,IXl*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:45  M1      MREQ RD                    | Opcode read from 001 -> 45\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"46\">Opcode: DD 46 d   => LD B,(IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:46  M1      MREQ RD                    | Opcode read from 001 -> 46\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:002 DB:--                                     | \n#013H T9  AB:002 DB:--                                     | \n#014H T10 AB:002 DB:--                                     | \n#015H T11 AB:002 DB:--                                     | \n#016H T12 AB:002 DB:--                                     | \n#017H T13 AB:001 DB:--                                     | \n#018H T14 AB:001 DB:46          MREQ RD                    | Memory read from 001 -> 46\n#019H T15 AB:001 DB:46          MREQ RD                    | Memory read from 001 -> 46\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"4C\">Opcode: DD 4C     => LD C,IXh*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:4C  M1      MREQ RD                    | Opcode read from 001 -> 4C\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"4D\">Opcode: DD 4D     => LD C,IXl*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:4D  M1      MREQ RD                    | Opcode read from 001 -> 4D\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"4E\">Opcode: DD 4E d   => LD C,(IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:4E  M1      MREQ RD                    | Opcode read from 001 -> 4E\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:002 DB:--                                     | \n#013H T9  AB:002 DB:--                                     | \n#014H T10 AB:002 DB:--                                     | \n#015H T11 AB:002 DB:--                                     | \n#016H T12 AB:002 DB:--                                     | \n#017H T13 AB:001 DB:--                                     | \n#018H T14 AB:001 DB:4E          MREQ RD                    | Memory read from 001 -> 4E\n#019H T15 AB:001 DB:4E          MREQ RD                    | Memory read from 001 -> 4E\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"54\">Opcode: DD 54     => LD D,IXh*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:54  M1      MREQ RD                    | Opcode read from 001 -> 54\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"55\">Opcode: DD 55     => LD D,IXl*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:55  M1      MREQ RD                    | Opcode read from 001 -> 55\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"56\">Opcode: DD 56 d   => LD D,(IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:56  M1      MREQ RD                    | Opcode read from 001 -> 56\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:002 DB:--                                     | \n#013H T9  AB:002 DB:--                                     | \n#014H T10 AB:002 DB:--                                     | \n#015H T11 AB:002 DB:--                                     | \n#016H T12 AB:002 DB:--                                     | \n#017H T13 AB:001 DB:--                                     | \n#018H T14 AB:001 DB:56          MREQ RD                    | Memory read from 001 -> 56\n#019H T15 AB:001 DB:56          MREQ RD                    | Memory read from 001 -> 56\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"5C\">Opcode: DD 5C     => LD E,IXh*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:5C  M1      MREQ RD                    | Opcode read from 001 -> 5C\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"5D\">Opcode: DD 5D     => LD E,IXl*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:5D  M1      MREQ RD                    | Opcode read from 001 -> 5D\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"5E\">Opcode: DD 5E d   => LD E,(IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:5E  M1      MREQ RD                    | Opcode read from 001 -> 5E\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:002 DB:--                                     | \n#013H T9  AB:002 DB:--                                     | \n#014H T10 AB:002 DB:--                                     | \n#015H T11 AB:002 DB:--                                     | \n#016H T12 AB:002 DB:--                                     | \n#017H T13 AB:001 DB:--                                     | \n#018H T14 AB:001 DB:5E          MREQ RD                    | Memory read from 001 -> 5E\n#019H T15 AB:001 DB:5E          MREQ RD                    | Memory read from 001 -> 5E\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"60\">Opcode: DD 60     => LD IXh,B*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:60  M1      MREQ RD                    | Opcode read from 001 -> 60\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"61\">Opcode: DD 61     => LD IXh,C*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:61  M1      MREQ RD                    | Opcode read from 001 -> 61\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"62\">Opcode: DD 62     => LD IXh,D*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:62  M1      MREQ RD                    | Opcode read from 001 -> 62\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"63\">Opcode: DD 63     => LD IXh,E*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:63  M1      MREQ RD                    | Opcode read from 001 -> 63\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"64\">Opcode: DD 64     => LD IXh,IXh*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:64  M1      MREQ RD                    | Opcode read from 001 -> 64\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"65\">Opcode: DD 65     => LD IXh,IXl*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:65  M1      MREQ RD                    | Opcode read from 001 -> 65\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"66\">Opcode: DD 66 d   => LD H,(IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:66  M1      MREQ RD                    | Opcode read from 001 -> 66\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:002 DB:--                                     | \n#013H T9  AB:002 DB:--                                     | \n#014H T10 AB:002 DB:--                                     | \n#015H T11 AB:002 DB:--                                     | \n#016H T12 AB:002 DB:--                                     | \n#017H T13 AB:001 DB:--                                     | \n#018H T14 AB:001 DB:66          MREQ RD                    | Memory read from 001 -> 66\n#019H T15 AB:001 DB:66          MREQ RD                    | Memory read from 001 -> 66\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"67\">Opcode: DD 67     => LD IXh,A*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:67  M1      MREQ RD                    | Opcode read from 001 -> 67\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"68\">Opcode: DD 68     => LD IXl,B*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:68  M1      MREQ RD                    | Opcode read from 001 -> 68\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"69\">Opcode: DD 69     => LD IXl,C*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:69  M1      MREQ RD                    | Opcode read from 001 -> 69\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"6A\">Opcode: DD 6A     => LD IXl,D*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:6A  M1      MREQ RD                    | Opcode read from 001 -> 6A\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"6B\">Opcode: DD 6B     => LD IXl,E*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:6B  M1      MREQ RD                    | Opcode read from 001 -> 6B\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"6C\">Opcode: DD 6C     => LD IXl,IXh*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:6C  M1      MREQ RD                    | Opcode read from 001 -> 6C\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"6D\">Opcode: DD 6D     => LD IXl,IXl*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:6D  M1      MREQ RD                    | Opcode read from 001 -> 6D\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"6E\">Opcode: DD 6E d   => LD L,(IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:6E  M1      MREQ RD                    | Opcode read from 001 -> 6E\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:002 DB:--                                     | \n#013H T9  AB:002 DB:--                                     | \n#014H T10 AB:002 DB:--                                     | \n#015H T11 AB:002 DB:--                                     | \n#016H T12 AB:002 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"6F\">Opcode: DD 6F     => LD IXl,A*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:6F  M1      MREQ RD                    | Opcode read from 001 -> 6F\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"70\">Opcode: DD 70 d   => LD (IX+d),B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:70  M1      MREQ RD                    | Opcode read from 001 -> 70\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:002 DB:--                                     | \n#013H T9  AB:002 DB:--                                     | \n#014H T10 AB:002 DB:--                                     | \n#015H T11 AB:002 DB:--                                     | \n#016H T12 AB:002 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:46          MREQ                       | \n#019H T15 AB:000 DB:46          MREQ    WR                 | Memory write to  000 <- 46\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"71\">Opcode: DD 71 d   => LD (IX+d),C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:71  M1      MREQ RD                    | Opcode read from 001 -> 71\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:002 DB:--                                     | \n#013H T9  AB:002 DB:--                                     | \n#014H T10 AB:002 DB:--                                     | \n#015H T11 AB:002 DB:--                                     | \n#016H T12 AB:002 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:4E          MREQ                       | \n#019H T15 AB:000 DB:4E          MREQ    WR                 | Memory write to  000 <- 4E\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"72\">Opcode: DD 72 d   => LD (IX+d),D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:72  M1      MREQ RD                    | Opcode read from 001 -> 72\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:002 DB:--                                     | \n#013H T9  AB:002 DB:--                                     | \n#014H T10 AB:002 DB:--                                     | \n#015H T11 AB:002 DB:--                                     | \n#016H T12 AB:002 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:56          MREQ                       | \n#019H T15 AB:000 DB:56          MREQ    WR                 | Memory write to  000 <- 56\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"73\">Opcode: DD 73 d   => LD (IX+d),E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:73  M1      MREQ RD                    | Opcode read from 001 -> 73\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:002 DB:--                                     | \n#013H T9  AB:002 DB:--                                     | \n#014H T10 AB:002 DB:--                                     | \n#015H T11 AB:002 DB:--                                     | \n#016H T12 AB:002 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:5E          MREQ                       | \n#019H T15 AB:000 DB:5E          MREQ    WR                 | Memory write to  000 <- 5E\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"74\">Opcode: DD 74 d   => LD (IX+d),H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:74  M1      MREQ RD                    | Opcode read from 001 -> 74\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:002 DB:--                                     | \n#013H T9  AB:002 DB:--                                     | \n#014H T10 AB:002 DB:--                                     | \n#015H T11 AB:002 DB:--                                     | \n#016H T12 AB:002 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:66          MREQ                       | \n#019H T15 AB:000 DB:66          MREQ    WR                 | Memory write to  000 <- 66\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"75\">Opcode: DD 75 d   => LD (IX+d),L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:75  M1      MREQ RD                    | Opcode read from 001 -> 75\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:002 DB:--                                     | \n#013H T9  AB:002 DB:--                                     | \n#014H T10 AB:002 DB:--                                     | \n#015H T11 AB:002 DB:--                                     | \n#016H T12 AB:002 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ                       | \n#019H T15 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"77\">Opcode: DD 77 d   => LD (IX+d),A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:77  M1      MREQ RD                    | Opcode read from 001 -> 77\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:002 DB:--                                     | \n#013H T9  AB:002 DB:--                                     | \n#014H T10 AB:002 DB:--                                     | \n#015H T11 AB:002 DB:--                                     | \n#016H T12 AB:002 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:FF          MREQ                       | \n#019H T15 AB:000 DB:FF          MREQ    WR                 | Memory write to  000 <- FF\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"7C\">Opcode: DD 7C     => LD A,IXh*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:7C  M1      MREQ RD                    | Opcode read from 001 -> 7C\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"7D\">Opcode: DD 7D     => LD A,IXl*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:7D  M1      MREQ RD                    | Opcode read from 001 -> 7D\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"7E\">Opcode: DD 7E d   => LD A,(IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:7E  M1      MREQ RD                    | Opcode read from 001 -> 7E\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:002 DB:--                                     | \n#013H T9  AB:002 DB:--                                     | \n#014H T10 AB:002 DB:--                                     | \n#015H T11 AB:002 DB:--                                     | \n#016H T12 AB:002 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"84\">Opcode: DD 84     => ADD A,IXh*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:84  M1      MREQ RD                    | Opcode read from 001 -> 84\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"85\">Opcode: DD 85     => ADD A,IXl*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:85  M1      MREQ RD                    | Opcode read from 001 -> 85\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"86\">Opcode: DD 86 d   => ADD A,(IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:86  M1      MREQ RD                    | Opcode read from 001 -> 86\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:002 DB:--                                     | \n#013H T9  AB:002 DB:--                                     | \n#014H T10 AB:002 DB:--                                     | \n#015H T11 AB:002 DB:--                                     | \n#016H T12 AB:002 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"8C\">Opcode: DD 8C     => ADC A,IXh*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:8C  M1      MREQ RD                    | Opcode read from 001 -> 8C\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"8D\">Opcode: DD 8D     => ADC A,IXl*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:8D  M1      MREQ RD                    | Opcode read from 001 -> 8D\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"8E\">Opcode: DD 8E d   => ADC A,(IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:8E  M1      MREQ RD                    | Opcode read from 001 -> 8E\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:002 DB:--                                     | \n#013H T9  AB:002 DB:--                                     | \n#014H T10 AB:002 DB:--                                     | \n#015H T11 AB:002 DB:--                                     | \n#016H T12 AB:002 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"94\">Opcode: DD 94     => SUB IXh*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:94  M1      MREQ RD                    | Opcode read from 001 -> 94\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"95\">Opcode: DD 95     => SUB IXl*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:95  M1      MREQ RD                    | Opcode read from 001 -> 95\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"96\">Opcode: DD 96 d   => SUB (IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:96  M1      MREQ RD                    | Opcode read from 001 -> 96\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:002 DB:--                                     | \n#013H T9  AB:002 DB:--                                     | \n#014H T10 AB:002 DB:--                                     | \n#015H T11 AB:002 DB:--                                     | \n#016H T12 AB:002 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"9C\">Opcode: DD 9C     => SBC A,IXh*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:9C  M1      MREQ RD                    | Opcode read from 001 -> 9C\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"9D\">Opcode: DD 9D     => SBC A,IXl*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:9D  M1      MREQ RD                    | Opcode read from 001 -> 9D\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"9E\">Opcode: DD 9E d   => SBC A,(IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:9E  M1      MREQ RD                    | Opcode read from 001 -> 9E\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:002 DB:--                                     | \n#013H T9  AB:002 DB:--                                     | \n#014H T10 AB:002 DB:--                                     | \n#015H T11 AB:002 DB:--                                     | \n#016H T12 AB:002 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"A4\">Opcode: DD A4     => AND IXh*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:A4  M1      MREQ RD                    | Opcode read from 001 -> A4\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"A5\">Opcode: DD A5     => AND IXl*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:A5  M1      MREQ RD                    | Opcode read from 001 -> A5\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"A6\">Opcode: DD A6 d   => AND (IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:A6  M1      MREQ RD                    | Opcode read from 001 -> A6\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:002 DB:--                                     | \n#013H T9  AB:002 DB:--                                     | \n#014H T10 AB:002 DB:--                                     | \n#015H T11 AB:002 DB:--                                     | \n#016H T12 AB:002 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"AC\">Opcode: DD AC     => XOR IXh*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:AC  M1      MREQ RD                    | Opcode read from 001 -> AC\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"AD\">Opcode: DD AD     => XOR IXl*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:AD  M1      MREQ RD                    | Opcode read from 001 -> AD\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"AE\">Opcode: DD AE d   => XOR (IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:AE  M1      MREQ RD                    | Opcode read from 001 -> AE\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:002 DB:--                                     | \n#013H T9  AB:002 DB:--                                     | \n#014H T10 AB:002 DB:--                                     | \n#015H T11 AB:002 DB:--                                     | \n#016H T12 AB:002 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"B4\">Opcode: DD B4     => OR IXh*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:B4  M1      MREQ RD                    | Opcode read from 001 -> B4\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"B5\">Opcode: DD B5     => OR IXl*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:B5  M1      MREQ RD                    | Opcode read from 001 -> B5\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"B6\">Opcode: DD B6 d   => OR (IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:B6  M1      MREQ RD                    | Opcode read from 001 -> B6\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:002 DB:--                                     | \n#013H T9  AB:002 DB:--                                     | \n#014H T10 AB:002 DB:--                                     | \n#015H T11 AB:002 DB:--                                     | \n#016H T12 AB:002 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"BC\">Opcode: DD BC     => CP IXh*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:BC  M1      MREQ RD                    | Opcode read from 001 -> BC\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"BD\">Opcode: DD BD     => CP IXl*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:BD  M1      MREQ RD                    | Opcode read from 001 -> BD\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"BE\">Opcode: DD BE d   => CP (IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:BE  M1      MREQ RD                    | Opcode read from 001 -> BE\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:002 DB:--                                     | \n#013H T9  AB:002 DB:--                                     | \n#014H T10 AB:002 DB:--                                     | \n#015H T11 AB:002 DB:--                                     | \n#016H T12 AB:002 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"E1\">Opcode: DD E1     => POP IX</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:E1  M1      MREQ RD                    | Opcode read from 001 -> E1\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:0FF DB:--                                     | \n#010H T6  AB:0FF DB:00          MREQ RD                    | Memory read from 0FF -> 00\n#011H T7  AB:0FF DB:00          MREQ RD                    | Memory read from 0FF -> 00\n#012H T8  AB:000 DB:--                                     | \n#013H T9  AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#014H T10 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"E3\">Opcode: DD E3     => EX (SP),IX</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:E3  M1      MREQ RD                    | Opcode read from 001 -> E3\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:001 DB:--                                     | \n#010H T6  AB:001 DB:E3          MREQ RD                    | Memory read from 001 -> E3\n#011H T7  AB:001 DB:E3          MREQ RD                    | Memory read from 001 -> E3\n#012H T8  AB:002 DB:--                                     | \n#013H T9  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#014H T10 AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#015H T11 AB:002 DB:--                                     | \n#016H T12 AB:002 DB:--                                     | \n#017H T13 AB:002 DB:DD          MREQ                       | \n#018H T14 AB:002 DB:DD          MREQ    WR                 | Memory write to  002 <- DD\n#019H T15 AB:001 DB:--                                     | \n#020H T16 AB:001 DB:00          MREQ                       | \n#021H T17 AB:001 DB:00          MREQ    WR                 | Memory write to  001 <- 00\n#022H T18 AB:001 DB:00                                     | \n#023H T19 AB:001 DB:00                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"E5\">Opcode: DD E5     => PUSH IX</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:E5  M1      MREQ RD                    | Opcode read from 001 -> E5\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:001 DB:--                                     | \n#010H T6  AB:000 DB:--                                     | \n#011H T7  AB:000 DB:01          MREQ                       | \n#012H T8  AB:000 DB:01          MREQ    WR                 | Memory write to  000 <- 01\n#013H T9  AB:0FF DB:--                                     | \n#014H T10 AB:0FF DB:E3          MREQ                       | \n#015H T11 AB:0FF DB:E3          MREQ    WR                 | Memory write to  0FF <- E3\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"E9\">Opcode: DD E9     => JP (IX)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:E9  M1      MREQ RD                    | Opcode read from 001 -> E9\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"F9\">Opcode: DD F9     => LD SP,IX</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:F9  M1      MREQ RD                    | Opcode read from 001 -> F9\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:001 DB:--                                     | \n#010H T6  AB:001 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n</BODY></HTML>\n"
  },
  {
    "path": "tools/dongle/ddcb.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD HTML 4.01//EN\">\n<HTML><HEAD><TITLE>Z80 Instructions Timing</TITLE></HEAD><BODY>\n<H1>Opcodes with DD/FD + CB prefix</H1>\nDD CB . 00 .. <A href=\"#00\">RLC (IX+d),B*</A><BR>\nDD CB . 01 .. <A href=\"#01\">RLC (IX+d),C*</A><BR>\nDD CB . 02 .. <A href=\"#02\">RLC (IX+d),D*</A><BR>\nDD CB . 03 .. <A href=\"#03\">RLC (IX+d),E*</A><BR>\nDD CB . 04 .. <A href=\"#04\">RLC (IX+d),H*</A><BR>\nDD CB . 05 .. <A href=\"#05\">RLC (IX+d),L*</A><BR>\nDD CB . 06 .. <A href=\"#06\">RLC (IX+d)</A><BR>\nDD CB . 07 .. <A href=\"#07\">RLC (IX+d),A*</A><BR>\nDD CB . 08 .. <A href=\"#08\">RRC (IX+d),B*</A><BR>\nDD CB . 09 .. <A href=\"#09\">RRC (IX+d),C*</A><BR>\nDD CB . 0A .. <A href=\"#0A\">RRC (IX+d),D*</A><BR>\nDD CB . 0B .. <A href=\"#0B\">RRC (IX+d),E*</A><BR>\nDD CB . 0C .. <A href=\"#0C\">RRC (IX+d),H*</A><BR>\nDD CB . 0D .. <A href=\"#0D\">RRC (IX+d),L*</A><BR>\nDD CB . 0E .. <A href=\"#0E\">RRC (IX+d)</A><BR>\nDD CB . 0F .. <A href=\"#0F\">RRC (IX+d),A*</A><BR>\nDD CB . 10 .. <A href=\"#10\">RL (IX+d),B*</A><BR>\nDD CB . 11 .. <A href=\"#11\">RL (IX+d),C*</A><BR>\nDD CB . 12 .. <A href=\"#12\">RL (IX+d),D*</A><BR>\nDD CB . 13 .. <A href=\"#13\">RL (IX+d),E*</A><BR>\nDD CB . 14 .. <A href=\"#14\">RL (IX+d),H*</A><BR>\nDD CB . 15 .. <A href=\"#15\">RL (IX+d),L*</A><BR>\nDD CB . 16 .. <A href=\"#16\">RL (IX+d)</A><BR>\nDD CB . 17 .. <A href=\"#17\">RL (IX+d),A*</A><BR>\nDD CB . 18 .. <A href=\"#18\">RR (IX+d),B*</A><BR>\nDD CB . 19 .. <A href=\"#19\">RR (IX+d),C*</A><BR>\nDD CB . 1A .. <A href=\"#1A\">RR (IX+d),D*</A><BR>\nDD CB . 1B .. <A href=\"#1B\">RR (IX+d),E*</A><BR>\nDD CB . 1C .. <A href=\"#1C\">RR (IX+d),H*</A><BR>\nDD CB . 1D .. <A href=\"#1D\">RR (IX+d),L*</A><BR>\nDD CB . 1E .. <A href=\"#1E\">RR (IX+d)</A><BR>\nDD CB . 1F .. <A href=\"#1F\">RR (IX+d),A*</A><BR>\nDD CB . 20 .. <A href=\"#20\">SLA (IX+d),B*</A><BR>\nDD CB . 21 .. <A href=\"#21\">SLA (IX+d),C*</A><BR>\nDD CB . 22 .. <A href=\"#22\">SLA (IX+d),D*</A><BR>\nDD CB . 23 .. <A href=\"#23\">SLA (IX+d),E*</A><BR>\nDD CB . 24 .. <A href=\"#24\">SLA (IX+d),H*</A><BR>\nDD CB . 25 .. <A href=\"#25\">SLA (IX+d),L*</A><BR>\nDD CB . 26 .. <A href=\"#26\">SLA (IX+d)</A><BR>\nDD CB . 27 .. <A href=\"#27\">SLA (IX+d),A*</A><BR>\nDD CB . 28 .. <A href=\"#28\">SRA (IX+d),B*</A><BR>\nDD CB . 29 .. <A href=\"#29\">SRA (IX+d),C*</A><BR>\nDD CB . 2A .. <A href=\"#2A\">SRA (IX+d),D*</A><BR>\nDD CB . 2B .. <A href=\"#2B\">SRA (IX+d),E*</A><BR>\nDD CB . 2C .. <A href=\"#2C\">SRA (IX+d),H*</A><BR>\nDD CB . 2D .. <A href=\"#2D\">SRA (IX+d),L*</A><BR>\nDD CB . 2E .. <A href=\"#2E\">SRA (IX+d)</A><BR>\nDD CB . 2F .. <A href=\"#2F\">SRA (IX+d),A*</A><BR>\nDD CB . 30 .. <A href=\"#30\">SLL (IX+d),B*</A><BR>\nDD CB . 31 .. <A href=\"#31\">SLL (IX+d),C*</A><BR>\nDD CB . 32 .. <A href=\"#32\">SLL (IX+d),D*</A><BR>\nDD CB . 33 .. <A href=\"#33\">SLL (IX+d),E*</A><BR>\nDD CB . 34 .. <A href=\"#34\">SLL (IX+d),H*</A><BR>\nDD CB . 35 .. <A href=\"#35\">SLL (IX+d),L*</A><BR>\nDD CB . 36 .. <A href=\"#36\">SLL (IX+d)*</A><BR>\nDD CB . 37 .. <A href=\"#37\">SLL (IX+d),A*</A><BR>\nDD CB . 38 .. <A href=\"#38\">SRL (IX+d),B*</A><BR>\nDD CB . 39 .. <A href=\"#39\">SRL (IX+d),C*</A><BR>\nDD CB . 3A .. <A href=\"#3A\">SRL (IX+d),D*</A><BR>\nDD CB . 3B .. <A href=\"#3B\">SRL (IX+d),E*</A><BR>\nDD CB . 3C .. <A href=\"#3C\">SRL (IX+d),H*</A><BR>\nDD CB . 3D .. <A href=\"#3D\">SRL (IX+d),L*</A><BR>\nDD CB . 3E .. <A href=\"#3E\">SRL (IX+d)</A><BR>\nDD CB . 3F .. <A href=\"#3F\">SRL (IX+d),A*</A><BR>\nDD CB . 40 .. <A href=\"#40\">BIT 0,(IX+d)*</A><BR>\nDD CB . 41 .. <A href=\"#41\">BIT 0,(IX+d)*</A><BR>\nDD CB . 42 .. <A href=\"#42\">BIT 0,(IX+d)*</A><BR>\nDD CB . 43 .. <A href=\"#43\">BIT 0,(IX+d)*</A><BR>\nDD CB . 44 .. <A href=\"#44\">BIT 0,(IX+d)*</A><BR>\nDD CB . 45 .. <A href=\"#45\">BIT 0,(IX+d)*</A><BR>\nDD CB . 46 .. <A href=\"#46\">BIT 0,(IX+d)</A><BR>\nDD CB . 47 .. <A href=\"#47\">BIT 0,(IX+d)*</A><BR>\nDD CB . 48 .. <A href=\"#48\">BIT 1,(IX+d)*</A><BR>\nDD CB . 49 .. <A href=\"#49\">BIT 1,(IX+d)*</A><BR>\nDD CB . 4A .. <A href=\"#4A\">BIT 1,(IX+d)*</A><BR>\nDD CB . 4B .. <A href=\"#4B\">BIT 1,(IX+d)*</A><BR>\nDD CB . 4C .. <A href=\"#4C\">BIT 1,(IX+d)*</A><BR>\nDD CB . 4D .. <A href=\"#4D\">BIT 1,(IX+d)*</A><BR>\nDD CB . 4E .. <A href=\"#4E\">BIT 1,(IX+d)</A><BR>\nDD CB . 4F .. <A href=\"#4F\">BIT 1,(IX+d)*</A><BR>\nDD CB . 50 .. <A href=\"#50\">BIT 2,(IX+d)*</A><BR>\nDD CB . 51 .. <A href=\"#51\">BIT 2,(IX+d)*</A><BR>\nDD CB . 52 .. <A href=\"#52\">BIT 2,(IX+d)*</A><BR>\nDD CB . 53 .. <A href=\"#53\">BIT 2,(IX+d)*</A><BR>\nDD CB . 54 .. <A href=\"#54\">BIT 2,(IX+d)*</A><BR>\nDD CB . 55 .. <A href=\"#55\">BIT 2,(IX+d)*</A><BR>\nDD CB . 56 .. <A href=\"#56\">BIT 2,(IX+d)</A><BR>\nDD CB . 57 .. <A href=\"#57\">BIT 2,(IX+d)*</A><BR>\nDD CB . 58 .. <A href=\"#58\">BIT 3,(IX+d)*</A><BR>\nDD CB . 59 .. <A href=\"#59\">BIT 3,(IX+d)*</A><BR>\nDD CB . 5A .. <A href=\"#5A\">BIT 3,(IX+d)*</A><BR>\nDD CB . 5B .. <A href=\"#5B\">BIT 3,(IX+d)*</A><BR>\nDD CB . 5C .. <A href=\"#5C\">BIT 3,(IX+d)*</A><BR>\nDD CB . 5D .. <A href=\"#5D\">BIT 3,(IX+d)*</A><BR>\nDD CB . 5E .. <A href=\"#5E\">BIT 3,(IX+d)</A><BR>\nDD CB . 5F .. <A href=\"#5F\">BIT 3,(IX+d)*</A><BR>\nDD CB . 60 .. <A href=\"#60\">BIT 4,(IX+d)*</A><BR>\nDD CB . 61 .. <A href=\"#61\">BIT 4,(IX+d)*</A><BR>\nDD CB . 62 .. <A href=\"#62\">BIT 4,(IX+d)*</A><BR>\nDD CB . 63 .. <A href=\"#63\">BIT 4,(IX+d)*</A><BR>\nDD CB . 64 .. <A href=\"#64\">BIT 4,(IX+d)*</A><BR>\nDD CB . 65 .. <A href=\"#65\">BIT 4,(IX+d)*</A><BR>\nDD CB . 66 .. <A href=\"#66\">BIT 4,(IX+d)</A><BR>\nDD CB . 67 .. <A href=\"#67\">BIT 4,(IX+d)*</A><BR>\nDD CB . 68 .. <A href=\"#68\">BIT 5,(IX+d)*</A><BR>\nDD CB . 69 .. <A href=\"#69\">BIT 5,(IX+d)*</A><BR>\nDD CB . 6A .. <A href=\"#6A\">BIT 5,(IX+d)*</A><BR>\nDD CB . 6B .. <A href=\"#6B\">BIT 5,(IX+d)*</A><BR>\nDD CB . 6C .. <A href=\"#6C\">BIT 5,(IX+d)*</A><BR>\nDD CB . 6D .. <A href=\"#6D\">BIT 5,(IX+d)*</A><BR>\nDD CB . 6E .. <A href=\"#6E\">BIT 5,(IX+d)</A><BR>\nDD CB . 6F .. <A href=\"#6F\">BIT 5,(IX+d)*</A><BR>\nDD CB . 70 .. <A href=\"#70\">BIT 6,(IX+d)*</A><BR>\nDD CB . 71 .. <A href=\"#71\">BIT 6,(IX+d)*</A><BR>\nDD CB . 72 .. <A href=\"#72\">BIT 6,(IX+d)*</A><BR>\nDD CB . 73 .. <A href=\"#73\">BIT 6,(IX+d)*</A><BR>\nDD CB . 74 .. <A href=\"#74\">BIT 6,(IX+d)*</A><BR>\nDD CB . 75 .. <A href=\"#75\">BIT 6,(IX+d)*</A><BR>\nDD CB . 76 .. <A href=\"#76\">BIT 6,(IX+d)</A><BR>\nDD CB . 77 .. <A href=\"#77\">BIT 6,(IX+d)*</A><BR>\nDD CB . 78 .. <A href=\"#78\">BIT 7,(IX+d)*</A><BR>\nDD CB . 79 .. <A href=\"#79\">BIT 7,(IX+d)*</A><BR>\nDD CB . 7A .. <A href=\"#7A\">BIT 7,(IX+d)*</A><BR>\nDD CB . 7B .. <A href=\"#7B\">BIT 7,(IX+d)*</A><BR>\nDD CB . 7C .. <A href=\"#7C\">BIT 7,(IX+d)*</A><BR>\nDD CB . 7D .. <A href=\"#7D\">BIT 7,(IX+d)*</A><BR>\nDD CB . 7E .. <A href=\"#7E\">BIT 7,(IX+d)</A><BR>\nDD CB . 7F .. <A href=\"#7F\">BIT 7,(IX+d)*</A><BR>\nDD CB . 80 .. <A href=\"#80\">RES 0,(IX+d),B*</A><BR>\nDD CB . 81 .. <A href=\"#81\">RES 0,(IX+d),C*</A><BR>\nDD CB . 82 .. <A href=\"#82\">RES 0,(IX+d),D*</A><BR>\nDD CB . 83 .. <A href=\"#83\">RES 0,(IX+d),E*</A><BR>\nDD CB . 84 .. <A href=\"#84\">RES 0,(IX+d),H*</A><BR>\nDD CB . 85 .. <A href=\"#85\">RES 0,(IX+d),L*</A><BR>\nDD CB . 86 .. <A href=\"#86\">RES 0,(IX+d)</A><BR>\nDD CB . 87 .. <A href=\"#87\">RES 0,(IX+d),A*</A><BR>\nDD CB . 88 .. <A href=\"#88\">RES 1,(IX+d),B*</A><BR>\nDD CB . 89 .. <A href=\"#89\">RES 1,(IX+d),C*</A><BR>\nDD CB . 8A .. <A href=\"#8A\">RES 1,(IX+d),D*</A><BR>\nDD CB . 8B .. <A href=\"#8B\">RES 1,(IX+d),E*</A><BR>\nDD CB . 8C .. <A href=\"#8C\">RES 1,(IX+d),H*</A><BR>\nDD CB . 8D .. <A href=\"#8D\">RES 1,(IX+d),L*</A><BR>\nDD CB . 8E .. <A href=\"#8E\">RES 1,(IX+d)</A><BR>\nDD CB . 8F .. <A href=\"#8F\">RES 1,(IX+d),A*</A><BR>\nDD CB . 90 .. <A href=\"#90\">RES 2,(IX+d),B*</A><BR>\nDD CB . 91 .. <A href=\"#91\">RES 2,(IX+d),C*</A><BR>\nDD CB . 92 .. <A href=\"#92\">RES 2,(IX+d),D*</A><BR>\nDD CB . 93 .. <A href=\"#93\">RES 2,(IX+d),E*</A><BR>\nDD CB . 94 .. <A href=\"#94\">RES 2,(IX+d),H*</A><BR>\nDD CB . 95 .. <A href=\"#95\">RES 2,(IX+d),L*</A><BR>\nDD CB . 96 .. <A href=\"#96\">RES 2,(IX+d)</A><BR>\nDD CB . 97 .. <A href=\"#97\">RES 2,(IX+d),A*</A><BR>\nDD CB . 98 .. <A href=\"#98\">RES 3,(IX+d),B*</A><BR>\nDD CB . 99 .. <A href=\"#99\">RES 3,(IX+d),C*</A><BR>\nDD CB . 9A .. <A href=\"#9A\">RES 3,(IX+d),D*</A><BR>\nDD CB . 9B .. <A href=\"#9B\">RES 3,(IX+d),E*</A><BR>\nDD CB . 9C .. <A href=\"#9C\">RES 3,(IX+d),H*</A><BR>\nDD CB . 9D .. <A href=\"#9D\">RES 3,(IX+d),L*</A><BR>\nDD CB . 9E .. <A href=\"#9E\">RES 3,(IX+d)</A><BR>\nDD CB . 9F .. <A href=\"#9F\">RES 3,(IX+d),A*</A><BR>\nDD CB . A0 .. <A href=\"#A0\">RES 4,(IX+d),B*</A><BR>\nDD CB . A1 .. <A href=\"#A1\">RES 4,(IX+d),C*</A><BR>\nDD CB . A2 .. <A href=\"#A2\">RES 4,(IX+d),D*</A><BR>\nDD CB . A3 .. <A href=\"#A3\">RES 4,(IX+d),E*</A><BR>\nDD CB . A4 .. <A href=\"#A4\">RES 4,(IX+d),H*</A><BR>\nDD CB . A5 .. <A href=\"#A5\">RES 4,(IX+d),L*</A><BR>\nDD CB . A6 .. <A href=\"#A6\">RES 4,(IX+d)</A><BR>\nDD CB . A7 .. <A href=\"#A7\">RES 4,(IX+d),A*</A><BR>\nDD CB . A8 .. <A href=\"#A8\">RES 5,(IX+d),B*</A><BR>\nDD CB . A9 .. <A href=\"#A9\">RES 5,(IX+d),C*</A><BR>\nDD CB . AA .. <A href=\"#AA\">RES 5,(IX+d),D*</A><BR>\nDD CB . AB .. <A href=\"#AB\">RES 5,(IX+d),E*</A><BR>\nDD CB . AC .. <A href=\"#AC\">RES 5,(IX+d),H*</A><BR>\nDD CB . AD .. <A href=\"#AD\">RES 5,(IX+d),L*</A><BR>\nDD CB . AE .. <A href=\"#AE\">RES 5,(IX+d)</A><BR>\nDD CB . AF .. <A href=\"#AF\">RES 5,(IX+d),A*</A><BR>\nDD CB . B0 .. <A href=\"#B0\">RES 6,(IX+d),B*</A><BR>\nDD CB . B1 .. <A href=\"#B1\">RES 6,(IX+d),C*</A><BR>\nDD CB . B2 .. <A href=\"#B2\">RES 6,(IX+d),D*</A><BR>\nDD CB . B3 .. <A href=\"#B3\">RES 6,(IX+d),E*</A><BR>\nDD CB . B4 .. <A href=\"#B4\">RES 6,(IX+d),H*</A><BR>\nDD CB . B5 .. <A href=\"#B5\">RES 6,(IX+d),L*</A><BR>\nDD CB . B6 .. <A href=\"#B6\">RES 6,(IX+d)</A><BR>\nDD CB . B7 .. <A href=\"#B7\">RES 6,(IX+d),A*</A><BR>\nDD CB . B8 .. <A href=\"#B8\">RES 7,(IX+d),B*</A><BR>\nDD CB . B9 .. <A href=\"#B9\">RES 7,(IX+d),C*</A><BR>\nDD CB . BA .. <A href=\"#BA\">RES 7,(IX+d),D*</A><BR>\nDD CB . BB .. <A href=\"#BB\">RES 7,(IX+d),E*</A><BR>\nDD CB . BC .. <A href=\"#BC\">RES 7,(IX+d),H*</A><BR>\nDD CB . BD .. <A href=\"#BD\">RES 7,(IX+d),L*</A><BR>\nDD CB . BE .. <A href=\"#BE\">RES 7,(IX+d)</A><BR>\nDD CB . BF .. <A href=\"#BF\">RES 7,(IX+d),A*</A><BR>\nDD CB . C0 .. <A href=\"#C0\">SET 0,(IX+d),B*</A><BR>\nDD CB . C1 .. <A href=\"#C1\">SET 0,(IX+d),C*</A><BR>\nDD CB . C2 .. <A href=\"#C2\">SET 0,(IX+d),D*</A><BR>\nDD CB . C3 .. <A href=\"#C3\">SET 0,(IX+d),E*</A><BR>\nDD CB . C4 .. <A href=\"#C4\">SET 0,(IX+d),H*</A><BR>\nDD CB . C5 .. <A href=\"#C5\">SET 0,(IX+d),L*</A><BR>\nDD CB . C6 .. <A href=\"#C6\">SET 0,(IX+d)</A><BR>\nDD CB . C7 .. <A href=\"#C7\">SET 0,(IX+d),A*</A><BR>\nDD CB . C8 .. <A href=\"#C8\">SET 1,(IX+d),B*</A><BR>\nDD CB . C9 .. <A href=\"#C9\">SET 1,(IX+d),C*</A><BR>\nDD CB . CA .. <A href=\"#CA\">SET 1,(IX+d),D*</A><BR>\nDD CB . CB .. <A href=\"#CB\">SET 1,(IX+d),E*</A><BR>\nDD CB . CC .. <A href=\"#CC\">SET 1,(IX+d),H*</A><BR>\nDD CB . CD .. <A href=\"#CD\">SET 1,(IX+d),L*</A><BR>\nDD CB . CE .. <A href=\"#CE\">SET 1,(IX+d)</A><BR>\nDD CB . CF .. <A href=\"#CF\">SET 1,(IX+d),A*</A><BR>\nDD CB . D0 .. <A href=\"#D0\">SET 2,(IX+d),B*</A><BR>\nDD CB . D1 .. <A href=\"#D1\">SET 2,(IX+d),C*</A><BR>\nDD CB . D2 .. <A href=\"#D2\">SET 2,(IX+d),D*</A><BR>\nDD CB . D3 .. <A href=\"#D3\">SET 2,(IX+d),E*</A><BR>\nDD CB . D4 .. <A href=\"#D4\">SET 2,(IX+d),H*</A><BR>\nDD CB . D5 .. <A href=\"#D5\">SET 2,(IX+d),L*</A><BR>\nDD CB . D6 .. <A href=\"#D6\">SET 2,(IX+d)</A><BR>\nDD CB . D7 .. <A href=\"#D7\">SET 2,(IX+d),A*</A><BR>\nDD CB . D8 .. <A href=\"#D8\">SET 3,(IX+d),B*</A><BR>\nDD CB . D9 .. <A href=\"#D9\">SET 3,(IX+d),C*</A><BR>\nDD CB . DA .. <A href=\"#DA\">SET 3,(IX+d),D*</A><BR>\nDD CB . DB .. <A href=\"#DB\">SET 3,(IX+d),E*</A><BR>\nDD CB . DC .. <A href=\"#DC\">SET 3,(IX+d),H*</A><BR>\nDD CB . DD .. <A href=\"#DD\">SET 3,(IX+d),L*</A><BR>\nDD CB . DE .. <A href=\"#DE\">SET 3,(IX+d)</A><BR>\nDD CB . DF .. <A href=\"#DF\">SET 3,(IX+d),A*</A><BR>\nDD CB . E0 .. <A href=\"#E0\">SET 4,(IX+d),B*</A><BR>\nDD CB . E1 .. <A href=\"#E1\">SET 4,(IX+d),C*</A><BR>\nDD CB . E2 .. <A href=\"#E2\">SET 4,(IX+d),D*</A><BR>\nDD CB . E3 .. <A href=\"#E3\">SET 4,(IX+d),E*</A><BR>\nDD CB . E4 .. <A href=\"#E4\">SET 4,(IX+d),H*</A><BR>\nDD CB . E5 .. <A href=\"#E5\">SET 4,(IX+d),L*</A><BR>\nDD CB . E6 .. <A href=\"#E6\">SET 4,(IX+d)</A><BR>\nDD CB . E7 .. <A href=\"#E7\">SET 4,(IX+d),A*</A><BR>\nDD CB . E8 .. <A href=\"#E8\">SET 5,(IX+d),B*</A><BR>\nDD CB . E9 .. <A href=\"#E9\">SET 5,(IX+d),C*</A><BR>\nDD CB . EA .. <A href=\"#EA\">SET 5,(IX+d),D*</A><BR>\nDD CB . EB .. <A href=\"#EB\">SET 5,(IX+d),E*</A><BR>\nDD CB . EC .. <A href=\"#EC\">SET 5,(IX+d),H*</A><BR>\nDD CB . ED .. <A href=\"#ED\">SET 5,(IX+d),L*</A><BR>\nDD CB . EE .. <A href=\"#EE\">SET 5,(IX+d)</A><BR>\nDD CB . EF .. <A href=\"#EF\">SET 5,(IX+d),A*</A><BR>\nDD CB . F0 .. <A href=\"#F0\">SET 6,(IX+d),B*</A><BR>\nDD CB . F1 .. <A href=\"#F1\">SET 6,(IX+d),C*</A><BR>\nDD CB . F2 .. <A href=\"#F2\">SET 6,(IX+d),D*</A><BR>\nDD CB . F3 .. <A href=\"#F3\">SET 6,(IX+d),E*</A><BR>\nDD CB . F4 .. <A href=\"#F4\">SET 6,(IX+d),H*</A><BR>\nDD CB . F5 .. <A href=\"#F5\">SET 6,(IX+d),L*</A><BR>\nDD CB . F6 .. <A href=\"#F6\">SET 6,(IX+d)</A><BR>\nDD CB . F7 .. <A href=\"#F7\">SET 6,(IX+d),A*</A><BR>\nDD CB . F8 .. <A href=\"#F8\">SET 7,(IX+d),B*</A><BR>\nDD CB . F9 .. <A href=\"#F9\">SET 7,(IX+d),C*</A><BR>\nDD CB . FA .. <A href=\"#FA\">SET 7,(IX+d),D*</A><BR>\nDD CB . FB .. <A href=\"#FB\">SET 7,(IX+d),E*</A><BR>\nDD CB . FC .. <A href=\"#FC\">SET 7,(IX+d),H*</A><BR>\nDD CB . FD .. <A href=\"#FD\">SET 7,(IX+d),L*</A><BR>\nDD CB . FE .. <A href=\"#FE\">SET 7,(IX+d)</A><BR>\nDD CB . FF .. <A href=\"#FF\">SET 7,(IX+d),A*</A><BR>\n<H1>Instructions Timing</H1>\n<H3 id=\"00\">Opcode: DD CB d 00 => RLC (IX+d),B*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:00          MREQ RD                    | Memory read from 003 -> 00\n#014H T10 AB:003 DB:00          MREQ RD                    | Memory read from 003 -> 00\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:BB          MREQ                       | \n#023H T19 AB:000 DB:BB          MREQ    WR                 | Memory write to  000 <- BB\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"01\">Opcode: DD CB d 01 => RLC (IX+d),C*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:01          MREQ RD                    | Memory read from 003 -> 01\n#014H T10 AB:003 DB:01          MREQ RD                    | Memory read from 003 -> 01\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:BB          MREQ                       | \n#023H T19 AB:000 DB:BB          MREQ    WR                 | Memory write to  000 <- BB\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"02\">Opcode: DD CB d 02 => RLC (IX+d),D*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#014H T10 AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:BB          MREQ                       | \n#023H T19 AB:000 DB:BB          MREQ    WR                 | Memory write to  000 <- BB\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"03\">Opcode: DD CB d 03 => RLC (IX+d),E*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:03          MREQ RD                    | Memory read from 003 -> 03\n#014H T10 AB:003 DB:03          MREQ RD                    | Memory read from 003 -> 03\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:BB          MREQ                       | \n#023H T19 AB:000 DB:BB          MREQ    WR                 | Memory write to  000 <- BB\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"04\">Opcode: DD CB d 04 => RLC (IX+d),H*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:04          MREQ RD                    | Memory read from 003 -> 04\n#014H T10 AB:003 DB:04          MREQ RD                    | Memory read from 003 -> 04\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:BB          MREQ                       | \n#023H T19 AB:000 DB:BB          MREQ    WR                 | Memory write to  000 <- BB\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"05\">Opcode: DD CB d 05 => RLC (IX+d),L*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:05          MREQ RD                    | Memory read from 003 -> 05\n#014H T10 AB:003 DB:05          MREQ RD                    | Memory read from 003 -> 05\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:BB          MREQ                       | \n#023H T19 AB:000 DB:BB          MREQ    WR                 | Memory write to  000 <- BB\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"06\">Opcode: DD CB d 06 => RLC (IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:06          MREQ RD                    | Memory read from 003 -> 06\n#014H T10 AB:003 DB:06          MREQ RD                    | Memory read from 003 -> 06\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:BB          MREQ                       | \n#023H T19 AB:000 DB:BB          MREQ    WR                 | Memory write to  000 <- BB\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"07\">Opcode: DD CB d 07 => RLC (IX+d),A*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:07          MREQ RD                    | Memory read from 003 -> 07\n#014H T10 AB:003 DB:07          MREQ RD                    | Memory read from 003 -> 07\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:BB          MREQ                       | \n#023H T19 AB:000 DB:BB          MREQ    WR                 | Memory write to  000 <- BB\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"08\">Opcode: DD CB d 08 => RRC (IX+d),B*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:08          MREQ RD                    | Memory read from 003 -> 08\n#014H T10 AB:003 DB:08          MREQ RD                    | Memory read from 003 -> 08\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:EE          MREQ                       | \n#023H T19 AB:000 DB:EE          MREQ    WR                 | Memory write to  000 <- EE\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"09\">Opcode: DD CB d 09 => RRC (IX+d),C*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:09          MREQ RD                    | Memory read from 003 -> 09\n#014H T10 AB:003 DB:09          MREQ RD                    | Memory read from 003 -> 09\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:EE          MREQ                       | \n#023H T19 AB:000 DB:EE          MREQ    WR                 | Memory write to  000 <- EE\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"0A\">Opcode: DD CB d 0A => RRC (IX+d),D*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:0A          MREQ RD                    | Memory read from 003 -> 0A\n#014H T10 AB:003 DB:0A          MREQ RD                    | Memory read from 003 -> 0A\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:EE          MREQ                       | \n#023H T19 AB:000 DB:EE          MREQ    WR                 | Memory write to  000 <- EE\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"0B\">Opcode: DD CB d 0B => RRC (IX+d),E*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:0B          MREQ RD                    | Memory read from 003 -> 0B\n#014H T10 AB:003 DB:0B          MREQ RD                    | Memory read from 003 -> 0B\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:EE          MREQ                       | \n#023H T19 AB:000 DB:EE          MREQ    WR                 | Memory write to  000 <- EE\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"0C\">Opcode: DD CB d 0C => RRC (IX+d),H*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:0C          MREQ RD                    | Memory read from 003 -> 0C\n#014H T10 AB:003 DB:0C          MREQ RD                    | Memory read from 003 -> 0C\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:EE          MREQ                       | \n#023H T19 AB:000 DB:EE          MREQ    WR                 | Memory write to  000 <- EE\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"0D\">Opcode: DD CB d 0D => RRC (IX+d),L*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:0D          MREQ RD                    | Memory read from 003 -> 0D\n#014H T10 AB:003 DB:0D          MREQ RD                    | Memory read from 003 -> 0D\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:EE          MREQ                       | \n#023H T19 AB:000 DB:EE          MREQ    WR                 | Memory write to  000 <- EE\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"0E\">Opcode: DD CB d 0E => RRC (IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:0E          MREQ RD                    | Memory read from 003 -> 0E\n#014H T10 AB:003 DB:0E          MREQ RD                    | Memory read from 003 -> 0E\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:EE          MREQ                       | \n#023H T19 AB:000 DB:EE          MREQ    WR                 | Memory write to  000 <- EE\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"0F\">Opcode: DD CB d 0F => RRC (IX+d),A*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:0F          MREQ RD                    | Memory read from 003 -> 0F\n#014H T10 AB:003 DB:0F          MREQ RD                    | Memory read from 003 -> 0F\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:EE          MREQ                       | \n#023H T19 AB:000 DB:EE          MREQ    WR                 | Memory write to  000 <- EE\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"10\">Opcode: DD CB d 10 => RL (IX+d),B*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:10          MREQ RD                    | Memory read from 003 -> 10\n#014H T10 AB:003 DB:10          MREQ RD                    | Memory read from 003 -> 10\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:BB          MREQ                       | \n#023H T19 AB:000 DB:BB          MREQ    WR                 | Memory write to  000 <- BB\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"11\">Opcode: DD CB d 11 => RL (IX+d),C*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:11          MREQ RD                    | Memory read from 003 -> 11\n#014H T10 AB:003 DB:11          MREQ RD                    | Memory read from 003 -> 11\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:BB          MREQ                       | \n#023H T19 AB:000 DB:BB          MREQ    WR                 | Memory write to  000 <- BB\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"12\">Opcode: DD CB d 12 => RL (IX+d),D*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:12          MREQ RD                    | Memory read from 003 -> 12\n#014H T10 AB:003 DB:12          MREQ RD                    | Memory read from 003 -> 12\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:BB          MREQ                       | \n#023H T19 AB:000 DB:BB          MREQ    WR                 | Memory write to  000 <- BB\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"13\">Opcode: DD CB d 13 => RL (IX+d),E*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:13          MREQ RD                    | Memory read from 003 -> 13\n#014H T10 AB:003 DB:13          MREQ RD                    | Memory read from 003 -> 13\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:BB          MREQ                       | \n#023H T19 AB:000 DB:BB          MREQ    WR                 | Memory write to  000 <- BB\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"14\">Opcode: DD CB d 14 => RL (IX+d),H*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:14          MREQ RD                    | Memory read from 003 -> 14\n#014H T10 AB:003 DB:14          MREQ RD                    | Memory read from 003 -> 14\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:BB          MREQ                       | \n#023H T19 AB:000 DB:BB          MREQ    WR                 | Memory write to  000 <- BB\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"15\">Opcode: DD CB d 15 => RL (IX+d),L*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:15          MREQ RD                    | Memory read from 003 -> 15\n#014H T10 AB:003 DB:15          MREQ RD                    | Memory read from 003 -> 15\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:BB          MREQ                       | \n#023H T19 AB:000 DB:BB          MREQ    WR                 | Memory write to  000 <- BB\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"16\">Opcode: DD CB d 16 => RL (IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:16          MREQ RD                    | Memory read from 003 -> 16\n#014H T10 AB:003 DB:16          MREQ RD                    | Memory read from 003 -> 16\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:BB          MREQ                       | \n#023H T19 AB:000 DB:BB          MREQ    WR                 | Memory write to  000 <- BB\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"17\">Opcode: DD CB d 17 => RL (IX+d),A*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:17          MREQ RD                    | Memory read from 003 -> 17\n#014H T10 AB:003 DB:17          MREQ RD                    | Memory read from 003 -> 17\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:BB          MREQ                       | \n#023H T19 AB:000 DB:BB          MREQ    WR                 | Memory write to  000 <- BB\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"18\">Opcode: DD CB d 18 => RR (IX+d),B*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:18          MREQ RD                    | Memory read from 003 -> 18\n#014H T10 AB:003 DB:18          MREQ RD                    | Memory read from 003 -> 18\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:EE          MREQ                       | \n#023H T19 AB:000 DB:EE          MREQ    WR                 | Memory write to  000 <- EE\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"19\">Opcode: DD CB d 19 => RR (IX+d),C*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:19          MREQ RD                    | Memory read from 003 -> 19\n#014H T10 AB:003 DB:19          MREQ RD                    | Memory read from 003 -> 19\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:EE          MREQ                       | \n#023H T19 AB:000 DB:EE          MREQ    WR                 | Memory write to  000 <- EE\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"1A\">Opcode: DD CB d 1A => RR (IX+d),D*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:1A          MREQ RD                    | Memory read from 003 -> 1A\n#014H T10 AB:003 DB:1A          MREQ RD                    | Memory read from 003 -> 1A\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:EE          MREQ                       | \n#023H T19 AB:000 DB:EE          MREQ    WR                 | Memory write to  000 <- EE\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"1B\">Opcode: DD CB d 1B => RR (IX+d),E*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:1B          MREQ RD                    | Memory read from 003 -> 1B\n#014H T10 AB:003 DB:1B          MREQ RD                    | Memory read from 003 -> 1B\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:EE          MREQ                       | \n#023H T19 AB:000 DB:EE          MREQ    WR                 | Memory write to  000 <- EE\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"1C\">Opcode: DD CB d 1C => RR (IX+d),H*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:1C          MREQ RD                    | Memory read from 003 -> 1C\n#014H T10 AB:003 DB:1C          MREQ RD                    | Memory read from 003 -> 1C\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:EE          MREQ                       | \n#023H T19 AB:000 DB:EE          MREQ    WR                 | Memory write to  000 <- EE\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"1D\">Opcode: DD CB d 1D => RR (IX+d),L*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:1D          MREQ RD                    | Memory read from 003 -> 1D\n#014H T10 AB:003 DB:1D          MREQ RD                    | Memory read from 003 -> 1D\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:EE          MREQ                       | \n#023H T19 AB:000 DB:EE          MREQ    WR                 | Memory write to  000 <- EE\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"1E\">Opcode: DD CB d 1E => RR (IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:1E          MREQ RD                    | Memory read from 003 -> 1E\n#014H T10 AB:003 DB:1E          MREQ RD                    | Memory read from 003 -> 1E\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:EE          MREQ                       | \n#023H T19 AB:000 DB:EE          MREQ    WR                 | Memory write to  000 <- EE\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"1F\">Opcode: DD CB d 1F => RR (IX+d),A*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:1F          MREQ RD                    | Memory read from 003 -> 1F\n#014H T10 AB:003 DB:1F          MREQ RD                    | Memory read from 003 -> 1F\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:EE          MREQ                       | \n#023H T19 AB:000 DB:EE          MREQ    WR                 | Memory write to  000 <- EE\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"20\">Opcode: DD CB d 20 => SLA (IX+d),B*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:20          MREQ RD                    | Memory read from 003 -> 20\n#014H T10 AB:003 DB:20          MREQ RD                    | Memory read from 003 -> 20\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:BA          MREQ                       | \n#023H T19 AB:000 DB:BA          MREQ    WR                 | Memory write to  000 <- BA\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"21\">Opcode: DD CB d 21 => SLA (IX+d),C*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:21          MREQ RD                    | Memory read from 003 -> 21\n#014H T10 AB:003 DB:21          MREQ RD                    | Memory read from 003 -> 21\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:BA          MREQ                       | \n#023H T19 AB:000 DB:BA          MREQ    WR                 | Memory write to  000 <- BA\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"22\">Opcode: DD CB d 22 => SLA (IX+d),D*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:22          MREQ RD                    | Memory read from 003 -> 22\n#014H T10 AB:003 DB:22          MREQ RD                    | Memory read from 003 -> 22\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:BA          MREQ                       | \n#023H T19 AB:000 DB:BA          MREQ    WR                 | Memory write to  000 <- BA\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"23\">Opcode: DD CB d 23 => SLA (IX+d),E*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:23          MREQ RD                    | Memory read from 003 -> 23\n#014H T10 AB:003 DB:23          MREQ RD                    | Memory read from 003 -> 23\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:BA          MREQ                       | \n#023H T19 AB:000 DB:BA          MREQ    WR                 | Memory write to  000 <- BA\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"24\">Opcode: DD CB d 24 => SLA (IX+d),H*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:24          MREQ RD                    | Memory read from 003 -> 24\n#014H T10 AB:003 DB:24          MREQ RD                    | Memory read from 003 -> 24\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:BA          MREQ                       | \n#023H T19 AB:000 DB:BA          MREQ    WR                 | Memory write to  000 <- BA\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"25\">Opcode: DD CB d 25 => SLA (IX+d),L*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:25          MREQ RD                    | Memory read from 003 -> 25\n#014H T10 AB:003 DB:25          MREQ RD                    | Memory read from 003 -> 25\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:BA          MREQ                       | \n#023H T19 AB:000 DB:BA          MREQ    WR                 | Memory write to  000 <- BA\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"26\">Opcode: DD CB d 26 => SLA (IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:26          MREQ RD                    | Memory read from 003 -> 26\n#014H T10 AB:003 DB:26          MREQ RD                    | Memory read from 003 -> 26\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:BA          MREQ                       | \n#023H T19 AB:000 DB:BA          MREQ    WR                 | Memory write to  000 <- BA\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"27\">Opcode: DD CB d 27 => SLA (IX+d),A*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:27          MREQ RD                    | Memory read from 003 -> 27\n#014H T10 AB:003 DB:27          MREQ RD                    | Memory read from 003 -> 27\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:BA          MREQ                       | \n#023H T19 AB:000 DB:BA          MREQ    WR                 | Memory write to  000 <- BA\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"28\">Opcode: DD CB d 28 => SRA (IX+d),B*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:28          MREQ RD                    | Memory read from 003 -> 28\n#014H T10 AB:003 DB:28          MREQ RD                    | Memory read from 003 -> 28\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:EE          MREQ                       | \n#023H T19 AB:000 DB:EE          MREQ    WR                 | Memory write to  000 <- EE\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"29\">Opcode: DD CB d 29 => SRA (IX+d),C*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:29          MREQ RD                    | Memory read from 003 -> 29\n#014H T10 AB:003 DB:29          MREQ RD                    | Memory read from 003 -> 29\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:EE          MREQ                       | \n#023H T19 AB:000 DB:EE          MREQ    WR                 | Memory write to  000 <- EE\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"2A\">Opcode: DD CB d 2A => SRA (IX+d),D*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:2A          MREQ RD                    | Memory read from 003 -> 2A\n#014H T10 AB:003 DB:2A          MREQ RD                    | Memory read from 003 -> 2A\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:EE          MREQ                       | \n#023H T19 AB:000 DB:EE          MREQ    WR                 | Memory write to  000 <- EE\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"2B\">Opcode: DD CB d 2B => SRA (IX+d),E*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:2B          MREQ RD                    | Memory read from 003 -> 2B\n#014H T10 AB:003 DB:2B          MREQ RD                    | Memory read from 003 -> 2B\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:EE          MREQ                       | \n#023H T19 AB:000 DB:EE          MREQ    WR                 | Memory write to  000 <- EE\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"2C\">Opcode: DD CB d 2C => SRA (IX+d),H*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:2C          MREQ RD                    | Memory read from 003 -> 2C\n#014H T10 AB:003 DB:2C          MREQ RD                    | Memory read from 003 -> 2C\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:EE          MREQ                       | \n#023H T19 AB:000 DB:EE          MREQ    WR                 | Memory write to  000 <- EE\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"2D\">Opcode: DD CB d 2D => SRA (IX+d),L*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:2D          MREQ RD                    | Memory read from 003 -> 2D\n#014H T10 AB:003 DB:2D          MREQ RD                    | Memory read from 003 -> 2D\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:EE          MREQ                       | \n#023H T19 AB:000 DB:EE          MREQ    WR                 | Memory write to  000 <- EE\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"2E\">Opcode: DD CB d 2E => SRA (IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:2E          MREQ RD                    | Memory read from 003 -> 2E\n#014H T10 AB:003 DB:2E          MREQ RD                    | Memory read from 003 -> 2E\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:EE          MREQ                       | \n#023H T19 AB:000 DB:EE          MREQ    WR                 | Memory write to  000 <- EE\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"2F\">Opcode: DD CB d 2F => SRA (IX+d),A*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:2F          MREQ RD                    | Memory read from 003 -> 2F\n#014H T10 AB:003 DB:2F          MREQ RD                    | Memory read from 003 -> 2F\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:EE          MREQ                       | \n#023H T19 AB:000 DB:EE          MREQ    WR                 | Memory write to  000 <- EE\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"30\">Opcode: DD CB d 30 => SLL (IX+d),B*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:30          MREQ RD                    | Memory read from 003 -> 30\n#014H T10 AB:003 DB:30          MREQ RD                    | Memory read from 003 -> 30\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:BB          MREQ                       | \n#023H T19 AB:000 DB:BB          MREQ    WR                 | Memory write to  000 <- BB\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"31\">Opcode: DD CB d 31 => SLL (IX+d),C*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:31          MREQ RD                    | Memory read from 003 -> 31\n#014H T10 AB:003 DB:31          MREQ RD                    | Memory read from 003 -> 31\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:BB          MREQ                       | \n#023H T19 AB:000 DB:BB          MREQ    WR                 | Memory write to  000 <- BB\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"32\">Opcode: DD CB d 32 => SLL (IX+d),D*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:32          MREQ RD                    | Memory read from 003 -> 32\n#014H T10 AB:003 DB:32          MREQ RD                    | Memory read from 003 -> 32\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:BB          MREQ                       | \n#023H T19 AB:000 DB:BB          MREQ    WR                 | Memory write to  000 <- BB\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"33\">Opcode: DD CB d 33 => SLL (IX+d),E*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:33          MREQ RD                    | Memory read from 003 -> 33\n#014H T10 AB:003 DB:33          MREQ RD                    | Memory read from 003 -> 33\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:BB          MREQ                       | \n#023H T19 AB:000 DB:BB          MREQ    WR                 | Memory write to  000 <- BB\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"34\">Opcode: DD CB d 34 => SLL (IX+d),H*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:34          MREQ RD                    | Memory read from 003 -> 34\n#014H T10 AB:003 DB:34          MREQ RD                    | Memory read from 003 -> 34\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:BB          MREQ                       | \n#023H T19 AB:000 DB:BB          MREQ    WR                 | Memory write to  000 <- BB\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"35\">Opcode: DD CB d 35 => SLL (IX+d),L*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:35          MREQ RD                    | Memory read from 003 -> 35\n#014H T10 AB:003 DB:35          MREQ RD                    | Memory read from 003 -> 35\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:BB          MREQ                       | \n#023H T19 AB:000 DB:BB          MREQ    WR                 | Memory write to  000 <- BB\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"36\">Opcode: DD CB d 36 => SLL (IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:36          MREQ RD                    | Memory read from 003 -> 36\n#014H T10 AB:003 DB:36          MREQ RD                    | Memory read from 003 -> 36\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:BB          MREQ                       | \n#023H T19 AB:000 DB:BB          MREQ    WR                 | Memory write to  000 <- BB\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"37\">Opcode: DD CB d 37 => SLL (IX+d),A*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:37          MREQ RD                    | Memory read from 003 -> 37\n#014H T10 AB:003 DB:37          MREQ RD                    | Memory read from 003 -> 37\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:BB          MREQ                       | \n#023H T19 AB:000 DB:BB          MREQ    WR                 | Memory write to  000 <- BB\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"38\">Opcode: DD CB d 38 => SRL (IX+d),B*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:38          MREQ RD                    | Memory read from 003 -> 38\n#014H T10 AB:003 DB:38          MREQ RD                    | Memory read from 003 -> 38\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:6E          MREQ                       | \n#023H T19 AB:000 DB:6E          MREQ    WR                 | Memory write to  000 <- 6E\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"39\">Opcode: DD CB d 39 => SRL (IX+d),C*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:39          MREQ RD                    | Memory read from 003 -> 39\n#014H T10 AB:003 DB:39          MREQ RD                    | Memory read from 003 -> 39\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:6E          MREQ                       | \n#023H T19 AB:000 DB:6E          MREQ    WR                 | Memory write to  000 <- 6E\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"3A\">Opcode: DD CB d 3A => SRL (IX+d),D*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:3A          MREQ RD                    | Memory read from 003 -> 3A\n#014H T10 AB:003 DB:3A          MREQ RD                    | Memory read from 003 -> 3A\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:6E          MREQ                       | \n#023H T19 AB:000 DB:6E          MREQ    WR                 | Memory write to  000 <- 6E\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"3B\">Opcode: DD CB d 3B => SRL (IX+d),E*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:3B          MREQ RD                    | Memory read from 003 -> 3B\n#014H T10 AB:003 DB:3B          MREQ RD                    | Memory read from 003 -> 3B\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:6E          MREQ                       | \n#023H T19 AB:000 DB:6E          MREQ    WR                 | Memory write to  000 <- 6E\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"3C\">Opcode: DD CB d 3C => SRL (IX+d),H*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:3C          MREQ RD                    | Memory read from 003 -> 3C\n#014H T10 AB:003 DB:3C          MREQ RD                    | Memory read from 003 -> 3C\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:6E          MREQ                       | \n#023H T19 AB:000 DB:6E          MREQ    WR                 | Memory write to  000 <- 6E\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"3D\">Opcode: DD CB d 3D => SRL (IX+d),L*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:3D          MREQ RD                    | Memory read from 003 -> 3D\n#014H T10 AB:003 DB:3D          MREQ RD                    | Memory read from 003 -> 3D\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:6E          MREQ                       | \n#023H T19 AB:000 DB:6E          MREQ    WR                 | Memory write to  000 <- 6E\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"3E\">Opcode: DD CB d 3E => SRL (IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:3E          MREQ RD                    | Memory read from 003 -> 3E\n#014H T10 AB:003 DB:3E          MREQ RD                    | Memory read from 003 -> 3E\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:6E          MREQ                       | \n#023H T19 AB:000 DB:6E          MREQ    WR                 | Memory write to  000 <- 6E\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"3F\">Opcode: DD CB d 3F => SRL (IX+d),A*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:3F          MREQ RD                    | Memory read from 003 -> 3F\n#014H T10 AB:003 DB:3F          MREQ RD                    | Memory read from 003 -> 3F\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:6E          MREQ                       | \n#023H T19 AB:000 DB:6E          MREQ    WR                 | Memory write to  000 <- 6E\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"40\">Opcode: DD CB d 40 => BIT 0,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:40          MREQ RD                    | Memory read from 003 -> 40\n#014H T10 AB:003 DB:40          MREQ RD                    | Memory read from 003 -> 40\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"41\">Opcode: DD CB d 41 => BIT 0,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:41          MREQ RD                    | Memory read from 003 -> 41\n#014H T10 AB:003 DB:41          MREQ RD                    | Memory read from 003 -> 41\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"42\">Opcode: DD CB d 42 => BIT 0,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:42          MREQ RD                    | Memory read from 003 -> 42\n#014H T10 AB:003 DB:42          MREQ RD                    | Memory read from 003 -> 42\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"43\">Opcode: DD CB d 43 => BIT 0,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:43          MREQ RD                    | Memory read from 003 -> 43\n#014H T10 AB:003 DB:43          MREQ RD                    | Memory read from 003 -> 43\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"44\">Opcode: DD CB d 44 => BIT 0,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:44          MREQ RD                    | Memory read from 003 -> 44\n#014H T10 AB:003 DB:44          MREQ RD                    | Memory read from 003 -> 44\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"45\">Opcode: DD CB d 45 => BIT 0,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:45          MREQ RD                    | Memory read from 003 -> 45\n#014H T10 AB:003 DB:45          MREQ RD                    | Memory read from 003 -> 45\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"46\">Opcode: DD CB d 46 => BIT 0,(IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:46          MREQ RD                    | Memory read from 003 -> 46\n#014H T10 AB:003 DB:46          MREQ RD                    | Memory read from 003 -> 46\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"47\">Opcode: DD CB d 47 => BIT 0,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:47          MREQ RD                    | Memory read from 003 -> 47\n#014H T10 AB:003 DB:47          MREQ RD                    | Memory read from 003 -> 47\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"48\">Opcode: DD CB d 48 => BIT 1,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:48          MREQ RD                    | Memory read from 003 -> 48\n#014H T10 AB:003 DB:48          MREQ RD                    | Memory read from 003 -> 48\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"49\">Opcode: DD CB d 49 => BIT 1,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:49          MREQ RD                    | Memory read from 003 -> 49\n#014H T10 AB:003 DB:49          MREQ RD                    | Memory read from 003 -> 49\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"4A\">Opcode: DD CB d 4A => BIT 1,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:4A          MREQ RD                    | Memory read from 003 -> 4A\n#014H T10 AB:003 DB:4A          MREQ RD                    | Memory read from 003 -> 4A\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"4B\">Opcode: DD CB d 4B => BIT 1,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:4B          MREQ RD                    | Memory read from 003 -> 4B\n#014H T10 AB:003 DB:4B          MREQ RD                    | Memory read from 003 -> 4B\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"4C\">Opcode: DD CB d 4C => BIT 1,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:4C          MREQ RD                    | Memory read from 003 -> 4C\n#014H T10 AB:003 DB:4C          MREQ RD                    | Memory read from 003 -> 4C\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"4D\">Opcode: DD CB d 4D => BIT 1,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:4D          MREQ RD                    | Memory read from 003 -> 4D\n#014H T10 AB:003 DB:4D          MREQ RD                    | Memory read from 003 -> 4D\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"4E\">Opcode: DD CB d 4E => BIT 1,(IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:4E          MREQ RD                    | Memory read from 003 -> 4E\n#014H T10 AB:003 DB:4E          MREQ RD                    | Memory read from 003 -> 4E\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"4F\">Opcode: DD CB d 4F => BIT 1,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:4F          MREQ RD                    | Memory read from 003 -> 4F\n#014H T10 AB:003 DB:4F          MREQ RD                    | Memory read from 003 -> 4F\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"50\">Opcode: DD CB d 50 => BIT 2,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:50          MREQ RD                    | Memory read from 003 -> 50\n#014H T10 AB:003 DB:50          MREQ RD                    | Memory read from 003 -> 50\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"51\">Opcode: DD CB d 51 => BIT 2,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:51          MREQ RD                    | Memory read from 003 -> 51\n#014H T10 AB:003 DB:51          MREQ RD                    | Memory read from 003 -> 51\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"52\">Opcode: DD CB d 52 => BIT 2,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:52          MREQ RD                    | Memory read from 003 -> 52\n#014H T10 AB:003 DB:52          MREQ RD                    | Memory read from 003 -> 52\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"53\">Opcode: DD CB d 53 => BIT 2,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:53          MREQ RD                    | Memory read from 003 -> 53\n#014H T10 AB:003 DB:53          MREQ RD                    | Memory read from 003 -> 53\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"54\">Opcode: DD CB d 54 => BIT 2,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:54          MREQ RD                    | Memory read from 003 -> 54\n#014H T10 AB:003 DB:54          MREQ RD                    | Memory read from 003 -> 54\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"55\">Opcode: DD CB d 55 => BIT 2,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:55          MREQ RD                    | Memory read from 003 -> 55\n#014H T10 AB:003 DB:55          MREQ RD                    | Memory read from 003 -> 55\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"56\">Opcode: DD CB d 56 => BIT 2,(IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:56          MREQ RD                    | Memory read from 003 -> 56\n#014H T10 AB:003 DB:56          MREQ RD                    | Memory read from 003 -> 56\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"57\">Opcode: DD CB d 57 => BIT 2,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:57          MREQ RD                    | Memory read from 003 -> 57\n#014H T10 AB:003 DB:57          MREQ RD                    | Memory read from 003 -> 57\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"58\">Opcode: DD CB d 58 => BIT 3,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:58          MREQ RD                    | Memory read from 003 -> 58\n#014H T10 AB:003 DB:58          MREQ RD                    | Memory read from 003 -> 58\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"59\">Opcode: DD CB d 59 => BIT 3,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:59          MREQ RD                    | Memory read from 003 -> 59\n#014H T10 AB:003 DB:59          MREQ RD                    | Memory read from 003 -> 59\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"5A\">Opcode: DD CB d 5A => BIT 3,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:5A          MREQ RD                    | Memory read from 003 -> 5A\n#014H T10 AB:003 DB:5A          MREQ RD                    | Memory read from 003 -> 5A\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"5B\">Opcode: DD CB d 5B => BIT 3,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:5B          MREQ RD                    | Memory read from 003 -> 5B\n#014H T10 AB:003 DB:5B          MREQ RD                    | Memory read from 003 -> 5B\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"5C\">Opcode: DD CB d 5C => BIT 3,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:5C          MREQ RD                    | Memory read from 003 -> 5C\n#014H T10 AB:003 DB:5C          MREQ RD                    | Memory read from 003 -> 5C\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"5D\">Opcode: DD CB d 5D => BIT 3,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:5D          MREQ RD                    | Memory read from 003 -> 5D\n#014H T10 AB:003 DB:5D          MREQ RD                    | Memory read from 003 -> 5D\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"5E\">Opcode: DD CB d 5E => BIT 3,(IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:5E          MREQ RD                    | Memory read from 003 -> 5E\n#014H T10 AB:003 DB:5E          MREQ RD                    | Memory read from 003 -> 5E\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"5F\">Opcode: DD CB d 5F => BIT 3,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:5F          MREQ RD                    | Memory read from 003 -> 5F\n#014H T10 AB:003 DB:5F          MREQ RD                    | Memory read from 003 -> 5F\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"60\">Opcode: DD CB d 60 => BIT 4,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:60          MREQ RD                    | Memory read from 003 -> 60\n#014H T10 AB:003 DB:60          MREQ RD                    | Memory read from 003 -> 60\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"61\">Opcode: DD CB d 61 => BIT 4,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:61          MREQ RD                    | Memory read from 003 -> 61\n#014H T10 AB:003 DB:61          MREQ RD                    | Memory read from 003 -> 61\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"62\">Opcode: DD CB d 62 => BIT 4,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:62          MREQ RD                    | Memory read from 003 -> 62\n#014H T10 AB:003 DB:62          MREQ RD                    | Memory read from 003 -> 62\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"63\">Opcode: DD CB d 63 => BIT 4,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:63          MREQ RD                    | Memory read from 003 -> 63\n#014H T10 AB:003 DB:63          MREQ RD                    | Memory read from 003 -> 63\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"64\">Opcode: DD CB d 64 => BIT 4,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:64          MREQ RD                    | Memory read from 003 -> 64\n#014H T10 AB:003 DB:64          MREQ RD                    | Memory read from 003 -> 64\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"65\">Opcode: DD CB d 65 => BIT 4,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:65          MREQ RD                    | Memory read from 003 -> 65\n#014H T10 AB:003 DB:65          MREQ RD                    | Memory read from 003 -> 65\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"66\">Opcode: DD CB d 66 => BIT 4,(IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:66          MREQ RD                    | Memory read from 003 -> 66\n#014H T10 AB:003 DB:66          MREQ RD                    | Memory read from 003 -> 66\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"67\">Opcode: DD CB d 67 => BIT 4,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:67          MREQ RD                    | Memory read from 003 -> 67\n#014H T10 AB:003 DB:67          MREQ RD                    | Memory read from 003 -> 67\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"68\">Opcode: DD CB d 68 => BIT 5,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:68          MREQ RD                    | Memory read from 003 -> 68\n#014H T10 AB:003 DB:68          MREQ RD                    | Memory read from 003 -> 68\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"69\">Opcode: DD CB d 69 => BIT 5,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:69          MREQ RD                    | Memory read from 003 -> 69\n#014H T10 AB:003 DB:69          MREQ RD                    | Memory read from 003 -> 69\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"6A\">Opcode: DD CB d 6A => BIT 5,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:6A          MREQ RD                    | Memory read from 003 -> 6A\n#014H T10 AB:003 DB:6A          MREQ RD                    | Memory read from 003 -> 6A\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"6B\">Opcode: DD CB d 6B => BIT 5,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:6B          MREQ RD                    | Memory read from 003 -> 6B\n#014H T10 AB:003 DB:6B          MREQ RD                    | Memory read from 003 -> 6B\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"6C\">Opcode: DD CB d 6C => BIT 5,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:6C          MREQ RD                    | Memory read from 003 -> 6C\n#014H T10 AB:003 DB:6C          MREQ RD                    | Memory read from 003 -> 6C\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"6D\">Opcode: DD CB d 6D => BIT 5,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:6D          MREQ RD                    | Memory read from 003 -> 6D\n#014H T10 AB:003 DB:6D          MREQ RD                    | Memory read from 003 -> 6D\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"6E\">Opcode: DD CB d 6E => BIT 5,(IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:6E          MREQ RD                    | Memory read from 003 -> 6E\n#014H T10 AB:003 DB:6E          MREQ RD                    | Memory read from 003 -> 6E\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"6F\">Opcode: DD CB d 6F => BIT 5,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:6F          MREQ RD                    | Memory read from 003 -> 6F\n#014H T10 AB:003 DB:6F          MREQ RD                    | Memory read from 003 -> 6F\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"70\">Opcode: DD CB d 70 => BIT 6,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:70          MREQ RD                    | Memory read from 003 -> 70\n#014H T10 AB:003 DB:70          MREQ RD                    | Memory read from 003 -> 70\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"71\">Opcode: DD CB d 71 => BIT 6,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:71          MREQ RD                    | Memory read from 003 -> 71\n#014H T10 AB:003 DB:71          MREQ RD                    | Memory read from 003 -> 71\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"72\">Opcode: DD CB d 72 => BIT 6,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:72          MREQ RD                    | Memory read from 003 -> 72\n#014H T10 AB:003 DB:72          MREQ RD                    | Memory read from 003 -> 72\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"73\">Opcode: DD CB d 73 => BIT 6,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:73          MREQ RD                    | Memory read from 003 -> 73\n#014H T10 AB:003 DB:73          MREQ RD                    | Memory read from 003 -> 73\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"74\">Opcode: DD CB d 74 => BIT 6,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:74          MREQ RD                    | Memory read from 003 -> 74\n#014H T10 AB:003 DB:74          MREQ RD                    | Memory read from 003 -> 74\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"75\">Opcode: DD CB d 75 => BIT 6,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:75          MREQ RD                    | Memory read from 003 -> 75\n#014H T10 AB:003 DB:75          MREQ RD                    | Memory read from 003 -> 75\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"76\">Opcode: DD CB d 76 => BIT 6,(IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:76          MREQ RD                    | Memory read from 003 -> 76\n#014H T10 AB:003 DB:76          MREQ RD                    | Memory read from 003 -> 76\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"77\">Opcode: DD CB d 77 => BIT 6,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:77          MREQ RD                    | Memory read from 003 -> 77\n#014H T10 AB:003 DB:77          MREQ RD                    | Memory read from 003 -> 77\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"78\">Opcode: DD CB d 78 => BIT 7,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:78          MREQ RD                    | Memory read from 003 -> 78\n#014H T10 AB:003 DB:78          MREQ RD                    | Memory read from 003 -> 78\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"79\">Opcode: DD CB d 79 => BIT 7,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:79          MREQ RD                    | Memory read from 003 -> 79\n#014H T10 AB:003 DB:79          MREQ RD                    | Memory read from 003 -> 79\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"7A\">Opcode: DD CB d 7A => BIT 7,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:7A          MREQ RD                    | Memory read from 003 -> 7A\n#014H T10 AB:003 DB:7A          MREQ RD                    | Memory read from 003 -> 7A\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"7B\">Opcode: DD CB d 7B => BIT 7,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:7B          MREQ RD                    | Memory read from 003 -> 7B\n#014H T10 AB:003 DB:7B          MREQ RD                    | Memory read from 003 -> 7B\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"7C\">Opcode: DD CB d 7C => BIT 7,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:7C          MREQ RD                    | Memory read from 003 -> 7C\n#014H T10 AB:003 DB:7C          MREQ RD                    | Memory read from 003 -> 7C\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"7D\">Opcode: DD CB d 7D => BIT 7,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:7D          MREQ RD                    | Memory read from 003 -> 7D\n#014H T10 AB:003 DB:7D          MREQ RD                    | Memory read from 003 -> 7D\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"7E\">Opcode: DD CB d 7E => BIT 7,(IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:7E          MREQ RD                    | Memory read from 003 -> 7E\n#014H T10 AB:003 DB:7E          MREQ RD                    | Memory read from 003 -> 7E\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"7F\">Opcode: DD CB d 7F => BIT 7,(IX+d)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:7F          MREQ RD                    | Memory read from 003 -> 7F\n#014H T10 AB:003 DB:7F          MREQ RD                    | Memory read from 003 -> 7F\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"80\">Opcode: DD CB d 80 => RES 0,(IX+d),B*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:80          MREQ RD                    | Memory read from 003 -> 80\n#014H T10 AB:003 DB:80          MREQ RD                    | Memory read from 003 -> 80\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DC          MREQ                       | \n#023H T19 AB:000 DB:DC          MREQ    WR                 | Memory write to  000 <- DC\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"81\">Opcode: DD CB d 81 => RES 0,(IX+d),C*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:81          MREQ RD                    | Memory read from 003 -> 81\n#014H T10 AB:003 DB:81          MREQ RD                    | Memory read from 003 -> 81\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DC          MREQ                       | \n#023H T19 AB:000 DB:DC          MREQ    WR                 | Memory write to  000 <- DC\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"82\">Opcode: DD CB d 82 => RES 0,(IX+d),D*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:82          MREQ RD                    | Memory read from 003 -> 82\n#014H T10 AB:003 DB:82          MREQ RD                    | Memory read from 003 -> 82\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DC          MREQ                       | \n#023H T19 AB:000 DB:DC          MREQ    WR                 | Memory write to  000 <- DC\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"83\">Opcode: DD CB d 83 => RES 0,(IX+d),E*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:83          MREQ RD                    | Memory read from 003 -> 83\n#014H T10 AB:003 DB:83          MREQ RD                    | Memory read from 003 -> 83\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DC          MREQ                       | \n#023H T19 AB:000 DB:DC          MREQ    WR                 | Memory write to  000 <- DC\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"84\">Opcode: DD CB d 84 => RES 0,(IX+d),H*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:84          MREQ RD                    | Memory read from 003 -> 84\n#014H T10 AB:003 DB:84          MREQ RD                    | Memory read from 003 -> 84\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DC          MREQ                       | \n#023H T19 AB:000 DB:DC          MREQ    WR                 | Memory write to  000 <- DC\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"85\">Opcode: DD CB d 85 => RES 0,(IX+d),L*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:85          MREQ RD                    | Memory read from 003 -> 85\n#014H T10 AB:003 DB:85          MREQ RD                    | Memory read from 003 -> 85\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DC          MREQ                       | \n#023H T19 AB:000 DB:DC          MREQ    WR                 | Memory write to  000 <- DC\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"86\">Opcode: DD CB d 86 => RES 0,(IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:86          MREQ RD                    | Memory read from 003 -> 86\n#014H T10 AB:003 DB:86          MREQ RD                    | Memory read from 003 -> 86\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DC          MREQ                       | \n#023H T19 AB:000 DB:DC          MREQ    WR                 | Memory write to  000 <- DC\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"87\">Opcode: DD CB d 87 => RES 0,(IX+d),A*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:87          MREQ RD                    | Memory read from 003 -> 87\n#014H T10 AB:003 DB:87          MREQ RD                    | Memory read from 003 -> 87\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DC          MREQ                       | \n#023H T19 AB:000 DB:DC          MREQ    WR                 | Memory write to  000 <- DC\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"88\">Opcode: DD CB d 88 => RES 1,(IX+d),B*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:88          MREQ RD                    | Memory read from 003 -> 88\n#014H T10 AB:003 DB:88          MREQ RD                    | Memory read from 003 -> 88\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"89\">Opcode: DD CB d 89 => RES 1,(IX+d),C*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:89          MREQ RD                    | Memory read from 003 -> 89\n#014H T10 AB:003 DB:89          MREQ RD                    | Memory read from 003 -> 89\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"8A\">Opcode: DD CB d 8A => RES 1,(IX+d),D*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:8A          MREQ RD                    | Memory read from 003 -> 8A\n#014H T10 AB:003 DB:8A          MREQ RD                    | Memory read from 003 -> 8A\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"8B\">Opcode: DD CB d 8B => RES 1,(IX+d),E*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:8B          MREQ RD                    | Memory read from 003 -> 8B\n#014H T10 AB:003 DB:8B          MREQ RD                    | Memory read from 003 -> 8B\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"8C\">Opcode: DD CB d 8C => RES 1,(IX+d),H*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:8C          MREQ RD                    | Memory read from 003 -> 8C\n#014H T10 AB:003 DB:8C          MREQ RD                    | Memory read from 003 -> 8C\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"8D\">Opcode: DD CB d 8D => RES 1,(IX+d),L*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:8D          MREQ RD                    | Memory read from 003 -> 8D\n#014H T10 AB:003 DB:8D          MREQ RD                    | Memory read from 003 -> 8D\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"8E\">Opcode: DD CB d 8E => RES 1,(IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:8E          MREQ RD                    | Memory read from 003 -> 8E\n#014H T10 AB:003 DB:8E          MREQ RD                    | Memory read from 003 -> 8E\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"8F\">Opcode: DD CB d 8F => RES 1,(IX+d),A*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:8F          MREQ RD                    | Memory read from 003 -> 8F\n#014H T10 AB:003 DB:8F          MREQ RD                    | Memory read from 003 -> 8F\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"90\">Opcode: DD CB d 90 => RES 2,(IX+d),B*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:90          MREQ RD                    | Memory read from 003 -> 90\n#014H T10 AB:003 DB:90          MREQ RD                    | Memory read from 003 -> 90\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:D9          MREQ                       | \n#023H T19 AB:000 DB:D9          MREQ    WR                 | Memory write to  000 <- D9\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"91\">Opcode: DD CB d 91 => RES 2,(IX+d),C*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:91          MREQ RD                    | Memory read from 003 -> 91\n#014H T10 AB:003 DB:91          MREQ RD                    | Memory read from 003 -> 91\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:D9          MREQ                       | \n#023H T19 AB:000 DB:D9          MREQ    WR                 | Memory write to  000 <- D9\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"92\">Opcode: DD CB d 92 => RES 2,(IX+d),D*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:92          MREQ RD                    | Memory read from 003 -> 92\n#014H T10 AB:003 DB:92          MREQ RD                    | Memory read from 003 -> 92\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:D9          MREQ                       | \n#023H T19 AB:000 DB:D9          MREQ    WR                 | Memory write to  000 <- D9\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"93\">Opcode: DD CB d 93 => RES 2,(IX+d),E*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:93          MREQ RD                    | Memory read from 003 -> 93\n#014H T10 AB:003 DB:93          MREQ RD                    | Memory read from 003 -> 93\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:D9          MREQ                       | \n#023H T19 AB:000 DB:D9          MREQ    WR                 | Memory write to  000 <- D9\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"94\">Opcode: DD CB d 94 => RES 2,(IX+d),H*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:94          MREQ RD                    | Memory read from 003 -> 94\n#014H T10 AB:003 DB:94          MREQ RD                    | Memory read from 003 -> 94\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:D9          MREQ                       | \n#023H T19 AB:000 DB:D9          MREQ    WR                 | Memory write to  000 <- D9\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"95\">Opcode: DD CB d 95 => RES 2,(IX+d),L*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:95          MREQ RD                    | Memory read from 003 -> 95\n#014H T10 AB:003 DB:95          MREQ RD                    | Memory read from 003 -> 95\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:D9          MREQ                       | \n#023H T19 AB:000 DB:D9          MREQ    WR                 | Memory write to  000 <- D9\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"96\">Opcode: DD CB d 96 => RES 2,(IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:96          MREQ RD                    | Memory read from 003 -> 96\n#014H T10 AB:003 DB:96          MREQ RD                    | Memory read from 003 -> 96\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:D9          MREQ                       | \n#023H T19 AB:000 DB:D9          MREQ    WR                 | Memory write to  000 <- D9\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"97\">Opcode: DD CB d 97 => RES 2,(IX+d),A*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:97          MREQ RD                    | Memory read from 003 -> 97\n#014H T10 AB:003 DB:97          MREQ RD                    | Memory read from 003 -> 97\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:D9          MREQ                       | \n#023H T19 AB:000 DB:D9          MREQ    WR                 | Memory write to  000 <- D9\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"98\">Opcode: DD CB d 98 => RES 3,(IX+d),B*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:98          MREQ RD                    | Memory read from 003 -> 98\n#014H T10 AB:003 DB:98          MREQ RD                    | Memory read from 003 -> 98\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:D5          MREQ                       | \n#023H T19 AB:000 DB:D5          MREQ    WR                 | Memory write to  000 <- D5\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"99\">Opcode: DD CB d 99 => RES 3,(IX+d),C*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:99          MREQ RD                    | Memory read from 003 -> 99\n#014H T10 AB:003 DB:99          MREQ RD                    | Memory read from 003 -> 99\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:D5          MREQ                       | \n#023H T19 AB:000 DB:D5          MREQ    WR                 | Memory write to  000 <- D5\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"9A\">Opcode: DD CB d 9A => RES 3,(IX+d),D*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:9A          MREQ RD                    | Memory read from 003 -> 9A\n#014H T10 AB:003 DB:9A          MREQ RD                    | Memory read from 003 -> 9A\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:D5          MREQ                       | \n#023H T19 AB:000 DB:D5          MREQ    WR                 | Memory write to  000 <- D5\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"9B\">Opcode: DD CB d 9B => RES 3,(IX+d),E*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:9B          MREQ RD                    | Memory read from 003 -> 9B\n#014H T10 AB:003 DB:9B          MREQ RD                    | Memory read from 003 -> 9B\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:D5          MREQ                       | \n#023H T19 AB:000 DB:D5          MREQ    WR                 | Memory write to  000 <- D5\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"9C\">Opcode: DD CB d 9C => RES 3,(IX+d),H*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:9C          MREQ RD                    | Memory read from 003 -> 9C\n#014H T10 AB:003 DB:9C          MREQ RD                    | Memory read from 003 -> 9C\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:D5          MREQ                       | \n#023H T19 AB:000 DB:D5          MREQ    WR                 | Memory write to  000 <- D5\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"9D\">Opcode: DD CB d 9D => RES 3,(IX+d),L*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:9D          MREQ RD                    | Memory read from 003 -> 9D\n#014H T10 AB:003 DB:9D          MREQ RD                    | Memory read from 003 -> 9D\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:D5          MREQ                       | \n#023H T19 AB:000 DB:D5          MREQ    WR                 | Memory write to  000 <- D5\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"9E\">Opcode: DD CB d 9E => RES 3,(IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:9E          MREQ RD                    | Memory read from 003 -> 9E\n#014H T10 AB:003 DB:9E          MREQ RD                    | Memory read from 003 -> 9E\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:D5          MREQ                       | \n#023H T19 AB:000 DB:D5          MREQ    WR                 | Memory write to  000 <- D5\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"9F\">Opcode: DD CB d 9F => RES 3,(IX+d),A*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:9F          MREQ RD                    | Memory read from 003 -> 9F\n#014H T10 AB:003 DB:9F          MREQ RD                    | Memory read from 003 -> 9F\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:D5          MREQ                       | \n#023H T19 AB:000 DB:D5          MREQ    WR                 | Memory write to  000 <- D5\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"A0\">Opcode: DD CB d A0 => RES 4,(IX+d),B*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:A0          MREQ RD                    | Memory read from 003 -> A0\n#014H T10 AB:003 DB:A0          MREQ RD                    | Memory read from 003 -> A0\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:CD          MREQ                       | \n#023H T19 AB:000 DB:CD          MREQ    WR                 | Memory write to  000 <- CD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"A1\">Opcode: DD CB d A1 => RES 4,(IX+d),C*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:A1          MREQ RD                    | Memory read from 003 -> A1\n#014H T10 AB:003 DB:A1          MREQ RD                    | Memory read from 003 -> A1\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:CD          MREQ                       | \n#023H T19 AB:000 DB:CD          MREQ    WR                 | Memory write to  000 <- CD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"A2\">Opcode: DD CB d A2 => RES 4,(IX+d),D*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:A2          MREQ RD                    | Memory read from 003 -> A2\n#014H T10 AB:003 DB:A2          MREQ RD                    | Memory read from 003 -> A2\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:CD          MREQ                       | \n#023H T19 AB:000 DB:CD          MREQ    WR                 | Memory write to  000 <- CD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"A3\">Opcode: DD CB d A3 => RES 4,(IX+d),E*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:A3          MREQ RD                    | Memory read from 003 -> A3\n#014H T10 AB:003 DB:A3          MREQ RD                    | Memory read from 003 -> A3\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:CD          MREQ                       | \n#023H T19 AB:000 DB:CD          MREQ    WR                 | Memory write to  000 <- CD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"A4\">Opcode: DD CB d A4 => RES 4,(IX+d),H*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:A4          MREQ RD                    | Memory read from 003 -> A4\n#014H T10 AB:003 DB:A4          MREQ RD                    | Memory read from 003 -> A4\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:CD          MREQ                       | \n#023H T19 AB:000 DB:CD          MREQ    WR                 | Memory write to  000 <- CD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"A5\">Opcode: DD CB d A5 => RES 4,(IX+d),L*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:A5          MREQ RD                    | Memory read from 003 -> A5\n#014H T10 AB:003 DB:A5          MREQ RD                    | Memory read from 003 -> A5\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:CD          MREQ                       | \n#023H T19 AB:000 DB:CD          MREQ    WR                 | Memory write to  000 <- CD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"A6\">Opcode: DD CB d A6 => RES 4,(IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:A6          MREQ RD                    | Memory read from 003 -> A6\n#014H T10 AB:003 DB:A6          MREQ RD                    | Memory read from 003 -> A6\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:CD          MREQ                       | \n#023H T19 AB:000 DB:CD          MREQ    WR                 | Memory write to  000 <- CD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"A7\">Opcode: DD CB d A7 => RES 4,(IX+d),A*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:A7          MREQ RD                    | Memory read from 003 -> A7\n#014H T10 AB:003 DB:A7          MREQ RD                    | Memory read from 003 -> A7\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:CD          MREQ                       | \n#023H T19 AB:000 DB:CD          MREQ    WR                 | Memory write to  000 <- CD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"A8\">Opcode: DD CB d A8 => RES 5,(IX+d),B*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:A8          MREQ RD                    | Memory read from 003 -> A8\n#014H T10 AB:003 DB:A8          MREQ RD                    | Memory read from 003 -> A8\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"A9\">Opcode: DD CB d A9 => RES 5,(IX+d),C*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:A9          MREQ RD                    | Memory read from 003 -> A9\n#014H T10 AB:003 DB:A9          MREQ RD                    | Memory read from 003 -> A9\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"AA\">Opcode: DD CB d AA => RES 5,(IX+d),D*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:AA          MREQ RD                    | Memory read from 003 -> AA\n#014H T10 AB:003 DB:AA          MREQ RD                    | Memory read from 003 -> AA\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"AB\">Opcode: DD CB d AB => RES 5,(IX+d),E*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:AB          MREQ RD                    | Memory read from 003 -> AB\n#014H T10 AB:003 DB:AB          MREQ RD                    | Memory read from 003 -> AB\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"AC\">Opcode: DD CB d AC => RES 5,(IX+d),H*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:AC          MREQ RD                    | Memory read from 003 -> AC\n#014H T10 AB:003 DB:AC          MREQ RD                    | Memory read from 003 -> AC\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"AD\">Opcode: DD CB d AD => RES 5,(IX+d),L*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:AD          MREQ RD                    | Memory read from 003 -> AD\n#014H T10 AB:003 DB:AD          MREQ RD                    | Memory read from 003 -> AD\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"AE\">Opcode: DD CB d AE => RES 5,(IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:AE          MREQ RD                    | Memory read from 003 -> AE\n#014H T10 AB:003 DB:AE          MREQ RD                    | Memory read from 003 -> AE\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"AF\">Opcode: DD CB d AF => RES 5,(IX+d),A*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:AF          MREQ RD                    | Memory read from 003 -> AF\n#014H T10 AB:003 DB:AF          MREQ RD                    | Memory read from 003 -> AF\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"B0\">Opcode: DD CB d B0 => RES 6,(IX+d),B*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:B0          MREQ RD                    | Memory read from 003 -> B0\n#014H T10 AB:003 DB:B0          MREQ RD                    | Memory read from 003 -> B0\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:9D          MREQ                       | \n#023H T19 AB:000 DB:9D          MREQ    WR                 | Memory write to  000 <- 9D\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"B1\">Opcode: DD CB d B1 => RES 6,(IX+d),C*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:B1          MREQ RD                    | Memory read from 003 -> B1\n#014H T10 AB:003 DB:B1          MREQ RD                    | Memory read from 003 -> B1\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:9D          MREQ                       | \n#023H T19 AB:000 DB:9D          MREQ    WR                 | Memory write to  000 <- 9D\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"B2\">Opcode: DD CB d B2 => RES 6,(IX+d),D*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:B2          MREQ RD                    | Memory read from 003 -> B2\n#014H T10 AB:003 DB:B2          MREQ RD                    | Memory read from 003 -> B2\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:9D          MREQ                       | \n#023H T19 AB:000 DB:9D          MREQ    WR                 | Memory write to  000 <- 9D\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"B3\">Opcode: DD CB d B3 => RES 6,(IX+d),E*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:B3          MREQ RD                    | Memory read from 003 -> B3\n#014H T10 AB:003 DB:B3          MREQ RD                    | Memory read from 003 -> B3\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:9D          MREQ                       | \n#023H T19 AB:000 DB:9D          MREQ    WR                 | Memory write to  000 <- 9D\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"B4\">Opcode: DD CB d B4 => RES 6,(IX+d),H*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:B4          MREQ RD                    | Memory read from 003 -> B4\n#014H T10 AB:003 DB:B4          MREQ RD                    | Memory read from 003 -> B4\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:9D          MREQ                       | \n#023H T19 AB:000 DB:9D          MREQ    WR                 | Memory write to  000 <- 9D\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"B5\">Opcode: DD CB d B5 => RES 6,(IX+d),L*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:B5          MREQ RD                    | Memory read from 003 -> B5\n#014H T10 AB:003 DB:B5          MREQ RD                    | Memory read from 003 -> B5\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:9D          MREQ                       | \n#023H T19 AB:000 DB:9D          MREQ    WR                 | Memory write to  000 <- 9D\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"B6\">Opcode: DD CB d B6 => RES 6,(IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:B6          MREQ RD                    | Memory read from 003 -> B6\n#014H T10 AB:003 DB:B6          MREQ RD                    | Memory read from 003 -> B6\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:9D          MREQ                       | \n#023H T19 AB:000 DB:9D          MREQ    WR                 | Memory write to  000 <- 9D\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"B7\">Opcode: DD CB d B7 => RES 6,(IX+d),A*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:B7          MREQ RD                    | Memory read from 003 -> B7\n#014H T10 AB:003 DB:B7          MREQ RD                    | Memory read from 003 -> B7\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:9D          MREQ                       | \n#023H T19 AB:000 DB:9D          MREQ    WR                 | Memory write to  000 <- 9D\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"B8\">Opcode: DD CB d B8 => RES 7,(IX+d),B*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:B8          MREQ RD                    | Memory read from 003 -> B8\n#014H T10 AB:003 DB:B8          MREQ RD                    | Memory read from 003 -> B8\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:5D          MREQ                       | \n#023H T19 AB:000 DB:5D          MREQ    WR                 | Memory write to  000 <- 5D\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"B9\">Opcode: DD CB d B9 => RES 7,(IX+d),C*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:B9          MREQ RD                    | Memory read from 003 -> B9\n#014H T10 AB:003 DB:B9          MREQ RD                    | Memory read from 003 -> B9\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:5D          MREQ                       | \n#023H T19 AB:000 DB:5D          MREQ    WR                 | Memory write to  000 <- 5D\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"BA\">Opcode: DD CB d BA => RES 7,(IX+d),D*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:BA          MREQ RD                    | Memory read from 003 -> BA\n#014H T10 AB:003 DB:BA          MREQ RD                    | Memory read from 003 -> BA\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:5D          MREQ                       | \n#023H T19 AB:000 DB:5D          MREQ    WR                 | Memory write to  000 <- 5D\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"BB\">Opcode: DD CB d BB => RES 7,(IX+d),E*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:BB          MREQ RD                    | Memory read from 003 -> BB\n#014H T10 AB:003 DB:BB          MREQ RD                    | Memory read from 003 -> BB\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:5D          MREQ                       | \n#023H T19 AB:000 DB:5D          MREQ    WR                 | Memory write to  000 <- 5D\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"BC\">Opcode: DD CB d BC => RES 7,(IX+d),H*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:BC          MREQ RD                    | Memory read from 003 -> BC\n#014H T10 AB:003 DB:BC          MREQ RD                    | Memory read from 003 -> BC\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:5D          MREQ                       | \n#023H T19 AB:000 DB:5D          MREQ    WR                 | Memory write to  000 <- 5D\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"BD\">Opcode: DD CB d BD => RES 7,(IX+d),L*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:BD          MREQ RD                    | Memory read from 003 -> BD\n#014H T10 AB:003 DB:BD          MREQ RD                    | Memory read from 003 -> BD\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:5D          MREQ                       | \n#023H T19 AB:000 DB:5D          MREQ    WR                 | Memory write to  000 <- 5D\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"BE\">Opcode: DD CB d BE => RES 7,(IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:BE          MREQ RD                    | Memory read from 003 -> BE\n#014H T10 AB:003 DB:BE          MREQ RD                    | Memory read from 003 -> BE\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:5D          MREQ                       | \n#023H T19 AB:000 DB:5D          MREQ    WR                 | Memory write to  000 <- 5D\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"BF\">Opcode: DD CB d BF => RES 7,(IX+d),A*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:BF          MREQ RD                    | Memory read from 003 -> BF\n#014H T10 AB:003 DB:BF          MREQ RD                    | Memory read from 003 -> BF\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:5D          MREQ                       | \n#023H T19 AB:000 DB:5D          MREQ    WR                 | Memory write to  000 <- 5D\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"C0\">Opcode: DD CB d C0 => SET 0,(IX+d),B*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:C0          MREQ RD                    | Memory read from 003 -> C0\n#014H T10 AB:003 DB:C0          MREQ RD                    | Memory read from 003 -> C0\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"C1\">Opcode: DD CB d C1 => SET 0,(IX+d),C*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:C1          MREQ RD                    | Memory read from 003 -> C1\n#014H T10 AB:003 DB:C1          MREQ RD                    | Memory read from 003 -> C1\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"C2\">Opcode: DD CB d C2 => SET 0,(IX+d),D*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:C2          MREQ RD                    | Memory read from 003 -> C2\n#014H T10 AB:003 DB:C2          MREQ RD                    | Memory read from 003 -> C2\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"C3\">Opcode: DD CB d C3 => SET 0,(IX+d),E*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:C3          MREQ RD                    | Memory read from 003 -> C3\n#014H T10 AB:003 DB:C3          MREQ RD                    | Memory read from 003 -> C3\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"C4\">Opcode: DD CB d C4 => SET 0,(IX+d),H*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:C4          MREQ RD                    | Memory read from 003 -> C4\n#014H T10 AB:003 DB:C4          MREQ RD                    | Memory read from 003 -> C4\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"C5\">Opcode: DD CB d C5 => SET 0,(IX+d),L*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:C5          MREQ RD                    | Memory read from 003 -> C5\n#014H T10 AB:003 DB:C5          MREQ RD                    | Memory read from 003 -> C5\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"C6\">Opcode: DD CB d C6 => SET 0,(IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:C6          MREQ RD                    | Memory read from 003 -> C6\n#014H T10 AB:003 DB:C6          MREQ RD                    | Memory read from 003 -> C6\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"C7\">Opcode: DD CB d C7 => SET 0,(IX+d),A*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:C7          MREQ RD                    | Memory read from 003 -> C7\n#014H T10 AB:003 DB:C7          MREQ RD                    | Memory read from 003 -> C7\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"C8\">Opcode: DD CB d C8 => SET 1,(IX+d),B*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:C8          MREQ RD                    | Memory read from 003 -> C8\n#014H T10 AB:003 DB:C8          MREQ RD                    | Memory read from 003 -> C8\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DF          MREQ                       | \n#023H T19 AB:000 DB:DF          MREQ    WR                 | Memory write to  000 <- DF\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"C9\">Opcode: DD CB d C9 => SET 1,(IX+d),C*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:C9          MREQ RD                    | Memory read from 003 -> C9\n#014H T10 AB:003 DB:C9          MREQ RD                    | Memory read from 003 -> C9\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DF          MREQ                       | \n#023H T19 AB:000 DB:DF          MREQ    WR                 | Memory write to  000 <- DF\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"CA\">Opcode: DD CB d CA => SET 1,(IX+d),D*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:CA          MREQ RD                    | Memory read from 003 -> CA\n#014H T10 AB:003 DB:CA          MREQ RD                    | Memory read from 003 -> CA\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DF          MREQ                       | \n#023H T19 AB:000 DB:DF          MREQ    WR                 | Memory write to  000 <- DF\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"CB\">Opcode: DD CB d CB => SET 1,(IX+d),E*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:CB          MREQ RD                    | Memory read from 003 -> CB\n#014H T10 AB:003 DB:CB          MREQ RD                    | Memory read from 003 -> CB\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DF          MREQ                       | \n#023H T19 AB:000 DB:DF          MREQ    WR                 | Memory write to  000 <- DF\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"CC\">Opcode: DD CB d CC => SET 1,(IX+d),H*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:CC          MREQ RD                    | Memory read from 003 -> CC\n#014H T10 AB:003 DB:CC          MREQ RD                    | Memory read from 003 -> CC\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DF          MREQ                       | \n#023H T19 AB:000 DB:DF          MREQ    WR                 | Memory write to  000 <- DF\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"CD\">Opcode: DD CB d CD => SET 1,(IX+d),L*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:CD          MREQ RD                    | Memory read from 003 -> CD\n#014H T10 AB:003 DB:CD          MREQ RD                    | Memory read from 003 -> CD\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DF          MREQ                       | \n#023H T19 AB:000 DB:DF          MREQ    WR                 | Memory write to  000 <- DF\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"CE\">Opcode: DD CB d CE => SET 1,(IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:CE          MREQ RD                    | Memory read from 003 -> CE\n#014H T10 AB:003 DB:CE          MREQ RD                    | Memory read from 003 -> CE\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DF          MREQ                       | \n#023H T19 AB:000 DB:DF          MREQ    WR                 | Memory write to  000 <- DF\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"CF\">Opcode: DD CB d CF => SET 1,(IX+d),A*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:CF          MREQ RD                    | Memory read from 003 -> CF\n#014H T10 AB:003 DB:CF          MREQ RD                    | Memory read from 003 -> CF\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DF          MREQ                       | \n#023H T19 AB:000 DB:DF          MREQ    WR                 | Memory write to  000 <- DF\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"D0\">Opcode: DD CB d D0 => SET 2,(IX+d),B*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:D0          MREQ RD                    | Memory read from 003 -> D0\n#014H T10 AB:003 DB:D0          MREQ RD                    | Memory read from 003 -> D0\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"D1\">Opcode: DD CB d D1 => SET 2,(IX+d),C*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:D1          MREQ RD                    | Memory read from 003 -> D1\n#014H T10 AB:003 DB:D1          MREQ RD                    | Memory read from 003 -> D1\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"D2\">Opcode: DD CB d D2 => SET 2,(IX+d),D*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:D2          MREQ RD                    | Memory read from 003 -> D2\n#014H T10 AB:003 DB:D2          MREQ RD                    | Memory read from 003 -> D2\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"D3\">Opcode: DD CB d D3 => SET 2,(IX+d),E*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:D3          MREQ RD                    | Memory read from 003 -> D3\n#014H T10 AB:003 DB:D3          MREQ RD                    | Memory read from 003 -> D3\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"D4\">Opcode: DD CB d D4 => SET 2,(IX+d),H*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:D4          MREQ RD                    | Memory read from 003 -> D4\n#014H T10 AB:003 DB:D4          MREQ RD                    | Memory read from 003 -> D4\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"D5\">Opcode: DD CB d D5 => SET 2,(IX+d),L*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:D5          MREQ RD                    | Memory read from 003 -> D5\n#014H T10 AB:003 DB:D5          MREQ RD                    | Memory read from 003 -> D5\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"D6\">Opcode: DD CB d D6 => SET 2,(IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:D6          MREQ RD                    | Memory read from 003 -> D6\n#014H T10 AB:003 DB:D6          MREQ RD                    | Memory read from 003 -> D6\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"D7\">Opcode: DD CB d D7 => SET 2,(IX+d),A*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:D7          MREQ RD                    | Memory read from 003 -> D7\n#014H T10 AB:003 DB:D7          MREQ RD                    | Memory read from 003 -> D7\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"D8\">Opcode: DD CB d D8 => SET 3,(IX+d),B*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:D8          MREQ RD                    | Memory read from 003 -> D8\n#014H T10 AB:003 DB:D8          MREQ RD                    | Memory read from 003 -> D8\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"D9\">Opcode: DD CB d D9 => SET 3,(IX+d),C*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:D9          MREQ RD                    | Memory read from 003 -> D9\n#014H T10 AB:003 DB:D9          MREQ RD                    | Memory read from 003 -> D9\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"DA\">Opcode: DD CB d DA => SET 3,(IX+d),D*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:DA          MREQ RD                    | Memory read from 003 -> DA\n#014H T10 AB:003 DB:DA          MREQ RD                    | Memory read from 003 -> DA\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"DB\">Opcode: DD CB d DB => SET 3,(IX+d),E*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:DB          MREQ RD                    | Memory read from 003 -> DB\n#014H T10 AB:003 DB:DB          MREQ RD                    | Memory read from 003 -> DB\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"DC\">Opcode: DD CB d DC => SET 3,(IX+d),H*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:DC          MREQ RD                    | Memory read from 003 -> DC\n#014H T10 AB:003 DB:DC          MREQ RD                    | Memory read from 003 -> DC\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"DD\">Opcode: DD CB d DD => SET 3,(IX+d),L*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:DD          MREQ RD                    | Memory read from 003 -> DD\n#014H T10 AB:003 DB:DD          MREQ RD                    | Memory read from 003 -> DD\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"DE\">Opcode: DD CB d DE => SET 3,(IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:DE          MREQ RD                    | Memory read from 003 -> DE\n#014H T10 AB:003 DB:DE          MREQ RD                    | Memory read from 003 -> DE\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"DF\">Opcode: DD CB d DF => SET 3,(IX+d),A*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:DF          MREQ RD                    | Memory read from 003 -> DF\n#014H T10 AB:003 DB:DF          MREQ RD                    | Memory read from 003 -> DF\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"E0\">Opcode: DD CB d E0 => SET 4,(IX+d),B*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:E0          MREQ RD                    | Memory read from 003 -> E0\n#014H T10 AB:003 DB:E0          MREQ RD                    | Memory read from 003 -> E0\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"E1\">Opcode: DD CB d E1 => SET 4,(IX+d),C*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:E1          MREQ RD                    | Memory read from 003 -> E1\n#014H T10 AB:003 DB:E1          MREQ RD                    | Memory read from 003 -> E1\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"E2\">Opcode: DD CB d E2 => SET 4,(IX+d),D*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:E2          MREQ RD                    | Memory read from 003 -> E2\n#014H T10 AB:003 DB:E2          MREQ RD                    | Memory read from 003 -> E2\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"E3\">Opcode: DD CB d E3 => SET 4,(IX+d),E*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:E3          MREQ RD                    | Memory read from 003 -> E3\n#014H T10 AB:003 DB:E3          MREQ RD                    | Memory read from 003 -> E3\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"E4\">Opcode: DD CB d E4 => SET 4,(IX+d),H*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:E4          MREQ RD                    | Memory read from 003 -> E4\n#014H T10 AB:003 DB:E4          MREQ RD                    | Memory read from 003 -> E4\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"E5\">Opcode: DD CB d E5 => SET 4,(IX+d),L*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:E5          MREQ RD                    | Memory read from 003 -> E5\n#014H T10 AB:003 DB:E5          MREQ RD                    | Memory read from 003 -> E5\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"E6\">Opcode: DD CB d E6 => SET 4,(IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:E6          MREQ RD                    | Memory read from 003 -> E6\n#014H T10 AB:003 DB:E6          MREQ RD                    | Memory read from 003 -> E6\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"E7\">Opcode: DD CB d E7 => SET 4,(IX+d),A*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:E7          MREQ RD                    | Memory read from 003 -> E7\n#014H T10 AB:003 DB:E7          MREQ RD                    | Memory read from 003 -> E7\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"E8\">Opcode: DD CB d E8 => SET 5,(IX+d),B*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:E8          MREQ RD                    | Memory read from 003 -> E8\n#014H T10 AB:003 DB:E8          MREQ RD                    | Memory read from 003 -> E8\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:FD          MREQ                       | \n#023H T19 AB:000 DB:FD          MREQ    WR                 | Memory write to  000 <- FD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"E9\">Opcode: DD CB d E9 => SET 5,(IX+d),C*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:E9          MREQ RD                    | Memory read from 003 -> E9\n#014H T10 AB:003 DB:E9          MREQ RD                    | Memory read from 003 -> E9\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:FD          MREQ                       | \n#023H T19 AB:000 DB:FD          MREQ    WR                 | Memory write to  000 <- FD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"EA\">Opcode: DD CB d EA => SET 5,(IX+d),D*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:EA          MREQ RD                    | Memory read from 003 -> EA\n#014H T10 AB:003 DB:EA          MREQ RD                    | Memory read from 003 -> EA\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:FD          MREQ                       | \n#023H T19 AB:000 DB:FD          MREQ    WR                 | Memory write to  000 <- FD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"EB\">Opcode: DD CB d EB => SET 5,(IX+d),E*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:EB          MREQ RD                    | Memory read from 003 -> EB\n#014H T10 AB:003 DB:EB          MREQ RD                    | Memory read from 003 -> EB\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:FD          MREQ                       | \n#023H T19 AB:000 DB:FD          MREQ    WR                 | Memory write to  000 <- FD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"EC\">Opcode: DD CB d EC => SET 5,(IX+d),H*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:EC          MREQ RD                    | Memory read from 003 -> EC\n#014H T10 AB:003 DB:EC          MREQ RD                    | Memory read from 003 -> EC\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:FD          MREQ                       | \n#023H T19 AB:000 DB:FD          MREQ    WR                 | Memory write to  000 <- FD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"ED\">Opcode: DD CB d ED => SET 5,(IX+d),L*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:ED          MREQ RD                    | Memory read from 003 -> ED\n#014H T10 AB:003 DB:ED          MREQ RD                    | Memory read from 003 -> ED\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:FD          MREQ                       | \n#023H T19 AB:000 DB:FD          MREQ    WR                 | Memory write to  000 <- FD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"EE\">Opcode: DD CB d EE => SET 5,(IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:EE          MREQ RD                    | Memory read from 003 -> EE\n#014H T10 AB:003 DB:EE          MREQ RD                    | Memory read from 003 -> EE\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:FD          MREQ                       | \n#023H T19 AB:000 DB:FD          MREQ    WR                 | Memory write to  000 <- FD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"EF\">Opcode: DD CB d EF => SET 5,(IX+d),A*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:EF          MREQ RD                    | Memory read from 003 -> EF\n#014H T10 AB:003 DB:EF          MREQ RD                    | Memory read from 003 -> EF\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:FD          MREQ                       | \n#023H T19 AB:000 DB:FD          MREQ    WR                 | Memory write to  000 <- FD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"F0\">Opcode: DD CB d F0 => SET 6,(IX+d),B*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:F0          MREQ RD                    | Memory read from 003 -> F0\n#014H T10 AB:003 DB:F0          MREQ RD                    | Memory read from 003 -> F0\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"F1\">Opcode: DD CB d F1 => SET 6,(IX+d),C*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:F1          MREQ RD                    | Memory read from 003 -> F1\n#014H T10 AB:003 DB:F1          MREQ RD                    | Memory read from 003 -> F1\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"F2\">Opcode: DD CB d F2 => SET 6,(IX+d),D*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:F2          MREQ RD                    | Memory read from 003 -> F2\n#014H T10 AB:003 DB:F2          MREQ RD                    | Memory read from 003 -> F2\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"F3\">Opcode: DD CB d F3 => SET 6,(IX+d),E*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:F3          MREQ RD                    | Memory read from 003 -> F3\n#014H T10 AB:003 DB:F3          MREQ RD                    | Memory read from 003 -> F3\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"F4\">Opcode: DD CB d F4 => SET 6,(IX+d),H*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:F4          MREQ RD                    | Memory read from 003 -> F4\n#014H T10 AB:003 DB:F4          MREQ RD                    | Memory read from 003 -> F4\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"F5\">Opcode: DD CB d F5 => SET 6,(IX+d),L*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:F5          MREQ RD                    | Memory read from 003 -> F5\n#014H T10 AB:003 DB:F5          MREQ RD                    | Memory read from 003 -> F5\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"F6\">Opcode: DD CB d F6 => SET 6,(IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:F6          MREQ RD                    | Memory read from 003 -> F6\n#014H T10 AB:003 DB:F6          MREQ RD                    | Memory read from 003 -> F6\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"F7\">Opcode: DD CB d F7 => SET 6,(IX+d),A*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:F7          MREQ RD                    | Memory read from 003 -> F7\n#014H T10 AB:003 DB:F7          MREQ RD                    | Memory read from 003 -> F7\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"F8\">Opcode: DD CB d F8 => SET 7,(IX+d),B*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:F8          MREQ RD                    | Memory read from 003 -> F8\n#014H T10 AB:003 DB:F8          MREQ RD                    | Memory read from 003 -> F8\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"F9\">Opcode: DD CB d F9 => SET 7,(IX+d),C*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:F9          MREQ RD                    | Memory read from 003 -> F9\n#014H T10 AB:003 DB:F9          MREQ RD                    | Memory read from 003 -> F9\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"FA\">Opcode: DD CB d FA => SET 7,(IX+d),D*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:FA          MREQ RD                    | Memory read from 003 -> FA\n#014H T10 AB:003 DB:FA          MREQ RD                    | Memory read from 003 -> FA\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"FB\">Opcode: DD CB d FB => SET 7,(IX+d),E*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:FB          MREQ RD                    | Memory read from 003 -> FB\n#014H T10 AB:003 DB:FB          MREQ RD                    | Memory read from 003 -> FB\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"FC\">Opcode: DD CB d FC => SET 7,(IX+d),H*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:FC          MREQ RD                    | Memory read from 003 -> FC\n#014H T10 AB:003 DB:FC          MREQ RD                    | Memory read from 003 -> FC\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"FD\">Opcode: DD CB d FD => SET 7,(IX+d),L*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:FD          MREQ RD                    | Memory read from 003 -> FD\n#014H T10 AB:003 DB:FD          MREQ RD                    | Memory read from 003 -> FD\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"FE\">Opcode: DD CB d FE => SET 7,(IX+d)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:FE          MREQ RD                    | Memory read from 003 -> FE\n#014H T10 AB:003 DB:FE          MREQ RD                    | Memory read from 003 -> FE\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"FF\">Opcode: DD CB d FF => SET 7,(IX+d),A*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:CB  M1      MREQ RD                    | Opcode read from 001 -> CB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:FF          MREQ RD                    | Memory read from 003 -> FF\n#014H T10 AB:003 DB:FF          MREQ RD                    | Memory read from 003 -> FF\n#015H T11 AB:003 DB:--                                     | \n#016H T12 AB:003 DB:--                                     | \n#017H T13 AB:000 DB:--                                     | \n#018H T14 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#019H T15 AB:000 DB:DD          MREQ RD                    | Memory read from 000 -> DD\n#020H T16 AB:000 DB:--                                     | \n#021H T17 AB:000 DB:--                                     | \n#022H T18 AB:000 DB:DD          MREQ                       | \n#023H T19 AB:000 DB:DD          MREQ    WR                 | Memory write to  000 <- DD\n-----------------------------------------------------------+\n</PRE>\n</BODY></HTML>\n"
  },
  {
    "path": "tools/dongle/ed.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD HTML 4.01//EN\">\n<HTML><HEAD><TITLE>Z80 Instructions Timing</TITLE></HEAD><BODY>\n<H1>Opcodes with ED prefix</H1>\nED 40 .. <A href=\"#40\">IN B,(C)</A><BR>\nED 41 .. <A href=\"#41\">OUT (C),B</A><BR>\nED 42 .. <A href=\"#42\">SBC HL,BC</A><BR>\nED 43 .. <A href=\"#43\">LD (nn),BC</A><BR>\nED 44 .. <A href=\"#44\">NEG</A><BR>\nED 45 .. <A href=\"#45\">RETN</A><BR>\nED 46 .. <A href=\"#46\">IM 0</A><BR>\nED 47 .. <A href=\"#47\">LD I,A</A><BR>\nED 48 .. <A href=\"#48\">IN C,(C)</A><BR>\nED 49 .. <A href=\"#49\">OUT (C),C</A><BR>\nED 4A .. <A href=\"#4A\">ADC HL,BC</A><BR>\nED 4B .. <A href=\"#4B\">LD BC,(nn)</A><BR>\nED 4C .. <A href=\"#4C\">NEG*</A><BR>\nED 4D .. <A href=\"#4D\">RETI</A><BR>\nED 4E .. <A href=\"#4E\">IM 0*</A><BR>\nED 4F .. <A href=\"#4F\">LD R,A</A><BR>\nED 50 .. <A href=\"#50\">IN D,(C)</A><BR>\nED 51 .. <A href=\"#51\">OUT (C),D</A><BR>\nED 52 .. <A href=\"#52\">SBC HL,DE</A><BR>\nED 53 .. <A href=\"#53\">LD (nn),DE</A><BR>\nED 54 .. <A href=\"#54\">NEG*</A><BR>\nED 55 .. <A href=\"#55\">RETN*</A><BR>\nED 56 .. <A href=\"#56\">IM 1</A><BR>\nED 57 .. <A href=\"#57\">LD A,I</A><BR>\nED 58 .. <A href=\"#58\">IN E,(C)</A><BR>\nED 59 .. <A href=\"#59\">OUT (C),E</A><BR>\nED 5A .. <A href=\"#5A\">ADC HL,DE</A><BR>\nED 5B .. <A href=\"#5B\">LD DE,(nn)</A><BR>\nED 5C .. <A href=\"#5C\">NEG*</A><BR>\nED 5D .. <A href=\"#5D\">RETN*</A><BR>\nED 5E .. <A href=\"#5E\">IM 2</A><BR>\nED 5F .. <A href=\"#5F\">LD A,R</A><BR>\nED 60 .. <A href=\"#60\">IN H,(C)</A><BR>\nED 61 .. <A href=\"#61\">OUT (C),H</A><BR>\nED 62 .. <A href=\"#62\">SBC HL,HL</A><BR>\nED 63 .. <A href=\"#63\">LD (nn),HL</A><BR>\nED 64 .. <A href=\"#64\">NEG*</A><BR>\nED 65 .. <A href=\"#65\">RETN*</A><BR>\nED 66 .. <A href=\"#66\">IM 0*</A><BR>\nED 67 .. <A href=\"#67\">RRD</A><BR>\nED 68 .. <A href=\"#68\">IN L,(C)</A><BR>\nED 69 .. <A href=\"#69\">OUT (C),L</A><BR>\nED 6A .. <A href=\"#6A\">ADC HL,HL</A><BR>\nED 6B .. <A href=\"#6B\">LD HL,(nn)</A><BR>\nED 6C .. <A href=\"#6C\">NEG*</A><BR>\nED 6D .. <A href=\"#6D\">RETN*</A><BR>\nED 6E .. <A href=\"#6E\">IM 0*</A><BR>\nED 6F .. <A href=\"#6F\">RLD</A><BR>\nED 70 .. <A href=\"#70\">IN F,(C)*</A><BR>\nED 71 .. <A href=\"#71\">OUT (C),0*</A><BR>\nED 72 .. <A href=\"#72\">SBC HL,SP</A><BR>\nED 73 .. <A href=\"#73\">LD (nn),SP</A><BR>\nED 74 .. <A href=\"#74\">NEG*</A><BR>\nED 75 .. <A href=\"#75\">RETN*</A><BR>\nED 76 .. <A href=\"#76\">IM 1*</A><BR>\nED 78 .. <A href=\"#78\">IN A,(C)</A><BR>\nED 79 .. <A href=\"#79\">OUT (C),A</A><BR>\nED 7A .. <A href=\"#7A\">ADC HL,SP</A><BR>\nED 7B .. <A href=\"#7B\">LD SP,(nn)</A><BR>\nED 7C .. <A href=\"#7C\">NEG*</A><BR>\nED 7D .. <A href=\"#7D\">RETN*</A><BR>\nED 7E .. <A href=\"#7E\">IM 2*</A><BR>\nED A0 .. <A href=\"#A0\">LDI</A><BR>\nED A1 .. <A href=\"#A1\">CPI</A><BR>\nED A2 .. <A href=\"#A2\">INI</A><BR>\nED A3 .. <A href=\"#A3\">OUTI</A><BR>\nED A8 .. <A href=\"#A8\">LDD</A><BR>\nED A9 .. <A href=\"#A9\">CPD</A><BR>\nED AA .. <A href=\"#AA\">IND</A><BR>\nED AB .. <A href=\"#AB\">OUTD</A><BR>\nED B0 .. <A href=\"#B0\">LDIR</A><BR>\nED B1 .. <A href=\"#B1\">CPIR</A><BR>\nED B2 .. <A href=\"#B2\">INIR</A><BR>\nED B3 .. <A href=\"#B3\">OTIR</A><BR>\nED B8 .. <A href=\"#B8\">LDDR</A><BR>\nED B9 .. <A href=\"#B9\">CPDR</A><BR>\nED BA .. <A href=\"#BA\">INDR</A><BR>\nED BB .. <A href=\"#BB\">OTDR</A><BR>\n<H1>Instructions Timing</H1>\n<H3 id=\"40\">Opcode: ED 40     => IN B,(C)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:40  M1      MREQ RD                    | Opcode read from 001 -> 40\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:0FF DB:--                                     | \n#010H T6  AB:0FF DB:--               RD    IORQ            | I/O read from 0FF\n#011H T7  AB:0FF DB:--               RD    IORQ            | I/O read from 0FF\n#012H T8  AB:0FF DB:--               RD    IORQ            | I/O read from 0FF\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"41\">Opcode: ED 41     => OUT (C),B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:41  M1      MREQ RD                    | Opcode read from 001 -> 41\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:0FF DB:--                                     | \n#010H T6  AB:0FF DB:C3                  WR IORQ            | I/O write to 0FF <- C3\n#011H T7  AB:0FF DB:C3                  WR IORQ            | I/O write to 0FF <- C3\n#012H T8  AB:0FF DB:C3                  WR IORQ            | I/O write to 0FF <- C3\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"42\">Opcode: ED 42     => SBC HL,BC</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:42  M1      MREQ RD                    | Opcode read from 001 -> 42\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:001 DB:--                                     | \n#010H T6  AB:001 DB:--                                     | \n#011H T7  AB:001 DB:--                                     | \n#012H T8  AB:001 DB:--                                     | \n#013H T9  AB:001 DB:--                                     | \n#014H T10 AB:001 DB:--                                     | \n#015H T11 AB:001 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"43\">Opcode: ED 43 n n => LD (nn),BC</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:43  M1      MREQ RD                    | Opcode read from 001 -> 43\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#014H T10 AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#015H T11 AB:001 DB:--                                     | \n#016H T12 AB:001 DB:FF          MREQ                       | \n#017H T13 AB:001 DB:FF          MREQ    WR                 | Memory write to  001 <- FF\n#018H T14 AB:002 DB:--                                     | \n#019H T15 AB:002 DB:C3          MREQ                       | \n#020H T16 AB:002 DB:C3          MREQ    WR                 | Memory write to  002 <- C3\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"44\">Opcode: ED 44     => NEG</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:44  M1      MREQ RD                    | Opcode read from 001 -> 44\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"45\">Opcode: ED 45     => RETN</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:45  M1      MREQ RD                    | Opcode read from 001 -> 45\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:001 DB:--                                     | \n#010H T6  AB:001 DB:45          MREQ RD                    | Memory read from 001 -> 45\n#011H T7  AB:001 DB:45          MREQ RD                    | Memory read from 001 -> 45\n#012H T8  AB:002 DB:--                                     | \n#013H T9  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#014H T10 AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"46\">Opcode: ED 46     => IM 0</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:46  M1      MREQ RD                    | Opcode read from 001 -> 46\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"47\">Opcode: ED 47     => LD I,A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:47  M1      MREQ RD                    | Opcode read from 001 -> 47\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:001 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"48\">Opcode: ED 48     => IN C,(C)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:48  M1      MREQ RD                    | Opcode read from 001 -> 48\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:0FF DB:--                                     | \n#010H T6  AB:0FF DB:--               RD    IORQ            | I/O read from 0FF\n#011H T7  AB:0FF DB:--               RD    IORQ            | I/O read from 0FF\n#012H T8  AB:0FF DB:--               RD    IORQ            | I/O read from 0FF\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"49\">Opcode: ED 49     => OUT (C),C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:49  M1      MREQ RD                    | Opcode read from 001 -> 49\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:0CB DB:--                                     | \n#010H T6  AB:0CB DB:CB                  WR IORQ            | I/O write to 0CB <- CB\n#011H T7  AB:0CB DB:CB                  WR IORQ            | I/O write to 0CB <- CB\n#012H T8  AB:0CB DB:CB                  WR IORQ            | I/O write to 0CB <- CB\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"4A\">Opcode: ED 4A     => ADC HL,BC</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:4A  M1      MREQ RD                    | Opcode read from 001 -> 4A\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:001 DB:--                                     | \n#010H T6  AB:001 DB:--                                     | \n#011H T7  AB:001 DB:--                                     | \n#012H T8  AB:001 DB:--                                     | \n#013H T9  AB:001 DB:--                                     | \n#014H T10 AB:001 DB:--                                     | \n#015H T11 AB:001 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"4B\">Opcode: ED 4B n n => LD BC,(nn)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:4B  M1      MREQ RD                    | Opcode read from 001 -> 4B\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#014H T10 AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#015H T11 AB:001 DB:--                                     | \n#016H T12 AB:001 DB:4B          MREQ RD                    | Memory read from 001 -> 4B\n#017H T13 AB:001 DB:4B          MREQ RD                    | Memory read from 001 -> 4B\n#018H T14 AB:002 DB:--                                     | \n#019H T15 AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#020H T16 AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"4C\">Opcode: ED 4C     => NEG*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:4C  M1      MREQ RD                    | Opcode read from 001 -> 4C\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"4D\">Opcode: ED 4D     => RETI</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:4D  M1      MREQ RD                    | Opcode read from 001 -> 4D\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:003 DB:--                                     | \n#010H T6  AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#011H T7  AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#012H T8  AB:004 DB:--                                     | \n#013H T9  AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n#014H T10 AB:004 DB:03          MREQ RD                    | Memory read from 004 -> 03\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"4E\">Opcode: ED 4E     => IM 0*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:4E  M1      MREQ RD                    | Opcode read from 001 -> 4E\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"4F\">Opcode: ED 4F     => LD R,A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:4F  M1      MREQ RD                    | Opcode read from 001 -> 4F\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:001 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"50\">Opcode: ED 50     => IN D,(C)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:50  M1      MREQ RD                    | Opcode read from 001 -> 50\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:04B DB:--                                     | \n#010H T6  AB:04B DB:--               RD    IORQ            | I/O read from 04B\n#011H T7  AB:04B DB:--               RD    IORQ            | I/O read from 04B\n#012H T8  AB:04B DB:--               RD    IORQ            | I/O read from 04B\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"51\">Opcode: ED 51     => OUT (C),D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:51  M1      MREQ RD                    | Opcode read from 001 -> 51\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:04B DB:--                                     | \n#010H T6  AB:04B DB:D3                  WR IORQ            | I/O write to 04B <- D3\n#011H T7  AB:04B DB:D3                  WR IORQ            | I/O write to 04B <- D3\n#012H T8  AB:04B DB:D3                  WR IORQ            | I/O write to 04B <- D3\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"52\">Opcode: ED 52     => SBC HL,DE</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:52  M1      MREQ RD                    | Opcode read from 001 -> 52\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:001 DB:--                                     | \n#010H T6  AB:001 DB:--                                     | \n#011H T7  AB:001 DB:--                                     | \n#012H T8  AB:001 DB:--                                     | \n#013H T9  AB:001 DB:--                                     | \n#014H T10 AB:001 DB:--                                     | \n#015H T11 AB:001 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"53\">Opcode: ED 53 n n => LD (nn),DE</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:53  M1      MREQ RD                    | Opcode read from 001 -> 53\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#014H T10 AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#015H T11 AB:001 DB:--                                     | \n#016H T12 AB:001 DB:FF          MREQ                       | \n#017H T13 AB:001 DB:FF          MREQ    WR                 | Memory write to  001 <- FF\n#018H T14 AB:002 DB:--                                     | \n#019H T15 AB:002 DB:D3          MREQ                       | \n#020H T16 AB:002 DB:D3          MREQ    WR                 | Memory write to  002 <- D3\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"54\">Opcode: ED 54     => NEG*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:54  M1      MREQ RD                    | Opcode read from 001 -> 54\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"55\">Opcode: ED 55     => RETN*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:55  M1      MREQ RD                    | Opcode read from 001 -> 55\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:005 DB:--                                     | \n#010H T6  AB:005 DB:04          MREQ RD                    | Memory read from 005 -> 04\n#011H T7  AB:005 DB:04          MREQ RD                    | Memory read from 005 -> 04\n#012H T8  AB:006 DB:--                                     | \n#013H T9  AB:006 DB:05          MREQ RD                    | Memory read from 006 -> 05\n#014H T10 AB:006 DB:05          MREQ RD                    | Memory read from 006 -> 05\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"56\">Opcode: ED 56     => IM 1</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:56  M1      MREQ RD                    | Opcode read from 001 -> 56\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"57\">Opcode: ED 57     => LD A,I</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:57  M1      MREQ RD                    | Opcode read from 001 -> 57\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:001 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"58\">Opcode: ED 58     => IN E,(C)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:58  M1      MREQ RD                    | Opcode read from 001 -> 58\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:04B DB:--                                     | \n#010H T6  AB:04B DB:--               RD    IORQ            | I/O read from 04B\n#011H T7  AB:04B DB:--               RD    IORQ            | I/O read from 04B\n#012H T8  AB:04B DB:--               RD    IORQ            | I/O read from 04B\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"59\">Opcode: ED 59     => OUT (C),E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:59  M1      MREQ RD                    | Opcode read from 001 -> 59\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:04B DB:--                                     | \n#010H T6  AB:04B DB:DB                  WR IORQ            | I/O write to 04B <- DB\n#011H T7  AB:04B DB:DB                  WR IORQ            | I/O write to 04B <- DB\n#012H T8  AB:04B DB:DB                  WR IORQ            | I/O write to 04B <- DB\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"5A\">Opcode: ED 5A     => ADC HL,DE</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:5A  M1      MREQ RD                    | Opcode read from 001 -> 5A\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:001 DB:--                                     | \n#010H T6  AB:001 DB:--                                     | \n#011H T7  AB:001 DB:--                                     | \n#012H T8  AB:001 DB:--                                     | \n#013H T9  AB:001 DB:--                                     | \n#014H T10 AB:001 DB:--                                     | \n#015H T11 AB:001 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"5B\">Opcode: ED 5B n n => LD DE,(nn)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:5B  M1      MREQ RD                    | Opcode read from 001 -> 5B\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#014H T10 AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#015H T11 AB:001 DB:--                                     | \n#016H T12 AB:001 DB:5B          MREQ RD                    | Memory read from 001 -> 5B\n#017H T13 AB:001 DB:5B          MREQ RD                    | Memory read from 001 -> 5B\n#018H T14 AB:002 DB:--                                     | \n#019H T15 AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#020H T16 AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"5C\">Opcode: ED 5C     => NEG*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:5C  M1      MREQ RD                    | Opcode read from 001 -> 5C\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"5D\">Opcode: ED 5D     => RETN*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:5D  M1      MREQ RD                    | Opcode read from 001 -> 5D\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:007 DB:--                                     | \n#010H T6  AB:007 DB:06          MREQ RD                    | Memory read from 007 -> 06\n#011H T7  AB:007 DB:06          MREQ RD                    | Memory read from 007 -> 06\n#012H T8  AB:008 DB:--                                     | \n#013H T9  AB:008 DB:07          MREQ RD                    | Memory read from 008 -> 07\n#014H T10 AB:008 DB:07          MREQ RD                    | Memory read from 008 -> 07\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"5E\">Opcode: ED 5E     => IM 2</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:5E  M1      MREQ RD                    | Opcode read from 001 -> 5E\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"5F\">Opcode: ED 5F     => LD A,R</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:5F  M1      MREQ RD                    | Opcode read from 001 -> 5F\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:001 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"60\">Opcode: ED 60     => IN H,(C)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:60  M1      MREQ RD                    | Opcode read from 001 -> 60\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:04B DB:--                                     | \n#010H T6  AB:04B DB:--               RD    IORQ            | I/O read from 04B\n#011H T7  AB:04B DB:--               RD    IORQ            | I/O read from 04B\n#012H T8  AB:04B DB:--               RD    IORQ            | I/O read from 04B\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"61\">Opcode: ED 61     => OUT (C),H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:61  M1      MREQ RD                    | Opcode read from 001 -> 61\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:04B DB:--                                     | \n#010H T6  AB:04B DB:E3                  WR IORQ            | I/O write to 04B <- E3\n#011H T7  AB:04B DB:E3                  WR IORQ            | I/O write to 04B <- E3\n#012H T8  AB:04B DB:E3                  WR IORQ            | I/O write to 04B <- E3\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"62\">Opcode: ED 62     => SBC HL,HL</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:62  M1      MREQ RD                    | Opcode read from 001 -> 62\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:001 DB:--                                     | \n#010H T6  AB:001 DB:--                                     | \n#011H T7  AB:001 DB:--                                     | \n#012H T8  AB:001 DB:--                                     | \n#013H T9  AB:001 DB:--                                     | \n#014H T10 AB:001 DB:--                                     | \n#015H T11 AB:001 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"63\">Opcode: ED 63 n n => LD (nn),HL</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:63  M1      MREQ RD                    | Opcode read from 001 -> 63\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#014H T10 AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#015H T11 AB:001 DB:--                                     | \n#016H T12 AB:001 DB:00          MREQ                       | \n#017H T13 AB:001 DB:00          MREQ    WR                 | Memory write to  001 <- 00\n#018H T14 AB:002 DB:--                                     | \n#019H T15 AB:002 DB:00          MREQ                       | \n#020H T16 AB:002 DB:00          MREQ    WR                 | Memory write to  002 <- 00\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"64\">Opcode: ED 64     => NEG*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:64  M1      MREQ RD                    | Opcode read from 001 -> 64\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"65\">Opcode: ED 65     => RETN*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:65  M1      MREQ RD                    | Opcode read from 001 -> 65\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:009 DB:--                                     | \n#010H T6  AB:009 DB:08          MREQ RD                    | Memory read from 009 -> 08\n#011H T7  AB:009 DB:08          MREQ RD                    | Memory read from 009 -> 08\n#012H T8  AB:00A DB:--                                     | \n#013H T9  AB:00A DB:09          MREQ RD                    | Memory read from 00A -> 09\n#014H T10 AB:00A DB:09          MREQ RD                    | Memory read from 00A -> 09\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"66\">Opcode: ED 66     => IM 0*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:66  M1      MREQ RD                    | Opcode read from 001 -> 66\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"67\">Opcode: ED 67     => RRD</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:67  M1      MREQ RD                    | Opcode read from 001 -> 67\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:000 DB:--                                     | \n#010H T6  AB:000 DB:ED          MREQ RD                    | Memory read from 000 -> ED\n#011H T7  AB:000 DB:ED          MREQ RD                    | Memory read from 000 -> ED\n#012H T8  AB:000 DB:--                                     | \n#013H T9  AB:000 DB:--                                     | \n#014H T10 AB:000 DB:--                                     | \n#015H T11 AB:000 DB:--                                     | \n#016H T12 AB:000 DB:--                                     | \n#017H T13 AB:000 DB:EE          MREQ                       | \n#018H T14 AB:000 DB:EE          MREQ    WR                 | Memory write to  000 <- EE\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"68\">Opcode: ED 68     => IN L,(C)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:68  M1      MREQ RD                    | Opcode read from 001 -> 68\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:04B DB:--                                     | \n#010H T6  AB:04B DB:--               RD    IORQ            | I/O read from 04B\n#011H T7  AB:04B DB:--               RD    IORQ            | I/O read from 04B\n#012H T8  AB:04B DB:--               RD    IORQ            | I/O read from 04B\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"69\">Opcode: ED 69     => OUT (C),L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:69  M1      MREQ RD                    | Opcode read from 001 -> 69\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:04B DB:--                                     | \n#010H T6  AB:04B DB:EB                  WR IORQ            | I/O write to 04B <- EB\n#011H T7  AB:04B DB:EB                  WR IORQ            | I/O write to 04B <- EB\n#012H T8  AB:04B DB:EB                  WR IORQ            | I/O write to 04B <- EB\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"6A\">Opcode: ED 6A     => ADC HL,HL</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:6A  M1      MREQ RD                    | Opcode read from 001 -> 6A\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:001 DB:--                                     | \n#010H T6  AB:001 DB:--                                     | \n#011H T7  AB:001 DB:--                                     | \n#012H T8  AB:001 DB:--                                     | \n#013H T9  AB:001 DB:--                                     | \n#014H T10 AB:001 DB:--                                     | \n#015H T11 AB:001 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"6B\">Opcode: ED 6B n n => LD HL,(nn)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:6B  M1      MREQ RD                    | Opcode read from 001 -> 6B\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#014H T10 AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#015H T11 AB:001 DB:--                                     | \n#016H T12 AB:001 DB:6B          MREQ RD                    | Memory read from 001 -> 6B\n#017H T13 AB:001 DB:6B          MREQ RD                    | Memory read from 001 -> 6B\n#018H T14 AB:002 DB:--                                     | \n#019H T15 AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#020H T16 AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"6C\">Opcode: ED 6C     => NEG*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:6C  M1      MREQ RD                    | Opcode read from 001 -> 6C\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"6D\">Opcode: ED 6D     => RETN*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:6D  M1      MREQ RD                    | Opcode read from 001 -> 6D\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:00B DB:--                                     | \n#010H T6  AB:00B DB:0A          MREQ RD                    | Memory read from 00B -> 0A\n#011H T7  AB:00B DB:0A          MREQ RD                    | Memory read from 00B -> 0A\n#012H T8  AB:00C DB:--                                     | \n#013H T9  AB:00C DB:0B          MREQ RD                    | Memory read from 00C -> 0B\n#014H T10 AB:00C DB:0B          MREQ RD                    | Memory read from 00C -> 0B\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"6E\">Opcode: ED 6E     => IM 0*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:6E  M1      MREQ RD                    | Opcode read from 001 -> 6E\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"6F\">Opcode: ED 6F     => RLD</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:6F  M1      MREQ RD                    | Opcode read from 001 -> 6F\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:06B DB:--                                     | \n#010H T6  AB:06B DB:00          MREQ RD                    | Memory read from 06B -> 00\n#011H T7  AB:06B DB:00          MREQ RD                    | Memory read from 06B -> 00\n#012H T8  AB:06B DB:--                                     | \n#013H T9  AB:06B DB:--                                     | \n#014H T10 AB:06B DB:--                                     | \n#015H T11 AB:06B DB:--                                     | \n#016H T12 AB:06B DB:--                                     | \n#017H T13 AB:06B DB:03          MREQ                       | \n#018H T14 AB:06B DB:03          MREQ    WR                 | Memory write to  06B <- 03\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"70\">Opcode: ED 70     => IN F,(C)*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:70  M1      MREQ RD                    | Opcode read from 001 -> 70\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:04B DB:--                                     | \n#010H T6  AB:04B DB:--               RD    IORQ            | I/O read from 04B\n#011H T7  AB:04B DB:--               RD    IORQ            | I/O read from 04B\n#012H T8  AB:04B DB:--               RD    IORQ            | I/O read from 04B\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"71\">Opcode: ED 71     => OUT (C),0*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:71  M1      MREQ RD                    | Opcode read from 001 -> 71\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:04B DB:--                                     | \n#010H T6  AB:04B DB:00                  WR IORQ            | I/O write to 04B <- 00\n#011H T7  AB:04B DB:00                  WR IORQ            | I/O write to 04B <- 00\n#012H T8  AB:04B DB:00                  WR IORQ            | I/O write to 04B <- 00\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"72\">Opcode: ED 72     => SBC HL,SP</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:72  M1      MREQ RD                    | Opcode read from 001 -> 72\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:001 DB:--                                     | \n#010H T6  AB:001 DB:--                                     | \n#011H T7  AB:001 DB:--                                     | \n#012H T8  AB:001 DB:--                                     | \n#013H T9  AB:001 DB:--                                     | \n#014H T10 AB:001 DB:--                                     | \n#015H T11 AB:001 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"73\">Opcode: ED 73 n n => LD (nn),SP</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:73  M1      MREQ RD                    | Opcode read from 001 -> 73\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#014H T10 AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#015H T11 AB:001 DB:--                                     | \n#016H T12 AB:001 DB:0D          MREQ                       | \n#017H T13 AB:001 DB:0D          MREQ    WR                 | Memory write to  001 <- 0D\n#018H T14 AB:002 DB:--                                     | \n#019H T15 AB:002 DB:D1          MREQ                       | \n#020H T16 AB:002 DB:D1          MREQ    WR                 | Memory write to  002 <- D1\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"74\">Opcode: ED 74     => NEG*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:74  M1      MREQ RD                    | Opcode read from 001 -> 74\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"75\">Opcode: ED 75     => RETN*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:75  M1      MREQ RD                    | Opcode read from 001 -> 75\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:00D DB:--                                     | \n#010H T6  AB:00D DB:0C          MREQ RD                    | Memory read from 00D -> 0C\n#011H T7  AB:00D DB:0C          MREQ RD                    | Memory read from 00D -> 0C\n#012H T8  AB:00E DB:--                                     | \n#013H T9  AB:00E DB:0D          MREQ RD                    | Memory read from 00E -> 0D\n#014H T10 AB:00E DB:0D          MREQ RD                    | Memory read from 00E -> 0D\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"76\">Opcode: ED 76     => IM 1*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:76  M1      MREQ RD                    | Opcode read from 001 -> 76\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"78\">Opcode: ED 78     => IN A,(C)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:78  M1      MREQ RD                    | Opcode read from 001 -> 78\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:04B DB:--                                     | \n#010H T6  AB:04B DB:--               RD    IORQ            | I/O read from 04B\n#011H T7  AB:04B DB:--               RD    IORQ            | I/O read from 04B\n#012H T8  AB:04B DB:--               RD    IORQ            | I/O read from 04B\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"79\">Opcode: ED 79     => OUT (C),A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:79  M1      MREQ RD                    | Opcode read from 001 -> 79\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:04B DB:--                                     | \n#010H T6  AB:04B DB:FB                  WR IORQ            | I/O write to 04B <- FB\n#011H T7  AB:04B DB:FB                  WR IORQ            | I/O write to 04B <- FB\n#012H T8  AB:04B DB:FB                  WR IORQ            | I/O write to 04B <- FB\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"7A\">Opcode: ED 7A     => ADC HL,SP</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:7A  M1      MREQ RD                    | Opcode read from 001 -> 7A\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:001 DB:--                                     | \n#010H T6  AB:001 DB:--                                     | \n#011H T7  AB:001 DB:--                                     | \n#012H T8  AB:001 DB:--                                     | \n#013H T9  AB:001 DB:--                                     | \n#014H T10 AB:001 DB:--                                     | \n#015H T11 AB:001 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"7B\">Opcode: ED 7B n n => LD SP,(nn)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:7B  M1      MREQ RD                    | Opcode read from 001 -> 7B\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:002 DB:--                                     | \n#010H T6  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#011H T7  AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#012H T8  AB:003 DB:--                                     | \n#013H T9  AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#014H T10 AB:003 DB:02          MREQ RD                    | Memory read from 003 -> 02\n#015H T11 AB:001 DB:--                                     | \n#016H T12 AB:001 DB:7B          MREQ RD                    | Memory read from 001 -> 7B\n#017H T13 AB:001 DB:7B          MREQ RD                    | Memory read from 001 -> 7B\n#018H T14 AB:002 DB:--                                     | \n#019H T15 AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n#020H T16 AB:002 DB:01          MREQ RD                    | Memory read from 002 -> 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"7C\">Opcode: ED 7C     => NEG*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:7C  M1      MREQ RD                    | Opcode read from 001 -> 7C\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"7D\">Opcode: ED 7D     => RETN*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:7D  M1      MREQ RD                    | Opcode read from 001 -> 7D\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:07B DB:--                                     | \n#010H T6  AB:07B DB:00          MREQ RD                    | Memory read from 07B -> 00\n#011H T7  AB:07B DB:00          MREQ RD                    | Memory read from 07B -> 00\n#012H T8  AB:07C DB:--                                     | \n#013H T9  AB:07C DB:00          MREQ RD                    | Memory read from 07C -> 00\n#014H T10 AB:07C DB:00          MREQ RD                    | Memory read from 07C -> 00\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"7E\">Opcode: ED 7E     => IM 2*</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:7E  M1      MREQ RD                    | Opcode read from 001 -> 7E\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"A0\">Opcode: ED A0     => LDI</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:A0  M1      MREQ RD                    | Opcode read from 001 -> A0\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:06C DB:--                                     | \n#010H T6  AB:06C DB:00          MREQ RD                    | Memory read from 06C -> 00\n#011H T7  AB:06C DB:00          MREQ RD                    | Memory read from 06C -> 00\n#012H T8  AB:05B DB:--                                     | \n#013H T9  AB:05B DB:00          MREQ                       | \n#014H T10 AB:05B DB:00          MREQ    WR                 | Memory write to  05B <- 00\n#015H T11 AB:05B DB:00                                     | \n#016H T12 AB:05B DB:00                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"A1\">Opcode: ED A1     => CPI</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:A1  M1      MREQ RD                    | Opcode read from 001 -> A1\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:06D DB:--                                     | \n#010H T6  AB:06D DB:00          MREQ RD                    | Memory read from 06D -> 00\n#011H T7  AB:06D DB:00          MREQ RD                    | Memory read from 06D -> 00\n#012H T8  AB:06D DB:--                                     | \n#013H T9  AB:06D DB:--                                     | \n#014H T10 AB:06D DB:--                                     | \n#015H T11 AB:06D DB:--                                     | \n#016H T12 AB:06D DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"A2\">Opcode: ED A2     => INI</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:A2  M1      MREQ RD                    | Opcode read from 001 -> A2\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:001 DB:--                                     | \n#010H T6  AB:049 DB:--                                     | \n#011H T7  AB:049 DB:--               RD    IORQ            | I/O read from 049\n#012H T8  AB:049 DB:--               RD    IORQ            | I/O read from 049\n#013H T9  AB:049 DB:--               RD    IORQ            | I/O read from 049\n#014H T10 AB:06E DB:--                                     | \n#015H T11 AB:06E DB:A3          MREQ                       | \n#016H T12 AB:06E DB:A3          MREQ    WR                 | Memory write to  06E <- A3\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"A3\">Opcode: ED A3     => OUTI</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:A3  M1      MREQ RD                    | Opcode read from 001 -> A3\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:001 DB:--                                     | \n#010H T6  AB:06F DB:--                                     | \n#011H T7  AB:06F DB:00          MREQ RD                    | Memory read from 06F -> 00\n#012H T8  AB:06F DB:00          MREQ RD                    | Memory read from 06F -> 00\n#013H T9  AB:049 DB:--                                     | \n#014H T10 AB:049 DB:00                  WR IORQ            | I/O write to 049 <- 00\n#015H T11 AB:049 DB:00                  WR IORQ            | I/O write to 049 <- 00\n#016H T12 AB:049 DB:00                  WR IORQ            | I/O write to 049 <- 00\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"A8\">Opcode: ED A8     => LDD</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:A8  M1      MREQ RD                    | Opcode read from 001 -> A8\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:070 DB:--                                     | \n#010H T6  AB:070 DB:00          MREQ RD                    | Memory read from 070 -> 00\n#011H T7  AB:070 DB:00          MREQ RD                    | Memory read from 070 -> 00\n#012H T8  AB:05C DB:--                                     | \n#013H T9  AB:05C DB:00          MREQ                       | \n#014H T10 AB:05C DB:00          MREQ    WR                 | Memory write to  05C <- 00\n#015H T11 AB:05C DB:00                                     | \n#016H T12 AB:05C DB:00                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"A9\">Opcode: ED A9     => CPD</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:A9  M1      MREQ RD                    | Opcode read from 001 -> A9\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:06F DB:--                                     | \n#010H T6  AB:06F DB:00          MREQ RD                    | Memory read from 06F -> 00\n#011H T7  AB:06F DB:00          MREQ RD                    | Memory read from 06F -> 00\n#012H T8  AB:06F DB:--                                     | \n#013H T9  AB:06F DB:--                                     | \n#014H T10 AB:06F DB:--                                     | \n#015H T11 AB:06F DB:--                                     | \n#016H T12 AB:06F DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"AA\">Opcode: ED AA     => IND</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:AA  M1      MREQ RD                    | Opcode read from 001 -> AA\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:001 DB:--                                     | \n#010H T6  AB:047 DB:--                                     | \n#011H T7  AB:047 DB:--               RD    IORQ            | I/O read from 047\n#012H T8  AB:047 DB:--               RD    IORQ            | I/O read from 047\n#013H T9  AB:047 DB:--               RD    IORQ            | I/O read from 047\n#014H T10 AB:06E DB:--                                     | \n#015H T11 AB:06E DB:AB          MREQ                       | \n#016H T12 AB:06E DB:AB          MREQ    WR                 | Memory write to  06E <- AB\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"AB\">Opcode: ED AB     => OUTD</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:AB  M1      MREQ RD                    | Opcode read from 001 -> AB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:001 DB:--                                     | \n#010H T6  AB:06D DB:--                                     | \n#011H T7  AB:06D DB:00          MREQ RD                    | Memory read from 06D -> 00\n#012H T8  AB:06D DB:00          MREQ RD                    | Memory read from 06D -> 00\n#013H T9  AB:047 DB:--                                     | \n#014H T10 AB:047 DB:00                  WR IORQ            | I/O write to 047 <- 00\n#015H T11 AB:047 DB:00                  WR IORQ            | I/O write to 047 <- 00\n#016H T12 AB:047 DB:00                  WR IORQ            | I/O write to 047 <- 00\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"B0\">Opcode: ED B0     => LDIR</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:B0  M1      MREQ RD                    | Opcode read from 001 -> B0\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:06C DB:--                                     | \n#010H T6  AB:06C DB:00          MREQ RD                    | Memory read from 06C -> 00\n#011H T7  AB:06C DB:00          MREQ RD                    | Memory read from 06C -> 00\n#012H T8  AB:05B DB:--                                     | \n#013H T9  AB:05B DB:00          MREQ                       | \n#014H T10 AB:05B DB:00          MREQ    WR                 | Memory write to  05B <- 00\n#015H T11 AB:05B DB:00                                     | \n#016H T12 AB:05B DB:00                                     | \n#017H T13 AB:05B DB:--                                     | \n#018H T14 AB:05B DB:--                                     | \n#019H T15 AB:05B DB:--                                     | \n#020H T16 AB:05B DB:--                                     | \n#021H T17 AB:05B DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"B1\">Opcode: ED B1     => CPIR</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:B1  M1      MREQ RD                    | Opcode read from 001 -> B1\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:06D DB:--                                     | \n#010H T6  AB:06D DB:00          MREQ RD                    | Memory read from 06D -> 00\n#011H T7  AB:06D DB:00          MREQ RD                    | Memory read from 06D -> 00\n#012H T8  AB:06D DB:--                                     | \n#013H T9  AB:06D DB:--                                     | \n#014H T10 AB:06D DB:--                                     | \n#015H T11 AB:06D DB:--                                     | \n#016H T12 AB:06D DB:--                                     | \n#017H T13 AB:06D DB:--                                     | \n#018H T14 AB:06D DB:--                                     | \n#019H T15 AB:06D DB:--                                     | \n#020H T16 AB:06D DB:--                                     | \n#021H T17 AB:06D DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"B2\">Opcode: ED B2     => INIR</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:B2  M1      MREQ RD                    | Opcode read from 001 -> B2\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:001 DB:--                                     | \n#010H T6  AB:045 DB:--                                     | \n#011H T7  AB:045 DB:--               RD    IORQ            | I/O read from 045\n#012H T8  AB:045 DB:--               RD    IORQ            | I/O read from 045\n#013H T9  AB:045 DB:--               RD    IORQ            | I/O read from 045\n#014H T10 AB:06E DB:--                                     | \n#015H T11 AB:06E DB:B3          MREQ                       | \n#016H T12 AB:06E DB:B3          MREQ    WR                 | Memory write to  06E <- B3\n#017H T13 AB:06E DB:--                                     | \n#018H T14 AB:06E DB:--                                     | \n#019H T15 AB:06E DB:--                                     | \n#020H T16 AB:06E DB:--                                     | \n#021H T17 AB:06E DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"B3\">Opcode: ED B3     => OTIR</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:B3  M1      MREQ RD                    | Opcode read from 001 -> B3\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:001 DB:--                                     | \n#010H T6  AB:06F DB:--                                     | \n#011H T7  AB:06F DB:00          MREQ RD                    | Memory read from 06F -> 00\n#012H T8  AB:06F DB:00          MREQ RD                    | Memory read from 06F -> 00\n#013H T9  AB:045 DB:--                                     | \n#014H T10 AB:045 DB:00                  WR IORQ            | I/O write to 045 <- 00\n#015H T11 AB:045 DB:00                  WR IORQ            | I/O write to 045 <- 00\n#016H T12 AB:045 DB:00                  WR IORQ            | I/O write to 045 <- 00\n#017H T13 AB:045 DB:--                                     | \n#018H T14 AB:045 DB:--                                     | \n#019H T15 AB:045 DB:--                                     | \n#020H T16 AB:045 DB:--                                     | \n#021H T17 AB:045 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"B8\">Opcode: ED B8     => LDDR</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:B8  M1      MREQ RD                    | Opcode read from 001 -> B8\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:070 DB:--                                     | \n#010H T6  AB:070 DB:00          MREQ RD                    | Memory read from 070 -> 00\n#011H T7  AB:070 DB:00          MREQ RD                    | Memory read from 070 -> 00\n#012H T8  AB:05C DB:--                                     | \n#013H T9  AB:05C DB:00          MREQ                       | \n#014H T10 AB:05C DB:00          MREQ    WR                 | Memory write to  05C <- 00\n#015H T11 AB:05C DB:00                                     | \n#016H T12 AB:05C DB:00                                     | \n#017H T13 AB:05C DB:--                                     | \n#018H T14 AB:05C DB:--                                     | \n#019H T15 AB:05C DB:--                                     | \n#020H T16 AB:05C DB:--                                     | \n#021H T17 AB:05C DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"B9\">Opcode: ED B9     => CPDR</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:B9  M1      MREQ RD                    | Opcode read from 001 -> B9\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:06F DB:--                                     | \n#010H T6  AB:06F DB:00          MREQ RD                    | Memory read from 06F -> 00\n#011H T7  AB:06F DB:00          MREQ RD                    | Memory read from 06F -> 00\n#012H T8  AB:06F DB:--                                     | \n#013H T9  AB:06F DB:--                                     | \n#014H T10 AB:06F DB:--                                     | \n#015H T11 AB:06F DB:--                                     | \n#016H T12 AB:06F DB:--                                     | \n#017H T13 AB:06F DB:--                                     | \n#018H T14 AB:06F DB:--                                     | \n#019H T15 AB:06F DB:--                                     | \n#020H T16 AB:06F DB:--                                     | \n#021H T17 AB:06F DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"BA\">Opcode: ED BA     => INDR</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:BA  M1      MREQ RD                    | Opcode read from 001 -> BA\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:001 DB:--                                     | \n#010H T6  AB:043 DB:--                                     | \n#011H T7  AB:043 DB:--               RD    IORQ            | I/O read from 043\n#012H T8  AB:043 DB:--               RD    IORQ            | I/O read from 043\n#013H T9  AB:043 DB:--               RD    IORQ            | I/O read from 043\n#014H T10 AB:06E DB:--                                     | \n#015H T11 AB:06E DB:BB          MREQ                       | \n#016H T12 AB:06E DB:BB          MREQ    WR                 | Memory write to  06E <- BB\n#017H T13 AB:06E DB:--                                     | \n#018H T14 AB:06E DB:--                                     | \n#019H T15 AB:06E DB:--                                     | \n#020H T16 AB:06E DB:--                                     | \n#021H T17 AB:06E DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"BB\">Opcode: ED BB     => OTDR</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n#005H T1  AB:001 DB:--  M1                                 | \n#006H T2  AB:001 DB:BB  M1      MREQ RD                    | Opcode read from 001 -> BB\n#007H T3  AB:001 DB:--     RFSH                            | \n#008H T4  AB:001 DB:--     RFSH MREQ                       | Refresh address  001\n#009H T5  AB:001 DB:--                                     | \n#010H T6  AB:06D DB:--                                     | \n#011H T7  AB:06D DB:00          MREQ RD                    | Memory read from 06D -> 00\n#012H T8  AB:06D DB:00          MREQ RD                    | Memory read from 06D -> 00\n#013H T9  AB:043 DB:--                                     | \n#014H T10 AB:043 DB:00                  WR IORQ            | I/O write to 043 <- 00\n#015H T11 AB:043 DB:00                  WR IORQ            | I/O write to 043 <- 00\n#016H T12 AB:043 DB:00                  WR IORQ            | I/O write to 043 <- 00\n#017H T13 AB:043 DB:--                                     | \n#018H T14 AB:043 DB:--                                     | \n#019H T15 AB:043 DB:--                                     | \n#020H T16 AB:043 DB:--                                     | \n#021H T17 AB:043 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n</BODY></HTML>\n"
  },
  {
    "path": "tools/dongle/neg/neg-concise.txt",
    "content": "00 -> 00  Flags = 42\n01 -> FF  Flags = BB\n02 -> FE  Flags = BB\n03 -> FD  Flags = BB\n04 -> FC  Flags = BB\n05 -> FB  Flags = BB\n06 -> FA  Flags = BB\n07 -> F9  Flags = BB\n08 -> F8  Flags = BB\n09 -> F7  Flags = B3\n0A -> F6  Flags = B3\n0B -> F5  Flags = B3\n0C -> F4  Flags = B3\n0D -> F3  Flags = B3\n0E -> F2  Flags = B3\n0F -> F1  Flags = B3\n10 -> F0  Flags = A3\n11 -> EF  Flags = BB\n12 -> EE  Flags = BB\n13 -> ED  Flags = BB\n14 -> EC  Flags = BB\n15 -> EB  Flags = BB\n16 -> EA  Flags = BB\n17 -> E9  Flags = BB\n18 -> E8  Flags = BB\n19 -> E7  Flags = B3\n1A -> E6  Flags = B3\n1B -> E5  Flags = B3\n1C -> E4  Flags = B3\n1D -> E3  Flags = B3\n1E -> E2  Flags = B3\n1F -> E1  Flags = B3\n20 -> E0  Flags = A3\n21 -> DF  Flags = 9B\n22 -> DE  Flags = 9B\n23 -> DD  Flags = 9B\n24 -> DC  Flags = 9B\n25 -> DB  Flags = 9B\n26 -> DA  Flags = 9B\n27 -> D9  Flags = 9B\n28 -> D8  Flags = 9B\n29 -> D7  Flags = 93\n2A -> D6  Flags = 93\n2B -> D5  Flags = 93\n2C -> D4  Flags = 93\n2D -> D3  Flags = 93\n2E -> D2  Flags = 93\n2F -> D1  Flags = 93\n30 -> D0  Flags = 83\n31 -> CF  Flags = 9B\n32 -> CE  Flags = 9B\n33 -> CD  Flags = 9B\n34 -> CC  Flags = 9B\n35 -> CB  Flags = 9B\n36 -> CA  Flags = 9B\n37 -> C9  Flags = 9B\n38 -> C8  Flags = 9B\n39 -> C7  Flags = 93\n3A -> C6  Flags = 93\n3B -> C5  Flags = 93\n3C -> C4  Flags = 93\n3D -> C3  Flags = 93\n3E -> C2  Flags = 93\n3F -> C1  Flags = 93\n40 -> C0  Flags = 83\n41 -> BF  Flags = BB\n42 -> BE  Flags = BB\n43 -> BD  Flags = BB\n44 -> BC  Flags = BB\n45 -> BB  Flags = BB\n46 -> BA  Flags = BB\n47 -> B9  Flags = BB\n48 -> B8  Flags = BB\n49 -> B7  Flags = B3\n4A -> B6  Flags = B3\n4B -> B5  Flags = B3\n4C -> B4  Flags = B3\n4D -> B3  Flags = B3\n4E -> B2  Flags = B3\n4F -> B1  Flags = B3\n50 -> B0  Flags = A3\n51 -> AF  Flags = BB\n52 -> AE  Flags = BB\n53 -> AD  Flags = BB\n54 -> AC  Flags = BB\n55 -> AB  Flags = BB\n56 -> AA  Flags = BB\n57 -> A9  Flags = BB\n58 -> A8  Flags = BB\n59 -> A7  Flags = B3\n5A -> A6  Flags = B3\n5B -> A5  Flags = B3\n5C -> A4  Flags = B3\n5D -> A3  Flags = B3\n5E -> A2  Flags = B3\n5F -> A1  Flags = B3\n60 -> A0  Flags = A3\n61 -> 9F  Flags = 9B\n62 -> 9E  Flags = 9B\n63 -> 9D  Flags = 9B\n64 -> 9C  Flags = 9B\n65 -> 9B  Flags = 9B\n66 -> 9A  Flags = 9B\n67 -> 99  Flags = 9B\n68 -> 98  Flags = 9B\n69 -> 97  Flags = 93\n6A -> 96  Flags = 93\n6B -> 95  Flags = 93\n6C -> 94  Flags = 93\n6D -> 93  Flags = 93\n6E -> 92  Flags = 93\n6F -> 91  Flags = 93\n70 -> 90  Flags = 83\n71 -> 8F  Flags = 9B\n72 -> 8E  Flags = 9B\n73 -> 8D  Flags = 9B\n74 -> 8C  Flags = 9B\n75 -> 8B  Flags = 9B\n76 -> 8A  Flags = 9B\n77 -> 89  Flags = 9B\n78 -> 88  Flags = 9B\n79 -> 87  Flags = 93\n7A -> 86  Flags = 93\n7B -> 85  Flags = 93\n7C -> 84  Flags = 93\n7D -> 83  Flags = 93\n7E -> 82  Flags = 93\n7F -> 81  Flags = 93\n80 -> 80  Flags = 87\n81 -> 7F  Flags = 3B\n82 -> 7E  Flags = 3B\n83 -> 7D  Flags = 3B\n84 -> 7C  Flags = 3B\n85 -> 7B  Flags = 3B\n86 -> 7A  Flags = 3B\n87 -> 79  Flags = 3B\n88 -> 78  Flags = 3B\n89 -> 77  Flags = 33\n8A -> 76  Flags = 33\n8B -> 75  Flags = 33\n8C -> 74  Flags = 33\n8D -> 73  Flags = 33\n8E -> 72  Flags = 33\n8F -> 71  Flags = 33\n90 -> 70  Flags = 23\n91 -> 6F  Flags = 3B\n92 -> 6E  Flags = 3B\n93 -> 6D  Flags = 3B\n94 -> 6C  Flags = 3B\n95 -> 6B  Flags = 3B\n96 -> 6A  Flags = 3B\n97 -> 69  Flags = 3B\n98 -> 68  Flags = 3B\n99 -> 67  Flags = 33\n9A -> 66  Flags = 33\n9B -> 65  Flags = 33\n9C -> 64  Flags = 33\n9D -> 63  Flags = 33\n9E -> 62  Flags = 33\n9F -> 61  Flags = 33\nA0 -> 60  Flags = 23\nA1 -> 5F  Flags = 1B\nA2 -> 5E  Flags = 1B\nA3 -> 5D  Flags = 1B\nA4 -> 5C  Flags = 1B\nA5 -> 5B  Flags = 1B\nA6 -> 5A  Flags = 1B\nA7 -> 59  Flags = 1B\nA8 -> 58  Flags = 1B\nA9 -> 57  Flags = 13\nAA -> 56  Flags = 13\nAB -> 55  Flags = 13\nAC -> 54  Flags = 13\nAD -> 53  Flags = 13\nAE -> 52  Flags = 13\nAF -> 51  Flags = 13\nB0 -> 50  Flags = 03\nB1 -> 4F  Flags = 1B\nB2 -> 4E  Flags = 1B\nB3 -> 4D  Flags = 1B\nB4 -> 4C  Flags = 1B\nB5 -> 4B  Flags = 1B\nB6 -> 4A  Flags = 1B\nB7 -> 49  Flags = 1B\nB8 -> 48  Flags = 1B\nB9 -> 47  Flags = 13\nBA -> 46  Flags = 13\nBB -> 45  Flags = 13\nBC -> 44  Flags = 13\nBD -> 43  Flags = 13\nBE -> 42  Flags = 13\nBF -> 41  Flags = 13\nC0 -> 40  Flags = 03\nC1 -> 3F  Flags = 3B\nC2 -> 3E  Flags = 3B\nC3 -> 3D  Flags = 3B\nC4 -> 3C  Flags = 3B\nC5 -> 3B  Flags = 3B\nC6 -> 3A  Flags = 3B\nC7 -> 39  Flags = 3B\nC8 -> 38  Flags = 3B\nC9 -> 37  Flags = 33\nCA -> 36  Flags = 33\nCB -> 35  Flags = 33\nCC -> 34  Flags = 33\nCD -> 33  Flags = 33\nCE -> 32  Flags = 33\nCF -> 31  Flags = 33\nD0 -> 30  Flags = 23\nD1 -> 2F  Flags = 3B\nD2 -> 2E  Flags = 3B\nD3 -> 2D  Flags = 3B\nD4 -> 2C  Flags = 3B\nD5 -> 2B  Flags = 3B\nD6 -> 2A  Flags = 3B\nD7 -> 29  Flags = 3B\nD8 -> 28  Flags = 3B\nD9 -> 27  Flags = 33\nDA -> 26  Flags = 33\nDB -> 25  Flags = 33\nDC -> 24  Flags = 33\nDD -> 23  Flags = 33\nDE -> 22  Flags = 33\nDF -> 21  Flags = 33\nE0 -> 20  Flags = 23\nE1 -> 1F  Flags = 1B\nE2 -> 1E  Flags = 1B\nE3 -> 1D  Flags = 1B\nE4 -> 1C  Flags = 1B\nE5 -> 1B  Flags = 1B\nE6 -> 1A  Flags = 1B\nE7 -> 19  Flags = 1B\nE8 -> 18  Flags = 1B\nE9 -> 17  Flags = 13\nEA -> 16  Flags = 13\nEB -> 15  Flags = 13\nEC -> 14  Flags = 13\nED -> 13  Flags = 13\nEE -> 12  Flags = 13\nEF -> 11  Flags = 13\nF0 -> 10  Flags = 03\nF1 -> 0F  Flags = 1B\nF2 -> 0E  Flags = 1B\nF3 -> 0D  Flags = 1B\nF4 -> 0C  Flags = 1B\nF5 -> 0B  Flags = 1B\nF6 -> 0A  Flags = 1B\nF7 -> 09  Flags = 1B\nF8 -> 08  Flags = 1B\nF9 -> 07  Flags = 13\nFA -> 06  Flags = 13\nFB -> 05  Flags = 13\nFC -> 04  Flags = 13\nFD -> 03  Flags = 13\nFE -> 02  Flags = 13\nFF -> 01  Flags = 13\n"
  },
  {
    "path": "tools/dongle/neg/neg.out",
    "content": "#006H T6  AB:001 DB:00          MREQ RD                    | Memory read from 001 -> 00\n#007H T7  AB:001 DB:00          MREQ RD                    | Memory read from 001 -> 00\n#023H T8  AB:040 DB:00          MREQ    WR                 | Memory write to  040 <- 00\n#026H T11 AB:03F DB:42          MREQ    WR                 | Memory write to  03F <- 42\n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#023H T8  AB:03E DB:FF          MREQ    WR                 | Memory write to  03E <- FF\n#026H T11 AB:03D DB:BB          MREQ    WR                 | Memory write to  03D <- BB\n#006H T6  AB:001 DB:02          MREQ RD                    | Memory read from 001 -> 02\n#007H T7  AB:001 DB:02          MREQ RD                    | Memory read from 001 -> 02\n#023H T8  AB:03C DB:FE          MREQ    WR                 | Memory write to  03C <- FE\n#026H T11 AB:03B DB:BB          MREQ    WR                 | Memory write to  03B <- BB\n#006H T6  AB:001 DB:03          MREQ RD                    | Memory read from 001 -> 03\n#007H T7  AB:001 DB:03          MREQ RD                    | Memory read from 001 -> 03\n#023H T8  AB:03A DB:FD          MREQ    WR                 | Memory write to  03A <- FD\n#026H T11 AB:039 DB:BB          MREQ    WR                 | Memory write to  039 <- BB\n#006H T6  AB:001 DB:04          MREQ RD                    | Memory read from 001 -> 04\n#007H T7  AB:001 DB:04          MREQ RD                    | Memory read from 001 -> 04\n#023H T8  AB:038 DB:FC          MREQ    WR                 | Memory write to  038 <- FC\n#026H T11 AB:037 DB:BB          MREQ    WR                 | Memory write to  037 <- BB\n#006H T6  AB:001 DB:05          MREQ RD                    | Memory read from 001 -> 05\n#007H T7  AB:001 DB:05          MREQ RD                    | Memory read from 001 -> 05\n#023H T8  AB:036 DB:FB          MREQ    WR                 | Memory write to  036 <- FB\n#026H T11 AB:035 DB:BB          MREQ    WR                 | Memory write to  035 <- BB\n#006H T6  AB:001 DB:06          MREQ RD                    | Memory read from 001 -> 06\n#007H T7  AB:001 DB:06          MREQ RD                    | Memory read from 001 -> 06\n#023H T8  AB:034 DB:FA          MREQ    WR                 | Memory write to  034 <- FA\n#026H T11 AB:033 DB:BB          MREQ    WR                 | Memory write to  033 <- BB\n#006H T6  AB:001 DB:07          MREQ RD                    | Memory read from 001 -> 07\n#007H T7  AB:001 DB:07          MREQ RD                    | Memory read from 001 -> 07\n#023H T8  AB:032 DB:F9          MREQ    WR                 | Memory write to  032 <- F9\n#026H T11 AB:031 DB:BB          MREQ    WR                 | Memory write to  031 <- BB\n#006H T6  AB:001 DB:08          MREQ RD                    | Memory read from 001 -> 08\n#007H T7  AB:001 DB:08          MREQ RD                    | Memory read from 001 -> 08\n#023H T8  AB:030 DB:F8          MREQ    WR                 | Memory write to  030 <- F8\n#026H T11 AB:02F DB:BB          MREQ    WR                 | Memory write to  02F <- BB\n#006H T6  AB:001 DB:09          MREQ RD                    | Memory read from 001 -> 09\n#007H T7  AB:001 DB:09          MREQ RD                    | Memory read from 001 -> 09\n#023H T8  AB:02E DB:F7          MREQ    WR                 | Memory write to  02E <- F7\n#026H T11 AB:02D DB:B3          MREQ    WR                 | Memory write to  02D <- B3\n#006H T6  AB:001 DB:0A          MREQ RD                    | Memory read from 001 -> 0A\n#007H T7  AB:001 DB:0A          MREQ RD                    | Memory read from 001 -> 0A\n#023H T8  AB:02C DB:F6          MREQ    WR                 | Memory write to  02C <- F6\n#026H T11 AB:02B DB:B3          MREQ    WR                 | Memory write to  02B <- B3\n#006H T6  AB:001 DB:0B          MREQ RD                    | Memory read from 001 -> 0B\n#007H T7  AB:001 DB:0B          MREQ RD                    | Memory read from 001 -> 0B\n#023H T8  AB:02A DB:F5          MREQ    WR                 | Memory write to  02A <- F5\n#026H T11 AB:029 DB:B3          MREQ    WR                 | Memory write to  029 <- B3\n#006H T6  AB:001 DB:0C          MREQ RD                    | Memory read from 001 -> 0C\n#007H T7  AB:001 DB:0C          MREQ RD                    | Memory read from 001 -> 0C\n#023H T8  AB:028 DB:F4          MREQ    WR                 | Memory write to  028 <- F4\n#026H T11 AB:027 DB:B3          MREQ    WR                 | Memory write to  027 <- B3\n#006H T6  AB:001 DB:0D          MREQ RD                    | Memory read from 001 -> 0D\n#007H T7  AB:001 DB:0D          MREQ RD                    | Memory read from 001 -> 0D\n#023H T8  AB:026 DB:F3          MREQ    WR                 | Memory write to  026 <- F3\n#026H T11 AB:025 DB:B3          MREQ    WR                 | Memory write to  025 <- B3\n#006H T6  AB:001 DB:0E          MREQ RD                    | Memory read from 001 -> 0E\n#007H T7  AB:001 DB:0E          MREQ RD                    | Memory read from 001 -> 0E\n#023H T8  AB:024 DB:F2          MREQ    WR                 | Memory write to  024 <- F2\n#026H T11 AB:023 DB:B3          MREQ    WR                 | Memory write to  023 <- B3\n#006H T6  AB:001 DB:0F          MREQ RD                    | Memory read from 001 -> 0F\n#007H T7  AB:001 DB:0F          MREQ RD                    | Memory read from 001 -> 0F\n#023H T8  AB:022 DB:F1          MREQ    WR                 | Memory write to  022 <- F1\n#026H T11 AB:021 DB:B3          MREQ    WR                 | Memory write to  021 <- B3\n#006H T6  AB:001 DB:10          MREQ RD                    | Memory read from 001 -> 10\n#007H T7  AB:001 DB:10          MREQ RD                    | Memory read from 001 -> 10\n#023H T8  AB:020 DB:F0          MREQ    WR                 | Memory write to  020 <- F0\n#026H T11 AB:01F DB:A3          MREQ    WR                 | Memory write to  01F <- A3\n#006H T6  AB:001 DB:11          MREQ RD                    | Memory read from 001 -> 11\n#007H T7  AB:001 DB:11          MREQ RD                    | Memory read from 001 -> 11\n#023H T8  AB:01E DB:EF          MREQ    WR                 | Memory write to  01E <- EF\n#026H T11 AB:01D DB:BB          MREQ    WR                 | Memory write to  01D <- BB\n#006H T6  AB:001 DB:12          MREQ RD                    | Memory read from 001 -> 12\n#007H T7  AB:001 DB:12          MREQ RD                    | Memory read from 001 -> 12\n#023H T8  AB:01C DB:EE          MREQ    WR                 | Memory write to  01C <- EE\n#026H T11 AB:01B DB:BB          MREQ    WR                 | Memory write to  01B <- BB\n#006H T6  AB:001 DB:13          MREQ RD                    | Memory read from 001 -> 13\n#007H T7  AB:001 DB:13          MREQ RD                    | Memory read from 001 -> 13\n#023H T8  AB:01A DB:ED          MREQ    WR                 | Memory write to  01A <- ED\n#026H T11 AB:019 DB:BB          MREQ    WR                 | Memory write to  019 <- BB\n#006H T6  AB:001 DB:14          MREQ RD                    | Memory read from 001 -> 14\n#007H T7  AB:001 DB:14          MREQ RD                    | Memory read from 001 -> 14\n#023H T8  AB:018 DB:EC          MREQ    WR                 | Memory write to  018 <- EC\n#026H T11 AB:017 DB:BB          MREQ    WR                 | Memory write to  017 <- BB\n#006H T6  AB:001 DB:15          MREQ RD                    | Memory read from 001 -> 15\n#007H T7  AB:001 DB:15          MREQ RD                    | Memory read from 001 -> 15\n#023H T8  AB:016 DB:EB          MREQ    WR                 | Memory write to  016 <- EB\n#026H T11 AB:015 DB:BB          MREQ    WR                 | Memory write to  015 <- BB\n#006H T6  AB:001 DB:16          MREQ RD                    | Memory read from 001 -> 16\n#007H T7  AB:001 DB:16          MREQ RD                    | Memory read from 001 -> 16\n#023H T8  AB:014 DB:EA          MREQ    WR                 | Memory write to  014 <- EA\n#026H T11 AB:013 DB:BB          MREQ    WR                 | Memory write to  013 <- BB\n#006H T6  AB:001 DB:17          MREQ RD                    | Memory read from 001 -> 17\n#007H T7  AB:001 DB:17          MREQ RD                    | Memory read from 001 -> 17\n#023H T8  AB:012 DB:E9          MREQ    WR                 | Memory write to  012 <- E9\n#026H T11 AB:011 DB:BB          MREQ    WR                 | Memory write to  011 <- BB\n#006H T6  AB:001 DB:18          MREQ RD                    | Memory read from 001 -> 18\n#007H T7  AB:001 DB:18          MREQ RD                    | Memory read from 001 -> 18\n#023H T8  AB:010 DB:E8          MREQ    WR                 | Memory write to  010 <- E8\n#026H T11 AB:00F DB:BB          MREQ    WR                 | Memory write to  00F <- BB\n#006H T6  AB:001 DB:19          MREQ RD                    | Memory read from 001 -> 19\n#007H T7  AB:001 DB:19          MREQ RD                    | Memory read from 001 -> 19\n#023H T8  AB:00E DB:E7          MREQ    WR                 | Memory write to  00E <- E7\n#026H T11 AB:00D DB:B3          MREQ    WR                 | Memory write to  00D <- B3\n#006H T6  AB:001 DB:1A          MREQ RD                    | Memory read from 001 -> 1A\n#007H T7  AB:001 DB:1A          MREQ RD                    | Memory read from 001 -> 1A\n#023H T8  AB:00C DB:E6          MREQ    WR                 | Memory write to  00C <- E6\n#026H T11 AB:00B DB:B3          MREQ    WR                 | Memory write to  00B <- B3\n#006H T6  AB:001 DB:1B          MREQ RD                    | Memory read from 001 -> 1B\n#007H T7  AB:001 DB:1B          MREQ RD                    | Memory read from 001 -> 1B\n#023H T8  AB:00A DB:E5          MREQ    WR                 | Memory write to  00A <- E5\n#026H T11 AB:009 DB:B3          MREQ    WR                 | Memory write to  009 <- B3\n#006H T6  AB:001 DB:1C          MREQ RD                    | Memory read from 001 -> 1C\n#007H T7  AB:001 DB:1C          MREQ RD                    | Memory read from 001 -> 1C\n#023H T8  AB:008 DB:E4          MREQ    WR                 | Memory write to  008 <- E4\n#026H T11 AB:007 DB:B3          MREQ    WR                 | Memory write to  007 <- B3\n#006H T6  AB:001 DB:1D          MREQ RD                    | Memory read from 001 -> 1D\n#007H T7  AB:001 DB:1D          MREQ RD                    | Memory read from 001 -> 1D\n#023H T8  AB:006 DB:E3          MREQ    WR                 | Memory write to  006 <- E3\n#026H T11 AB:005 DB:B3          MREQ    WR                 | Memory write to  005 <- B3\n#006H T6  AB:001 DB:1E          MREQ RD                    | Memory read from 001 -> 1E\n#007H T7  AB:001 DB:1E          MREQ RD                    | Memory read from 001 -> 1E\n#023H T8  AB:004 DB:E2          MREQ    WR                 | Memory write to  004 <- E2\n#026H T11 AB:003 DB:B3          MREQ    WR                 | Memory write to  003 <- B3\n#006H T6  AB:001 DB:1F          MREQ RD                    | Memory read from 001 -> 1F\n#007H T7  AB:001 DB:1F          MREQ RD                    | Memory read from 001 -> 1F\n#023H T8  AB:002 DB:E1          MREQ    WR                 | Memory write to  002 <- E1\n#026H T11 AB:001 DB:B3          MREQ    WR                 | Memory write to  001 <- B3\n#006H T6  AB:001 DB:20          MREQ RD                    | Memory read from 001 -> 20\n#007H T7  AB:001 DB:20          MREQ RD                    | Memory read from 001 -> 20\n#023H T8  AB:000 DB:E0          MREQ    WR                 | Memory write to  000 <- E0\n#026H T11 AB:0FF DB:A3          MREQ    WR                 | Memory write to  0FF <- A3\n#006H T6  AB:001 DB:21          MREQ RD                    | Memory read from 001 -> 21\n#007H T7  AB:001 DB:21          MREQ RD                    | Memory read from 001 -> 21\n#023H T8  AB:0FE DB:DF          MREQ    WR                 | Memory write to  0FE <- DF\n#026H T11 AB:0FD DB:9B          MREQ    WR                 | Memory write to  0FD <- 9B\n#006H T6  AB:001 DB:22          MREQ RD                    | Memory read from 001 -> 22\n#007H T7  AB:001 DB:22          MREQ RD                    | Memory read from 001 -> 22\n#023H T8  AB:0FC DB:DE          MREQ    WR                 | Memory write to  0FC <- DE\n#026H T11 AB:0FB DB:9B          MREQ    WR                 | Memory write to  0FB <- 9B\n#006H T6  AB:001 DB:23          MREQ RD                    | Memory read from 001 -> 23\n#007H T7  AB:001 DB:23          MREQ RD                    | Memory read from 001 -> 23\n#023H T8  AB:0FA DB:DD          MREQ    WR                 | Memory write to  0FA <- DD\n#026H T11 AB:0F9 DB:9B          MREQ    WR                 | Memory write to  0F9 <- 9B\n#006H T6  AB:001 DB:24          MREQ RD                    | Memory read from 001 -> 24\n#007H T7  AB:001 DB:24          MREQ RD                    | Memory read from 001 -> 24\n#023H T8  AB:0F8 DB:DC          MREQ    WR                 | Memory write to  0F8 <- DC\n#026H T11 AB:0F7 DB:9B          MREQ    WR                 | Memory write to  0F7 <- 9B\n#006H T6  AB:001 DB:25          MREQ RD                    | Memory read from 001 -> 25\n#007H T7  AB:001 DB:25          MREQ RD                    | Memory read from 001 -> 25\n#023H T8  AB:0F6 DB:DB          MREQ    WR                 | Memory write to  0F6 <- DB\n#026H T11 AB:0F5 DB:9B          MREQ    WR                 | Memory write to  0F5 <- 9B\n#006H T6  AB:001 DB:26          MREQ RD                    | Memory read from 001 -> 26\n#007H T7  AB:001 DB:26          MREQ RD                    | Memory read from 001 -> 26\n#023H T8  AB:0F4 DB:DA          MREQ    WR                 | Memory write to  0F4 <- DA\n#026H T11 AB:0F3 DB:9B          MREQ    WR                 | Memory write to  0F3 <- 9B\n#006H T6  AB:001 DB:27          MREQ RD                    | Memory read from 001 -> 27\n#007H T7  AB:001 DB:27          MREQ RD                    | Memory read from 001 -> 27\n#023H T8  AB:0F2 DB:D9          MREQ    WR                 | Memory write to  0F2 <- D9\n#026H T11 AB:0F1 DB:9B          MREQ    WR                 | Memory write to  0F1 <- 9B\n#006H T6  AB:001 DB:28          MREQ RD                    | Memory read from 001 -> 28\n#007H T7  AB:001 DB:28          MREQ RD                    | Memory read from 001 -> 28\n#023H T8  AB:0F0 DB:D8          MREQ    WR                 | Memory write to  0F0 <- D8\n#026H T11 AB:0EF DB:9B          MREQ    WR                 | Memory write to  0EF <- 9B\n#006H T6  AB:001 DB:29          MREQ RD                    | Memory read from 001 -> 29\n#007H T7  AB:001 DB:29          MREQ RD                    | Memory read from 001 -> 29\n#023H T8  AB:0EE DB:D7          MREQ    WR                 | Memory write to  0EE <- D7\n#026H T11 AB:0ED DB:93          MREQ    WR                 | Memory write to  0ED <- 93\n#006H T6  AB:001 DB:2A          MREQ RD                    | Memory read from 001 -> 2A\n#007H T7  AB:001 DB:2A          MREQ RD                    | Memory read from 001 -> 2A\n#023H T8  AB:0EC DB:D6          MREQ    WR                 | Memory write to  0EC <- D6\n#026H T11 AB:0EB DB:93          MREQ    WR                 | Memory write to  0EB <- 93\n#006H T6  AB:001 DB:2B          MREQ RD                    | Memory read from 001 -> 2B\n#007H T7  AB:001 DB:2B          MREQ RD                    | Memory read from 001 -> 2B\n#023H T8  AB:0EA DB:D5          MREQ    WR                 | Memory write to  0EA <- D5\n#026H T11 AB:0E9 DB:93          MREQ    WR                 | Memory write to  0E9 <- 93\n#006H T6  AB:001 DB:2C          MREQ RD                    | Memory read from 001 -> 2C\n#007H T7  AB:001 DB:2C          MREQ RD                    | Memory read from 001 -> 2C\n#023H T8  AB:0E8 DB:D4          MREQ    WR                 | Memory write to  0E8 <- D4\n#026H T11 AB:0E7 DB:93          MREQ    WR                 | Memory write to  0E7 <- 93\n#006H T6  AB:001 DB:2D          MREQ RD                    | Memory read from 001 -> 2D\n#007H T7  AB:001 DB:2D          MREQ RD                    | Memory read from 001 -> 2D\n#023H T8  AB:0E6 DB:D3          MREQ    WR                 | Memory write to  0E6 <- D3\n#026H T11 AB:0E5 DB:93          MREQ    WR                 | Memory write to  0E5 <- 93\n#006H T6  AB:001 DB:2E          MREQ RD                    | Memory read from 001 -> 2E\n#007H T7  AB:001 DB:2E          MREQ RD                    | Memory read from 001 -> 2E\n#023H T8  AB:0E4 DB:D2          MREQ    WR                 | Memory write to  0E4 <- D2\n#026H T11 AB:0E3 DB:93          MREQ    WR                 | Memory write to  0E3 <- 93\n#006H T6  AB:001 DB:2F          MREQ RD                    | Memory read from 001 -> 2F\n#007H T7  AB:001 DB:2F          MREQ RD                    | Memory read from 001 -> 2F\n#023H T8  AB:0E2 DB:D1          MREQ    WR                 | Memory write to  0E2 <- D1\n#026H T11 AB:0E1 DB:93          MREQ    WR                 | Memory write to  0E1 <- 93\n#006H T6  AB:001 DB:30          MREQ RD                    | Memory read from 001 -> 30\n#007H T7  AB:001 DB:30          MREQ RD                    | Memory read from 001 -> 30\n#023H T8  AB:0E0 DB:D0          MREQ    WR                 | Memory write to  0E0 <- D0\n#026H T11 AB:0DF DB:83          MREQ    WR                 | Memory write to  0DF <- 83\n#006H T6  AB:001 DB:31          MREQ RD                    | Memory read from 001 -> 31\n#007H T7  AB:001 DB:31          MREQ RD                    | Memory read from 001 -> 31\n#023H T8  AB:0DE DB:CF          MREQ    WR                 | Memory write to  0DE <- CF\n#026H T11 AB:0DD DB:9B          MREQ    WR                 | Memory write to  0DD <- 9B\n#006H T6  AB:001 DB:32          MREQ RD                    | Memory read from 001 -> 32\n#007H T7  AB:001 DB:32          MREQ RD                    | Memory read from 001 -> 32\n#023H T8  AB:0DC DB:CE          MREQ    WR                 | Memory write to  0DC <- CE\n#026H T11 AB:0DB DB:9B          MREQ    WR                 | Memory write to  0DB <- 9B\n#006H T6  AB:001 DB:33          MREQ RD                    | Memory read from 001 -> 33\n#007H T7  AB:001 DB:33          MREQ RD                    | Memory read from 001 -> 33\n#023H T8  AB:0DA DB:CD          MREQ    WR                 | Memory write to  0DA <- CD\n#026H T11 AB:0D9 DB:9B          MREQ    WR                 | Memory write to  0D9 <- 9B\n#006H T6  AB:001 DB:34          MREQ RD                    | Memory read from 001 -> 34\n#007H T7  AB:001 DB:34          MREQ RD                    | Memory read from 001 -> 34\n#023H T8  AB:0D8 DB:CC          MREQ    WR                 | Memory write to  0D8 <- CC\n#026H T11 AB:0D7 DB:9B          MREQ    WR                 | Memory write to  0D7 <- 9B\n#006H T6  AB:001 DB:35          MREQ RD                    | Memory read from 001 -> 35\n#007H T7  AB:001 DB:35          MREQ RD                    | Memory read from 001 -> 35\n#023H T8  AB:0D6 DB:CB          MREQ    WR                 | Memory write to  0D6 <- CB\n#026H T11 AB:0D5 DB:9B          MREQ    WR                 | Memory write to  0D5 <- 9B\n#006H T6  AB:001 DB:36          MREQ RD                    | Memory read from 001 -> 36\n#007H T7  AB:001 DB:36          MREQ RD                    | Memory read from 001 -> 36\n#023H T8  AB:0D4 DB:CA          MREQ    WR                 | Memory write to  0D4 <- CA\n#026H T11 AB:0D3 DB:9B          MREQ    WR                 | Memory write to  0D3 <- 9B\n#006H T6  AB:001 DB:37          MREQ RD                    | Memory read from 001 -> 37\n#007H T7  AB:001 DB:37          MREQ RD                    | Memory read from 001 -> 37\n#023H T8  AB:0D2 DB:C9          MREQ    WR                 | Memory write to  0D2 <- C9\n#026H T11 AB:0D1 DB:9B          MREQ    WR                 | Memory write to  0D1 <- 9B\n#006H T6  AB:001 DB:38          MREQ RD                    | Memory read from 001 -> 38\n#007H T7  AB:001 DB:38          MREQ RD                    | Memory read from 001 -> 38\n#023H T8  AB:0D0 DB:C8          MREQ    WR                 | Memory write to  0D0 <- C8\n#026H T11 AB:0CF DB:9B          MREQ    WR                 | Memory write to  0CF <- 9B\n#006H T6  AB:001 DB:39          MREQ RD                    | Memory read from 001 -> 39\n#007H T7  AB:001 DB:39          MREQ RD                    | Memory read from 001 -> 39\n#023H T8  AB:0CE DB:C7          MREQ    WR                 | Memory write to  0CE <- C7\n#026H T11 AB:0CD DB:93          MREQ    WR                 | Memory write to  0CD <- 93\n#006H T6  AB:001 DB:3A          MREQ RD                    | Memory read from 001 -> 3A\n#007H T7  AB:001 DB:3A          MREQ RD                    | Memory read from 001 -> 3A\n#023H T8  AB:0CC DB:C6          MREQ    WR                 | Memory write to  0CC <- C6\n#026H T11 AB:0CB DB:93          MREQ    WR                 | Memory write to  0CB <- 93\n#006H T6  AB:001 DB:3B          MREQ RD                    | Memory read from 001 -> 3B\n#007H T7  AB:001 DB:3B          MREQ RD                    | Memory read from 001 -> 3B\n#023H T8  AB:0CA DB:C5          MREQ    WR                 | Memory write to  0CA <- C5\n#026H T11 AB:0C9 DB:93          MREQ    WR                 | Memory write to  0C9 <- 93\n#006H T6  AB:001 DB:3C          MREQ RD                    | Memory read from 001 -> 3C\n#007H T7  AB:001 DB:3C          MREQ RD                    | Memory read from 001 -> 3C\n#023H T8  AB:0C8 DB:C4          MREQ    WR                 | Memory write to  0C8 <- C4\n#026H T11 AB:0C7 DB:93          MREQ    WR                 | Memory write to  0C7 <- 93\n#006H T6  AB:001 DB:3D          MREQ RD                    | Memory read from 001 -> 3D\n#007H T7  AB:001 DB:3D          MREQ RD                    | Memory read from 001 -> 3D\n#023H T8  AB:0C6 DB:C3          MREQ    WR                 | Memory write to  0C6 <- C3\n#026H T11 AB:0C5 DB:93          MREQ    WR                 | Memory write to  0C5 <- 93\n#006H T6  AB:001 DB:3E          MREQ RD                    | Memory read from 001 -> 3E\n#007H T7  AB:001 DB:3E          MREQ RD                    | Memory read from 001 -> 3E\n#023H T8  AB:0C4 DB:C2          MREQ    WR                 | Memory write to  0C4 <- C2\n#026H T11 AB:0C3 DB:93          MREQ    WR                 | Memory write to  0C3 <- 93\n#006H T6  AB:001 DB:3F          MREQ RD                    | Memory read from 001 -> 3F\n#007H T7  AB:001 DB:3F          MREQ RD                    | Memory read from 001 -> 3F\n#023H T8  AB:0C2 DB:C1          MREQ    WR                 | Memory write to  0C2 <- C1\n#026H T11 AB:0C1 DB:93          MREQ    WR                 | Memory write to  0C1 <- 93\n#006H T6  AB:001 DB:40          MREQ RD                    | Memory read from 001 -> 40\n#007H T7  AB:001 DB:40          MREQ RD                    | Memory read from 001 -> 40\n#023H T8  AB:0C0 DB:C0          MREQ    WR                 | Memory write to  0C0 <- C0\n#026H T11 AB:0BF DB:83          MREQ    WR                 | Memory write to  0BF <- 83\n#006H T6  AB:001 DB:41          MREQ RD                    | Memory read from 001 -> 41\n#007H T7  AB:001 DB:41          MREQ RD                    | Memory read from 001 -> 41\n#023H T8  AB:0BE DB:BF          MREQ    WR                 | Memory write to  0BE <- BF\n#026H T11 AB:0BD DB:BB          MREQ    WR                 | Memory write to  0BD <- BB\n#006H T6  AB:001 DB:42          MREQ RD                    | Memory read from 001 -> 42\n#007H T7  AB:001 DB:42          MREQ RD                    | Memory read from 001 -> 42\n#023H T8  AB:0BC DB:BE          MREQ    WR                 | Memory write to  0BC <- BE\n#026H T11 AB:0BB DB:BB          MREQ    WR                 | Memory write to  0BB <- BB\n#006H T6  AB:001 DB:43          MREQ RD                    | Memory read from 001 -> 43\n#007H T7  AB:001 DB:43          MREQ RD                    | Memory read from 001 -> 43\n#023H T8  AB:0BA DB:BD          MREQ    WR                 | Memory write to  0BA <- BD\n#026H T11 AB:0B9 DB:BB          MREQ    WR                 | Memory write to  0B9 <- BB\n#006H T6  AB:001 DB:44          MREQ RD                    | Memory read from 001 -> 44\n#007H T7  AB:001 DB:44          MREQ RD                    | Memory read from 001 -> 44\n#023H T8  AB:0B8 DB:BC          MREQ    WR                 | Memory write to  0B8 <- BC\n#026H T11 AB:0B7 DB:BB          MREQ    WR                 | Memory write to  0B7 <- BB\n#006H T6  AB:001 DB:45          MREQ RD                    | Memory read from 001 -> 45\n#007H T7  AB:001 DB:45          MREQ RD                    | Memory read from 001 -> 45\n#023H T8  AB:0B6 DB:BB          MREQ    WR                 | Memory write to  0B6 <- BB\n#026H T11 AB:0B5 DB:BB          MREQ    WR                 | Memory write to  0B5 <- BB\n#006H T6  AB:001 DB:46          MREQ RD                    | Memory read from 001 -> 46\n#007H T7  AB:001 DB:46          MREQ RD                    | Memory read from 001 -> 46\n#023H T8  AB:0B4 DB:BA          MREQ    WR                 | Memory write to  0B4 <- BA\n#026H T11 AB:0B3 DB:BB          MREQ    WR                 | Memory write to  0B3 <- BB\n#006H T6  AB:001 DB:47          MREQ RD                    | Memory read from 001 -> 47\n#007H T7  AB:001 DB:47          MREQ RD                    | Memory read from 001 -> 47\n#023H T8  AB:0B2 DB:B9          MREQ    WR                 | Memory write to  0B2 <- B9\n#026H T11 AB:0B1 DB:BB          MREQ    WR                 | Memory write to  0B1 <- BB\n#006H T6  AB:001 DB:48          MREQ RD                    | Memory read from 001 -> 48\n#007H T7  AB:001 DB:48          MREQ RD                    | Memory read from 001 -> 48\n#023H T8  AB:0B0 DB:B8          MREQ    WR                 | Memory write to  0B0 <- B8\n#026H T11 AB:0AF DB:BB          MREQ    WR                 | Memory write to  0AF <- BB\n#006H T6  AB:001 DB:49          MREQ RD                    | Memory read from 001 -> 49\n#007H T7  AB:001 DB:49          MREQ RD                    | Memory read from 001 -> 49\n#023H T8  AB:0AE DB:B7          MREQ    WR                 | Memory write to  0AE <- B7\n#026H T11 AB:0AD DB:B3          MREQ    WR                 | Memory write to  0AD <- B3\n#006H T6  AB:001 DB:4A          MREQ RD                    | Memory read from 001 -> 4A\n#007H T7  AB:001 DB:4A          MREQ RD                    | Memory read from 001 -> 4A\n#023H T8  AB:0AC DB:B6          MREQ    WR                 | Memory write to  0AC <- B6\n#026H T11 AB:0AB DB:B3          MREQ    WR                 | Memory write to  0AB <- B3\n#006H T6  AB:001 DB:4B          MREQ RD                    | Memory read from 001 -> 4B\n#007H T7  AB:001 DB:4B          MREQ RD                    | Memory read from 001 -> 4B\n#023H T8  AB:0AA DB:B5          MREQ    WR                 | Memory write to  0AA <- B5\n#026H T11 AB:0A9 DB:B3          MREQ    WR                 | Memory write to  0A9 <- B3\n#006H T6  AB:001 DB:4C          MREQ RD                    | Memory read from 001 -> 4C\n#007H T7  AB:001 DB:4C          MREQ RD                    | Memory read from 001 -> 4C\n#023H T8  AB:0A8 DB:B4          MREQ    WR                 | Memory write to  0A8 <- B4\n#026H T11 AB:0A7 DB:B3          MREQ    WR                 | Memory write to  0A7 <- B3\n#006H T6  AB:001 DB:4D          MREQ RD                    | Memory read from 001 -> 4D\n#007H T7  AB:001 DB:4D          MREQ RD                    | Memory read from 001 -> 4D\n#023H T8  AB:0A6 DB:B3          MREQ    WR                 | Memory write to  0A6 <- B3\n#026H T11 AB:0A5 DB:B3          MREQ    WR                 | Memory write to  0A5 <- B3\n#006H T6  AB:001 DB:4E          MREQ RD                    | Memory read from 001 -> 4E\n#007H T7  AB:001 DB:4E          MREQ RD                    | Memory read from 001 -> 4E\n#023H T8  AB:0A4 DB:B2          MREQ    WR                 | Memory write to  0A4 <- B2\n#026H T11 AB:0A3 DB:B3          MREQ    WR                 | Memory write to  0A3 <- B3\n#006H T6  AB:001 DB:4F          MREQ RD                    | Memory read from 001 -> 4F\n#007H T7  AB:001 DB:4F          MREQ RD                    | Memory read from 001 -> 4F\n#023H T8  AB:0A2 DB:B1          MREQ    WR                 | Memory write to  0A2 <- B1\n#026H T11 AB:0A1 DB:B3          MREQ    WR                 | Memory write to  0A1 <- B3\n#006H T6  AB:001 DB:50          MREQ RD                    | Memory read from 001 -> 50\n#007H T7  AB:001 DB:50          MREQ RD                    | Memory read from 001 -> 50\n#023H T8  AB:0A0 DB:B0          MREQ    WR                 | Memory write to  0A0 <- B0\n#026H T11 AB:09F DB:A3          MREQ    WR                 | Memory write to  09F <- A3\n#006H T6  AB:001 DB:51          MREQ RD                    | Memory read from 001 -> 51\n#007H T7  AB:001 DB:51          MREQ RD                    | Memory read from 001 -> 51\n#023H T8  AB:09E DB:AF          MREQ    WR                 | Memory write to  09E <- AF\n#026H T11 AB:09D DB:BB          MREQ    WR                 | Memory write to  09D <- BB\n#006H T6  AB:001 DB:52          MREQ RD                    | Memory read from 001 -> 52\n#007H T7  AB:001 DB:52          MREQ RD                    | Memory read from 001 -> 52\n#023H T8  AB:09C DB:AE          MREQ    WR                 | Memory write to  09C <- AE\n#026H T11 AB:09B DB:BB          MREQ    WR                 | Memory write to  09B <- BB\n#006H T6  AB:001 DB:53          MREQ RD                    | Memory read from 001 -> 53\n#007H T7  AB:001 DB:53          MREQ RD                    | Memory read from 001 -> 53\n#023H T8  AB:09A DB:AD          MREQ    WR                 | Memory write to  09A <- AD\n#026H T11 AB:099 DB:BB          MREQ    WR                 | Memory write to  099 <- BB\n#006H T6  AB:001 DB:54          MREQ RD                    | Memory read from 001 -> 54\n#007H T7  AB:001 DB:54          MREQ RD                    | Memory read from 001 -> 54\n#023H T8  AB:098 DB:AC          MREQ    WR                 | Memory write to  098 <- AC\n#026H T11 AB:097 DB:BB          MREQ    WR                 | Memory write to  097 <- BB\n#006H T6  AB:001 DB:55          MREQ RD                    | Memory read from 001 -> 55\n#007H T7  AB:001 DB:55          MREQ RD                    | Memory read from 001 -> 55\n#023H T8  AB:096 DB:AB          MREQ    WR                 | Memory write to  096 <- AB\n#026H T11 AB:095 DB:BB          MREQ    WR                 | Memory write to  095 <- BB\n#006H T6  AB:001 DB:56          MREQ RD                    | Memory read from 001 -> 56\n#007H T7  AB:001 DB:56          MREQ RD                    | Memory read from 001 -> 56\n#023H T8  AB:094 DB:AA          MREQ    WR                 | Memory write to  094 <- AA\n#026H T11 AB:093 DB:BB          MREQ    WR                 | Memory write to  093 <- BB\n#006H T6  AB:001 DB:57          MREQ RD                    | Memory read from 001 -> 57\n#007H T7  AB:001 DB:57          MREQ RD                    | Memory read from 001 -> 57\n#023H T8  AB:092 DB:A9          MREQ    WR                 | Memory write to  092 <- A9\n#026H T11 AB:091 DB:BB          MREQ    WR                 | Memory write to  091 <- BB\n#006H T6  AB:001 DB:58          MREQ RD                    | Memory read from 001 -> 58\n#007H T7  AB:001 DB:58          MREQ RD                    | Memory read from 001 -> 58\n#023H T8  AB:090 DB:A8          MREQ    WR                 | Memory write to  090 <- A8\n#026H T11 AB:08F DB:BB          MREQ    WR                 | Memory write to  08F <- BB\n#006H T6  AB:001 DB:59          MREQ RD                    | Memory read from 001 -> 59\n#007H T7  AB:001 DB:59          MREQ RD                    | Memory read from 001 -> 59\n#023H T8  AB:08E DB:A7          MREQ    WR                 | Memory write to  08E <- A7\n#026H T11 AB:08D DB:B3          MREQ    WR                 | Memory write to  08D <- B3\n#006H T6  AB:001 DB:5A          MREQ RD                    | Memory read from 001 -> 5A\n#007H T7  AB:001 DB:5A          MREQ RD                    | Memory read from 001 -> 5A\n#023H T8  AB:08C DB:A6          MREQ    WR                 | Memory write to  08C <- A6\n#026H T11 AB:08B DB:B3          MREQ    WR                 | Memory write to  08B <- B3\n#006H T6  AB:001 DB:5B          MREQ RD                    | Memory read from 001 -> 5B\n#007H T7  AB:001 DB:5B          MREQ RD                    | Memory read from 001 -> 5B\n#023H T8  AB:08A DB:A5          MREQ    WR                 | Memory write to  08A <- A5\n#026H T11 AB:089 DB:B3          MREQ    WR                 | Memory write to  089 <- B3\n#006H T6  AB:001 DB:5C          MREQ RD                    | Memory read from 001 -> 5C\n#007H T7  AB:001 DB:5C          MREQ RD                    | Memory read from 001 -> 5C\n#023H T8  AB:088 DB:A4          MREQ    WR                 | Memory write to  088 <- A4\n#026H T11 AB:087 DB:B3          MREQ    WR                 | Memory write to  087 <- B3\n#006H T6  AB:001 DB:5D          MREQ RD                    | Memory read from 001 -> 5D\n#007H T7  AB:001 DB:5D          MREQ RD                    | Memory read from 001 -> 5D\n#023H T8  AB:086 DB:A3          MREQ    WR                 | Memory write to  086 <- A3\n#026H T11 AB:085 DB:B3          MREQ    WR                 | Memory write to  085 <- B3\n#006H T6  AB:001 DB:5E          MREQ RD                    | Memory read from 001 -> 5E\n#007H T7  AB:001 DB:5E          MREQ RD                    | Memory read from 001 -> 5E\n#023H T8  AB:084 DB:A2          MREQ    WR                 | Memory write to  084 <- A2\n#026H T11 AB:083 DB:B3          MREQ    WR                 | Memory write to  083 <- B3\n#006H T6  AB:001 DB:5F          MREQ RD                    | Memory read from 001 -> 5F\n#007H T7  AB:001 DB:5F          MREQ RD                    | Memory read from 001 -> 5F\n#023H T8  AB:082 DB:A1          MREQ    WR                 | Memory write to  082 <- A1\n#026H T11 AB:081 DB:B3          MREQ    WR                 | Memory write to  081 <- B3\n#006H T6  AB:001 DB:60          MREQ RD                    | Memory read from 001 -> 60\n#007H T7  AB:001 DB:60          MREQ RD                    | Memory read from 001 -> 60\n#023H T8  AB:080 DB:A0          MREQ    WR                 | Memory write to  080 <- A0\n#026H T11 AB:07F DB:A3          MREQ    WR                 | Memory write to  07F <- A3\n#006H T6  AB:001 DB:61          MREQ RD                    | Memory read from 001 -> 61\n#007H T7  AB:001 DB:61          MREQ RD                    | Memory read from 001 -> 61\n#023H T8  AB:07E DB:9F          MREQ    WR                 | Memory write to  07E <- 9F\n#026H T11 AB:07D DB:9B          MREQ    WR                 | Memory write to  07D <- 9B\n#006H T6  AB:001 DB:62          MREQ RD                    | Memory read from 001 -> 62\n#007H T7  AB:001 DB:62          MREQ RD                    | Memory read from 001 -> 62\n#023H T8  AB:07C DB:9E          MREQ    WR                 | Memory write to  07C <- 9E\n#026H T11 AB:07B DB:9B          MREQ    WR                 | Memory write to  07B <- 9B\n#006H T6  AB:001 DB:63          MREQ RD                    | Memory read from 001 -> 63\n#007H T7  AB:001 DB:63          MREQ RD                    | Memory read from 001 -> 63\n#023H T8  AB:07A DB:9D          MREQ    WR                 | Memory write to  07A <- 9D\n#026H T11 AB:079 DB:9B          MREQ    WR                 | Memory write to  079 <- 9B\n#006H T6  AB:001 DB:64          MREQ RD                    | Memory read from 001 -> 64\n#007H T7  AB:001 DB:64          MREQ RD                    | Memory read from 001 -> 64\n#023H T8  AB:078 DB:9C          MREQ    WR                 | Memory write to  078 <- 9C\n#026H T11 AB:077 DB:9B          MREQ    WR                 | Memory write to  077 <- 9B\n#006H T6  AB:001 DB:65          MREQ RD                    | Memory read from 001 -> 65\n#007H T7  AB:001 DB:65          MREQ RD                    | Memory read from 001 -> 65\n#023H T8  AB:076 DB:9B          MREQ    WR                 | Memory write to  076 <- 9B\n#026H T11 AB:075 DB:9B          MREQ    WR                 | Memory write to  075 <- 9B\n#006H T6  AB:001 DB:66          MREQ RD                    | Memory read from 001 -> 66\n#007H T7  AB:001 DB:66          MREQ RD                    | Memory read from 001 -> 66\n#023H T8  AB:074 DB:9A          MREQ    WR                 | Memory write to  074 <- 9A\n#026H T11 AB:073 DB:9B          MREQ    WR                 | Memory write to  073 <- 9B\n#006H T6  AB:001 DB:67          MREQ RD                    | Memory read from 001 -> 67\n#007H T7  AB:001 DB:67          MREQ RD                    | Memory read from 001 -> 67\n#023H T8  AB:072 DB:99          MREQ    WR                 | Memory write to  072 <- 99\n#026H T11 AB:071 DB:9B          MREQ    WR                 | Memory write to  071 <- 9B\n#006H T6  AB:001 DB:68          MREQ RD                    | Memory read from 001 -> 68\n#007H T7  AB:001 DB:68          MREQ RD                    | Memory read from 001 -> 68\n#023H T8  AB:070 DB:98          MREQ    WR                 | Memory write to  070 <- 98\n#026H T11 AB:06F DB:9B          MREQ    WR                 | Memory write to  06F <- 9B\n#006H T6  AB:001 DB:69          MREQ RD                    | Memory read from 001 -> 69\n#007H T7  AB:001 DB:69          MREQ RD                    | Memory read from 001 -> 69\n#023H T8  AB:06E DB:97          MREQ    WR                 | Memory write to  06E <- 97\n#026H T11 AB:06D DB:93          MREQ    WR                 | Memory write to  06D <- 93\n#006H T6  AB:001 DB:6A          MREQ RD                    | Memory read from 001 -> 6A\n#007H T7  AB:001 DB:6A          MREQ RD                    | Memory read from 001 -> 6A\n#023H T8  AB:06C DB:96          MREQ    WR                 | Memory write to  06C <- 96\n#026H T11 AB:06B DB:93          MREQ    WR                 | Memory write to  06B <- 93\n#006H T6  AB:001 DB:6B          MREQ RD                    | Memory read from 001 -> 6B\n#007H T7  AB:001 DB:6B          MREQ RD                    | Memory read from 001 -> 6B\n#023H T8  AB:06A DB:95          MREQ    WR                 | Memory write to  06A <- 95\n#026H T11 AB:069 DB:93          MREQ    WR                 | Memory write to  069 <- 93\n#006H T6  AB:001 DB:6C          MREQ RD                    | Memory read from 001 -> 6C\n#007H T7  AB:001 DB:6C          MREQ RD                    | Memory read from 001 -> 6C\n#023H T8  AB:068 DB:94          MREQ    WR                 | Memory write to  068 <- 94\n#026H T11 AB:067 DB:93          MREQ    WR                 | Memory write to  067 <- 93\n#006H T6  AB:001 DB:6D          MREQ RD                    | Memory read from 001 -> 6D\n#007H T7  AB:001 DB:6D          MREQ RD                    | Memory read from 001 -> 6D\n#023H T8  AB:066 DB:93          MREQ    WR                 | Memory write to  066 <- 93\n#026H T11 AB:065 DB:93          MREQ    WR                 | Memory write to  065 <- 93\n#006H T6  AB:001 DB:6E          MREQ RD                    | Memory read from 001 -> 6E\n#007H T7  AB:001 DB:6E          MREQ RD                    | Memory read from 001 -> 6E\n#023H T8  AB:064 DB:92          MREQ    WR                 | Memory write to  064 <- 92\n#026H T11 AB:063 DB:93          MREQ    WR                 | Memory write to  063 <- 93\n#006H T6  AB:001 DB:6F          MREQ RD                    | Memory read from 001 -> 6F\n#007H T7  AB:001 DB:6F          MREQ RD                    | Memory read from 001 -> 6F\n#023H T8  AB:062 DB:91          MREQ    WR                 | Memory write to  062 <- 91\n#026H T11 AB:061 DB:93          MREQ    WR                 | Memory write to  061 <- 93\n#006H T6  AB:001 DB:70          MREQ RD                    | Memory read from 001 -> 70\n#007H T7  AB:001 DB:70          MREQ RD                    | Memory read from 001 -> 70\n#023H T8  AB:060 DB:90          MREQ    WR                 | Memory write to  060 <- 90\n#026H T11 AB:05F DB:83          MREQ    WR                 | Memory write to  05F <- 83\n#006H T6  AB:001 DB:71          MREQ RD                    | Memory read from 001 -> 71\n#007H T7  AB:001 DB:71          MREQ RD                    | Memory read from 001 -> 71\n#023H T8  AB:05E DB:8F          MREQ    WR                 | Memory write to  05E <- 8F\n#026H T11 AB:05D DB:9B          MREQ    WR                 | Memory write to  05D <- 9B\n#006H T6  AB:001 DB:72          MREQ RD                    | Memory read from 001 -> 72\n#007H T7  AB:001 DB:72          MREQ RD                    | Memory read from 001 -> 72\n#023H T8  AB:05C DB:8E          MREQ    WR                 | Memory write to  05C <- 8E\n#026H T11 AB:05B DB:9B          MREQ    WR                 | Memory write to  05B <- 9B\n#006H T6  AB:001 DB:73          MREQ RD                    | Memory read from 001 -> 73\n#007H T7  AB:001 DB:73          MREQ RD                    | Memory read from 001 -> 73\n#023H T8  AB:05A DB:8D          MREQ    WR                 | Memory write to  05A <- 8D\n#026H T11 AB:059 DB:9B          MREQ    WR                 | Memory write to  059 <- 9B\n#006H T6  AB:001 DB:74          MREQ RD                    | Memory read from 001 -> 74\n#007H T7  AB:001 DB:74          MREQ RD                    | Memory read from 001 -> 74\n#023H T8  AB:058 DB:8C          MREQ    WR                 | Memory write to  058 <- 8C\n#026H T11 AB:057 DB:9B          MREQ    WR                 | Memory write to  057 <- 9B\n#006H T6  AB:001 DB:75          MREQ RD                    | Memory read from 001 -> 75\n#007H T7  AB:001 DB:75          MREQ RD                    | Memory read from 001 -> 75\n#023H T8  AB:056 DB:8B          MREQ    WR                 | Memory write to  056 <- 8B\n#026H T11 AB:055 DB:9B          MREQ    WR                 | Memory write to  055 <- 9B\n#006H T6  AB:001 DB:76          MREQ RD                    | Memory read from 001 -> 76\n#007H T7  AB:001 DB:76          MREQ RD                    | Memory read from 001 -> 76\n#023H T8  AB:054 DB:8A          MREQ    WR                 | Memory write to  054 <- 8A\n#026H T11 AB:053 DB:9B          MREQ    WR                 | Memory write to  053 <- 9B\n#006H T6  AB:001 DB:77          MREQ RD                    | Memory read from 001 -> 77\n#007H T7  AB:001 DB:77          MREQ RD                    | Memory read from 001 -> 77\n#023H T8  AB:052 DB:89          MREQ    WR                 | Memory write to  052 <- 89\n#026H T11 AB:051 DB:9B          MREQ    WR                 | Memory write to  051 <- 9B\n#006H T6  AB:001 DB:78          MREQ RD                    | Memory read from 001 -> 78\n#007H T7  AB:001 DB:78          MREQ RD                    | Memory read from 001 -> 78\n#023H T8  AB:050 DB:88          MREQ    WR                 | Memory write to  050 <- 88\n#026H T11 AB:04F DB:9B          MREQ    WR                 | Memory write to  04F <- 9B\n#006H T6  AB:001 DB:79          MREQ RD                    | Memory read from 001 -> 79\n#007H T7  AB:001 DB:79          MREQ RD                    | Memory read from 001 -> 79\n#023H T8  AB:04E DB:87          MREQ    WR                 | Memory write to  04E <- 87\n#026H T11 AB:04D DB:93          MREQ    WR                 | Memory write to  04D <- 93\n#006H T6  AB:001 DB:7A          MREQ RD                    | Memory read from 001 -> 7A\n#007H T7  AB:001 DB:7A          MREQ RD                    | Memory read from 001 -> 7A\n#023H T8  AB:04C DB:86          MREQ    WR                 | Memory write to  04C <- 86\n#026H T11 AB:04B DB:93          MREQ    WR                 | Memory write to  04B <- 93\n#006H T6  AB:001 DB:7B          MREQ RD                    | Memory read from 001 -> 7B\n#007H T7  AB:001 DB:7B          MREQ RD                    | Memory read from 001 -> 7B\n#023H T8  AB:04A DB:85          MREQ    WR                 | Memory write to  04A <- 85\n#026H T11 AB:049 DB:93          MREQ    WR                 | Memory write to  049 <- 93\n#006H T6  AB:001 DB:7C          MREQ RD                    | Memory read from 001 -> 7C\n#007H T7  AB:001 DB:7C          MREQ RD                    | Memory read from 001 -> 7C\n#023H T8  AB:048 DB:84          MREQ    WR                 | Memory write to  048 <- 84\n#026H T11 AB:047 DB:93          MREQ    WR                 | Memory write to  047 <- 93\n#006H T6  AB:001 DB:7D          MREQ RD                    | Memory read from 001 -> 7D\n#007H T7  AB:001 DB:7D          MREQ RD                    | Memory read from 001 -> 7D\n#023H T8  AB:046 DB:83          MREQ    WR                 | Memory write to  046 <- 83\n#026H T11 AB:045 DB:93          MREQ    WR                 | Memory write to  045 <- 93\n#006H T6  AB:001 DB:7E          MREQ RD                    | Memory read from 001 -> 7E\n#007H T7  AB:001 DB:7E          MREQ RD                    | Memory read from 001 -> 7E\n#023H T8  AB:044 DB:82          MREQ    WR                 | Memory write to  044 <- 82\n#026H T11 AB:043 DB:93          MREQ    WR                 | Memory write to  043 <- 93\n#006H T6  AB:001 DB:7F          MREQ RD                    | Memory read from 001 -> 7F\n#007H T7  AB:001 DB:7F          MREQ RD                    | Memory read from 001 -> 7F\n#023H T8  AB:042 DB:81          MREQ    WR                 | Memory write to  042 <- 81\n#026H T11 AB:041 DB:93          MREQ    WR                 | Memory write to  041 <- 93\n#006H T6  AB:001 DB:80          MREQ RD                    | Memory read from 001 -> 80\n#007H T7  AB:001 DB:80          MREQ RD                    | Memory read from 001 -> 80\n#023H T8  AB:040 DB:80          MREQ    WR                 | Memory write to  040 <- 80\n#026H T11 AB:03F DB:87          MREQ    WR                 | Memory write to  03F <- 87\n#006H T6  AB:001 DB:81          MREQ RD                    | Memory read from 001 -> 81\n#007H T7  AB:001 DB:81          MREQ RD                    | Memory read from 001 -> 81\n#023H T8  AB:03E DB:7F          MREQ    WR                 | Memory write to  03E <- 7F\n#026H T11 AB:03D DB:3B          MREQ    WR                 | Memory write to  03D <- 3B\n#006H T6  AB:001 DB:82          MREQ RD                    | Memory read from 001 -> 82\n#007H T7  AB:001 DB:82          MREQ RD                    | Memory read from 001 -> 82\n#023H T8  AB:03C DB:7E          MREQ    WR                 | Memory write to  03C <- 7E\n#026H T11 AB:03B DB:3B          MREQ    WR                 | Memory write to  03B <- 3B\n#006H T6  AB:001 DB:83          MREQ RD                    | Memory read from 001 -> 83\n#007H T7  AB:001 DB:83          MREQ RD                    | Memory read from 001 -> 83\n#023H T8  AB:03A DB:7D          MREQ    WR                 | Memory write to  03A <- 7D\n#026H T11 AB:039 DB:3B          MREQ    WR                 | Memory write to  039 <- 3B\n#006H T6  AB:001 DB:84          MREQ RD                    | Memory read from 001 -> 84\n#007H T7  AB:001 DB:84          MREQ RD                    | Memory read from 001 -> 84\n#023H T8  AB:038 DB:7C          MREQ    WR                 | Memory write to  038 <- 7C\n#026H T11 AB:037 DB:3B          MREQ    WR                 | Memory write to  037 <- 3B\n#006H T6  AB:001 DB:85          MREQ RD                    | Memory read from 001 -> 85\n#007H T7  AB:001 DB:85          MREQ RD                    | Memory read from 001 -> 85\n#023H T8  AB:036 DB:7B          MREQ    WR                 | Memory write to  036 <- 7B\n#026H T11 AB:035 DB:3B          MREQ    WR                 | Memory write to  035 <- 3B\n#006H T6  AB:001 DB:86          MREQ RD                    | Memory read from 001 -> 86\n#007H T7  AB:001 DB:86          MREQ RD                    | Memory read from 001 -> 86\n#023H T8  AB:034 DB:7A          MREQ    WR                 | Memory write to  034 <- 7A\n#026H T11 AB:033 DB:3B          MREQ    WR                 | Memory write to  033 <- 3B\n#006H T6  AB:001 DB:87          MREQ RD                    | Memory read from 001 -> 87\n#007H T7  AB:001 DB:87          MREQ RD                    | Memory read from 001 -> 87\n#023H T8  AB:032 DB:79          MREQ    WR                 | Memory write to  032 <- 79\n#026H T11 AB:031 DB:3B          MREQ    WR                 | Memory write to  031 <- 3B\n#006H T6  AB:001 DB:88          MREQ RD                    | Memory read from 001 -> 88\n#007H T7  AB:001 DB:88          MREQ RD                    | Memory read from 001 -> 88\n#023H T8  AB:030 DB:78          MREQ    WR                 | Memory write to  030 <- 78\n#026H T11 AB:02F DB:3B          MREQ    WR                 | Memory write to  02F <- 3B\n#006H T6  AB:001 DB:89          MREQ RD                    | Memory read from 001 -> 89\n#007H T7  AB:001 DB:89          MREQ RD                    | Memory read from 001 -> 89\n#023H T8  AB:02E DB:77          MREQ    WR                 | Memory write to  02E <- 77\n#026H T11 AB:02D DB:33          MREQ    WR                 | Memory write to  02D <- 33\n#006H T6  AB:001 DB:8A          MREQ RD                    | Memory read from 001 -> 8A\n#007H T7  AB:001 DB:8A          MREQ RD                    | Memory read from 001 -> 8A\n#023H T8  AB:02C DB:76          MREQ    WR                 | Memory write to  02C <- 76\n#026H T11 AB:02B DB:33          MREQ    WR                 | Memory write to  02B <- 33\n#006H T6  AB:001 DB:8B          MREQ RD                    | Memory read from 001 -> 8B\n#007H T7  AB:001 DB:8B          MREQ RD                    | Memory read from 001 -> 8B\n#023H T8  AB:02A DB:75          MREQ    WR                 | Memory write to  02A <- 75\n#026H T11 AB:029 DB:33          MREQ    WR                 | Memory write to  029 <- 33\n#006H T6  AB:001 DB:8C          MREQ RD                    | Memory read from 001 -> 8C\n#007H T7  AB:001 DB:8C          MREQ RD                    | Memory read from 001 -> 8C\n#023H T8  AB:028 DB:74          MREQ    WR                 | Memory write to  028 <- 74\n#026H T11 AB:027 DB:33          MREQ    WR                 | Memory write to  027 <- 33\n#006H T6  AB:001 DB:8D          MREQ RD                    | Memory read from 001 -> 8D\n#007H T7  AB:001 DB:8D          MREQ RD                    | Memory read from 001 -> 8D\n#023H T8  AB:026 DB:73          MREQ    WR                 | Memory write to  026 <- 73\n#026H T11 AB:025 DB:33          MREQ    WR                 | Memory write to  025 <- 33\n#006H T6  AB:001 DB:8E          MREQ RD                    | Memory read from 001 -> 8E\n#007H T7  AB:001 DB:8E          MREQ RD                    | Memory read from 001 -> 8E\n#023H T8  AB:024 DB:72          MREQ    WR                 | Memory write to  024 <- 72\n#026H T11 AB:023 DB:33          MREQ    WR                 | Memory write to  023 <- 33\n#006H T6  AB:001 DB:8F          MREQ RD                    | Memory read from 001 -> 8F\n#007H T7  AB:001 DB:8F          MREQ RD                    | Memory read from 001 -> 8F\n#023H T8  AB:022 DB:71          MREQ    WR                 | Memory write to  022 <- 71\n#026H T11 AB:021 DB:33          MREQ    WR                 | Memory write to  021 <- 33\n#006H T6  AB:001 DB:90          MREQ RD                    | Memory read from 001 -> 90\n#007H T7  AB:001 DB:90          MREQ RD                    | Memory read from 001 -> 90\n#023H T8  AB:020 DB:70          MREQ    WR                 | Memory write to  020 <- 70\n#026H T11 AB:01F DB:23          MREQ    WR                 | Memory write to  01F <- 23\n#006H T6  AB:001 DB:91          MREQ RD                    | Memory read from 001 -> 91\n#007H T7  AB:001 DB:91          MREQ RD                    | Memory read from 001 -> 91\n#023H T8  AB:01E DB:6F          MREQ    WR                 | Memory write to  01E <- 6F\n#026H T11 AB:01D DB:3B          MREQ    WR                 | Memory write to  01D <- 3B\n#006H T6  AB:001 DB:92          MREQ RD                    | Memory read from 001 -> 92\n#007H T7  AB:001 DB:92          MREQ RD                    | Memory read from 001 -> 92\n#023H T8  AB:01C DB:6E          MREQ    WR                 | Memory write to  01C <- 6E\n#026H T11 AB:01B DB:3B          MREQ    WR                 | Memory write to  01B <- 3B\n#006H T6  AB:001 DB:93          MREQ RD                    | Memory read from 001 -> 93\n#007H T7  AB:001 DB:93          MREQ RD                    | Memory read from 001 -> 93\n#023H T8  AB:01A DB:6D          MREQ    WR                 | Memory write to  01A <- 6D\n#026H T11 AB:019 DB:3B          MREQ    WR                 | Memory write to  019 <- 3B\n#006H T6  AB:001 DB:94          MREQ RD                    | Memory read from 001 -> 94\n#007H T7  AB:001 DB:94          MREQ RD                    | Memory read from 001 -> 94\n#023H T8  AB:018 DB:6C          MREQ    WR                 | Memory write to  018 <- 6C\n#026H T11 AB:017 DB:3B          MREQ    WR                 | Memory write to  017 <- 3B\n#006H T6  AB:001 DB:95          MREQ RD                    | Memory read from 001 -> 95\n#007H T7  AB:001 DB:95          MREQ RD                    | Memory read from 001 -> 95\n#023H T8  AB:016 DB:6B          MREQ    WR                 | Memory write to  016 <- 6B\n#026H T11 AB:015 DB:3B          MREQ    WR                 | Memory write to  015 <- 3B\n#006H T6  AB:001 DB:96          MREQ RD                    | Memory read from 001 -> 96\n#007H T7  AB:001 DB:96          MREQ RD                    | Memory read from 001 -> 96\n#023H T8  AB:014 DB:6A          MREQ    WR                 | Memory write to  014 <- 6A\n#026H T11 AB:013 DB:3B          MREQ    WR                 | Memory write to  013 <- 3B\n#006H T6  AB:001 DB:97          MREQ RD                    | Memory read from 001 -> 97\n#007H T7  AB:001 DB:97          MREQ RD                    | Memory read from 001 -> 97\n#023H T8  AB:012 DB:69          MREQ    WR                 | Memory write to  012 <- 69\n#026H T11 AB:011 DB:3B          MREQ    WR                 | Memory write to  011 <- 3B\n#006H T6  AB:001 DB:98          MREQ RD                    | Memory read from 001 -> 98\n#007H T7  AB:001 DB:98          MREQ RD                    | Memory read from 001 -> 98\n#023H T8  AB:010 DB:68          MREQ    WR                 | Memory write to  010 <- 68\n#026H T11 AB:00F DB:3B          MREQ    WR                 | Memory write to  00F <- 3B\n#006H T6  AB:001 DB:99          MREQ RD                    | Memory read from 001 -> 99\n#007H T7  AB:001 DB:99          MREQ RD                    | Memory read from 001 -> 99\n#023H T8  AB:00E DB:67          MREQ    WR                 | Memory write to  00E <- 67\n#026H T11 AB:00D DB:33          MREQ    WR                 | Memory write to  00D <- 33\n#006H T6  AB:001 DB:9A          MREQ RD                    | Memory read from 001 -> 9A\n#007H T7  AB:001 DB:9A          MREQ RD                    | Memory read from 001 -> 9A\n#023H T8  AB:00C DB:66          MREQ    WR                 | Memory write to  00C <- 66\n#026H T11 AB:00B DB:33          MREQ    WR                 | Memory write to  00B <- 33\n#006H T6  AB:001 DB:9B          MREQ RD                    | Memory read from 001 -> 9B\n#007H T7  AB:001 DB:9B          MREQ RD                    | Memory read from 001 -> 9B\n#023H T8  AB:00A DB:65          MREQ    WR                 | Memory write to  00A <- 65\n#026H T11 AB:009 DB:33          MREQ    WR                 | Memory write to  009 <- 33\n#006H T6  AB:001 DB:9C          MREQ RD                    | Memory read from 001 -> 9C\n#007H T7  AB:001 DB:9C          MREQ RD                    | Memory read from 001 -> 9C\n#023H T8  AB:008 DB:64          MREQ    WR                 | Memory write to  008 <- 64\n#026H T11 AB:007 DB:33          MREQ    WR                 | Memory write to  007 <- 33\n#006H T6  AB:001 DB:9D          MREQ RD                    | Memory read from 001 -> 9D\n#007H T7  AB:001 DB:9D          MREQ RD                    | Memory read from 001 -> 9D\n#023H T8  AB:006 DB:63          MREQ    WR                 | Memory write to  006 <- 63\n#026H T11 AB:005 DB:33          MREQ    WR                 | Memory write to  005 <- 33\n#006H T6  AB:001 DB:9E          MREQ RD                    | Memory read from 001 -> 9E\n#007H T7  AB:001 DB:9E          MREQ RD                    | Memory read from 001 -> 9E\n#023H T8  AB:004 DB:62          MREQ    WR                 | Memory write to  004 <- 62\n#026H T11 AB:003 DB:33          MREQ    WR                 | Memory write to  003 <- 33\n#006H T6  AB:001 DB:9F          MREQ RD                    | Memory read from 001 -> 9F\n#007H T7  AB:001 DB:9F          MREQ RD                    | Memory read from 001 -> 9F\n#023H T8  AB:002 DB:61          MREQ    WR                 | Memory write to  002 <- 61\n#026H T11 AB:001 DB:33          MREQ    WR                 | Memory write to  001 <- 33\n#006H T6  AB:001 DB:A0          MREQ RD                    | Memory read from 001 -> A0\n#007H T7  AB:001 DB:A0          MREQ RD                    | Memory read from 001 -> A0\n#023H T8  AB:000 DB:60          MREQ    WR                 | Memory write to  000 <- 60\n#026H T11 AB:0FF DB:23          MREQ    WR                 | Memory write to  0FF <- 23\n#006H T6  AB:001 DB:A1          MREQ RD                    | Memory read from 001 -> A1\n#007H T7  AB:001 DB:A1          MREQ RD                    | Memory read from 001 -> A1\n#023H T8  AB:0FE DB:5F          MREQ    WR                 | Memory write to  0FE <- 5F\n#026H T11 AB:0FD DB:1B          MREQ    WR                 | Memory write to  0FD <- 1B\n#006H T6  AB:001 DB:A2          MREQ RD                    | Memory read from 001 -> A2\n#007H T7  AB:001 DB:A2          MREQ RD                    | Memory read from 001 -> A2\n#023H T8  AB:0FC DB:5E          MREQ    WR                 | Memory write to  0FC <- 5E\n#026H T11 AB:0FB DB:1B          MREQ    WR                 | Memory write to  0FB <- 1B\n#006H T6  AB:001 DB:A3          MREQ RD                    | Memory read from 001 -> A3\n#007H T7  AB:001 DB:A3          MREQ RD                    | Memory read from 001 -> A3\n#023H T8  AB:0FA DB:5D          MREQ    WR                 | Memory write to  0FA <- 5D\n#026H T11 AB:0F9 DB:1B          MREQ    WR                 | Memory write to  0F9 <- 1B\n#006H T6  AB:001 DB:A4          MREQ RD                    | Memory read from 001 -> A4\n#007H T7  AB:001 DB:A4          MREQ RD                    | Memory read from 001 -> A4\n#023H T8  AB:0F8 DB:5C          MREQ    WR                 | Memory write to  0F8 <- 5C\n#026H T11 AB:0F7 DB:1B          MREQ    WR                 | Memory write to  0F7 <- 1B\n#006H T6  AB:001 DB:A5          MREQ RD                    | Memory read from 001 -> A5\n#007H T7  AB:001 DB:A5          MREQ RD                    | Memory read from 001 -> A5\n#023H T8  AB:0F6 DB:5B          MREQ    WR                 | Memory write to  0F6 <- 5B\n#026H T11 AB:0F5 DB:1B          MREQ    WR                 | Memory write to  0F5 <- 1B\n#006H T6  AB:001 DB:A6          MREQ RD                    | Memory read from 001 -> A6\n#007H T7  AB:001 DB:A6          MREQ RD                    | Memory read from 001 -> A6\n#023H T8  AB:0F4 DB:5A          MREQ    WR                 | Memory write to  0F4 <- 5A\n#026H T11 AB:0F3 DB:1B          MREQ    WR                 | Memory write to  0F3 <- 1B\n#006H T6  AB:001 DB:A7          MREQ RD                    | Memory read from 001 -> A7\n#007H T7  AB:001 DB:A7          MREQ RD                    | Memory read from 001 -> A7\n#023H T8  AB:0F2 DB:59          MREQ    WR                 | Memory write to  0F2 <- 59\n#026H T11 AB:0F1 DB:1B          MREQ    WR                 | Memory write to  0F1 <- 1B\n#006H T6  AB:001 DB:A8          MREQ RD                    | Memory read from 001 -> A8\n#007H T7  AB:001 DB:A8          MREQ RD                    | Memory read from 001 -> A8\n#023H T8  AB:0F0 DB:58          MREQ    WR                 | Memory write to  0F0 <- 58\n#026H T11 AB:0EF DB:1B          MREQ    WR                 | Memory write to  0EF <- 1B\n#006H T6  AB:001 DB:A9          MREQ RD                    | Memory read from 001 -> A9\n#007H T7  AB:001 DB:A9          MREQ RD                    | Memory read from 001 -> A9\n#023H T8  AB:0EE DB:57          MREQ    WR                 | Memory write to  0EE <- 57\n#026H T11 AB:0ED DB:13          MREQ    WR                 | Memory write to  0ED <- 13\n#006H T6  AB:001 DB:AA          MREQ RD                    | Memory read from 001 -> AA\n#007H T7  AB:001 DB:AA          MREQ RD                    | Memory read from 001 -> AA\n#023H T8  AB:0EC DB:56          MREQ    WR                 | Memory write to  0EC <- 56\n#026H T11 AB:0EB DB:13          MREQ    WR                 | Memory write to  0EB <- 13\n#006H T6  AB:001 DB:AB          MREQ RD                    | Memory read from 001 -> AB\n#007H T7  AB:001 DB:AB          MREQ RD                    | Memory read from 001 -> AB\n#023H T8  AB:0EA DB:55          MREQ    WR                 | Memory write to  0EA <- 55\n#026H T11 AB:0E9 DB:13          MREQ    WR                 | Memory write to  0E9 <- 13\n#006H T6  AB:001 DB:AC          MREQ RD                    | Memory read from 001 -> AC\n#007H T7  AB:001 DB:AC          MREQ RD                    | Memory read from 001 -> AC\n#023H T8  AB:0E8 DB:54          MREQ    WR                 | Memory write to  0E8 <- 54\n#026H T11 AB:0E7 DB:13          MREQ    WR                 | Memory write to  0E7 <- 13\n#006H T6  AB:001 DB:AD          MREQ RD                    | Memory read from 001 -> AD\n#007H T7  AB:001 DB:AD          MREQ RD                    | Memory read from 001 -> AD\n#023H T8  AB:0E6 DB:53          MREQ    WR                 | Memory write to  0E6 <- 53\n#026H T11 AB:0E5 DB:13          MREQ    WR                 | Memory write to  0E5 <- 13\n#006H T6  AB:001 DB:AE          MREQ RD                    | Memory read from 001 -> AE\n#007H T7  AB:001 DB:AE          MREQ RD                    | Memory read from 001 -> AE\n#023H T8  AB:0E4 DB:52          MREQ    WR                 | Memory write to  0E4 <- 52\n#026H T11 AB:0E3 DB:13          MREQ    WR                 | Memory write to  0E3 <- 13\n#006H T6  AB:001 DB:AF          MREQ RD                    | Memory read from 001 -> AF\n#007H T7  AB:001 DB:AF          MREQ RD                    | Memory read from 001 -> AF\n#023H T8  AB:0E2 DB:51          MREQ    WR                 | Memory write to  0E2 <- 51\n#026H T11 AB:0E1 DB:13          MREQ    WR                 | Memory write to  0E1 <- 13\n#006H T6  AB:001 DB:B0          MREQ RD                    | Memory read from 001 -> B0\n#007H T7  AB:001 DB:B0          MREQ RD                    | Memory read from 001 -> B0\n#023H T8  AB:0E0 DB:50          MREQ    WR                 | Memory write to  0E0 <- 50\n#026H T11 AB:0DF DB:03          MREQ    WR                 | Memory write to  0DF <- 03\n#006H T6  AB:001 DB:B1          MREQ RD                    | Memory read from 001 -> B1\n#007H T7  AB:001 DB:B1          MREQ RD                    | Memory read from 001 -> B1\n#023H T8  AB:0DE DB:4F          MREQ    WR                 | Memory write to  0DE <- 4F\n#026H T11 AB:0DD DB:1B          MREQ    WR                 | Memory write to  0DD <- 1B\n#006H T6  AB:001 DB:B2          MREQ RD                    | Memory read from 001 -> B2\n#007H T7  AB:001 DB:B2          MREQ RD                    | Memory read from 001 -> B2\n#023H T8  AB:0DC DB:4E          MREQ    WR                 | Memory write to  0DC <- 4E\n#026H T11 AB:0DB DB:1B          MREQ    WR                 | Memory write to  0DB <- 1B\n#006H T6  AB:001 DB:B3          MREQ RD                    | Memory read from 001 -> B3\n#007H T7  AB:001 DB:B3          MREQ RD                    | Memory read from 001 -> B3\n#023H T8  AB:0DA DB:4D          MREQ    WR                 | Memory write to  0DA <- 4D\n#026H T11 AB:0D9 DB:1B          MREQ    WR                 | Memory write to  0D9 <- 1B\n#006H T6  AB:001 DB:B4          MREQ RD                    | Memory read from 001 -> B4\n#007H T7  AB:001 DB:B4          MREQ RD                    | Memory read from 001 -> B4\n#023H T8  AB:0D8 DB:4C          MREQ    WR                 | Memory write to  0D8 <- 4C\n#026H T11 AB:0D7 DB:1B          MREQ    WR                 | Memory write to  0D7 <- 1B\n#006H T6  AB:001 DB:B5          MREQ RD                    | Memory read from 001 -> B5\n#007H T7  AB:001 DB:B5          MREQ RD                    | Memory read from 001 -> B5\n#023H T8  AB:0D6 DB:4B          MREQ    WR                 | Memory write to  0D6 <- 4B\n#026H T11 AB:0D5 DB:1B          MREQ    WR                 | Memory write to  0D5 <- 1B\n#006H T6  AB:001 DB:B6          MREQ RD                    | Memory read from 001 -> B6\n#007H T7  AB:001 DB:B6          MREQ RD                    | Memory read from 001 -> B6\n#023H T8  AB:0D4 DB:4A          MREQ    WR                 | Memory write to  0D4 <- 4A\n#026H T11 AB:0D3 DB:1B          MREQ    WR                 | Memory write to  0D3 <- 1B\n#006H T6  AB:001 DB:B7          MREQ RD                    | Memory read from 001 -> B7\n#007H T7  AB:001 DB:B7          MREQ RD                    | Memory read from 001 -> B7\n#023H T8  AB:0D2 DB:49          MREQ    WR                 | Memory write to  0D2 <- 49\n#026H T11 AB:0D1 DB:1B          MREQ    WR                 | Memory write to  0D1 <- 1B\n#006H T6  AB:001 DB:B8          MREQ RD                    | Memory read from 001 -> B8\n#007H T7  AB:001 DB:B8          MREQ RD                    | Memory read from 001 -> B8\n#023H T8  AB:0D0 DB:48          MREQ    WR                 | Memory write to  0D0 <- 48\n#026H T11 AB:0CF DB:1B          MREQ    WR                 | Memory write to  0CF <- 1B\n#006H T6  AB:001 DB:B9          MREQ RD                    | Memory read from 001 -> B9\n#007H T7  AB:001 DB:B9          MREQ RD                    | Memory read from 001 -> B9\n#023H T8  AB:0CE DB:47          MREQ    WR                 | Memory write to  0CE <- 47\n#026H T11 AB:0CD DB:13          MREQ    WR                 | Memory write to  0CD <- 13\n#006H T6  AB:001 DB:BA          MREQ RD                    | Memory read from 001 -> BA\n#007H T7  AB:001 DB:BA          MREQ RD                    | Memory read from 001 -> BA\n#023H T8  AB:0CC DB:46          MREQ    WR                 | Memory write to  0CC <- 46\n#026H T11 AB:0CB DB:13          MREQ    WR                 | Memory write to  0CB <- 13\n#006H T6  AB:001 DB:BB          MREQ RD                    | Memory read from 001 -> BB\n#007H T7  AB:001 DB:BB          MREQ RD                    | Memory read from 001 -> BB\n#023H T8  AB:0CA DB:45          MREQ    WR                 | Memory write to  0CA <- 45\n#026H T11 AB:0C9 DB:13          MREQ    WR                 | Memory write to  0C9 <- 13\n#006H T6  AB:001 DB:BC          MREQ RD                    | Memory read from 001 -> BC\n#007H T7  AB:001 DB:BC          MREQ RD                    | Memory read from 001 -> BC\n#023H T8  AB:0C8 DB:44          MREQ    WR                 | Memory write to  0C8 <- 44\n#026H T11 AB:0C7 DB:13          MREQ    WR                 | Memory write to  0C7 <- 13\n#006H T6  AB:001 DB:BD          MREQ RD                    | Memory read from 001 -> BD\n#007H T7  AB:001 DB:BD          MREQ RD                    | Memory read from 001 -> BD\n#023H T8  AB:0C6 DB:43          MREQ    WR                 | Memory write to  0C6 <- 43\n#026H T11 AB:0C5 DB:13          MREQ    WR                 | Memory write to  0C5 <- 13\n#006H T6  AB:001 DB:BE          MREQ RD                    | Memory read from 001 -> BE\n#007H T7  AB:001 DB:BE          MREQ RD                    | Memory read from 001 -> BE\n#023H T8  AB:0C4 DB:42          MREQ    WR                 | Memory write to  0C4 <- 42\n#026H T11 AB:0C3 DB:13          MREQ    WR                 | Memory write to  0C3 <- 13\n#006H T6  AB:001 DB:BF          MREQ RD                    | Memory read from 001 -> BF\n#007H T7  AB:001 DB:BF          MREQ RD                    | Memory read from 001 -> BF\n#023H T8  AB:0C2 DB:41          MREQ    WR                 | Memory write to  0C2 <- 41\n#026H T11 AB:0C1 DB:13          MREQ    WR                 | Memory write to  0C1 <- 13\n#006H T6  AB:001 DB:C0          MREQ RD                    | Memory read from 001 -> C0\n#007H T7  AB:001 DB:C0          MREQ RD                    | Memory read from 001 -> C0\n#023H T8  AB:0C0 DB:40          MREQ    WR                 | Memory write to  0C0 <- 40\n#026H T11 AB:0BF DB:03          MREQ    WR                 | Memory write to  0BF <- 03\n#006H T6  AB:001 DB:C1          MREQ RD                    | Memory read from 001 -> C1\n#007H T7  AB:001 DB:C1          MREQ RD                    | Memory read from 001 -> C1\n#023H T8  AB:0BE DB:3F          MREQ    WR                 | Memory write to  0BE <- 3F\n#026H T11 AB:0BD DB:3B          MREQ    WR                 | Memory write to  0BD <- 3B\n#006H T6  AB:001 DB:C2          MREQ RD                    | Memory read from 001 -> C2\n#007H T7  AB:001 DB:C2          MREQ RD                    | Memory read from 001 -> C2\n#023H T8  AB:0BC DB:3E          MREQ    WR                 | Memory write to  0BC <- 3E\n#026H T11 AB:0BB DB:3B          MREQ    WR                 | Memory write to  0BB <- 3B\n#006H T6  AB:001 DB:C3          MREQ RD                    | Memory read from 001 -> C3\n#007H T7  AB:001 DB:C3          MREQ RD                    | Memory read from 001 -> C3\n#023H T8  AB:0BA DB:3D          MREQ    WR                 | Memory write to  0BA <- 3D\n#026H T11 AB:0B9 DB:3B          MREQ    WR                 | Memory write to  0B9 <- 3B\n#006H T6  AB:001 DB:C4          MREQ RD                    | Memory read from 001 -> C4\n#007H T7  AB:001 DB:C4          MREQ RD                    | Memory read from 001 -> C4\n#023H T8  AB:0B8 DB:3C          MREQ    WR                 | Memory write to  0B8 <- 3C\n#026H T11 AB:0B7 DB:3B          MREQ    WR                 | Memory write to  0B7 <- 3B\n#006H T6  AB:001 DB:C5          MREQ RD                    | Memory read from 001 -> C5\n#007H T7  AB:001 DB:C5          MREQ RD                    | Memory read from 001 -> C5\n#023H T8  AB:0B6 DB:3B          MREQ    WR                 | Memory write to  0B6 <- 3B\n#026H T11 AB:0B5 DB:3B          MREQ    WR                 | Memory write to  0B5 <- 3B\n#006H T6  AB:001 DB:C6          MREQ RD                    | Memory read from 001 -> C6\n#007H T7  AB:001 DB:C6          MREQ RD                    | Memory read from 001 -> C6\n#023H T8  AB:0B4 DB:3A          MREQ    WR                 | Memory write to  0B4 <- 3A\n#026H T11 AB:0B3 DB:3B          MREQ    WR                 | Memory write to  0B3 <- 3B\n#006H T6  AB:001 DB:C7          MREQ RD                    | Memory read from 001 -> C7\n#007H T7  AB:001 DB:C7          MREQ RD                    | Memory read from 001 -> C7\n#023H T8  AB:0B2 DB:39          MREQ    WR                 | Memory write to  0B2 <- 39\n#026H T11 AB:0B1 DB:3B          MREQ    WR                 | Memory write to  0B1 <- 3B\n#006H T6  AB:001 DB:C8          MREQ RD                    | Memory read from 001 -> C8\n#007H T7  AB:001 DB:C8          MREQ RD                    | Memory read from 001 -> C8\n#023H T8  AB:0B0 DB:38          MREQ    WR                 | Memory write to  0B0 <- 38\n#026H T11 AB:0AF DB:3B          MREQ    WR                 | Memory write to  0AF <- 3B\n#006H T6  AB:001 DB:C9          MREQ RD                    | Memory read from 001 -> C9\n#007H T7  AB:001 DB:C9          MREQ RD                    | Memory read from 001 -> C9\n#023H T8  AB:0AE DB:37          MREQ    WR                 | Memory write to  0AE <- 37\n#026H T11 AB:0AD DB:33          MREQ    WR                 | Memory write to  0AD <- 33\n#006H T6  AB:001 DB:CA          MREQ RD                    | Memory read from 001 -> CA\n#007H T7  AB:001 DB:CA          MREQ RD                    | Memory read from 001 -> CA\n#023H T8  AB:0AC DB:36          MREQ    WR                 | Memory write to  0AC <- 36\n#026H T11 AB:0AB DB:33          MREQ    WR                 | Memory write to  0AB <- 33\n#006H T6  AB:001 DB:CB          MREQ RD                    | Memory read from 001 -> CB\n#007H T7  AB:001 DB:CB          MREQ RD                    | Memory read from 001 -> CB\n#023H T8  AB:0AA DB:35          MREQ    WR                 | Memory write to  0AA <- 35\n#026H T11 AB:0A9 DB:33          MREQ    WR                 | Memory write to  0A9 <- 33\n#006H T6  AB:001 DB:CC          MREQ RD                    | Memory read from 001 -> CC\n#007H T7  AB:001 DB:CC          MREQ RD                    | Memory read from 001 -> CC\n#023H T8  AB:0A8 DB:34          MREQ    WR                 | Memory write to  0A8 <- 34\n#026H T11 AB:0A7 DB:33          MREQ    WR                 | Memory write to  0A7 <- 33\n#006H T6  AB:001 DB:CD          MREQ RD                    | Memory read from 001 -> CD\n#007H T7  AB:001 DB:CD          MREQ RD                    | Memory read from 001 -> CD\n#023H T8  AB:0A6 DB:33          MREQ    WR                 | Memory write to  0A6 <- 33\n#026H T11 AB:0A5 DB:33          MREQ    WR                 | Memory write to  0A5 <- 33\n#006H T6  AB:001 DB:CE          MREQ RD                    | Memory read from 001 -> CE\n#007H T7  AB:001 DB:CE          MREQ RD                    | Memory read from 001 -> CE\n#023H T8  AB:0A4 DB:32          MREQ    WR                 | Memory write to  0A4 <- 32\n#026H T11 AB:0A3 DB:33          MREQ    WR                 | Memory write to  0A3 <- 33\n#006H T6  AB:001 DB:CF          MREQ RD                    | Memory read from 001 -> CF\n#007H T7  AB:001 DB:CF          MREQ RD                    | Memory read from 001 -> CF\n#023H T8  AB:0A2 DB:31          MREQ    WR                 | Memory write to  0A2 <- 31\n#026H T11 AB:0A1 DB:33          MREQ    WR                 | Memory write to  0A1 <- 33\n#006H T6  AB:001 DB:D0          MREQ RD                    | Memory read from 001 -> D0\n#007H T7  AB:001 DB:D0          MREQ RD                    | Memory read from 001 -> D0\n#023H T8  AB:0A0 DB:30          MREQ    WR                 | Memory write to  0A0 <- 30\n#026H T11 AB:09F DB:23          MREQ    WR                 | Memory write to  09F <- 23\n#006H T6  AB:001 DB:D1          MREQ RD                    | Memory read from 001 -> D1\n#007H T7  AB:001 DB:D1          MREQ RD                    | Memory read from 001 -> D1\n#023H T8  AB:09E DB:2F          MREQ    WR                 | Memory write to  09E <- 2F\n#026H T11 AB:09D DB:3B          MREQ    WR                 | Memory write to  09D <- 3B\n#006H T6  AB:001 DB:D2          MREQ RD                    | Memory read from 001 -> D2\n#007H T7  AB:001 DB:D2          MREQ RD                    | Memory read from 001 -> D2\n#023H T8  AB:09C DB:2E          MREQ    WR                 | Memory write to  09C <- 2E\n#026H T11 AB:09B DB:3B          MREQ    WR                 | Memory write to  09B <- 3B\n#006H T6  AB:001 DB:D3          MREQ RD                    | Memory read from 001 -> D3\n#007H T7  AB:001 DB:D3          MREQ RD                    | Memory read from 001 -> D3\n#023H T8  AB:09A DB:2D          MREQ    WR                 | Memory write to  09A <- 2D\n#026H T11 AB:099 DB:3B          MREQ    WR                 | Memory write to  099 <- 3B\n#006H T6  AB:001 DB:D4          MREQ RD                    | Memory read from 001 -> D4\n#007H T7  AB:001 DB:D4          MREQ RD                    | Memory read from 001 -> D4\n#023H T8  AB:098 DB:2C          MREQ    WR                 | Memory write to  098 <- 2C\n#026H T11 AB:097 DB:3B          MREQ    WR                 | Memory write to  097 <- 3B\n#006H T6  AB:001 DB:D5          MREQ RD                    | Memory read from 001 -> D5\n#007H T7  AB:001 DB:D5          MREQ RD                    | Memory read from 001 -> D5\n#023H T8  AB:096 DB:2B          MREQ    WR                 | Memory write to  096 <- 2B\n#026H T11 AB:095 DB:3B          MREQ    WR                 | Memory write to  095 <- 3B\n#006H T6  AB:001 DB:D6          MREQ RD                    | Memory read from 001 -> D6\n#007H T7  AB:001 DB:D6          MREQ RD                    | Memory read from 001 -> D6\n#023H T8  AB:094 DB:2A          MREQ    WR                 | Memory write to  094 <- 2A\n#026H T11 AB:093 DB:3B          MREQ    WR                 | Memory write to  093 <- 3B\n#006H T6  AB:001 DB:D7          MREQ RD                    | Memory read from 001 -> D7\n#007H T7  AB:001 DB:D7          MREQ RD                    | Memory read from 001 -> D7\n#023H T8  AB:092 DB:29          MREQ    WR                 | Memory write to  092 <- 29\n#026H T11 AB:091 DB:3B          MREQ    WR                 | Memory write to  091 <- 3B\n#006H T6  AB:001 DB:D8          MREQ RD                    | Memory read from 001 -> D8\n#007H T7  AB:001 DB:D8          MREQ RD                    | Memory read from 001 -> D8\n#023H T8  AB:090 DB:28          MREQ    WR                 | Memory write to  090 <- 28\n#026H T11 AB:08F DB:3B          MREQ    WR                 | Memory write to  08F <- 3B\n#006H T6  AB:001 DB:D9          MREQ RD                    | Memory read from 001 -> D9\n#007H T7  AB:001 DB:D9          MREQ RD                    | Memory read from 001 -> D9\n#023H T8  AB:08E DB:27          MREQ    WR                 | Memory write to  08E <- 27\n#026H T11 AB:08D DB:33          MREQ    WR                 | Memory write to  08D <- 33\n#006H T6  AB:001 DB:DA          MREQ RD                    | Memory read from 001 -> DA\n#007H T7  AB:001 DB:DA          MREQ RD                    | Memory read from 001 -> DA\n#023H T8  AB:08C DB:26          MREQ    WR                 | Memory write to  08C <- 26\n#026H T11 AB:08B DB:33          MREQ    WR                 | Memory write to  08B <- 33\n#006H T6  AB:001 DB:DB          MREQ RD                    | Memory read from 001 -> DB\n#007H T7  AB:001 DB:DB          MREQ RD                    | Memory read from 001 -> DB\n#023H T8  AB:08A DB:25          MREQ    WR                 | Memory write to  08A <- 25\n#026H T11 AB:089 DB:33          MREQ    WR                 | Memory write to  089 <- 33\n#006H T6  AB:001 DB:DC          MREQ RD                    | Memory read from 001 -> DC\n#007H T7  AB:001 DB:DC          MREQ RD                    | Memory read from 001 -> DC\n#023H T8  AB:088 DB:24          MREQ    WR                 | Memory write to  088 <- 24\n#026H T11 AB:087 DB:33          MREQ    WR                 | Memory write to  087 <- 33\n#006H T6  AB:001 DB:DD          MREQ RD                    | Memory read from 001 -> DD\n#007H T7  AB:001 DB:DD          MREQ RD                    | Memory read from 001 -> DD\n#023H T8  AB:086 DB:23          MREQ    WR                 | Memory write to  086 <- 23\n#026H T11 AB:085 DB:33          MREQ    WR                 | Memory write to  085 <- 33\n#006H T6  AB:001 DB:DE          MREQ RD                    | Memory read from 001 -> DE\n#007H T7  AB:001 DB:DE          MREQ RD                    | Memory read from 001 -> DE\n#023H T8  AB:084 DB:22          MREQ    WR                 | Memory write to  084 <- 22\n#026H T11 AB:083 DB:33          MREQ    WR                 | Memory write to  083 <- 33\n#006H T6  AB:001 DB:DF          MREQ RD                    | Memory read from 001 -> DF\n#007H T7  AB:001 DB:DF          MREQ RD                    | Memory read from 001 -> DF\n#023H T8  AB:082 DB:21          MREQ    WR                 | Memory write to  082 <- 21\n#026H T11 AB:081 DB:33          MREQ    WR                 | Memory write to  081 <- 33\n#006H T6  AB:001 DB:E0          MREQ RD                    | Memory read from 001 -> E0\n#007H T7  AB:001 DB:E0          MREQ RD                    | Memory read from 001 -> E0\n#023H T8  AB:080 DB:20          MREQ    WR                 | Memory write to  080 <- 20\n#026H T11 AB:07F DB:23          MREQ    WR                 | Memory write to  07F <- 23\n#006H T6  AB:001 DB:E1          MREQ RD                    | Memory read from 001 -> E1\n#007H T7  AB:001 DB:E1          MREQ RD                    | Memory read from 001 -> E1\n#023H T8  AB:07E DB:1F          MREQ    WR                 | Memory write to  07E <- 1F\n#026H T11 AB:07D DB:1B          MREQ    WR                 | Memory write to  07D <- 1B\n#006H T6  AB:001 DB:E2          MREQ RD                    | Memory read from 001 -> E2\n#007H T7  AB:001 DB:E2          MREQ RD                    | Memory read from 001 -> E2\n#023H T8  AB:07C DB:1E          MREQ    WR                 | Memory write to  07C <- 1E\n#026H T11 AB:07B DB:1B          MREQ    WR                 | Memory write to  07B <- 1B\n#006H T6  AB:001 DB:E3          MREQ RD                    | Memory read from 001 -> E3\n#007H T7  AB:001 DB:E3          MREQ RD                    | Memory read from 001 -> E3\n#023H T8  AB:07A DB:1D          MREQ    WR                 | Memory write to  07A <- 1D\n#026H T11 AB:079 DB:1B          MREQ    WR                 | Memory write to  079 <- 1B\n#006H T6  AB:001 DB:E4          MREQ RD                    | Memory read from 001 -> E4\n#007H T7  AB:001 DB:E4          MREQ RD                    | Memory read from 001 -> E4\n#023H T8  AB:078 DB:1C          MREQ    WR                 | Memory write to  078 <- 1C\n#026H T11 AB:077 DB:1B          MREQ    WR                 | Memory write to  077 <- 1B\n#006H T6  AB:001 DB:E5          MREQ RD                    | Memory read from 001 -> E5\n#007H T7  AB:001 DB:E5          MREQ RD                    | Memory read from 001 -> E5\n#023H T8  AB:076 DB:1B          MREQ    WR                 | Memory write to  076 <- 1B\n#026H T11 AB:075 DB:1B          MREQ    WR                 | Memory write to  075 <- 1B\n#006H T6  AB:001 DB:E6          MREQ RD                    | Memory read from 001 -> E6\n#007H T7  AB:001 DB:E6          MREQ RD                    | Memory read from 001 -> E6\n#023H T8  AB:074 DB:1A          MREQ    WR                 | Memory write to  074 <- 1A\n#026H T11 AB:073 DB:1B          MREQ    WR                 | Memory write to  073 <- 1B\n#006H T6  AB:001 DB:E7          MREQ RD                    | Memory read from 001 -> E7\n#007H T7  AB:001 DB:E7          MREQ RD                    | Memory read from 001 -> E7\n#023H T8  AB:072 DB:19          MREQ    WR                 | Memory write to  072 <- 19\n#026H T11 AB:071 DB:1B          MREQ    WR                 | Memory write to  071 <- 1B\n#006H T6  AB:001 DB:E8          MREQ RD                    | Memory read from 001 -> E8\n#007H T7  AB:001 DB:E8          MREQ RD                    | Memory read from 001 -> E8\n#023H T8  AB:070 DB:18          MREQ    WR                 | Memory write to  070 <- 18\n#026H T11 AB:06F DB:1B          MREQ    WR                 | Memory write to  06F <- 1B\n#006H T6  AB:001 DB:E9          MREQ RD                    | Memory read from 001 -> E9\n#007H T7  AB:001 DB:E9          MREQ RD                    | Memory read from 001 -> E9\n#023H T8  AB:06E DB:17          MREQ    WR                 | Memory write to  06E <- 17\n#026H T11 AB:06D DB:13          MREQ    WR                 | Memory write to  06D <- 13\n#006H T6  AB:001 DB:EA          MREQ RD                    | Memory read from 001 -> EA\n#007H T7  AB:001 DB:EA          MREQ RD                    | Memory read from 001 -> EA\n#023H T8  AB:06C DB:16          MREQ    WR                 | Memory write to  06C <- 16\n#026H T11 AB:06B DB:13          MREQ    WR                 | Memory write to  06B <- 13\n#006H T6  AB:001 DB:EB          MREQ RD                    | Memory read from 001 -> EB\n#007H T7  AB:001 DB:EB          MREQ RD                    | Memory read from 001 -> EB\n#023H T8  AB:06A DB:15          MREQ    WR                 | Memory write to  06A <- 15\n#026H T11 AB:069 DB:13          MREQ    WR                 | Memory write to  069 <- 13\n#006H T6  AB:001 DB:EC          MREQ RD                    | Memory read from 001 -> EC\n#007H T7  AB:001 DB:EC          MREQ RD                    | Memory read from 001 -> EC\n#023H T8  AB:068 DB:14          MREQ    WR                 | Memory write to  068 <- 14\n#026H T11 AB:067 DB:13          MREQ    WR                 | Memory write to  067 <- 13\n#006H T6  AB:001 DB:ED          MREQ RD                    | Memory read from 001 -> ED\n#007H T7  AB:001 DB:ED          MREQ RD                    | Memory read from 001 -> ED\n#023H T8  AB:066 DB:13          MREQ    WR                 | Memory write to  066 <- 13\n#026H T11 AB:065 DB:13          MREQ    WR                 | Memory write to  065 <- 13\n#006H T6  AB:001 DB:EE          MREQ RD                    | Memory read from 001 -> EE\n#007H T7  AB:001 DB:EE          MREQ RD                    | Memory read from 001 -> EE\n#023H T8  AB:064 DB:12          MREQ    WR                 | Memory write to  064 <- 12\n#026H T11 AB:063 DB:13          MREQ    WR                 | Memory write to  063 <- 13\n#006H T6  AB:001 DB:EF          MREQ RD                    | Memory read from 001 -> EF\n#007H T7  AB:001 DB:EF          MREQ RD                    | Memory read from 001 -> EF\n#023H T8  AB:062 DB:11          MREQ    WR                 | Memory write to  062 <- 11\n#026H T11 AB:061 DB:13          MREQ    WR                 | Memory write to  061 <- 13\n#006H T6  AB:001 DB:F0          MREQ RD                    | Memory read from 001 -> F0\n#007H T7  AB:001 DB:F0          MREQ RD                    | Memory read from 001 -> F0\n#023H T8  AB:060 DB:10          MREQ    WR                 | Memory write to  060 <- 10\n#026H T11 AB:05F DB:03          MREQ    WR                 | Memory write to  05F <- 03\n#006H T6  AB:001 DB:F1          MREQ RD                    | Memory read from 001 -> F1\n#007H T7  AB:001 DB:F1          MREQ RD                    | Memory read from 001 -> F1\n#023H T8  AB:05E DB:0F          MREQ    WR                 | Memory write to  05E <- 0F\n#026H T11 AB:05D DB:1B          MREQ    WR                 | Memory write to  05D <- 1B\n#006H T6  AB:001 DB:F2          MREQ RD                    | Memory read from 001 -> F2\n#007H T7  AB:001 DB:F2          MREQ RD                    | Memory read from 001 -> F2\n#023H T8  AB:05C DB:0E          MREQ    WR                 | Memory write to  05C <- 0E\n#026H T11 AB:05B DB:1B          MREQ    WR                 | Memory write to  05B <- 1B\n#006H T6  AB:001 DB:F3          MREQ RD                    | Memory read from 001 -> F3\n#007H T7  AB:001 DB:F3          MREQ RD                    | Memory read from 001 -> F3\n#023H T8  AB:05A DB:0D          MREQ    WR                 | Memory write to  05A <- 0D\n#026H T11 AB:059 DB:1B          MREQ    WR                 | Memory write to  059 <- 1B\n#006H T6  AB:001 DB:F4          MREQ RD                    | Memory read from 001 -> F4\n#007H T7  AB:001 DB:F4          MREQ RD                    | Memory read from 001 -> F4\n#023H T8  AB:058 DB:0C          MREQ    WR                 | Memory write to  058 <- 0C\n#026H T11 AB:057 DB:1B          MREQ    WR                 | Memory write to  057 <- 1B\n#006H T6  AB:001 DB:F5          MREQ RD                    | Memory read from 001 -> F5\n#007H T7  AB:001 DB:F5          MREQ RD                    | Memory read from 001 -> F5\n#023H T8  AB:056 DB:0B          MREQ    WR                 | Memory write to  056 <- 0B\n#026H T11 AB:055 DB:1B          MREQ    WR                 | Memory write to  055 <- 1B\n#006H T6  AB:001 DB:F6          MREQ RD                    | Memory read from 001 -> F6\n#007H T7  AB:001 DB:F6          MREQ RD                    | Memory read from 001 -> F6\n#023H T8  AB:054 DB:0A          MREQ    WR                 | Memory write to  054 <- 0A\n#026H T11 AB:053 DB:1B          MREQ    WR                 | Memory write to  053 <- 1B\n#006H T6  AB:001 DB:F7          MREQ RD                    | Memory read from 001 -> F7\n#007H T7  AB:001 DB:F7          MREQ RD                    | Memory read from 001 -> F7\n#023H T8  AB:052 DB:09          MREQ    WR                 | Memory write to  052 <- 09\n#026H T11 AB:051 DB:1B          MREQ    WR                 | Memory write to  051 <- 1B\n#006H T6  AB:001 DB:F8          MREQ RD                    | Memory read from 001 -> F8\n#007H T7  AB:001 DB:F8          MREQ RD                    | Memory read from 001 -> F8\n#023H T8  AB:050 DB:08          MREQ    WR                 | Memory write to  050 <- 08\n#026H T11 AB:04F DB:1B          MREQ    WR                 | Memory write to  04F <- 1B\n#006H T6  AB:001 DB:F9          MREQ RD                    | Memory read from 001 -> F9\n#007H T7  AB:001 DB:F9          MREQ RD                    | Memory read from 001 -> F9\n#023H T8  AB:04E DB:07          MREQ    WR                 | Memory write to  04E <- 07\n#026H T11 AB:04D DB:13          MREQ    WR                 | Memory write to  04D <- 13\n#006H T6  AB:001 DB:FA          MREQ RD                    | Memory read from 001 -> FA\n#007H T7  AB:001 DB:FA          MREQ RD                    | Memory read from 001 -> FA\n#023H T8  AB:04C DB:06          MREQ    WR                 | Memory write to  04C <- 06\n#026H T11 AB:04B DB:13          MREQ    WR                 | Memory write to  04B <- 13\n#006H T6  AB:001 DB:FB          MREQ RD                    | Memory read from 001 -> FB\n#007H T7  AB:001 DB:FB          MREQ RD                    | Memory read from 001 -> FB\n#023H T8  AB:04A DB:05          MREQ    WR                 | Memory write to  04A <- 05\n#026H T11 AB:049 DB:13          MREQ    WR                 | Memory write to  049 <- 13\n#006H T6  AB:001 DB:FC          MREQ RD                    | Memory read from 001 -> FC\n#007H T7  AB:001 DB:FC          MREQ RD                    | Memory read from 001 -> FC\n#023H T8  AB:048 DB:04          MREQ    WR                 | Memory write to  048 <- 04\n#026H T11 AB:047 DB:13          MREQ    WR                 | Memory write to  047 <- 13\n#006H T6  AB:001 DB:FD          MREQ RD                    | Memory read from 001 -> FD\n#007H T7  AB:001 DB:FD          MREQ RD                    | Memory read from 001 -> FD\n#023H T8  AB:046 DB:03          MREQ    WR                 | Memory write to  046 <- 03\n#026H T11 AB:045 DB:13          MREQ    WR                 | Memory write to  045 <- 13\n#006H T6  AB:001 DB:FE          MREQ RD                    | Memory read from 001 -> FE\n#007H T7  AB:001 DB:FE          MREQ RD                    | Memory read from 001 -> FE\n#023H T8  AB:044 DB:02          MREQ    WR                 | Memory write to  044 <- 02\n#026H T11 AB:043 DB:13          MREQ    WR                 | Memory write to  043 <- 13\n"
  },
  {
    "path": "tools/dongle/neg/simulate-neg.py",
    "content": "#!/usr/bin/env python3\n#\n# This script simulates 'neg' calculation and generates values for numbers 0-255.\n# These can be compared with a real Z80 run values.\n#\nimport sys\n\nfor inA in range(0, 256):\n    # neg is: 0 - A\n    # or:     255 - inA + 1\n    # or:     255 - -(cpl(A)+1) + 1   (second complement of A; can change the sign)\n    # or:     255 + cpl(A)+1 + 1\n    # or:     cpl(A) + 255 + 1 + 1\n    # or:     cpl(A) + 0 + 1      (+CY)\n#    cplA = inA ^ 0xFF;              # Bit-wise complement of A\n#    CYin = 1                        # Carry in force to 1\n#    op2  = 0                        # Load operand 2 with a constant value of 0\n#    finalA = cplA + op2 + CYin\n\n    acct = inA                      # ACCT is always loaded with A\n    op2 = inA                       # Load A again into OP2\n    mux1 = 0                        # MUX1 selects 0 instead of ACCT\n    mux2 = op2 ^ 0xFF               # MUX2 selects complement of OP2\n    CYin = 1                        # Carry in force to 1\n    finalA = mux1 + mux2 + CYin\n    carry_ins = finalA ^ mux1 ^ mux2  # Bitfield of all internal carry-ins\n    carry_ins ^= 0x90   # !?!?! Need to invert both H and V carry-ins?\n\n    # Calculate CF while we have bit [9] available\n    cf = 0\n    if finalA > 255 or finalA < 0:\n        cf = 1\n\n    cf ^= 1                         # Complement CY since we used cpl(A) and not A\n    nf = 1                          # 1 for SUB operation\n\n    finalA = finalA & 0xFF          # Clamp final value to 8 bits\n\n    #-------------------------------------------------------------------------------\n    # Flag calculation: SF, ZF, YF, HF, XF, VF/PF, NF, CF\n    #-------------------------------------------------------------------------------\n    # Carry and Overflow calculation on Z80 require us to use internal carry-ins\n    # http://stackoverflow.com/questions/8034566/overflow-and-carry-flags-on-z80\n    #carry_ins = finalA ^ inA ^ op2  # Bitfield of all internal carry-ins\n\n    sf = (finalA>>7) & 1            # SF = Copy of [7]\n    zf = finalA==0                  # ZF = Set if all result bits are zero\n    yf = (finalA>>5) & 1            # YF = Copy of [5]\n    hf = (carry_ins>>4)&1           # HF = Internal carry from bit [3] to [4]\n    xf = (finalA>>3) & 1            # XF = Copy of [3]\n    #                               # PF = XOR all final bits to get odd parity value\n    pf = (((finalA>>7)^(finalA>>6)^(finalA>>5)^(finalA>>4)^(finalA>>3)^(finalA>>2)^(finalA>>1)^(finalA>>0))&1)^1\n    vf = (carry_ins>>7)&1           # VF = Internal carry from bit [6] to [7]\n    vf ^= cf                        # XOR'ed with the final carry out\n\n    flags = (sf<<7) | (zf<<6) | (yf<<5) | (hf<<4) | (xf<<3) | (vf<<2) | (nf<<1) | (cf<<0)\n\n    print ('%0.2X -> %0.2X  Flags = %0.2X' % ( inA, finalA, flags))\n"
  },
  {
    "path": "tools/dongle/neg/z80-instruction-test-neg.py",
    "content": "#!/usr/bin/env python\n#\n# This script runs Z80 command 'neg' for all 256 values and prints out\n# memory access log data. This data is used to feed the simulation\n# script and verify its algorithm correctness.\n# It needs:\n#   1. Arduino Z80 dongle: http://www.baltazarstudios.com\n# Needs pyserial from https://pypi.python.org/pypi/pyserial\n#\nimport serial\nimport sys\n\nser = serial.Serial(\"\\\\.\\COM9\", 115200, timeout=1)\n\n# Flush the serial buffer, removes any command response\ndef serialFlush(ser):\n    while 1:\n        indata = ser.readline().rstrip('\\n')\n        if not indata:\n            break\n\ntry:\n    serialFlush(ser)\n    # Stop after selected M1 cycle effectively running only that one sequence\n    ser.write(\"s 4 5\\r\")\n    serialFlush(ser)\n\n    # Loop for all 256 arguments\n    for x in range(0, 256):\n    #   3E00            ld      a, 00h\n    #   ED44            neg\n    #   F5              push    af\n        ram = ':10000000' + '3E' + (\"%0.2X\" % x) + 'ED44F50405060708090A0B0C0D00'\n\n        ser.write(ram + '\\r')\n        indata = ser.readline().rstrip('\\n')\n        ser.write('r\\r')\n\n        sys.stderr.write (ram + '\\n')\n\n        # Skip initial response from Arduino, includes two empty cycles after the reset\n        for x in range(1,7):\n            indata = ser.readline()\n\n        while 1:\n            indata = ser.readline()\n            if not indata:\n                break\n            if indata[0]!=':':\n                if \"Memory\" in indata:\n                    print (indata.rstrip('\\r\\n'))\n\nexcept KeyboardInterrupt:\n     ser.close()\n"
  },
  {
    "path": "tools/dongle/sbc/simulate-sbc.py",
    "content": "#!/usr/bin/env python3\n#\n# This script simulates 'sbc' calculation and generates values for selected numbers.\n# These can be compared with a real Z80 run values.\n#\nimport sys\n\ndef printFlags(f):\n    s = ''\n    if f & (1 << 7):\n        s += 'S'\n    else:\n        s += ' '\n    if f & (1 << 6):\n        s += 'Z'\n    else:\n        s += ' '\n    if f & (1 << 5):\n        s += 'Y'\n    else:\n        s += ' '\n    if f & (1 << 4):\n        s += 'H'\n    else:\n        s += ' '\n    if f & (1 << 3):\n        s += 'X'\n    else:\n        s += ' '\n    if f & (1 << 2):\n        s += 'P'\n    else:\n        s += ' '\n    if f & (1 << 1):\n        s += 'V'\n    else:\n        s += ' '\n    if f & (1 << 0):\n        s += 'C'\n    else:\n        s += ' '\n    print ('Flags =                           %s' % s)\n\ndef sbc(inA, op2, CYin):\n    print ('------------------------------------------')\n    print ('Input: %0.2X SBC %0.2X  CY = %0.2X' % ( inA, op2, CYin))\n\n    double_cpl = 0                  # Flag that we did a double 1's complement\n    cplOp2 = op2 ^ 0xFF             # Bit-wise complement of OP2\n\n    if CYin:                        # If CF was set, we'll also use complemented ACCT\n        double_cpl = 1\n        cplA = inA ^ 0xFF\n        finalA = cplA + cplOp2 + CYin\n        carry_ins = finalA ^ cplA ^ cplOp2   # Bitfield of all internal carry-ins\n    else:                           # Otherwise, set CF to act as '+1' in NEG\n        CYin = 1\n        finalA = inA + cplOp2 + CYin\n        carry_ins = finalA ^ inA ^ cplOp2    # Bitfield of all internal carry-ins\n        carry_ins ^= 0xFF\n\n    # Calculate CF while we have bit [9] available\n    cf = 0\n    if finalA > 255 or finalA < 0:\n        cf = 1\n\n    cf ^= 1                         # Complement CY since we used cpl(A) and not A\n    if double_cpl:\n        cf ^= 1\n\n    nf = 1                          # 1 for SUB operation\n\n    finalA = finalA & 0xFF          # Clamp final value to 8 bits\n\n    #-------------------------------------------------------------------------------\n    # Flag calculation: SF, ZF, YF, HF, XF, VF/PF, NF, CF\n    #-------------------------------------------------------------------------------\n    # Carry and Overflow calculation on Z80 require us to use internal carry-ins\n    # http://stackoverflow.com/questions/8034566/overflow-and-carry-flags-on-z80\n    #carry_ins = finalA ^ inA ^ op2  # Bitfield of all internal carry-ins\n\n    sf = (finalA>>7) & 1            # SF = Copy of [7]\n    zf = finalA==0                  # ZF = Set if all result bits are zero\n    yf = (finalA>>5) & 1            # YF = Copy of [5]\n    hf = (carry_ins>>4)&1           # HF = Internal carry from bit [3] to [4]\n    xf = (finalA>>3) & 1            # XF = Copy of [3]\n    #                               # PF = XOR all final bits to get odd parity value\n    pf = (((finalA>>7)^(finalA>>6)^(finalA>>5)^(finalA>>4)^(finalA>>3)^(finalA>>2)^(finalA>>1)^(finalA>>0))&1)^1\n    vf = (carry_ins>>7)&1           # VF = Internal carry from bit [6] to [7]\n    vf ^= cf                        # XOR'ed with the final carry out\n\n    flags = (sf<<7) | (zf<<6) | (yf<<5) | (hf<<4) | (xf<<3) | (vf<<2) | (nf<<1) | (cf<<0)\n\n    print ('Out:      A -> %0.2X    Flags = %0.2X' % ( finalA, flags))\n    printFlags(flags)\n\nsbc(0, 0, 0)\nprint ('Should be A -> 00    Flags = 42')\nprintFlags(0x42)\nsbc(0, 1, 0)\nprint ('Should be A -> FF    Flags = BB')\nprintFlags(0xBB)\n\nsbc(0, 0, 1)\nprint ('Should be A -> FF    Flags = BB')\nprintFlags(0xBB)\nsbc(0, 1, 1)\nprint ('Should be A -> FE    Flags = BB')\nprintFlags(0xBB)\n\nsbc(0xAA, 0x55, 0)\nprint ('Should be A -> 55    Flags = 06')\nprintFlags(0x06)\nsbc(0x55, 0xAA, 0)\nprint ('Should be A -> AB    Flags = BF')\nprintFlags(0xBF)\n\nsbc(0xAA, 0x55, 1)\nprint ('Should be A -> 54    Flags = 06')\nprintFlags(0x06)\nsbc(0x55, 0xAA, 1)\nprint ('Should be A -> AA    Flags = BF')\nprintFlags(0xBF)\n\nsbc(0x0F, 0x03, 1)\nprint ('Should be A -> 0B    Flags = 0A')\nprintFlags(0x0A)\n"
  },
  {
    "path": "tools/dongle/sbc/simulate-sub.py",
    "content": "#!/usr/bin/env python3\n#\n# This script simulates 'sub' calculation and generates values for selected numbers.\n# These can be compared with a real Z80 run values.\n#\nimport sys\n\ndef printFlags(f):\n    s = ''\n    if f & (1 << 7):\n        s += 'S'\n    else:\n        s += ' '\n    if f & (1 << 6):\n        s += 'Z'\n    else:\n        s += ' '\n    if f & (1 << 5):\n        s += 'Y'\n    else:\n        s += ' '\n    if f & (1 << 4):\n        s += 'H'\n    else:\n        s += ' '\n    if f & (1 << 3):\n        s += 'X'\n    else:\n        s += ' '\n    if f & (1 << 2):\n        s += 'P'\n    else:\n        s += ' '\n    if f & (1 << 1):\n        s += 'V'\n    else:\n        s += ' '\n    if f & (1 << 0):\n        s += 'C'\n    else:\n        s += ' '\n    print ('Flags =                           %s' % s)\n\ndef sbc(inA, op2, CYin):\n    print ('------------------------------------------')\n    print ('Input: %0.2X SUB %0.2X' % ( inA, op2))\n\n    cplA = inA ^ 0xFF               # Bit-wise complement of A\n    CYin = 1\n    finalA = cplA + 0 + CYin\n    finalA = finalA + op2\n\n    # Calculate CF while we have bit [9] available\n    cf = 0\n    if finalA > 255 or finalA < 0:\n        cf = 1\n\n    cf ^= 1                         # Complement CY since we used cpl(A) and not A\n    nf = 1                          # 1 for SUB operation\n\n    finalA = finalA & 0xFF          # Clamp final value to 8 bits\n\n    #-------------------------------------------------------------------------------\n    # Flag calculation: SF, ZF, YF, HF, XF, VF/PF, NF, CF\n    #-------------------------------------------------------------------------------\n    # Carry and Overflow calculation on Z80 require us to use internal carry-ins\n    # http://stackoverflow.com/questions/8034566/overflow-and-carry-flags-on-z80\n    carry_ins = finalA ^ inA ^ op2  # Bitfield of all internal carry-ins\n\n    sf = (finalA>>7) & 1            # SF = Copy of [7]\n    zf = finalA==0                  # ZF = Set if all result bits are zero\n    yf = (finalA>>5) & 1            # YF = Copy of [5]\n    hf = (carry_ins>>4)&1           # HF = Internal carry from bit [3] to [4]\n    xf = (finalA>>3) & 1            # XF = Copy of [3]\n    #                               # PF = XOR all final bits to get odd parity value\n    pf = (((finalA>>7)^(finalA>>6)^(finalA>>5)^(finalA>>4)^(finalA>>3)^(finalA>>2)^(finalA>>1)^(finalA>>0))&1)^1\n    vf = (carry_ins>>7)&1           # VF = Internal carry from bit [6] to [7]\n    vf ^= cf                        # XOR'ed with the final carry out\n\n    flags = (sf<<7) | (zf<<6) | (yf<<5) | (hf<<4) | (xf<<3) | (vf<<2) | (nf<<1) | (cf<<0)\n\n    print ('Out:      A -> %0.2X    Flags = %0.2X' % ( finalA, flags))\n    printFlags(flags)\n\nsbc(0, 0, 0)\nprint ('Should be A -> 00    Flags = 42')\nprintFlags(0x42)\nsbc(0, 1, 0)\nprint ('Should be A -> FF    Flags = BB')\nprintFlags(0xBB)\n\nsbc(0xAA, 0x55, 0)\nprint ('Should be A -> 55    Flags = 06')\nprintFlags(0x06)\nsbc(0x55, 0xAA, 0)\nprint ('Should be A -> AB    Flags = BF')\nprintFlags(0xBF)\n\nsbc(0x0F, 0x03, 0)\nprint ('Should be A -> 0C    Flags = 0A')\nprintFlags(0x0A)\n"
  },
  {
    "path": "tools/dongle/xx.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD HTML 4.01//EN\">\n<HTML><HEAD><TITLE>Z80 Instructions Timing</TITLE></HEAD><BODY>\n<H1>Regular opcodes</H1>\n00 .. <A href=\"#00\">NOP</A><BR>\n01 .. <A href=\"#01\">LD BC,nn</A><BR>\n02 .. <A href=\"#02\">LD (BC),A</A><BR>\n03 .. <A href=\"#03\">INC BC</A><BR>\n04 .. <A href=\"#04\">INC B</A><BR>\n05 .. <A href=\"#05\">DEC B</A><BR>\n06 .. <A href=\"#06\">LD B,n</A><BR>\n07 .. <A href=\"#07\">RLCA</A><BR>\n08 .. <A href=\"#08\">EX AF,AF'</A><BR>\n09 .. <A href=\"#09\">ADD HL,BC</A><BR>\n0A .. <A href=\"#0A\">LD A,(BC)</A><BR>\n0B .. <A href=\"#0B\">DEC BC</A><BR>\n0C .. <A href=\"#0C\">INC C</A><BR>\n0D .. <A href=\"#0D\">DEC C</A><BR>\n0E .. <A href=\"#0E\">LD C,n</A><BR>\n0F .. <A href=\"#0F\">RRCA</A><BR>\n10 .. <A href=\"#10\">DJNZ (PC+e)</A><BR>\n11 .. <A href=\"#11\">LD DE,nn</A><BR>\n12 .. <A href=\"#12\">LD (DE),A</A><BR>\n13 .. <A href=\"#13\">INC DE</A><BR>\n14 .. <A href=\"#14\">INC D</A><BR>\n15 .. <A href=\"#15\">DEC D</A><BR>\n16 .. <A href=\"#16\">LD D,n</A><BR>\n17 .. <A href=\"#17\">RLA</A><BR>\n18 .. <A href=\"#18\">JR e</A><BR>\n19 .. <A href=\"#19\">ADD HL,DE</A><BR>\n1A .. <A href=\"#1A\">LD A,(DE)</A><BR>\n1B .. <A href=\"#1B\">DEC DE</A><BR>\n1C .. <A href=\"#1C\">INC E</A><BR>\n1D .. <A href=\"#1D\">DEC E</A><BR>\n1E .. <A href=\"#1E\">LD E,n</A><BR>\n1F .. <A href=\"#1F\">RRA</A><BR>\n20 .. <A href=\"#20\">JR NZ,e</A><BR>\n21 .. <A href=\"#21\">LD HL,nn</A><BR>\n22 .. <A href=\"#22\">LD (nn),HL</A><BR>\n23 .. <A href=\"#23\">INC HL</A><BR>\n24 .. <A href=\"#24\">INC H</A><BR>\n25 .. <A href=\"#25\">DEC H</A><BR>\n26 .. <A href=\"#26\">LD H,n</A><BR>\n27 .. <A href=\"#27\">DAA</A><BR>\n28 .. <A href=\"#28\">JR Z,e</A><BR>\n29 .. <A href=\"#29\">ADD HL,HL</A><BR>\n2A .. <A href=\"#2A\">LD HL,(nn)</A><BR>\n2B .. <A href=\"#2B\">DEC HL</A><BR>\n2C .. <A href=\"#2C\">INC L</A><BR>\n2D .. <A href=\"#2D\">DEC L</A><BR>\n2E .. <A href=\"#2E\">LD L,n</A><BR>\n2F .. <A href=\"#2F\">CPL</A><BR>\n30 .. <A href=\"#30\">JR NC,e</A><BR>\n31 .. <A href=\"#31\">LD SP,nn</A><BR>\n32 .. <A href=\"#32\">LD (nn),A</A><BR>\n33 .. <A href=\"#33\">INC SP</A><BR>\n34 .. <A href=\"#34\">INC (HL)</A><BR>\n35 .. <A href=\"#35\">DEC (HL)</A><BR>\n36 .. <A href=\"#36\">LD (HL),n</A><BR>\n37 .. <A href=\"#37\">SCF</A><BR>\n38 .. <A href=\"#38\">JR C,e</A><BR>\n39 .. <A href=\"#39\">ADD HL,SP</A><BR>\n3A .. <A href=\"#3A\">LD A,(nn)</A><BR>\n3B .. <A href=\"#3B\">DEC SP</A><BR>\n3C .. <A href=\"#3C\">INC A</A><BR>\n3D .. <A href=\"#3D\">DEC A</A><BR>\n3E .. <A href=\"#3E\">LD A,n</A><BR>\n3F .. <A href=\"#3F\">CCF</A><BR>\n40 .. <A href=\"#40\">LD B,B</A><BR>\n41 .. <A href=\"#41\">LD B,C</A><BR>\n42 .. <A href=\"#42\">LD B,D</A><BR>\n43 .. <A href=\"#43\">LD B,E</A><BR>\n44 .. <A href=\"#44\">LD B,H</A><BR>\n45 .. <A href=\"#45\">LD B,L</A><BR>\n46 .. <A href=\"#46\">LD B,(HL)</A><BR>\n47 .. <A href=\"#47\">LD B,A</A><BR>\n48 .. <A href=\"#48\">LD C,B</A><BR>\n49 .. <A href=\"#49\">LD C,C</A><BR>\n4A .. <A href=\"#4A\">LD C,D</A><BR>\n4B .. <A href=\"#4B\">LD C,E</A><BR>\n4C .. <A href=\"#4C\">LD C,H</A><BR>\n4D .. <A href=\"#4D\">LD C,L</A><BR>\n4E .. <A href=\"#4E\">LD C,(HL)</A><BR>\n4F .. <A href=\"#4F\">LD C,A</A><BR>\n50 .. <A href=\"#50\">LD D,B</A><BR>\n51 .. <A href=\"#51\">LD D,C</A><BR>\n52 .. <A href=\"#52\">LD D,D</A><BR>\n53 .. <A href=\"#53\">LD D,E</A><BR>\n54 .. <A href=\"#54\">LD D,H</A><BR>\n55 .. <A href=\"#55\">LD D,L</A><BR>\n56 .. <A href=\"#56\">LD D,(HL)</A><BR>\n57 .. <A href=\"#57\">LD D,A</A><BR>\n58 .. <A href=\"#58\">LD E,B</A><BR>\n59 .. <A href=\"#59\">LD E,C</A><BR>\n5A .. <A href=\"#5A\">LD E,D</A><BR>\n5B .. <A href=\"#5B\">LD E,E</A><BR>\n5C .. <A href=\"#5C\">LD E,H</A><BR>\n5D .. <A href=\"#5D\">LD E,L</A><BR>\n5E .. <A href=\"#5E\">LD E,(HL)</A><BR>\n5F .. <A href=\"#5F\">LD E,A</A><BR>\n60 .. <A href=\"#60\">LD H,B</A><BR>\n61 .. <A href=\"#61\">LD H,C</A><BR>\n62 .. <A href=\"#62\">LD H,D</A><BR>\n63 .. <A href=\"#63\">LD H,E</A><BR>\n64 .. <A href=\"#64\">LD H,H</A><BR>\n65 .. <A href=\"#65\">LD H,L</A><BR>\n66 .. <A href=\"#66\">LD H,(HL)</A><BR>\n67 .. <A href=\"#67\">LD H,A</A><BR>\n68 .. <A href=\"#68\">LD L,B</A><BR>\n69 .. <A href=\"#69\">LD L,C</A><BR>\n6A .. <A href=\"#6A\">LD L,D</A><BR>\n6B .. <A href=\"#6B\">LD L,E</A><BR>\n6C .. <A href=\"#6C\">LD L,H</A><BR>\n6D .. <A href=\"#6D\">LD L,L</A><BR>\n6E .. <A href=\"#6E\">LD L,(HL)</A><BR>\n6F .. <A href=\"#6F\">LD L,A</A><BR>\n70 .. <A href=\"#70\">LD (HL),B</A><BR>\n71 .. <A href=\"#71\">LD (HL),C</A><BR>\n72 .. <A href=\"#72\">LD (HL),D</A><BR>\n73 .. <A href=\"#73\">LD (HL),E</A><BR>\n74 .. <A href=\"#74\">LD (HL),H</A><BR>\n75 .. <A href=\"#75\">LD (HL),L</A><BR>\n76 .. <A href=\"#76\">HALT</A><BR>\n77 .. <A href=\"#77\">LD (HL),A</A><BR>\n78 .. <A href=\"#78\">LD A,B</A><BR>\n79 .. <A href=\"#79\">LD A,C</A><BR>\n7A .. <A href=\"#7A\">LD A,D</A><BR>\n7B .. <A href=\"#7B\">LD A,E</A><BR>\n7C .. <A href=\"#7C\">LD A,H</A><BR>\n7D .. <A href=\"#7D\">LD A,L</A><BR>\n7E .. <A href=\"#7E\">LD A,(HL)</A><BR>\n7F .. <A href=\"#7F\">LD A,A</A><BR>\n80 .. <A href=\"#80\">ADD A,B</A><BR>\n81 .. <A href=\"#81\">ADD A,C</A><BR>\n82 .. <A href=\"#82\">ADD A,D</A><BR>\n83 .. <A href=\"#83\">ADD A,E</A><BR>\n84 .. <A href=\"#84\">ADD A,H</A><BR>\n85 .. <A href=\"#85\">ADD A,L</A><BR>\n86 .. <A href=\"#86\">ADD A,(HL)</A><BR>\n87 .. <A href=\"#87\">ADD A,A</A><BR>\n88 .. <A href=\"#88\">ADC A,B</A><BR>\n89 .. <A href=\"#89\">ADC A,C</A><BR>\n8A .. <A href=\"#8A\">ADC A,D</A><BR>\n8B .. <A href=\"#8B\">ADC A,E</A><BR>\n8C .. <A href=\"#8C\">ADC A,H</A><BR>\n8D .. <A href=\"#8D\">ADC A,L</A><BR>\n8E .. <A href=\"#8E\">ADC A,(HL)</A><BR>\n8F .. <A href=\"#8F\">ADC A,A</A><BR>\n90 .. <A href=\"#90\">SUB B</A><BR>\n91 .. <A href=\"#91\">SUB C</A><BR>\n92 .. <A href=\"#92\">SUB D</A><BR>\n93 .. <A href=\"#93\">SUB E</A><BR>\n94 .. <A href=\"#94\">SUB H</A><BR>\n95 .. <A href=\"#95\">SUB L</A><BR>\n96 .. <A href=\"#96\">SUB (HL)</A><BR>\n97 .. <A href=\"#97\">SUB A</A><BR>\n98 .. <A href=\"#98\">SBC A,B</A><BR>\n99 .. <A href=\"#99\">SBC A,C</A><BR>\n9A .. <A href=\"#9A\">SBC A,D</A><BR>\n9B .. <A href=\"#9B\">SBC A,E</A><BR>\n9C .. <A href=\"#9C\">SBC A,H</A><BR>\n9D .. <A href=\"#9D\">SBC A,L</A><BR>\n9E .. <A href=\"#9E\">SBC A,(HL)</A><BR>\n9F .. <A href=\"#9F\">SBC A,A</A><BR>\nA0 .. <A href=\"#A0\">AND B</A><BR>\nA1 .. <A href=\"#A1\">AND C</A><BR>\nA2 .. <A href=\"#A2\">AND D</A><BR>\nA3 .. <A href=\"#A3\">AND E</A><BR>\nA4 .. <A href=\"#A4\">AND H</A><BR>\nA5 .. <A href=\"#A5\">AND L</A><BR>\nA6 .. <A href=\"#A6\">AND (HL)</A><BR>\nA7 .. <A href=\"#A7\">AND A</A><BR>\nA8 .. <A href=\"#A8\">XOR B</A><BR>\nA9 .. <A href=\"#A9\">XOR C</A><BR>\nAA .. <A href=\"#AA\">XOR D</A><BR>\nAB .. <A href=\"#AB\">XOR E</A><BR>\nAC .. <A href=\"#AC\">XOR H</A><BR>\nAD .. <A href=\"#AD\">XOR L</A><BR>\nAE .. <A href=\"#AE\">XOR (HL)</A><BR>\nAF .. <A href=\"#AF\">XOR A</A><BR>\nB0 .. <A href=\"#B0\">OR B</A><BR>\nB1 .. <A href=\"#B1\">OR C</A><BR>\nB2 .. <A href=\"#B2\">OR D</A><BR>\nB3 .. <A href=\"#B3\">OR E</A><BR>\nB4 .. <A href=\"#B4\">OR H</A><BR>\nB5 .. <A href=\"#B5\">OR L</A><BR>\nB6 .. <A href=\"#B6\">OR (HL)</A><BR>\nB7 .. <A href=\"#B7\">OR A</A><BR>\nB8 .. <A href=\"#B8\">CP B</A><BR>\nB9 .. <A href=\"#B9\">CP C</A><BR>\nBA .. <A href=\"#BA\">CP D</A><BR>\nBB .. <A href=\"#BB\">CP E</A><BR>\nBC .. <A href=\"#BC\">CP H</A><BR>\nBD .. <A href=\"#BD\">CP L</A><BR>\nBE .. <A href=\"#BE\">CP (HL)</A><BR>\nBF .. <A href=\"#BF\">CP A</A><BR>\nC0 .. <A href=\"#C0\">RET NZ</A><BR>\nC1 .. <A href=\"#C1\">POP BC</A><BR>\nC2 .. <A href=\"#C2\">JP NZ,nn</A><BR>\nC3 .. <A href=\"#C3\">JP nn</A><BR>\nC4 .. <A href=\"#C4\">CALL NZ,nn</A><BR>\nC5 .. <A href=\"#C5\">PUSH BC</A><BR>\nC6 .. <A href=\"#C6\">ADD A,n</A><BR>\nC7 .. <A href=\"#C7\">RST 0H</A><BR>\nC8 .. <A href=\"#C8\">RET Z</A><BR>\nC9 .. <A href=\"#C9\">RET</A><BR>\nCA .. <A href=\"#CA\">JP Z,nn</A><BR>\nCB .. <A href=\"#CB\">CB</A><BR>\nCC .. <A href=\"#CC\">CALL Z,nn</A><BR>\nCD .. <A href=\"#CD\">CALL nn</A><BR>\nCE .. <A href=\"#CE\">ADC A,n</A><BR>\nCF .. <A href=\"#CF\">RST 8H</A><BR>\nD0 .. <A href=\"#D0\">RET NC</A><BR>\nD1 .. <A href=\"#D1\">POP DE</A><BR>\nD2 .. <A href=\"#D2\">JP NC,nn</A><BR>\nD3 .. <A href=\"#D3\">OUT (n),A</A><BR>\nD4 .. <A href=\"#D4\">CALL NC,nn</A><BR>\nD5 .. <A href=\"#D5\">PUSH DE</A><BR>\nD6 .. <A href=\"#D6\">SUB n</A><BR>\nD7 .. <A href=\"#D7\">RST 10H</A><BR>\nD8 .. <A href=\"#D8\">RET C</A><BR>\nD9 .. <A href=\"#D9\">EXX</A><BR>\nDA .. <A href=\"#DA\">JP C,nn</A><BR>\nDB .. <A href=\"#DB\">IN A,(n)</A><BR>\nDC .. <A href=\"#DC\">CALL C,nn</A><BR>\nDD .. <A href=\"#DD\">DD</A><BR>\nDE .. <A href=\"#DE\">SBC A,n</A><BR>\nDF .. <A href=\"#DF\">RST 18H</A><BR>\nE0 .. <A href=\"#E0\">RET PO</A><BR>\nE1 .. <A href=\"#E1\">POP HL</A><BR>\nE2 .. <A href=\"#E2\">JP PO,nn</A><BR>\nE3 .. <A href=\"#E3\">EX (SP),HL</A><BR>\nE4 .. <A href=\"#E4\">CALL PO,nn</A><BR>\nE5 .. <A href=\"#E5\">PUSH HL</A><BR>\nE6 .. <A href=\"#E6\">AND n</A><BR>\nE7 .. <A href=\"#E7\">RST 20H</A><BR>\nE8 .. <A href=\"#E8\">RET PE</A><BR>\nE9 .. <A href=\"#E9\">JP (HL)</A><BR>\nEA .. <A href=\"#EA\">JP PE,nn</A><BR>\nEB .. <A href=\"#EB\">EX DE,HL</A><BR>\nEC .. <A href=\"#EC\">CALL PE,nn</A><BR>\nED .. <A href=\"#ED\">ED</A><BR>\nEE .. <A href=\"#EE\">XOR n</A><BR>\nEF .. <A href=\"#EF\">RST 28H</A><BR>\nF0 .. <A href=\"#F0\">RET P</A><BR>\nF1 .. <A href=\"#F1\">POP AF</A><BR>\nF2 .. <A href=\"#F2\">JP P,nn</A><BR>\nF3 .. <A href=\"#F3\">DI</A><BR>\nF4 .. <A href=\"#F4\">CALL P,nn</A><BR>\nF5 .. <A href=\"#F5\">PUSH AF</A><BR>\nF6 .. <A href=\"#F6\">OR n</A><BR>\nF7 .. <A href=\"#F7\">RST 30H</A><BR>\nF8 .. <A href=\"#F8\">RET M</A><BR>\nF9 .. <A href=\"#F9\">LD SP,HL</A><BR>\nFA .. <A href=\"#FA\">JP M,nn</A><BR>\nFB .. <A href=\"#FB\">EI</A><BR>\nFC .. <A href=\"#FC\">CALL M,nn</A><BR>\nFD .. <A href=\"#FD\">FD</A><BR>\nFE .. <A href=\"#FE\">CP n</A><BR>\nFF .. <A href=\"#FF\">RST 38H</A><BR>\n<H1>Instructions Timing</H1>\n<H3 id=\"00\">Opcode: 00     => NOP</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:00  M1      MREQ RD                    | Opcode read from 000 -> 00\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"01\">Opcode: 01 n n => LD BC,nn</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:01  M1      MREQ RD                    | Opcode read from 000 -> 01\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#008H T8  AB:002 DB:--                                     | \n#009H T9  AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n#010H T10 AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"02\">Opcode: 02     => LD (BC),A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:02  M1      MREQ RD                    | Opcode read from 000 -> 02\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:FF          MREQ                       | \n#007H T7  AB:001 DB:FF          MREQ    WR                 | Memory write to  001 <- FF\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"03\">Opcode: 03     => INC BC</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:03  M1      MREQ RD                    | Opcode read from 000 -> 03\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:000 DB:--                                     | \n#006H T6  AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"04\">Opcode: 04     => INC B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:04  M1      MREQ RD                    | Opcode read from 000 -> 04\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"05\">Opcode: 05     => DEC B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:05  M1      MREQ RD                    | Opcode read from 000 -> 05\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"06\">Opcode: 06 n   => LD B,n</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:06  M1      MREQ RD                    | Opcode read from 000 -> 06\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"07\">Opcode: 07     => RLCA</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:07  M1      MREQ RD                    | Opcode read from 000 -> 07\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"08\">Opcode: 08     => EX AF,AF'</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:08  M1      MREQ RD                    | Opcode read from 000 -> 08\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"09\">Opcode: 09     => ADD HL,BC</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:09  M1      MREQ RD                    | Opcode read from 000 -> 09\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:000 DB:--                                     | \n#006H T6  AB:000 DB:--                                     | \n#007H T7  AB:000 DB:--                                     | \n#008H T8  AB:000 DB:--                                     | \n#009H T9  AB:000 DB:--                                     | \n#010H T10 AB:000 DB:--                                     | \n#011H T11 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"0A\">Opcode: 0A     => LD A,(BC)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:0A  M1      MREQ RD                    | Opcode read from 000 -> 0A\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:002 DB:--                                     | \n#006H T6  AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n#007H T7  AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"0B\">Opcode: 0B     => DEC BC</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:0B  M1      MREQ RD                    | Opcode read from 000 -> 0B\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:000 DB:--                                     | \n#006H T6  AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"0C\">Opcode: 0C     => INC C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:0C  M1      MREQ RD                    | Opcode read from 000 -> 0C\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"0D\">Opcode: 0D     => DEC C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:0D  M1      MREQ RD                    | Opcode read from 000 -> 0D\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"0E\">Opcode: 0E n   => LD C,n</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:0E  M1      MREQ RD                    | Opcode read from 000 -> 0E\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"0F\">Opcode: 0F     => RRCA</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:0F  M1      MREQ RD                    | Opcode read from 000 -> 0F\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"10\">Opcode: 10 e   => DJNZ (PC+e)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:10  M1      MREQ RD                    | Opcode read from 000 -> 10\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:000 DB:--                                     | \n#006H T6  AB:001 DB:--                                     | \n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#008H T8  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"11\">Opcode: 11 n n => LD DE,nn</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:11  M1      MREQ RD                    | Opcode read from 000 -> 11\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#008H T8  AB:002 DB:--                                     | \n#009H T9  AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n#010H T10 AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"12\">Opcode: 12     => LD (DE),A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:12  M1      MREQ RD                    | Opcode read from 000 -> 12\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ                       | \n#007H T7  AB:001 DB:01          MREQ    WR                 | Memory write to  001 <- 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"13\">Opcode: 13     => INC DE</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:13  M1      MREQ RD                    | Opcode read from 000 -> 13\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:000 DB:--                                     | \n#006H T6  AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"14\">Opcode: 14     => INC D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:14  M1      MREQ RD                    | Opcode read from 000 -> 14\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"15\">Opcode: 15     => DEC D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:15  M1      MREQ RD                    | Opcode read from 000 -> 15\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"16\">Opcode: 16 n   => LD D,n</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:16  M1      MREQ RD                    | Opcode read from 000 -> 16\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"17\">Opcode: 17     => RLA</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:17  M1      MREQ RD                    | Opcode read from 000 -> 17\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"18\">Opcode: 18 e   => JR e</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:18  M1      MREQ RD                    | Opcode read from 000 -> 18\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#008H T8  AB:001 DB:--                                     | \n#009H T9  AB:001 DB:--                                     | \n#010H T10 AB:001 DB:--                                     | \n#011H T11 AB:001 DB:--                                     | \n#012H T12 AB:001 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"19\">Opcode: 19     => ADD HL,DE</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:19  M1      MREQ RD                    | Opcode read from 000 -> 19\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:000 DB:--                                     | \n#006H T6  AB:000 DB:--                                     | \n#007H T7  AB:000 DB:--                                     | \n#008H T8  AB:000 DB:--                                     | \n#009H T9  AB:000 DB:--                                     | \n#010H T10 AB:000 DB:--                                     | \n#011H T11 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"1A\">Opcode: 1A     => LD A,(DE)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:1A  M1      MREQ RD                    | Opcode read from 000 -> 1A\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:002 DB:--                                     | \n#006H T6  AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n#007H T7  AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"1B\">Opcode: 1B     => DEC DE</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:1B  M1      MREQ RD                    | Opcode read from 000 -> 1B\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:000 DB:--                                     | \n#006H T6  AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"1C\">Opcode: 1C     => INC E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:1C  M1      MREQ RD                    | Opcode read from 000 -> 1C\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"1D\">Opcode: 1D     => DEC E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:1D  M1      MREQ RD                    | Opcode read from 000 -> 1D\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"1E\">Opcode: 1E n   => LD E,n</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:1E  M1      MREQ RD                    | Opcode read from 000 -> 1E\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"1F\">Opcode: 1F     => RRA</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:1F  M1      MREQ RD                    | Opcode read from 000 -> 1F\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"20\">Opcode: 20 e   => JR NZ,e</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:20  M1      MREQ RD                    | Opcode read from 000 -> 20\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#008H T8  AB:001 DB:--                                     | \n#009H T9  AB:001 DB:--                                     | \n#010H T10 AB:001 DB:--                                     | \n#011H T11 AB:001 DB:--                                     | \n#012H T12 AB:001 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"21\">Opcode: 21 n n => LD HL,nn</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:21  M1      MREQ RD                    | Opcode read from 000 -> 21\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#008H T8  AB:002 DB:--                                     | \n#009H T9  AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n#010H T10 AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"22\">Opcode: 22 n n => LD (nn),HL</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:22  M1      MREQ RD                    | Opcode read from 000 -> 22\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#008H T8  AB:002 DB:--                                     | \n#009H T9  AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n#010H T10 AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n#011H T11 AB:001 DB:--                                     | \n#012H T12 AB:001 DB:01          MREQ                       | \n#013H T13 AB:001 DB:01          MREQ    WR                 | Memory write to  001 <- 01\n#014H T14 AB:002 DB:--                                     | \n#015H T15 AB:002 DB:02          MREQ                       | \n#016H T16 AB:002 DB:02          MREQ    WR                 | Memory write to  002 <- 02\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"23\">Opcode: 23     => INC HL</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:23  M1      MREQ RD                    | Opcode read from 000 -> 23\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:000 DB:--                                     | \n#006H T6  AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"24\">Opcode: 24     => INC H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:24  M1      MREQ RD                    | Opcode read from 000 -> 24\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"25\">Opcode: 25     => DEC H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:25  M1      MREQ RD                    | Opcode read from 000 -> 25\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"26\">Opcode: 26 n   => LD H,n</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:26  M1      MREQ RD                    | Opcode read from 000 -> 26\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"27\">Opcode: 27     => DAA</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:27  M1      MREQ RD                    | Opcode read from 000 -> 27\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"28\">Opcode: 28 e   => JR Z,e</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:28  M1      MREQ RD                    | Opcode read from 000 -> 28\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"29\">Opcode: 29     => ADD HL,HL</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:29  M1      MREQ RD                    | Opcode read from 000 -> 29\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:000 DB:--                                     | \n#006H T6  AB:000 DB:--                                     | \n#007H T7  AB:000 DB:--                                     | \n#008H T8  AB:000 DB:--                                     | \n#009H T9  AB:000 DB:--                                     | \n#010H T10 AB:000 DB:--                                     | \n#011H T11 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"2A\">Opcode: 2A n n => LD HL,(nn)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:2A  M1      MREQ RD                    | Opcode read from 000 -> 2A\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#008H T8  AB:002 DB:--                                     | \n#009H T9  AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n#010H T10 AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n#011H T11 AB:001 DB:--                                     | \n#012H T12 AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#013H T13 AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#014H T14 AB:002 DB:--                                     | \n#015H T15 AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n#016H T16 AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"2B\">Opcode: 2B     => DEC HL</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:2B  M1      MREQ RD                    | Opcode read from 000 -> 2B\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:000 DB:--                                     | \n#006H T6  AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"2C\">Opcode: 2C     => INC L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:2C  M1      MREQ RD                    | Opcode read from 000 -> 2C\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"2D\">Opcode: 2D     => DEC L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:2D  M1      MREQ RD                    | Opcode read from 000 -> 2D\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"2E\">Opcode: 2E n   => LD L,n</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:2E  M1      MREQ RD                    | Opcode read from 000 -> 2E\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"2F\">Opcode: 2F     => CPL</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:2F  M1      MREQ RD                    | Opcode read from 000 -> 2F\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"30\">Opcode: 30 e   => JR NC,e</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:30  M1      MREQ RD                    | Opcode read from 000 -> 30\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#008H T8  AB:001 DB:--                                     | \n#009H T9  AB:001 DB:--                                     | \n#010H T10 AB:001 DB:--                                     | \n#011H T11 AB:001 DB:--                                     | \n#012H T12 AB:001 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"31\">Opcode: 31 n n => LD SP,nn</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:31  M1      MREQ RD                    | Opcode read from 000 -> 31\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#008H T8  AB:002 DB:--                                     | \n#009H T9  AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n#010H T10 AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"32\">Opcode: 32 n n => LD (nn),A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:32  M1      MREQ RD                    | Opcode read from 000 -> 32\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#008H T8  AB:002 DB:--                                     | \n#009H T9  AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n#010H T10 AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n#011H T11 AB:001 DB:--                                     | \n#012H T12 AB:001 DB:FE          MREQ                       | \n#013H T13 AB:001 DB:FE          MREQ    WR                 | Memory write to  001 <- FE\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"33\">Opcode: 33     => INC SP</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:33  M1      MREQ RD                    | Opcode read from 000 -> 33\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:000 DB:--                                     | \n#006H T6  AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"34\">Opcode: 34     => INC (HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:34  M1      MREQ RD                    | Opcode read from 000 -> 34\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#008H T8  AB:001 DB:--                                     | \n#009H T9  AB:001 DB:--                                     | \n#010H T10 AB:001 DB:02          MREQ                       | \n#011H T11 AB:001 DB:02          MREQ    WR                 | Memory write to  001 <- 02\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"35\">Opcode: 35     => DEC (HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:35  M1      MREQ RD                    | Opcode read from 000 -> 35\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#008H T8  AB:001 DB:--                                     | \n#009H T9  AB:001 DB:--                                     | \n#010H T10 AB:001 DB:00          MREQ                       | \n#011H T11 AB:001 DB:00          MREQ    WR                 | Memory write to  001 <- 00\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"36\">Opcode: 36 n   => LD (HL),n</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:36  M1      MREQ RD                    | Opcode read from 000 -> 36\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#008H T8  AB:001 DB:--                                     | \n#009H T9  AB:001 DB:01          MREQ                       | \n#010H T10 AB:001 DB:01          MREQ    WR                 | Memory write to  001 <- 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"37\">Opcode: 37     => SCF</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:37  M1      MREQ RD                    | Opcode read from 000 -> 37\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"38\">Opcode: 38 e   => JR C,e</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:38  M1      MREQ RD                    | Opcode read from 000 -> 38\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#008H T8  AB:001 DB:--                                     | \n#009H T9  AB:001 DB:--                                     | \n#010H T10 AB:001 DB:--                                     | \n#011H T11 AB:001 DB:--                                     | \n#012H T12 AB:001 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"39\">Opcode: 39     => ADD HL,SP</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:39  M1      MREQ RD                    | Opcode read from 000 -> 39\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:000 DB:--                                     | \n#006H T6  AB:000 DB:--                                     | \n#007H T7  AB:000 DB:--                                     | \n#008H T8  AB:000 DB:--                                     | \n#009H T9  AB:000 DB:--                                     | \n#010H T10 AB:000 DB:--                                     | \n#011H T11 AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"3A\">Opcode: 3A n n => LD A,(nn)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:3A  M1      MREQ RD                    | Opcode read from 000 -> 3A\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#008H T8  AB:002 DB:--                                     | \n#009H T9  AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n#010H T10 AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n#011H T11 AB:001 DB:--                                     | \n#012H T12 AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#013H T13 AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"3B\">Opcode: 3B     => DEC SP</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:3B  M1      MREQ RD                    | Opcode read from 000 -> 3B\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:000 DB:--                                     | \n#006H T6  AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"3C\">Opcode: 3C     => INC A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:3C  M1      MREQ RD                    | Opcode read from 000 -> 3C\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"3D\">Opcode: 3D     => DEC A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:3D  M1      MREQ RD                    | Opcode read from 000 -> 3D\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"3E\">Opcode: 3E n   => LD A,n</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:3E  M1      MREQ RD                    | Opcode read from 000 -> 3E\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"3F\">Opcode: 3F     => CCF</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:3F  M1      MREQ RD                    | Opcode read from 000 -> 3F\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"40\">Opcode: 40     => LD B,B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:40  M1      MREQ RD                    | Opcode read from 000 -> 40\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"41\">Opcode: 41     => LD B,C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:41  M1      MREQ RD                    | Opcode read from 000 -> 41\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"42\">Opcode: 42     => LD B,D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:42  M1      MREQ RD                    | Opcode read from 000 -> 42\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"43\">Opcode: 43     => LD B,E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:43  M1      MREQ RD                    | Opcode read from 000 -> 43\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"44\">Opcode: 44     => LD B,H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:44  M1      MREQ RD                    | Opcode read from 000 -> 44\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"45\">Opcode: 45     => LD B,L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:45  M1      MREQ RD                    | Opcode read from 000 -> 45\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"46\">Opcode: 46     => LD B,(HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:46  M1      MREQ RD                    | Opcode read from 000 -> 46\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:003 DB:--                                     | \n#006H T6  AB:003 DB:03          MREQ RD                    | Memory read from 003 -> 03\n#007H T7  AB:003 DB:03          MREQ RD                    | Memory read from 003 -> 03\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"47\">Opcode: 47     => LD B,A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:47  M1      MREQ RD                    | Opcode read from 000 -> 47\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"48\">Opcode: 48     => LD C,B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:48  M1      MREQ RD                    | Opcode read from 000 -> 48\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"49\">Opcode: 49     => LD C,C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:49  M1      MREQ RD                    | Opcode read from 000 -> 49\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"4A\">Opcode: 4A     => LD C,D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:4A  M1      MREQ RD                    | Opcode read from 000 -> 4A\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"4B\">Opcode: 4B     => LD C,E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:4B  M1      MREQ RD                    | Opcode read from 000 -> 4B\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"4C\">Opcode: 4C     => LD C,H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:4C  M1      MREQ RD                    | Opcode read from 000 -> 4C\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"4D\">Opcode: 4D     => LD C,L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:4D  M1      MREQ RD                    | Opcode read from 000 -> 4D\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"4E\">Opcode: 4E     => LD C,(HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:4E  M1      MREQ RD                    | Opcode read from 000 -> 4E\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:003 DB:--                                     | \n#006H T6  AB:003 DB:03          MREQ RD                    | Memory read from 003 -> 03\n#007H T7  AB:003 DB:03          MREQ RD                    | Memory read from 003 -> 03\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"4F\">Opcode: 4F     => LD C,A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:4F  M1      MREQ RD                    | Opcode read from 000 -> 4F\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"50\">Opcode: 50     => LD D,B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:50  M1      MREQ RD                    | Opcode read from 000 -> 50\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"51\">Opcode: 51     => LD D,C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:51  M1      MREQ RD                    | Opcode read from 000 -> 51\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"52\">Opcode: 52     => LD D,D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:52  M1      MREQ RD                    | Opcode read from 000 -> 52\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"53\">Opcode: 53     => LD D,E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:53  M1      MREQ RD                    | Opcode read from 000 -> 53\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"54\">Opcode: 54     => LD D,H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:54  M1      MREQ RD                    | Opcode read from 000 -> 54\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"55\">Opcode: 55     => LD D,L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:55  M1      MREQ RD                    | Opcode read from 000 -> 55\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"56\">Opcode: 56     => LD D,(HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:56  M1      MREQ RD                    | Opcode read from 000 -> 56\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:003 DB:--                                     | \n#006H T6  AB:003 DB:03          MREQ RD                    | Memory read from 003 -> 03\n#007H T7  AB:003 DB:03          MREQ RD                    | Memory read from 003 -> 03\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"57\">Opcode: 57     => LD D,A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:57  M1      MREQ RD                    | Opcode read from 000 -> 57\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"58\">Opcode: 58     => LD E,B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:58  M1      MREQ RD                    | Opcode read from 000 -> 58\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"59\">Opcode: 59     => LD E,C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:59  M1      MREQ RD                    | Opcode read from 000 -> 59\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"5A\">Opcode: 5A     => LD E,D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:5A  M1      MREQ RD                    | Opcode read from 000 -> 5A\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"5B\">Opcode: 5B     => LD E,E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:5B  M1      MREQ RD                    | Opcode read from 000 -> 5B\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"5C\">Opcode: 5C     => LD E,H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:5C  M1      MREQ RD                    | Opcode read from 000 -> 5C\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"5D\">Opcode: 5D     => LD E,L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:5D  M1      MREQ RD                    | Opcode read from 000 -> 5D\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"5E\">Opcode: 5E     => LD E,(HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:5E  M1      MREQ RD                    | Opcode read from 000 -> 5E\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:003 DB:--                                     | \n#006H T6  AB:003 DB:03          MREQ RD                    | Memory read from 003 -> 03\n#007H T7  AB:003 DB:03          MREQ RD                    | Memory read from 003 -> 03\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"5F\">Opcode: 5F     => LD E,A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:5F  M1      MREQ RD                    | Opcode read from 000 -> 5F\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"60\">Opcode: 60     => LD H,B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:60  M1      MREQ RD                    | Opcode read from 000 -> 60\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"61\">Opcode: 61     => LD H,C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:61  M1      MREQ RD                    | Opcode read from 000 -> 61\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"62\">Opcode: 62     => LD H,D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:62  M1      MREQ RD                    | Opcode read from 000 -> 62\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"63\">Opcode: 63     => LD H,E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:63  M1      MREQ RD                    | Opcode read from 000 -> 63\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"64\">Opcode: 64     => LD H,H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:64  M1      MREQ RD                    | Opcode read from 000 -> 64\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"65\">Opcode: 65     => LD H,L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:65  M1      MREQ RD                    | Opcode read from 000 -> 65\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"66\">Opcode: 66     => LD H,(HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:66  M1      MREQ RD                    | Opcode read from 000 -> 66\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:003 DB:--                                     | \n#006H T6  AB:003 DB:03          MREQ RD                    | Memory read from 003 -> 03\n#007H T7  AB:003 DB:03          MREQ RD                    | Memory read from 003 -> 03\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"67\">Opcode: 67     => LD H,A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:67  M1      MREQ RD                    | Opcode read from 000 -> 67\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"68\">Opcode: 68     => LD L,B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:68  M1      MREQ RD                    | Opcode read from 000 -> 68\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"69\">Opcode: 69     => LD L,C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:69  M1      MREQ RD                    | Opcode read from 000 -> 69\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"6A\">Opcode: 6A     => LD L,D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:6A  M1      MREQ RD                    | Opcode read from 000 -> 6A\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"6B\">Opcode: 6B     => LD L,E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:6B  M1      MREQ RD                    | Opcode read from 000 -> 6B\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"6C\">Opcode: 6C     => LD L,H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:6C  M1      MREQ RD                    | Opcode read from 000 -> 6C\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"6D\">Opcode: 6D     => LD L,L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:6D  M1      MREQ RD                    | Opcode read from 000 -> 6D\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"6E\">Opcode: 6E     => LD L,(HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:6E  M1      MREQ RD                    | Opcode read from 000 -> 6E\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"6F\">Opcode: 6F     => LD L,A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:6F  M1      MREQ RD                    | Opcode read from 000 -> 6F\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"70\">Opcode: 70     => LD (HL),B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:70  M1      MREQ RD                    | Opcode read from 000 -> 70\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ                       | \n#007H T7  AB:001 DB:01          MREQ    WR                 | Memory write to  001 <- 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"71\">Opcode: 71     => LD (HL),C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:71  M1      MREQ RD                    | Opcode read from 000 -> 71\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ                       | \n#007H T7  AB:001 DB:01          MREQ    WR                 | Memory write to  001 <- 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"72\">Opcode: 72     => LD (HL),D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:72  M1      MREQ RD                    | Opcode read from 000 -> 72\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ                       | \n#007H T7  AB:001 DB:01          MREQ    WR                 | Memory write to  001 <- 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"73\">Opcode: 73     => LD (HL),E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:73  M1      MREQ RD                    | Opcode read from 000 -> 73\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ                       | \n#007H T7  AB:001 DB:01          MREQ    WR                 | Memory write to  001 <- 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"74\">Opcode: 74     => LD (HL),H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:74  M1      MREQ RD                    | Opcode read from 000 -> 74\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ                       | \n#007H T7  AB:001 DB:01          MREQ    WR                 | Memory write to  001 <- 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"75\">Opcode: 75     => LD (HL),L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:75  M1      MREQ RD                    | Opcode read from 000 -> 75\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ                       | \n#007H T7  AB:001 DB:01          MREQ    WR                 | Memory write to  001 <- 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"76\">Opcode: 76     => HALT</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:76  M1      MREQ RD                    | Opcode read from 000 -> 76\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"77\">Opcode: 77     => LD (HL),A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:77  M1      MREQ RD                    | Opcode read from 000 -> 77\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ                       | \n#007H T7  AB:001 DB:01          MREQ    WR                 | Memory write to  001 <- 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"78\">Opcode: 78     => LD A,B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:78  M1      MREQ RD                    | Opcode read from 000 -> 78\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"79\">Opcode: 79     => LD A,C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:79  M1      MREQ RD                    | Opcode read from 000 -> 79\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"7A\">Opcode: 7A     => LD A,D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:7A  M1      MREQ RD                    | Opcode read from 000 -> 7A\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"7B\">Opcode: 7B     => LD A,E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:7B  M1      MREQ RD                    | Opcode read from 000 -> 7B\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"7C\">Opcode: 7C     => LD A,H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:7C  M1      MREQ RD                    | Opcode read from 000 -> 7C\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"7D\">Opcode: 7D     => LD A,L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:7D  M1      MREQ RD                    | Opcode read from 000 -> 7D\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"7E\">Opcode: 7E     => LD A,(HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:7E  M1      MREQ RD                    | Opcode read from 000 -> 7E\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"7F\">Opcode: 7F     => LD A,A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:7F  M1      MREQ RD                    | Opcode read from 000 -> 7F\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"80\">Opcode: 80     => ADD A,B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:80  M1      MREQ RD                    | Opcode read from 000 -> 80\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"81\">Opcode: 81     => ADD A,C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:81  M1      MREQ RD                    | Opcode read from 000 -> 81\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"82\">Opcode: 82     => ADD A,D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:82  M1      MREQ RD                    | Opcode read from 000 -> 82\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"83\">Opcode: 83     => ADD A,E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:83  M1      MREQ RD                    | Opcode read from 000 -> 83\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"84\">Opcode: 84     => ADD A,H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:84  M1      MREQ RD                    | Opcode read from 000 -> 84\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"85\">Opcode: 85     => ADD A,L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:85  M1      MREQ RD                    | Opcode read from 000 -> 85\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"86\">Opcode: 86     => ADD A,(HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:86  M1      MREQ RD                    | Opcode read from 000 -> 86\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"87\">Opcode: 87     => ADD A,A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:87  M1      MREQ RD                    | Opcode read from 000 -> 87\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"88\">Opcode: 88     => ADC A,B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:88  M1      MREQ RD                    | Opcode read from 000 -> 88\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"89\">Opcode: 89     => ADC A,C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:89  M1      MREQ RD                    | Opcode read from 000 -> 89\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"8A\">Opcode: 8A     => ADC A,D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:8A  M1      MREQ RD                    | Opcode read from 000 -> 8A\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"8B\">Opcode: 8B     => ADC A,E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:8B  M1      MREQ RD                    | Opcode read from 000 -> 8B\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"8C\">Opcode: 8C     => ADC A,H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:8C  M1      MREQ RD                    | Opcode read from 000 -> 8C\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"8D\">Opcode: 8D     => ADC A,L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:8D  M1      MREQ RD                    | Opcode read from 000 -> 8D\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"8E\">Opcode: 8E     => ADC A,(HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:8E  M1      MREQ RD                    | Opcode read from 000 -> 8E\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"8F\">Opcode: 8F     => ADC A,A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:8F  M1      MREQ RD                    | Opcode read from 000 -> 8F\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"90\">Opcode: 90     => SUB B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:90  M1      MREQ RD                    | Opcode read from 000 -> 90\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"91\">Opcode: 91     => SUB C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:91  M1      MREQ RD                    | Opcode read from 000 -> 91\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"92\">Opcode: 92     => SUB D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:92  M1      MREQ RD                    | Opcode read from 000 -> 92\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"93\">Opcode: 93     => SUB E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:93  M1      MREQ RD                    | Opcode read from 000 -> 93\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"94\">Opcode: 94     => SUB H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:94  M1      MREQ RD                    | Opcode read from 000 -> 94\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"95\">Opcode: 95     => SUB L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:95  M1      MREQ RD                    | Opcode read from 000 -> 95\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"96\">Opcode: 96     => SUB (HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:96  M1      MREQ RD                    | Opcode read from 000 -> 96\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"97\">Opcode: 97     => SUB A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:97  M1      MREQ RD                    | Opcode read from 000 -> 97\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"98\">Opcode: 98     => SBC A,B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:98  M1      MREQ RD                    | Opcode read from 000 -> 98\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"99\">Opcode: 99     => SBC A,C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:99  M1      MREQ RD                    | Opcode read from 000 -> 99\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"9A\">Opcode: 9A     => SBC A,D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:9A  M1      MREQ RD                    | Opcode read from 000 -> 9A\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"9B\">Opcode: 9B     => SBC A,E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:9B  M1      MREQ RD                    | Opcode read from 000 -> 9B\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"9C\">Opcode: 9C     => SBC A,H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:9C  M1      MREQ RD                    | Opcode read from 000 -> 9C\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"9D\">Opcode: 9D     => SBC A,L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:9D  M1      MREQ RD                    | Opcode read from 000 -> 9D\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"9E\">Opcode: 9E     => SBC A,(HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:9E  M1      MREQ RD                    | Opcode read from 000 -> 9E\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"9F\">Opcode: 9F     => SBC A,A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:9F  M1      MREQ RD                    | Opcode read from 000 -> 9F\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"A0\">Opcode: A0     => AND B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:A0  M1      MREQ RD                    | Opcode read from 000 -> A0\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"A1\">Opcode: A1     => AND C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:A1  M1      MREQ RD                    | Opcode read from 000 -> A1\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"A2\">Opcode: A2     => AND D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:A2  M1      MREQ RD                    | Opcode read from 000 -> A2\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"A3\">Opcode: A3     => AND E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:A3  M1      MREQ RD                    | Opcode read from 000 -> A3\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"A4\">Opcode: A4     => AND H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:A4  M1      MREQ RD                    | Opcode read from 000 -> A4\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"A5\">Opcode: A5     => AND L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:A5  M1      MREQ RD                    | Opcode read from 000 -> A5\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"A6\">Opcode: A6     => AND (HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:A6  M1      MREQ RD                    | Opcode read from 000 -> A6\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"A7\">Opcode: A7     => AND A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:A7  M1      MREQ RD                    | Opcode read from 000 -> A7\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"A8\">Opcode: A8     => XOR B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:A8  M1      MREQ RD                    | Opcode read from 000 -> A8\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"A9\">Opcode: A9     => XOR C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:A9  M1      MREQ RD                    | Opcode read from 000 -> A9\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"AA\">Opcode: AA     => XOR D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:AA  M1      MREQ RD                    | Opcode read from 000 -> AA\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"AB\">Opcode: AB     => XOR E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:AB  M1      MREQ RD                    | Opcode read from 000 -> AB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"AC\">Opcode: AC     => XOR H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:AC  M1      MREQ RD                    | Opcode read from 000 -> AC\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"AD\">Opcode: AD     => XOR L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:AD  M1      MREQ RD                    | Opcode read from 000 -> AD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"AE\">Opcode: AE     => XOR (HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:AE  M1      MREQ RD                    | Opcode read from 000 -> AE\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"AF\">Opcode: AF     => XOR A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:AF  M1      MREQ RD                    | Opcode read from 000 -> AF\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"B0\">Opcode: B0     => OR B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:B0  M1      MREQ RD                    | Opcode read from 000 -> B0\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"B1\">Opcode: B1     => OR C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:B1  M1      MREQ RD                    | Opcode read from 000 -> B1\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"B2\">Opcode: B2     => OR D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:B2  M1      MREQ RD                    | Opcode read from 000 -> B2\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"B3\">Opcode: B3     => OR E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:B3  M1      MREQ RD                    | Opcode read from 000 -> B3\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"B4\">Opcode: B4     => OR H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:B4  M1      MREQ RD                    | Opcode read from 000 -> B4\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"B5\">Opcode: B5     => OR L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:B5  M1      MREQ RD                    | Opcode read from 000 -> B5\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"B6\">Opcode: B6     => OR (HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:B6  M1      MREQ RD                    | Opcode read from 000 -> B6\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"B7\">Opcode: B7     => OR A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:B7  M1      MREQ RD                    | Opcode read from 000 -> B7\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"B8\">Opcode: B8     => CP B</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:B8  M1      MREQ RD                    | Opcode read from 000 -> B8\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"B9\">Opcode: B9     => CP C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:B9  M1      MREQ RD                    | Opcode read from 000 -> B9\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"BA\">Opcode: BA     => CP D</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:BA  M1      MREQ RD                    | Opcode read from 000 -> BA\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"BB\">Opcode: BB     => CP E</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:BB  M1      MREQ RD                    | Opcode read from 000 -> BB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"BC\">Opcode: BC     => CP H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:BC  M1      MREQ RD                    | Opcode read from 000 -> BC\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"BD\">Opcode: BD     => CP L</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:BD  M1      MREQ RD                    | Opcode read from 000 -> BD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"BE\">Opcode: BE     => CP (HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:BE  M1      MREQ RD                    | Opcode read from 000 -> BE\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"BF\">Opcode: BF     => CP A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:BF  M1      MREQ RD                    | Opcode read from 000 -> BF\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"C0\">Opcode: C0     => RET NZ</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:C0  M1      MREQ RD                    | Opcode read from 000 -> C0\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"C1\">Opcode: C1     => POP BC</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:C1  M1      MREQ RD                    | Opcode read from 000 -> C1\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#008H T8  AB:002 DB:--                                     | \n#009H T9  AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n#010H T10 AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"C2\">Opcode: C2 n n => JP NZ,nn</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:C2  M1      MREQ RD                    | Opcode read from 000 -> C2\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#008H T8  AB:002 DB:--                                     | \n#009H T9  AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n#010H T10 AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"C3\">Opcode: C3 n n => JP nn</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:C3  M1      MREQ RD                    | Opcode read from 000 -> C3\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#008H T8  AB:002 DB:--                                     | \n#009H T9  AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n#010H T10 AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"C4\">Opcode: C4 n n => CALL NZ,nn</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:C4  M1      MREQ RD                    | Opcode read from 000 -> C4\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#008H T8  AB:002 DB:--                                     | \n#009H T9  AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n#010H T10 AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"C5\">Opcode: C5     => PUSH BC</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:C5  M1      MREQ RD                    | Opcode read from 000 -> C5\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:000 DB:--                                     | \n#006H T6  AB:002 DB:--                                     | \n#007H T7  AB:002 DB:02          MREQ                       | \n#008H T8  AB:002 DB:02          MREQ    WR                 | Memory write to  002 <- 02\n#009H T9  AB:001 DB:--                                     | \n#010H T10 AB:001 DB:01          MREQ                       | \n#011H T11 AB:001 DB:01          MREQ    WR                 | Memory write to  001 <- 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"C6\">Opcode: C6 n   => ADD A,n</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:C6  M1      MREQ RD                    | Opcode read from 000 -> C6\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"C7\">Opcode: C7     => RST 0H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:C7  M1      MREQ RD                    | Opcode read from 000 -> C7\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:000 DB:--                                     | \n#006H T6  AB:000 DB:--                                     | \n#007H T7  AB:000 DB:00          MREQ                       | \n#008H T8  AB:000 DB:00          MREQ    WR                 | Memory write to  000 <- 00\n#009H T9  AB:0FF DB:--                                     | \n#010H T10 AB:0FF DB:01          MREQ                       | \n#011H T11 AB:0FF DB:01          MREQ    WR                 | Memory write to  0FF <- 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"C8\">Opcode: C8     => RET Z</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:C8  M1      MREQ RD                    | Opcode read from 000 -> C8\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"C9\">Opcode: C9     => RET</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:C9  M1      MREQ RD                    | Opcode read from 000 -> C9\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:0FF DB:--                                     | \n#006H T6  AB:0FF DB:01          MREQ RD                    | Memory read from 0FF -> 01\n#007H T7  AB:0FF DB:01          MREQ RD                    | Memory read from 0FF -> 01\n#008H T8  AB:000 DB:--                                     | \n#009H T9  AB:000 DB:C9          MREQ RD                    | Memory read from 000 -> C9\n#010H T10 AB:000 DB:C9          MREQ RD                    | Memory read from 000 -> C9\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"CA\">Opcode: CA n n => JP Z,nn</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CA  M1      MREQ RD                    | Opcode read from 000 -> CA\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#008H T8  AB:002 DB:--                                     | \n#009H T9  AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n#010H T10 AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"CB\">Opcode: CB     => CB</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CB  M1      MREQ RD                    | Opcode read from 000 -> CB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"CC\">Opcode: CC n n => CALL Z,nn</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CC  M1      MREQ RD                    | Opcode read from 000 -> CC\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#008H T8  AB:002 DB:--                                     | \n#009H T9  AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n#010H T10 AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"CD\">Opcode: CD n n => CALL nn</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CD  M1      MREQ RD                    | Opcode read from 000 -> CD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#008H T8  AB:002 DB:--                                     | \n#009H T9  AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n#010H T10 AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n#011H T11 AB:002 DB:--                                     | \n#012H T12 AB:000 DB:--                                     | \n#013H T13 AB:000 DB:00          MREQ                       | \n#014H T14 AB:000 DB:00          MREQ    WR                 | Memory write to  000 <- 00\n#015H T15 AB:0FF DB:--                                     | \n#016H T16 AB:0FF DB:03          MREQ                       | \n#017H T17 AB:0FF DB:03          MREQ    WR                 | Memory write to  0FF <- 03\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"CE\">Opcode: CE n   => ADC A,n</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CE  M1      MREQ RD                    | Opcode read from 000 -> CE\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"CF\">Opcode: CF     => RST 8H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:CF  M1      MREQ RD                    | Opcode read from 000 -> CF\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:000 DB:--                                     | \n#006H T6  AB:0FE DB:--                                     | \n#007H T7  AB:0FE DB:00          MREQ                       | \n#008H T8  AB:0FE DB:00          MREQ    WR                 | Memory write to  0FE <- 00\n#009H T9  AB:0FD DB:--                                     | \n#010H T10 AB:0FD DB:01          MREQ                       | \n#011H T11 AB:0FD DB:01          MREQ    WR                 | Memory write to  0FD <- 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"D0\">Opcode: D0     => RET NC</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:D0  M1      MREQ RD                    | Opcode read from 000 -> D0\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:000 DB:--                                     | \n#006H T6  AB:0FD DB:--                                     | \n#007H T7  AB:0FD DB:01          MREQ RD                    | Memory read from 0FD -> 01\n#008H T8  AB:0FD DB:01          MREQ RD                    | Memory read from 0FD -> 01\n#009H T9  AB:0FE DB:--                                     | \n#010H T10 AB:0FE DB:00          MREQ RD                    | Memory read from 0FE -> 00\n#011H T11 AB:0FE DB:00          MREQ RD                    | Memory read from 0FE -> 00\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"D1\">Opcode: D1     => POP DE</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:D1  M1      MREQ RD                    | Opcode read from 000 -> D1\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:0FF DB:--                                     | \n#006H T6  AB:0FF DB:03          MREQ RD                    | Memory read from 0FF -> 03\n#007H T7  AB:0FF DB:03          MREQ RD                    | Memory read from 0FF -> 03\n#008H T8  AB:000 DB:--                                     | \n#009H T9  AB:000 DB:D1          MREQ RD                    | Memory read from 000 -> D1\n#010H T10 AB:000 DB:D1          MREQ RD                    | Memory read from 000 -> D1\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"D2\">Opcode: D2 n n => JP NC,nn</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:D2  M1      MREQ RD                    | Opcode read from 000 -> D2\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#008H T8  AB:002 DB:--                                     | \n#009H T9  AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n#010H T10 AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"D3\">Opcode: D3 n   => OUT (n),A</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:D3  M1      MREQ RD                    | Opcode read from 000 -> D3\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#008H T8  AB:001 DB:--                                     | \n#009H T9  AB:001 DB:03                  WR IORQ            | I/O write to 001 <- 03\n#010H T10 AB:001 DB:03                  WR IORQ            | I/O write to 001 <- 03\n#011H T11 AB:001 DB:03                  WR IORQ            | I/O write to 001 <- 03\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"D4\">Opcode: D4 n n => CALL NC,nn</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:D4  M1      MREQ RD                    | Opcode read from 000 -> D4\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#008H T8  AB:002 DB:--                                     | \n#009H T9  AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n#010H T10 AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n#011H T11 AB:002 DB:--                                     | \n#012H T12 AB:000 DB:--                                     | \n#013H T13 AB:000 DB:00          MREQ                       | \n#014H T14 AB:000 DB:00          MREQ    WR                 | Memory write to  000 <- 00\n#015H T15 AB:0FF DB:--                                     | \n#016H T16 AB:0FF DB:03          MREQ                       | \n#017H T17 AB:0FF DB:03          MREQ    WR                 | Memory write to  0FF <- 03\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"D5\">Opcode: D5     => PUSH DE</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:D5  M1      MREQ RD                    | Opcode read from 000 -> D5\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:000 DB:--                                     | \n#006H T6  AB:0FE DB:--                                     | \n#007H T7  AB:0FE DB:D1          MREQ                       | \n#008H T8  AB:0FE DB:D1          MREQ    WR                 | Memory write to  0FE <- D1\n#009H T9  AB:0FD DB:--                                     | \n#010H T10 AB:0FD DB:03          MREQ                       | \n#011H T11 AB:0FD DB:03          MREQ    WR                 | Memory write to  0FD <- 03\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"D6\">Opcode: D6 n   => SUB n</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:D6  M1      MREQ RD                    | Opcode read from 000 -> D6\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"D7\">Opcode: D7     => RST 10H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:D7  M1      MREQ RD                    | Opcode read from 000 -> D7\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:000 DB:--                                     | \n#006H T6  AB:0FC DB:--                                     | \n#007H T7  AB:0FC DB:00          MREQ                       | \n#008H T8  AB:0FC DB:00          MREQ    WR                 | Memory write to  0FC <- 00\n#009H T9  AB:0FB DB:--                                     | \n#010H T10 AB:0FB DB:01          MREQ                       | \n#011H T11 AB:0FB DB:01          MREQ    WR                 | Memory write to  0FB <- 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"D8\">Opcode: D8     => RET C</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:D8  M1      MREQ RD                    | Opcode read from 000 -> D8\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"D9\">Opcode: D9     => EXX</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:D9  M1      MREQ RD                    | Opcode read from 000 -> D9\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"DA\">Opcode: DA n n => JP C,nn</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DA  M1      MREQ RD                    | Opcode read from 000 -> DA\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#008H T8  AB:002 DB:--                                     | \n#009H T9  AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n#010H T10 AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"DB\">Opcode: DB n   => IN A,(n)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DB  M1      MREQ RD                    | Opcode read from 000 -> DB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#008H T8  AB:001 DB:--                                     | \n#009H T9  AB:001 DB:--               RD    IORQ            | I/O read from 001\n#010H T10 AB:001 DB:--               RD    IORQ            | I/O read from 001\n#011H T11 AB:001 DB:--               RD    IORQ            | I/O read from 001\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"DC\">Opcode: DC n n => CALL C,nn</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DC  M1      MREQ RD                    | Opcode read from 000 -> DC\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#008H T8  AB:002 DB:--                                     | \n#009H T9  AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n#010H T10 AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"DD\">Opcode: DD     => DD</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DD  M1      MREQ RD                    | Opcode read from 000 -> DD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"DE\">Opcode: DE n   => SBC A,n</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DE  M1      MREQ RD                    | Opcode read from 000 -> DE\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"DF\">Opcode: DF     => RST 18H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:DF  M1      MREQ RD                    | Opcode read from 000 -> DF\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:000 DB:--                                     | \n#006H T6  AB:0FA DB:--                                     | \n#007H T7  AB:0FA DB:00          MREQ                       | \n#008H T8  AB:0FA DB:00          MREQ    WR                 | Memory write to  0FA <- 00\n#009H T9  AB:0F9 DB:--                                     | \n#010H T10 AB:0F9 DB:01          MREQ                       | \n#011H T11 AB:0F9 DB:01          MREQ    WR                 | Memory write to  0F9 <- 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"E0\">Opcode: E0     => RET PO</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:E0  M1      MREQ RD                    | Opcode read from 000 -> E0\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:000 DB:--                                     | \n#006H T6  AB:0F9 DB:--                                     | \n#007H T7  AB:0F9 DB:01          MREQ RD                    | Memory read from 0F9 -> 01\n#008H T8  AB:0F9 DB:01          MREQ RD                    | Memory read from 0F9 -> 01\n#009H T9  AB:0FA DB:--                                     | \n#010H T10 AB:0FA DB:00          MREQ RD                    | Memory read from 0FA -> 00\n#011H T11 AB:0FA DB:00          MREQ RD                    | Memory read from 0FA -> 00\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"E1\">Opcode: E1     => POP HL</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:E1  M1      MREQ RD                    | Opcode read from 000 -> E1\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:0FB DB:--                                     | \n#006H T6  AB:0FB DB:01          MREQ RD                    | Memory read from 0FB -> 01\n#007H T7  AB:0FB DB:01          MREQ RD                    | Memory read from 0FB -> 01\n#008H T8  AB:0FC DB:--                                     | \n#009H T9  AB:0FC DB:00          MREQ RD                    | Memory read from 0FC -> 00\n#010H T10 AB:0FC DB:00          MREQ RD                    | Memory read from 0FC -> 00\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"E2\">Opcode: E2 n n => JP PO,nn</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:E2  M1      MREQ RD                    | Opcode read from 000 -> E2\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#008H T8  AB:002 DB:--                                     | \n#009H T9  AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n#010H T10 AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"E3\">Opcode: E3     => EX (SP),HL</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:E3  M1      MREQ RD                    | Opcode read from 000 -> E3\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:0FD DB:--                                     | \n#006H T6  AB:0FD DB:03          MREQ RD                    | Memory read from 0FD -> 03\n#007H T7  AB:0FD DB:03          MREQ RD                    | Memory read from 0FD -> 03\n#008H T8  AB:0FE DB:--                                     | \n#009H T9  AB:0FE DB:D1          MREQ RD                    | Memory read from 0FE -> D1\n#010H T10 AB:0FE DB:D1          MREQ RD                    | Memory read from 0FE -> D1\n#011H T11 AB:0FE DB:--                                     | \n#012H T12 AB:0FE DB:--                                     | \n#013H T13 AB:0FE DB:00          MREQ                       | \n#014H T14 AB:0FE DB:00          MREQ    WR                 | Memory write to  0FE <- 00\n#015H T15 AB:0FD DB:--                                     | \n#016H T16 AB:0FD DB:01          MREQ                       | \n#017H T17 AB:0FD DB:01          MREQ    WR                 | Memory write to  0FD <- 01\n#018H T18 AB:0FD DB:01                                     | \n#019H T19 AB:0FD DB:01                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"E4\">Opcode: E4 n n => CALL PO,nn</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:E4  M1      MREQ RD                    | Opcode read from 000 -> E4\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#008H T8  AB:002 DB:--                                     | \n#009H T9  AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n#010H T10 AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n#011H T11 AB:002 DB:--                                     | \n#012H T12 AB:0FC DB:--                                     | \n#013H T13 AB:0FC DB:00          MREQ                       | \n#014H T14 AB:0FC DB:00          MREQ    WR                 | Memory write to  0FC <- 00\n#015H T15 AB:0FB DB:--                                     | \n#016H T16 AB:0FB DB:03          MREQ                       | \n#017H T17 AB:0FB DB:03          MREQ    WR                 | Memory write to  0FB <- 03\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"E5\">Opcode: E5     => PUSH HL</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:E5  M1      MREQ RD                    | Opcode read from 000 -> E5\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:000 DB:--                                     | \n#006H T6  AB:0FA DB:--                                     | \n#007H T7  AB:0FA DB:D1          MREQ                       | \n#008H T8  AB:0FA DB:D1          MREQ    WR                 | Memory write to  0FA <- D1\n#009H T9  AB:0F9 DB:--                                     | \n#010H T10 AB:0F9 DB:03          MREQ                       | \n#011H T11 AB:0F9 DB:03          MREQ    WR                 | Memory write to  0F9 <- 03\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"E6\">Opcode: E6 n   => AND n</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:E6  M1      MREQ RD                    | Opcode read from 000 -> E6\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"E7\">Opcode: E7     => RST 20H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:E7  M1      MREQ RD                    | Opcode read from 000 -> E7\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:000 DB:--                                     | \n#006H T6  AB:0F8 DB:--                                     | \n#007H T7  AB:0F8 DB:00          MREQ                       | \n#008H T8  AB:0F8 DB:00          MREQ    WR                 | Memory write to  0F8 <- 00\n#009H T9  AB:0F7 DB:--                                     | \n#010H T10 AB:0F7 DB:01          MREQ                       | \n#011H T11 AB:0F7 DB:01          MREQ    WR                 | Memory write to  0F7 <- 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"E8\">Opcode: E8     => RET PE</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:E8  M1      MREQ RD                    | Opcode read from 000 -> E8\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:000 DB:--                                     | \n#006H T6  AB:0F7 DB:--                                     | \n#007H T7  AB:0F7 DB:01          MREQ RD                    | Memory read from 0F7 -> 01\n#008H T8  AB:0F7 DB:01          MREQ RD                    | Memory read from 0F7 -> 01\n#009H T9  AB:0F8 DB:--                                     | \n#010H T10 AB:0F8 DB:00          MREQ RD                    | Memory read from 0F8 -> 00\n#011H T11 AB:0F8 DB:00          MREQ RD                    | Memory read from 0F8 -> 00\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"E9\">Opcode: E9     => JP (HL)</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:E9  M1      MREQ RD                    | Opcode read from 000 -> E9\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"EA\">Opcode: EA n n => JP PE,nn</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:EA  M1      MREQ RD                    | Opcode read from 000 -> EA\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#008H T8  AB:002 DB:--                                     | \n#009H T9  AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n#010H T10 AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"EB\">Opcode: EB     => EX DE,HL</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:EB  M1      MREQ RD                    | Opcode read from 000 -> EB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"EC\">Opcode: EC n n => CALL PE,nn</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:EC  M1      MREQ RD                    | Opcode read from 000 -> EC\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#008H T8  AB:002 DB:--                                     | \n#009H T9  AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n#010H T10 AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n#011H T11 AB:002 DB:--                                     | \n#012H T12 AB:0F8 DB:--                                     | \n#013H T13 AB:0F8 DB:00          MREQ                       | \n#014H T14 AB:0F8 DB:00          MREQ    WR                 | Memory write to  0F8 <- 00\n#015H T15 AB:0F7 DB:--                                     | \n#016H T16 AB:0F7 DB:03          MREQ                       | \n#017H T17 AB:0F7 DB:03          MREQ    WR                 | Memory write to  0F7 <- 03\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"ED\">Opcode: ED     => ED</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:ED  M1      MREQ RD                    | Opcode read from 000 -> ED\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"EE\">Opcode: EE n   => XOR n</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:EE  M1      MREQ RD                    | Opcode read from 000 -> EE\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"EF\">Opcode: EF     => RST 28H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:EF  M1      MREQ RD                    | Opcode read from 000 -> EF\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:000 DB:--                                     | \n#006H T6  AB:0F6 DB:--                                     | \n#007H T7  AB:0F6 DB:00          MREQ                       | \n#008H T8  AB:0F6 DB:00          MREQ    WR                 | Memory write to  0F6 <- 00\n#009H T9  AB:0F5 DB:--                                     | \n#010H T10 AB:0F5 DB:01          MREQ                       | \n#011H T11 AB:0F5 DB:01          MREQ    WR                 | Memory write to  0F5 <- 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"F0\">Opcode: F0     => RET P</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:F0  M1      MREQ RD                    | Opcode read from 000 -> F0\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:000 DB:--                                     | \n#006H T6  AB:0F5 DB:--                                     | \n#007H T7  AB:0F5 DB:01          MREQ RD                    | Memory read from 0F5 -> 01\n#008H T8  AB:0F5 DB:01          MREQ RD                    | Memory read from 0F5 -> 01\n#009H T9  AB:0F6 DB:--                                     | \n#010H T10 AB:0F6 DB:00          MREQ RD                    | Memory read from 0F6 -> 00\n#011H T11 AB:0F6 DB:00          MREQ RD                    | Memory read from 0F6 -> 00\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"F1\">Opcode: F1     => POP AF</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:F1  M1      MREQ RD                    | Opcode read from 000 -> F1\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:0F7 DB:--                                     | \n#006H T6  AB:0F7 DB:03          MREQ RD                    | Memory read from 0F7 -> 03\n#007H T7  AB:0F7 DB:03          MREQ RD                    | Memory read from 0F7 -> 03\n#008H T8  AB:0F8 DB:--                                     | \n#009H T9  AB:0F8 DB:00          MREQ RD                    | Memory read from 0F8 -> 00\n#010H T10 AB:0F8 DB:00          MREQ RD                    | Memory read from 0F8 -> 00\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"F2\">Opcode: F2 n n => JP P,nn</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:F2  M1      MREQ RD                    | Opcode read from 000 -> F2\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#008H T8  AB:002 DB:--                                     | \n#009H T9  AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n#010H T10 AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"F3\">Opcode: F3     => DI</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:F3  M1      MREQ RD                    | Opcode read from 000 -> F3\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"F4\">Opcode: F4 n n => CALL P,nn</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:F4  M1      MREQ RD                    | Opcode read from 000 -> F4\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#008H T8  AB:002 DB:--                                     | \n#009H T9  AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n#010H T10 AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n#011H T11 AB:002 DB:--                                     | \n#012H T12 AB:0F8 DB:--                                     | \n#013H T13 AB:0F8 DB:00          MREQ                       | \n#014H T14 AB:0F8 DB:00          MREQ    WR                 | Memory write to  0F8 <- 00\n#015H T15 AB:0F7 DB:--                                     | \n#016H T16 AB:0F7 DB:03          MREQ                       | \n#017H T17 AB:0F7 DB:03          MREQ    WR                 | Memory write to  0F7 <- 03\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"F5\">Opcode: F5     => PUSH AF</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:F5  M1      MREQ RD                    | Opcode read from 000 -> F5\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:000 DB:--                                     | \n#006H T6  AB:0F6 DB:--                                     | \n#007H T7  AB:0F6 DB:00          MREQ                       | \n#008H T8  AB:0F6 DB:00          MREQ    WR                 | Memory write to  0F6 <- 00\n#009H T9  AB:0F5 DB:--                                     | \n#010H T10 AB:0F5 DB:03          MREQ                       | \n#011H T11 AB:0F5 DB:03          MREQ    WR                 | Memory write to  0F5 <- 03\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"F6\">Opcode: F6 n   => OR n</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:F6  M1      MREQ RD                    | Opcode read from 000 -> F6\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"F7\">Opcode: F7     => RST 30H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:F7  M1      MREQ RD                    | Opcode read from 000 -> F7\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:000 DB:--                                     | \n#006H T6  AB:0F4 DB:--                                     | \n#007H T7  AB:0F4 DB:00          MREQ                       | \n#008H T8  AB:0F4 DB:00          MREQ    WR                 | Memory write to  0F4 <- 00\n#009H T9  AB:0F3 DB:--                                     | \n#010H T10 AB:0F3 DB:01          MREQ                       | \n#011H T11 AB:0F3 DB:01          MREQ    WR                 | Memory write to  0F3 <- 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"F8\">Opcode: F8     => RET M</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:F8  M1      MREQ RD                    | Opcode read from 000 -> F8\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"F9\">Opcode: F9     => LD SP,HL</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:F9  M1      MREQ RD                    | Opcode read from 000 -> F9\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:000 DB:--                                     | \n#006H T6  AB:000 DB:--                                     | \n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"FA\">Opcode: FA n n => JP M,nn</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:FA  M1      MREQ RD                    | Opcode read from 000 -> FA\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#008H T8  AB:002 DB:--                                     | \n#009H T9  AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n#010H T10 AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"FB\">Opcode: FB     => EI</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:FB  M1      MREQ RD                    | Opcode read from 000 -> FB\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"FC\">Opcode: FC n n => CALL M,nn</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:FC  M1      MREQ RD                    | Opcode read from 000 -> FC\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#008H T8  AB:002 DB:--                                     | \n#009H T9  AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n#010H T10 AB:002 DB:02          MREQ RD                    | Memory read from 002 -> 02\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"FD\">Opcode: FD     => FD</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:FD  M1      MREQ RD                    | Opcode read from 000 -> FD\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"FE\">Opcode: FE n   => CP n</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:FE  M1      MREQ RD                    | Opcode read from 000 -> FE\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:001 DB:--                                     | \n#006H T6  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n#007H T7  AB:001 DB:01          MREQ RD                    | Memory read from 001 -> 01\n-----------------------------------------------------------+\n</PRE>\n<H3 id=\"FF\">Opcode: FF     => RST 38H</H3>\n<PRE>\n-----------------------------------------------------------+\n#001H T1  AB:000 DB:--  M1                                 | \n#002H T2  AB:000 DB:FF  M1      MREQ RD                    | Opcode read from 000 -> FF\n#003H T3  AB:000 DB:--     RFSH                            | \n#004H T4  AB:000 DB:--     RFSH MREQ                       | Refresh address  000\n#005H T5  AB:000 DB:--                                     | \n#006H T6  AB:002 DB:--                                     | \n#007H T7  AB:002 DB:00          MREQ                       | \n#008H T8  AB:002 DB:00          MREQ    WR                 | Memory write to  002 <- 00\n#009H T9  AB:001 DB:--                                     | \n#010H T10 AB:001 DB:01          MREQ                       | \n#011H T11 AB:001 DB:01          MREQ    WR                 | Memory write to  001 <- 01\n-----------------------------------------------------------+\n</PRE>\n</BODY></HTML>\n"
  },
  {
    "path": "tools/dongle/z80-instruction-run-cb.py",
    "content": "#!/usr/bin/env python\n#\n# This script is used to dump Z80 instruction timing data by running the\n# instructions through the Arduino Z80 dongle and parsing the dump output.\n# It needs:\n#   1. Arduino Z80 dongle: http://www.baltazarstudios.com\n#   2. Instructions data file: '../../resources/opcodes-??.txt'\n# Needs pyserial from https://pypi.python.org/pypi/pyserial\n#\nimport serial\nimport sys\n\nser = serial.Serial(\"\\\\.\\COM9\", 115200, timeout=1)\n\n# Flush the serial buffer, removes any command response\ndef serialFlush(ser):\n    while 1:\n        indata = ser.readline().rstrip('\\n')\n        if not indata:\n            break\n\ntry:\n    # Open opcode file and read opcode + mnemonics\n    with open('../../resources/opcodes-cb.txt') as tmpFile:\n        ops = [line.rstrip('\\n') for line in tmpFile]\n\n    serialFlush(ser)\n    # Stop after the second M1 cycle effectively running only one instruction\n    ser.write(\"s 4 3\\r\")\n    serialFlush(ser)\n\n    print ('<!DOCTYPE html PUBLIC \"-//W3C//DTD HTML 4.01//EN\">')\n    print ('<HTML><HEAD><TITLE>Z80 Instructions Timing</TITLE></HEAD><BODY>')\n    print ('<H1>Opcodes with CB prefix</H1>')\n    for line in ops:\n        print (line[0:2] + ' ' + line[2:4] + ' .. <A href=\\\"#' + line[2:4] + '\\\">' + line[12:] + '</A><BR>')\n\n    print ('<H1>Instructions Timing</H1>')\n\n    for line in ops:\n        ram = ':10000000' + line[0:4] + '0102030405060708090A0B0C0D00'\n\n        ser.write(ram + '\\r')\n        indata = ser.readline().rstrip('\\n')\n        ser.write('r\\r')\n\n        print ('<H3 id=\\\"' + line[2:4] + '\\\">Opcode: ' + line[0:2] + \" \" + line[2:4] + ' => ' + line[12:] + '</H3>')\n        sys.stderr.write (line + '\\n')\n\n        # Skip initial response from Arduino, includes two empty cycles after the reset\n        for x in range(1,7):\n            indata = ser.readline()\n\n        print ('<PRE>')\n        while 1:\n            indata = ser.readline()\n            if not indata:\n                break\n            if indata[0]!=':':\n                print (indata.rstrip('\\r\\n'))\n        print ('</PRE>')\n\n    print ('</BODY></HTML>')\n\nexcept KeyboardInterrupt:\n     ser.close()\n"
  },
  {
    "path": "tools/dongle/z80-instruction-run-dd-cb.py",
    "content": "#!/usr/bin/env python\n#\n# This script is used to dump Z80 instruction timing data by running the\n# instructions through the Arduino Z80 dongle and parsing the dump output.\n# It needs:\n#   1. Arduino Z80 dongle: http://www.baltazarstudios.com\n#   2. Instructions data file: '../../resources/opcodes-??.txt'\n# Needs pyserial from https://pypi.python.org/pypi/pyserial\n#\nimport serial\nimport sys\n\nser = serial.Serial(\"\\\\.\\COM9\", 115200, timeout=1)\n\n# Flush the serial buffer, removes any command response\ndef serialFlush(ser):\n    while 1:\n        indata = ser.readline().rstrip('\\n')\n        if not indata:\n            break\n\ntry:\n    # Open opcode file and read opcode + mnemonics\n    with open('../../resources/opcodes-dd-cb.txt') as tmpFile:\n        ops = [line.rstrip('\\n') for line in tmpFile]\n\n    serialFlush(ser)\n    # Stop after the second M1 cycle effectively running only one instruction\n    ser.write(\"s 4 3\\r\")\n    serialFlush(ser)\n\n    print ('<!DOCTYPE html PUBLIC \"-//W3C//DTD HTML 4.01//EN\">')\n    print ('<HTML><HEAD><TITLE>Z80 Instructions Timing</TITLE></HEAD><BODY>')\n    print ('<H1>Opcodes with DD/FD + CB prefix</H1>')\n    for line in ops:\n        print (line[0:2] + ' ' + line[2:4] + ' . ' + line[7:9] + ' .. <A href=\\\"#' + line[7:9] + '\\\">' + line[12:] + '</A><BR>')\n\n    print ('<H1>Instructions Timing</H1>')\n\n    for line in ops:\n        ram = ':10000000' + line[0:4] + '01' + line[7:9] + '02030405060708090A0B0C00'\n\n        ser.write(ram + '\\r')\n        indata = ser.readline().rstrip('\\n')\n        ser.write('r\\r')\n\n        print ('<H3 id=\\\"' + line[7:9] + '\\\">Opcode: ' + line[0:2] + \" \" + line[2:4] + ' d ' + line[7:9] + ' => ' + line[12:] + '</H3>')\n        sys.stderr.write (line + '\\n')\n\n        # Skip initial response from Arduino, includes two empty cycles after the reset\n        for x in range(1,7):\n            indata = ser.readline()\n\n        print ('<PRE>')\n        while 1:\n            indata = ser.readline()\n            if not indata:\n                break\n            if indata[0]!=':':\n                print (indata.rstrip('\\r\\n'))\n        print ('</PRE>')\n\n    print ('</BODY></HTML>')\n\nexcept KeyboardInterrupt:\n     ser.close()\n"
  },
  {
    "path": "tools/dongle/z80-instruction-run-dd.py",
    "content": "#!/usr/bin/env python\n#\n# This script is used to dump Z80 instruction timing data by running the\n# instructions through the Arduino Z80 dongle and parsing the dump output.\n# It needs:\n#   1. Arduino Z80 dongle: http://www.baltazarstudios.com\n#   2. Instructions data file: '../../resources/opcodes-??.txt'\n# Needs pyserial from https://pypi.python.org/pypi/pyserial\n#\nimport serial\nimport sys\n\nser = serial.Serial(\"\\\\.\\COM9\", 115200, timeout=1)\n\n# Flush the serial buffer, removes any command response\ndef serialFlush(ser):\n    while 1:\n        indata = ser.readline().rstrip('\\n')\n        if not indata:\n            break\n\ntry:\n    # Open opcode file and read opcode + mnemonics\n    with open('../../resources/opcodes-dd.txt') as tmpFile:\n        ops = [line.rstrip('\\n') for line in tmpFile]\n\n    serialFlush(ser)\n    # Stop after the second M1 cycle effectively running only one instruction\n    ser.write(\"s 4 3\\r\")\n    serialFlush(ser)\n\n    print ('<!DOCTYPE html PUBLIC \"-//W3C//DTD HTML 4.01//EN\">')\n    print ('<HTML><HEAD><TITLE>Z80 Instructions Timing</TITLE></HEAD><BODY>')\n    print ('<H1>Opcodes with DD prefix</H1>')\n    for line in ops:\n        print (line[0:2] + ' ' + line[2:4] + ' .. <A href=\\\"#' + line[2:4] + '\\\">' + line[12:] + '</A><BR>')\n\n    print ('<H1>Instructions Timing</H1>')\n\n    for line in ops:\n        ram = ':10000000' + line[0:4] + '0102030405060708090A0B0C0D00'\n\n        ser.write(ram + '\\r')\n        indata = ser.readline().rstrip('\\n')\n        ser.write('r\\r')\n\n        print ('<H3 id=\\\"' + line[2:4] + '\\\">Opcode: ' + line[0:2] + \" \" + line[2:8] + ' => ' + line[12:] + '</H3>')\n        sys.stderr.write (line + '\\n')\n\n        # Skip initial response from Arduino, includes two empty cycles after the reset\n        for x in range(1,7):\n            indata = ser.readline()\n\n        print ('<PRE>')\n        while 1:\n            indata = ser.readline()\n            if not indata:\n                break\n            if indata[0]!=':':\n                print (indata.rstrip('\\r\\n'))\n        print ('</PRE>')\n\n    print ('</BODY></HTML>')\n\nexcept KeyboardInterrupt:\n     ser.close()\n"
  },
  {
    "path": "tools/dongle/z80-instruction-run-ed.py",
    "content": "#!/usr/bin/env python\n#\n# This script is used to dump Z80 instruction timing data by running the\n# instructions through the Arduino Z80 dongle and parsing the dump output.\n# It needs:\n#   1. Arduino Z80 dongle: http://www.baltazarstudios.com\n#   2. Instructions data file: '../../resources/opcodes-??.txt'\n# Needs pyserial from https://pypi.python.org/pypi/pyserial\n#\nimport serial\nimport sys\n\nser = serial.Serial(\"\\\\.\\COM9\", 115200, timeout=1)\n\n# Flush the serial buffer, removes any command response\ndef serialFlush(ser):\n    while 1:\n        indata = ser.readline().rstrip('\\n')\n        if not indata:\n            break\n\ntry:\n    # Open opcode file and read opcode + mnemonics\n    with open('../../resources/opcodes-ed.txt') as tmpFile:\n        ops = [line.rstrip('\\n') for line in tmpFile]\n\n    serialFlush(ser)\n    # Stop after the second M1 cycle effectively running only one instruction\n    ser.write(\"s 4 3\\r\")\n    serialFlush(ser)\n\n    print ('<!DOCTYPE html PUBLIC \"-//W3C//DTD HTML 4.01//EN\">')\n    print ('<HTML><HEAD><TITLE>Z80 Instructions Timing</TITLE></HEAD><BODY>')\n    print ('<H1>Opcodes with ED prefix</H1>')\n    for line in ops:\n        print (line[0:2] + ' ' + line[2:4] + ' .. <A href=\\\"#' + line[2:4] + '\\\">' + line[12:] + '</A><BR>')\n\n    print ('<H1>Instructions Timing</H1>')\n\n    for line in ops:\n        ram = ':10000000' + line[0:4] + '0102030405060708090A0B0C0D00'\n\n        ser.write(ram + '\\r')\n        indata = ser.readline().rstrip('\\n')\n        ser.write('r\\r')\n\n        print ('<H3 id=\\\"' + line[2:4] + '\\\">Opcode: ' + line[0:2] + \" \" + line[2:8] + ' => ' + line[12:] + '</H3>')\n        sys.stderr.write (line + '\\n')\n\n        # Skip initial response from Arduino, includes two empty cycles after the reset\n        for x in range(1,7):\n            indata = ser.readline()\n\n        print ('<PRE>')\n        while 1:\n            indata = ser.readline()\n            if not indata:\n                break\n            if indata[0]!=':':\n                print (indata.rstrip('\\r\\n'))\n        print ('</PRE>')\n\n    print ('</BODY></HTML>')\n\nexcept KeyboardInterrupt:\n     ser.close()\n"
  },
  {
    "path": "tools/dongle/z80-instruction-run-xx.py",
    "content": "#!/usr/bin/env python\n#\n# This script is used to dump Z80 instruction timing data by running the\n# instructions through the Arduino Z80 dongle and parsing the dump output.\n# It needs:\n#   1. Arduino Z80 dongle: http://www.baltazarstudios.com\n#   2. Instructions data file: '../../resources/opcodes-??.txt'\n# Needs pyserial from https://pypi.python.org/pypi/pyserial\n#\nimport serial\nimport sys\n\nser = serial.Serial(\"\\\\.\\COM9\", 115200, timeout=1)\n\n# Flush the serial buffer, removes any command response\ndef serialFlush(ser):\n    while 1:\n        indata = ser.readline().rstrip('\\n')\n        if not indata:\n            break\n\ntry:\n    # Open opcode file and read opcode + mnemonics\n    with open('../../resources/opcodes-xx.txt') as tmpFile:\n        ops = [line.rstrip('\\n') for line in tmpFile]\n\n    serialFlush(ser)\n    # Stop after the first M1 cycle effectively running only one instruction\n    ser.write(\"s 4 2\\r\")\n    serialFlush(ser)\n\n    print ('<!DOCTYPE html PUBLIC \"-//W3C//DTD HTML 4.01//EN\">')\n    print ('<HTML><HEAD><TITLE>Z80 Instructions Timing</TITLE></HEAD><BODY>')\n    print ('<H1>Regular opcodes</H1>')\n    for line in ops:\n        print (line[0:2] + ' .. <A href=\\\"#' + line[0:2] + '\\\">' + line[12:] + '</A><BR>')\n\n    print ('<H1>Instructions Timing</H1>')\n\n    for line in ops:\n        ram = ':10000000' + line[0:2] + '0102030405060708090A0B0C0D0E00'\n\n        ser.write(ram + '\\r')\n        indata = ser.readline().rstrip('\\n')\n        ser.write('r\\r')\n\n        print ('<H3 id=\\\"' + line[0:2] + '\\\">Opcode: ' + line[0:6] + \" => \" + line[12:] + '</H3>')\n        sys.stderr.write (line + '\\n')\n\n        # Skip initial response from Arduino, includes two empty cycles after the reset\n        for x in range(1,7):\n            indata = ser.readline()\n\n        print ('<PRE>')\n        while 1:\n            indata = ser.readline()\n            if not indata:\n                break\n            if indata[0]!=':':\n                print (indata.rstrip('\\r\\n'))\n        print ('</PRE>')\n\n    print ('</BODY></HTML>')\n\nexcept KeyboardInterrupt:\n     ser.close()\n"
  },
  {
    "path": "tools/dongle/z80-instruction-run.bat",
    "content": "python z80-instruction-run-xx.py > xx.html\npython z80-instruction-run-cb.py > cb.html\npython z80-instruction-run-ed.py > ed.html\npython z80-instruction-run-dd.py > dd.html\npython z80-instruction-run-dd-cb.py > ddcb.html\n"
  },
  {
    "path": "tools/readme.txt",
    "content": "This directory contains various tools related to the project:\n\nArduino\n=======\nThe Arduino Mega firmware to be run with a dongle described in this blog:\nhttps://baltazarstudios.com/arduino-zilog-z80\n\n\ndongle\n======\nScripts and files that run Z80 instructions through the Arduino\ndongle to collect timing and functional data.\n\nSome instructions (daa, neg, sbc) have separate simulation scripts\ncontaining functional implementation which is then compared to\nthe response of a physical Z80 CPU (through the dongle).\n\n\nz80_pla_checker\n===============\nA Visual Studio project that loads PLA table and provides interactive\nsimulation of opcodes and logic responses. The program also generates a\nVerilog PLA table source code used in the A-Z80 project.\n\n\nzmac\n====\nA handy Z80 assember.\nVarious assembly source files that test and verify A-Z80 processor.\n"
  },
  {
    "path": "tools/z80_pla_checker/readme.txt",
    "content": "z80_pla_checker\n===============\nExperiment with the Z80 PLA table! The content of the PLA table is published here:\nhttp://arcfn.com/files/z80-pla-table.html\n\nThe master PLA table is in ../resources/z80-pla.txt\n\nOther instruction tables that the tool uses are also in that folder.\n\nThis executable application was written in portable C# and it should run\non Windows as well as on Linux OS with a mono support.\n\nOn Windows, the project file should build using Visual Studio 2015 or above.\nOn Linux, the project file should build using a mono xbuild command:\n  xbuild /p:TargetFrameworkVersion=\"v4.5\" /p:Configuration=Release\n"
  },
  {
    "path": "tools/z80_pla_checker/source/ClassLog.cs",
    "content": "namespace z80_pla_checker\n{\n    /// <summary>\n    /// Implements the logging to the main window\n    /// </summary>\n    static public class ClassLog\n    {\n        static public void Log(string m)\n        {\n            Program.MainForm.Log(m);\n        }\n    }\n}\n"
  },
  {
    "path": "tools/z80_pla_checker/source/ClassOpcodeTable.cs",
    "content": "using System;\nusing System.Collections.Generic;\nusing System.IO;\n\nnamespace z80_pla_checker\n{\n    /// <summary>\n    /// This class loads from a file the opcode table and provides\n    /// access functions to a table.\n    /// </summary>\n    class ClassOpcodeTable\n    {\n        /// <summary>\n        /// Contains the opcode description indexed by the opcode byte\n        /// </summary>\n        private readonly Dictionary<int, string> op = new Dictionary<int, string>();\n\n        /// <summary>\n        /// Loads an opcode table from a text file\n        /// </summary>\n        public void Load(string filename, int xxindex)\n        {\n            ClassLog.Log(\"Loading opcode table: \" + filename);\n\n            try\n            {\n                string[] lines = File.ReadAllLines(filename);\n                op.Clear();\n                foreach (string line in lines)\n                {\n                    string hex = line.Substring(xxindex, 2);\n                    string instr = line.Substring(12);\n                    int xx = Convert.ToInt32(hex, 16);\n                    op[xx] = instr;\n                }\n\n            }\n            catch (Exception ex)\n            {\n                ClassLog.Log(ex.Message);\n            }\n        }\n\n        /// <summary>\n        /// Dumps the opcode table in a table format\n        /// The opcode numbers in the list t will be tagged (marked with *)\n        /// </summary>\n        public void Dump(List<int> t)\n        {\n            ClassLog.Log(new string('-', 242));\n            for (int y = 0; y < 16; y++)\n            {\n                string line = string.Format(\"{0:X} \", y);\n                for (int x = 0; x < 16; x++)\n                {\n                    string opcode = \"\";\n                    if (op.ContainsKey(y * 16 + x))\n                        opcode = op[y * 16 + x];\n                    if (opcode.Length > 12)\n                        opcode = opcode.Substring(0, 12);\n                    char tag = ' ';\n                    if (t.Contains(y * 16 + x)) tag = '*';\n                    line += string.Format(\" |{0}{1,-12}\", tag, opcode);\n                }\n                ClassLog.Log(line);\n            }\n        }\n    }\n}\n"
  },
  {
    "path": "tools/z80_pla_checker/source/ClassPLA.cs",
    "content": "using System;\nusing System.Collections.Generic;\nusing System.IO;\nusing System.Linq;\n\nnamespace z80_pla_checker\n{\n    /// <summary>\n    /// This class defines a complete PLA table and operations on it\n    /// </summary>\n    class ClassPla\n    {\n        /// <summary>\n        /// List of all PLA entries that we read from the input file\n        /// </summary>\n        private readonly List<ClassPlaEntry> pla = new List<ClassPlaEntry>();\n\n        /// <summary>\n        /// List of PLA entries which we want to ignore for various reasons\n        /// </summary>\n        public List<int> IgnoredPla = new List<int>();\n\n        /// <summary>\n        /// List of PLA entries not used by our Timings matrix\n        /// </summary>\n        public List<int> NotUsedPla = new List<int>();\n\n        /// <summary>\n        /// Returns the total number of PLA table entries\n        /// </summary>\n        public int Count()\n        {\n            return pla.Count();\n        }\n\n        /// <summary>\n        /// Read the master PLA table from a text file\n        /// </summary>\n        public bool Load(string filename)\n        {\n            // Read each line of the file into a string array. Each element\n            // of the array is one line of the file.\n            ClassLog.Log(\"Loading PLA: \" + filename);\n\n            try\n            {\n                string[] lines = File.ReadAllLines(filename);\n                pla.Clear();\n                foreach (string line in lines)\n                {\n                    if (line[0] == '#')\n                        continue;\n                    var p = new ClassPlaEntry();\n                    if (p.Init(line))\n                        pla.Add(p);\n                }\n            }\n            catch (Exception ex)\n            {\n                ClassLog.Log(ex.Message);\n                return false;\n            }\n            ClassLog.Log(string.Format(\"Total {0} PLA lines\", pla.Count()));\n\n            ////============================================================\n            //// Ignore duplicate PLA entries\n            //IgnoredPla.Add(98);     // Duplicate of 37\n            //IgnoredPla.Add(94);     // Duplicate of 12 and 18\n            //IgnoredPla.Add(93);     // Duplicate of 11 and 19\n            //IgnoredPla.Add(90);     // Duplicate of 26\n            //IgnoredPla.Add(87);     // Duplicate of 83\n            //IgnoredPla.Add(71);     // Duplicate of 25\n            //IgnoredPla.Add(63);     // Duplicate of 17\n            //IgnoredPla.Add(60);     // Duplicate of 15\n            //IgnoredPla.Add(41);     // Duplicate of 3\n            //IgnoredPla.Add(36);     // Duplicate of 8\n            //IgnoredPla.Add(32);     // Duplicate of 4\n            //IgnoredPla.Add(19);     // Duplicate of 11 and 93\n            //IgnoredPla.Add(18);     // Duplicate of 12 and 94\n\n            ////============================================================\n            //// Special signals (not instructions)\n            //IgnoredPla.Add(91);     // This signal goes along block IN/OUT instructions.\n            //IgnoredPla.Add(75);     // This signal specifies a decrement operation for PLA 53, 66 and 105. Otherwise, it is an increment.\n            //IgnoredPla.Add(55);     // This signal specifies (HL) addressing for all CB-table instructions, PLA entries 70, 72, 73, 74.\n            //IgnoredPla.Add(44);     // This signal specifies a regular CB opcode (ignoring IX/IY).\n            //IgnoredPla.Add(33);     // This signal specifies whether the register is being loaded or stored to memory for PLA entry 31.\n            //IgnoredPla.Add(28);     // This signal specifies the OUT operation for PLA 37. Otherwise, it is operation.\n            //IgnoredPla.Add(27);     // This signal goes along individual IN/OUT instructions in the ED table.\n            //IgnoredPla.Add(16);     // This signal specifies a PUSH operation for PLA23. Otherwise, it is a POP operation.\n            //IgnoredPla.Add(13);     // This signal specifies whether the value is being loaded or stored for PLA entries 8, 30 and 38.\n            //IgnoredPla.Add(0);      // This signal specifies *not* to repeat block instructions.\n\n            ////============================================================\n            //// Ignore our own reserved entries\n            //IgnoredPla.Add(107);\n            //IgnoredPla.Add(106);\n\n            //============================================================\n            // Remove op-bits so we the output is more readable\n            IgnoredPla.Add(99);\n            IgnoredPla.Add(100);\n            IgnoredPla.Add(101);\n            IgnoredPla.Add(102);\n            IgnoredPla.Add(103);\n            IgnoredPla.Add(104);\n\n            // Remove ALU operation entries so the output is more readable\n            IgnoredPla.Add(88);\n            IgnoredPla.Add(86);\n            IgnoredPla.Add(85);\n            IgnoredPla.Add(84);\n            IgnoredPla.Add(80);\n            IgnoredPla.Add(79);\n            IgnoredPla.Add(78);\n            IgnoredPla.Add(76);\n\n            //============================================================\n            // Signals not used in the Timings spreadsheet. For those, PLA table entries are not generated.\n            // This list is used only when generating the PLA table.\n            NotUsedPla.Add(67);       // This signal defines a specific in(), but we use in/out pla[27] + pla[34]\n            NotUsedPla.Add(62);       // This signal is issued for all CB opcodes\n            NotUsedPla.Add(54);       // This signal specifies every CB with IX/IY\n            NotUsedPla.Add(22);       // This signal specifies CB prefix w/o IX/IY\n            NotUsedPla.Add(14);       // This signal specifies a decrement operation for PLA 9. Otherwise, it is an increment.\n            NotUsedPla.Add(4);        // This signal goes along instructions that access I and R register (PLA 57 and 83).\n\n            //============================================================\n            // Mark all PLA entries we decided to ignore\n            foreach (var p in pla)\n            {\n                if (IgnoredPla.Contains<int>(p.N))\n                    p.Ignored = true;\n            }\n            return true;\n        }\n\n        /// <summary>\n        /// Dumps the content of the entire PLA table\n        /// </summary>\n        public void Dump()\n        {\n            ClassLog.Log(\"Content of the PLA table:\");\n            foreach (var p in pla.Where(p => !p.IsDuplicate()))\n                ClassLog.Log(p.Raw);\n        }\n\n        /// <summary>\n        /// Find and return all PLA table entries that trigger on a given condition.\n        /// </summary>\n        public List<string> TableMatch(ClassPlaEntry.Modifier modifier, byte instr)\n        {\n            var t = new bool[pla.Count];\n\n            // First do a simple search to find the list of *all* PLA entries that match\n            foreach (var p in pla)\n            {\n                if (p.Ignored) continue;\n                String match = p.Match(modifier, instr);\n                t[p.N] = !string.IsNullOrEmpty(match);\n            }\n\n            ////============================================================\n            //// Apply any intra-PLA conditions. These are hard-coded into the\n            //// timing spreadsheet and we are duplicating them here:\n\n            //// INC/DEC variations with register, (hl) or (ix+d)\n            //if (t[66] && !(t[53] || t[105])) ; else t[66] = false;\n\n            //// Generic LD r,r' + (hl), IX variations and on top of that NHALT\n            //if (t[61] && !(t[59] || t[103] || t[58] || t[102] || t[95])) ; else t[61] = false;\n            //if (t[58] && !t[95]) ; else t[58] = false;\n            //if (t[102] && !t[95]) ; else t[102] = false;\n            //if (t[59] && !t[95]) ; else t[59] = false;\n            //if (t[103] && !t[95]) ; else t[103] = false;\n\n            //// A single LD (hl),n and LD (ix+d),n has precedence over a set of LD r,n\n            //if (t[17] && !(t[40] || t[50])) ; else t[17] = false;\n\n            //// ALU A,r' and variations on (hl) and (ix+d)\n            //if (t[65] && !(t[52] || t[104])) ; else t[65] = false;\n\n            //// ALU\n            //if (t[88] && (t[65] || t[64] || t[52] || t[104])) ; else t[88] = false;\n            //if (t[86] && (t[65] || t[64] || t[52] || t[104])) ; else t[86] = false;\n            //if (t[85] && (t[65] || t[64] || t[52] || t[104])) ; else t[85] = false;\n            //if (t[84] && (t[65] || t[64] || t[52] || t[104])) ; else t[84] = false;\n            //if (t[80] && (t[65] || t[64] || t[52] || t[104])) ; else t[80] = false;\n            //if (t[79] && (t[65] || t[64] || t[52] || t[104])) ; else t[79] = false;\n            //if (t[78] && (t[65] || t[64] || t[52] || t[104])) ; else t[78] = false;\n            //if (t[76] && (t[65] || t[64] || t[52] || t[104])) ; else t[76] = false;\n\n            //============================================================\n\n            // Finally, collect and return all PLA entries that are left asserted\n            return (from p in pla\n                    where t[p.N]\n                    select p.Match(modifier, instr)).ToList();\n        }\n\n        /// <summary>\n        /// Given the PLA ID, return a list of all opcodes that trigger it\n        /// </summary>\n        public List<string> MatchPLA(ClassPlaEntry.Modifier modifier, int id)\n        {\n            var m = new List<string>();\n\n            // Find the pla with a given index\n            foreach (ClassPlaEntry p in pla)\n            {\n                if (p.N == id)\n                {\n                    // For each possible opcode...\n                    for (int i = 0; i < 256; i++)\n                    {\n                        String match = p.Match(modifier, Convert.ToByte(i));\n                        if (!string.IsNullOrEmpty(match))\n                            m.Add(string.Format(\"{0:X02} => {1}\", i, match));\n                    }\n                    return m;\n                }\n            }\n            ClassLog.Log(\"Non-existent PLA index\");\n            return m;\n        }\n\n        /// <summary>\n        /// Dump opcode table in various ways.\n        /// Returns a \"selected\" list of opcode numbers, that is, opcodes which were tagged by\n        /// the optional input PLA table number given in arg parameter.\n        /// </summary>\n        public List<int> Table(ClassPlaEntry.Modifier modifier, int testNum, int arg)\n        {\n            ClassLog.Log(new string('-', 242));\n            List<int> tagged = new List<int>();\n            for (int y = 0; y < 16; y++)\n            {\n                string line = string.Format(\"{0:X} \", y);\n                for (int x = 0; x < 16; x++)\n                {\n                    char prefix = ' ';\n                    byte opcode = Convert.ToByte(y * 16 + x);\n                    List<string> match = TableMatch(modifier, opcode);\n                    foreach (string oneMatch in match.Where(oneMatch => Convert.ToInt32(oneMatch.Substring(1, oneMatch.LastIndexOf(']') - 1)) == arg))\n                    {\n                        tagged.Add(y * 16 + x);\n                        prefix = '*';\n                    }\n                    string entry = \"\";\n\n                    //===============================================================================\n                    // Table 0 - Show the number of PLA entries that match each opcode\n                    //===============================================================================\n                    if (testNum == 0)\n                    {\n                        entry = string.Join(\",\", match);\n                        if (match.Count == 0)\n                            entry = \".\";\n                        if (match.Count > 1)\n                            entry = \"[\" + match.Count + \"]\";\n                    }\n\n                    //===============================================================================\n                    // Table 1 - For each opcode, show all PLA entries that trigger\n                    //===============================================================================\n                    if (testNum == 1)\n                    {\n                        foreach (string oneMatch in match)\n                        {\n                            string n = oneMatch.Substring(1, oneMatch.LastIndexOf(']') - 1);\n                            entry += n + \",\";\n                        }\n                        entry = entry.TrimEnd(',');\n                    }\n\n                    // -------------------------------------------\n                    if (entry.Length > 12)\n                        entry = entry.Substring(0, 12);\n                    line += string.Format(\" |{0}{1,-12}\", prefix, entry);\n                }\n                ClassLog.Log(line);\n            }\n            return tagged;\n        }\n\n        /// <summary>\n        /// Query PLA table string given as a vector of 0's and 1's\n        /// This vector is coped from a ModelSim simulation run. The function will decode PLA string\n        /// into a set of PLA entries that are being triggered (\"1\")\n        /// </summary>\n        public void QueryPla(String bits)\n        {\n            int max = pla.Count();\n            if (bits.Count() != max)\n            {\n                ClassLog.Log(\"Invalid PLA length - the bit array should be \" + max + \" and it is \" + bits.Count());\n                return;\n            }\n            for (int i = 0; i < max; i++)\n                if (bits[max - i - 1] == '1')\n                    ClassLog.Log(string.Format(@\"pla[{0,3}] = 1;   // {1}\", pla[i].N, pla[i].Comment));\n        }\n\n        /// <summary>\n        /// Generates a Verilog module with the PLA logic\n        /// </summary>\n        public void GenVerilogPla()\n        {\n            string max = (pla.Count() - 1).ToString();\n            string module = \"\";\n            module += @\"//=====================================================================================\" + Environment.NewLine;\n            module += @\"// This file is automatically generated by the z80_pla_checker tool. Do not edit!      \" + Environment.NewLine;\n            module += @\"//=====================================================================================\" + Environment.NewLine;\n            module += @\"module pla_decode\" + Environment.NewLine;\n            module += @\"(\" + Environment.NewLine;\n            module += @\"    input wire [6:0] prefix,\" + Environment.NewLine;\n            module += @\"    input wire [7:0] opcode,\" + Environment.NewLine;\n            module += @\"    output wire [\" + max + \":0] pla\" + Environment.NewLine;\n            module += @\");\" + Environment.NewLine;\n            module += @\"\" + Environment.NewLine;\n\n            foreach (var p in pla)\n            {\n                if (p.IsDuplicate() || NotUsedPla.Contains(p.N))\n                    continue;\n\n                String bitstream = p.GetBitstream();\n                module += string.Format(@\"assign pla[{0,3}] = (({{prefix[6:0], opcode[7:0]}} & 15'b{1}) == 15'b{2}) ? 1'b1 : 1'b0;   // {3}\",\n                    p.N,\n                    bitstream.Replace('0', '1').Replace('X', '0'),  // Create \"AND\" mask\n                    bitstream.Replace('X', '0'),                    // Create a value to compare to\n                    p.Comment) + Environment.NewLine;\n            }\n\n            // List all PLA entries that are not used\n            module += @\"\" + Environment.NewLine;\n            module += @\"// Entries not used by our timing matrix\" + Environment.NewLine;\n            foreach (var n in NotUsedPla)\n            {\n                module += string.Format(@\"assign pla[{0,3}] = 1'b0;   // {1}\", n, pla[n].Comment) + Environment.NewLine;\n            }\n\n            // List all PLA entries that are ignored\n            module += @\"\" + Environment.NewLine;\n            module += @\"// Duplicate entries\" + Environment.NewLine;\n            foreach (var p in pla)\n            {\n                if (p.IsDuplicate())\n                    module += string.Format(@\"assign pla[{0,3}] = 1'b0;   // {1}\", p.N, p.Comment) + Environment.NewLine;\n            }\n\n            module += @\"\" + Environment.NewLine;\n            module += @\"endmodule\" + Environment.NewLine;\n\n            ClassLog.Log(module);\n        }\n    }\n}\n"
  },
  {
    "path": "tools/z80_pla_checker/source/ClassPLAEntry.cs",
    "content": "using System;\n\nnamespace z80_pla_checker\n{\n    /// <summary>\n    /// This class defines a single PLA entry and the operations on it\n    /// </summary>\n    public class ClassPlaEntry\n    {\n        // IX/IY Modifiers\n        [FlagsAttribute] \n        public enum Modifier\n        {\n            IXY0 = (1 << 6),                    // IX or IY flag is reset \n            IXY1 = (1 << 5),                    // IX or IY flag is set\n            NHALT = (1 << 4),                   // Not in HALT state\n            ALU  = (1 << 3),                    // ALU operation\n            XX = (1 << 2),                      // Regular instruction\n            CB = (1 << 1),                      // CB instruction table modifier\n            ED = (1 << 0)                       // ED instruction table modifier\n        };\n\n        private int prefix;                         // Modifier bitfield\n        private int opcode;                         // Opcode bitfield\n        private bool duplicate;                     // This entry is a duplicate\n        public bool IsDuplicate() { return duplicate; }\n\n        public int N { get; private set; }          // Ordinal number of this entry, or the entry ID\n        public string Comment { get; private set; } // PLA line description / comment text\n        public string Raw { get; private set; }     // Raw line as-is\n        public bool Ignored = false;                // This entry can optionally be ignored\n\n        /// <summary>\n        /// PLA entry class constructor\n        /// Accepts the init string which should contain a line from the PLA master table.\n        /// Various fields from that line are read into this class.\n        /// </summary>\n        public bool Init(string init)\n        {\n            try\n            {\n                Raw = init;\n                char[] delimiterChars = { '\\t' };\n                string[] w = init.Split(delimiterChars);\n\n                // Example of an input line:\n                // w[0]                    w[1] w[2] w[3]     w[4]\n                // ....1.. 1.1........1.11.  D   63  00xxx110 ld r,*\n\n                // Mark a duplicate\n                duplicate = w[1].Contains(\"D\");\n\n                // Read the 7 bits of the prefix\n                for (int i = 0; i < 7; i++)\n                    if (w[0][6-i] == '1') prefix |= (1 << i);\n\n                // Read 16 bits of the opcode mask\n                for (int i = 0; i < 16; i++)\n                    if (w[0][23 - i] == '1') opcode |= (1 << i);\n\n                N = Convert.ToInt32(w[2]);\n                Comment = w[4];\n\n                return true;\n            }\n            catch (Exception ex)\n            {\n                ClassLog.Log(\"ClassPlaEntry: Can't parse line: \" + init);\n                ClassLog.Log(ex.Message);\n            }\n            return false;\n        }\n\n\n        /// <summary>\n        /// Matches a given opcode to this PLA line. Returns empty string if not a match\n        /// or PLA number and mnemonic if there is a match. Duplicates are ignored.\n        /// </summary>\n        public string Match(Modifier modifier, Byte instr)\n        {\n            if (duplicate) return string.Empty;\n\n            // Check the modifiers against the prefix bitfield.\n            if ((((int)modifier) & prefix) != prefix)\n                return string.Empty;\n\n            // Check each opcode bit\n            // If any bit in the opcode map is 1, the instruction needs to be \"0\" or \"1\"\n            for (int i = 0; i < 8; i++)\n            {\n                int testbit = (instr >> i) & 1;\n                int test1 = (opcode >> (i * 2)) & 1;\n                int test0 = (opcode >> (i * 2 + 1)) & 1;\n                if (test1 == 1 && testbit != 1) return string.Empty;\n                if (test0 == 1 && testbit != 0) return string.Empty;\n            }\n\n            return string.Format(\"[{0}] {1}\", N, Comment);\n        }\n\n        /// <summary>\n        /// Return a PLA entry suitable to use in a System Verilog compare statement\n        /// </summary>\n        public string GetBitstream()\n        {\n            // Write out these bits in order; they can be 1 or don't care (X)\n            string bitstream = \"\";\n            // Create 7 bits of the prefix\n            for (int i = 6; i >= 0; i--)\n                bitstream += (prefix & (1 << i))==0 ? \"X\" : \"1\";\n            bitstream += \"_\";\n            // Followed by the 8 bits of the opcode mask\n            for (int i = 7; i >= 0; i--)\n            {\n                string code = \"X\";\n                int test1 = (opcode >> (i * 2)) & 1;\n                int test0 = (opcode >> (i * 2 + 1)) & 1;\n                if (test1 == 1)\n                    code = \"1\";\n                if (test0 == 1)\n                    code = \"0\";\n                bitstream += code;\n            }\n            return bitstream;\n        }\n    }\n}\n"
  },
  {
    "path": "tools/z80_pla_checker/source/FormMain.Designer.cs",
    "content": "namespace z80_pla_checker\n{\n    partial class FormMain\n    {\n        /// <summary>\n        /// Required designer variable.\n        /// </summary>\n        private System.ComponentModel.IContainer components = null;\n\n        /// <summary>\n        /// Clean up any resources being used.\n        /// </summary>\n        /// <param name=\"disposing\">true if managed resources should be disposed; otherwise, false.</param>\n        protected override void Dispose(bool disposing)\n        {\n            if (disposing && (components != null))\n            {\n                components.Dispose();\n            }\n            base.Dispose(disposing);\n        }\n\n        #region Windows Form Designer generated code\n\n        /// <summary>\n        /// Required method for Designer support - do not modify\n        /// the contents of this method with the code editor.\n        /// </summary>\n        private void InitializeComponent()\n        {\n            System.ComponentModel.ComponentResourceManager resources = new System.ComponentModel.ComponentResourceManager(typeof(FormMain));\n            this.menuStrip1 = new System.Windows.Forms.MenuStrip();\n            this.fileToolStripMenuItem = new System.Windows.Forms.ToolStripMenuItem();\n            this.loadPLATableToolStripMenuItem = new System.Windows.Forms.ToolStripMenuItem();\n            this.opcodeDirToolStripMenuItem = new System.Windows.Forms.ToolStripMenuItem();\n            this.exitToolStripMenuItem = new System.Windows.Forms.ToolStripMenuItem();\n            this.statusStrip1 = new System.Windows.Forms.StatusStrip();\n            this.logText = new System.Windows.Forms.RichTextBox();\n            this.toolStrip = new System.Windows.Forms.ToolStrip();\n            this.label1 = new System.Windows.Forms.ToolStripLabel();\n            this.btIX0 = new System.Windows.Forms.ToolStripButton();\n            this.btIX1 = new System.Windows.Forms.ToolStripButton();\n            this.btHALT = new System.Windows.Forms.ToolStripButton();\n            this.btALU = new System.Windows.Forms.ToolStripButton();\n            this.btXX = new System.Windows.Forms.ToolStripButton();\n            this.btCB = new System.Windows.Forms.ToolStripButton();\n            this.btED = new System.Windows.Forms.ToolStripButton();\n            this.toolStripSeparator1 = new System.Windows.Forms.ToolStripSeparator();\n            this.btClear = new System.Windows.Forms.ToolStripButton();\n            this.btRedo = new System.Windows.Forms.ToolStripButton();\n            this.textOp = new System.Windows.Forms.TextBox();\n            this.menuStrip1.SuspendLayout();\n            this.toolStrip.SuspendLayout();\n            this.SuspendLayout();\n            // \n            // menuStrip1\n            // \n            this.menuStrip1.Items.AddRange(new System.Windows.Forms.ToolStripItem[] {\n            this.fileToolStripMenuItem});\n            this.menuStrip1.Location = new System.Drawing.Point(0, 0);\n            this.menuStrip1.Name = \"menuStrip1\";\n            this.menuStrip1.Size = new System.Drawing.Size(548, 24);\n            this.menuStrip1.TabIndex = 0;\n            this.menuStrip1.Text = \"menuStrip1\";\n            // \n            // fileToolStripMenuItem\n            // \n            this.fileToolStripMenuItem.DropDownItems.AddRange(new System.Windows.Forms.ToolStripItem[] {\n            this.loadPLATableToolStripMenuItem,\n            this.opcodeDirToolStripMenuItem,\n            this.exitToolStripMenuItem});\n            this.fileToolStripMenuItem.Name = \"fileToolStripMenuItem\";\n            this.fileToolStripMenuItem.Size = new System.Drawing.Size(37, 20);\n            this.fileToolStripMenuItem.Text = \"File\";\n            // \n            // loadPLATableToolStripMenuItem\n            // \n            this.loadPLATableToolStripMenuItem.Name = \"loadPLATableToolStripMenuItem\";\n            this.loadPLATableToolStripMenuItem.Size = new System.Drawing.Size(162, 22);\n            this.loadPLATableToolStripMenuItem.Text = \"Load PLA table...\";\n            this.loadPLATableToolStripMenuItem.Click += new System.EventHandler(this.LoadPlaTable);\n            // \n            // opcodeDirToolStripMenuItem\n            // \n            this.opcodeDirToolStripMenuItem.Name = \"opcodeDirToolStripMenuItem\";\n            this.opcodeDirToolStripMenuItem.Size = new System.Drawing.Size(162, 22);\n            this.opcodeDirToolStripMenuItem.Text = \"Opcode dir...\";\n            this.opcodeDirToolStripMenuItem.Click += new System.EventHandler(this.SelectOpcodeDir);\n            // \n            // exitToolStripMenuItem\n            // \n            this.exitToolStripMenuItem.Name = \"exitToolStripMenuItem\";\n            this.exitToolStripMenuItem.ShortcutKeys = ((System.Windows.Forms.Keys)((System.Windows.Forms.Keys.Alt | System.Windows.Forms.Keys.F4)));\n            this.exitToolStripMenuItem.Size = new System.Drawing.Size(162, 22);\n            this.exitToolStripMenuItem.Text = \"Exit\";\n            this.exitToolStripMenuItem.Click += new System.EventHandler(this.ExitToolStripMenuItemClick);\n            // \n            // statusStrip1\n            // \n            this.statusStrip1.Location = new System.Drawing.Point(0, 516);\n            this.statusStrip1.Name = \"statusStrip1\";\n            this.statusStrip1.Size = new System.Drawing.Size(548, 22);\n            this.statusStrip1.TabIndex = 3;\n            this.statusStrip1.Text = \"statusStrip1\";\n            // \n            // logText\n            // \n            this.logText.Anchor = ((System.Windows.Forms.AnchorStyles)((((System.Windows.Forms.AnchorStyles.Top | System.Windows.Forms.AnchorStyles.Bottom) \n            | System.Windows.Forms.AnchorStyles.Left) \n            | System.Windows.Forms.AnchorStyles.Right)));\n            this.logText.AutoWordSelection = true;\n            this.logText.Font = new System.Drawing.Font(\"Consolas\", 8.25F, System.Drawing.FontStyle.Regular, System.Drawing.GraphicsUnit.Point, ((byte)(0)));\n            this.logText.HideSelection = false;\n            this.logText.Location = new System.Drawing.Point(0, 49);\n            this.logText.Name = \"logText\";\n            this.logText.ReadOnly = true;\n            this.logText.ScrollBars = System.Windows.Forms.RichTextBoxScrollBars.ForcedBoth;\n            this.logText.ShowSelectionMargin = true;\n            this.logText.Size = new System.Drawing.Size(548, 438);\n            this.logText.TabIndex = 2;\n            this.logText.Text = \"\";\n            this.logText.WordWrap = false;\n            // \n            // toolStrip\n            // \n            this.toolStrip.Items.AddRange(new System.Windows.Forms.ToolStripItem[] {\n            this.label1,\n            this.btIX0,\n            this.btIX1,\n            this.btHALT,\n            this.btALU,\n            this.btXX,\n            this.btCB,\n            this.btED,\n            this.toolStripSeparator1,\n            this.btClear,\n            this.btRedo});\n            this.toolStrip.Location = new System.Drawing.Point(0, 24);\n            this.toolStrip.Name = \"toolStrip\";\n            this.toolStrip.Size = new System.Drawing.Size(548, 25);\n            this.toolStrip.TabIndex = 1;\n            this.toolStrip.Text = \"toolStrip\";\n            // \n            // label1\n            // \n            this.label1.Name = \"label1\";\n            this.label1.Size = new System.Drawing.Size(60, 22);\n            this.label1.Text = \"Modifiers:\";\n            // \n            // btIX0\n            // \n            this.btIX0.DisplayStyle = System.Windows.Forms.ToolStripItemDisplayStyle.Text;\n            this.btIX0.Image = ((System.Drawing.Image)(resources.GetObject(\"btIX0.Image\")));\n            this.btIX0.ImageTransparentColor = System.Drawing.Color.Magenta;\n            this.btIX0.Name = \"btIX0\";\n            this.btIX0.Size = new System.Drawing.Size(27, 22);\n            this.btIX0.Text = \"IX0\";\n            this.btIX0.ToolTipText = \"IX/IY prefix *not* present\";\n            this.btIX0.Click += new System.EventHandler(this.BtIx0Click);\n            // \n            // btIX1\n            // \n            this.btIX1.DisplayStyle = System.Windows.Forms.ToolStripItemDisplayStyle.Text;\n            this.btIX1.Image = ((System.Drawing.Image)(resources.GetObject(\"btIX1.Image\")));\n            this.btIX1.ImageTransparentColor = System.Drawing.Color.Magenta;\n            this.btIX1.Name = \"btIX1\";\n            this.btIX1.Size = new System.Drawing.Size(27, 22);\n            this.btIX1.Text = \"IX1\";\n            this.btIX1.ToolTipText = \"IX/IY prefixed instruction\";\n            this.btIX1.Click += new System.EventHandler(this.BtIx1Click);\n            // \n            // btHALT\n            // \n            this.btHALT.Checked = true;\n            this.btHALT.CheckState = System.Windows.Forms.CheckState.Checked;\n            this.btHALT.DisplayStyle = System.Windows.Forms.ToolStripItemDisplayStyle.Text;\n            this.btHALT.Image = ((System.Drawing.Image)(resources.GetObject(\"btHALT.Image\")));\n            this.btHALT.ImageTransparentColor = System.Drawing.Color.Magenta;\n            this.btHALT.Name = \"btHALT\";\n            this.btHALT.Size = new System.Drawing.Size(50, 22);\n            this.btHALT.Text = \"NHALT\";\n            this.btHALT.ToolTipText = \"Not in HALT state\";\n            this.btHALT.Click += new System.EventHandler(this.BtNHaltClick);\n            // \n            // btALU\n            // \n            this.btALU.DisplayStyle = System.Windows.Forms.ToolStripItemDisplayStyle.Text;\n            this.btALU.Image = ((System.Drawing.Image)(resources.GetObject(\"btALU.Image\")));\n            this.btALU.ImageTransparentColor = System.Drawing.Color.Magenta;\n            this.btALU.Name = \"btALU\";\n            this.btALU.Size = new System.Drawing.Size(33, 22);\n            this.btALU.Text = \"ALU\";\n            this.btALU.ToolTipText = \"ALU operation\";\n            this.btALU.Click += new System.EventHandler(this.BtAluClick);\n            // \n            // btXX\n            // \n            this.btXX.Checked = true;\n            this.btXX.CheckState = System.Windows.Forms.CheckState.Checked;\n            this.btXX.DisplayStyle = System.Windows.Forms.ToolStripItemDisplayStyle.Text;\n            this.btXX.Image = ((System.Drawing.Image)(resources.GetObject(\"btXX.Image\")));\n            this.btXX.ImageTransparentColor = System.Drawing.Color.Magenta;\n            this.btXX.Name = \"btXX\";\n            this.btXX.Size = new System.Drawing.Size(25, 22);\n            this.btXX.Text = \"XX\";\n            this.btXX.ToolTipText = \"Regular instruction\";\n            this.btXX.Click += new System.EventHandler(this.BtXxClick);\n            // \n            // btCB\n            // \n            this.btCB.DisplayStyle = System.Windows.Forms.ToolStripItemDisplayStyle.Text;\n            this.btCB.Image = ((System.Drawing.Image)(resources.GetObject(\"btCB.Image\")));\n            this.btCB.ImageTransparentColor = System.Drawing.Color.Magenta;\n            this.btCB.Name = \"btCB\";\n            this.btCB.Size = new System.Drawing.Size(26, 22);\n            this.btCB.Text = \"CB\";\n            this.btCB.ToolTipText = \"CB prefix\";\n            this.btCB.Click += new System.EventHandler(this.BtCbClick);\n            // \n            // btED\n            // \n            this.btED.DisplayStyle = System.Windows.Forms.ToolStripItemDisplayStyle.Text;\n            this.btED.Image = ((System.Drawing.Image)(resources.GetObject(\"btED.Image\")));\n            this.btED.ImageTransparentColor = System.Drawing.Color.Magenta;\n            this.btED.Name = \"btED\";\n            this.btED.Size = new System.Drawing.Size(25, 22);\n            this.btED.Text = \"ED\";\n            this.btED.ToolTipText = \"ED prefix\";\n            this.btED.Click += new System.EventHandler(this.BtEdClick);\n            // \n            // toolStripSeparator1\n            // \n            this.toolStripSeparator1.Name = \"toolStripSeparator1\";\n            this.toolStripSeparator1.Size = new System.Drawing.Size(6, 25);\n            // \n            // btClear\n            // \n            this.btClear.DisplayStyle = System.Windows.Forms.ToolStripItemDisplayStyle.Text;\n            this.btClear.Image = ((System.Drawing.Image)(resources.GetObject(\"btClear.Image\")));\n            this.btClear.ImageTransparentColor = System.Drawing.Color.Magenta;\n            this.btClear.Name = \"btClear\";\n            this.btClear.Size = new System.Drawing.Size(25, 22);\n            this.btClear.Text = \"cls\";\n            this.btClear.Click += new System.EventHandler(this.BtClearClick);\n            // \n            // btRedo\n            // \n            this.btRedo.DisplayStyle = System.Windows.Forms.ToolStripItemDisplayStyle.Text;\n            this.btRedo.Enabled = false;\n            this.btRedo.Image = ((System.Drawing.Image)(resources.GetObject(\"btRedo.Image\")));\n            this.btRedo.ImageTransparentColor = System.Drawing.Color.Magenta;\n            this.btRedo.Name = \"btRedo\";\n            this.btRedo.Size = new System.Drawing.Size(35, 22);\n            this.btRedo.Text = \"redo\";\n            this.btRedo.Click += new System.EventHandler(this.BtRedoClick);\n            // \n            // textOp\n            // \n            this.textOp.Anchor = ((System.Windows.Forms.AnchorStyles)(((System.Windows.Forms.AnchorStyles.Bottom | System.Windows.Forms.AnchorStyles.Left) \n            | System.Windows.Forms.AnchorStyles.Right)));\n            this.textOp.Location = new System.Drawing.Point(0, 493);\n            this.textOp.Name = \"textOp\";\n            this.textOp.Size = new System.Drawing.Size(548, 20);\n            this.textOp.TabIndex = 4;\n            this.textOp.KeyDown += new System.Windows.Forms.KeyEventHandler(this.TextOpKeyDown);\n            // \n            // FormMain\n            // \n            this.AutoScaleDimensions = new System.Drawing.SizeF(6F, 13F);\n            this.AutoScaleMode = System.Windows.Forms.AutoScaleMode.Font;\n            this.ClientSize = new System.Drawing.Size(548, 538);\n            this.Controls.Add(this.logText);\n            this.Controls.Add(this.statusStrip1);\n            this.Controls.Add(this.toolStrip);\n            this.Controls.Add(this.menuStrip1);\n            this.Controls.Add(this.textOp);\n            this.MainMenuStrip = this.menuStrip1;\n            this.Name = \"FormMain\";\n            this.Text = \"Z80 PLA\";\n            this.FormClosing += new System.Windows.Forms.FormClosingEventHandler(this.FormMainFormClosing);\n            this.menuStrip1.ResumeLayout(false);\n            this.menuStrip1.PerformLayout();\n            this.toolStrip.ResumeLayout(false);\n            this.toolStrip.PerformLayout();\n            this.ResumeLayout(false);\n            this.PerformLayout();\n\n        }\n\n        #endregion\n\n        private System.Windows.Forms.MenuStrip menuStrip1;\n        private System.Windows.Forms.StatusStrip statusStrip1;\n        private System.Windows.Forms.ToolStripMenuItem fileToolStripMenuItem;\n        private System.Windows.Forms.ToolStripMenuItem exitToolStripMenuItem;\n        private System.Windows.Forms.RichTextBox logText;\n        private System.Windows.Forms.ToolStrip toolStrip;\n        private System.Windows.Forms.ToolStripButton btRedo;\n        private System.Windows.Forms.ToolStripButton btXX;\n        private System.Windows.Forms.ToolStripButton btCB;\n        private System.Windows.Forms.ToolStripButton btED;\n        private System.Windows.Forms.ToolStripButton btClear;\n        private System.Windows.Forms.TextBox textOp;\n        private System.Windows.Forms.ToolStripButton btIX0;\n        private System.Windows.Forms.ToolStripSeparator toolStripSeparator1;\n        private System.Windows.Forms.ToolStripButton btIX1;\n        private System.Windows.Forms.ToolStripLabel label1;\n        private System.Windows.Forms.ToolStripMenuItem loadPLATableToolStripMenuItem;\n        private System.Windows.Forms.ToolStripButton btHALT;\n        private System.Windows.Forms.ToolStripButton btALU;\n        private System.Windows.Forms.ToolStripMenuItem opcodeDirToolStripMenuItem;\n    }\n}\n\n"
  },
  {
    "path": "tools/z80_pla_checker/source/FormMain.cs",
    "content": "using System;\nusing System.Collections.Generic;\nusing System.IO;\nusing System.Windows.Forms;\n\nnamespace z80_pla_checker\n{\n    public partial class FormMain : Form\n    {\n        /// <summary>\n        /// Master PLA table\n        /// </summary>\n        private readonly ClassPla pla = new ClassPla();\n\n        /// <summary>\n        /// Current modifiers\n        /// </summary>\n        private ClassPlaEntry.Modifier modifier = ClassPlaEntry.Modifier.XX | ClassPlaEntry.Modifier.NHALT;\n\n        /// <summary>\n        /// Various opcode tables we need to display mnemonics\n        /// </summary>\n        private readonly ClassOpcodeTable tableXX__ = new ClassOpcodeTable();\n        private readonly ClassOpcodeTable tableCBXX = new ClassOpcodeTable();\n        private readonly ClassOpcodeTable tableEDXX = new ClassOpcodeTable();\n        private readonly ClassOpcodeTable tableDDXX = new ClassOpcodeTable();\n        private readonly ClassOpcodeTable tableDDCB = new ClassOpcodeTable();\n\n        private readonly List<string> commands = new List<string>();\n        private int commandsBrowseIndex;\n\n        public FormMain()\n        {\n            InitializeComponent();\n            WindowState = FormWindowState.Maximized;\n        }\n\n        /// <summary>\n        /// This is the main program's startup function\n        /// </summary>\n        public void OnStart()\n        {\n            ClassLog.Log(\"PLA Checker Tool  Copyright (C) 2014  Goran Devic\");\n            ClassLog.Log(\"This program comes with ABSOLUTELY NO WARRANTY\");\n            ClassLog.Log(\"This is free software and you are welcome to redistribute it under certain conditions; for details see GPLv3 license.\");\n            ClassLog.Log(\"---------------------------------------------------------------------------------------------------------------------\");\n\n            // Load the PLA table from a text file.\n            String plaFile = Properties.Settings.Default.plaFileName;\n            if (!pla.Load(plaFile))\n            {\n                ClassLog.Log(\"*** Error loading the master input PLA source table ***\");\n                ClassLog.Log(\"Click on File -> Load PLA table... and select a resource file z80-pla.txt\");\n                return;\n            }\n\n            // Load opcode tables from a previously selected directory\n            // We use only IX variation tables since IY's are the same\n            String opFile = Properties.Settings.Default.opcodeDir;\n            char p = Path.DirectorySeparatorChar;\n            tableXX__.Load(opFile + p + \"opcodes-xx.txt\", 0);\n            tableCBXX.Load(opFile + p + \"opcodes-cb-xx.txt\", 2);\n            tableEDXX.Load(opFile + p + \"opcodes-ed-xx.txt\", 2);\n            tableDDXX.Load(opFile + p + \"opcodes-dd-xx.txt\", 2);\n            tableDDCB.Load(opFile + p + \"opcodes-dd-cb.txt\", 7);\n\n            ClassLog.Log(Command(\"?\"));\n        }\n\n        /// <summary>\n        /// Print out a log message & always show the last line\n        /// </summary>\n        public void Log(String s)\n        {\n            logText.AppendText(s + Environment.NewLine);\n            logText.SelectionStart = logText.Text.Length;\n            logText.ScrollToCaret();\n        }\n\n        /// <summary>\n        /// Exit the application\n        /// </summary>\n        private void ExitToolStripMenuItemClick(object sender, EventArgs e)\n        {\n            Close();\n        }\n\n        /// <summary>\n        /// Application is closing\n        /// </summary>\n        private void FormMainFormClosing(object sender, FormClosingEventArgs e)\n        {\n            Properties.Settings.Default.Save();\n        }\n\n        private static int ScanNumber(string arg, int baseValue)\n        {\n            try\n            {\n                return Convert.ToInt32(arg, baseValue);\n            }\n            catch(Exception ex)\n            {\n                ClassLog.Log(ex.Message + \": \" + arg);\n                return -1;\n            }\n        }\n\n        /// <summary>\n        /// List all PLA entries that trigger on a specific opcode\n        /// If the opcode # (hex) was not given, dump that information for all opcodes (0-FF)\n        /// </summary>\n        private void MatchPLA(string arg)\n        {\n            int op = -1;\n            if (!string.IsNullOrEmpty(arg))\n            {\n                op = ScanNumber(arg, 16);\n                if (op < 0)\n                    return;\n            }\n            for (int x = 0; x < 256; x++)\n            {\n                if (op >= 0 && x != op)\n                    continue;\n                ClassLog.Log(String.Format(\"Opcode: {0:X02} \", x));\n\n                Byte opcode = Convert.ToByte(x);\n                List<string> m = pla.TableMatch(modifier, opcode);\n\n                foreach (var s in m)\n                    ClassLog.Log(s);\n            }\n        }\n\n        /// <summary>\n        /// List all opcodes that trigger on a given PLA table index\n        /// </summary>\n        private void MatchOpcodes(ClassPlaEntry.Modifier modifier, string arg)\n        {\n            int index = ScanNumber(arg, 10);\n            if (index < 0)\n                return;\n            List<string> m = pla.MatchPLA(modifier, index);\n            if (m.Count == 0)\n                return;\n            ClassLog.Log(String.Format(\"PLA Entry: {0}  Modifier: {1}\", index, modifier));\n            foreach (var s in m)\n                ClassLog.Log(s);\n        }\n\n        /// <summary>\n        /// Dumps one of the opcode tables depending on the current set of modifiers\n        /// </summary>\n        private void DumpOpcodeTable(List<int> t)\n        {\n            bool cb = (modifier & ClassPlaEntry.Modifier.CB) != 0;\n            bool ed = (modifier & ClassPlaEntry.Modifier.ED) != 0;\n            bool ix = (modifier & ClassPlaEntry.Modifier.IXY1) != 0;\n            if (ix & cb)\n                tableDDCB.Dump(t);\n            else if (cb)\n                tableCBXX.Dump(t);\n            else if (ed)\n                tableEDXX.Dump(t);\n            else if (ix)\n                tableDDXX.Dump(t);\n            else tableXX__.Dump(t);\n        }\n\n        /// <summary>\n        /// Select the input PLA table file to load\n        /// </summary>\n        private void LoadPlaTable(object sender, EventArgs e)\n        {\n            var dlg = new OpenFileDialog();\n            dlg.Title = \"Select a PLA table source file\";\n            dlg.Filter = @\"z80-pla.txt|*.txt|All files|*.*\";\n            dlg.FileName = Properties.Settings.Default.plaFileName;\n            if (dlg.ShowDialog() == DialogResult.OK)\n                Properties.Settings.Default.plaFileName = dlg.FileName;\n        }\n\n        /// <summary>\n        /// Select the directory that contains opcode tables\n        /// </summary>\n        private void SelectOpcodeDir(object sender, EventArgs e)\n        {\n            var dlg = new FolderBrowserDialog();\n            dlg.Description = \"Select the directory containing opcode files (opcodes-xx.txt etc.):\";\n            if (dlg.ShowDialog() == DialogResult.OK)\n                Properties.Settings.Default.opcodeDir = dlg.SelectedPath;\n        }\n\n        /// <summary>\n        /// Clear the log text panel\n        /// </summary>\n        private void BtClearClick(object sender, EventArgs e)\n        {\n            logText.Clear();\n        }\n\n        /// <summary>\n        /// User clicked on the Redo button: repeat the command\n        /// </summary>\n        private void BtRedoClick(object sender, EventArgs e)\n        {\n            ClassLog.Log(string.Format(\"{0}>>> {1}\", commands.Count, commands[commands.Count - 1]));\n            string response = Command(commands[commands.Count - 1]);\n            if (!string.IsNullOrEmpty(response))\n                ClassLog.Log(response);\n        }\n\n        /// <summary>\n        /// Update button state after the internal flag state change\n        /// </summary>\n        private void UpdateButtons()\n        {\n            btIX0.Checked = (modifier & ClassPlaEntry.Modifier.IXY0) != 0;\n            btIX1.Checked = (modifier & ClassPlaEntry.Modifier.IXY1) != 0;\n            btHALT.Checked = (modifier & ClassPlaEntry.Modifier.NHALT) != 0;\n            btALU.Checked = (modifier & ClassPlaEntry.Modifier.ALU) != 0;\n            btXX.Checked = (modifier & ClassPlaEntry.Modifier.XX) != 0;\n            btCB.Checked = (modifier & ClassPlaEntry.Modifier.CB) != 0;\n            btED.Checked = (modifier & ClassPlaEntry.Modifier.ED) != 0;\n\n            ClassLog.Log(\"Set modifier to \" + modifier);\n        }\n\n        private void BtIx0Click(object sender, EventArgs e)\n        {\n            if ((modifier & ClassPlaEntry.Modifier.IXY0) != 0)\n                modifier &= ~ClassPlaEntry.Modifier.IXY0;\n            else\n            {\n                modifier |= ClassPlaEntry.Modifier.IXY0;\n                modifier &= ~ClassPlaEntry.Modifier.IXY1;                \n            }\n            UpdateButtons();\n        }\n\n        private void BtIx1Click(object sender, EventArgs e)\n        {\n            if ((modifier & ClassPlaEntry.Modifier.IXY1) != 0)\n                modifier &= ~ClassPlaEntry.Modifier.IXY1;\n            else\n            {\n                modifier |= ClassPlaEntry.Modifier.IXY1;\n                modifier &= ~ClassPlaEntry.Modifier.IXY0;\n            }\n            UpdateButtons();\n        }\n\n        private void BtNHaltClick(object sender, EventArgs e)\n        {\n            modifier ^= ClassPlaEntry.Modifier.NHALT;\n            UpdateButtons();\n        }\n\n        private void BtAluClick(object sender, EventArgs e)\n        {\n            modifier ^= ClassPlaEntry.Modifier.ALU;\n            UpdateButtons();\n        }\n\n        private void BtXxClick(object sender, EventArgs e)\n        {\n            if ((modifier & ClassPlaEntry.Modifier.XX) != 0)\n                modifier &= ~ClassPlaEntry.Modifier.XX;\n            else\n            {\n                modifier |= ClassPlaEntry.Modifier.XX;\n                modifier &= ~(ClassPlaEntry.Modifier.CB | ClassPlaEntry.Modifier.ED);\n            }\n            UpdateButtons();\n        }\n\n        private void BtCbClick(object sender, EventArgs e)\n        {\n            if ((modifier & ClassPlaEntry.Modifier.CB) != 0)\n                modifier &= ~ClassPlaEntry.Modifier.CB;\n            else\n            {\n                modifier |= ClassPlaEntry.Modifier.CB;\n                modifier &= ~(ClassPlaEntry.Modifier.XX | ClassPlaEntry.Modifier.ED);\n            }\n            UpdateButtons();\n        }\n\n        private void BtEdClick(object sender, EventArgs e)\n        {\n            if ((modifier & ClassPlaEntry.Modifier.ED) != 0)\n                modifier &= ~ClassPlaEntry.Modifier.ED;\n            else\n            {\n                modifier |= ClassPlaEntry.Modifier.ED;\n                modifier &= ~(ClassPlaEntry.Modifier.XX | ClassPlaEntry.Modifier.CB);\n            }\n            UpdateButtons();\n        }\n\n        /// <summary>\n        /// Implements a simple command history\n        /// </summary>\n        private void TextOpKeyDown(object sender, KeyEventArgs e)\n        {\n            if (e.KeyCode == Keys.Enter)\n            {\n                // Mark the handled flag so this key won't be processed.\n                e.Handled = true;\n                string cmd = textOp.Text.Trim();\n                if (cmd.Length > 0)\n                {\n                    commands.Add(cmd);\n                    btRedo.Enabled = true;\n                    ClassLog.Log(string.Format(\"{0}>>> {1}\", commands.Count, cmd));\n                    string response = Command(textOp.Text);\n                    if (!string.IsNullOrEmpty(response))\n                        ClassLog.Log(response);\n\n                    commandsBrowseIndex = commands.Count;\n                    textOp.Text = \"\";\n                }\n                textOp.Focus();\n            }\n            if (e.KeyCode == Keys.PageUp && commandsBrowseIndex > 0)\n            {\n                commandsBrowseIndex--;\n                textOp.Text = commands[commandsBrowseIndex];\n                e.Handled = true;\n            }\n            if (e.KeyCode == Keys.PageDown && commandsBrowseIndex < commands.Count - 1)\n            {\n                commandsBrowseIndex++;\n                textOp.Text = commands[commandsBrowseIndex];\n                e.Handled = true;\n            }\n            if (e.KeyCode == Keys.Escape)\n            {\n                textOp.Text = \"\";\n                e.Handled = true;\n            }\n        }\n\n        /// <summary>\n        /// Execute a command\n        /// </summary>\n        private string Command(string cmd)\n        {\n            try\n            {\n                string[] tokens = cmd.Split(new string[] { \" \" }, StringSplitOptions.RemoveEmptyEntries);\n                if (tokens.Length == 0)\n                    return \"\";\n                switch (tokens[0])\n                {\n                    case \"?\":\n                    case \"h\":\n                        return Environment.NewLine +\n                            \"p         - Dump the content of the PLA table\" + Environment.NewLine +\n                            \"p [#]     - For a given PLA entry # (dec) show opcodes that trigger it\" + Environment.NewLine +\n                            \"m [#]     - Match opcode # (hex) with a PLA entry (or match 0-FF)\" + Environment.NewLine +\n                            \"g         - Generate a Verilog PLA module\" + Environment.NewLine +\n                            \"t [#] <#> - Show opcode table in various ways\" + Environment.NewLine +\n                            \"            0 - Display number of PLA entries that trigger on each opcode\" + Environment.NewLine +\n                            \"            1 - For each opcode, display all PLA entry numbers that trigger\" + Environment.NewLine +\n                            \"            <#> - Add a * to opcodes for which the specified PLA entry triggers\" + Environment.NewLine +\n                            \"q 101000... Query PLA table string\" + Environment.NewLine +\n                            \"c         - Clear the screen\";\n                    case \"p\": if (tokens.Length > 1)\n                            MatchOpcodes(modifier, tokens[1]);\n                        else\n                            pla.Dump();\n                        break;\n                    case \"m\": MatchPLA(tokens.Length > 1 ? tokens[1] : \"\");\n                        break;\n                    case \"g\": pla.GenVerilogPla();\n                        break;\n                    case \"c\": BtClearClick(null, null);\n                        break;\n                    case \"t\":\n                        {\n                            int arg1 = 0, arg2 = -1;\n                            if (tokens.Length > 1)\n                                arg1 = ScanNumber(tokens[1], 10);\n                            if (tokens.Length > 2)\n                                arg2 = ScanNumber(tokens[2], 10);\n                            if (arg1 == 0 || arg1 == 1)\n                            {\n                                List<int> tagged = pla.Table(modifier, arg1, arg2);\n                                DumpOpcodeTable(tagged);\n                            }\n                            else\n                                ClassLog.Log(\"Invalid table number!\");\n                        }\n                        break;\n                    case \"q\": pla.QueryPla(tokens[1].Trim());\n                        break;\n                    default:\n                        return \"?\";\n                }\n            }\n            catch (Exception ex)\n            {\n                ClassLog.Log(\"Error: \" + ex.Message);\n            }\n            return string.Empty;\n        }\n    }\n}\n"
  },
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  },
  {
    "path": "tools/z80_pla_checker/source/Program.cs",
    "content": "/*  Copyright (C) 2014 Goran Devic\n\n    This program is free software: you can redistribute it and/or modify\n    it under the terms of the GNU General Public License as published by\n    the Free Software Foundation, either version 3 of the License, or\n    (at your option) any later version.\n\n    This program is distributed in the hope that it will be useful,\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n    GNU General Public License for more details.\n\n    You should have received a copy of the GNU General Public License\n    along with this program.  If not, see <http://www.gnu.org/licenses/>.\n */\nusing System;\nusing System.Windows.Forms;\n\nnamespace z80_pla_checker\n{\n    static class Program\n    {\n        internal static FormMain MainForm;\n\n        /// <summary>\n        /// The main entry point for the application.\n        /// </summary>\n        [STAThread]\n        static void Main()\n        {\n            Application.EnableVisualStyles();\n            Application.SetCompatibleTextRenderingDefault(false);\n            MainForm = new FormMain();\n            MainForm.OnStart();\n            Application.Run(MainForm);\n        }\n    }\n}\n"
  },
  {
    "path": "tools/z80_pla_checker/source/Properties/AssemblyInfo.cs",
    "content": "using System.Reflection;\nusing System.Runtime.InteropServices;\n\n// General Information about an assembly is controlled through the following \n// set of attributes. Change these attribute values to modify the information\n// associated with an assembly.\n[assembly: AssemblyTitle(\"z80_pla_checker\")]\n[assembly: AssemblyDescription(\"Experiment with and generate A-Z80 PLA table\")]\n[assembly: AssemblyConfiguration(\"\")]\n[assembly: AssemblyCompany(\"Baltazar Studios, LLC\")]\n[assembly: AssemblyProduct(\"z80_pla_checker\")]\n[assembly: AssemblyCopyright(\"Copyright © Goran Devic, 2014, released under GPL\")]\n[assembly: AssemblyTrademark(\"\")]\n[assembly: AssemblyCulture(\"\")]\n\n// Setting ComVisible to false makes the types in this assembly not visible \n// to COM components.  If you need to access a type in this assembly from \n// COM, set the ComVisible attribute to true on that type.\n[assembly: ComVisible(false)]\n\n// The following GUID is for the ID of the typelib if this project is exposed to COM\n[assembly: Guid(\"26b49697-d259-4ed7-8e05-a6077d07b140\")]\n\n// Version information for an assembly consists of the following four values:\n//\n//      Major Version\n//      Minor Version \n//      Build Number\n//      Revision\n//\n// You can specify all the values or you can default the Build and Revision Numbers \n// by using the '*' as shown below:\n// [assembly: AssemblyVersion(\"1.0.*\")]\n[assembly: AssemblyVersion(\"1.0.0.0\")]\n[assembly: AssemblyFileVersion(\"1.0.0.0\")]\n"
  },
  {
    "path": "tools/z80_pla_checker/source/Properties/Resources.Designer.cs",
    "content": "//------------------------------------------------------------------------------\n// <auto-generated>\n//     This code was generated by a tool.\n//     Runtime Version:4.0.30319.18408\n//\n//     Changes to this file may cause incorrect behavior and will be lost if\n//     the code is regenerated.\n// </auto-generated>\n//------------------------------------------------------------------------------\n\nnamespace z80_pla_checker.Properties {\n    using System;\n    \n    \n    /// <summary>\n    ///   A strongly-typed resource class, for looking up localized strings, etc.\n    /// </summary>\n    // This class was auto-generated by the StronglyTypedResourceBuilder\n    // class via a tool like ResGen or Visual Studio.\n    // To add or remove a member, edit your .ResX file then rerun ResGen\n    // with the /str option, or rebuild your VS project.\n    [global::System.CodeDom.Compiler.GeneratedCodeAttribute(\"System.Resources.Tools.StronglyTypedResourceBuilder\", \"4.0.0.0\")]\n    [global::System.Diagnostics.DebuggerNonUserCodeAttribute()]\n    [global::System.Runtime.CompilerServices.CompilerGeneratedAttribute()]\n    internal class Resources {\n        \n        private static global::System.Resources.ResourceManager resourceMan;\n        \n        private static global::System.Globalization.CultureInfo resourceCulture;\n        \n        [global::System.Diagnostics.CodeAnalysis.SuppressMessageAttribute(\"Microsoft.Performance\", \"CA1811:AvoidUncalledPrivateCode\")]\n        internal Resources() {\n        }\n        \n        /// <summary>\n        ///   Returns the cached ResourceManager instance used by this class.\n        /// </summary>\n        [global::System.ComponentModel.EditorBrowsableAttribute(global::System.ComponentModel.EditorBrowsableState.Advanced)]\n        internal static global::System.Resources.ResourceManager ResourceManager {\n            get {\n                if (object.ReferenceEquals(resourceMan, null)) {\n                    global::System.Resources.ResourceManager temp = new global::System.Resources.ResourceManager(\"z80_pla_checker.Properties.Resources\", typeof(Resources).Assembly);\n                    resourceMan = temp;\n                }\n                return resourceMan;\n            }\n        }\n        \n        /// <summary>\n        ///   Overrides the current thread's CurrentUICulture property for all\n        ///   resource lookups using this strongly typed resource class.\n        /// </summary>\n        [global::System.ComponentModel.EditorBrowsableAttribute(global::System.ComponentModel.EditorBrowsableState.Advanced)]\n        internal static global::System.Globalization.CultureInfo Culture {\n            get {\n                return resourceCulture;\n            }\n            set {\n                resourceCulture = value;\n            }\n        }\n    }\n}\n"
  },
  {
    "path": "tools/z80_pla_checker/source/Properties/Resources.resx",
    "content": "<?xml version=\"1.0\" encoding=\"utf-8\"?>\n<root>\n  <!-- \n    Microsoft ResX Schema \n    \n    Version 2.0\n    \n    The primary goals of this format is to allow a simple XML format \n    that is mostly human readable. The generation and parsing of the \n    various data types are done through the TypeConverter classes \n    associated with the data types.\n    \n    Example:\n    \n    ... ado.net/XML headers & schema ...\n    <resheader name=\"resmimetype\">text/microsoft-resx</resheader>\n    <resheader name=\"version\">2.0</resheader>\n    <resheader name=\"reader\">System.Resources.ResXResourceReader, System.Windows.Forms, ...</resheader>\n    <resheader name=\"writer\">System.Resources.ResXResourceWriter, System.Windows.Forms, ...</resheader>\n    <data name=\"Name1\"><value>this is my long string</value><comment>this is a comment</comment></data>\n    <data name=\"Color1\" type=\"System.Drawing.Color, System.Drawing\">Blue</data>\n    <data name=\"Bitmap1\" mimetype=\"application/x-microsoft.net.object.binary.base64\">\n        <value>[base64 mime encoded serialized .NET Framework object]</value>\n    </data>\n    <data name=\"Icon1\" type=\"System.Drawing.Icon, System.Drawing\" mimetype=\"application/x-microsoft.net.object.bytearray.base64\">\n        <value>[base64 mime encoded string representing a byte array form of the .NET Framework object]</value>\n        <comment>This is a comment</comment>\n    </data>\n                \n    There are any number of \"resheader\" rows that contain simple \n    name/value pairs.\n    \n    Each data row contains a name, and value. The row also contains a \n    type or mimetype. Type corresponds to a .NET class that support \n    text/value conversion through the TypeConverter architecture. \n    Classes that don't support this are serialized and stored with the \n    mimetype set.\n    \n    The mimetype is used for serialized objects, and tells the \n    ResXResourceReader how to depersist the object. This is currently not \n    extensible. For a given mimetype the value must be set accordingly:\n    \n    Note - application/x-microsoft.net.object.binary.base64 is the format \n    that the ResXResourceWriter will generate, however the reader can \n    read any of the formats listed below.\n    \n    mimetype: application/x-microsoft.net.object.binary.base64\n    value   : The object must be serialized with \n            : System.Serialization.Formatters.Binary.BinaryFormatter\n            : and then encoded with base64 encoding.\n    \n    mimetype: application/x-microsoft.net.object.soap.base64\n    value   : The object must be serialized with \n            : System.Runtime.Serialization.Formatters.Soap.SoapFormatter\n            : and then encoded with base64 encoding.\n\n    mimetype: application/x-microsoft.net.object.bytearray.base64\n    value   : The object must be serialized into a byte array \n            : using a System.ComponentModel.TypeConverter\n            : and then encoded with base64 encoding.\n    -->\n  <xsd:schema id=\"root\" xmlns=\"\" xmlns:xsd=\"http://www.w3.org/2001/XMLSchema\" xmlns:msdata=\"urn:schemas-microsoft-com:xml-msdata\">\n    <xsd:element name=\"root\" msdata:IsDataSet=\"true\">\n      <xsd:complexType>\n        <xsd:choice maxOccurs=\"unbounded\">\n          <xsd:element name=\"metadata\">\n            <xsd:complexType>\n              <xsd:sequence>\n                <xsd:element name=\"value\" type=\"xsd:string\" minOccurs=\"0\" />\n              </xsd:sequence>\n              <xsd:attribute name=\"name\" type=\"xsd:string\" />\n              <xsd:attribute name=\"type\" type=\"xsd:string\" />\n              <xsd:attribute name=\"mimetype\" type=\"xsd:string\" />\n            </xsd:complexType>\n          </xsd:element>\n          <xsd:element name=\"assembly\">\n            <xsd:complexType>\n              <xsd:attribute name=\"alias\" type=\"xsd:string\" />\n              <xsd:attribute name=\"name\" type=\"xsd:string\" />\n            </xsd:complexType>\n          </xsd:element>\n          <xsd:element name=\"data\">\n            <xsd:complexType>\n              <xsd:sequence>\n                <xsd:element name=\"value\" type=\"xsd:string\" minOccurs=\"0\" msdata:Ordinal=\"1\" />\n                <xsd:element name=\"comment\" type=\"xsd:string\" minOccurs=\"0\" msdata:Ordinal=\"2\" />\n              </xsd:sequence>\n              <xsd:attribute name=\"name\" type=\"xsd:string\" msdata:Ordinal=\"1\" />\n              <xsd:attribute name=\"type\" type=\"xsd:string\" msdata:Ordinal=\"3\" />\n              <xsd:attribute name=\"mimetype\" type=\"xsd:string\" msdata:Ordinal=\"4\" />\n            </xsd:complexType>\n          </xsd:element>\n          <xsd:element name=\"resheader\">\n            <xsd:complexType>\n              <xsd:sequence>\n                <xsd:element name=\"value\" type=\"xsd:string\" minOccurs=\"0\" msdata:Ordinal=\"1\" />\n              </xsd:sequence>\n              <xsd:attribute name=\"name\" type=\"xsd:string\" use=\"required\" />\n            </xsd:complexType>\n          </xsd:element>\n        </xsd:choice>\n      </xsd:complexType>\n    </xsd:element>\n  </xsd:schema>\n  <resheader name=\"resmimetype\">\n    <value>text/microsoft-resx</value>\n  </resheader>\n  <resheader name=\"version\">\n    <value>2.0</value>\n  </resheader>\n  <resheader name=\"reader\">\n    <value>System.Resources.ResXResourceReader, System.Windows.Forms, Version=2.0.0.0, Culture=neutral, PublicKeyToken=b77a5c561934e089</value>\n  </resheader>\n  <resheader name=\"writer\">\n    <value>System.Resources.ResXResourceWriter, System.Windows.Forms, Version=2.0.0.0, Culture=neutral, PublicKeyToken=b77a5c561934e089</value>\n  </resheader>\n</root>"
  },
  {
    "path": "tools/z80_pla_checker/source/Properties/Settings.Designer.cs",
    "content": "//------------------------------------------------------------------------------\n// <auto-generated>\n//     This code was generated by a tool.\n//     Runtime Version:4.0.30319.18444\n//\n//     Changes to this file may cause incorrect behavior and will be lost if\n//     the code is regenerated.\n// </auto-generated>\n//------------------------------------------------------------------------------\n\nnamespace z80_pla_checker.Properties {\n    \n    \n    [global::System.Runtime.CompilerServices.CompilerGeneratedAttribute()]\n    [global::System.CodeDom.Compiler.GeneratedCodeAttribute(\"Microsoft.VisualStudio.Editors.SettingsDesigner.SettingsSingleFileGenerator\", \"10.0.0.0\")]\n    internal sealed partial class Settings : global::System.Configuration.ApplicationSettingsBase {\n        \n        private static Settings defaultInstance = ((Settings)(global::System.Configuration.ApplicationSettingsBase.Synchronized(new Settings())));\n        \n        public static Settings Default {\n            get {\n                return defaultInstance;\n            }\n        }\n        \n        [global::System.Configuration.UserScopedSettingAttribute()]\n        [global::System.Diagnostics.DebuggerNonUserCodeAttribute()]\n        [global::System.Configuration.DefaultSettingValueAttribute(\"../../resources/z80-pla.txt\")]\n        public string plaFileName {\n            get {\n                return ((string)(this[\"plaFileName\"]));\n            }\n            set {\n                this[\"plaFileName\"] = value;\n            }\n        }\n        \n        [global::System.Configuration.UserScopedSettingAttribute()]\n        [global::System.Diagnostics.DebuggerNonUserCodeAttribute()]\n        [global::System.Configuration.DefaultSettingValueAttribute(\"../../resources\")]\n        public string opcodeDir {\n            get {\n                return ((string)(this[\"opcodeDir\"]));\n            }\n            set {\n                this[\"opcodeDir\"] = value;\n            }\n        }\n    }\n}\n"
  },
  {
    "path": "tools/z80_pla_checker/source/Properties/Settings.settings",
    "content": "<?xml version='1.0' encoding='utf-8'?>\n<SettingsFile xmlns=\"http://schemas.microsoft.com/VisualStudio/2004/01/settings\" CurrentProfile=\"(Default)\" GeneratedClassNamespace=\"z80_pla_checker.Properties\" GeneratedClassName=\"Settings\">\n  <Profiles />\n  <Settings>\n    <Setting Name=\"plaFileName\" Type=\"System.String\" Scope=\"User\">\n      <Value Profile=\"(Default)\">../../resources/z80-pla.txt</Value>\n    </Setting>\n    <Setting Name=\"opcodeDir\" Type=\"System.String\" Scope=\"User\">\n      <Value Profile=\"(Default)\">../../resources</Value>\n    </Setting>\n  </Settings>\n</SettingsFile>"
  },
  {
    "path": "tools/z80_pla_checker/source/app.config",
    "content": "<?xml version=\"1.0\"?>\n<configuration>\n<configSections>\n    <sectionGroup name=\"userSettings\" type=\"System.Configuration.UserSettingsGroup, System, Version=4.0.0.0, Culture=neutral, PublicKeyToken=b77a5c561934e089\" >\n        <section name=\"z80_pla_checker.Properties.Settings\" type=\"System.Configuration.ClientSettingsSection, System, Version=4.0.0.0, Culture=neutral, PublicKeyToken=b77a5c561934e089\" allowExeDefinition=\"MachineToLocalUser\" requirePermission=\"false\" />\n    </sectionGroup>\n</configSections>\n<startup><supportedRuntime version=\"v4.0\" sku=\".NETFramework,Version=v4.0\"/></startup><userSettings>\n        <z80_pla_checker.Properties.Settings>\n            <setting name=\"plaFileName\" serializeAs=\"String\">\n                <value>../../resources/z80-pla.txt</value>\n            </setting>\n            <setting name=\"opcodeDir\" serializeAs=\"String\">\n                <value>../../resources</value>\n            </setting>\n        </z80_pla_checker.Properties.Settings>\n    </userSettings>\n</configuration>\n"
  },
  {
    "path": "tools/z80_pla_checker/source/z80_pla_checker.csproj",
    "content": "<?xml version=\"1.0\" encoding=\"utf-8\"?>\n<Project ToolsVersion=\"4.0\" DefaultTargets=\"Build\" xmlns=\"http://schemas.microsoft.com/developer/msbuild/2003\">\n  <PropertyGroup>\n    <Configuration Condition=\" '$(Configuration)' == '' \">Debug</Configuration>\n    <Platform Condition=\" '$(Platform)' == '' \">x86</Platform>\n    <ProductVersion>8.0.30703</ProductVersion>\n    <SchemaVersion>2.0</SchemaVersion>\n    <ProjectGuid>{5BBBB640-6055-46CA-9BEB-3CD35B1CE3EF}</ProjectGuid>\n    <OutputType>WinExe</OutputType>\n    <AppDesignerFolder>Properties</AppDesignerFolder>\n    <RootNamespace>z80_pla_checker</RootNamespace>\n    <AssemblyName>z80_pla_checker</AssemblyName>\n    <TargetFrameworkVersion>v4.0</TargetFrameworkVersion>\n    <TargetFrameworkProfile>\n    </TargetFrameworkProfile>\n    <FileAlignment>512</FileAlignment>\n  </PropertyGroup>\n  <PropertyGroup Condition=\" '$(Configuration)|$(Platform)' == 'Debug|x86' \">\n    <PlatformTarget>x86</PlatformTarget>\n    <DebugSymbols>true</DebugSymbols>\n    <DebugType>full</DebugType>\n    <Optimize>false</Optimize>\n    <OutputPath>bin\\Debug\\</OutputPath>\n    <DefineConstants>DEBUG;TRACE</DefineConstants>\n    <ErrorReport>prompt</ErrorReport>\n    <WarningLevel>4</WarningLevel>\n  </PropertyGroup>\n  <PropertyGroup Condition=\" '$(Configuration)|$(Platform)' == 'Release|x86' \">\n    <PlatformTarget>x86</PlatformTarget>\n    <DebugType>pdbonly</DebugType>\n    <Optimize>true</Optimize>\n    <OutputPath>bin\\Release\\</OutputPath>\n    <DefineConstants>TRACE</DefineConstants>\n    <ErrorReport>prompt</ErrorReport>\n    <WarningLevel>4</WarningLevel>\n  </PropertyGroup>\n  <ItemGroup>\n    <Reference Include=\"System\" />\n    <Reference Include=\"System.Core\" />\n    <Reference Include=\"System.Xml.Linq\" />\n    <Reference Include=\"System.Data.DataSetExtensions\" />\n    <Reference Include=\"Microsoft.CSharp\" />\n    <Reference Include=\"System.Data\" />\n    <Reference Include=\"System.Deployment\" />\n    <Reference Include=\"System.Drawing\" />\n    <Reference Include=\"System.Windows.Forms\" />\n    <Reference Include=\"System.Xml\" />\n  </ItemGroup>\n  <ItemGroup>\n    <Compile Include=\"ClassLog.cs\" />\n    <Compile Include=\"ClassOpcodeTable.cs\" />\n    <Compile Include=\"ClassPLA.cs\" />\n    <Compile Include=\"ClassPLAEntry.cs\" />\n    <Compile Include=\"FormMain.cs\">\n      <SubType>Form</SubType>\n    </Compile>\n    <Compile Include=\"FormMain.Designer.cs\">\n      <DependentUpon>FormMain.cs</DependentUpon>\n    </Compile>\n    <Compile Include=\"Program.cs\" />\n    <Compile Include=\"Properties\\AssemblyInfo.cs\" />\n    <EmbeddedResource Include=\"FormMain.resx\">\n      <DependentUpon>FormMain.cs</DependentUpon>\n    </EmbeddedResource>\n    <EmbeddedResource Include=\"Properties\\Resources.resx\">\n      <Generator>ResXFileCodeGenerator</Generator>\n      <LastGenOutput>Resources.Designer.cs</LastGenOutput>\n      <SubType>Designer</SubType>\n    </EmbeddedResource>\n    <Compile Include=\"Properties\\Resources.Designer.cs\">\n      <AutoGen>True</AutoGen>\n      <DependentUpon>Resources.resx</DependentUpon>\n      <DesignTime>True</DesignTime>\n    </Compile>\n    <None Include=\"app.config\" />\n    <None Include=\"Properties\\Settings.settings\">\n      <Generator>SettingsSingleFileGenerator</Generator>\n      <LastGenOutput>Settings.Designer.cs</LastGenOutput>\n    </None>\n    <Compile Include=\"Properties\\Settings.Designer.cs\">\n      <AutoGen>True</AutoGen>\n      <DependentUpon>Settings.settings</DependentUpon>\n      <DesignTimeSharedInput>True</DesignTimeSharedInput>\n    </Compile>\n  </ItemGroup>\n  <Import Project=\"$(MSBuildToolsPath)\\Microsoft.CSharp.targets\" />\n  <!-- To modify your build process, add your task inside one of the targets below and uncomment it. \n       Other similar extension points exist, see Microsoft.Common.targets.\n  <Target Name=\"BeforeBuild\">\n  </Target>\n  <Target Name=\"AfterBuild\">\n  </Target>\n  -->\n</Project>"
  },
  {
    "path": "tools/z80_pla_checker/source/z80_pla_checker.sln",
    "content": "\nMicrosoft Visual Studio Solution File, Format Version 11.00\n# Visual Studio 2010\nProject(\"{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC}\") = \"z80_pla_checker\", \"z80_pla_checker.csproj\", \"{5BBBB640-6055-46CA-9BEB-3CD35B1CE3EF}\"\nEndProject\nGlobal\n\tGlobalSection(SolutionConfigurationPlatforms) = preSolution\n\t\tDebug|x86 = Debug|x86\n\t\tRelease|x86 = Release|x86\n\tEndGlobalSection\n\tGlobalSection(ProjectConfigurationPlatforms) = postSolution\n\t\t{5BBBB640-6055-46CA-9BEB-3CD35B1CE3EF}.Debug|x86.ActiveCfg = Debug|x86\n\t\t{5BBBB640-6055-46CA-9BEB-3CD35B1CE3EF}.Debug|x86.Build.0 = Debug|x86\n\t\t{5BBBB640-6055-46CA-9BEB-3CD35B1CE3EF}.Release|x86.ActiveCfg = Release|x86\n\t\t{5BBBB640-6055-46CA-9BEB-3CD35B1CE3EF}.Release|x86.Build.0 = Release|x86\n\tEndGlobalSection\n\tGlobalSection(SolutionProperties) = preSolution\n\t\tHideSolutionNode = FALSE\n\tEndGlobalSection\nEndGlobal\n"
  },
  {
    "path": "tools/zmac/bin2coe.py",
    "content": "#!/usr/bin/env python3\nimport sys, os\nfrom argparse import ArgumentParser\n\nparser = ArgumentParser(description='Converts binary file to Xilinx coe file')\n\nparser.add_argument('infile', help='Input binary file')\nparser.add_argument('outfile', help='Output coe file')\nparser.add_argument('-d', '--depth', type=int, default=0)\nargs = parser.parse_args()\n\nwith open(args.infile, 'rb') as f:\n    depth = os.path.getsize(args.infile)\n    if args.depth > 0:\n        if args.depth < depth:\n            print (\"ERROR: Input file is larger than the specified depth!\")\n            exit (-1)\n        depth = args.depth\n\n    with open(args.outfile, 'w') as fmif:\n        fmif.write('; Automatically generated by bin2coe.py\\n')\n        fmif.write('; Translated from ' + args.infile + '\\n')\n        fmif.write('memory_initialization_radix=16;\\n')\n        fmif.write('memory_initialization_vector=\\n')\n\n        count = 0\n        buffer = f.read()\n        for b in buffer:\n            if count > 0:\n                fmif.write(',\\n')\n            fmif.write('{0:02x}'.format(b))\n            count += 1\n\n        while count < depth:\n            if count < depth:\n                fmif.write(',\\n')\n            fmif.write('00')\n            count += 1\n        fmif.write(';\\n')\n"
  },
  {
    "path": "tools/zmac/bin2hex.txt",
    "content": "Bin2Hex utility:\n\nhttp://www.ht-lab.com/freeutils/bin2hex/bin2hex.html\n\nBIN2HEX is a simple utility which converts a binary file to an Intel HEX file. BIN2HEX is limited to 64Kbyte binary files.\n\nBIN2HEX <input_binary_filename> <output_hex_filename>  {-o offset} {-s segment} {-e execute}\n\nWhere Optional:\n    offset      Output file address offset in hex. \n    segment     Extended address record offset in hex (e.g. Segment address on a 8086).\n    execute     Execute address offset in hex (e.g. IP address on a 8086).\n"
  },
  {
    "path": "tools/zmac/bin2mif.py",
    "content": "#!/usr/bin/env python3\nimport sys, os\nfrom argparse import ArgumentParser\n\nparser = ArgumentParser(description='Converts binary file to mif file')\n\nparser.add_argument('infile', help='Input binary file')\nparser.add_argument('outfile', help='Output mif file')\nparser.add_argument('-d', '--depth', help='Total memory depth (fill with zeros)', type=int, default=0)\nparser.add_argument('-s', '--simple', help='Simple format (data only)', action=\"store_true\", default=False)\nargs = parser.parse_args()\n\nwith open(args.infile, 'rb') as f:\n    depth = os.path.getsize(args.infile)\n    if args.depth > 0:\n        if args.depth < depth:\n            print (\"ERROR: Input file is larger than the specified depth!\")\n            exit (-1)\n        depth = args.depth\n\n    with open(args.outfile, 'w') as fmif:\n        if args.simple:\n            count = 0\n            buffer = f.read()\n            for b in buffer:\n                fmif.write('{0:08b}\\n'.format(b))\n                count += 1\n            while count < depth:\n                fmif.write('00000000')\n                count += 1\n        else:\n            fmif.write('-- Automatically generated by bin2mif.py\\n')\n            fmif.write('-- Translated from ' + args.infile + '\\n')\n            fmif.write('DEPTH = {};\\n'.format(depth))\n            fmif.write('WIDTH = 8;\\n')\n            fmif.write('ADDRESS_RADIX = DEC;\\n')\n            fmif.write('DATA_RADIX = HEX;\\n')\n            fmif.write('CONTENT\\n')\n            fmif.write('BEGIN\\n')\n\n            count = 0\n            buffer = f.read()\n            for b in buffer:\n                fmif.write('{0:<4}: {1:02x};\\n'.format(count, b))\n                count += 1\n            if count < depth:\n                fmif.write('[{0}..{1}] : 0;\\n'.format(count, depth))\n            fmif.write('END;\\n')\n"
  },
  {
    "path": "tools/zmac/bindump.py",
    "content": "#!/usr/bin/env python3\n#\n# This script reads a binary file and writes it out in the ASCII format\n# that lists each 8-bit word in a hex format without 0x.\n#\n# This format can be read by SystemVerilog function $readmemh()\n#\n# Usage:  python bindump.py <input-file> [<output-file>]\n#\n# If the output file is not given, \"out.hex\" will be created.\n#\nimport sys\n\nif len(sys.argv)<2:\n    print (\"Usage:  python bindump.py <input-file> [<output-file>]\")\n    exit(-1)\n\nfilename = sys.argv[1]\noutfile = \"out.hex\"\ncol = 0;\nif len(sys.argv)==3:\n    outfile = sys.argv[2]\nwith open(filename, \"rb\") as f, open(outfile, \"w\") as o:\n    block = f.read(65536)\n    for ch in block:\n        #print ('{0:02X}'.format(ch))\n        o.write('{0:02X} '.format(ch))\n        col = col + 1\n        if col==16:\n            o.write(\"\\n\")\n            col = 0;\nprint (\"Created\", outfile)\n"
  },
  {
    "path": "tools/zmac/hello_world.asm",
    "content": ";==============================================================================\n; Test code for the A-Z80 CPU that prints \"Hello, World!\"\n; Also used to test responses to interrupts.\n;==============================================================================\n    org 0\nstart:\n    jmp boot\n\n    ; BDOS entry point for various functions\n    ; We implement subfunctions:\n    ;  C=2  Print a character given in E\n    ;  C=9  Print a string pointed to by DE; string ends with '$'\n    org 5\n    ld  a,c\n    cp  a,2\n    jz  bdos_ascii\n    cp  a,9\n    jz  bdos_msg\n    ret\n\nbdos_ascii:\n    ld  bc,10*256   ; Port to check for busy\n    in  a,(c)       ; Poll until the port is not busy\n    bit 0,a\n    jnz bdos_ascii\n    ld  bc,8*256    ; Port to write a character out\n    out (c),e\n    ret\n\nbdos_msg:\n    push de\n    pop hl\nlp0:\n    ld  e,(hl)\n    ld  a,e\n    cp  a,'$'\n    ret z\n    call bdos_ascii\n    inc hl\n    jmp lp0\n\n;---------------------------------------------------------------------\n; RST38 (also INT M0)  handler\n;---------------------------------------------------------------------\n    org 038h\n    push de\n    ld  de,int_msg\nint_common:\n    push af\n    push bc\n    push hl\n    ld  c,9\n    call 5\n    pop hl\n    pop bc\n    pop af\n    pop de\n    ei\n    reti\nint_msg:\n    db  \"_INT_\",'$'\n\n;---------------------------------------------------------------------\n; NMI handler\n;---------------------------------------------------------------------\n    org 066h\n    push af\n    push bc\n    push de\n    push hl\n    ld  de,nmi_msg\n    ld  c,9\n    call 5\n    pop hl\n    pop de\n    pop bc\n    pop af\n    retn\nnmi_msg:\n    db  \"_NMI_\",'$'\n\n;---------------------------------------------------------------------\n; IM2 vector address and the handler (to push 0x80 by the IORQ)\n;---------------------------------------------------------------------\n    org 080h\n    dw  im2_handler\nim2_handler:\n    push de\n    ld  de,int_im2_msg\n    jmp int_common\nint_im2_msg:\n    db  \"_IM2_\",'$'\nboot:\n    ; Set the stack pointer\n    ld  sp, 16384    ; 16 Kb of RAM\n    ; Set up for interrupt testing: see Z80\\cpu\\toplevel\\test_top.sv\n    ; IMPORTANT: To test IM0, Verilog test code needs to put 0xFF on the bus\n    ;            To test IM2, the test code needs to put a vector of 0x80 !!\n    ;            This is done in tb_iorq.sv\n    im  2\n    ld  a,0\n    ld  i,a\n    ei\n    ;halt\n    ; Jump into the executable at 100h\n    jmp 100h\n\n;==============================================================================\n;\n; Prints \"Hello, World!\"\n;\n;==============================================================================\n    org 100h\n    ld  hl,0\n    ld  (counter),hl\nexec:\n    ld  de,hello\n    ld  c,9\n    call 5\n\n    ; Print the counter and the stack pointer to make sure it does not change\n    ld  hl, (counter)\n    inc hl\n    ld  (counter),hl\n\n    ld  hl, text\n    ld  a,(counter+1)\n    call tohex\n    ld  hl, text+2\n    ld  a,(counter)\n    call tohex\n\n    ld  (stack),sp\n\n; Several options on which values we want to dump, uncomment only one:\n    ld  hl, text+5\n;   ld  a,(stack+1)     ; Dump stack pointer (useful to check SP)\n    ld  a, i            ; Show IR register\n    call tohex\n    ld  hl, text+7\n;   ld  a,(stack)       ; Dump stack pointer (useful to check SP)\n    ld  a, r            ; Show IR register\n    call tohex\n\n; Two versions of the code: either keep printing the text indefinitely (which\n; can be used for interrupt testing), or print it only once and die\ndie:\n    jr exec\n;    jr die\n\ntohex:\n    ; HL = Address to store a hex value\n    ; A  = Hex value 00-FF\n    push af\n    and  a,0fh\n    cmp  a,10\n    jc   skip1\n    add  a, 'A'-'9'-1\nskip1:\n    add  a, '0'\n    inc  hl\n    ld   (hl),a\n    dec  hl\n    pop  af\n    rra\n    rra\n    rra\n    rra\n    and  a,0fh\n    cmp  a,10\n    jc   skip2\n    add  a, 'A'-'9'-1\nskip2:\n    add  a, '0'\n    ld   (hl),a\n    ret\n\n; Print a counter before Hello, World so we can see if the\n; processor rebooted during one of the interrupts. Also, print the content\n; of the SP register which should stay fixed and \"uninterrupted\"\ncounter: dw 0\nstack: dw 0\n\nhello:\n    db  13,10\ntext:\n    db '---- ---- Hello, World!$'\n\nend\n"
  },
  {
    "path": "tools/zmac/make_fpga.bat",
    "content": "@echo off\nRem\nRem     Assembles Z80 source file into object code and generates various\nRem     formats of that code to be used by FPGA test projects.\nRem\nRem     Intel HEX files are used by ModelSim and Altera synthesis,\nRem     COE and MIF files are used by Xilinx and its ISim simulation.\nRem\nRem     Give it an argument of the ASM file you want to use, or you can simply drag\nRem     and drop an asm file into it. If you drop an ASM file and there were errors,\nRem     this script will keep the DOS window open so you can see the errors.\nRem\nzmac.exe --zmac %1\nif errorlevel 1 goto error\nbin2hex.exe zout\\%~n1.cim fpga.hex\nif errorlevel 1 goto error\npython bin2coe.py zout\\%~n1.cim ram.coe\nif errorlevel 1 goto error\npython bin2mif.py --simple zout\\%~n1.cim ram.mif\nif errorlevel 1 goto error\n\nRem     Copy hex files to their target Quartus/ModelSim host directories\ncopy /Y fpga.hex ..\\..\\host\\basic_de1\ncopy /Y fpga.hex ..\\..\\host\\basic_de1\\simulation\\modelsim\n\nRem     Copy .mif and .coe files to their target Xilinx host directories\ncopy /Y ram.mif ..\\..\\host\\basic_nexys3\\work\ngoto end\n\n:error\n@echo ------------------------------------------------------\n@echo Errors processing %1\n@echo ------------------------------------------------------\ncmd\n:end"
  },
  {
    "path": "tools/zmac/make_modelsim.bat",
    "content": "@echo off\nRem\nRem     This batch file assembles and generates executable code for a ModelSim test at\nRem     \\cpu\\toplevel\\simulation\\modelsim         (Select \"test_top\" test in ModelSim)\nRem\nRem     Give it an argument of the ASM file you want to use, or you can simply drag\nRem     and drop an asm file into it. If you drop an ASM file and there were errors,\nRem     this script will keep the DOS window open so you can see the errors.\nRem\nzmac --zmac %1\nif errorlevel 1 goto error\npython bindump.py zout\\%~n1.cim ..\\..\\cpu\\toplevel\\simulation\\modelsim\\ram.hexdump\nif errorlevel 1 goto error\ngoto end\n\n:error\n@echo ------------------------------------------------------\n@echo Errors assembling %1\n@echo ------------------------------------------------------\ncmd\n:end"
  },
  {
    "path": "tools/zmac/readme.txt",
    "content": "This directory supports several processes:\n\n1. Generation of Z80 test code for ModelSim and FPGA at the \"host/basic\" level:\n\n  Run the batch file \"make_fpga.bat\" to generate \"fpga.hex\" from a test source file.\n  This file is included by the host/basic/ram.v module into the FPGA image.\n\n2. Generation of Z80 test code for the toplevel A-Z80 CPU ModelSim at the\n   \"cpu/toplevel/simulation/modelsim\" level:\n\n  Run the batch file \"make_modelsim.bat\" to generate this test file.\n\n  /cpu/toplevel/tb_ram.sv is a ModelSim test bench for the toplevel A-Z80 block.\n  There is no \"host board\" at that level but ModelSim's UART device will capture\n  and print any output.\n\n  \"ram.hexdump\" contains the test code that provides UART print functions as well\n  as INT/NMI handlers used to test interrupts.\n\nCurrently tested sources, which should work in both of those use cases, are:\n\n     \"hello_world.asm\" - simply test UART print out functions\n\n     \"test.daa.asm\" - runs DAA instruction on all values. The output should be\n     ASCII-identical to the output of the DAA tests at tools/dongle/daa\n\n     \"test.neg.asm\" - runs NEG instruction on all values. The output should be\n     ASCII-identical to the output of the NEG tests at tools/dongle/neg\n\n     \"zexdoc.asm\" - modified ZEXDOC test program\n"
  },
  {
    "path": "tools/zmac/test.daa.asm",
    "content": ";==============================================================================\n; Test code for the A-Z80 CPU\n;==============================================================================\n    org 0\nstart:\n    jmp boot\n\n    ; BDOS entry point for various functions\n    ; We implement subfunctions:\n    ;  C=2  Print a character given in E\n    ;  C=9  Print a string pointed to by DE; string ends with '$'\n    org 5\n    ld  a,c\n    cp  a,2\n    jz  bdos_ascii\n    cp  a,9\n    jz  bdos_msg\n    ret\n\nbdos_ascii:\n    ld  bc,10*256   ; Port to check for busy\n    in  a,(c)       ; Poll until the port is not busy\n    bit 0,a\n    jnz bdos_ascii\n    ld  bc,8*256    ; Port to write a character out\n    out (c),e\n    ret\n\nbdos_msg:\n    push de\n    pop hl\nlp0:\n    ld  e,(hl)\n    ld  a,e\n    cp  a,'$'\n    ret z\n    call bdos_ascii\n    inc hl\n    jmp lp0\n\n;---------------------------------------------------------------------\n; RST38 (also INT M0)  handler\n;---------------------------------------------------------------------\n    org 038h\n    push de\n    ld  de,int_msg\nint_common:\n    push af\n    push bc\n    push hl\n    ld  c,9\n    call 5\n    pop hl\n    pop bc\n    pop af\n    pop de\n    ei\n    reti\nint_msg:\n    db  \"_INT_\",'$'\n\n;---------------------------------------------------------------------\n; NMI handler\n;---------------------------------------------------------------------\n    org 066h\n    push af\n    push bc\n    push de\n    push hl\n    ld  de,nmi_msg\n    ld  c,9\n    call 5\n    pop hl\n    pop de\n    pop bc\n    pop af\n    retn\nnmi_msg:\n    db  \"_NMI_\",'$'\n\n;---------------------------------------------------------------------\n; IM2 vector address and the handler (to push 0x80 by the IORQ)\n;---------------------------------------------------------------------\n    org 080h\n    dw  im2_handler\nim2_handler:\n    push de\n    ld  de,int_im2_msg\n    jmp int_common\nint_im2_msg:\n    db  \"_IM2_\",'$'\nboot:\n    ; Set the stack pointer\n    ld  sp, 16384    ; 16 Kb of RAM\n    ; Jump into the executable at 100h\n    jmp 100h\n\n;==============================================================================\n;\n; Dumps DAA variations\n;\n;==============================================================================\n    org 100h\nexec:\n    ld  hl, flag_f\nlp1:\n    ld  a, (hl)\n    cp  a, 0ffh\ndie:jz  die\n    push hl\n    ld  c,a\n    ld  b,0\nlp2:\n    push bc\n    ld  a,c\n    ld  hl, text+2\n    call tohex\n    ld  a,b\n    ld  hl, text+7\n    call tohex\n\n    push bc\n    pop  af\n    daa\n    push af\n    pop bc\n\n    ld  a,b\n    ld  hl, text+13\n    call tohex\n    ld  a,c\n    ld  hl, text+18\n    call tohex\n\n    exx\n    ld  de,text\n    ld  c,9\n    call 5\n    exx\n\n    pop bc\n    inc b\n    ld  a,b\n    or  a,a\n    jnz lp2\n\n    pop  hl\n    inc  hl\n    jmp  lp1\n\ntohex:\n    ; HL = Address to store a hex value\n    ; A  = Hex value 00-FF\n    push af\n    and  a,0fh\n    cmp  a,10\n    jc   skip1\n    add  a, 'A'-'9'-1\nskip1:\n    add  a, '0'\n    inc  hl\n    ld   (hl),a\n    dec  hl\n    pop  af\n    rra\n    rra\n    rra\n    rra\n    and  a,0fh\n    cmp  a,10\n    jc   skip2\n    add  a, 'A'-'9'-1\nskip2:\n    add  a, '0'\n    ld   (hl),a\n    ret\n\nflag_f:\n    db  00h, 01h, 10h, 11h, 02h, 03h, 12h, 13h, 0ffh\ntext:\n    ;    01234567890123456789\n    db  \"F:00 A:00 -> 00 F:00\",13,10,'$'\nend\n"
  },
  {
    "path": "tools/zmac/test.neg.asm",
    "content": ";==============================================================================\n; Test code for the A-Z80 CPU\n;==============================================================================\n    org 0\nstart:\n    jmp boot\n\n    ; BDOS entry point for various functions\n    ; We implement subfunctions:\n    ;  C=2  Print a character given in E\n    ;  C=9  Print a string pointed to by DE; string ends with '$'\n    org 5\n    ld  a,c\n    cp  a,2\n    jz  bdos_ascii\n    cp  a,9\n    jz  bdos_msg\n    ret\n\nbdos_ascii:\n    ld  bc,10*256   ; Port to check for busy\n    in  a,(c)       ; Poll until the port is not busy\n    bit 0,a\n    jnz bdos_ascii\n    ld  bc,8*256    ; Port to write a character out\n    out (c),e\n    ret\n\nbdos_msg:\n    push de\n    pop hl\nlp0:\n    ld  e,(hl)\n    ld  a,e\n    cp  a,'$'\n    ret z\n    call bdos_ascii\n    inc hl\n    jmp lp0\n\n;---------------------------------------------------------------------\n; RST38 (also INT M0)  handler\n;---------------------------------------------------------------------\n    org 038h\n    push de\n    ld  de,int_msg\nint_common:\n    push af\n    push bc\n    push hl\n    ld  c,9\n    call 5\n    pop hl\n    pop bc\n    pop af\n    pop de\n    ei\n    reti\nint_msg:\n    db  \"_INT_\",'$'\n\n;---------------------------------------------------------------------\n; NMI handler\n;---------------------------------------------------------------------\n    org 066h\n    push af\n    push bc\n    push de\n    push hl\n    ld  de,nmi_msg\n    ld  c,9\n    call 5\n    pop hl\n    pop de\n    pop bc\n    pop af\n    retn\nnmi_msg:\n    db  \"_NMI_\",'$'\n\n;---------------------------------------------------------------------\n; IM2 vector address and the handler (to push 0x80 by the IORQ)\n;---------------------------------------------------------------------\n    org 080h\n    dw  im2_handler\nim2_handler:\n    push de\n    ld  de,int_im2_msg\n    jmp int_common\nint_im2_msg:\n    db  \"_IM2_\",'$'\nboot:\n    ; Set the stack pointer\n    ld  sp, 16384    ; 16 Kb of RAM\n    ; Jump into the executable at 100h\n    jmp 100h\n\n;==============================================================================\n;\n; Dumps NEG variations\n;\n;==============================================================================\n    org 100h\nexec:\n    ld  b,0\nlp2:\n    push bc\n    ld  a,b\n    ld  hl, text+0\n    call tohex\n\n    push bc\n    pop  af\n    neg\n    push af\n    pop bc\n\n    ld  a,b\n    ld  hl, text+6\n    call tohex\n    ld  a,c\n    ld  hl, text+18\n    call tohex\n\n    exx\n    ld  de,text\n    ld  c,9\n    call 5\n    exx\n\n    pop bc\n    inc b\n    ld  a,b\n    or  a,a\n    jnz lp2\ndie:\n    jmp die\n\ntohex:\n    ; HL = Address to store a hex value\n    ; A  = Hex value 00-FF\n    push af\n    and  a,0fh\n    cmp  a,10\n    jc   skip1\n    add  a, 'A'-'9'-1\nskip1:\n    add  a, '0'\n    inc  hl\n    ld   (hl),a\n    dec  hl\n    pop  af\n    rra\n    rra\n    rra\n    rra\n    and  a,0fh\n    cmp  a,10\n    jc   skip2\n    add  a, 'A'-'9'-1\nskip2:\n    add  a, '0'\n    ld   (hl),a\n    ret\n\ntext:\n    ;    01234567890123456789\n    db  \"00 -> 00  Flags = 00\",13,10,'$'\nend\n"
  },
  {
    "path": "tools/zmac/zexall.asm",
    "content": "\ttitle\t'Z80 instruction set exerciser'\n\n; zexall.src - Z80 instruction set exerciser\n; Original Copyright (C) 1994  Frank D. Cringle\n; Changes at 03-Nov-2002 Copyright (C) 2002 J.G.Harston\n; + Source syntax tweeked to assemble with ZMAC Z80 Macro Assembler\n;   and MAXAM Assembler, marked in the source with 'jgh:'\n; + labels on equates mustn't have trailing colon\n; + macros don't understand <...> sequence, so parameters are passed\n;   explicitly\n; + ds n,c not supported, so strings are set to full explicity length\n;\n; This program is free software; you can redistribute it and/or\n; modify it under the terms of the GNU General Public License\n; as published by the Free Software Foundation; either version 2\n; of the License, or (at your option) any later version.\n;\n; This program is distributed in the hope that it will be useful,\n; but WITHOUT ANY WARRANTY; without even the implied warranty of\n; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n; GNU General Public License for more details.\n;\n; You should have received a copy of the GNU General Public License\n; along with this program; if not, write to the Free Software\n; Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.\n\n\taseg\n\n;\n; Boot code for the A-Z80 CPU FPGA implementation\n;\n    org 0\nstart:\n    jmp boot\n\n    ; BDOS entry point for various functions\n    ; We implement subfunctions:\n    ;  C=2  Print a character given in E\n    ;  C=9  Print a string pointed to by DE; string ends with '$'\n    org 5\n    ld  a,c\n    cp  a,2\n    jz  bdos_ascii\n    cp  a,9\n    jz  bdos_msg\n    ret\n\nbdos_ascii:\n    ld  bc,10*256   ; Port to check for busy\n    in  a,(c)       ; Poll until the port is not busy\n    bit 0,a\n    jnz bdos_ascii\n    ld  bc,8*256    ; Port to write a character out\n    out (c),e\n    ret\n\nbdos_msg:\n    push de\n    pop hl\nlp0:\n    ld  e,(hl)\n    ld  a,e\n    cp  a,'$'\n    ret z\n    call bdos_ascii\n    inc hl\n    jmp lp0\n\n;---------------------------------------------------------------------\n; RST38 (also INT M0)  handler\n;---------------------------------------------------------------------\n    org 038h\n    push de\n    ld  de,int_msg\nint_common:\n    push af\n    push bc\n    push hl\n    ld  c,9\n    call 5\n    pop hl\n    pop bc\n    pop af\n    pop de\n    ei\n    reti\nint_msg:\n    db  \"_INT_\",'$'\n\n;---------------------------------------------------------------------\n; NMI handler\n;---------------------------------------------------------------------\n    org 066h\n    push af\n    push bc\n    push de\n    push hl\n    ld  de,nmi_msg\n    ld  c,9\n    call 5\n    pop hl\n    pop de\n    pop bc\n    pop af\n    retn\nnmi_msg:\n    db  \"_NMI_\",'$'\n\n;---------------------------------------------------------------------\n; IM2 vector address and the handler (to push 0x80 by the IORQ)\n;---------------------------------------------------------------------\n    org 080h\n    dw  im2_handler\nim2_handler:\n    push de\n    ld  de,int_im2_msg\n    jmp int_common\nint_im2_msg:\n    db  \"_IM2_\",'$'\n\nboot:\n    ; Set the stack pointer\n    ld  sp, 16384   ; 16 Kb of RAM\n    ; Jump into the executable at 100h\n    jmp 100h\n\n\torg\t100h\n\n\tjp\tstart100\n\n; machine state before test (needs to be at predictably constant address)\nmsbt:\tds\t14\nspbt:\tds\t2\nmsbthi\tequ\tmsbt / 0100h\nmsbtlo\tequ\tmsbt & 0ffh\n\n\n; For the purposes of this test program, the machine state consists of:\n;\ta 2 byte memory operand, followed by\n;\tthe registers iy,ix,hl,de,bc,af,sp\n; for a total of 16 bytes.\n\n; The program tests instructions (or groups of similar instructions)\n; by cycling through a sequence of machine states, executing the test\n; instruction for each one and running a 32-bit crc over the resulting\n; machine states.  At the end of the sequence the crc is compared to\n; an expected value that was found empirically on a real Z80.\n\n; A test case is defined by a descriptor which consists of:\n;\ta flag mask byte,\n;\tthe base case,\n;\tthe incement vector,\n;\tthe shift vector,\n;\tthe expected crc,\n;\ta short descriptive message.\n;\n; The flag mask byte is used to prevent undefined flag bits from\n; influencing the results.  Documented flags are as per Mostek Z80\n; Technical Manual.\n;\n; The next three parts of the descriptor are 20 byte vectors\n; corresponding to a 4 byte instruction and a 16 byte machine state.\n; The first part is the base case, which is the first test case of\n; the sequence.  This base is then modified according to the next 2\n; vectors.  Each 1 bit in the increment vector specifies a bit to be\n; cycled in the form of a binary counter.  For instance, if the byte\n; corresponding to the accumulator is set to 0ffh in the increment\n; vector, the test will be repeated for all 256 values of the\n; accumulator.  Note that 1 bits don't have to be contiguous.  The\n; number of test cases 'caused' by the increment vector is equal to\n; 2^(number of 1 bits).  The shift vector is similar, but specifies a\n; set of bits in the test case that are to be successively inverted.\n; Thus the shift vector 'causes' a number of test cases equal to the\n; number of 1 bits in it.\n\n; The total number of test cases is the product of those caused by the\n; counter and shift vectors and can easily become unweildy.  Each\n; individual test case can take a few milliseconds to execute, due to\n; the overhead of test setup and crc calculation, so test design is a\n; compromise between coverage and execution time.\n\n; This program is designed to detect differences between\n; implementations and is not ideal for diagnosing the causes of any\n; discrepancies.  However, provided a reference implementation (or\n; real system) is available, a failing test case can be isolated by\n; hand using a binary search of the test space.\n\n\nstart100:\tld\thl,(6)\n\t;ld\tsp,hl\n\tld\tde,msg1\n\tld\tc,9\n\tcall\tbdos\n\n\tld\thl,tests\t; first test case\nloop:\tld\ta,(hl)\t\t; end of list ?\n\tinc\thl\n\tor\t(hl)\n\tjp\tz,done\n\tdec\thl\n\tcall\tstt\n\tjp\tloop\n\t\ndone:\tld\tde,msg2\n\tld\tc,9\n\tcall\tbdos\ndie: jr die\n\tjp\t0\t\t; warm boot\n\ntests:\n\tdw\tadc16\n\tdw\tadd16\n\tdw\tadd16x\n\tdw\tadd16y\n\tdw\talu8i\n\tdw\talu8r\n\tdw\talu8rx\n\tdw\talu8x\n\tdw\tbitx\n\tdw\tbitz80\n\tdw\tcpd1\n\tdw\tcpi1\n\tdw\tdaaop\t; can't use opcode as label\n\tdw\tinca\n\tdw\tincb\n\tdw\tincbc\n\tdw\tincc\n\tdw\tincd\n\tdw\tincde\n\tdw\tince\n\tdw\tinch\n\tdw\tinchl\n\tdw\tincix\n\tdw\tinciy\n\tdw\tincl\n\tdw\tincm\n\tdw\tincsp\n\tdw\tincx\n\tdw\tincxh\n\tdw\tincxl\n\tdw\tincyh\n\tdw\tincyl\n\tdw\tld161\n\tdw\tld162\n\tdw\tld163\n\tdw\tld164\n\tdw\tld165\n\tdw\tld166\n\tdw\tld167\n\tdw\tld168\n\tdw\tld16im\n\tdw\tld16ix\n\tdw\tld8bd\n\tdw\tld8im\n\tdw\tld8imx\n\tdw\tld8ix1\n\tdw\tld8ix2\n\tdw\tld8ix3\n\tdw\tld8ixy\n\tdw\tld8rr\n\tdw\tld8rrx\n\tdw\tlda\n\tdw\tldd1\n\tdw\tldd2\n\tdw\tldi1\n\tdw\tldi2\n\tdw\tnegop\t; jgh: can't use opcode as label\n\tdw\trldop\t; jgh: can't use opcode as label\n\tdw\trot8080\n\tdw\trotxy\n\tdw\trotz80\n\tdw\tsrz80\n\tdw\tsrzx\n\tdw\tst8ix1\n\tdw\tst8ix2\n\tdw\tst8ix3\n\tdw\tstabd\n\tdw\t0\n\n; jgh: macro syntax changed for ZMAC and MAXAM\n;\tcan't use opcodes as labels\n;\tZMAC allows &nn as hex, so & removed from local labels\n;\ntstr\tmacro\tinsn1,insn2,insn3,insn4,memop,riy,rix,rhl,rde,rbc,flags,acc,rsp,?lab\n?lab:\tdb\tinsn1,insn2,insn3,insn4\n\tdw\tmemop,riy,rix,rhl,rde,rbc\n\tdb\tflags\n\tdb\tacc\n\tdw\trsp\n\tif\t$-?lab ne 20\n\terror\t'missing parameter'\n\tendif\n\tendm\n\ntmsg\tmacro\tmsg,?lab\n?lab:\tdb\t'msg'\n\tif\t$ ge ?lab+31\n\terror\t'message too long'\n\telse\n;\tds\t?lab+30-$,'.'\t; jgh: ZMAC/MAXAM don't have char parameter\n\tendif\n\tdb\t'$'\n\tendm\n\n; jgh: ZMAC/MAXAM don't recognise <n,m> syntax for macros, so full parameters given\n; jgh: each tmsg has full string, as ZMAC/MAXAM don't have ds n,c pseudo-op\n\n; <adc,sbc> hl,<bc,de,hl,sp> (38,912 cycles)\nadc16:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0edh,042h,0,0,0832ch,04f88h,0f22bh,0b339h,07e1fh,01563h,0d3h,089h,0465eh\n\ttstr\t0,038h,0,0,0,0,0,0f821h,0,0,0,0,0\t; (1024 cycles)\n\ttstr\t0,0,0,0,0,0,0,-1,-1,-1,0d7h,0,-1\t; (38 cycles)\n\tdb\t0d4h,08ah,0d5h,019h\t\t\t; expected crc\n\ttmsg\t'<adc,sbc> hl,<bc,de,hl,sp>....'\n\n; add hl,<bc,de,hl,sp> (19,456 cycles)\nadd16:\tdb\t0ffh\t\t; flag mask\n\ttstr\t9,0,0,0,0c4a5h,0c4c7h,0d226h,0a050h,058eah,08566h,0c6h,0deh,09bc9h\n\ttstr\t030h,0,0,0,0,0,0,0f821h,0,0,0,0,0\t; (512 cycles)\n\ttstr\t0,0,0,0,0,0,0,-1,-1,-1,0d7h,0,-1\t; (38 cycles)\n\tdb\t0d9h,0a4h,0cah,005h\t\t\t; expected crc\n\ttmsg\t'add hl,<bc,de,hl,sp>..........'\n\n; add ix,<bc,de,ix,sp> (19,456 cycles)\nadd16x:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0ddh,9,0,0,0ddach,0c294h,0635bh,033d3h,06a76h,0fa20h,094h,068h,036f5h\n\ttstr\t0,030h,0,0,0,0,0f821h,0,0,0,0,0,0\t; (512 cycles)\n\ttstr\t0,0,0,0,0,0,-1,0,-1,-1,0d7h,0,-1\t; (38 cycles)\n\tdb\t0b1h,0dfh,08eh,0c0h\t\t\t; expected crc\n\ttmsg\t'add ix,<bc,de,ix,sp>..........'\n\n; add iy,<bc,de,iy,sp> (19,456 cycles)\nadd16y:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0fdh,9,0,0,0c7c2h,0f407h,051c1h,03e96h,00bf4h,0510fh,092h,01eh,071eah\n\ttstr\t0,030h,0,0,0,0f821h,0,0,0,0,0,0,0\t; (512 cycles)\n\ttstr\t0,0,0,0,0,-1,0,0,-1,-1,0d7h,0,-1\t\t; (38 cycles)\n\tdb\t039h,0c8h,058h,09bh\t\t\t; expected crc\n\ttmsg\t'add iy,<bc,de,iy,sp>..........'\n\n; aluop a,nn (28,672 cycles)\nalu8i:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0c6h,0,0,0,009140h,07e3ch,07a67h,0df6dh,05b61h,00b29h,010h,066h,085b2h\n\ttstr\t038h,0,0,0,0,0,0,0,0,0,0,-1,0\t\t; (2048 cycles)\n\ttstr\t0,-1,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (14 cycles)\n\tdb\t051h,0c1h,09ch,02eh\t\t\t; expected crc\n\ttmsg\t'aluop a,nn....................'\n\n; aluop a,<b,c,d,e,h,l,(hl),a> (753,664 cycles)\nalu8r:\tdb\t0ffh\t\t; flag mask\n\ttstr\t080h,0,0,0,0c53eh,0573ah,04c4dh,msbt,0e309h,0a666h,0d0h,03bh,0adbbh\n\ttstr\t03fh,0,0,0,0,0,0,0,0,0,0,-1,0\t\t; (16,384 cycles)\n\ttstr\t0,0,0,0,0ffh,0,0,0,-1,-1,0d7h,0,0\t; (46 cycles)\n\tdb\t006h,0c7h,0aah,08eh\t\t\t; expected crc\n\ttmsg\t'aluop a,<b,c,d,e,h,l,(hl),a>..'\n\n; aluop a,<ixh,ixl,iyh,iyl> (376,832 cycles)\nalu8rx:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0ddh,084h,0,0,0d6f7h,0c76eh,0accfh,02847h,022ddh,0c035h,0c5h,038h,0234bh\n\ttstr\t020h,039h,0,0,0,0,0,0,0,0,0,-1,0\t; (8,192 cycles)\n\ttstr\t0,0,0,0,0ffh,0,0,0,-1,-1,0d7h,0,0\t; (46 cycles)\n\tdb\t0a8h,086h,0cch,044h\t\t\t; expected crc\n\ttmsg\t'aluop a,<ixh,ixl,iyh,iyl>.....'\n\n; aluop a,(<ix,iy>+1) (229,376 cycles)\nalu8x:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0ddh,086h,1,0,090b7h,msbt-1,msbt-1,032fdh,0406eh,0c1dch,045h,06eh,0e5fah\n\ttstr\t020h,038h,0,0,0,1,1,0,0,0,0,-1,0\t; (16,384 cycles)\n\ttstr\t0,0,0,0,0ffh,0,0,0,0,0,0d7h,0,0\t\t; (14 cycles)\n\tdb\t0d3h,0f2h,0d7h,04ah\t\t\t; expected crc\n\ttmsg\t'aluop a,(<ix,iy>+1)...........'\n\n; bit n,(<ix,iy>+1) (2048 cycles)\nbitx:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0ddh,0cbh,1,046h,02075h,msbt-1,msbt-1,03cfch,0a79ah,03d74h,051h,027h,0ca14h\n\ttstr\t020h,0,0,038h,0,0,0,0,0,0,053h,0,0\t; (256 cycles)\n\ttstr\t0,0,0,0,0ffh,0,0,0,0,0,0,0,0\t\t; (8 cycles)\n\tdb\t083h,053h,04eh,0e1h\t\t\t; expected crc\n\ttmsg\t'bit n,(<ix,iy>+1).............'\n\n; bit n,<b,c,d,e,h,l,(hl),a> (49,152 cycles)\nbitz80:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0cbh,040h,0,0,03ef1h,09dfch,07acch,msbt,0be61h,07a86h,050h,024h,01998h\n\ttstr\t0,03fh,0,0,0,0,0,0,0,0,053h,0,0\t\t; (1024 cycles)\n\ttstr\t0,0,0,0,0ffh,0,0,0,-1,-1,0,-1,0\t\t; (48 cycles)\n\tdb\t05eh,002h,00eh,098h\t\t\t; expected crc\n\ttmsg\t'bit n,<b,c,d,e,h,l,(hl),a>....'\n\n; cpd<r> (1) (6144 cycles)\ncpd1:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0edh,0a9h,0,0,0c7b6h,072b4h,018f6h,msbt+17,08dbdh,1,0c0h,030h,094a3h\n\ttstr\t0,010h,0,0,0,0,0,0,0,010,0,-1,0\t\t; (1024 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t013h,04bh,062h,02dh\t\t\t; expected crc\n\ttmsg\t'cpd<r>........................'\n\n; cpi<r> (1) (6144 cycles)\ncpi1:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0edh,0a1h,0,0,04d48h,0af4ah,0906bh,msbt,04e71h,1,093h,06ah,0907ch\n\ttstr\t0,010h,0,0,0,0,0,0,0,010,0,-1,0\t\t; (1024 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t02dh,0a4h,02dh,019h\t\t\t; expected crc\n\ttmsg\t'cpi<r>........................'\n\n; <daa,cpl,scf,ccf>\ndaaop:\tdb\t0ffh\t\t; flag mask\n\ttstr\t027h,0,0,0,02141h,009fah,01d60h,0a559h,08d5bh,09079h,004h,08eh,0299dh\n\ttstr\t018h,0,0,0,0,0,0,0,0,0,0d7h,-1,0\t; (65,536 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0,0,0\t\t; (1 cycle)\n\tdb\t06dh,02dh,0d2h,013h\t\t\t; expected crc\n\ttmsg\t'<daa,cpl,scf,ccf>.............'\n\n; <inc,dec> a (3072 cycles)\ninca:\tdb\t0ffh\t\t; flag mask\n\ttstr\t03ch,0,0,0,04adfh,0d5d8h,0e598h,08a2bh,0a7b0h,0431bh,044h,05ah,0d030h\n\ttstr\t001h,0,0,0,0,0,0,0,0,0,0,-1,0\t\t; (512 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t081h,0fah,081h,000h\t\t\t; expected crc\n\ttmsg\t'<inc,dec> a...................'\n\n; <inc,dec> b (3072 cycles)\nincb:\tdb\t0ffh\t\t; flag mask\n\ttstr\t004h,0,0,0,0d623h,0432dh,07a61h,08180h,05a86h,01e85h,086h,058h,09bbbh\n\ttstr\t001h,0,0,0,0,0,0,0,0,0ff00h,0,0,0\t; (512 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t077h,0f3h,05ah,073h\t\t\t; expected crc\n\ttmsg\t'<inc,dec> b...................'\n\n; <inc,dec> bc (1536 cycles)\nincbc:\tdb\t0ffh\t\t; flag mask\n\ttstr\t003h,0,0,0,0cd97h,044abh,08dc9h,0e3e3h,011cch,0e8a4h,002h,049h,02a4dh\n\ttstr\t008h,0,0,0,0,0,0,0,0,0f821h,0,0,0\t; (256 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t0d2h,0aeh,03bh,0ech\t\t\t; expected crc\n\ttmsg\t'<inc,dec> bc..................'\n\n; <inc,dec> c (3072 cycles)\nincc:\tdb\t0ffh\t\t; flag mask\n\ttstr\t00ch,0,0,0,0d789h,00935h,0055bh,09f85h,08b27h,0d208h,095h,005h,00660h\n\ttstr\t001h,0,0,0,0,0,0,0,0,0ffh,0,0,0\t\t; (512 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t01ah,0f6h,012h,0a7h\t\t\t; expected crc\n\ttmsg\t'<inc,dec> c...................'\n\n; <inc,dec> d (3072 cycles)\nincd:\tdb\t0ffh\t\t; flag mask\n\ttstr\t014h,0,0,0,0a0eah,05fbah,065fbh,0981ch,038cch,0debch,043h,05ch,003bdh\n\ttstr\t001h,0,0,0,0,0,0,0,0ff00h,0,0,0,0\t; (512 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t0d1h,046h,0bfh,051h\t\t\t; expected crc\n\ttmsg\t'<inc,dec> d...................'\n\n; <inc,dec> de (1536 cycles)\nincde:\tdb\t0ffh\t\t; flag mask\n\ttstr\t013h,0,0,0,0342eh,0131dh,028c9h,00acah,09967h,03a2eh,092h,0f6h,09d54h\n\ttstr\t008h,0,0,0,0,0,0,0,0f821h,0,0,0,0\t; (256 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t0aeh,0c6h,0d4h,02ch\t\t\t; expected crc\n\ttmsg\t'<inc,dec> de..................'\n\n; <inc,dec> e (3072 cycles)\nince:\tdb\t0ffh\t\t; flag mask\n\ttstr\t01ch,0,0,0,0602fh,04c0dh,02402h,0e2f5h,0a0f4h,0a10ah,013h,032h,05925h\n\ttstr\t001h,0,0,0,0,0,0,0,0ffh,0,0,0,0\t\t; (512 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t0cah,08ch,06ah,0c2h\t\t\t; expected crc\n\ttmsg\t'<inc,dec> e...................'\n\n; <inc,dec> h (3072 cycles)\ninch:\tdb\t0ffh\t\t; flag mask\n\ttstr\t024h,0,0,0,01506h,0f2ebh,0e8ddh,0262bh,011a6h,0bc1ah,017h,006h,02818h\n\ttstr\t001h,0,0,0,0,0,0,0ff00h,0,0,0,0,0\t; (512 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t056h,00fh,095h,05eh\t\t\t; expected crc\n\ttmsg\t'<inc,dec> h...................'\n\n; <inc,dec> hl (1536 cycles)\ninchl:\tdb\t0ffh\t\t; flag mask\n\ttstr\t023h,0,0,0,0c3f4h,007a5h,01b6dh,04f04h,0e2c2h,0822ah,057h,0e0h,0c3e1h\n\ttstr\t008h,0,0,0,0,0,0,0f821h,0,0,0,0,0\t; (256 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t0fch,00dh,06dh,04ah\t\t\t; expected crc\n\ttmsg\t'<inc,dec> hl..................'\n\n; <inc,dec> ix (1536 cycles)\nincix:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0ddh,023h,0,0,0bc3ch,00d9bh,0e081h,0adfdh,09a7fh,096e5h,013h,085h,00be2h\n\ttstr\t0,8,0,0,0,0,0f821h,0,0,0,0,0,0\t\t; (256 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t0a5h,04dh,0beh,031h\t\t\t; expected crc\n\ttmsg\t'<inc,dec> ix..................'\n\n; <inc,dec> iy (1536 cycles)\ninciy:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0fdh,023h,0,0,09402h,0637ah,03182h,0c65ah,0b2e9h,0abb4h,016h,0f2h,06d05h\n\ttstr\t0,8,0,0,0,0f821h,0,0,0,0,0,0,0\t\t; (256 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t050h,05dh,051h,0a3h\t\t\t; expected crc\n\ttmsg\t'<inc,dec> iy..................'\n\n; <inc,dec> l (3072 cycles)\nincl:\tdb\t0ffh\t\t; flag mask\n\ttstr\t02ch,0,0,0,08031h,0a520h,04356h,0b409h,0f4c1h,0dfa2h,0d1h,03ch,03ea2h\n\ttstr\t001h,0,0,0,0,0,0,0ffh,0,0,0,0,0\t\t; (512 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t0a0h,0a1h,0b4h,09fh\t\t\t; expected crc\n\ttmsg\t'<inc,dec> l...................'\n\n; <inc,dec> (hl) (3072 cycles)\nincm:\tdb\t0ffh\t\t; flag mask\n\ttstr\t034h,0,0,0,0b856h,00c7ch,0e53eh,msbt,0877eh,0da58h,015h,05ch,01f37h\n\ttstr\t001h,0,0,0,0ffh,0,0,0,0,0,0,0,0\t\t; (512 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t028h,029h,05eh,0ceh\t\t\t; expected crc\n\ttmsg\t'<inc,dec> (hl)................'\n\n; <inc,dec> sp (1536 cycles)\nincsp:\tdb\t0ffh\t\t; flag mask\n\ttstr\t033h,0,0,0,0346fh,0d482h,0d169h,0deb6h,0a494h,0f476h,053h,002h,0855bh\n\ttstr\t008h,0,0,0,0,0,0,0,0,0,0,0,0f821h\t; (256 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t05dh,0ach,0d5h,027h\t\t\t; expected crc\n\ttmsg\t'<inc,dec> sp..................'\n\n; <inc,dec> (<ix,iy>+1) (6144 cycles)\nincx:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0ddh,034h,1,0,0fa6eh,msbt-1,msbt-1,02c28h,08894h,05057h,016h,033h,0286fh\n\ttstr\t020h,1,0,0,0ffh,0,0,0,0,0,0,0,0\t\t; (1024 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t00bh,095h,0a8h,0eah\t\t\t; expected crc\n\ttmsg\t'<inc,dec> (<ix,iy>+1).........'\n\n; <inc,dec> ixh (3072 cycles)\nincxh:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0ddh,024h,0,0,0b838h,0316ch,0c6d4h,03e01h,08358h,015b4h,081h,0deh,04259h\n\ttstr\t0,1,0,0,0,0ff00h,0,0,0,0,0,0,0\t\t; (512 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t06fh,046h,036h,062h\t\t\t; expected crc\n\ttmsg\t'<inc,dec> ixh.................'\n\n; <inc,dec> ixl (3072 cycles)\nincxl:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0ddh,02ch,0,0,04d14h,07460h,076d4h,006e7h,032a2h,0213ch,0d6h,0d7h,099a5h\n\ttstr\t0,1,0,0,0,0ffh,0,0,0,0,0,0,0\t\t; (512 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t002h,07bh,0efh,02ch\t\t\t; expected crc\n\ttmsg\t'<inc,dec> ixl.................'\n\n; <inc,dec> iyh (3072 cycles)\nincyh:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0ddh,024h,0,0,02836h,09f6fh,09116h,061b9h,082cbh,0e219h,092h,073h,0a98ch\n\ttstr\t0,1,0,0,0ff00h,0,0,0,0,0,0,0,0\t\t; (512 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t02dh,096h,06ch,0f3h\t\t\t; expected crc\n\ttmsg\t'<inc,dec> iyh.................'\n\n; <inc,dec> iyl (3072 cycles)\nincyl:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0ddh,02ch,0,0,0d7c6h,062d5h,0a09eh,07039h,03e7eh,09f12h,090h,0d9h,0220fh\n\ttstr\t0,1,0,0,0ffh,0,0,0,0,0,0,0,0\t\t; (512 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t036h,0c1h,01eh,075h\t\t\t; expected crc\n\ttmsg\t'<inc,dec> iyl.................'\n\n; ld <bc,de>,(nnnn) (32 cycles)\nld161:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0edh,04bh,msbtlo,msbthi,0f9a8h,0f559h,093a4h,0f5edh,06f96h,0d968h,086h,0e6h,04bd8h\n\ttstr\t0,010h,0,0,0,0,0,0,0,0,0,0,0\t\t; (2 cycles)\n\ttstr\t0,0,0,0,-1,0,0,0,0,0,0,0,0\t\t; (16 cycles)\n\tdb\t04dh,045h,0a9h,0ach\t\t\t; expected crc\n\ttmsg\t'ld <bc,de>,(nnnn).............'\n\n; ld hl,(nnnn) (16 cycles)\nld162:\tdb\t0ffh\t\t; flag mask\n\ttstr\t02ah,msbtlo,msbthi,0,09863h,07830h,02077h,0b1feh,0b9fah,0abb8h,004h,006h,06015h\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0,0,0\t\t; (1 cycle)\n\ttstr\t0,0,0,0,-1,0,0,0,0,0,0,0,0\t\t; (16 cycles)\n\tdb\t05fh,097h,024h,087h\t\t\t; expected crc\n\ttmsg\t'ld hl,(nnnn)..................'\n\t\n; ld sp,(nnnn) (16 cycles)\nld163:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0edh,07bh,msbtlo,msbthi,08dfch,057d7h,02161h,0ca18h,0c185h,027dah,083h,01eh,0f460h\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0,0,0\t\t; (1 cycles)\n\ttstr\t0,0,0,0,-1,0,0,0,0,0,0,0,0\t\t; (16 cycles)\n\tdb\t07ah,0ceh,0a1h,01bh\t\t\t; expected crc\n\ttmsg\t'ld sp,(nnnn)..................'\n\n; ld <ix,iy>,(nnnn) (32 cycles)\nld164:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0ddh,02ah,msbtlo,msbthi,0ded7h,0a6fah,0f780h,0244ch,087deh,0bcc2h,016h,063h,04c96h\n\ttstr\t020h,0,0,0,0,0,0,0,0,0,0,0,0\t\t; (2 cycles)\n\ttstr\t0,0,0,0,-1,0,0,0,0,0,0,0,0\t\t; (16 cycles)\n\tdb\t085h,08bh,0f1h,06dh\t\t\t; expected crc\n\ttmsg\t'ld <ix,iy>,(nnnn).............'\n\t\n; ld (nnnn),<bc,de> (64 cycles)\nld165:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0edh,043h,msbtlo,msbthi,01f98h,0844dh,0e8ach,0c9edh,0c95dh,08f61h,080h,03fh,0c7bfh\n\ttstr\t0,010h,0,0,0,0,0,0,0,0,0,0,0\t\t; (2 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,-1,-1,0,0,0\t\t; (32 cycles)\n\tdb\t064h,01eh,087h,015h\t\t\t; expected crc\n\ttmsg\t'ld (nnnn),<bc,de>.............'\n\n; ld (nnnn),hl (16 cycles)\nld166:\tdb\t0ffh\t\t; flag mask\n\ttstr\t022h,msbtlo,msbthi,0,0d003h,07772h,07f53h,03f72h,064eah,0e180h,010h,02dh,035e9h\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0,0,0\t\t; (1 cycle)\n\ttstr\t0,0,0,0,0,0,0,-1,0,0,0,0,0\t\t; (16 cycles)\n\tdb\t0a3h,060h,08bh,047h\t\t\t; expected crc\n\ttmsg\t'ld (nnnn),hl..................'\n\n; ld (nnnn),sp (16 cycles)\nld167:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0edh,073h,msbtlo,msbthi,0c0dch,0d1d6h,0ed5ah,0f356h,0afdah,06ca7h,044h,09fh,03f0ah\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0,0,0\t\t; (1 cycle)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0,0,-1\t\t; (16 cycles)\n\tdb\t016h,058h,05fh,0d7h\t\t\t; expected crc\n\ttmsg\t'ld (nnnn),sp..................'\n\n; ld (nnnn),<ix,iy> (64 cycles)\nld168:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0ddh,022h,msbtlo,msbthi,06cc3h,00d91h,06900h,08ef8h,0e3d6h,0c3f7h,0c6h,0d9h,0c2dfh\n\ttstr\t020h,0,0,0,0,0,0,0,0,0,0,0,0\t\t; (2 cycles)\n\ttstr\t0,0,0,0,0,-1,-1,0,0,0,0,0,0\t\t; (32 cycles)\n\tdb\t0bah,010h,02ah,06bh\t\t\t; expected crc\n\ttmsg\t'ld (nnnn),<ix,iy>.............'\n\n; ld <bc,de,hl,sp>,nnnn (64 cycles)\nld16im:\tdb\t0ffh\t\t; flag mask\n\ttstr\t1,0,0,0,05c1ch,02d46h,08eb9h,06078h,074b1h,0b30eh,046h,0d1h,030cch\n\ttstr\t030h,0,0,0,0,0,0,0,0,0,0,0,0\t\t; (4 cycles)\n\ttstr\t0,0ffh,0ffh,0,0,0,0,0,0,0,0,0,0\t\t; (16 cycles)\n\tdb\t0deh,039h,019h,069h\t\t\t; expected crc\n\ttmsg\t'ld <bc,de,hl,sp>,nnnn.........'\n\n; ld <ix,iy>,nnnn (32 cycles)\nld16ix:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0ddh,021h,0,0,087e8h,02006h,0bd12h,0b69bh,07253h,0a1e5h,051h,013h,0f1bdh\n\ttstr\t020h,0,0,0,0,0,0,0,0,0,0,0,0\t\t; (2 cycles)\n\ttstr\t0,0,0ffh,0ffh,0,0,0,0,0,0,0,0,0\t\t; (16 cycles)\n\tdb\t022h,07dh,0d5h,025h\t\t\t; expected crc\n\ttmsg\t'ld <ix,iy>,nnnn...............'\n\n; ld a,<(bc),(de)> (44 cycles)\nld8bd:\tdb\t0ffh\t\t; flag mask\n\ttstr\t00ah,0,0,0,0b3a8h,01d2ah,07f8eh,042ach,msbt,msbt,0c6h,0b1h,0ef8eh\n\ttstr\t010h,0,0,0,0,0,0,0,0,0,0,0,0\t\t; (2 cycles)\n\ttstr\t0,0,0,0,0ffh,0,0,0,0,0,0d7h,-1,0\t; (22 cycles)\n\tdb\t0b0h,081h,089h,035h\t\t\t; expected crc\n\ttmsg\t'ld a,<(bc),(de)>..............'\n\n; ld <b,c,d,e,h,l,(hl),a>,nn (64 cycles)\nld8im:\tdb\t0ffh\t\t; flag mask\n\ttstr\t6,0,0,0,0c407h,0f49dh,0d13dh,00339h,0de89h,07455h,053h,0c0h,05509h\n\ttstr\t038h,0,0,0,0,0,0,0,0,0,0,0,0\t\t; (8 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0,-1,0\t\t; (8 cycles)\n\tdb\t0f1h,0dah,0b5h,056h\t\t\t; expected crc\n\ttmsg\t'ld <b,c,d,e,h,l,(hl),a>,nn....'\n\n; ld (<ix,iy>+1),nn (32 cycles)\nld8imx:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0ddh,036h,1,0,01b45h,msbt-1,msbt-1,0d5c1h,061c7h,0bdc4h,0c0h,085h,0cd16h\n\ttstr\t020h,0,0,0,0,0,0,0,0,0,0,0,0\t\t; (2 cycles)\n\ttstr\t0,0,0,-1,0,0,0,0,0,0,0,-1,0\t\t; (16 cycles)\n\tdb\t026h,0dbh,047h,07eh\t\t\t; expected crc\n\ttmsg\t'ld (<ix,iy>+1),nn.............'\n\n; ld <b,c,d,e>,(<ix,iy>+1) (512 cycles)\nld8ix1:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0ddh,046h,1,0,0d016h,msbt-1,msbt-1,04260h,07f39h,00404h,097h,04ah,0d085h\n\ttstr\t020h,018h,0,0,0,1,1,0,0,0,0,0,0\t\t; (32 cycles)\n\ttstr\t0,0,0,0,-1,0,0,0,0,0,0,0,0\t\t; (16 cycles)\n\tdb\t0cch,011h,006h,0a8h\t\t\t; expected crc\n\ttmsg\t'ld <b,c,d,e>,(<ix,iy>+1)......'\n\n; ld <h,l>,(<ix,iy>+1) (256 cycles)\nld8ix2:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0ddh,066h,1,0,084e0h,msbt-1,msbt-1,09c52h,0a799h,049b6h,093h,000h,0eeadh\n\ttstr\t020h,008h,0,0,0,1,1,0,0,0,0,0,0\t\t; (16 cycles)\n\ttstr\t0,0,0,0,-1,0,0,0,0,0,0,0,0\t\t; (16 cycles)\n\tdb\t0fah,02ah,04dh,003h\t\t\t; expected crc\n\ttmsg\t'ld <h,l>,(<ix,iy>+1)..........'\n\n; ld a,(<ix,iy>+1) (128 cycles)\nld8ix3:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0ddh,07eh,1,0,0d8b6h,msbt-1,msbt-1,0c612h,0df07h,09cd0h,043h,0a6h,0a0e5h\n\ttstr\t020h,0,0,0,0,1,1,0,0,0,0,0,0\t\t; (8 cycles)\n\ttstr\t0,0,0,0,-1,0,0,0,0,0,0,0,0\t\t; (16 cycles)\n\tdb\t0a5h,0e9h,0ach,064h\t\t\t; expected crc\n\ttmsg\t'ld a,(<ix,iy>+1)..............'\n\n; ld <ixh,ixl,iyh,iyl>,nn (32 cycles)\nld8ixy:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0ddh,026h,0,0,03c53h,04640h,0e179h,07711h,0c107h,01afah,081h,0adh,05d9bh\n\ttstr\t020h,8,0,0,0,0,0,0,0,0,0,0,0\t\t; (4 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0,-1,0\t\t; (8 cycles)\n\tdb\t024h,0e8h,082h,08bh\t\t\t; expected crc\n\ttmsg\t'ld <ixh,ixl,iyh,iyl>,nn.......'\n\n; ld <b,c,d,e,h,l,a>,<b,c,d,e,h,l,a> (3456 cycles)\nld8rr:\tdb\t0ffh\t\t; flag mask\n\ttstr\t040h,0,0,0,072a4h,0a024h,061ach,msbt,082c7h,0718fh,097h,08fh,0ef8eh\n\ttstr\t03fh,0,0,0,0,0,0,0,0,0,0,0,0\t\t; (64 cycles)\n\ttstr\t0,0,0,0,0ffh,0,0,0,-1,-1,0d7h,-1,0\t; (54 cycles)\n\tdb\t074h,04bh,001h,018h\t\t\t; expected crc\n\ttmsg\t'ld <bcdehla>,<bcdehla>........'\n\n; ld <b,c,d,e,ixy,a>,<b,c,d,e,ixy,a> (6912 cycles)\nld8rrx:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0ddh,040h,0,0,0bcc5h,msbt,msbt,msbt,02fc2h,098c0h,083h,01fh,03bcdh\n\ttstr\t020h,03fh,0,0,0,0,0,0,0,0,0,0,0\t\t; (128 cycles)\n\ttstr\t0,0,0,0,0ffh,0,0,0,-1,-1,0d7h,-1,0\t; (54 cycles)\n\tdb\t047h,08bh,0a3h,06bh\t\t\t; expected crc\n\ttmsg\t'ld <bcdexya>,<bcdexya>........'\n\n; ld a,(nnnn) / ld (nnnn),a (44 cycles)\nlda:\tdb\t0ffh\t\t; flag mask\n\ttstr\t032h,msbtlo,msbthi,0,0fd68h,0f4ech,044a0h,0b543h,00653h,0cdbah,0d2h,04fh,01fd8h\n\ttstr\t008h,0,0,0,0,0,0,0,0,0,0,0,0\t\t; (2 cycle)\n\ttstr\t0,0,0,0,0ffh,0,0,0,0,0,0d7h,-1,0\t; (22 cycles)\n\tdb\t0c9h,026h,02dh,0e5h\t\t\t; expected crc\n\ttmsg\t'ld a,(nnnn) / ld (nnnn),a.....'\n\n; ldd<r> (1) (44 cycles)\nldd1:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0edh,0a8h,0,0,09852h,068fah,066a1h,msbt+3,msbt+1,1,0c1h,068h,020b7h\n\ttstr\t0,010h,0,0,0,0,0,0,0,0,0,0,0\t\t; (2 cycles)\n\ttstr\t0,0,0,0,-1,0,0,0,0,0,0d7h,0,0\t\t; (22 cycles)\n\tdb\t094h,0f4h,027h,069h\t\t\t; expected crc\n\ttmsg\t'ldd<r> (1)....................'\n\n; ldd<r> (2) (44 cycles)\nldd2:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0edh,0a8h,0,0,0f12eh,0eb2ah,0d5bah,msbt+3,msbt+1,2,047h,0ffh,0fbe4h\n\ttstr\t0,010h,0,0,0,0,0,0,0,0,0,0,0\t\t; (2 cycles)\n\ttstr\t0,0,0,0,-1,0,0,0,0,0,0d7h,0,0\t\t; (22 cycles)\n\tdb\t039h,0ddh,03dh,0e1h\t\t\t; expected crc\n\ttmsg\t'ldd<r> (2)....................'\n\n; ldi<r> (1) (44 cycles)\nldi1:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0edh,0a0h,0,0,0fe30h,003cdh,06058h,msbt+2,msbt,1,004h,060h,02688h\n\ttstr\t0,010h,0,0,0,0,0,0,0,0,0,0,0\t\t; (2 cycles)\n\ttstr\t0,0,0,0,-1,0,0,0,0,0,0d7h,0,0\t\t; (22 cycles)\n\tdb\t0f7h,082h,0b0h,0d1h\t\t\t; expected crc\n\ttmsg\t'ldi<r> (1)....................'\n\n; ldi<r> (2) (44 cycles)\nldi2:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0edh,0a0h,0,0,04aceh,0c26eh,0b188h,msbt+2,msbt,2,014h,02dh,0a39fh\n\ttstr\t0,010h,0,0,0,0,0,0,0,0,0,0,0\t\t; (2 cycles)\n\ttstr\t0,0,0,0,-1,0,0,0,0,0,0d7h,0,0\t\t; (22 cycles)\n\tdb\t0e9h,0eah,0d0h,0aeh\t\t\t; expected crc\n\ttmsg\t'ldi<r> (2)....................'\n\n; neg (16,384 cycles)\nnegop:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0edh,044h,0,0,038a2h,05f6bh,0d934h,057e4h,0d2d6h,04642h,043h,05ah,009cch\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,-1,0\t\t; (16,384 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0,0,0\t\t; (1 cycle)\n\tdb\t0d6h,038h,0ddh,06ah\t\t\t; expected crc\n\ttmsg\t'neg...........................'\n\n; <rld,rrd> (7168 cycles)\nrldop:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0edh,067h,0,0,091cbh,0c48bh,0fa62h,msbt,0e720h,0b479h,040h,006h,08ae2h\n\ttstr\t0,8,0,0,0ffh,0,0,0,0,0,0,0,0\t\t; (512 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,-1,0\t\t; (14 cycles)\n\tdb\t0ffh,082h,03eh,077h\t\t\t; expected crc\n\ttmsg\t'<rrd,rld>.....................'\n\n; <rlca,rrca,rla,rra> (6144 cycles)\nrot8080: db\t0ffh\t\t; flag mask\n\ttstr\t7,0,0,0,0cb92h,06d43h,00a90h,0c284h,00c53h,0f50eh,091h,0ebh,040fch\n\ttstr\t018h,0,0,0,0,0,0,0,0,0,0,-1,0\t\t; (1024 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t09bh,0a3h,080h,07ch\t\t\t; expected crc\n\ttmsg\t'<rlca,rrca,rla,rra>...........'\n\n; shift/rotate (<ix,iy>+1) (416 cycles)\nrotxy:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0ddh,0cbh,1,6,0ddafh,msbt-1,msbt-1,0ff3ch,0dbf6h,094f4h,082h,080h,061d9h\n\ttstr\t020h,0,0,038h,0,0,0,0,0,0,080h,0,0\t; (32 cycles)\n\ttstr\t0,0,0,0,0ffh,0,0,0,0,0,057h,0,0\t\t; (13 cycles)\n\tdb\t071h,000h,034h,0cbh\t\t\t; expected crc\n\ttmsg\t'shf/rot (<ix,iy>+1)...........'\n\n; shift/rotate <b,c,d,e,h,l,(hl),a> (6784 cycles)\nrotz80:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0cbh,0,0,0,0ccebh,05d4ah,0e007h,msbt,01395h,030eeh,043h,078h,03dadh\n\ttstr\t0,03fh,0,0,0,0,0,0,0,0,080h,0,0\t\t; (128 cycles)\n\ttstr\t0,0,0,0,0ffh,0,0,0,-1,-1,057h,-1,0\t; (53 cycles)\n\tdb\t0a4h,025h,058h,033h\t\t\t; expected crc\n\ttmsg\t'shf/rot <b,c,d,e,h,l,(hl),a>..'\n\n; <set,res> n,<b,c,d,e,h,l,(hl),a> (7936 cycles)\nsrz80:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0cbh,080h,0,0,02cd5h,097abh,039ffh,msbt,0d14bh,06ab2h,053h,027h,0b538h\n\ttstr\t0,07fh,0,0,0,0,0,0,0,0,0,0,0\t\t; (128 cycles)\n\ttstr\t0,0,0,0,0ffh,0,0,0,-1,-1,0d7h,-1,0\t; (62 cycles)\n\tdb\t08bh,057h,0f0h,008h\t\t\t; expected crc\n\ttmsg\t'<set,res> n,<bcdehl(hl)a>.....'\n\n; <set,res> n,(<ix,iy>+1) (1792 cycles)\nsrzx:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0ddh,0cbh,1,086h,0fb44h,msbt-1,msbt-1,0ba09h,068beh,032d8h,010h,05eh,0a867h\n\ttstr\t020h,0,0,078h,0,0,0,0,0,0,0,0,0\t; (128 cycles)\n\ttstr\t0,0,0,0,0ffh,0,0,0,0,0,0d7h,0,0\t\t;(14 cycles)\n\tdb\t0cch,063h,0f9h,08ah\t\t\t; expected crc\n\ttmsg\t'<set,res> n,(<ix,iy>+1).......'\n\n; ld (<ix,iy>+1),<b,c,d,e> (1024 cycles)\nst8ix1:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0ddh,070h,1,0,0270dh,msbt-1,msbt-1,0b73ah,0887bh,099eeh,086h,070h,0ca07h\n\ttstr\t020h,003h,0,0,0,1,1,0,0,0,0,0,0\t\t; (32 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,-1,-1,0,0,0\t\t; (32 cycles)\n\tdb\t004h,062h,06ah,0bfh\t\t\t; expected crc\n\ttmsg\t'ld (<ix,iy>+1),<b,c,d,e>......'\n\n; ld (<ix,iy>+1),<h,l> (256 cycles)\nst8ix2:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0ddh,074h,1,0,0b664h,msbt-1,msbt-1,0e8ach,0b5f5h,0aafeh,012h,010h,09566h\n\ttstr\t020h,001h,0,0,0,1,1,0,0,0,0,0,0\t\t; (16 cycles)\n\ttstr\t0,0,0,0,0,0,0,-1,0,0,0,0,0\t\t; (32 cycles)\n\tdb\t06ah,01ah,088h,031h\t\t\t; expected crc\n\ttmsg\t'ld (<ix,iy>+1),<h,l>..........'\n\n; ld (<ix,iy>+1),a (64 cycles)\nst8ix3:\tdb\t0ffh\t\t; flag mask\n\ttstr\t0ddh,077h,1,0,067afh,msbt-1,msbt-1,04f13h,00644h,0bcd7h,050h,0ach,05fafh\n\ttstr\t020h,0,0,0,0,1,1,0,0,0,0,0,0\t\t; (8 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0,-1,0\t\t; (8 cycles)\n\tdb\t0cch,0beh,05ah,096h\t\t\t; expected crc\n\ttmsg\t'ld (<ix,iy>+1),a..............'\n\n; ld (<bc,de>),a (96 cycles)\nstabd:\tdb\t0ffh\t\t; flag mask\n\ttstr\t2,0,0,0,00c3bh,0b592h,06cffh,0959eh,msbt,msbt+1,0c1h,021h,0bde7h\n\ttstr\t018h,0,0,0,0,0,0,0,0,0,0,0,0\t\t; (4 cycles)\n\ttstr\t0,0,0,0,-1,0,0,0,0,0,0,-1,0\t\t; (24 cycles)\n\tdb\t07ah,04ch,011h,04fh\t\t\t; expected crc\n\ttmsg\t'ld (<bc,de>),a................'\n\n; start test pointed to by (hl)\nstt:\tpush\thl\n\tld\ta,(hl)\t\t; get pointer to test\n\tinc\thl\n\tld\th,(hl)\n\tld\tl,a\n\tld\ta,(hl)\t\t; flag mask\n\tld\t(flgmsk+1),a\n\tinc\thl\n\tpush\thl\n\tld\tde,20\n\tadd\thl,de\t\t; point to incmask\n\tld\tde,counter\n\tcall\tinitmask\n\tpop\thl\n\tpush\thl\n\tld\tde,20+20\n\tadd\thl,de\t\t; point to scanmask\n\tld\tde,shifter\n\tcall\tinitmask\n\tld\thl,shifter\n\tld\t(hl),1\t\t; first bit\n\tpop\thl\n\tpush\thl\n\tld\tde,iut\t\t; copy initial instruction under test\n\tld\tbc,4\n\tldir\n\tld\tde,msbt\t\t; copy initial machine state\n\tld\tbc,16\n\tldir\n\tld\tde,20+20+4\t; skip incmask, scanmask and expcrc\n\tadd\thl,de\n\tex\tde,hl\n\tld\tc,9\n\tcall\tbdos\t\t; show test name\n\tcall\tinitcrc\t\t; initialise crc\n; test loop\ntlp:\tld\ta,(iut)\n\tcp\t076h\t\t; pragmatically avoid halt intructions\n\tjp\tz,tlp2\n\tand\ta,0dfh\n\tcp\t0ddh\n\tjp\tnz,tlp1\n\tld\ta,(iut+1)\n\tcp\t076h\ntlp1:\tcall\tnz,test\t\t; execute the test instruction\ntlp2:\tcall\tcount\t\t; increment the counter\n\tcall\tnz,shift\t; shift the scan bit\n\tpop\thl\t\t; pointer to test case\n\tjp\tz,tlp3\t\t; done if shift returned NZ\n\tld\tde,20+20+20\n\tadd\thl,de\t\t; point to expected crc\n\tcall\tcmpcrc\n\tld\tde,okmsg\n\tjp\tz,tlpok\n\tld\tde,ermsg1\n\tld\tc,9\n\tcall\tbdos\n\tcall\tphex8\n\tld\tde,ermsg2\n\tld\tc,9\n\tcall\tbdos\n\tld\thl,crcval\n\tcall\tphex8\n\tld\tde,crlf\ntlpok:\tld\tc,9\n\tcall\tbdos\n\tpop\thl\n\tinc\thl\n\tinc\thl\n\tret\n\ntlp3:\tpush\thl\n\tld\ta,1\t\t; initialise count and shift scanners\n\tld\t(cntbit),a\n\tld\t(shfbit),a\n\tld\thl,counter\n\tld\t(cntbyt),hl\n\tld\thl,shifter\n\tld\t(shfbyt),hl\n\n\tld\tb,4\t\t; bytes in iut field\n\tpop\thl\t\t; pointer to test case\n\tpush\thl\n\tld\tde,iut\n\tcall\tsetup\t\t; setup iut\n\tld\tb,16\t\t; bytes in machine state\n\tld\tde,msbt\n\tcall\tsetup\t\t; setup machine state\n\tjp\ttlp\n\n; setup a field of the test case\n; b  = number of bytes\n; hl = pointer to base case\n; de = destination\nsetup:\tcall\tsubyte\n\tinc\thl\n\tdec\tb\n\tjp\tnz,setup\n\tret\n\nsubyte:\tpush\tbc\n\tpush\tde\n\tpush\thl\n\tld\tc,(hl)\t\t; get base byte\n\tld\tde,20\n\tadd\thl,de\t\t; point to incmask\n\tld\ta,(hl)\n\tcp\t0\n\tjp\tz,subshf\n\tld\tb,8\t\t; 8 bits\nsubclp:\trrca\n\tpush\taf\n\tld\ta,0\n\tcall\tc,nxtcbit\t; get next counter bit if mask bit was set\n\txor\tc\t\t; flip bit if counter bit was set\n\trrca\n\tld\tc,a\n\tpop\taf\n\tdec\tb\n\tjp\tnz,subclp\n\tld\tb,8\nsubshf:\tld\tde,20\n\tadd\thl,de\t\t; point to shift mask\n\tld\ta,(hl)\n\tcp\t0\n\tjp\tz,substr\n\tld\tb,8\t\t; 8 bits\nsbshf1:\trrca\n\tpush\taf\n\tld\ta,0\n\tcall\tc,nxtsbit\t; get next shifter bit if mask bit was set\n\txor\tc\t\t; flip bit if shifter bit was set\n\trrca\n\tld\tc,a\n\tpop\taf\n\tdec\tb\n\tjp\tnz,sbshf1\nsubstr:\tpop\thl\n\tpop\tde\n\tld\ta,c\n\tld\t(de),a\t\t; mangled byte to destination\n\tinc\tde\n\tpop\tbc\n\tret\n\n; get next counter bit in low bit of a\ncntbit:\tds\t1\ncntbyt:\tds\t2\n\nnxtcbit: push\tbc\n\tpush\thl\n\tld\thl,(cntbyt)\n\tld\tb,(hl)\n\tld\thl,cntbit\n\tld\ta,(hl)\n\tld\tc,a\n\trlca\n\tld\t(hl),a\n\tcp\ta,1\n\tjp\tnz,ncb1\n\tld\thl,(cntbyt)\n\tinc\thl\n\tld\t(cntbyt),hl\nncb1:\tld\ta,b\n\tand\tc\n\tpop\thl\n\tpop\tbc\n\tret\tz\n\tld\ta,1\n\tret\n\t\n; get next shifter bit in low bit of a\nshfbit:\tds\t1\nshfbyt:\tds\t2\n\nnxtsbit: push\tbc\n\tpush\thl\n\tld\thl,(shfbyt)\n\tld\tb,(hl)\n\tld\thl,shfbit\n\tld\ta,(hl)\n\tld\tc,a\n\trlca\n\tld\t(hl),a\n\tcp\ta,1\n\tjp\tnz,nsb1\n\tld\thl,(shfbyt)\n\tinc\thl\n\tld\t(shfbyt),hl\nnsb1:\tld\ta,b\n\tand\tc\n\tpop\thl\n\tpop\tbc\n\tret\tz\n\tld\ta,1\n\tret\n\t\n\n; clear memory at hl, bc bytes\nclrmem:\tpush\taf\n\tpush\tbc\n\tpush\tde\n\tpush\thl\n\tld\t(hl),0\n\tld\td,h\n\tld\te,l\n\tinc\tde\n\tdec\tbc\n\tldir\n\tpop\thl\n\tpop\tde\n\tpop\tbc\n\tpop\taf\n\tret\n\n; initialise counter or shifter\n; de = pointer to work area for counter or shifter\n; hl = pointer to mask\ninitmask:\n\tpush\tde\n\tex\tde,hl\n\tld\tbc,20+20\n\tcall\tclrmem\t\t; clear work area\n\tex\tde,hl\n\tld\tb,20\t\t; byte counter\n\tld\tc,1\t\t; first bit\n\tld\td,0\t\t; bit counter\nimlp:\tld\te,(hl)\nimlp1:\tld\ta,e\n\tand\ta,c\n\tjp\tz,imlp2\n\tinc\td\nimlp2:\tld\ta,c\n\trlca\n\tld\tc,a\n\tcp\ta,1\n\tjp\tnz,imlp1\n\tinc\thl\n\tdec\tb\n\tjp\tnz,imlp\n; got number of 1-bits in mask in reg d\n\tld\ta,d\n\tand\t0f8h\n\trrca\n\trrca\n\trrca\t\t\t; divide by 8 (get byte offset)\n\tld\tl,a\n\tld\th,0\n\tld\ta,d\n\tand\ta,7\t\t; bit offset\n\tinc\ta\n\tld\tb,a\n\tld\ta,080h\nimlp3:\trlca\n\tdec\tb\n\tjp\tnz,imlp3\n\tpop\tde\n\tadd\thl,de\n\tld\tde,20\n\tadd\thl,de\n\tld\t(hl),a\n\tret\n\n; multi-byte counter\ncount:\tpush\tbc\n\tpush\tde\n\tpush\thl\n\tld\thl,counter\t; 20 byte counter starts here\n\tld\tde,20\t\t; somewhere in here is the stop bit\n\tex\tde,hl\n\tadd\thl,de\n\tex\tde,hl\ncntlp:\tinc\t(hl)\n\tld\ta,(hl)\n\tcp\t0\n\tjp\tz,cntlp1\t; overflow to next byte\n\tld\tb,a\n\tld\ta,(de)\n\tand\ta,b\t\t; test for terminal value\n\tjp\tz,cntend\n\tld\t(hl),0\t\t; reset to zero\ncntend:\tpop\tbc\n\tpop\tde\n\tpop\thl\n\tret\n\ncntlp1:\tinc\thl\n\tinc\tde\n\tjp\tcntlp\n\t\n\n; multi-byte shifter\nshift:\tpush\tbc\n\tpush\tde\n\tpush\thl\n\tld\thl,shifter\t; 20 byte shift register starts here\n\tld\tde,20\t\t; somewhere in here is the stop bit\n\tex\tde,hl\n\tadd\thl,de\n\tex\tde,hl\nshflp:\tld\ta,(hl)\n\tor\ta\n\tjp\tz,shflp1\n\tld\tb,a\n\tld\ta,(de)\n\tand\tb\n\tjp\tnz,shlpe\n\tld\ta,b\n\trlca\n\tcp\ta,1\n\tjp\tnz,shflp2\n\tld\t(hl),0\n\tinc\thl\n\tinc\tde\nshflp2:\tld\t(hl),a\n\txor\ta\t\t; set Z\nshlpe:\tpop\thl\n\tpop\tde\n\tpop\tbc\n\tret\nshflp1:\tinc\thl\n\tinc\tde\n\tjp\tshflp\n\ncounter: ds\t2*20\nshifter: ds\t2*20\n\n; test harness\ntest:\tpush\taf\n\tpush\tbc\n\tpush\tde\n\tpush\thl\n      if\t0\n\tld\tde,crlf\n\tld\tc,9\n\tcall\tbdos\n\tld\thl,iut\n\tld\tb,4\n\tcall\thexstr\n\tld\te,' '\n\tld\tc,2\n\tcall\tbdos\n\tld\tb,16\n\tld\thl,msbt\n\tcall\thexstr\n      endif\t\n\tdi\t\t\t; disable interrupts\n\tld\t(spsav),sp\t; save stack pointer\n\tld\tsp,msbt+2\t; point to test-case machine state\n\tpop\tiy\t\t; and load all regs\n\tpop\tix\n\tpop\thl\n\tpop\tde\n\tpop\tbc\n\tpop\taf\n\tld\tsp,(spbt)\niut:\tds\t4\t\t; max 4 byte instruction under test\n\tld\t(spat),sp\t; save stack pointer\n\tld\tsp,spat\n\tpush\taf\t\t; save other registers\n\tpush\tbc\n\tpush\tde\n\tpush\thl\n\tpush\tix\n\tpush\tiy\n\tld\tsp,(spsav)\t; restore stack pointer\n\tei\t\t\t; enable interrupts\n\tld\thl,(msbt)\t; copy memory operand\n\tld\t(msat),hl\n\tld\thl,flgsat\t; flags after test\n\tld\ta,(hl)\nflgmsk:\tand\ta,0d7h\t\t; mask-out irrelevant bits (self-modified code!)\n\tld\t(hl),a\n\tld\tb,16\t\t; total of 16 bytes of state\n\tld\tde,msat\n\tld\thl,crcval\ntcrc:\tld\ta,(de)\n\tinc\tde\n\tcall\tupdcrc\t\t; accumulate crc of this test case\n\tdec\tb\n\tjp\tnz,tcrc\n      if\t0\n\tld\te,' '\n\tld\tc,2\n\tcall\tbdos\n\tld\thl,crcval\n\tcall\tphex8\n\tld\tde,crlf\n\tld\tc,9\n\tcall\tbdos\n\tld\thl,msat\n\tld\tb,16\n\tcall\thexstr\n\tld\tde,crlf\n\tld\tc,9\n\tcall\tbdos\n      endif\n\tpop\thl\n\tpop\tde\n\tpop\tbc\n\tpop\taf\n\tret\n\n; machine state after test\nmsat:\tds\t14\t; memop,iy,ix,hl,de,bc,af\nspat:\tds\t2\t; stack pointer after test\n; ZMAC/MAXAM doesn't like ':' after label with EQUs\nflgsat\tequ\tspat-2\t; flags\n\nspsav:\tds\t2\t; saved stack pointer\n\n; display hex string (pointer in hl, byte count in b)\nhexstr:\tld\ta,(hl)\n\tcall\tphex2\n\tinc\thl\n\tdec\tb\n\tjp\tnz,hexstr\n\tret\n\n; display hex\n; display the big-endian 32-bit value pointed to by hl\nphex8:\tpush\taf\n\tpush\tbc\n\tpush\thl\n\tld\tb,4\nph8lp:\tld\ta,(hl)\n\tcall\tphex2\n\tinc\thl\n\tdec\tb\n\tjp\tnz,ph8lp\n\tpop\thl\n\tpop\tbc\n\tpop\taf\n\tret\n\n; display byte in a\nphex2:\tpush\taf\n\trrca\n\trrca\n\trrca\n\trrca\n\tcall\tphex1\n\tpop\taf\n; fall through\t\n\n; display low nibble in a\nphex1:\tpush\taf\n\tpush\tbc\n\tpush\tde\n\tpush\thl\n\tand\ta,0fh\n\tcp\ta,10\n\tjp\tc,ph11\n\tadd\ta,'a'-'9'-1\nph11:\tadd\ta,'0'\n\tld\te,a\n\tld\tc,2\n\tcall\tbdos\n\tpop\thl\n\tpop\tde\n\tpop\tbc\n\tpop\taf\n\tret\n\nbdos\tpush\taf\n\tpush\tbc\n\tpush\tde\n\tpush\thl\n\tcall\t5\n\tpop\thl\n\tpop\tde\n\tpop\tbc\n\tpop\taf\n\tret\n\nmsg1:\tdb\t10,13,10,13,'Z80all instruction exerciser',10,13,'$'\nmsg2:\tdb\t'Tests complete$'\nokmsg:\tdb\t'  OK',10,13,'$'\nermsg1:\tdb\t'  ERROR **** crc expected:$'\nermsg2:\tdb\t' found:$'\ncrlf:\tdb\t10,13,'$'\n\n; compare crc\n; hl points to value to compare to crcval\ncmpcrc:\tpush\tbc\n\tpush\tde\n\tpush\thl\n\tld\tde,crcval\n\tld\tb,4\ncclp:\tld\ta,(de)\n\tcp\ta,(hl)\n\tjp\tnz,cce\n\tinc\thl\n\tinc\tde\n\tdec\tb\n\tjp\tnz,cclp\ncce:\tpop\thl\n\tpop\tde\n\tpop\tbc\n\tret\n\n; 32-bit crc routine\n; entry: a contains next byte, hl points to crc\n; exit:  crc updated\nupdcrc:\tpush\taf\n\tpush\tbc\n\tpush\tde\n\tpush\thl\n\tpush\thl\n\tld\tde,3\n\tadd\thl,de\t; point to low byte of old crc\n\txor\ta,(hl)\t; xor with new byte\n\tld\tl,a\n\tld\th,0\n\tadd\thl,hl\t; use result as index into table of 4 byte entries\n\tadd\thl,hl\n\tex\tde,hl\n\tld\thl,crctab\n\tadd\thl,de\t; point to selected entry in crctab\n\tex\tde,hl\n\tpop\thl\n\tld\tbc,4\t; c = byte count, b = accumulator\ncrclp:\tld\ta,(de)\n\txor\ta,b\n\tld\tb,(hl)\n\tld\t(hl),a\n\tinc\tde\n\tinc\thl\n\tdec\tc\n\tjp\tnz,crclp\n      if\t0\n\tld\thl,crcval\n\tcall\tphex8\n\tld\tde,crlf\n\tld\tc,9\n\tcall\tbdos\n      endif\n\tpop\thl\n\tpop\tde\n\tpop\tbc\n\tpop\taf\n\tret\n\ninitcrc:push\taf\n\tpush\tbc\n\tpush\thl\n\tld\thl,crcval\n\tld\ta,0ffh\n\tld\tb,4\nicrclp:\tld\t(hl),a\n\tinc\thl\n\tdec\tb\n\tjp\tnz,icrclp\n\tpop\thl\n\tpop\tbc\n\tpop\taf\n\tret\n\ncrcval\tds\t4\n\ncrctab:\tdb\t000h,000h,000h,000h\n\tdb\t077h,007h,030h,096h\n\tdb\t0eeh,00eh,061h,02ch\n\tdb\t099h,009h,051h,0bah\n\tdb\t007h,06dh,0c4h,019h\n\tdb\t070h,06ah,0f4h,08fh\n\tdb\t0e9h,063h,0a5h,035h\n\tdb\t09eh,064h,095h,0a3h\n\tdb\t00eh,0dbh,088h,032h\n\tdb\t079h,0dch,0b8h,0a4h\n\tdb\t0e0h,0d5h,0e9h,01eh\n\tdb\t097h,0d2h,0d9h,088h\n\tdb\t009h,0b6h,04ch,02bh\n\tdb\t07eh,0b1h,07ch,0bdh\n\tdb\t0e7h,0b8h,02dh,007h\n\tdb\t090h,0bfh,01dh,091h\n\tdb\t01dh,0b7h,010h,064h\n\tdb\t06ah,0b0h,020h,0f2h\n\tdb\t0f3h,0b9h,071h,048h\n\tdb\t084h,0beh,041h,0deh\n\tdb\t01ah,0dah,0d4h,07dh\n\tdb\t06dh,0ddh,0e4h,0ebh\n\tdb\t0f4h,0d4h,0b5h,051h\n\tdb\t083h,0d3h,085h,0c7h\n\tdb\t013h,06ch,098h,056h\n\tdb\t064h,06bh,0a8h,0c0h\n\tdb\t0fdh,062h,0f9h,07ah\n\tdb\t08ah,065h,0c9h,0ech\n\tdb\t014h,001h,05ch,04fh\n\tdb\t063h,006h,06ch,0d9h\n\tdb\t0fah,00fh,03dh,063h\n\tdb\t08dh,008h,00dh,0f5h\n\tdb\t03bh,06eh,020h,0c8h\n\tdb\t04ch,069h,010h,05eh\n\tdb\t0d5h,060h,041h,0e4h\n\tdb\t0a2h,067h,071h,072h\n\tdb\t03ch,003h,0e4h,0d1h\n\tdb\t04bh,004h,0d4h,047h\n\tdb\t0d2h,00dh,085h,0fdh\n\tdb\t0a5h,00ah,0b5h,06bh\n\tdb\t035h,0b5h,0a8h,0fah\n\tdb\t042h,0b2h,098h,06ch\n\tdb\t0dbh,0bbh,0c9h,0d6h\n\tdb\t0ach,0bch,0f9h,040h\n\tdb\t032h,0d8h,06ch,0e3h\n\tdb\t045h,0dfh,05ch,075h\n\tdb\t0dch,0d6h,00dh,0cfh\n\tdb\t0abh,0d1h,03dh,059h\n\tdb\t026h,0d9h,030h,0ach\n\tdb\t051h,0deh,000h,03ah\n\tdb\t0c8h,0d7h,051h,080h\n\tdb\t0bfh,0d0h,061h,016h\n\tdb\t021h,0b4h,0f4h,0b5h\n\tdb\t056h,0b3h,0c4h,023h\n\tdb\t0cfh,0bah,095h,099h\n\tdb\t0b8h,0bdh,0a5h,00fh\n\tdb\t028h,002h,0b8h,09eh\n\tdb\t05fh,005h,088h,008h\n\tdb\t0c6h,00ch,0d9h,0b2h\n\tdb\t0b1h,00bh,0e9h,024h\n\tdb\t02fh,06fh,07ch,087h\n\tdb\t058h,068h,04ch,011h\n\tdb\t0c1h,061h,01dh,0abh\n\tdb\t0b6h,066h,02dh,03dh\n\tdb\t076h,0dch,041h,090h\n\tdb\t001h,0dbh,071h,006h\n\tdb\t098h,0d2h,020h,0bch\n\tdb\t0efh,0d5h,010h,02ah\n\tdb\t071h,0b1h,085h,089h\n\tdb\t006h,0b6h,0b5h,01fh\n\tdb\t09fh,0bfh,0e4h,0a5h\n\tdb\t0e8h,0b8h,0d4h,033h\n\tdb\t078h,007h,0c9h,0a2h\n\tdb\t00fh,000h,0f9h,034h\n\tdb\t096h,009h,0a8h,08eh\n\tdb\t0e1h,00eh,098h,018h\n\tdb\t07fh,06ah,00dh,0bbh\n\tdb\t008h,06dh,03dh,02dh\n\tdb\t091h,064h,06ch,097h\n\tdb\t0e6h,063h,05ch,001h\n\tdb\t06bh,06bh,051h,0f4h\n\tdb\t01ch,06ch,061h,062h\n\tdb\t085h,065h,030h,0d8h\n\tdb\t0f2h,062h,000h,04eh\n\tdb\t06ch,006h,095h,0edh\n\tdb\t01bh,001h,0a5h,07bh\n\tdb\t082h,008h,0f4h,0c1h\n\tdb\t0f5h,00fh,0c4h,057h\n\tdb\t065h,0b0h,0d9h,0c6h\n\tdb\t012h,0b7h,0e9h,050h\n\tdb\t08bh,0beh,0b8h,0eah\n\tdb\t0fch,0b9h,088h,07ch\n\tdb\t062h,0ddh,01dh,0dfh\n\tdb\t015h,0dah,02dh,049h\n\tdb\t08ch,0d3h,07ch,0f3h\n\tdb\t0fbh,0d4h,04ch,065h\n\tdb\t04dh,0b2h,061h,058h\n\tdb\t03ah,0b5h,051h,0ceh\n\tdb\t0a3h,0bch,000h,074h\n\tdb\t0d4h,0bbh,030h,0e2h\n\tdb\t04ah,0dfh,0a5h,041h\n\tdb\t03dh,0d8h,095h,0d7h\n\tdb\t0a4h,0d1h,0c4h,06dh\n\tdb\t0d3h,0d6h,0f4h,0fbh\n\tdb\t043h,069h,0e9h,06ah\n\tdb\t034h,06eh,0d9h,0fch\n\tdb\t0adh,067h,088h,046h\n\tdb\t0dah,060h,0b8h,0d0h\n\tdb\t044h,004h,02dh,073h\n\tdb\t033h,003h,01dh,0e5h\n\tdb\t0aah,00ah,04ch,05fh\n\tdb\t0ddh,00dh,07ch,0c9h\n\tdb\t050h,005h,071h,03ch\n\tdb\t027h,002h,041h,0aah\n\tdb\t0beh,00bh,010h,010h\n\tdb\t0c9h,00ch,020h,086h\n\tdb\t057h,068h,0b5h,025h\n\tdb\t020h,06fh,085h,0b3h\n\tdb\t0b9h,066h,0d4h,009h\n\tdb\t0ceh,061h,0e4h,09fh\n\tdb\t05eh,0deh,0f9h,00eh\n\tdb\t029h,0d9h,0c9h,098h\n\tdb\t0b0h,0d0h,098h,022h\n\tdb\t0c7h,0d7h,0a8h,0b4h\n\tdb\t059h,0b3h,03dh,017h\n\tdb\t02eh,0b4h,00dh,081h\n\tdb\t0b7h,0bdh,05ch,03bh\n\tdb\t0c0h,0bah,06ch,0adh\n\tdb\t0edh,0b8h,083h,020h\n\tdb\t09ah,0bfh,0b3h,0b6h\n\tdb\t003h,0b6h,0e2h,00ch\n\tdb\t074h,0b1h,0d2h,09ah\n\tdb\t0eah,0d5h,047h,039h\n\tdb\t09dh,0d2h,077h,0afh\n\tdb\t004h,0dbh,026h,015h\n\tdb\t073h,0dch,016h,083h\n\tdb\t0e3h,063h,00bh,012h\n\tdb\t094h,064h,03bh,084h\n\tdb\t00dh,06dh,06ah,03eh\n\tdb\t07ah,06ah,05ah,0a8h\n\tdb\t0e4h,00eh,0cfh,00bh\n\tdb\t093h,009h,0ffh,09dh\n\tdb\t00ah,000h,0aeh,027h\n\tdb\t07dh,007h,09eh,0b1h\n\tdb\t0f0h,00fh,093h,044h\n\tdb\t087h,008h,0a3h,0d2h\n\tdb\t01eh,001h,0f2h,068h\n\tdb\t069h,006h,0c2h,0feh\n\tdb\t0f7h,062h,057h,05dh\n\tdb\t080h,065h,067h,0cbh\n\tdb\t019h,06ch,036h,071h\n\tdb\t06eh,06bh,006h,0e7h\n\tdb\t0feh,0d4h,01bh,076h\n\tdb\t089h,0d3h,02bh,0e0h\n\tdb\t010h,0dah,07ah,05ah\n\tdb\t067h,0ddh,04ah,0cch\n\tdb\t0f9h,0b9h,0dfh,06fh\n\tdb\t08eh,0beh,0efh,0f9h\n\tdb\t017h,0b7h,0beh,043h\n\tdb\t060h,0b0h,08eh,0d5h\n\tdb\t0d6h,0d6h,0a3h,0e8h\n\tdb\t0a1h,0d1h,093h,07eh\n\tdb\t038h,0d8h,0c2h,0c4h\n\tdb\t04fh,0dfh,0f2h,052h\n\tdb\t0d1h,0bbh,067h,0f1h\n\tdb\t0a6h,0bch,057h,067h\n\tdb\t03fh,0b5h,006h,0ddh\n\tdb\t048h,0b2h,036h,04bh\n\tdb\t0d8h,00dh,02bh,0dah\n\tdb\t0afh,00ah,01bh,04ch\n\tdb\t036h,003h,04ah,0f6h\n\tdb\t041h,004h,07ah,060h\n\tdb\t0dfh,060h,0efh,0c3h\n\tdb\t0a8h,067h,0dfh,055h\n\tdb\t031h,06eh,08eh,0efh\n\tdb\t046h,069h,0beh,079h\n\tdb\t0cbh,061h,0b3h,08ch\n\tdb\t0bch,066h,083h,01ah\n\tdb\t025h,06fh,0d2h,0a0h\n\tdb\t052h,068h,0e2h,036h\n\tdb\t0cch,00ch,077h,095h\n\tdb\t0bbh,00bh,047h,003h\n\tdb\t022h,002h,016h,0b9h\n\tdb\t055h,005h,026h,02fh\n\tdb\t0c5h,0bah,03bh,0beh\n\tdb\t0b2h,0bdh,00bh,028h\n\tdb\t02bh,0b4h,05ah,092h\n\tdb\t05ch,0b3h,06ah,004h\n\tdb\t0c2h,0d7h,0ffh,0a7h\n\tdb\t0b5h,0d0h,0cfh,031h\n\tdb\t02ch,0d9h,09eh,08bh\n\tdb\t05bh,0deh,0aeh,01dh\n\tdb\t09bh,064h,0c2h,0b0h\n\tdb\t0ech,063h,0f2h,026h\n\tdb\t075h,06ah,0a3h,09ch\n\tdb\t002h,06dh,093h,00ah\n\tdb\t09ch,009h,006h,0a9h\n\tdb\t0ebh,00eh,036h,03fh\n\tdb\t072h,007h,067h,085h\n\tdb\t005h,000h,057h,013h\n\tdb\t095h,0bfh,04ah,082h\n\tdb\t0e2h,0b8h,07ah,014h\n\tdb\t07bh,0b1h,02bh,0aeh\n\tdb\t00ch,0b6h,01bh,038h\n\tdb\t092h,0d2h,08eh,09bh\n\tdb\t0e5h,0d5h,0beh,00dh\n\tdb\t07ch,0dch,0efh,0b7h\n\tdb\t00bh,0dbh,0dfh,021h\n\tdb\t086h,0d3h,0d2h,0d4h\n\tdb\t0f1h,0d4h,0e2h,042h\n\tdb\t068h,0ddh,0b3h,0f8h\n\tdb\t01fh,0dah,083h,06eh\n\tdb\t081h,0beh,016h,0cdh\n\tdb\t0f6h,0b9h,026h,05bh\n\tdb\t06fh,0b0h,077h,0e1h\n\tdb\t018h,0b7h,047h,077h\n\tdb\t088h,008h,05ah,0e6h\n\tdb\t0ffh,00fh,06ah,070h\n\tdb\t066h,006h,03bh,0cah\n\tdb\t011h,001h,00bh,05ch\n\tdb\t08fh,065h,09eh,0ffh\n\tdb\t0f8h,062h,0aeh,069h\n\tdb\t061h,06bh,0ffh,0d3h\n\tdb\t016h,06ch,0cfh,045h\n\tdb\t0a0h,00ah,0e2h,078h\n\tdb\t0d7h,00dh,0d2h,0eeh\n\tdb\t04eh,004h,083h,054h\n\tdb\t039h,003h,0b3h,0c2h\n\tdb\t0a7h,067h,026h,061h\n\tdb\t0d0h,060h,016h,0f7h\n\tdb\t049h,069h,047h,04dh\n\tdb\t03eh,06eh,077h,0dbh\n\tdb\t0aeh,0d1h,06ah,04ah\n\tdb\t0d9h,0d6h,05ah,0dch\n\tdb\t040h,0dfh,00bh,066h\n\tdb\t037h,0d8h,03bh,0f0h\n\tdb\t0a9h,0bch,0aeh,053h\n\tdb\t0deh,0bbh,09eh,0c5h\n\tdb\t047h,0b2h,0cfh,07fh\n\tdb\t030h,0b5h,0ffh,0e9h\n\tdb\t0bdh,0bdh,0f2h,01ch\n\tdb\t0cah,0bah,0c2h,08ah\n\tdb\t053h,0b3h,093h,030h\n\tdb\t024h,0b4h,0a3h,0a6h\n\tdb\t0bah,0d0h,036h,005h\n\tdb\t0cdh,0d7h,006h,093h\n\tdb\t054h,0deh,057h,029h\n\tdb\t023h,0d9h,067h,0bfh\n\tdb\t0b3h,066h,07ah,02eh\n\tdb\t0c4h,061h,04ah,0b8h\n\tdb\t05dh,068h,01bh,002h\n\tdb\t02ah,06fh,02bh,094h\n\tdb\t0b4h,00bh,0beh,037h\n\tdb\t0c3h,00ch,08eh,0a1h\n\tdb\t05ah,005h,0dfh,01bh\n\tdb\t02dh,002h,0efh,08dh\n\n"
  },
  {
    "path": "tools/zmac/zexdoc.asm",
    "content": "\ttitle\t'Z80 instruction set exerciser'\n\n; zexdoc.src - Z80 documented instruction set exerciser\n; Original Copyright (C) 1994  Frank D. Cringle\n; Changes at 03-Nov-2002 Copyright (C) 2002 J.G.Harston\n; + Source syntax tweeked to assemble with ZMAC Z80 Macro Assembler\n;   and MAXAM Assembler, marked in the source with 'jgh:'\n; + labels on equates mustn't have trailing colon\n; + macros don't understand <...> sequence, so parameters are passed\n;   explicitly\n; + ds n,c not supported, so strings are set to full explicity length\n;\n; This program is free software; you can redistribute it and/or\n; modify it under the terms of the GNU General Public License\n; as published by the Free Software Foundation; either version 2\n; of the License, or (at your option) any later version.\n;\n; This program is distributed in the hope that it will be useful,\n; but WITHOUT ANY WARRANTY; without even the implied warranty of\n; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n; GNU General Public License for more details.\n;\n; You should have received a copy of the GNU General Public License\n; along with this program; if not, write to the Free Software\n; Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.\n\n\taseg\n\n;\n; Boot code for the A-Z80 CPU FPGA implementation\n;\n    org 0\nstart:\n    jmp boot\n\n    ; BDOS entry point for various functions\n    ; We implement subfunctions:\n    ;  C=2  Print a character given in E\n    ;  C=9  Print a string pointed to by DE; string ends with '$'\n    org 5\n    ld  a,c\n    cp  a,2\n    jz  bdos_ascii\n    cp  a,9\n    jz  bdos_msg\n    ret\n\nbdos_ascii:\n    ld  bc,10*256   ; Port to check for busy\n    in  a,(c)       ; Poll until the port is not busy\n    bit 0,a\n    jnz bdos_ascii\n    ld  bc,8*256    ; Port to write a character out\n    out (c),e\n    ret\n\nbdos_msg:\n    push de\n    pop hl\nlp0:\n    ld  e,(hl)\n    ld  a,e\n    cp  a,'$'\n    ret z\n    call bdos_ascii\n    inc hl\n    jmp lp0\n\n;---------------------------------------------------------------------\n; RST38 (also INT M0)  handler\n;---------------------------------------------------------------------\n    org 038h\n    push de\n    ld  de,int_msg\nint_common:\n    push af\n    push bc\n    push hl\n    ld  c,9\n    call 5\n    pop hl\n    pop bc\n    pop af\n    pop de\n    ei\n    reti\nint_msg:\n    db  \"_INT_\",'$'\n\n;---------------------------------------------------------------------\n; NMI handler\n;---------------------------------------------------------------------\n    org 066h\n    push af\n    push bc\n    push de\n    push hl\n    ld  de,nmi_msg\n    ld  c,9\n    call 5\n    pop hl\n    pop de\n    pop bc\n    pop af\n    retn\nnmi_msg:\n    db  \"_NMI_\",'$'\n\n;---------------------------------------------------------------------\n; IM2 vector address and the handler (to push 0x80 by the IORQ)\n;---------------------------------------------------------------------\n    org 080h\n    dw  im2_handler\nim2_handler:\n    push de\n    ld  de,int_im2_msg\n    jmp int_common\nint_im2_msg:\n    db  \"_IM2_\",'$'\n\nboot:\n    ; Set the stack pointer\n    ld  sp, 16384   ; 16 Kb of RAM\n    ; Jump into the executable at 100h\n    jmp 100h\n\n\torg\t100h\n\n\tjp\tstart100\n\n; machine state before test (needs to be at predictably constant address)\nmsbt:\tds\t14\nspbt:\tds\t2\nmsbthi\tequ\tmsbt / 0100h\nmsbtlo\tequ\tmsbt & 0ffh\n\n\n; For the purposes of this test program, the machine state consists of:\n;\ta 2 byte memory operand, followed by\n;\tthe registers iy,ix,hl,de,bc,af,sp\n; for a total of 16 bytes.\n\n; The program tests instructions (or groups of similar instructions)\n; by cycling through a sequence of machine states, executing the test\n; instruction for each one and running a 32-bit crc over the resulting\n; machine states.  At the end of the sequence the crc is compared to\n; an expected value that was found empirically on a real Z80.\n\n; A test case is defined by a descriptor which consists of:\n;\ta flag mask byte,\n;\tthe base case,\n;\tthe incement vector,\n;\tthe shift vector,\n;\tthe expected crc,\n;\ta short descriptive message.\n;\n; The flag mask byte is used to prevent undefined flag bits from\n; influencing the results.  Documented flags are as per Mostek Z80\n; Technical Manual.\n;\n; The next three parts of the descriptor are 20 byte vectors\n; corresponding to a 4 byte instruction and a 16 byte machine state.\n; The first part is the base case, which is the first test case of\n; the sequence.  This base is then modified according to the next 2\n; vectors.  Each 1 bit in the increment vector specifies a bit to be\n; cycled in the form of a binary counter.  For instance, if the byte\n; corresponding to the accumulator is set to 0ffh in the increment\n; vector, the test will be repeated for all 256 values of the\n; accumulator.  Note that 1 bits don't have to be contiguous.  The\n; number of test cases 'caused' by the increment vector is equal to\n; 2^(number of 1 bits).  The shift vector is similar, but specifies a\n; set of bits in the test case that are to be successively inverted.\n; Thus the shift vector 'causes' a number of test cases equal to the\n; number of 1 bits in it.\n\n; The total number of test cases is the product of those caused by the\n; counter and shift vectors and can easily become unweildy.  Each\n; individual test case can take a few milliseconds to execute, due to\n; the overhead of test setup and crc calculation, so test design is a\n; compromise between coverage and execution time.\n\n; This program is designed to detect differences between\n; implementations and is not ideal for diagnosing the causes of any\n; discrepancies.  However, provided a reference implementation (or\n; real system) is available, a failing test case can be isolated by\n; hand using a binary search of the test space.\n\n\nstart100:\tld\thl,(6)\n\t;ld\tsp,hl\n\tld\tde,msg1\n\tld\tc,9\n\tcall\tbdos\n\n\tld\thl,tests\t; first test case\nloop:\tld\ta,(hl)\t\t; end of list ?\n\tinc\thl\n\tor\t(hl)\n\tjp\tz,done\n\tdec\thl\n\tcall\tstt\n\tjp\tloop\n\t\ndone:\tld\tde,msg2\n\tld\tc,9\n\tcall\tbdos\ndie: jr die\n\tjp\t0\t\t; warm boot\n\ntests:\n\tdw\tadc16\n\tdw\tadd16\n\tdw\tadd16x\n\tdw\tadd16y\n\tdw\talu8i\n;\tdw\talu8r   ; takes _very_long_ time, but it passes!\n\tdw\talu8rx\n\tdw\talu8x\n\tdw\tbitx\n\tdw\tbitz80\n\tdw\tcpd1\n\tdw\tcpi1\n\tdw\tdaaop\t; can't use opcode as label\n\tdw\tinca\n\tdw\tincb\n\tdw\tincbc\n\tdw\tincc\n\tdw\tincd\n\tdw\tincde\n\tdw\tince\n\tdw\tinch\n\tdw\tinchl\n\tdw\tincix\n\tdw\tinciy\n\tdw\tincl\n\tdw\tincm\n\tdw\tincsp\n\tdw\tincx\n\tdw\tincxh\n\tdw\tincxl\n\tdw\tincyh\n\tdw\tincyl\n\tdw\tld161\n\tdw\tld162\n\tdw\tld163\n\tdw\tld164\n\tdw\tld165\n\tdw\tld166\n\tdw\tld167\n\tdw\tld168\n\tdw\tld16im\n\tdw\tld16ix\n\tdw\tld8bd\n\tdw\tld8im\n\tdw\tld8imx\n\tdw\tld8ix1\n\tdw\tld8ix2\n\tdw\tld8ix3\n\tdw\tld8ixy\n\tdw\tld8rr\n\tdw\tld8rrx\n\tdw\tlda\n\tdw\tldd1\n\tdw\tldd2\n\tdw\tldi1\n\tdw\tldi2\n\tdw\tnegop\t; jgh: can't use opcode as label\n\tdw\trldop\t; jgh: can't use opcode as label\n\tdw\trot8080\n\tdw\trotxy\n\tdw\trotz80\n\tdw\tsrz80\n\tdw\tsrzx\n\tdw\tst8ix1\n\tdw\tst8ix2\n\tdw\tst8ix3\n\tdw\tstabd\n\tdw\t0\n\n; jgh: macro syntax changed for ZMAC and MAXAM\n;\tcan't use opcodes as labels\n;\tZMAC allows &nn as hex, so & removed from local labels\n;\ntstr\tmacro\tinsn1,insn2,insn3,insn4,memop,riy,rix,rhl,rde,rbc,flags,acc,rsp,?lab\n?lab:\tdb\tinsn1,insn2,insn3,insn4\n\tdw\tmemop,riy,rix,rhl,rde,rbc\n\tdb\tflags\n\tdb\tacc\n\tdw\trsp\n\tif\t$-?lab ne 20\n\terror\t'missing parameter'\n\tendif\n\tendm\n\ntmsg\tmacro\tmsg,?lab\n?lab:\tdb\t'msg'\n\tif\t$ ge ?lab+31\n\terror\t'message too long'\n\telse\n;\tds\t?lab+30-$,'.'\t; jgh: ZMAC/MAXAM don't have char parameter\n\tendif\n\tdb\t'$'\n\tendm\n\n; jgh: ZMAC/MAXAM don't recognise <n,m> syntax for macros, so full parameters given\n; jgh: each tmsg has full string, as ZMAC/MAXAM don't have ds n,c pseudo-op\n\n; <adc,sbc> hl,<bc,de,hl,sp> (38,912 cycles)\nadc16:\tdb\t0c7h\t\t; flag mask\n\ttstr\t0edh,042h,0,0,0832ch,04f88h,0f22bh,0b339h,07e1fh,01563h,0d3h,089h,0465eh\n\ttstr\t0,038h,0,0,0,0,0,0f821h,0,0,0,0,0\t; (1024 cycles)\n\ttstr\t0,0,0,0,0,0,0,-1,-1,-1,0d7h,0,-1\t; (38 cycles)\n\tdb\t0f8h,0b4h,0eah,0a9h\t\t\t; expected crc\n\ttmsg\t'<adc,sbc> hl,<bc,de,hl,sp>....'\n\n; add hl,<bc,de,hl,sp> (19,456 cycles)\nadd16:\tdb\t0c7h\t\t; flag mask\n\ttstr\t9,0,0,0,0c4a5h,0c4c7h,0d226h,0a050h,058eah,08566h,0c6h,0deh,09bc9h\n\ttstr\t030h,0,0,0,0,0,0,0f821h,0,0,0,0,0\t; (512 cycles)\n\ttstr\t0,0,0,0,0,0,0,-1,-1,-1,0d7h,0,-1\t; (38 cycles)\n\tdb\t089h,0fdh,0b6h,035h\t\t\t; expected crc\n\ttmsg\t'add hl,<bc,de,hl,sp>..........'\n\n; add ix,<bc,de,ix,sp> (19,456 cycles)\nadd16x:\tdb\t0c7h\t\t; flag mask\n\ttstr\t0ddh,9,0,0,0ddach,0c294h,0635bh,033d3h,06a76h,0fa20h,094h,068h,036f5h\n\ttstr\t0,030h,0,0,0,0,0f821h,0,0,0,0,0,0\t; (512 cycles)\n\ttstr\t0,0,0,0,0,0,-1,0,-1,-1,0d7h,0,-1\t; (38 cycles)\n\tdb\t0c1h,033h,079h,00bh\t\t\t; expected crc\n\ttmsg\t'add ix,<bc,de,ix,sp>..........'\n\n; add iy,<bc,de,iy,sp> (19,456 cycles)\nadd16y:\tdb\t0c7h\t\t; flag mask\n\ttstr\t0fdh,9,0,0,0c7c2h,0f407h,051c1h,03e96h,00bf4h,0510fh,092h,01eh,071eah\n\ttstr\t0,030h,0,0,0,0f821h,0,0,0,0,0,0,0\t; (512 cycles)\n\ttstr\t0,0,0,0,0,-1,0,0,-1,-1,0d7h,0,-1\t\t; (38 cycles)\n\tdb\t0e8h,081h,07bh,09eh\t\t\t; expected crc\n\ttmsg\t'add iy,<bc,de,iy,sp>..........'\n\n; aluop a,nn (28,672 cycles)\nalu8i:\tdb\t0d7h\t\t; flag mask\n\ttstr\t0c6h,0,0,0,009140h,07e3ch,07a67h,0df6dh,05b61h,00b29h,010h,066h,085b2h\n\ttstr\t038h,0,0,0,0,0,0,0,0,0,0,-1,0\t\t; (2048 cycles)\n\ttstr\t0,-1,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (14 cycles)\n\tdb\t048h,079h,093h,060h\t\t\t; expected crc\n\ttmsg\t'aluop a,nn....................'\n\n; aluop a,<b,c,d,e,h,l,(hl),a> (753,664 cycles)\nalu8r:\tdb\t0d7h\t\t; flag mask\n\ttstr\t080h,0,0,0,0c53eh,0573ah,04c4dh,msbt,0e309h,0a666h,0d0h,03bh,0adbbh\n\ttstr\t03fh,0,0,0,0,0,0,0,0,0,0,-1,0\t\t; (16,384 cycles)\n\ttstr\t0,0,0,0,0ffh,0,0,0,-1,-1,0d7h,0,0\t; (46 cycles)\n\tdb\t0feh,043h,0b0h,016h\t\t\t; expected crc\n\ttmsg\t'aluop a,<b,c,d,e,h,l,(hl),a>..'\n\n; aluop a,<ixh,ixl,iyh,iyl> (376,832 cycles)\nalu8rx:\tdb\t0d7h\t\t; flag mask\n\ttstr\t0ddh,084h,0,0,0d6f7h,0c76eh,0accfh,02847h,022ddh,0c035h,0c5h,038h,0234bh\n\ttstr\t020h,039h,0,0,0,0,0,0,0,0,0,-1,0\t; (8,192 cycles)\n\ttstr\t0,0,0,0,0ffh,0,0,0,-1,-1,0d7h,0,0\t; (46 cycles)\n\tdb\t0a4h,002h,06dh,05ah\t\t\t; expected crc\n\ttmsg\t'aluop a,<ixh,ixl,iyh,iyl>.....'\n\n; aluop a,(<ix,iy>+1) (229,376 cycles)\nalu8x:\tdb\t0d7h\t\t; flag mask\n\ttstr\t0ddh,086h,1,0,090b7h,msbt-1,msbt-1,032fdh,0406eh,0c1dch,045h,06eh,0e5fah\n\ttstr\t020h,038h,0,0,0,1,1,0,0,0,0,-1,0\t; (16,384 cycles)\n\ttstr\t0,0,0,0,0ffh,0,0,0,0,0,0d7h,0,0\t\t; (14 cycles)\n\tdb\t0e8h,049h,067h,06eh\t\t\t; expected crc\n\ttmsg\t'aluop a,(<ix,iy>+1)...........'\n\n; bit n,(<ix,iy>+1) (2048 cycles)\nbitx:\tdb\t053h\t\t; flag mask\n\ttstr\t0ddh,0cbh,1,046h,02075h,msbt-1,msbt-1,03cfch,0a79ah,03d74h,051h,027h,0ca14h\n\ttstr\t020h,0,0,038h,0,0,0,0,0,0,053h,0,0\t; (256 cycles)\n\ttstr\t0,0,0,0,0ffh,0,0,0,0,0,0,0,0\t\t; (8 cycles)\n\tdb\t0a8h,0eeh,008h,067h\t\t\t; expected crc\n\ttmsg\t'bit n,(<ix,iy>+1).............'\n\n; bit n,<b,c,d,e,h,l,(hl),a> (49,152 cycles)\nbitz80:\tdb\t053h\t\t; flag mask\n\ttstr\t0cbh,040h,0,0,03ef1h,09dfch,07acch,msbt,0be61h,07a86h,050h,024h,01998h\n\ttstr\t0,03fh,0,0,0,0,0,0,0,0,053h,0,0\t\t; (1024 cycles)\n\ttstr\t0,0,0,0,0ffh,0,0,0,-1,-1,0,-1,0\t\t; (48 cycles)\n\tdb\t07bh,055h,0e6h,0c8h\t\t\t; expected crc\n\ttmsg\t'bit n,<b,c,d,e,h,l,(hl),a>....'\n\n; cpd<r> (1) (6144 cycles)\ncpd1:\tdb\t0d7h\t\t; flag mask\n\ttstr\t0edh,0a9h,0,0,0c7b6h,072b4h,018f6h,msbt+17,08dbdh,1,0c0h,030h,094a3h\n\ttstr\t0,010h,0,0,0,0,0,0,0,010,0,-1,0\t\t; (1024 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t0a8h,07eh,06ch,0fah\t\t\t; expected crc\n\ttmsg\t'cpd<r>........................'\n\n; cpi<r> (1) (6144 cycles)\ncpi1:\tdb\t0d7h\t\t; flag mask\n\ttstr\t0edh,0a1h,0,0,04d48h,0af4ah,0906bh,msbt,04e71h,1,093h,06ah,0907ch\n\ttstr\t0,010h,0,0,0,0,0,0,0,010,0,-1,0\t\t; (1024 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t006h,0deh,0b3h,056h\t\t\t; expected crc\n\ttmsg\t'cpi<r>........................'\n\n; <daa,cpl,scf,ccf>\ndaaop:\tdb\t0d7h\t\t; flag mask\n\ttstr\t027h,0,0,0,02141h,009fah,01d60h,0a559h,08d5bh,09079h,004h,08eh,0299dh\n\ttstr\t018h,0,0,0,0,0,0,0,0,0,0d7h,-1,0\t; (65,536 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0,0,0\t\t; (1 cycle)\n\tdb\t09bh,04bh,0a6h,075h\t\t\t; expected crc\n\ttmsg\t'<daa,cpl,scf,ccf>.............'\n\n; <inc,dec> a (3072 cycles)\ninca:\tdb\t0d7h\t\t; flag mask\n\ttstr\t03ch,0,0,0,04adfh,0d5d8h,0e598h,08a2bh,0a7b0h,0431bh,044h,05ah,0d030h\n\ttstr\t001h,0,0,0,0,0,0,0,0,0,0,-1,0\t\t; (512 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t0d1h,088h,015h,0a4h\t\t\t; expected crc\n\ttmsg\t'<inc,dec> a...................'\n\n; <inc,dec> b (3072 cycles)\nincb:\tdb\t0d7h\t\t; flag mask\n\ttstr\t004h,0,0,0,0d623h,0432dh,07a61h,08180h,05a86h,01e85h,086h,058h,09bbbh\n\ttstr\t001h,0,0,0,0,0,0,0,0,0ff00h,0,0,0\t; (512 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t05fh,068h,022h,064h\t\t\t; expected crc\n\ttmsg\t'<inc,dec> b...................'\n\n; <inc,dec> bc (1536 cycles)\nincbc:\tdb\t0d7h\t\t; flag mask\n\ttstr\t003h,0,0,0,0cd97h,044abh,08dc9h,0e3e3h,011cch,0e8a4h,002h,049h,02a4dh\n\ttstr\t008h,0,0,0,0,0,0,0,0,0f821h,0,0,0\t; (256 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t0d2h,0aeh,03bh,0ech\t\t\t; expected crc\n\ttmsg\t'<inc,dec> bc..................'\n\n; <inc,dec> c (3072 cycles)\nincc:\tdb\t0d7h\t\t; flag mask\n\ttstr\t00ch,0,0,0,0d789h,00935h,0055bh,09f85h,08b27h,0d208h,095h,005h,00660h\n\ttstr\t001h,0,0,0,0,0,0,0,0,0ffh,0,0,0\t\t; (512 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t0c2h,084h,055h,04ch\t\t\t; expected crc\n\ttmsg\t'<inc,dec> c...................'\n\n; <inc,dec> d (3072 cycles)\nincd:\tdb\t0d7h\t\t; flag mask\n\ttstr\t014h,0,0,0,0a0eah,05fbah,065fbh,0981ch,038cch,0debch,043h,05ch,003bdh\n\ttstr\t001h,0,0,0,0,0,0,0,0ff00h,0,0,0,0\t; (512 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t045h,023h,0deh,010h\t\t\t; expected crc\n\ttmsg\t'<inc,dec> d...................'\n\n; <inc,dec> de (1536 cycles)\nincde:\tdb\t0d7h\t\t; flag mask\n\ttstr\t013h,0,0,0,0342eh,0131dh,028c9h,00acah,09967h,03a2eh,092h,0f6h,09d54h\n\ttstr\t008h,0,0,0,0,0,0,0,0f821h,0,0,0,0\t; (256 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t0aeh,0c6h,0d4h,02ch\t\t\t; expected crc\n\ttmsg\t'<inc,dec> de..................'\n\n; <inc,dec> e (3072 cycles)\nince:\tdb\t0d7h\t\t; flag mask\n\ttstr\t01ch,0,0,0,0602fh,04c0dh,02402h,0e2f5h,0a0f4h,0a10ah,013h,032h,05925h\n\ttstr\t001h,0,0,0,0,0,0,0,0ffh,0,0,0,0\t\t; (512 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t0e1h,075h,0afh,0cch\t\t\t; expected crc\n\ttmsg\t'<inc,dec> e...................'\n\n; <inc,dec> h (3072 cycles)\ninch:\tdb\t0d7h\t\t; flag mask\n\ttstr\t024h,0,0,0,01506h,0f2ebh,0e8ddh,0262bh,011a6h,0bc1ah,017h,006h,02818h\n\ttstr\t001h,0,0,0,0,0,0,0ff00h,0,0,0,0,0\t; (512 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t01ch,0edh,084h,07dh\t\t\t; expected crc\n\ttmsg\t'<inc,dec> h...................'\n\n; <inc,dec> hl (1536 cycles)\ninchl:\tdb\t0d7h\t\t; flag mask\n\ttstr\t023h,0,0,0,0c3f4h,007a5h,01b6dh,04f04h,0e2c2h,0822ah,057h,0e0h,0c3e1h\n\ttstr\t008h,0,0,0,0,0,0,0f821h,0,0,0,0,0\t; (256 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t0fch,00dh,06dh,04ah\t\t\t; expected crc\n\ttmsg\t'<inc,dec> hl..................'\n\n; <inc,dec> ix (1536 cycles)\nincix:\tdb\t0d7h\t\t; flag mask\n\ttstr\t0ddh,023h,0,0,0bc3ch,00d9bh,0e081h,0adfdh,09a7fh,096e5h,013h,085h,00be2h\n\ttstr\t0,8,0,0,0,0,0f821h,0,0,0,0,0,0\t\t; (256 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t0a5h,04dh,0beh,031h\t\t\t; expected crc\n\ttmsg\t'<inc,dec> ix..................'\n\n; <inc,dec> iy (1536 cycles)\ninciy:\tdb\t0d7h\t\t; flag mask\n\ttstr\t0fdh,023h,0,0,09402h,0637ah,03182h,0c65ah,0b2e9h,0abb4h,016h,0f2h,06d05h\n\ttstr\t0,8,0,0,0,0f821h,0,0,0,0,0,0,0\t\t; (256 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t050h,05dh,051h,0a3h\t\t\t; expected crc\n\ttmsg\t'<inc,dec> iy..................'\n\n; <inc,dec> l (3072 cycles)\nincl:\tdb\t0d7h\t\t; flag mask\n\ttstr\t02ch,0,0,0,08031h,0a520h,04356h,0b409h,0f4c1h,0dfa2h,0d1h,03ch,03ea2h\n\ttstr\t001h,0,0,0,0,0,0,0ffh,0,0,0,0,0\t\t; (512 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t056h,0cdh,006h,0f3h\t\t\t; expected crc\n\ttmsg\t'<inc,dec> l...................'\n\n; <inc,dec> (hl) (3072 cycles)\nincm:\tdb\t0d7h\t\t; flag mask\n\ttstr\t034h,0,0,0,0b856h,00c7ch,0e53eh,msbt,0877eh,0da58h,015h,05ch,01f37h\n\ttstr\t001h,0,0,0,0ffh,0,0,0,0,0,0,0,0\t\t; (512 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t0b8h,03ah,0dch,0efh\t\t\t; expected crc\n\ttmsg\t'<inc,dec> (hl)................'\n\n; <inc,dec> sp (1536 cycles)\nincsp:\tdb\t0d7h\t\t; flag mask\n\ttstr\t033h,0,0,0,0346fh,0d482h,0d169h,0deb6h,0a494h,0f476h,053h,002h,0855bh\n\ttstr\t008h,0,0,0,0,0,0,0,0,0,0,0,0f821h\t; (256 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t05dh,0ach,0d5h,027h\t\t\t; expected crc\n\ttmsg\t'<inc,dec> sp..................'\n\n; <inc,dec> (<ix,iy>+1) (6144 cycles)\nincx:\tdb\t0d7h\t\t; flag mask\n\ttstr\t0ddh,034h,1,0,0fa6eh,msbt-1,msbt-1,02c28h,08894h,05057h,016h,033h,0286fh\n\ttstr\t020h,1,0,0,0ffh,0,0,0,0,0,0,0,0\t\t; (1024 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t020h,058h,014h,070h\t\t\t; expected crc\n\ttmsg\t'<inc,dec> (<ix,iy>+1).........'\n\n; <inc,dec> ixh (3072 cycles)\nincxh:\tdb\t0d7h\t\t; flag mask\n\ttstr\t0ddh,024h,0,0,0b838h,0316ch,0c6d4h,03e01h,08358h,015b4h,081h,0deh,04259h\n\ttstr\t0,1,0,0,0,0ff00h,0,0,0,0,0,0,0\t\t; (512 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t06fh,046h,036h,062h\t\t\t; expected crc\n\ttmsg\t'<inc,dec> ixh.................'\n\n; <inc,dec> ixl (3072 cycles)\nincxl:\tdb\t0d7h\t\t; flag mask\n\ttstr\t0ddh,02ch,0,0,04d14h,07460h,076d4h,006e7h,032a2h,0213ch,0d6h,0d7h,099a5h\n\ttstr\t0,1,0,0,0,0ffh,0,0,0,0,0,0,0\t\t; (512 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t002h,07bh,0efh,02ch\t\t\t; expected crc\n\ttmsg\t'<inc,dec> ixl.................'\n\n; <inc,dec> iyh (3072 cycles)\nincyh:\tdb\t0d7h\t\t; flag mask\n\ttstr\t0ddh,024h,0,0,02836h,09f6fh,09116h,061b9h,082cbh,0e219h,092h,073h,0a98ch\n\ttstr\t0,1,0,0,0ff00h,0,0,0,0,0,0,0,0\t\t; (512 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t02dh,096h,06ch,0f3h\t\t\t; expected crc\n\ttmsg\t'<inc,dec> iyh.................'\n\n; <inc,dec> iyl (3072 cycles)\nincyl:\tdb\t0d7h\t\t; flag mask\n\ttstr\t0ddh,02ch,0,0,0d7c6h,062d5h,0a09eh,07039h,03e7eh,09f12h,090h,0d9h,0220fh\n\ttstr\t0,1,0,0,0ffh,0,0,0,0,0,0,0,0\t\t; (512 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t0fbh,0cbh,0bah,095h\t\t\t; expected crc\n\ttmsg\t'<inc,dec> iyl.................'\n\n; ld <bc,de>,(nnnn) (32 cycles)\nld161:\tdb\t0d7h\t\t; flag mask\n\ttstr\t0edh,04bh,msbtlo,msbthi,0f9a8h,0f559h,093a4h,0f5edh,06f96h,0d968h,086h,0e6h,04bd8h\n\ttstr\t0,010h,0,0,0,0,0,0,0,0,0,0,0\t\t; (2 cycles)\n\ttstr\t0,0,0,0,-1,0,0,0,0,0,0,0,0\t\t; (16 cycles)\n\tdb\t04dh,045h,0a9h,0ach\t\t\t; expected crc\n\ttmsg\t'ld <bc,de>,(nnnn).............'\n\n; ld hl,(nnnn) (16 cycles)\nld162:\tdb\t0d7h\t\t; flag mask\n\ttstr\t02ah,msbtlo,msbthi,0,09863h,07830h,02077h,0b1feh,0b9fah,0abb8h,004h,006h,06015h\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0,0,0\t\t; (1 cycle)\n\ttstr\t0,0,0,0,-1,0,0,0,0,0,0,0,0\t\t; (16 cycles)\n\tdb\t05fh,097h,024h,087h\t\t\t; expected crc\n\ttmsg\t'ld hl,(nnnn)..................'\n\t\n; ld sp,(nnnn) (16 cycles)\nld163:\tdb\t0d7h\t\t; flag mask\n\ttstr\t0edh,07bh,msbtlo,msbthi,08dfch,057d7h,02161h,0ca18h,0c185h,027dah,083h,01eh,0f460h\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0,0,0\t\t; (1 cycles)\n\ttstr\t0,0,0,0,-1,0,0,0,0,0,0,0,0\t\t; (16 cycles)\n\tdb\t07ah,0ceh,0a1h,01bh\t\t\t; expected crc\n\ttmsg\t'ld sp,(nnnn)..................'\n\n; ld <ix,iy>,(nnnn) (32 cycles)\nld164:\tdb\t0d7h\t\t; flag mask\n\ttstr\t0ddh,02ah,msbtlo,msbthi,0ded7h,0a6fah,0f780h,0244ch,087deh,0bcc2h,016h,063h,04c96h\n\ttstr\t020h,0,0,0,0,0,0,0,0,0,0,0,0\t\t; (2 cycles)\n\ttstr\t0,0,0,0,-1,0,0,0,0,0,0,0,0\t\t; (16 cycles)\n\tdb\t085h,08bh,0f1h,06dh\t\t\t; expected crc\n\ttmsg\t'ld <ix,iy>,(nnnn).............'\n\t\n; ld (nnnn),<bc,de> (64 cycles)\nld165:\tdb\t0d7h\t\t; flag mask\n\ttstr\t0edh,043h,msbtlo,msbthi,01f98h,0844dh,0e8ach,0c9edh,0c95dh,08f61h,080h,03fh,0c7bfh\n\ttstr\t0,010h,0,0,0,0,0,0,0,0,0,0,0\t\t; (2 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,-1,-1,0,0,0\t\t; (32 cycles)\n\tdb\t064h,01eh,087h,015h\t\t\t; expected crc\n\ttmsg\t'ld (nnnn),<bc,de>.............'\n\n; ld (nnnn),hl (16 cycles)\nld166:\tdb\t0d7h\t\t; flag mask\n\ttstr\t022h,msbtlo,msbthi,0,0d003h,07772h,07f53h,03f72h,064eah,0e180h,010h,02dh,035e9h\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0,0,0\t\t; (1 cycle)\n\ttstr\t0,0,0,0,0,0,0,-1,0,0,0,0,0\t\t; (16 cycles)\n\tdb\t0a3h,060h,08bh,047h\t\t\t; expected crc\n\ttmsg\t'ld (nnnn),hl..................'\n\n; ld (nnnn),sp (16 cycles)\nld167:\tdb\t0d7h\t\t; flag mask\n\ttstr\t0edh,073h,msbtlo,msbthi,0c0dch,0d1d6h,0ed5ah,0f356h,0afdah,06ca7h,044h,09fh,03f0ah\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0,0,0\t\t; (1 cycle)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0,0,-1\t\t; (16 cycles)\n\tdb\t016h,058h,05fh,0d7h\t\t\t; expected crc\n\ttmsg\t'ld (nnnn),sp..................'\n\n; ld (nnnn),<ix,iy> (64 cycles)\nld168:\tdb\t0d7h\t\t; flag mask\n\ttstr\t0ddh,022h,msbtlo,msbthi,06cc3h,00d91h,06900h,08ef8h,0e3d6h,0c3f7h,0c6h,0d9h,0c2dfh\n\ttstr\t020h,0,0,0,0,0,0,0,0,0,0,0,0\t\t; (2 cycles)\n\ttstr\t0,0,0,0,0,-1,-1,0,0,0,0,0,0\t\t; (32 cycles)\n\tdb\t0bah,010h,02ah,06bh\t\t\t; expected crc\n\ttmsg\t'ld (nnnn),<ix,iy>.............'\n\n; ld <bc,de,hl,sp>,nnnn (64 cycles)\nld16im:\tdb\t0d7h\t\t; flag mask\n\ttstr\t1,0,0,0,05c1ch,02d46h,08eb9h,06078h,074b1h,0b30eh,046h,0d1h,030cch\n\ttstr\t030h,0,0,0,0,0,0,0,0,0,0,0,0\t\t; (4 cycles)\n\ttstr\t0,0ffh,0ffh,0,0,0,0,0,0,0,0,0,0\t\t; (16 cycles)\n\tdb\t0deh,039h,019h,069h\t\t\t; expected crc\n\ttmsg\t'ld <bc,de,hl,sp>,nnnn.........'\n\n; ld <ix,iy>,nnnn (32 cycles)\nld16ix:\tdb\t0d7h\t\t; flag mask\n\ttstr\t0ddh,021h,0,0,087e8h,02006h,0bd12h,0b69bh,07253h,0a1e5h,051h,013h,0f1bdh\n\ttstr\t020h,0,0,0,0,0,0,0,0,0,0,0,0\t\t; (2 cycles)\n\ttstr\t0,0,0ffh,0ffh,0,0,0,0,0,0,0,0,0\t\t; (16 cycles)\n\tdb\t022h,07dh,0d5h,025h\t\t\t; expected crc\n\ttmsg\t'ld <ix,iy>,nnnn...............'\n\n; ld a,<(bc),(de)> (44 cycles)\nld8bd:\tdb\t0d7h\t\t; flag mask\n\ttstr\t00ah,0,0,0,0b3a8h,01d2ah,07f8eh,042ach,msbt,msbt,0c6h,0b1h,0ef8eh\n\ttstr\t010h,0,0,0,0,0,0,0,0,0,0,0,0\t\t; (2 cycles)\n\ttstr\t0,0,0,0,0ffh,0,0,0,0,0,0d7h,-1,0\t; (22 cycles)\n\tdb\t0b0h,081h,089h,035h\t\t\t; expected crc\n\ttmsg\t'ld a,<(bc),(de)>..............'\n\n; ld <b,c,d,e,h,l,(hl),a>,nn (64 cycles)\nld8im:\tdb\t0d7h\t\t; flag mask\n\ttstr\t6,0,0,0,0c407h,0f49dh,0d13dh,00339h,0de89h,07455h,053h,0c0h,05509h\n\ttstr\t038h,0,0,0,0,0,0,0,0,0,0,0,0\t\t; (8 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0,-1,0\t\t; (8 cycles)\n\tdb\t0f1h,0dah,0b5h,056h\t\t\t; expected crc\n\ttmsg\t'ld <b,c,d,e,h,l,(hl),a>,nn....'\n\n; ld (<ix,iy>+1),nn (32 cycles)\nld8imx:\tdb\t0d7h\t\t; flag mask\n\ttstr\t0ddh,036h,1,0,01b45h,msbt-1,msbt-1,0d5c1h,061c7h,0bdc4h,0c0h,085h,0cd16h\n\ttstr\t020h,0,0,0,0,0,0,0,0,0,0,0,0\t\t; (2 cycles)\n\ttstr\t0,0,0,-1,0,0,0,0,0,0,0,-1,0\t\t; (16 cycles)\n\tdb\t026h,0dbh,047h,07eh\t\t\t; expected crc\n\ttmsg\t'ld (<ix,iy>+1),nn.............'\n\n; ld <b,c,d,e>,(<ix,iy>+1) (512 cycles)\nld8ix1:\tdb\t0d7h\t\t; flag mask\n\ttstr\t0ddh,046h,1,0,0d016h,msbt-1,msbt-1,04260h,07f39h,00404h,097h,04ah,0d085h\n\ttstr\t020h,018h,0,0,0,1,1,0,0,0,0,0,0\t\t; (32 cycles)\n\ttstr\t0,0,0,0,-1,0,0,0,0,0,0,0,0\t\t; (16 cycles)\n\tdb\t0cch,011h,006h,0a8h\t\t\t; expected crc\n\ttmsg\t'ld <b,c,d,e>,(<ix,iy>+1)......'\n\n; ld <h,l>,(<ix,iy>+1) (256 cycles)\nld8ix2:\tdb\t0d7h\t\t; flag mask\n\ttstr\t0ddh,066h,1,0,084e0h,msbt-1,msbt-1,09c52h,0a799h,049b6h,093h,000h,0eeadh\n\ttstr\t020h,008h,0,0,0,1,1,0,0,0,0,0,0\t\t; (16 cycles)\n\ttstr\t0,0,0,0,-1,0,0,0,0,0,0,0,0\t\t; (16 cycles)\n\tdb\t0fah,02ah,04dh,003h\t\t\t; expected crc\n\ttmsg\t'ld <h,l>,(<ix,iy>+1)..........'\n\n; ld a,(<ix,iy>+1) (128 cycles)\nld8ix3:\tdb\t0d7h\t\t; flag mask\n\ttstr\t0ddh,07eh,1,0,0d8b6h,msbt-1,msbt-1,0c612h,0df07h,09cd0h,043h,0a6h,0a0e5h\n\ttstr\t020h,0,0,0,0,1,1,0,0,0,0,0,0\t\t; (8 cycles)\n\ttstr\t0,0,0,0,-1,0,0,0,0,0,0,0,0\t\t; (16 cycles)\n\tdb\t0a5h,0e9h,0ach,064h\t\t\t; expected crc\n\ttmsg\t'ld a,(<ix,iy>+1)..............'\n\n; ld <ixh,ixl,iyh,iyl>,nn (32 cycles)\nld8ixy:\tdb\t0d7h\t\t; flag mask\n\ttstr\t0ddh,026h,0,0,03c53h,04640h,0e179h,07711h,0c107h,01afah,081h,0adh,05d9bh\n\ttstr\t020h,8,0,0,0,0,0,0,0,0,0,0,0\t\t; (4 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0,-1,0\t\t; (8 cycles)\n\tdb\t024h,0e8h,082h,08bh\t\t\t; expected crc\n\ttmsg\t'ld <ixh,ixl,iyh,iyl>,nn.......'\n\n; ld <b,c,d,e,h,l,a>,<b,c,d,e,h,l,a> (3456 cycles)\nld8rr:\tdb\t0d7h\t\t; flag mask\n\ttstr\t040h,0,0,0,072a4h,0a024h,061ach,msbt,082c7h,0718fh,097h,08fh,0ef8eh\n\ttstr\t03fh,0,0,0,0,0,0,0,0,0,0,0,0\t\t; (64 cycles)\n\ttstr\t0,0,0,0,0ffh,0,0,0,-1,-1,0d7h,-1,0\t; (54 cycles)\n\tdb\t074h,04bh,001h,018h\t\t\t; expected crc\n\ttmsg\t'ld <bcdehla>,<bcdehla>........'\n\n; ld <b,c,d,e,ixy,a>,<b,c,d,e,ixy,a> (6912 cycles)\nld8rrx:\tdb\t0d7h\t\t; flag mask\n\ttstr\t0ddh,040h,0,0,0bcc5h,msbt,msbt,msbt,02fc2h,098c0h,083h,01fh,03bcdh\n\ttstr\t020h,03fh,0,0,0,0,0,0,0,0,0,0,0\t\t; (128 cycles)\n\ttstr\t0,0,0,0,0ffh,0,0,0,-1,-1,0d7h,-1,0\t; (54 cycles)\n\tdb\t047h,08bh,0a3h,06bh\t\t\t; expected crc\n\ttmsg\t'ld <bcdexya>,<bcdexya>........'\n\n; ld a,(nnnn) / ld (nnnn),a (44 cycles)\nlda:\tdb\t0d7h\t\t; flag mask\n\ttstr\t032h,msbtlo,msbthi,0,0fd68h,0f4ech,044a0h,0b543h,00653h,0cdbah,0d2h,04fh,01fd8h\n\ttstr\t008h,0,0,0,0,0,0,0,0,0,0,0,0\t\t; (2 cycle)\n\ttstr\t0,0,0,0,0ffh,0,0,0,0,0,0d7h,-1,0\t; (22 cycles)\n\tdb\t0c9h,026h,02dh,0e5h\t\t\t; expected crc\n\ttmsg\t'ld a,(nnnn) / ld (nnnn),a.....'\n\n; ldd<r> (1) (44 cycles)\nldd1:\tdb\t0d7h\t\t; flag mask\n\ttstr\t0edh,0a8h,0,0,09852h,068fah,066a1h,msbt+3,msbt+1,1,0c1h,068h,020b7h\n\ttstr\t0,010h,0,0,0,0,0,0,0,0,0,0,0\t\t; (2 cycles)\n\ttstr\t0,0,0,0,-1,0,0,0,0,0,0d7h,0,0\t\t; (22 cycles)\n\tdb\t094h,0f4h,027h,069h\t\t\t; expected crc\n\ttmsg\t'ldd<r> (1)....................'\n\n; ldd<r> (2) (44 cycles)\nldd2:\tdb\t0d7h\t\t; flag mask\n\ttstr\t0edh,0a8h,0,0,0f12eh,0eb2ah,0d5bah,msbt+3,msbt+1,2,047h,0ffh,0fbe4h\n\ttstr\t0,010h,0,0,0,0,0,0,0,0,0,0,0\t\t; (2 cycles)\n\ttstr\t0,0,0,0,-1,0,0,0,0,0,0d7h,0,0\t\t; (22 cycles)\n\tdb\t05ah,090h,07eh,0d4h\t\t\t; expected crc\n\ttmsg\t'ldd<r> (2)....................'\n\n; ldi<r> (1) (44 cycles)\nldi1:\tdb\t0d7h\t\t; flag mask\n\ttstr\t0edh,0a0h,0,0,0fe30h,003cdh,06058h,msbt+2,msbt,1,004h,060h,02688h\n\ttstr\t0,010h,0,0,0,0,0,0,0,0,0,0,0\t\t; (2 cycles)\n\ttstr\t0,0,0,0,-1,0,0,0,0,0,0d7h,0,0\t\t; (22 cycles)\n\tdb\t09ah,0bdh,0f6h,0b5h\t\t\t; expected crc\n\ttmsg\t'ldi<r> (1)....................'\n\n; ldi<r> (2) (44 cycles)\nldi2:\tdb\t0d7h\t\t; flag mask\n\ttstr\t0edh,0a0h,0,0,04aceh,0c26eh,0b188h,msbt+2,msbt,2,014h,02dh,0a39fh\n\ttstr\t0,010h,0,0,0,0,0,0,0,0,0,0,0\t\t; (2 cycles)\n\ttstr\t0,0,0,0,-1,0,0,0,0,0,0d7h,0,0\t\t; (22 cycles)\n\tdb\t0ebh,059h,089h,01bh\t\t\t; expected crc\n\ttmsg\t'ldi<r> (2)....................'\n\n; neg (16,384 cycles)\nnegop:\tdb\t0d7h\t\t; flag mask\n\ttstr\t0edh,044h,0,0,038a2h,05f6bh,0d934h,057e4h,0d2d6h,04642h,043h,05ah,009cch\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,-1,0\t\t; (16,384 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0,0,0\t\t; (1 cycle)\n\tdb\t06ah,03ch,03bh,0bdh\t\t\t; expected crc\n\ttmsg\t'neg...........................'\n\n; <rld,rrd> (7168 cycles)\nrldop:\tdb\t0d7h\t\t; flag mask\n\ttstr\t0edh,067h,0,0,091cbh,0c48bh,0fa62h,msbt,0e720h,0b479h,040h,006h,08ae2h\n\ttstr\t0,8,0,0,0ffh,0,0,0,0,0,0,0,0\t\t; (512 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,-1,0\t\t; (14 cycles)\n\tdb\t095h,05bh,0a3h,026h\t\t\t; expected crc\n\ttmsg\t'<rrd,rld>.....................'\n\n; <rlca,rrca,rla,rra> (6144 cycles)\nrot8080: db\t0d7h\t\t; flag mask\n\ttstr\t7,0,0,0,0cb92h,06d43h,00a90h,0c284h,00c53h,0f50eh,091h,0ebh,040fch\n\ttstr\t018h,0,0,0,0,0,0,0,0,0,0,-1,0\t\t; (1024 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0d7h,0,0\t\t; (6 cycles)\n\tdb\t025h,013h,030h,0aeh\t\t\t; expected crc\n\ttmsg\t'<rlca,rrca,rla,rra>...........'\n\n; shift/rotate (<ix,iy>+1) (416 cycles)\nrotxy:\tdb\t0d7h\t\t; flag mask\n\ttstr\t0ddh,0cbh,1,6,0ddafh,msbt-1,msbt-1,0ff3ch,0dbf6h,094f4h,082h,080h,061d9h\n\ttstr\t020h,0,0,038h,0,0,0,0,0,0,080h,0,0\t; (32 cycles)\n\ttstr\t0,0,0,0,0ffh,0,0,0,0,0,057h,0,0\t\t; (13 cycles)\n\tdb\t071h,03ah,0cdh,081h\t\t\t; expected crc\n\ttmsg\t'shf/rot (<ix,iy>+1)...........'\n\n; shift/rotate <b,c,d,e,h,l,(hl),a> (6784 cycles)\nrotz80:\tdb\t0d7h\t\t; flag mask\n\ttstr\t0cbh,0,0,0,0ccebh,05d4ah,0e007h,msbt,01395h,030eeh,043h,078h,03dadh\n\ttstr\t0,03fh,0,0,0,0,0,0,0,0,080h,0,0\t\t; (128 cycles)\n\ttstr\t0,0,0,0,0ffh,0,0,0,-1,-1,057h,-1,0\t; (53 cycles)\n\tdb\t0ebh,060h,04dh,058h\t\t\t; expected crc\n\ttmsg\t'shf/rot <b,c,d,e,h,l,(hl),a>..'\n\n; <set,res> n,<b,c,d,e,h,l,(hl),a> (7936 cycles)\nsrz80:\tdb\t0d7h\t\t; flag mask\n\ttstr\t0cbh,080h,0,0,02cd5h,097abh,039ffh,msbt,0d14bh,06ab2h,053h,027h,0b538h\n\ttstr\t0,07fh,0,0,0,0,0,0,0,0,0,0,0\t\t; (128 cycles)\n\ttstr\t0,0,0,0,0ffh,0,0,0,-1,-1,0d7h,-1,0\t; (62 cycles)\n\tdb\t08bh,057h,0f0h,008h\t\t\t; expected crc\n\ttmsg\t'<set,res> n,<bcdehl(hl)a>.....'\n\n; <set,res> n,(<ix,iy>+1) (1792 cycles)\nsrzx:\tdb\t0d7h\t\t; flag mask\n\ttstr\t0ddh,0cbh,1,086h,0fb44h,msbt-1,msbt-1,0ba09h,068beh,032d8h,010h,05eh,0a867h\n\ttstr\t020h,0,0,078h,0,0,0,0,0,0,0,0,0\t; (128 cycles)\n\ttstr\t0,0,0,0,0ffh,0,0,0,0,0,0d7h,0,0\t\t;(14 cycles)\n\tdb\t0cch,063h,0f9h,08ah\t\t\t; expected crc\n\ttmsg\t'<set,res> n,(<ix,iy>+1).......'\n\n; ld (<ix,iy>+1),<b,c,d,e> (1024 cycles)\nst8ix1:\tdb\t0d7h\t\t; flag mask\n\ttstr\t0ddh,070h,1,0,0270dh,msbt-1,msbt-1,0b73ah,0887bh,099eeh,086h,070h,0ca07h\n\ttstr\t020h,003h,0,0,0,1,1,0,0,0,0,0,0\t\t; (32 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,-1,-1,0,0,0\t\t; (32 cycles)\n\tdb\t004h,062h,06ah,0bfh\t\t\t; expected crc\n\ttmsg\t'ld (<ix,iy>+1),<b,c,d,e>......'\n\n; ld (<ix,iy>+1),<h,l> (256 cycles)\nst8ix2:\tdb\t0d7h\t\t; flag mask\n\ttstr\t0ddh,074h,1,0,0b664h,msbt-1,msbt-1,0e8ach,0b5f5h,0aafeh,012h,010h,09566h\n\ttstr\t020h,001h,0,0,0,1,1,0,0,0,0,0,0\t\t; (16 cycles)\n\ttstr\t0,0,0,0,0,0,0,-1,0,0,0,0,0\t\t; (32 cycles)\n\tdb\t06ah,01ah,088h,031h\t\t\t; expected crc\n\ttmsg\t'ld (<ix,iy>+1),<h,l>..........'\n\n; ld (<ix,iy>+1),a (64 cycles)\nst8ix3:\tdb\t0d7h\t\t; flag mask\n\ttstr\t0ddh,077h,1,0,067afh,msbt-1,msbt-1,04f13h,00644h,0bcd7h,050h,0ach,05fafh\n\ttstr\t020h,0,0,0,0,1,1,0,0,0,0,0,0\t\t; (8 cycles)\n\ttstr\t0,0,0,0,0,0,0,0,0,0,0,-1,0\t\t; (8 cycles)\n\tdb\t0cch,0beh,05ah,096h\t\t\t; expected crc\n\ttmsg\t'ld (<ix,iy>+1),a..............'\n\n; ld (<bc,de>),a (96 cycles)\nstabd:\tdb\t0d7h\t\t; flag mask\n\ttstr\t2,0,0,0,00c3bh,0b592h,06cffh,0959eh,msbt,msbt+1,0c1h,021h,0bde7h\n\ttstr\t018h,0,0,0,0,0,0,0,0,0,0,0,0\t\t; (4 cycles)\n\ttstr\t0,0,0,0,-1,0,0,0,0,0,0,-1,0\t\t; (24 cycles)\n\tdb\t07ah,04ch,011h,04fh\t\t\t; expected crc\n\ttmsg\t'ld (<bc,de>),a................'\n\n; start test pointed to by (hl)\nstt:\tpush\thl\n\tld\ta,(hl)\t\t; get pointer to test\n\tinc\thl\n\tld\th,(hl)\n\tld\tl,a\n\tld\ta,(hl)\t\t; flag mask\n\tld\t(flgmsk+1),a\n\tinc\thl\n\tpush\thl\n\tld\tde,20\n\tadd\thl,de\t\t; point to incmask\n\tld\tde,counter\n\tcall\tinitmask\n\tpop\thl\n\tpush\thl\n\tld\tde,20+20\n\tadd\thl,de\t\t; point to scanmask\n\tld\tde,shifter\n\tcall\tinitmask\n\tld\thl,shifter\n\tld\t(hl),1\t\t; first bit\n\tpop\thl\n\tpush\thl\n\tld\tde,iut\t\t; copy initial instruction under test\n\tld\tbc,4\n\tldir\n\tld\tde,msbt\t\t; copy initial machine state\n\tld\tbc,16\n\tldir\n\tld\tde,20+20+4\t; skip incmask, scanmask and expcrc\n\tadd\thl,de\n\tex\tde,hl\n\tld\tc,9\n\tcall\tbdos\t\t; show test name\n\tcall\tinitcrc\t\t; initialise crc\n; test loop\ntlp:\tld\ta,(iut)\n\tcp\t076h\t\t; pragmatically avoid halt intructions\n\tjp\tz,tlp2\n\tand\ta,0dfh\n\tcp\t0ddh\n\tjp\tnz,tlp1\n\tld\ta,(iut+1)\n\tcp\t076h\ntlp1:\tcall\tnz,test\t\t; execute the test instruction\ntlp2:\tcall\tcount\t\t; increment the counter\n\tcall\tnz,shift\t; shift the scan bit\n\tpop\thl\t\t; pointer to test case\n\tjp\tz,tlp3\t\t; done if shift returned NZ\n\tld\tde,20+20+20\n\tadd\thl,de\t\t; point to expected crc\n\tcall\tcmpcrc\n\tld\tde,okmsg\n\tjp\tz,tlpok\n\tld\tde,ermsg1\n\tld\tc,9\n\tcall\tbdos\n\tcall\tphex8\n\tld\tde,ermsg2\n\tld\tc,9\n\tcall\tbdos\n\tld\thl,crcval\n\tcall\tphex8\n\tld\tde,crlf\ntlpok:\tld\tc,9\n\tcall\tbdos\n\tpop\thl\n\tinc\thl\n\tinc\thl\n\tret\n\ntlp3:\tpush\thl\n\tld\ta,1\t\t; initialise count and shift scanners\n\tld\t(cntbit),a\n\tld\t(shfbit),a\n\tld\thl,counter\n\tld\t(cntbyt),hl\n\tld\thl,shifter\n\tld\t(shfbyt),hl\n\n\tld\tb,4\t\t; bytes in iut field\n\tpop\thl\t\t; pointer to test case\n\tpush\thl\n\tld\tde,iut\n\tcall\tsetup\t\t; setup iut\n\tld\tb,16\t\t; bytes in machine state\n\tld\tde,msbt\n\tcall\tsetup\t\t; setup machine state\n\tjp\ttlp\n\n; setup a field of the test case\n; b  = number of bytes\n; hl = pointer to base case\n; de = destination\nsetup:\tcall\tsubyte\n\tinc\thl\n\tdec\tb\n\tjp\tnz,setup\n\tret\n\nsubyte:\tpush\tbc\n\tpush\tde\n\tpush\thl\n\tld\tc,(hl)\t\t; get base byte\n\tld\tde,20\n\tadd\thl,de\t\t; point to incmask\n\tld\ta,(hl)\n\tcp\t0\n\tjp\tz,subshf\n\tld\tb,8\t\t; 8 bits\nsubclp:\trrca\n\tpush\taf\n\tld\ta,0\n\tcall\tc,nxtcbit\t; get next counter bit if mask bit was set\n\txor\tc\t\t; flip bit if counter bit was set\n\trrca\n\tld\tc,a\n\tpop\taf\n\tdec\tb\n\tjp\tnz,subclp\n\tld\tb,8\nsubshf:\tld\tde,20\n\tadd\thl,de\t\t; point to shift mask\n\tld\ta,(hl)\n\tcp\t0\n\tjp\tz,substr\n\tld\tb,8\t\t; 8 bits\nsbshf1:\trrca\n\tpush\taf\n\tld\ta,0\n\tcall\tc,nxtsbit\t; get next shifter bit if mask bit was set\n\txor\tc\t\t; flip bit if shifter bit was set\n\trrca\n\tld\tc,a\n\tpop\taf\n\tdec\tb\n\tjp\tnz,sbshf1\nsubstr:\tpop\thl\n\tpop\tde\n\tld\ta,c\n\tld\t(de),a\t\t; mangled byte to destination\n\tinc\tde\n\tpop\tbc\n\tret\n\n; get next counter bit in low bit of a\ncntbit:\tds\t1\ncntbyt:\tds\t2\n\nnxtcbit: push\tbc\n\tpush\thl\n\tld\thl,(cntbyt)\n\tld\tb,(hl)\n\tld\thl,cntbit\n\tld\ta,(hl)\n\tld\tc,a\n\trlca\n\tld\t(hl),a\n\tcp\ta,1\n\tjp\tnz,ncb1\n\tld\thl,(cntbyt)\n\tinc\thl\n\tld\t(cntbyt),hl\nncb1:\tld\ta,b\n\tand\tc\n\tpop\thl\n\tpop\tbc\n\tret\tz\n\tld\ta,1\n\tret\n\t\n; get next shifter bit in low bit of a\nshfbit:\tds\t1\nshfbyt:\tds\t2\n\nnxtsbit: push\tbc\n\tpush\thl\n\tld\thl,(shfbyt)\n\tld\tb,(hl)\n\tld\thl,shfbit\n\tld\ta,(hl)\n\tld\tc,a\n\trlca\n\tld\t(hl),a\n\tcp\ta,1\n\tjp\tnz,nsb1\n\tld\thl,(shfbyt)\n\tinc\thl\n\tld\t(shfbyt),hl\nnsb1:\tld\ta,b\n\tand\tc\n\tpop\thl\n\tpop\tbc\n\tret\tz\n\tld\ta,1\n\tret\n\t\n\n; clear memory at hl, bc bytes\nclrmem:\tpush\taf\n\tpush\tbc\n\tpush\tde\n\tpush\thl\n\tld\t(hl),0\n\tld\td,h\n\tld\te,l\n\tinc\tde\n\tdec\tbc\n\tldir\n\tpop\thl\n\tpop\tde\n\tpop\tbc\n\tpop\taf\n\tret\n\n; initialise counter or shifter\n; de = pointer to work area for counter or shifter\n; hl = pointer to mask\ninitmask:\n\tpush\tde\n\tex\tde,hl\n\tld\tbc,20+20\n\tcall\tclrmem\t\t; clear work area\n\tex\tde,hl\n\tld\tb,20\t\t; byte counter\n\tld\tc,1\t\t; first bit\n\tld\td,0\t\t; bit counter\nimlp:\tld\te,(hl)\nimlp1:\tld\ta,e\n\tand\ta,c\n\tjp\tz,imlp2\n\tinc\td\nimlp2:\tld\ta,c\n\trlca\n\tld\tc,a\n\tcp\ta,1\n\tjp\tnz,imlp1\n\tinc\thl\n\tdec\tb\n\tjp\tnz,imlp\n; got number of 1-bits in mask in reg d\n\tld\ta,d\n\tand\t0f8h\n\trrca\n\trrca\n\trrca\t\t\t; divide by 8 (get byte offset)\n\tld\tl,a\n\tld\th,0\n\tld\ta,d\n\tand\ta,7\t\t; bit offset\n\tinc\ta\n\tld\tb,a\n\tld\ta,080h\nimlp3:\trlca\n\tdec\tb\n\tjp\tnz,imlp3\n\tpop\tde\n\tadd\thl,de\n\tld\tde,20\n\tadd\thl,de\n\tld\t(hl),a\n\tret\n\n; multi-byte counter\ncount:\tpush\tbc\n\tpush\tde\n\tpush\thl\n\tld\thl,counter\t; 20 byte counter starts here\n\tld\tde,20\t\t; somewhere in here is the stop bit\n\tex\tde,hl\n\tadd\thl,de\n\tex\tde,hl\ncntlp:\tinc\t(hl)\n\tld\ta,(hl)\n\tcp\t0\n\tjp\tz,cntlp1\t; overflow to next byte\n\tld\tb,a\n\tld\ta,(de)\n\tand\ta,b\t\t; test for terminal value\n\tjp\tz,cntend\n\tld\t(hl),0\t\t; reset to zero\ncntend:\tpop\tbc\n\tpop\tde\n\tpop\thl\n\tret\n\ncntlp1:\tinc\thl\n\tinc\tde\n\tjp\tcntlp\n\t\n\n; multi-byte shifter\nshift:\tpush\tbc\n\tpush\tde\n\tpush\thl\n\tld\thl,shifter\t; 20 byte shift register starts here\n\tld\tde,20\t\t; somewhere in here is the stop bit\n\tex\tde,hl\n\tadd\thl,de\n\tex\tde,hl\nshflp:\tld\ta,(hl)\n\tor\ta\n\tjp\tz,shflp1\n\tld\tb,a\n\tld\ta,(de)\n\tand\tb\n\tjp\tnz,shlpe\n\tld\ta,b\n\trlca\n\tcp\ta,1\n\tjp\tnz,shflp2\n\tld\t(hl),0\n\tinc\thl\n\tinc\tde\nshflp2:\tld\t(hl),a\n\txor\ta\t\t; set Z\nshlpe:\tpop\thl\n\tpop\tde\n\tpop\tbc\n\tret\nshflp1:\tinc\thl\n\tinc\tde\n\tjp\tshflp\n\ncounter: ds\t2*20\nshifter: ds\t2*20\n\n; test harness\ntest:\tpush\taf\n\tpush\tbc\n\tpush\tde\n\tpush\thl\n      if\t0\n\tld\tde,crlf\n\tld\tc,9\n\tcall\tbdos\n\tld\thl,iut\n\tld\tb,4\n\tcall\thexstr\n\tld\te,' '\n\tld\tc,2\n\tcall\tbdos\n\tld\tb,16\n\tld\thl,msbt\n\tcall\thexstr\n      endif\t\n\tdi\t\t\t; disable interrupts\n\tld\t(spsav),sp\t; save stack pointer\n\tld\tsp,msbt+2\t; point to test-case machine state\n\tpop\tiy\t\t; and load all regs\n\tpop\tix\n\tpop\thl\n\tpop\tde\n\tpop\tbc\n\tpop\taf\n\tld\tsp,(spbt)\niut:\tds\t4\t\t; max 4 byte instruction under test\n\tld\t(spat),sp\t; save stack pointer\n\tld\tsp,spat\n\tpush\taf\t\t; save other registers\n\tpush\tbc\n\tpush\tde\n\tpush\thl\n\tpush\tix\n\tpush\tiy\n\tld\tsp,(spsav)\t; restore stack pointer\n\tei\t\t\t; enable interrupts\n\tld\thl,(msbt)\t; copy memory operand\n\tld\t(msat),hl\n\tld\thl,flgsat\t; flags after test\n\tld\ta,(hl)\nflgmsk:\tand\ta,0d7h\t\t; mask-out irrelevant bits (self-modified code!)\n\tld\t(hl),a\n\tld\tb,16\t\t; total of 16 bytes of state\n\tld\tde,msat\n\tld\thl,crcval\ntcrc:\tld\ta,(de)\n\tinc\tde\n\tcall\tupdcrc\t\t; accumulate crc of this test case\n\tdec\tb\n\tjp\tnz,tcrc\n      if\t0\n\tld\te,' '\n\tld\tc,2\n\tcall\tbdos\n\tld\thl,crcval\n\tcall\tphex8\n\tld\tde,crlf\n\tld\tc,9\n\tcall\tbdos\n\tld\thl,msat\n\tld\tb,16\n\tcall\thexstr\n\tld\tde,crlf\n\tld\tc,9\n\tcall\tbdos\n      endif\n\tpop\thl\n\tpop\tde\n\tpop\tbc\n\tpop\taf\n\tret\n\n; machine state after test\nmsat:\tds\t14\t; memop,iy,ix,hl,de,bc,af\nspat:\tds\t2\t; stack pointer after test\n; ZMAC/MAXAM doesn't like ':' after label with EQUs\nflgsat\tequ\tspat-2\t; flags\n\nspsav:\tds\t2\t; saved stack pointer\n\n; display hex string (pointer in hl, byte count in b)\nhexstr:\tld\ta,(hl)\n\tcall\tphex2\n\tinc\thl\n\tdec\tb\n\tjp\tnz,hexstr\n\tret\n\n; display hex\n; display the big-endian 32-bit value pointed to by hl\nphex8:\tpush\taf\n\tpush\tbc\n\tpush\thl\n\tld\tb,4\nph8lp:\tld\ta,(hl)\n\tcall\tphex2\n\tinc\thl\n\tdec\tb\n\tjp\tnz,ph8lp\n\tpop\thl\n\tpop\tbc\n\tpop\taf\n\tret\n\n; display byte in a\nphex2:\tpush\taf\n\trrca\n\trrca\n\trrca\n\trrca\n\tcall\tphex1\n\tpop\taf\n; fall through\t\n\n; display low nibble in a\nphex1:\tpush\taf\n\tpush\tbc\n\tpush\tde\n\tpush\thl\n\tand\ta,0fh\n\tcp\ta,10\n\tjp\tc,ph11\n\tadd\ta,'a'-'9'-1\nph11:\tadd\ta,'0'\n\tld\te,a\n\tld\tc,2\n\tcall\tbdos\n\tpop\thl\n\tpop\tde\n\tpop\tbc\n\tpop\taf\n\tret\n\nbdos\tpush\taf\n\tpush\tbc\n\tpush\tde\n\tpush\thl\n\tcall\t5\n\tpop\thl\n\tpop\tde\n\tpop\tbc\n\tpop\taf\n\tret\n\nmsg1:\tdb\t10,13,10,13,'Z80doc instruction exerciser',10,13,'$'\nmsg2:\tdb\t'Tests complete$'\nokmsg:\tdb\t'  OK',10,13,'$'\nermsg1:\tdb\t'  ERROR **** crc expected:$'\nermsg2:\tdb\t' found:$'\ncrlf:\tdb\t10,13,'$'\n\n; compare crc\n; hl points to value to compare to crcval\ncmpcrc:\tpush\tbc\n\tpush\tde\n\tpush\thl\n\tld\tde,crcval\n\tld\tb,4\ncclp:\tld\ta,(de)\n\tcp\ta,(hl)\n\tjp\tnz,cce\n\tinc\thl\n\tinc\tde\n\tdec\tb\n\tjp\tnz,cclp\ncce:\tpop\thl\n\tpop\tde\n\tpop\tbc\n\tret\n\n; 32-bit crc routine\n; entry: a contains next byte, hl points to crc\n; exit:  crc updated\nupdcrc:\tpush\taf\n\tpush\tbc\n\tpush\tde\n\tpush\thl\n\tpush\thl\n\tld\tde,3\n\tadd\thl,de\t; point to low byte of old crc\n\txor\ta,(hl)\t; xor with new byte\n\tld\tl,a\n\tld\th,0\n\tadd\thl,hl\t; use result as index into table of 4 byte entries\n\tadd\thl,hl\n\tex\tde,hl\n\tld\thl,crctab\n\tadd\thl,de\t; point to selected entry in crctab\n\tex\tde,hl\n\tpop\thl\n\tld\tbc,4\t; c = byte count, b = accumulator\ncrclp:\tld\ta,(de)\n\txor\ta,b\n\tld\tb,(hl)\n\tld\t(hl),a\n\tinc\tde\n\tinc\thl\n\tdec\tc\n\tjp\tnz,crclp\n      if\t0\n\tld\thl,crcval\n\tcall\tphex8\n\tld\tde,crlf\n\tld\tc,9\n\tcall\tbdos\n      endif\n\tpop\thl\n\tpop\tde\n\tpop\tbc\n\tpop\taf\n\tret\n\ninitcrc:push\taf\n\tpush\tbc\n\tpush\thl\n\tld\thl,crcval\n\tld\ta,0ffh\n\tld\tb,4\nicrclp:\tld\t(hl),a\n\tinc\thl\n\tdec\tb\n\tjp\tnz,icrclp\n\tpop\thl\n\tpop\tbc\n\tpop\taf\n\tret\n\ncrcval\tds\t4\n\ncrctab:\tdb\t000h,000h,000h,000h\n\tdb\t077h,007h,030h,096h\n\tdb\t0eeh,00eh,061h,02ch\n\tdb\t099h,009h,051h,0bah\n\tdb\t007h,06dh,0c4h,019h\n\tdb\t070h,06ah,0f4h,08fh\n\tdb\t0e9h,063h,0a5h,035h\n\tdb\t09eh,064h,095h,0a3h\n\tdb\t00eh,0dbh,088h,032h\n\tdb\t079h,0dch,0b8h,0a4h\n\tdb\t0e0h,0d5h,0e9h,01eh\n\tdb\t097h,0d2h,0d9h,088h\n\tdb\t009h,0b6h,04ch,02bh\n\tdb\t07eh,0b1h,07ch,0bdh\n\tdb\t0e7h,0b8h,02dh,007h\n\tdb\t090h,0bfh,01dh,091h\n\tdb\t01dh,0b7h,010h,064h\n\tdb\t06ah,0b0h,020h,0f2h\n\tdb\t0f3h,0b9h,071h,048h\n\tdb\t084h,0beh,041h,0deh\n\tdb\t01ah,0dah,0d4h,07dh\n\tdb\t06dh,0ddh,0e4h,0ebh\n\tdb\t0f4h,0d4h,0b5h,051h\n\tdb\t083h,0d3h,085h,0c7h\n\tdb\t013h,06ch,098h,056h\n\tdb\t064h,06bh,0a8h,0c0h\n\tdb\t0fdh,062h,0f9h,07ah\n\tdb\t08ah,065h,0c9h,0ech\n\tdb\t014h,001h,05ch,04fh\n\tdb\t063h,006h,06ch,0d9h\n\tdb\t0fah,00fh,03dh,063h\n\tdb\t08dh,008h,00dh,0f5h\n\tdb\t03bh,06eh,020h,0c8h\n\tdb\t04ch,069h,010h,05eh\n\tdb\t0d5h,060h,041h,0e4h\n\tdb\t0a2h,067h,071h,072h\n\tdb\t03ch,003h,0e4h,0d1h\n\tdb\t04bh,004h,0d4h,047h\n\tdb\t0d2h,00dh,085h,0fdh\n\tdb\t0a5h,00ah,0b5h,06bh\n\tdb\t035h,0b5h,0a8h,0fah\n\tdb\t042h,0b2h,098h,06ch\n\tdb\t0dbh,0bbh,0c9h,0d6h\n\tdb\t0ach,0bch,0f9h,040h\n\tdb\t032h,0d8h,06ch,0e3h\n\tdb\t045h,0dfh,05ch,075h\n\tdb\t0dch,0d6h,00dh,0cfh\n\tdb\t0abh,0d1h,03dh,059h\n\tdb\t026h,0d9h,030h,0ach\n\tdb\t051h,0deh,000h,03ah\n\tdb\t0c8h,0d7h,051h,080h\n\tdb\t0bfh,0d0h,061h,016h\n\tdb\t021h,0b4h,0f4h,0b5h\n\tdb\t056h,0b3h,0c4h,023h\n\tdb\t0cfh,0bah,095h,099h\n\tdb\t0b8h,0bdh,0a5h,00fh\n\tdb\t028h,002h,0b8h,09eh\n\tdb\t05fh,005h,088h,008h\n\tdb\t0c6h,00ch,0d9h,0b2h\n\tdb\t0b1h,00bh,0e9h,024h\n\tdb\t02fh,06fh,07ch,087h\n\tdb\t058h,068h,04ch,011h\n\tdb\t0c1h,061h,01dh,0abh\n\tdb\t0b6h,066h,02dh,03dh\n\tdb\t076h,0dch,041h,090h\n\tdb\t001h,0dbh,071h,006h\n\tdb\t098h,0d2h,020h,0bch\n\tdb\t0efh,0d5h,010h,02ah\n\tdb\t071h,0b1h,085h,089h\n\tdb\t006h,0b6h,0b5h,01fh\n\tdb\t09fh,0bfh,0e4h,0a5h\n\tdb\t0e8h,0b8h,0d4h,033h\n\tdb\t078h,007h,0c9h,0a2h\n\tdb\t00fh,000h,0f9h,034h\n\tdb\t096h,009h,0a8h,08eh\n\tdb\t0e1h,00eh,098h,018h\n\tdb\t07fh,06ah,00dh,0bbh\n\tdb\t008h,06dh,03dh,02dh\n\tdb\t091h,064h,06ch,097h\n\tdb\t0e6h,063h,05ch,001h\n\tdb\t06bh,06bh,051h,0f4h\n\tdb\t01ch,06ch,061h,062h\n\tdb\t085h,065h,030h,0d8h\n\tdb\t0f2h,062h,000h,04eh\n\tdb\t06ch,006h,095h,0edh\n\tdb\t01bh,001h,0a5h,07bh\n\tdb\t082h,008h,0f4h,0c1h\n\tdb\t0f5h,00fh,0c4h,057h\n\tdb\t065h,0b0h,0d9h,0c6h\n\tdb\t012h,0b7h,0e9h,050h\n\tdb\t08bh,0beh,0b8h,0eah\n\tdb\t0fch,0b9h,088h,07ch\n\tdb\t062h,0ddh,01dh,0dfh\n\tdb\t015h,0dah,02dh,049h\n\tdb\t08ch,0d3h,07ch,0f3h\n\tdb\t0fbh,0d4h,04ch,065h\n\tdb\t04dh,0b2h,061h,058h\n\tdb\t03ah,0b5h,051h,0ceh\n\tdb\t0a3h,0bch,000h,074h\n\tdb\t0d4h,0bbh,030h,0e2h\n\tdb\t04ah,0dfh,0a5h,041h\n\tdb\t03dh,0d8h,095h,0d7h\n\tdb\t0a4h,0d1h,0c4h,06dh\n\tdb\t0d3h,0d6h,0f4h,0fbh\n\tdb\t043h,069h,0e9h,06ah\n\tdb\t034h,06eh,0d9h,0fch\n\tdb\t0adh,067h,088h,046h\n\tdb\t0dah,060h,0b8h,0d0h\n\tdb\t044h,004h,02dh,073h\n\tdb\t033h,003h,01dh,0e5h\n\tdb\t0aah,00ah,04ch,05fh\n\tdb\t0ddh,00dh,07ch,0c9h\n\tdb\t050h,005h,071h,03ch\n\tdb\t027h,002h,041h,0aah\n\tdb\t0beh,00bh,010h,010h\n\tdb\t0c9h,00ch,020h,086h\n\tdb\t057h,068h,0b5h,025h\n\tdb\t020h,06fh,085h,0b3h\n\tdb\t0b9h,066h,0d4h,009h\n\tdb\t0ceh,061h,0e4h,09fh\n\tdb\t05eh,0deh,0f9h,00eh\n\tdb\t029h,0d9h,0c9h,098h\n\tdb\t0b0h,0d0h,098h,022h\n\tdb\t0c7h,0d7h,0a8h,0b4h\n\tdb\t059h,0b3h,03dh,017h\n\tdb\t02eh,0b4h,00dh,081h\n\tdb\t0b7h,0bdh,05ch,03bh\n\tdb\t0c0h,0bah,06ch,0adh\n\tdb\t0edh,0b8h,083h,020h\n\tdb\t09ah,0bfh,0b3h,0b6h\n\tdb\t003h,0b6h,0e2h,00ch\n\tdb\t074h,0b1h,0d2h,09ah\n\tdb\t0eah,0d5h,047h,039h\n\tdb\t09dh,0d2h,077h,0afh\n\tdb\t004h,0dbh,026h,015h\n\tdb\t073h,0dch,016h,083h\n\tdb\t0e3h,063h,00bh,012h\n\tdb\t094h,064h,03bh,084h\n\tdb\t00dh,06dh,06ah,03eh\n\tdb\t07ah,06ah,05ah,0a8h\n\tdb\t0e4h,00eh,0cfh,00bh\n\tdb\t093h,009h,0ffh,09dh\n\tdb\t00ah,000h,0aeh,027h\n\tdb\t07dh,007h,09eh,0b1h\n\tdb\t0f0h,00fh,093h,044h\n\tdb\t087h,008h,0a3h,0d2h\n\tdb\t01eh,001h,0f2h,068h\n\tdb\t069h,006h,0c2h,0feh\n\tdb\t0f7h,062h,057h,05dh\n\tdb\t080h,065h,067h,0cbh\n\tdb\t019h,06ch,036h,071h\n\tdb\t06eh,06bh,006h,0e7h\n\tdb\t0feh,0d4h,01bh,076h\n\tdb\t089h,0d3h,02bh,0e0h\n\tdb\t010h,0dah,07ah,05ah\n\tdb\t067h,0ddh,04ah,0cch\n\tdb\t0f9h,0b9h,0dfh,06fh\n\tdb\t08eh,0beh,0efh,0f9h\n\tdb\t017h,0b7h,0beh,043h\n\tdb\t060h,0b0h,08eh,0d5h\n\tdb\t0d6h,0d6h,0a3h,0e8h\n\tdb\t0a1h,0d1h,093h,07eh\n\tdb\t038h,0d8h,0c2h,0c4h\n\tdb\t04fh,0dfh,0f2h,052h\n\tdb\t0d1h,0bbh,067h,0f1h\n\tdb\t0a6h,0bch,057h,067h\n\tdb\t03fh,0b5h,006h,0ddh\n\tdb\t048h,0b2h,036h,04bh\n\tdb\t0d8h,00dh,02bh,0dah\n\tdb\t0afh,00ah,01bh,04ch\n\tdb\t036h,003h,04ah,0f6h\n\tdb\t041h,004h,07ah,060h\n\tdb\t0dfh,060h,0efh,0c3h\n\tdb\t0a8h,067h,0dfh,055h\n\tdb\t031h,06eh,08eh,0efh\n\tdb\t046h,069h,0beh,079h\n\tdb\t0cbh,061h,0b3h,08ch\n\tdb\t0bch,066h,083h,01ah\n\tdb\t025h,06fh,0d2h,0a0h\n\tdb\t052h,068h,0e2h,036h\n\tdb\t0cch,00ch,077h,095h\n\tdb\t0bbh,00bh,047h,003h\n\tdb\t022h,002h,016h,0b9h\n\tdb\t055h,005h,026h,02fh\n\tdb\t0c5h,0bah,03bh,0beh\n\tdb\t0b2h,0bdh,00bh,028h\n\tdb\t02bh,0b4h,05ah,092h\n\tdb\t05ch,0b3h,06ah,004h\n\tdb\t0c2h,0d7h,0ffh,0a7h\n\tdb\t0b5h,0d0h,0cfh,031h\n\tdb\t02ch,0d9h,09eh,08bh\n\tdb\t05bh,0deh,0aeh,01dh\n\tdb\t09bh,064h,0c2h,0b0h\n\tdb\t0ech,063h,0f2h,026h\n\tdb\t075h,06ah,0a3h,09ch\n\tdb\t002h,06dh,093h,00ah\n\tdb\t09ch,009h,006h,0a9h\n\tdb\t0ebh,00eh,036h,03fh\n\tdb\t072h,007h,067h,085h\n\tdb\t005h,000h,057h,013h\n\tdb\t095h,0bfh,04ah,082h\n\tdb\t0e2h,0b8h,07ah,014h\n\tdb\t07bh,0b1h,02bh,0aeh\n\tdb\t00ch,0b6h,01bh,038h\n\tdb\t092h,0d2h,08eh,09bh\n\tdb\t0e5h,0d5h,0beh,00dh\n\tdb\t07ch,0dch,0efh,0b7h\n\tdb\t00bh,0dbh,0dfh,021h\n\tdb\t086h,0d3h,0d2h,0d4h\n\tdb\t0f1h,0d4h,0e2h,042h\n\tdb\t068h,0ddh,0b3h,0f8h\n\tdb\t01fh,0dah,083h,06eh\n\tdb\t081h,0beh,016h,0cdh\n\tdb\t0f6h,0b9h,026h,05bh\n\tdb\t06fh,0b0h,077h,0e1h\n\tdb\t018h,0b7h,047h,077h\n\tdb\t088h,008h,05ah,0e6h\n\tdb\t0ffh,00fh,06ah,070h\n\tdb\t066h,006h,03bh,0cah\n\tdb\t011h,001h,00bh,05ch\n\tdb\t08fh,065h,09eh,0ffh\n\tdb\t0f8h,062h,0aeh,069h\n\tdb\t061h,06bh,0ffh,0d3h\n\tdb\t016h,06ch,0cfh,045h\n\tdb\t0a0h,00ah,0e2h,078h\n\tdb\t0d7h,00dh,0d2h,0eeh\n\tdb\t04eh,004h,083h,054h\n\tdb\t039h,003h,0b3h,0c2h\n\tdb\t0a7h,067h,026h,061h\n\tdb\t0d0h,060h,016h,0f7h\n\tdb\t049h,069h,047h,04dh\n\tdb\t03eh,06eh,077h,0dbh\n\tdb\t0aeh,0d1h,06ah,04ah\n\tdb\t0d9h,0d6h,05ah,0dch\n\tdb\t040h,0dfh,00bh,066h\n\tdb\t037h,0d8h,03bh,0f0h\n\tdb\t0a9h,0bch,0aeh,053h\n\tdb\t0deh,0bbh,09eh,0c5h\n\tdb\t047h,0b2h,0cfh,07fh\n\tdb\t030h,0b5h,0ffh,0e9h\n\tdb\t0bdh,0bdh,0f2h,01ch\n\tdb\t0cah,0bah,0c2h,08ah\n\tdb\t053h,0b3h,093h,030h\n\tdb\t024h,0b4h,0a3h,0a6h\n\tdb\t0bah,0d0h,036h,005h\n\tdb\t0cdh,0d7h,006h,093h\n\tdb\t054h,0deh,057h,029h\n\tdb\t023h,0d9h,067h,0bfh\n\tdb\t0b3h,066h,07ah,02eh\n\tdb\t0c4h,061h,04ah,0b8h\n\tdb\t05dh,068h,01bh,002h\n\tdb\t02ah,06fh,02bh,094h\n\tdb\t0b4h,00bh,0beh,037h\n\tdb\t0c3h,00ch,08eh,0a1h\n\tdb\t05ah,005h,0dfh,01bh\n\tdb\t02dh,002h,0efh,08dh\n\n"
  },
  {
    "path": "tools/zmac/zmac.html",
    "content": "<H3>Overview of zmac</H3>\nzmac is a Z-80 macro cross-assembler. It has all the features you'd\nexpect. It assembles the specified input file (with a '.z' extension\nif there is no pre-existing extension and the file as given doesn't\nexist) and produces program output in many different <A HREF=\"#format\">formats</A>.\nIt also produces a nicely-formatted\nlisting of the machine code and cycle counts alongside the source\nin a \".lst\" file.\n<P>\nTo reduce clutter and command line option usage, by default all zmac output is put\ninto an (auto-created) <TT>zout</TT> subdirectory.  For <TT>file.z</TT> the listing\nwill be in <TT>zout/file.lst</TT>, the TRS-80 executable format in <TT>zout/file.cmd</TT>\nand so on.  For more friendly usage in make files and integrated development\nenvironments the <TT>-o</TT>, <TT>--oo</TT>, <TT>--xo</TT> and <TT>--xd</TT> options may be used to select\nsepcific output file formats and where they are written.\n<P>\n<A HREF=\"#undoc\">Undocumented</A> Z-80 instructions are supported as well as 8080 code.\n<P>\nzmac strives to be a powerful assembler with expressions familiar to C\nprogrammers while providing good backward compatibility with original\nassemblers such as Edtasm, MRAS and Macro-80.\n<HR>\n<H3>Usage</H3>\nzmac\n[ --help ]\n[ --version ]\n[ --dep ]\n[ --mras ]\n[ --od dir ]\n[ --oo sfx1,sfx2 ]\n[ --xo sfx1,sfx2 ]\n[ --rel ]\n[ --rel7 ]\n[ --doc ]\n[ --zmac ]\n[ -8bcefghijJlLmnopstz ]\n[ filename[.z] ]\n<P>\n<H3>Options</H3>\n<P>\n<TABLE>\n<TR><TD VALIGN=\"TOP\"><PRE>--help </PRE></TD><TD>Display a list of options and a terse description of what the options do. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>--version </PRE></TD><TD>Print zmac version name. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>--mras </PRE></TD><TD>MRAS compatibility mode.  Any <TT>?</TT> in a label will be expanded to the current module identifier as set by <TT>*mod</TT>. Operator <A HREF=\"#mrasord\">precedence</A> and results are changed. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>--od dir </PRE></TD><TD>Place output files in <TT>dir</TT> instead of the default \"zout\" subdirectory. Creates <TT>dir</TT> if necessary. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>--oo hex,cmd </PRE></TD><TD>Output only the the file types by suffix.  Multiple --oo arguments may be used.  \"--oo lst,cas\" is equivalent to \"--oo lst --oo cas\". See \"Output Formats\" for a list of output types by <A HREF=\"#format\">suffix</A>. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>--xo tap,wav </PRE></TD><TD>Do not output the file type types listed by suffix.  </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>--rel </PRE></TD><TD>Output \".rel\" (relocatable object file) format only.  Exported symbols are truncated to length 6. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>--rel7 </PRE></TD><TD>Output \".rel\" (relocatable object file) format only.  Exported symbols are truncated to length 7. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>--zmac </PRE></TD><TD>zmac compatibility mode.  <TT>defl</TT> labels are undefined after each pass. Quotes and double quotes are stripped from macro arguments before expansion. <TT>$</TT> is ignored in identifiers allowing <TT>foo$bar</TT> to construct identifiers in macro expansions.  Use <TT>`</TT> (backquote) instead in normal mode.  Labels starting with <TT>\".\"</TT> are temporary and are reset whenever a non-temporary label is defined (thus they may be reused).  Labels starting with <TT>\"_\"</TT> are local to their file thus avoid multiple definition when brought in with <TT>include</TT>. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>--dep </PRE></TD><TD>Print all files read by <TT>include</TT>, <TT>incbin</TT> and <TT>import</TT>. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>--doc </PRE></TD><TD>Print this documentation in HTML format to standard output. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>-Pk=number </PRE></TD><TD>Set <TT>@@k</TT> to the given numeric value before assembly.  Up to 10 parameters can be set from 0 though 9.  <TT>-Pk</TT> is shorthand for <TT>-Pk=-1</TT>. For example, <TT>P4=$123</TT> effectively puts <TT>@@4 equ $123</TT> at the top of the first file. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>-8 </PRE></TD><TD>Accept 8080 mnemonics preferentially and use 8080 instruction timings. Equivalent to <TT>.8080</TT> pseudo-op. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>-b </PRE></TD><TD>Don't generate any machine code output at all. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>-c </PRE></TD><TD>Don't display cycle counts in the listing. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>-e </PRE></TD><TD>Omit the \"error report\" section in the listing. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>-f </PRE></TD><TD>List instructions not assembled due to \"<TT>if</TT>\" expressions being false. (Normally these are not shown in the listing.) </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>-g </PRE></TD><TD>List only the first line of equivalent hex for a source line. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>-h </PRE></TD><TD>Display a list of options and a terse description of what the options do. (same as --help) </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>-i </PRE></TD><TD>Don't list files included with <TT>include</TT>, <TT>read</TT> or <TT>import</TT>. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>-I dir </PRE></TD><TD>Add <TT>dir</TT> to the end of the include file search path. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>-j </PRE></TD><TD>Promote relative jumps and <TT>DJNZ</TT> to absolute equivalents as needed. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>-J </PRE></TD><TD>Error if an absolute jump could be replaced with a relative jump. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>-l </PRE></TD><TD>List to standard output. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>-L </PRE></TD><TD>Generate listing no matter what. Overrides any conflicting options. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>-m </PRE></TD><TD>List macro expansions. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>-n </PRE></TD><TD>Omit line numbers from listing. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>-o filename.cmd </PRE></TD><TD>Output only the named file.  Multiple \"-o\" options can be used to name a set of different files. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>-p </PRE></TD><TD>Use a few linefeeds for page break in listing rather than ^L. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>-P </PRE></TD><TD>Output listing for a printer with headers, multiple symbols per column, etc. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>-s </PRE></TD><TD>Omit the symbol table from the listing. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>-t </PRE></TD><TD>Only output number of errors instead list of each one. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>-z </PRE></TD><TD>Accept Z-80 mnemonics preferentially and use Z-80 instruction timings. Equivalent to <TT>.z80</TT> pseudo-op. </TD></TR>\n</TABLE>\n<HR>\n<H3>Input Format</H3>\n<P>\nzmac uses the standard Zilog mnemonics, and the pseudo-ops are also\nlargely as you'd expect.\n<P>\nA \"<TT>.</TT>\" may optionally preceeed any psuedo-op.\nFor example, \"<TT>.org</TT>\" and \"<TT>org</TT>\" are treated as equivalent.\n<P>\nInput can be upper or lowercase.\n<P>\nComments start with <TT>;</TT> and carry on to the end of the line.\n<P>\nNumber constants can take a trailing h or a leading $ or 0x for hex,\na trailing b for binary, a trailing o or q for octal, or a trailing\nd for decimal.\n<P>\n<TT>'LH'</TT> (any length 2 string) can be treated as a number whose value\nis <TT>'H'</TT> * 256 + <TT>'L'</TT>.\n<P>\nLabels are declared with <TT>label:</TT> or just <TT>label</TT> - indentation is unimportant.\nLabels can be up to 40 chars long.  They can start with and contain \nletters, digits, <TT>$</TT>, <TT>.</TT>, <TT>?</TT>, <TT>@</TT> and _.  Ambiguous identifiers like\n<TT>$FCB</TT> will be treated as hex constants unless defined as a label.  Labels\ndeclared with two colons (<TT>label::</TT>) make the label public.\n<P>\nSingle quotes are ignored at the end of identifiers allowing non-binding\n<A HREF=\"#prime\">notation</A> indicating alternate register use during heavy applications\nof <TT>exx</TT> and <TT>ex</TT>.\n<P>\nHere is how other things work.  Numbers are used as examples, but a full\n<A HREF=\"#expr\">expression</A> can be used in their place.\n<P>\n<H4>Data</H4>\n<P>\n<TT>defb 42</TT>\n<BLOCKQUOTE>A byte.  <TT>ascii</TT>, <TT>byte</TT>, <TT>db</TT>, <TT>defm</TT>, <TT>dm</TT> and <TT>text</TT> are synonyms.\n</BLOCKQUOTE>\n<P>\n<TT>defb 'foobar'</TT>\n<BLOCKQUOTE>An ASCII character string (not NUL-terminated).\nDouble quotes can also be used.\n</BLOCKQUOTE>\n<P>\n<TT>defb 'Who needs anything more than CP/M?',13,10,'$'</TT>\n<BLOCKQUOTE>Strings and bytes can mix together.\n</BLOCKQUOTE>\n<P>\n<TT>defw 2112</TT>\n<P>\n<TT>defw $123,0x456</TT>\n<BLOCKQUOTE>A word (16 bits).  <TT>word</TT> and <TT>dw</TT> are synonyms.\n</BLOCKQUOTE>\n<P>\n<TT>defd $12345678</TT>\n<BLOCKQUOTE>A double word (32 bits). <TT>dword</TT> is a synonym.\n</BLOCKQUOTE>\n<P>\n<TT>defs 500</TT>\n<BLOCKQUOTE>Skip output ahead 500 bytes.  This will insert 500 zeros in the \".ams\"\nand \".cim\" output files or if inside a \".phase\" section.\n<TT>block</TT>, <TT>ds</TT> and <TT>rmem</TT> are synonyms.\n</BLOCKQUOTE>\n<P>\n<TT>dc 'string'</TT>\n<BLOCKQUOTE>Like <TT>ascii</TT> but accepts only a single string and the high bit of the\nlast character will be set. <TT>bytes</TT> is a synonym.\n</BLOCKQUOTE>\n<P>\n<TT>dc count,value</TT>\n<BLOCKQUOTE>Repeat the byte <TT>value</TT> a total of <TT>count</TT> times.  Similar to <TT>defs</TT>\nexcept that memory is always filled with <TT>value</TT>.\n</BLOCKQUOTE>\n<P>\n<TT>incbin file</TT>\n<BLOCKQUOTE>Inserts the raw contents of the file into the assembly.  Simpler for\nlarge amounts of data.\n</BLOCKQUOTE>\n<P>\n<H4>Symbols</H4>\n<P>\n<TT>label equ 100</TT>\n<BLOCKQUOTE>Define a symbol to have a fixed value.  The symbol can be used before it\nis defined.  A symbol defined with <TT>equ</TT> or as a label can be defined only\nonce, except that a symbol defined with <TT>equ</TT> may be redefined to the\nsame value.\n</BLOCKQUOTE>\n<P>\n<TT>varname defl 200</TT>\n<BLOCKQUOTE>Define a symbol to have a changeable value.  The symbol cannot be used\nbefore it is defined, and it can be redefined to a different value later\nwith another <TT>defl</TT>. <TT>aset</TT>, <TT>set</TT> and <TT>=</TT> are synonyms (despite <TT>set</TT>\nalso being a Z-80 mnemonic).\n</BLOCKQUOTE>\n<P>\n<TT>varname OP = expression</TT>\n<BLOCKQUOTE>Shorthand for <TT>varname defl varname OP expression</TT>.  Allows for C-like\nhandling of variable such as <TT>var += 5</TT>.  <TT>OP</TT> can be <TT>+</TT>, <TT>-</TT>, <TT>*</TT>, <TT>/</TT>,\n<TT>%</TT>, <TT>&amp;</TT>, <TT>|</TT>, <TT>^</TT>, <TT>&lt;&lt;</TT>, <TT>&gt;&gt;</TT>, <TT>&amp;&amp;</TT> or <TT>||</TT>.\n</BLOCKQUOTE>\n<P>\n<TT>varname++</TT>\n<BLOCKQUOTE>Shorthand for <TT>varname defl varname + 1</TT>\n</BLOCKQUOTE>\n<P>\n<TT>varname--</TT>\n<BLOCKQUOTE>Shorthand for <TT>varname defl varname - 1</TT>\n</BLOCKQUOTE>\n<P>\n<TT>min</TT>\n<P>\n<TT>max</TT>\n<BLOCKQUOTE>Same as <TT>defl</TT> except that the symbol is defined as the\nsmaller or bigger of two comma-separated expressions.\n</BLOCKQUOTE>\n<P>\n<TT>*mod</TT>\n<BLOCKQUOTE>Increment the internal module name string.  The first time this results\nin \"a\".  Then \"b\", \"c\", ... \"z\".  Then \"aa\", \"ab\", \"ac\", etc. all the way\nup to \"zzzz\".  The module name string is used in <TT>--mras</TT> mode where \"?\" in\nlabel names is replaced with the current module name.\n</BLOCKQUOTE>\n<P>\n<TT>extern lab1,lab2,...</TT>\n<BLOCKQUOTE>The listed labels are defined in an external module for later linking.\nNo effect unless zmac is producing \".rel\" output.\n<TT>ext</TT> and <TT>extrn</TT> are synonyms.\n</BLOCKQUOTE>\n<P>\n<TT>public lab1,lab2,...</TT>\n<BLOCKQUOTE>The given labels will be visible to external modules when linking.\nNo effect unless zmac is producing \".rel\" output.\n<TT>global</TT> and <TT>entry</TT> are synonyms.\n</BLOCKQUOTE>\n<P>\n<TT>label ++</TT>\n<BLOCKQUOTE>Equivalent to <TT>label defl label + 1</TT>.\n</BLOCKQUOTE>\n<P>\n<TT>label --</TT>\n<BLOCKQUOTE>Equivalent to <TT>label defl label - 1</TT>.\n</BLOCKQUOTE>\n<P>\n<TT>label += 10</TT>\n<P>\n<TT>label -= 10</TT>\n<P>\n<BLOCKQUOTE>Equivalent to <TT>label defl label + 10</TT> and <TT>label defl label - 10</TT> respectively.\nAlso works for <TT>*=</TT>, <TT>/=</TT>, <TT>%=</TT>, <TT>|=</TT>, <TT>&amp;=</TT>, <TT>^=</TT>, <TT>&lt;&lt;=</TT> and <TT>&gt;&gt;=</TT>.\n</BLOCKQUOTE>\n<P>\n<H4>Location Control</H4>\n<P>\n<TT>org 9000h</TT>\n<BLOCKQUOTE>Set the address to assemble to 0x9000.\n</BLOCKQUOTE>\n<P>\n<TT>phase address</TT>\n<BLOCKQUOTE>Continue to produce code and data for loading at the current address\nbut assemble instructions and define labels as if they originated at\nthe given address.  Useful when producing code that will be copied to\na different location before being executed (e.g., an overlay).\n</BLOCKQUOTE>\n<P>\n<TT>dephase</TT>\n<BLOCKQUOTE>End <TT>phase</TT> mode assembly.\n</BLOCKQUOTE>\n<P>\n<TT>aseg</TT>\n<TT>cseg</TT>\n<TT>dseg</TT>\n<BLOCKQUOTE>Switch to the absolute, code and data segments respectively.\nNo effect unless zmac is producing \".rel\" output.\n</BLOCKQUOTE>\n<P>\n<TT>common /name/</TT>\n<BLOCKQUOTE>Set the address to the start of the selected common block.  The blank\ncommon block will be selected if name is empty or all blanks or\nomitted entirely.\nNo effect unless zmac is producing \".rel\" output.\n</BLOCKQUOTE>\n<P>\n<H4>Input Control</H4>\n<P>\n<TT>end</TT>\n<BLOCKQUOTE>Ends the input.  Any lines after an <TT>end</TT> are silently ignored.\nIf an arg is given, it declares the entry address for the program.\nThis has no effect in \".cim\" output. In \".hex\" output\nit generates an S-record directing 0 bytes of data to be loaded\nat the given address.  It is required for \".500.cas\", \".1000.cas\"\nand \".1500.cas\" output.\n</BLOCKQUOTE>\n<P>\n<TT>if</TT> ... [ <TT>else</TT> ... ] <TT>endif</TT>\n<BLOCKQUOTE>For conditional assembly. If you do <TT>if foo</TT> and <TT>foo</TT> evaluates to\nzero, all the lines up until the next corresponding <TT>else</TT> or <TT>endif</TT>\nare completely ignored.  Conversely, if <TT>foo</TT> evaluates to non-zero, any\nlines from a corresponding <TT>else</TT> to the <TT>endif</TT> are ignored.  Ifs can\nbe nested.  <TT>cond</TT>/<TT>endc</TT> are synonyms for <TT>if</TT>/<TT>endif</TT>.\n</BLOCKQUOTE>\n<P>\n<TT>ifdef symbol</TT>\n<BLOCKQUOTE>Like <TT>if</TT>, but tests if <TT>symbol</TT> has been defined.  Declaring a symbol\nas external counts as it being defined.\n</BLOCKQUOTE>\n<P>\n<TT>ifndef symbol</TT>\n<BLOCKQUOTE>Like <TT>if</TT>, but tests if <TT>symbol</TT> has not yet been defined.\n</BLOCKQUOTE>\n<P>\n<TT>import file</TT>\n<BLOCKQUOTE>Like <TT>include</TT> but will only bring in the file once.  File tracking is done\nusing only the file name so, for example, an <TT>import file</TT> will stop\nboth <TT>import ./file</TT> and <TT>import dir/file</TT> even if they actually refer to\ndifferent files.\n</BLOCKQUOTE>\n<P>\n<TT>include file</TT>\n<BLOCKQUOTE>Include a file. Like C's (well, cpp's) #include and follows the same\ninclude path search rules, but the filename arg\nlacks the angle brackets or quotes (though single or double quotes may be used).\n<TT>read</TT> is a synonym.  <TT>*include file</TT> also works if started in the first\ncolumn.  In <TT>--mras</TT> mode <TT>\".asm\"</TT> will be added if <TT>file</TT> has\nno suffix.\n</BLOCKQUOTE>\n<P>\n<TT>maclib file</TT>\n<BLOCKQUOTE>Like <TT>include</TT> but adds <TT>.lib</TT> to the file name so includes <TT>file.lib</TT>.\n</BLOCKQUOTE>\n<P>\n<TT>comment X</TT>\n<BLOCKQUOTE>Suspend assembly until the next occurence of character <TT>X</TT> on a line.\nThe rest of the line will be ignored.  A multi-line comment.\n</BLOCKQUOTE>\n<P>\n<TT>assert expr</TT>\n<BLOCKQUOTE>Stop assembly if <TT>expr</TT> is non-zero.\n</BLOCKQUOTE>\n<P>\n<H4>Cycle Counting</H4>\n<P>\n<TT>sett expr</TT>\n<BLOCKQUOTE>Set the current T-state count to <TT>expr</TT>. <TT>tstate</TT> is a synonym.\n</BLOCKQUOTE>\n<P>\n<TT>setocf expr</TT>\n<BLOCKQUOTE>Set the current opcode fetch count to <TT>expr</TT>.\n</BLOCKQUOTE>\n<P>\n<H4>Code Generation</H4>\n<P>\n<TT>8080</TT>\n<BLOCKQUOTE>Make cycle counting operators return 8080 cycle counts and\ninterpret any ambiguous assembly statements as Intel 8080 mnemonics.\n<TT>CP</TT> will be interpreted as \"call on positive\" and <TT>JP</TT> as \"jump on positive\".\n</BLOCKQUOTE>\n<P>\n<TT>z80</TT>\n<BLOCKQUOTE>Make cycle counting operators return Z-80 cycle counts and\ninterpret any ambiguous assembly statements as Zilog Z-80 mnemonics.\n<TT>CP</TT> will be interpreted as \"compare accumulator\" and <TT>JP</TT> as \"jump unconditionally\".\n</BLOCKQUOTE>\n<P>\n<TT>jperror enable</TT>\n<BLOCKQUOTE>If <TT>enable</TT> is non-zero, turn on errors when <TT>JR</TT> instructions could be used\ninstead of <TT>JP</TT>, off otherwise.  Used to check existing code for situations\nwhere shorter code could be generated.  Same as <TT>-J</TT> option.\nNo effect if in 8080 mode.\n</BLOCKQUOTE>\n<P>\n<TT>jrpromote enable</TT>\n<BLOCKQUOTE>If <TT>enable</TT> is non-zero, <TT>JR</TT> and <TT>DJNZ</TT> instructions will be promoted to\nequivalent <TT>JP</TT> and <TT>DEC&nbsp;B</TT>, <TT>JP&nbsp;NZ</TT> instructions if the relative branch\noffset is out of range.  If <TT>enable</TT> is zero, promotion is disabled.\nSame as the <TT>-j</TT> option.\nNo effect if in 8080 mode.\n</BLOCKQUOTE>\n<P>\n<H4>Undocumented <A NAME=\"undoc\">Instructions</A></H4>\n<P>\nMost Z-80 chips support a number of undocumented instructions that were part of\nthe original design but not made an offical part of the Zilog specification.\nThese instructions may not be supported by all Z-80 chips, especially\nlicensed variants, but are fairly widely available nonetheless.\n<P>\n<TT>sl1 r</TT>\n<BLOCKQUOTE>Same as <TT>sla r</TT> but shifts a 1 into the lower bit of <TT>r</TT> rather than a 0.\n</BLOCKQUOTE>\n<P>\n<TT>in (c)</TT>\n<BLOCKQUOTE>Inputs a byte from port <TT>c</TT> but does not store the value.  Flags are still\nset as with the normal <TT>in r,(c)</TT> instruction.\n</BLOCKQUOTE>\n<P>\n<TT>out (c),0</TT>\n<BLOCKQUOTE>Outputs a zero to port <TT>c</TT>.\n</BLOCKQUOTE>\n<P>\n<TT>bit/set/res n,(ix+d),r</TT>\n<P>\n<TT>rlc/rrc/rl/rr/sla/sl1/sra/srl (iy+d),r</TT>\n<BLOCKQUOTE>Same as the corresponding operation on just <TT>(ix+d)</TT> or <TT>(iy+d)</TT> but with\nthe result being stored both into <TT>(ix+d)</TT> and register <TT>r</TT>.  Except for <TT>bit</TT>\nwhich has no effect on <TT>r</TT>. zmac supports the syntax to allow those\ninstruction patterns to be generated.\n</BLOCKQUOTE>\n<P>\nThe upper and lower bytes of the <TT>ix</TT> and <TT>iy</TT> can be used in a number of\ninstructions much in the same way as <TT>d</TT> and <TT>e</TT> correspond to the upper and\nlower bytes of <TT>de</TT>.  zmac names these <TT>ixh</TT>, <TT>ixl</TT>, <TT>iyh</TT> and <TT>iyl</TT> and\nare referred to generically as <TT>ixylh</TT> here.\n<P>\n<TT>inc/dec/add/adc/sub/sbc/and/xor/or/cp ixylh</TT>\n<BLOCKQUOTE>Arithmetic or logical operation on <TT>ix</TT> or <TT>iy</TT> high or low byte.\n</BLOCKQUOTE>\n<P>\n<TT>ld a/b/c/d/e,ixylh</TT>\n<BLOCKQUOTE>Load register with <TT>ix</TT> or <TT>iy</TT> high or low byte.\n</BLOCKQUOTE>\n<P>\n<TT>ld ixylh,a/b/c/d/e</TT>\n<BLOCKQUOTE>Load <TT>ix</TT> or <TT>iy</TT> high or low byte with register.\n</BLOCKQUOTE>\n<P>\n<TT>pfix</TT>\n<P>\n<TT>pfiy</TT>\n<BLOCKQUOTE>Output $DD and $FD prefix bytes.  The Z-80 allows multiple prefix bytes\nfor IX and IY instructions.  This allows you to specify them abstractly.\nThere is little purpose except for delaying an interrupt or confusing\ndisassemblers.\n</BLOCKQUOTE>\n<P>\n<H4>Miscellaneous</H4>\n<P>\n<TT>pragma str ...</TT>\n<BLOCKQUOTE>Like C's #pragma, a generic hook for special purpose operations.  Only two\nare currently defined.\n</BLOCKQUOTE>\n<P>\n<BLOCKQUOTE><TT>pragma bds rest-of-line</TT> to\noutput <TT>rest-of-line</TT> to the <TT>.bds</TT> output file.\n</BLOCKQUOTE>\n<P>\n<BLOCKQUOTE><TT>pragma mds rest-of-line</TT> to\noutput <TT>rest-of-line</TT> to the <TT>.mds</TT> output file.\n</BLOCKQUOTE>\n<P>\n<BLOCKQUOTE>The <TT>.bds</TT> output format supports setting initial values for Z-80 registers\nand I/O ports so <TT>pragma</TT> gives you access to that.\n</BLOCKQUOTE>\n<P>\n<BLOCKQUOTE>The <TT>.mds</TT> output format is a MAME debug script thus additional initial\ndebugging commands may be output.  Of particular use on the TRS-80 Model II\nis <TT>pragma mds ib@$ff=1</TT> which maps page 1 of RAM into $8000 .. $FFFF\nand thus allows programs to load into that area.\n</BLOCKQUOTE>\n<P>\n<TT>name str</TT>\n<BLOCKQUOTE>Set the name of the output module to <TT>str</TT>.  For compatibility reasons\n<TT>str</TT> may be parenthesized (e.g., \"<TT>name ('foo')</TT>\").  Not all output\nformats support an internal name and many have severe length limits.\n</BLOCKQUOTE>\n<P>\n<TT>rsym</TT> and <TT>wsym</TT>\n<BLOCKQUOTE>Read/write a symbol file. These simply load/save the currently defined\nsymbols from/to the file specified (in a non-portable format). <TT>rsym</TT>\ntakes place at the point it is encountered in the file (on the first\npass); <TT>wsym</TT> is delayed until assembly has finished.\n</BLOCKQUOTE>\n<P>\n<H4>Listing Pseudo-ops</H4>\n<P>\nThere are several pseudo-ops for controlling the listing. None of\nthese ops appear in the listing themselves:\n<P>\n<TT>eject</TT>\n<BLOCKQUOTE>Start a new listing page.\n</BLOCKQUOTE>\n<P>\n<TT>nolist</TT>\n<BLOCKQUOTE>Do nothing. This can be used to have a comment in the source but not\nthe listing, I suppose.\n</BLOCKQUOTE>\n<P>\n<TT>elist</TT>, <TT>flist</TT>, <TT>glist</TT>, <TT>mlist</TT>\n<BLOCKQUOTE>These have the same effect as the similarly-named command-line\noptions, though possibly with the sense reversed depending on the\ndefault. Use an arg &gt;0 (or no arg) to enable, and an arg &lt;0 to\ndisable.\n</BLOCKQUOTE>\n<P>\n<TT>list arg</TT>\n<BLOCKQUOTE>Turns output to listing file (.list) off if <TT>arg</TT> &lt; 0 or on if <TT>arg</TT> &gt; 0.\nIf no <TT>arg</TT> supplied then listing is enabled.\nUse this to avoid listing certain parts of the source.\nIn <TT>--mras</TT> mode <TT>arg</TT> must be either <TT>on</TT> or <TT>off</TT> and\n<TT>*list</TT> can be used if started in the first column.\n</BLOCKQUOTE>\n<P>\n<TT>title</TT>\n<BLOCKQUOTE>Set title (used in listing and symbol file).\n</BLOCKQUOTE>\n<P>\n<TT>space arg</TT>\n<BLOCKQUOTE>Output arg blank lines in the listing, or one line if no arg is given.\n</BLOCKQUOTE>\n<P>\n<HR>\n<P>\n<H3><A NAME=\"expr\">Expressions</A></H3>\n<P>\nExpressions feature a full set of C operators with the same precedence\nrules and some common assembler extensions and names.\nHere is the complete list of operators, highest-precedence first.\nOperators separated only by a space are synonyms; for example, <TT>~</TT>\nis the same as <TT>not</TT>.\n<P>\n<TT>!</TT> (logical), <TT>~ not</TT> (bitwise), <TT>+</TT> (unary), <TT>-</TT> (unary), <TT>low</TT>, <TT>high</TT>, <TT>t</TT>, <TT>tilo</TT>, <TT>tihi</TT>, <TT>ocf</TT>\n<P>\n<TT>*</TT>, <TT>/</TT>, <TT>% mod</TT>\n<P>\n<TT>+</TT>, <TT>-</TT>\n<P>\n<TT>&lt;&lt; shl</TT>, <TT>&gt;&gt; shr</TT>\n<P>\n<TT>&lt; lt</TT>, <TT>&gt; gt</TT>, <TT>&lt;= le</TT>, <TT>&gt;= ge</TT>\n<P>\n<TT>== = eq</TT>, <TT>!= &lt;&gt; ne</TT>\n<P>\n<TT>&amp; and</TT> (bitwise)\n<P>\n<TT>^ xor</TT> (bitwise)\n<P>\n<TT>| or</TT> (bitwise)\n<P>\n<TT>&amp;&amp;</TT>\n<P>\n<TT>||</TT>\n<P>\n<TT>? :</TT>  (ternary choice operator)\n<P>\n<A NAME=\"mrasord\">Expressions</A> change significantly in <TT>--mras</TT> mode:\n<BLOCKQUOTE>Evaluation is strictly left to right.  Except for <TT>and</TT>, <TT>or</TT>,\n<TT>xor</TT> and <TT>=</TT>.  This doesn't break compatibility as original MRAS\nsource code only allows <TT>.and.</TT>, <TT>.or.</TT> and <TT>.xor.</TT> but the precedence\ndifference may surprise if code is added.\n</BLOCKQUOTE>\n<P>\n<BLOCKQUOTE><TT>!</TT> is bitwise OR instead of logical not.\n</BLOCKQUOTE>\n<P>\n<BLOCKQUOTE><TT>&lt;</TT> is left shift (or right shift when shift amount is negative)\n</BLOCKQUOTE>\n<P>\n<BLOCKQUOTE>MRAS operators (<TT>.and.</TT> <TT>.eq.</TT> <TT>.ge.</TT> <TT>.gt.</TT> <TT>.high.</TT> <TT>.le.</TT> <TT>.low.</TT>\n<TT>.lt.</TT> <TT>.mod.</TT> <TT>.ne.</TT> <TT>.not.</TT> <TT>.or.</TT> <TT>.shl.</TT> <TT>.shr.</TT> <TT>.xor.</TT>)\nare recognized even if apparently in identifers.  (e.g., <TT>a.or.b</TT> is\nseen as <TT>a .or. </TT>b).\n</BLOCKQUOTE>\n<P>\n<BLOCKQUOTE>Logical operators return -1 for true and 0 for false.  Normally\nzmac, like C, uses 1 for true.\n</BLOCKQUOTE>\n<P>\nYou can use normal parentheses or square brackets to override\nthe precedence rules. Square brackets can be used where parentheses would\nconflict with Z-80 mnemonic syntax, but this is not necessary in any\npractical case.\n<P>\nThe <TT>?</TT> may need spaces around it to distinguish it from a label that\nhas <TT>?</TT> in it.\n<P>\nThe unary operators not familiar to C programmers:\n<P>\n<TABLE>\n<TR><TD VALIGN=\"TOP\"><PRE>low expr </PRE></TD><TD>Returns low 8 bits of <TT>expr</TT> </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>high expr </PRE></TD><TD>Returns high 8 bits of <TT>expr</TT> </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>t expr </PRE></TD><TD>Current count of T-states up to memory location <TT>expr</TT> </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>tilo expr </PRE></TD><TD>Low count of T-states used by instruction at memory location <TT>expr</TT> </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>tihi expr </PRE></TD><TD>High count of T-states used by instruction at memory location <TT>expr</TT> </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>ocf expr </PRE></TD><TD>Current count of opcode fetches up to memory location <TT>expr</TT> </TD></TR>\n</TABLE>\n<HR>\n<H3>Macros</H3>\nThe following defines a macro named m with zero or more formal parameters\n<TT>p1</TT>, <TT>p2</TT>, ..., <TT>pn</TT>, zero or more local symbols <TT>?s1</TT>, <TT>?s2</TT>, ..., <TT>?sm</TT>,\nand body <TT>b1</TT>, <TT>b2</TT>, ...:\n<P>\n<TABLE>\n<TR><TD VALIGN=\"TOP\"><PRE><TT>m macro p1, p2, ..., pn, ?s1, ?s2, ..., ?sm</TT> </PRE></TD><TD> </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE><TT>&nbsp;&nbsp;&nbsp;b1</TT> </PRE></TD><TD> </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE><TT>&nbsp;&nbsp;&nbsp;b2</TT> </PRE></TD><TD> </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE><TT>&nbsp;&nbsp;&nbsp;...</TT> </PRE></TD><TD> </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE><TT>&nbsp;&nbsp;&nbsp;endm</TT> </TD></TR>\n</TABLE>\n<P>\nThe macro is called by writing:\n<BLOCKQUOTE><TT>m v1, v2, ..., vn</TT>\n</BLOCKQUOTE>\n<P>\nA macro call expands to the text of the macro's body, with each \noccurrence of a formal parameter <TT>pk</TT> replaced by the corresponding \nvalue <TT>vk</TT>, and with each local symbol <TT>?sk</TT> replaced by a new, unique \nsymbol invented for this call.  Invented symbols begin with <TT>?</TT>,\nso you should avoid using such symbols elsewhere in your program.\n<P>\nzmac currently does not check that you have provided the right number \nof parameters when calling a macro.  If you provide too few, unmatched \nformals are replaced with the empty string.  If you provide too \nmany, the additional values begin to replace local symbols as if \nthey were ordinary parameters.  (This could be considered a feature.)  \nAfter the local symbols are all replaced, additional parameters \nare silently ignored.\n<P>\nFor compatibility with Macro-80, the first line of a macro definition can\nlist other labels that will be treated locally:\n<P>\n<BLOCKQUOTE><TT>&nbsp;&nbsp;&nbsp;local lab1,lab2,...</TT>\n</BLOCKQUOTE>\n<P>\nEach time the macro is expanded the local labels are replaced with unique\nnames thus avoiding multiple definition problems.\n<P>\nFor compatability with MRAS, macro arguments may be preceeded by <TT>#</TT>\nin their definition and use.\n<P>\nAny <TT>`</TT> (backquote) in a macro is ignored thus allowing a macro to\nconstruct identifiers.  For example:\n<P>\n<TABLE>\n<TR><TD VALIGN=\"TOP\"><PRE><TT>move macro dir</TT> </PRE></TD><TD> </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE><TT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;ld`dir`r</TT> </PRE></TD><TD> </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE><TT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;endm</TT> </TD></TR>\n</TABLE>\n<P>\nInvoking <TT>move i</TT> will construct a <TT>ldir</TT> block move instruction.\n<P>\nFor compatibility, <TT>&amp;</TT> can also be used as in MAC to concatenate\nmacro parameters.  This conflicts with zmac's bitwise and operator but\nyou can use the <TT>and</TT> synonym in macros to avoid the conflict.\n<P>\nIn <TT>--mras</TT> mode arguments will be expanded even if they are inside other\nidentifiers.  The <TT>move</TT> could be written:\n<P>\n<TABLE>\n<TR><TD VALIGN=\"TOP\"><PRE><TT>move macro dir</TT> </PRE></TD><TD> </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE><TT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;lddirr</TT> </PRE></TD><TD> </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE><TT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;endm</TT> </TD></TR>\n</TABLE>\n<P>\nMacro definitions can contain macro definitions which will be defined\nwhen the outer macro is first exapnded.  Macros can be redefined as\nwell.\n<P>\nMacro expansion continues to the <TT>endm</TT> directive but can be stopped\nprematurely by the <TT>exitm</TT> directive.  Typically the <TT>exitm</TT> is inside\nsome conditional part of the macro.\n<P>\nParameters passed to a macro can be empty and are tested with the <TT>nul</TT>\noperator:\n<P>\n<TABLE>\n<TR><TD VALIGN=\"TOP\"><PRE><TT>if nul &amp;par</TT> </PRE></TD><TD> </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE><TT>...</TT> </PRE></TD><TD> </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE><TT>endif</TT> </TD></TR>\n</TABLE>\n<P>\nMacro parameters can contain commas if grouped inside <TT>&lt;</TT> and <TT>&gt;</TT>.\nOr a comma can be escaped with <TT>^</TT> which can also escape spaces and other\nspecial characters.  It is also be put in front of a macro parameter\nname inside the expansion to suppress the replacement by its value.\n<P>\nExpansion of parameters in a macro body is purely textual.  This can\nlead to surprises in complex situations.  The <TT>%</TT> character can be used\nto force a macro parameter to be replaced with the evaluation of it\nas an expression.\n<P>\n<P>\n<H4>Inline Macros</H4>\n<P>\nzmac supports the commonly available <TT>rept</TT>, <TT>irp</TT> and <TT>irpc</TT> inline macros\n<P>\n<TT>rept</TT> repeats its block the given number of times.  This will output 10\n<TT>nop</TT> instructions:\n<P>\n<TABLE>\n<TR><TD VALIGN=\"TOP\"><PRE><TT>rept 10</TT> </PRE></TD><TD> </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE><TT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;nop</TT> </PRE></TD><TD> </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE><TT>endm</TT> </TD></TR>\n</TABLE>\n<P>\n<TT>irpc</TT> runs through a string of letters assigned them to a variable and\nexpanding the macro block each time.  For example, this will load 7 into\nregisters <TT>b</TT>, <TT>d</TT> and <TT>h</TT>:\n<P>\n<TABLE>\n<TR><TD VALIGN=\"TOP\"><PRE><TT>irpc reg,bdh</TT> </PRE></TD><TD> </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE><TT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;ld &amp;reg,7</TT> </PRE></TD><TD> </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE><TT>endm</TT> </TD></TR>\n</TABLE>\n<P>\n<TT>irp</TT> runs through a list of parameters assiging each entry to a variable\nand expanding the macro block.  Here we load <TT>bc</TT>, <TT>de</TT> and <TT>hl</TT> with 0:\n<P>\n<TABLE>\n<TR><TD VALIGN=\"TOP\"><PRE><TT>irp rpair,&lt;bc,de,hl&gt;</TT> </PRE></TD><TD> </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE><TT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;ld &amp;rpair,0</TT> </PRE></TD><TD> </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE><TT>endm</TT> </TD></TR>\n</TABLE>\n<P>\nLists can be nested.  Here's an example of and <TT>irp</TT> passing lists on down\nto another <TT>irp</TT>:\n<P>\n<TABLE>\n<TR><TD VALIGN=\"TOP\"><PRE><TT>irp listlist,&lt;&lt;one,two,three&gt;,&lt;four,five,six&gt;&gt;</TT> </PRE></TD><TD> </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE><TT>irp list,&lt;listlist&gt;</TT> </PRE></TD><TD> </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE><TT>ascii '&amp;list'</TT> </PRE></TD><TD> </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE><TT>endm</TT> </PRE></TD><TD> </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE><TT>endm</TT> </TD></TR>\n</TABLE>\n<P>\n<P>\n<HR>\n<H3>Compatibility</H3>\n<P>\nzmac is broadly compatible with many original Z-80 and 8080 assemblers\nbecause it accepts many different names for common operations and has\nliberal identifier and numeric formats.  It also accepts most simple\nusage of macros.\n<P>\nWhen assembling old code keep these portability problems in mind.\n<P>\nExpression order of evaluation may be different.  zmac uses C semantics\nmore order of evaluation but assemblers often used simple left to right\nordering.  zmac will evaluate <TT>2+2*3</TT> as <TT>8</TT> where other assemblers will\nyield <TT>12</TT>.  However, in <TT>--mras</TT> mode expressions are evaluated strictly\nleft-to-right for compatibility.\n<P>\nzmac has no support operating on strings in macros.  Assemblers like Macro-80\ncould perform conditional tests on strings.\n<P>\nAdvanced macros are unlikely to work.  zmac hasn't advanced to the state where\nall the possible ways of substituting parameters are supported.\n<P>\nConsult the original assembler manual.  zmac error messages won't help you\nfigure out what an unknown assembler command is supposed to do.\n<P>\nCompare against original output.  The very safest thing to do when porting\nassembly code is to compare the binary output of zmac against that produced\nby the original assembler.  This way you can ensure everything has been\ninterpreted correctly.  Only once that has been achieved should you modify\nthe code.\n<HR>\n<H3>Errors and Warnings</H3>\n<P>\nAny errors or warnings encountered during assembly are reported to standard\nerror and in the listing file.  The errors output immediately give the source\nfile and line number containing the error.  In listings the error letter\nand message appear just after the line containing the error.\n<P>\n<TABLE>\n<TR><TD VALIGN=\"TOP\"><PRE>B </PRE></TD><TD>Balance error </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>&nbsp; </PRE></TD><TD>A string is missing an closing quote or an <TT>if</TT> is missing an <TT>endif</TT> </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>E </PRE></TD><TD>Expression error </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>&nbsp; </PRE></TD><TD>An expression did not parse or attempts a divide or modulus by 0. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>F </PRE></TD><TD>Syntax error </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>&nbsp; </PRE></TD><TD>General problem with the syntax on a line.  Sometimes extra explanation will be printed on standard output. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>I </PRE></TD><TD>Digit error </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>&nbsp; </PRE></TD><TD>A numeric constant has too many digits to be represented as a 32 bit number. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>M </PRE></TD><TD>Mult. def. error </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>&nbsp; </PRE></TD><TD>A symbol has been defined more than once and those values differ. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>P </PRE></TD><TD>Phase error </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>&nbsp; </PRE></TD><TD>On the second or subsequent assembly passes the assembly has changed significantly.  Most commonly it means an <TT>if</TT> has changed conditions but can also happen when labels or equated values do not converge to a fixed value. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>U </PRE></TD><TD>Undeclared error </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>&nbsp; </PRE></TD><TD>An undeclared symbol was used in an expression or <TT>public</TT> statement. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>V </PRE></TD><TD>Value error </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>&nbsp; </PRE></TD><TD>An invalid value was given to a statement.  Often this means using less than -128 or greater then 255 in a <TT>defb</TT> or less than -32768 or greater than 65535 in a <TT>defw</TT>.  Or similar invalid values used Z-80/8080 opcodes requiring an 8 or 16 bit value (and other restrictions like 0 to 7 for <TT>BIT</TT>). Also if a relative jump is out of range or if a negative value is given in <TT>defs</TT> or <TT>dc</TT>. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>O </PRE></TD><TD>Phase/Dephase error </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>&nbsp; </PRE></TD><TD><TT>phase</TT> was used within another <TT>phase</TT> or <TT>dephase</TT> without <TT>phase</TT>. Or if <TT>org</TT> is used within <TT>phase</TT>. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>A </PRE></TD><TD>Assertion failure error </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>&nbsp; </PRE></TD><TD>An assert statement evaluated to zero. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>J </PRE></TD><TD>Use JR error </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>&nbsp; </PRE></TD><TD>An absolute jump instruction was used where relative jump was in range of the destination address.  Only generated if <TT>-j</TT> or <TT>jrpromote</TT> is in effect. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>R </PRE></TD><TD>Not relocatable error </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>&nbsp; </PRE></TD><TD>An expression was used that must be generated at link time but cannot be handled by the \".rel\" format.  For instance, an <TT>org</TT> to a symbol in the data segment when in the code segment.  Or a relative jump to a different segment.  The \".rel\" format can evaluate expressions at link time using the <TT>high</TT>, <TT>low</TT>, <TT>not</TT>, <TT>-</TT>, <TT>+</TT>, <TT>*</TT>, <TT>/</TT> and <TT>%</TT> operators. zmac is clever enough to use <TT>high</TT> or <TT>low</TT> in place of <TT>&amp; $ff00</TT> and <TT>&amp; 255</TT>.  But it won't replace a <TT>shl</TT> with a multiply. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>G </PRE></TD><TD>Register usage error </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>&nbsp; </PRE></TD><TD>A invalid register was given to an instruction.  For example, <TT>LD B,(DE)</TT> or <TT>ADD HL,IX</TT>. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>Z </PRE></TD><TD>Z-80 instruction in 8080 mode error </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>&nbsp; </PRE></TD><TD>An instruction was assembled that is only valid on the Z-80 but <TT>.8080</TT> (or <TT>-8</TT>) mode is in effect.  However, use use of Z-80 mnemonics that output valid 8080 instructions is always OK. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>H </PRE></TD><TD>$hex constant interpreted as symbol warning </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>&nbsp; </PRE></TD><TD>A symbol such as <TT>$FCB</TT> has been defined even though it could appear to be a hexadecimal constant.  zmac will treat <TT>$FCB</TT> as symbol for the entire assembly which could be rather surprising if that were not the intent. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>N </PRE></TD><TD>Not implemented warning </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>&nbsp; </PRE></TD><TD>For statements that have been added as parse rules but have no effect. The only current example is <TT>subttl</TT> which sets the sub title of a listing in certain assemblers. </TD></TR>\n</TABLE>\n<P>\n<HR>\n<H3>Output <A NAME=\"format\">Formats</A></H3>\n<P>\nExcept for \".rel\", zmac writes every known output when assembling by default.\nThis is no burden on modern computers and saves having to meticulously select\nthe desired output format.\n<P>\n\".rel\" is a special case since that format is intended for linking and\ncan have undefined external symbols which would be errors in the other formats.\nConversely, a simple \"org $8000\" will be an error for \".rel\" output as it\ndefaults to the code segment where absolute origin statements are forbidden.\n<P>\nIf \".rel\" is selected for output either by <TT>--relopt</TT> or with\n<TT>--oo rel</TT> or <TT>-o file.rel</TT> then all other output formats are suppressed\n(except the \".lst\" source file listing).\n<P>\n<TABLE>\n<TR><TD VALIGN=\"TOP\"><PRE>.ams </PRE></TD><TD>AMSDOS executable format for Amstrad computers. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>.bds </PRE></TD><TD>For source-level debugging in <A HREF=\"http://www.48k.ca/trs80gp.html\">trs80gp</A> </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>.1500.cas </PRE></TD><TD>TRS-80 high-speed (1500 baud) cassette SYSTEM file.  The internal name of the file is the source file name shortened to 6 characters with suffixes removed.  Requires an entry address. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>.250.cas </PRE></TD><TD>TRS-80 250 baud cassette Level I CLOAD file.  If your program has an entry address and $41FE does not contain that entry address then the file will be loaded at $41FE with relocation code added to move it to the desired location. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>.500.cas </PRE></TD><TD>TRS-80 low-speed (500 baud) cassette SYSTEM file.  The internal name of the file is the source file name shortened to 6 characters with suffixes removed. Requires an entry address. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>.1000.cas </PRE></TD><TD>Identical to 500 baud but intended for double-speed LNW-80 which can can load cassette files at double speed for an effective 1000 baud rate. Requires an entry address. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>.cim </PRE></TD><TD>Core In-Memory image.  A raw binary format with the first byte corresponding to the lowest generated code or data and proceeding contiguously until the highest address generated.  Any gaps are filled with zeros.  Typically used for CP/M where all executables start at address 256 or for ROM images. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>.cmd </PRE></TD><TD>TRS-80 DOS executable file format as used by all major DOSes on the TRS-80 (TRS-DOS, LDOS, MULTIDOS, NEWDOS, etc.) </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>.hex </PRE></TD><TD>Intel hex record format. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>.rel </PRE></TD><TD>Relocatable object module format as produced by MACRO-80 and other assemblers. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>.tap </PRE></TD><TD>ZX Spectrum cassette tape format. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>.1500.wav </PRE></TD><TD>Same as .1500.cas but in ready-to-play audio format. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>.250.wav </PRE></TD><TD>Same as .250.cas but in ready-to-play audio format. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>.500.wav </PRE></TD><TD>Same as .500.cas but in ready-to-play audio format. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>.1000.wav </PRE></TD><TD>Same as .1000.cas but in ready-to-play audio format. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>.mds </PRE></TD><TD>MAME debug script (e.g., mame trs80 -d -debugscript zout/prog.mds) </TD></TR>\n</TABLE>\n<P>\n<HR>\n<H3>Miscellaneous</H3>\nIn the symbol table listing, the <TT>=</TT> prefix is given for those symbols\ndefined by <TT>equ</TT> or <TT>defl</TT>.  The <TT>/</TT> prefix is shown for common blocks.\n<P>\nThe <TT>.rel</TT> file format can store symbol names of up to 7 characters in length.\nHowever, MACRO-80 truncates symbols to 6 characters so that it has one\ncharacter in reserve for extending linking operations such as subtracting\ntwo externals from each other.  To be compatible (and sensible), <TT>--rel</TT>\ntruncates externals to 6 characters.  For MRAS compatibility, <TT>--mras</TT>\ntruncates symbols to 7 characters.  This is not a problem for MRAS as it\ndoesn't support extended linking.  But necessary if you want zmac to produce\n<TT>.rel</TT> files that will link with MRAS generated <TT>.rel</TT> files.  The <TT>--rel7</TT>\noption sets symbol truncation to 7 characters so you can assemble files\nthat will link with MRAS output.  However, it will break extended linking\non labels longer than 6 characters.\n<P>\nThe <A NAME=\"prime\">ignoring</A> of single quotes can be handy for tracking alternate\nregister usage.  Consider the following code fragment:\n<P>\n<TABLE>\n<TR><TD VALIGN=\"TOP\"><PRE><TT>ld    a,(hl)</TT> </PRE></TD><TD> </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE><TT>rra</TT> </PRE></TD><TD> </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE><TT>exx</TT> </PRE></TD><TD> </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE><TT>ld    a,(hl')</TT> </PRE></TD><TD> </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE><TT>ex    af,af'</TT> </PRE></TD><TD> </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE><TT>ld    a',(hl') </PRE></TD><TD> </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE></TT>rra'<TT> </PRE></TD><TD> </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE></TT>ex    af,af'<TT> </PRE></TD><TD> </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE></TT>djnz' loop<TT> </PRE></TD><TD> </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE></TT>ld    d',e'<TT> </PRE></TD><TD> </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE></TT>exx<TT> </TD></TR>\n</TABLE>\n<P>\nAlthough zmac does nothing but ignore the single quotes they are useful for\nindicating which register we're talking using.  A more advanced mode\nwhere zmac pays attention to the trailing quotes and emits exchange instrucitons\nas needed has been considered.\n<P>\n<HR>\n<H3>Exit Status</H3>\n<P>\n<TABLE>\n<TR><TD VALIGN=\"TOP\"><PRE>0 </PRE></TD><TD>No errors. </TD></TR>\n<TR><TD VALIGN=\"TOP\"><PRE>1 </PRE></TD><TD>One or more errors were found during assembly, or zmac exited with a fatal error. </TD></TR>\n</TABLE>\n<P>\n<HR>\n<H3>Credits</H3>\nBruce Norskog originally wrote zmac in 1978.\n<P>\nUpdates and bugfixes over the years by John Providenza, Colin Kelley,\nand more recently by Russell Marks, Mark RISON, Chris Smith,\nMatthew Phillips and Tim Mann.\n<P>\nExtensive modifications for cycle counting, multiple output formats,\n\".rel\" output, 8080 mode and older assembler compatibilty were written\nby George Phillips.\n<P>\nThis document was based on Russell Marks zmac man page which had\ntweaks by Mark RISON and Tim Mann.  George Phillips converted it to HTML\nand documented the new features and some older ones (e.g., </TT>phase<TT>/</TT>dephase<TT>).\n</TT>\n<p xmlns:dct=\"http://purl.org/dc/terms/\" xmlns:vcard=\"http://www.w3.org/2001/vcard-rdf/3.0#\">\n  <a rel=\"license\"\n     href=\"http://creativecommons.org/publicdomain/zero/1.0/\">\n    <img src=\"http://i.creativecommons.org/p/zero/1.0/88x31.png\" style=\"border-style: none;\" alt=\"CC0\" />\n  </a>\n  <br />\n  To the extent possible under law,\n  <a rel=\"dct:publisher\"\n     href=\"http://48k.ca/zmac.html\">\n    <span property=\"dct:title\">George Phillips</span></a>\n  has waived all copyright and related or neighboring rights to\n  <span property=\"dct:title\">zmac macro cross assembler for the Zilog Z-80 microprocessor</span>.\nThis work is published from:\n<span property=\"vcard:Country\" datatype=\"dct:ISO3166\"\n      content=\"CA\" about=\"http://48k.ca/zmac.html\">\n  Canada</span>.\n</p>\n\n<!--\n  If you ran \"zmac --doc\" you may want to send the output\n  to a file using \"zmac --doc >zmac.html\" and then open\n  zmac.html in your web browser.\n-->\n"
  }
]