Repository: gdevic/A-Z80 Branch: master Commit: d70a4f9ab3b0 Files: 407 Total size: 7.1 MB Directory structure: gitextract_gd2ymr2z/ ├── .gitignore ├── cpu/ │ ├── alu/ │ │ ├── alu.bdf │ │ ├── alu.bsf │ │ ├── alu.v │ │ ├── alu_bit_select.bdf │ │ ├── alu_bit_select.bsf │ │ ├── alu_bit_select.v │ │ ├── alu_control.bdf │ │ ├── alu_control.bsf │ │ ├── alu_control.v │ │ ├── alu_core.bdf │ │ ├── alu_core.bsf │ │ ├── alu_core.v │ │ ├── alu_flags.bdf │ │ ├── alu_flags.bsf │ │ ├── alu_flags.v │ │ ├── alu_mux_2.bdf │ │ ├── alu_mux_2.bsf │ │ ├── alu_mux_2.v │ │ ├── alu_mux_2z.bdf │ │ ├── alu_mux_2z.bsf │ │ ├── alu_mux_2z.v │ │ ├── alu_mux_3z.bdf │ │ ├── alu_mux_3z.bsf │ │ ├── alu_mux_3z.v │ │ ├── alu_mux_4.bdf │ │ ├── alu_mux_4.bsf │ │ ├── alu_mux_4.v │ │ ├── alu_mux_8.bdf │ │ ├── alu_mux_8.bsf │ │ ├── alu_mux_8.v │ │ ├── alu_prep_daa.bdf │ │ ├── alu_prep_daa.bsf │ │ ├── alu_prep_daa.v │ │ ├── alu_select.bdf │ │ ├── alu_select.bsf │ │ ├── alu_select.v │ │ ├── alu_shifter_core.bdf │ │ ├── alu_shifter_core.bsf │ │ ├── alu_shifter_core.v │ │ ├── alu_slice.bdf │ │ ├── alu_slice.bsf │ │ ├── alu_slice.v │ │ ├── simulation/ │ │ │ └── modelsim/ │ │ │ ├── r │ │ │ ├── test_alu.mpf │ │ │ ├── wave_alu.do │ │ │ ├── wave_core.do │ │ │ ├── wave_mux_3z.do │ │ │ ├── wave_prep_daa.do │ │ │ ├── wave_shifter_core.do │ │ │ └── wave_slice.do │ │ ├── test_alu.qpf │ │ ├── test_alu.qsf │ │ ├── test_alu.sv │ │ ├── test_core.sv │ │ ├── test_mux_3z.sv │ │ ├── test_prep_daa.sv │ │ ├── test_shifter_core.sv │ │ └── test_slice.sv │ ├── bus/ │ │ ├── address_latch.bdf │ │ ├── address_latch.bsf │ │ ├── address_latch.v │ │ ├── address_mux.bdf │ │ ├── address_mux.bsf │ │ ├── address_mux.v │ │ ├── address_pins.bdf │ │ ├── address_pins.bsf │ │ ├── address_pins.v │ │ ├── bus_control.bdf │ │ ├── bus_control.bsf │ │ ├── bus_control.v │ │ ├── bus_switch.bsf │ │ ├── bus_switch.v │ │ ├── control_pins_n.bdf │ │ ├── control_pins_n.bsf │ │ ├── control_pins_n.v │ │ ├── data_pins.bdf │ │ ├── data_pins.bsf │ │ ├── data_pins.v │ │ ├── data_pins_lattice.v │ │ ├── data_switch.bdf │ │ ├── data_switch.bsf │ │ ├── data_switch.v │ │ ├── data_switch_mask.bdf │ │ ├── data_switch_mask.bsf │ │ ├── data_switch_mask.v │ │ ├── inc_dec.bdf │ │ ├── inc_dec.bsf │ │ ├── inc_dec.v │ │ ├── inc_dec_2bit.bdf │ │ ├── inc_dec_2bit.bsf │ │ ├── inc_dec_2bit.v │ │ ├── simulation/ │ │ │ └── modelsim/ │ │ │ ├── r │ │ │ ├── test_bus.mpf │ │ │ ├── wave_bus.do │ │ │ └── wave_pins.do │ │ ├── test_bus.qpf │ │ ├── test_bus.qsf │ │ ├── test_bus.sv │ │ └── test_pins.sv │ ├── control/ │ │ ├── Timings.csv │ │ ├── Timings.xlsm │ │ ├── clk_delay.bdf │ │ ├── clk_delay.bsf │ │ ├── clk_delay.v │ │ ├── decode_state.bdf │ │ ├── decode_state.bsf │ │ ├── decode_state.v │ │ ├── exec_matrix.vh │ │ ├── exec_matrix_compiled.vh │ │ ├── exec_module.vh │ │ ├── exec_zero.vh │ │ ├── execute.bsf │ │ ├── execute.v │ │ ├── gencompile.py │ │ ├── genmatrix.py │ │ ├── genref.py │ │ ├── interrupts.bdf │ │ ├── interrupts.bsf │ │ ├── interrupts.v │ │ ├── ir.bdf │ │ ├── ir.bsf │ │ ├── ir.v │ │ ├── memory_ifc.bdf │ │ ├── memory_ifc.bsf │ │ ├── memory_ifc.v │ │ ├── pin_control.bdf │ │ ├── pin_control.bsf │ │ ├── pin_control.v │ │ ├── pla_decode.bsf │ │ ├── pla_decode.v │ │ ├── resets.bdf │ │ ├── resets.bsf │ │ ├── resets.v │ │ ├── sequencer.bdf │ │ ├── sequencer.bsf │ │ ├── sequencer.v │ │ ├── simulation/ │ │ │ └── modelsim/ │ │ │ ├── r │ │ │ ├── test_control.mpf │ │ │ ├── wave_interrupts.do │ │ │ ├── wave_pin_control.do │ │ │ ├── wave_reset.do │ │ │ └── wave_sequencer.do │ │ ├── temp_wires.vh │ │ ├── test_control.qpf │ │ ├── test_control.qsf │ │ ├── test_decode.sv │ │ ├── test_interrupts.sv │ │ ├── test_pin_control.sv │ │ ├── test_reset.sv │ │ ├── test_sequencer.sv │ │ └── timing_macros.i │ ├── copyleft.txt │ ├── export.py │ ├── readme.txt │ ├── registers/ │ │ ├── reg_control.bdf │ │ ├── reg_control.bsf │ │ ├── reg_control.v │ │ ├── reg_file.bdf │ │ ├── reg_file.bsf │ │ ├── reg_file.v │ │ ├── reg_latch.bdf │ │ ├── reg_latch.bsf │ │ ├── reg_latch.v │ │ ├── simulation/ │ │ │ └── modelsim/ │ │ │ ├── r │ │ │ ├── test_registers.mpf │ │ │ ├── wave_latch.do │ │ │ ├── wave_regfile.do │ │ │ └── wave_registers.do │ │ ├── test_latch.sv │ │ ├── test_regfile.sv │ │ ├── test_registers.qpf │ │ ├── test_registers.qsf │ │ └── test_registers.sv │ ├── top-level-files.txt │ └── toplevel/ │ ├── core.vh │ ├── coremodules.vh │ ├── fuse/ │ │ ├── README │ │ ├── regress.expected │ │ ├── regress.in │ │ ├── tests.expected │ │ └── tests.in │ ├── gencoremodules.py │ ├── genfuse.py │ ├── genglobals.py │ ├── globals.vh │ ├── simulation/ │ │ └── modelsim/ │ │ ├── io.hex │ │ ├── r │ │ ├── ram.hexdump │ │ ├── test_top.mpf │ │ ├── wave_fuse.do │ │ └── wave_top.do │ ├── tb_io.sv │ ├── tb_iorq.sv │ ├── tb_ram.sv │ ├── test_fuse.sv │ ├── test_fuse.vh │ ├── test_top.sv │ ├── toplevel.bdf │ ├── toplevel.qpf │ ├── toplevel.qsf │ ├── z80.svh │ ├── z80_top_direct_n.v │ └── z80_top_ifc_n.sv ├── docs/ │ ├── A-Z80_UsersGuide.docx │ ├── QuickStart.docx │ └── Spectrum-VGA-timings.xlsx ├── host/ │ ├── basic_de1/ │ │ ├── basic_de1.qpf │ │ ├── basic_de1.qsf │ │ ├── basic_de1.sdc │ │ ├── basic_de1_ModelSim.sv │ │ ├── basic_de1_fpga.sv │ │ ├── fpga.hex │ │ ├── pll.ppf │ │ ├── pll.qip │ │ ├── pll.v │ │ ├── ram.qip │ │ ├── ram.v │ │ ├── readme.txt │ │ ├── simulation/ │ │ │ └── modelsim/ │ │ │ ├── fpga.hex │ │ │ ├── r │ │ │ ├── test_host.mpf │ │ │ └── wave_host.do │ │ └── test_host.sv │ ├── basic_nexys3/ │ │ ├── Nexys3_master.ucf │ │ ├── basic_nexys3.xise │ │ ├── basic_nexys3_fpga.v │ │ ├── cscope.cdc │ │ ├── ipcore_dir/ │ │ │ ├── clock/ │ │ │ │ ├── example_design/ │ │ │ │ │ ├── clock_exdes.ucf │ │ │ │ │ ├── clock_exdes.v │ │ │ │ │ └── clock_exdes.xdc │ │ │ │ ├── implement/ │ │ │ │ │ ├── implement.bat │ │ │ │ │ ├── implement.sh │ │ │ │ │ ├── planAhead_ise.bat │ │ │ │ │ ├── planAhead_ise.sh │ │ │ │ │ ├── planAhead_ise.tcl │ │ │ │ │ ├── planAhead_rdn.bat │ │ │ │ │ ├── planAhead_rdn.sh │ │ │ │ │ ├── planAhead_rdn.tcl │ │ │ │ │ ├── xst.prj │ │ │ │ │ └── xst.scr │ │ │ │ └── simulation/ │ │ │ │ ├── clock_tb.v │ │ │ │ ├── functional/ │ │ │ │ │ ├── simcmds.tcl │ │ │ │ │ ├── simulate_isim.bat │ │ │ │ │ ├── simulate_isim.sh │ │ │ │ │ ├── simulate_mti.bat │ │ │ │ │ ├── simulate_mti.do │ │ │ │ │ ├── simulate_mti.sh │ │ │ │ │ ├── simulate_ncsim.sh │ │ │ │ │ ├── simulate_vcs.sh │ │ │ │ │ ├── ucli_commands.key │ │ │ │ │ ├── vcs_session.tcl │ │ │ │ │ ├── wave.do │ │ │ │ │ └── wave.sv │ │ │ │ └── timing/ │ │ │ │ ├── clock_tb.v │ │ │ │ ├── sdf_cmd_file │ │ │ │ ├── simcmds.tcl │ │ │ │ ├── simulate_isim.sh │ │ │ │ ├── simulate_mti.bat │ │ │ │ ├── simulate_mti.do │ │ │ │ ├── simulate_mti.sh │ │ │ │ ├── simulate_ncsim.sh │ │ │ │ ├── simulate_vcs.sh │ │ │ │ ├── ucli_commands.key │ │ │ │ ├── vcs_session.tcl │ │ │ │ └── wave.do │ │ │ ├── clock.asy │ │ │ ├── clock.gise │ │ │ ├── clock.ucf │ │ │ ├── clock.v │ │ │ ├── clock.veo │ │ │ ├── clock.xco │ │ │ ├── clock.xise │ │ │ ├── coregen.cgp │ │ │ ├── ila.asy │ │ │ ├── ila.cdc │ │ │ ├── ila.constraints/ │ │ │ │ ├── ila.ucf │ │ │ │ └── ila.xdc │ │ │ ├── ila.gise │ │ │ ├── ila.ncf │ │ │ ├── ila.ngc │ │ │ ├── ila.sym │ │ │ ├── ila.ucf │ │ │ ├── ila.v │ │ │ ├── ila.veo │ │ │ ├── ila.xco │ │ │ ├── ila.xdc │ │ │ ├── ila.xise │ │ │ └── ila_xmdf.tcl │ │ ├── ram.v │ │ ├── readme.txt │ │ ├── test_host.v │ │ └── work/ │ │ └── ram.mif │ ├── common/ │ │ ├── uart.v │ │ ├── wait_state.bdf │ │ ├── wait_state.bsf │ │ └── wait_state.v │ └── zxspectrum_de1/ │ ├── pll.ppf │ ├── pll.qip │ ├── pll.v │ ├── ram16.qip │ ├── ram16.v │ ├── readme.txt │ ├── rom/ │ │ ├── assemble.bat │ │ ├── combined.rom │ │ ├── gw03.rom │ │ ├── readme.txt │ │ ├── tasm80.tab │ │ └── zxspectrum_rom.asm │ ├── ula/ │ │ ├── clocks.sv │ │ ├── i2c_loader.vhd │ │ ├── i2s_intf.vhd │ │ ├── pll.ppf │ │ ├── pll.qip │ │ ├── pll.v │ │ ├── ps2_kbd.sv │ │ ├── ram8.qip │ │ ├── ram8.v │ │ ├── test_scr.hex │ │ ├── test_ula.qpf │ │ ├── test_ula.qsf │ │ ├── test_ula.sv │ │ ├── ula.sv │ │ ├── video.sv │ │ └── zx_kbd.sv │ ├── zxspectrum_de1.qpf │ ├── zxspectrum_de1.qsf │ ├── zxspectrum_de1.sdc │ └── zxspectrum_de1.sv ├── license.txt ├── modelsim_pre_commit.py ├── modelsim_setup.py ├── readme.txt ├── resources/ │ ├── connotate-fuse.bat │ ├── connotate-fuse.py │ ├── opcodes-cb-xx.txt │ ├── opcodes-dd-cb.txt │ ├── opcodes-dd-xx.txt │ ├── opcodes-ed-xx.txt │ ├── opcodes-fd-cb.txt │ ├── opcodes-fd-xx.txt │ ├── opcodes-xx.txt │ ├── process-pla.py │ ├── title-custom-medium.bsf │ ├── title-custom-small.bsf │ ├── z80-pla-original.txt │ └── z80-pla.txt └── tools/ ├── Arduino/ │ └── Z80_dongle/ │ └── Z80_dongle.ino ├── dongle/ │ ├── cb.html │ ├── daa/ │ │ ├── daa-concise.txt │ │ ├── daa_a-00.out │ │ ├── daa_a-0c.out │ │ ├── daa_a-h0.out │ │ ├── daa_a-hc.out │ │ ├── daa_s-00.out │ │ ├── daa_s-0c.out │ │ ├── daa_s-h0.out │ │ ├── daa_s-hc.out │ │ ├── simulate-daa.py │ │ └── z80-instruction-test-daa.py │ ├── dd.html │ ├── ddcb.html │ ├── ed.html │ ├── neg/ │ │ ├── neg-concise.txt │ │ ├── neg.out │ │ ├── simulate-neg.py │ │ └── z80-instruction-test-neg.py │ ├── sbc/ │ │ ├── simulate-sbc.py │ │ └── simulate-sub.py │ ├── xx.html │ ├── z80-instruction-run-cb.py │ ├── z80-instruction-run-dd-cb.py │ ├── z80-instruction-run-dd.py │ ├── z80-instruction-run-ed.py │ ├── z80-instruction-run-xx.py │ └── z80-instruction-run.bat ├── readme.txt ├── z80_pla_checker/ │ ├── readme.txt │ └── source/ │ ├── ClassLog.cs │ ├── ClassOpcodeTable.cs │ ├── ClassPLA.cs │ ├── ClassPLAEntry.cs │ ├── FormMain.Designer.cs │ ├── FormMain.cs │ ├── FormMain.resx │ ├── Program.cs │ ├── Properties/ │ │ ├── AssemblyInfo.cs │ │ ├── Resources.Designer.cs │ │ ├── Resources.resx │ │ ├── Settings.Designer.cs │ │ └── Settings.settings │ ├── app.config │ ├── z80_pla_checker.csproj │ └── z80_pla_checker.sln └── zmac/ ├── bin2coe.py ├── bin2hex.txt ├── bin2mif.py ├── bindump.py ├── hello_world.asm ├── make_fpga.bat ├── make_modelsim.bat ├── readme.txt ├── test.daa.asm ├── test.neg.asm ├── zexall.asm ├── zexdoc.asm └── zmac.html ================================================ FILE CONTENTS ================================================ ================================================ FILE: .gitignore ================================================ # Quartus generated files and folders *.rpt *.done *.rpt *.smsg *.summary *.ddb db/ incremental_db/ out/ output_files/ greybox_tmp/ # Quartus workspace file: stores window position, dock state etc. *.qws # ModelSim files and folders transcript *.mti *.wlf _* _temp/ _primary.* *.prw *.psm *.vstf mgc_location_map # Generic backup files *~ *.bak # Visual Studio temporary files *.suo *.tss *.user obj/ Debug/ Release/ *.DotSettings # ZMAC assembler output directory zout/ ================================================ FILE: cpu/alu/alu.bdf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. 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40 3457 101) (name "title-custom-medium") (section (rect 0 0 320 20)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 106 21)(font "Arial" (font_size 12)(bold)))(border)) (section (rect 130 0 320 20)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "alu" (rect 43 2 70 21)(font "Arial" (font_size 12)(bold)))(border)) (section (rect 0 21 320 40)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 151 19)(font "Arial" (font_size 11)))(border)) (section (rect 0 41 240 60)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "May 18, 2014" (rect 56 3 149 19)(font "Arial" (font_size 10)))(border)) (section (rect 241 41 320 60)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.4" (rect 43 3 64 19)(font "Arial" (font_size 10)))(border)) (drawing ) ) ================================================ FILE: cpu/alu/alu.bsf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "symbol" (version "1.2")) (symbol (rect 16 16 272 464) (text "alu" (rect 5 0 21 14)(font "Arial" (font_size 8))) (text "inst" (rect 8 432 25 444)(font "Arial" )) (port (pt 0 32) (input) (text "alu_oe" (rect 0 0 37 14)(font "Arial" (font_size 8))) (text "alu_oe" (rect 21 27 58 41)(font "Arial" (font_size 8))) (line (pt 0 32)(pt 16 32)) ) (port (pt 0 48) (input) (text "alu_shift_in" (rect 0 0 64 14)(font "Arial" (font_size 8))) (text "alu_shift_in" (rect 21 43 85 57)(font "Arial" (font_size 8))) (line (pt 0 48)(pt 16 48)) ) (port (pt 0 64) (input) (text "alu_shift_left" (rect 0 0 73 14)(font "Arial" (font_size 8))) (text "alu_shift_left" (rect 21 59 94 73)(font "Arial" (font_size 8))) (line (pt 0 64)(pt 16 64)) ) (port (pt 0 80) (input) (text "alu_shift_right" (rect 0 0 80 14)(font "Arial" (font_size 8))) (text "alu_shift_right" (rect 21 75 101 89)(font "Arial" (font_size 8))) (line (pt 0 80)(pt 16 80)) ) (port (pt 0 96) (input) (text "alu_core_R" (rect 0 0 64 14)(font "Arial" (font_size 8))) (text "alu_core_R" (rect 21 91 85 105)(font "Arial" (font_size 8))) (line (pt 0 96)(pt 16 96)) ) (port (pt 0 112) (input) (text "alu_core_V" (rect 0 0 66 14)(font "Arial" (font_size 8))) (text "alu_core_V" (rect 21 107 87 121)(font "Arial" (font_size 8))) (line (pt 0 112)(pt 16 112)) ) (port (pt 0 128) (input) (text "alu_core_S" (rect 0 0 64 14)(font "Arial" (font_size 8))) (text "alu_core_S" (rect 21 123 85 137)(font "Arial" (font_size 8))) (line (pt 0 128)(pt 16 128)) ) (port (pt 0 144) (input) (text "alu_bs_oe" (rect 0 0 59 14)(font "Arial" (font_size 8))) (text "alu_bs_oe" (rect 21 139 80 153)(font "Arial" (font_size 8))) (line (pt 0 144)(pt 16 144)) ) (port (pt 0 160) (input) (text "alu_parity_in" (rect 0 0 71 14)(font "Arial" (font_size 8))) (text "alu_parity_in" (rect 21 155 92 169)(font "Arial" (font_size 8))) (line (pt 0 160)(pt 16 160)) ) (port (pt 0 176) (input) (text "alu_shift_oe" (rect 0 0 69 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(rect 21 411 72 425)(font "Arial" (font_size 8))) (line (pt 0 416)(pt 16 416)(line_width 3)) ) (port (pt 256 32) (output) (text "alu_zero" (rect 0 0 49 14)(font "Arial" (font_size 8))) (text "alu_zero" (rect 186 27 235 41)(font "Arial" (font_size 8))) (line (pt 256 32)(pt 240 32)) ) (port (pt 256 48) (output) (text "alu_parity_out" (rect 0 0 80 14)(font "Arial" (font_size 8))) (text "alu_parity_out" (rect 155 43 235 57)(font "Arial" (font_size 8))) (line (pt 256 48)(pt 240 48)) ) (port (pt 256 64) (output) (text "alu_high_eq_9" (rect 0 0 82 14)(font "Arial" (font_size 8))) (text "alu_high_eq_9" (rect 153 59 235 73)(font "Arial" (font_size 8))) (line (pt 256 64)(pt 240 64)) ) (port (pt 256 80) (output) (text "alu_high_gt_9" (rect 0 0 79 14)(font "Arial" (font_size 8))) (text "alu_high_gt_9" (rect 156 75 235 89)(font "Arial" (font_size 8))) (line (pt 256 80)(pt 240 80)) ) (port (pt 256 96) (output) (text "alu_low_gt_9" (rect 0 0 76 14)(font "Arial" (font_size 8))) (text "alu_low_gt_9" (rect 159 91 235 105)(font "Arial" (font_size 8))) (line (pt 256 96)(pt 240 96)) ) (port (pt 256 112) (output) (text "alu_shift_db0" (rect 0 0 76 14)(font "Arial" (font_size 8))) (text "alu_shift_db0" (rect 159 107 235 121)(font "Arial" (font_size 8))) (line (pt 256 112)(pt 240 112)) ) (port (pt 256 128) (output) (text "alu_shift_db7" (rect 0 0 76 14)(font "Arial" (font_size 8))) (text "alu_shift_db7" (rect 159 123 235 137)(font "Arial" (font_size 8))) (line (pt 256 128)(pt 240 128)) ) (port (pt 256 144) (output) (text "alu_core_cf_out" (rect 0 0 93 14)(font "Arial" (font_size 8))) (text "alu_core_cf_out" (rect 142 139 235 153)(font "Arial" (font_size 8))) (line (pt 256 144)(pt 240 144)) ) (port (pt 256 160) (output) (text "alu_sf_out" (rect 0 0 60 14)(font "Arial" (font_size 8))) (text "alu_sf_out" (rect 175 155 235 169)(font "Arial" (font_size 8))) (line (pt 256 160)(pt 240 160)) ) (port (pt 256 176) (output) (text "alu_yf_out" (rect 0 0 60 14)(font "Arial" (font_size 8))) (text "alu_yf_out" (rect 175 171 235 185)(font "Arial" (font_size 8))) (line (pt 256 176)(pt 240 176)) ) (port (pt 256 192) (output) (text "alu_xf_out" (rect 0 0 60 14)(font "Arial" (font_size 8))) (text "alu_xf_out" (rect 175 187 235 201)(font "Arial" (font_size 8))) (line (pt 256 192)(pt 240 192)) ) (port (pt 256 208) (output) (text "alu_vf_out" (rect 0 0 60 14)(font "Arial" (font_size 8))) (text "alu_vf_out" (rect 175 203 235 217)(font "Arial" (font_size 8))) (line (pt 256 208)(pt 240 208)) ) (port (pt 256 224) (output) (text "test_db_low[3..0]" (rect 0 0 99 14)(font "Arial" (font_size 8))) (text "test_db_low[3..0]" (rect 136 219 235 233)(font "Arial" (font_size 8))) (line (pt 256 224)(pt 240 224)(line_width 3)) ) (port (pt 256 256) (output) (text "test_db_high[3..0]" (rect 0 0 101 14)(font "Arial" (font_size 8))) (text "test_db_high[3..0]" (rect 134 251 235 265)(font "Arial" (font_size 8))) (line (pt 256 256)(pt 240 256)(line_width 3)) ) (port (pt 256 240) (bidir) (text "db[7..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) (text "db[7..0]" (rect 193 235 235 249)(font "Arial" (font_size 8))) (line (pt 256 240)(pt 240 240)(line_width 3)) ) (drawing (rectangle (rect 16 16 240 432)) ) ) ================================================ FILE: cpu/alu/alu.v ================================================ // Copyright (C) 1991-2013 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // PROGRAM "Quartus II 64-Bit" // VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" // CREATED "Fri Nov 07 19:44:45 2014" module alu( alu_core_R, alu_core_V, alu_core_S, alu_bs_oe, alu_parity_in, alu_oe, alu_shift_oe, alu_core_cf_in, alu_op2_oe, alu_op1_oe, alu_res_oe, alu_op1_sel_low, alu_op1_sel_zero, alu_op1_sel_bus, alu_op2_sel_zero, alu_op2_sel_bus, alu_op2_sel_lq, alu_op_low, alu_shift_in, alu_sel_op2_neg, alu_sel_op2_high, alu_shift_left, alu_shift_right, clk, bsel, alu_zero, alu_parity_out, alu_high_eq_9, alu_high_gt_9, alu_low_gt_9, alu_shift_db0, alu_shift_db7, alu_core_cf_out, alu_sf_out, alu_yf_out, alu_xf_out, alu_vf_out, db, test_db_high, test_db_low ); input wire alu_core_R; input wire alu_core_V; input wire alu_core_S; input wire alu_bs_oe; input wire alu_parity_in; input wire alu_oe; input wire alu_shift_oe; input wire alu_core_cf_in; input wire alu_op2_oe; input wire alu_op1_oe; input wire alu_res_oe; input wire alu_op1_sel_low; input wire alu_op1_sel_zero; input wire alu_op1_sel_bus; input wire alu_op2_sel_zero; input wire alu_op2_sel_bus; input wire alu_op2_sel_lq; input wire alu_op_low; input wire alu_shift_in; input wire alu_sel_op2_neg; input wire alu_sel_op2_high; input wire alu_shift_left; input wire alu_shift_right; input wire clk; input wire [2:0] bsel; output wire alu_zero; output wire alu_parity_out; output wire alu_high_eq_9; output wire alu_high_gt_9; output wire alu_low_gt_9; output wire alu_shift_db0; output wire alu_shift_db7; output wire alu_core_cf_out; output wire alu_sf_out; output wire alu_yf_out; output wire alu_xf_out; output wire alu_vf_out; inout wire [7:0] db; output wire [3:0] test_db_high; output wire [3:0] test_db_low; wire [3:0] alu_op1; wire [3:0] alu_op2; wire [3:0] db_high; wire [3:0] db_low; reg [3:0] op1_high; reg [3:0] op1_low; reg [3:0] op2_high; reg [3:0] op2_low; wire [3:0] result_hi; reg [3:0] result_lo; wire [3:0] SYNTHESIZED_WIRE_0; wire [3:0] SYNTHESIZED_WIRE_1; wire [3:0] SYNTHESIZED_WIRE_2; wire [3:0] SYNTHESIZED_WIRE_3; wire SYNTHESIZED_WIRE_35; wire [3:0] SYNTHESIZED_WIRE_5; wire [3:0] SYNTHESIZED_WIRE_7; wire [3:0] SYNTHESIZED_WIRE_8; wire SYNTHESIZED_WIRE_9; wire [3:0] SYNTHESIZED_WIRE_10; wire [3:0] SYNTHESIZED_WIRE_11; wire [3:0] SYNTHESIZED_WIRE_12; wire [3:0] SYNTHESIZED_WIRE_13; wire [3:0] SYNTHESIZED_WIRE_14; wire [3:0] SYNTHESIZED_WIRE_15; wire [3:0] SYNTHESIZED_WIRE_16; wire SYNTHESIZED_WIRE_17; wire [3:0] SYNTHESIZED_WIRE_18; wire SYNTHESIZED_WIRE_36; wire SYNTHESIZED_WIRE_20; wire [3:0] SYNTHESIZED_WIRE_21; wire SYNTHESIZED_WIRE_23; wire [3:0] SYNTHESIZED_WIRE_24; wire SYNTHESIZED_WIRE_37; wire SYNTHESIZED_WIRE_26; wire [3:0] SYNTHESIZED_WIRE_27; wire SYNTHESIZED_WIRE_29; wire SYNTHESIZED_WIRE_30; wire SYNTHESIZED_WIRE_31; wire SYNTHESIZED_WIRE_32; wire [3:0] SYNTHESIZED_WIRE_33; wire [3:0] SYNTHESIZED_WIRE_34; assign db_low[3] = alu_bs_oe ? SYNTHESIZED_WIRE_0[3] : 1'bz; assign db_low[2] = alu_bs_oe ? SYNTHESIZED_WIRE_0[2] : 1'bz; assign db_low[1] = alu_bs_oe ? SYNTHESIZED_WIRE_0[1] : 1'bz; assign db_low[0] = alu_bs_oe ? SYNTHESIZED_WIRE_0[0] : 1'bz; assign db_high[3] = alu_bs_oe ? SYNTHESIZED_WIRE_1[3] : 1'bz; assign db_high[2] = alu_bs_oe ? SYNTHESIZED_WIRE_1[2] : 1'bz; assign db_high[1] = alu_bs_oe ? SYNTHESIZED_WIRE_1[1] : 1'bz; assign db_high[0] = alu_bs_oe ? SYNTHESIZED_WIRE_1[0] : 1'bz; alu_core b2v_core( .cy_in(alu_core_cf_in), .S(alu_core_S), .V(alu_core_V), .R(alu_core_R), .op1(alu_op1), .op2(alu_op2), .cy_out(alu_core_cf_out), .vf_out(alu_vf_out), .result(result_hi)); assign db[3] = alu_oe ? db_low[3] : 1'bz; assign db[2] = alu_oe ? db_low[2] : 1'bz; assign db[1] = alu_oe ? db_low[1] : 1'bz; assign db[0] = alu_oe ? db_low[0] : 1'bz; assign db[7] = alu_oe ? db_high[3] : 1'bz; assign db[6] = alu_oe ? db_high[2] : 1'bz; assign db[5] = alu_oe ? db_high[1] : 1'bz; assign db[4] = alu_oe ? db_high[0] : 1'bz; alu_bit_select b2v_input_bit_select( .bsel(bsel), .bs_out_high(SYNTHESIZED_WIRE_1), .bs_out_low(SYNTHESIZED_WIRE_0)); alu_shifter_core b2v_input_shift( .shift_in(alu_shift_in), .shift_left(alu_shift_left), .shift_right(alu_shift_right), .db(db), .shift_db0(alu_shift_db0), .shift_db7(alu_shift_db7), .out_high(SYNTHESIZED_WIRE_34), .out_low(SYNTHESIZED_WIRE_33)); always@(posedge clk) begin if (alu_op_low) begin result_lo[3:0] <= result_hi[3:0]; end end assign alu_op1 = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_3; assign SYNTHESIZED_WIRE_17 = ~alu_op_low; assign db_low[3] = alu_op2_oe ? op2_low[3] : 1'bz; assign db_low[2] = alu_op2_oe ? op2_low[2] : 1'bz; assign db_low[1] = alu_op2_oe ? op2_low[1] : 1'bz; assign db_low[0] = alu_op2_oe ? op2_low[0] : 1'bz; assign db_high[3] = alu_op2_oe ? op2_high[3] : 1'bz; assign db_high[2] = alu_op2_oe ? op2_high[2] : 1'bz; assign db_high[1] = alu_op2_oe ? op2_high[1] : 1'bz; assign db_high[0] = alu_op2_oe ? op2_high[0] : 1'bz; assign SYNTHESIZED_WIRE_5 = ~op2_low; assign SYNTHESIZED_WIRE_7 = ~op2_high; assign SYNTHESIZED_WIRE_12 = op2_low & {SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_35}; assign SYNTHESIZED_WIRE_11 = {alu_sel_op2_neg,alu_sel_op2_neg,alu_sel_op2_neg,alu_sel_op2_neg} & SYNTHESIZED_WIRE_5; assign SYNTHESIZED_WIRE_14 = op2_high & {SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_35}; assign SYNTHESIZED_WIRE_13 = {alu_sel_op2_neg,alu_sel_op2_neg,alu_sel_op2_neg,alu_sel_op2_neg} & SYNTHESIZED_WIRE_7; assign SYNTHESIZED_WIRE_16 = SYNTHESIZED_WIRE_8 & {SYNTHESIZED_WIRE_9,SYNTHESIZED_WIRE_9,SYNTHESIZED_WIRE_9,SYNTHESIZED_WIRE_9}; assign SYNTHESIZED_WIRE_15 = {alu_sel_op2_high,alu_sel_op2_high,alu_sel_op2_high,alu_sel_op2_high} & SYNTHESIZED_WIRE_10; assign SYNTHESIZED_WIRE_8 = SYNTHESIZED_WIRE_11 | SYNTHESIZED_WIRE_12; assign SYNTHESIZED_WIRE_10 = SYNTHESIZED_WIRE_13 | SYNTHESIZED_WIRE_14; assign alu_op2 = SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16; assign SYNTHESIZED_WIRE_35 = ~alu_sel_op2_neg; assign SYNTHESIZED_WIRE_9 = ~alu_sel_op2_high; assign db_low[3] = alu_res_oe ? result_lo[3] : 1'bz; assign db_low[2] = alu_res_oe ? result_lo[2] : 1'bz; assign db_low[1] = alu_res_oe ? result_lo[1] : 1'bz; assign db_low[0] = alu_res_oe ? result_lo[0] : 1'bz; assign db_high[3] = alu_res_oe ? result_hi[3] : 1'bz; assign db_high[2] = alu_res_oe ? result_hi[2] : 1'bz; assign db_high[1] = alu_res_oe ? result_hi[1] : 1'bz; assign db_high[0] = alu_res_oe ? result_hi[0] : 1'bz; assign SYNTHESIZED_WIRE_3 = op1_low & {alu_op_low,alu_op_low,alu_op_low,alu_op_low}; assign SYNTHESIZED_WIRE_2 = {SYNTHESIZED_WIRE_17,SYNTHESIZED_WIRE_17,SYNTHESIZED_WIRE_17,SYNTHESIZED_WIRE_17} & op1_high; always@(posedge SYNTHESIZED_WIRE_36) begin if (SYNTHESIZED_WIRE_20) begin op1_high[3:0] <= SYNTHESIZED_WIRE_18[3:0]; end end always@(posedge SYNTHESIZED_WIRE_36) begin if (SYNTHESIZED_WIRE_23) begin op1_low[3:0] <= SYNTHESIZED_WIRE_21[3:0]; end end always@(posedge SYNTHESIZED_WIRE_37) begin if (SYNTHESIZED_WIRE_26) begin op2_high[3:0] <= SYNTHESIZED_WIRE_24[3:0]; end end always@(posedge SYNTHESIZED_WIRE_37) begin if (SYNTHESIZED_WIRE_29) begin op2_low[3:0] <= SYNTHESIZED_WIRE_27[3:0]; end end assign db_low[3] = alu_op1_oe ? op1_low[3] : 1'bz; assign db_low[2] = alu_op1_oe ? op1_low[2] : 1'bz; assign db_low[1] = alu_op1_oe ? op1_low[1] : 1'bz; assign db_low[0] = alu_op1_oe ? op1_low[0] : 1'bz; assign db_high[3] = alu_op1_oe ? op1_high[3] : 1'bz; assign db_high[2] = alu_op1_oe ? op1_high[2] : 1'bz; assign db_high[1] = alu_op1_oe ? op1_high[1] : 1'bz; assign db_high[0] = alu_op1_oe ? op1_high[0] : 1'bz; assign SYNTHESIZED_WIRE_36 = ~clk; assign SYNTHESIZED_WIRE_37 = ~clk; alu_mux_2z b2v_op1_latch_mux_high( .sel_a(alu_op1_sel_bus), .sel_zero(alu_op1_sel_zero), .a(db_high), .ena(SYNTHESIZED_WIRE_20), .Q(SYNTHESIZED_WIRE_18)); alu_mux_3z b2v_op1_latch_mux_low( .sel_a(alu_op1_sel_bus), .sel_b(alu_op1_sel_low), .sel_zero(alu_op1_sel_zero), .a(db_low), .b(db_high), .ena(SYNTHESIZED_WIRE_23), .Q(SYNTHESIZED_WIRE_21)); alu_mux_3z b2v_op2_latch_mux_high( .sel_a(alu_op2_sel_bus), .sel_b(alu_op2_sel_lq), .sel_zero(alu_op2_sel_zero), .a(db_high), .b(db_low), .ena(SYNTHESIZED_WIRE_26), .Q(SYNTHESIZED_WIRE_24)); alu_mux_3z b2v_op2_latch_mux_low( .sel_a(alu_op2_sel_bus), .sel_b(alu_op2_sel_lq), .sel_zero(alu_op2_sel_zero), .a(db_low), .b(alu_op1), .ena(SYNTHESIZED_WIRE_29), .Q(SYNTHESIZED_WIRE_27)); assign alu_parity_out = SYNTHESIZED_WIRE_30 ^ result_hi[0]; assign SYNTHESIZED_WIRE_30 = SYNTHESIZED_WIRE_31 ^ result_hi[1]; assign SYNTHESIZED_WIRE_31 = SYNTHESIZED_WIRE_32 ^ result_hi[2]; assign SYNTHESIZED_WIRE_32 = alu_parity_in ^ result_hi[3]; alu_prep_daa b2v_prep_daa( .high(op1_high), .low(op1_low), .low_gt_9(alu_low_gt_9), .high_gt_9(alu_high_gt_9), .high_eq_9(alu_high_eq_9)); assign db_low[3] = alu_shift_oe ? SYNTHESIZED_WIRE_33[3] : 1'bz; assign db_low[2] = alu_shift_oe ? SYNTHESIZED_WIRE_33[2] : 1'bz; assign db_low[1] = alu_shift_oe ? SYNTHESIZED_WIRE_33[1] : 1'bz; assign db_low[0] = alu_shift_oe ? SYNTHESIZED_WIRE_33[0] : 1'bz; assign db_high[3] = alu_shift_oe ? SYNTHESIZED_WIRE_34[3] : 1'bz; assign db_high[2] = alu_shift_oe ? SYNTHESIZED_WIRE_34[2] : 1'bz; assign db_high[1] = alu_shift_oe ? SYNTHESIZED_WIRE_34[1] : 1'bz; assign db_high[0] = alu_shift_oe ? SYNTHESIZED_WIRE_34[0] : 1'bz; assign alu_zero = ~(db_low[2] | db_low[1] | db_low[3] | db_high[1] | db_high[0] | db_high[2] | db_low[0] | db_high[3]); assign alu_sf_out = db_high[3]; assign alu_yf_out = db_high[1]; assign alu_xf_out = db_low[3]; assign test_db_high = db_high; assign test_db_low = db_low; endmodule ================================================ FILE: cpu/alu/alu_bit_select.bdf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "graphic" (version "1.4")) (pin (input) (rect 24 32 200 48) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "bsel[2..0]" (rect 9 0 55 12)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) (line (pt 121 8)(pt 176 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) ) (pin (output) (rect 712 136 888 152) (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) (text "bs_out_low[3..0]" (rect 90 0 170 12)(font "Arial" )) (pt 0 8) (drawing (line (pt 0 8)(pt 52 8)) (line (pt 52 4)(pt 78 4)) (line (pt 52 12)(pt 78 12)) (line (pt 52 12)(pt 52 4)) (line (pt 78 4)(pt 82 8)) (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) ) (pin (output) (rect 720 328 896 344) (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) (text "bs_out_high[3..0]" (rect 90 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13)(font "Arial" ))(text "1.0" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border)) (drawing ) ) ================================================ FILE: cpu/alu/alu_bit_select.bsf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "symbol" (version "1.2")) (symbol (rect 16 16 216 112) (text "alu_bit_select" (rect 5 0 82 14)(font "Arial" (font_size 8))) (text "inst" (rect 8 80 25 92)(font "Arial" )) (port (pt 0 32) (input) (text "bsel[2..0]" (rect 0 0 51 14)(font "Arial" (font_size 8))) (text "bsel[2..0]" (rect 21 27 72 41)(font "Arial" (font_size 8))) (line (pt 0 32)(pt 16 32)(line_width 3)) ) (port (pt 200 32) (output) (text "bs_out_low[3..0]" (rect 0 0 95 14)(font "Arial" (font_size 8))) (text "bs_out_low[3..0]" (rect 84 27 179 41)(font "Arial" (font_size 8))) (line (pt 200 32)(pt 184 32)(line_width 3)) ) (port (pt 200 48) (output) (text "bs_out_high[3..0]" (rect 0 0 97 14)(font "Arial" (font_size 8))) (text "bs_out_high[3..0]" (rect 82 43 179 57)(font "Arial" (font_size 8))) (line (pt 200 48)(pt 184 48)(line_width 3)) ) (drawing (rectangle (rect 16 16 184 80)) ) (fill (color 217 255 255)) ) ================================================ FILE: cpu/alu/alu_bit_select.v ================================================ // Copyright (C) 1991-2013 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // PROGRAM "Quartus II 64-Bit" // VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" // CREATED "Mon Oct 13 12:21:31 2014" module alu_bit_select( bsel, bs_out_high, bs_out_low ); input wire [2:0] bsel; output wire [3:0] bs_out_high; output wire [3:0] bs_out_low; wire [3:0] bs_out_high_ALTERA_SYNTHESIZED; wire [3:0] bs_out_low_ALTERA_SYNTHESIZED; wire SYNTHESIZED_WIRE_12; wire SYNTHESIZED_WIRE_13; wire SYNTHESIZED_WIRE_14; assign bs_out_low_ALTERA_SYNTHESIZED[0] = SYNTHESIZED_WIRE_12 & SYNTHESIZED_WIRE_13 & SYNTHESIZED_WIRE_14; assign bs_out_low_ALTERA_SYNTHESIZED[1] = bsel[0] & SYNTHESIZED_WIRE_13 & SYNTHESIZED_WIRE_14; assign bs_out_low_ALTERA_SYNTHESIZED[2] = SYNTHESIZED_WIRE_12 & bsel[1] & SYNTHESIZED_WIRE_14; assign bs_out_low_ALTERA_SYNTHESIZED[3] = bsel[0] & bsel[1] & SYNTHESIZED_WIRE_14; assign bs_out_high_ALTERA_SYNTHESIZED[0] = SYNTHESIZED_WIRE_12 & SYNTHESIZED_WIRE_13 & bsel[2]; assign bs_out_high_ALTERA_SYNTHESIZED[1] = bsel[0] & SYNTHESIZED_WIRE_13 & bsel[2]; assign bs_out_high_ALTERA_SYNTHESIZED[2] = SYNTHESIZED_WIRE_12 & bsel[1] & bsel[2]; assign bs_out_high_ALTERA_SYNTHESIZED[3] = bsel[0] & bsel[1] & bsel[2]; assign SYNTHESIZED_WIRE_12 = ~bsel[0]; assign SYNTHESIZED_WIRE_13 = ~bsel[1]; assign SYNTHESIZED_WIRE_14 = ~bsel[2]; assign bs_out_high = bs_out_high_ALTERA_SYNTHESIZED; assign bs_out_low = bs_out_low_ALTERA_SYNTHESIZED; endmodule ================================================ FILE: cpu/alu/alu_control.bdf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. 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392)) (junction (pt 264 48)) (junction (pt 376 280)) (junction (pt 320 264)) (junction (pt 232 264)) (junction (pt 320 112)) (junction (pt 288 96)) (junction (pt 264 1168)) (junction (pt 288 1264)) (junction (pt 232 1584)) (junction (pt 400 312)) (junction (pt 520 904)) (junction (pt 600 960)) (junction (pt 600 984)) (junction (pt 600 1064)) (junction (pt 656 960)) (junction (pt 656 984)) (junction (pt 656 880)) (junction (pt 656 904)) (junction (pt 656 936)) (junction (pt 656 1008)) (junction (pt 656 1040)) (junction (pt 240 880)) (junction (pt 416 872)) (junction (pt 520 1008)) (junction (pt 520 1040)) (junction (pt 240 848)) (junction (pt 232 512)) (junction (pt 232 552)) (junction (pt 392 600)) (junction (pt 288 1200)) (text "Bit that is shifted in depends on the opcode:" (rect 576 288 824 302)(font "Arial" (font_size 8))) (text "000 RLC -> old D[7]" (rect 576 304 685 318)(font "Arial" (font_size 8))) (text "001 RRC -> old D[0]" (rect 576 320 686 334)(font "Arial" (font_size 8))) (text "010 RL -> CF" (rect 576 336 650 350)(font "Arial" (font_size 8))) (text "011 RR -> CF" (rect 576 352 651 366)(font "Arial" (font_size 8))) (text "100 SLA -> 0" (rect 576 368 651 382)(font "Arial" (font_size 8))) (text "101 SRA -> D[7]" (rect 576 384 668 398)(font "Arial" (font_size 8))) (text "110 SLL -> 1" (rect 576 400 649 414)(font "Arial" (font_size 8))) (text "111 SRL -> 0" (rect 576 416 650 430)(font "Arial" (font_size 8))) (text "Select cf out based on the shift direction" (rect 560 32 790 46)(font "Arial" (font_size 8))) (text "Low nibble 0x6" (rect 432 832 519 846)(font "Arial" (font_size 8))) (text "High nibble 0x6" (rect 432 912 518 926)(font "Arial" (font_size 8))) (text "Shifter control" (rect 352 16 446 32)(font "Arial" (font_size 10))) (text "DAA + bus(66) logic" (rect 336 768 474 784)(font "Arial" (font_size 10))) (text "Half-parity control" (rect 352 1104 471 1120)(font "Arial" (font_size 10))) (text "Flag condition mux" (rect 440 536 569 552)(font "Arial" (font_size 10))) (text "Parity / Overflow input selector" (rect 336 1328 543 1344)(font "Arial" (font_size 10))) (text "Mux: when op is low, \"1\"; else pf_tmp" (rect 432 1192 647 1206)(font "Arial" (font_size 8))) (text "Carry flag into ALU core" (rect 352 1520 514 1536)(font "Arial" (font_size 10))) (title_block (rect 32 1696 289 1748) (name "title-custom-small") (section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "alu_control" (rect 43 2 118 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border)) (section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "June 28, 2014" (rect 56 3 136 17)(font "Arial" (font_size 8)))(border)) (section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.6" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border)) (drawing ) ) ================================================ FILE: cpu/alu/alu_control.bsf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "symbol" (version "1.2")) (symbol (rect 16 16 248 496) (text "alu_control" (rect 5 0 67 14)(font "Arial" (font_size 8))) (text "inst" (rect 8 464 25 476)(font "Arial" )) (port (pt 0 32) (input) (text "alu_shift_db7" (rect 0 0 76 14)(font "Arial" (font_size 8))) (text "alu_shift_db7" (rect 21 27 97 41)(font "Arial" (font_size 8))) (line (pt 0 32)(pt 16 32)) ) (port (pt 0 48) (input) (text "alu_shift_db0" (rect 0 0 76 14)(font "Arial" (font_size 8))) (text "alu_shift_db0" (rect 21 43 97 57)(font "Arial" (font_size 8))) (line (pt 0 48)(pt 16 48)) ) (port (pt 0 64) (input) (text "ctl_shift_en" (rect 0 0 66 14)(font "Arial" (font_size 8))) (text "ctl_shift_en" (rect 21 59 87 73)(font "Arial" (font_size 8))) (line (pt 0 64)(pt 16 64)) ) (port (pt 0 80) (input) (text "op543[2..0]" (rect 0 0 63 14)(font "Arial" (font_size 8))) (text "op543[2..0]" (rect 21 75 84 89)(font "Arial" (font_size 8))) (line (pt 0 80)(pt 16 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169)(font "Arial" (font_size 8))) (line (pt 232 160)(pt 216 160)) ) (port (pt 232 176) (output) (text "pf_sel" (rect 0 0 35 14)(font "Arial" (font_size 8))) (text "pf_sel" (rect 176 171 211 185)(font "Arial" (font_size 8))) (line (pt 232 176)(pt 216 176)) ) (port (pt 232 192) (output) (text "alu_core_cf_in" (rect 0 0 84 14)(font "Arial" (font_size 8))) (text "alu_core_cf_in" (rect 127 187 211 201)(font "Arial" (font_size 8))) (line (pt 232 192)(pt 216 192)) ) (drawing (rectangle (rect 16 16 216 464)) ) ) ================================================ FILE: cpu/alu/alu_control.v ================================================ // Copyright (C) 1991-2013 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // PROGRAM "Quartus II 64-Bit" // VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" // CREATED "Tue Oct 21 20:41:52 2014" module alu_control( alu_shift_db0, alu_shift_db7, ctl_shift_en, alu_low_gt_9, alu_high_gt_9, alu_high_eq_9, ctl_daa_oe, ctl_alu_op_low, alu_parity_out, flags_cf, flags_zf, flags_pf, flags_sf, ctl_cond_short, alu_vf_out, iff2, ctl_alu_core_hf, ctl_eval_cond, repeat_en, flags_cf_latch, flags_hf2, flags_hf, ctl_66_oe, clk, ctl_pf_sel, op543, alu_shift_in, alu_shift_right, alu_shift_left, shift_cf_out, alu_parity_in, flags_cond_true, daa_cf_out, pf_sel, alu_op_low, alu_core_cf_in, db ); input wire alu_shift_db0; input wire alu_shift_db7; input wire ctl_shift_en; input wire alu_low_gt_9; input wire alu_high_gt_9; input wire alu_high_eq_9; input wire ctl_daa_oe; input wire ctl_alu_op_low; input wire alu_parity_out; input wire flags_cf; input wire flags_zf; input wire flags_pf; input wire flags_sf; input wire ctl_cond_short; input wire alu_vf_out; input wire iff2; input wire ctl_alu_core_hf; input wire ctl_eval_cond; input wire repeat_en; input wire flags_cf_latch; input wire flags_hf2; input wire flags_hf; input wire ctl_66_oe; input wire clk; input wire [1:0] ctl_pf_sel; input wire [2:0] op543; output wire alu_shift_in; output wire alu_shift_right; output wire alu_shift_left; output wire shift_cf_out; output wire alu_parity_in; output reg flags_cond_true; output wire daa_cf_out; output wire pf_sel; output wire alu_op_low; output wire alu_core_cf_in; output wire [7:0] db; wire condition; wire [7:0] out; wire [1:0] sel; wire SYNTHESIZED_WIRE_0; wire SYNTHESIZED_WIRE_1; wire SYNTHESIZED_WIRE_2; reg DFFE_latch_pf_tmp; wire SYNTHESIZED_WIRE_20; wire SYNTHESIZED_WIRE_21; wire SYNTHESIZED_WIRE_7; wire SYNTHESIZED_WIRE_8; wire SYNTHESIZED_WIRE_9; wire SYNTHESIZED_WIRE_10; wire SYNTHESIZED_WIRE_11; wire SYNTHESIZED_WIRE_12; wire SYNTHESIZED_WIRE_13; wire SYNTHESIZED_WIRE_14; wire SYNTHESIZED_WIRE_15; wire SYNTHESIZED_WIRE_16; wire SYNTHESIZED_WIRE_22; wire SYNTHESIZED_WIRE_18; assign alu_op_low = ctl_alu_op_low; assign daa_cf_out = SYNTHESIZED_WIRE_21; assign SYNTHESIZED_WIRE_22 = 0; assign SYNTHESIZED_WIRE_18 = 1; assign condition = SYNTHESIZED_WIRE_0 ^ SYNTHESIZED_WIRE_1; assign db[7] = SYNTHESIZED_WIRE_2 ? out[7] : 1'bz; assign db[6] = SYNTHESIZED_WIRE_2 ? out[6] : 1'bz; assign db[5] = SYNTHESIZED_WIRE_2 ? out[5] : 1'bz; assign db[4] = SYNTHESIZED_WIRE_2 ? out[4] : 1'bz; assign db[3] = SYNTHESIZED_WIRE_2 ? out[3] : 1'bz; assign db[2] = SYNTHESIZED_WIRE_2 ? out[2] : 1'bz; assign db[1] = SYNTHESIZED_WIRE_2 ? out[1] : 1'bz; assign db[0] = SYNTHESIZED_WIRE_2 ? out[0] : 1'bz; assign alu_shift_right = ctl_shift_en & op543[0]; assign alu_parity_in = ctl_alu_op_low | DFFE_latch_pf_tmp; assign SYNTHESIZED_WIRE_2 = ctl_66_oe | ctl_daa_oe; assign sel[0] = op543[1]; assign out[1] = SYNTHESIZED_WIRE_20; assign out[2] = SYNTHESIZED_WIRE_20; assign out[5] = SYNTHESIZED_WIRE_21; assign out[6] = SYNTHESIZED_WIRE_21; assign alu_shift_left = ctl_shift_en & SYNTHESIZED_WIRE_7; assign SYNTHESIZED_WIRE_21 = ctl_66_oe | alu_high_gt_9 | flags_cf_latch | SYNTHESIZED_WIRE_8; assign SYNTHESIZED_WIRE_9 = flags_hf2 | alu_low_gt_9; assign SYNTHESIZED_WIRE_8 = alu_low_gt_9 & alu_high_eq_9; assign SYNTHESIZED_WIRE_20 = SYNTHESIZED_WIRE_9 | ctl_66_oe; assign SYNTHESIZED_WIRE_0 = ~op543[0]; assign sel[1] = op543[2] & SYNTHESIZED_WIRE_10; assign SYNTHESIZED_WIRE_12 = alu_shift_db0 & op543[0]; assign SYNTHESIZED_WIRE_13 = alu_shift_db7 & SYNTHESIZED_WIRE_11; assign shift_cf_out = SYNTHESIZED_WIRE_12 | SYNTHESIZED_WIRE_13; assign SYNTHESIZED_WIRE_16 = ctl_alu_core_hf & flags_hf; assign SYNTHESIZED_WIRE_15 = SYNTHESIZED_WIRE_14 & flags_cf; assign alu_core_cf_in = SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16; assign SYNTHESIZED_WIRE_14 = ~ctl_alu_core_hf; always@(posedge clk) begin if (ctl_eval_cond) begin flags_cond_true <= condition; end end alu_mux_4 b2v_inst_cond_mux( .in0(flags_zf), .in1(flags_cf), .in2(flags_pf), .in3(flags_sf), .sel(sel), .out(SYNTHESIZED_WIRE_1)); alu_mux_4 b2v_inst_pf_sel( .in0(alu_parity_out), .in1(alu_vf_out), .in2(iff2), .in3(repeat_en), .sel(ctl_pf_sel), .out(pf_sel)); alu_mux_8 b2v_inst_shift_mux( .in0(alu_shift_db7), .in1(alu_shift_db0), .in2(flags_cf_latch), .in3(flags_cf_latch), .in4(SYNTHESIZED_WIRE_22), .in5(alu_shift_db7), .in6(SYNTHESIZED_WIRE_18), .in7(SYNTHESIZED_WIRE_22), .sel(op543), .out(alu_shift_in)); always@(posedge clk) begin if (ctl_alu_op_low) begin DFFE_latch_pf_tmp <= alu_parity_out; end end assign SYNTHESIZED_WIRE_7 = ~op543[0]; assign SYNTHESIZED_WIRE_11 = ~op543[0]; assign SYNTHESIZED_WIRE_10 = ~ctl_cond_short; assign out[3] = 0; assign out[7] = 0; assign out[0] = 0; assign out[4] = 0; endmodule ================================================ FILE: cpu/alu/alu_core.bdf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. 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13)(font "Arial" ))(text "alu_core" (rect 43 2 102 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border)) (section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "May 18, 2014" (rect 56 3 132 17)(font "Arial" (font_size 8)))(border)) (section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.2" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border)) (drawing ) ) ================================================ FILE: cpu/alu/alu_core.bsf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "symbol" (version "1.2")) (symbol (rect 16 16 176 176) (text "alu_core" (rect 5 0 54 14)(font "Arial" (font_size 8))) (text "inst" (rect 8 144 25 156)(font "Arial" )) (port (pt 0 32) (input) (text "op1[3..0]" (rect 0 0 49 14)(font "Arial" (font_size 8))) (text "op1[3..0]" (rect 21 27 70 41)(font "Arial" (font_size 8))) (line (pt 0 32)(pt 16 32)(line_width 3)) ) (port (pt 0 48) (input) (text "op2[3..0]" (rect 0 0 49 14)(font "Arial" (font_size 8))) (text "op2[3..0]" (rect 21 43 70 57)(font "Arial" (font_size 8))) (line (pt 0 48)(pt 16 48)(line_width 3)) ) (port (pt 0 64) (input) (text "cy_in" (rect 0 0 30 14)(font "Arial" (font_size 8))) (text "cy_in" (rect 21 59 51 73)(font "Arial" (font_size 8))) (line (pt 0 64)(pt 16 64)) ) (port (pt 0 80) (input) (text "S" (rect 0 0 8 14)(font "Arial" (font_size 8))) (text "S" (rect 21 75 29 89)(font "Arial" (font_size 8))) (line (pt 0 80)(pt 16 80)) ) (port (pt 0 96) (input) (text "V" (rect 0 0 9 14)(font "Arial" (font_size 8))) (text "V" (rect 21 91 30 105)(font "Arial" (font_size 8))) (line (pt 0 96)(pt 16 96)) ) (port (pt 0 112) (input) (text "R" (rect 0 0 8 14)(font "Arial" (font_size 8))) (text "R" (rect 21 107 29 121)(font "Arial" (font_size 8))) (line (pt 0 112)(pt 16 112)) ) (port (pt 160 32) (output) (text "result[3..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) (text "result[3..0]" (rect 79 27 139 41)(font "Arial" (font_size 8))) (line (pt 160 32)(pt 144 32)(line_width 3)) ) (port (pt 160 48) (output) (text "cy_out" (rect 0 0 38 14)(font "Arial" (font_size 8))) (text "cy_out" (rect 101 43 139 57)(font "Arial" (font_size 8))) (line (pt 160 48)(pt 144 48)) ) (port (pt 160 64) (output) (text "vf_out" (rect 0 0 36 14)(font "Arial" (font_size 8))) (text "vf_out" (rect 103 59 139 73)(font "Arial" (font_size 8))) (line (pt 160 64)(pt 144 64)) ) (drawing (rectangle (rect 16 16 144 144)) ) ) ================================================ FILE: cpu/alu/alu_core.v ================================================ // Copyright (C) 1991-2013 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // PROGRAM "Quartus II 64-Bit" // VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" // CREATED "Mon Oct 13 12:17:04 2014" module alu_core( cy_in, S, V, R, op1, op2, cy_out, vf_out, result ); input wire cy_in; input wire S; input wire V; input wire R; input wire [3:0] op1; input wire [3:0] op2; output wire cy_out; output wire vf_out; output wire [3:0] result; wire [3:0] result_ALTERA_SYNTHESIZED; wire SYNTHESIZED_WIRE_0; wire SYNTHESIZED_WIRE_1; wire SYNTHESIZED_WIRE_5; wire SYNTHESIZED_WIRE_3; assign cy_out = SYNTHESIZED_WIRE_3; alu_slice b2v_alu_slice_bit_0( .cy_in(cy_in), .op1(op1[0]), .op2(op2[0]), .S(S), .V(V), .R(R), .result(result_ALTERA_SYNTHESIZED[0]), .cy_out(SYNTHESIZED_WIRE_0)); alu_slice b2v_alu_slice_bit_1( .cy_in(SYNTHESIZED_WIRE_0), .op1(op1[1]), .op2(op2[1]), .S(S), .V(V), .R(R), .result(result_ALTERA_SYNTHESIZED[1]), .cy_out(SYNTHESIZED_WIRE_1)); alu_slice b2v_alu_slice_bit_2( .cy_in(SYNTHESIZED_WIRE_1), .op1(op1[2]), .op2(op2[2]), .S(S), .V(V), .R(R), .result(result_ALTERA_SYNTHESIZED[2]), .cy_out(SYNTHESIZED_WIRE_5)); alu_slice b2v_alu_slice_bit_3( .cy_in(SYNTHESIZED_WIRE_5), .op1(op1[3]), .op2(op2[3]), .S(S), .V(V), .R(R), .result(result_ALTERA_SYNTHESIZED[3]), .cy_out(SYNTHESIZED_WIRE_3)); assign vf_out = SYNTHESIZED_WIRE_3 ^ SYNTHESIZED_WIRE_5; assign result = result_ALTERA_SYNTHESIZED; endmodule ================================================ FILE: cpu/alu/alu_flags.bdf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "graphic" (version "1.4")) (pin (input) (rect 24 32 200 48) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "ctl_flags_oe" (rect 9 0 69 12)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) (line (pt 121 8)(pt 176 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) ) (pin (input) (rect 24 48 200 64) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "ctl_flags_bus" (rect 9 0 75 12)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) (line (pt 121 8)(pt 176 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) ) (pin (input) (rect 24 64 200 80) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 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392 556 408)(font "Arial" (font_size 10))) (text "X Flag" (rect 512 768 554 784)(font "Arial" (font_size 10))) (text "H Flag" (rect 512 528 556 544)(font "Arial" (font_size 10))) (text "Force set" (rect 768 1440 822 1454)(font "Arial" (font_size 8))) (text "Force complement" (rect 856 1448 959 1462)(font "Arial" (font_size 8))) (text "Primary latch" (rect 536 1240 609 1254)(font "Arial" (font_size 8))) (text "Secondary latch" (rect 528 1368 621 1382)(font "Arial" (font_size 8))) (title_block (rect 808 1624 1065 1676) (name "title-custom-small") (section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "June 21, 2014, 2016" (rect 56 3 171 17)(font "Arial" (font_size 8)))(border)) (section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border)) (section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "alu_flags" (rect 43 2 104 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.8" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border)) (drawing ) ) ================================================ FILE: cpu/alu/alu_flags.bsf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "symbol" (version "1.2")) (symbol (rect 16 16 280 560) (text "alu_flags" (rect 5 0 56 14)(font "Arial" (font_size 8))) (text "inst" (rect 8 528 25 540)(font "Arial" )) (port (pt 0 32) (input) (text "ctl_flags_oe" (rect 0 0 69 14)(font "Arial" (font_size 8))) (text "ctl_flags_oe" (rect 21 27 90 41)(font "Arial" (font_size 8))) (line (pt 0 32)(pt 16 32)) ) (port (pt 0 48) (input) (text "ctl_flags_bus" (rect 0 0 76 14)(font "Arial" (font_size 8))) (text "ctl_flags_bus" (rect 21 43 97 57)(font "Arial" (font_size 8))) (line (pt 0 48)(pt 16 48)) ) (port (pt 0 64) (input) (text "ctl_flags_alu" (rect 0 0 71 14)(font "Arial" (font_size 8))) (text "ctl_flags_alu" (rect 21 59 92 73)(font "Arial" (font_size 8))) (line (pt 0 64)(pt 16 64)) ) (port (pt 0 80) (input) (text "alu_sf_out" (rect 0 0 60 14)(font "Arial" (font_size 8))) (text "alu_sf_out" (rect 21 75 81 89)(font "Arial" (font_size 8))) (line (pt 0 80)(pt 16 80)) ) (port (pt 0 96) (input) (text "ctl_flags_sz_we" (rect 0 0 95 14)(font "Arial" (font_size 8))) (text "ctl_flags_sz_we" (rect 21 91 116 105)(font "Arial" (font_size 8))) (line (pt 0 96)(pt 16 96)) ) (port (pt 0 112) (input) (text "alu_zero" (rect 0 0 49 14)(font "Arial" (font_size 8))) (text "alu_zero" (rect 21 107 70 121)(font "Arial" (font_size 8))) (line (pt 0 112)(pt 16 112)) ) (port (pt 0 128) (input) (text "ctl_alu_zero_16bit" (rect 0 0 103 14)(font "Arial" (font_size 8))) (text "ctl_alu_zero_16bit" (rect 21 123 124 137)(font "Arial" (font_size 8))) (line (pt 0 128)(pt 16 128)) ) (port (pt 0 144) (input) (text "alu_yf_out" (rect 0 0 60 14)(font "Arial" (font_size 8))) (text "alu_yf_out" (rect 21 139 81 153)(font "Arial" (font_size 8))) (line (pt 0 144)(pt 16 144)) ) (port (pt 0 160) (input) (text "ctl_flags_xy_we" (rect 0 0 95 14)(font "Arial" (font_size 8))) (text "ctl_flags_xy_we" (rect 21 155 116 169)(font "Arial" (font_size 8))) (line (pt 0 160)(pt 16 160)) ) (port (pt 0 176) (input) (text "ctl_flags_hf_we" (rect 0 0 93 14)(font "Arial" (font_size 8))) (text "ctl_flags_hf_we" (rect 21 171 114 185)(font "Arial" (font_size 8))) (line (pt 0 176)(pt 16 176)) ) (port (pt 0 192) (input) (text "ctl_flags_hf_cpl" (rect 0 0 90 14)(font "Arial" (font_size 8))) (text "ctl_flags_hf_cpl" (rect 21 187 111 201)(font "Arial" (font_size 8))) (line (pt 0 192)(pt 16 192)) ) (port (pt 0 208) (input) (text "ctl_flags_hf2_we" (rect 0 0 100 14)(font "Arial" (font_size 8))) (text "ctl_flags_hf2_we" (rect 21 203 121 217)(font "Arial" (font_size 8))) (line (pt 0 208)(pt 16 208)) ) (port (pt 0 224) (input) (text "alu_xf_out" (rect 0 0 60 14)(font "Arial" (font_size 8))) (text "alu_xf_out" (rect 21 219 81 233)(font "Arial" (font_size 8))) (line (pt 0 224)(pt 16 224)) ) (port (pt 0 240) (input) (text "pf_sel" (rect 0 0 35 14)(font "Arial" (font_size 8))) (text "pf_sel" (rect 21 235 56 249)(font "Arial" (font_size 8))) (line (pt 0 240)(pt 16 240)) ) (port (pt 0 256) (input) (text "ctl_flags_pf_we" (rect 0 0 93 14)(font "Arial" (font_size 8))) (text "ctl_flags_pf_we" (rect 21 251 114 265)(font "Arial" (font_size 8))) (line (pt 0 256)(pt 16 256)) ) (port (pt 0 272) (input) (text "ctl_flags_nf_set" (rect 0 0 92 14)(font "Arial" (font_size 8))) (text "ctl_flags_nf_set" (rect 21 267 113 281)(font "Arial" (font_size 8))) (line (pt 0 272)(pt 16 272)) ) (port (pt 0 288) (input) (text "ctl_flags_nf_clr" (rect 0 0 88 14)(font "Arial" (font_size 8))) (text "ctl_flags_nf_clr" (rect 21 283 109 297)(font "Arial" (font_size 8))) (line (pt 0 288)(pt 16 288)) ) (port (pt 0 304) (input) (text "ctl_flags_nf_we" (rect 0 0 93 14)(font "Arial" (font_size 8))) (text "ctl_flags_nf_we" (rect 21 299 114 313)(font "Arial" (font_size 8))) (line (pt 0 304)(pt 16 304)) ) (port (pt 0 320) (input) (text "alu_core_cf_out" (rect 0 0 93 14)(font "Arial" (font_size 8))) (text "alu_core_cf_out" (rect 21 315 114 329)(font "Arial" (font_size 8))) (line (pt 0 320)(pt 16 320)) ) (port (pt 0 336) (input) (text "ctl_flags_cf_we" (rect 0 0 93 14)(font "Arial" (font_size 8))) (text "ctl_flags_cf_we" (rect 21 331 114 345)(font "Arial" (font_size 8))) (line (pt 0 336)(pt 16 336)) ) (port (pt 0 352) (input) (text "ctl_flags_cf2_we" (rect 0 0 100 14)(font "Arial" (font_size 8))) (text "ctl_flags_cf2_we" (rect 21 347 121 361)(font "Arial" (font_size 8))) (line (pt 0 352)(pt 16 352)) ) (port (pt 0 368) (input) (text "ctl_flags_cf2_sel_shift" (rect 0 0 129 14)(font "Arial" (font_size 8))) (text "ctl_flags_cf2_sel_shift" (rect 21 363 150 377)(font "Arial" (font_size 8))) (line (pt 0 368)(pt 16 368)) ) (port (pt 0 384) (input) (text "ctl_flags_cf2_sel_daa" (rect 0 0 126 14)(font "Arial" (font_size 8))) (text "ctl_flags_cf2_sel_daa" (rect 21 379 147 393)(font "Arial" (font_size 8))) (line (pt 0 384)(pt 16 384)) ) (port (pt 0 400) (input) (text "shift_cf_out" (rect 0 0 68 14)(font "Arial" (font_size 8))) (text "shift_cf_out" (rect 21 395 89 409)(font "Arial" (font_size 8))) (line (pt 0 400)(pt 16 400)) ) (port (pt 0 416) (input) (text "daa_cf_out" (rect 0 0 64 14)(font "Arial" (font_size 8))) (text "daa_cf_out" (rect 21 411 85 425)(font "Arial" (font_size 8))) (line (pt 0 416)(pt 16 416)) ) (port (pt 0 432) (input) (text "clk" (rect 0 0 15 14)(font "Arial" (font_size 8))) (text "clk" (rect 21 427 36 441)(font "Arial" (font_size 8))) (line (pt 0 432)(pt 16 432)) ) (port (pt 0 448) (input) (text "ctl_flags_use_cf2" (rect 0 0 102 14)(font "Arial" (font_size 8))) (text "ctl_flags_use_cf2" (rect 21 443 123 457)(font "Arial" (font_size 8))) (line (pt 0 448)(pt 16 448)) ) (port (pt 0 464) (input) (text "ctl_flags_cf_set" (rect 0 0 92 14)(font "Arial" (font_size 8))) (text "ctl_flags_cf_set" (rect 21 459 113 473)(font "Arial" (font_size 8))) (line (pt 0 464)(pt 16 464)) ) (port (pt 0 480) (input) (text "ctl_flags_cf_cpl" (rect 0 0 90 14)(font "Arial" (font_size 8))) (text "ctl_flags_cf_cpl" (rect 21 475 111 489)(font "Arial" (font_size 8))) (line (pt 0 480)(pt 16 480)) ) (port (pt 0 496) (input) (text "nhold_clk_wait" (rect 0 0 84 14)(font "Arial" (font_size 8))) (text "nhold_clk_wait" (rect 21 491 105 505)(font "Arial" (font_size 8))) (line (pt 0 496)(pt 16 496)) ) (port (pt 264 48) (output) (text "flags_sf" (rect 0 0 47 14)(font "Arial" (font_size 8))) (text "flags_sf" (rect 196 43 243 57)(font "Arial" (font_size 8))) (line (pt 264 48)(pt 248 48)) ) (port (pt 264 64) (output) (text "flags_zf" (rect 0 0 47 14)(font "Arial" (font_size 8))) (text "flags_zf" (rect 196 59 243 73)(font "Arial" (font_size 8))) (line (pt 264 64)(pt 248 64)) ) (port (pt 264 80) (output) (text "flags_hf" (rect 0 0 47 14)(font "Arial" (font_size 8))) (text "flags_hf" (rect 196 75 243 89)(font "Arial" (font_size 8))) (line (pt 264 80)(pt 248 80)) ) (port (pt 264 96) (output) (text "flags_hf2" (rect 0 0 54 14)(font "Arial" (font_size 8))) (text "flags_hf2" (rect 189 91 243 105)(font "Arial" (font_size 8))) (line (pt 264 96)(pt 248 96)) ) (port (pt 264 112) (output) (text "flags_pf" (rect 0 0 47 14)(font "Arial" (font_size 8))) (text "flags_pf" (rect 196 107 243 121)(font "Arial" (font_size 8))) (line (pt 264 112)(pt 248 112)) ) (port (pt 264 128) (output) (text "flags_nf" (rect 0 0 47 14)(font "Arial" (font_size 8))) (text "flags_nf" (rect 196 123 243 137)(font "Arial" (font_size 8))) (line (pt 264 128)(pt 248 128)) ) (port (pt 264 144) (output) (text "flags_cf_latch" (rect 0 0 81 14)(font "Arial" (font_size 8))) (text "flags_cf_latch" (rect 162 139 243 153)(font "Arial" (font_size 8))) (line (pt 264 144)(pt 248 144)) ) (port (pt 264 160) (output) (text "flags_cf" (rect 0 0 47 14)(font "Arial" (font_size 8))) (text "flags_cf" (rect 196 155 243 169)(font "Arial" (font_size 8))) (line (pt 264 160)(pt 248 160)) ) (port (pt 264 32) (bidir) (text "db[7..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) (text "db[7..0]" (rect 201 27 243 41)(font "Arial" (font_size 8))) (line (pt 264 32)(pt 248 32)(line_width 3)) ) (drawing (rectangle (rect 16 16 248 528)) ) ) ================================================ FILE: cpu/alu/alu_flags.v ================================================ // Copyright (C) 1991-2013 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // PROGRAM "Quartus II 64-Bit" // VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" // CREATED "Sat Dec 10 09:01:30 2016" module alu_flags( ctl_flags_oe, ctl_flags_bus, ctl_flags_alu, alu_sf_out, alu_yf_out, alu_xf_out, ctl_flags_nf_set, alu_zero, shift_cf_out, alu_core_cf_out, daa_cf_out, ctl_flags_cf_set, ctl_flags_cf_cpl, pf_sel, ctl_flags_cf_we, ctl_flags_sz_we, ctl_flags_xy_we, ctl_flags_hf_we, ctl_flags_pf_we, ctl_flags_nf_we, ctl_flags_cf2_we, ctl_flags_hf_cpl, ctl_flags_use_cf2, ctl_flags_hf2_we, ctl_flags_nf_clr, ctl_alu_zero_16bit, clk, ctl_flags_cf2_sel_shift, ctl_flags_cf2_sel_daa, nhold_clk_wait, flags_sf, flags_zf, flags_hf, flags_pf, flags_cf, flags_nf, flags_cf_latch, flags_hf2, db ); input wire ctl_flags_oe; input wire ctl_flags_bus; input wire ctl_flags_alu; input wire alu_sf_out; input wire alu_yf_out; input wire alu_xf_out; input wire ctl_flags_nf_set; input wire alu_zero; input wire shift_cf_out; input wire alu_core_cf_out; input wire daa_cf_out; input wire ctl_flags_cf_set; input wire ctl_flags_cf_cpl; input wire pf_sel; input wire ctl_flags_cf_we; input wire ctl_flags_sz_we; input wire ctl_flags_xy_we; input wire ctl_flags_hf_we; input wire ctl_flags_pf_we; input wire ctl_flags_nf_we; input wire ctl_flags_cf2_we; input wire ctl_flags_hf_cpl; input wire ctl_flags_use_cf2; input wire ctl_flags_hf2_we; input wire ctl_flags_nf_clr; input wire ctl_alu_zero_16bit; input wire clk; input wire ctl_flags_cf2_sel_shift; input wire ctl_flags_cf2_sel_daa; input wire nhold_clk_wait; output wire flags_sf; output wire flags_zf; output wire flags_hf; output wire flags_pf; output wire flags_cf; output wire flags_nf; output wire flags_cf_latch; output reg flags_hf2; inout wire [7:0] db; reg flags_xf; reg flags_yf; wire [1:0] sel; reg DFFE_inst_latch_hf; wire SYNTHESIZED_WIRE_0; wire SYNTHESIZED_WIRE_1; wire SYNTHESIZED_WIRE_2; wire SYNTHESIZED_WIRE_3; wire SYNTHESIZED_WIRE_4; wire SYNTHESIZED_WIRE_5; wire SYNTHESIZED_WIRE_6; wire SYNTHESIZED_WIRE_7; reg SYNTHESIZED_WIRE_39; wire SYNTHESIZED_WIRE_8; wire SYNTHESIZED_WIRE_9; wire SYNTHESIZED_WIRE_10; wire SYNTHESIZED_WIRE_11; wire SYNTHESIZED_WIRE_12; wire SYNTHESIZED_WIRE_13; wire SYNTHESIZED_WIRE_14; wire SYNTHESIZED_WIRE_15; wire SYNTHESIZED_WIRE_16; wire SYNTHESIZED_WIRE_17; wire SYNTHESIZED_WIRE_18; wire SYNTHESIZED_WIRE_19; wire SYNTHESIZED_WIRE_20; wire SYNTHESIZED_WIRE_21; wire SYNTHESIZED_WIRE_22; reg DFFE_inst_latch_sf; wire SYNTHESIZED_WIRE_23; reg DFFE_inst_latch_pf; reg DFFE_inst_latch_nf; wire SYNTHESIZED_WIRE_24; wire SYNTHESIZED_WIRE_25; wire SYNTHESIZED_WIRE_26; wire SYNTHESIZED_WIRE_27; wire SYNTHESIZED_WIRE_28; wire SYNTHESIZED_WIRE_29; wire SYNTHESIZED_WIRE_40; wire SYNTHESIZED_WIRE_32; wire SYNTHESIZED_WIRE_33; wire SYNTHESIZED_WIRE_34; wire SYNTHESIZED_WIRE_35; wire SYNTHESIZED_WIRE_36; wire SYNTHESIZED_WIRE_37; reg DFFE_inst_latch_cf; reg DFFE_inst_latch_cf2; wire SYNTHESIZED_WIRE_38; assign flags_sf = DFFE_inst_latch_sf; assign flags_zf = SYNTHESIZED_WIRE_39; assign flags_hf = SYNTHESIZED_WIRE_23; assign flags_pf = DFFE_inst_latch_pf; assign flags_cf = SYNTHESIZED_WIRE_24; assign flags_nf = DFFE_inst_latch_nf; assign flags_cf_latch = DFFE_inst_latch_cf; assign SYNTHESIZED_WIRE_38 = 0; assign SYNTHESIZED_WIRE_10 = db[7] & ctl_flags_bus; assign SYNTHESIZED_WIRE_17 = alu_xf_out & ctl_flags_alu; assign SYNTHESIZED_WIRE_20 = db[2] & ctl_flags_bus; assign SYNTHESIZED_WIRE_19 = pf_sel & ctl_flags_alu; assign SYNTHESIZED_WIRE_2 = db[1] & ctl_flags_bus; assign SYNTHESIZED_WIRE_23 = DFFE_inst_latch_hf ^ ctl_flags_hf_cpl; assign SYNTHESIZED_WIRE_22 = db[0] & ctl_flags_bus; assign SYNTHESIZED_WIRE_21 = ctl_flags_alu & alu_core_cf_out; assign SYNTHESIZED_WIRE_8 = ~ctl_flags_cf2_we; assign SYNTHESIZED_WIRE_24 = SYNTHESIZED_WIRE_0 ^ ctl_flags_cf_cpl; assign SYNTHESIZED_WIRE_1 = alu_sf_out & ctl_flags_alu; assign SYNTHESIZED_WIRE_9 = alu_sf_out & ctl_flags_alu; assign SYNTHESIZED_WIRE_5 = ctl_flags_nf_set | SYNTHESIZED_WIRE_1 | SYNTHESIZED_WIRE_2; assign SYNTHESIZED_WIRE_37 = SYNTHESIZED_WIRE_3 & SYNTHESIZED_WIRE_4; assign SYNTHESIZED_WIRE_32 = SYNTHESIZED_WIRE_5 & SYNTHESIZED_WIRE_6; assign SYNTHESIZED_WIRE_6 = ~ctl_flags_nf_clr; assign SYNTHESIZED_WIRE_7 = ~ctl_alu_zero_16bit; assign SYNTHESIZED_WIRE_4 = SYNTHESIZED_WIRE_7 | SYNTHESIZED_WIRE_39; assign SYNTHESIZED_WIRE_27 = ctl_flags_cf_we & nhold_clk_wait & SYNTHESIZED_WIRE_8; assign SYNTHESIZED_WIRE_29 = ctl_flags_cf2_we & nhold_clk_wait; assign SYNTHESIZED_WIRE_12 = db[6] & ctl_flags_bus; assign SYNTHESIZED_WIRE_34 = SYNTHESIZED_WIRE_9 | SYNTHESIZED_WIRE_10; assign SYNTHESIZED_WIRE_3 = SYNTHESIZED_WIRE_11 | SYNTHESIZED_WIRE_12; assign SYNTHESIZED_WIRE_36 = SYNTHESIZED_WIRE_13 | SYNTHESIZED_WIRE_14; assign SYNTHESIZED_WIRE_40 = SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16; assign SYNTHESIZED_WIRE_35 = SYNTHESIZED_WIRE_17 | SYNTHESIZED_WIRE_18; assign SYNTHESIZED_WIRE_33 = SYNTHESIZED_WIRE_19 | SYNTHESIZED_WIRE_20; assign SYNTHESIZED_WIRE_11 = alu_zero & ctl_flags_alu; assign SYNTHESIZED_WIRE_26 = SYNTHESIZED_WIRE_21 | SYNTHESIZED_WIRE_22; assign db[7] = ctl_flags_oe ? DFFE_inst_latch_sf : 1'bz; assign SYNTHESIZED_WIRE_14 = db[5] & ctl_flags_bus; assign db[6] = ctl_flags_oe ? SYNTHESIZED_WIRE_39 : 1'bz; assign db[5] = ctl_flags_oe ? flags_yf : 1'bz; assign db[4] = ctl_flags_oe ? SYNTHESIZED_WIRE_23 : 1'bz; assign db[3] = ctl_flags_oe ? flags_xf : 1'bz; assign db[2] = ctl_flags_oe ? DFFE_inst_latch_pf : 1'bz; assign db[1] = ctl_flags_oe ? DFFE_inst_latch_nf : 1'bz; assign db[0] = ctl_flags_oe ? SYNTHESIZED_WIRE_24 : 1'bz; assign SYNTHESIZED_WIRE_13 = alu_yf_out & ctl_flags_alu; assign SYNTHESIZED_WIRE_0 = ctl_flags_cf_set | SYNTHESIZED_WIRE_25; assign SYNTHESIZED_WIRE_16 = db[4] & ctl_flags_bus; assign SYNTHESIZED_WIRE_15 = alu_core_cf_out & ctl_flags_alu; assign SYNTHESIZED_WIRE_18 = db[3] & ctl_flags_bus; always@(posedge clk) begin if (SYNTHESIZED_WIRE_27) begin DFFE_inst_latch_cf <= SYNTHESIZED_WIRE_26; end end always@(posedge clk) begin if (SYNTHESIZED_WIRE_29) begin DFFE_inst_latch_cf2 <= SYNTHESIZED_WIRE_28; end end always@(posedge clk) begin if (ctl_flags_hf_we) begin DFFE_inst_latch_hf <= SYNTHESIZED_WIRE_40; end end always@(posedge clk) begin if (ctl_flags_hf2_we) begin flags_hf2 <= SYNTHESIZED_WIRE_40; end end always@(posedge clk) begin if (ctl_flags_nf_we) begin DFFE_inst_latch_nf <= SYNTHESIZED_WIRE_32; end end always@(posedge clk) begin if (ctl_flags_pf_we) begin DFFE_inst_latch_pf <= SYNTHESIZED_WIRE_33; end end always@(posedge clk) begin if (ctl_flags_sz_we) begin DFFE_inst_latch_sf <= SYNTHESIZED_WIRE_34; end end always@(posedge clk) begin if (ctl_flags_xy_we) begin flags_xf <= SYNTHESIZED_WIRE_35; end end always@(posedge clk) begin if (ctl_flags_xy_we) begin flags_yf <= SYNTHESIZED_WIRE_36; end end always@(posedge clk) begin if (ctl_flags_sz_we) begin SYNTHESIZED_WIRE_39 <= SYNTHESIZED_WIRE_37; end end alu_mux_2 b2v_inst_mux_cf( .in0(DFFE_inst_latch_cf), .in1(DFFE_inst_latch_cf2), .sel1(ctl_flags_use_cf2), .out(SYNTHESIZED_WIRE_25)); alu_mux_4 b2v_inst_mux_cf2( .in0(alu_core_cf_out), .in1(shift_cf_out), .in2(daa_cf_out), .in3(SYNTHESIZED_WIRE_38), .sel(sel), .out(SYNTHESIZED_WIRE_28)); assign sel[0] = ctl_flags_cf2_sel_shift; assign sel[1] = ctl_flags_cf2_sel_daa; endmodule ================================================ FILE: cpu/alu/alu_mux_2.bdf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "graphic" (version "1.4")) (pin (input) (rect 32 104 208 120) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "sel1" (rect 9 0 29 12)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) (line (pt 121 8)(pt 176 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) ) (pin (input) (rect 32 88 208 104) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "in1" (rect 9 0 23 12)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) (line (pt 121 8)(pt 176 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) ) (pin (input) (rect 32 40 208 56) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "in0" 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256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.0" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border)) (drawing ) ) ================================================ FILE: cpu/alu/alu_mux_2.bsf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "symbol" (version "1.2")) (symbol (rect 16 16 112 112) (text "alu_mux_2" (rect 5 0 66 14)(font "Arial" (font_size 8))) (text "inst" (rect 8 80 25 92)(font "Arial" )) (port (pt 0 32) (input) (text "in0" (rect 0 0 16 14)(font "Arial" (font_size 8))) (text "in0" (rect 21 27 37 41)(font "Arial" (font_size 8))) (line (pt 0 32)(pt 16 32)) ) (port (pt 0 48) (input) (text "in1" (rect 0 0 16 14)(font "Arial" (font_size 8))) (text "in1" (rect 21 43 37 57)(font "Arial" (font_size 8))) (line (pt 0 48)(pt 16 48)) ) (port (pt 0 64) (input) (text "sel1" (rect 0 0 23 14)(font "Arial" (font_size 8))) (text "sel1" (rect 21 59 44 73)(font "Arial" (font_size 8))) (line (pt 0 64)(pt 16 64)) ) (port (pt 96 32) (output) (text "out" (rect 0 0 17 14)(font "Arial" (font_size 8))) (text "out" (rect 58 27 75 41)(font "Arial" (font_size 8))) (line (pt 96 32)(pt 80 32)) ) (drawing (rectangle (rect 16 16 80 80)) ) ) ================================================ FILE: cpu/alu/alu_mux_2.v ================================================ // Copyright (C) 1991-2013 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // PROGRAM "Quartus II 64-Bit" // VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" // CREATED "Mon Oct 13 12:10:35 2014" module alu_mux_2( sel1, in1, in0, out ); input wire sel1; input wire in1; input wire in0; output wire out; wire SYNTHESIZED_WIRE_0; wire SYNTHESIZED_WIRE_1; wire SYNTHESIZED_WIRE_2; assign SYNTHESIZED_WIRE_2 = in0 & SYNTHESIZED_WIRE_0; assign SYNTHESIZED_WIRE_1 = in1 & sel1; assign out = SYNTHESIZED_WIRE_1 | SYNTHESIZED_WIRE_2; assign SYNTHESIZED_WIRE_0 = ~sel1; endmodule ================================================ FILE: cpu/alu/alu_mux_2z.bdf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. 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15 62 27)(font "Courier New" (bold))(invisible)) (line (pt 48 24)(pt 64 24)) ) (drawing (line (pt 14 36)(pt 25 36)) (line (pt 14 13)(pt 25 13)) (arc (pt 7 29)(pt 7 19)(rect -14 8 19 41)) (arc (pt 49 24)(pt 25 13)(rect -6 13 57 76)) (arc (pt 25 35)(pt 49 24)(rect -6 -27 57 36)) ) ) (connector (pt 368 64) (pt 392 64) ) (connector (pt 344 48) (pt 392 48) (bus) ) (connector (pt 456 56) (pt 480 56) (bus) ) (connector (pt 200 40) (pt 280 40) (bus) ) (connector (pt 456 152) (pt 480 152) ) (connector (pt 368 64) (pt 368 104) ) (connector (pt 368 104) (pt 344 104) ) (connector (pt 232 56) (pt 232 160) ) (connector (pt 200 56) (pt 232 56) ) (connector (pt 232 56) (pt 280 56) ) (connector (pt 232 160) (pt 392 160) ) (connector (pt 264 104) (pt 264 144) ) (connector (pt 264 144) (pt 392 144) ) (connector (pt 200 104) (pt 264 104) ) (connector (pt 264 104) (pt 296 104) ) (junction (pt 232 56)) (junction (pt 264 104)) (title_block (rect 24 192 281 244) (name "title-custom-small") (section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "alu_mux_2z" (rect 43 2 124 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border)) (section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "May 18, 2014" (rect 56 3 132 17)(font "Arial" (font_size 8)))(border)) (section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.2" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border)) (drawing ) ) ================================================ FILE: cpu/alu/alu_mux_2z.bsf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "symbol" (version "1.2")) (symbol (rect 16 16 160 112) (text "alu_mux_2z" (rect 5 0 73 14)(font "Arial" (font_size 8))) (text "inst" (rect 8 80 25 92)(font "Arial" )) (port (pt 0 32) (input) (text "a[3..0]" (rect 0 0 35 14)(font "Arial" (font_size 8))) (text "a[3..0]" (rect 21 27 56 41)(font "Arial" (font_size 8))) (line (pt 0 32)(pt 16 32)(line_width 3)) ) (port (pt 0 48) (input) (text "sel_a" (rect 0 0 30 14)(font "Arial" (font_size 8))) (text "sel_a" (rect 21 43 51 57)(font "Arial" (font_size 8))) (line (pt 0 48)(pt 16 48)) ) (port (pt 0 64) (input) (text "sel_zero" (rect 0 0 49 14)(font "Arial" (font_size 8))) (text "sel_zero" (rect 21 59 70 73)(font "Arial" (font_size 8))) (line (pt 0 64)(pt 16 64)) ) (port (pt 144 32) (output) (text "Q[3..0]" (rect 0 0 37 14)(font "Arial" (font_size 8))) (text "Q[3..0]" (rect 86 27 123 41)(font "Arial" (font_size 8))) (line (pt 144 32)(pt 128 32)(line_width 3)) ) (port (pt 144 48) (output) (text "ena" (rect 0 0 21 14)(font "Arial" (font_size 8))) (text "ena" (rect 102 43 123 57)(font "Arial" (font_size 8))) (line (pt 144 48)(pt 128 48)) ) (drawing (rectangle (rect 16 16 128 80)) ) ) ================================================ FILE: cpu/alu/alu_mux_2z.v ================================================ // Copyright (C) 1991-2013 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // PROGRAM "Quartus II 64-Bit" // VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" // CREATED "Fri Oct 31 21:18:33 2014" module alu_mux_2z( sel_a, sel_zero, a, ena, Q ); input wire sel_a; input wire sel_zero; input wire [3:0] a; output wire ena; output wire [3:0] Q; wire [3:0] SYNTHESIZED_WIRE_0; wire SYNTHESIZED_WIRE_1; assign SYNTHESIZED_WIRE_0 = a & {sel_a,sel_a,sel_a,sel_a}; assign ena = sel_a | sel_zero; assign Q = SYNTHESIZED_WIRE_0 & {SYNTHESIZED_WIRE_1,SYNTHESIZED_WIRE_1,SYNTHESIZED_WIRE_1,SYNTHESIZED_WIRE_1}; assign SYNTHESIZED_WIRE_1 = ~sel_zero; endmodule ================================================ FILE: cpu/alu/alu_mux_3z.bdf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. 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cpu/alu/alu_mux_3z.bsf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "symbol" (version "1.2")) (symbol (rect 16 16 160 144) (text "alu_mux_3z" (rect 5 0 73 14)(font "Arial" (font_size 8))) (text "inst" (rect 8 112 25 124)(font "Arial" )) (port (pt 0 32) (input) (text "a[3..0]" (rect 0 0 35 14)(font "Arial" (font_size 8))) (text "a[3..0]" (rect 21 27 56 41)(font "Arial" (font_size 8))) (line (pt 0 32)(pt 16 32)(line_width 3)) ) (port (pt 0 48) (input) (text "sel_a" (rect 0 0 30 14)(font "Arial" (font_size 8))) (text "sel_a" (rect 21 43 51 57)(font "Arial" (font_size 8))) (line (pt 0 48)(pt 16 48)) ) (port (pt 0 64) (input) (text "b[3..0]" (rect 0 0 35 14)(font "Arial" (font_size 8))) (text "b[3..0]" (rect 21 59 56 73)(font "Arial" (font_size 8))) (line (pt 0 64)(pt 16 64)(line_width 3)) ) (port (pt 0 80) (input) (text "sel_b" (rect 0 0 30 14)(font "Arial" (font_size 8))) (text "sel_b" (rect 21 75 51 89)(font "Arial" (font_size 8))) (line (pt 0 80)(pt 16 80)) ) (port (pt 0 96) (input) (text "sel_zero" (rect 0 0 49 14)(font "Arial" (font_size 8))) (text "sel_zero" (rect 21 91 70 105)(font "Arial" (font_size 8))) (line (pt 0 96)(pt 16 96)) ) (port (pt 144 32) (output) (text "Q[3..0]" (rect 0 0 37 14)(font "Arial" (font_size 8))) (text "Q[3..0]" (rect 86 27 123 41)(font "Arial" (font_size 8))) (line (pt 144 32)(pt 128 32)(line_width 3)) ) (port (pt 144 48) (output) (text "ena" (rect 0 0 21 14)(font "Arial" (font_size 8))) (text "ena" (rect 102 43 123 57)(font "Arial" (font_size 8))) (line (pt 144 48)(pt 128 48)) ) (drawing (rectangle (rect 16 16 128 112)) ) ) ================================================ FILE: cpu/alu/alu_mux_3z.v ================================================ // Copyright (C) 1991-2013 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // PROGRAM "Quartus II 64-Bit" // VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" // CREATED "Fri Oct 31 21:08:42 2014" module alu_mux_3z( sel_zero, sel_a, sel_b, a, b, ena, Q ); input wire sel_zero; input wire sel_a; input wire sel_b; input wire [3:0] a; input wire [3:0] b; output wire ena; output wire [3:0] Q; wire [3:0] SYNTHESIZED_WIRE_0; wire SYNTHESIZED_WIRE_1; wire [3:0] SYNTHESIZED_WIRE_2; wire [3:0] SYNTHESIZED_WIRE_3; assign SYNTHESIZED_WIRE_3 = a & {sel_a,sel_a,sel_a,sel_a}; assign Q = SYNTHESIZED_WIRE_0 & {SYNTHESIZED_WIRE_1,SYNTHESIZED_WIRE_1,SYNTHESIZED_WIRE_1,SYNTHESIZED_WIRE_1}; assign SYNTHESIZED_WIRE_1 = ~sel_zero; assign SYNTHESIZED_WIRE_0 = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_3; assign ena = sel_a | sel_b | sel_zero; assign SYNTHESIZED_WIRE_2 = b & {sel_b,sel_b,sel_b,sel_b}; endmodule ================================================ FILE: cpu/alu/alu_mux_4.bdf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. 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(bus) ) (connector (pt 208 200) (pt 376 200) ) (connector (pt 208 248) (pt 376 248) ) (connector (pt 208 296) (pt 376 296) ) (connector (pt 208 344) (pt 376 344) ) (junction (pt 328 40)) (junction (pt 304 40)) (junction (pt 280 40)) (junction (pt 280 192)) (junction (pt 328 184)) (junction (pt 352 232)) (junction (pt 304 288)) (title_block (rect 32 392 289 444) (name "title-custom-small") (section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "June 21, 2014" (rect 56 3 136 17)(font "Arial" (font_size 8)))(border)) (section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border)) (section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "alu_mux_4" (rect 43 2 117 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 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File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "symbol" (version "1.2")) (symbol (rect 16 16 128 144) (text "alu_mux_4" (rect 5 0 66 14)(font "Arial" (font_size 8))) (text "inst" (rect 8 112 25 124)(font "Arial" )) (port (pt 0 32) (input) (text "sel[1..0]" (rect 0 0 44 14)(font "Arial" (font_size 8))) (text "sel[1..0]" (rect 21 27 65 41)(font "Arial" (font_size 8))) (line (pt 0 32)(pt 16 32)(line_width 3)) ) (port (pt 0 48) (input) (text "in0" (rect 0 0 16 14)(font "Arial" (font_size 8))) (text "in0" (rect 21 43 37 57)(font "Arial" (font_size 8))) (line (pt 0 48)(pt 16 48)) ) (port (pt 0 64) (input) (text "in1" (rect 0 0 16 14)(font "Arial" (font_size 8))) (text "in1" (rect 21 59 37 73)(font "Arial" (font_size 8))) (line (pt 0 64)(pt 16 64)) ) (port (pt 0 80) (input) (text "in2" (rect 0 0 16 14)(font "Arial" (font_size 8))) (text "in2" (rect 21 75 37 89)(font "Arial" (font_size 8))) (line (pt 0 80)(pt 16 80)) ) (port (pt 0 96) (input) (text "in3" (rect 0 0 16 14)(font "Arial" (font_size 8))) (text "in3" (rect 21 91 37 105)(font "Arial" (font_size 8))) (line (pt 0 96)(pt 16 96)) ) (port (pt 112 32) (output) (text "out" (rect 0 0 17 14)(font "Arial" (font_size 8))) (text "out" (rect 74 27 91 41)(font "Arial" (font_size 8))) (line (pt 112 32)(pt 96 32)) ) (drawing (rectangle (rect 16 16 96 112)) ) ) ================================================ FILE: cpu/alu/alu_mux_4.v ================================================ // Copyright (C) 1991-2013 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // PROGRAM "Quartus II 64-Bit" // VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" // CREATED "Mon Oct 13 12:05:38 2014" module alu_mux_4( in0, in1, in2, in3, sel, out ); input wire in0; input wire in1; input wire in2; input wire in3; input wire [1:0] sel; output wire out; wire SYNTHESIZED_WIRE_8; wire SYNTHESIZED_WIRE_9; wire SYNTHESIZED_WIRE_4; wire SYNTHESIZED_WIRE_5; wire SYNTHESIZED_WIRE_6; wire SYNTHESIZED_WIRE_7; assign SYNTHESIZED_WIRE_4 = SYNTHESIZED_WIRE_8 & SYNTHESIZED_WIRE_9 & in0; assign SYNTHESIZED_WIRE_7 = sel[0] & SYNTHESIZED_WIRE_9 & in1; assign SYNTHESIZED_WIRE_5 = SYNTHESIZED_WIRE_8 & sel[1] & in2; assign SYNTHESIZED_WIRE_6 = sel[0] & sel[1] & in3; assign out = SYNTHESIZED_WIRE_4 | SYNTHESIZED_WIRE_5 | SYNTHESIZED_WIRE_6 | SYNTHESIZED_WIRE_7; assign SYNTHESIZED_WIRE_8 = ~sel[0]; assign SYNTHESIZED_WIRE_9 = ~sel[1]; endmodule ================================================ FILE: cpu/alu/alu_mux_8.bdf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. 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(section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border)) (section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "alu_mux_8" (rect 43 2 117 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.0" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border)) (drawing ) ) ================================================ FILE: cpu/alu/alu_mux_8.bsf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "symbol" (version "1.2")) (symbol (rect 16 16 128 208) (text "alu_mux_8" (rect 5 0 66 14)(font "Arial" (font_size 8))) (text "inst" (rect 8 176 25 188)(font "Arial" )) (port (pt 0 32) (input) (text "sel[2..0]" (rect 0 0 44 14)(font "Arial" (font_size 8))) (text "sel[2..0]" (rect 21 27 65 41)(font "Arial" (font_size 8))) (line (pt 0 32)(pt 16 32)(line_width 3)) ) (port (pt 0 48) (input) (text "in0" (rect 0 0 16 14)(font "Arial" (font_size 8))) (text "in0" (rect 21 43 37 57)(font "Arial" (font_size 8))) (line (pt 0 48)(pt 16 48)) ) (port (pt 0 64) (input) (text "in1" (rect 0 0 16 14)(font "Arial" (font_size 8))) (text "in1" (rect 21 59 37 73)(font "Arial" (font_size 8))) (line (pt 0 64)(pt 16 64)) ) (port (pt 0 80) (input) (text "in2" (rect 0 0 16 14)(font "Arial" (font_size 8))) (text "in2" (rect 21 75 37 89)(font "Arial" (font_size 8))) (line (pt 0 80)(pt 16 80)) ) (port (pt 0 96) (input) (text "in3" (rect 0 0 16 14)(font "Arial" (font_size 8))) (text "in3" (rect 21 91 37 105)(font "Arial" (font_size 8))) (line (pt 0 96)(pt 16 96)) ) (port (pt 0 112) (input) (text "in4" (rect 0 0 16 14)(font "Arial" (font_size 8))) (text "in4" (rect 21 107 37 121)(font "Arial" (font_size 8))) (line (pt 0 112)(pt 16 112)) ) (port (pt 0 128) (input) (text "in5" (rect 0 0 16 14)(font "Arial" (font_size 8))) (text "in5" (rect 21 123 37 137)(font "Arial" (font_size 8))) (line (pt 0 128)(pt 16 128)) ) (port (pt 0 144) (input) (text "in6" (rect 0 0 16 14)(font "Arial" (font_size 8))) (text "in6" (rect 21 139 37 153)(font "Arial" (font_size 8))) (line (pt 0 144)(pt 16 144)) ) (port (pt 0 160) (input) (text "in7" (rect 0 0 16 14)(font "Arial" (font_size 8))) (text "in7" (rect 21 155 37 169)(font "Arial" (font_size 8))) (line (pt 0 160)(pt 16 160)) ) (port (pt 112 32) (output) (text "out" (rect 0 0 17 14)(font "Arial" (font_size 8))) (text "out" (rect 74 27 91 41)(font "Arial" (font_size 8))) (line (pt 112 32)(pt 96 32)) ) (drawing (rectangle (rect 16 16 96 176)) ) ) ================================================ FILE: cpu/alu/alu_mux_8.v ================================================ // Copyright (C) 1991-2013 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // PROGRAM "Quartus II 64-Bit" // VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" // CREATED "Mon Oct 13 12:04:13 2014" module alu_mux_8( in0, in1, in2, in3, in4, in5, in6, in7, sel, out ); input wire in0; input wire in1; input wire in2; input wire in3; input wire in4; input wire in5; input wire in6; input wire in7; input wire [2:0] sel; output wire out; wire SYNTHESIZED_WIRE_20; wire SYNTHESIZED_WIRE_21; wire SYNTHESIZED_WIRE_22; wire SYNTHESIZED_WIRE_12; wire SYNTHESIZED_WIRE_13; wire SYNTHESIZED_WIRE_14; wire SYNTHESIZED_WIRE_15; wire SYNTHESIZED_WIRE_16; wire SYNTHESIZED_WIRE_17; wire SYNTHESIZED_WIRE_18; wire SYNTHESIZED_WIRE_19; assign SYNTHESIZED_WIRE_12 = SYNTHESIZED_WIRE_20 & SYNTHESIZED_WIRE_21 & SYNTHESIZED_WIRE_22 & in0; assign SYNTHESIZED_WIRE_14 = sel[0] & SYNTHESIZED_WIRE_21 & SYNTHESIZED_WIRE_22 & in1; assign SYNTHESIZED_WIRE_13 = SYNTHESIZED_WIRE_20 & sel[1] & SYNTHESIZED_WIRE_22 & in2; assign SYNTHESIZED_WIRE_15 = sel[0] & sel[1] & SYNTHESIZED_WIRE_22 & in3; assign SYNTHESIZED_WIRE_17 = SYNTHESIZED_WIRE_20 & SYNTHESIZED_WIRE_21 & sel[2] & in4; assign SYNTHESIZED_WIRE_16 = sel[0] & SYNTHESIZED_WIRE_21 & sel[2] & in5; assign SYNTHESIZED_WIRE_18 = SYNTHESIZED_WIRE_20 & sel[1] & sel[2] & in6; assign SYNTHESIZED_WIRE_19 = sel[0] & sel[1] & sel[2] & in7; assign out = SYNTHESIZED_WIRE_12 | SYNTHESIZED_WIRE_13 | SYNTHESIZED_WIRE_14 | SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16 | SYNTHESIZED_WIRE_17 | SYNTHESIZED_WIRE_18 | SYNTHESIZED_WIRE_19; assign SYNTHESIZED_WIRE_20 = ~sel[0]; assign SYNTHESIZED_WIRE_21 = ~sel[1]; assign SYNTHESIZED_WIRE_22 = ~sel[2]; endmodule ================================================ FILE: cpu/alu/alu_prep_daa.bdf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. 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"May 18, 2014" (rect 56 3 132 17)(font "Arial" (font_size 8)))(border)) (section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border)) (section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "alu_prep_daa" (rect 43 2 135 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.0" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border)) (drawing ) ) ================================================ FILE: cpu/alu/alu_prep_daa.bsf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "symbol" (version "1.2")) (symbol (rect 16 16 184 112) (text "alu_prep_daa" (rect 5 0 82 14)(font "Arial" (font_size 8))) (text "inst" (rect 8 80 25 92)(font "Arial" )) (port (pt 0 32) (input) (text "low[3..0]" (rect 0 0 49 14)(font "Arial" (font_size 8))) (text "low[3..0]" (rect 21 27 70 41)(font "Arial" (font_size 8))) (line (pt 0 32)(pt 16 32)(line_width 3)) ) (port (pt 0 48) (input) (text "high[3..0]" (rect 0 0 51 14)(font "Arial" (font_size 8))) (text "high[3..0]" (rect 21 43 72 57)(font "Arial" (font_size 8))) (line (pt 0 48)(pt 16 48)(line_width 3)) ) (port (pt 168 32) (output) (text "low_gt_9" (rect 0 0 53 14)(font "Arial" (font_size 8))) (text "low_gt_9" (rect 94 27 147 41)(font "Arial" (font_size 8))) (line (pt 168 32)(pt 152 32)) ) (port (pt 168 48) (output) (text "high_gt_9" (rect 0 0 55 14)(font "Arial" (font_size 8))) (text "high_gt_9" (rect 92 43 147 57)(font "Arial" (font_size 8))) (line (pt 168 48)(pt 152 48)) ) (port (pt 168 64) (output) (text "high_eq_9" (rect 0 0 59 14)(font "Arial" (font_size 8))) (text "high_eq_9" (rect 88 59 147 73)(font "Arial" (font_size 8))) (line (pt 168 64)(pt 152 64)) ) (drawing (rectangle (rect 16 16 152 80)) ) ) ================================================ FILE: cpu/alu/alu_prep_daa.v ================================================ // Copyright (C) 1991-2013 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // PROGRAM "Quartus II 64-Bit" // VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" // CREATED "Mon Oct 13 12:01:36 2014" module alu_prep_daa( high, low, low_gt_9, high_eq_9, high_gt_9 ); input wire [3:0] high; input wire [3:0] low; output wire low_gt_9; output wire high_eq_9; output wire high_gt_9; wire SYNTHESIZED_WIRE_0; wire SYNTHESIZED_WIRE_1; wire SYNTHESIZED_WIRE_2; wire SYNTHESIZED_WIRE_3; wire SYNTHESIZED_WIRE_4; wire SYNTHESIZED_WIRE_5; assign SYNTHESIZED_WIRE_4 = ~high[2]; assign SYNTHESIZED_WIRE_1 = low[3] & low[2]; assign SYNTHESIZED_WIRE_3 = high[3] & high[2]; assign SYNTHESIZED_WIRE_0 = low[3] & low[1]; assign low_gt_9 = SYNTHESIZED_WIRE_0 | SYNTHESIZED_WIRE_1; assign SYNTHESIZED_WIRE_2 = high[3] & high[1]; assign high_gt_9 = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_3; assign SYNTHESIZED_WIRE_5 = ~high[1]; assign high_eq_9 = high[3] & high[0] & SYNTHESIZED_WIRE_4 & SYNTHESIZED_WIRE_5; endmodule ================================================ FILE: cpu/alu/alu_select.bdf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "graphic" (version "1.4")) (pin (input) (rect 40 40 216 56) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "ctl_alu_oe" (rect 9 0 58 12)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) (line (pt 121 8)(pt 176 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) ) (pin (input) (rect 40 80 216 96) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "ctl_alu_shift_oe" (rect 9 0 86 12)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) (line (pt 121 8)(pt 176 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) ) (pin (input) (rect 40 104 216 120) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 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(font_size 6))) ) (pin (input) (rect 40 400 216 416) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "ctl_alu_sel_op2_neg" (rect 9 0 108 12)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) (line (pt 121 8)(pt 176 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) ) (pin (input) (rect 40 424 216 440) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "ctl_alu_sel_op2_high" (rect 9 0 110 12)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) (line (pt 121 8)(pt 176 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) ) (pin (input) (rect 40 472 216 488) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "ctl_alu_core_R" (rect 9 0 82 12)(font "Arial" )) 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12)(font "Arial" )) (pt 0 8) (drawing (line (pt 0 8)(pt 52 8)) (line (pt 52 4)(pt 78 4)) (line (pt 52 12)(pt 78 12)) (line (pt 52 12)(pt 52 4)) (line (pt 78 4)(pt 82 8)) (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) ) (pin (output) (rect 480 232 656 248) (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) (text "alu_op1_sel_bus" (rect 90 0 171 12)(font "Arial" )) (pt 0 8) (drawing (line (pt 0 8)(pt 52 8)) (line (pt 52 4)(pt 78 4)) (line (pt 52 12)(pt 78 12)) (line (pt 52 12)(pt 52 4)) (line (pt 78 4)(pt 82 8)) (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) ) (pin (output) (rect 480 256 656 272) (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) (text "alu_op1_sel_low" (rect 90 0 169 12)(font "Arial" )) (pt 0 8) (drawing (line (pt 0 8)(pt 52 8)) (line (pt 52 4)(pt 78 4)) (line (pt 52 12)(pt 78 12)) (line (pt 52 12)(pt 52 4)) (line (pt 78 4)(pt 82 8)) (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) ) (pin (output) (rect 480 280 656 296) (text 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(line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) ) (pin (output) (rect 480 376 656 392) (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) (text "alu_op2_sel_lq" (rect 90 0 161 12)(font "Arial" )) (pt 0 8) (drawing (line (pt 0 8)(pt 52 8)) (line (pt 52 4)(pt 78 4)) (line (pt 52 12)(pt 78 12)) (line (pt 52 12)(pt 52 4)) (line (pt 78 4)(pt 82 8)) (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) ) (pin (output) (rect 480 400 656 416) (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) (text "alu_sel_op2_neg" (rect 90 0 171 12)(font "Arial" )) (pt 0 8) (drawing (line (pt 0 8)(pt 52 8)) (line (pt 52 4)(pt 78 4)) (line (pt 52 12)(pt 78 12)) (line (pt 52 12)(pt 52 4)) (line (pt 78 4)(pt 82 8)) (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) ) (pin (output) (rect 480 424 656 440) (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) (text "alu_sel_op2_high" (rect 90 0 173 12)(font "Arial" )) (pt 0 8) (drawing (line (pt 0 8)(pt 52 8)) (line (pt 52 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144 12)(font "Arial" )) (pt 0 8) (drawing (line (pt 0 8)(pt 52 8)) (line (pt 52 4)(pt 78 4)) (line (pt 52 12)(pt 78 12)) (line (pt 52 12)(pt 52 4)) (line (pt 78 4)(pt 82 8)) (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) ) (connector (pt 216 88) (pt 480 88) ) (connector (pt 216 112) (pt 480 112) ) (connector (pt 216 136) (pt 480 136) ) (connector (pt 216 160) (pt 480 160) ) (connector (pt 216 240) (pt 480 240) ) (connector (pt 216 264) (pt 480 264) ) (connector (pt 216 288) (pt 480 288) ) (connector (pt 216 336) (pt 480 336) ) (connector (pt 216 360) (pt 480 360) ) (connector (pt 216 384) (pt 480 384) ) (connector (pt 216 408) (pt 480 408) ) (connector (pt 216 432) (pt 480 432) ) (connector (pt 216 480) (pt 480 480) ) (connector (pt 216 504) (pt 480 504) ) (connector (pt 216 528) (pt 480 528) ) (connector (pt 216 48) (pt 480 48) ) (connector (pt 216 184) (pt 480 184) ) (text "ALU internal bus to db output enable" (rect 232 32 438 46)(font "Arial" (font_size 8))) (text "Shifter to internal bus" (rect 232 72 353 86)(font "Arial" (font_size 8))) (text "OP2 to internal bus" (rect 232 96 339 110)(font "Arial" (font_size 8))) (text "Result to internal bus" (rect 232 120 351 134)(font "Arial" (font_size 8))) (text "OP1 to internal bus" (rect 232 144 339 158)(font "Arial" (font_size 8))) (text "Bit selector to internal bus" (rect 232 168 379 182)(font "Arial" (font_size 8))) (text "OP1 latch selector mux" (rect 288 216 418 230)(font "Arial" (font_size 8))) (text "OP2 latch selector mux" (rect 288 312 418 326)(font "Arial" (font_size 8))) (text "ALU core operation" (rect 296 456 406 470)(font "Arial" (font_size 8))) (title_block (rect 40 568 297 620) (name "title-custom-small") (section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "July 27, 2014" (rect 56 3 131 17)(font "Arial" (font_size 8)))(border)) (section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border)) (section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "alu_select" (rect 43 2 112 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.0" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border)) (drawing ) ) ================================================ FILE: cpu/alu/alu_select.bsf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "symbol" (version "1.2")) (symbol (rect 16 16 296 336) (text "alu_select" (rect 5 0 62 14)(font "Arial" (font_size 8))) (text "inst" (rect 8 304 25 316)(font "Arial" )) (port (pt 0 32) (input) (text "ctl_alu_oe" (rect 0 0 57 14)(font "Arial" (font_size 8))) (text "ctl_alu_oe" (rect 21 27 78 41)(font "Arial" (font_size 8))) (line (pt 0 32)(pt 16 32)) ) (port (pt 0 48) (input) (text "ctl_alu_shift_oe" (rect 0 0 89 14)(font "Arial" (font_size 8))) (text "ctl_alu_shift_oe" (rect 21 43 110 57)(font "Arial" (font_size 8))) (line (pt 0 48)(pt 16 48)) ) (port (pt 0 64) (input) (text "ctl_alu_op2_oe" (rect 0 0 86 14)(font "Arial" (font_size 8))) (text "ctl_alu_op2_oe" (rect 21 59 107 73)(font "Arial" (font_size 8))) (line (pt 0 64)(pt 16 64)) ) (port (pt 0 80) (input) (text "ctl_alu_res_oe" (rect 0 0 83 14)(font "Arial" (font_size 8))) (text "ctl_alu_res_oe" (rect 21 75 104 89)(font "Arial" (font_size 8))) (line (pt 0 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14)(font "Arial" (font_size 8))) (text "alu_core_S" (rect 195 283 259 297)(font "Arial" (font_size 8))) (line (pt 280 288)(pt 264 288)) ) (drawing (rectangle (rect 16 16 264 304)) ) ) ================================================ FILE: cpu/alu/alu_select.v ================================================ // Copyright (C) 1991-2013 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // PROGRAM "Quartus II 64-Bit" // VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" // CREATED "Mon Oct 13 11:59:39 2014" module alu_select( ctl_alu_oe, ctl_alu_shift_oe, ctl_alu_op2_oe, ctl_alu_res_oe, ctl_alu_op1_oe, ctl_alu_bs_oe, ctl_alu_op1_sel_bus, ctl_alu_op1_sel_low, ctl_alu_op1_sel_zero, ctl_alu_op2_sel_zero, ctl_alu_op2_sel_bus, ctl_alu_op2_sel_lq, ctl_alu_sel_op2_neg, ctl_alu_sel_op2_high, ctl_alu_core_R, ctl_alu_core_V, ctl_alu_core_S, alu_oe, alu_shift_oe, alu_op2_oe, alu_res_oe, alu_op1_oe, alu_bs_oe, alu_op1_sel_bus, alu_op1_sel_low, alu_op1_sel_zero, alu_op2_sel_zero, alu_op2_sel_bus, alu_op2_sel_lq, alu_sel_op2_neg, alu_sel_op2_high, alu_core_R, alu_core_V, alu_core_S ); input wire ctl_alu_oe; input wire ctl_alu_shift_oe; input wire ctl_alu_op2_oe; input wire ctl_alu_res_oe; input wire ctl_alu_op1_oe; input wire ctl_alu_bs_oe; input wire ctl_alu_op1_sel_bus; input wire ctl_alu_op1_sel_low; input wire ctl_alu_op1_sel_zero; input wire ctl_alu_op2_sel_zero; input wire ctl_alu_op2_sel_bus; input wire ctl_alu_op2_sel_lq; input wire ctl_alu_sel_op2_neg; input wire ctl_alu_sel_op2_high; input wire ctl_alu_core_R; input wire ctl_alu_core_V; input wire ctl_alu_core_S; output wire alu_oe; output wire alu_shift_oe; output wire alu_op2_oe; output wire alu_res_oe; output wire alu_op1_oe; output wire alu_bs_oe; output wire alu_op1_sel_bus; output wire alu_op1_sel_low; output wire alu_op1_sel_zero; output wire alu_op2_sel_zero; output wire alu_op2_sel_bus; output wire alu_op2_sel_lq; output wire alu_sel_op2_neg; output wire alu_sel_op2_high; output wire alu_core_R; output wire alu_core_V; output wire alu_core_S; assign alu_oe = ctl_alu_oe; assign alu_shift_oe = ctl_alu_shift_oe; assign alu_op2_oe = ctl_alu_op2_oe; assign alu_res_oe = ctl_alu_res_oe; assign alu_op1_oe = ctl_alu_op1_oe; assign alu_bs_oe = ctl_alu_bs_oe; assign alu_op1_sel_bus = ctl_alu_op1_sel_bus; assign alu_op1_sel_low = ctl_alu_op1_sel_low; assign alu_op1_sel_zero = ctl_alu_op1_sel_zero; assign alu_op2_sel_zero = ctl_alu_op2_sel_zero; assign alu_op2_sel_bus = ctl_alu_op2_sel_bus; assign alu_op2_sel_lq = ctl_alu_op2_sel_lq; assign alu_sel_op2_neg = ctl_alu_sel_op2_neg; assign alu_sel_op2_high = ctl_alu_sel_op2_high; assign alu_core_R = ctl_alu_core_R; assign alu_core_V = ctl_alu_core_V; assign alu_core_S = ctl_alu_core_S; endmodule ================================================ FILE: cpu/alu/alu_shifter_core.bdf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. 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the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "symbol" (version "1.2")) (symbol (rect 16 16 200 144) (text "alu_shifter_core" (rect 5 0 98 14)(font "Arial" (font_size 8))) (text "inst" (rect 8 112 25 124)(font "Arial" )) (port (pt 0 32) (input) (text "db[7..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) (text "db[7..0]" (rect 21 27 63 41)(font "Arial" (font_size 8))) (line (pt 0 32)(pt 16 32)(line_width 3)) ) (port (pt 0 48) (input) (text "shift_in" (rect 0 0 41 14)(font "Arial" (font_size 8))) (text "shift_in" (rect 21 43 62 57)(font "Arial" (font_size 8))) (line (pt 0 48)(pt 16 48)) ) (port (pt 0 64) (input) (text "shift_left" (rect 0 0 49 14)(font "Arial" (font_size 8))) (text "shift_left" (rect 21 59 70 73)(font "Arial" (font_size 8))) (line (pt 0 64)(pt 16 64)) ) (port (pt 0 80) (input) (text "shift_right" (rect 0 0 56 14)(font "Arial" (font_size 8))) (text "shift_right" (rect 21 75 77 89)(font "Arial" (font_size 8))) (line (pt 0 80)(pt 16 80)) ) (port (pt 184 32) (output) (text "shift_db0" (rect 0 0 53 14)(font "Arial" (font_size 8))) (text "shift_db0" (rect 110 27 163 41)(font "Arial" (font_size 8))) (line (pt 184 32)(pt 168 32)) ) (port (pt 184 48) (output) (text "shift_db7" (rect 0 0 53 14)(font "Arial" (font_size 8))) (text "shift_db7" (rect 110 43 163 57)(font "Arial" (font_size 8))) (line (pt 184 48)(pt 168 48)) ) (port (pt 184 64) (output) (text "out_low[3..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) (text "out_low[3..0]" (rect 89 59 163 73)(font "Arial" (font_size 8))) (line (pt 184 64)(pt 168 64)(line_width 3)) ) (port (pt 184 80) (output) (text "out_high[3..0]" (rect 0 0 76 14)(font "Arial" (font_size 8))) (text "out_high[3..0]" (rect 87 75 163 89)(font "Arial" (font_size 8))) (line (pt 184 80)(pt 168 80)(line_width 3)) ) (drawing (rectangle (rect 16 16 168 112)) ) (fill (color 217 255 255)) ) ================================================ FILE: cpu/alu/alu_shifter_core.v ================================================ // Copyright (C) 1991-2013 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // PROGRAM "Quartus II 64-Bit" // VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" // CREATED "Mon Oct 13 11:55:31 2014" module alu_shifter_core( shift_in, shift_right, shift_left, db, shift_db0, shift_db7, out_high, out_low ); input wire shift_in; input wire shift_right; input wire shift_left; input wire [7:0] db; output wire shift_db0; output wire shift_db7; output wire [3:0] out_high; output wire [3:0] out_low; wire [3:0] out_high_ALTERA_SYNTHESIZED; wire [3:0] out_low_ALTERA_SYNTHESIZED; wire SYNTHESIZED_WIRE_32; wire SYNTHESIZED_WIRE_8; wire SYNTHESIZED_WIRE_9; wire SYNTHESIZED_WIRE_10; wire SYNTHESIZED_WIRE_11; wire SYNTHESIZED_WIRE_12; wire SYNTHESIZED_WIRE_13; wire SYNTHESIZED_WIRE_14; wire SYNTHESIZED_WIRE_15; wire SYNTHESIZED_WIRE_16; wire SYNTHESIZED_WIRE_17; wire SYNTHESIZED_WIRE_18; wire SYNTHESIZED_WIRE_19; wire SYNTHESIZED_WIRE_20; wire SYNTHESIZED_WIRE_21; wire SYNTHESIZED_WIRE_22; wire SYNTHESIZED_WIRE_23; wire SYNTHESIZED_WIRE_24; wire SYNTHESIZED_WIRE_25; wire SYNTHESIZED_WIRE_26; wire SYNTHESIZED_WIRE_27; wire SYNTHESIZED_WIRE_28; wire SYNTHESIZED_WIRE_29; wire SYNTHESIZED_WIRE_30; wire SYNTHESIZED_WIRE_31; assign shift_db0 = db[0]; assign shift_db7 = db[7]; assign SYNTHESIZED_WIRE_9 = shift_in & shift_left; assign SYNTHESIZED_WIRE_8 = db[0] & SYNTHESIZED_WIRE_32; assign SYNTHESIZED_WIRE_10 = db[1] & shift_right; assign SYNTHESIZED_WIRE_12 = db[0] & shift_left; assign SYNTHESIZED_WIRE_11 = db[1] & SYNTHESIZED_WIRE_32; assign SYNTHESIZED_WIRE_13 = db[2] & shift_right; assign SYNTHESIZED_WIRE_15 = db[1] & shift_left; assign SYNTHESIZED_WIRE_14 = db[2] & SYNTHESIZED_WIRE_32; assign SYNTHESIZED_WIRE_16 = db[3] & shift_right; assign SYNTHESIZED_WIRE_18 = db[2] & shift_left; assign SYNTHESIZED_WIRE_17 = db[3] & SYNTHESIZED_WIRE_32; assign SYNTHESIZED_WIRE_19 = db[4] & shift_right; assign SYNTHESIZED_WIRE_21 = db[3] & shift_left; assign SYNTHESIZED_WIRE_20 = db[4] & SYNTHESIZED_WIRE_32; assign SYNTHESIZED_WIRE_22 = db[5] & shift_right; assign SYNTHESIZED_WIRE_24 = db[4] & shift_left; assign SYNTHESIZED_WIRE_23 = db[5] & SYNTHESIZED_WIRE_32; assign SYNTHESIZED_WIRE_25 = db[6] & shift_right; assign SYNTHESIZED_WIRE_27 = db[5] & shift_left; assign SYNTHESIZED_WIRE_26 = db[6] & SYNTHESIZED_WIRE_32; assign SYNTHESIZED_WIRE_28 = db[7] & shift_right; assign SYNTHESIZED_WIRE_30 = db[6] & shift_left; assign SYNTHESIZED_WIRE_29 = db[7] & SYNTHESIZED_WIRE_32; assign SYNTHESIZED_WIRE_31 = shift_in & shift_right; assign SYNTHESIZED_WIRE_32 = ~(shift_right | shift_left); assign out_low_ALTERA_SYNTHESIZED[0] = SYNTHESIZED_WIRE_8 | SYNTHESIZED_WIRE_9 | SYNTHESIZED_WIRE_10; assign out_low_ALTERA_SYNTHESIZED[1] = SYNTHESIZED_WIRE_11 | SYNTHESIZED_WIRE_12 | SYNTHESIZED_WIRE_13; assign out_low_ALTERA_SYNTHESIZED[2] = SYNTHESIZED_WIRE_14 | SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16; assign out_low_ALTERA_SYNTHESIZED[3] = SYNTHESIZED_WIRE_17 | SYNTHESIZED_WIRE_18 | SYNTHESIZED_WIRE_19; assign out_high_ALTERA_SYNTHESIZED[0] = SYNTHESIZED_WIRE_20 | SYNTHESIZED_WIRE_21 | SYNTHESIZED_WIRE_22; assign out_high_ALTERA_SYNTHESIZED[1] = SYNTHESIZED_WIRE_23 | SYNTHESIZED_WIRE_24 | SYNTHESIZED_WIRE_25; assign out_high_ALTERA_SYNTHESIZED[2] = SYNTHESIZED_WIRE_26 | SYNTHESIZED_WIRE_27 | SYNTHESIZED_WIRE_28; assign out_high_ALTERA_SYNTHESIZED[3] = SYNTHESIZED_WIRE_29 | SYNTHESIZED_WIRE_30 | SYNTHESIZED_WIRE_31; assign out_high = out_high_ALTERA_SYNTHESIZED; assign out_low = out_low_ALTERA_SYNTHESIZED; endmodule ================================================ FILE: cpu/alu/alu_slice.bdf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. 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0 16)(pt 16 16)) ) (port (pt 64 24) (output) (text "OUT" (rect 47 15 64 27)(font "Courier New" (bold))(invisible)) (text "OUT" (rect 47 15 61 27)(font "Courier New" (bold))(invisible)) (line (pt 49 24)(pt 64 24)) ) (drawing (line (pt 14 13)(pt 25 13)) (line (pt 14 36)(pt 25 36)) (arc (pt 7 29)(pt 7 19)(rect -14 8 19 41)) (arc (pt 49 24)(pt 25 13)(rect -6 13 57 76)) (arc (pt 25 35)(pt 49 24)(rect -6 -27 57 36)) ) ) (connector (pt 256 96) (pt 240 96) ) (connector (pt 336 152) (pt 224 152) ) (connector (pt 256 112) (pt 224 112) ) (connector (pt 336 88) (pt 328 88) ) (connector (pt 416 152) (pt 408 152) ) (connector (pt 408 184) (pt 408 152) ) (connector (pt 416 136) (pt 408 136) ) (connector (pt 408 136) (pt 408 96) ) (connector (pt 408 96) (pt 400 96) ) (connector (pt 336 136) (pt 240 136) ) (connector (pt 328 48) (pt 328 88) ) (connector (pt 504 144) (pt 504 200) ) (connector (pt 592 136) (pt 600 136) ) (connector (pt 664 56) (pt 672 56) ) (connector (pt 672 56) (pt 672 128) ) (connector (pt 672 128) (pt 680 128) ) (connector (pt 744 136) (pt 752 136) ) (connector (pt 800 136) (pt 808 136) ) (connector (pt 504 200) (pt 520 200) ) (connector (pt 488 160) (pt 488 200) ) (connector (pt 520 160) (pt 488 160) ) (connector (pt 504 64) (pt 504 88) ) (connector (pt 488 56) (pt 488 96) ) (connector (pt 472 48) (pt 472 104) ) (connector (pt 592 96) (pt 584 96) ) (connector (pt 592 136) (pt 592 96) ) (connector (pt 488 96) (pt 520 96) ) (connector (pt 472 104) (pt 520 104) ) (connector (pt 504 88) (pt 520 88) ) (connector (pt 240 64) (pt 240 96) ) (connector (pt 240 96) (pt 240 136) ) (connector (pt 224 56) (pt 488 56) ) (connector (pt 488 56) (pt 600 56) ) (connector (pt 224 112) (pt 224 152) ) (connector (pt 504 64) (pt 600 64) ) (connector (pt 472 48) (pt 600 48) ) (connector (pt 504 144) (pt 520 144) ) (connector (pt 224 56) (pt 224 80) ) (connector (pt 224 80) (pt 224 112) ) (connector (pt 320 104) (pt 336 104) ) (connector (pt 400 144) (pt 416 144) ) (connector (pt 584 208) (pt 808 208) ) (connector (pt 480 144) (pt 504 144) ) (connector (pt 584 152) (pt 600 152) ) (connector (pt 664 144) (pt 680 144) ) (connector (pt 240 64) (pt 504 64) ) (connector (pt 328 48) (pt 472 48) ) (connector (pt 200 48) (pt 328 48) ) (connector (pt 200 64) (pt 240 64) ) (connector (pt 200 80) (pt 224 80) ) (connector (pt 200 184) (pt 408 184) ) (connector (pt 200 200) (pt 488 200) ) (connector (pt 200 216) (pt 520 216) ) (junction (pt 240 96)) (junction (pt 488 56)) (junction (pt 504 144)) (junction (pt 224 112)) (junction (pt 504 64)) (junction (pt 240 64)) (junction (pt 328 48)) (junction (pt 472 48)) (junction (pt 224 80)) (title_block (rect 24 264 281 316) (name "title-custom-small") (section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "alu_slice" (rect 43 2 103 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border)) (section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "May 18, 2014" (rect 56 3 132 17)(font "Arial" (font_size 8)))(border)) (section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.0" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border)) (drawing ) ) ================================================ FILE: cpu/alu/alu_slice.bsf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "symbol" (version "1.2")) (symbol (rect 16 16 136 176) (text "alu_slice" (rect 5 0 54 14)(font "Arial" (font_size 8))) (text "inst" (rect 8 144 25 156)(font "Arial" )) (port (pt 0 32) (input) (text "cy_in" (rect 0 0 30 14)(font "Arial" (font_size 8))) (text "cy_in" (rect 21 27 51 41)(font "Arial" (font_size 8))) (line (pt 0 32)(pt 16 32)) ) (port (pt 0 48) (input) (text "op1" (rect 0 0 21 14)(font "Arial" (font_size 8))) (text "op1" (rect 21 43 42 57)(font "Arial" (font_size 8))) (line (pt 0 48)(pt 16 48)) ) (port (pt 0 64) (input) (text "op2" (rect 0 0 21 14)(font "Arial" (font_size 8))) (text "op2" (rect 21 59 42 73)(font "Arial" (font_size 8))) (line (pt 0 64)(pt 16 64)) ) (port (pt 0 80) (input) (text "S" (rect 0 0 8 14)(font "Arial" (font_size 8))) (text "S" (rect 21 75 29 89)(font "Arial" (font_size 8))) (line (pt 0 80)(pt 16 80)) ) (port (pt 0 96) (input) (text "V" (rect 0 0 9 14)(font "Arial" (font_size 8))) (text "V" (rect 21 91 30 105)(font "Arial" (font_size 8))) (line (pt 0 96)(pt 16 96)) ) (port (pt 0 112) (input) (text "R" (rect 0 0 8 14)(font "Arial" (font_size 8))) (text "R" (rect 21 107 29 121)(font "Arial" (font_size 8))) (line (pt 0 112)(pt 16 112)) ) (port (pt 120 32) (output) (text "result" (rect 0 0 31 14)(font "Arial" (font_size 8))) (text "result" (rect 68 27 99 41)(font "Arial" (font_size 8))) (line (pt 120 32)(pt 104 32)) ) (port (pt 120 48) (output) (text "cy_out" (rect 0 0 38 14)(font "Arial" (font_size 8))) (text "cy_out" (rect 61 43 99 57)(font "Arial" (font_size 8))) (line (pt 120 48)(pt 104 48)) ) (drawing (rectangle (rect 16 16 104 144)) ) ) ================================================ FILE: cpu/alu/alu_slice.v ================================================ // Copyright (C) 1991-2013 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // PROGRAM "Quartus II 64-Bit" // VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" // CREATED "Mon Oct 13 11:51:12 2014" module alu_slice( op2, op1, cy_in, R, S, V, cy_out, result ); input wire op2; input wire op1; input wire cy_in; input wire R; input wire S; input wire V; output wire cy_out; output wire result; wire SYNTHESIZED_WIRE_0; wire SYNTHESIZED_WIRE_1; wire SYNTHESIZED_WIRE_2; wire SYNTHESIZED_WIRE_3; wire SYNTHESIZED_WIRE_4; wire SYNTHESIZED_WIRE_5; wire SYNTHESIZED_WIRE_10; wire SYNTHESIZED_WIRE_7; wire SYNTHESIZED_WIRE_8; assign SYNTHESIZED_WIRE_0 = op2 | cy_in | op1; assign SYNTHESIZED_WIRE_3 = SYNTHESIZED_WIRE_0 & SYNTHESIZED_WIRE_1; assign SYNTHESIZED_WIRE_4 = cy_in & op2 & op1; assign result = ~SYNTHESIZED_WIRE_2; assign SYNTHESIZED_WIRE_2 = ~(SYNTHESIZED_WIRE_3 | SYNTHESIZED_WIRE_4); assign SYNTHESIZED_WIRE_5 = op2 | op1; assign SYNTHESIZED_WIRE_7 = cy_in & SYNTHESIZED_WIRE_5; assign SYNTHESIZED_WIRE_8 = op1 & op2; assign cy_out = ~(R | SYNTHESIZED_WIRE_10); assign SYNTHESIZED_WIRE_10 = ~(SYNTHESIZED_WIRE_7 | SYNTHESIZED_WIRE_8 | S); assign SYNTHESIZED_WIRE_1 = V | SYNTHESIZED_WIRE_10; endmodule ================================================ FILE: cpu/alu/simulation/modelsim/r ================================================ restart -f ; run -all ================================================ FILE: cpu/alu/simulation/modelsim/test_alu.mpf ================================================ ; Copyright 1991-2009 Mentor Graphics Corporation ; ; All Rights Reserved. ; ; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF ; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. ; [Library] std = $MODEL_TECH/../std ieee = $MODEL_TECH/../ieee verilog = $MODEL_TECH/../verilog vital2000 = $MODEL_TECH/../vital2000 std_developerskit = $MODEL_TECH/../std_developerskit synopsys = $MODEL_TECH/../synopsys modelsim_lib = $MODEL_TECH/../modelsim_lib sv_std = $MODEL_TECH/../sv_std ; Altera Primitive libraries ; ; VHDL Section ; altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf altera = $MODEL_TECH/../altera/vhdl/altera altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim lpm = $MODEL_TECH/../altera/vhdl/220model 220model = $MODEL_TECH/../altera/vhdl/220model max = $MODEL_TECH/../altera/vhdl/max maxii = $MODEL_TECH/../altera/vhdl/maxii maxv = $MODEL_TECH/../altera/vhdl/maxv stratix = $MODEL_TECH/../altera/vhdl/stratix stratixii = $MODEL_TECH/../altera/vhdl/stratixii stratixiigx = $MODEL_TECH/../altera/vhdl/stratixiigx hardcopyii = $MODEL_TECH/../altera/vhdl/hardcopyii hardcopyiii = $MODEL_TECH/../altera/vhdl/hardcopyiii hardcopyiv = $MODEL_TECH/../altera/vhdl/hardcopyiv cyclone = $MODEL_TECH/../altera/vhdl/cyclone cycloneii = $MODEL_TECH/../altera/vhdl/cycloneii cycloneiii = $MODEL_TECH/../altera/vhdl/cycloneiii cycloneiiils = $MODEL_TECH/../altera/vhdl/cycloneiiils sgate = $MODEL_TECH/../altera/vhdl/sgate stratixgx = $MODEL_TECH/../altera/vhdl/stratixgx altgxb = $MODEL_TECH/../altera/vhdl/altgxb stratixgx_gxb = $MODEL_TECH/../altera/vhdl/stratixgx_gxb stratixiigx_hssi = $MODEL_TECH/../altera/vhdl/stratixiigx_hssi arriagx_hssi = $MODEL_TECH/../altera/vhdl/arriagx_hssi arriaii = $MODEL_TECH/../altera/vhdl/arriaii arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip arriagx = $MODEL_TECH/../altera/vhdl/arriagx altgxb_lib = $MODEL_TECH/../altera/vhdl/altgxb stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive hardcopyiv_hssi = $MODEL_TECH/../altera/vhdl/hardcopyiv_hssi hardcopyiv_pcie_hip = $MODEL_TECH/../altera/vhdl/hardcopyiv_pcie_hip stratixv = $MODEL_TECH/../altera/vhdl/stratixv stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip arriav = $MODEL_TECH/../altera/vhdl/arriav cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev ; ; Verilog Section ; altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf altera_ver = $MODEL_TECH/../altera/verilog/altera altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim lpm_ver = $MODEL_TECH/../altera/verilog/220model 220model_ver = $MODEL_TECH/../altera/verilog/220model max_ver = $MODEL_TECH/../altera/verilog/max maxii_ver = $MODEL_TECH/../altera/verilog/maxii maxv_ver = $MODEL_TECH/../altera/verilog/maxv stratix_ver = $MODEL_TECH/../altera/verilog/stratix stratixii_ver = $MODEL_TECH/../altera/verilog/stratixii stratixiigx_ver = $MODEL_TECH/../altera/verilog/stratixiigx arriagx_ver = $MODEL_TECH/../altera/verilog/arriagx hardcopyii_ver = $MODEL_TECH/../altera/verilog/hardcopyii hardcopyiii_ver = $MODEL_TECH/../altera/verilog/hardcopyiii hardcopyiv_ver = $MODEL_TECH/../altera/verilog/hardcopyiv cyclone_ver = $MODEL_TECH/../altera/verilog/cyclone cycloneii_ver = $MODEL_TECH/../altera/verilog/cycloneii cycloneiii_ver = $MODEL_TECH/../altera/verilog/cycloneiii cycloneiiils_ver = $MODEL_TECH/../altera/verilog/cycloneiiils sgate_ver = $MODEL_TECH/../altera/verilog/sgate stratixgx_ver = $MODEL_TECH/../altera/verilog/stratixgx altgxb_ver = $MODEL_TECH/../altera/verilog/altgxb stratixgx_gxb_ver = $MODEL_TECH/../altera/verilog/stratixgx_gxb stratixiigx_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiigx_hssi arriagx_hssi_ver = $MODEL_TECH/../altera/verilog/arriagx_hssi arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip stratixiii_ver = $MODEL_TECH/../altera/verilog/stratixiii stratixiii = $MODEL_TECH/../altera/vhdl/stratixiii stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip arriav_ver = $MODEL_TECH/../altera/verilog/arriav arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive hardcopyiv_hssi_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_hssi hardcopyiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_pcie_hip work = work [vcom] ; VHDL93 variable selects language version as the default. ; Default is VHDL-2002. ; Value of 0 or 1987 for VHDL-1987. ; Value of 1 or 1993 for VHDL-1993. ; Default or value of 2 or 2002 for VHDL-2002. ; Default or value of 3 or 2008 for VHDL-2008. VHDL93 = 2002 ; Show source line containing error. Default is off. ; Show_source = 1 ; Turn off unbound-component warnings. Default is on. ; Show_Warning1 = 0 ; Turn off process-without-a-wait-statement warnings. Default is on. ; Show_Warning2 = 0 ; Turn off null-range warnings. Default is on. ; Show_Warning3 = 0 ; Turn off no-space-in-time-literal warnings. Default is on. ; Show_Warning4 = 0 ; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. ; Show_Warning5 = 0 ; Turn off optimization for IEEE std_logic_1164 package. Default is on. ; Optimize_1164 = 0 ; Turn on resolving of ambiguous function overloading in favor of the ; "explicit" function declaration (not the one automatically created by ; the compiler for each type declaration). Default is off. ; The .ini file has Explicit enabled so that std_logic_signed/unsigned ; will match the behavior of synthesis tools. Explicit = 1 ; Turn off acceleration of the VITAL packages. Default is to accelerate. ; NoVital = 1 ; Turn off VITAL compliance checking. Default is checking on. ; NoVitalCheck = 1 ; Ignore VITAL compliance checking errors. Default is to not ignore. ; IgnoreVitalErrors = 1 ; Turn off VITAL compliance checking warnings. Default is to show warnings. ; Show_VitalChecksWarnings = 0 ; Keep silent about case statement static warnings. ; Default is to give a warning. ; NoCaseStaticError = 1 ; Keep silent about warnings caused by aggregates that are not locally static. ; Default is to give a warning. ; NoOthersStaticError = 1 ; Turn off inclusion of debugging info within design units. ; Default is to include debugging info. ; NoDebug = 1 ; Turn off "Loading..." messages. Default is messages on. ; Quiet = 1 ; Turn on some limited synthesis rule compliance checking. Checks only: ; -- signals used (read) by a process must be in the sensitivity list ; CheckSynthesis = 1 ; Activate optimizations on expressions that do not involve signals, ; waits, or function/procedure/task invocations. Default is off. ; ScalarOpts = 1 ; Require the user to specify a configuration for all bindings, ; and do not generate a compile time default binding for the ; component. This will result in an elaboration error of ; 'component not bound' if the user fails to do so. Avoids the rare ; issue of a false dependency upon the unused default binding. ; RequireConfigForAllDefaultBinding = 1 ; Inhibit range checking on subscripts of arrays. Range checking on ; scalars defined with subtypes is inhibited by default. ; NoIndexCheck = 1 ; Inhibit range checks on all (implicit and explicit) assignments to ; scalar objects defined with subtypes. ; NoRangeCheck = 1 [vlog] ; Turn off inclusion of debugging info within design units. ; Default is to include debugging info. ; NoDebug = 1 ; Turn off "loading..." messages. Default is messages on. ; Quiet = 1 ; Turn on Verilog hazard checking (order-dependent accessing of global vars). ; Default is off. ; Hazard = 1 ; Turn on converting regular Verilog identifiers to uppercase. Allows case ; insensitivity for module names. Default is no conversion. ; UpCase = 1 ; Turn on incremental compilation of modules. Default is off. ; Incremental = 1 ; Turns on lint-style checking. ; Show_Lint = 1 [vsim] ; Simulator resolution ; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. Resolution = ps ; User time unit for run commands ; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the ; unit specified for Resolution. For example, if Resolution is 100ps, ; then UserTimeUnit defaults to ps. ; Should generally be set to default. UserTimeUnit = default ; Default run length RunLength = 0 ns ; Maximum iterations that can be run without advancing simulation time IterationLimit = 5000 ; Directive to license manager: ; vhdl Immediately reserve a VHDL license ; vlog Immediately reserve a Verilog license ; plus Immediately reserve a VHDL and Verilog license ; nomgc Do not look for Mentor Graphics Licenses ; nomti Do not look for Model Technology Licenses ; noqueue Do not wait in the license queue when a license isn't available ; viewsim Try for viewer license but accept simulator license(s) instead ; of queuing for viewer license ; License = plus ; Stop the simulator after a VHDL/Verilog assertion message ; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal BreakOnAssertion = 3 ; Assertion Message Format ; %S - Severity Level ; %R - Report Message ; %T - Time of assertion ; %D - Delta ; %I - Instance or Region pathname (if available) ; %% - print '%' character ; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" ; Assertion File - alternate file for storing VHDL/Verilog assertion messages ; AssertFile = assert.log ; Default radix for all windows and commands... ; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned DefaultRadix = symbolic ; VSIM Startup command ; Startup = do startup.do ; File for saving command transcript TranscriptFile = transcript ; File for saving command history ; CommandHistory = cmdhist.log ; Specify whether paths in simulator commands should be described ; in VHDL or Verilog format. ; For VHDL, PathSeparator = / ; For Verilog, PathSeparator = . ; Must not be the same character as DatasetSeparator. PathSeparator = / ; Specify the dataset separator for fully rooted contexts. ; The default is ':'. For example, sim:/top ; Must not be the same character as PathSeparator. DatasetSeparator = : ; Disable VHDL assertion messages ; IgnoreNote = 1 ; IgnoreWarning = 1 ; IgnoreError = 1 ; IgnoreFailure = 1 ; Default force kind. May be freeze, drive, deposit, or default ; or in other terms, fixed, wired, or charged. ; A value of "default" will use the signal kind to determine the ; force kind, drive for resolved signals, freeze for unresolved signals ; DefaultForceKind = freeze ; If zero, open files when elaborated; otherwise, open files on ; first read or write. Default is 0. ; DelayFileOpen = 1 ; Control VHDL files opened for write. ; 0 = Buffered, 1 = Unbuffered UnbufferedOutput = 0 ; Control the number of VHDL files open concurrently. ; This number should always be less than the current ulimit ; setting for max file descriptors. ; 0 = unlimited ConcurrentFileLimit = 40 ; Control the number of hierarchical regions displayed as ; part of a signal name shown in the Wave window. ; A value of zero tells VSIM to display the full name. ; The default is 0. ; WaveSignalNameWidth = 0 ; Turn off warnings from the std_logic_arith, std_logic_unsigned ; and std_logic_signed packages. ; StdArithNoWarnings = 1 ; Turn off warnings from the IEEE numeric_std and numeric_bit packages. ; NumericStdNoWarnings = 1 ; Control the format of the (VHDL) FOR generate statement label ; for each iteration. Do not quote it. ; The format string here must contain the conversion codes %s and %d, ; in that order, and no other conversion codes. The %s represents ; the generate_label; the %d represents the generate parameter value ; at a particular generate iteration (this is the position number if ; the generate parameter is of an enumeration type). Embedded whitespace ; is allowed (but discouraged); leading and trailing whitespace is ignored. ; Application of the format must result in a unique scope name over all ; such names in the design so that name lookup can function properly. ; GenerateFormat = %s__%d ; Specify whether checkpoint files should be compressed. ; The default is 1 (compressed). ; CheckpointCompressMode = 0 ; List of dynamically loaded objects for Verilog PLI applications ; Veriuser = veriuser.sl ; Specify default options for the restart command. Options can be one ; or more of: -force -nobreakpoint -nolist -nolog -nowave ; DefaultRestartOptions = -force ; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs ; (> 500 megabyte memory footprint). Default is disabled. ; Specify number of megabytes to lock. ; LockedMemory = 1000 ; Turn on (1) or off (0) WLF file compression. ; The default is 1 (compress WLF file). ; WLFCompress = 0 ; Specify whether to save all design hierarchy (1) in the WLF file ; or only regions containing logged signals (0). ; The default is 0 (save only regions with logged signals). ; WLFSaveAllRegions = 1 ; WLF file time limit. Limit WLF file by time, as closely as possible, ; to the specified amount of simulation time. When the limit is exceeded ; the earliest times get truncated from the file. ; If both time and size limits are specified the most restrictive is used. ; UserTimeUnits are used if time units are not specified. ; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} ; WLFTimeLimit = 0 ; WLF file size limit. Limit WLF file size, as closely as possible, ; to the specified number of megabytes. If both time and size limits ; are specified then the most restrictive is used. ; The default is 0 (no limit). ; WLFSizeLimit = 1000 ; Specify whether or not a WLF file should be deleted when the ; simulation ends. A value of 1 will cause the WLF file to be deleted. ; The default is 0 (do not delete WLF file when simulation ends). ; WLFDeleteOnQuit = 1 ; Automatic SDF compilation ; Disables automatic compilation of SDF files in flows that support it. ; Default is on, uncomment to turn off. ; NoAutoSDFCompile = 1 [lmc] [msg_system] ; Change a message severity or suppress a message. ; The format is: = [,...] ; Examples: ; note = 3009 ; warning = 3033 ; error = 3010,3016 ; fatal = 3016,3033 ; suppress = 3009,3016,3043 ; The command verror can be used to get the complete ; description of a message. ; Control transcripting of elaboration/runtime messages. ; The default is to have messages appear in the transcript and ; recorded in the wlf file (messages that are recorded in the ; wlf file can be viewed in the MsgViewer). The other settings ; are to send messages only to the transcript or only to the ; wlf file. The valid values are ; both {default} ; tran {transcript only} ; wlf {wlf file only} ; msgmode = both [Project] ; Warning -- Do not edit the project properties directly. ; Property names are dynamic in nature and property ; values have special syntax. Changing property data directly ; can result in a corrupt MPF file. All project properties ; can be modified through project window dialogs. Project_Version = 6 Project_DefaultLib = work Project_SortMethod = unused Project_Files_Count = 14 Project_File_0 = $ROOT/cpu/alu/alu.v Project_File_P_0 = compile_order 11 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {ALU Complete} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 Project_File_1 = $ROOT/cpu/alu/alu_bit_select.v Project_File_P_1 = compile_order 12 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {ALU Complete} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 Project_File_2 = $ROOT/cpu/alu/alu_core.v Project_File_P_2 = compile_order 2 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 Project_File_3 = $ROOT/cpu/alu/alu_mux_2z.v Project_File_P_3 = compile_order 13 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {ALU Complete} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 Project_File_4 = $ROOT/cpu/alu/alu_mux_3z.v Project_File_P_4 = compile_order 7 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder misc group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 Project_File_5 = $ROOT/cpu/alu/alu_prep_daa.v Project_File_P_5 = compile_order 8 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder misc group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 Project_File_6 = $ROOT/cpu/alu/alu_shifter_core.v Project_File_P_6 = compile_order 4 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder shifter group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 Project_File_7 = $ROOT/cpu/alu/alu_slice.v Project_File_P_7 = compile_order 0 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 Project_File_8 = $ROOT/cpu/alu/test_alu.sv Project_File_P_8 = compile_order 10 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder {ALU Complete} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 1 vlog_enable0In 0 vlog_hazard 1 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 Project_File_9 = $ROOT/cpu/alu/test_core.sv Project_File_P_9 = compile_order 3 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 Project_File_10 = $ROOT/cpu/alu/test_mux_3z.sv Project_File_P_10 = compile_order 6 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder misc group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 Project_File_11 = $ROOT/cpu/alu/test_prep_daa.sv Project_File_P_11 = compile_order 9 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder misc group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 Project_File_12 = $ROOT/cpu/alu/test_shifter_core.sv Project_File_P_12 = compile_order 5 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder shifter group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 Project_File_13 = $ROOT/cpu/alu/test_slice.sv Project_File_P_13 = compile_order 1 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder alu group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 Project_Sim_Count = 6 Project_Sim_0 = Test slice Project_Sim_P_0 = timing default -t default -sdfnoerror 0 -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder alu +pulse_e {} additional_dus work.test_slice -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {} Project_Sim_1 = Test core Project_Sim_P_1 = timing default -sdfnoerror 0 -t default -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder alu +pulse_e {} additional_dus work.test_core -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {} Project_Sim_2 = Test prep daa Project_Sim_P_2 = timing default cover_exttoggle 0 vlog_nodebug 0 last_compile 1418395911 -t default -sdfnoerror 0 compile_to work -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} file_type systemverilog +notimingchecks 0 cover_cond 0 ok 1 folder misc vlog_noload 0 cover_fsm 0 cover_excludedefault 0 +pulse_e {} cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 compile_order 3 additional_dus work.test_prep_daa -assertfile {} cover_toggle 0 vlog_protect 0 -std_output {} -L {} -nopsl 0 -nosva 0 -absentisempty 0 +pulse_r {} -assertcover 0 vlog_disableopt 0 OtherArgs {} -multisource_delay {} -vital2.2b 0 voptflow 1 ood 0 -memprof 0 is_vopt_flow 0 vlog_upper 0 -noglitch 0 -0in_options {} selected_du {} cover_nofec 0 group_id 0 -hazards 0 -sdf {} vlog_1995compat SV -0in 0 cover_branch 0 vlog_enable0In 0 cover_covercells 0 +plusarg {} -coverage 0 vopt_env 1 toggle - vlog_0InOptions {} cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 -wlf {} -assertdebug 0 cover_stmt 0 -std_input {} -sdfnowarn 0 Project_Sim_3 = Test ALU Project_Sim_P_3 = timing default -sdfnoerror 0 -t default -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder {ALU Complete} +pulse_e {} additional_dus work.test_alu -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {} Project_Sim_4 = Test shifter core Project_Sim_P_4 = timing default -t default -sdfnoerror 0 -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder shifter +pulse_e {} additional_dus work.test_shifter_core -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {} Project_Sim_5 = Test mux 3z Project_Sim_P_5 = timing default cover_exttoggle 0 vlog_nodebug 0 last_compile 1418395911 -t default -sdfnoerror 0 compile_to work -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} file_type systemverilog +notimingchecks 0 cover_cond 0 ok 1 folder misc vlog_noload 0 cover_fsm 0 cover_excludedefault 0 +pulse_e {} cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 compile_order 3 additional_dus work.test_mux_3z -assertfile {} cover_toggle 0 vlog_protect 0 -std_output {} -L {} -nopsl 0 -nosva 0 -absentisempty 0 +pulse_r {} -assertcover 0 vlog_disableopt 0 OtherArgs {} -multisource_delay {} -vital2.2b 0 voptflow 1 ood 0 -memprof 0 is_vopt_flow 0 vlog_upper 0 -noglitch 0 -0in_options {} selected_du {} cover_nofec 0 group_id 0 -hazards 0 -sdf {} vlog_1995compat SV -0in 0 cover_branch 0 vlog_enable0In 0 cover_covercells 0 +plusarg {} -coverage 0 vopt_env 1 toggle - vlog_0InOptions {} cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 -wlf {} -assertdebug 0 cover_stmt 0 -std_input {} -sdfnowarn 0 Project_Folder_Count = 4 Project_Folder_0 = misc Project_Folder_P_0 = folder {Top Level} Project_Folder_1 = shifter Project_Folder_P_1 = folder {Top Level} Project_Folder_2 = alu Project_Folder_P_2 = folder {Top Level} Project_Folder_3 = ALU Complete Project_Folder_P_3 = folder {Top Level} Echo_Compile_Output = 0 Save_Compile_Report = 1 Project_Opt_Count = 0 ForceSoftPaths = 1 ProjectStatusDelay = 5000 VERILOG_DoubleClick = Edit VERILOG_CustomDoubleClick = SYSTEMVERILOG_DoubleClick = Edit SYSTEMVERILOG_CustomDoubleClick = VHDL_DoubleClick = Edit VHDL_CustomDoubleClick = PSL_DoubleClick = Edit PSL_CustomDoubleClick = TEXT_DoubleClick = Edit TEXT_CustomDoubleClick = SYSTEMC_DoubleClick = Edit SYSTEMC_CustomDoubleClick = TCL_DoubleClick = Edit TCL_CustomDoubleClick = MACRO_DoubleClick = Edit MACRO_CustomDoubleClick = VCD_DoubleClick = Edit VCD_CustomDoubleClick = SDF_DoubleClick = Edit SDF_CustomDoubleClick = XML_DoubleClick = Edit XML_CustomDoubleClick = LOGFILE_DoubleClick = Edit LOGFILE_CustomDoubleClick = UCDB_DoubleClick = Edit UCDB_CustomDoubleClick = UPF_DoubleClick = Edit UPF_CustomDoubleClick = PCF_DoubleClick = Edit PCF_CustomDoubleClick = PROJECT_DoubleClick = Edit PROJECT_CustomDoubleClick = VRM_DoubleClick = Edit VRM_CustomDoubleClick = DEBUGDATABASE_DoubleClick = Edit DEBUGDATABASE_CustomDoubleClick = DEBUGARCHIVE_DoubleClick = Edit DEBUGARCHIVE_CustomDoubleClick = Project_Major_Version = 10 Project_Minor_Version = 1 ================================================ FILE: cpu/alu/simulation/modelsim/wave_alu.do ================================================ onerror {resume} quietly virtual signal -install /test_alu { (context /test_alu )&{test_db_low ,test_db_high }} test_bus quietly virtual signal -install /test_alu { (context /test_alu )&{test_db_high ,test_db_low }} test_bus001 quietly virtual function -install /test_alu/alu_inst -env /test_alu { &{/test_alu/alu_inst/op1_high, /test_alu/alu_inst/op1_low }} OP1 quietly virtual function -install /test_alu/alu_inst -env /test_alu { &{/test_alu/alu_inst/op2_high, /test_alu/alu_inst/op2_low }} OP2 quietly virtual function -install /test_alu/alu_inst -env /test_alu { &{/test_alu/alu_inst/result_hi, /test_alu/alu_inst/result_lo }} RESULT quietly WaveActivateNextPane {} 0 add wave -noupdate -color Gold -itemcolor Gold -radix hexadecimal -childformat {{{/test_alu/db_w[7]} -radix hexadecimal} {{/test_alu/db_w[6]} -radix hexadecimal} {{/test_alu/db_w[5]} -radix hexadecimal} {{/test_alu/db_w[4]} -radix hexadecimal} {{/test_alu/db_w[3]} -radix hexadecimal} {{/test_alu/db_w[2]} -radix hexadecimal} {{/test_alu/db_w[1]} -radix hexadecimal} {{/test_alu/db_w[0]} -radix hexadecimal}} -subitemconfig {{/test_alu/db_w[7]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal} {/test_alu/db_w[6]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal} {/test_alu/db_w[5]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal} {/test_alu/db_w[4]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal} {/test_alu/db_w[3]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal} {/test_alu/db_w[2]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal} {/test_alu/db_w[1]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal} {/test_alu/db_w[0]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal}} /test_alu/db_w add wave -noupdate -color Gold -itemcolor Gold -radix hexadecimal -childformat {{{/test_alu/db[7]} -radix hexadecimal} {{/test_alu/db[6]} -radix hexadecimal} {{/test_alu/db[5]} -radix hexadecimal} {{/test_alu/db[4]} -radix hexadecimal} {{/test_alu/db[3]} -radix hexadecimal} {{/test_alu/db[2]} -radix hexadecimal} {{/test_alu/db[1]} -radix hexadecimal} {{/test_alu/db[0]} -radix hexadecimal}} -subitemconfig {{/test_alu/db[7]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal} {/test_alu/db[6]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal} {/test_alu/db[5]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal} {/test_alu/db[4]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal} {/test_alu/db[3]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal} {/test_alu/db[2]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal} {/test_alu/db[1]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal} {/test_alu/db[0]} {-color Gold -height 15 -itemcolor Gold -radix hexadecimal}} /test_alu/db add wave -noupdate -color {Medium Orchid} -itemcolor Gold -label test_bus -radix hexadecimal -childformat {{{/test_alu/test_bus001[7]} -radix hexadecimal} {{/test_alu/test_bus001[6]} -radix hexadecimal} {{/test_alu/test_bus001[5]} -radix hexadecimal} {{/test_alu/test_bus001[4]} -radix hexadecimal} {{/test_alu/test_bus001[3]} -radix hexadecimal} {{/test_alu/test_bus001[2]} -radix hexadecimal} {{/test_alu/test_bus001[1]} -radix hexadecimal} {{/test_alu/test_bus001[0]} -radix hexadecimal}} -subitemconfig {{/test_alu/test_db_high[3]} {-color {Medium Orchid} -itemcolor Gold -radix hexadecimal} {/test_alu/test_db_high[2]} {-color {Medium Orchid} -itemcolor Gold -radix hexadecimal} {/test_alu/test_db_high[1]} {-color {Medium Orchid} -itemcolor Gold -radix hexadecimal} {/test_alu/test_db_high[0]} {-color {Medium Orchid} -itemcolor Gold -radix hexadecimal} {/test_alu/test_db_low[3]} {-color {Medium Orchid} -itemcolor Gold -radix hexadecimal} {/test_alu/test_db_low[2]} {-color {Medium Orchid} -itemcolor Gold -radix hexadecimal} {/test_alu/test_db_low[1]} {-color {Medium Orchid} -itemcolor Gold -radix hexadecimal} {/test_alu/test_db_low[0]} {-color {Medium Orchid} -itemcolor Gold -radix hexadecimal}} /test_alu/test_bus001 add wave -noupdate /test_alu/clk add wave -noupdate -expand -group Registers -color Pink -radix hexadecimal /test_alu/alu_inst/alu_op1 add wave -noupdate -expand -group Registers -color Pink -radix hexadecimal /test_alu/alu_inst/alu_op2 add wave -noupdate -expand -group Registers -radix hexadecimal -childformat {{(7) -radix hexadecimal} {(6) -radix hexadecimal} {(5) -radix hexadecimal} {(4) -radix hexadecimal} {(3) -radix hexadecimal} {(2) -radix hexadecimal} {(1) -radix hexadecimal} {(0) -radix hexadecimal}} -subitemconfig {{/test_alu/alu_inst/op1_high[3]} {-radix hexadecimal} {/test_alu/alu_inst/op1_high[2]} {-radix hexadecimal} {/test_alu/alu_inst/op1_high[1]} {-radix hexadecimal} {/test_alu/alu_inst/op1_high[0]} {-radix hexadecimal} {/test_alu/alu_inst/op1_low[3]} {-radix hexadecimal} {/test_alu/alu_inst/op1_low[2]} {-radix hexadecimal} {/test_alu/alu_inst/op1_low[1]} {-radix hexadecimal} {/test_alu/alu_inst/op1_low[0]} {-radix hexadecimal}} /test_alu/alu_inst/OP1 add wave -noupdate -expand -group Registers -radix hexadecimal /test_alu/alu_inst/OP2 add wave -noupdate -radix hexadecimal /test_alu/alu_inst/result_hi add wave -noupdate -radix hexadecimal /test_alu/alu_inst/result_lo add wave -noupdate -expand -group {Bus control} /test_alu/alu_oe add wave -noupdate -expand -group {Bus control} /test_alu/alu_op1_oe add wave -noupdate -expand -group {Bus control} /test_alu/alu_op2_oe add wave -noupdate -expand -group {Bus control} /test_alu/alu_res_oe add wave -noupdate -expand -group {Bus control} /test_alu/alu_shift_oe add wave -noupdate -expand -group {Bus control} /test_alu/alu_bs_oe add wave -noupdate -expand -group {Input shifter} /test_alu/alu_shift_db0 add wave -noupdate -expand -group {Input shifter} /test_alu/alu_shift_db7 add wave -noupdate -expand -group {Input shifter} /test_alu/alu_shift_in add wave -noupdate -expand -group {Input shifter} /test_alu/alu_shift_right add wave -noupdate -expand -group {Input shifter} /test_alu/alu_shift_left add wave -noupdate /test_alu/bsel add wave -noupdate -expand -group {Operand selectors} /test_alu/alu_op1_sel_bus add wave -noupdate -expand -group {Operand selectors} /test_alu/alu_op1_sel_low add wave -noupdate -expand -group {Operand selectors} /test_alu/alu_op1_sel_zero add wave -noupdate -expand -group {Operand selectors} /test_alu/alu_op2_sel_bus add wave -noupdate -expand -group {Operand selectors} /test_alu/alu_op2_sel_lq add wave -noupdate -expand -group {Operand selectors} /test_alu/alu_op2_sel_zero add wave -noupdate -expand -group {ALU core} /test_alu/alu_core_R add wave -noupdate -expand -group {ALU core} /test_alu/alu_core_S add wave -noupdate -expand -group {ALU core} /test_alu/alu_core_V add wave -noupdate -expand -group {ALU core} /test_alu/alu_sel_op2_neg add wave -noupdate -expand -group {ALU core} /test_alu/alu_sel_op2_high add wave -noupdate -expand -group {ALU core} /test_alu/alu_op_low add wave -noupdate -expand -group Flags /test_alu/alu_core_cf_in add wave -noupdate -expand -group Flags /test_alu/alu_core_cf_out add wave -noupdate -expand -group Flags /test_alu/alu_parity_in add wave -noupdate -expand -group Flags /test_alu/alu_parity_out add wave -noupdate -expand -group Flags /test_alu/alu_zero add wave -noupdate -expand -group Flags /test_alu/alu_vf_out add wave -noupdate -expand -group Flags /test_alu/alu_sf_out add wave -noupdate -expand -group Flags /test_alu/alu_xf_out add wave -noupdate -expand -group Flags /test_alu/alu_yf_out add wave -noupdate -expand -group Flags /test_alu/alu_low_gt_9 add wave -noupdate -expand -group Flags /test_alu/alu_high_gt_9 add wave -noupdate -expand -group Flags /test_alu/alu_high_eq_9 add wave -noupdate /test_alu/cf add wave -noupdate /test_alu/pf add wave -noupdate /test_alu/hf TreeUpdate [SetDefaultTree] WaveRestoreCursors {{Cursor 1} {1800 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 180 configure wave -valuecolwidth 58 configure wave -justifyvalue right configure wave -signalnamewidth 1 configure wave -snapdistance 10 configure wave -datasetprefix 0 configure wave -rowmargin 4 configure wave -childrowmargin 2 configure wave -gridoffset 0 configure wave -gridperiod 1 configure wave -griddelta 40 configure wave -timeline 1 configure wave -timelineunits us update WaveRestoreZoom {0 ns} {4800 ns} ================================================ FILE: cpu/alu/simulation/modelsim/wave_core.do ================================================ onerror {resume} quietly WaveActivateNextPane {} 0 add wave -noupdate -radix hexadecimal /test_core/op1_sig add wave -noupdate -radix hexadecimal /test_core/op2_sig add wave -noupdate /test_core/cy_in_sig add wave -noupdate -color Gold -itemcolor Gold -radix hexadecimal /test_core/result_sig add wave -noupdate -color Gold -format Literal -itemcolor Gold /test_core/cy_out_sig add wave -noupdate -color Gray75 -itemcolor Gray75 /test_core/vf_out_sig add wave -noupdate /test_core/R_sig add wave -noupdate /test_core/S_sig add wave -noupdate /test_core/V_sig TreeUpdate [SetDefaultTree] WaveRestoreCursors {{Cursor 1} {2000 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 140 configure wave -valuecolwidth 53 configure wave -justifyvalue right configure wave -signalnamewidth 1 configure wave -snapdistance 10 configure wave -datasetprefix 0 configure wave -rowmargin 4 configure wave -childrowmargin 2 configure wave -gridoffset 0 configure wave -gridperiod 1 configure wave -griddelta 40 configure wave -timeline 1 configure wave -timelineunits us update WaveRestoreZoom {0 ns} {4400 ns} ================================================ FILE: cpu/alu/simulation/modelsim/wave_mux_3z.do ================================================ onerror {resume} quietly WaveActivateNextPane {} 0 add wave -noupdate -radix hexadecimal /test_mux_3z/a_sig add wave -noupdate -radix hexadecimal /test_mux_3z/b_sig add wave -noupdate -color Gold -itemcolor Gold -radix hexadecimal /test_mux_3z/Q_sig add wave -noupdate /test_mux_3z/sel_a_sig add wave -noupdate /test_mux_3z/sel_b_sig add wave -noupdate /test_mux_3z/sel_zero_sig add wave -noupdate /test_mux_3z/ena_out_sig TreeUpdate [SetDefaultTree] WaveRestoreCursors {{Cursor 1} {600 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 118 configure wave -valuecolwidth 59 configure wave -justifyvalue right configure wave -signalnamewidth 1 configure wave -snapdistance 10 configure wave -datasetprefix 0 configure wave -rowmargin 4 configure wave -childrowmargin 2 configure wave -gridoffset 0 configure wave -gridperiod 1 configure wave -griddelta 40 configure wave -timeline 1 configure wave -timelineunits us update WaveRestoreZoom {0 ns} {3800 ns} ================================================ FILE: cpu/alu/simulation/modelsim/wave_prep_daa.do ================================================ onerror {resume} quietly WaveActivateNextPane {} 0 add wave -noupdate -color Gold -itemcolor Gold -radix hexadecimal /test_prep_daa/low_sig add wave -noupdate -color Gold -itemcolor Gold -radix hexadecimal /test_prep_daa/high_sig add wave -noupdate /test_prep_daa/low_gt_9_sig add wave -noupdate /test_prep_daa/high_gt_9_sig add wave -noupdate /test_prep_daa/high_eq_9_sig TreeUpdate [SetDefaultTree] WaveRestoreCursors {{Cursor 1} {1400 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 138 configure wave -valuecolwidth 60 configure wave -justifyvalue right configure wave -signalnamewidth 1 configure wave -snapdistance 10 configure wave -datasetprefix 0 configure wave -rowmargin 4 configure wave -childrowmargin 2 configure wave -gridoffset 0 configure wave -gridperiod 1 configure wave -griddelta 40 configure wave -timeline 1 configure wave -timelineunits us update WaveRestoreZoom {0 ns} {4100 ns} ================================================ FILE: cpu/alu/simulation/modelsim/wave_shifter_core.do ================================================ onerror {resume} quietly virtual signal -install /test_shifter_core { (context /test_shifter_core )&{out_high ,out_low }} db_out quietly WaveActivateNextPane {} 0 add wave -noupdate -radix binary -childformat {{{/test_shifter_core/db[7]} -radix binary} {{/test_shifter_core/db[6]} -radix binary} {{/test_shifter_core/db[5]} -radix binary} {{/test_shifter_core/db[4]} -radix binary} {{/test_shifter_core/db[3]} -radix binary} {{/test_shifter_core/db[2]} -radix binary} {{/test_shifter_core/db[1]} -radix binary} {{/test_shifter_core/db[0]} -radix binary}} -subitemconfig {{/test_shifter_core/db[7]} {-height 15 -radix binary} {/test_shifter_core/db[6]} {-height 15 -radix binary} {/test_shifter_core/db[5]} {-height 15 -radix binary} {/test_shifter_core/db[4]} {-height 15 -radix binary} {/test_shifter_core/db[3]} {-height 15 -radix binary} {/test_shifter_core/db[2]} {-height 15 -radix binary} {/test_shifter_core/db[1]} {-height 15 -radix binary} {/test_shifter_core/db[0]} {-height 15 -radix binary}} /test_shifter_core/db add wave -noupdate -color Gold -itemcolor Gold /test_shifter_core/db_out add wave -noupdate -color {Medium Aquamarine} -itemcolor {Medium Aquamarine} /test_shifter_core/shift_db0 add wave -noupdate -color Cyan -itemcolor Cyan /test_shifter_core/shift_db7 add wave -noupdate /test_shifter_core/shift_in add wave -noupdate /test_shifter_core/shift_left add wave -noupdate /test_shifter_core/shift_right add wave -noupdate /test_shifter_core/out_high add wave -noupdate /test_shifter_core/out_low TreeUpdate [SetDefaultTree] WaveRestoreCursors {{Cursor 1} {5100 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 143 configure wave -valuecolwidth 64 configure wave -justifyvalue right configure wave -signalnamewidth 1 configure wave -snapdistance 10 configure wave -datasetprefix 0 configure wave -rowmargin 4 configure wave -childrowmargin 2 configure wave -gridoffset 0 configure wave -gridperiod 1 configure wave -griddelta 40 configure wave -timeline 1 configure wave -timelineunits us update WaveRestoreZoom {0 ns} {9500 ns} ================================================ FILE: cpu/alu/simulation/modelsim/wave_slice.do ================================================ onerror {resume} quietly WaveActivateNextPane {} 0 add wave -noupdate -radix hexadecimal /test_slice/op1_sig add wave -noupdate -radix hexadecimal /test_slice/op2_sig add wave -noupdate /test_slice/cy_in_sig add wave -noupdate -color Gold -itemcolor Gold -radix hexadecimal /test_slice/result_sig add wave -noupdate -color Gold -format Literal -itemcolor Gold /test_slice/cy_out_sig add wave -noupdate /test_slice/R_sig add wave -noupdate /test_slice/S_sig add wave -noupdate /test_slice/V_sig add wave -noupdate /test_slice/cy_out_D_sig add wave -noupdate /test_slice/cy_out_C_sig add wave -noupdate /test_slice/cy_out_B_sig TreeUpdate [SetDefaultTree] WaveRestoreCursors {{Cursor 1} {2000 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 132 configure wave -valuecolwidth 57 configure wave -justifyvalue right configure wave -signalnamewidth 1 configure wave -snapdistance 10 configure wave -datasetprefix 0 configure wave -rowmargin 4 configure wave -childrowmargin 2 configure wave -gridoffset 0 configure wave -gridperiod 1 configure wave -griddelta 40 configure wave -timeline 1 configure wave -timelineunits us update WaveRestoreZoom {0 ns} {4100 ns} ================================================ FILE: cpu/alu/test_alu.qpf ================================================ # -------------------------------------------------------------------------- # # # Copyright (C) 1991-2013 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Altera Program License # Subscription Agreement, Altera MegaCore Function License # Agreement, or other applicable license agreement, including, # without limitation, that your use is for the sole purpose of # programming logic devices manufactured by Altera and sold by # Altera or its authorized distributors. Please refer to the # applicable agreement for further details. # # -------------------------------------------------------------------------- # # # Quartus II 64-Bit # Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition # Date created = 09:01:54 October 13, 2014 # # -------------------------------------------------------------------------- # QUARTUS_VERSION = "13.0" DATE = "09:01:54 October 13, 2014" # Revisions PROJECT_REVISION = "test_alu" ================================================ FILE: cpu/alu/test_alu.qsf ================================================ # -------------------------------------------------------------------------- # # # Copyright (C) 1991-2013 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Altera Program License # Subscription Agreement, Altera MegaCore Function License # Agreement, or other applicable license agreement, including, # without limitation, that your use is for the sole purpose of # programming logic devices manufactured by Altera and sold by # Altera or its authorized distributors. Please refer to the # applicable agreement for further details. # # -------------------------------------------------------------------------- # # # Quartus II 64-Bit # Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition # Date created = 09:01:54 October 13, 2014 # # -------------------------------------------------------------------------- # # # Notes: # # 1) The default values for assignments are stored in the file: # test_alu_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # # 2) Altera recommends that you do not modify this file. This # file is updated automatically by the Quartus II software # and any changes you make may be lost or overwritten. # # -------------------------------------------------------------------------- # set_global_assignment -name FAMILY "Cyclone II" set_global_assignment -name DEVICE EP2C20F484C7 set_global_assignment -name TOP_LEVEL_ENTITY alu_control set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:01:54 OCTOBER 13, 2014" set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name BDF_FILE alu_slice.bdf set_global_assignment -name BDF_FILE alu_shifter_core.bdf set_global_assignment -name BDF_FILE alu_select.bdf set_global_assignment -name BDF_FILE alu_prep_daa.bdf set_global_assignment -name BDF_FILE alu_mux_8.bdf set_global_assignment -name BDF_FILE alu_mux_4.bdf set_global_assignment -name BDF_FILE alu_mux_3z.bdf set_global_assignment -name BDF_FILE alu_mux_2z.bdf set_global_assignment -name BDF_FILE alu_mux_2.bdf set_global_assignment -name BDF_FILE alu_flags.bdf set_global_assignment -name BDF_FILE alu_core.bdf set_global_assignment -name BDF_FILE alu_control.bdf set_global_assignment -name BDF_FILE alu_bit_select.bdf set_global_assignment -name BDF_FILE alu.bdf set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top ================================================ FILE: cpu/alu/test_alu.sv ================================================ //============================================================== // Test complete ALU block //============================================================== `timescale 100 ns/ 100 ns module test_alu; // ----------------- CLOCKS AND RESET ----------------- // Define one full T-clock cycle delay `define T #2 bit clk = 1; initial repeat (24) #1 clk = ~clk; // ------------------------ BUS LOGIC ------------------------ // Bus control logic alu_oe; // ALU unit output enable to the outside bus // Write to the ALU internal data buses logic alu_op1_oe; // Enable writing by the OP1 latch logic alu_op2_oe; // Enable writing by the OP2 latch logic alu_res_oe; // Enable writing by the ALU result latch logic alu_shift_oe; // Enable writing by the input shifter logic alu_bs_oe; // Enable writing by the input bit selector // Our own test internal mux to select ALU bus writers logic [2:0] bus_sel; // Select internal bus writer: typedef enum logic[2:0] { BUS_HIGHZ, BUS_OP1, BUS_OP2, BUS_RES, BUS_SHIFT, BUS_BS } bus_t; // Mux to select only one block to drive internal ALU bus always_comb begin alu_op1_oe = 0; alu_op2_oe = 0; alu_res_oe = 0; alu_shift_oe = 0; alu_bs_oe = 0; case (bus_sel) BUS_OP1 : alu_op1_oe = 1; BUS_OP2 : alu_op2_oe = 1; BUS_RES : alu_res_oe = 1; BUS_SHIFT : alu_shift_oe = 1; BUS_BS : alu_bs_oe = 1; endcase end // ------------------------ INPUT ------------------------ // Input shifter control wires and output from the shifter logic alu_shift_in; // Carry-in into the shifter logic alu_shift_right; // Shift right logic alu_shift_left; // Shift left wire alu_shift_db0; // Output db[0] from the shifter for the shift logic wire alu_shift_db7; // Output db[7] from the shifter for the shift logic // Input bit selector control wires logic [2:0] bsel; // Selects a bit to generate // Operator latch 1 mux select logic alu_op1_sel_bus; // OP1 is read from the internal bus logic alu_op1_sel_low; // OP1 is read from the low nibble logic alu_op1_sel_zero; // OP1 is loaded with zero // Operator 2 latch mux select logic alu_op2_sel_bus; // OP2 is read from the internal bus logic alu_op2_sel_lq; // OP2 is read from the L-Q gates (see schematic) logic alu_op2_sel_zero; // OP2 is loaded with zero // ALU operator mux select logic alu_sel_op2_neg; // Selects complemented OP2 logic alu_sel_op2_high; // Selects high OP2 nibble as opposed to low // ALU Core operations logic alu_core_cf_in; // Carry input into the ALU core logic alu_core_R; // Operation control "R" logic alu_core_S; // Operation control "S" logic alu_core_V; // Operation control "V" logic alu_op_low; // Signal to compute and store the low nibble (see schematic) wire alu_core_cf_out; // Output carry bit from the ALU core wire alu_vf_out; // Output overflow flag from the ALU // Zero-detect, parity calculation, flag preparation and DAA-preparation logic logic alu_parity_in; // Input parity bit from a previous nibble wire alu_parity_out; // Output parity on the result and a previous nibble wire alu_zero; // Output signal that the result is zero wire alu_sf_out; // Output signal containing the result sign bit wire alu_yf_out; // Output signal containing the result[5] bit which is YF wire alu_xf_out; // Output signal containing the result[3] bit which is XF wire alu_low_gt_9; // Output signal that the low nibble result > 9 wire alu_high_gt_9; // Output signal that the high nibble result > 9 wire alu_high_eq_9; // Output signal that the high nibble result == 9 // ------------------------ BUSSES ------------------------ // Bidirectional data bus, interface to the outside world logic [7:0] db_w; // Drive it using this bus wire [7:0] db; // Read it using this bus wire [3:0] test_db_low; // Test point to probe internal low nibble bus wire [3:0] test_db_high; // Test point to probe internal high nibble bus // ------------------------ FLAGS ------------------------ reg cf; // Carry flag reg pf; // Parity flag reg hf; // Half-carry flag // ----------------- TEST ------------------- initial begin // Init / reset db_w = 8'h00; bus_sel = BUS_HIGHZ; alu_shift_in = 0; alu_shift_right = 0; alu_shift_left = 0; bsel = 2'h0; alu_op1_sel_bus = 0; alu_op1_sel_low = 0; alu_op1_sel_zero = 0; alu_op2_sel_bus = 0; alu_op2_sel_lq = 0; alu_op2_sel_zero = 0; alu_sel_op2_neg = 0; alu_sel_op2_high = 0; alu_parity_in = 0; alu_core_cf_in = 0; alu_core_R = 0; alu_core_S = 0; alu_core_V = 0; alu_op_low = 0; cf = 0; hf = 0; pf = 0; //------------------------------------------------------------ // Test loading to internal bus from the input shifter through the OP1 latch `T db_w = 8'h24; // High: 0010 Low: 0100 bus_sel = BUS_SHIFT; alu_shift_right = 1; // Enable shift and shift *right* alu_shift_in = 1; // shift in <- 1 alu_op1_sel_bus = 1; // Write into the OP1 latch `T db_w = 'z; alu_op1_sel_bus = 0; alu_shift_in = 0; bus_sel = BUS_OP1; // Read back OP1 latch alu_shift_right = 0; // Expected output on the external ALU bus : 1001 0010, 0x92 `T assert(db==8'h92); // Reset bus_sel = BUS_HIGHZ; //------------------------------------------------------------ // Test loading to internal bus from the input bit selector through the OP2 latch `T db_w = 'z; // Not using external bus to load, but the bit-select bsel = 2'h3; // Bit 3: 0000 1000 bus_sel = BUS_BS; alu_op2_sel_bus = 1; // Write into the OP2 latch `T db_w = 'z; alu_op2_sel_bus = 0; alu_shift_in = 0; bus_sel = BUS_OP2; bsel = 2'h0; // Expected output on the external ALU bus : 0000 1000, 0x08 `T assert(db==8'h08); // Reset `T bus_sel = BUS_HIGHZ; //------------------------------------------------------------ // Test the full adding function, ADD `T db_w = 8'h8C; // Operand 1: 8C bus_sel = BUS_SHIFT; // Shifter writes to internal bus alu_op1_sel_bus = 1; // Write into the OP1 latch `T db_w = 8'h68; // Operand 1: 68 alu_op_low = 1; // Perform the low nibble calculation alu_op1_sel_bus = 0; bus_sel = BUS_SHIFT; // Shifter writes to internal bus alu_op2_sel_bus = 1; // Write into the OP2 latch // Do a low nibble addition in this cycle alu_sel_op2_high = 0; // ALU select low OP nibble alu_parity_in = 0; // Reset parity of the nibble alu_core_cf_in = 0; // CF in 0 alu_core_R = 0; alu_core_S = 0; alu_core_V = 0; hf = alu_core_cf_out; // Load the HF with the half-carry out pf = alu_parity_out; // Load the PF with the parity of the nibble result `T db_w = 'z; alu_op_low = 0; // Perform the high nibble calculation alu_op2_sel_bus = 0; alu_sel_op2_high = 1; // ALU select high OP2 nibble alu_core_cf_in = 0; alu_core_cf_in = hf; // Carry in the half-carry alu_parity_in = pf; // Parity in the parity of the low result nibble bus_sel = BUS_RES; // ALU result latch writes to the bus // Expected output on the external ALU bus : 8C + 68 = F4 `T assert(db==8'hF4); // Reset bus_sel = BUS_HIGHZ; `T $display("End of test"); end //-------------------------------------------------------------- // External bus logic assign db = db_w; // Drive 3-state bidirectional bus always_comb // Output internal ALU bus only when our begin // test is not driving it if (db_w==='z) alu_oe = 1; else alu_oe = 0; end //-------------------------------------------------------------- // Instantiate ALU block and assign identical nets and variables //-------------------------------------------------------------- alu alu_inst( .* ); endmodule ================================================ FILE: cpu/alu/test_core.sv ================================================ //============================================================== // Test ALU core //============================================================== `timescale 100 ns/ 100 ns module test_core; // ----------------- INPUT ----------------- reg [3:0] op1_sig; // Operand 1 reg [3:0] op2_sig; // Operand 2 reg cy_in_sig; // Carry in (to slice D) reg R_sig; // Operation control "R" reg S_sig; // Operation control "S" reg V_sig; // Operation control "V" // ----------------- OUTPUT ----------------- wire cy_out_sig; // Carry out (from slice A) wire vf_out_sig; // Overflow out wire [3:0] result_sig; // Result bits // ----------------- TEST ------------------- `define CHECK(arg) \ assert(result_sig==arg); initial begin //------------------------------------------------------------ // Test ADD/ADC: R=0 S=0 V=0 Cin for ADC operation R_sig = 0; S_sig = 0; V_sig = 0; op1_sig = 4'h0; // 0 + 0 + 0 = 0 op2_sig = 4'h0; cy_in_sig = 0; #1 `CHECK(4'h0); cy_in_sig = 1; // 0 + 0 + 1 = 1 #1 `CHECK(4'h1); op1_sig = 4'h2; // 2 + 8 + 0 = A op2_sig = 4'h8; cy_in_sig = 0; #1 `CHECK(4'hA); cy_in_sig = 1; // 2 + 8 + 1 = B #1 `CHECK(4'hB); op1_sig = 4'hB; // B + 4 + 0 = F op2_sig = 4'h4; cy_in_sig = 0; #1 `CHECK(4'hF); cy_in_sig = 1; // B + 4 + 1 = 0 + CY #1 `CHECK(4'h0); op1_sig = 4'hD; // D + 6 + 0 = 3 + CY op2_sig = 4'h6; cy_in_sig = 0; #1 `CHECK(4'h3); cy_in_sig = 1; // D + 6 + 1 = 4 + CY #1 `CHECK(4'h4); //------------------------------------------------------------ // Test XOR: R=1 S=0 V=0 Cin=0 #1 R_sig = 1; S_sig = 0; V_sig = 0; cy_in_sig = 0; op1_sig = 4'h0; // 0 ^ 0 = 0 op2_sig = 4'h0; #1 `CHECK(4'h0); op1_sig = 4'h3; // 3 ^ C = F op2_sig = 4'hC; #1 `CHECK(4'hF); op1_sig = 4'h6; // 6 ^ 3 = 5 op2_sig = 4'h3; #1 `CHECK(4'h5); op1_sig = 4'hF; // F ^ F = 0 op2_sig = 4'hF; #1 `CHECK(4'h0); //------------------------------------------------------------ // Test AND: R=0 S=1 V=0 Cin=1 #1 R_sig = 0; S_sig = 1; V_sig = 0; cy_in_sig = 1; op1_sig = 4'h0; // 0 & 0 = 0 op2_sig = 4'h0; #1 `CHECK(4'h0); op1_sig = 4'h3; // 3 & C = 0 op2_sig = 4'hC; #1 `CHECK(4'h0); op1_sig = 4'h6; // 6 & 3 = 2 op2_sig = 4'h3; #1 `CHECK(4'h2); op1_sig = 4'hF; // F & F = F op2_sig = 4'hF; #1 `CHECK(4'hF); //------------------------------------------------------------ // Test OR: R=1 S=1 V=1 Cin=0 #1 R_sig = 1; S_sig = 1; V_sig = 1; cy_in_sig = 0; op1_sig = 4'h0; // 0 | 0 = 0 op2_sig = 4'h0; #1 `CHECK(4'h0); op1_sig = 4'h3; // 3 | C = F op2_sig = 4'hC; #1 `CHECK(4'hF); op1_sig = 4'h6; // 6 | 3 = 7 op2_sig = 4'h3; #1 `CHECK(4'h7); op1_sig = 4'hF; // F | F = F op2_sig = 4'hF; #1 `CHECK(4'hf); #1 $display("End of test"); end //-------------------------------------------------------------- // Instantiate ALU core block //-------------------------------------------------------------- alu_core alu_core_inst ( .cy_in(cy_in_sig) , // input cy_in_sig .op1(op1_sig[3:0]) , // input [3:0] op1_sig .op2(op2_sig[3:0]) , // input [3:0] op2_sig .S(S_sig) , // input S_sig .V(V_sig) , // input V_sig .R(R_sig) , // input R_sig .cy_out(cy_out_sig) , // output cy_out_sig .vf_out(vf_out_sig) , // output vf_out_sig .result(result_sig[3:0]) // output [3:0] result_sig ); endmodule ================================================ FILE: cpu/alu/test_mux_3z.sv ================================================ //============================================================== // Test ALU op1 MUX which is a bit more complicated //============================================================== `timescale 100 ns/ 100 ns module test_mux_3z; // ----------------- INPUT ----------------- reg sel_a_sig; reg sel_b_sig; reg sel_zero_sig; reg [3:0] a_sig; reg [3:0] b_sig; // ----------------- OUTPUT ----------------- wire [3:0] Q_sig; // Output of a mux wire ena_out_sig; // Write enable to the latch // ----------------- TEST ------------------- `define CHECK(arg) \ assert(Q_sig==arg); initial begin sel_a_sig = 0; sel_b_sig = 0; sel_zero_sig = 0; a_sig = 4'hA; b_sig = 4'h5; #1 `CHECK(0); sel_zero_sig = 0; sel_a_sig = 0; sel_b_sig = 0; #1 `CHECK(0); sel_zero_sig = 1; sel_a_sig = 0; sel_b_sig = 0; #1 `CHECK(0); sel_zero_sig = 0; sel_a_sig = 1; sel_b_sig = 0; #1 `CHECK(a_sig); sel_zero_sig = 0; sel_a_sig = 0; sel_b_sig = 1; #1 `CHECK(b_sig); sel_zero_sig = 1; sel_a_sig = 1; sel_b_sig = 1; #1 `CHECK(0); #1 $display("End of test"); end //-------------------------------------------------------------- // Instantiate a mux //-------------------------------------------------------------- alu_mux_3z alu_mux_3z_inst ( .sel_zero(sel_zero_sig) , // input sel_zero_sig .sel_a(sel_a_sig) , // input sel_a_sig .b(b_sig) , // input [3:0] b_sig .sel_b(sel_b_sig) , // input sel_b_sig .a(a_sig) , // input [3:0] a_sig .Q(Q_sig) , // output [3:0] Q_sig .ena(ena_out_sig) // output ena_out_sig ); endmodule ================================================ FILE: cpu/alu/test_prep_daa.sv ================================================ //============================================================== // Test ALU state preparation for DAA instruction //============================================================== `timescale 100 ns/ 100 ns module test_prep_daa; // ----------------- INPUT ----------------- reg [3:0] low_sig; // Input data bus A (independent) reg [3:0] high_sig; // Input data bus B (independent) // ----------------- OUTPUT ----------------- wire low_gt_9_sig; // low bus > 9 wire high_gt_9_sig; // high bus > 9 wire high_eq_9_sig; // high bus == 9 // ----------------- TEST ------------------- `define CHECK \ assert(low_gt_9_sig==low_sig>9 && high_gt_9_sig==high_sig>9 && high_eq_9_sig==(high_sig==9)); initial begin low_sig = 4'h0; high_sig = 4'h0; #1 `CHECK low_sig = 4'h1; high_sig = 4'h1; #1 `CHECK low_sig = 4'h2; high_sig = 4'h2; #1 `CHECK low_sig = 4'h3; high_sig = 4'h3; #1 `CHECK low_sig = 4'h4; high_sig = 4'h4; #1 `CHECK low_sig = 4'h5; high_sig = 4'h5; #1 `CHECK low_sig = 4'h6; high_sig = 4'h6; #1 `CHECK low_sig = 4'h7; high_sig = 4'h7; #1 `CHECK low_sig = 4'h8; high_sig = 4'h8; #1 `CHECK low_sig = 4'h9; high_sig = 4'h9; #1 `CHECK low_sig = 4'hA; high_sig = 4'hA; #1 `CHECK low_sig = 4'hB; high_sig = 4'hB; #1 `CHECK low_sig = 4'hC; high_sig = 4'hC; #1 `CHECK low_sig = 4'hD; high_sig = 4'hD; #1 `CHECK low_sig = 4'hE; high_sig = 4'hE; #1 `CHECK low_sig = 4'hF; high_sig = 4'hF; #1 `CHECK #1 $display("End of test"); end //-------------------------------------------------------------- // Instantiate prep-DAA block //-------------------------------------------------------------- alu_prep_daa alu_prep_daa_inst ( .low(low_sig) , // input [3:0] low_sig .high(high_sig) , // input [3:0] high_sig .low_gt_9(low_gt_9_sig) , // output low_gt_9_sig .high_eq_9(high_eq_9_sig) , // output high_eq_9_sig .high_gt_9(high_gt_9_sig) // output high_gt_9_sig ); endmodule ================================================ FILE: cpu/alu/test_shifter_core.sv ================================================ //============================================================== // Test ALU shifter core block //============================================================== `timescale 100 ns/ 100 ns module test_shifter_core; // ----------------- INPUT ----------------- logic [7:0] db; // Input data bus logic shift_in; // Input bit to be shifted in logic shift_left; // Input control to left-shift logic shift_right; // Input control to right-shift // ----------------- OUTPUT ----------------- wire shift_db0; // db[0] for shift logic wire shift_db7; // db[7] for shift logic wire [3:0] out_high; // To internal ALU bus, high nibble wire [3:0] out_low; // ..low nibble // ----------------- TEST ------------------- `define CHECK(arg) \ assert({out_high,out_low}==arg); initial begin db = 8'h00; shift_left = 0; shift_right = 0; shift_in = 0; //------------------------------------------------------------ // Test load without shifting db = 8'hAA; #1 `CHECK(8'hAA); db = 8'h55; #1 `CHECK(8'h55); //------------------------------------------------------------ // Test right shift, no carry-in #1 db = 8'b00000001; shift_right = 1; shift_in = 0; #1 `CHECK(8'b00000000); db = 8'b00000010; #1 `CHECK(8'b00000001); db = 8'b00000100; #1 `CHECK(8'b00000010); db = 8'b00001000; #1 `CHECK(8'b00000100); db = 8'b00010000; #1 `CHECK(8'b00001000); db = 8'b00100000; #1 `CHECK(8'b00010000); db = 8'b01000000; #1 `CHECK(8'b00100000); db = 8'b10000000; #1 `CHECK(8'b01000000); // With carry-in #1 db = 8'b00000001; shift_in = 1; #1 `CHECK(8'b10000000); db = 8'b00000010; #1 `CHECK(8'b10000001); db = 8'b00000100; #1 `CHECK(8'b10000010); db = 8'b00001000; #1 `CHECK(8'b10000100); db = 8'b00010000; #1 `CHECK(8'b10001000); db = 8'b00100000; #1 `CHECK(8'b10010000); db = 8'b01000000; #1 `CHECK(8'b10100000); db = 8'b10000000; #1 `CHECK(8'b11000000); //------------------------------------------------------------ // Test left shift, no carry-in #1 db = 8'b00000001; shift_right = 0; shift_left = 1; shift_in = 0; #1 `CHECK(8'b00000010); db = 8'b00000010; #1 `CHECK(8'b00000100); db = 8'b00000100; #1 `CHECK(8'b00001000); db = 8'b00001000; #1 `CHECK(8'b00010000); db = 8'b00010000; #1 `CHECK(8'b00100000); db = 8'b00100000; #1 `CHECK(8'b01000000); db = 8'b01000000; #1 `CHECK(8'b10000000); db = 8'b10000000; #1 `CHECK(8'b00000000); // With carry-in #1 db = 8'b00000001; shift_in = 1; #1 `CHECK(8'b00000011); db = 8'b00000010; #1 `CHECK(8'b00000101); db = 8'b00000100; #1 `CHECK(8'b00001001); db = 8'b00001000; #1 `CHECK(8'b00010001); db = 8'b00010000; #1 `CHECK(8'b00100001); db = 8'b00100000; #1 `CHECK(8'b01000001); db = 8'b01000000; #1 `CHECK(8'b10000001); db = 8'b10000000; #1 `CHECK(8'b00000001); //------------------------------------------------------------ // Test right shift, no carry-in - special SRA instruction // This instruction simply duplicates bit [7] instead of using CY #1 db = 8'b00000001; shift_right = 1; shift_left = 0; shift_in = shift_db7; #1 `CHECK(8'b10000000); db = 8'b00000010; #1 `CHECK(8'b10000001); db = 8'b00000100; #1 `CHECK(8'b10000010); db = 8'b00001000; #1 `CHECK(8'b10000100); db = 8'b00010000; #1 `CHECK(8'b10001000); db = 8'b00100000; #1 `CHECK(8'b10010000); db = 8'b01000000; #1 `CHECK(8'b10100000); db = 8'b10000000; #1 `CHECK(8'b11000000); // With carry-in #1 db = 8'b00000001; shift_in = 1; #1 `CHECK(8'b10000000); db = 8'b00000010; #1 `CHECK(8'b10000001); db = 8'b00000100; #1 `CHECK(8'b10000010); db = 8'b00001000; #1 `CHECK(8'b10000100); db = 8'b00010000; #1 `CHECK(8'b10001000); db = 8'b00100000; #1 `CHECK(8'b10010000); db = 8'b01000000; #1 `CHECK(8'b10100000); db = 8'b10000000; #1 `CHECK(8'b11000000); #1 $display("End of test"); end //-------------------------------------------------------------- // Instantiate shifter core block and assign identical nets and variables //-------------------------------------------------------------- alu_shifter_core alu_shifter_core_inst( .* ); endmodule ================================================ FILE: cpu/alu/test_slice.sv ================================================ //============================================================== // Test ALU slice //============================================================== `timescale 100 ns/ 100 ns module test_slice; // ----------------- INPUT ----------------- reg [3:0] op1_sig; // Operand 1 reg [3:0] op2_sig; // Operand 2 reg cy_in_sig; // Carry in (to slice D) reg R_sig; // Operation control "R" reg S_sig; // Operation control "S" reg V_sig; // Operation control "V" // ----------------- OUTPUT ----------------- wire cy_out_sig; // Carry out (from slice A) wire [3:0] result_sig; // Result bits // ----------------- CONNECTIONS ----------------- wire cy_out_D_sig; // Carry out from slice D into slice C wire cy_out_C_sig; // Carry out from slice C into slice B wire cy_out_B_sig; // Carry out from slice B into slice A // ----------------- TEST ------------------- `define CHECK(arg) \ assert(result_sig==arg); initial begin op1_sig = '0; op2_sig = '0; cy_in_sig = 0; R_sig = 0; S_sig = 0; V_sig = 0; //------------------------------------------------------------ // Test ADD/ADC: R=0 S=0 V=0 Cin for ADC operation R_sig = 0; S_sig = 0; V_sig = 0; op1_sig = 4'h0; // 0 + 0 + 0 = 0 op2_sig = 4'h0; cy_in_sig = 0; #1 `CHECK(0); cy_in_sig = 1; // 0 + 0 + 1 = 1 #1 `CHECK(1); op1_sig = 4'h2; // 2 + 8 + 0 = A op2_sig = 4'h8; cy_in_sig = 0; #1 `CHECK(4'hA); cy_in_sig = 1; // 2 + 8 + 1 = B #1 `CHECK(4'hB); op1_sig = 4'hB; // B + 4 + 0 = F op2_sig = 4'h4; cy_in_sig = 0; #1 `CHECK(4'hF); cy_in_sig = 1; // B + 4 + 1 = 0 + CY #1 `CHECK(4'h0); op1_sig = 4'hD; // D + 6 + 0 = 3 + CY op2_sig = 4'h6; cy_in_sig = 0; #1 `CHECK(4'h3); cy_in_sig = 1; // D + 6 + 1 = 4 + CY #1 `CHECK(4'h4); //------------------------------------------------------------ // Test XOR: R=1 S=0 V=0 Cin=0 #1 R_sig = 1; S_sig = 0; V_sig = 0; cy_in_sig = 0; op1_sig = 4'h0; // 0 ^ 0 = 0 op2_sig = 4'h0; #1 `CHECK(4'h0); op1_sig = 4'h3; // 3 ^ C = F op2_sig = 4'hC; #1 `CHECK(4'hF); op1_sig = 4'h6; // 6 ^ 3 = 5 op2_sig = 4'h3; #1 `CHECK(4'h5); op1_sig = 4'hF; // F ^ F = 0 op2_sig = 4'hF; #1 `CHECK(4'h0); //------------------------------------------------------------ // Test AND: R=0 S=1 V=0 Cin=1 #1 R_sig = 0; S_sig = 1; V_sig = 0; cy_in_sig = 1; op1_sig = 4'h0; // 0 & 0 = 0 op2_sig = 4'h0; #1 `CHECK(4'h0); op1_sig = 4'h3; // 3 & C = 0 op2_sig = 4'hC; #1 `CHECK(4'h0); op1_sig = 4'h6; // 6 & 3 = 2 op2_sig = 4'h3; #1 `CHECK(4'h2); op1_sig = 4'hF; // F & F = F op2_sig = 4'hF; #1 `CHECK(4'hF); //------------------------------------------------------------ // Test OR: R=1 S=1 V=1 Cin=0 #1 R_sig = 1; S_sig = 1; V_sig = 1; cy_in_sig = 0; op1_sig = 4'h0; // 0 | 0 = 0 op2_sig = 4'h0; #1 `CHECK(4'h0); op1_sig = 4'h3; // 3 | C = F op2_sig = 4'hC; #1 `CHECK(4'hF); op1_sig = 4'h6; // 6 | 3 = 7 op2_sig = 4'h3; #1 `CHECK(4'h7); op1_sig = 4'hF; // F | F = F op2_sig = 4'hF; #1 `CHECK(4'hF); #1 $display("End of test"); end //-------------------------------------------------------------- // Instantiate 4 ALU slice units, daisy-chained; MSB is slice A // // slice_A slice_B slice_C slice_D // cy_out <= [3] [2] [1] [0] <= cy_in //-------------------------------------------------------------- alu_slice slice_A ( .op1(op1_sig[3]) , // input op1_sig .op2(op2_sig[3]) , // input op2_sig .cy_in(cy_out_B_sig) , // input cy_in_sig .R(R_sig) , // input R_sig .S(S_sig) , // input S_sig .V(V_sig) , // input V_sig .cy_out(cy_out_sig) , // output cy_out_sig .result(result_sig[3]) // output result_sig ); alu_slice slice_B ( .op1(op1_sig[2]) , // input op1_sig .op2(op2_sig[2]) , // input op2_sig .cy_in(cy_out_C_sig) , // input cy_in_sig .R(R_sig) , // input R_sig .S(S_sig) , // input S_sig .V(V_sig) , // input V_sig .cy_out(cy_out_B_sig) , // output cy_out_sig .result(result_sig[2]) // output result_sig ); alu_slice slice_C ( .op1(op1_sig[1]) , // input op1_sig .op2(op2_sig[1]) , // input op2_sig .cy_in(cy_out_D_sig) , // input cy_in_sig .R(R_sig) , // input R_sig .S(S_sig) , // input S_sig .V(V_sig) , // input V_sig .cy_out(cy_out_C_sig) , // output cy_out_sig .result(result_sig[1]) // output result_sig ); alu_slice slice_D ( .op1(op1_sig[0]) , // input op1_sig .op2(op2_sig[0]) , // input op2_sig .cy_in(cy_in_sig) , // input cy_in_sig .R(R_sig) , // input R_sig .S(S_sig) , // input S_sig .V(V_sig) , // input V_sig .cy_out(cy_out_D_sig) , // output cy_out_sig .result(result_sig[0]) // output result_sig ); endmodule ================================================ FILE: cpu/bus/address_latch.bdf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. 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work around the latch => flop translation" (rect 440 472 737 486)(font "Arial" (font_size 8))) (title_block (rect 24 472 281 524) (name "title-custom-small") (section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "May 17, 2014, 2016" (rect 56 3 168 17)(font "Arial" (font_size 8)))(border)) (section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border)) (section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "address_latch" (rect 43 2 139 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.5" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border)) (drawing ) ) ================================================ FILE: cpu/bus/address_latch.bsf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "symbol" (version "1.2")) (symbol (rect 16 16 240 240) (text "address_latch" (rect 5 0 86 14)(font "Arial" (font_size 8))) (text "inst" (rect 8 208 25 220)(font "Arial" )) (port (pt 0 32) (input) (text "clrpc" (rect 0 0 28 14)(font "Arial" (font_size 8))) (text "clrpc" (rect 21 27 49 41)(font "Arial" (font_size 8))) (line (pt 0 32)(pt 16 32)) ) (port (pt 0 48) (input) (text "ctl_bus_inc_oe" (rect 0 0 86 14)(font "Arial" (font_size 8))) (text "ctl_bus_inc_oe" (rect 21 43 107 57)(font "Arial" (font_size 8))) (line (pt 0 48)(pt 16 48)) ) (port (pt 0 64) (input) (text "ctl_inc_limit6" (rect 0 0 70 14)(font "Arial" (font_size 8))) (text "ctl_inc_limit6" (rect 21 59 91 73)(font "Arial" (font_size 8))) (line (pt 0 64)(pt 16 64)) ) (port (pt 0 80) (input) (text "ctl_inc_dec" (rect 0 0 64 14)(font "Arial" (font_size 8))) (text "ctl_inc_dec" (rect 21 75 85 89)(font "Arial" (font_size 8))) (line (pt 0 80)(pt 16 80)) ) (port (pt 0 96) (input) (text "ctl_inc_cy" (rect 0 0 57 14)(font "Arial" (font_size 8))) (text "ctl_inc_cy" (rect 21 91 78 105)(font "Arial" (font_size 8))) (line (pt 0 96)(pt 16 96)) ) (port (pt 0 112) (input) (text "clk" (rect 0 0 15 14)(font "Arial" (font_size 8))) (text "clk" (rect 21 107 36 121)(font "Arial" (font_size 8))) (line (pt 0 112)(pt 16 112)) ) (port (pt 0 128) (input) (text "ctl_al_we" (rect 0 0 55 14)(font "Arial" (font_size 8))) (text "ctl_al_we" (rect 21 123 76 137)(font "Arial" (font_size 8))) (line (pt 0 128)(pt 16 128)) ) (port (pt 0 144) (input) (text "nreset" (rect 0 0 36 14)(font "Arial" (font_size 8))) (text "nreset" (rect 21 139 57 153)(font "Arial" (font_size 8))) (line (pt 0 144)(pt 16 144)) ) (port (pt 0 160) (input) (text "ctl_apin_mux2" (rect 0 0 81 14)(font "Arial" (font_size 8))) (text "ctl_apin_mux2" (rect 21 155 102 169)(font "Arial" (font_size 8))) (line (pt 0 160)(pt 16 160)) ) (port (pt 0 176) (input) (text "ctl_apin_mux" (rect 0 0 74 14)(font "Arial" (font_size 8))) (text "ctl_apin_mux" (rect 21 171 95 185)(font "Arial" (font_size 8))) (line (pt 0 176)(pt 16 176)) ) (port (pt 224 48) (output) (text "address_is_1" (rect 0 0 77 14)(font "Arial" (font_size 8))) (text "address_is_1" (rect 126 43 203 57)(font "Arial" (font_size 8))) (line (pt 224 48)(pt 208 48)) ) (port (pt 224 64) (output) (text "address[15..0]" (rect 0 0 82 14)(font "Arial" (font_size 8))) (text "address[15..0]" (rect 121 59 203 73)(font "Arial" (font_size 8))) (line (pt 224 64)(pt 208 64)(line_width 3)) ) (port (pt 224 32) (bidir) (text "abus[15..0]" (rect 0 0 63 14)(font "Arial" (font_size 8))) (text "abus[15..0]" (rect 140 27 203 41)(font "Arial" (font_size 8))) (line (pt 224 32)(pt 208 32)(line_width 3)) ) (drawing (rectangle (rect 16 16 208 208)) ) ) ================================================ FILE: cpu/bus/address_latch.v ================================================ // Copyright (C) 1991-2013 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // PROGRAM "Quartus II 64-Bit" // VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" // CREATED "Sat Feb 27 08:13:14 2016" module address_latch( ctl_inc_cy, ctl_inc_dec, ctl_al_we, ctl_inc_limit6, ctl_bus_inc_oe, clk, ctl_apin_mux, ctl_apin_mux2, clrpc, nreset, address_is_1, abus, address ); input wire ctl_inc_cy; input wire ctl_inc_dec; input wire ctl_al_we; input wire ctl_inc_limit6; input wire ctl_bus_inc_oe; input wire clk; input wire ctl_apin_mux; input wire ctl_apin_mux2; input wire clrpc; input wire nreset; output wire address_is_1; inout wire [15:0] abus; output wire [15:0] address; wire [15:0] abusz; reg [15:0] Q; wire SYNTHESIZED_WIRE_0; wire SYNTHESIZED_WIRE_1; wire SYNTHESIZED_WIRE_2; wire [15:0] SYNTHESIZED_WIRE_7; wire SYNTHESIZED_WIRE_4; wire [15:0] SYNTHESIZED_WIRE_5; always@(posedge clk or negedge nreset) begin if (!nreset) begin Q[15:0] <= 16'b0000000000000000; end else if (ctl_al_we) begin Q[15:0] <= abusz[15:0]; end end assign address_is_1 = ~(SYNTHESIZED_WIRE_0 | SYNTHESIZED_WIRE_1); assign abusz = {SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_2} & abus; assign abus[15] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[15] : 1'bz; assign abus[14] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[14] : 1'bz; assign abus[13] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[13] : 1'bz; assign abus[12] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[12] : 1'bz; assign abus[11] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[11] : 1'bz; assign abus[10] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[10] : 1'bz; assign abus[9] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[9] : 1'bz; assign abus[8] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[8] : 1'bz; assign abus[7] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[7] : 1'bz; assign abus[6] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[6] : 1'bz; assign abus[5] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[5] : 1'bz; assign abus[4] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[4] : 1'bz; assign abus[3] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[3] : 1'bz; assign abus[2] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[2] : 1'bz; assign abus[1] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[1] : 1'bz; assign abus[0] = ctl_bus_inc_oe ? SYNTHESIZED_WIRE_7[0] : 1'bz; assign SYNTHESIZED_WIRE_0 = Q[7] | Q[5] | Q[6] | Q[4] | Q[2] | Q[3] | Q[1] | SYNTHESIZED_WIRE_4; assign SYNTHESIZED_WIRE_1 = Q[15] | Q[13] | Q[14] | Q[12] | Q[10] | Q[11] | Q[9] | Q[8]; address_mux b2v_inst7( .select(ctl_apin_mux2), .in0(SYNTHESIZED_WIRE_5), .in1(Q), .out(address)); assign SYNTHESIZED_WIRE_2 = ~clrpc; inc_dec b2v_inst_inc_dec( .limit6(ctl_inc_limit6), .decrement(ctl_inc_dec), .carry_in(ctl_inc_cy), .d(Q), .address(SYNTHESIZED_WIRE_7)); address_mux b2v_mux( .select(ctl_apin_mux), .in0(abusz), .in1(SYNTHESIZED_WIRE_7), .out(SYNTHESIZED_WIRE_5)); assign SYNTHESIZED_WIRE_4 = ~Q[0]; endmodule ================================================ FILE: cpu/bus/address_mux.bdf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "graphic" (version "1.4")) (pin (input) (rect 32 168 208 184) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "select" (rect 9 0 38 12)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) (line (pt 121 8)(pt 176 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) ) (pin (input) (rect 32 48 208 64) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "in1[15..0]" (rect 9 0 55 12)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) (line (pt 121 8)(pt 176 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) ) (pin (input) (rect 32 112 208 128) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "in0[15..0]" (rect 9 0 55 12)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) (line (pt 121 8)(pt 176 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) ) (pin (output) (rect 528 88 704 104) (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) (text "out[15..0]" (rect 90 0 137 12)(font "Arial" )) (pt 0 8) (drawing (line (pt 0 8)(pt 52 8)) (line (pt 52 4)(pt 78 4)) (line (pt 52 12)(pt 78 12)) (line (pt 52 12)(pt 52 4)) (line (pt 78 4)(pt 82 8)) (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) ) (symbol (rect 336 40 400 88) (text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6))) (text "sel1" (rect 3 37 23 49)(font "Arial" )) (port (pt 0 16) (input) (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible)) (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible)) (line (pt 0 16)(pt 14 16)) ) (port (pt 0 32) (input) (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible)) (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible)) (line (pt 0 32)(pt 14 32)) ) (port (pt 64 24) (output) (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible)) (text "OUT" (rect 48 15 62 27)(font "Courier New" (bold))(invisible)) (line (pt 42 24)(pt 64 24)) ) (drawing (line (pt 14 12)(pt 30 12)) (line (pt 14 37)(pt 31 37)) (line (pt 14 12)(pt 14 37)) (arc (pt 31 37)(pt 30 12)(rect 18 12 43 37)) ) ) (symbol (rect 336 104 400 152) (text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6))) (text "sel0" (rect 3 37 23 49)(font "Arial" )) (port (pt 0 16) (input) (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible)) (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible)) (line (pt 0 16)(pt 14 16)) ) (port (pt 0 32) (input) (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible)) (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible)) (line (pt 0 32)(pt 14 32)) ) (port (pt 64 24) (output) (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible)) (text "OUT" (rect 48 15 62 27)(font "Courier New" (bold))(invisible)) (line (pt 42 24)(pt 64 24)) ) (drawing (line (pt 14 12)(pt 30 12)) (line (pt 14 37)(pt 31 37)) (line (pt 14 12)(pt 14 37)) (arc (pt 31 37)(pt 30 12)(rect 18 12 43 37)) ) ) (symbol (rect 432 72 496 120) (text "OR2" (rect 1 0 19 10)(font "Arial" (font_size 6))) (text "sel_or" (rect 3 37 32 49)(font "Arial" )) (port (pt 0 32) (input) (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible)) (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible)) (line (pt 0 32)(pt 15 32)) ) (port (pt 0 16) (input) (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible)) (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible)) (line (pt 0 16)(pt 15 16)) ) (port (pt 64 24) (output) (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible)) (text "OUT" (rect 48 15 62 27)(font "Courier New" (bold))(invisible)) (line (pt 48 24)(pt 64 24)) ) (drawing (line (pt 14 36)(pt 25 36)) (line (pt 14 13)(pt 25 13)) (arc (pt 7 29)(pt 7 19)(rect -14 8 19 41)) (arc (pt 49 24)(pt 25 13)(rect -6 13 57 76)) (arc (pt 25 35)(pt 49 24)(rect -6 -27 57 36)) ) ) (symbol (rect 256 160 304 192) (text "NOT" (rect 1 0 21 10)(font "Arial" (font_size 6))) (text "sel_not" (rect 3 21 38 33)(font "Arial" )) (port (pt 0 16) (input) (text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible)) (text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible)) (line (pt 0 16)(pt 13 16)) ) (port (pt 48 16) (output) (text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible)) (text "OUT" (rect 32 7 46 19)(font "Courier New" (bold))(invisible)) (line (pt 39 16)(pt 48 16)) ) (drawing (line (pt 13 25)(pt 13 7)) (line (pt 13 7)(pt 31 16)) (line (pt 13 25)(pt 31 16)) (circle (rect 31 12 39 20)) ) ) (connector (pt 304 176) (pt 320 176) ) (connector (pt 320 176) (pt 320 136) ) (connector (pt 320 136) (pt 336 136) ) (connector (pt 336 72) (pt 240 72) ) (connector (pt 240 176) (pt 240 72) ) (connector (pt 208 176) (pt 240 176) ) (connector (pt 240 176) (pt 256 176) ) (connector (pt 208 56) (pt 336 56) (bus) ) (connector (pt 208 120) (pt 336 120) (bus) ) (connector (pt 496 96) (pt 528 96) (bus) ) (connector (pt 400 64) (pt 416 64) (bus) ) (connector (pt 416 64) (pt 416 88) (bus) ) (connector (pt 400 128) (pt 416 128) (bus) ) (connector (pt 416 128) (pt 416 104) (bus) ) (connector (pt 416 104) (pt 432 104) (bus) ) (connector (pt 416 88) (pt 432 88) (bus) ) (junction (pt 240 176)) (title_block (rect 32 240 289 292) (name "title-custom-small") (section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "address_mux" (rect 43 2 136 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border)) (section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "November 8, 2014" (rect 56 3 159 17)(font "Arial" (font_size 8)))(border)) (section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.0" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border)) (drawing ) ) ================================================ FILE: cpu/bus/address_mux.bsf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "symbol" (version "1.2")) (symbol (rect 64 64 152 208) (text "address_mux" (rect 5 0 82 14)(font "Arial" (font_size 8))) (text "inst" (rect 0 128 17 140)(font "Arial" )) (port (pt 0 32) (input) (text "in1[15..0]" (rect 0 0 51 14)(font "Arial" (font_size 8))) (text "in1[15..0]" (rect 21 27 72 41)(font "Arial" (font_size 8))) (line (pt 0 32)(pt 16 32)(line_width 3)) ) (port (pt 0 72) (input) (text "in0[15..0]" (rect 0 0 51 14)(font "Arial" (font_size 8))) (text "in0[15..0]" (rect 21 67 72 81)(font "Arial" (font_size 8))) (line (pt 0 72)(pt 16 72)(line_width 3)) ) (port (pt 0 120) (input) (text "select" (rect 0 0 34 14)(font "Arial" (font_size 8))) (text "select" (rect 5 99 39 113)(font "Arial" (font_size 8))) (line (pt 0 120)(pt 16 120)) ) (port (pt 88 56) (output) (text "out[15..0]" (rect -72 0 -19 14)(font "Arial" (font_size 8))) (text "out[15..0]" (rect 24 48 77 62)(font "Arial" (font_size 8))) (line (pt 88 56)(pt 72 56)(line_width 3)) ) (drawing (line (pt 8 16)(pt 80 40)) (line (pt 8 120)(pt 48 120)) (line (pt 80 40)(pt 80 72)) (line (pt 8 16)(pt 8 96)) (line (pt 80 72)(pt 8 96)) (line (pt 48 120)(pt 48 80)) ) ) ================================================ FILE: cpu/bus/address_mux.v ================================================ // Copyright (C) 1991-2013 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // PROGRAM "Quartus II 64-Bit" // VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" // CREATED "Sat Nov 08 09:37:58 2014" module address_mux( select, in0, in1, out ); input wire select; input wire [15:0] in0; input wire [15:0] in1; output wire [15:0] out; wire SYNTHESIZED_WIRE_0; wire [15:0] SYNTHESIZED_WIRE_1; wire [15:0] SYNTHESIZED_WIRE_2; assign SYNTHESIZED_WIRE_1 = in0 & {SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_0}; assign SYNTHESIZED_WIRE_2 = in1 & {select,select,select,select,select,select,select,select,select,select,select,select,select,select,select,select}; assign SYNTHESIZED_WIRE_0 = ~select; assign out = SYNTHESIZED_WIRE_1 | SYNTHESIZED_WIRE_2; endmodule ================================================ FILE: cpu/bus/address_pins.bdf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "graphic" (version "1.4")) (pin (input) (rect 40 80 216 96) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "address[15..0]" (rect 9 0 79 12)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) (line (pt 121 8)(pt 176 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) ) (pin (input) (rect 40 96 216 112) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "clk" (rect 9 0 23 12)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) (line (pt 121 8)(pt 176 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) ) (pin (input) (rect 40 112 216 128) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "bus_ab_pin_we" (rect 9 0 83 12)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) (line (pt 121 8)(pt 176 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) ) (pin (input) (rect 40 32 216 48) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "pin_control_oe" (rect 9 0 79 12)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) (line (pt 121 8)(pt 176 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) ) (pin (output) (rect 568 80 744 96) (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) (text "abus[15..0]" (rect 90 0 145 12)(font "Arial" )) (pt 0 8) (drawing (line (pt 0 8)(pt 52 8)) (line (pt 52 4)(pt 78 4)) (line (pt 52 12)(pt 78 12)) (line (pt 52 12)(pt 52 4)) (line (pt 78 4)(pt 82 8)) (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) ) (symbol (rect 480 72 528 104) (text "TRI" (rect 1 0 16 10)(font "Arial" (font_size 6))) (text "inst" (rect 3 21 20 33)(font "Arial" )) (port (pt 0 16) (input) (text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible)) (text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible)) (line (pt 0 16)(pt 14 16)) ) (port (pt 24 0) (input) (text "OE" (rect 26 0 37 12)(font "Courier New" (bold))(invisible)) (text "OE" (rect 26 0 37 12)(font "Courier New" (bold))(invisible)) (line (pt 24 12)(pt 24 0)) ) (port (pt 48 16) (output) (text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible)) (text "OUT" (rect 32 7 46 19)(font "Courier New" (bold))(invisible)) (line (pt 32 16)(pt 48 16)) ) (drawing (line (pt 14 25)(pt 14 7)) (line (pt 14 25)(pt 32 16)) (line (pt 14 7)(pt 32 16)) ) ) (symbol (rect 312 64 376 144) (text "DFFE" (rect 1 0 25 10)(font "Arial" (font_size 6))) (text "apin_latch" (rect 3 68 52 80)(font "Arial" )) (port (pt 32 0) (input) (text "PRN" (rect 24 13 41 25)(font "Courier New" (bold))) (text "PRN" (rect 24 11 41 23)(font "Courier New" (bold))) (line (pt 32 4)(pt 32 0)) ) (port (pt 32 80) (input) (text "CLRN" (rect 21 59 44 71)(font "Courier New" (bold))) (text "CLRN" (rect 21 58 44 70)(font "Courier New" (bold))) (line (pt 32 80)(pt 32 76)) ) (port (pt 0 24) (input) (text "D" (rect 14 20 19 32)(font "Courier New" (bold))) (text "D" (rect 14 20 19 32)(font "Courier New" (bold))) (line (pt 0 24)(pt 12 24)) ) (port (pt 0 40) (input) (text "CLK" (rect 2 28 19 40)(font "Courier New" (bold))(invisible)) (text "CLK" (rect 2 28 19 40)(font "Courier New" (bold))(invisible)) (line (pt 0 40)(pt 12 40)) ) (port (pt 0 56) (input) (text "ENA" (rect 14 50 31 62)(font "Courier New" (bold))) (text "ENA" (rect 14 50 31 62)(font "Courier New" (bold))) (line (pt 0 56)(pt 12 56)) ) (port (pt 64 24) (output) (text "Q" (rect 44 20 49 32)(font "Courier New" (bold))) (text "Q" (rect 44 20 48 32)(font "Courier New" (bold))) (line (pt 53 24)(pt 64 24)) ) (drawing (line (pt 12 68)(pt 52 68)) (line (pt 12 12)(pt 52 12)) (line (pt 52 68)(pt 52 12)) (line (pt 12 68)(pt 12 12)) (line (pt 12 34)(pt 19 41)) (line (pt 18 41)(pt 12 47)) (circle (rect 28 4 36 12)) (circle (rect 28 68 36 76)) ) ) (symbol (rect 240 88 288 120) (text "NOT" (rect 1 0 21 10)(font "Arial" (font_size 6))) (text "nclk" (rect 3 21 23 33)(font "Arial" )) (port (pt 0 16) (input) (text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible)) (text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible)) (line (pt 0 16)(pt 13 16)) ) (port (pt 48 16) (output) (text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible)) (text "OUT" (rect 32 7 46 19)(font "Courier New" (bold))(invisible)) (line (pt 39 16)(pt 48 16)) ) (drawing (line (pt 13 25)(pt 13 7)) (line (pt 13 7)(pt 31 16)) (line (pt 13 25)(pt 31 16)) (circle (rect 31 12 39 20)) ) ) (connector (pt 216 88) (pt 312 88) (bus) ) (connector (pt 216 120) (pt 312 120) ) (connector (pt 504 40) (pt 504 72) ) (connector (pt 216 40) (pt 504 40) ) (connector (pt 376 88) (pt 480 88) (bus) ) (connector (pt 528 88) (pt 568 88) (bus) ) (connector (pt 216 104) (pt 240 104) ) (connector (pt 288 104) (pt 312 104) ) (text "Repeated 16 times, once for each address pin." (rect 472 144 738 158)(font "Arial" (font_size 8))) (title_block (rect 40 184 297 236) (name "title-custom-small") (section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "address_pins" (rect 43 2 135 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border)) (section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "June 14, 2014" (rect 56 3 136 17)(font "Arial" (font_size 8)))(border)) (section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.3" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border)) (drawing ) ) ================================================ FILE: cpu/bus/address_pins.bsf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "symbol" (version "1.2")) (symbol (rect 16 16 224 144) (text "address_pins" (rect 5 0 82 14)(font "Arial" (font_size 8))) (text "inst" (rect 8 112 25 124)(font "Arial" )) (port (pt 0 32) (input) (text "pin_control_oe" (rect 0 0 83 14)(font "Arial" (font_size 8))) (text "pin_control_oe" (rect 21 27 104 41)(font "Arial" (font_size 8))) (line (pt 0 32)(pt 16 32)) ) (port (pt 0 48) (input) (text "address[15..0]" (rect 0 0 82 14)(font "Arial" (font_size 8))) (text "address[15..0]" (rect 21 43 103 57)(font "Arial" (font_size 8))) (line (pt 0 48)(pt 16 48)(line_width 3)) ) (port (pt 0 64) (input) (text "clk" (rect 0 0 15 14)(font "Arial" (font_size 8))) (text "clk" (rect 21 59 36 73)(font "Arial" (font_size 8))) (line (pt 0 64)(pt 16 64)) ) (port (pt 0 80) (input) (text "bus_ab_pin_we" (rect 0 0 92 14)(font "Arial" (font_size 8))) (text "bus_ab_pin_we" (rect 21 75 113 89)(font "Arial" (font_size 8))) (line (pt 0 80)(pt 16 80)) ) (port (pt 208 32) (output) (text "abus[15..0]" (rect 0 0 63 14)(font "Arial" (font_size 8))) (text "abus[15..0]" (rect 124 27 187 41)(font "Arial" (font_size 8))) (line (pt 208 32)(pt 192 32)(line_width 3)) ) (drawing (rectangle (rect 16 16 192 112)) ) ) ================================================ FILE: cpu/bus/address_pins.v ================================================ // Copyright (C) 1991-2013 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // PROGRAM "Quartus II 64-Bit" // VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" // CREATED "Sun Nov 16 16:56:05 2014" module address_pins( clk, bus_ab_pin_we, pin_control_oe, address, abus ); input wire clk; input wire bus_ab_pin_we; input wire pin_control_oe; input wire [15:0] address; output wire [15:0] abus; wire SYNTHESIZED_WIRE_0; reg [15:0] DFFE_apin_latch; always@(posedge SYNTHESIZED_WIRE_0) begin if (bus_ab_pin_we) begin DFFE_apin_latch[15:0] <= address[15:0]; end end assign abus[15] = pin_control_oe ? DFFE_apin_latch[15] : 1'bz; assign abus[14] = pin_control_oe ? DFFE_apin_latch[14] : 1'bz; assign abus[13] = pin_control_oe ? DFFE_apin_latch[13] : 1'bz; assign abus[12] = pin_control_oe ? DFFE_apin_latch[12] : 1'bz; assign abus[11] = pin_control_oe ? DFFE_apin_latch[11] : 1'bz; assign abus[10] = pin_control_oe ? DFFE_apin_latch[10] : 1'bz; assign abus[9] = pin_control_oe ? DFFE_apin_latch[9] : 1'bz; assign abus[8] = pin_control_oe ? DFFE_apin_latch[8] : 1'bz; assign abus[7] = pin_control_oe ? DFFE_apin_latch[7] : 1'bz; assign abus[6] = pin_control_oe ? DFFE_apin_latch[6] : 1'bz; assign abus[5] = pin_control_oe ? DFFE_apin_latch[5] : 1'bz; assign abus[4] = pin_control_oe ? DFFE_apin_latch[4] : 1'bz; assign abus[3] = pin_control_oe ? DFFE_apin_latch[3] : 1'bz; assign abus[2] = pin_control_oe ? DFFE_apin_latch[2] : 1'bz; assign abus[1] = pin_control_oe ? DFFE_apin_latch[1] : 1'bz; assign abus[0] = pin_control_oe ? DFFE_apin_latch[0] : 1'bz; assign SYNTHESIZED_WIRE_0 = ~clk; endmodule ================================================ FILE: cpu/bus/bus_control.bdf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "graphic" (version "1.4")) (pin (input) (rect 32 64 208 80) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "ctl_bus_ff_oe" (rect 9 0 77 12)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) (line (pt 121 8)(pt 176 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) ) (pin (input) (rect 32 48 208 64) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "ctl_bus_zero_oe" (rect 9 0 88 12)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) (line (pt 121 8)(pt 176 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) ) (pin (bidir) (rect 600 136 776 152) (text "BIDIR" (rect 1 0 25 10)(font "Arial" (font_size 6))) (text "db[7..0]" (rect 90 0 127 12)(font "Arial" )) (pt 0 8) (drawing (line (pt 56 4)(pt 78 4)) (line (pt 0 8)(pt 52 8)) (line (pt 56 12)(pt 78 12)) (line (pt 78 4)(pt 82 8)) (line (pt 78 12)(pt 82 8)) (line (pt 56 4)(pt 52 8)) (line (pt 52 8)(pt 56 12)) ) (text "VCC" (rect 4 7 24 17)(font "Arial" (font_size 6))) ) (symbol (rect 512 128 560 160) (text "TRI" (rect 1 0 16 10)(font "Arial" (font_size 6))) (text "inst" (rect 3 21 20 33)(font "Arial" )) (port (pt 0 16) (input) (text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible)) (text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible)) (line (pt 0 16)(pt 14 16)) ) (port (pt 24 0) (input) (text "OE" (rect 26 0 37 12)(font "Courier New" (bold))(invisible)) (text "OE" (rect 26 0 37 12)(font "Courier New" (bold))(invisible)) (line (pt 24 12)(pt 24 0)) ) (port (pt 48 16) (output) (text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible)) (text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible)) (line (pt 32 16)(pt 48 16)) ) (drawing (line (pt 14 25)(pt 14 7)) (line (pt 14 25)(pt 32 16)) (line (pt 14 7)(pt 32 16)) ) ) (symbol (rect 304 120 368 168) (text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6))) (text "inst2" (rect 3 37 26 49)(font "Arial" )) (port (pt 0 16) (input) (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible)) (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible)) (line (pt 0 16)(pt 14 16)) ) (port (pt 0 32) (input) (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible)) (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible)) (line (pt 0 32)(pt 14 32)) ) (port (pt 64 24) (output) (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible)) (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible)) (line (pt 42 24)(pt 64 24)) ) (drawing (line (pt 14 12)(pt 30 12)) (line (pt 14 37)(pt 31 37)) (line (pt 14 12)(pt 14 37)) (arc (pt 31 37)(pt 30 12)(rect 18 12 43 37)) ) ) (symbol (rect 144 120 176 136) (text "VCC" (rect 7 0 27 10)(font "Arial" (font_size 6))) (text "inst1" (rect 3 5 26 17)(font "Arial" )(invisible)) (port (pt 16 16) (output) (text "1" (rect 19 7 24 19)(font "Courier New" (bold))(invisible)) (text "1" (rect 19 7 24 19)(font "Courier New" (bold))(invisible)) (line (pt 16 16)(pt 16 8)) ) (drawing (line (pt 8 8)(pt 24 8)) ) ) (symbol (rect 304 40 368 88) (text "OR2" (rect 1 0 19 10)(font "Arial" (font_size 6))) (text "inst6" (rect 3 37 26 49)(font "Arial" )) (port (pt 0 32) (input) (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible)) (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible)) (line (pt 0 32)(pt 15 32)) ) (port (pt 0 16) (input) (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible)) (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible)) (line (pt 0 16)(pt 15 16)) ) (port (pt 64 24) (output) (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible)) (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible)) (line (pt 48 24)(pt 64 24)) ) (drawing (line (pt 14 36)(pt 25 36)) (line (pt 14 13)(pt 25 13)) (arc (pt 7 29)(pt 7 19)(rect -14 8 19 41)) (arc (pt 49 24)(pt 25 13)(rect -6 13 57 76)) (arc (pt 25 35)(pt 49 24)(rect -6 -27 57 36)) ) ) (connector (pt 600 144) (pt 560 144) (bus) ) (connector (pt 208 56) (pt 304 56) ) (connector (pt 304 136) (pt 232 136) ) (connector (pt 232 72) (pt 232 136) ) (connector (text "bus[7..0]" (rect 387 128 430 140)(font "Arial" )) (pt 368 144) (pt 512 144) (bus) ) (connector (text "vcc[7..0]" (rect 190 136 234 148)(font "Arial" )) (pt 304 152) (pt 160 152) (bus) ) (connector (pt 368 64) (pt 536 64) ) (connector (pt 160 136) (pt 160 152) (bus) ) (connector (pt 208 72) (pt 232 72) ) (connector (pt 232 72) (pt 304 72) ) (connector (pt 536 64) (pt 536 128) ) (junction (pt 232 72)) (title_block (rect 32 208 289 260) (name "title-custom-small") (section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "August 17, 2014, 2016" (rect 56 3 185 17)(font "Arial" (font_size 8)))(border)) (section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border)) (section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "bus_control" (rect 43 2 123 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.3" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border)) (drawing ) ) ================================================ FILE: cpu/bus/bus_control.bsf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "symbol" (version "1.2")) (symbol (rect 16 16 208 112) (text "bus_control" (rect 5 0 72 14)(font "Arial" (font_size 8))) (text "inst" (rect 8 80 25 92)(font "Arial" )) (port (pt 0 32) (input) (text "ctl_bus_zero_oe" (rect 0 0 95 14)(font "Arial" (font_size 8))) (text "ctl_bus_zero_oe" (rect 21 27 116 41)(font "Arial" (font_size 8))) (line (pt 0 32)(pt 16 32)) ) (port (pt 0 48) (input) (text "ctl_bus_ff_oe" (rect 0 0 79 14)(font "Arial" (font_size 8))) (text "ctl_bus_ff_oe" (rect 21 43 100 57)(font "Arial" (font_size 8))) (line (pt 0 48)(pt 16 48)) ) (port (pt 192 32) (bidir) (text "db[7..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) (text "db[7..0]" (rect 129 27 171 41)(font "Arial" (font_size 8))) (line (pt 192 32)(pt 176 32)(line_width 3)) ) (drawing (rectangle (rect 16 16 176 80)) ) ) ================================================ FILE: cpu/bus/bus_control.v ================================================ // Copyright (C) 1991-2013 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // PROGRAM "Quartus II 64-Bit" // VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" // CREATED "Fri Feb 26 22:25:37 2016" module bus_control( ctl_bus_ff_oe, ctl_bus_zero_oe, db ); input wire ctl_bus_ff_oe; input wire ctl_bus_zero_oe; inout wire [7:0] db; wire [7:0] bus; wire [7:0] vcc; wire SYNTHESIZED_WIRE_0; assign db[7] = SYNTHESIZED_WIRE_0 ? bus[7] : 1'bz; assign db[6] = SYNTHESIZED_WIRE_0 ? bus[6] : 1'bz; assign db[5] = SYNTHESIZED_WIRE_0 ? bus[5] : 1'bz; assign db[4] = SYNTHESIZED_WIRE_0 ? bus[4] : 1'bz; assign db[3] = SYNTHESIZED_WIRE_0 ? bus[3] : 1'bz; assign db[2] = SYNTHESIZED_WIRE_0 ? bus[2] : 1'bz; assign db[1] = SYNTHESIZED_WIRE_0 ? bus[1] : 1'bz; assign db[0] = SYNTHESIZED_WIRE_0 ? bus[0] : 1'bz; assign bus = {ctl_bus_ff_oe,ctl_bus_ff_oe,ctl_bus_ff_oe,ctl_bus_ff_oe,ctl_bus_ff_oe,ctl_bus_ff_oe,ctl_bus_ff_oe,ctl_bus_ff_oe} & vcc; assign SYNTHESIZED_WIRE_0 = ctl_bus_ff_oe | ctl_bus_zero_oe; assign vcc = 8'b11111111; endmodule ================================================ FILE: cpu/bus/bus_switch.bsf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "symbol" (version "1.1")) (symbol (rect 16 16 288 160) (text "bus_switch" (rect 5 0 48 12)(font "Arial" )) (text "inst" (rect 8 128 20 140)(font "Arial" )) (port (pt 0 32) (input) (text "ctl_sw_1u" (rect 0 0 38 12)(font "Arial" )) (text "ctl_sw_1u" (rect 21 27 59 39)(font "Arial" )) (line (pt 0 32)(pt 16 32)(line_width 1)) ) (port (pt 0 48) (input) (text "ctl_sw_1d" (rect 0 0 38 12)(font "Arial" )) (text "ctl_sw_1d" (rect 21 43 59 55)(font "Arial" )) (line (pt 0 48)(pt 16 48)(line_width 1)) ) (port (pt 0 64) (input) (text "ctl_sw_2u" (rect 0 0 40 12)(font "Arial" )) (text "ctl_sw_2u" (rect 21 59 61 71)(font "Arial" )) (line (pt 0 64)(pt 16 64)(line_width 1)) ) (port (pt 0 80) (input) (text "ctl_sw_2d" (rect 0 0 40 12)(font "Arial" )) (text "ctl_sw_2d" (rect 21 75 61 87)(font "Arial" )) (line (pt 0 80)(pt 16 80)(line_width 1)) ) (port (pt 0 96) (input) (text "ctl_sw_mask543_en" (rect 0 0 83 12)(font "Arial" )) (text "ctl_sw_mask543_en" (rect 21 91 104 103)(font "Arial" )) (line (pt 0 96)(pt 16 96)(line_width 1)) ) (port (pt 272 32) (output) (text "bus_sw_1u" (rect 0 0 44 12)(font "Arial" )) (text "bus_sw_1u" (rect 207 27 251 39)(font "Arial" )) (line (pt 272 32)(pt 256 32)(line_width 1)) ) (port (pt 272 48) (output) (text "bus_sw_1d" (rect 0 0 44 12)(font "Arial" )) (text "bus_sw_1d" (rect 207 43 251 55)(font "Arial" )) (line (pt 272 48)(pt 256 48)(line_width 1)) ) (port (pt 272 64) (output) (text "bus_sw_2u" (rect 0 0 46 12)(font "Arial" )) (text "bus_sw_2u" (rect 205 59 251 71)(font "Arial" )) (line (pt 272 64)(pt 256 64)(line_width 1)) ) (port (pt 272 80) (output) (text "bus_sw_2d" (rect 0 0 46 12)(font "Arial" )) (text "bus_sw_2d" (rect 205 75 251 87)(font "Arial" )) (line (pt 272 80)(pt 256 80)(line_width 1)) ) (port (pt 272 96) (output) (text "bus_sw_mask543_en" (rect 0 0 89 12)(font "Arial" )) (text "bus_sw_mask543_en" (rect 162 91 251 103)(font "Arial" )) (line (pt 272 96)(pt 256 96)(line_width 1)) ) (drawing (rectangle (rect 16 16 256 128)(line_width 1)) ) ) ================================================ FILE: cpu/bus/bus_switch.v ================================================ //============================================================================ // Bus switch in bus A-Z80 CPU // // Copyright 2014, 2016 Goran Devic // // This module provides control data bus switch signals. The sole purpose of // having these wires defined in this module is to get all control signals // (which are processed by genglobals.py) to appear in the list of global // control signals ("globals.vh") for consistency. //============================================================================ module bus_switch ( input wire ctl_sw_1u, // Control input for the SW1 upstream input wire ctl_sw_1d, // Control input for the SW1 downstream input wire ctl_sw_2u, // Control input for the SW2 upstream input wire ctl_sw_2d, // Control input for the SW2 downstream input wire ctl_sw_mask543_en, // Enables masking [5:3] on the data bus switch 1 //-------------------------------------------------------------------- output wire bus_sw_1u, // SW1 upstream output wire bus_sw_1d, // SW1 downstream output wire bus_sw_2u, // SW2 upstream output wire bus_sw_2d, // SW2 downstream output wire bus_sw_mask543_en // Affects SW1 downstream ); assign bus_sw_1u = ctl_sw_1u; assign bus_sw_1d = ctl_sw_1d; assign bus_sw_2u = ctl_sw_2u; assign bus_sw_2d = ctl_sw_2d; assign bus_sw_mask543_en = ctl_sw_mask543_en; endmodule ================================================ FILE: cpu/bus/control_pins_n.bdf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "graphic" (version "1.4")) (pin (input) (rect 32 472 208 488) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "busack" (rect 9 0 44 12)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) (line (pt 121 8)(pt 176 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) ) (pin (input) (rect 456 512 632 528) (text "INPUT" (rect 15 0 43 10)(font "Arial" (font_size 6))) (text "CPUCLK" (rect 123 0 167 12)(font "Arial" )) (pt 0 8) (drawing (line (pt 84 12)(pt 59 12)) (line (pt 84 4)(pt 59 4)) (line (pt 55 8)(pt 0 8)) (line (pt 84 12)(pt 84 4)) (line (pt 59 4)(pt 55 8)) (line (pt 59 12)(pt 55 8)) ) (flipy) (text "VCC" (rect 20 7 40 17)(font "Arial" (font_size 6))) ) (pin (input) (rect 32 80 208 96) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text 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File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. 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14)(font "Arial" (font_size 8))) (text "clk" (rect 180 187 195 201)(font "Arial" (font_size 8))) (line (pt 216 192)(pt 200 192)) ) (port (pt 216 208) (output) (text "intr" (rect 0 0 17 14)(font "Arial" (font_size 8))) (text "intr" (rect 178 203 195 217)(font "Arial" (font_size 8))) (line (pt 216 208)(pt 200 208)) ) (port (pt 216 224) (output) (text "nmi" (rect 0 0 18 14)(font "Arial" (font_size 8))) (text "nmi" (rect 177 219 195 233)(font "Arial" (font_size 8))) (line (pt 216 224)(pt 200 224)) ) (port (pt 216 240) (output) (text "reset_in" (rect 0 0 46 14)(font "Arial" (font_size 8))) (text "reset_in" (rect 149 235 195 249)(font "Arial" (font_size 8))) (line (pt 216 240)(pt 200 240)) ) (drawing (rectangle (rect 16 16 200 272)) ) ) ================================================ FILE: cpu/bus/control_pins_n.v ================================================ // Copyright (C) 1991-2013 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // PROGRAM "Quartus II 64-Bit" // VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" // CREATED "Sun Nov 16 23:06:14 2014" module control_pins_n( busack, CPUCLK, pin_control_oe, in_halt, pin_nWAIT, pin_nBUSRQ, pin_nINT, pin_nNMI, pin_nRESET, nM1_out, nRFSH_out, nRD_out, nWR_out, nIORQ_out, nMREQ_out, nmi, busrq, clk, intr, mwait, reset_in, pin_nM1, pin_nMREQ, pin_nIORQ, pin_nRD, pin_nWR, pin_nRFSH, pin_nHALT, pin_nBUSACK ); input wire busack; input wire CPUCLK; input wire pin_control_oe; input wire in_halt; input wire pin_nWAIT; input wire pin_nBUSRQ; input wire pin_nINT; input wire pin_nNMI; input wire pin_nRESET; input wire nM1_out; input wire nRFSH_out; input wire nRD_out; input wire nWR_out; input wire nIORQ_out; input wire nMREQ_out; output wire nmi; output wire busrq; output wire clk; output wire intr; output wire mwait; output wire reset_in; output wire pin_nM1; output wire pin_nMREQ; output wire pin_nIORQ; output wire pin_nRD; output wire pin_nWR; output wire pin_nRFSH; output wire pin_nHALT; output wire pin_nBUSACK; assign clk = CPUCLK; assign pin_nM1 = nM1_out; assign pin_nRFSH = nRFSH_out; assign pin_nMREQ = pin_control_oe ? nMREQ_out : 1'bz; assign pin_nIORQ = pin_control_oe ? nIORQ_out : 1'bz; assign pin_nRD = pin_control_oe ? nRD_out : 1'bz; assign pin_nWR = pin_control_oe ? nWR_out : 1'bz; assign busrq = ~pin_nBUSRQ; assign pin_nHALT = ~in_halt; assign mwait = ~pin_nWAIT; assign pin_nBUSACK = ~busack; assign intr = ~pin_nINT; assign nmi = ~pin_nNMI; assign reset_in = ~pin_nRESET; endmodule ================================================ FILE: cpu/bus/data_pins.bdf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "graphic" (version "1.4")) (pin (input) (rect 24 32 200 48) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "bus_db_pin_oe" (rect 9 0 82 12)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) (line (pt 121 8)(pt 176 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) ) (pin (input) (rect 24 200 200 216) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "bus_db_pin_re" (rect 9 0 79 12)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) (line (pt 121 8)(pt 176 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) ) (pin (input) (rect 24 216 200 232) (text "INPUT" (rect 133 0 161 10)(font "Arial" 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(rect 648 280 885 294)(font "Arial" (font_size 8))) (title_block (rect 24 360 281 412) (name "title-custom-small") (section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "June 14, 2014, 2016" (rect 56 3 171 17)(font "Arial" (font_size 8)))(border)) (section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border)) (section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "data_pins" (rect 43 2 109 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.4" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border)) (drawing ) ) ================================================ FILE: cpu/bus/data_pins.bsf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "symbol" (version "1.2")) (symbol (rect 16 16 200 144) (text "data_pins" (rect 5 0 60 14)(font "Arial" (font_size 8))) (text "inst" (rect 8 112 25 124)(font "Arial" )) (port (pt 0 32) (input) (text "bus_db_pin_oe" (rect 0 0 87 14)(font "Arial" (font_size 8))) (text "bus_db_pin_oe" (rect 21 27 108 41)(font "Arial" (font_size 8))) (line (pt 0 32)(pt 16 32)) ) (port (pt 0 48) (input) (text "clk" (rect 0 0 15 14)(font "Arial" (font_size 8))) (text "clk" (rect 21 43 36 57)(font "Arial" (font_size 8))) (line (pt 0 48)(pt 16 48)) ) (port (pt 0 64) (input) (text "bus_db_pin_re" (rect 0 0 84 14)(font "Arial" (font_size 8))) (text "bus_db_pin_re" (rect 21 59 105 73)(font "Arial" (font_size 8))) (line (pt 0 64)(pt 16 64)) ) (port (pt 0 80) (input) (text "ctl_bus_db_we" (rect 0 0 88 14)(font "Arial" (font_size 8))) (text "ctl_bus_db_we" (rect 21 75 109 89)(font "Arial" (font_size 8))) (line (pt 0 80)(pt 16 80)) ) (port (pt 0 96) (input) (text "ctl_bus_db_oe" (rect 0 0 83 14)(font "Arial" (font_size 8))) (text "ctl_bus_db_oe" (rect 21 91 104 105)(font "Arial" (font_size 8))) (line (pt 0 96)(pt 16 96)) ) (port (pt 184 32) (bidir) (text "D[7..0]" (rect 0 0 36 14)(font "Arial" (font_size 8))) (text "D[7..0]" (rect 127 27 163 41)(font "Arial" (font_size 8))) (line (pt 184 32)(pt 168 32)(line_width 3)) ) (port (pt 184 48) (bidir) (text "db[7..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) (text "db[7..0]" (rect 121 43 163 57)(font "Arial" (font_size 8))) (line (pt 184 48)(pt 168 48)(line_width 3)) ) (drawing (rectangle (rect 16 16 168 112)) ) ) ================================================ FILE: cpu/bus/data_pins.v ================================================ // Copyright (C) 1991-2013 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // PROGRAM "Quartus II 64-Bit" // VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" // CREATED "Thu Nov 06 23:28:26 2014" module data_pins( bus_db_pin_oe, bus_db_pin_re, ctl_bus_db_we, clk, ctl_bus_db_oe, D, db ); input wire bus_db_pin_oe; input wire bus_db_pin_re; input wire ctl_bus_db_we; input wire clk; input wire ctl_bus_db_oe; inout wire [7:0] D; inout wire [7:0] db; reg [7:0] dout; wire [7:0] SYNTHESIZED_WIRE_0; wire SYNTHESIZED_WIRE_1; wire SYNTHESIZED_WIRE_2; wire [7:0] SYNTHESIZED_WIRE_3; wire [7:0] SYNTHESIZED_WIRE_4; always@(posedge SYNTHESIZED_WIRE_1) begin if (SYNTHESIZED_WIRE_2) begin dout[7:0] <= SYNTHESIZED_WIRE_0[7:0]; end end assign SYNTHESIZED_WIRE_4 = {ctl_bus_db_we,ctl_bus_db_we,ctl_bus_db_we,ctl_bus_db_we,ctl_bus_db_we,ctl_bus_db_we,ctl_bus_db_we,ctl_bus_db_we} & db; assign SYNTHESIZED_WIRE_3 = {bus_db_pin_re,bus_db_pin_re,bus_db_pin_re,bus_db_pin_re,bus_db_pin_re,bus_db_pin_re,bus_db_pin_re,bus_db_pin_re} & D; assign SYNTHESIZED_WIRE_0 = SYNTHESIZED_WIRE_3 | SYNTHESIZED_WIRE_4; assign SYNTHESIZED_WIRE_2 = ctl_bus_db_we | bus_db_pin_re; assign db[7] = ctl_bus_db_oe ? dout[7] : 1'bz; assign db[6] = ctl_bus_db_oe ? dout[6] : 1'bz; assign db[5] = ctl_bus_db_oe ? dout[5] : 1'bz; assign db[4] = ctl_bus_db_oe ? dout[4] : 1'bz; assign db[3] = ctl_bus_db_oe ? dout[3] : 1'bz; assign db[2] = ctl_bus_db_oe ? dout[2] : 1'bz; assign db[1] = ctl_bus_db_oe ? dout[1] : 1'bz; assign db[0] = ctl_bus_db_oe ? dout[0] : 1'bz; assign D[7] = bus_db_pin_oe ? dout[7] : 1'bz; assign D[6] = bus_db_pin_oe ? dout[6] : 1'bz; assign D[5] = bus_db_pin_oe ? dout[5] : 1'bz; assign D[4] = bus_db_pin_oe ? dout[4] : 1'bz; assign D[3] = bus_db_pin_oe ? dout[3] : 1'bz; assign D[2] = bus_db_pin_oe ? dout[2] : 1'bz; assign D[1] = bus_db_pin_oe ? dout[1] : 1'bz; assign D[0] = bus_db_pin_oe ? dout[0] : 1'bz; assign SYNTHESIZED_WIRE_1 = ~clk; endmodule ================================================ FILE: cpu/bus/data_pins_lattice.v ================================================ // Use this file with Lattice toolset instead of data_pins.v // // This file is provided courtesy by JuanS module data_pins( bus_db_pin_oe, bus_db_pin_re, ctl_bus_db_we, clk, ctl_bus_db_oe, D, db ); input wire bus_db_pin_oe; input wire bus_db_pin_re; input wire ctl_bus_db_we; input wire clk; input wire ctl_bus_db_oe; inout wire [7:0] D; inout wire [7:0] db; reg [7:0] dout; always@(negedge clk) begin if (ctl_bus_db_we | bus_db_pin_re) begin if (bus_db_pin_re) dout <= D; else if (ctl_bus_db_we) dout <= db; end end assign db = ctl_bus_db_oe ? dout : 8'hZ; assign D = bus_db_pin_oe ? dout : 8'hZ; endmodule ================================================ FILE: cpu/bus/data_switch.bdf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. 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22 32)(font "Courier New" (bold))(invisible)) (line (pt 24 20)(pt 24 32)) ) (port (pt 0 16) (output) (text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible)) (text "OUT" (rect -1 13 16 25)(font "Courier New" (bold))(invisible)) (line (pt 16 16)(pt 0 16)) ) (drawing (line (pt 34 7)(pt 34 25)) (line (pt 34 7)(pt 16 16)) (line (pt 34 25)(pt 16 16)) ) (rotate180) ) (connector (pt 208 88) (pt 232 88) (bus) ) (connector (pt 232 72) (pt 256 72) (bus) ) (connector (pt 232 104) (pt 256 104) (bus) ) (connector (pt 304 72) (pt 328 72) (bus) ) (connector (pt 328 104) (pt 304 104) (bus) ) (connector (pt 328 88) (pt 352 88) (bus) ) (connector (pt 280 40) (pt 280 56) ) (connector (pt 280 136) (pt 280 120) ) (connector (pt 232 72) (pt 232 88) (bus) ) (connector (pt 232 88) (pt 232 104) (bus) ) (connector (pt 328 72) (pt 328 88) (bus) ) (connector (pt 328 88) (pt 328 104) (bus) ) (connector (pt 208 40) (pt 280 40) ) (connector (pt 208 136) (pt 280 136) ) (junction (pt 232 88)) (junction (pt 328 88)) (title_block (rect 32 184 289 236) (name "title-custom-small") (section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "June 14, 2014" (rect 56 3 136 17)(font "Arial" (font_size 8)))(border)) (section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border)) (section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "data_switch" (rect 43 2 125 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.0" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border)) (drawing ) ) ================================================ FILE: cpu/bus/data_switch.bsf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "symbol" (version "1.2")) (symbol (rect 16 16 232 112) (text "data_switch" (rect 5 0 75 14)(font "Arial" (font_size 8))) (text "inst" (rect 8 80 25 92)(font "Arial" )) (port (pt 0 32) (input) (text "sw_up_en" (rect 0 0 61 14)(font "Arial" (font_size 8))) (text "sw_up_en" (rect 21 27 82 41)(font "Arial" (font_size 8))) (line (pt 0 32)(pt 16 32)) ) (port (pt 0 48) (input) (text "sw_down_en" (rect 0 0 80 14)(font "Arial" (font_size 8))) (text "sw_down_en" (rect 21 43 101 57)(font "Arial" (font_size 8))) (line (pt 0 48)(pt 16 48)) ) (port (pt 216 32) (bidir) (text "db_down[7..0]" (rect 0 0 82 14)(font "Arial" (font_size 8))) (text "db_down[7..0]" (rect 113 27 195 41)(font "Arial" (font_size 8))) (line (pt 216 32)(pt 200 32)(line_width 3)) ) (port (pt 216 48) (bidir) (text "db_up[7..0]" (rect 0 0 63 14)(font "Arial" (font_size 8))) (text "db_up[7..0]" (rect 132 43 195 57)(font "Arial" (font_size 8))) (line (pt 216 48)(pt 200 48)(line_width 3)) ) (drawing (rectangle (rect 16 16 200 80)) ) ) ================================================ FILE: cpu/bus/data_switch.v ================================================ // Copyright (C) 1991-2013 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // PROGRAM "Quartus II 64-Bit" // VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" // CREATED "Mon Oct 13 12:33:19 2014" module data_switch( sw_up_en, sw_down_en, db_down, db_up ); input wire sw_up_en; input wire sw_down_en; inout wire [7:0] db_down; inout wire [7:0] db_up; assign db_up[7] = sw_up_en ? db_down[7] : 1'bz; assign db_up[6] = sw_up_en ? db_down[6] : 1'bz; assign db_up[5] = sw_up_en ? db_down[5] : 1'bz; assign db_up[4] = sw_up_en ? db_down[4] : 1'bz; assign db_up[3] = sw_up_en ? db_down[3] : 1'bz; assign db_up[2] = sw_up_en ? db_down[2] : 1'bz; assign db_up[1] = sw_up_en ? db_down[1] : 1'bz; assign db_up[0] = sw_up_en ? db_down[0] : 1'bz; assign db_down[7] = sw_down_en ? db_up[7] : 1'bz; assign db_down[6] = sw_down_en ? db_up[6] : 1'bz; assign db_down[5] = sw_down_en ? db_up[5] : 1'bz; assign db_down[4] = sw_down_en ? db_up[4] : 1'bz; assign db_down[3] = sw_down_en ? db_up[3] : 1'bz; assign db_down[2] = sw_down_en ? db_up[2] : 1'bz; assign db_down[1] = sw_down_en ? db_up[1] : 1'bz; assign db_down[0] = sw_down_en ? db_up[0] : 1'bz; endmodule ================================================ FILE: cpu/bus/data_switch_mask.bdf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "graphic" (version "1.4")) (pin (input) (rect 32 32 208 48) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "sw_up_en" (rect 9 0 57 12)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) (line (pt 121 8)(pt 176 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) ) (pin (input) (rect 32 304 208 320) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "sw_down_en" (rect 9 0 70 12)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) (line (pt 121 8)(pt 176 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) ) (pin (input) (rect 32 336 208 352) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) 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(pt 600 128)) (junction (pt 600 88)) (junction (pt 520 272)) (title_block (rect 32 392 289 444) (name "title-custom-small") (section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "data_switch_mask" (rect 43 2 171 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border)) (section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "August 31, 2014" (rect 56 3 150 17)(font "Arial" (font_size 8)))(border)) (section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.0" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border)) (drawing ) ) ================================================ FILE: cpu/bus/data_switch_mask.bsf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "symbol" (version "1.2")) (symbol (rect 16 16 248 112) (text "data_switch_mask" (rect 5 0 112 14)(font "Arial" (font_size 8))) (text "inst" (rect 8 80 25 92)(font "Arial" )) (port (pt 0 32) (input) (text "sw_up_en" (rect 0 0 61 14)(font "Arial" (font_size 8))) (text "sw_up_en" (rect 21 27 82 41)(font "Arial" (font_size 8))) (line (pt 0 32)(pt 16 32)) ) (port (pt 0 48) (input) (text "sw_down_en" (rect 0 0 80 14)(font "Arial" (font_size 8))) (text "sw_down_en" (rect 21 43 101 57)(font "Arial" (font_size 8))) (line (pt 0 48)(pt 16 48)) ) (port (pt 0 64) (input) (text "sw_mask543_en" (rect 0 0 97 14)(font "Arial" (font_size 8))) (text "sw_mask543_en" (rect 21 59 118 73)(font "Arial" (font_size 8))) (line (pt 0 64)(pt 16 64)) ) (port (pt 232 32) (bidir) (text "db_down[7..0]" (rect 0 0 82 14)(font "Arial" (font_size 8))) (text "db_down[7..0]" (rect 129 27 211 41)(font "Arial" (font_size 8))) (line (pt 232 32)(pt 216 32)(line_width 3)) ) (port (pt 232 48) (bidir) (text "db_up[7..0]" (rect 0 0 63 14)(font "Arial" (font_size 8))) (text "db_up[7..0]" (rect 148 43 211 57)(font "Arial" (font_size 8))) (line (pt 232 48)(pt 216 48)(line_width 3)) ) (drawing (rectangle (rect 16 16 216 80)) ) ) ================================================ FILE: cpu/bus/data_switch_mask.v ================================================ // Copyright (C) 1991-2013 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // PROGRAM "Quartus II 64-Bit" // VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" // CREATED "Mon Oct 13 12:32:03 2014" module data_switch_mask( sw_up_en, sw_down_en, sw_mask543_en, db_down, db_up ); input wire sw_up_en; input wire sw_down_en; input wire sw_mask543_en; inout wire [7:0] db_down; inout wire [7:0] db_up; wire SYNTHESIZED_WIRE_4; wire [1:0] SYNTHESIZED_WIRE_1; wire [2:0] SYNTHESIZED_WIRE_2; assign SYNTHESIZED_WIRE_4 = ~sw_mask543_en; assign SYNTHESIZED_WIRE_1 = db_up[7:6] & {SYNTHESIZED_WIRE_4,SYNTHESIZED_WIRE_4}; assign db_down[7] = sw_down_en ? SYNTHESIZED_WIRE_1[1] : 1'bz; assign db_down[6] = sw_down_en ? SYNTHESIZED_WIRE_1[0] : 1'bz; assign db_down[2] = sw_down_en ? SYNTHESIZED_WIRE_2[2] : 1'bz; assign db_down[1] = sw_down_en ? SYNTHESIZED_WIRE_2[1] : 1'bz; assign db_down[0] = sw_down_en ? SYNTHESIZED_WIRE_2[0] : 1'bz; assign SYNTHESIZED_WIRE_2 = db_up[2:0] & {SYNTHESIZED_WIRE_4,SYNTHESIZED_WIRE_4,SYNTHESIZED_WIRE_4}; assign db_up[7] = sw_up_en ? db_down[7] : 1'bz; assign db_up[6] = sw_up_en ? db_down[6] : 1'bz; assign db_up[5] = sw_up_en ? db_down[5] : 1'bz; assign db_up[4] = sw_up_en ? db_down[4] : 1'bz; assign db_up[3] = sw_up_en ? db_down[3] : 1'bz; assign db_up[2] = sw_up_en ? db_down[2] : 1'bz; assign db_up[1] = sw_up_en ? db_down[1] : 1'bz; assign db_up[0] = sw_up_en ? db_down[0] : 1'bz; assign db_down[5] = sw_down_en ? db_up[5] : 1'bz; assign db_down[4] = sw_down_en ? db_up[4] : 1'bz; assign db_down[3] = sw_down_en ? db_up[3] : 1'bz; endmodule ================================================ FILE: cpu/bus/inc_dec.bdf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. 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(rect 2 1 48 13)(font "Arial" ))(text "inc_dec" (rect 43 2 113 21)(font "Arial" (font_size 12)(bold)))(border)) (section (rect 0 0 320 20)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 106 21)(font "Arial" (font_size 12)(bold)))(border)) (section (rect 241 41 320 60)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.0" (rect 43 3 64 19)(font "Arial" (font_size 10)))(border)) (drawing ) ) ================================================ FILE: cpu/bus/inc_dec.bsf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "symbol" (version "1.2")) (symbol (rect 16 16 216 144) (text "inc_dec" (rect 5 0 49 14)(font "Arial" (font_size 8))) (text "inst" (rect 8 112 25 124)(font "Arial" )) (port (pt 0 32) (input) (text "limit6" (rect 0 0 27 14)(font "Arial" (font_size 8))) (text "limit6" (rect 21 27 48 41)(font "Arial" (font_size 8))) (line (pt 0 32)(pt 16 32)) ) (port (pt 0 48) (input) (text "decrement" (rect 0 0 60 14)(font "Arial" (font_size 8))) (text "decrement" (rect 21 43 81 57)(font "Arial" (font_size 8))) (line (pt 0 48)(pt 16 48)) ) (port (pt 0 64) (input) (text "d[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) (text "d[15..0]" (rect 21 59 63 73)(font "Arial" (font_size 8))) (line (pt 0 64)(pt 16 64)(line_width 3)) ) (port (pt 0 80) (input) (text "carry_in" (rect 0 0 47 14)(font "Arial" (font_size 8))) (text "carry_in" (rect 21 75 68 89)(font "Arial" (font_size 8))) (line (pt 0 80)(pt 16 80)) ) (port (pt 200 32) (output) (text "address[15..0]" (rect 0 0 82 14)(font "Arial" (font_size 8))) (text "address[15..0]" (rect 97 27 179 41)(font "Arial" (font_size 8))) (line (pt 200 32)(pt 184 32)(line_width 3)) ) (drawing (rectangle (rect 16 16 184 112)) ) ) ================================================ FILE: cpu/bus/inc_dec.v ================================================ // Copyright (C) 1991-2013 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // PROGRAM "Quartus II 64-Bit" // VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" // CREATED "Mon Oct 13 12:30:20 2014" module inc_dec( carry_in, limit6, decrement, d, address ); input wire carry_in; input wire limit6; input wire decrement; input wire [15:0] d; output wire [15:0] address; wire [15:0] address_ALTERA_SYNTHESIZED; wire SYNTHESIZED_WIRE_40; wire SYNTHESIZED_WIRE_41; wire SYNTHESIZED_WIRE_42; wire SYNTHESIZED_WIRE_43; wire SYNTHESIZED_WIRE_44; wire SYNTHESIZED_WIRE_5; wire SYNTHESIZED_WIRE_45; wire SYNTHESIZED_WIRE_46; wire SYNTHESIZED_WIRE_47; wire SYNTHESIZED_WIRE_48; wire SYNTHESIZED_WIRE_49; wire SYNTHESIZED_WIRE_50; wire SYNTHESIZED_WIRE_12; wire SYNTHESIZED_WIRE_51; wire SYNTHESIZED_WIRE_52; wire SYNTHESIZED_WIRE_53; wire SYNTHESIZED_WIRE_16; wire SYNTHESIZED_WIRE_22; wire SYNTHESIZED_WIRE_25; wire SYNTHESIZED_WIRE_31; wire SYNTHESIZED_WIRE_34; wire SYNTHESIZED_WIRE_35; wire SYNTHESIZED_WIRE_36; wire SYNTHESIZED_WIRE_37; wire SYNTHESIZED_WIRE_38; wire SYNTHESIZED_WIRE_39; assign SYNTHESIZED_WIRE_34 = carry_in & SYNTHESIZED_WIRE_40 & SYNTHESIZED_WIRE_41 & SYNTHESIZED_WIRE_42 & SYNTHESIZED_WIRE_43 & SYNTHESIZED_WIRE_44 & SYNTHESIZED_WIRE_5 & SYNTHESIZED_WIRE_45; assign SYNTHESIZED_WIRE_51 = SYNTHESIZED_WIRE_46 & SYNTHESIZED_WIRE_47 & SYNTHESIZED_WIRE_48 & SYNTHESIZED_WIRE_49 & SYNTHESIZED_WIRE_50 & SYNTHESIZED_WIRE_12; assign SYNTHESIZED_WIRE_38 = SYNTHESIZED_WIRE_51 & SYNTHESIZED_WIRE_52 & SYNTHESIZED_WIRE_53 & SYNTHESIZED_WIRE_16; inc_dec_2bit b2v_dual_adder_0( .carry_borrow_in(carry_in), .d1_in(d[1]), .d0_in(d[0]), .dec1_in(SYNTHESIZED_WIRE_40), .dec0_in(SYNTHESIZED_WIRE_41), .carry_borrow_out(SYNTHESIZED_WIRE_22), .d1_out(address_ALTERA_SYNTHESIZED[1]), .d0_out(address_ALTERA_SYNTHESIZED[0])); inc_dec_2bit b2v_dual_adder_10( .carry_borrow_in(SYNTHESIZED_WIRE_51), .d1_in(d[13]), .d0_in(d[12]), .dec1_in(SYNTHESIZED_WIRE_53), .dec0_in(SYNTHESIZED_WIRE_52), .carry_borrow_out(SYNTHESIZED_WIRE_37), .d1_out(address_ALTERA_SYNTHESIZED[13]), .d0_out(address_ALTERA_SYNTHESIZED[12])); inc_dec_2bit b2v_dual_adder_2( .carry_borrow_in(SYNTHESIZED_WIRE_22), .d1_in(d[3]), .d0_in(d[2]), .dec1_in(SYNTHESIZED_WIRE_45), .dec0_in(SYNTHESIZED_WIRE_42), .carry_borrow_out(SYNTHESIZED_WIRE_25), .d1_out(address_ALTERA_SYNTHESIZED[3]), .d0_out(address_ALTERA_SYNTHESIZED[2])); inc_dec_2bit b2v_dual_adder_4( .carry_borrow_in(SYNTHESIZED_WIRE_25), .d1_in(d[5]), .d0_in(d[4]), .dec1_in(SYNTHESIZED_WIRE_43), .dec0_in(SYNTHESIZED_WIRE_44), .carry_borrow_out(SYNTHESIZED_WIRE_39), .d1_out(address_ALTERA_SYNTHESIZED[5]), .d0_out(address_ALTERA_SYNTHESIZED[4])); inc_dec_2bit b2v_dual_adder_7( .carry_borrow_in(SYNTHESIZED_WIRE_47), .d1_in(d[8]), .d0_in(d[7]), .dec1_in(SYNTHESIZED_WIRE_46), .dec0_in(SYNTHESIZED_WIRE_48), .carry_borrow_out(SYNTHESIZED_WIRE_31), .d1_out(address_ALTERA_SYNTHESIZED[8]), .d0_out(address_ALTERA_SYNTHESIZED[7])); inc_dec_2bit b2v_dual_adder_9( .carry_borrow_in(SYNTHESIZED_WIRE_31), .d1_in(d[10]), .d0_in(d[9]), .dec1_in(SYNTHESIZED_WIRE_50), .dec0_in(SYNTHESIZED_WIRE_49), .carry_borrow_out(SYNTHESIZED_WIRE_36), .d1_out(address_ALTERA_SYNTHESIZED[10]), .d0_out(address_ALTERA_SYNTHESIZED[9])); assign SYNTHESIZED_WIRE_47 = SYNTHESIZED_WIRE_34 & SYNTHESIZED_WIRE_35; assign SYNTHESIZED_WIRE_35 = ~limit6; assign SYNTHESIZED_WIRE_41 = d[0] ^ decrement; assign SYNTHESIZED_WIRE_40 = d[1] ^ decrement; assign SYNTHESIZED_WIRE_50 = d[10] ^ decrement; assign SYNTHESIZED_WIRE_12 = d[11] ^ decrement; assign address_ALTERA_SYNTHESIZED[11] = SYNTHESIZED_WIRE_36 ^ d[11]; assign SYNTHESIZED_WIRE_52 = d[12] ^ decrement; assign SYNTHESIZED_WIRE_53 = d[13] ^ decrement; assign SYNTHESIZED_WIRE_16 = d[14] ^ decrement; assign address_ALTERA_SYNTHESIZED[14] = SYNTHESIZED_WIRE_37 ^ d[14]; assign address_ALTERA_SYNTHESIZED[15] = SYNTHESIZED_WIRE_38 ^ d[15]; assign SYNTHESIZED_WIRE_42 = d[2] ^ decrement; assign SYNTHESIZED_WIRE_45 = d[3] ^ decrement; assign SYNTHESIZED_WIRE_44 = d[4] ^ decrement; assign SYNTHESIZED_WIRE_43 = d[5] ^ decrement; assign SYNTHESIZED_WIRE_5 = d[6] ^ decrement; assign address_ALTERA_SYNTHESIZED[6] = SYNTHESIZED_WIRE_39 ^ d[6]; assign SYNTHESIZED_WIRE_48 = d[7] ^ decrement; assign SYNTHESIZED_WIRE_46 = d[8] ^ decrement; assign SYNTHESIZED_WIRE_49 = d[9] ^ decrement; assign address = address_ALTERA_SYNTHESIZED; endmodule ================================================ FILE: cpu/bus/inc_dec_2bit.bdf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "graphic" (version "1.4")) (pin (input) (rect 24 80 200 96) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "carry_borrow_in" (rect 9 0 86 12)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) (line (pt 121 8)(pt 176 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) ) (pin (input) (rect 24 32 200 48) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "d1_in" (rect 9 0 34 12)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) (line (pt 121 8)(pt 176 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) ) (pin (input) (rect 24 200 200 216) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "d0_in" (rect 9 0 34 12)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) (line (pt 121 8)(pt 176 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) ) (pin (input) (rect 24 128 200 144) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "dec1_in" (rect 9 0 46 12)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) (line (pt 121 8)(pt 176 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) ) (pin (input) (rect 24 64 200 80) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "dec0_in" (rect 9 0 46 12)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) (line (pt 121 8)(pt 176 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) ) (pin (output) (rect 480 128 656 144) (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) (text "carry_borrow_out" (rect 90 0 174 12)(font "Arial" )) (pt 0 8) (drawing (line (pt 0 8)(pt 52 8)) (line (pt 52 4)(pt 78 4)) (line (pt 52 12)(pt 78 12)) (line (pt 52 12)(pt 52 4)) (line (pt 78 4)(pt 82 8)) (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) ) (pin (output) (rect 480 64 656 80) (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) (text "d1_out" (rect 90 0 123 12)(font "Arial" )) (pt 0 8) (drawing (line (pt 0 8)(pt 52 8)) (line (pt 52 4)(pt 78 4)) (line (pt 52 12)(pt 78 12)) (line (pt 52 12)(pt 52 4)) (line (pt 78 4)(pt 82 8)) (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) ) (pin (output) (rect 488 192 664 208) (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) (text "d0_out" (rect 90 0 123 12)(font "Arial" )) (pt 0 8) (drawing (line (pt 0 8)(pt 52 8)) (line (pt 52 4)(pt 78 4)) (line (pt 52 12)(pt 78 12)) (line (pt 52 12)(pt 52 4)) (line (pt 78 4)(pt 82 8)) (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) ) (symbol (rect 400 48 464 96) (text "XOR" (rect 1 0 21 10)(font "Arial" (font_size 6))) (text "xor2" (rect 3 37 24 49)(font "Arial" )) (port (pt 0 16) (input) (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible)) (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible)) (line (pt 0 16)(pt 11 16)) ) (port (pt 0 32) (input) (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible)) (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible)) (line (pt 0 32)(pt 11 32)) ) (port (pt 64 24) (output) (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible)) (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible)) (line (pt 49 24)(pt 64 24)) ) (drawing (line (pt 14 13)(pt 25 13)) (line (pt 14 36)(pt 25 36)) (arc (pt 7 29)(pt 7 19)(rect -14 8 19 41)) (arc (pt 49 24)(pt 25 13)(rect -6 13 57 76)) (arc (pt 25 35)(pt 49 24)(rect -6 -27 57 36)) (arc (pt 8 36)(pt 8 12)(rect -21 7 14 42)) ) ) (symbol (rect 400 176 464 224) (text "XOR" (rect 1 0 21 10)(font "Arial" (font_size 6))) (text "xor3" (rect 3 37 24 49)(font "Arial" )) (port (pt 0 16) (input) (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible)) (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible)) (line (pt 0 16)(pt 11 16)) ) (port (pt 0 32) (input) (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible)) (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible)) (line (pt 0 32)(pt 11 32)) ) (port (pt 64 24) (output) (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible)) (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible)) (line (pt 49 24)(pt 64 24)) ) (drawing (line (pt 14 13)(pt 25 13)) (line (pt 14 36)(pt 25 36)) (arc (pt 7 29)(pt 7 19)(rect -14 8 19 41)) (arc (pt 49 24)(pt 25 13)(rect -6 13 57 76)) (arc (pt 25 35)(pt 49 24)(rect -6 -27 57 36)) (arc (pt 8 36)(pt 8 12)(rect -21 7 14 42)) ) ) (symbol (rect 400 112 464 160) (text "AND3" (rect 1 0 25 10)(font "Arial" (font_size 6))) (text "and3" (rect 3 37 26 49)(font "Arial" )) (port (pt 0 16) (input) (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible)) (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible)) (line (pt 0 16)(pt 16 16)) ) (port (pt 0 24) (input) (text "IN2" (rect 2 15 19 27)(font "Courier New" (bold))(invisible)) (text "IN2" (rect 2 15 19 27)(font "Courier New" (bold))(invisible)) (line (pt 0 24)(pt 16 24)) ) (port (pt 0 32) (input) (text "IN3" (rect 2 23 19 35)(font "Courier New" (bold))(invisible)) (text "IN3" (rect 2 23 19 35)(font "Courier New" (bold))(invisible)) (line (pt 0 32)(pt 16 32)) ) (port (pt 64 24) (output) (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible)) (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible)) (line (pt 43 24)(pt 64 24)) ) (drawing (line (pt 16 12)(pt 31 12)) (line (pt 16 37)(pt 31 37)) (line (pt 16 12)(pt 16 37)) (arc (pt 31 36)(pt 31 12)(rect 19 12 44 37)) ) ) (symbol (rect 280 56 344 104) (text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6))) (text "and2" (rect 3 37 26 49)(font "Arial" )) (port (pt 0 16) (input) (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible)) (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible)) (line (pt 0 16)(pt 14 16)) ) (port (pt 0 32) (input) (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible)) (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible)) (line (pt 0 32)(pt 14 32)) ) (port (pt 64 24) (output) (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible)) (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible)) (line (pt 42 24)(pt 64 24)) ) (drawing (line (pt 14 12)(pt 30 12)) (line (pt 14 37)(pt 31 37)) (line (pt 14 12)(pt 14 37)) (arc (pt 31 37)(pt 30 12)(rect 18 12 43 37)) ) ) (connector (pt 480 72) (pt 464 72) ) (connector (pt 400 64) (pt 368 64) ) (connector (pt 400 80) (pt 344 80) ) (connector (pt 368 40) (pt 200 40) ) (connector (pt 368 64) (pt 368 40) ) (connector (pt 464 136) (pt 480 136) ) (connector (pt 200 136) (pt 400 136) ) (connector (pt 464 200) (pt 488 200) ) (connector (pt 200 208) (pt 400 208) ) (connector (pt 400 128) (pt 256 128) ) (connector (pt 256 72) (pt 256 128) ) (connector (pt 200 72) (pt 256 72) ) (connector (pt 256 72) (pt 280 72) ) (connector (pt 232 144) (pt 400 144) ) (connector (pt 232 192) (pt 400 192) ) (connector (pt 232 88) (pt 232 144) ) (connector (pt 232 144) (pt 232 192) ) (connector (pt 200 88) (pt 232 88) ) (connector (pt 232 88) (pt 280 88) ) (junction (pt 256 72)) (junction (pt 232 144)) (junction (pt 232 88)) (title_block (rect 24 256 281 308) (name "title-custom-small") (section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "May 3, 2014" (rect 56 3 125 17)(font "Arial" (font_size 8)))(border)) (section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border)) (section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "inc_dec_2bit" (rect 43 2 129 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.0" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border)) (drawing ) ) ================================================ FILE: cpu/bus/inc_dec_2bit.bsf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2011 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "symbol" (version "1.2")) (symbol (rect 64 64 312 224) (text "inc_dec_2bit" (rect 16 0 87 14)(font "Arial" (font_size 8))) (text "inst" (rect 112 72 129 84)(font "Arial" )) (port (pt 0 24) (input) (text "carry_borrow_in" (rect 0 0 96 14)(font "Arial" (font_size 8))) (text "carry_borrow_in" (rect 21 19 117 33)(font "Arial" (font_size 8))) (line (pt 0 24)(pt 16 24)) ) (port (pt 0 104) (input) (text "d1_in" (rect 0 0 30 14)(font "Arial" (font_size 8))) (text "d1_in" (rect 21 99 51 113)(font "Arial" (font_size 8))) (line (pt 0 104)(pt 16 104)) ) (port (pt 0 40) (input) (text "d0_in" (rect 0 0 30 14)(font "Arial" (font_size 8))) (text "d0_in" (rect 21 35 51 49)(font "Arial" (font_size 8))) (line (pt 0 40)(pt 16 40)) ) (port (pt 0 136) (input) (text "dec1_in" (rect 0 0 44 14)(font "Arial" (font_size 8))) (text "dec1_in" (rect 21 131 65 145)(font "Arial" (font_size 8))) (line (pt 0 136)(pt 16 136)) ) (port (pt 0 72) (input) (text "dec0_in" (rect 0 0 44 14)(font "Arial" (font_size 8))) (text "dec0_in" (rect 21 67 65 81)(font "Arial" (font_size 8))) (line (pt 0 72)(pt 16 72)) ) (port (pt 248 128) (output) (text "carry_borrow_out" (rect -8 0 97 14)(font "Arial" (font_size 8))) (text "carry_borrow_out" (rect 122 123 227 137)(font "Arial" (font_size 8))) (line (pt 248 128)(pt 232 128)) ) (port (pt 248 80) (output) (text "d1_out" (rect -8 0 30 14)(font "Arial" (font_size 8))) (text "d1_out" (rect 189 75 227 89)(font "Arial" (font_size 8))) (line (pt 248 80)(pt 232 80)) ) (port (pt 248 56) (output) (text "d0_out" (rect -8 0 30 14)(font "Arial" (font_size 8))) (text "d0_out" (rect 189 51 227 65)(font "Arial" (font_size 8))) (line (pt 248 56)(pt 232 56)) ) (drawing (rectangle (rect 16 16 240 152)) ) (fill (color 253 211 206)) ) ================================================ FILE: cpu/bus/inc_dec_2bit.v ================================================ // Copyright (C) 1991-2013 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // PROGRAM "Quartus II 64-Bit" // VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" // CREATED "Mon Oct 13 12:26:57 2014" module inc_dec_2bit( carry_borrow_in, d1_in, d0_in, dec1_in, dec0_in, carry_borrow_out, d1_out, d0_out ); input wire carry_borrow_in; input wire d1_in; input wire d0_in; input wire dec1_in; input wire dec0_in; output wire carry_borrow_out; output wire d1_out; output wire d0_out; wire SYNTHESIZED_WIRE_0; assign SYNTHESIZED_WIRE_0 = dec0_in & carry_borrow_in; assign carry_borrow_out = dec0_in & dec1_in & carry_borrow_in; assign d1_out = d1_in ^ SYNTHESIZED_WIRE_0; assign d0_out = carry_borrow_in ^ d0_in; endmodule ================================================ FILE: cpu/bus/simulation/modelsim/r ================================================ restart -f ; run -all ================================================ FILE: cpu/bus/simulation/modelsim/test_bus.mpf ================================================ ; Copyright 1991-2009 Mentor Graphics Corporation ; ; All Rights Reserved. ; ; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF ; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. ; [Library] std = $MODEL_TECH/../std ieee = $MODEL_TECH/../ieee verilog = $MODEL_TECH/../verilog vital2000 = $MODEL_TECH/../vital2000 std_developerskit = $MODEL_TECH/../std_developerskit synopsys = $MODEL_TECH/../synopsys modelsim_lib = $MODEL_TECH/../modelsim_lib sv_std = $MODEL_TECH/../sv_std ; Altera Primitive libraries ; ; VHDL Section ; altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf altera = $MODEL_TECH/../altera/vhdl/altera altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim lpm = $MODEL_TECH/../altera/vhdl/220model 220model = $MODEL_TECH/../altera/vhdl/220model max = $MODEL_TECH/../altera/vhdl/max maxii = $MODEL_TECH/../altera/vhdl/maxii maxv = $MODEL_TECH/../altera/vhdl/maxv stratix = $MODEL_TECH/../altera/vhdl/stratix stratixii = $MODEL_TECH/../altera/vhdl/stratixii stratixiigx = $MODEL_TECH/../altera/vhdl/stratixiigx hardcopyii = $MODEL_TECH/../altera/vhdl/hardcopyii hardcopyiii = $MODEL_TECH/../altera/vhdl/hardcopyiii hardcopyiv = $MODEL_TECH/../altera/vhdl/hardcopyiv cyclone = $MODEL_TECH/../altera/vhdl/cyclone cycloneii = $MODEL_TECH/../altera/vhdl/cycloneii cycloneiii = $MODEL_TECH/../altera/vhdl/cycloneiii cycloneiiils = $MODEL_TECH/../altera/vhdl/cycloneiiils sgate = $MODEL_TECH/../altera/vhdl/sgate stratixgx = $MODEL_TECH/../altera/vhdl/stratixgx altgxb = $MODEL_TECH/../altera/vhdl/altgxb stratixgx_gxb = $MODEL_TECH/../altera/vhdl/stratixgx_gxb stratixiigx_hssi = $MODEL_TECH/../altera/vhdl/stratixiigx_hssi arriagx_hssi = $MODEL_TECH/../altera/vhdl/arriagx_hssi arriaii = $MODEL_TECH/../altera/vhdl/arriaii arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip arriagx = $MODEL_TECH/../altera/vhdl/arriagx altgxb_lib = $MODEL_TECH/../altera/vhdl/altgxb stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive hardcopyiv_hssi = $MODEL_TECH/../altera/vhdl/hardcopyiv_hssi hardcopyiv_pcie_hip = $MODEL_TECH/../altera/vhdl/hardcopyiv_pcie_hip stratixv = $MODEL_TECH/../altera/vhdl/stratixv stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip arriav = $MODEL_TECH/../altera/vhdl/arriav cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev ; ; Verilog Section ; altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf altera_ver = $MODEL_TECH/../altera/verilog/altera altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim lpm_ver = $MODEL_TECH/../altera/verilog/220model 220model_ver = $MODEL_TECH/../altera/verilog/220model max_ver = $MODEL_TECH/../altera/verilog/max maxii_ver = $MODEL_TECH/../altera/verilog/maxii maxv_ver = $MODEL_TECH/../altera/verilog/maxv stratix_ver = $MODEL_TECH/../altera/verilog/stratix stratixii_ver = $MODEL_TECH/../altera/verilog/stratixii stratixiigx_ver = $MODEL_TECH/../altera/verilog/stratixiigx arriagx_ver = $MODEL_TECH/../altera/verilog/arriagx hardcopyii_ver = $MODEL_TECH/../altera/verilog/hardcopyii hardcopyiii_ver = $MODEL_TECH/../altera/verilog/hardcopyiii hardcopyiv_ver = $MODEL_TECH/../altera/verilog/hardcopyiv cyclone_ver = $MODEL_TECH/../altera/verilog/cyclone cycloneii_ver = $MODEL_TECH/../altera/verilog/cycloneii cycloneiii_ver = $MODEL_TECH/../altera/verilog/cycloneiii cycloneiiils_ver = $MODEL_TECH/../altera/verilog/cycloneiiils sgate_ver = $MODEL_TECH/../altera/verilog/sgate stratixgx_ver = $MODEL_TECH/../altera/verilog/stratixgx altgxb_ver = $MODEL_TECH/../altera/verilog/altgxb stratixgx_gxb_ver = $MODEL_TECH/../altera/verilog/stratixgx_gxb stratixiigx_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiigx_hssi arriagx_hssi_ver = $MODEL_TECH/../altera/verilog/arriagx_hssi arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip stratixiii_ver = $MODEL_TECH/../altera/verilog/stratixiii stratixiii = $MODEL_TECH/../altera/vhdl/stratixiii stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip arriav_ver = $MODEL_TECH/../altera/verilog/arriav arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive hardcopyiv_hssi_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_hssi hardcopyiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_pcie_hip work = work [vcom] ; VHDL93 variable selects language version as the default. ; Default is VHDL-2002. ; Value of 0 or 1987 for VHDL-1987. ; Value of 1 or 1993 for VHDL-1993. ; Default or value of 2 or 2002 for VHDL-2002. ; Default or value of 3 or 2008 for VHDL-2008. VHDL93 = 2002 ; Show source line containing error. Default is off. ; Show_source = 1 ; Turn off unbound-component warnings. Default is on. ; Show_Warning1 = 0 ; Turn off process-without-a-wait-statement warnings. Default is on. ; Show_Warning2 = 0 ; Turn off null-range warnings. Default is on. ; Show_Warning3 = 0 ; Turn off no-space-in-time-literal warnings. Default is on. ; Show_Warning4 = 0 ; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. ; Show_Warning5 = 0 ; Turn off optimization for IEEE std_logic_1164 package. Default is on. ; Optimize_1164 = 0 ; Turn on resolving of ambiguous function overloading in favor of the ; "explicit" function declaration (not the one automatically created by ; the compiler for each type declaration). Default is off. ; The .ini file has Explicit enabled so that std_logic_signed/unsigned ; will match the behavior of synthesis tools. Explicit = 1 ; Turn off acceleration of the VITAL packages. Default is to accelerate. ; NoVital = 1 ; Turn off VITAL compliance checking. Default is checking on. ; NoVitalCheck = 1 ; Ignore VITAL compliance checking errors. Default is to not ignore. ; IgnoreVitalErrors = 1 ; Turn off VITAL compliance checking warnings. Default is to show warnings. ; Show_VitalChecksWarnings = 0 ; Keep silent about case statement static warnings. ; Default is to give a warning. ; NoCaseStaticError = 1 ; Keep silent about warnings caused by aggregates that are not locally static. ; Default is to give a warning. ; NoOthersStaticError = 1 ; Turn off inclusion of debugging info within design units. ; Default is to include debugging info. ; NoDebug = 1 ; Turn off "Loading..." messages. Default is messages on. ; Quiet = 1 ; Turn on some limited synthesis rule compliance checking. Checks only: ; -- signals used (read) by a process must be in the sensitivity list ; CheckSynthesis = 1 ; Activate optimizations on expressions that do not involve signals, ; waits, or function/procedure/task invocations. Default is off. ; ScalarOpts = 1 ; Require the user to specify a configuration for all bindings, ; and do not generate a compile time default binding for the ; component. This will result in an elaboration error of ; 'component not bound' if the user fails to do so. Avoids the rare ; issue of a false dependency upon the unused default binding. ; RequireConfigForAllDefaultBinding = 1 ; Inhibit range checking on subscripts of arrays. Range checking on ; scalars defined with subtypes is inhibited by default. ; NoIndexCheck = 1 ; Inhibit range checks on all (implicit and explicit) assignments to ; scalar objects defined with subtypes. ; NoRangeCheck = 1 [vlog] ; Turn off inclusion of debugging info within design units. ; Default is to include debugging info. ; NoDebug = 1 ; Turn off "loading..." messages. Default is messages on. ; Quiet = 1 ; Turn on Verilog hazard checking (order-dependent accessing of global vars). ; Default is off. ; Hazard = 1 ; Turn on converting regular Verilog identifiers to uppercase. Allows case ; insensitivity for module names. Default is no conversion. ; UpCase = 1 ; Turn on incremental compilation of modules. Default is off. ; Incremental = 1 ; Turns on lint-style checking. ; Show_Lint = 1 [vsim] ; Simulator resolution ; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. Resolution = ps ; User time unit for run commands ; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the ; unit specified for Resolution. For example, if Resolution is 100ps, ; then UserTimeUnit defaults to ps. ; Should generally be set to default. UserTimeUnit = default ; Default run length RunLength = 1 us ; Maximum iterations that can be run without advancing simulation time IterationLimit = 5000 ; Directive to license manager: ; vhdl Immediately reserve a VHDL license ; vlog Immediately reserve a Verilog license ; plus Immediately reserve a VHDL and Verilog license ; nomgc Do not look for Mentor Graphics Licenses ; nomti Do not look for Model Technology Licenses ; noqueue Do not wait in the license queue when a license isn't available ; viewsim Try for viewer license but accept simulator license(s) instead ; of queuing for viewer license ; License = plus ; Stop the simulator after a VHDL/Verilog assertion message ; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal BreakOnAssertion = 3 ; Assertion Message Format ; %S - Severity Level ; %R - Report Message ; %T - Time of assertion ; %D - Delta ; %I - Instance or Region pathname (if available) ; %% - print '%' character ; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" ; Assertion File - alternate file for storing VHDL/Verilog assertion messages ; AssertFile = assert.log ; Default radix for all windows and commands... ; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned DefaultRadix = hexadecimal ; VSIM Startup command ; Startup = do startup.do ; File for saving command transcript TranscriptFile = transcript ; File for saving command history ; CommandHistory = cmdhist.log ; Specify whether paths in simulator commands should be described ; in VHDL or Verilog format. ; For VHDL, PathSeparator = / ; For Verilog, PathSeparator = . ; Must not be the same character as DatasetSeparator. PathSeparator = / ; Specify the dataset separator for fully rooted contexts. ; The default is ':'. For example, sim:/top ; Must not be the same character as PathSeparator. DatasetSeparator = : ; Disable VHDL assertion messages ; IgnoreNote = 1 ; IgnoreWarning = 1 ; IgnoreError = 1 ; IgnoreFailure = 1 ; Default force kind. May be freeze, drive, deposit, or default ; or in other terms, fixed, wired, or charged. ; A value of "default" will use the signal kind to determine the ; force kind, drive for resolved signals, freeze for unresolved signals ; DefaultForceKind = freeze ; If zero, open files when elaborated; otherwise, open files on ; first read or write. Default is 0. ; DelayFileOpen = 1 ; Control VHDL files opened for write. ; 0 = Buffered, 1 = Unbuffered UnbufferedOutput = 0 ; Control the number of VHDL files open concurrently. ; This number should always be less than the current ulimit ; setting for max file descriptors. ; 0 = unlimited ConcurrentFileLimit = 40 ; Control the number of hierarchical regions displayed as ; part of a signal name shown in the Wave window. ; A value of zero tells VSIM to display the full name. ; The default is 0. ; WaveSignalNameWidth = 0 ; Turn off warnings from the std_logic_arith, std_logic_unsigned ; and std_logic_signed packages. ; StdArithNoWarnings = 1 ; Turn off warnings from the IEEE numeric_std and numeric_bit packages. ; NumericStdNoWarnings = 1 ; Control the format of the (VHDL) FOR generate statement label ; for each iteration. Do not quote it. ; The format string here must contain the conversion codes %s and %d, ; in that order, and no other conversion codes. The %s represents ; the generate_label; the %d represents the generate parameter value ; at a particular generate iteration (this is the position number if ; the generate parameter is of an enumeration type). Embedded whitespace ; is allowed (but discouraged); leading and trailing whitespace is ignored. ; Application of the format must result in a unique scope name over all ; such names in the design so that name lookup can function properly. ; GenerateFormat = %s__%d ; Specify whether checkpoint files should be compressed. ; The default is 1 (compressed). ; CheckpointCompressMode = 0 ; List of dynamically loaded objects for Verilog PLI applications ; Veriuser = veriuser.sl ; Specify default options for the restart command. Options can be one ; or more of: -force -nobreakpoint -nolist -nolog -nowave ; DefaultRestartOptions = -force ; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs ; (> 500 megabyte memory footprint). Default is disabled. ; Specify number of megabytes to lock. ; LockedMemory = 1000 ; Turn on (1) or off (0) WLF file compression. ; The default is 1 (compress WLF file). ; WLFCompress = 0 ; Specify whether to save all design hierarchy (1) in the WLF file ; or only regions containing logged signals (0). ; The default is 0 (save only regions with logged signals). ; WLFSaveAllRegions = 1 ; WLF file time limit. Limit WLF file by time, as closely as possible, ; to the specified amount of simulation time. When the limit is exceeded ; the earliest times get truncated from the file. ; If both time and size limits are specified the most restrictive is used. ; UserTimeUnits are used if time units are not specified. ; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} ; WLFTimeLimit = 0 ; WLF file size limit. Limit WLF file size, as closely as possible, ; to the specified number of megabytes. If both time and size limits ; are specified then the most restrictive is used. ; The default is 0 (no limit). ; WLFSizeLimit = 1000 ; Specify whether or not a WLF file should be deleted when the ; simulation ends. A value of 1 will cause the WLF file to be deleted. ; The default is 0 (do not delete WLF file when simulation ends). ; WLFDeleteOnQuit = 1 ; Automatic SDF compilation ; Disables automatic compilation of SDF files in flows that support it. ; Default is on, uncomment to turn off. ; NoAutoSDFCompile = 1 [lmc] [msg_system] ; Change a message severity or suppress a message. ; The format is: = [,...] ; Examples: ; note = 3009 ; warning = 3033 ; error = 3010,3016 ; fatal = 3016,3033 ; suppress = 3009,3016,3043 ; The command verror can be used to get the complete ; description of a message. ; Control transcripting of elaboration/runtime messages. ; The default is to have messages appear in the transcript and ; recorded in the wlf file (messages that are recorded in the ; wlf file can be viewed in the MsgViewer). The other settings ; are to send messages only to the transcript or only to the ; wlf file. The valid values are ; both {default} ; tran {transcript only} ; wlf {wlf file only} ; msgmode = both [Project] ; Warning -- Do not edit the project properties directly. ; Property names are dynamic in nature and property ; values have special syntax. Changing property data directly ; can result in a corrupt MPF file. All project properties ; can be modified through project window dialogs. Project_Version = 6 Project_DefaultLib = work Project_SortMethod = unused Project_Files_Count = 8 Project_File_0 = $ROOT/cpu/bus/address_latch.v Project_File_P_0 = compile_order 0 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 Project_File_1 = $ROOT/cpu/bus/address_mux.v Project_File_P_1 = compile_order 7 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 Project_File_2 = $ROOT/cpu/bus/address_pins.v Project_File_P_2 = compile_order 5 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 Project_File_3 = $ROOT/cpu/bus/data_pins.v Project_File_P_3 = compile_order 6 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 Project_File_4 = $ROOT/cpu/bus/inc_dec.v Project_File_P_4 = compile_order 1 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 Project_File_5 = $ROOT/cpu/bus/inc_dec_2bit.v Project_File_P_5 = compile_order 3 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 Project_File_6 = $ROOT/cpu/bus/test_bus.sv Project_File_P_6 = compile_order 2 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 Project_File_7 = $ROOT/cpu/bus/test_pins.sv Project_File_P_7 = compile_order 4 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 Project_Sim_Count = 2 Project_Sim_0 = Test pins Project_Sim_P_0 = timing default -t default -sdfnoerror 0 -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder {Top Level} +pulse_e {} additional_dus work.test_pins -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {} Project_Sim_1 = Test bus Project_Sim_P_1 = timing default -t default -sdfnoerror 0 -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder {Top Level} +pulse_e {} additional_dus work.test_bus -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {} Project_Folder_Count = 0 Echo_Compile_Output = 0 Save_Compile_Report = 1 Project_Opt_Count = 0 ForceSoftPaths = 1 ProjectStatusDelay = 5000 VERILOG_DoubleClick = Edit VERILOG_CustomDoubleClick = SYSTEMVERILOG_DoubleClick = Edit SYSTEMVERILOG_CustomDoubleClick = VHDL_DoubleClick = Edit VHDL_CustomDoubleClick = PSL_DoubleClick = Edit PSL_CustomDoubleClick = TEXT_DoubleClick = Edit TEXT_CustomDoubleClick = SYSTEMC_DoubleClick = Edit SYSTEMC_CustomDoubleClick = TCL_DoubleClick = Edit TCL_CustomDoubleClick = MACRO_DoubleClick = Edit MACRO_CustomDoubleClick = VCD_DoubleClick = Edit VCD_CustomDoubleClick = SDF_DoubleClick = Edit SDF_CustomDoubleClick = XML_DoubleClick = Edit XML_CustomDoubleClick = LOGFILE_DoubleClick = Edit LOGFILE_CustomDoubleClick = UCDB_DoubleClick = Edit UCDB_CustomDoubleClick = UPF_DoubleClick = Edit UPF_CustomDoubleClick = PCF_DoubleClick = Edit PCF_CustomDoubleClick = PROJECT_DoubleClick = Edit PROJECT_CustomDoubleClick = VRM_DoubleClick = Edit VRM_CustomDoubleClick = DEBUGDATABASE_DoubleClick = Edit DEBUGDATABASE_CustomDoubleClick = DEBUGARCHIVE_DoubleClick = Edit DEBUGARCHIVE_CustomDoubleClick = Project_Major_Version = 10 Project_Minor_Version = 1 ================================================ FILE: cpu/bus/simulation/modelsim/wave_bus.do ================================================ onerror {resume} quietly WaveActivateNextPane {} 0 add wave -noupdate /test_bus/nreset add wave -noupdate /test_bus/clk add wave -noupdate /test_bus/abusw add wave -noupdate /test_bus/abus add wave -noupdate -color Gold /test_bus/address add wave -noupdate /test_bus/ctl_al_we add wave -noupdate /test_bus/ctl_bus_inc_oe add wave -noupdate /test_bus/ctl_inc_dec add wave -noupdate /test_bus/ctl_inc_limit6 add wave -noupdate /test_bus/ctl_inc_cy add wave -noupdate /test_bus/clrpc add wave -noupdate /test_bus/address_is_1 add wave -noupdate /test_bus/address_latch_/ctl_apin_mux add wave -noupdate /test_bus/address_latch_/ctl_apin_mux2 TreeUpdate [SetDefaultTree] WaveRestoreCursors {{Cursor 1} {5500 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 141 configure wave -valuecolwidth 62 configure wave -justifyvalue left configure wave -signalnamewidth 1 configure wave -snapdistance 10 configure wave -datasetprefix 0 configure wave -rowmargin 4 configure wave -childrowmargin 2 configure wave -gridoffset 0 configure wave -gridperiod 1 configure wave -griddelta 40 configure wave -timeline 1 configure wave -timelineunits ps update WaveRestoreZoom {0 ns} {39500 ns} ================================================ FILE: cpu/bus/simulation/modelsim/wave_pins.do ================================================ onerror {resume} quietly WaveActivateNextPane {} 0 add wave -noupdate /test_pins/clk add wave -noupdate -divider apins add wave -noupdate -color Gold -radix hexadecimal /test_pins/apin add wave -noupdate -radix hexadecimal /test_pins/ab add wave -noupdate /test_pins/ctl_ab_we add wave -noupdate -divider dpins add wave -noupdate -radix hexadecimal /test_pins/dpin add wave -noupdate -color Gold -radix hexadecimal /test_pins/db add wave -noupdate /test_pins/ctl_db_we add wave -noupdate /test_pins/ctl_db_pin_re add wave -noupdate /test_pins/ctl_db_pin_oe add wave -noupdate /test_pins/ctl_db_oe add wave -noupdate -radix hexadecimal /test_pins/db_w add wave -noupdate -radix hexadecimal /test_pins/dpin_w TreeUpdate [SetDefaultTree] WaveRestoreCursors {{Cursor 1} {19000 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 138 configure wave -valuecolwidth 54 configure wave -justifyvalue right configure wave -signalnamewidth 1 configure wave -snapdistance 10 configure wave -datasetprefix 0 configure wave -rowmargin 4 configure wave -childrowmargin 2 configure wave -gridoffset 0 configure wave -gridperiod 1 configure wave -griddelta 40 configure wave -timeline 1 configure wave -timelineunits us update WaveRestoreZoom {0 ns} {57700 ns} ================================================ FILE: cpu/bus/test_bus.qpf ================================================ # -------------------------------------------------------------------------- # # # Copyright (C) 1991-2013 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Altera Program License # Subscription Agreement, Altera MegaCore Function License # Agreement, or other applicable license agreement, including, # without limitation, that your use is for the sole purpose of # programming logic devices manufactured by Altera and sold by # Altera or its authorized distributors. Please refer to the # applicable agreement for further details. # # -------------------------------------------------------------------------- # # # Quartus II 64-Bit # Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition # Date created = 09:15:26 October 13, 2014 # # -------------------------------------------------------------------------- # QUARTUS_VERSION = "13.0" DATE = "09:15:26 October 13, 2014" # Revisions PROJECT_REVISION = "test_bus" ================================================ FILE: cpu/bus/test_bus.qsf ================================================ # -------------------------------------------------------------------------- # # # Copyright (C) 1991-2013 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Altera Program License # Subscription Agreement, Altera MegaCore Function License # Agreement, or other applicable license agreement, including, # without limitation, that your use is for the sole purpose of # programming logic devices manufactured by Altera and sold by # Altera or its authorized distributors. Please refer to the # applicable agreement for further details. # # -------------------------------------------------------------------------- # # # Quartus II 64-Bit # Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition # Date created = 09:15:26 October 13, 2014 # # -------------------------------------------------------------------------- # # # Notes: # # 1) The default values for assignments are stored in the file: # test_bus_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # # 2) Altera recommends that you do not modify this file. This # file is updated automatically by the Quartus II software # and any changes you make may be lost or overwritten. # # -------------------------------------------------------------------------- # set_global_assignment -name FAMILY "Cyclone II" set_global_assignment -name DEVICE EP2C20F484C7 set_global_assignment -name TOP_LEVEL_ENTITY control_pins_n set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:15:26 OCTOBER 13, 2014" set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS OFF set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF set_global_assignment -name USE_CONFIGURATION_DEVICE ON set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP" set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON set_global_assignment -name BSF_FILE address_mux.bsf set_global_assignment -name BSF_FILE inc_dec_2bit.bsf set_global_assignment -name BDF_FILE inc_dec_2bit.bdf set_global_assignment -name BDF_FILE inc_dec.bdf set_global_assignment -name BDF_FILE data_switch_mask.bdf set_global_assignment -name BDF_FILE data_switch.bdf set_global_assignment -name BDF_FILE data_pins.bdf set_global_assignment -name BDF_FILE control_pins_n.bdf set_global_assignment -name BDF_FILE bus_control.bdf set_global_assignment -name BDF_FILE address_pins.bdf set_global_assignment -name BDF_FILE address_latch.bdf set_global_assignment -name BDF_FILE address_mux.bdf set_global_assignment -name VERILOG_FILE bus_switch.v set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top ================================================ FILE: cpu/bus/test_bus.sv ================================================ //============================================================== // Test address latch and increment block //============================================================== `timescale 1us/ 100 ns module test_bus; // ----------------- CLOCKS AND RESET ----------------- // Define one full T-clock cycle delay `define T #2 bit clk = 1; initial repeat (26) #1 clk = ~clk; reg nreset; // ---------------------------------------------------- // Bi-directional bus that can also be tri-stated reg [15:0] abusw; // Drive it using this bus wire [15:0] abus; // Read it using this bus wire [15:0] address; // Final address ouput // ----------------- INPUT CONTROL ----------------- reg ctl_al_we; // Write enable to address latch reg ctl_bus_inc_oe; // Write incrementer onto the internal data bus reg ctl_apin_mux; // Selects mux1 reg ctl_apin_mux2; // Selects mux2 // ----------------- INC/DEC ----------------- reg ctl_inc_dec; // Perform decrement (1) or increment (0) reg ctl_inc_limit6; // Limit increment to 6 bits (for incrementing IR) reg ctl_inc_cy; // Address increment, carry in value (+/-1 or 0) reg clrpc; // Force zero (to clear PC/IR) // ----------------- OUTPUT/STATUS ----------------- wire address_is_1; // Signals when the final address is 1 // ----------------- TEST ------------------- `define CHECK(arg) \ assert(address==arg); initial begin nreset = 0; abusw = 'z; ctl_al_we = 0; ctl_bus_inc_oe = 0; ctl_inc_dec = 0; ctl_inc_limit6 = 0; ctl_inc_cy = 0; clrpc = 0; ctl_apin_mux = 0; ctl_apin_mux2 = 0; //------------------------------------------------------------ `T nreset = 1; //------------------------------------------------------------ // Perform a simple increment and decrement `T abusw = 16'h1234; ctl_al_we = 1; // Write value to the latch ctl_apin_mux = 1; // Output incrementer to the address bus ctl_inc_cy = 1; // +1 show "1235" `T `CHECK(16'h1235); ctl_inc_dec = 1; // -1 show "1233" `T `CHECK(16'h1233); // ...through overflow abusw = 16'hffff; ctl_inc_dec = 0; ctl_inc_cy = 1; // +1 show "0" `T `CHECK(16'h0000); ctl_inc_dec = 1; // -1 show "FFFE" `T `CHECK(16'hFFFE); abusw = 16'h0; ctl_inc_dec = 0; ctl_inc_cy = 1; // +1 show "1" `T `CHECK(16'h0001); ctl_inc_dec = 1; // -1 show "FFFF" `T `CHECK(16'hFFFF); ctl_inc_cy = 0; // show "0000" `T `CHECK(16'h0000); ctl_inc_dec = 0; // show "0000" //------------------------------------------------------------ // Test the address latch and the mux `T abusw = 16'hAA50; ctl_al_we = 1; // Write AA55 to the latch ctl_inc_cy = 1; `T ctl_al_we = 0; // show "AA51" `T `CHECK(16'hAA51); ctl_apin_mux = 0; ctl_apin_mux2 = 1; //------------------------------------------------------------ // Test the tri-state db `T abusw = 'z; ctl_bus_inc_oe = 1; // Output latched value (AA50) `T `CHECK(16'hAA50); `T $display("End of test"); end // Drive 3-state bidirectional bus with these statements assign abus = abusw; //-------------------------------------------------------------- // Instantiate address latch block //-------------------------------------------------------------- address_latch address_latch_( .* ); endmodule ================================================ FILE: cpu/bus/test_pins.sv ================================================ //============================================================== // Test address and data pins blocks //============================================================== `timescale 1us/ 100 ns module test_pins; // ----------------- CLOCKS AND RESET ----------------- // Define one full T-clock cycle delay `define T #2 bit clk = 1; initial repeat (24) #1 clk = ~clk; // ------------------------ ADDRESS PINS --------------------- logic [15:0] ab; // Internal address bus logic ctl_ab_we; // Write enable to address pin latch logic pin_control_oe; // Output enable to address pins; otherwise tri-stated wire [15:0] apin; // Output address bus to address pins // ------------------------ DATA PINS ------------------------ logic ctl_db_we; // Write enable to data pin output latch logic ctl_db_oe; // Output enable to internal data bus logic ctl_db_pin_re; // Read from the data pin into the latch logic ctl_db_pin_oe; // Output enable to data pins; otherwise tri-stated logic ctl_pin_oe; // ---------------------------------------------------- // Bidirectional internal data bus logic [7:0] db_w; // Drive it using this bus wire [7:0] db; // Read it using this bus assign db = db_w; // Drive 3-state bidirectional bus always_comb // Output to pin bus only when our begin // test is not driving it if (db_w==='z) ctl_db_oe = 1; else ctl_db_oe = 0; end // ---------------------------------------------------- // Bidirectional external data pins logic [7:0] dpin_w; // Drive it using this bus wire [7:0] dpin; // Read it using this bus assign dpin = dpin_w; // Drive 3-state bidirectional always_comb // Output to pin bus only when our begin // test is not driving it if (dpin_w==='z) ctl_db_pin_oe = 1; else ctl_db_pin_oe = 0; end // ----------------- TEST ------------------- `define CHECKA(arg) \ assert(apin===arg); `define CHECKD(arg) \ assert(dpin===arg); initial begin ab = 16'h0; ctl_ab_we = 0; pin_control_oe = 0; db_w = 'z; dpin_w = 'z; ctl_db_we = 0; //------------------------------------------------------------ // Test the address pin logic `T ab = 16'hAA55; // Latch a value and output it ctl_ab_we = 1; pin_control_oe = 1; `T ctl_ab_we = 0; `T `CHECKA(16'hAA55); pin_control_oe = 0; ab = 16'h1234; // Should not affect `T pin_control_oe = 1; // Toggle output on and off `T `CHECKA(16'hAA55); pin_control_oe = 0; `T `CHECKA(16'hz); //------------------------------------------------------------ // Test the data pin logic `T dpin_w = 8'hAA; // Load and latch a value ctl_db_pin_re = 1; // Read into the latch `T dpin_w = 'z; db_w = 8'h55; ctl_db_pin_re = 0; ctl_db_we = 1; `CHECKD(8'hAA); `T db_w = 'z; `T $display("End of test"); end //-------------------------------------------------------------- // Instantiate bus block and assign identical nets and variables //-------------------------------------------------------------- address_pins address_pins_inst( .*, .bus_ab_pin_we(ctl_ab_we), .address(ab[15:0]), .abus(apin[15:0]) ); data_pins data_pins_inst( .*, .ctl_bus_db_oe(ctl_db_pin_oe), .ctl_bus_db_we(ctl_db_we), .bus_db_pin_oe(ctl_db_pin_oe), .bus_db_pin_re(ctl_db_pin_re), .D(dpin[7:0]) ); endmodule ================================================ FILE: cpu/control/Timings.csv ================================================ A-Z80 Timing Table M_ T_ Function valid nextM setM1 A:reg rd A:reg wr inc/dec A:latch D:reg rd D:reg wr Reg gate SW2 SW1 DB pads FLAGT ALU ALU bus op2 latch op1 latch nibble operation SZ XY HF PF NF CF CF2 Special Comments // 8-bit Load Group "#if pla[17] & ~pla[50] : ld r,n" "4,3" #001H T1 AB:000 DB:-- M1 1 1 fMFetch r8 < d < R #002H T2 AB:000 DB:46 M1 MREQ RD 1 2 fMFetch #003H T3 AB:000 DB:-- RFSH 1 3 fMFetch #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr #005H T5 AB:001 DB:-- 2 1 fMRead PC W #006H T6 AB:001 DB:01 MREQ RD 2 2 fMRead PC + R #007H T7 AB:001 DB:01 MREQ RD 2 3 fMRead Y #end "#if pla[61] & ~pla[58] & ~pla[59] : ld r,r'" 4 #001H T1 AB:000 DB:-- M1 1 1 fMFetch r8 < u < op1 #002H T2 AB:000 DB:05 M1 MREQ RD 1 2 fMFetch #003H T3 AB:000 DB:-- RFSH 1 3 fMFetch #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y Y r8 >r8 - >s0 bus #end "#if use_ixiy & pla[58] : ld r,(ix+d)" "4,3,5,3" #005H T1 AB:001 DB:-- M1 1 1 fMFetch r8 < d < R #006H T2 AB:001 DB:4E M1 MREQ RD 1 2 fMFetch #007H T3 AB:001 DB:-- RFSH 1 3 fMFetch #008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y mr #009H T5 AB:002 DB:-- 2 1 fMRead PC W #010H T6 AB:002 DB:01 MREQ RD 2 2 fMRead PC + R #011H T7 AB:002 DB:01 MREQ RD 2 3 fMRead Y #012H T8 AB:002 DB:-- 3 1 WZ=IX+d #013H T9 AB:002 DB:-- 3 2 WZ=IX+d #014H T10 AB:002 DB:-- 3 3 WZ=IX+d #015H T11 AB:002 DB:-- 3 4 WZ=IX+d #016H T12 AB:002 DB:-- 3 5 mr WZ=IX+d Clears the IX/IY and ... #end "#if ~use_ixiy & pla[58] : ld r,(hl)" "4,3" #001H T1 AB:000 DB:-- M1 1 1 fMFetch r8 < d < R #002H T2 AB:000 DB:46 M1 MREQ RD 1 2 fMFetch #003H T3 AB:000 DB:-- RFSH 1 3 fMFetch #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr #005H T5 AB:003 DB:-- 2 1 fMRead HL W #006H T6 AB:003 DB:03 MREQ RD 2 2 fMRead #007H T7 AB:003 DB:03 MREQ RD 2 3 fMRead Y #017H T13 AB:001 DB:-- 4 1 fMRead R ...continues here #018H T14 AB:001 DB:4E MREQ RD 4 2 fMRead #019H T15 AB:001 DB:4E MREQ RD 4 3 fMRead Y #end "#if use_ixiy & pla[59] : ld (ix+d),r" "4,3,5,3" #005H T1 AB:001 DB:-- M1 1 1 fMFetch #006H T2 AB:001 DB:70 M1 MREQ RD 1 2 fMFetch #007H T3 AB:001 DB:-- RFSH 1 3 fMFetch #008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y mr #009H T5 AB:002 DB:-- 2 1 fMRead PC W #010H T6 AB:002 DB:01 MREQ RD 2 2 fMRead PC + R #011H T7 AB:002 DB:01 MREQ RD 2 3 fMRead Y #012H T8 AB:002 DB:-- 3 1 WZ=IX+d #013H T9 AB:002 DB:-- 3 2 WZ=IX+d #014H T10 AB:002 DB:-- 3 3 WZ=IX+d #015H T11 AB:002 DB:-- 3 4 WZ=IX+d #016H T12 AB:002 DB:-- 3 5 mw WZ=IX+d Clears the IX/IY and ... #end "#if ~use_ixiy & pla[59] : ld (hl),r" "4,3" #001H T1 AB:000 DB:-- M1 1 1 fMFetch #002H T2 AB:000 DB:70 M1 MREQ RD 1 2 fMFetch #003H T3 AB:000 DB:-- RFSH 1 3 fMFetch #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mw r8 >r8 - > W #005H T5 AB:001 DB:-- 2 1 fMWrite HL W #006H T6 AB:001 DB:01 MREQ 2 2 fMWrite #007H T7 AB:001 DB:01 MREQ WR 2 3 fMWrite Y #017H T13 AB:000 DB:-- 4 1 fMWrite R r8 >r8 - > W ...continues here #018H T14 AB:000 DB:46 MREQ 4 2 fMWrite #019H T15 AB:000 DB:46 MREQ WR 4 3 fMWrite Y #end "#if pla[40] : ld (ix+d),n" "4,3,5,3" #005H T1 AB:001 DB:-- M1 1 1 fMFetch #006H T2 AB:001 DB:36 M1 MREQ RD 1 2 fMFetch #007H T3 AB:001 DB:-- RFSH 1 3 fMFetch #008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y mr #009H T5 AB:002 DB:-- 2 1 fMRead PC W #010H T6 AB:002 DB:01 MREQ RD 2 2 fMRead PC + R #011H T7 AB:002 DB:01 MREQ RD 2 3 fMRead mr #012H T8 AB:003 DB:-- 3 1 fMRead PC W WZ=IX+d #013H T9 AB:003 DB:02 MREQ RD 3 2 fMRead PC + R WZ=IX+d #014H T10 AB:003 DB:02 MREQ RD 3 3 fMRead WZ=IX+d "Reads ""n"" at the same time" #015H T11 AB:003 DB:-- 3 4 WZ=IX+d #016H T12 AB:003 DB:-- 3 5 mw WZ=IX+d Clears the IX/IY and ... #end "#if pla[50] & ~pla[40] : ld (hl),n" "4,3,3" #001H T1 AB:000 DB:-- M1 1 1 fMFetch #002H T2 AB:000 DB:36 M1 MREQ RD 1 2 fMFetch #003H T3 AB:000 DB:-- RFSH 1 3 fMFetch #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr #005H T5 AB:001 DB:-- 2 1 fMRead PC W #006H T6 AB:001 DB:01 MREQ RD 2 2 fMRead PC + R #007H T7 AB:001 DB:01 MREQ RD 2 3 fMRead mw #008H T8 AB:001 DB:-- 3 1 fMWrite HL W #009H T9 AB:001 DB:01 MREQ 3 2 fMWrite #010H T10 AB:001 DB:01 MREQ WR 3 3 fMWrite Y #017H T13 AB:002 DB:-- 4 1 fMWrite R ...continues here #018H T14 AB:002 DB:02 MREQ 4 2 fMWrite #019H T15 AB:002 DB:02 MREQ WR 4 3 fMWrite Y #end "#if pla[8] & pla[13] : ld (rr),a" "4,3" #001H T1 AB:000 DB:-- M1 1 1 fMFetch #002H T2 AB:000 DB:02 M1 MREQ RD 1 2 fMFetch #003H T3 AB:000 DB:-- RFSH 1 3 fMFetch #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mw A >h u > W #005H T5 AB:001 DB:-- 2 1 fMWrite r16 W #006H T6 AB:001 DB:FF MREQ 2 2 fMWrite WZ + R #007H T7 AB:001 DB:FF MREQ WR 2 3 fMWrite Y #end "#if pla[8] & ~pla[13] : ld a,(rr)" "4,3" #001H T1 AB:000 DB:-- M1 1 1 fMFetch A < d < R #002H T2 AB:000 DB:0A M1 MREQ RD 1 2 fMFetch #003H T3 AB:000 DB:-- RFSH 1 3 fMFetch #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr #005H T5 AB:002 DB:-- 2 1 fMRead r16 W #006H T6 AB:002 DB:02 MREQ RD 2 2 fMRead WZ + R #007H T7 AB:002 DB:02 MREQ RD 2 3 fMRead Y #end "#if pla[38] & pla[13] : ld (nn),a" "4,3,3,3" #001H T1 AB:000 DB:-- M1 1 1 fMFetch #002H T2 AB:000 DB:32 M1 MREQ RD 1 2 fMFetch #003H T3 AB:000 DB:-- RFSH 1 3 fMFetch #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr #005H T5 AB:001 DB:-- 2 1 fMRead PC W #006H T6 AB:001 DB:01 MREQ RD 2 2 fMRead PC + R #007H T7 AB:001 DB:01 MREQ RD 2 3 fMRead mr Z h u > W #012H T12 AB:001 DB:FE MREQ 4 2 fMWrite WZ + R #013H T13 AB:001 DB:FE MREQ WR 4 3 fMWrite Y #end "#if pla[38] & ~pla[13] : ld a,(nn)" "4,3,3,3" #001H T1 AB:000 DB:-- M1 1 1 fMFetch A < d < R #002H T2 AB:000 DB:3A M1 MREQ RD 1 2 fMFetch #003H T3 AB:000 DB:-- RFSH 1 3 fMFetch #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr #005H T5 AB:001 DB:-- 2 1 fMRead PC W #006H T6 AB:001 DB:01 MREQ RD 2 2 fMRead PC + R #007H T7 AB:001 DB:01 MREQ RD 2 3 fMRead mr Z > >s0 bus bus * * * * * * #008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y I/R >r8' - alu >s0 bus bus L OR * * * 0 #009H T5 AB:001 DB:-- 1 5 Y #end "#if pla[57] : ld i,a/r,a" 5 #005H T1 AB:001 DB:-- M1 1 1 fMFetch #006H T2 AB:001 DB:47 M1 MREQ RD 1 2 fMFetch #007H T3 AB:001 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * * #008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y I/R < u < op1 #009H T5 AB:001 DB:-- 1 5 Y #end // 16-bit Load Group "#if pla[7] : ld rr,nn" "4,3,3" #001H T1 AB:000 DB:-- M1 1 1 fMFetch rh < d < R USE_SP #002H T2 AB:000 DB:01 M1 MREQ RD 1 2 fMFetch #003H T3 AB:000 DB:-- RFSH 1 3 fMFetch #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr #005H T5 AB:001 DB:-- 2 1 fMRead PC W #006H T6 AB:001 DB:01 MREQ RD 2 2 fMRead PC + R #007H T7 AB:001 DB:01 MREQ RD 2 3 fMRead mr #008H T8 AB:002 DB:-- 3 1 fMRead PC W rl < d < R USE_SP #009H T9 AB:002 DB:02 MREQ RD 3 2 fMRead PC + R #010H T10 AB:002 DB:02 MREQ RD 3 3 fMRead Y #end "#if pla[30] & pla[13] : ld (nn),hl" "4,3,3,3,3" #001H T1 AB:000 DB:-- M1 1 1 fMFetch #002H T2 AB:000 DB:22 M1 MREQ RD 1 2 fMFetch #003H T3 AB:000 DB:-- RFSH 1 3 fMFetch #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr #005H T5 AB:001 DB:-- 2 1 fMRead PC W #006H T6 AB:001 DB:01 MREQ RD 2 2 fMRead PC + R #007H T7 AB:001 DB:01 MREQ RD 2 3 fMRead mr Z l > W #012H T12 AB:001 DB:01 MREQ 4 2 fMWrite WZ + R #013H T13 AB:001 DB:01 MREQ WR 4 3 fMWrite mw WZ W #014H T14 AB:002 DB:-- 5 1 fMWrite R rh >h u > W #015H T15 AB:002 DB:02 MREQ 5 2 fMWrite WZ + R #016H T16 AB:002 DB:02 MREQ WR 5 3 fMWrite Y #end "#if pla[30] & ~pla[13] : ld hl,(nn)" "4,3,3,3,3" #001H T1 AB:000 DB:-- M1 1 1 fMFetch #002H T2 AB:000 DB:2A M1 MREQ RD 1 2 fMFetch #003H T3 AB:000 DB:-- RFSH 1 3 fMFetch #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr #005H T5 AB:001 DB:-- 2 1 fMRead PC W #006H T6 AB:001 DB:01 MREQ RD 2 2 fMRead PC + R #007H T7 AB:001 DB:01 MREQ RD 2 3 fMRead mr Z l > W USE_SP #016H T12 AB:001 DB:FF MREQ 4 2 fMWrite WZ + R #017H T13 AB:001 DB:FF MREQ WR 4 3 fMWrite mw WZ W #018H T14 AB:002 DB:-- 5 1 fMWrite R rh >h u > W USE_SP #019H T15 AB:002 DB:C3 MREQ 5 2 fMWrite WZ + R #020H T16 AB:002 DB:C3 MREQ WR 5 3 fMWrite Y #end "#if pla[31] & ~pla[33] : ld rr,(nn)" "4,3,3,3,3" #005H T1 AB:001 DB:-- M1 1 1 fMFetch #006H T2 AB:001 DB:43 M1 MREQ RD 1 2 fMFetch #007H T3 AB:001 DB:-- RFSH 1 3 fMFetch #008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y mr #009H T5 AB:002 DB:-- 2 1 fMRead PC W #010H T6 AB:002 DB:01 MREQ RD 2 2 fMRead PC + R #011H T7 AB:002 DB:01 MREQ RD 2 3 fMRead mr Z h u > W #007H T7 AB:002 DB:02 MREQ 2 2 fMWrite SP - R #008H T8 AB:002 DB:02 MREQ WR 2 3 fMWrite mw SP - W #009H T9 AB:001 DB:-- 3 1 fMWrite - P rl >l > W #010H T10 AB:001 DB:01 MREQ 3 2 fMWrite SP - R #011H T11 AB:001 DB:01 MREQ WR 3 3 fMWrite Y #end #if pla[23] & ~pla[16] : pop qq "4,3,3" #001H T1 AB:000 DB:-- M1 1 1 fMFetch #002H T2 AB:000 DB:C1 M1 MREQ RD 1 2 fMFetch #003H T3 AB:000 DB:-- RFSH 1 3 fMFetch #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr #005H T5 AB:001 DB:-- 2 1 fMRead SP W #006H T6 AB:001 DB:01 MREQ RD 2 2 fMRead SP + R #007H T7 AB:001 DB:01 MREQ RD 2 3 fMRead mr rl < d < R #008H T8 AB:002 DB:-- 3 1 fMRead SP W #009H T9 AB:002 DB:02 MREQ RD 3 2 fMRead SP + R #010H T10 AB:002 DB:02 MREQ RD 3 3 fMRead Y rh < d < R #end "// Exchange, Block Transfer and Search Groups" "#if pla[2] : ex de,hl" 4 #001H T1 AB:000 DB:-- M1 1 1 fMFetch #002H T2 AB:000 DB:EB M1 MREQ RD 1 2 fMFetch Ex_DE_HL #003H T3 AB:000 DB:-- RFSH 1 3 fMFetch #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y Y #end "#if pla[39] : ex af,af'" 4 #001H T1 AB:000 DB:-- M1 1 1 fMFetch #002H T2 AB:000 DB:08 M1 MREQ RD 1 2 fMFetch Ex_AF_AF' #003H T3 AB:000 DB:-- RFSH 1 3 fMFetch #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y Y #end #if pla[1] : exx 4 #001H T1 AB:000 DB:-- M1 1 1 fMFetch #002H T2 AB:000 DB:D9 M1 MREQ RD 1 2 fMFetch EXX #003H T3 AB:000 DB:-- RFSH 1 3 fMFetch #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y Y #end "#if pla[10] : ex (sp),hl" "4,3,4,3,5" #001H T1 AB:000 DB:-- M1 1 1 fMFetch #002H T2 AB:000 DB:E3 M1 MREQ RD 1 2 fMFetch #003H T3 AB:000 DB:-- RFSH 1 3 fMFetch #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr #005H T5 AB:0FD DB:-- 2 1 fMRead SP W #006H T6 AB:0FD DB:03 MREQ RD 2 2 fMRead SP + R #007H T7 AB:0FD DB:03 MREQ RD 2 3 fMRead mr Z h u > W #013H T13 AB:0FE DB:00 MREQ 4 2 fMWrite SP - R #014H T14 AB:0FE DB:00 MREQ WR 4 3 fMWrite mw SP - W #015H T15 AB:0FD DB:-- 5 1 fMWrite - P rl >l > W #016H T16 AB:0FD DB:01 MREQ 5 2 fMWrite SP - R #017H T17 AB:0FD DB:01 MREQ WR 5 3 fMWrite WZ W #018H T18 AB:0FD DB:01 5 4 HL R #019H T19 AB:0FD DB:01 5 5 Y #end #if pla[0] : Non-repeating version of a block instruction "4,3,5,(5)" #always NonRep #end #if pla[12] : ldi/ldir/ldd/lddr "4,3,5,(5)" #035H T1 AB:00A DB:-- M1 1 1 fMFetch alu res H OR * * REP 0 R #036H T2 AB:00A DB:B0 M1 MREQ RD 1 2 fMFetch F < < #037H T3 AB:004 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * * #038H T4 AB:004 DB:-- RFSH MREQ 1 4 fMFetch Y mr #039H T5 AB:000 DB:-- 2 1 fMRead HL W #040H T6 AB:000 DB:21 MREQ RD 2 2 fMRead HL op3 R #041H T7 AB:000 DB:21 MREQ RD 2 3 fMRead mw d < R alu >s0 bus L ADD * W #042H T8 AB:000 DB:-- 3 1 fMWrite DE W alu < res H ADD R #043H T9 AB:000 DB:21 MREQ 3 2 fMWrite DE op3 R #044H T10 AB:000 DB:21 MREQ WR 3 3 fMWrite BC W #045H T11 AB:000 DB:21 3 4 BC - R WriteBC=1 Update repeat flag latch #046H T12 AB:000 DB:21 3 5 Y BR #047H T13 AB:000 DB:-- 4 1 PC W #048H T14 AB:000 DB:-- 4 2 PC - R #049H T15 AB:000 DB:-- 4 3 PC W #050H T16 AB:000 DB:-- 4 4 PC - R #051H T17 AB:000 DB:-- 4 5 Y #end #if pla[11] : cpi/cpir/cpd/cpdr "4,3,5,(5)" #035H T1 AB:00A DB:-- M1 1 1 fMFetch alu < res 0 H SUB * REP 1 R #036H T2 AB:00A DB:B1 M1 MREQ RD 1 2 fMFetch F < < ?NF_HF #037H T3 AB:004 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * * #038H T4 AB:004 DB:-- RFSH MREQ 1 4 fMFetch Y mr #039H T5 AB:000 DB:-- 2 1 fMRead HL W #040H T6 AB:000 DB:21 MREQ RD 2 2 fMRead HL op3 R #041H T7 AB:000 DB:21 MREQ RD 2 3 fMRead Y d < R alu >s0 bus L SUB * W #042H T8 AB:000 DB:-- 3 1 alu < res H SUB * R #043H T9 AB:000 DB:-- 3 2 #044H T10 AB:000 DB:-- 3 3 BC W #045H T11 AB:000 DB:-- 3 4 BC - R WriteBC=1 Update repeat flag latch #046H T12 AB:000 DB:-- 3 5 Y BRZ #047H T13 AB:000 DB:-- 4 1 PC W #048H T14 AB:000 DB:-- 4 2 PC - R #049H T15 AB:000 DB:-- 4 3 PC W #050H T16 AB:000 DB:-- 4 4 PC - R #051H T17 AB:000 DB:-- 4 5 Y #end // 8-bit Arithmetic and Logic Group "#if pla[65] & ~pla[52] : add/sub/and/or/xor/cmp a,r" 4 #001H T1 AB:000 DB:-- M1 1 1 fMFetch ? < u alu < res H PLA * ? ? ? * A is stored in each ALU PLA below #002H T2 AB:000 DB:80 M1 MREQ RD 1 2 fMFetch F < < PLA ?NF_HF_CF "If (NF), complement HF, CF" #003H T3 AB:000 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * * #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y Y r8 >r8 - alu >s0 bus L PLA * * * ? #end "#if pla[64] : add/sub/and/or/xor/cmp a,n" "4,3" #001H T1 AB:000 DB:-- M1 1 1 fMFetch ? < u alu < res H PLA * ? ? ? * A is stored in each ALU PLA below #002H T2 AB:000 DB:C6 M1 MREQ RD 1 2 fMFetch F < < PLA ?NF_HF_CF "If (NF), complement HF, CF" #003H T3 AB:000 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * * #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr r8 >r8 - alu >s0 bus L PLA * * * ? #005H T5 AB:001 DB:-- 2 1 fMRead PC W PLA #006H T6 AB:001 DB:01 MREQ RD 2 2 fMRead PC + R #007H T7 AB:001 DB:01 MREQ RD 2 3 fMRead Y d < R alu >s0 bus L PLA * * * ? #end #if use_ixiy & pla[52] : add/sub/and/or/xor/cp (ix+d) "4,3,5,3" #005H T1 AB:001 DB:-- M1 1 1 fMFetch #006H T2 AB:001 DB:86 M1 MREQ RD 1 2 fMFetch #007H T3 AB:001 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * * #008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y mr #009H T5 AB:002 DB:-- 2 1 fMRead PC W #010H T6 AB:002 DB:01 MREQ RD 2 2 fMRead PC + R #011H T7 AB:002 DB:01 MREQ RD 2 3 fMRead Y #012H T8 AB:002 DB:-- 3 1 WZ=IX+d #013H T9 AB:002 DB:-- 3 2 WZ=IX+d #014H T10 AB:002 DB:-- 3 3 WZ=IX+d "Reads ""n"" at the same time" #015H T11 AB:002 DB:-- 3 4 WZ=IX+d #016H T12 AB:002 DB:-- 3 5 mr WZ=IX+d Clears the IX/IY and ... #end #if ~use_ixiy & pla[52] : add/sub/and/or/xor/cp (hl) "4,3" #001H T1 AB:000 DB:-- M1 1 1 fMFetch ? < u alu < res H PLA * ? ? ? * A is stored in each ALU PLA below #002H T2 AB:000 DB:86 M1 MREQ RD 1 2 fMFetch F < < PLA ?NF_HF_CF "If (NF), complement HF, CF" #003H T3 AB:000 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * * #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr #005H T5 AB:001 DB:-- 2 1 fMRead HL W #006H T6 AB:001 DB:01 MREQ RD 2 2 fMRead WZ + R #007H T7 AB:001 DB:01 MREQ RD 2 3 fMRead Y d < R alu >s0 bus L PLA * * * ? #017H T13 AB:000 DB:-- 4 1 fMRead R ...continues here #018H T14 AB:000 DB:DD MREQ RD 4 2 fMRead AF > > >s0 bus bus * * * * * Reloads AF since (IX+d) used ALU core #019H T15 AB:000 DB:DD MREQ RD 4 3 fMRead Y d < R alu >s0 bus L PLA * * * ? #end #if pla[66] & ~pla[53] : inc/dec r 4 #001H T1 AB:000 DB:-- M1 1 1 fMFetch r8 < u alu < res H ADC * * V R #002H T2 AB:000 DB:05 M1 MREQ RD 1 2 fMFetch F < < ?NF_HF "If (NF), complement HF" #003H T3 AB:000 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * * #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y Y r8' >r8' - alu >s0 0 bus L ADC * * * 0 1 W #end #if pla[75] : dec #001H T1 AB:000 DB:-- M1 1 1 fMFetch 1 0 NEG_OP2 #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch 1 0 NEG_OP2 #end #if (M2 | M4) & pla[75] : dec #always 1 0 NEG_OP2 #end #if use_ixiy & pla[53] : inc/dec (ix+d) "4,3,5,4,3" #005H T1 AB:001 DB:-- M1 1 1 fMFetch #006H T2 AB:001 DB:34 M1 MREQ RD 1 2 fMFetch #007H T3 AB:001 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * * #008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y mr #009H T5 AB:002 DB:-- 2 1 fMRead PC W #010H T6 AB:002 DB:01 MREQ RD 2 2 fMRead PC + R #011H T7 AB:002 DB:01 MREQ RD 2 3 fMRead Y #012H T8 AB:002 DB:-- 3 1 WZ=IX+d #013H T9 AB:002 DB:-- 3 2 WZ=IX+d #014H T10 AB:002 DB:-- 3 3 WZ=IX+d #015H T11 AB:002 DB:-- 3 4 WZ=IX+d #016H T12 AB:002 DB:-- 3 5 mr WZ=IX+d Clears the IX/IY and ... #end #if ~use_ixiy & pla[53] : inc/dec (hl) "4,4,3" #001H T1 AB:000 DB:-- M1 1 1 fMFetch #002H T2 AB:000 DB:34 M1 MREQ RD 1 2 fMFetch F < < ?NF_HF "If (NF), complement HF" #003H T3 AB:000 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * * #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr #005H T5 AB:001 DB:-- 2 1 fMRead HL W #006H T6 AB:001 DB:01 MREQ RD 2 2 fMRead #007H T7 AB:001 DB:01 MREQ RD 2 3 fMRead d < R alu >s0 0 bus L ADC * 0 1 W #008H T8 AB:001 DB:-- 2 4 mw u > W alu < res H ADC * * V R #009H T9 AB:001 DB:-- 3 1 fMWrite R #010H T10 AB:001 DB:02 MREQ 3 2 fMWrite #011H T11 AB:001 DB:02 MREQ WR 3 3 fMWrite Y #017H T13 AB:002 DB:-- 4 1 fMRead R ...continues here #018H T14 AB:002 DB:01 MREQ RD 4 2 fMRead #019H T15 AB:002 DB:01 MREQ RD 4 3 fMRead d < R alu >s0 0 bus L ADC * 0 1 W #020H T16 AB:002 DB:-- 4 4 mw u > W alu < res H ADC * * V R #021H T17 AB:002 DB:-- 5 1 fMWrite R #022H T18 AB:002 DB:02 MREQ 5 2 fMWrite #023H T19 AB:002 DB:02 MREQ WR 5 3 fMWrite Y #end // 16-bit Arithmetic Group "#if pla[69] : add hl,ss" "4,4,3" #001H T1 AB:000 DB:-- M1 1 1 fMFetch #002H T2 AB:000 DB:09 M1 MREQ RD 1 2 fMFetch F < < #003H T3 AB:000 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * 0 * #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y Y L >l d >s0 bus #005H T5 AB:000 DB:-- 2 1 rl >l d alu >s0 bus L ADD * USE_SP #006H T6 AB:000 DB:-- 2 2 Z >s0 bus #008H T8 AB:000 DB:-- 2 4 Y rh > alu >s0 bus L ADC * USE_SP #009H T9 AB:000 DB:-- 3 1 WZ W W > >s0 bus bus * * * * 0 * #008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y Y L >l d >s0 bus #009H T5 AB:001 DB:-- 2 1 rl >l d alu >s0 bus L ADC * USE_SP #010H T6 AB:001 DB:-- 2 2 Z >s0 bus #012H T8 AB:001 DB:-- 2 4 Y rh > alu >s0 bus L ADC * USE_SP #013H T9 AB:001 DB:-- 3 1 WZ W W > >s0 bus bus * * * * 1 * #008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y Y L >l d >s0 bus #009H T5 AB:001 DB:-- 2 1 rl >l d alu >s0 bus L SBC * USE_SP #010H T6 AB:001 DB:-- 2 2 Z >s0 bus #012H T8 AB:001 DB:-- 2 4 Y rh > alu >s0 bus L SBCh * USE_SP #013H T9 AB:001 DB:-- 3 1 WZ W W > >s0 bus bus * * W2 * * * "Only for DAA, write HF2 flag" #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y Y d alu >s0 bus L ADC * * * 1 W.daa "DAA,?NF_SUB" #end #if pla[81] : cpl 4 #001H T1 AB:000 DB:-- M1 1 1 fMFetch A < alu < res H OR * 1 NEG_OP2 #002H T2 AB:000 DB:2F M1 MREQ RD 1 2 fMFetch F < < ?NF_HF #003H T3 AB:000 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * * #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y Y alu 0 L OR * * 1 NEG_OP2 #end #if pla[82] : neg 4 #005H T1 AB:001 DB:-- M1 1 1 fMFetch A < alu < res H SUB * * V 1 * #006H T2 AB:001 DB:44 M1 MREQ RD 1 2 fMFetch F < < ?NF_HF_CF #007H T3 AB:001 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * * #008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y Y alu 0 L SUB * * * 1 * #end #if pla[89] : ccf 4 #001H T1 AB:000 DB:-- M1 1 1 fMFetch alu < res H OR * 0 #002H T2 AB:000 DB:3F M1 MREQ RD 1 2 fMFetch F < < ^ ?~CF_HF #003H T3 AB:000 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * * #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y Y alu L OR * * 0 #end #if pla[92] : scf 4 #001H T1 AB:000 DB:-- M1 1 1 fMFetch alu < res H OR * 0 #002H T2 AB:000 DB:37 M1 MREQ RD 1 2 fMFetch F < < 1 #003H T3 AB:000 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * * #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y Y alu L OR * * 0 #end #if pla[95] : halt 4 #001H T1 AB:000 DB:-- M1 1 1 fMFetch #002H T2 AB:000 DB:76 M1 MREQ RD 1 2 fMFetch #003H T3 AB:000 DB:-- RFSH 1 3 fMFetch HALT #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y Y #end #if pla[97] : di/ei 4 #001H T1 AB:000 DB:-- M1 1 1 fMFetch #002H T2 AB:000 DB:F3 M1 MREQ RD 1 2 fMFetch #003H T3 AB:000 DB:-- RFSH 1 3 fMFetch DI_EI #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y Y NO_INTS "At last M/T, inhibit interrupts" #end #if pla[96] : im n 4 #005H T1 AB:001 DB:-- M1 1 1 fMFetch #006H T2 AB:001 DB:46 M1 MREQ RD 1 2 fMFetch #007H T3 AB:001 DB:-- RFSH 1 3 fMFetch < R IM M1/T3 reads in mode # from opcode[4:3] #008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y Y #end // Rotate and Shift Group #if pla[25] : rlca/rla/rrca/rra 4 #001H T1 AB:000 DB:-- M1 1 1 fMFetch A < alu < res H OR * * 0 * #002H T2 AB:000 DB:07 M1 MREQ RD 1 2 fMFetch F < < R #003H T3 AB:000 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * * #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y Y A > alu >s1 bus bus L OR * * 0 W.sh #end #if ~use_ixiy & pla[70] & ~pla[55] : rlc r 4 #005H T1 AB:001 DB:-- M1 1 1 fMFetch r8' < u alu < res H OR * * * P 0 * #006H T2 AB:001 DB:00 M1 MREQ RD 1 2 fMFetch F < < R #007H T3 AB:001 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * * #008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y Y r8 >r8 - alu >s1 bus bus L OR * * * 0 W.sh #017H T13 AB:000 DB:-- 4 1 fMRead WZ W R OpcodeToIR ...continues here from the (ix+d) addressing mode #018H T14 AB:000 DB:DD MREQ RD 4 2 fMRead #019H T15 AB:000 DB:DD MREQ RD 4 3 fMRead mw d < R alu >s1 bus bus L OR 0 W.sh #029H T17 AB:002 DB:-- 5 1 fMWrite R u > W alu < res H OR * * * P 0 * #030H T18 AB:002 DB:BB MREQ 5 2 fMWrite #031H T19 AB:002 DB:BB MREQ WR 5 3 fMWrite Y #end #if ~use_ixiy & pla[70] & pla[55] : rlc (hl) "4,4,3" #005H T1 AB:001 DB:-- M1 1 1 fMFetch #006H T2 AB:001 DB:00 M1 MREQ RD 1 2 fMFetch F < < R #007H T3 AB:001 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * * #008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y mr #009H T5 AB:006 DB:-- 2 1 fMRead HL W #010H T6 AB:006 DB:05 MREQ RD 2 2 fMRead #011H T7 AB:006 DB:05 MREQ RD 2 3 fMRead #012H T8 AB:006 DB:-- 2 4 mw d < R alu >s1 bus bus L OR 0 W.sh #013H T9 AB:006 DB:-- 3 1 fMWrite R u > W alu < res H OR * * * P 0 * #014H T10 AB:006 DB:0A MREQ 3 2 fMWrite #015H T11 AB:006 DB:0A MREQ WR 3 3 fMWrite Y #017H T13 AB:000 DB:-- 4 1 fMRead WZ W R OpcodeToIR ...continues here from the (ix+d) addressing mode #018H T14 AB:000 DB:DD MREQ RD 4 2 fMRead #019H T15 AB:000 DB:DD MREQ RD 4 3 fMRead mw d < R alu >s1 bus bus L OR 0 W.sh #029H T17 AB:002 DB:-- 5 1 fMWrite R u > W alu < res H OR * * * P 0 * #030H T18 AB:002 DB:BB MREQ 5 2 fMWrite #031H T19 AB:002 DB:BB MREQ WR 5 3 fMWrite Y #end #if pla[15] & op3 : rld "4,3,4,3" #005H T1 AB:001 DB:-- M1 1 1 fMFetch A < alu < res H OR * * P 0 #006H T2 AB:001 DB:67 M1 MREQ RD 1 2 fMFetch F < < #007H T3 AB:001 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * * #008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y mr #009H T5 AB:000 DB:-- 2 1 fMRead HL W #010H T6 AB:000 DB:ED MREQ RD 2 2 fMRead WZ + R #011H T7 AB:000 DB:ED MREQ RD 2 3 fMRead Y #012H T8 AB:000 DB:-- 3 1 d < R >s0 lq L #013H T9 AB:000 DB:-- 3 2 #014H T10 AB:000 DB:-- 3 3 #015H T11 AB:000 DB:-- 3 4 mw d < R >s0 low H #016H T12 AB:000 DB:-- 4 1 fMWrite R u > W < op2 #017H T13 AB:000 DB:EE MREQ 4 2 fMWrite op1 bus #018H T14 AB:000 DB:EE MREQ WR 4 3 fMWrite Y alu L OR * * * 0 #end #if pla[15] & ~op3 : rrd "4,3,4,3" #005H T1 AB:001 DB:-- M1 1 1 fMFetch A < alu < res H OR * * P 0 #006H T2 AB:001 DB:67 M1 MREQ RD 1 2 fMFetch F < < #007H T3 AB:001 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * * #008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y mr #009H T5 AB:000 DB:-- 2 1 fMRead HL W #010H T6 AB:000 DB:ED MREQ RD 2 2 fMRead WZ + R #011H T7 AB:000 DB:ED MREQ RD 2 3 fMRead Y #012H T8 AB:000 DB:-- 3 1 d < R >s0 lq low L #013H T9 AB:000 DB:-- 3 2 u > W < op2 #014H T10 AB:000 DB:-- 3 3 A > >s0 lq L #015H T11 AB:000 DB:-- 3 4 mw d < R >s0 low H #016H T12 AB:000 DB:-- 4 1 fMWrite R u > W < op2 #017H T13 AB:000 DB:EE MREQ 4 2 fMWrite op1 bus #018H T14 AB:000 DB:EE MREQ WR 4 3 fMWrite Y alu L OR * * * 0 #end // Bit Manipulation Group "#if ~use_ixiy & pla[72] & ~pla[55] : bit b,r" 4 #005H T1 AB:001 DB:-- M1 1 1 fMFetch alu < res H AND * * P 0 #006H T2 AB:001 DB:40 M1 MREQ RD 1 2 fMFetch F < < #007H T3 AB:001 DB:-- RFSH 1 3 fMFetch AF > R > >bs bus bus * * * * * * Override M1/T3 load with a bit select #008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y Y r8 >r8 - alu >s0 bus L AND * * * 0 #017H T13 AB:000 DB:-- 4 1 fMRead R R >bs bus bus OpcodeToIR ...continues here from the (ix+d) addressing mode #018H T14 AB:000 DB:DD MREQ RD 4 2 fMRead #019H T15 AB:000 DB:DD MREQ RD 4 3 fMRead #020H T16 AB:000 DB:-- 4 4 Y d < R alu >s0 bus L AND * * 0 #end "#if ~use_ixiy & pla[72] & pla[55] : bit b,(hl)" "4,4" #005H T1 AB:001 DB:-- M1 1 1 fMFetch alu < res H AND * * P 0 #006H T2 AB:001 DB:06 M1 MREQ RD 1 2 fMFetch F < < #007H T3 AB:001 DB:-- RFSH 1 3 fMFetch AF > R > >bs bus bus * * * * * * Override M1/T3 load with a bit select #008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y mr #009H T5 AB:006 DB:-- 2 1 fMRead HL W #010H T6 AB:006 DB:05 MREQ RD 2 2 fMRead #011H T7 AB:006 DB:05 MREQ RD 2 3 fMRead WZ > > * "BIT n,(HL) saves WZ in X,Y (""MEMPTR"")" #012H T8 AB:006 DB:-- 2 4 Y d < R alu >s0 bus L AND * * 0 #017H T13 AB:000 DB:-- 4 1 fMRead WZ W R >bs bus bus OpcodeToIR ...continues here from the (ix+d) addressing mode #018H T14 AB:000 DB:DD MREQ RD 4 2 fMRead #019H T15 AB:000 DB:DD MREQ RD 4 3 fMRead #020H T16 AB:000 DB:-- 4 4 Y d < R alu >s0 bus L AND * * 0 #end "#if ~use_ixiy & pla[74] & ~pla[55] : set b,r" 4 #005H T1 AB:001 DB:-- M1 1 1 fMFetch r8' < u < res H OR #006H T2 AB:001 DB:40 M1 MREQ RD 1 2 fMFetch #007H T3 AB:001 DB:-- RFSH 1 3 fMFetch AF > R > >bs bus bus * * * * * * Override M1/T3 load with a bit select #008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y Y r8 >r8 - >s0 bus L OR #017H T13 AB:000 DB:-- 4 1 fMRead WZ W R >bs bus bus OpcodeToIR ...continues here from the (ix+d) addressing mode #018H T14 AB:000 DB:DD MREQ RD 4 2 fMRead #019H T15 AB:000 DB:DD MREQ RD 4 3 fMRead mw d < R alu >s0 bus L OR #029H T17 AB:002 DB:-- 5 1 fMWrite R u > W < res H OR #030H T18 AB:002 DB:BB MREQ 5 2 fMWrite #031H T19 AB:002 DB:BB MREQ WR 5 3 fMWrite Y #end "#if ~use_ixiy & pla[74] & pla[55] : set b,(hl)" "4,4,3" #005H T1 AB:001 DB:-- M1 1 1 fMFetch #006H T2 AB:001 DB:06 M1 MREQ RD 1 2 fMFetch #007H T3 AB:001 DB:-- RFSH 1 3 fMFetch AF > R > >bs bus bus * * * * * * Override M1/T3 load with a bit select #008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y mr #009H T5 AB:006 DB:-- 2 1 fMRead HL W #010H T6 AB:006 DB:05 MREQ RD 2 2 fMRead #011H T7 AB:006 DB:05 MREQ RD 2 3 fMRead d < R >s0 bus L OR #012H T8 AB:006 DB:-- 2 4 mw u > W < res H OR #013H T9 AB:006 DB:-- 3 1 fMWrite R #014H T10 AB:006 DB:0A MREQ 3 2 fMWrite #015H T11 AB:006 DB:0A MREQ WR 3 3 fMWrite Y #017H T13 AB:000 DB:-- 4 1 fMRead WZ W R >bs bus bus OpcodeToIR ...continues here from the (ix+d) addressing mode #018H T14 AB:000 DB:DD MREQ RD 4 2 fMRead #019H T15 AB:000 DB:DD MREQ RD 4 3 fMRead mw d < R alu >s0 bus L OR #029H T17 AB:002 DB:-- 5 1 fMWrite R u > W < res H OR #030H T18 AB:002 DB:BB MREQ 5 2 fMWrite #031H T19 AB:002 DB:BB MREQ WR 5 3 fMWrite Y #end "#if ~use_ixiy & pla[73] & ~pla[55] : res b,r" 4 #005H T1 AB:001 DB:-- M1 1 1 fMFetch r8' < u < res H NAND #006H T2 AB:001 DB:40 M1 MREQ RD 1 2 fMFetch #007H T3 AB:001 DB:-- RFSH 1 3 fMFetch AF > R > >bs bus bus * * * * * * Override M1/T3 load with a bit select #008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y Y r8 >r8 - >s0 bus L NAND #017H T13 AB:000 DB:-- 4 1 fMRead WZ W R >bs bus bus OpcodeToIR ...continues here from the (ix+d) addressing mode #018H T14 AB:000 DB:DD MREQ RD 4 2 fMRead #019H T15 AB:000 DB:DD MREQ RD 4 3 fMRead mw d < R alu >s0 bus L NAND #029H T17 AB:002 DB:-- 5 1 fMWrite R u > W < res H NAND #030H T18 AB:002 DB:BB MREQ 5 2 fMWrite #031H T19 AB:002 DB:BB MREQ WR 5 3 fMWrite Y #end "#if ~use_ixiy & pla[73] & pla[55] : res b,(hl)" "4,4,3" #005H T1 AB:001 DB:-- M1 1 1 fMFetch #006H T2 AB:001 DB:06 M1 MREQ RD 1 2 fMFetch #007H T3 AB:001 DB:-- RFSH 1 3 fMFetch AF > R > >bs bus bus * * * * * * Override M1/T3 load with a bit select #008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y mr #009H T5 AB:006 DB:-- 2 1 fMRead HL W #010H T6 AB:006 DB:05 MREQ RD 2 2 fMRead #011H T7 AB:006 DB:05 MREQ RD 2 3 fMRead d < R >s0 bus L NAND #012H T8 AB:006 DB:-- 2 4 mw u > W < res H NAND #013H T9 AB:006 DB:-- 3 1 fMWrite R #014H T10 AB:006 DB:0A MREQ 3 2 fMWrite #015H T11 AB:006 DB:0A MREQ WR 3 3 fMWrite Y #017H T13 AB:000 DB:-- 4 1 fMRead WZ W R >bs bus bus OpcodeToIR ...continues here from the (ix+d) addressing mode #018H T14 AB:000 DB:DD MREQ RD 4 2 fMRead #019H T15 AB:000 DB:DD MREQ RD 4 3 fMRead mw d < R alu >s0 bus L NAND #029H T17 AB:002 DB:-- 5 1 fMWrite R u > W < res H NAND #030H T18 AB:002 DB:BB MREQ 5 2 fMWrite #031H T19 AB:002 DB:BB MREQ WR 5 3 fMWrite Y #end // Input and Output Groups "#if pla[37] & ~pla[28] : in a,(n)" "4,3,4" #001H T1 AB:000 DB:-- M1 1 1 fMFetch A < d < R #002H T2 AB:000 DB:DB M1 MREQ RD 1 2 fMFetch #003H T3 AB:000 DB:-- RFSH 1 3 fMFetch #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr #005H T5 AB:001 DB:-- 2 1 fMRead PC W #006H T6 AB:001 DB:01 MREQ RD 2 2 fMRead PC + R #007H T7 AB:001 DB:01 MREQ RD 2 3 fMRead ior #008H T8 AB:001 DB:-- 3 1 fIORead A W ? < < R #009H T9 AB:001 DB:-- RD IORQ 3 2 fIORead #010H T10 AB:001 DB:-- RD IORQ 3 3 fIORead #011H T11 AB:001 DB:-- RD IORQ 3 4 fIORead Y #end "#if pla[27] & ~pla[34] : in r,(c)" "4,4" #005H T1 AB:001 DB:-- M1 1 1 fMFetch r8 < d < R alu res H OR * * P 0 #006H T2 AB:001 DB:40 M1 MREQ RD 1 2 fMFetch F < < #007H T3 AB:001 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * * #008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y ior #009H T5 AB:0FF DB:-- 2 1 fIORead BC W #010H T6 AB:0FF DB:-- RD IORQ 2 2 fIORead #011H T7 AB:0FF DB:-- RD IORQ 2 3 fIORead #012H T8 AB:0FF DB:-- RD IORQ 2 4 fIORead Y d < R alu >s0 bus bus L OR * * * 0 #end "#if pla[37] & pla[28] : out (n),a" "4,3,4" #001H T1 AB:000 DB:-- M1 1 1 fMFetch #002H T2 AB:000 DB:D3 M1 MREQ RD 1 2 fMFetch #003H T3 AB:000 DB:-- RFSH 1 3 fMFetch #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr #005H T5 AB:001 DB:-- 2 1 fMRead PC W #006H T6 AB:001 DB:01 MREQ RD 2 2 fMRead PC + R #007H T7 AB:001 DB:01 MREQ RD 2 3 fMRead iow A W h u > W #009H T9 AB:001 DB:03 WR IORQ 3 2 fIOWrite #010H T10 AB:001 DB:03 WR IORQ 3 3 fIOWrite #011H T11 AB:001 DB:03 WR IORQ 3 4 fIOWrite Y #end "#if pla[27] & pla[34] : out (c),r" "4,4" #005H T1 AB:001 DB:-- M1 1 1 fMFetch #006H T2 AB:001 DB:41 M1 MREQ RD 1 2 fMFetch #007H T3 AB:001 DB:-- RFSH 1 3 fMFetch #008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y iow r8' >r8' - > W #009H T5 AB:0FF DB:-- 2 1 fIOWrite BC W #010H T6 AB:0FF DB:C3 WR IORQ 2 2 fIOWrite #011H T7 AB:0FF DB:C3 WR IORQ 2 3 fIOWrite #012H T8 AB:0FF DB:C3 WR IORQ 2 4 fIOWrite Y #end #if pla[91] & pla[21] : ini/inir/ind/indr "5,4,3,(5)" #035H T1 AB:00A DB:-- M1 1 1 fMFetch < res H XOR P #036H T2 AB:00A DB:B2 M1 MREQ RD 1 2 fMFetch F < < #037H T3 AB:004 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * * #038H T4 AB:004 DB:-- RFSH MREQ 1 4 fMFetch Y #039H T5 AB:004 DB:-- 1 5 ior #040H T6 AB:000 DB:-- 2 1 fIORead BC W #041H T7 AB:000 DB:-- RD IORQ 2 2 fIORead B > alu >s0 0 bus L ADD * NEG_OP2 #042H T8 AB:000 DB:-- RD IORQ 2 3 fIORead B < alu < res H ADD * * * NEG_OP2 #043H T9 AB:000 DB:-- RD IORQ 2 4 fIORead mw d < R alu >s0 bus S NEG_OP2 #044H T10 AB:000 DB:-- 3 1 fMWrite HL W #045H T11 AB:000 DB:B1 MREQ 3 2 fMWrite HL op3 R #046H T12 AB:000 DB:B1 MREQ WR 3 3 fMWrite Y BZ #047H T13 AB:000 DB:-- 4 1 PC W #048H T14 AB:000 DB:-- 4 2 PC - R #049H T15 AB:000 DB:-- 4 3 PC W #050H T16 AB:000 DB:-- 4 4 PC - R #051H T17 AB:000 DB:-- 4 5 Y #end #if pla[91] & pla[20] : outi/outir/outd/outdr "5,4,3,(5)" #035H T1 AB:00A DB:-- M1 1 1 fMFetch alu < res H XOR P #036H T2 AB:00A DB:B3 M1 MREQ RD 1 2 fMFetch F < < #037H T3 AB:004 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * * #038H T4 AB:004 DB:-- RFSH MREQ 1 4 fMFetch Y B > alu >s0 0 bus L ADD * NEG_OP2 #039H T5 AB:004 DB:-- 1 5 mr B < alu < res H ADD * * NEG_OP2 #040H T6 AB:000 DB:-- 2 1 fMRead HL W #041H T7 AB:000 DB:21 MREQ RD 2 2 fMRead HL op3 R #042H T8 AB:000 DB:21 MREQ RD 2 3 fMRead iow L >l d >s0 bus #043H T9 AB:000 DB:-- 3 1 fIOWrite BC W #044H T10 AB:000 DB:21 WR IORQ 3 2 fIOWrite d < R alu >s0 bus L ADD * S #045H T11 AB:000 DB:21 WR IORQ 3 3 fIOWrite alu < res H ADD * #046H T12 AB:000 DB:21 WR IORQ 3 4 fIOWrite Y BZ #047H T13 AB:000 DB:-- 4 1 PC W #048H T14 AB:000 DB:-- 4 2 PC - R #049H T15 AB:000 DB:-- 4 3 PC W #050H T16 AB:000 DB:-- 4 4 PC - R #051H T17 AB:000 DB:-- 4 5 Y #end // Jump Group #if pla[29] : jp nn "4,3,3" #001H T1 AB:000 DB:-- M1 1 1 fMFetch #002H T2 AB:000 DB:C3 M1 MREQ RD 1 2 fMFetch #003H T3 AB:000 DB:-- RFSH 1 3 fMFetch #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr #005H T5 AB:001 DB:-- 2 1 fMRead PC W #006H T6 AB:001 DB:01 MREQ RD 2 2 fMRead PC + R #007H T7 AB:001 DB:01 MREQ RD 2 3 fMRead mr Z > >s0 bus bus * * * * * * #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr #005H T5 AB:001 DB:-- 2 1 fMRead PC W #006H T6 AB:001 DB:01 MREQ RD 2 2 fMRead PC + R #007H T7 AB:001 DB:01 MREQ RD 2 3 fMRead mr Z > >s0 bus bus * * * * * * #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr #005H T5 AB:001 DB:-- 2 1 fMRead PC W #006H T6 AB:001 DB:01 MREQ RD 2 2 fMRead PC + R #007H T7 AB:001 DB:01 MREQ RD 2 3 fMRead Y #008H T8 AB:001 DB:-- 3 1 d < R alu >s0 bus * "Reads ""e"" from the data latch" #009H T9 AB:001 DB:-- 3 2 PCl >l d alu >s0 bus L ADD * #010H T10 AB:001 DB:-- 3 3 Z alu >s0 0 bus L ADC * ?SF_NEG #012H T12 AB:001 DB:-- 3 5 Y WZ W W > >s0 bus bus * * * * * * #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr CondShort M1/T4 evaluates a condition: force short #005H T5 AB:001 DB:-- 2 1 fMRead PC W #006H T6 AB:001 DB:01 MREQ RD 2 2 fMRead PC + R #007H T7 AB:001 DB:01 MREQ RD 2 3 fMRead Y SS #008H T8 AB:001 DB:-- 3 1 d < R alu >s0 bus * "Reads ""e"" from the data latch" #009H T9 AB:001 DB:-- 3 2 PCl >l d alu >s0 bus L ADD * #010H T10 AB:001 DB:-- 3 3 Z alu >s0 0 bus L ADC * ?SF_NEG #012H T12 AB:001 DB:-- 3 5 Y WZ W W > >s0 bus bus * * * * * * #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y B >h alu >s0 0 bus L ADD * NEG_OP2 B=B-1 #005H T5 AB:000 DB:-- 1 5 mr B < alu < res H ADD * NEG_OP2 #006H T6 AB:001 DB:-- 2 1 fMRead PC W #007H T7 AB:001 DB:01 MREQ RD 2 2 fMRead PC + R #008H T8 AB:001 DB:01 MREQ RD 2 3 fMRead Y ZF #009H T9 AB:001 DB:-- 3 1 d < R alu >s0 bus * "Reads ""e"" from the data latch" #010H T10 AB:001 DB:-- 3 2 PCl >l d alu >s0 bus L ADD * #011H T11 AB:001 DB:-- 3 3 Z h alu >s0 0 bus L ADC * ?SF_NEG #013H T13 AB:001 DB:-- 3 5 Y WZ W W h u > W #013H T13 AB:000 DB:00 MREQ 4 2 fMWrite SP - R #014H T14 AB:000 DB:00 MREQ WR 4 3 fMWrite mw SP - W #015H T15 AB:0FF DB:-- 5 1 fMWrite - P PCl >l > W #016H T16 AB:0FF DB:03 MREQ 5 2 fMWrite SP - R #017H T17 AB:0FF DB:03 MREQ WR 5 3 fMWrite Y WZ W NOT_PC! #end "#if pla[42] : call cc,nn" "4,3,3/(4,3,4,3,3)" #001H T1 AB:000 DB:-- M1 1 1 fMFetch #002H T2 AB:000 DB:C4 M1 MREQ RD 1 2 fMFetch #003H T3 AB:000 DB:-- RFSH 1 3 fMFetch AF > > >s0 bus bus * * * * * * #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr #005H T5 AB:001 DB:-- 2 1 fMRead PC W #006H T6 AB:001 DB:01 MREQ RD 2 2 fMRead PC + R #007H T7 AB:001 DB:01 MREQ RD 2 3 fMRead mr Z h u > W #013H T13 AB:000 DB:00 MREQ 4 2 fMWrite SP - R #014H T14 AB:000 DB:00 MREQ WR 4 3 fMWrite mw SP - W #015H T15 AB:0FF DB:-- 5 1 fMWrite - P PCl >l > W #016H T16 AB:0FF DB:03 MREQ 5 2 fMWrite SP - R #017H T17 AB:0FF DB:03 MREQ WR 5 3 fMWrite Y WZ W NOT_PC! #end #if pla[35] : ret "4,3,3" #001H T1 AB:000 DB:-- M1 1 1 fMFetch #002H T2 AB:000 DB:C9 M1 MREQ RD 1 2 fMFetch #003H T3 AB:000 DB:-- RFSH 1 3 fMFetch #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y mr #005H T5 AB:0FF DB:-- 2 1 fMRead SP W #006H T6 AB:0FF DB:01 MREQ RD 2 2 fMRead SP + R #007H T7 AB:0FF DB:01 MREQ RD 2 3 fMRead mr Z > >s0 bus bus * * * * * * #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y #005H T5 AB:000 DB:-- 1 5 mr CC #006H T6 AB:001 DB:-- 2 1 fMRead SP W #007H T7 AB:001 DB:01 MREQ RD 2 2 fMRead SP + R #008H T8 AB:001 DB:01 MREQ RD 2 3 fMRead mr Z s0 bus Store im2 vector into the ALU op1 #006H T6 AB:000 DB:-- 2 1 fMWrite - P PCh >h u > W #007H T7 AB:000 DB:00 MREQ 2 2 fMWrite SP - R #008H T8 AB:000 DB:00 MREQ WR 2 3 fMWrite mw SP - W #009H T9 AB:0FF DB:-- 3 1 fMWrite - P PCl >l > W #010H T10 AB:0FF DB:01 MREQ 3 2 fMWrite SP - R #011H T11 AB:0FF DB:01 MREQ WR 3 3 fMWrite INT INT WZ W NOT_PC! Value on the bus into ALU OP // INTR IM2 continues here... Extension for IM2 interrupt mode #012H T12 AB:001 DB:-- 4 1 fMRead I* W + R >l d >s0 bus #014H T14 AB:001 DB:01 MREQ RD 4 3 fMRead mr Z > >s0 bus bus * * * * * * CB #008H T4 AB:001 DB:-- RFSH MREQ 1 4 fMFetch Y mr #009H T5 AB:002 DB:-- 2 1 fMRead PC W #010H T6 AB:002 DB:01 MREQ RD 2 2 fMRead PC + R #011H T7 AB:002 DB:01 MREQ RD 2 3 fMRead mr #012H T8 AB:003 DB:-- 3 1 fMRead PC W WZ=IX+d #013H T9 AB:003 DB:00 MREQ RD 3 2 fMRead PC + R WZ=IX+d #014H T10 AB:003 DB:00 MREQ RD 3 3 fMRead WZ=IX+d Loads the opcode byte in parallel #015H T11 AB:003 DB:-- 3 4 WZ=IX+d #016H T12 AB:003 DB:-- 3 5 mr WZ=IX+d #017H T13 AB:000 DB:-- 4 1 R >bs bus bus OpcodeToIR Loads instruction register; starts the execute cycle // Loading a new instruction immediately changes PLA wires and continues into the new effective instructions' M4/T1 cycle #end // Special Purposes PLA Entries #if pla[3] : IX/IY 4 #001H T1 AB:000 DB:-- M1 1 1 fMFetch #002H T2 AB:000 DB:DD M1 MREQ RD 1 2 fMFetch IX_IY #003H T3 AB:000 DB:-- RFSH 1 3 fMFetch #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y Y NO_INTS "At last M/T, inhibit interrupts" #end #if pla[44] : CB prefix 4 #001H T1 AB:000 DB:-- M1 1 1 fMFetch #002H T2 AB:000 DB:CB M1 MREQ RD 1 2 fMFetch CB #003H T3 AB:000 DB:-- RFSH 1 3 fMFetch #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y Y NO_INTS "At last M/T, inhibit interrupts" "#end Only set CB ff and clear ED, XX ff" #if pla[51] : ED prefix 4 #001H T1 AB:000 DB:-- M1 1 1 fMFetch #002H T2 AB:000 DB:ED M1 MREQ RD 1 2 fMFetch ED #003H T3 AB:000 DB:-- RFSH 1 3 fMFetch #004H T4 AB:000 DB:-- RFSH MREQ 1 4 fMFetch Y Y NO_INTS "At last M/T, inhibit interrupts" "#end Only set ED ff and clear CB, XX ff" #if pla[76] : ALU CP #always CP 1 #001H T1 AB:000 DB:-- M1 1 1 fMFetch V Update P/V once on a high nibble phase #end Does not store the result! #if pla[78] : ALU SUB #always SUB 1 #001H T1 AB:000 DB:-- M1 1 1 fMFetch A < * V Update P/V and store result to A #end #if pla[79] : ALU SBC #always SBC 1 #001H T1 AB:000 DB:-- M1 1 1 fMFetch A < * V Update P/V and store result to A #end #if pla[80] : ALU ADC #always ADC 0 #001H T1 AB:000 DB:-- M1 1 1 fMFetch A < * V Update P/V and store result to A #end #if pla[84] : ALU ADD #always ADD 0 #001H T1 AB:000 DB:-- M1 1 1 fMFetch A < * V Update P/V and store result to A #end #if pla[85] : ALU AND #always AND 0 #001H T1 AB:000 DB:-- M1 1 1 fMFetch A < * P Update P/V and store result to A #002H T2 AB:000 DB:A0 M1 MREQ RD 1 2 fMFetch 0 AND clears CF #end #if pla[86] : ALU OR #always OR 0 #001H T1 AB:000 DB:-- M1 1 1 fMFetch A < * P Update P/V and store result to A #002H T2 AB:000 DB:B0 M1 MREQ RD 1 2 fMFetch 0 OR clears CF #end #if pla[88] : ALU XOR #always XOR 0 #001H T1 AB:000 DB:-- M1 1 1 fMFetch A < * P Update P/V and store result to A #002H T2 AB:000 DB:A8 M1 MREQ RD 1 2 fMFetch 0 XOR clears CF #end // State machine to compute (IX+d) #if ixy_d : Compute WZ=IX+d #001H T1 any M-cycle ? 1 d < R alu >s0 bus * "Reads ""d"" from the data latch" #002H T2 ? 2 L >l d alu >s0 bus L ADD * #003H T3 ? 3 Z alu >s0 0 bus L ADC * R ?SF_NEG Stores result into WZ #005H T5 ? 5 WZ W W =0: return s[:i] i = s.find('/*') # Remove comments within a line j = s.find('*/') if i>=0 and j>=0: return decomment(s[:i] + s[j+2:]) return s #-------------------------------------------------------------------------------- # Generate a sequential-or form for all control wires #-------------------------------------------------------------------------------- def sequential_or(f, t, tokens): incond = False # Inside an "if" condition state cond = [] # Condition nested lists ccond = [] # Currently scanned condition list ctls = {} # Dictionary of control wires and their equations ccwires = [] # List of wires at the current condition list level i = 0 # Current index into the tokens list while i < len(tokens): tok = tokens[i] (toknum, tokval, _, _, _) = tok if incond and not (toknum==NAME and tokval=='begin'): if toknum != DEDENT and toknum != INDENT: ccond.append(tok) if toknum==NAME: if tokval=='if': incond = True if tokval=='begin': # Push a condition list incond = False cond.append(copy.deepcopy(ccond)) ccond.clear() ccwires.clear() if tokval=='end': # Pop a condition list cond.pop() if is_ctl(tokval) and not incond: rval = get_rval(tokens, i) linesub = tok2str(cond) rhs = tok2str(rval) line = "{0} = {0} | ".format(tokval) if tokval in ccwires: # Check for duplicate assignments hint = [ cond[n][m].string for n in range(len(cond)) for m in range(len(cond[n])) ] print ("WARNING: {0}: Multiple assignment of {1}".format(''.join(hint), tokval)) ccwires.append(tokval) # Track this wire as assigned at this condition level if tokval in ctls_wide: tr = linesub.translate(str.maketrans(dict.fromkeys('~','n'))) # Make temporary name tmpname = "{0}_{1}_{2}".format(tokval, tr.translate(str.maketrans(dict.fromkeys('[]()&',None))), len(ccwires)) t.write("reg {0};\n".format(tmpname)) line = "{0} = {1};\n".format(tmpname, linesub) + line line += "({{{0},{0}}}){1}".format(tmpname, rhs) else: line += linesub + rhs line = line.replace(')(', ')&(') line = line.replace('&&', '&') line = line.replace('(1)&', '') line = line.replace('&(1)', '') i += len(rval[0]) f.write ('{0};\n'.format(line)) i += 1 #-------------------------------------------------------------------------------- tokens = [] # Input file which we are processing with open(fname) as f: lines = f.readlines() for line in lines: src = decomment(line) src = bytes(src.encode()) src = io.BytesIO(src) toklist = list(tokenize.tokenize(src.readline)) tokens.extend(toklist) with open(oname, 'w') as f: with open(tname, 'w') as t: f.write("// Automatically generated by gencompile.py\n\n") t.write("// Automatically generated by gencompile.py\n\n") sequential_or(f, t, tokens) # Touch a file that includes 'exec_matrix_compiled.vh' to ensure it will recompile correctly os.utime("execute.v", None) ================================================ FILE: cpu/control/genmatrix.py ================================================ #!/usr/bin/env python3 # # This script reads A-Z80 instruction timing data from a spreadsheet text file # 'Timings.csv' (which is a TAB-delimited text file exported from 'Timings.xlsm') # and generates a Verilog include file defining the control block execution matrix. # Token keywords in the timing spreadsheet are substituted using a list of keys # defined in 'timing_macros.i'. # #------------------------------------------------------------------------------- # Copyright (C) 2014,2016 Goran Devic # # This program is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by the Free # Software Foundation; either version 2 of the License, or (at your option) # any later version. # # This program is distributed in the hope that it will be useful, but WITHOUT # ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or # FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for # more details. #------------------------------------------------------------------------------- import string import sys import csv import os # Input file (exported from 'Timings.xlsm'): fname = "Timings.csv" # Input file containing macro substitution keys kname = "timing_macros.i" # Set this to 1 if you want abbreviated matrix (no-action lines removed) abbr = 1 # Set this to 0 if you want to strip all comments from the resulting file comment = 1 # Set this to 1 if you want debug $display() printout on each PLA line debug = 0 # Print this string in front of every line that starts with "ctl_". This helps # formatting the output to be more readable. ctl_prefix = "\n"+" "*19 # Read in the content of the macro substitution file macros = [] with open(kname, 'r') as f: for line in f: if len(line.strip())>0 and line[0]!='/': # Wrap up non-starting //-style comments into /* ... */ so the # line can be concatenated while preserving comments i = line.find("//") if i>0: if comment==1: macros.append( line.rstrip().replace("//", "/*", 1) + " */" ) else: macros.append( line.rstrip()[0:i] ) else: macros.append(line.rstrip()) # List of errors / keys and macros that did not match. We stash them as we go # and then print at the end so it is easier to find them errors = [] # Returns a substitution string given the section name (key) and the macro token # This is done by simply traversing macro substitution list of lines, finding a # section that starts with a :key and copying the substitution lines verbatim. def getSubst(key, token): subst = [] multiline = False validset = False if key=="Comments": # Special case: ignore "Comments" column! return "" for l in macros: if multiline==True: # Multiline copies lines until a char at [0] is not a space if len(l.strip())==0 or l[0]!=' ': return '\n' + "\n".join(subst).rstrip() else: subst.append(l.rstrip()) lx = l.split(' ') # Split the string and then ignore (duplicate) lx = list(filter(None, lx)) # spaces in the list left by the split() if l.startswith(":"): # Find and recognize a matching set (key) section if validset: # Error if there is a new section going from the macthing one break # meaning we did not find our macro in there if l[1:]==key: validset = True elif validset and lx[0]==token: if len(lx)==1: return "" if lx[1]=='\\': # Multi-line macro state starts with '\' character multiline = True continue lx.pop(0) s = " ".join(lx) return ' ' + s.strip() err = "{0} not in {1}".format(token, key) if err not in errors: errors.append(err) return " --- {0} ?? {1} --- ".format(token, key) # Read the content of a file and using the csv reader and remove any quotes from the input fields content = [] # Content of the spreadsheet timing file with open(fname, 'r') as csvFile: reader = csv.reader(csvFile, delimiter='\t', quotechar='"') for row in reader: content.append('\t'.join(row)) # The first line is special: it contains names of sets for our macro substitutions tkeys = {} # Spreadsheet table column keys tokens = content.pop(0).split('\t') for col in range(len(tokens)): if len(tokens[col])==0: continue tkeys[col] = tokens[col] # Process each line separately (stateless processor) imatrix = [] # Verilog execution matrix code for line in content: col = line.split('\t') # Split the string into a list of columns col_clean = list(filter(None, col)) # Removed all empty fields (between the separators) if len(col_clean)==0: # Ignore completely empty lines continue if col_clean[0].startswith('//') and comment==1: imatrix.append(col_clean[0]) # Optionally print comment lines if col_clean[0].startswith("#end"): # Print the end of a condition imatrix.append("end\n") if col_clean[0].startswith('#if'): # Print the start of a condition s = col_clean[0] tag = s.find(":") condition = s[4:tag] imatrix.append("if ({0}) begin".format(condition.strip())) if debug and len(s[tag:])>1: # Print only in debug and there is something to print imatrix.append(" $display(\"{0}\");".format(s[4:])) # We recognize 2 kinds of timing statements based on the starting characters: # "#0".. common timings using M and T cycles (M being optional) # "#always" timing that does not depend on M and T cycles (ex. ALU operations) if col_clean[0].startswith('#0') or col_clean[0].startswith('#always'): # M and T states are hard-coded in the table at the index 1 and 2 if col_clean[0].startswith('#0'): if col[1]=='?': # M is optional, use '?' to skip it state = " if (T{0}) begin".format(col[2]) else: state = " if (M{0} & T{1}) begin".format(col[1], col[2]) else: state = " begin" # Loop over all other columns and perform verbatim substitution action = "" for i in range(3,len(col)): # There may be multiple tokens separated by commas tokList = col[i].strip().split(',') tokList = list(filter(None, tokList)) # Filter out empty lines for token in tokList: token = token.strip() if i in tkeys and len(token)>0: macro = getSubst(tkeys[i], token) if macro.strip().startswith("ctl_"): action += ctl_prefix action += macro if state.find("ERROR")>=0: print ("{0} {1}".format(state, action)) break # Complete and write out a line if abbr and len(action)==0: continue imatrix.append("{0}{1} end".format(state, action)) # Create a file containing the logic matrix code with open('exec_matrix.vh', 'w') as file: if comment==1: file.write("// Automatically generated by genmatrix.py\n\n") # If there were errors, print them first (and output to the console) if len(errors)>0: for error in errors: print (error) file.write(error + "\n") file.write("-" * 80 + "\n") for item in imatrix: file.write("{}\n".format(item)) # Touch a file that includes 'exec_matrix.vh' to ensure it will recompile correctly os.utime("execute.v", None) ================================================ FILE: cpu/control/genref.py ================================================ #!/usr/bin/env python3 # # This script reads and parses selected Verilog and SystemVerilog modules # and generates a set of Verilog include files for the control block. # #------------------------------------------------------------------------------- # Copyright (C) 2014 Goran Devic # # This program is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by the Free # Software Foundation; either version 2 of the License, or (at your option) # any later version. # # This program is distributed in the hope that it will be useful, but WITHOUT # ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or # FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for # more details. #------------------------------------------------------------------------------- import glob import os with open('../top-level-files.txt') as f: files = f.read().splitlines() # Create 2 files that should be included by the execution engine: # 1. A file listing all control signals # 2. A file containing statements initializing control signals to zero with open('exec_module.vh', 'w') as file1, open('exec_zero.vh', 'w') as file0: file1.write("// Automatically generated by genref.py\n") file0.write("// Automatically generated by genref.py\n") # Read and parse each file from the list of input files for infile in files: wires = [] if not os.path.isfile('../' + infile): continue with open('../' + infile, "r") as f: for line in f: info = line.split() # input wire register case if len(info)>2 and info[0]=="input" and info[1]=="wire" and info[2].startswith("ctl_"): wires.append(info[2].strip(';,')) # input wire bus case (ex. "[1:0]") if len(info)>3 and info[0]=="input" and info[1]=="wire" and info[2].startswith("[") and info[3].startswith("ctl_"): wires.append(info[2] + " " + info[3].strip(';,')) if len(wires)>0: with open('exec_module.vh', 'a') as file1, open('exec_zero.vh', 'a') as file0: print ("MODULE:", infile) file0.write("\n// Module: " + infile + "\n") file1.write("\n// Module: " + infile + "\n") for wire in wires: print (" ", wire) file1.write("output reg " + wire + ",\n") if "[" in wire: file0.write(wire.split()[1] + " = 0;\n") else: file0.write(wire + " = 0;\n") # Touch a file that includes 'exec_module.vh' and 'exec_zero.vh' to ensure it will recompile correctly os.utime("execute.v", None) ================================================ FILE: cpu/control/interrupts.bdf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. 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IFF1 can be loaded from IFF2 or op3" (rect 400 176 637 190)(font "Arial" (font_size 8))) (title_block (rect 24 1144 281 1196) (name "title-custom-small") (section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "July 19, 2014, 2016" (rect 56 3 166 17)(font "Arial" (font_size 8)))(border)) (section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border)) (section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "interrupts" (rect 43 2 109 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.4" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border)) (drawing ) ) ================================================ FILE: cpu/control/interrupts.bsf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "symbol" (version "1.2")) (symbol (rect 64 64 216 288) (text "interrupts" (rect 5 0 59 14)(font "Arial" (font_size 8))) (text "inst" (rect 8 208 25 220)(font "Arial" )) (port (pt 0 32) (input) (text "ctl_iff1_iff2" (rect 0 0 64 14)(font "Arial" (font_size 8))) (text "ctl_iff1_iff2" (rect 21 27 85 41)(font "Arial" (font_size 8))) (line (pt 0 32)(pt 16 32)) ) (port (pt 0 48) (input) (text "ctl_iffx_we" (rect 0 0 64 14)(font "Arial" (font_size 8))) (text "ctl_iffx_we" (rect 21 43 85 57)(font "Arial" (font_size 8))) (line (pt 0 48)(pt 16 48)) ) (port (pt 0 64) (input) (text "ctl_iffx_bit" (rect 0 0 59 14)(font "Arial" (font_size 8))) (text "ctl_iffx_bit" (rect 21 59 80 73)(font "Arial" (font_size 8))) (line (pt 0 64)(pt 16 64)) ) (port (pt 0 80) (input) (text "nmi" (rect 0 0 18 14)(font "Arial" (font_size 8))) (text "nmi" (rect 21 75 39 89)(font "Arial" (font_size 8))) (line (pt 0 80)(pt 16 80)) ) (port (pt 0 96) (input) (text "intr" (rect 0 0 17 14)(font "Arial" (font_size 8))) (text "intr" (rect 21 91 38 105)(font "Arial" (font_size 8))) (line (pt 0 96)(pt 16 96)) ) (port (pt 0 112) (input) (text "setM1" (rect 0 0 34 14)(font "Arial" (font_size 8))) (text "setM1" (rect 21 107 55 121)(font "Arial" (font_size 8))) (line (pt 0 112)(pt 16 112)) ) (port (pt 0 128) (input) (text "ctl_no_ints" (rect 0 0 61 14)(font "Arial" (font_size 8))) (text "ctl_no_ints" (rect 21 123 82 137)(font "Arial" (font_size 8))) (line (pt 0 128)(pt 16 128)) ) (port (pt 0 144) (input) (text "db[1..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) (text "db[1..0]" (rect 21 139 63 153)(font "Arial" (font_size 8))) (line (pt 0 144)(pt 16 144)(line_width 3)) ) (port (pt 0 160) (input) (text "clk" (rect 0 0 15 14)(font "Arial" (font_size 8))) (text "clk" (rect 21 155 36 169)(font "Arial" (font_size 8))) (line (pt 0 160)(pt 16 160)) ) (port (pt 0 176) (input) (text "ctl_im_we" (rect 0 0 57 14)(font "Arial" (font_size 8))) (text "ctl_im_we" (rect 21 171 78 185)(font "Arial" (font_size 8))) (line (pt 0 176)(pt 16 176)) ) (port (pt 0 192) (input) (text "nreset" (rect 0 0 36 14)(font "Arial" (font_size 8))) (text "nreset" (rect 21 187 57 201)(font "Arial" (font_size 8))) (line (pt 0 192)(pt 16 192)) ) (port (pt 152 32) (output) (text "iff2" (rect 0 0 18 14)(font "Arial" (font_size 8))) (text "iff2" (rect 113 27 131 41)(font "Arial" (font_size 8))) (line (pt 152 32)(pt 136 32)) ) (port (pt 152 48) (output) (text "in_nmi" (rect 0 0 35 14)(font "Arial" (font_size 8))) (text "in_nmi" (rect 96 43 131 57)(font "Arial" (font_size 8))) (line (pt 152 48)(pt 136 48)) ) (port (pt 152 64) (output) (text "in_intr" (rect 0 0 34 14)(font "Arial" (font_size 8))) (text "in_intr" (rect 97 59 131 73)(font "Arial" (font_size 8))) (line (pt 152 64)(pt 136 64)) ) (port (pt 152 80) (output) (text "im1" (rect 0 0 18 14)(font "Arial" (font_size 8))) (text "im1" (rect 113 75 131 89)(font "Arial" (font_size 8))) (line (pt 152 80)(pt 136 80)) ) (port (pt 152 96) (output) (text "im2" (rect 0 0 18 14)(font "Arial" (font_size 8))) (text "im2" (rect 113 91 131 105)(font "Arial" (font_size 8))) (line (pt 152 96)(pt 136 96)) ) (drawing (rectangle (rect 16 16 136 208)) ) ) ================================================ FILE: cpu/control/interrupts.v ================================================ // Copyright (C) 1991-2013 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // PROGRAM "Quartus II 64-Bit" // VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" // CREATED "Sat Feb 13 19:23:03 2016" module interrupts( ctl_iff1_iff2, nmi, setM1, intr, ctl_iffx_we, ctl_iffx_bit, ctl_im_we, clk, ctl_no_ints, nreset, db, iff2, im1, im2, in_nmi, in_intr ); input wire ctl_iff1_iff2; input wire nmi; input wire setM1; input wire intr; input wire ctl_iffx_we; input wire ctl_iffx_bit; input wire ctl_im_we; input wire clk; input wire ctl_no_ints; input wire nreset; input wire [1:0] db; output wire iff2; output reg im1; output reg im2; output wire in_nmi; output wire in_intr; reg iff1; wire in_intr_ALTERA_SYNTHESIZED; reg in_nmi_ALTERA_SYNTHESIZED; reg int_armed; reg nmi_armed; wire test1; wire SYNTHESIZED_WIRE_0; reg DFFE_instIFF2; wire SYNTHESIZED_WIRE_1; wire SYNTHESIZED_WIRE_2; wire SYNTHESIZED_WIRE_3; wire SYNTHESIZED_WIRE_4; wire SYNTHESIZED_WIRE_5; reg DFFE_inst44; wire SYNTHESIZED_WIRE_21; wire SYNTHESIZED_WIRE_7; wire SYNTHESIZED_WIRE_8; wire SYNTHESIZED_WIRE_9; wire SYNTHESIZED_WIRE_10; wire SYNTHESIZED_WIRE_11; wire SYNTHESIZED_WIRE_12; wire SYNTHESIZED_WIRE_13; wire SYNTHESIZED_WIRE_14; wire SYNTHESIZED_WIRE_15; wire SYNTHESIZED_WIRE_16; wire SYNTHESIZED_WIRE_17; wire SYNTHESIZED_WIRE_19; wire SYNTHESIZED_WIRE_20; assign iff2 = DFFE_instIFF2; assign SYNTHESIZED_WIRE_10 = 1; assign SYNTHESIZED_WIRE_2 = ctl_iffx_bit & SYNTHESIZED_WIRE_0; assign SYNTHESIZED_WIRE_1 = ctl_iff1_iff2 & DFFE_instIFF2; assign SYNTHESIZED_WIRE_16 = SYNTHESIZED_WIRE_1 | SYNTHESIZED_WIRE_2; assign SYNTHESIZED_WIRE_17 = ctl_iffx_we | ctl_iff1_iff2; assign SYNTHESIZED_WIRE_21 = SYNTHESIZED_WIRE_3 & nreset; assign SYNTHESIZED_WIRE_0 = ~ctl_iff1_iff2; assign SYNTHESIZED_WIRE_4 = ~db[0]; assign SYNTHESIZED_WIRE_5 = ~in_nmi_ALTERA_SYNTHESIZED; assign SYNTHESIZED_WIRE_20 = db[1] & db[0]; assign SYNTHESIZED_WIRE_19 = db[1] & SYNTHESIZED_WIRE_4; assign in_intr_ALTERA_SYNTHESIZED = SYNTHESIZED_WIRE_5 & DFFE_inst44; assign SYNTHESIZED_WIRE_15 = SYNTHESIZED_WIRE_21 & SYNTHESIZED_WIRE_7; assign SYNTHESIZED_WIRE_13 = iff1 & intr; assign test1 = setM1 & SYNTHESIZED_WIRE_8; always@(posedge nmi or negedge SYNTHESIZED_WIRE_9) begin if (!SYNTHESIZED_WIRE_9) begin nmi_armed <= 0; end else begin nmi_armed <= SYNTHESIZED_WIRE_10; end end assign SYNTHESIZED_WIRE_12 = SYNTHESIZED_WIRE_11 & nreset; always@(posedge clk or negedge nreset) begin if (!nreset) begin in_nmi_ALTERA_SYNTHESIZED <= 0; end else if (test1) begin in_nmi_ALTERA_SYNTHESIZED <= nmi_armed; end end always@(posedge clk or negedge nreset) begin if (!nreset) begin DFFE_inst44 <= 0; end else if (test1) begin DFFE_inst44 <= int_armed; end end always@(posedge clk or negedge SYNTHESIZED_WIRE_12) begin if (!SYNTHESIZED_WIRE_12) begin int_armed <= 0; end else begin int_armed <= SYNTHESIZED_WIRE_13; end end assign SYNTHESIZED_WIRE_9 = SYNTHESIZED_WIRE_14 & nreset; assign SYNTHESIZED_WIRE_8 = ~ctl_no_ints; always@(posedge clk or negedge SYNTHESIZED_WIRE_15) begin if (!SYNTHESIZED_WIRE_15) begin iff1 <= 0; end else if (SYNTHESIZED_WIRE_17) begin iff1 <= SYNTHESIZED_WIRE_16; end end always@(posedge clk or negedge SYNTHESIZED_WIRE_21) begin if (!SYNTHESIZED_WIRE_21) begin DFFE_instIFF2 <= 0; end else if (ctl_iffx_we) begin DFFE_instIFF2 <= ctl_iffx_bit; end end always@(posedge clk or negedge nreset) begin if (!nreset) begin im1 <= 0; end else if (ctl_im_we) begin im1 <= SYNTHESIZED_WIRE_19; end end always@(posedge clk or negedge nreset) begin if (!nreset) begin im2 <= 0; end else if (ctl_im_we) begin im2 <= SYNTHESIZED_WIRE_20; end end assign SYNTHESIZED_WIRE_3 = ~in_intr_ALTERA_SYNTHESIZED; assign SYNTHESIZED_WIRE_11 = ~in_intr_ALTERA_SYNTHESIZED; assign SYNTHESIZED_WIRE_7 = ~in_nmi_ALTERA_SYNTHESIZED; assign SYNTHESIZED_WIRE_14 = ~in_nmi_ALTERA_SYNTHESIZED; assign in_nmi = in_nmi_ALTERA_SYNTHESIZED; assign in_intr = in_intr_ALTERA_SYNTHESIZED; endmodule ================================================ FILE: cpu/control/ir.bdf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "graphic" (version "1.4")) (pin (input) (rect 40 96 216 112) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "ctl_ir_we" (rect 9 0 51 12)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) (line (pt 121 8)(pt 176 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) ) (pin (input) (rect 40 48 216 64) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "db[7..0]" (rect 9 0 46 12)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) (line (pt 121 8)(pt 176 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) ) (pin (input) (rect 40 64 216 80) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "clk" (rect 9 0 23 12)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) (line (pt 121 8)(pt 176 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) ) (pin (input) (rect 40 152 216 168) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "nreset" (rect 9 0 39 12)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) (line (pt 121 8)(pt 176 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) ) (pin (input) (rect 40 112 216 128) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "nhold_clk_wait" (rect 9 0 79 12)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) (line (pt 121 8)(pt 176 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) ) (pin (output) (rect 504 48 680 64) (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) (text "opcode[7..0]" (rect 90 0 151 12)(font "Arial" )) (pt 0 8) (drawing (line (pt 0 8)(pt 52 8)) (line (pt 52 4)(pt 78 4)) (line (pt 52 12)(pt 78 12)) (line (pt 52 12)(pt 52 4)) (line (pt 78 4)(pt 82 8)) (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) ) (symbol (rect 392 32 456 112) (text "DFFE" (rect 1 0 25 10)(font "Arial" (font_size 6))) (text "ir" (rect 3 68 8 80)(font "Arial" )) (port (pt 32 0) (input) (text "PRN" (rect 24 13 41 25)(font "Courier New" (bold))) (text "PRN" (rect 24 11 41 23)(font "Courier New" (bold))) (line (pt 32 4)(pt 32 0)) ) (port (pt 32 80) (input) (text "CLRN" (rect 21 59 44 71)(font "Courier New" (bold))) (text "CLRN" (rect 21 58 44 70)(font "Courier New" (bold))) (line (pt 32 80)(pt 32 76)) ) (port (pt 0 24) (input) (text "D" (rect 14 20 19 32)(font "Courier New" (bold))) (text "D" (rect 14 20 19 32)(font "Courier New" (bold))) (line (pt 0 24)(pt 12 24)) ) (port (pt 0 40) (input) (text "CLK" (rect 2 28 19 40)(font "Courier New" (bold))(invisible)) (text "CLK" (rect 2 28 19 40)(font "Courier New" (bold))(invisible)) (line (pt 0 40)(pt 12 40)) ) (port (pt 0 56) (input) (text "ENA" (rect 14 50 31 62)(font "Courier New" (bold))) (text "ENA" (rect 14 50 31 62)(font "Courier New" (bold))) (line (pt 0 56)(pt 12 56)) ) (port (pt 64 24) (output) (text "Q" (rect 44 20 49 32)(font "Courier New" (bold))) (text "Q" (rect 44 20 48 32)(font "Courier New" (bold))) (line (pt 53 24)(pt 64 24)) ) (drawing (line (pt 12 68)(pt 52 68)) (line (pt 12 12)(pt 52 12)) (line (pt 52 68)(pt 52 12)) (line (pt 12 68)(pt 12 12)) (line (pt 12 34)(pt 19 41)) (line (pt 18 41)(pt 12 47)) (circle (rect 28 4 36 12)) (circle (rect 28 68 36 76)) ) ) (symbol (rect 296 88 360 136) (text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6))) (text "inst5" (rect 3 37 26 49)(font "Arial" )) (port (pt 0 16) (input) (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible)) (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible)) (line (pt 0 16)(pt 14 16)) ) (port (pt 0 32) (input) (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible)) (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible)) (line (pt 0 32)(pt 14 32)) ) (port (pt 64 24) (output) (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible)) (text "OUT" (rect 48 15 62 27)(font "Courier New" (bold))(invisible)) (line (pt 42 24)(pt 64 24)) ) (drawing (line (pt 14 12)(pt 30 12)) (line (pt 14 37)(pt 31 37)) (line (pt 14 12)(pt 14 37)) (arc (pt 31 37)(pt 30 12)(rect 18 12 43 37)) ) ) (connector (pt 216 56) (pt 392 56) (bus) ) (connector (pt 216 72) (pt 392 72) ) (connector (pt 456 56) (pt 504 56) (bus) ) (connector (pt 424 160) (pt 216 160) ) (connector (pt 424 112) (pt 424 160) ) (connector (pt 392 88) (pt 376 88) ) (connector (pt 376 88) (pt 376 112) ) (connector (pt 376 112) (pt 360 112) ) (connector (pt 216 104) (pt 296 104) ) (connector (pt 216 120) (pt 296 120) ) (text "8 latches implement the opcode Instruction Register" (rect 328 216 619 230)(font "Arial" (font_size 8))) (title_block (rect 40 216 297 268) (name "title-custom-small") (section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "ir" (rect 43 2 52 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border)) (section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "May 3, 2014, 2016" (rect 56 3 161 17)(font "Arial" (font_size 8)))(border)) (section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.5" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border)) (drawing ) ) ================================================ FILE: cpu/control/ir.bsf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "symbol" (version "1.2")) (symbol (rect 16 16 224 144) (text "ir" (rect 5 0 12 14)(font "Arial" (font_size 8))) (text "inst" (rect 8 112 25 124)(font "Arial" )) (port (pt 0 32) (input) (text "db[7..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) (text "db[7..0]" (rect 21 27 63 41)(font "Arial" (font_size 8))) (line (pt 0 32)(pt 16 32)(line_width 3)) ) (port (pt 0 48) (input) (text "clk" (rect 0 0 15 14)(font "Arial" (font_size 8))) (text "clk" (rect 21 43 36 57)(font "Arial" (font_size 8))) (line (pt 0 48)(pt 16 48)) ) (port (pt 0 64) (input) (text "ctl_ir_we" (rect 0 0 53 14)(font "Arial" (font_size 8))) (text "ctl_ir_we" (rect 21 59 74 73)(font "Arial" (font_size 8))) (line (pt 0 64)(pt 16 64)) ) (port (pt 0 80) (input) (text "nhold_clk_wait" (rect 0 0 84 14)(font "Arial" (font_size 8))) (text "nhold_clk_wait" (rect 21 75 105 89)(font "Arial" (font_size 8))) (line (pt 0 80)(pt 16 80)) ) (port (pt 0 96) (input) (text "nreset" (rect 0 0 36 14)(font "Arial" (font_size 8))) (text "nreset" (rect 21 91 57 105)(font "Arial" (font_size 8))) (line (pt 0 96)(pt 16 96)) ) (port (pt 208 32) (output) (text "opcode[7..0]" (rect 0 0 70 14)(font "Arial" (font_size 8))) (text "opcode[7..0]" (rect 117 27 187 41)(font "Arial" (font_size 8))) (line (pt 208 32)(pt 192 32)(line_width 3)) ) (drawing (rectangle (rect 16 16 192 112)) ) ) ================================================ FILE: cpu/control/ir.v ================================================ // Copyright (C) 1991-2013 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // PROGRAM "Quartus II 64-Bit" // VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" // CREATED "Sat Dec 10 08:56:46 2016" module ir( ctl_ir_we, clk, nreset, nhold_clk_wait, db, opcode ); input wire ctl_ir_we; input wire clk; input wire nreset; input wire nhold_clk_wait; input wire [7:0] db; output reg [7:0] opcode; wire SYNTHESIZED_WIRE_0; assign SYNTHESIZED_WIRE_0 = ctl_ir_we & nhold_clk_wait; always@(posedge clk or negedge nreset) begin if (!nreset) begin opcode[7:0] <= 8'b00000000; end else if (SYNTHESIZED_WIRE_0) begin opcode[7:0] <= db[7:0]; end end endmodule ================================================ FILE: cpu/control/memory_ifc.bdf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. 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720) (pt 640 720) ) (connector (pt 624 704) (pt 640 704) ) (connector (pt 208 920) (pt 320 920) ) (connector (pt 384 920) (pt 432 920) ) (connector (pt 208 1112) (pt 320 1112) ) (connector (pt 384 1112) (pt 432 1112) ) (connector (pt 512 1112) (pt 512 1056) ) (connector (pt 624 1112) (pt 624 1072) ) (connector (pt 512 1056) (pt 752 1056) ) (connector (pt 736 1072) (pt 736 1104) ) (connector (pt 752 1056) (pt 752 1096) ) (connector (text "iorq" (rect 886 1088 903 1100)(font "Arial" )) (pt 832 1104) (pt 904 1104) ) (connector (pt 736 1104) (pt 768 1104) ) (connector (pt 720 1112) (pt 768 1112) ) (connector (pt 752 1096) (pt 768 1096) ) (connector (pt 384 720) (pt 432 720) ) (connector (pt 320 720) (pt 208 720) ) (connector (pt 752 1632) (pt 768 1632) ) (connector (text "m1_mreq" (rect 618 1608 664 1620)(font "Arial" )) (pt 688 1624) (pt 608 1624) ) (connector (pt 752 1696) (pt 768 1696) ) (connector (text "m1_mreq" (rect 617 1544 663 1556)(font "Arial" )) (pt 688 1560) (pt 608 1560) ) (connector (text "mwr_wr" (rect 617 1672 653 1684)(font "Arial" )) (pt 688 1688) (pt 608 1688) ) (connector (text "mrd_mreq" (rect 536 1552 585 1564)(font "Arial" )) (pt 528 1568) (pt 688 1568) ) (connector (text "mwr_mreq" (rect 455 1560 505 1572)(font "Arial" )) (pt 448 1576) (pt 688 1576) ) (connector (text "mrd_mreq" (rect 534 1616 583 1628)(font "Arial" )) (pt 528 1632) (pt 688 1632) ) (connector (text "ioRead" (rect 455 1624 489 1636)(font "Arial" )) (pt 448 1640) (pt 688 1640) ) (connector (text "ioWrite" (rect 537 1688 571 1700)(font "Arial" )) (pt 528 1704) (pt 688 1704) ) (connector (text "nMEMRQ_int" (rect 834 1552 897 1564)(font "Arial" )) (pt 752 1568) (pt 896 1568) ) (connector (pt 752 1760) (pt 768 1760) ) (connector (text "iorq" (rect 617 1736 634 1748)(font "Arial" )) (pt 608 1752) (pt 688 1752) ) (connector (text "intr_iorq" (rect 536 1752 574 1764)(font "Arial" )) (pt 528 1768) (pt 688 1768) ) (connector (pt 208 1416) (pt 296 1416) ) (connector (pt 392 1504) (pt 392 1448) ) (connector (pt 384 1376) (pt 384 1416) ) (connector (pt 392 1448) (pt 408 1448) ) (connector (pt 488 1376) (pt 488 1400) ) (connector (pt 472 1416) (pt 504 1416) ) (connector (pt 488 1400) (pt 504 1400) ) (connector (text "intr_iorq" (rect 635 1392 673 1404)(font "Arial" )) (pt 568 1408) (pt 672 1408) ) (connector (pt 480 1264) (pt 480 1312) ) (connector (text "ioRead" (rect 638 1256 672 1268)(font "Arial" )) (pt 568 1272) (pt 672 1272) ) (connector (text "ioWrite" (rect 641 1304 675 1316)(font "Arial" )) (pt 568 1320) (pt 672 1320) ) (connector (pt 480 1264) (pt 504 1264) ) (connector (pt 208 1280) (pt 504 1280) ) (connector (pt 208 1328) (pt 504 1328) ) (connector (pt 720 656) (pt 208 656) ) (connector (pt 720 528) (pt 736 528) ) (connector (pt 720 656) (pt 720 528) ) (connector (pt 704 512) (pt 736 512) ) (connector (text "m1_mreq" (rect 821 504 867 516)(font "Arial" )) (pt 800 520) (pt 864 520) ) (connector (pt 496 520) (pt 512 520) ) (connector (pt 512 520) (pt 544 520) ) (connector (pt 496 720) (pt 512 720) ) (connector (pt 512 720) (pt 544 720) ) (connector (pt 496 1112) (pt 512 1112) ) (connector (pt 512 1112) (pt 544 1112) ) (connector (pt 608 1112) (pt 624 1112) ) (connector (pt 624 1112) (pt 656 1112) ) (connector (pt 512 680) (pt 624 680) ) (connector (text "wait_mrd" (rect 738 664 781 676)(font "Arial" )) (pt 624 680) (pt 776 680) ) (connector (pt 360 1416) (pt 384 1416) ) (connector (pt 384 1416) (pt 408 1416) ) (connector (text "iorq" (rect 408 1296 425 1308)(font "Arial" )) (pt 400 1312) (pt 480 1312) ) (connector (pt 480 1312) (pt 504 1312) ) (connector (text "nreset" (rect 176 624 206 636)(font "Arial" )) (pt 168 640) (pt 464 640) ) (connector (pt 464 640) (pt 576 640) ) (connector (text "nreset" (rect 174 808 204 820)(font "Arial" )) (pt 168 824) (pt 352 824) ) (connector (text "nreset" (rect 174 1008 204 1020)(font "Arial" )) (pt 168 1024) (pt 352 1024) ) (connector (pt 352 1024) (pt 464 1024) ) (connector (pt 464 1024) (pt 576 1024) ) (connector (text "nreset" (rect 176 1216 206 1228)(font "Arial" )) (pt 168 1232) (pt 352 1232) ) (connector (pt 352 1232) (pt 464 1232) ) (connector (pt 464 1232) (pt 576 1232) ) (connector (pt 576 1232) (pt 688 1232) ) (connector (text "nreset" (rect 175 1520 205 1532)(font "Arial" )) (pt 168 1536) (pt 328 1536) ) (connector (pt 328 1536) (pt 440 1536) ) (connector (pt 464 576) (pt 464 640) ) (connector (pt 576 576) (pt 576 640) ) (connector (pt 352 776) (pt 352 824) ) (connector (pt 352 976) (pt 352 1024) ) (connector (pt 464 976) (pt 464 1024) ) (connector (pt 576 976) (pt 576 1024) ) (connector (pt 352 1168) (pt 352 1232) ) (connector (pt 464 1168) (pt 464 1232) ) (connector (pt 576 1168) (pt 576 1232) ) (connector (pt 688 1168) (pt 688 1232) ) (connector (pt 328 1472) (pt 328 1536) ) (connector (pt 440 1472) (pt 440 1536) ) (connector (pt 352 496) (pt 352 480) ) (connector (text "nreset" (rect 174 464 204 476)(font "Arial" )) (pt 352 480) (pt 168 480) ) (connector (pt 624 920) (pt 624 896) ) (connector (pt 512 920) (pt 512 880) ) (connector (pt 624 896) (pt 640 896) ) (connector (text "mwr_mreq" (rect 725 872 775 884)(font "Arial" )) (pt 704 888) (pt 776 888) ) (connector (pt 608 920) (pt 624 920) ) (connector (text "mwr_wr" (rect 739 904 775 916)(font "Arial" )) (pt 624 920) (pt 776 920) ) (connector (pt 496 920) (pt 512 920) ) (connector (pt 512 920) (pt 544 920) ) (connector (pt 464 776) (pt 464 824) ) (connector (pt 576 776) (pt 576 824) ) (connector (pt 352 824) (pt 464 824) ) (connector (pt 464 824) (pt 576 824) ) (connector (pt 624 880) (pt 624 856) ) (connector (text "wait_mwr" (rect 727 840 771 852)(font "Arial" )) (pt 776 856) (pt 624 856) ) (connector (pt 512 880) (pt 624 880) ) (connector (pt 624 880) (pt 640 880) ) (connector (pt 448 144) (pt 416 144) (color 84 84 252) ) (connector (pt 560 144) (pt 528 144) (color 84 84 252) ) (connector (pt 208 144) (pt 248 144) (color 84 84 252) ) (connector (pt 528 144) (pt 528 200) (color 84 84 252) ) (connector (pt 416 144) (pt 416 200) (color 84 84 252) ) (connector (pt 248 200) (pt 416 200) (color 84 84 252) ) (connector (pt 416 200) (pt 528 200) (color 84 84 252) ) (connector (pt 248 144) (pt 320 144) (color 84 84 252) ) (connector (pt 272 256) (pt 272 248) (color 84 84 252) ) (connector (pt 272 248) (pt 248 248) (color 84 84 252) ) (connector (pt 544 536) (pt 512 536) (color 84 84 252) ) (connector (pt 248 608) (pt 512 608) (color 84 84 252) ) (connector (pt 512 536) (pt 512 608) (color 84 84 252) ) (connector (pt 248 736) (pt 320 736) (color 84 84 252) ) (connector (pt 248 936) (pt 320 936) (color 84 84 252) ) (connector (pt 248 1128) (pt 320 1128) (color 84 84 252) ) (connector (pt 432 1128) (pt 400 1128) (color 84 84 252) ) (connector (pt 248 1184) (pt 400 1184) (color 84 84 252) ) (connector (pt 400 1128) (pt 400 1184) (color 84 84 252) ) (connector (pt 376 1432) (pt 376 1488) (color 84 84 252) ) (connector (pt 248 1488) (pt 376 1488) (color 84 84 252) ) (connector (pt 376 1432) (pt 408 1432) (color 84 84 252) ) (connector (pt 248 144) (pt 248 200) (color 84 84 252) ) (connector (pt 248 200) (pt 248 248) (color 84 84 252) ) (connector (pt 248 248) (pt 248 608) (color 84 84 252) ) (connector (pt 248 608) (pt 248 736) (color 84 84 252) ) (connector (pt 248 736) (pt 248 936) (color 84 84 252) ) (connector (pt 248 936) (pt 248 1128) (color 84 84 252) ) (connector (pt 248 1128) (pt 248 1184) (color 84 84 252) ) (connector (pt 248 1184) (pt 248 1488) (color 84 84 252) ) (connector (pt 272 320) (pt 320 320) (color 250 0 0) ) (connector (pt 448 320) (pt 416 320) (color 250 0 0) ) (connector (pt 416 320) (pt 416 376) (color 250 0 0) ) (connector (pt 272 376) (pt 416 376) (color 250 0 0) ) (connector (pt 272 536) (pt 320 536) (color 250 0 0) ) (connector (pt 432 536) (pt 400 536) (color 250 0 0) ) (connector (pt 272 592) (pt 400 592) (color 250 0 0) ) (connector (pt 400 536) (pt 400 592) (color 250 0 0) ) (connector (pt 432 736) (pt 400 736) (color 250 0 0) ) (connector (pt 544 736) (pt 512 736) (color 250 0 0) ) (connector (pt 432 936) (pt 400 936) (color 250 0 0) ) (connector (pt 544 936) (pt 512 936) (color 250 0 0) ) (connector (pt 544 1128) (pt 512 1128) (color 250 0 0) ) (connector (pt 656 1128) (pt 624 1128) (color 250 0 0) ) (connector (pt 512 1128) (pt 512 1200) (color 250 0 0) ) (connector (pt 624 1128) (pt 624 1200) (color 250 0 0) ) (connector (pt 400 936) (pt 400 992) (color 250 0 0) ) (connector (pt 512 936) (pt 512 992) (color 250 0 0) ) (connector (pt 400 736) (pt 400 792) (color 250 0 0) ) (connector (pt 512 736) (pt 512 792) (color 250 0 0) ) (connector (pt 272 1432) (pt 296 1432) (color 250 0 0) ) (connector (pt 272 1200) (pt 512 1200) (color 250 0 0) ) (connector (pt 512 1200) (pt 624 1200) (color 250 0 0) ) (connector (pt 272 992) (pt 400 992) (color 250 0 0) ) (connector (pt 400 992) (pt 512 992) (color 250 0 0) ) (connector (pt 272 792) (pt 400 792) (color 250 0 0) ) (connector (pt 400 792) (pt 512 792) (color 250 0 0) ) (connector (pt 272 304) (pt 272 320) (color 250 0 0) ) (connector (pt 272 320) (pt 272 376) (color 250 0 0) ) (connector (pt 272 376) (pt 272 536) (color 250 0 0) ) (connector (pt 272 536) (pt 272 592) (color 250 0 0) ) (connector (pt 272 592) (pt 272 792) (color 250 0 0) ) (connector (pt 272 792) (pt 272 992) (color 250 0 0) ) (connector (pt 272 992) (pt 272 1200) (color 250 0 0) ) (connector (pt 272 1200) (pt 272 1432) (color 250 0 0) ) (connector (pt 752 1832) (pt 768 1832) ) (connector (text "wait_mwr" (rect 532 1808 576 1820)(font "Arial" )) (pt 528 1824) (pt 688 1824) ) (connector (text "wait_mrd" (rect 612 1792 655 1804)(font "Arial" )) (pt 608 1808) (pt 688 1808) ) (connector (pt 784 192) (pt 800 192) ) (connector (pt 720 184) (pt 704 184) ) (connector (pt 704 88) (pt 704 112) ) (connector (pt 704 112) (pt 704 184) ) (connector (pt 592 200) (pt 640 200) ) (connector (pt 592 184) (pt 592 200) ) (connector (pt 592 200) (pt 592 232) ) (connector (pt 688 200) (pt 720 200) ) (connector (pt 512 480) (pt 624 480) ) (connector (text "wait_m1" (rect 752 464 792 476)(font "Arial" )) (pt 624 480) (pt 800 480) ) (connector (text "wait_m1" (rect 377 1840 417 1852)(font "Arial" )) (pt 376 1856) (pt 688 1856) ) (connector (pt 560 160) (pt 544 160) (color 76 152 0) ) (connector (pt 448 160) (pt 432 160) (color 76 152 0) ) (connector (pt 448 336) (pt 432 336) (color 76 152 0) ) (connector (pt 224 160) (pt 320 160) (color 76 152 0) ) (connector (pt 320 336) (pt 304 336) (color 76 152 0) ) (connector (pt 432 336) (pt 432 392) (color 76 152 0) ) (connector (pt 304 336) (pt 304 392) (color 76 152 0) ) (connector (pt 224 392) (pt 304 392) (color 76 152 0) ) (connector (pt 304 392) (pt 432 392) (color 76 152 0) ) (connector (pt 544 160) (pt 544 216) (color 76 152 0) ) (connector (pt 432 160) (pt 432 216) (color 76 152 0) ) (connector (pt 224 216) (pt 432 216) (color 76 152 0) ) (connector (pt 432 216) (pt 544 216) (color 76 152 0) ) (connector (pt 544 552) (pt 536 552) (color 76 152 0) ) (connector (pt 432 552) (pt 416 552) (color 76 152 0) ) (connector (pt 320 552) (pt 304 552) (color 76 152 0) ) (connector (pt 304 552) (pt 304 624) (color 76 152 0) ) (connector (pt 416 552) (pt 416 624) (color 76 152 0) ) (connector (pt 536 552) (pt 536 624) (color 76 152 0) ) (connector (pt 224 560) (pt 208 560) (color 76 152 0) ) (connector (pt 544 752) (pt 528 752) (color 76 152 0) ) (connector (pt 432 752) (pt 416 752) (color 76 152 0) ) (connector (pt 320 752) (pt 304 752) (color 76 152 0) ) (connector (pt 544 952) (pt 528 952) (color 76 152 0) ) (connector (pt 432 952) (pt 416 952) (color 76 152 0) ) (connector (pt 320 952) (pt 304 952) (color 76 152 0) ) (connector (pt 656 1144) (pt 640 1144) (color 76 152 0) ) (connector (pt 544 1144) (pt 528 1144) (color 76 152 0) ) (connector (pt 432 1144) (pt 416 1144) (color 76 152 0) ) (connector (pt 320 1144) (pt 304 1144) (color 76 152 0) ) (connector (pt 640 1144) (pt 640 1216) (color 76 152 0) ) (connector (pt 528 1144) (pt 528 1216) (color 76 152 0) ) (connector (pt 416 1144) (pt 416 1216) (color 76 152 0) ) (connector (pt 304 1144) (pt 304 1216) (color 76 152 0) ) (connector (pt 528 952) (pt 528 1008) (color 76 152 0) ) (connector (pt 416 952) (pt 416 1008) (color 76 152 0) ) (connector (pt 304 952) (pt 304 1008) (color 76 152 0) ) (connector (pt 528 752) (pt 528 808) (color 76 152 0) ) (connector (pt 416 752) (pt 416 808) (color 76 152 0) ) (connector (pt 304 752) (pt 304 808) (color 76 152 0) ) (connector (pt 224 624) (pt 304 624) (color 76 152 0) ) (connector (pt 304 624) (pt 416 624) (color 76 152 0) ) (connector (pt 416 624) (pt 536 624) (color 76 152 0) ) (connector (pt 224 1216) (pt 304 1216) (color 76 152 0) ) (connector (pt 304 1216) (pt 416 1216) (color 76 152 0) ) (connector (pt 416 1216) (pt 528 1216) (color 76 152 0) ) (connector (pt 528 1216) (pt 640 1216) (color 76 152 0) ) (connector (pt 224 1008) (pt 304 1008) (color 76 152 0) ) (connector (pt 304 1008) (pt 416 1008) (color 76 152 0) ) (connector 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(connector (text "wait_io" (rect 793 1352 826 1364)(font "Arial" )) (pt 752 1368) (pt 824 1368) ) (connector (text "wait_iorq" (rect 619 1344 661 1356)(font "Arial" )) (pt 616 1360) (pt 688 1360) ) (connector (pt 208 1504) (pt 392 1504) ) (junction (pt 248 144)) (junction (pt 272 320)) (junction (pt 416 304)) (junction (pt 400 128)) (junction (pt 352 408)) (junction (pt 272 376)) (junction (pt 304 392)) (junction (pt 224 392)) (junction (pt 480 232)) (junction (pt 432 216)) (junction (pt 224 216)) (junction (pt 416 200)) (junction (pt 248 200)) (junction (pt 352 232)) (junction (pt 248 248)) (junction (pt 304 624)) (junction (pt 416 624)) (junction (pt 512 520)) (junction (pt 624 480)) (junction (pt 512 720)) (junction (pt 512 1112)) (junction (pt 624 1112)) (junction (pt 304 1216)) (junction (pt 416 1216)) (junction (pt 528 1216)) (junction (pt 304 1008)) (junction (pt 416 1008)) (junction (pt 304 808)) (junction (pt 416 808)) (junction (pt 224 560)) (junction (pt 624 680)) (junction (pt 512 920)) (junction (pt 624 920)) (junction (pt 224 624)) (junction (pt 224 808)) (junction (pt 224 1008)) (junction (pt 512 1200)) (junction (pt 400 992)) (junction (pt 400 792)) (junction (pt 272 536)) (junction (pt 272 592)) (junction (pt 272 792)) (junction (pt 272 992)) (junction (pt 272 1200)) (junction (pt 384 1416)) (junction (pt 488 1376)) (junction (pt 480 1312)) (junction (pt 248 608)) (junction (pt 248 736)) (junction (pt 248 936)) (junction (pt 248 1128)) (junction (pt 248 1184)) (junction (pt 464 640)) (junction (pt 352 824)) (junction (pt 464 824)) (junction (pt 352 1024)) (junction (pt 464 1024)) (junction (pt 352 1232)) (junction (pt 464 1232)) (junction (pt 576 1232)) (junction (pt 328 1536)) (junction (pt 624 880)) (junction (pt 704 112)) (junction (pt 592 200)) (junction (pt 736 1072)) (text "MREQ DURING REFRESH" (rect 640 248 780 262)(font "Arial" (font_size 8))) (text "STANDARD MEM REQ" (rect 712 408 837 422)(font "Arial" (font_size 8))) (text "Refresh generator logic, USPTO 4,332,008 by Shima et al. FIG. 9A" (rect 40 32 506 48)(font "Arial" (font_size 10))(border)) (text "(End of patented circuit)" (rect 56 424 234 440)(font "Arial" (font_size 10)(bold))) (text "MREQ DURING M1" (rect 736 600 838 614)(font "Arial" (font_size 8))) (text "MEMORY WRITE" (rect 640 936 733 950)(font "Arial" (font_size 8))) (text "IO READ /. WRITE" (rect 736 1216 835 1230)(font "Arial" (font_size 8))) (text "IORQ DURING INTERRUPT ACK" (rect 504 1456 678 1470)(font "Arial" (font_size 8))) (text "MEMORY READ" (rect 640 752 729 766)(font "Arial" (font_size 8))) (line (pt 32 448)(pt 992 448)(color 0 255 0)) (title_block (rect 32 1816 289 1868) (name "title-custom-small") (section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "memory_ifc" (rect 43 2 123 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border)) (section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "November 1, 2014, 2016" (rect 56 3 195 17)(font "Arial" (font_size 8)))(border)) (section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.2" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border)) (drawing ) ) ================================================ FILE: cpu/control/memory_ifc.bsf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "symbol" (version "1.2")) (symbol (rect 16 16 224 272) (text "memory_ifc" (rect 5 0 71 14)(font "Arial" (font_size 8))) (text "inst" (rect 8 240 25 252)(font "Arial" )) (port (pt 0 32) (input) (text "nM1_int" (rect 0 0 43 14)(font "Arial" (font_size 8))) (text "nM1_int" (rect 21 27 64 41)(font "Arial" (font_size 8))) (line (pt 0 32)(pt 16 32)) ) (port (pt 0 48) (input) (text "clk" (rect 0 0 15 14)(font "Arial" (font_size 8))) (text "clk" (rect 21 43 36 57)(font "Arial" (font_size 8))) (line (pt 0 48)(pt 16 48)) ) (port (pt 0 64) (input) (text "nreset" (rect 0 0 36 14)(font "Arial" (font_size 8))) (text "nreset" (rect 21 59 57 73)(font "Arial" (font_size 8))) (line (pt 0 64)(pt 16 64)) ) (port (pt 0 80) (input) (text "setM1" (rect 0 0 34 14)(font "Arial" (font_size 8))) (text "setM1" (rect 21 75 55 89)(font "Arial" (font_size 8))) (line (pt 0 80)(pt 16 80)) ) (port (pt 0 96) (input) (text "timings_en" (rect 0 0 60 14)(font "Arial" (font_size 8))) (text "timings_en" (rect 21 91 81 105)(font "Arial" (font_size 8))) (line (pt 0 96)(pt 16 96)) ) (port (pt 0 112) (input) (text "in_intr" (rect 0 0 34 14)(font "Arial" (font_size 8))) (text "in_intr" (rect 21 107 55 121)(font "Arial" (font_size 8))) (line (pt 0 112)(pt 16 112)) ) (port (pt 0 128) (input) (text "ctl_mRead" (rect 0 0 59 14)(font "Arial" (font_size 8))) (text "ctl_mRead" (rect 21 123 80 137)(font "Arial" (font_size 8))) (line (pt 0 128)(pt 16 128)) ) (port (pt 0 144) (input) (text "ctl_mWrite" (rect 0 0 59 14)(font "Arial" (font_size 8))) (text "ctl_mWrite" (rect 21 139 80 153)(font "Arial" (font_size 8))) (line (pt 0 144)(pt 16 144)) ) (port (pt 0 160) (input) (text "ctl_iorw" (rect 0 0 46 14)(font "Arial" (font_size 8))) (text "ctl_iorw" (rect 21 155 67 169)(font "Arial" (font_size 8))) (line (pt 0 160)(pt 16 160)) ) (port (pt 0 176) (input) (text "fIORead" (rect 0 0 46 14)(font "Arial" (font_size 8))) (text "fIORead" (rect 21 171 67 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"latch_wait" (rect 0 0 59 14)(font "Arial" (font_size 8))) (text "latch_wait" (rect 128 139 187 153)(font "Arial" (font_size 8))) (line (pt 208 144)(pt 192 144)) ) (drawing (rectangle (rect 16 16 192 240)) ) ) ================================================ FILE: cpu/control/memory_ifc.v ================================================ // Copyright (C) 1991-2013 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // PROGRAM "Quartus II 64-Bit" // VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" // CREATED "Sun Dec 09 19:14:29 2018" module memory_ifc( clk, nM1_int, ctl_mRead, ctl_mWrite, in_intr, nreset, fIORead, fIOWrite, setM1, ctl_iorw, timings_en, iorq_Tw, nhold_clk_wait, nM1_out, nRFSH_out, nMREQ_out, nRD_out, nWR_out, nIORQ_out, latch_wait, wait_m1 ); input wire clk; input wire nM1_int; input wire ctl_mRead; input wire ctl_mWrite; input wire in_intr; input wire nreset; input wire fIORead; input wire fIOWrite; input wire setM1; input wire ctl_iorw; input wire timings_en; input wire iorq_Tw; input wire nhold_clk_wait; output wire nM1_out; output wire nRFSH_out; output wire nMREQ_out; output wire nRD_out; output wire nWR_out; output wire nIORQ_out; output wire latch_wait; output wire wait_m1; wire intr_iorq; wire ioRead; wire iorq; wire ioWrite; wire m1_mreq; wire mrd_mreq; wire mwr_mreq; reg mwr_wr; wire nMEMRQ_int; wire nq2; reg q1; reg q2; wire wait_io; reg wait_iorq; reg wait_iorqinta; reg wait_m_ALTERA_SYNTHESIZED1; reg wait_mrd; reg wait_mwr; wire SYNTHESIZED_WIRE_0; reg DFFE_m1_ff3; wire SYNTHESIZED_WIRE_1; reg DFFE_iorq_ff4; reg SYNTHESIZED_WIRE_15; reg DFFE_mrd_ff3; reg DFFE_intr_ff3; wire SYNTHESIZED_WIRE_2; reg SYNTHESIZED_WIRE_16; wire SYNTHESIZED_WIRE_3; reg SYNTHESIZED_WIRE_17; wire SYNTHESIZED_WIRE_18; reg DFFE_iorq_ff1; reg DFFE_m1_ff1; reg DFFE_mrd_ff1; reg DFFE_mwr_ff1; reg DFFE_mreq_ff2; assign nMREQ_out = SYNTHESIZED_WIRE_0 & nMEMRQ_int; assign ioRead = iorq & fIORead; assign SYNTHESIZED_WIRE_1 = ~(DFFE_m1_ff3 | wait_m_ALTERA_SYNTHESIZED1); assign m1_mreq = ~(in_intr | SYNTHESIZED_WIRE_1); assign iorq = wait_iorq | DFFE_iorq_ff4 | SYNTHESIZED_WIRE_15; assign ioWrite = iorq & fIOWrite; assign latch_wait = wait_mrd | wait_io | wait_m_ALTERA_SYNTHESIZED1 | wait_mwr; assign nMEMRQ_int = ~(m1_mreq | mrd_mreq | mwr_mreq); assign nRD_out = ~(m1_mreq | mrd_mreq | ioRead); assign mrd_mreq = DFFE_mrd_ff3 | wait_mrd; assign nWR_out = ~(ioWrite | mwr_wr); assign mwr_mreq = mwr_wr | wait_mwr; assign nIORQ_out = ~(intr_iorq | iorq); assign wait_io = wait_iorqinta | wait_iorq; assign intr_iorq = DFFE_intr_ff3 | wait_iorqinta; assign nM1_out = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_16; assign SYNTHESIZED_WIRE_0 = ~(SYNTHESIZED_WIRE_3 & SYNTHESIZED_WIRE_17); assign nRFSH_out = ~(nq2 & SYNTHESIZED_WIRE_16); always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset) begin if (!nreset) begin wait_iorqinta <= 0; end else begin wait_iorqinta <= iorq_Tw; end end always@(posedge clk or negedge nreset) begin if (!nreset) begin DFFE_intr_ff3 <= 0; end else if (nhold_clk_wait) begin DFFE_intr_ff3 <= wait_iorqinta; end end always@(posedge clk or negedge nreset) begin if (!nreset) begin DFFE_iorq_ff1 <= 0; end else if (timings_en) begin DFFE_iorq_ff1 <= ctl_iorw; end end always@(posedge clk or negedge nreset) begin if (!nreset) begin SYNTHESIZED_WIRE_15 <= 0; end else if (timings_en) begin SYNTHESIZED_WIRE_15 <= DFFE_iorq_ff1; end end always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset) begin if (!nreset) begin wait_iorq <= 0; end else if (timings_en) begin wait_iorq <= SYNTHESIZED_WIRE_15; end end always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset) begin if (!nreset) begin DFFE_iorq_ff4 <= 0; end else if (timings_en) begin DFFE_iorq_ff4 <= wait_iorq; end end always@(posedge clk or negedge nreset) begin if (!nreset) begin SYNTHESIZED_WIRE_16 <= 0; end else if (timings_en) begin SYNTHESIZED_WIRE_16 <= nM1_int; end end always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset) begin if (!nreset) begin DFFE_m1_ff1 <= 1; end else if (timings_en) begin DFFE_m1_ff1 <= setM1; end end always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset) begin if (!nreset) begin wait_m_ALTERA_SYNTHESIZED1 <= 0; end else if (timings_en) begin wait_m_ALTERA_SYNTHESIZED1 <= DFFE_m1_ff1; end end always@(posedge clk or negedge nreset) begin if (!nreset) begin DFFE_m1_ff3 <= 0; end else if (timings_en) begin DFFE_m1_ff3 <= wait_m_ALTERA_SYNTHESIZED1; end end always@(posedge clk or negedge nreset) begin if (!nreset) begin DFFE_mrd_ff1 <= 0; end else if (timings_en) begin DFFE_mrd_ff1 <= ctl_mRead; end end always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset) begin if (!nreset) begin wait_mrd <= 0; end else if (timings_en) begin wait_mrd <= DFFE_mrd_ff1; end end always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset) begin if (!nreset) begin DFFE_mrd_ff3 <= 0; end else if (timings_en) begin DFFE_mrd_ff3 <= wait_mrd; end end always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset) begin if (!nreset) begin SYNTHESIZED_WIRE_17 <= 0; end else if (timings_en) begin SYNTHESIZED_WIRE_17 <= SYNTHESIZED_WIRE_16; end end always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset) begin if (!nreset) begin DFFE_mreq_ff2 <= 0; end else if (timings_en) begin DFFE_mreq_ff2 <= SYNTHESIZED_WIRE_17; end end always@(posedge clk or negedge nreset) begin if (!nreset) begin DFFE_mwr_ff1 <= 0; end else if (timings_en) begin DFFE_mwr_ff1 <= ctl_mWrite; end end always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset) begin if (!nreset) begin wait_mwr <= 0; end else if (timings_en) begin wait_mwr <= DFFE_mwr_ff1; end end always@(posedge SYNTHESIZED_WIRE_18 or negedge nreset) begin if (!nreset) begin mwr_wr <= 0; end else if (timings_en) begin mwr_wr <= wait_mwr; end end assign SYNTHESIZED_WIRE_18 = ~clk; assign nq2 = ~q2; assign SYNTHESIZED_WIRE_2 = ~nreset; assign SYNTHESIZED_WIRE_3 = ~DFFE_mreq_ff2; always@(posedge clk or negedge nreset) begin if (!nreset) begin q1 <= 0; end else if (timings_en) begin q1 <= SYNTHESIZED_WIRE_16; end end always@(posedge clk or negedge nreset) begin if (!nreset) begin q2 <= 0; end else if (timings_en) begin q2 <= q1; end end assign wait_m1 = wait_m_ALTERA_SYNTHESIZED1; endmodule ================================================ FILE: cpu/control/pin_control.bdf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "graphic" (version "1.4")) (pin (input) (rect 32 112 208 128) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "fFetch" (rect 9 0 42 12)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) (line (pt 121 8)(pt 176 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) ) (pin (input) (rect 32 128 208 144) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "fMRead" (rect 9 0 47 12)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) (line (pt 121 8)(pt 176 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) ) (pin (input) (rect 32 144 208 160) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) 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(pt 344 72) ) (connector (pt 344 72) (pt 384 72) ) (connector (pt 208 88) (pt 360 88) ) (connector (pt 360 88) (pt 600 88) ) (junction (pt 384 328)) (junction (pt 264 296)) (junction (pt 264 400)) (junction (pt 296 328)) (junction (pt 296 512)) (junction (pt 248 280)) (junction (pt 248 632)) (junction (pt 280 312)) (junction (pt 280 680)) (junction (pt 232 224)) (junction (pt 232 264)) (junction (pt 232 584)) (junction (pt 384 72)) (junction (pt 344 440)) (junction (pt 328 424)) (junction (pt 328 568)) (junction (pt 328 480)) (junction (pt 344 488)) (junction (pt 360 88)) (junction (pt 480 40)) (junction (pt 344 72)) (junction (pt 328 56)) (text "bus_ab_pin_we = (fFetch & (T1 | T3)) |\n (fMRead & (T1)) |\n (fMWrite & (T1)) |\n (fIORead & (T1)) |\n (fIOWrite & (T1));\n" (rect 624 296 851 380)(font "Arial" (color 170 0 0)(font_size 8))) (text "bus_db_pin_oe = (fFetch & 1'h0) |\n (fMRead & 1'h0) |\n (fMWrite & (T2 | T3)) |\n (fIORead & 1'h0) |\n (fIOWrite & (T2 | T3 | T4));\n" (rect 608 496 834 580)(font "Arial" (color 170 0 0)(font_size 8))) (text "bus_db_pin_re = (fFetch & (T2)) |\n (fMRead & (T2)) |\n (fMWrite & 1'h0) |\n (fIORead & (T3)) |\n (fIOWrite & 1'h0);" (rect 608 664 805 734)(font "Arial" (color 170 0 0)(font_size 8))) (title_block (rect 32 720 289 772) (name "title-custom-small") (section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "pin_control" (rect 43 2 118 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border)) (section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "November 16, 2014" (rect 56 3 166 17)(font "Arial" (font_size 8)))(border)) (section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.0" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border)) (drawing ) ) ================================================ FILE: cpu/control/pin_control.bsf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "symbol" (version "1.2")) (symbol (rect 16 16 208 208) (text "pin_control" (rect 5 0 67 14)(font "Arial" (font_size 8))) (text "inst" (rect 8 176 25 188)(font "Arial" )) (port (pt 0 32) (input) (text "T1" (rect 0 0 14 14)(font "Arial" (font_size 8))) (text "T1" (rect 21 27 35 41)(font "Arial" (font_size 8))) (line (pt 0 32)(pt 16 32)) ) (port (pt 0 48) (input) (text "T2" (rect 0 0 14 14)(font "Arial" (font_size 8))) (text "T2" (rect 21 43 35 57)(font "Arial" (font_size 8))) (line (pt 0 48)(pt 16 48)) ) (port (pt 0 64) (input) (text "T3" (rect 0 0 14 14)(font "Arial" (font_size 8))) (text "T3" (rect 21 59 35 73)(font "Arial" (font_size 8))) (line (pt 0 64)(pt 16 64)) ) (port (pt 0 80) (input) (text "T4" (rect 0 0 14 14)(font "Arial" (font_size 8))) (text "T4" (rect 21 75 35 89)(font "Arial" (font_size 8))) (line (pt 0 80)(pt 16 80)) ) (port (pt 0 96) (input) (text "fFetch" (rect 0 0 36 14)(font "Arial" (font_size 8))) (text "fFetch" (rect 21 91 57 105)(font "Arial" (font_size 8))) (line (pt 0 96)(pt 16 96)) ) (port (pt 0 112) (input) (text "fMRead" (rect 0 0 43 14)(font "Arial" (font_size 8))) (text "fMRead" (rect 21 107 64 121)(font "Arial" (font_size 8))) (line (pt 0 112)(pt 16 112)) ) (port (pt 0 128) (input) (text "fMWrite" (rect 0 0 43 14)(font "Arial" (font_size 8))) (text "fMWrite" (rect 21 123 64 137)(font "Arial" (font_size 8))) (line (pt 0 128)(pt 16 128)) ) (port (pt 0 144) (input) (text "fIORead" (rect 0 0 46 14)(font "Arial" (font_size 8))) (text "fIORead" (rect 21 139 67 153)(font "Arial" (font_size 8))) (line (pt 0 144)(pt 16 144)) ) (port (pt 0 160) (input) (text "fIOWrite" (rect 0 0 46 14)(font "Arial" (font_size 8))) (text "fIOWrite" (rect 21 155 67 169)(font "Arial" (font_size 8))) (line (pt 0 160)(pt 16 160)) ) (port (pt 192 32) (output) (text "bus_ab_pin_we" (rect 0 0 92 14)(font "Arial" (font_size 8))) (text "bus_ab_pin_we" (rect 79 27 171 41)(font "Arial" (font_size 8))) (line (pt 192 32)(pt 176 32)) ) (port (pt 192 48) (output) (text "bus_db_pin_oe" (rect 0 0 87 14)(font "Arial" (font_size 8))) (text "bus_db_pin_oe" (rect 84 43 171 57)(font "Arial" (font_size 8))) (line (pt 192 48)(pt 176 48)) ) (port (pt 192 64) (output) (text "bus_db_pin_re" (rect 0 0 84 14)(font "Arial" (font_size 8))) (text "bus_db_pin_re" (rect 87 59 171 73)(font "Arial" (font_size 8))) (line (pt 192 64)(pt 176 64)) ) (drawing (rectangle (rect 16 16 176 176)) ) ) ================================================ FILE: cpu/control/pin_control.v ================================================ // Copyright (C) 1991-2013 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // PROGRAM "Quartus II 64-Bit" // VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" // CREATED "Sun Nov 16 21:18:37 2014" module pin_control( fFetch, fMRead, fMWrite, fIORead, fIOWrite, T1, T2, T3, T4, bus_ab_pin_we, bus_db_pin_oe, bus_db_pin_re ); input wire fFetch; input wire fMRead; input wire fMWrite; input wire fIORead; input wire fIOWrite; input wire T1; input wire T2; input wire T3; input wire T4; output wire bus_ab_pin_we; output wire bus_db_pin_oe; output wire bus_db_pin_re; wire SYNTHESIZED_WIRE_0; wire SYNTHESIZED_WIRE_1; wire SYNTHESIZED_WIRE_2; wire SYNTHESIZED_WIRE_3; wire SYNTHESIZED_WIRE_4; wire SYNTHESIZED_WIRE_5; wire SYNTHESIZED_WIRE_6; wire SYNTHESIZED_WIRE_7; wire SYNTHESIZED_WIRE_8; wire SYNTHESIZED_WIRE_9; assign SYNTHESIZED_WIRE_9 = fFetch | fMWrite | fMRead | fIORead | fIOWrite | fIOWrite; assign SYNTHESIZED_WIRE_7 = T3 | T2; assign bus_db_pin_oe = SYNTHESIZED_WIRE_0 | SYNTHESIZED_WIRE_1; assign SYNTHESIZED_WIRE_3 = T3 & fIORead; assign bus_db_pin_re = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_3 | SYNTHESIZED_WIRE_4; assign bus_ab_pin_we = SYNTHESIZED_WIRE_5 | SYNTHESIZED_WIRE_6; assign SYNTHESIZED_WIRE_8 = T2 | T3 | T4; assign SYNTHESIZED_WIRE_1 = fMWrite & SYNTHESIZED_WIRE_7; assign SYNTHESIZED_WIRE_0 = SYNTHESIZED_WIRE_8 & fIOWrite; assign SYNTHESIZED_WIRE_4 = T2 & fFetch; assign SYNTHESIZED_WIRE_2 = T2 & fMRead; assign SYNTHESIZED_WIRE_6 = T3 & fFetch; assign SYNTHESIZED_WIRE_5 = T1 & SYNTHESIZED_WIRE_9; endmodule ================================================ FILE: cpu/control/pla_decode.bsf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "symbol" (version "1.1")) (symbol (rect 16 16 208 96) (text "pla_decode" (rect 5 0 49 12)(font "Arial" )) (text "inst" (rect 8 64 20 76)(font "Arial" )) (port (pt 0 32) (input) (text "opcode[7..0]" (rect 0 0 48 12)(font "Arial" )) (text "opcode[7..0]" (rect 21 27 69 39)(font "Arial" )) (line (pt 0 32)(pt 16 32)(line_width 3)) ) (port (pt 0 48) (input) (text "prefix[6..0]" (rect 0 0 42 12)(font "Arial" )) (text "prefix[6..0]" (rect 21 43 63 55)(font "Arial" )) (line (pt 0 48)(pt 16 48)(line_width 3)) ) (port (pt 192 32) (output) (text "pla[104..0]" (rect 0 0 40 12)(font "Arial" )) (text "pla[104..0]" (rect 131 27 171 39)(font "Arial" )) (line (pt 192 32)(pt 176 32)(line_width 3)) ) (drawing (rectangle (rect 16 16 176 64)(line_width 1)) ) ) ================================================ FILE: cpu/control/pla_decode.v ================================================ //===================================================================================== // This file is automatically generated by the z80_pla_checker tool. Do not edit! //===================================================================================== module pla_decode ( input wire [6:0] prefix, input wire [7:0] opcode, output wire [104:0] pla ); assign pla[ 0] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11110100) == 15'b0000001_10100000) ? 1'b1 : 1'b0; // ldx/cpx/inx/outx brk assign pla[ 1] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11011001) ? 1'b1 : 1'b0; // exx assign pla[ 2] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11101011) ? 1'b1 : 1'b0; // ex de,hl assign pla[ 3] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11011111) == 15'b0000100_11011101) ? 1'b1 : 1'b0; // IX/IY prefix assign pla[ 5] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11111001) ? 1'b1 : 1'b0; // ld sp,hl assign pla[ 6] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11101001) ? 1'b1 : 1'b0; // jp hl assign pla[ 7] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11001111) == 15'b0000100_00000001) ? 1'b1 : 1'b0; // ld rr,nn assign pla[ 8] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11100111) == 15'b0000100_00000010) ? 1'b1 : 1'b0; // ld (rr),a/a,(rr) assign pla[ 9] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_00000011) ? 1'b1 : 1'b0; // inc/dec rr assign pla[ 10] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11100011) ? 1'b1 : 1'b0; // ex (sp),hl assign pla[ 11] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11100111) == 15'b0000001_10100001) ? 1'b1 : 1'b0; // cpi/cpir/cpd/cpdr assign pla[ 12] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11100111) == 15'b0000001_10100000) ? 1'b1 : 1'b0; // ldi/ldir/ldd/lddr assign pla[ 13] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11001111) == 15'b0000100_00000010) ? 1'b1 : 1'b0; // ld direction assign pla[ 15] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11110111) == 15'b0000001_01100111) ? 1'b1 : 1'b0; // rrd/rld assign pla[ 16] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11001111) == 15'b0000100_11000101) ? 1'b1 : 1'b0; // push rr assign pla[ 17] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_00000110) ? 1'b1 : 1'b0; // ld r,n assign pla[ 20] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11100111) == 15'b0000001_10100011) ? 1'b1 : 1'b0; // outx/otxr assign pla[ 21] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11100111) == 15'b0000001_10100010) ? 1'b1 : 1'b0; // inx/inxr assign pla[ 23] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11001011) == 15'b0000100_11000001) ? 1'b1 : 1'b0; // push/pop assign pla[ 24] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11001101) ? 1'b1 : 1'b0; // call nn assign pla[ 25] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11100111) == 15'b0000100_00000111) ? 1'b1 : 1'b0; // rlca/rla/rrca/rra assign pla[ 26] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00010000) ? 1'b1 : 1'b0; // djnz e assign pla[ 27] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11000110) == 15'b0000001_01000000) ? 1'b1 : 1'b0; // in/out r,(c) assign pla[ 28] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11010011) ? 1'b1 : 1'b0; // out (n),a assign pla[ 29] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11000011) ? 1'b1 : 1'b0; // jp nn assign pla[ 30] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11110111) == 15'b0000100_00100010) ? 1'b1 : 1'b0; // ld hl,(nn)/(nn),hl assign pla[ 31] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11000111) == 15'b0000001_01000011) ? 1'b1 : 1'b0; // ld rr,(nn)/(nn),rr assign pla[ 33] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11001111) == 15'b0000001_01000011) ? 1'b1 : 1'b0; // ld direction assign pla[ 34] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11000111) == 15'b0000001_01000001) ? 1'b1 : 1'b0; // out (c),r assign pla[ 35] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11001001) ? 1'b1 : 1'b0; // ret assign pla[ 37] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11110111) == 15'b0000100_11010011) ? 1'b1 : 1'b0; // out (n),a/a,(n) assign pla[ 38] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11110111) == 15'b0000100_00110010) ? 1'b1 : 1'b0; // ld (nn),a/a,(nn) assign pla[ 39] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00001000) ? 1'b1 : 1'b0; // ex af,af' assign pla[ 40] = (({prefix[6:0], opcode[7:0]} & 15'b0100100_11111111) == 15'b0100100_00110110) ? 1'b1 : 1'b0; // ld (ix+d),n assign pla[ 42] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_11000100) ? 1'b1 : 1'b0; // call cc,nn assign pla[ 43] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_11000010) ? 1'b1 : 1'b0; // jp cc,nn assign pla[ 44] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11001011) ? 1'b1 : 1'b0; // CB prefix assign pla[ 45] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_11000000) ? 1'b1 : 1'b0; // ret cc assign pla[ 46] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11000111) == 15'b0000001_01000101) ? 1'b1 : 1'b0; // reti/retn assign pla[ 47] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00011000) ? 1'b1 : 1'b0; // jr e assign pla[ 48] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11100111) == 15'b0000100_00100000) ? 1'b1 : 1'b0; // jr ss,e assign pla[ 49] = (({prefix[6:0], opcode[7:0]} & 15'b0100000_11111111) == 15'b0100000_11001011) ? 1'b1 : 1'b0; // CB prefix with IX/IY assign pla[ 50] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00110110) ? 1'b1 : 1'b0; // ld (hl),n assign pla[ 51] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_11101101) ? 1'b1 : 1'b0; // ED prefix assign pla[ 52] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_10000110) ? 1'b1 : 1'b0; // add/sub/and/or/xor/cp (hl) assign pla[ 53] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111110) == 15'b0000100_00110100) ? 1'b1 : 1'b0; // inc/dec (hl) assign pla[ 55] = (({prefix[6:0], opcode[7:0]} & 15'b0000010_00000111) == 15'b0000010_00000110) ? 1'b1 : 1'b0; // Every CB op (hl) assign pla[ 56] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_11000111) ? 1'b1 : 1'b0; // rst p assign pla[ 57] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11110111) == 15'b0000001_01000111) ? 1'b1 : 1'b0; // ld i,a/r,a assign pla[ 58] = (({prefix[6:0], opcode[7:0]} & 15'b0010100_11000111) == 15'b0010100_01000110) ? 1'b1 : 1'b0; // ld r,(hl) assign pla[ 59] = (({prefix[6:0], opcode[7:0]} & 15'b0010100_11111000) == 15'b0010100_01110000) ? 1'b1 : 1'b0; // ld (hl),r assign pla[ 61] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000000) == 15'b0000100_01000000) ? 1'b1 : 1'b0; // ld r,r' assign pla[ 64] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_11000110) ? 1'b1 : 1'b0; // add/sub/and/or/xor/cmp a,imm assign pla[ 65] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000000) == 15'b0000100_10000000) ? 1'b1 : 1'b0; // add/sub/and/or/xor/cmp a,r assign pla[ 66] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000110) == 15'b0000100_00000100) ? 1'b1 : 1'b0; // inc/dec r assign pla[ 68] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11000111) == 15'b0000001_01000010) ? 1'b1 : 1'b0; // adc/sbc hl,rr assign pla[ 69] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11001111) == 15'b0000100_00001001) ? 1'b1 : 1'b0; // add hl,rr assign pla[ 70] = (({prefix[6:0], opcode[7:0]} & 15'b0000010_11000000) == 15'b0000010_00000000) ? 1'b1 : 1'b0; // rlc r assign pla[ 72] = (({prefix[6:0], opcode[7:0]} & 15'b0000010_11000000) == 15'b0000010_01000000) ? 1'b1 : 1'b0; // bit b,r assign pla[ 73] = (({prefix[6:0], opcode[7:0]} & 15'b0000010_11000000) == 15'b0000010_10000000) ? 1'b1 : 1'b0; // res b,r assign pla[ 74] = (({prefix[6:0], opcode[7:0]} & 15'b0000010_11000000) == 15'b0000010_11000000) ? 1'b1 : 1'b0; // set b,r assign pla[ 75] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11000111) == 15'b0000100_00000101) ? 1'b1 : 1'b0; // dec r assign pla[ 76] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00111000) ? 1'b1 : 1'b0; // 111 (CP) assign pla[ 77] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00100111) ? 1'b1 : 1'b0; // daa assign pla[ 78] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00010000) ? 1'b1 : 1'b0; // 010 (SUB) assign pla[ 79] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00011000) ? 1'b1 : 1'b0; // 011 (SBC) assign pla[ 80] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00001000) ? 1'b1 : 1'b0; // 001 (ADC) assign pla[ 81] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00101111) ? 1'b1 : 1'b0; // cpl assign pla[ 82] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11000111) == 15'b0000001_01000100) ? 1'b1 : 1'b0; // neg assign pla[ 83] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11110111) == 15'b0000001_01010111) ? 1'b1 : 1'b0; // ld a,i/a,r assign pla[ 84] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00000000) ? 1'b1 : 1'b0; // 000 (ADD) assign pla[ 85] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00100000) ? 1'b1 : 1'b0; // 100 (AND) assign pla[ 86] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00110000) ? 1'b1 : 1'b0; // 110 (OR) assign pla[ 88] = (({prefix[6:0], opcode[7:0]} & 15'b0001000_00111000) == 15'b0001000_00101000) ? 1'b1 : 1'b0; // 101 (XOR) assign pla[ 89] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00111111) ? 1'b1 : 1'b0; // ccf assign pla[ 91] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11100110) == 15'b0000001_10100010) ? 1'b1 : 1'b0; // inx/outx/inxr/otxr assign pla[ 92] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_00110111) ? 1'b1 : 1'b0; // scf assign pla[ 95] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11111111) == 15'b0000100_01110110) ? 1'b1 : 1'b0; // halt assign pla[ 96] = (({prefix[6:0], opcode[7:0]} & 15'b0000001_11000111) == 15'b0000001_01000110) ? 1'b1 : 1'b0; // im n assign pla[ 97] = (({prefix[6:0], opcode[7:0]} & 15'b0000100_11110111) == 15'b0000100_11110011) ? 1'b1 : 1'b0; // di/ei assign pla[ 99] = (({prefix[6:0], opcode[7:0]} & 15'b0000000_00000001) == 15'b0000000_00000001) ? 1'b1 : 1'b0; // opcode[0] assign pla[100] = (({prefix[6:0], opcode[7:0]} & 15'b0000000_00000010) == 15'b0000000_00000010) ? 1'b1 : 1'b0; // opcode[1] assign pla[101] = (({prefix[6:0], opcode[7:0]} & 15'b0000000_00000100) == 15'b0000000_00000100) ? 1'b1 : 1'b0; // opcode[2] assign pla[102] = (({prefix[6:0], opcode[7:0]} & 15'b0000000_00001000) == 15'b0000000_00001000) ? 1'b1 : 1'b0; // opcode[3] assign pla[103] = (({prefix[6:0], opcode[7:0]} & 15'b0000000_00010000) == 15'b0000000_00010000) ? 1'b1 : 1'b0; // opcode[4] assign pla[104] = (({prefix[6:0], opcode[7:0]} & 15'b0000000_00100000) == 15'b0000000_00100000) ? 1'b1 : 1'b0; // opcode[5] // Entries not used by our timing matrix assign pla[ 67] = 1'b0; // in assign pla[ 62] = 1'b0; // For all CB opcodes assign pla[ 54] = 1'b0; // Every CB with IX/IY assign pla[ 22] = 1'b0; // CB prefix w/o IX/IY assign pla[ 14] = 1'b0; // dec rr assign pla[ 4] = 1'b0; // ld x,a/a,x // Duplicate entries assign pla[ 18] = 1'b0; // ldi/ldir/ldd/lddr assign pla[ 19] = 1'b0; // cpi/cpir/cpd/cpdr assign pla[ 32] = 1'b0; // ld i,a/a,i/r,a/a,r assign pla[ 36] = 1'b0; // ld(rr),a/a,(rr) assign pla[ 41] = 1'b0; // IX/IY assign pla[ 60] = 1'b0; // rrd/rld assign pla[ 63] = 1'b0; // ld r,* assign pla[ 71] = 1'b0; // rlca/rla/rrca/rra assign pla[ 87] = 1'b0; // ld a,i / ld a,r assign pla[ 90] = 1'b0; // djnz * assign pla[ 93] = 1'b0; // cpi/cpir/cpd/cpdr assign pla[ 94] = 1'b0; // ldi/ldir/ldd/lddr assign pla[ 98] = 1'b0; // out (*),a/in a,(*) endmodule ================================================ FILE: cpu/control/resets.bdf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. 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(connector (pt 392 640) (pt 504 640) ) (connector (pt 208 640) (pt 280 640) ) (connector (pt 280 640) (pt 392 640) ) (connector (pt 712 432) (pt 264 432) ) (connector (pt 264 544) (pt 264 432) ) (connector (pt 712 296) (pt 712 336) ) (connector (pt 712 336) (pt 712 432) ) (junction (pt 232 144)) (junction (pt 368 96)) (junction (pt 336 272)) (junction (pt 464 144)) (junction (pt 440 184)) (junction (pt 320 320)) (junction (pt 232 352)) (junction (pt 712 224)) (junction (pt 712 336)) (junction (pt 264 616)) (junction (pt 376 616)) (junction (pt 376 544)) (junction (pt 488 544)) (junction (pt 392 640)) (junction (pt 280 640)) (text "Needed only for FPGAs" (rect 40 72 174 86)(font "Arial" (font_size 8))) (text "Special reset, USPTO 4,486,827 by Shima et al." (rect 40 24 371 40)(font "Arial" (font_size 10))(border)) (text "Required 3 clock reset cycles to clear PC and IR" (rect 304 464 576 478)(font "Arial" (font_size 8))) (text "(End of patented circuit)" (rect 64 384 242 400)(font "Arial" (font_size 10)(bold))) (line (pt 32 408)(pt 952 408)(color 0 255 0)) (title_block (rect 696 584 953 636) (name "title-custom-small") (section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "resets" (rect 43 2 86 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border)) (section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "September 6, 2014, 2016" (rect 56 3 198 17)(font "Arial" (font_size 8)))(border)) (section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.5" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border)) (drawing ) ) ================================================ FILE: cpu/control/resets.bsf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "symbol" (version "1.2")) (symbol (rect 16 16 192 176) (text "resets" (rect 5 0 41 14)(font "Arial" (font_size 8))) (text "inst" (rect 8 144 25 156)(font "Arial" )) (port (pt 0 32) (input) (text "fpga_reset" (rect 0 0 62 14)(font "Arial" (font_size 8))) (text "fpga_reset" (rect 21 27 83 41)(font "Arial" (font_size 8))) (line (pt 0 32)(pt 16 32)) ) (port (pt 0 48) (input) (text "reset_in" (rect 0 0 46 14)(font "Arial" (font_size 8))) (text "reset_in" (rect 21 43 67 57)(font "Arial" (font_size 8))) (line (pt 0 48)(pt 16 48)) ) (port (pt 0 64) (input) (text "M1" (rect 0 0 16 14)(font "Arial" (font_size 8))) (text "M1" (rect 21 59 37 73)(font "Arial" (font_size 8))) (line (pt 0 64)(pt 16 64)) ) (port (pt 0 80) (input) (text "T2" (rect 0 0 14 14)(font "Arial" (font_size 8))) (text "T2" (rect 21 75 35 89)(font "Arial" (font_size 8))) (line (pt 0 80)(pt 16 80)) ) (port (pt 0 96) (input) (text "clk" (rect 0 0 15 14)(font "Arial" (font_size 8))) (text "clk" (rect 21 91 36 105)(font "Arial" (font_size 8))) (line (pt 0 96)(pt 16 96)) ) (port (pt 0 112) (input) (text "nhold_clk_wait" (rect 0 0 84 14)(font "Arial" (font_size 8))) (text "nhold_clk_wait" (rect 21 107 105 121)(font "Arial" (font_size 8))) (line (pt 0 112)(pt 16 112)) ) (port (pt 176 32) (output) (text "nreset" (rect 0 0 36 14)(font "Arial" (font_size 8))) (text "nreset" (rect 119 27 155 41)(font "Arial" (font_size 8))) (line (pt 176 32)(pt 160 32)) ) (port (pt 176 48) (output) (text "clrpc" (rect 0 0 28 14)(font "Arial" (font_size 8))) (text "clrpc" (rect 127 43 155 57)(font "Arial" (font_size 8))) (line (pt 176 48)(pt 160 48)) ) (drawing (rectangle (rect 16 16 160 144)) ) ) ================================================ FILE: cpu/control/resets.v ================================================ // Copyright (C) 1991-2013 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // PROGRAM "Quartus II 64-Bit" // VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" // CREATED "Sat Dec 10 08:57:54 2016" module resets( reset_in, clk, M1, T2, fpga_reset, nhold_clk_wait, clrpc, nreset ); input wire reset_in; input wire clk; input wire M1; input wire T2; input wire fpga_reset; input wire nhold_clk_wait; output wire clrpc; output wire nreset; reg clrpc_int; wire nclk; reg x1; wire x2; wire x3; wire SYNTHESIZED_WIRE_8; wire SYNTHESIZED_WIRE_1; reg SYNTHESIZED_WIRE_9; reg DFFE_intr_ff3; reg SYNTHESIZED_WIRE_10; wire SYNTHESIZED_WIRE_11; wire SYNTHESIZED_WIRE_3; reg SYNTHESIZED_WIRE_12; wire SYNTHESIZED_WIRE_6; assign nreset = SYNTHESIZED_WIRE_6; always@(posedge nclk or negedge SYNTHESIZED_WIRE_8) begin if (!SYNTHESIZED_WIRE_8) begin x1 <= 1; end else begin x1 <= ~x1 & reset_in | x1 & ~SYNTHESIZED_WIRE_1; end end assign clrpc = clrpc_int | SYNTHESIZED_WIRE_9 | DFFE_intr_ff3 | SYNTHESIZED_WIRE_10; assign SYNTHESIZED_WIRE_1 = ~reset_in; assign x2 = x1 & SYNTHESIZED_WIRE_11; assign SYNTHESIZED_WIRE_11 = M1 & T2; assign x3 = x1 & SYNTHESIZED_WIRE_3; assign SYNTHESIZED_WIRE_6 = ~SYNTHESIZED_WIRE_12; assign SYNTHESIZED_WIRE_3 = ~SYNTHESIZED_WIRE_11; assign nclk = ~clk; assign SYNTHESIZED_WIRE_8 = ~fpga_reset; always@(posedge nclk) begin if (nhold_clk_wait) begin DFFE_intr_ff3 <= SYNTHESIZED_WIRE_9; end end always@(posedge nclk) begin if (nhold_clk_wait) begin SYNTHESIZED_WIRE_10 <= SYNTHESIZED_WIRE_12; end end always@(posedge nclk) begin if (nhold_clk_wait) begin SYNTHESIZED_WIRE_9 <= SYNTHESIZED_WIRE_10; end end always@(posedge clk or negedge SYNTHESIZED_WIRE_8) begin if (!SYNTHESIZED_WIRE_8) begin SYNTHESIZED_WIRE_12 <= 1; end else begin SYNTHESIZED_WIRE_12 <= x3; end end always@(posedge nclk or negedge SYNTHESIZED_WIRE_6) begin if (!SYNTHESIZED_WIRE_6) begin clrpc_int <= 0; end else begin clrpc_int <= ~clrpc_int & x2 | clrpc_int & ~SYNTHESIZED_WIRE_11; end end endmodule ================================================ FILE: cpu/control/sequencer.bdf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "graphic" (version "1.4")) (pin (input) (rect 24 416 200 432) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "clk" (rect 9 0 23 12)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) (line (pt 121 8)(pt 176 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) ) (pin (input) (rect 24 360 200 376) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "nextM" (rect 9 0 38 12)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) (line (pt 121 8)(pt 176 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) ) (pin (input) (rect 24 296 200 312) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text 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"Goran Devic" (rect 56 2 151 19)(font "Arial" (font_size 11)))(border)) (section (rect 130 0 320 20)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "sequencer" (rect 43 2 138 21)(font "Arial" (font_size 12)(bold)))(border)) (section (rect 0 0 320 20)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 106 21)(font "Arial" (font_size 12)(bold)))(border)) (section (rect 241 41 320 60)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.4" (rect 43 3 64 19)(font "Arial" (font_size 10)))(border)) (drawing ) ) ================================================ FILE: cpu/control/sequencer.bsf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "symbol" (version "1.2")) (symbol (rect 16 16 216 272) (text "sequencer" (rect 5 0 66 14)(font "Arial" (font_size 8))) (text "inst" (rect 8 240 25 252)(font "Arial" )) (port (pt 0 32) (input) (text "setM1" (rect 0 0 34 14)(font "Arial" (font_size 8))) (text "setM1" (rect 21 27 55 41)(font "Arial" (font_size 8))) (line (pt 0 32)(pt 16 32)) ) (port (pt 0 48) (input) (text "clk" (rect 0 0 15 14)(font "Arial" (font_size 8))) (text "clk" (rect 21 43 36 57)(font "Arial" (font_size 8))) (line (pt 0 48)(pt 16 48)) ) (port (pt 0 64) (input) (text "nreset" (rect 0 0 36 14)(font "Arial" (font_size 8))) (text "nreset" (rect 21 59 57 73)(font "Arial" (font_size 8))) (line (pt 0 64)(pt 16 64)) ) (port (pt 0 80) (input) (text "nextM" (rect 0 0 34 14)(font "Arial" (font_size 8))) (text "nextM" (rect 21 75 55 89)(font "Arial" (font_size 8))) (line (pt 0 80)(pt 16 80)) ) (port (pt 0 96) (input) (text "hold_clk_iorq" (rect 0 0 74 14)(font "Arial" (font_size 8))) (text "hold_clk_iorq" (rect 21 91 95 105)(font "Arial" (font_size 8))) (line (pt 0 96)(pt 16 96)) ) (port (pt 0 112) (input) (text "hold_clk_wait" (rect 0 0 77 14)(font "Arial" (font_size 8))) (text "hold_clk_wait" (rect 21 107 98 121)(font "Arial" (font_size 8))) (line (pt 0 112)(pt 16 112)) ) (port (pt 0 128) (input) (text "hold_clk_busrq" (rect 0 0 86 14)(font "Arial" (font_size 8))) (text "hold_clk_busrq" (rect 21 123 107 137)(font "Arial" (font_size 8))) (line (pt 0 128)(pt 16 128)) ) (port (pt 200 32) (output) (text "M1" (rect 0 0 16 14)(font "Arial" (font_size 8))) (text "M1" (rect 163 27 179 41)(font "Arial" (font_size 8))) (line (pt 200 32)(pt 184 32)) ) (port (pt 200 48) (output) (text "M2" (rect 0 0 16 14)(font "Arial" (font_size 8))) (text "M2" (rect 163 43 179 57)(font "Arial" (font_size 8))) (line (pt 200 48)(pt 184 48)) ) (port (pt 200 64) (output) (text "M3" (rect 0 0 16 14)(font "Arial" (font_size 8))) (text "M3" (rect 163 59 179 73)(font "Arial" (font_size 8))) (line (pt 200 64)(pt 184 64)) ) (port (pt 200 80) (output) (text "M4" (rect 0 0 16 14)(font "Arial" (font_size 8))) (text "M4" (rect 163 75 179 89)(font "Arial" (font_size 8))) (line (pt 200 80)(pt 184 80)) ) (port (pt 200 96) (output) (text "M5" (rect 0 0 16 14)(font "Arial" (font_size 8))) (text "M5" (rect 163 91 179 105)(font "Arial" (font_size 8))) (line (pt 200 96)(pt 184 96)) ) (port (pt 200 128) (output) (text "T1" (rect 0 0 14 14)(font "Arial" (font_size 8))) (text "T1" (rect 165 123 179 137)(font "Arial" (font_size 8))) (line (pt 200 128)(pt 184 128)) ) (port (pt 200 144) (output) (text "T2" (rect 0 0 14 14)(font "Arial" (font_size 8))) (text "T2" (rect 165 139 179 153)(font "Arial" (font_size 8))) (line (pt 200 144)(pt 184 144)) ) (port (pt 200 160) (output) (text "T3" (rect 0 0 14 14)(font "Arial" (font_size 8))) (text "T3" (rect 165 155 179 169)(font "Arial" (font_size 8))) (line (pt 200 160)(pt 184 160)) ) (port (pt 200 176) (output) (text "T4" (rect 0 0 14 14)(font "Arial" (font_size 8))) (text "T4" (rect 165 171 179 185)(font "Arial" (font_size 8))) (line (pt 200 176)(pt 184 176)) ) (port (pt 200 192) (output) (text "T5" (rect 0 0 14 14)(font "Arial" (font_size 8))) (text "T5" (rect 165 187 179 201)(font "Arial" (font_size 8))) (line (pt 200 192)(pt 184 192)) ) (port (pt 200 208) (output) (text "T6" (rect 0 0 14 14)(font "Arial" (font_size 8))) (text "T6" (rect 165 203 179 217)(font "Arial" (font_size 8))) (line (pt 200 208)(pt 184 208)) ) (port (pt 200 224) (output) (text "timings_en" (rect 0 0 60 14)(font "Arial" (font_size 8))) (text "timings_en" (rect 119 219 179 233)(font "Arial" (font_size 8))) (line (pt 200 224)(pt 184 224)) ) (drawing (rectangle (rect 16 16 184 240)) ) ) ================================================ FILE: cpu/control/sequencer.v ================================================ // Copyright (C) 1991-2013 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // PROGRAM "Quartus II 64-Bit" // VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" // CREATED "Sat Feb 13 17:56:57 2016" module sequencer( clk, nextM, setM1, nreset, hold_clk_iorq, hold_clk_wait, hold_clk_busrq, M1, M2, M3, M4, M5, T1, T2, T3, T4, T5, T6, timings_en ); input wire clk; input wire nextM; input wire setM1; input wire nreset; input wire hold_clk_iorq; input wire hold_clk_wait; input wire hold_clk_busrq; output wire M1; output wire M2; output wire M3; output wire M4; output reg M5; output wire T1; output wire T2; output wire T3; output wire T4; output wire T5; output reg T6; output wire timings_en; wire ena_M; wire ena_T; reg DFFE_M4_ff; wire SYNTHESIZED_WIRE_18; reg DFFE_T1_ff; wire SYNTHESIZED_WIRE_19; reg DFFE_T2_ff; reg DFFE_T3_ff; reg DFFE_T4_ff; reg DFFE_T5_ff; reg DFFE_M1_ff; reg DFFE_M2_ff; reg DFFE_M3_ff; wire SYNTHESIZED_WIRE_9; wire SYNTHESIZED_WIRE_10; wire SYNTHESIZED_WIRE_11; wire SYNTHESIZED_WIRE_12; wire SYNTHESIZED_WIRE_13; wire SYNTHESIZED_WIRE_14; wire SYNTHESIZED_WIRE_15; wire SYNTHESIZED_WIRE_16; wire SYNTHESIZED_WIRE_17; assign M1 = DFFE_M1_ff; assign M2 = DFFE_M2_ff; assign M3 = DFFE_M3_ff; assign M4 = DFFE_M4_ff; assign T1 = DFFE_T1_ff; assign T2 = DFFE_T2_ff; assign T3 = DFFE_T3_ff; assign T4 = DFFE_T4_ff; assign T5 = DFFE_T5_ff; assign ena_M = nextM | setM1; assign SYNTHESIZED_WIRE_12 = DFFE_M4_ff & SYNTHESIZED_WIRE_18; assign SYNTHESIZED_WIRE_13 = DFFE_T1_ff & SYNTHESIZED_WIRE_19; assign SYNTHESIZED_WIRE_14 = DFFE_T2_ff & SYNTHESIZED_WIRE_19; assign SYNTHESIZED_WIRE_15 = DFFE_T3_ff & SYNTHESIZED_WIRE_19; assign SYNTHESIZED_WIRE_16 = DFFE_T4_ff & SYNTHESIZED_WIRE_19; assign SYNTHESIZED_WIRE_17 = DFFE_T5_ff & SYNTHESIZED_WIRE_19; assign SYNTHESIZED_WIRE_9 = DFFE_M1_ff & SYNTHESIZED_WIRE_18; assign SYNTHESIZED_WIRE_10 = DFFE_M2_ff & SYNTHESIZED_WIRE_18; assign SYNTHESIZED_WIRE_11 = DFFE_M3_ff & SYNTHESIZED_WIRE_18; assign ena_T = ~(hold_clk_iorq | hold_clk_wait | hold_clk_busrq); always@(posedge clk or negedge nreset) begin if (!nreset) begin DFFE_M1_ff <= 1; end else if (ena_M) begin DFFE_M1_ff <= setM1; end end always@(posedge clk or negedge nreset) begin if (!nreset) begin DFFE_M2_ff <= 0; end else if (ena_M) begin DFFE_M2_ff <= SYNTHESIZED_WIRE_9; end end always@(posedge clk or negedge nreset) begin if (!nreset) begin DFFE_M3_ff <= 0; end else if (ena_M) begin DFFE_M3_ff <= SYNTHESIZED_WIRE_10; end end always@(posedge clk or negedge nreset) begin if (!nreset) begin DFFE_M4_ff <= 0; end else if (ena_M) begin DFFE_M4_ff <= SYNTHESIZED_WIRE_11; end end always@(posedge clk or negedge nreset) begin if (!nreset) begin M5 <= 0; end else if (ena_M) begin M5 <= SYNTHESIZED_WIRE_12; end end assign SYNTHESIZED_WIRE_19 = ~ena_M; assign SYNTHESIZED_WIRE_18 = ~setM1; always@(posedge clk or negedge nreset) begin if (!nreset) begin DFFE_T1_ff <= 1; end else if (ena_T) begin DFFE_T1_ff <= ena_M; end end always@(posedge clk or negedge nreset) begin if (!nreset) begin DFFE_T2_ff <= 0; end else if (ena_T) begin DFFE_T2_ff <= SYNTHESIZED_WIRE_13; end end always@(posedge clk or negedge nreset) begin if (!nreset) begin DFFE_T3_ff <= 0; end else if (ena_T) begin DFFE_T3_ff <= SYNTHESIZED_WIRE_14; end end always@(posedge clk or negedge nreset) begin if (!nreset) begin DFFE_T4_ff <= 0; end else if (ena_T) begin DFFE_T4_ff <= SYNTHESIZED_WIRE_15; end end always@(posedge clk or negedge nreset) begin if (!nreset) begin DFFE_T5_ff <= 0; end else if (ena_T) begin DFFE_T5_ff <= SYNTHESIZED_WIRE_16; end end always@(posedge clk or negedge nreset) begin if (!nreset) begin T6 <= 0; end else if (ena_T) begin T6 <= SYNTHESIZED_WIRE_17; end end assign timings_en = ena_T; endmodule ================================================ FILE: cpu/control/simulation/modelsim/r ================================================ restart -f ; run -all ================================================ FILE: cpu/control/simulation/modelsim/test_control.mpf ================================================ ; Copyright 1991-2009 Mentor Graphics Corporation ; ; All Rights Reserved. ; ; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF ; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. ; [Library] std = $MODEL_TECH/../std ieee = $MODEL_TECH/../ieee verilog = $MODEL_TECH/../verilog vital2000 = $MODEL_TECH/../vital2000 std_developerskit = $MODEL_TECH/../std_developerskit synopsys = $MODEL_TECH/../synopsys modelsim_lib = $MODEL_TECH/../modelsim_lib sv_std = $MODEL_TECH/../sv_std ; Altera Primitive libraries ; ; VHDL Section ; altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf altera = $MODEL_TECH/../altera/vhdl/altera altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim lpm = $MODEL_TECH/../altera/vhdl/220model 220model = $MODEL_TECH/../altera/vhdl/220model max = $MODEL_TECH/../altera/vhdl/max maxii = $MODEL_TECH/../altera/vhdl/maxii maxv = $MODEL_TECH/../altera/vhdl/maxv stratix = $MODEL_TECH/../altera/vhdl/stratix stratixii = $MODEL_TECH/../altera/vhdl/stratixii stratixiigx = $MODEL_TECH/../altera/vhdl/stratixiigx hardcopyii = $MODEL_TECH/../altera/vhdl/hardcopyii hardcopyiii = $MODEL_TECH/../altera/vhdl/hardcopyiii hardcopyiv = $MODEL_TECH/../altera/vhdl/hardcopyiv cyclone = $MODEL_TECH/../altera/vhdl/cyclone cycloneii = $MODEL_TECH/../altera/vhdl/cycloneii cycloneiii = $MODEL_TECH/../altera/vhdl/cycloneiii cycloneiiils = $MODEL_TECH/../altera/vhdl/cycloneiiils sgate = $MODEL_TECH/../altera/vhdl/sgate stratixgx = $MODEL_TECH/../altera/vhdl/stratixgx altgxb = $MODEL_TECH/../altera/vhdl/altgxb stratixgx_gxb = $MODEL_TECH/../altera/vhdl/stratixgx_gxb stratixiigx_hssi = $MODEL_TECH/../altera/vhdl/stratixiigx_hssi arriagx_hssi = $MODEL_TECH/../altera/vhdl/arriagx_hssi arriaii = $MODEL_TECH/../altera/vhdl/arriaii arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip arriagx = $MODEL_TECH/../altera/vhdl/arriagx altgxb_lib = $MODEL_TECH/../altera/vhdl/altgxb stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive hardcopyiv_hssi = $MODEL_TECH/../altera/vhdl/hardcopyiv_hssi hardcopyiv_pcie_hip = $MODEL_TECH/../altera/vhdl/hardcopyiv_pcie_hip stratixv = $MODEL_TECH/../altera/vhdl/stratixv stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip arriav = $MODEL_TECH/../altera/vhdl/arriav cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev ; ; Verilog Section ; altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf altera_ver = $MODEL_TECH/../altera/verilog/altera altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim lpm_ver = $MODEL_TECH/../altera/verilog/220model 220model_ver = $MODEL_TECH/../altera/verilog/220model max_ver = $MODEL_TECH/../altera/verilog/max maxii_ver = $MODEL_TECH/../altera/verilog/maxii maxv_ver = $MODEL_TECH/../altera/verilog/maxv stratix_ver = $MODEL_TECH/../altera/verilog/stratix stratixii_ver = $MODEL_TECH/../altera/verilog/stratixii stratixiigx_ver = $MODEL_TECH/../altera/verilog/stratixiigx arriagx_ver = $MODEL_TECH/../altera/verilog/arriagx hardcopyii_ver = $MODEL_TECH/../altera/verilog/hardcopyii hardcopyiii_ver = $MODEL_TECH/../altera/verilog/hardcopyiii hardcopyiv_ver = $MODEL_TECH/../altera/verilog/hardcopyiv cyclone_ver = $MODEL_TECH/../altera/verilog/cyclone cycloneii_ver = $MODEL_TECH/../altera/verilog/cycloneii cycloneiii_ver = $MODEL_TECH/../altera/verilog/cycloneiii cycloneiiils_ver = $MODEL_TECH/../altera/verilog/cycloneiiils sgate_ver = $MODEL_TECH/../altera/verilog/sgate stratixgx_ver = $MODEL_TECH/../altera/verilog/stratixgx altgxb_ver = $MODEL_TECH/../altera/verilog/altgxb stratixgx_gxb_ver = $MODEL_TECH/../altera/verilog/stratixgx_gxb stratixiigx_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiigx_hssi arriagx_hssi_ver = $MODEL_TECH/../altera/verilog/arriagx_hssi arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip stratixiii_ver = $MODEL_TECH/../altera/verilog/stratixiii stratixiii = $MODEL_TECH/../altera/vhdl/stratixiii stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip arriav_ver = $MODEL_TECH/../altera/verilog/arriav arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive hardcopyiv_hssi_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_hssi hardcopyiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_pcie_hip work = work [vcom] ; VHDL93 variable selects language version as the default. ; Default is VHDL-2002. ; Value of 0 or 1987 for VHDL-1987. ; Value of 1 or 1993 for VHDL-1993. ; Default or value of 2 or 2002 for VHDL-2002. ; Default or value of 3 or 2008 for VHDL-2008. VHDL93 = 2002 ; Show source line containing error. Default is off. ; Show_source = 1 ; Turn off unbound-component warnings. Default is on. ; Show_Warning1 = 0 ; Turn off process-without-a-wait-statement warnings. Default is on. ; Show_Warning2 = 0 ; Turn off null-range warnings. Default is on. ; Show_Warning3 = 0 ; Turn off no-space-in-time-literal warnings. Default is on. ; Show_Warning4 = 0 ; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. ; Show_Warning5 = 0 ; Turn off optimization for IEEE std_logic_1164 package. Default is on. ; Optimize_1164 = 0 ; Turn on resolving of ambiguous function overloading in favor of the ; "explicit" function declaration (not the one automatically created by ; the compiler for each type declaration). Default is off. ; The .ini file has Explicit enabled so that std_logic_signed/unsigned ; will match the behavior of synthesis tools. Explicit = 1 ; Turn off acceleration of the VITAL packages. Default is to accelerate. ; NoVital = 1 ; Turn off VITAL compliance checking. Default is checking on. ; NoVitalCheck = 1 ; Ignore VITAL compliance checking errors. Default is to not ignore. ; IgnoreVitalErrors = 1 ; Turn off VITAL compliance checking warnings. Default is to show warnings. ; Show_VitalChecksWarnings = 0 ; Keep silent about case statement static warnings. ; Default is to give a warning. ; NoCaseStaticError = 1 ; Keep silent about warnings caused by aggregates that are not locally static. ; Default is to give a warning. ; NoOthersStaticError = 1 ; Turn off inclusion of debugging info within design units. ; Default is to include debugging info. ; NoDebug = 1 ; Turn off "Loading..." messages. Default is messages on. ; Quiet = 1 ; Turn on some limited synthesis rule compliance checking. Checks only: ; -- signals used (read) by a process must be in the sensitivity list ; CheckSynthesis = 1 ; Activate optimizations on expressions that do not involve signals, ; waits, or function/procedure/task invocations. Default is off. ; ScalarOpts = 1 ; Require the user to specify a configuration for all bindings, ; and do not generate a compile time default binding for the ; component. This will result in an elaboration error of ; 'component not bound' if the user fails to do so. Avoids the rare ; issue of a false dependency upon the unused default binding. ; RequireConfigForAllDefaultBinding = 1 ; Inhibit range checking on subscripts of arrays. Range checking on ; scalars defined with subtypes is inhibited by default. ; NoIndexCheck = 1 ; Inhibit range checks on all (implicit and explicit) assignments to ; scalar objects defined with subtypes. ; NoRangeCheck = 1 [vlog] ; Turn off inclusion of debugging info within design units. ; Default is to include debugging info. ; NoDebug = 1 ; Turn off "loading..." messages. Default is messages on. ; Quiet = 1 ; Turn on Verilog hazard checking (order-dependent accessing of global vars). ; Default is off. ; Hazard = 1 ; Turn on converting regular Verilog identifiers to uppercase. Allows case ; insensitivity for module names. Default is no conversion. ; UpCase = 1 ; Turn on incremental compilation of modules. Default is off. ; Incremental = 1 ; Turns on lint-style checking. ; Show_Lint = 1 [vsim] ; Simulator resolution ; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. Resolution = ps ; User time unit for run commands ; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the ; unit specified for Resolution. For example, if Resolution is 100ps, ; then UserTimeUnit defaults to ps. ; Should generally be set to default. UserTimeUnit = default ; Default run length RunLength = 0 ns ; Maximum iterations that can be run without advancing simulation time IterationLimit = 5000 ; Directive to license manager: ; vhdl Immediately reserve a VHDL license ; vlog Immediately reserve a Verilog license ; plus Immediately reserve a VHDL and Verilog license ; nomgc Do not look for Mentor Graphics Licenses ; nomti Do not look for Model Technology Licenses ; noqueue Do not wait in the license queue when a license isn't available ; viewsim Try for viewer license but accept simulator license(s) instead ; of queuing for viewer license ; License = plus ; Stop the simulator after a VHDL/Verilog assertion message ; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal BreakOnAssertion = 4 ; Assertion Message Format ; %S - Severity Level ; %R - Report Message ; %T - Time of assertion ; %D - Delta ; %I - Instance or Region pathname (if available) ; %% - print '%' character ; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" ; Assertion File - alternate file for storing VHDL/Verilog assertion messages ; AssertFile = assert.log ; Default radix for all windows and commands... ; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned DefaultRadix = symbolic ; VSIM Startup command ; Startup = do startup.do ; File for saving command transcript TranscriptFile = transcript ; File for saving command history ; CommandHistory = cmdhist.log ; Specify whether paths in simulator commands should be described ; in VHDL or Verilog format. ; For VHDL, PathSeparator = / ; For Verilog, PathSeparator = . ; Must not be the same character as DatasetSeparator. PathSeparator = / ; Specify the dataset separator for fully rooted contexts. ; The default is ':'. For example, sim:/top ; Must not be the same character as PathSeparator. DatasetSeparator = : ; Disable VHDL assertion messages ; IgnoreNote = 1 ; IgnoreWarning = 1 ; IgnoreError = 1 ; IgnoreFailure = 1 ; Default force kind. May be freeze, drive, deposit, or default ; or in other terms, fixed, wired, or charged. ; A value of "default" will use the signal kind to determine the ; force kind, drive for resolved signals, freeze for unresolved signals ; DefaultForceKind = freeze ; If zero, open files when elaborated; otherwise, open files on ; first read or write. Default is 0. ; DelayFileOpen = 1 ; Control VHDL files opened for write. ; 0 = Buffered, 1 = Unbuffered UnbufferedOutput = 0 ; Control the number of VHDL files open concurrently. ; This number should always be less than the current ulimit ; setting for max file descriptors. ; 0 = unlimited ConcurrentFileLimit = 40 ; Control the number of hierarchical regions displayed as ; part of a signal name shown in the Wave window. ; A value of zero tells VSIM to display the full name. ; The default is 0. ; WaveSignalNameWidth = 0 ; Turn off warnings from the std_logic_arith, std_logic_unsigned ; and std_logic_signed packages. ; StdArithNoWarnings = 1 ; Turn off warnings from the IEEE numeric_std and numeric_bit packages. ; NumericStdNoWarnings = 1 ; Control the format of the (VHDL) FOR generate statement label ; for each iteration. Do not quote it. ; The format string here must contain the conversion codes %s and %d, ; in that order, and no other conversion codes. The %s represents ; the generate_label; the %d represents the generate parameter value ; at a particular generate iteration (this is the position number if ; the generate parameter is of an enumeration type). Embedded whitespace ; is allowed (but discouraged); leading and trailing whitespace is ignored. ; Application of the format must result in a unique scope name over all ; such names in the design so that name lookup can function properly. ; GenerateFormat = %s__%d ; Specify whether checkpoint files should be compressed. ; The default is 1 (compressed). ; CheckpointCompressMode = 0 ; List of dynamically loaded objects for Verilog PLI applications ; Veriuser = veriuser.sl ; Specify default options for the restart command. Options can be one ; or more of: -force -nobreakpoint -nolist -nolog -nowave ; DefaultRestartOptions = -force ; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs ; (> 500 megabyte memory footprint). Default is disabled. ; Specify number of megabytes to lock. ; LockedMemory = 1000 ; Turn on (1) or off (0) WLF file compression. ; The default is 1 (compress WLF file). ; WLFCompress = 0 ; Specify whether to save all design hierarchy (1) in the WLF file ; or only regions containing logged signals (0). ; The default is 0 (save only regions with logged signals). ; WLFSaveAllRegions = 1 ; WLF file time limit. Limit WLF file by time, as closely as possible, ; to the specified amount of simulation time. When the limit is exceeded ; the earliest times get truncated from the file. ; If both time and size limits are specified the most restrictive is used. ; UserTimeUnits are used if time units are not specified. ; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} ; WLFTimeLimit = 0 ; WLF file size limit. Limit WLF file size, as closely as possible, ; to the specified number of megabytes. If both time and size limits ; are specified then the most restrictive is used. ; The default is 0 (no limit). ; WLFSizeLimit = 1000 ; Specify whether or not a WLF file should be deleted when the ; simulation ends. A value of 1 will cause the WLF file to be deleted. ; The default is 0 (do not delete WLF file when simulation ends). ; WLFDeleteOnQuit = 1 ; Automatic SDF compilation ; Disables automatic compilation of SDF files in flows that support it. ; Default is on, uncomment to turn off. ; NoAutoSDFCompile = 1 DelayFileOpen = 1 [lmc] [msg_system] ; Change a message severity or suppress a message. ; The format is: = [,...] ; Examples: ; note = 3009 ; warning = 3033 ; error = 3010,3016 ; fatal = 3016,3033 ; suppress = 3009,3016,3043 ; The command verror can be used to get the complete ; description of a message. ; Control transcripting of elaboration/runtime messages. ; The default is to have messages appear in the transcript and ; recorded in the wlf file (messages that are recorded in the ; wlf file can be viewed in the MsgViewer). The other settings ; are to send messages only to the transcript or only to the ; wlf file. The valid values are ; both {default} ; tran {transcript only} ; wlf {wlf file only} ; msgmode = both [Project] ; Warning -- Do not edit the project properties directly. ; Property names are dynamic in nature and property ; values have special syntax. Changing property data directly ; can result in a corrupt MPF file. All project properties ; can be modified through project window dialogs. Project_Version = 6 Project_DefaultLib = work Project_SortMethod = unused Project_Files_Count = 8 Project_File_0 = $ROOT/cpu/control/interrupts.v Project_File_P_0 = compile_order 1 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder interrupts group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 Project_File_1 = $ROOT/cpu/control/pin_control.v Project_File_P_1 = compile_order 6 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {pin control} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 Project_File_2 = $ROOT/cpu/control/resets.v Project_File_P_2 = compile_order 4 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder reset group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 Project_File_3 = $ROOT/cpu/control/sequencer.v Project_File_P_3 = compile_order 7 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder sequencer group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 Project_File_4 = $ROOT/cpu/control/test_interrupts.sv Project_File_P_4 = compile_order 2 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder interrupts group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 Project_File_5 = $ROOT/cpu/control/test_pin_control.sv Project_File_P_5 = compile_order 0 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder {pin control} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 Project_File_6 = $ROOT/cpu/control/test_reset.sv Project_File_P_6 = compile_order 3 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder reset group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 Project_File_7 = $ROOT/cpu/control/test_sequencer.sv Project_File_P_7 = compile_order 5 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder sequencer group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 Project_Sim_Count = 4 Project_Sim_0 = Test pin control Project_Sim_P_0 = timing default -sdfnoerror 0 -t default -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder {pin control} +pulse_e {} additional_dus work.test_pin_control -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {} Project_Sim_1 = Test interrupts Project_Sim_P_1 = timing default -sdfnoerror 0 -t default -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder interrupts +pulse_e {} additional_dus work.test_interrupts -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {} Project_Sim_2 = Test reset Project_Sim_P_2 = timing default -sdfnoerror 0 -t default -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder reset +pulse_e {} additional_dus work.test_reset -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {} Project_Sim_3 = Test sequencer Project_Sim_P_3 = timing default -t default -sdfnoerror 0 -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder sequencer +pulse_e {} additional_dus work.test_sequencer -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {} Project_Folder_Count = 4 Project_Folder_0 = interrupts Project_Folder_P_0 = folder {Top Level} Project_Folder_1 = pin control Project_Folder_P_1 = folder {Top Level} Project_Folder_2 = reset Project_Folder_P_2 = folder {Top Level} Project_Folder_3 = sequencer Project_Folder_P_3 = folder {Top Level} Echo_Compile_Output = 0 Save_Compile_Report = 1 Project_Opt_Count = 0 ForceSoftPaths = 1 ProjectStatusDelay = 5000 VERILOG_DoubleClick = Edit VERILOG_CustomDoubleClick = SYSTEMVERILOG_DoubleClick = Edit SYSTEMVERILOG_CustomDoubleClick = VHDL_DoubleClick = Edit VHDL_CustomDoubleClick = PSL_DoubleClick = Edit PSL_CustomDoubleClick = TEXT_DoubleClick = Edit TEXT_CustomDoubleClick = SYSTEMC_DoubleClick = Edit SYSTEMC_CustomDoubleClick = TCL_DoubleClick = Edit TCL_CustomDoubleClick = MACRO_DoubleClick = Edit MACRO_CustomDoubleClick = VCD_DoubleClick = Edit VCD_CustomDoubleClick = SDF_DoubleClick = Edit SDF_CustomDoubleClick = XML_DoubleClick = Edit XML_CustomDoubleClick = LOGFILE_DoubleClick = Edit LOGFILE_CustomDoubleClick = UCDB_DoubleClick = Edit UCDB_CustomDoubleClick = UPF_DoubleClick = Edit UPF_CustomDoubleClick = PCF_DoubleClick = Edit PCF_CustomDoubleClick = PROJECT_DoubleClick = Edit PROJECT_CustomDoubleClick = VRM_DoubleClick = Edit VRM_CustomDoubleClick = DEBUGDATABASE_DoubleClick = Edit DEBUGDATABASE_CustomDoubleClick = DEBUGARCHIVE_DoubleClick = Edit DEBUGARCHIVE_CustomDoubleClick = Project_Major_Version = 10 Project_Minor_Version = 1 ================================================ FILE: cpu/control/simulation/modelsim/wave_interrupts.do ================================================ onerror {resume} quietly WaveActivateNextPane {} 0 add wave -noupdate /test_interrupts/clk add wave -noupdate /test_interrupts/nreset add wave -noupdate /test_interrupts/ctl_iff1_iff2_sig add wave -noupdate /test_interrupts/nmi_sig add wave -noupdate /test_interrupts/setM1_sig add wave -noupdate /test_interrupts/intr_sig add wave -noupdate /test_interrupts/ctl_iffx_we_sig add wave -noupdate /test_interrupts/ctl_iffx_bit_sig add wave -noupdate /test_interrupts/ctl_im_we_sig add wave -noupdate /test_interrupts/db_sig add wave -noupdate /test_interrupts/ctl_no_ints_sig add wave -noupdate -divider STATE add wave -noupdate -color Aquamarine /test_interrupts/iff1_sig add wave -noupdate -color Aquamarine /test_interrupts/iff2_sig add wave -noupdate -color Pink /test_interrupts/im1_sig add wave -noupdate -color Pink /test_interrupts/im2_sig add wave -noupdate /test_interrupts/in_nmi_sig add wave -noupdate /test_interrupts/in_intr_sig TreeUpdate [SetDefaultTree] WaveRestoreCursors {{Cursor 1} {1800 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 202 configure wave -valuecolwidth 66 configure wave -justifyvalue left configure wave -signalnamewidth 0 configure wave -snapdistance 10 configure wave -datasetprefix 0 configure wave -rowmargin 4 configure wave -childrowmargin 2 configure wave -gridoffset 0 configure wave -gridperiod 1 configure wave -griddelta 40 configure wave -timeline 1 configure wave -timelineunits ps update WaveRestoreZoom {0 ns} {25800 ns} ================================================ FILE: cpu/control/simulation/modelsim/wave_pin_control.do ================================================ onerror {resume} quietly WaveActivateNextPane {} 0 add wave -noupdate /test_pin_control/fFetch_sig add wave -noupdate /test_pin_control/fMRead_sig add wave -noupdate /test_pin_control/fMWrite_sig add wave -noupdate /test_pin_control/fIORead_sig add wave -noupdate /test_pin_control/fIOWrite_sig add wave -noupdate /test_pin_control/T1_sig add wave -noupdate /test_pin_control/T2_sig add wave -noupdate /test_pin_control/T3_sig add wave -noupdate /test_pin_control/T4_sig add wave -noupdate -divider STATE add wave -noupdate -color Pink /test_pin_control/bus_ab_pin_we_sig add wave -noupdate -color Pink /test_pin_control/bus_db_pin_oe_sig add wave -noupdate -color Pink /test_pin_control/bus_db_pin_re_sig TreeUpdate [SetDefaultTree] WaveRestoreCursors {{Cursor 1} {1400 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 240 configure wave -valuecolwidth 54 configure wave -justifyvalue left configure wave -signalnamewidth 2 configure wave -snapdistance 10 configure wave -datasetprefix 0 configure wave -rowmargin 4 configure wave -childrowmargin 2 configure wave -gridoffset 0 configure wave -gridperiod 1 configure wave -griddelta 40 configure wave -timeline 1 configure wave -timelineunits us update WaveRestoreZoom {0 ns} {4600 ns} ================================================ FILE: cpu/control/simulation/modelsim/wave_reset.do ================================================ onerror {resume} quietly WaveActivateNextPane {} 0 add wave -noupdate /test_reset/clk add wave -noupdate /test_reset/reset_in add wave -noupdate /test_reset/fpga_reset add wave -noupdate /test_reset/M1 add wave -noupdate /test_reset/T2 add wave -noupdate -color Gold /test_reset/clrpc add wave -noupdate /test_reset/reset_block/nhold_clk_wait add wave -noupdate /test_reset/nreset add wave -noupdate -color {Cadet Blue} /test_reset/reset_block/x1 add wave -noupdate -color {Cadet Blue} /test_reset/reset_block/x2 add wave -noupdate -color {Cadet Blue} /test_reset/reset_block/x3 TreeUpdate [SetDefaultTree] WaveRestoreCursors {{Cursor 1} {2800 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 112 configure wave -valuecolwidth 73 configure wave -justifyvalue right configure wave -signalnamewidth 1 configure wave -snapdistance 10 configure wave -datasetprefix 0 configure wave -rowmargin 4 configure wave -childrowmargin 2 configure wave -gridoffset 0 configure wave -gridperiod 1 configure wave -griddelta 40 configure wave -timeline 1 configure wave -timelineunits us update WaveRestoreZoom {0 ns} {13700 ns} ================================================ FILE: cpu/control/simulation/modelsim/wave_sequencer.do ================================================ onerror {resume} quietly WaveActivateNextPane {} 0 add wave -noupdate /test_sequencer/clk add wave -noupdate /test_sequencer/nreset add wave -noupdate /test_sequencer/nextM_sig add wave -noupdate /test_sequencer/setM1_sig add wave -noupdate /test_sequencer/hold_clk_iorq_sig add wave -noupdate /test_sequencer/hold_clk_wait_sig add wave -noupdate /test_sequencer/hold_clk_busrq_sig add wave -noupdate -divider M-STATE add wave -noupdate -color Aquamarine /test_sequencer/M1_sig add wave -noupdate -color Aquamarine /test_sequencer/M2_sig add wave -noupdate -color Aquamarine /test_sequencer/M3_sig add wave -noupdate -color Aquamarine /test_sequencer/M4_sig add wave -noupdate -color Aquamarine /test_sequencer/M5_sig add wave -noupdate -divider T-STATE add wave -noupdate -color Pink /test_sequencer/T1_sig add wave -noupdate -color Pink /test_sequencer/T2_sig add wave -noupdate -color Pink /test_sequencer/T3_sig add wave -noupdate -color Pink /test_sequencer/T4_sig add wave -noupdate -color Pink /test_sequencer/T5_sig add wave -noupdate -color Pink /test_sequencer/T6_sig TreeUpdate [SetDefaultTree] WaveRestoreCursors {{Cursor 1} {6800 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 226 configure wave -valuecolwidth 78 configure wave -justifyvalue left configure wave -signalnamewidth 2 configure wave -snapdistance 10 configure wave -datasetprefix 0 configure wave -rowmargin 4 configure wave -childrowmargin 2 configure wave -gridoffset 0 configure wave -gridperiod 1 configure wave -griddelta 40 configure wave -timeline 1 configure wave -timelineunits us update WaveRestoreZoom {0 ns} {25 us} ================================================ FILE: cpu/control/temp_wires.vh ================================================ // Automatically generated by gencompile.py reg ctl_reg_gp_sel_pla17npla50M1T1_2; reg ctl_reg_gp_hilo_pla17npla50M1T1_3; reg ctl_reg_sys_hilo_pla17npla50M2T1_3; reg ctl_reg_sys_hilo_pla17npla50M2T2_4; reg ctl_reg_gp_sel_pla61npla58npla59M1T1_2; reg ctl_reg_gp_hilo_pla61npla58npla59M1T1_3; reg ctl_reg_gp_sel_pla61npla58npla59M1T4_3; reg ctl_reg_gp_hilo_pla61npla58npla59M1T4_4; reg ctl_reg_gp_sel_use_ixiypla58M1T1_2; reg ctl_reg_gp_hilo_use_ixiypla58M1T1_3; reg ctl_reg_sys_hilo_use_ixiypla58M2T1_3; reg ctl_reg_sys_hilo_use_ixiypla58M2T2_4; reg ctl_reg_gp_sel_nuse_ixiypla58M1T1_2; reg ctl_reg_gp_hilo_nuse_ixiypla58M1T1_3; reg ctl_reg_gp_sel_nuse_ixiypla58M2T1_2; reg ctl_reg_gp_hilo_nuse_ixiypla58M2T1_3; reg ctl_reg_sys_hilo_use_ixiypla59M2T1_3; reg ctl_reg_sys_hilo_use_ixiypla59M2T2_4; reg ctl_reg_gp_sel_nuse_ixiypla59M1T4_4; reg ctl_reg_gp_hilo_nuse_ixiypla59M1T4_5; reg ctl_reg_gp_sel_nuse_ixiypla59M2T1_2; reg ctl_reg_gp_hilo_nuse_ixiypla59M2T1_3; reg ctl_reg_gp_sel_nuse_ixiypla59M4T1_3; reg ctl_reg_gp_hilo_nuse_ixiypla59M4T1_4; reg ctl_reg_sys_hilo_pla40M2T1_3; reg ctl_reg_sys_hilo_pla40M2T2_4; reg ctl_reg_sys_hilo_pla40M3T1_3; reg ctl_reg_sys_hilo_pla40M3T2_4; reg ctl_reg_sys_hilo_pla50npla40M2T1_3; reg ctl_reg_sys_hilo_pla50npla40M2T2_4; reg ctl_reg_gp_sel_pla50npla40M3T1_2; reg ctl_reg_gp_hilo_pla50npla40M3T1_3; reg ctl_reg_gp_sel_pla8pla13M1T4_4; reg ctl_reg_gp_hilo_pla8pla13M1T4_5; reg ctl_reg_gp_sel_pla8pla13M2T1_2; reg ctl_reg_gp_hilo_pla8pla13M2T1_3; reg ctl_reg_sys_hilo_pla8pla13M2T2_4; reg ctl_reg_gp_sel_pla8npla13M1T1_2; reg ctl_reg_gp_hilo_pla8npla13M1T1_3; reg ctl_reg_gp_sel_pla8npla13M2T1_2; reg ctl_reg_gp_hilo_pla8npla13M2T1_3; reg ctl_reg_sys_hilo_pla8npla13M2T2_4; reg ctl_reg_sys_hilo_pla38pla13M2T1_3; reg ctl_reg_sys_hilo_pla38pla13M2T2_4; reg ctl_reg_sys_hilo_pla38pla13M2T3_6; reg ctl_reg_sys_hilo_pla38pla13M3T1_3; reg ctl_reg_sys_hilo_pla38pla13M3T2_4; reg ctl_reg_sys_hilo_pla38pla13M3T3_5; reg ctl_reg_sys_hilo_pla38pla13M3T3_10; reg ctl_reg_gp_sel_pla38pla13M4T1_3; reg ctl_reg_gp_hilo_pla38pla13M4T1_4; reg ctl_reg_sys_hilo_pla38pla13M4T2_4; reg ctl_reg_gp_sel_pla38npla13M1T1_2; reg ctl_reg_gp_hilo_pla38npla13M1T1_3; reg ctl_reg_sys_hilo_pla38npla13M2T1_3; reg ctl_reg_sys_hilo_pla38npla13M2T2_4; reg ctl_reg_sys_hilo_pla38npla13M2T3_6; reg ctl_reg_sys_hilo_pla38npla13M3T1_3; reg ctl_reg_sys_hilo_pla38npla13M3T2_4; reg ctl_reg_sys_hilo_pla38npla13M3T3_6; reg ctl_reg_sys_hilo_pla38npla13M4T1_3; reg ctl_reg_sys_hilo_pla38npla13M4T2_4; reg ctl_reg_gp_sel_pla83M1T1_2; reg ctl_reg_gp_hilo_pla83M1T1_3; reg ctl_pf_sel_pla83M1T1_19; reg ctl_reg_gp_sel_pla83M1T2_2; reg ctl_reg_gp_hilo_pla83M1T2_3; reg ctl_reg_gp_sel_pla83M1T3_1; reg ctl_reg_gp_hilo_pla83M1T3_2; reg ctl_reg_sys_hilo_pla83M1T4_3; reg ctl_reg_gp_sel_pla57M1T3_1; reg ctl_reg_gp_hilo_pla57M1T3_2; reg ctl_reg_sys_hilo_pla57M1T4_4; reg ctl_reg_gp_sel_pla7M1T1_2; reg ctl_reg_gp_hilo_pla7M1T1_3; reg ctl_reg_sys_hilo_pla7M2T1_3; reg ctl_reg_sys_hilo_pla7M2T2_4; reg ctl_reg_sys_hilo_pla7M3T1_3; reg ctl_reg_gp_sel_pla7M3T1_6; reg ctl_reg_gp_hilo_pla7M3T1_7; reg ctl_reg_sys_hilo_pla7M3T2_4; reg ctl_reg_sys_hilo_pla30pla13M2T1_3; reg ctl_reg_sys_hilo_pla30pla13M2T2_4; reg ctl_reg_sys_hilo_pla30pla13M2T3_6; reg ctl_reg_sys_hilo_pla30pla13M3T1_3; reg ctl_reg_sys_hilo_pla30pla13M3T2_4; reg ctl_reg_sys_hilo_pla30pla13M3T3_5; reg ctl_reg_sys_hilo_pla30pla13M3T3_10; reg ctl_reg_gp_sel_pla30pla13M4T1_3; reg ctl_reg_gp_hilo_pla30pla13M4T1_4; reg ctl_reg_sys_hilo_pla30pla13M4T2_4; reg ctl_reg_sys_hilo_pla30pla13M4T3_5; reg ctl_reg_gp_sel_pla30pla13M5T1_3; reg ctl_reg_gp_hilo_pla30pla13M5T1_4; reg ctl_reg_sys_hilo_pla30pla13M5T2_4; reg ctl_reg_sys_hilo_pla30npla13M2T1_3; reg ctl_reg_sys_hilo_pla30npla13M2T2_4; reg ctl_reg_sys_hilo_pla30npla13M2T3_6; reg ctl_reg_sys_hilo_pla30npla13M3T1_3; reg ctl_reg_sys_hilo_pla30npla13M3T2_4; reg ctl_reg_sys_hilo_pla30npla13M3T3_6; reg ctl_reg_sys_hilo_pla30npla13M4T1_3; reg ctl_reg_sys_hilo_pla30npla13M4T2_4; reg ctl_reg_gp_sel_pla30npla13M4T3_5; reg ctl_reg_gp_hilo_pla30npla13M4T3_6; reg ctl_reg_sys_hilo_pla30npla13M5T1_3; reg ctl_reg_sys_hilo_pla30npla13M5T2_4; reg ctl_reg_gp_sel_pla30npla13M5T3_4; reg ctl_reg_gp_hilo_pla30npla13M5T3_5; reg ctl_reg_sys_hilo_pla31pla33M2T1_3; reg ctl_reg_sys_hilo_pla31pla33M2T2_4; reg ctl_reg_sys_hilo_pla31pla33M2T3_6; reg ctl_reg_sys_hilo_pla31pla33M3T1_3; reg ctl_reg_sys_hilo_pla31pla33M3T2_4; reg ctl_reg_sys_hilo_pla31pla33M3T3_5; reg ctl_reg_sys_hilo_pla31pla33M3T3_10; reg ctl_reg_gp_sel_pla31pla33M4T1_3; reg ctl_reg_gp_hilo_pla31pla33M4T1_4; reg ctl_reg_sys_hilo_pla31pla33M4T2_4; reg ctl_reg_sys_hilo_pla31pla33M4T3_5; reg ctl_reg_gp_sel_pla31pla33M5T1_3; reg ctl_reg_gp_hilo_pla31pla33M5T1_4; reg ctl_reg_sys_hilo_pla31pla33M5T2_4; reg ctl_reg_sys_hilo_pla31npla33M2T1_3; reg ctl_reg_sys_hilo_pla31npla33M2T2_4; reg ctl_reg_sys_hilo_pla31npla33M2T3_6; reg ctl_reg_sys_hilo_pla31npla33M3T1_3; reg ctl_reg_sys_hilo_pla31npla33M3T2_4; reg ctl_reg_sys_hilo_pla31npla33M3T3_6; reg ctl_reg_sys_hilo_pla31npla33M4T1_3; reg ctl_reg_sys_hilo_pla31npla33M4T2_4; reg ctl_reg_gp_sel_pla31npla33M4T3_5; reg ctl_reg_gp_hilo_pla31npla33M4T3_6; reg ctl_reg_sys_hilo_pla31npla33M5T1_3; reg ctl_reg_sys_hilo_pla31npla33M5T2_4; reg ctl_reg_gp_sel_pla31npla33M5T3_4; reg ctl_reg_gp_hilo_pla31npla33M5T3_5; reg ctl_reg_gp_sel_pla5M1T4_2; reg ctl_reg_gp_hilo_pla5M1T4_3; reg ctl_reg_gp_sel_pla5M1T5_2; reg ctl_reg_gp_hilo_pla5M1T5_3; reg ctl_reg_gp_sel_pla23pla16M1T5_4; reg ctl_reg_gp_hilo_pla23pla16M1T5_5; reg ctl_reg_gp_sel_pla23pla16M2T1_5; reg ctl_reg_gp_hilo_pla23pla16M2T1_6; reg ctl_reg_gp_sel_pla23pla16M2T2_3; reg ctl_reg_gp_hilo_pla23pla16M2T2_4; reg ctl_reg_gp_sel_pla23pla16M2T3_5; reg ctl_reg_gp_hilo_pla23pla16M2T3_6; reg ctl_reg_gp_sel_pla23pla16M3T1_5; reg ctl_reg_gp_hilo_pla23pla16M3T1_6; reg ctl_reg_gp_sel_pla23pla16M3T2_3; reg ctl_reg_gp_hilo_pla23pla16M3T2_4; reg ctl_reg_gp_sel_pla23npla16M2T1_3; reg ctl_reg_gp_hilo_pla23npla16M2T1_4; reg ctl_reg_gp_sel_pla23npla16M2T2_3; reg ctl_reg_gp_hilo_pla23npla16M2T2_4; reg ctl_reg_gp_sel_pla23npla16M2T3_5; reg ctl_reg_gp_hilo_pla23npla16M2T3_6; reg ctl_reg_gp_sel_pla23npla16M3T1_3; reg ctl_reg_gp_hilo_pla23npla16M3T1_4; reg ctl_reg_gp_sel_pla23npla16M3T2_3; reg ctl_reg_gp_hilo_pla23npla16M3T2_4; reg ctl_reg_gp_sel_pla23npla16M3T3_4; reg ctl_reg_gp_hilo_pla23npla16M3T3_5; reg ctl_reg_gp_sel_pla10M2T1_3; reg ctl_reg_gp_hilo_pla10M2T1_4; reg ctl_reg_gp_sel_pla10M2T2_3; reg ctl_reg_gp_hilo_pla10M2T2_4; reg ctl_reg_sys_hilo_pla10M2T3_6; reg ctl_reg_gp_sel_pla10M3T1_3; reg ctl_reg_gp_hilo_pla10M3T1_4; reg ctl_reg_gp_sel_pla10M3T2_3; reg ctl_reg_gp_hilo_pla10M3T2_4; reg ctl_reg_sys_hilo_pla10M3T3_4; reg ctl_reg_gp_sel_pla10M3T4_4; reg ctl_reg_gp_hilo_pla10M3T4_5; reg ctl_reg_gp_sel_pla10M4T1_5; reg ctl_reg_gp_hilo_pla10M4T1_6; reg ctl_reg_gp_sel_pla10M4T2_3; reg ctl_reg_gp_hilo_pla10M4T2_4; reg ctl_reg_gp_sel_pla10M4T3_5; reg ctl_reg_gp_hilo_pla10M4T3_6; reg ctl_reg_gp_sel_pla10M5T1_5; reg ctl_reg_gp_hilo_pla10M5T1_6; reg ctl_reg_gp_sel_pla10M5T2_3; reg ctl_reg_gp_hilo_pla10M5T2_4; reg ctl_reg_sys_hilo_pla10M5T3_3; reg ctl_reg_gp_sel_pla10M5T4_2; reg ctl_reg_gp_hilo_pla10M5T4_3; reg ctl_pf_sel_pla12M1T1_12; reg ctl_reg_gp_sel_pla12M1T2_2; reg ctl_reg_gp_hilo_pla12M1T2_3; reg ctl_reg_gp_sel_pla12M1T3_1; reg ctl_reg_gp_hilo_pla12M1T3_2; reg ctl_reg_gp_sel_pla12M2T1_2; reg ctl_reg_gp_hilo_pla12M2T1_3; reg ctl_reg_gp_sel_pla12M2T2_3; reg ctl_reg_gp_hilo_pla12M2T2_4; reg ctl_reg_gp_sel_pla12M3T1_2; reg ctl_reg_gp_hilo_pla12M3T1_3; reg ctl_reg_gp_sel_pla12M3T2_3; reg ctl_reg_gp_hilo_pla12M3T2_4; reg ctl_reg_gp_sel_pla12M3T3_2; reg ctl_reg_gp_hilo_pla12M3T3_3; reg ctl_reg_gp_sel_pla12M3T4_2; reg ctl_reg_gp_hilo_pla12M3T4_3; reg ctl_reg_sys_hilo_pla12M4T1_2; reg ctl_reg_sys_hilo_pla12M4T2_3; reg ctl_reg_sys_hilo_pla12M4T3_2; reg ctl_reg_sys_hilo_pla12M4T4_3; reg ctl_pf_sel_pla11M1T1_11; reg ctl_reg_gp_sel_pla11M1T2_2; reg ctl_reg_gp_hilo_pla11M1T2_3; reg ctl_reg_gp_sel_pla11M1T3_1; reg ctl_reg_gp_hilo_pla11M1T3_2; reg ctl_reg_gp_sel_pla11M2T1_2; reg ctl_reg_gp_hilo_pla11M2T1_3; reg ctl_reg_gp_sel_pla11M2T2_3; reg ctl_reg_gp_hilo_pla11M2T2_4; reg ctl_reg_gp_sel_pla11M3T3_1; reg ctl_reg_gp_hilo_pla11M3T3_2; reg ctl_reg_gp_sel_pla11M3T4_2; reg ctl_reg_gp_hilo_pla11M3T4_3; reg ctl_reg_sys_hilo_pla11M4T1_2; reg ctl_reg_sys_hilo_pla11M4T2_3; reg ctl_reg_sys_hilo_pla11M4T3_2; reg ctl_reg_sys_hilo_pla11M4T4_3; reg ctl_reg_gp_sel_pla65npla52M1T2_2; reg ctl_reg_gp_hilo_pla65npla52M1T2_3; reg ctl_reg_gp_sel_pla65npla52M1T3_1; reg ctl_reg_gp_hilo_pla65npla52M1T3_2; reg ctl_reg_gp_sel_pla65npla52M1T4_3; reg ctl_reg_gp_hilo_pla65npla52M1T4_4; reg ctl_reg_gp_sel_pla64M1T2_2; reg ctl_reg_gp_hilo_pla64M1T2_3; reg ctl_reg_gp_sel_pla64M1T3_1; reg ctl_reg_gp_hilo_pla64M1T3_2; reg ctl_reg_gp_sel_pla64M1T4_4; reg ctl_reg_gp_hilo_pla64M1T4_5; reg ctl_reg_sys_hilo_pla64M2T1_3; reg ctl_reg_sys_hilo_pla64M2T2_4; reg ctl_reg_gp_sel_use_ixiypla52M1T3_1; reg ctl_reg_gp_hilo_use_ixiypla52M1T3_2; reg ctl_reg_sys_hilo_use_ixiypla52M2T1_3; reg ctl_reg_sys_hilo_use_ixiypla52M2T2_4; reg ctl_reg_gp_sel_nuse_ixiypla52M1T2_2; reg ctl_reg_gp_hilo_nuse_ixiypla52M1T2_3; reg ctl_reg_gp_sel_nuse_ixiypla52M1T3_1; reg ctl_reg_gp_hilo_nuse_ixiypla52M1T3_2; reg ctl_reg_gp_sel_nuse_ixiypla52M2T1_2; reg ctl_reg_gp_hilo_nuse_ixiypla52M2T1_3; reg ctl_reg_sys_hilo_nuse_ixiypla52M2T2_4; reg ctl_reg_gp_sel_nuse_ixiypla52M4T2_2; reg ctl_reg_gp_hilo_nuse_ixiypla52M4T2_3; reg ctl_reg_gp_sel_pla66npla53M1T1_2; reg ctl_reg_gp_hilo_pla66npla53M1T1_3; reg ctl_pf_sel_pla66npla53M1T1_15; reg ctl_reg_gp_sel_pla66npla53M1T2_2; reg ctl_reg_gp_hilo_pla66npla53M1T2_3; reg ctl_reg_gp_sel_pla66npla53M1T3_1; reg ctl_reg_gp_hilo_pla66npla53M1T3_2; reg ctl_reg_gp_sel_pla66npla53M1T4nop4op5nop3_1; reg ctl_reg_gp_hilo_pla66npla53M1T4nop4op5nop3_2; reg ctl_reg_gp_sel_use_ixiypla53M1T3_1; reg ctl_reg_gp_hilo_use_ixiypla53M1T3_2; reg ctl_reg_sys_hilo_use_ixiypla53M2T1_3; reg ctl_reg_sys_hilo_use_ixiypla53M2T2_4; reg ctl_reg_gp_sel_nuse_ixiypla53M1T2_2; reg ctl_reg_gp_hilo_nuse_ixiypla53M1T2_3; reg ctl_reg_gp_sel_nuse_ixiypla53M1T3_1; reg ctl_reg_gp_hilo_nuse_ixiypla53M1T3_2; reg ctl_reg_gp_sel_nuse_ixiypla53M2T1_2; reg ctl_reg_gp_hilo_nuse_ixiypla53M2T1_3; reg ctl_pf_sel_nuse_ixiypla53M2T4_14; reg ctl_pf_sel_nuse_ixiypla53M4T4_14; reg ctl_reg_gp_sel_pla69M1T2_2; reg ctl_reg_gp_hilo_pla69M1T2_3; reg ctl_reg_gp_sel_pla69M1T3_1; reg ctl_reg_gp_hilo_pla69M1T3_2; reg ctl_reg_gp_sel_pla69M1T4_3; reg ctl_reg_gp_hilo_pla69M1T4_4; reg ctl_reg_gp_sel_pla69M2T1_1; reg ctl_reg_gp_hilo_pla69M2T1_2; reg ctl_reg_sys_hilo_pla69M2T2_3; reg ctl_reg_gp_sel_pla69M2T3_1; reg ctl_reg_gp_hilo_pla69M2T3_2; reg ctl_reg_gp_sel_pla69M2T4_2; reg ctl_reg_gp_hilo_pla69M2T4_3; reg ctl_reg_sys_hilo_pla69M3T1_2; reg ctl_reg_sys_hilo_pla69M3T1_7; reg ctl_reg_gp_sel_pla69M3T2_2; reg ctl_reg_gp_hilo_pla69M3T2_3; reg ctl_reg_gp_sel_op3pla68M1T2_2; reg ctl_reg_gp_hilo_op3pla68M1T2_3; reg ctl_reg_gp_sel_op3pla68M1T3_1; reg ctl_reg_gp_hilo_op3pla68M1T3_2; reg ctl_reg_gp_sel_op3pla68M1T4_3; reg ctl_reg_gp_hilo_op3pla68M1T4_4; reg ctl_reg_gp_sel_op3pla68M2T1_1; reg ctl_reg_gp_hilo_op3pla68M2T1_2; reg ctl_reg_sys_hilo_op3pla68M2T2_3; reg ctl_reg_gp_sel_op3pla68M2T3_1; reg ctl_reg_gp_hilo_op3pla68M2T3_2; reg ctl_reg_gp_sel_op3pla68M2T4_2; reg ctl_reg_gp_hilo_op3pla68M2T4_3; reg ctl_reg_sys_hilo_op3pla68M3T1_2; reg ctl_reg_sys_hilo_op3pla68M3T1_7; reg ctl_pf_sel_op3pla68M3T1_18; reg ctl_reg_gp_sel_op3pla68M3T2_2; reg ctl_reg_gp_hilo_op3pla68M3T2_3; reg ctl_reg_gp_sel_nop3pla68M1T2_2; reg ctl_reg_gp_hilo_nop3pla68M1T2_3; reg ctl_reg_gp_sel_nop3pla68M1T3_1; reg ctl_reg_gp_hilo_nop3pla68M1T3_2; reg ctl_reg_gp_sel_nop3pla68M1T4_3; reg ctl_reg_gp_hilo_nop3pla68M1T4_4; reg ctl_reg_gp_sel_nop3pla68M2T1_1; reg ctl_reg_gp_hilo_nop3pla68M2T1_2; reg ctl_reg_sys_hilo_nop3pla68M2T2_3; reg ctl_reg_gp_sel_nop3pla68M2T3_1; reg ctl_reg_gp_hilo_nop3pla68M2T3_2; reg ctl_reg_gp_sel_nop3pla68M2T4_2; reg ctl_reg_gp_hilo_nop3pla68M2T4_3; reg ctl_reg_sys_hilo_nop3pla68M3T1_2; reg ctl_reg_sys_hilo_nop3pla68M3T1_7; reg ctl_pf_sel_nop3pla68M3T1_20; reg ctl_reg_gp_sel_nop3pla68M3T2_2; reg ctl_reg_gp_hilo_nop3pla68M3T2_3; reg ctl_reg_gp_sel_pla9M1T4_2; reg ctl_reg_gp_hilo_pla9M1T4_3; reg ctl_reg_gp_sel_pla9M1T5_2; reg ctl_reg_gp_hilo_pla9M1T5_3; reg ctl_reg_gp_sel_pla77M1T1_2; reg ctl_reg_gp_hilo_pla77M1T1_3; reg ctl_pf_sel_pla77M1T1_14; reg ctl_reg_gp_sel_pla77M1T2_2; reg ctl_reg_gp_hilo_pla77M1T2_3; reg ctl_reg_gp_sel_pla77M1T3_1; reg ctl_reg_gp_hilo_pla77M1T3_2; reg ctl_reg_gp_sel_pla81M1T1_2; reg ctl_reg_gp_hilo_pla81M1T1_3; reg ctl_reg_gp_sel_pla81M1T2_2; reg ctl_reg_gp_hilo_pla81M1T2_3; reg ctl_reg_gp_sel_pla81M1T3_1; reg ctl_reg_gp_hilo_pla81M1T3_2; reg ctl_reg_gp_sel_pla82M1T1_2; reg ctl_reg_gp_hilo_pla82M1T1_3; reg ctl_pf_sel_pla82M1T1_16; reg ctl_reg_gp_sel_pla82M1T2_2; reg ctl_reg_gp_hilo_pla82M1T2_3; reg ctl_reg_gp_sel_pla82M1T3_1; reg ctl_reg_gp_hilo_pla82M1T3_2; reg ctl_reg_gp_sel_pla89M1T2_2; reg ctl_reg_gp_hilo_pla89M1T2_3; reg ctl_reg_gp_sel_pla89M1T3_1; reg ctl_reg_gp_hilo_pla89M1T3_2; reg ctl_reg_gp_sel_pla92M1T2_2; reg ctl_reg_gp_hilo_pla92M1T2_3; reg ctl_reg_gp_sel_pla92M1T3_1; reg ctl_reg_gp_hilo_pla92M1T3_2; reg ctl_reg_gp_sel_pla25M1T1_2; reg ctl_reg_gp_hilo_pla25M1T1_3; reg ctl_reg_gp_sel_pla25M1T2_2; reg ctl_reg_gp_hilo_pla25M1T2_3; reg ctl_reg_gp_sel_pla25M1T3_1; reg ctl_reg_gp_hilo_pla25M1T3_2; reg ctl_reg_gp_sel_pla25M1T4_3; reg ctl_reg_gp_hilo_pla25M1T4_4; reg ctl_reg_gp_sel_nuse_ixiypla70npla55M1T1_2; reg ctl_reg_gp_hilo_nuse_ixiypla70npla55M1T1_3; reg ctl_pf_sel_nuse_ixiypla70npla55M1T1_20; reg ctl_reg_gp_sel_nuse_ixiypla70npla55M1T2_2; reg ctl_reg_gp_hilo_nuse_ixiypla70npla55M1T2_3; reg ctl_reg_gp_sel_nuse_ixiypla70npla55M1T3_1; reg ctl_reg_gp_hilo_nuse_ixiypla70npla55M1T3_2; reg ctl_reg_gp_sel_nuse_ixiypla70npla55M1T4_3; reg ctl_reg_gp_hilo_nuse_ixiypla70npla55M1T4_4; reg ctl_reg_sys_hilo_nuse_ixiypla70npla55M4T1_3; reg ctl_pf_sel_nuse_ixiypla70npla55M5T1_19; reg ctl_reg_gp_sel_nuse_ixiypla70pla55M1T2_2; reg ctl_reg_gp_hilo_nuse_ixiypla70pla55M1T2_3; reg ctl_reg_gp_sel_nuse_ixiypla70pla55M1T3_1; reg ctl_reg_gp_hilo_nuse_ixiypla70pla55M1T3_2; reg ctl_reg_gp_sel_nuse_ixiypla70pla55M2T1_2; reg ctl_reg_gp_hilo_nuse_ixiypla70pla55M2T1_3; reg ctl_pf_sel_nuse_ixiypla70pla55M3T1_19; reg ctl_reg_sys_hilo_nuse_ixiypla70pla55M4T1_3; reg ctl_pf_sel_nuse_ixiypla70pla55M5T1_19; reg ctl_reg_gp_sel_pla15op3M1T1_2; reg ctl_reg_gp_hilo_pla15op3M1T1_3; reg ctl_pf_sel_pla15op3M1T1_18; reg ctl_reg_gp_sel_pla15op3M1T2_2; reg ctl_reg_gp_hilo_pla15op3M1T2_3; reg ctl_reg_gp_sel_pla15op3M1T3_1; reg ctl_reg_gp_hilo_pla15op3M1T3_2; reg ctl_reg_gp_sel_pla15op3M2T1_2; reg ctl_reg_gp_hilo_pla15op3M2T1_3; reg ctl_reg_sys_hilo_pla15op3M2T2_4; reg ctl_reg_gp_sel_pla15nop3M1T1_2; reg ctl_reg_gp_hilo_pla15nop3M1T1_3; reg ctl_pf_sel_pla15nop3M1T1_18; reg ctl_reg_gp_sel_pla15nop3M1T2_2; reg ctl_reg_gp_hilo_pla15nop3M1T2_3; reg ctl_reg_gp_sel_pla15nop3M1T3_1; reg ctl_reg_gp_hilo_pla15nop3M1T3_2; reg ctl_reg_gp_sel_pla15nop3M2T1_2; reg ctl_reg_gp_hilo_pla15nop3M2T1_3; reg ctl_reg_sys_hilo_pla15nop3M2T2_4; reg ctl_reg_gp_sel_pla15nop3M3T3_1; reg ctl_reg_gp_hilo_pla15nop3M3T3_2; reg ctl_pf_sel_nuse_ixiypla72npla55M1T1_10; reg ctl_reg_gp_sel_nuse_ixiypla72npla55M1T2_2; reg ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T2_3; reg ctl_reg_gp_sel_nuse_ixiypla72npla55M1T3_1; reg ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T3_2; reg ctl_reg_gp_sel_nuse_ixiypla72npla55M1T4_3; reg ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4; reg ctl_pf_sel_nuse_ixiypla72pla55M1T1_10; reg ctl_reg_gp_sel_nuse_ixiypla72pla55M1T2_2; reg ctl_reg_gp_hilo_nuse_ixiypla72pla55M1T2_3; reg ctl_reg_gp_sel_nuse_ixiypla72pla55M1T3_1; reg ctl_reg_gp_hilo_nuse_ixiypla72pla55M1T3_2; reg ctl_reg_gp_sel_nuse_ixiypla72pla55M2T1_2; reg ctl_reg_gp_hilo_nuse_ixiypla72pla55M2T1_3; reg ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3; reg ctl_reg_sys_hilo_nuse_ixiypla72pla55M4T1_3; reg ctl_reg_gp_sel_nuse_ixiypla74npla55M1T1_2; reg ctl_reg_gp_hilo_nuse_ixiypla74npla55M1T1_3; reg ctl_reg_gp_sel_nuse_ixiypla74npla55M1T3_1; reg ctl_reg_gp_hilo_nuse_ixiypla74npla55M1T3_2; reg ctl_reg_gp_sel_nuse_ixiypla74npla55M1T4_3; reg ctl_reg_gp_hilo_nuse_ixiypla74npla55M1T4_4; reg ctl_reg_sys_hilo_nuse_ixiypla74npla55M4T1_3; reg ctl_reg_gp_sel_nuse_ixiypla74pla55M1T3_1; reg ctl_reg_gp_hilo_nuse_ixiypla74pla55M1T3_2; reg ctl_reg_gp_sel_nuse_ixiypla74pla55M2T1_2; reg ctl_reg_gp_hilo_nuse_ixiypla74pla55M2T1_3; reg ctl_reg_sys_hilo_nuse_ixiypla74pla55M4T1_3; reg ctl_reg_gp_sel_nuse_ixiypla73npla55M1T1_2; reg ctl_reg_gp_hilo_nuse_ixiypla73npla55M1T1_3; reg ctl_reg_gp_sel_nuse_ixiypla73npla55M1T3_1; reg ctl_reg_gp_hilo_nuse_ixiypla73npla55M1T3_2; reg ctl_reg_gp_sel_nuse_ixiypla73npla55M1T4_3; reg ctl_reg_gp_hilo_nuse_ixiypla73npla55M1T4_4; reg ctl_reg_sys_hilo_nuse_ixiypla73npla55M4T1_3; reg ctl_reg_gp_sel_nuse_ixiypla73pla55M1T3_1; reg ctl_reg_gp_hilo_nuse_ixiypla73pla55M1T3_2; reg ctl_reg_gp_sel_nuse_ixiypla73pla55M2T1_2; reg ctl_reg_gp_hilo_nuse_ixiypla73pla55M2T1_3; reg ctl_reg_sys_hilo_nuse_ixiypla73pla55M4T1_3; reg ctl_reg_gp_sel_pla37npla28M1T1_2; reg ctl_reg_gp_hilo_pla37npla28M1T1_3; reg ctl_reg_sys_hilo_pla37npla28M2T1_3; reg ctl_reg_sys_hilo_pla37npla28M2T2_4; reg ctl_reg_gp_sel_pla37npla28M3T1_2; reg ctl_reg_gp_hilo_pla37npla28M3T1_3; reg ctl_reg_gp_sel_pla27npla34M1T1_2; reg ctl_reg_gp_hilo_pla27npla34M1T1_3; reg ctl_pf_sel_pla27npla34M1T1_20; reg ctl_reg_gp_sel_pla27npla34M1T2_2; reg ctl_reg_gp_hilo_pla27npla34M1T2_3; reg ctl_reg_gp_sel_pla27npla34M1T3_1; reg ctl_reg_gp_hilo_pla27npla34M1T3_2; reg ctl_reg_gp_sel_pla27npla34M2T1_2; reg ctl_reg_gp_hilo_pla27npla34M2T1_3; reg ctl_reg_sys_hilo_pla37pla28M2T1_3; reg ctl_reg_sys_hilo_pla37pla28M2T2_4; reg ctl_reg_gp_sel_pla37pla28M2T3_4; reg ctl_reg_gp_hilo_pla37pla28M2T3_5; reg ctl_reg_gp_sel_pla37pla28M3T1_3; reg ctl_reg_gp_hilo_pla37pla28M3T1_4; reg ctl_reg_gp_sel_pla27pla34M1T4nop4op5nop3_1; reg ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2; reg ctl_reg_gp_sel_pla27pla34M2T1_2; reg ctl_reg_gp_hilo_pla27pla34M2T1_3; reg ctl_pf_sel_pla91pla21M1T1_8; reg ctl_reg_gp_sel_pla91pla21M1T2_2; reg ctl_reg_gp_hilo_pla91pla21M1T2_3; reg ctl_reg_gp_sel_pla91pla21M1T3_1; reg ctl_reg_gp_hilo_pla91pla21M1T3_2; reg ctl_reg_gp_sel_pla91pla21M2T1_2; reg ctl_reg_gp_hilo_pla91pla21M2T1_3; reg ctl_reg_gp_sel_pla91pla21M2T2_2; reg ctl_reg_gp_hilo_pla91pla21M2T2_3; reg ctl_reg_gp_sel_pla91pla21M2T3_3; reg ctl_reg_gp_hilo_pla91pla21M2T3_4; reg ctl_reg_gp_sel_pla91pla21M3T1_2; reg ctl_reg_gp_hilo_pla91pla21M3T1_3; reg ctl_reg_gp_sel_pla91pla21M3T2_3; reg ctl_reg_gp_hilo_pla91pla21M3T2_4; reg ctl_reg_sys_hilo_pla91pla21M4T1_2; reg ctl_reg_sys_hilo_pla91pla21M4T2_3; reg ctl_reg_sys_hilo_pla91pla21M4T3_2; reg ctl_reg_sys_hilo_pla91pla21M4T4_3; reg ctl_pf_sel_pla91pla20M1T1_9; reg ctl_reg_gp_sel_pla91pla20M1T2_2; reg ctl_reg_gp_hilo_pla91pla20M1T2_3; reg ctl_reg_gp_sel_pla91pla20M1T3_1; reg ctl_reg_gp_hilo_pla91pla20M1T3_2; reg ctl_reg_gp_sel_pla91pla20M1T4_2; reg ctl_reg_gp_hilo_pla91pla20M1T4_3; reg ctl_reg_gp_sel_pla91pla20M1T5_4; reg ctl_reg_gp_hilo_pla91pla20M1T5_5; reg ctl_reg_gp_sel_pla91pla20M2T1_2; reg ctl_reg_gp_hilo_pla91pla20M2T1_3; reg ctl_reg_gp_sel_pla91pla20M2T2_3; reg ctl_reg_gp_hilo_pla91pla20M2T2_4; reg ctl_reg_gp_sel_pla91pla20M2T3_4; reg ctl_reg_gp_hilo_pla91pla20M2T3_5; reg ctl_reg_gp_sel_pla91pla20M3T1_2; reg ctl_reg_gp_hilo_pla91pla20M3T1_3; reg ctl_reg_sys_hilo_pla91pla20M4T1_2; reg ctl_reg_sys_hilo_pla91pla20M4T2_3; reg ctl_reg_sys_hilo_pla91pla20M4T3_2; reg ctl_reg_sys_hilo_pla91pla20M4T4_3; reg ctl_reg_sys_hilo_pla29M2T1_3; reg ctl_reg_sys_hilo_pla29M2T2_4; reg ctl_reg_sys_hilo_pla29M2T3_6; reg ctl_reg_sys_hilo_pla29M3T1_3; reg ctl_reg_sys_hilo_pla29M3T2_4; reg ctl_reg_sys_hilo_pla29M3T3_4; reg ctl_reg_sys_hilo_pla29M3T3_9; reg ctl_reg_gp_sel_pla43M1T3_1; reg ctl_reg_gp_hilo_pla43M1T3_2; reg ctl_reg_sys_hilo_pla43M2T1_3; reg ctl_reg_sys_hilo_pla43M2T2_4; reg ctl_reg_sys_hilo_pla43M2T3_6; reg ctl_reg_sys_hilo_pla43M3T1_3; reg ctl_reg_sys_hilo_pla43M3T2_4; reg ctl_reg_sys_hilo_pla43M3T3_5; reg ctl_reg_sys_hilo_pla43M3T3_10; reg ctl_reg_gp_sel_pla47M1T3_1; reg ctl_reg_gp_hilo_pla47M1T3_2; reg ctl_reg_sys_hilo_pla47M2T1_3; reg ctl_reg_sys_hilo_pla47M2T2_4; reg ctl_reg_sys_hilo_pla47M3T2_2; reg ctl_reg_sys_hilo_pla47M3T3_3; reg ctl_reg_sys_hilo_pla47M3T4_2; reg ctl_reg_sys_hilo_pla47M3T5_3; reg ctl_reg_sys_hilo_pla47M3T5_8; reg ctl_reg_gp_sel_pla48M1T3_1; reg ctl_reg_gp_hilo_pla48M1T3_2; reg ctl_reg_sys_hilo_pla48M2T1_3; reg ctl_reg_sys_hilo_pla48M2T2_4; reg ctl_reg_sys_hilo_pla48M3T2_2; reg ctl_reg_sys_hilo_pla48M3T3_3; reg ctl_reg_sys_hilo_pla48M3T4_2; reg ctl_reg_sys_hilo_pla48M3T5_3; reg ctl_reg_sys_hilo_pla48M3T5_8; reg ctl_reg_gp_sel_pla6M1T4_3; reg ctl_reg_gp_hilo_pla6M1T4_4; reg ctl_reg_gp_sel_pla26M1T3_1; reg ctl_reg_gp_hilo_pla26M1T3_2; reg ctl_reg_gp_sel_pla26M1T4_2; reg ctl_reg_gp_hilo_pla26M1T4_3; reg ctl_reg_gp_sel_pla26M1T5_4; reg ctl_reg_gp_hilo_pla26M1T5_5; reg ctl_reg_sys_hilo_pla26M2T1_3; reg ctl_reg_sys_hilo_pla26M2T2_4; reg ctl_reg_sys_hilo_pla26M3T2_2; reg ctl_reg_sys_hilo_pla26M3T3_3; reg ctl_reg_sys_hilo_pla26M3T4_2; reg ctl_reg_sys_hilo_pla26M3T5_3; reg ctl_reg_sys_hilo_pla26M3T5_8; reg ctl_reg_sys_hilo_pla24M2T1_3; reg ctl_reg_sys_hilo_pla24M2T2_4; reg ctl_reg_sys_hilo_pla24M2T3_6; reg ctl_reg_sys_hilo_pla24M3T1_3; reg ctl_reg_sys_hilo_pla24M3T2_4; reg ctl_reg_sys_hilo_pla24M3T3_4; reg ctl_reg_gp_sel_pla24M3T4_4; reg ctl_reg_gp_hilo_pla24M3T4_5; reg ctl_reg_sys_hilo_pla24M4T1_6; reg ctl_reg_gp_sel_pla24M4T2_3; reg ctl_reg_gp_hilo_pla24M4T2_4; reg ctl_reg_gp_sel_pla24M4T3_5; reg ctl_reg_gp_hilo_pla24M4T3_6; reg ctl_reg_sys_hilo_pla24M5T1_6; reg ctl_reg_gp_sel_pla24M5T2_3; reg ctl_reg_gp_hilo_pla24M5T2_4; reg ctl_reg_sys_hilo_pla24M5T3_4; reg ctl_reg_gp_sel_pla42M1T3_1; reg ctl_reg_gp_hilo_pla42M1T3_2; reg ctl_reg_sys_hilo_pla42M2T1_3; reg ctl_reg_sys_hilo_pla42M2T2_4; reg ctl_reg_sys_hilo_pla42M2T3_6; reg ctl_reg_sys_hilo_pla42M3T1_3; reg ctl_reg_sys_hilo_pla42M3T2_4; reg ctl_reg_sys_hilo_pla42M3T3_6; reg ctl_reg_gp_sel_pla42M3T4_4; reg ctl_reg_gp_hilo_pla42M3T4_5; reg ctl_reg_sys_hilo_pla42M4T1_6; reg ctl_reg_gp_sel_pla42M4T2_3; reg ctl_reg_gp_hilo_pla42M4T2_4; reg ctl_reg_gp_sel_pla42M4T3_5; reg ctl_reg_gp_hilo_pla42M4T3_6; reg ctl_reg_sys_hilo_pla42M5T1_6; reg ctl_reg_gp_sel_pla42M5T2_3; reg ctl_reg_gp_hilo_pla42M5T2_4; reg ctl_reg_sys_hilo_pla42M5T3_4; reg ctl_reg_gp_sel_pla35M2T1_3; reg ctl_reg_gp_hilo_pla35M2T1_4; reg ctl_reg_gp_sel_pla35M2T2_3; reg ctl_reg_gp_hilo_pla35M2T2_4; reg ctl_reg_sys_hilo_pla35M2T3_6; reg ctl_reg_gp_sel_pla35M3T1_3; reg ctl_reg_gp_hilo_pla35M3T1_4; reg ctl_reg_gp_sel_pla35M3T2_3; reg ctl_reg_gp_hilo_pla35M3T2_4; reg ctl_reg_sys_hilo_pla35M3T3_4; reg ctl_reg_sys_hilo_pla35M3T3_9; reg ctl_reg_gp_sel_pla45M1T3_1; reg ctl_reg_gp_hilo_pla45M1T3_2; reg ctl_reg_gp_sel_pla45M2T1_3; reg ctl_reg_gp_hilo_pla45M2T1_4; reg ctl_reg_gp_sel_pla45M2T2_3; reg ctl_reg_gp_hilo_pla45M2T2_4; reg ctl_reg_sys_hilo_pla45M2T3_6; reg ctl_reg_gp_sel_pla45M3T1_3; reg ctl_reg_gp_hilo_pla45M3T1_4; reg ctl_reg_gp_sel_pla45M3T2_3; reg ctl_reg_gp_hilo_pla45M3T2_4; reg ctl_reg_sys_hilo_pla45M3T3_4; reg ctl_reg_sys_hilo_pla45M3T3_9; reg ctl_reg_gp_sel_pla46M2T1_3; reg ctl_reg_gp_hilo_pla46M2T1_4; reg ctl_reg_gp_sel_pla46M2T2_3; reg ctl_reg_gp_hilo_pla46M2T2_4; reg ctl_reg_sys_hilo_pla46M2T3_6; reg ctl_reg_gp_sel_pla46M3T1_3; reg ctl_reg_gp_hilo_pla46M3T1_4; reg ctl_reg_gp_sel_pla46M3T2_3; reg ctl_reg_gp_hilo_pla46M3T2_4; reg ctl_reg_sys_hilo_pla46M3T3_4; reg ctl_reg_sys_hilo_pla46M3T3_9; reg ctl_reg_sys_hilo_pla56M1T3_3; reg ctl_reg_gp_sel_pla56M1T5_4; reg ctl_reg_gp_hilo_pla56M1T5_5; reg ctl_reg_sys_hilo_pla56M2T1_6; reg ctl_reg_gp_sel_pla56M2T2_3; reg ctl_reg_gp_hilo_pla56M2T2_4; reg ctl_reg_gp_sel_pla56M2T3_5; reg ctl_reg_gp_hilo_pla56M2T3_6; reg ctl_reg_sys_hilo_pla56M3T1_6; reg ctl_reg_gp_sel_pla56M3T2_3; reg ctl_reg_gp_hilo_pla56M3T2_4; reg ctl_reg_sys_hilo_pla56M3T3_6; reg ctl_reg_sys_hilo_pla56M4T1_3; reg ctl_reg_sys_hilo_pla56M4T3_6; reg ctl_reg_sys_hilo_pla56M5T1_3; reg ctl_reg_sys_hilo_pla56M5T3_4; reg ctl_reg_sys_hilo_pla56M5T3_9; reg ctl_reg_gp_sel_pla49M1T3_1; reg ctl_reg_gp_hilo_pla49M1T3_2; reg ctl_reg_sys_hilo_pla49M2T1_3; reg ctl_reg_sys_hilo_pla49M2T2_4; reg ctl_reg_sys_hilo_pla49M3T1_3; reg ctl_reg_sys_hilo_pla49M3T2_4; reg ctl_pf_sel_pla76M1T1_2; reg ctl_reg_gp_sel_pla78M1T1_2; reg ctl_reg_gp_hilo_pla78M1T1_3; reg ctl_pf_sel_pla78M1T1_8; reg ctl_reg_gp_sel_pla79M1T1_2; reg ctl_reg_gp_hilo_pla79M1T1_3; reg ctl_pf_sel_pla79M1T1_8; reg ctl_reg_gp_sel_pla80M1T1_2; reg ctl_reg_gp_hilo_pla80M1T1_3; reg ctl_pf_sel_pla80M1T1_8; reg ctl_reg_gp_sel_pla84M1T1_2; reg ctl_reg_gp_hilo_pla84M1T1_3; reg ctl_pf_sel_pla84M1T1_8; reg ctl_reg_gp_sel_pla85M1T1_2; reg ctl_reg_gp_hilo_pla85M1T1_3; reg ctl_pf_sel_pla85M1T1_8; reg ctl_reg_gp_sel_pla86M1T1_2; reg ctl_reg_gp_hilo_pla86M1T1_3; reg ctl_pf_sel_pla86M1T1_8; reg ctl_reg_gp_sel_pla88M1T1_2; reg ctl_reg_gp_hilo_pla88M1T1_3; reg ctl_pf_sel_pla88M1T1_8; reg ctl_reg_gp_sel_ixy_dT2_1; reg ctl_reg_gp_hilo_ixy_dT2_2; reg ctl_reg_sys_hilo_ixy_dT3_3; reg ctl_reg_gp_sel_ixy_dT4_1; reg ctl_reg_gp_hilo_ixy_dT4_2; reg ctl_reg_sys_hilo_ixy_dT5_2; reg ctl_reg_sys_hilo_ixy_dT5_7; reg ctl_reg_sys_hilo_1M1T1_3; reg ctl_reg_sys_hilo_1M1T2_2; reg ctl_reg_sys_hilo_1M1T3_3; reg ctl_reg_sys_hilo_setM1_2; ================================================ FILE: cpu/control/test_control.qpf ================================================ # -------------------------------------------------------------------------- # # # Copyright (C) 1991-2013 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Altera Program License # Subscription Agreement, Altera MegaCore Function License # Agreement, or other applicable license agreement, including, # without limitation, that your use is for the sole purpose of # programming logic devices manufactured by Altera and sold by # Altera or its authorized distributors. Please refer to the # applicable agreement for further details. # # -------------------------------------------------------------------------- # # # Quartus II 64-Bit # Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition # Date created = 09:22:29 October 13, 2014 # # -------------------------------------------------------------------------- # QUARTUS_VERSION = "13.0" DATE = "09:22:29 October 13, 2014" # Revisions PROJECT_REVISION = "test_control" ================================================ FILE: cpu/control/test_control.qsf ================================================ # -------------------------------------------------------------------------- # # # Copyright (C) 1991-2013 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Altera Program License # Subscription Agreement, Altera MegaCore Function License # Agreement, or other applicable license agreement, including, # without limitation, that your use is for the sole purpose of # programming logic devices manufactured by Altera and sold by # Altera or its authorized distributors. Please refer to the # applicable agreement for further details. # # -------------------------------------------------------------------------- # # # Quartus II 64-Bit # Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition # Date created = 09:22:29 October 13, 2014 # # -------------------------------------------------------------------------- # # # Notes: # # 1) The default values for assignments are stored in the file: # test_control_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # # 2) Altera recommends that you do not modify this file. This # file is updated automatically by the Quartus II software # and any changes you make may be lost or overwritten. # # -------------------------------------------------------------------------- # set_global_assignment -name FAMILY "Cyclone II" set_global_assignment -name DEVICE EP2C20F484C7 set_global_assignment -name TOP_LEVEL_ENTITY execute set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:22:29 OCTOBER 13, 2014" set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" set_global_assignment -name USE_CONFIGURATION_DEVICE ON set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP" set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS OFF set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON set_global_assignment -name VERILOG_FILE pla_decode.v set_global_assignment -name VERILOG_FILE execute.v set_global_assignment -name BDF_FILE sequencer.bdf set_global_assignment -name BDF_FILE resets.bdf set_global_assignment -name BDF_FILE memory_ifc.bdf set_global_assignment -name BDF_FILE ir.bdf set_global_assignment -name BDF_FILE interrupts.bdf set_global_assignment -name BDF_FILE decode_state.bdf set_global_assignment -name BDF_FILE clk_delay.bdf set_global_assignment -name BDF_FILE pin_control.bdf set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top ================================================ FILE: cpu/control/test_decode.sv ================================================ //============================================================== // Test PLA decode and combinatorial static execute //============================================================== `timescale 100 ns/ 100 ns module test_decode; reg [7:0] ir_sig; reg [4:0] prefix_sig; wire [107:0] pla_sig; // ----------------- TEST ------------------- initial begin integer opcode; // Test every opcode in the first table //================================================ // Regular instructions with no prefix //================================================ $display("START IXY0:XX"); opcode = 0; while(opcode<256) begin #1 $display("OPCODE: 0x%2H", opcode); prefix_sig[4:0] = 5'b10100; ir_sig[7:0] = opcode; #1 // Reset the IR into NOP so we get the trigger signal again prefix_sig[4:0] = 5'b01100; ir_sig[7:0] = 0; opcode++; end #1 $display("END"); //================================================ // Regular instructions with IX/IY prefix //================================================ $display("START IXY1:XX"); opcode = 0; while(opcode<256) begin #1 $display("OPCODE: 0x%2H", opcode); prefix_sig[4:0] = 5'b01100; ir_sig[7:0] = opcode; #1 // Reset the IR into NOP so we get the trigger signal again prefix_sig[4:0] = 5'b01100; ir_sig[7:0] = 0; opcode++; end #1 $display("END"); //================================================ // CD instructions with no prefix //================================================ $display("START IXY0:CB"); opcode = 0; while(opcode<256) begin #1 $display("OPCODE: 0x%2H", opcode); prefix_sig[4:0] = 5'b10010; ir_sig[7:0] = opcode; #1 // Reset the IR into NOP so we get the trigger signal again prefix_sig[4:0] = 5'b01100; ir_sig[7:0] = 0; opcode++; end #1 $display("END"); //================================================ // CB instructions with IX/IY prefix //================================================ $display("START IXY1:CB"); opcode = 0; while(opcode<256) begin #1 $display("OPCODE: 0x%2H", opcode); prefix_sig[4:0] = 5'b01010; ir_sig[7:0] = opcode; #1 // Reset the IR into NOP so we get the trigger signal again prefix_sig[4:0] = 5'b01100; ir_sig[7:0] = 0; opcode++; end #1 $display("END"); //================================================ // ED instructions with no prefix //================================================ $display("START IXY0:ED"); opcode = 0; while(opcode<256) begin #1 $display("OPCODE: 0x%2H", opcode); prefix_sig[4:0] = 5'b10001; ir_sig[7:0] = opcode; #1 // Reset the IR into NOP so we get the trigger signal again prefix_sig[4:0] = 5'b01100; ir_sig[7:0] = 0; opcode++; end #1 $display("END"); //================================================ // ED instructions with IX/IY prefix //================================================ $display("START IXY1:ED"); opcode = 0; while(opcode<256) begin #1 $display("OPCODE: 0x%2H", opcode); prefix_sig[4:0] = 5'b01001; ir_sig[7:0] = opcode; #1 // Reset the IR into NOP so we get the trigger signal again prefix_sig[4:0] = 5'b01001; ir_sig[7:0] = 0; opcode++; end #1 $display("END"); end //-------------------------------------------------------------- // Instantiate decode blocks //-------------------------------------------------------------- pla_decode pla_decode_inst ( .prefix(prefix_sig) , // input [6:0] prefix_sig .opcode(ir_sig) , // input [7:0] opcode .pla(pla_sig) // output [104:0] pla_sig ); execute execute_inst ( .pla(pla_sig) , // input [107:0] pla_sig .M1(M1_sig) , // input M1_sig .M2(M2_sig) , // input M2_sig .M3(M3_sig) , // input M3_sig .M4(M4_sig) , // input M4_sig .M5(M5_sig) , // input M5_sig .T1(T1_sig) , // input T1_sig .T2(T2_sig) , // input T2_sig .T3(T3_sig) , // input T3_sig .T4(T4_sig) , // input T4_sig .T5(T5_sig) , // input T5_sig .T6(T6_sig) , // input T6_sig .nextM(nextM_sig) , // output nextM_sig .setM1(setM1_sig) , // output setM1_sig .setM1ss(setM1ss_sig) , // output setM1ss_sig .setM1cc(setM1cc_sig) , // output setM1cc_sig .setM1bz(setM1bz_sig) , // output setM1bz_sig .fFetch(fFetch_sig) , // output fFetch_sig .fMRead(fMRead_sig) , // output fMRead_sig .fMWrite(fMWrite_sig) , // output fMWrite_sig .fIORead(fIORead_sig) , // output fIORead_sig .fIOWrite(fIOWrite_sig) , // output fIOWrite_sig .FIntr(FIntr_sig) , // output FIntr_sig .ctl_bus_sw1(ctl_bus_sw1_sig) , // output ctl_bus_sw1_sig .ctl_bus_sw2(ctl_bus_sw2_sig) , // output ctl_bus_sw2_sig .ctl_bus_sw4(ctl_bus_sw4_sig) , // output ctl_bus_sw4_sig .ctl_al_we(ctl_al_we_sig) , // output ctl_al_we_sig .ctl_inc_dec(ctl_inc_dec_sig) , // output ctl_inc_dec_sig .ctl_inc_limit6(ctl_inc_limit6_sig) , // output ctl_inc_limit6_sig .ctl_inc_cy(ctl_inc_cy_sig) , // output ctl_inc_cy_sig .ctl_ab_mux_inc(ctl_ab_mux_inc_sig) , // output ctl_ab_mux_inc_sig .explode(explode_sig) // output explode_sig ); endmodule ================================================ FILE: cpu/control/test_interrupts.sv ================================================ //============================================================== // Test interrupts unit //============================================================== `timescale 100 ns/ 100 ns module test_interrupts; // ----------------- CLOCKS AND RESET ----------------- // Define one full T-clock cycle delay `define T #2 bit clk = 1; initial repeat (20) #1 clk = ~clk; logic nreset = 0; // ----------------- CONTROL ---------------- logic ctl_iff1_iff2_sig=0; logic ctl_iffx_we_sig=0; logic ctl_iffx_bit_sig=0; logic nmi_sig=0; logic setM1_sig=0; logic intr_sig=0; logic ctl_im_we_sig=0; logic [1:0] db_sig=0; logic clk_sig=0; logic ctl_no_ints_sig=0; // ----------------- STATES ---------------- wire iff1_sig; assign iff1_sig = interrupts_inst.iff1; wire iff2_sig; wire im1_sig; wire im2_sig; wire in_nmi_sig; wire in_intr_sig; // ----------------- TEST ------------------- initial begin // Init / reset `T nreset = 1; // Test interrupt modes db_sig = 2'b10; // IM1 ctl_im_we_sig = 1; `T assert(im1_sig==1 && im2_sig==0); db_sig = 2'b11; // IM2 `T assert(im1_sig==0 && im2_sig==1); db_sig = 2'b00; // IM0 `T assert(im1_sig==0 && im2_sig==0); // Test IFF state flags assert(iff1_sig==0 && iff2_sig==0); ctl_iff1_iff2_sig = 1; ctl_iffx_we_sig = 1; ctl_iffx_bit_sig = 1; `T assert(iff1_sig==0 && iff2_sig==1); `T assert(iff1_sig==1 && iff2_sig==1); ctl_iff1_iff2_sig = 0; ctl_iffx_we_sig = 0; ctl_iffx_bit_sig = 0; // Simulate NMI triggering nmi_sig = 1; `T setM1_sig = 1; `T assert(iff1_sig==0 && iff2_sig==1); `T $display("End of test"); end //-------------------------------------------------------------- // Instantiate interrupts //-------------------------------------------------------------- interrupts interrupts_inst ( .ctl_iff1_iff2(ctl_iff1_iff2_sig) , // input ctl_iff1_iff2_sig .nmi(nmi_sig) , // input nmi_sig .setM1(setM1_sig) , // input setM1_sig .intr(intr_sig) , // input intr_sig .ctl_iffx_we(ctl_iffx_we_sig) , // input ctl_iffx_we_sig .ctl_iffx_bit(ctl_iffx_bit_sig) , // input ctl_iffx_bit_sig .ctl_im_we(ctl_im_we_sig) , // input ctl_im_we_sig .db(db_sig) , // input [1:0] db_sig .clk(clk) , // input clk .ctl_no_ints(ctl_no_ints_sig) , // input ctl_no_ints_sig .nreset(nreset) , // input nreset .iff2(iff2_sig) , // output iff2_sig .im1(im1_sig) , // output im1_sig .im2(im2_sig) , // output im2_sig .in_nmi(in_nmi_sig) , // output in_nmi_sig .in_intr(in_intr_sig) // output in_intr_sig ); endmodule ================================================ FILE: cpu/control/test_pin_control.sv ================================================ //============================================================== // Test pin control unit //============================================================== `timescale 100 ns/ 100 ns module test_pin_control; // ----------------- CONTROL ---------------- logic fFetch_sig=0; logic fMRead_sig=0; logic fMWrite_sig=0; logic fIORead_sig=0; logic fIOWrite_sig=0; logic T1_sig=0; logic T2_sig=0; logic T3_sig=0; logic T4_sig=0; // ----------------- STATES ---------------- wire bus_ab_pin_we_sig; wire bus_db_pin_oe_sig; wire bus_db_pin_re_sig; // ----------------- TEST ------------------- initial begin // Initial condition #1 assert(bus_ab_pin_we_sig==0 && bus_db_pin_oe_sig==0 && bus_db_pin_re_sig==0); // Activate formula for each signal fFetch_sig = 1; T1_sig = 1; #1 assert(bus_ab_pin_we_sig==1 && bus_db_pin_oe_sig==0 && bus_db_pin_re_sig==0); T1_sig = 0; T3_sig = 1; #1 assert(bus_ab_pin_we_sig==1 && bus_db_pin_oe_sig==0 && bus_db_pin_re_sig==0); fFetch_sig = 0; T1_sig = 0; T3_sig = 0; #1 assert(bus_ab_pin_we_sig==0 && bus_db_pin_oe_sig==0 && bus_db_pin_re_sig==0); // Read phase fMRead_sig = 1; #1 assert(bus_ab_pin_we_sig==0 && bus_db_pin_oe_sig==0 && bus_db_pin_re_sig==0); T1_sig = 1; #1 assert(bus_ab_pin_we_sig==1 && bus_db_pin_oe_sig==0 && bus_db_pin_re_sig==0); // Write phase fMRead_sig = 0; fMWrite_sig = 1; fIORead_sig = 0; fIOWrite_sig = 0; #1 assert(bus_ab_pin_we_sig==1 && bus_db_pin_oe_sig==0 && bus_db_pin_re_sig==0); // IO Read phase fMRead_sig = 0; fMWrite_sig = 0; fIORead_sig = 1; fIOWrite_sig = 0; #1 assert(bus_ab_pin_we_sig==1 && bus_db_pin_oe_sig==0 && bus_db_pin_re_sig==0); // IO Write phase fMRead_sig = 0; fMWrite_sig = 0; fIORead_sig = 0; fIOWrite_sig = 1; #1 assert(bus_ab_pin_we_sig==1 && bus_db_pin_oe_sig==0 && bus_db_pin_re_sig==0); fIOWrite_sig = 0; #1 assert(bus_ab_pin_we_sig==0 && bus_db_pin_oe_sig==0 && bus_db_pin_re_sig==0); // Test bus pin control T2_sig = 1; fMWrite_sig = 1; #1 assert(bus_ab_pin_we_sig==1 && bus_db_pin_oe_sig==1 && bus_db_pin_re_sig==0); fMWrite_sig = 0; fIORead_sig = 1; #1 assert(bus_ab_pin_we_sig==1 && bus_db_pin_oe_sig==0 && bus_db_pin_re_sig==0); T3_sig = 1; #1 assert(bus_ab_pin_we_sig==1 && bus_db_pin_oe_sig==0 && bus_db_pin_re_sig==1); #1 $display("End of test"); end //-------------------------------------------------------------- // Instantiate pin control //-------------------------------------------------------------- pin_control pin_control_inst ( .fFetch(fFetch_sig) , // input fFetch_sig .fMRead(fMRead_sig) , // input fMRead_sig .fMWrite(fMWrite_sig) , // input fMWrite_sig .fIORead(fIORead_sig) , // input fIORead_sig .fIOWrite(fIOWrite_sig) , // input fIOWrite_sig .T1(T1_sig) , // input T1_sig .T2(T2_sig) , // input T2_sig .T3(T3_sig) , // input T3_sig .T4(T4_sig) , // input T4_sig .bus_ab_pin_we(bus_ab_pin_we_sig) , // output bus_ab_pin_we_sig .bus_db_pin_oe(bus_db_pin_oe_sig) , // output bus_db_pin_oe_sig .bus_db_pin_re(bus_db_pin_re_sig) // output bus_db_pin_re_sig ); endmodule ================================================ FILE: cpu/control/test_reset.sv ================================================ //============================================================== // Test reset circuit //============================================================== `timescale 100 ns/ 100 ns module test_reset; // ----------------- CLOCKS AND RESET ----------------- `define T #2 bit clk = 1; initial repeat (40) #1 clk = ~clk; // Specific to FPGA, some modules in the schematic need to be pre-initialized reg fpga_reset = 1; always_latch if (clk) fpga_reset <= 0; //---------------------------------------------------------- // Input reset from the pin; state from the sequencer //---------------------------------------------------------- logic reset_in = 0; logic M1 = 0; logic T2 = 0; wire clrpc; // Load 0 to PC wire nhold_clk_wait; // Hold clrpc wire nreset; // Internal inverted reset signal assign nhold_clk_wait = 1; // Will not test this case // ----------------- TEST ------------------- initial begin // Test normal reset sequence - 3 clocks long `T reset_in = 1; `T `T `T reset_in = 0; `T assert(nreset==0); // Out of the reset for several more cycles // Check that the clrpc is set for the next 2 1/2 cycles (see waveform) `T assert(nreset==1 && clrpc==1); `T assert(nreset==1 && clrpc==1); `T assert(nreset==1 && clrpc==0); `T assert(nreset==1 && clrpc==0); `T assert(nreset==1 && clrpc==0); // Test special reset sequence: a reset pin is briefly // asserted at M1/T1 and CLRPC should hold until the next // M1/T2 `T reset_in = 1; M1=1; `T reset_in = 0; M1=1; T2=1; `T M1=1; T2=0; `T `T `T assert(nreset==1 && clrpc==1); `T M1=1; T2=1; `T M1=1; T2=0; `T assert(nreset==1 && clrpc==0); `T $display("End of test"); end //-------------------------------------------------------------- // Instantiate DUT //-------------------------------------------------------------- resets reset_block ( .* ); endmodule ================================================ FILE: cpu/control/test_sequencer.sv ================================================ //============================================================== // Test sequencer //============================================================== `timescale 100 ns/ 100 ns module test_sequencer; // ----------------- CLOCKS AND RESET ----------------- // Define one full T-clock cycle delay `define T #2 bit clk = 1; initial repeat (100) #1 clk = ~clk; logic nreset = 0; // ----------------- CONTROL ---------------- logic nextM_sig; logic setM1_sig; logic hold_clk_iorq_sig=0; logic hold_clk_wait_sig=0; logic hold_clk_busrq_sig=0; wire T6_sig; wire M5_sig; assign nextM_sig = T6_sig; // Restart when reaching T6 assign setM1_sig = M5_sig & T6_sig; // Restart when reaching M5/T6 // ----------------- TEST ------------------- initial begin // Init / reset `T nreset = 1; repeat (100) @(posedge clk); nreset <= 1; // This test does not use assert() -- we just check visually `T $display("End of test"); end //-------------------------------------------------------------- // Instantiate sequencer //-------------------------------------------------------------- sequencer sequencer_inst ( .clk(clk) , // input clk .nextM(nextM_sig) , // input nextM_sig .setM1(setM1_sig) , // input setM1_sig .nreset(nreset) , // input nreset .hold_clk_iorq(hold_clk_iorq_sig) , // input hold_clk_iorq_sig .hold_clk_wait(hold_clk_wait_sig) , // input hold_clk_wait_sig .hold_clk_busrq(hold_clk_busrq_sig),// input hold_clk_busrq_sig .M1(M1_sig) , // output M1_sig .M2(M2_sig) , // output M2_sig .M3(M3_sig) , // output M3_sig .M4(M4_sig) , // output M4_sig .M5(M5_sig) , // output M5_sig .T1(T1_sig) , // output T1_sig .T2(T2_sig) , // output T2_sig .T3(T3_sig) , // output T3_sig .T4(T4_sig) , // output T4_sig .T5(T5_sig) , // output T5_sig .T6(T6_sig) , // output T6_sig .timings_en(timings_en_sig) // output timings_en_sig ); endmodule ================================================ FILE: cpu/control/timing_macros.i ================================================ //========================================================================================= // This file contains substitute strings for macro expansions. Macros are defined in an // Excel timing spreadsheet 'Timings.xlsm' and exported to a .csv file which is then read // and processed by genmatrix.py script to generate exec_matrix.vh include file. // // Macro format: // // * Each key is prefixed by ':' and corresponds to a spreadsheet *column* name. // * A key may contain several different macros, one per line. // * A macro may span multiple lines; use the '\' character to continue on the next line. // * Multi-line macros end when a line does not start with a space character. // //-style comments are wrapped within /* ... */ if they don't start a line. //========================================================================================= //----------------------------------------------------------------------------------------- // CPU machine state //----------------------------------------------------------------------------------------- :Function //Fetch is M1 fMFetch fMRead fMRead=1; fMWrite fMWrite=1; fIORead fIORead=1; fIOWrite fIOWrite=1; //----------------------------------------------------------------------------------------- // Basic timing control //----------------------------------------------------------------------------------------- :valid Y validPLA=1; :nextM Y nextM=1; mr nextM=1; ctl_mRead=1; mw nextM=1; ctl_mWrite=1; ior nextM=1; ctl_iorw=1; iow nextM=1; ctl_iorw=1; CC nextM=~flags_cond_true; INT nextM=1; ctl_mRead=in_intr & im2; // RST38 interrupt extension :setM1 Y setM1=1; SS setM1=~flags_cond_true; CC setM1=~flags_cond_true; ZF setM1=flags_zf; // Used in DJNZ BR setM1=nonRep | ~repeat_en; BRZ setM1=nonRep | ~repeat_en | flags_zf; BZ setM1=nonRep | flags_zf; INT setM1=~(in_intr & im2); // RST38 interrupt extension //----------------------------------------------------------------------------------------- // Register file, address (downstream) endpoint //----------------------------------------------------------------------------------------- :A:reg rd // General purpose registers A ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; ctl_sw_4d=1; // Read 8-bit general purpose A register, enable SW4 downstream r16 ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; // Read 16-bit general purpose register, enable SW4 downstream BC ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; // Read 16-bit BC, enable SW4 downstream DE ctl_reg_gp_sel=`GP_REG_DE; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; // Read 16-bit DE, enable SW4 downstream HL ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; // Read 16-bit HL, enable SW4 downstream SP ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;// Read 16-bit SP, enable SW4 downstream // System registers WZ ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; // Select 16-bit WZ IR ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b11; // Select 16-bit IR I* ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4d=1; // Select 8-bit I register PC ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; // Select 16-bit PC // Conditional assertions of WZ, HL instead of PC WZ? ctl_reg_not_pc|=flags_cond_true; ctl_reg_sel_wz|=flags_cond_true; ctl_reg_sys_hilo|={flags_cond_true,flags_cond_true}; ctl_sw_4d|=flags_cond_true; // Alternate format: // if (flags_cond_true) begin // If cc is true, use WZ instead of PC (for jumps) // ctl_reg_not_pc=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; // end :A:reg wr // General purpose registers r16 ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; // Write 16-bit general purpose register, enable SW4 upstream BC ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; // Write 16-bit BC, enable SW4 upstream DE ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_DE; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; // Write 16-bit BC, enable SW4 upstream HL ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; // Write 16-bit HL, enable SW4 upstream SP ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; // Write 16-bit SP, enable SW4 upstream // System registers WZ ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; // Write 16-bit WZ, enable SW4 upstream IR ctl_reg_sys_we=1; ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b11; // Write 16-bit IR // PC will not be incremented if we are in HALT, INTR or NMI state PC ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc_hold=(in_halt | in_intr | in_nmi); // Write 16-bit PC and control incrementer > ctl_sw_4u=1; //----------------------------------------------------------------------------------------- // Controls the address latch incrementer, the address latch and the address pin mux //----------------------------------------------------------------------------------------- :inc/dec + ctl_inc_cy=~pc_inc_hold; // Increment - ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=1; // Decrement op3 ctl_inc_cy=~pc_inc_hold; ctl_inc_dec=op3; // Decrement if op3 is set; increment otherwise :A:latch W ctl_al_we=1; // Write a value from the register bus to the address latch R ctl_bus_inc_oe=1; // Output enable incrementer to the register bus P ctl_apin_mux=1; // Apin sourced from incrementer RL ctl_bus_inc_oe=1; ctl_apin_mux2=1; // Apin sourced from AL //----------------------------------------------------------------------------------------- // Register file, data (upstream) endpoint //----------------------------------------------------------------------------------------- :D:reg rd //----- General purpose registers ----- A ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; AF ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; B ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10; H ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b10; L ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b01; r8 ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0};// Read 8-bit GP register selected by op[2:0] r8' \ // r8 addressing does not allow reading F register (indices of A and F are also swapped) (ex. in OUT (c),r) if (op4 & op5 & ~op3) begin ctl_bus_zero_oe=1; end // Trying to read flags? Put 0 on the bus instead. if (~(op4 & op5 & ~op3)) begin ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; end // Read 8-bit GP register rh ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; // Read 8-bit GP register high byte rl ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; // Read 8-bit GP register low byte //----- System registers ----- WZ ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; Z ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1; // Selecting strictly Z I/R ctl_reg_sel_ir=1; ctl_reg_sys_hilo={~op3,op3}; ctl_sw_4u=1; // Read either I or R based on op3 (0 or 1) PCh ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4u=1; PCl ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1; :D:reg wr ? // Which register to be written is decided elsewhere //----- General purpose registers ----- A ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; F ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01; B ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10; r8 ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={~rsel3,rsel3}; // Write 8-bit GP register r8' ctl_reg_gp_we=1; ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={~rsel0,rsel0}; // Write 8-bit GP register selected by op[2:0] rh ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; // Write 8-bit GP register high byte rl ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; // Write 8-bit GP register low byte //----- System registers ----- I/R ctl_reg_sys_we=1; ctl_reg_sel_ir=1; ctl_reg_sys_hilo={~op3,op3}; ctl_sw_4d=1; // Write either I or R based on op3 (0 or 1) WZ ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; W ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; // Selecting only W W? ctl_reg_sys_we_hi=flags_cond_true; ctl_reg_sel_wz=flags_cond_true; ctl_reg_sys_hilo={1'b1,ctl_reg_sys_hilo[0]}; // Conditionally selecting only W Z ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo={ctl_reg_sys_hilo[1],1'b1}; // Selecting only Z //----------------------------------------------------------------------------------------- // Controls the register file gate connecting it with the ALU and data bus //----------------------------------------------------------------------------------------- :Reg gate < ctl_reg_in_hi=1; ctl_reg_in_lo=1; // From the ALU side into the register file ctl_reg_out_hi=1; ctl_reg_out_lo=1; // From the register file into the FLAGT and ALU // Enables a register gate (high/low) corresponding to the selected 8-bit register >r8 ctl_reg_out_hi=~rsel0; ctl_reg_out_lo=rsel0; ctl_sw_2u=~rsel0; ctl_sw_2d=rsel0; // Enable register gate based on the rsel0 >r8' ctl_reg_out_hi=~rsel3; ctl_reg_out_lo=rsel3; ctl_sw_2u=~rsel3; ctl_sw_2d=rsel3; // Enable register gate based on the rsel3 >l ctl_reg_out_lo=1; // From the register file onto the db1 (sw2 + FLAGT + sw1) >h ctl_reg_out_hi=1; // From the register file onto the db2 (sw2 + ALU) //----------------------------------------------------------------------------------------- // Switches on the data bus for each direction (upstream, downstream) //----------------------------------------------------------------------------------------- :SW2 d ctl_sw_2d=1; u ctl_sw_2u=1; - // Controlled by register gate :SW1 < ctl_sw_1d=1; > ctl_sw_1u=1; //----------------------------------------------------------------------------------------- // Data bus latches and pads control //----------------------------------------------------------------------------------------- :DB pads R ctl_bus_db_oe=1; // Read DB pads to internal data bus W ctl_bus_db_we=1; // Write DB pads with internal data bus value 00 ctl_bus_zero_oe=1; // Force 0x00 on the data bus FF ctl_bus_ff_oe=1; // Force 0xFF on the data bus //----------------------------------------------------------------------------------------- // ALU //----------------------------------------------------------------------------------------- :ALU // Controls the master ALU output enable and the ALU input, only one can be active at a time // >bs if set, will override >s0 which is used by bit instructions to override default M1/T3 load < ctl_alu_oe=1; // Enable ALU onto the data bus >s0 ctl_alu_shift_oe=~ctl_alu_bs_oe; // Shifter unit without shift-enable >s1 ctl_alu_shift_oe=1; ctl_shift_en=1; // Shifter unit AND shift enable! >bs ctl_alu_bs_oe=1; // Bit-selector unit :ALU bus // Controls the writer to the internal ALU bus op1 ctl_alu_op1_oe=1; // OP1 latch op2 ctl_alu_op2_oe=1; // OP2 latch res ctl_alu_res_oe=1; // Result latch :op2 latch // Controls a MUX to select the input to the OP2 latch bus ctl_alu_op2_sel_bus=1; // Internal bus lq ctl_alu_op2_sel_lq=1; // Cross-bus wire (see schematic) 0 ctl_alu_op2_sel_zero=1; // Zero :op1 latch // Controls a MUX to select the input to the OP1 latch bus ctl_alu_op1_sel_bus=1; // Internal bus low ctl_alu_op1_sel_low=1; // Write low nibble with a high nibble 0 ctl_alu_op1_sel_zero=1; // Zero :operation // Defines the ALU core compute operation // The listing is also showing their alternate formats (using if/then) //----------------------------------------------------------------------------------------- CP ctl_alu_sel_op2_neg=1; ctl_flags_cf_set|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low; // ctl_alu_sel_op2_neg=1; // if (ctl_alu_op_low) begin // ctl_flags_cf_set=1; // end else begin // ctl_alu_core_hf=1; // end //----------------------------------------------------------------------------------------- SUB ctl_alu_sel_op2_neg=1; ctl_flags_cf_set|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low; // ctl_alu_sel_op2_neg=1; // if (ctl_alu_op_low) begin // ctl_flags_cf_set=1; // end else begin // ctl_alu_core_hf=1; // end //----------------------------------------------------------------------------------------- SBC ctl_alu_sel_op2_neg=1; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low; // ctl_alu_sel_op2_neg=1; // if (ctl_alu_op_low) begin // ctl_flags_cf_cpl=1; // end else begin // ctl_alu_core_hf=1; // end //----------------------------------------------------------------------------------------- SBCh ctl_alu_sel_op2_neg=1; ctl_alu_core_hf|=~ctl_alu_op_low; // ctl_alu_sel_op2_neg=1; // if (~ctl_alu_op_low) begin // ctl_alu_core_hf=1; // end //----------------------------------------------------------------------------------------- ADC ctl_alu_core_hf|=~ctl_alu_op_low; // if (~ctl_alu_op_low) begin // ctl_alu_core_hf=1; // end //----------------------------------------------------------------------------------------- ADD ctl_flags_cf_set|=ctl_alu_op_low; ctl_flags_cf_cpl|=ctl_alu_op_low; ctl_alu_core_hf|=~ctl_alu_op_low; // if (ctl_alu_op_low) begin // ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; // end else begin // ctl_alu_core_hf=1; // end //----------------------------------------------------------------------------------------- AND ctl_alu_core_S=1; ctl_flags_cf_set=1; OR ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; XOR ctl_alu_core_R=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; NAND ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; NOR ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; ctl_alu_sel_op2_neg=1; //----------------------------------------------------------------------------------------- PLA ctl_state_alu=1; // Assert the ALU PLA modifier to determine operation :nibble // ALU compute phase: working on low nibble or high nibble L ctl_alu_op_low=1; // Activate ALU operation on low nibble H ctl_alu_sel_op2_high=1; // Activate ALU operation on high nibble //----------------------------------------------------------------------------------------- // FLAGT //----------------------------------------------------------------------------------------- :FLAGT < ctl_flags_oe=1; // Enable FLAGT onto the data bus > ctl_flags_bus=1; // Load FLAGT from the data bus alu ctl_flags_alu=1; // Load FLAGT from the ALU // Write enables for various flag bits and segments :SZ * ctl_flags_sz_we=1; :XY * ctl_flags_xy_we=1; ? :HF * ctl_flags_hf_we=1; W2 ctl_flags_hf2_we=1; // Write HF2 flag (DAA only) :PF * ctl_flags_pf_we=1; P ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; V ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V; iff2 ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_IFF2; REP ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_REP; ? :NF * ctl_flags_nf_we=1; // Previous NF, to be used when loading FLAGT 0 ctl_flags_nf_we=1; ctl_flags_nf_clr=1; 1 ctl_flags_nf_we=1; ctl_flags_nf_set=1; S ctl_flags_nf_we=1; // Sign bit, to be used with FLAGT source set to "alu" ? :CF * ctl_flags_cf_we=1; 0 ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; // Clear CF going into the ALU core 1 ctl_flags_cf_set=1; // Set CF going into the ALU core ^ ctl_flags_cf_we=1; ctl_flags_cf_cpl=1; // CCF :CF2 R ctl_flags_use_cf2=1; W ctl_flags_cf2_we=1; W.sh ctl_flags_cf2_we=1; ctl_flags_cf2_sel_shift=1; W.daa ctl_flags_cf2_we=1; ctl_flags_cf2_sel_daa=1; //------------------------------------------------------------------------------------------ // Macros for some special cases; also simplifies control logic for a number of instructions //------------------------------------------------------------------------------------------ :Special USE_SP ctl_reg_use_sp=1; // For 16-bit loads: use SP instead of AF // A few more specific states and instructions: Ex_DE_HL ctl_reg_ex_de_hl=1; // EX DE,HL Ex_AF_AF' ctl_reg_ex_af=1; // EX AF,AF' EXX ctl_reg_exx=1; // EXX HALT ctl_state_halt_set=1; // Enter HALT state DI_EI ctl_iffx_bit=op3; ctl_iffx_we=1; // DI/EI IM ctl_im_we=1; // IM n ('n' is read by opcode[4:3]) WZ=IX+d ixy_d=1; // Compute WZ=IX+d IX_IY ctl_state_ixiy_we=1; ctl_state_iy_set=op5; setIXIY=1; // IX/IY prefix CLR_IX_IY ctl_state_ixiy_we=1; ctl_state_ixiy_clr=~setIXIY; // Clear IX/IY flag if not explicitly set CB ctl_state_tbl_we=1; ctl_state_tbl_cb_set=1; // CB-table prefix ED ctl_state_tbl_we=1; ctl_state_tbl_ed_set=1; // ED-table prefix CLR_CB_ED ctl_state_tbl_we=1; // Clear CB/ED prefix if not explicitly set // If the NF is set, complement HF and CF on the way out to the bus // This is used to correctly set those flags after subtraction operations ?NF_HF_CF ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; ?NF_HF ctl_flags_hf_cpl=flags_nf; ?~CF_HF ctl_flags_hf_cpl=~flags_cf; // Used for CCF ?SF_NEG ctl_alu_sel_op2_neg=flags_sf; NEG_OP2 ctl_alu_sel_op2_neg=1; ?NF_SUB ctl_alu_sel_op2_neg=flags_nf; ctl_flags_cf_cpl=~flags_nf; // M1 opcode read cycle and the refresh register increment cycle // Write opcode into the instruction register through internal db0 bus: OpcodeToIR ctl_ir_we=1; // At the common instruction load M1/T3, override opcode byte when servicing interrupts: // 1. We are in HALT mode: push NOP (0x00) instead // 2. We are in INTR mode (IM1 or IM2): push RST38 (0xFF) instead // 3. We are in NMI mode: push RST38 (0xFF) instead OverrideIR ctl_bus_zero_oe=in_halt; ctl_bus_ff_oe=(in_intr & (im1 | im2)) | in_nmi; // RST instruction uses opcode[5:3] to specify a vector and this macro passes those 3 bits through MASK_543 ctl_sw_mask543_en=~((in_intr & im2) | in_nmi); // Based on the in_nmi state: // 1. Disable SW1 so the opcode will not get onto db1 bus // 2. Generate 0x66 on the db1 bus which will be used as the target vector address // 3. Clear IFF1 (done by the nmi logic on posedge of in_nmi) RST_NMI ctl_sw_1d=~in_nmi; ctl_66_oe=in_nmi; // Based on the in_intr state: // 1. IM1 mode, force 0xFF on the db0 bus // 2. Clear IFF1 and IFF2 (done by the intr logic on posedge of in_intr) RST_INT ctl_bus_ff_oe=in_intr & im1; RETN ctl_iff1_iff2=1; // RETN copies IFF2 into IFF1 NO_INTS ctl_no_ints=1; // Disable interrupt generation for this opcode (DI/EI/CB/ED/DD/FD) EvalCond ctl_eval_cond=1; // Evaluate flags condition based on the opcode[5:3] CondShort ctl_cond_short=1; // M1/T3 only: force a short flags condition (SS) Limit6 ctl_inc_limit6=1; // Limit the incrementer to 6 bits DAA ctl_daa_oe=1; // Write DAA correction factor to the bus ZERO_16BIT ctl_alu_zero_16bit=1; // 16-bit arithmetic operation uses ZF calculated over 2 bytes NonRep nonRep=1; // Non-repeating block instruction WriteBC=1 ctl_repeat_we=1; // Update repeating flag latch with BC=1 status NOT_PC! ctl_reg_not_pc=1; // For M1/T1 load from a register other than PC ================================================ FILE: cpu/copyleft.txt ================================================ //---------------------------------------------------------------------------- // A-Z80 CPU Copyright (C) 2014,2017 Goran Devic, www.baltazarstudios.com // // This program is free software; you can redistribute it and/or modify it // under the terms of the GNU General Public License as published by the Free // Software Foundation; either version 2 of the License, or (at your option) // any later version. // // This program is distributed in the hope that it will be useful, but WITHOUT // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for // more details. //---------------------------------------------------------------------------- ================================================ FILE: cpu/export.py ================================================ #!/usr/bin/env python3 # # Run this script to export necessary CPU files away and into your project. # #------------------------------------------------------------------------------- # Copyright (C) 2014,2018 Goran Devic, www.baltazarstudios.com # # This program is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by the Free # Software Foundation; either version 2 of the License, or (at your option) # any later version. # # This program is distributed in the hope that it will be useful, but WITHOUT # ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or # FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for # more details. #------------------------------------------------------------------------------- import sys import os from shutil import copyfile if len(sys.argv) != 2: print ("\nUsage: export.py \n") print ("Exports all necessary A-Z80 Verilog files to a project folder of your choice.") exit(-1) dest = sys.argv[1] total = 0 if not os.path.exists(dest): print ("ERROR: Destination folder does not exist!") exit(-1) if not os.path.isdir(dest): print ("ERROR: Destination is not a directory!") exit(-1) with open('top-level-files.txt') as f: files = f.read().splitlines() with open('copyleft.txt') as f: copyleft = f.read() # Read and copy each file from the list of input files for infile in files: if infile.startswith('+'): infile = infile[2:] if infile.startswith('Files='): files = int(infile[6:]) if total != files: print ("ERROR: Incorrect number of files copied!") exit(-1) else: print ("\nDone copying {0} files.\n".format(files)) if not os.path.isfile(infile): continue name = os.path.basename(infile) print ('Copying', infile) with open(dest + '/' + name, 'wt') as f: f.write(copyleft) with open(infile) as g: f.write(g.read()) total += 1 print ("All necessary A-Z80 CPU files are copied to", dest) print ("Add all Verilog files (*.v) to your project and ensure that Verilog include") print ("files (*.vh) are on the include path.\n") print ("Use z80_top_direct_n.v as your top-level interface file.\n") print ("Note for the users of Lattice FPGA toolset: instead of data_pins.v, manually") print ("copy and use data_pins_lattice.v file instead.") ================================================ FILE: cpu/readme.txt ================================================ A-Z80 Logic Design ================== Each functional block contains a Quartus project file: .//test_.qpf Quartus projects are only used as containers for files within individual modules; complete and working top-level solutions that use A-Z80 are in the "host" folder. Majority of sub-modules are designed in the Quartus schematic editor and then exported to Verilog for simulation and top-level integration. Simulation ========== Before you can load and simulate any module through Modelsim, you need to set up the environment by running 'modelsim_setup.py'. The script creates relative file path mapping to source files in all module project folders. Each functional block, including the top level, contains a Modelsim simulation profile: .//simulation/modelsim/test_.mpf After opening a Modelsim session, create a library and compile sources: ModelSim> vlib work Compile->Compile All Run a simulation through one of the defined configurations. If you get a message "Unable to compile", you likely forgot to run 'modelsim_setup.py'. Exit ModelSim, revert changes to ".mpf" file, delete "work" folder and run 'modelsim_setup.py'. Each project contains a set of predefined waveform scripts which you can load before running a simulation: .//simulation/modelsim/wave_.do ================================================ FILE: cpu/registers/reg_control.bdf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. 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10))) (text "General Purpose registers control" (rect 592 32 820 48)(font "Arial" (font_size 10))) (text "Set 0" (rect 752 264 781 278)(font "Arial" (font_size 8))) (text "Set 1" (rect 752 248 781 262)(font "Arial" (font_size 8))) (text "Block PC (use for override to WZ, HL for jumps)" (rect 232 1464 503 1478)(font "Arial" (font_size 8))) (text "Fix bus contention when reading I reg and bypassing int # (used for interrupt handling)" (rect 680 1288 1172 1302)(font "Arial" (font_size 8))) (title_block (rect 32 1552 353 1613) (name "title-custom-medium") (section (rect 0 0 320 20)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 106 21)(font "Arial" (font_size 12)(bold)))(border)) (section (rect 130 0 320 20)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "reg_control" (rect 43 2 146 21)(font "Arial" (font_size 12)(bold)))(border)) (section (rect 0 21 320 40)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 151 19)(font "Arial" (font_size 11)))(border)) (section (rect 0 41 240 60)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "May 17, 2014, 2016" (rect 56 3 191 19)(font "Arial" (font_size 10)))(border)) (section (rect 241 41 320 60)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.5" (rect 43 3 64 19)(font "Arial" (font_size 10)))(border)) (drawing ) ) ================================================ FILE: cpu/registers/reg_control.bsf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "symbol" (version "1.2")) (symbol (rect 16 16 280 432) (text "reg_control" (rect 5 0 69 14)(font "Arial" (font_size 8))) (text "inst" (rect 8 400 25 412)(font "Arial" )) (port (pt 0 32) (input) (text "ctl_reg_gp_we" (rect 0 0 86 14)(font "Arial" (font_size 8))) (text "ctl_reg_gp_we" (rect 21 27 107 41)(font "Arial" (font_size 8))) (line (pt 0 32)(pt 16 32)) ) (port (pt 0 48) (input) (text "ctl_reg_gp_hilo[1..0]" (rect 0 0 114 14)(font "Arial" (font_size 8))) (text "ctl_reg_gp_hilo[1..0]" (rect 21 43 135 57)(font "Arial" (font_size 8))) (line (pt 0 48)(pt 16 48)(line_width 3)) ) (port (pt 0 64) (input) (text "ctl_reg_gp_sel[1..0]" (rect 0 0 112 14)(font "Arial" (font_size 8))) (text "ctl_reg_gp_sel[1..0]" (rect 21 59 133 73)(font "Arial" (font_size 8))) (line (pt 0 64)(pt 16 64)(line_width 3)) ) (port (pt 0 80) (input) (text "ctl_reg_ex_de_hl" (rect 0 0 97 14)(font "Arial" (font_size 8))) (text "ctl_reg_ex_de_hl" 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240) (output) (text "reg_sel_sp" (rect 0 0 63 14)(font "Arial" (font_size 8))) (text "reg_sel_sp" (rect 180 235 243 249)(font "Arial" (font_size 8))) (line (pt 264 240)(pt 248 240)) ) (port (pt 264 256) (output) (text "reg_sys_we_hi" (rect 0 0 89 14)(font "Arial" (font_size 8))) (text "reg_sys_we_hi" (rect 154 251 243 265)(font "Arial" (font_size 8))) (line (pt 264 256)(pt 248 256)) ) (port (pt 264 272) (output) (text "reg_sys_we_lo" (rect 0 0 89 14)(font "Arial" (font_size 8))) (text "reg_sys_we_lo" (rect 154 267 243 281)(font "Arial" (font_size 8))) (line (pt 264 272)(pt 248 272)) ) (port (pt 264 288) (output) (text "reg_sel_sys_lo" (rect 0 0 87 14)(font "Arial" (font_size 8))) (text "reg_sel_sys_lo" (rect 156 283 243 297)(font "Arial" (font_size 8))) (line (pt 264 288)(pt 248 288)) ) (port (pt 264 304) (output) (text "reg_sel_sys_hi" (rect 0 0 87 14)(font "Arial" (font_size 8))) (text "reg_sel_sys_hi" (rect 156 299 243 313)(font "Arial" (font_size 8))) (line (pt 264 304)(pt 248 304)) ) (port (pt 264 320) (output) (text "reg_sw_4d_lo" (rect 0 0 82 14)(font "Arial" (font_size 8))) (text "reg_sw_4d_lo" (rect 161 315 243 329)(font "Arial" (font_size 8))) (line (pt 264 320)(pt 248 320)) ) (port (pt 264 336) (output) (text "reg_sw_4d_hi" (rect 0 0 82 14)(font "Arial" (font_size 8))) (text "reg_sw_4d_hi" (rect 161 331 243 345)(font "Arial" (font_size 8))) (line (pt 264 336)(pt 248 336)) ) (port (pt 264 352) (output) (text "reg_sel_ir" (rect 0 0 56 14)(font "Arial" (font_size 8))) (text "reg_sel_ir" (rect 187 347 243 361)(font "Arial" (font_size 8))) (line (pt 264 352)(pt 248 352)) ) (port (pt 264 368) (output) (text "reg_sel_pc" (rect 0 0 63 14)(font "Arial" (font_size 8))) (text "reg_sel_pc" (rect 180 363 243 377)(font "Arial" (font_size 8))) (line (pt 264 368)(pt 248 368)) ) (port (pt 264 384) (output) (text "reg_sel_wz" (rect 0 0 68 14)(font "Arial" (font_size 8))) (text "reg_sel_wz" (rect 175 379 243 393)(font "Arial" (font_size 8))) (line (pt 264 384)(pt 248 384)) ) (drawing (rectangle (rect 16 16 248 400)) ) ) ================================================ FILE: cpu/registers/reg_control.v ================================================ // Copyright (C) 1991-2013 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // PROGRAM "Quartus II 64-Bit" // VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" // CREATED "Sat Dec 10 09:05:10 2016" module reg_control( ctl_reg_exx, ctl_reg_ex_af, ctl_reg_ex_de_hl, ctl_reg_use_sp, nreset, ctl_reg_sel_pc, ctl_reg_sel_ir, ctl_reg_sel_wz, ctl_reg_gp_we, ctl_reg_not_pc, use_ixiy, use_ix, ctl_reg_sys_we_lo, ctl_reg_sys_we_hi, ctl_reg_sys_we, clk, ctl_sw_4d, nhold_clk_wait, ctl_reg_gp_hilo, ctl_reg_gp_sel, ctl_reg_sys_hilo, reg_sel_bc, reg_sel_bc2, reg_sel_ix, reg_sel_iy, reg_sel_de, reg_sel_hl, reg_sel_de2, reg_sel_hl2, reg_sel_af, reg_sel_af2, reg_sel_wz, reg_sel_pc, reg_sel_ir, reg_sel_sp, reg_sel_gp_hi, reg_sel_gp_lo, reg_sel_sys_lo, reg_sel_sys_hi, reg_gp_we, reg_sys_we_lo, reg_sys_we_hi, reg_sw_4d_lo, reg_sw_4d_hi ); input wire ctl_reg_exx; input wire ctl_reg_ex_af; input wire ctl_reg_ex_de_hl; input wire ctl_reg_use_sp; input wire nreset; input wire ctl_reg_sel_pc; input wire ctl_reg_sel_ir; input wire ctl_reg_sel_wz; input wire ctl_reg_gp_we; input wire ctl_reg_not_pc; input wire use_ixiy; input wire use_ix; input wire ctl_reg_sys_we_lo; input wire ctl_reg_sys_we_hi; input wire ctl_reg_sys_we; input wire clk; input wire ctl_sw_4d; input wire nhold_clk_wait; input wire [1:0] ctl_reg_gp_hilo; input wire [1:0] ctl_reg_gp_sel; input wire [1:0] ctl_reg_sys_hilo; output wire reg_sel_bc; output wire reg_sel_bc2; output wire reg_sel_ix; output wire reg_sel_iy; output wire reg_sel_de; output wire reg_sel_hl; output wire reg_sel_de2; output wire reg_sel_hl2; output wire reg_sel_af; output wire reg_sel_af2; output wire reg_sel_wz; output wire reg_sel_pc; output wire reg_sel_ir; output wire reg_sel_sp; output wire reg_sel_gp_hi; output wire reg_sel_gp_lo; output wire reg_sel_sys_lo; output wire reg_sel_sys_hi; output wire reg_gp_we; output wire reg_sys_we_lo; output wire reg_sys_we_hi; output wire reg_sw_4d_lo; output wire reg_sw_4d_hi; reg bank_af; reg bank_exx; reg bank_hl_de1; reg bank_hl_de2; wire reg_sys_we_lo_ALTERA_SYNTHESIZED; wire SYNTHESIZED_WIRE_52; wire SYNTHESIZED_WIRE_53; wire SYNTHESIZED_WIRE_2; wire SYNTHESIZED_WIRE_54; wire SYNTHESIZED_WIRE_55; wire SYNTHESIZED_WIRE_5; wire SYNTHESIZED_WIRE_56; wire SYNTHESIZED_WIRE_10; wire SYNTHESIZED_WIRE_57; wire SYNTHESIZED_WIRE_58; wire SYNTHESIZED_WIRE_59; wire SYNTHESIZED_WIRE_60; wire SYNTHESIZED_WIRE_21; wire SYNTHESIZED_WIRE_23; wire SYNTHESIZED_WIRE_24; wire SYNTHESIZED_WIRE_25; wire SYNTHESIZED_WIRE_30; wire SYNTHESIZED_WIRE_31; wire SYNTHESIZED_WIRE_32; wire SYNTHESIZED_WIRE_61; wire SYNTHESIZED_WIRE_34; wire SYNTHESIZED_WIRE_36; wire SYNTHESIZED_WIRE_37; wire SYNTHESIZED_WIRE_38; wire SYNTHESIZED_WIRE_39; wire SYNTHESIZED_WIRE_40; wire SYNTHESIZED_WIRE_41; wire SYNTHESIZED_WIRE_42; wire SYNTHESIZED_WIRE_43; wire SYNTHESIZED_WIRE_44; wire SYNTHESIZED_WIRE_45; wire SYNTHESIZED_WIRE_46; wire SYNTHESIZED_WIRE_47; wire SYNTHESIZED_WIRE_48; wire SYNTHESIZED_WIRE_49; wire SYNTHESIZED_WIRE_50; assign reg_sel_wz = ctl_reg_sel_wz; assign reg_sel_ir = ctl_reg_sel_ir; assign reg_sel_gp_hi = ctl_reg_gp_hilo[1]; assign reg_sel_gp_lo = ctl_reg_gp_hilo[0]; assign reg_sel_sys_lo = ctl_reg_sys_hilo[0]; assign reg_sel_sys_hi = ctl_reg_sys_hilo[1]; assign reg_gp_we = ctl_reg_gp_we; assign reg_sw_4d_lo = ctl_sw_4d; assign reg_sel_bc = SYNTHESIZED_WIRE_52 & SYNTHESIZED_WIRE_53; assign reg_sel_af = SYNTHESIZED_WIRE_2 & SYNTHESIZED_WIRE_54; assign SYNTHESIZED_WIRE_54 = SYNTHESIZED_WIRE_55 & SYNTHESIZED_WIRE_5; assign reg_sel_sp = SYNTHESIZED_WIRE_55 & ctl_reg_use_sp; assign SYNTHESIZED_WIRE_5 = ~ctl_reg_use_sp; assign reg_sel_ix = SYNTHESIZED_WIRE_56 & use_ix; assign SYNTHESIZED_WIRE_50 = ctl_reg_ex_de_hl & SYNTHESIZED_WIRE_53; assign reg_sel_iy = SYNTHESIZED_WIRE_56 & SYNTHESIZED_WIRE_10; assign reg_sel_af2 = bank_af & SYNTHESIZED_WIRE_54; assign SYNTHESIZED_WIRE_2 = ~bank_af; assign SYNTHESIZED_WIRE_47 = SYNTHESIZED_WIRE_57 & SYNTHESIZED_WIRE_58; assign SYNTHESIZED_WIRE_46 = bank_hl_de2 & SYNTHESIZED_WIRE_59; assign SYNTHESIZED_WIRE_39 = SYNTHESIZED_WIRE_60 & SYNTHESIZED_WIRE_58; assign SYNTHESIZED_WIRE_49 = bank_hl_de2 & SYNTHESIZED_WIRE_58; assign SYNTHESIZED_WIRE_48 = SYNTHESIZED_WIRE_57 & SYNTHESIZED_WIRE_59; assign reg_sel_de = SYNTHESIZED_WIRE_53 & SYNTHESIZED_WIRE_21; assign reg_sel_hl = SYNTHESIZED_WIRE_53 & SYNTHESIZED_WIRE_23; assign reg_sel_de2 = bank_exx & SYNTHESIZED_WIRE_24; assign reg_sel_hl2 = bank_exx & SYNTHESIZED_WIRE_25; assign SYNTHESIZED_WIRE_38 = bank_hl_de1 & SYNTHESIZED_WIRE_59; assign SYNTHESIZED_WIRE_53 = ~bank_exx; assign SYNTHESIZED_WIRE_45 = bank_hl_de1 & SYNTHESIZED_WIRE_58; assign SYNTHESIZED_WIRE_44 = SYNTHESIZED_WIRE_60 & SYNTHESIZED_WIRE_59; assign SYNTHESIZED_WIRE_52 = SYNTHESIZED_WIRE_30 & SYNTHESIZED_WIRE_31; assign SYNTHESIZED_WIRE_60 = ~bank_hl_de1; assign reg_sys_we_hi = ctl_reg_sys_we | ctl_reg_sys_we_hi; assign reg_sel_pc = ctl_reg_sel_pc & SYNTHESIZED_WIRE_32; assign SYNTHESIZED_WIRE_58 = SYNTHESIZED_WIRE_61 & SYNTHESIZED_WIRE_34; assign SYNTHESIZED_WIRE_32 = ~ctl_reg_not_pc; assign SYNTHESIZED_WIRE_36 = ~ctl_reg_gp_sel[1]; assign reg_sys_we_lo_ALTERA_SYNTHESIZED = ctl_reg_sys_we_lo | ctl_reg_sys_we; assign SYNTHESIZED_WIRE_56 = SYNTHESIZED_WIRE_61 & use_ixiy; assign SYNTHESIZED_WIRE_42 = ~ctl_reg_gp_sel[0]; assign SYNTHESIZED_WIRE_43 = ctl_reg_ex_de_hl & bank_exx; assign SYNTHESIZED_WIRE_34 = ~use_ixiy; assign SYNTHESIZED_WIRE_59 = ctl_reg_gp_sel[0] & SYNTHESIZED_WIRE_36; always@(posedge clk or negedge nreset) begin if (!nreset) begin bank_af <= 0; end else if (nhold_clk_wait) begin bank_af <= bank_af ^ ctl_reg_ex_af; end end assign SYNTHESIZED_WIRE_10 = ~use_ix; assign SYNTHESIZED_WIRE_57 = ~bank_hl_de2; assign SYNTHESIZED_WIRE_41 = ~reg_sys_we_lo_ALTERA_SYNTHESIZED; assign SYNTHESIZED_WIRE_40 = ~SYNTHESIZED_WIRE_37; assign SYNTHESIZED_WIRE_23 = SYNTHESIZED_WIRE_38 | SYNTHESIZED_WIRE_39; assign reg_sw_4d_hi = ctl_sw_4d & SYNTHESIZED_WIRE_40; assign SYNTHESIZED_WIRE_37 = ctl_reg_sys_hilo[1] & SYNTHESIZED_WIRE_41 & ctl_reg_sel_ir; assign SYNTHESIZED_WIRE_61 = SYNTHESIZED_WIRE_42 & ctl_reg_gp_sel[1]; always@(posedge clk or negedge nreset) begin if (!nreset) begin bank_hl_de2 <= 0; end else if (nhold_clk_wait) begin bank_hl_de2 <= bank_hl_de2 ^ SYNTHESIZED_WIRE_43; end end assign SYNTHESIZED_WIRE_21 = SYNTHESIZED_WIRE_44 | SYNTHESIZED_WIRE_45; assign SYNTHESIZED_WIRE_25 = SYNTHESIZED_WIRE_46 | SYNTHESIZED_WIRE_47; assign SYNTHESIZED_WIRE_24 = SYNTHESIZED_WIRE_48 | SYNTHESIZED_WIRE_49; always@(posedge clk or negedge nreset) begin if (!nreset) begin bank_hl_de1 <= 0; end else if (nhold_clk_wait) begin bank_hl_de1 <= bank_hl_de1 ^ SYNTHESIZED_WIRE_50; end end always@(posedge clk or negedge nreset) begin if (!nreset) begin bank_exx <= 0; end else if (nhold_clk_wait) begin bank_exx <= bank_exx ^ ctl_reg_exx; end end assign SYNTHESIZED_WIRE_55 = ctl_reg_gp_sel[0] & ctl_reg_gp_sel[1]; assign SYNTHESIZED_WIRE_30 = ~ctl_reg_gp_sel[0]; assign SYNTHESIZED_WIRE_31 = ~ctl_reg_gp_sel[1]; assign reg_sel_bc2 = SYNTHESIZED_WIRE_52 & bank_exx; assign reg_sys_we_lo = reg_sys_we_lo_ALTERA_SYNTHESIZED; endmodule ================================================ FILE: cpu/registers/reg_file.bdf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "graphic" (version "1.4")) (pin (input) (rect 32 256 208 272) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "reg_sel_sys_lo" (rect 9 0 83 12)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) (line (pt 121 8)(pt 176 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) ) (pin (input) (rect 2688 256 2864 272) (text "INPUT" (rect 15 6 43 16)(font "Arial" (font_size 6))) (text "reg_sel_gp_lo" (rect 100 4 167 16)(font "Arial" )) (pt 0 8) (drawing (line (pt 84 4)(pt 59 4)) (line (pt 84 12)(pt 59 12)) (line (pt 55 8)(pt 0 8)) (line (pt 84 4)(pt 84 12)) (line (pt 59 12)(pt 55 8)) (line (pt 59 4)(pt 55 8)) ) (rotate180) (text "VCC" (rect 20 -1 40 9)(font "Arial" (font_size 6))) ) (pin (input) (rect 32 848 208 864) (text "INPUT" (rect 133 0 161 10)(font "Arial" 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(connector (pt 2096 344) (pt 2096 376) ) (connector (pt 2240 344) (pt 2240 376) ) (connector (pt 2384 344) (pt 2384 376) ) (connector (pt 776 792) (pt 776 808) ) (connector (pt 784 792) (pt 784 840) ) (connector (pt 792 792) (pt 792 856) ) (connector (pt 920 792) (pt 920 808) ) (connector (pt 928 792) (pt 928 840) ) (connector (pt 936 792) (pt 936 856) ) (connector (pt 1080 792) (pt 1080 808) ) (connector (pt 1088 792) (pt 1088 840) ) (connector (pt 1096 792) (pt 1096 856) ) (connector (pt 1224 792) (pt 1224 808) ) (connector (pt 1232 792) (pt 1232 840) ) (connector (pt 1240 792) (pt 1240 856) ) (connector (pt 1368 792) (pt 1368 808) ) (connector (pt 1376 792) (pt 1376 840) ) (connector (pt 1384 792) (pt 1384 856) ) (connector (pt 1512 792) (pt 1512 808) ) (connector (pt 1520 792) (pt 1520 840) ) (connector (pt 1528 792) (pt 1528 856) ) (connector (pt 1656 792) (pt 1656 808) ) (connector (pt 1664 792) (pt 1664 840) ) (connector (pt 1672 792) (pt 1672 856) ) (connector (pt 1800 792) (pt 1800 808) ) (connector (pt 1808 792) (pt 1808 840) ) (connector (pt 1816 792) (pt 1816 856) ) (connector (pt 1944 792) (pt 1944 808) ) (connector (pt 1952 792) (pt 1952 840) ) (connector (pt 1960 792) (pt 1960 856) ) (connector (pt 2088 792) (pt 2088 808) ) (connector (pt 2096 792) (pt 2096 840) ) (connector (pt 2104 792) (pt 2104 856) ) (connector (pt 2232 792) (pt 2232 808) ) (connector (pt 2240 792) (pt 2240 840) ) (connector (pt 2248 792) (pt 2248 856) ) (connector (pt 2376 792) (pt 2376 808) ) (connector (pt 2384 792) (pt 2384 840) ) (connector (pt 2392 792) (pt 2392 856) ) (connector (pt 672 744) (pt 672 760) ) (connector (pt 880 528) (pt 840 528) (bus) ) (connector (pt 784 376) (pt 824 376) ) (connector (pt 840 344) (pt 840 400) ) (connector (pt 824 376) (pt 824 400) ) (connector (pt 928 376) (pt 968 376) ) (connector (pt 984 344) (pt 984 400) ) (connector (pt 968 376) (pt 968 400) ) (connector (pt 1088 376) (pt 1128 376) ) (connector (pt 1144 344) (pt 1144 400) ) (connector (pt 1128 376) (pt 1128 400) ) (connector (pt 1232 376) (pt 1272 376) ) (connector (pt 1288 344) (pt 1288 400) ) (connector (pt 1272 376) (pt 1272 400) ) (connector (pt 1376 376) (pt 1416 376) ) (connector (pt 1432 344) (pt 1432 400) ) (connector (pt 1416 376) (pt 1416 400) ) (connector (pt 1520 376) (pt 1560 376) ) (connector (pt 1576 344) (pt 1576 400) ) (connector (pt 1560 376) (pt 1560 400) ) (connector (pt 1664 376) (pt 1704 376) ) (connector (pt 1720 344) (pt 1720 400) ) (connector (pt 1704 376) (pt 1704 400) ) (connector (pt 1808 376) (pt 1848 376) ) (connector (pt 1864 344) (pt 1864 400) ) (connector (pt 1848 376) (pt 1848 400) ) (connector (pt 1952 376) (pt 1992 376) ) (connector (pt 2008 344) (pt 2008 400) ) (connector (pt 1992 376) (pt 1992 400) ) (connector (pt 2096 376) (pt 2136 376) ) (connector (pt 2152 344) (pt 2152 400) ) (connector (pt 2136 376) (pt 2136 400) ) (connector (pt 2240 376) (pt 2280 376) ) (connector (pt 2296 344) (pt 2296 400) ) (connector (pt 2280 376) (pt 2280 400) ) (connector (pt 2384 376) (pt 2424 376) ) (connector (pt 2440 344) (pt 2440 400) ) (connector (pt 2424 376) (pt 2424 400) ) (connector (pt 2384 696) (pt 2424 696) ) (connector (pt 2480 544) (pt 2440 544) (bus) ) (connector (pt 2440 544) (pt 2440 560) (bus) ) (connector (pt 2240 696) (pt 2280 696) ) (connector (pt 2336 544) (pt 2296 544) (bus) ) (connector (pt 2296 544) (pt 2296 560) (bus) ) (connector (pt 2096 696) (pt 2136 696) ) (connector (pt 2192 544) (pt 2152 544) (bus) ) (connector (pt 2152 544) (pt 2152 560) (bus) ) (connector (pt 1952 696) (pt 1992 696) ) (connector (pt 2048 544) (pt 2008 544) (bus) ) (connector (pt 2008 544) (pt 2008 560) (bus) ) (connector (pt 1808 696) (pt 1848 696) ) (connector (pt 1904 544) (pt 1864 544) (bus) ) (connector (pt 1864 544) (pt 1864 560) (bus) ) (connector (pt 1664 696) (pt 1704 696) ) (connector (pt 1760 544) (pt 1720 544) (bus) ) (connector (pt 1720 544) (pt 1720 560) (bus) ) (connector (pt 1520 696) (pt 1560 696) ) (connector (pt 1616 544) (pt 1576 544) (bus) ) (connector (pt 1576 544) (pt 1576 560) (bus) ) (connector (pt 1376 696) (pt 1416 696) ) (connector (pt 1472 544) (pt 1432 544) (bus) ) (connector (pt 1432 544) (pt 1432 560) (bus) ) (connector (pt 1232 696) (pt 1272 696) ) (connector (pt 1328 544) (pt 1288 544) (bus) ) (connector (pt 1288 544) (pt 1288 560) (bus) ) (connector (pt 1088 696) (pt 1128 696) ) (connector (pt 1184 544) (pt 1144 544) (bus) ) (connector (pt 1144 544) (pt 1144 560) (bus) ) (connector (pt 928 696) (pt 968 696) ) (connector (pt 1024 544) (pt 984 544) (bus) ) (connector (pt 984 544) (pt 984 560) (bus) ) (connector (pt 784 696) (pt 824 696) ) (connector (pt 880 544) (pt 840 544) (bus) ) (connector (pt 840 544) (pt 840 560) (bus) ) (connector (pt 696 344) (pt 712 344) (bus) ) (connector (pt 696 376) (pt 712 376) (bus) ) (connector (pt 696 696) (pt 712 696) (bus) ) (connector (pt 696 728) (pt 712 728) (bus) ) (connector (pt 2664 248) (pt 2672 248) ) (connector (pt 2672 248) (pt 2672 232) ) (connector (pt 2608 392) (pt 2608 400) ) (connector (pt 2608 416) (pt 2608 680) ) (connector (pt 2608 744) (pt 2608 760) ) (connector (pt 2632 344) (pt 2648 344) (bus) ) (connector (pt 2632 376) (pt 2648 376) (bus) ) (connector (pt 2632 696) (pt 2648 696) (bus) ) (connector (pt 2632 728) (pt 2648 728) (bus) ) (connector (pt 2608 416) (pt 2656 416) ) (connector (pt 2608 760) (pt 2544 760) ) (connector (pt 2560 400) (pt 2608 400) ) (connector (pt 2608 328) (pt 2608 320) ) (connector (pt 2608 320) (pt 2584 320) ) (connector (pt 2656 304) (pt 2656 416) ) (connector (pt 2600 304) (pt 2656 304) ) (connector (pt 984 520) (pt 984 528) (bus) ) (connector (pt 1144 520) (pt 1144 528) (bus) ) (connector (pt 1288 520) (pt 1288 528) (bus) ) (connector (pt 1432 520) (pt 1432 528) (bus) ) (connector (pt 1576 520) (pt 1576 528) (bus) ) (connector (pt 1720 520) (pt 1720 528) (bus) ) (connector (pt 1864 520) (pt 1864 528) (bus) ) (connector (pt 2008 520) (pt 2008 528) (bus) ) (connector (pt 2152 520) (pt 2152 528) (bus) ) (connector (pt 2296 520) (pt 2296 528) (bus) ) (connector (pt 2440 520) (pt 2440 528) (bus) ) (connector (pt 840 528) (pt 840 520) (bus) ) (connector (pt 2440 680) (pt 2440 728) ) (connector (pt 2424 680) (pt 2424 696) ) (connector (pt 2296 680) (pt 2296 728) ) (connector (pt 2280 680) (pt 2280 696) ) (connector (pt 2152 680) (pt 2152 728) ) (connector (pt 2136 680) (pt 2136 696) ) (connector (pt 2008 680) (pt 2008 728) ) (connector (pt 1992 680) (pt 1992 696) ) (connector (pt 1864 680) (pt 1864 728) ) (connector (pt 1848 680) (pt 1848 696) ) (connector (pt 1720 680) (pt 1720 728) ) (connector (pt 1704 680) (pt 1704 696) ) (connector (pt 1576 680) (pt 1576 728) ) (connector (pt 1560 680) (pt 1560 696) ) (connector (pt 1432 680) (pt 1432 728) ) (connector (pt 1416 680) (pt 1416 696) ) (connector (pt 1288 680) (pt 1288 728) ) (connector (pt 1272 680) (pt 1272 696) ) (connector (pt 1144 680) (pt 1144 728) ) (connector (pt 1128 680) (pt 1128 696) ) (connector (pt 984 680) (pt 984 728) ) (connector (pt 968 680) (pt 968 696) ) (connector (pt 840 680) (pt 840 728) ) (connector (pt 824 680) (pt 824 696) ) (connector (pt 2584 208) (pt 2584 320) ) (connector (pt 2600 208) (pt 2600 304) ) (connector (pt 2544 208) (pt 2544 760) ) (connector (pt 2560 208) (pt 2560 400) ) (connector (pt 936 264) (pt 984 264) ) (connector (pt 984 264) (pt 1096 264) ) (connector (pt 1096 264) (pt 1144 264) ) (connector (pt 1144 264) (pt 1240 264) ) (connector (pt 1240 264) (pt 1288 264) ) (connector (pt 1288 264) (pt 1384 264) ) (connector (pt 1384 264) (pt 1432 264) ) (connector (pt 1432 264) (pt 1528 264) ) (connector (pt 992 248) (pt 1152 248) ) (connector (pt 1152 248) (pt 1296 248) ) (connector (pt 1296 248) (pt 1440 248) ) (connector (pt 1440 248) (pt 1584 248) ) (connector (pt 1584 248) (pt 1728 248) ) (connector (pt 1728 248) (pt 1872 248) ) (connector (pt 1872 248) (pt 2016 248) ) (connector (pt 2016 248) (pt 2160 248) ) (connector (pt 776 208) (pt 776 216) ) (connector (pt 776 216) (pt 776 280) ) (connector (pt 752 216) (pt 776 216) ) (connector (pt 776 216) (pt 832 216) ) (connector (pt 920 208) (pt 920 216) ) (connector (pt 920 216) (pt 920 280) ) (connector (pt 896 216) (pt 920 216) ) (connector (pt 920 216) (pt 976 216) ) (connector (pt 1080 208) (pt 1080 216) ) (connector (pt 1080 216) (pt 1080 280) ) (connector (pt 1056 216) (pt 1080 216) ) (connector (pt 1080 216) (pt 1136 216) ) (connector (pt 1224 208) (pt 1224 216) ) (connector (pt 1224 216) (pt 1224 280) ) (connector (pt 1200 216) (pt 1224 216) ) (connector (pt 1224 216) (pt 1280 216) ) (connector (pt 1368 208) (pt 1368 216) ) (connector (pt 1368 216) (pt 1368 280) ) (connector (pt 1344 216) (pt 1368 216) ) (connector (pt 1368 216) (pt 1424 216) ) (connector (pt 1512 208) (pt 1512 216) ) (connector (pt 1512 216) (pt 1512 280) ) (connector (pt 1488 216) (pt 1512 216) ) (connector (pt 1512 216) (pt 1568 216) ) (connector (pt 1656 208) (pt 1656 216) ) (connector (pt 1656 216) (pt 1656 280) ) (connector (pt 1632 216) (pt 1656 216) ) (connector (pt 1656 216) (pt 1712 216) ) (connector (pt 1800 208) (pt 1800 216) ) (connector (pt 1800 216) (pt 1800 280) ) (connector (pt 1776 216) (pt 1800 216) ) (connector (pt 1800 216) (pt 1856 216) ) (connector (pt 1944 208) (pt 1944 216) ) (connector (pt 1944 216) (pt 1944 280) ) (connector (pt 1920 216) (pt 1944 216) ) (connector (pt 1944 216) (pt 2000 216) ) (connector (pt 2088 208) (pt 2088 216) ) (connector (pt 2088 216) (pt 2088 280) ) (connector (pt 2064 216) (pt 2088 216) ) (connector (pt 2088 216) (pt 2144 216) ) (connector (pt 2232 208) (pt 2232 216) ) (connector (pt 2232 216) (pt 2232 280) ) (connector (pt 2208 216) (pt 2232 216) ) (connector (pt 2232 216) (pt 2288 216) ) (connector (pt 2376 208) (pt 2376 216) ) (connector (pt 2376 216) (pt 2376 280) ) (connector (pt 2352 216) (pt 2376 216) ) (connector (pt 2376 216) (pt 2432 216) ) (connector (pt 384 264) (pt 480 264) ) (connector (pt 480 264) (pt 528 264) ) (connector (pt 528 264) (pt 792 264) ) (connector (pt 792 264) (pt 840 264) ) (connector (pt 208 360) (pt 424 360) (bus) ) (connector (pt 632 344) (pt 632 360) (bus) ) (connector (pt 632 360) (pt 632 376) (bus) ) (connector (pt 424 360) (pt 568 360) (bus) ) (connector (pt 568 360) (pt 632 360) (bus) ) (connector (pt 208 712) (pt 424 712) (bus) ) (connector (pt 632 696) (pt 632 712) (bus) ) (connector (pt 632 712) (pt 632 728) (bus) ) (connector (pt 424 712) (pt 568 712) (bus) ) (connector (pt 568 712) (pt 632 712) (bus) ) (connector (pt 992 824) (pt 1152 824) ) (connector (pt 1152 824) (pt 1296 824) ) (connector (pt 1296 824) (pt 1440 824) ) (connector (pt 1440 824) (pt 1584 824) ) (connector (pt 1584 824) (pt 1728 824) ) (connector (pt 1728 824) (pt 1872 824) ) (connector (pt 1872 824) (pt 2016 824) ) (connector (pt 2016 824) (pt 2160 824) ) (connector (pt 2160 824) (pt 2304 824) ) (connector (pt 2304 824) (pt 2448 824) ) (connector (pt 2448 824) (pt 2496 824) ) (connector (pt 752 808) (pt 776 808) ) (connector (pt 776 808) (pt 832 808) ) (connector (pt 896 808) (pt 920 808) ) (connector (pt 920 808) (pt 976 808) ) (connector (pt 1056 808) (pt 1080 808) ) (connector (pt 1080 808) (pt 1136 808) ) (connector (pt 1200 808) (pt 1224 808) ) (connector (pt 1224 808) (pt 1280 808) ) (connector (pt 1344 808) (pt 1368 808) ) (connector (pt 1368 808) (pt 1424 808) ) (connector (pt 936 856) (pt 984 856) ) (connector (pt 984 856) (pt 1096 856) ) (connector (pt 1488 808) (pt 1512 808) ) (connector (pt 1512 808) (pt 1568 808) ) (connector (pt 1096 856) (pt 1144 856) ) (connector (pt 1144 856) (pt 1240 856) ) (connector (pt 1632 808) (pt 1656 808) ) (connector (pt 1656 808) (pt 1712 808) ) (connector (pt 1240 856) (pt 1288 856) ) (connector (pt 1288 856) (pt 1384 856) ) (connector (pt 1776 808) (pt 1800 808) ) (connector (pt 1800 808) (pt 1856 808) ) (connector (pt 928 840) (pt 1088 840) ) (connector (pt 1384 856) (pt 1432 856) ) (connector (pt 1432 856) (pt 1528 856) ) (connector (pt 1920 808) (pt 1944 808) ) (connector (pt 1944 808) (pt 2000 808) ) (connector (pt 1088 840) (pt 1232 840) ) (connector (pt 1528 856) (pt 1576 856) ) (connector (pt 1576 856) (pt 1672 856) ) (connector (pt 2064 808) (pt 2088 808) ) (connector (pt 2088 808) (pt 2144 808) ) (connector (pt 1232 840) (pt 1376 840) ) (connector (pt 1672 856) (pt 1720 856) ) (connector (pt 1720 856) (pt 1816 856) ) (connector (pt 2208 808) (pt 2232 808) ) (connector (pt 2232 808) (pt 2288 808) ) (connector (pt 1376 840) (pt 1520 840) ) (connector (pt 1816 856) (pt 1864 856) ) (connector (pt 1864 856) (pt 1960 856) ) (connector (pt 2352 808) (pt 2376 808) ) (connector (pt 2376 808) (pt 2432 808) ) (connector (pt 1520 840) (pt 1664 840) ) (connector (pt 1664 840) (pt 1808 840) ) (connector (pt 1808 840) (pt 1952 840) ) (connector (pt 1952 840) (pt 2096 840) ) (connector (pt 2096 840) (pt 2240 840) ) (connector (pt 2240 840) (pt 2384 840) ) (connector (pt 2384 840) (pt 2512 840) ) (connector (pt 1960 856) (pt 2008 856) ) (connector (pt 2008 856) (pt 2104 856) ) (connector (pt 2104 856) (pt 2152 856) ) (connector (pt 2152 856) (pt 2248 856) ) (connector (pt 280 824) (pt 392 824) ) (connector (pt 392 824) (pt 536 824) ) (connector (pt 536 824) (pt 848 824) ) (connector (pt 216 840) (pt 328 840) ) (connector (pt 328 840) (pt 472 840) ) (connector (pt 472 840) (pt 784 840) ) (connector (pt 384 856) (pt 480 856) ) (connector (pt 480 856) (pt 528 856) ) (connector (pt 528 856) (pt 792 856) ) (connector (pt 792 856) (pt 840 856) ) (connector (pt 672 208) (pt 672 312) ) (connector (pt 672 312) (pt 672 328) ) (connector (pt 216 232) (pt 328 232) ) (connector (pt 328 232) (pt 472 232) ) (connector (pt 472 232) (pt 784 232) ) (connector (pt 280 248) (pt 392 248) ) (connector (pt 392 248) (pt 536 248) ) (connector (pt 536 248) (pt 848 248) ) (connector (pt 712 344) (pt 712 360) (bus) ) (connector (pt 712 360) (pt 712 376) (bus) ) (connector (pt 712 360) (pt 880 360) (bus) ) (connector (pt 880 360) (pt 1024 360) (bus) ) (connector (pt 1024 360) (pt 1184 360) (bus) ) (connector (pt 1184 360) (pt 1328 360) (bus) ) (connector (pt 1328 360) (pt 1472 360) (bus) ) (connector (pt 1472 360) (pt 1616 360) (bus) ) (connector (pt 1616 360) (pt 1760 360) (bus) ) (connector (pt 1760 360) (pt 1904 360) (bus) ) (connector (pt 1904 360) (pt 2048 360) (bus) ) (connector (pt 712 696) (pt 712 712) (bus) ) (connector (pt 712 712) (pt 712 728) (bus) ) (connector (pt 712 712) (pt 880 712) (bus) ) (connector (pt 880 712) (pt 1024 712) (bus) ) (connector (pt 1024 712) (pt 1184 712) (bus) ) (connector (pt 1184 712) (pt 1328 712) (bus) ) (connector (pt 1328 712) (pt 1472 712) (bus) ) (connector (pt 1472 712) (pt 1616 712) (bus) ) (connector (pt 1616 712) (pt 1760 712) (bus) ) (connector (pt 1760 712) (pt 1904 712) (bus) ) (connector (pt 1904 712) (pt 2048 712) (bus) ) (connector (pt 928 232) (pt 1088 232) ) (connector (pt 1088 232) (pt 1232 232) ) (connector (pt 1232 232) (pt 1376 232) ) (connector (pt 1376 232) (pt 1520 232) ) (connector (pt 1520 232) (pt 1664 232) ) (connector (pt 1664 232) (pt 1808 232) ) (connector (pt 1808 232) (pt 1952 232) ) (connector (pt 1952 232) (pt 2096 232) ) (connector (pt 1528 264) (pt 1576 264) ) (connector (pt 1576 264) (pt 1672 264) ) (connector (pt 1672 264) (pt 1720 264) ) (connector (pt 1720 264) (pt 1816 264) ) (connector (pt 1816 264) (pt 1864 264) ) (connector (pt 1864 264) (pt 1960 264) ) (connector (pt 1960 264) (pt 2008 264) ) (connector (pt 2008 264) (pt 2104 264) ) (connector (pt 2104 264) (pt 2152 264) ) (connector (pt 2152 264) (pt 2248 264) ) (connector (pt 2096 232) (pt 2240 232) ) (connector (pt 2160 248) (pt 2304 248) ) (connector (pt 2248 264) (pt 2296 264) ) (connector (pt 2240 232) (pt 2384 232) ) (connector (pt 2304 248) (pt 2448 248) ) (connector (pt 2296 264) (pt 2392 264) ) (connector (pt 2384 232) (pt 2512 232) ) (connector (pt 2248 856) (pt 2296 856) ) (connector (pt 2296 856) (pt 2392 856) ) (connector (pt 2048 360) (pt 2192 360) (bus) ) (connector (pt 2192 360) (pt 2336 360) (bus) ) (connector (pt 2568 344) (pt 2568 360) (bus) ) (connector (pt 2568 360) (pt 2568 376) (bus) ) (connector (pt 2336 360) (pt 2480 360) (bus) ) (connector (pt 2480 360) (pt 2568 360) (bus) ) (connector (pt 2048 712) (pt 2192 712) (bus) ) (connector (pt 2192 712) (pt 2336 712) (bus) ) (connector (pt 2568 696) (pt 2568 712) (bus) ) (connector (pt 2568 712) (pt 2568 728) (bus) ) (connector (pt 2336 712) (pt 2480 712) (bus) ) (connector (pt 2480 712) (pt 2568 712) (bus) ) (connector (pt 2264 520) (pt 2264 536) ) (connector (pt 2264 536) (pt 2264 560) ) (connector (pt 2408 520) (pt 2408 536) ) (connector (pt 2408 536) (pt 2408 560) ) (connector (pt 2120 520) (pt 2120 536) ) (connector (pt 2120 536) (pt 2120 560) ) (connector (pt 2264 536) (pt 2408 536) ) (connector (pt 1976 520) (pt 1976 536) ) (connector (pt 1976 536) (pt 1976 560) ) (connector (pt 2120 536) (pt 2264 536) ) (connector (pt 1832 520) (pt 1832 536) ) (connector (pt 1832 536) (pt 1832 560) ) (connector (pt 1976 536) (pt 2120 536) ) (connector (pt 1688 520) (pt 1688 536) ) (connector (pt 1688 536) (pt 1688 560) ) (connector (pt 1832 536) (pt 1976 536) ) (connector (pt 1544 520) (pt 1544 536) ) (connector (pt 1544 536) (pt 1544 560) ) (connector (pt 1688 536) (pt 1832 536) ) (connector (pt 1400 520) (pt 1400 536) ) (connector (pt 1400 536) (pt 1400 560) ) (connector (pt 1544 536) (pt 1688 536) ) (connector (pt 1256 520) (pt 1256 536) ) (connector (pt 1256 536) (pt 1256 560) ) (connector (pt 1400 536) (pt 1544 536) ) (connector (pt 1112 520) (pt 1112 536) ) (connector (pt 1112 536) (pt 1112 560) ) (connector (pt 1256 536) (pt 1400 536) ) (connector (pt 952 520) (pt 952 536) ) (connector (pt 952 536) (pt 952 560) ) (connector (pt 1112 536) (pt 1256 536) ) (connector (pt 496 520) (pt 496 536) ) (connector (pt 496 536) (pt 496 560) ) (connector (pt 208 536) (pt 352 536) ) (connector (pt 808 520) (pt 808 536) ) (connector (pt 808 536) (pt 808 560) ) (connector (pt 352 536) (pt 496 536) ) (connector (pt 496 536) (pt 808 536) ) (connector (pt 808 536) (pt 952 536) ) (connector (pt 952 536) (pt 1112 536) ) (connector (pt 2448 248) (pt 2496 248) ) (connector (pt 2392 264) (pt 2440 264) ) (connector (pt 2392 856) (pt 2440 856) ) (connector (pt 2512 232) (pt 2672 232) ) (connector (pt 2648 344) (pt 2648 360) (bus) ) (connector (pt 2648 360) (pt 2648 376) (bus) ) (connector (pt 2648 696) (pt 2648 712) (bus) ) (connector (pt 2648 712) (pt 2648 728) (bus) ) (connector (pt 632 344) (pt 648 344) (bus) ) (connector (pt 632 376) (pt 648 376) (bus) ) (connector (pt 632 696) (pt 648 696) (bus) ) (connector (pt 632 728) (pt 648 728) (bus) ) (connector (pt 2496 248) (pt 2616 248) ) (connector (pt 2568 344) (pt 2584 344) (bus) ) (connector (pt 2568 376) (pt 2584 376) (bus) ) (connector (pt 2568 696) (pt 2584 696) (bus) ) (connector (pt 2568 728) (pt 2584 728) (bus) ) (connector (pt 2440 264) (pt 2688 264) ) (connector (pt 2440 856) (pt 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(junction (pt 1960 264)) (junction (pt 2008 264)) (junction (pt 2104 264)) (junction (pt 2152 264)) (junction (pt 2248 264)) (junction (pt 2296 264)) (junction (pt 2384 232)) (junction (pt 2448 248)) (junction (pt 2392 264)) (junction (pt 2512 232)) (junction (pt 2496 248)) (junction (pt 2440 264)) (junction (pt 2672 232)) (junction (pt 2392 856)) (junction (pt 2440 856)) (junction (pt 2336 360)) (junction (pt 2480 360)) (junction (pt 2568 360)) (junction (pt 2336 712)) (junction (pt 2480 712)) (junction (pt 2568 712)) (junction (pt 2264 536)) (junction (pt 2408 536)) (junction (pt 2120 536)) (junction (pt 1976 536)) (junction (pt 1832 536)) (junction (pt 1688 536)) (junction (pt 1544 536)) (junction (pt 1400 536)) (junction (pt 1256 536)) (junction (pt 1112 536)) (junction (pt 952 536)) (junction (pt 808 536)) (junction (pt 2648 360)) (junction (pt 2648 712)) (text "SW4" (rect 640 792 681 810)(font "Arial" (color 0 0 0)(font_size 12))) (text "Register Gate" (rect 2552 800 2666 818)(font "Arial" (color 0 0 0)(font_size 12))) (rectangle (rect 592 296 728 776)(fill (color 255 170 255))) (rectangle (rect 2528 296 2664 776)(fill (color 255 170 255))) (title_block (rect 32 888 353 949) (name "title-custom-medium") (section (rect 0 41 240 60)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "May 17, 2014, 2016" (rect 56 3 191 19)(font "Arial" (font_size 10)))(border)) (section (rect 0 21 320 40)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 151 19)(font "Arial" (font_size 11)))(border)) (section (rect 130 0 320 20)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "reg_file" (rect 43 2 109 21)(font "Arial" (font_size 12)(bold)))(border)) (section (rect 0 0 320 20)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 106 21)(font "Arial" (font_size 12)(bold)))(border)) (section (rect 241 41 320 60)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.5" (rect 43 3 64 19)(font "Arial" (font_size 10)))(border)) (drawing ) ) ================================================ FILE: cpu/registers/reg_file.bsf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "symbol" (version "1.2")) (symbol (rect 16 16 240 528) (text "reg_file" (rect 5 0 47 14)(font "Arial" (font_size 8))) (text "inst" (rect 8 496 25 508)(font "Arial" )) (port (pt 0 32) (input) (text "reg_sel_ir" (rect 0 0 56 14)(font "Arial" (font_size 8))) (text "reg_sel_ir" (rect 21 27 77 41)(font "Arial" (font_size 8))) (line (pt 0 32)(pt 16 32)) ) (port (pt 0 48) (input) (text "reg_sel_pc" (rect 0 0 63 14)(font "Arial" (font_size 8))) (text "reg_sel_pc" (rect 21 43 84 57)(font "Arial" (font_size 8))) (line (pt 0 48)(pt 16 48)) ) (port (pt 0 64) (input) (text "ctl_sw_4u" (rect 0 0 60 14)(font "Arial" (font_size 8))) (text "ctl_sw_4u" (rect 21 59 81 73)(font "Arial" (font_size 8))) (line (pt 0 64)(pt 16 64)) ) (port (pt 0 80) (input) (text "reg_sel_wz" (rect 0 0 68 14)(font "Arial" (font_size 8))) (text "reg_sel_wz" (rect 21 75 89 89)(font "Arial" (font_size 8))) (line (pt 0 80)(pt 16 80)) ) (port (pt 0 96) (input) (text "reg_sel_sp" (rect 0 0 63 14)(font "Arial" (font_size 8))) (text "reg_sel_sp" (rect 21 91 84 105)(font "Arial" (font_size 8))) (line (pt 0 96)(pt 16 96)) ) (port (pt 0 112) (input) (text "reg_sel_iy" (rect 0 0 59 14)(font "Arial" (font_size 8))) (text "reg_sel_iy" (rect 21 107 80 121)(font "Arial" (font_size 8))) (line (pt 0 112)(pt 16 112)) ) (port (pt 0 128) (input) (text "reg_sel_ix" (rect 0 0 59 14)(font "Arial" (font_size 8))) (text "reg_sel_ix" (rect 21 123 80 137)(font "Arial" (font_size 8))) (line (pt 0 128)(pt 16 128)) ) (port (pt 0 144) (input) (text "reg_sel_hl2" (rect 0 0 66 14)(font "Arial" (font_size 8))) (text "reg_sel_hl2" (rect 21 139 87 153)(font "Arial" (font_size 8))) (line (pt 0 144)(pt 16 144)) ) (port (pt 0 160) (input) (text "reg_sel_hl" (rect 0 0 59 14)(font "Arial" (font_size 8))) (text "reg_sel_hl" (rect 21 155 80 169)(font "Arial" (font_size 8))) (line (pt 0 160)(pt 16 160)) ) (port (pt 0 176) (input) (text "reg_sel_de2" (rect 0 0 70 14)(font "Arial" (font_size 8))) (text "reg_sel_de2" (rect 21 171 91 185)(font "Arial" (font_size 8))) (line (pt 0 176)(pt 16 176)) ) (port (pt 0 192) (input) (text "reg_sel_de" (rect 0 0 63 14)(font "Arial" (font_size 8))) (text "reg_sel_de" (rect 21 187 84 201)(font "Arial" (font_size 8))) (line (pt 0 192)(pt 16 192)) ) (port (pt 0 208) (input) (text "reg_sel_bc2" (rect 0 0 70 14)(font "Arial" (font_size 8))) (text "reg_sel_bc2" (rect 21 203 91 217)(font "Arial" (font_size 8))) (line (pt 0 208)(pt 16 208)) ) (port (pt 0 224) (input) (text "reg_sel_bc" (rect 0 0 63 14)(font "Arial" (font_size 8))) (text "reg_sel_bc" (rect 21 219 84 233)(font "Arial" (font_size 8))) (line (pt 0 224)(pt 16 224)) ) (port (pt 0 240) (input) (text "reg_sel_af2" (rect 0 0 68 14)(font "Arial" (font_size 8))) (text "reg_sel_af2" (rect 21 235 89 249)(font "Arial" (font_size 8))) (line (pt 0 240)(pt 16 240)) ) (port (pt 0 256) (input) (text "reg_sel_af" (rect 0 0 61 14)(font "Arial" (font_size 8))) (text "reg_sel_af" (rect 21 251 82 265)(font "Arial" (font_size 8))) (line (pt 0 256)(pt 16 256)) ) (port (pt 0 272) (input) (text "ctl_reg_in_hi" (rect 0 0 71 14)(font "Arial" (font_size 8))) (text "ctl_reg_in_hi" (rect 21 267 92 281)(font "Arial" (font_size 8))) (line (pt 0 272)(pt 16 272)) ) (port (pt 0 288) (input) (text "ctl_reg_in_lo" (rect 0 0 71 14)(font "Arial" (font_size 8))) (text "ctl_reg_in_lo" (rect 21 283 92 297)(font "Arial" (font_size 8))) (line (pt 0 288)(pt 16 288)) ) (port (pt 0 304) (input) (text "ctl_reg_out_lo" (rect 0 0 80 14)(font "Arial" (font_size 8))) (text "ctl_reg_out_lo" (rect 21 299 101 313)(font "Arial" (font_size 8))) (line (pt 0 304)(pt 16 304)) ) (port (pt 0 320) (input) (text "ctl_reg_out_hi" (rect 0 0 80 14)(font "Arial" (font_size 8))) (text "ctl_reg_out_hi" (rect 21 315 101 329)(font "Arial" (font_size 8))) (line (pt 0 320)(pt 16 320)) ) (port (pt 0 336) (input) (text "reg_sw_4d_lo" (rect 0 0 82 14)(font "Arial" (font_size 8))) (text "reg_sw_4d_lo" (rect 21 331 103 345)(font "Arial" (font_size 8))) (line (pt 0 336)(pt 16 336)) ) (port (pt 0 352) (input) (text "reg_sw_4d_hi" (rect 0 0 82 14)(font "Arial" (font_size 8))) (text "reg_sw_4d_hi" (rect 21 347 103 361)(font "Arial" (font_size 8))) (line (pt 0 352)(pt 16 352)) ) (port (pt 0 368) (input) (text "reg_gp_we" (rect 0 0 66 14)(font "Arial" (font_size 8))) (text "reg_gp_we" (rect 21 363 87 377)(font "Arial" (font_size 8))) (line (pt 0 368)(pt 16 368)) ) (port (pt 0 384) (input) (text "reg_sys_we_lo" (rect 0 0 89 14)(font "Arial" (font_size 8))) (text "reg_sys_we_lo" (rect 21 379 110 393)(font "Arial" (font_size 8))) (line (pt 0 384)(pt 16 384)) ) (port (pt 0 400) (input) (text "reg_sel_sys_lo" (rect 0 0 87 14)(font "Arial" (font_size 8))) (text "reg_sel_sys_lo" (rect 21 395 108 409)(font "Arial" (font_size 8))) (line (pt 0 400)(pt 16 400)) ) (port (pt 0 416) (input) (text "reg_sel_gp_lo" (rect 0 0 80 14)(font "Arial" (font_size 8))) (text "reg_sel_gp_lo" (rect 21 411 101 425)(font "Arial" (font_size 8))) (line (pt 0 416)(pt 16 416)) ) (port (pt 0 432) (input) (text "clk" (rect 0 0 15 14)(font "Arial" (font_size 8))) (text "clk" (rect 21 427 36 441)(font "Arial" (font_size 8))) (line (pt 0 432)(pt 16 432)) ) (port (pt 0 448) (input) (text "reg_sys_we_hi" (rect 0 0 89 14)(font "Arial" (font_size 8))) (text "reg_sys_we_hi" (rect 21 443 110 457)(font "Arial" (font_size 8))) (line (pt 0 448)(pt 16 448)) ) (port (pt 0 464) (input) (text "reg_sel_sys_hi" (rect 0 0 87 14)(font "Arial" (font_size 8))) (text "reg_sel_sys_hi" (rect 21 459 108 473)(font "Arial" (font_size 8))) (line (pt 0 464)(pt 16 464)) ) (port (pt 0 480) (input) (text "reg_sel_gp_hi" (rect 0 0 80 14)(font "Arial" (font_size 8))) (text "reg_sel_gp_hi" (rect 21 475 101 489)(font "Arial" (font_size 8))) (line (pt 0 480)(pt 16 480)) ) (port (pt 224 32) (bidir) (text "db_lo_ds[7..0]" (rect 0 0 80 14)(font "Arial" (font_size 8))) (text "db_lo_ds[7..0]" (rect 123 27 203 41)(font "Arial" (font_size 8))) (line (pt 224 32)(pt 208 32)(line_width 3)) ) (port (pt 224 48) (bidir) (text "db_lo_as[7..0]" (rect 0 0 80 14)(font "Arial" (font_size 8))) (text "db_lo_as[7..0]" (rect 123 43 203 57)(font "Arial" (font_size 8))) (line (pt 224 48)(pt 208 48)(line_width 3)) ) (port (pt 224 64) (bidir) (text "db_hi_ds[7..0]" (rect 0 0 80 14)(font "Arial" (font_size 8))) (text "db_hi_ds[7..0]" (rect 123 59 203 73)(font "Arial" (font_size 8))) (line (pt 224 64)(pt 208 64)(line_width 3)) ) (port (pt 224 80) (bidir) (text "db_hi_as[7..0]" (rect 0 0 80 14)(font "Arial" (font_size 8))) (text "db_hi_as[7..0]" (rect 123 75 203 89)(font "Arial" (font_size 8))) (line (pt 224 80)(pt 208 80)(line_width 3)) ) (drawing (rectangle (rect 16 16 208 496)) ) ) ================================================ FILE: cpu/registers/reg_file.v ================================================ // Copyright (C) 1991-2013 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // PROGRAM "Quartus II 64-Bit" // VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" // CREATED "Tue Mar 08 06:12:46 2016" module reg_file( reg_sel_sys_lo, reg_sel_gp_lo, reg_sel_sys_hi, reg_sel_gp_hi, reg_sel_ir, reg_sel_pc, ctl_sw_4u, reg_sel_wz, reg_sel_sp, reg_sel_iy, reg_sel_ix, reg_sel_hl2, reg_sel_hl, reg_sel_de2, reg_sel_de, reg_sel_bc2, reg_sel_bc, reg_sel_af2, reg_sel_af, reg_gp_we, reg_sys_we_lo, reg_sys_we_hi, ctl_reg_in_hi, ctl_reg_in_lo, ctl_reg_out_lo, ctl_reg_out_hi, clk, reg_sw_4d_lo, reg_sw_4d_hi, db_hi_as, db_hi_ds, db_lo_as, db_lo_ds ); input wire reg_sel_sys_lo; input wire reg_sel_gp_lo; input wire reg_sel_sys_hi; input wire reg_sel_gp_hi; input wire reg_sel_ir; input wire reg_sel_pc; input wire ctl_sw_4u; input wire reg_sel_wz; input wire reg_sel_sp; input wire reg_sel_iy; input wire reg_sel_ix; input wire reg_sel_hl2; input wire reg_sel_hl; input wire reg_sel_de2; input wire reg_sel_de; input wire reg_sel_bc2; input wire reg_sel_bc; input wire reg_sel_af2; input wire reg_sel_af; input wire reg_gp_we; input wire reg_sys_we_lo; input wire reg_sys_we_hi; input wire ctl_reg_in_hi; input wire ctl_reg_in_lo; input wire ctl_reg_out_lo; input wire ctl_reg_out_hi; input wire clk; input wire reg_sw_4d_lo; input wire reg_sw_4d_hi; inout wire [7:0] db_hi_as; inout wire [7:0] db_hi_ds; inout wire [7:0] db_lo_as; inout wire [7:0] db_lo_ds; wire [7:0] gdfx_temp0; wire [7:0] gdfx_temp1; wire SYNTHESIZED_WIRE_84; wire SYNTHESIZED_WIRE_85; wire SYNTHESIZED_WIRE_86; wire SYNTHESIZED_WIRE_28; wire SYNTHESIZED_WIRE_29; wire SYNTHESIZED_WIRE_30; wire SYNTHESIZED_WIRE_31; wire SYNTHESIZED_WIRE_32; wire SYNTHESIZED_WIRE_33; wire SYNTHESIZED_WIRE_34; wire SYNTHESIZED_WIRE_35; wire SYNTHESIZED_WIRE_36; wire SYNTHESIZED_WIRE_37; wire SYNTHESIZED_WIRE_38; wire SYNTHESIZED_WIRE_39; wire SYNTHESIZED_WIRE_40; wire SYNTHESIZED_WIRE_41; wire SYNTHESIZED_WIRE_42; wire SYNTHESIZED_WIRE_43; wire SYNTHESIZED_WIRE_44; wire SYNTHESIZED_WIRE_45; wire SYNTHESIZED_WIRE_46; wire SYNTHESIZED_WIRE_47; wire SYNTHESIZED_WIRE_48; wire SYNTHESIZED_WIRE_49; wire SYNTHESIZED_WIRE_50; wire SYNTHESIZED_WIRE_51; wire SYNTHESIZED_WIRE_52; wire SYNTHESIZED_WIRE_53; wire SYNTHESIZED_WIRE_54; wire SYNTHESIZED_WIRE_55; wire SYNTHESIZED_WIRE_56; wire SYNTHESIZED_WIRE_57; wire SYNTHESIZED_WIRE_58; wire SYNTHESIZED_WIRE_59; wire SYNTHESIZED_WIRE_60; wire SYNTHESIZED_WIRE_61; wire SYNTHESIZED_WIRE_62; wire SYNTHESIZED_WIRE_63; wire SYNTHESIZED_WIRE_64; wire SYNTHESIZED_WIRE_65; wire SYNTHESIZED_WIRE_66; wire SYNTHESIZED_WIRE_67; wire SYNTHESIZED_WIRE_68; wire SYNTHESIZED_WIRE_69; wire SYNTHESIZED_WIRE_70; wire SYNTHESIZED_WIRE_71; wire SYNTHESIZED_WIRE_72; wire SYNTHESIZED_WIRE_73; wire SYNTHESIZED_WIRE_74; wire SYNTHESIZED_WIRE_75; wire SYNTHESIZED_WIRE_76; wire SYNTHESIZED_WIRE_77; wire SYNTHESIZED_WIRE_78; wire SYNTHESIZED_WIRE_79; wire SYNTHESIZED_WIRE_80; wire SYNTHESIZED_WIRE_81; wire SYNTHESIZED_WIRE_82; wire SYNTHESIZED_WIRE_83; assign SYNTHESIZED_WIRE_82 = SYNTHESIZED_WIRE_84 & reg_sel_sys_lo & reg_sel_wz; assign SYNTHESIZED_WIRE_80 = reg_sel_wz & reg_sel_sys_hi & SYNTHESIZED_WIRE_85; assign SYNTHESIZED_WIRE_78 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_sp; assign SYNTHESIZED_WIRE_76 = reg_sel_sp & reg_sel_gp_hi & SYNTHESIZED_WIRE_86; assign SYNTHESIZED_WIRE_84 = ~reg_sys_we_lo; assign SYNTHESIZED_WIRE_71 = reg_sel_gp_lo & reg_gp_we & reg_sel_iy; assign SYNTHESIZED_WIRE_85 = ~reg_sys_we_hi; assign SYNTHESIZED_WIRE_74 = SYNTHESIZED_WIRE_84 & reg_sel_sys_lo & reg_sel_pc; assign SYNTHESIZED_WIRE_67 = reg_sel_gp_lo & reg_gp_we & reg_sel_ix; assign SYNTHESIZED_WIRE_55 = reg_sel_gp_lo & reg_gp_we & reg_sel_hl2; assign SYNTHESIZED_WIRE_72 = reg_sel_pc & reg_sel_sys_hi & SYNTHESIZED_WIRE_85; assign SYNTHESIZED_WIRE_59 = reg_sel_gp_lo & reg_gp_we & reg_sel_hl; assign SYNTHESIZED_WIRE_47 = reg_sel_gp_lo & reg_gp_we & reg_sel_de2; assign SYNTHESIZED_WIRE_51 = reg_sel_gp_lo & reg_gp_we & reg_sel_de; assign SYNTHESIZED_WIRE_81 = reg_sel_wz & reg_sys_we_hi & reg_sel_sys_hi; assign SYNTHESIZED_WIRE_86 = ~reg_gp_we; assign SYNTHESIZED_WIRE_70 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_iy; assign SYNTHESIZED_WIRE_68 = reg_sel_iy & reg_sel_gp_hi & SYNTHESIZED_WIRE_86; assign SYNTHESIZED_WIRE_39 = reg_sel_gp_lo & reg_gp_we & reg_sel_bc2; assign SYNTHESIZED_WIRE_43 = reg_sel_gp_lo & reg_gp_we & reg_sel_bc; assign SYNTHESIZED_WIRE_31 = reg_sel_gp_lo & reg_gp_we & reg_sel_af2; assign SYNTHESIZED_WIRE_77 = reg_sel_sp & reg_gp_we & reg_sel_gp_hi; assign SYNTHESIZED_WIRE_66 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_ix; assign SYNTHESIZED_WIRE_64 = reg_sel_ix & reg_sel_gp_hi & SYNTHESIZED_WIRE_86; assign SYNTHESIZED_WIRE_35 = reg_sel_gp_lo & reg_gp_we & reg_sel_af; assign SYNTHESIZED_WIRE_69 = reg_sel_iy & reg_gp_we & reg_sel_gp_hi; assign SYNTHESIZED_WIRE_63 = reg_sel_sys_lo & reg_sys_we_lo & reg_sel_ir; assign SYNTHESIZED_WIRE_65 = reg_sel_ix & reg_gp_we & reg_sel_gp_hi; assign SYNTHESIZED_WIRE_53 = reg_sel_hl2 & reg_gp_we & reg_sel_gp_hi; assign SYNTHESIZED_WIRE_54 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_hl2; assign SYNTHESIZED_WIRE_52 = reg_sel_hl2 & reg_sel_gp_hi & SYNTHESIZED_WIRE_86; assign SYNTHESIZED_WIRE_57 = reg_sel_hl & reg_gp_we & reg_sel_gp_hi; assign SYNTHESIZED_WIRE_45 = reg_sel_de2 & reg_gp_we & reg_sel_gp_hi; assign SYNTHESIZED_WIRE_49 = reg_sel_de & reg_gp_we & reg_sel_gp_hi; assign SYNTHESIZED_WIRE_37 = reg_sel_bc2 & reg_gp_we & reg_sel_gp_hi; assign SYNTHESIZED_WIRE_58 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_hl; assign SYNTHESIZED_WIRE_56 = reg_sel_hl & reg_sel_gp_hi & SYNTHESIZED_WIRE_86; assign SYNTHESIZED_WIRE_75 = reg_sel_sys_lo & reg_sys_we_lo & reg_sel_pc; assign SYNTHESIZED_WIRE_41 = reg_sel_bc & reg_gp_we & reg_sel_gp_hi; assign SYNTHESIZED_WIRE_29 = reg_sel_af2 & reg_gp_we & reg_sel_gp_hi; assign SYNTHESIZED_WIRE_33 = reg_sel_af & reg_gp_we & reg_sel_gp_hi; assign SYNTHESIZED_WIRE_61 = reg_sel_ir & reg_sys_we_hi & reg_sel_sys_hi; assign SYNTHESIZED_WIRE_46 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_de2; assign SYNTHESIZED_WIRE_44 = reg_sel_de2 & reg_sel_gp_hi & SYNTHESIZED_WIRE_86; assign SYNTHESIZED_WIRE_73 = reg_sel_pc & reg_sys_we_hi & reg_sel_sys_hi; assign SYNTHESIZED_WIRE_83 = reg_sel_sys_lo & reg_sys_we_lo & reg_sel_wz; assign SYNTHESIZED_WIRE_50 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_de; assign SYNTHESIZED_WIRE_48 = reg_sel_de & reg_sel_gp_hi & SYNTHESIZED_WIRE_86; assign SYNTHESIZED_WIRE_38 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_bc2; assign SYNTHESIZED_WIRE_36 = reg_sel_bc2 & reg_sel_gp_hi & SYNTHESIZED_WIRE_86; assign SYNTHESIZED_WIRE_42 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_bc; assign SYNTHESIZED_WIRE_40 = reg_sel_bc & reg_sel_gp_hi & SYNTHESIZED_WIRE_86; assign SYNTHESIZED_WIRE_30 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_af2; assign SYNTHESIZED_WIRE_28 = reg_sel_af2 & reg_sel_gp_hi & SYNTHESIZED_WIRE_86; assign SYNTHESIZED_WIRE_62 = SYNTHESIZED_WIRE_84 & reg_sel_sys_lo & reg_sel_ir; assign SYNTHESIZED_WIRE_34 = SYNTHESIZED_WIRE_86 & reg_sel_gp_lo & reg_sel_af; assign SYNTHESIZED_WIRE_32 = reg_sel_af & reg_sel_gp_hi & SYNTHESIZED_WIRE_86; assign SYNTHESIZED_WIRE_60 = reg_sel_ir & reg_sel_sys_hi & SYNTHESIZED_WIRE_85; assign SYNTHESIZED_WIRE_79 = reg_sel_gp_lo & reg_gp_we & reg_sel_sp; reg_latch b2v_latch_af2_hi( .oe(SYNTHESIZED_WIRE_28), .we(SYNTHESIZED_WIRE_29), .clk(clk), .db(gdfx_temp1) ); reg_latch b2v_latch_af2_lo( .oe(SYNTHESIZED_WIRE_30), .we(SYNTHESIZED_WIRE_31), .clk(clk), .db(gdfx_temp0) ); reg_latch b2v_latch_af_hi( .oe(SYNTHESIZED_WIRE_32), .we(SYNTHESIZED_WIRE_33), .clk(clk), .db(gdfx_temp1) ); reg_latch b2v_latch_af_lo( .oe(SYNTHESIZED_WIRE_34), .we(SYNTHESIZED_WIRE_35), .clk(clk), .db(gdfx_temp0) ); reg_latch b2v_latch_bc2_hi( .oe(SYNTHESIZED_WIRE_36), .we(SYNTHESIZED_WIRE_37), .clk(clk), .db(gdfx_temp1) ); reg_latch b2v_latch_bc2_lo( .oe(SYNTHESIZED_WIRE_38), .we(SYNTHESIZED_WIRE_39), .clk(clk), .db(gdfx_temp0) ); reg_latch b2v_latch_bc_hi( .oe(SYNTHESIZED_WIRE_40), .we(SYNTHESIZED_WIRE_41), .clk(clk), .db(gdfx_temp1) ); reg_latch b2v_latch_bc_lo( .oe(SYNTHESIZED_WIRE_42), .we(SYNTHESIZED_WIRE_43), .clk(clk), .db(gdfx_temp0) ); reg_latch b2v_latch_de2_hi( .oe(SYNTHESIZED_WIRE_44), .we(SYNTHESIZED_WIRE_45), .clk(clk), .db(gdfx_temp1) ); reg_latch b2v_latch_de2_lo( .oe(SYNTHESIZED_WIRE_46), .we(SYNTHESIZED_WIRE_47), .clk(clk), .db(gdfx_temp0) ); reg_latch b2v_latch_de_hi( .oe(SYNTHESIZED_WIRE_48), .we(SYNTHESIZED_WIRE_49), .clk(clk), .db(gdfx_temp1) ); reg_latch b2v_latch_de_lo( .oe(SYNTHESIZED_WIRE_50), .we(SYNTHESIZED_WIRE_51), .clk(clk), .db(gdfx_temp0) ); reg_latch b2v_latch_hl2_hi( .oe(SYNTHESIZED_WIRE_52), .we(SYNTHESIZED_WIRE_53), .clk(clk), .db(gdfx_temp1) ); reg_latch b2v_latch_hl2_lo( .oe(SYNTHESIZED_WIRE_54), .we(SYNTHESIZED_WIRE_55), .clk(clk), .db(gdfx_temp0) ); reg_latch b2v_latch_hl_hi( .oe(SYNTHESIZED_WIRE_56), .we(SYNTHESIZED_WIRE_57), .clk(clk), .db(gdfx_temp1) ); reg_latch b2v_latch_hl_lo( .oe(SYNTHESIZED_WIRE_58), .we(SYNTHESIZED_WIRE_59), .clk(clk), .db(gdfx_temp0) ); reg_latch b2v_latch_ir_hi( .oe(SYNTHESIZED_WIRE_60), .we(SYNTHESIZED_WIRE_61), .clk(clk), .db(db_hi_as) ); reg_latch b2v_latch_ir_lo( .oe(SYNTHESIZED_WIRE_62), .we(SYNTHESIZED_WIRE_63), .clk(clk), .db(db_lo_as) ); reg_latch b2v_latch_ix_hi( .oe(SYNTHESIZED_WIRE_64), .we(SYNTHESIZED_WIRE_65), .clk(clk), .db(gdfx_temp1) ); reg_latch b2v_latch_ix_lo( .oe(SYNTHESIZED_WIRE_66), .we(SYNTHESIZED_WIRE_67), .clk(clk), .db(gdfx_temp0) ); reg_latch b2v_latch_iy_hi( .oe(SYNTHESIZED_WIRE_68), .we(SYNTHESIZED_WIRE_69), .clk(clk), .db(gdfx_temp1) ); reg_latch b2v_latch_iy_lo( .oe(SYNTHESIZED_WIRE_70), .we(SYNTHESIZED_WIRE_71), .clk(clk), .db(gdfx_temp0) ); reg_latch b2v_latch_pc_hi( .oe(SYNTHESIZED_WIRE_72), .we(SYNTHESIZED_WIRE_73), .clk(clk), .db(db_hi_as) ); reg_latch b2v_latch_pc_lo( .oe(SYNTHESIZED_WIRE_74), .we(SYNTHESIZED_WIRE_75), .clk(clk), .db(db_lo_as) ); reg_latch b2v_latch_sp_hi( .oe(SYNTHESIZED_WIRE_76), .we(SYNTHESIZED_WIRE_77), .clk(clk), .db(gdfx_temp1) ); reg_latch b2v_latch_sp_lo( .oe(SYNTHESIZED_WIRE_78), .we(SYNTHESIZED_WIRE_79), .clk(clk), .db(gdfx_temp0) ); reg_latch b2v_latch_wz_hi( .oe(SYNTHESIZED_WIRE_80), .we(SYNTHESIZED_WIRE_81), .clk(clk), .db(gdfx_temp1) ); reg_latch b2v_latch_wz_lo( .oe(SYNTHESIZED_WIRE_82), .we(SYNTHESIZED_WIRE_83), .clk(clk), .db(gdfx_temp0) ); assign gdfx_temp0[7] = ctl_sw_4u ? db_lo_as[7] : 1'bz; assign gdfx_temp0[6] = ctl_sw_4u ? db_lo_as[6] : 1'bz; assign gdfx_temp0[5] = ctl_sw_4u ? db_lo_as[5] : 1'bz; assign gdfx_temp0[4] = ctl_sw_4u ? db_lo_as[4] : 1'bz; assign gdfx_temp0[3] = ctl_sw_4u ? db_lo_as[3] : 1'bz; assign gdfx_temp0[2] = ctl_sw_4u ? db_lo_as[2] : 1'bz; assign gdfx_temp0[1] = ctl_sw_4u ? db_lo_as[1] : 1'bz; assign gdfx_temp0[0] = ctl_sw_4u ? db_lo_as[0] : 1'bz; assign db_lo_as[7] = reg_sw_4d_lo ? gdfx_temp0[7] : 1'bz; assign db_lo_as[6] = reg_sw_4d_lo ? gdfx_temp0[6] : 1'bz; assign db_lo_as[5] = reg_sw_4d_lo ? gdfx_temp0[5] : 1'bz; assign db_lo_as[4] = reg_sw_4d_lo ? gdfx_temp0[4] : 1'bz; assign db_lo_as[3] = reg_sw_4d_lo ? gdfx_temp0[3] : 1'bz; assign db_lo_as[2] = reg_sw_4d_lo ? gdfx_temp0[2] : 1'bz; assign db_lo_as[1] = reg_sw_4d_lo ? gdfx_temp0[1] : 1'bz; assign db_lo_as[0] = reg_sw_4d_lo ? gdfx_temp0[0] : 1'bz; assign gdfx_temp1[7] = ctl_sw_4u ? db_hi_as[7] : 1'bz; assign gdfx_temp1[6] = ctl_sw_4u ? db_hi_as[6] : 1'bz; assign gdfx_temp1[5] = ctl_sw_4u ? db_hi_as[5] : 1'bz; assign gdfx_temp1[4] = ctl_sw_4u ? db_hi_as[4] : 1'bz; assign gdfx_temp1[3] = ctl_sw_4u ? db_hi_as[3] : 1'bz; assign gdfx_temp1[2] = ctl_sw_4u ? db_hi_as[2] : 1'bz; assign gdfx_temp1[1] = ctl_sw_4u ? db_hi_as[1] : 1'bz; assign gdfx_temp1[0] = ctl_sw_4u ? db_hi_as[0] : 1'bz; assign db_hi_as[7] = reg_sw_4d_hi ? gdfx_temp1[7] : 1'bz; assign db_hi_as[6] = reg_sw_4d_hi ? gdfx_temp1[6] : 1'bz; assign db_hi_as[5] = reg_sw_4d_hi ? gdfx_temp1[5] : 1'bz; assign db_hi_as[4] = reg_sw_4d_hi ? gdfx_temp1[4] : 1'bz; assign db_hi_as[3] = reg_sw_4d_hi ? gdfx_temp1[3] : 1'bz; assign db_hi_as[2] = reg_sw_4d_hi ? gdfx_temp1[2] : 1'bz; assign db_hi_as[1] = reg_sw_4d_hi ? gdfx_temp1[1] : 1'bz; assign db_hi_as[0] = reg_sw_4d_hi ? gdfx_temp1[0] : 1'bz; assign db_lo_ds[7] = ctl_reg_out_lo ? gdfx_temp0[7] : 1'bz; assign db_lo_ds[6] = ctl_reg_out_lo ? gdfx_temp0[6] : 1'bz; assign db_lo_ds[5] = ctl_reg_out_lo ? gdfx_temp0[5] : 1'bz; assign db_lo_ds[4] = ctl_reg_out_lo ? gdfx_temp0[4] : 1'bz; assign db_lo_ds[3] = ctl_reg_out_lo ? gdfx_temp0[3] : 1'bz; assign db_lo_ds[2] = ctl_reg_out_lo ? gdfx_temp0[2] : 1'bz; assign db_lo_ds[1] = ctl_reg_out_lo ? gdfx_temp0[1] : 1'bz; assign db_lo_ds[0] = ctl_reg_out_lo ? gdfx_temp0[0] : 1'bz; assign gdfx_temp0[7] = ctl_reg_in_lo ? db_lo_ds[7] : 1'bz; assign gdfx_temp0[6] = ctl_reg_in_lo ? db_lo_ds[6] : 1'bz; assign gdfx_temp0[5] = ctl_reg_in_lo ? db_lo_ds[5] : 1'bz; assign gdfx_temp0[4] = ctl_reg_in_lo ? db_lo_ds[4] : 1'bz; assign gdfx_temp0[3] = ctl_reg_in_lo ? db_lo_ds[3] : 1'bz; assign gdfx_temp0[2] = ctl_reg_in_lo ? db_lo_ds[2] : 1'bz; assign gdfx_temp0[1] = ctl_reg_in_lo ? db_lo_ds[1] : 1'bz; assign gdfx_temp0[0] = ctl_reg_in_lo ? db_lo_ds[0] : 1'bz; assign db_hi_ds[7] = ctl_reg_out_hi ? gdfx_temp1[7] : 1'bz; assign db_hi_ds[6] = ctl_reg_out_hi ? gdfx_temp1[6] : 1'bz; assign db_hi_ds[5] = ctl_reg_out_hi ? gdfx_temp1[5] : 1'bz; assign db_hi_ds[4] = ctl_reg_out_hi ? gdfx_temp1[4] : 1'bz; assign db_hi_ds[3] = ctl_reg_out_hi ? gdfx_temp1[3] : 1'bz; assign db_hi_ds[2] = ctl_reg_out_hi ? gdfx_temp1[2] : 1'bz; assign db_hi_ds[1] = ctl_reg_out_hi ? gdfx_temp1[1] : 1'bz; assign db_hi_ds[0] = ctl_reg_out_hi ? gdfx_temp1[0] : 1'bz; assign gdfx_temp1[7] = ctl_reg_in_hi ? db_hi_ds[7] : 1'bz; assign gdfx_temp1[6] = ctl_reg_in_hi ? db_hi_ds[6] : 1'bz; assign gdfx_temp1[5] = ctl_reg_in_hi ? db_hi_ds[5] : 1'bz; assign gdfx_temp1[4] = ctl_reg_in_hi ? db_hi_ds[4] : 1'bz; assign gdfx_temp1[3] = ctl_reg_in_hi ? db_hi_ds[3] : 1'bz; assign gdfx_temp1[2] = ctl_reg_in_hi ? db_hi_ds[2] : 1'bz; assign gdfx_temp1[1] = ctl_reg_in_hi ? db_hi_ds[1] : 1'bz; assign gdfx_temp1[0] = ctl_reg_in_hi ? db_hi_ds[0] : 1'bz; endmodule ================================================ FILE: cpu/registers/reg_latch.bdf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "graphic" (version "1.4")) (pin (input) (rect 24 144 200 160) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "we" (rect 9 0 21 12)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) (line (pt 121 8)(pt 176 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) ) (pin (input) (rect 24 32 200 48) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "oe" (rect 9 0 20 12)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) (line (pt 121 8)(pt 176 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) ) (pin (input) (rect 24 128 200 144) (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) (text "clk" (rect 9 0 23 12)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) (line (pt 121 8)(pt 176 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) ) (pin (bidir) (rect 560 112 736 128) (text "BIDIR" (rect 1 0 25 10)(font "Arial" (font_size 6))) (text "db[7..0]" (rect 90 0 127 12)(font "Arial" )) (pt 0 8) (drawing (line (pt 56 4)(pt 78 4)) (line (pt 0 8)(pt 52 8)) (line (pt 56 12)(pt 78 12)) (line (pt 78 4)(pt 82 8)) (line (pt 78 12)(pt 82 8)) (line (pt 56 4)(pt 52 8)) (line (pt 52 8)(pt 56 12)) ) (text "VCC" (rect 4 7 24 17)(font "Arial" (font_size 6))) ) (symbol (rect 472 104 520 136) (text "TRI" (rect 1 0 16 10)(font "Arial" (font_size 6))) (text "inst" (rect 3 21 20 33)(font "Arial" )) (port (pt 0 16) (input) (text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible)) (text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible)) (line (pt 0 16)(pt 14 16)) ) (port (pt 24 0) (input) (text "OE" (rect 26 0 37 12)(font "Courier New" (bold))(invisible)) (text "OE" (rect 26 0 37 12)(font "Courier New" (bold))(invisible)) (line (pt 24 12)(pt 24 0)) ) (port (pt 48 16) (output) (text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible)) (text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible)) (line (pt 32 16)(pt 48 16)) ) (drawing (line (pt 14 25)(pt 14 7)) (line (pt 14 25)(pt 32 16)) (line (pt 14 7)(pt 32 16)) ) ) (symbol (rect 320 96 384 176) (text "DFFE" (rect 1 0 25 10)(font "Arial" (font_size 6))) (text "reg" (rect 3 68 18 80)(font "Arial" )) (port (pt 32 0) (input) (text "PRN" (rect 24 13 41 25)(font "Courier New" (bold))) (text "PRN" (rect 24 11 41 23)(font "Courier New" (bold))) (line (pt 32 4)(pt 32 0)) ) (port (pt 32 80) (input) (text "CLRN" (rect 21 59 44 71)(font "Courier New" (bold))) (text "CLRN" (rect 21 58 44 70)(font "Courier New" (bold))) (line (pt 32 80)(pt 32 76)) ) (port (pt 0 24) (input) (text "D" (rect 14 20 19 32)(font "Courier New" (bold))) (text "D" (rect 14 20 19 32)(font "Courier New" (bold))) (line (pt 0 24)(pt 12 24)) ) (port (pt 0 40) (input) (text "CLK" (rect 2 28 19 40)(font "Courier New" (bold))(invisible)) (text "CLK" (rect 2 28 19 40)(font "Courier New" (bold))(invisible)) (line (pt 0 40)(pt 12 40)) ) (port (pt 0 56) (input) (text "ENA" (rect 14 50 31 62)(font "Courier New" (bold))) (text "ENA" (rect 14 50 31 62)(font "Courier New" (bold))) (line (pt 0 56)(pt 12 56)) ) (port (pt 64 24) (output) (text "Q" (rect 44 20 49 32)(font "Courier New" (bold))) (text "Q" (rect 44 20 49 32)(font "Courier New" (bold))) (line (pt 53 24)(pt 64 24)) ) (drawing (line (pt 12 68)(pt 52 68)) (line (pt 12 12)(pt 52 12)) (line (pt 52 68)(pt 52 12)) (line (pt 12 68)(pt 12 12)) (line (pt 12 34)(pt 19 41)) (line (pt 18 41)(pt 12 47)) (circle (rect 28 4 36 12)) (circle (rect 28 68 36 76)) ) ) (connector (pt 536 120) (pt 536 72) (bus) ) (connector (pt 496 104) (pt 496 40) ) (connector (pt 200 40) (pt 496 40) ) (connector (pt 520 120) (pt 536 120) (bus) ) (connector (pt 536 120) (pt 560 120) (bus) ) (connector (pt 248 72) (pt 536 72) (bus) ) (connector (pt 248 72) (pt 248 120) (bus) ) (connector (pt 248 120) (pt 320 120) (bus) ) (connector (pt 200 152) (pt 320 152) ) (connector (text "latch[7..0]" (rect 402 104 451 116)(font "Arial" )) (pt 384 120) (pt 472 120) (bus) ) (connector (pt 200 136) (pt 320 136) ) (junction (pt 536 120)) (text "Repeated 8 times to form a byte register" (rect 472 160 699 174)(font "Arial" (font_size 8))) (title_block (rect 24 208 281 260) (name "title-custom-small") (section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "reg_latch" (rect 43 2 106 17)(font "Arial" (font_size 9)(bold)))(border)) (section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border)) (section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "May 17, 2014" (rect 56 3 132 17)(font "Arial" (font_size 8)))(border)) (section (rect 192 35 256 51)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.1" (rect 43 3 60 17)(font "Arial" (font_size 8)))(border)) (drawing ) ) ================================================ FILE: cpu/registers/reg_latch.bsf ================================================ /* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ (header "symbol" (version "1.2")) (symbol (rect 64 64 184 160) (text "reg_latch" (rect 5 0 58 14)(font "Arial" (font_size 8))) (text "inst" (rect 8 80 25 92)(font "Arial" )) (port (pt 0 32) (input) (text "oe" (rect 0 0 14 14)(font "Arial" (font_size 8))) (text "oe" (rect 21 27 35 41)(font "Arial" (font_size 8))) (line (pt 0 32)(pt 16 32)) ) (port (pt 0 48) (input) (text "we" (rect 0 0 18 14)(font "Arial" (font_size 8))) (text "we" (rect 21 43 39 57)(font "Arial" (font_size 8))) (line (pt 0 48)(pt 16 48)) ) (port (pt 120 64) (input) (text "clk" (rect 0 0 15 14)(font "Arial" (font_size 8))) (text "clk" (rect 73 56 88 70)(font "Arial" (font_size 8))) (line (pt 104 64)(pt 120 64)) ) (port (pt 120 32) (bidir) (text "db[7..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) (text "db[7..0]" (rect 57 27 99 41)(font "Arial" (font_size 8))) (line (pt 120 32)(pt 104 32)(line_width 3)) ) (drawing (rectangle (rect 16 16 104 80)) ) (fill (color 85 255 127)) ) ================================================ FILE: cpu/registers/reg_latch.v ================================================ // Copyright (C) 1991-2013 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // PROGRAM "Quartus II 64-Bit" // VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" // CREATED "Fri Nov 07 10:28:37 2014" module reg_latch( we, oe, clk, db ); input wire we; input wire oe; input wire clk; inout wire [7:0] db; reg [7:0] latch; assign db[7] = oe ? latch[7] : 1'bz; assign db[6] = oe ? latch[6] : 1'bz; assign db[5] = oe ? latch[5] : 1'bz; assign db[4] = oe ? latch[4] : 1'bz; assign db[3] = oe ? latch[3] : 1'bz; assign db[2] = oe ? latch[2] : 1'bz; assign db[1] = oe ? latch[1] : 1'bz; assign db[0] = oe ? latch[0] : 1'bz; always@(posedge clk) begin if (we) begin latch[7:0] <= db[7:0]; end end endmodule ================================================ FILE: cpu/registers/simulation/modelsim/r ================================================ restart -f ; run -all ================================================ FILE: cpu/registers/simulation/modelsim/test_registers.mpf ================================================ ; Copyright 1991-2009 Mentor Graphics Corporation ; ; All Rights Reserved. ; ; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF ; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. ; [Library] std = $MODEL_TECH/../std ieee = $MODEL_TECH/../ieee verilog = $MODEL_TECH/../verilog vital2000 = $MODEL_TECH/../vital2000 std_developerskit = $MODEL_TECH/../std_developerskit synopsys = $MODEL_TECH/../synopsys modelsim_lib = $MODEL_TECH/../modelsim_lib sv_std = $MODEL_TECH/../sv_std ; Altera Primitive libraries ; ; VHDL Section ; altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf altera = $MODEL_TECH/../altera/vhdl/altera altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim lpm = $MODEL_TECH/../altera/vhdl/220model 220model = $MODEL_TECH/../altera/vhdl/220model max = $MODEL_TECH/../altera/vhdl/max maxii = $MODEL_TECH/../altera/vhdl/maxii maxv = $MODEL_TECH/../altera/vhdl/maxv stratix = $MODEL_TECH/../altera/vhdl/stratix stratixii = $MODEL_TECH/../altera/vhdl/stratixii stratixiigx = $MODEL_TECH/../altera/vhdl/stratixiigx hardcopyii = $MODEL_TECH/../altera/vhdl/hardcopyii hardcopyiii = $MODEL_TECH/../altera/vhdl/hardcopyiii hardcopyiv = $MODEL_TECH/../altera/vhdl/hardcopyiv cyclone = $MODEL_TECH/../altera/vhdl/cyclone cycloneii = $MODEL_TECH/../altera/vhdl/cycloneii cycloneiii = $MODEL_TECH/../altera/vhdl/cycloneiii cycloneiiils = $MODEL_TECH/../altera/vhdl/cycloneiiils sgate = $MODEL_TECH/../altera/vhdl/sgate stratixgx = $MODEL_TECH/../altera/vhdl/stratixgx altgxb = $MODEL_TECH/../altera/vhdl/altgxb stratixgx_gxb = $MODEL_TECH/../altera/vhdl/stratixgx_gxb stratixiigx_hssi = $MODEL_TECH/../altera/vhdl/stratixiigx_hssi arriagx_hssi = $MODEL_TECH/../altera/vhdl/arriagx_hssi arriaii = $MODEL_TECH/../altera/vhdl/arriaii arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip arriagx = $MODEL_TECH/../altera/vhdl/arriagx altgxb_lib = $MODEL_TECH/../altera/vhdl/altgxb stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive hardcopyiv_hssi = $MODEL_TECH/../altera/vhdl/hardcopyiv_hssi hardcopyiv_pcie_hip = $MODEL_TECH/../altera/vhdl/hardcopyiv_pcie_hip stratixv = $MODEL_TECH/../altera/vhdl/stratixv stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip arriav = $MODEL_TECH/../altera/vhdl/arriav cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev ; ; Verilog Section ; altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf altera_ver = $MODEL_TECH/../altera/verilog/altera altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim lpm_ver = $MODEL_TECH/../altera/verilog/220model 220model_ver = $MODEL_TECH/../altera/verilog/220model max_ver = $MODEL_TECH/../altera/verilog/max maxii_ver = $MODEL_TECH/../altera/verilog/maxii maxv_ver = $MODEL_TECH/../altera/verilog/maxv stratix_ver = $MODEL_TECH/../altera/verilog/stratix stratixii_ver = $MODEL_TECH/../altera/verilog/stratixii stratixiigx_ver = $MODEL_TECH/../altera/verilog/stratixiigx arriagx_ver = $MODEL_TECH/../altera/verilog/arriagx hardcopyii_ver = $MODEL_TECH/../altera/verilog/hardcopyii hardcopyiii_ver = $MODEL_TECH/../altera/verilog/hardcopyiii hardcopyiv_ver = $MODEL_TECH/../altera/verilog/hardcopyiv cyclone_ver = $MODEL_TECH/../altera/verilog/cyclone cycloneii_ver = $MODEL_TECH/../altera/verilog/cycloneii cycloneiii_ver = $MODEL_TECH/../altera/verilog/cycloneiii cycloneiiils_ver = $MODEL_TECH/../altera/verilog/cycloneiiils sgate_ver = $MODEL_TECH/../altera/verilog/sgate stratixgx_ver = $MODEL_TECH/../altera/verilog/stratixgx altgxb_ver = $MODEL_TECH/../altera/verilog/altgxb stratixgx_gxb_ver = $MODEL_TECH/../altera/verilog/stratixgx_gxb stratixiigx_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiigx_hssi arriagx_hssi_ver = $MODEL_TECH/../altera/verilog/arriagx_hssi arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip stratixiii_ver = $MODEL_TECH/../altera/verilog/stratixiii stratixiii = $MODEL_TECH/../altera/vhdl/stratixiii stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip arriav_ver = $MODEL_TECH/../altera/verilog/arriav arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive hardcopyiv_hssi_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_hssi hardcopyiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_pcie_hip work = work [vcom] ; VHDL93 variable selects language version as the default. ; Default is VHDL-2002. ; Value of 0 or 1987 for VHDL-1987. ; Value of 1 or 1993 for VHDL-1993. ; Default or value of 2 or 2002 for VHDL-2002. ; Default or value of 3 or 2008 for VHDL-2008. VHDL93 = 2002 ; Show source line containing error. Default is off. ; Show_source = 1 ; Turn off unbound-component warnings. Default is on. ; Show_Warning1 = 0 ; Turn off process-without-a-wait-statement warnings. Default is on. ; Show_Warning2 = 0 ; Turn off null-range warnings. Default is on. ; Show_Warning3 = 0 ; Turn off no-space-in-time-literal warnings. Default is on. ; Show_Warning4 = 0 ; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. ; Show_Warning5 = 0 ; Turn off optimization for IEEE std_logic_1164 package. Default is on. ; Optimize_1164 = 0 ; Turn on resolving of ambiguous function overloading in favor of the ; "explicit" function declaration (not the one automatically created by ; the compiler for each type declaration). Default is off. ; The .ini file has Explicit enabled so that std_logic_signed/unsigned ; will match the behavior of synthesis tools. Explicit = 1 ; Turn off acceleration of the VITAL packages. Default is to accelerate. ; NoVital = 1 ; Turn off VITAL compliance checking. Default is checking on. ; NoVitalCheck = 1 ; Ignore VITAL compliance checking errors. Default is to not ignore. ; IgnoreVitalErrors = 1 ; Turn off VITAL compliance checking warnings. Default is to show warnings. ; Show_VitalChecksWarnings = 0 ; Keep silent about case statement static warnings. ; Default is to give a warning. ; NoCaseStaticError = 1 ; Keep silent about warnings caused by aggregates that are not locally static. ; Default is to give a warning. ; NoOthersStaticError = 1 ; Turn off inclusion of debugging info within design units. ; Default is to include debugging info. ; NoDebug = 1 ; Turn off "Loading..." messages. Default is messages on. ; Quiet = 1 ; Turn on some limited synthesis rule compliance checking. Checks only: ; -- signals used (read) by a process must be in the sensitivity list ; CheckSynthesis = 1 ; Activate optimizations on expressions that do not involve signals, ; waits, or function/procedure/task invocations. Default is off. ; ScalarOpts = 1 ; Require the user to specify a configuration for all bindings, ; and do not generate a compile time default binding for the ; component. This will result in an elaboration error of ; 'component not bound' if the user fails to do so. Avoids the rare ; issue of a false dependency upon the unused default binding. ; RequireConfigForAllDefaultBinding = 1 ; Inhibit range checking on subscripts of arrays. Range checking on ; scalars defined with subtypes is inhibited by default. ; NoIndexCheck = 1 ; Inhibit range checks on all (implicit and explicit) assignments to ; scalar objects defined with subtypes. ; NoRangeCheck = 1 [vlog] ; Turn off inclusion of debugging info within design units. ; Default is to include debugging info. ; NoDebug = 1 ; Turn off "loading..." messages. Default is messages on. ; Quiet = 1 ; Turn on Verilog hazard checking (order-dependent accessing of global vars). ; Default is off. ; Hazard = 1 ; Turn on converting regular Verilog identifiers to uppercase. Allows case ; insensitivity for module names. Default is no conversion. ; UpCase = 1 ; Turn on incremental compilation of modules. Default is off. ; Incremental = 1 ; Turns on lint-style checking. ; Show_Lint = 1 [vsim] ; Simulator resolution ; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. Resolution = ps ; User time unit for run commands ; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the ; unit specified for Resolution. For example, if Resolution is 100ps, ; then UserTimeUnit defaults to ps. ; Should generally be set to default. UserTimeUnit = default ; Default run length RunLength = 100 ns ; Maximum iterations that can be run without advancing simulation time IterationLimit = 5000 ; Directive to license manager: ; vhdl Immediately reserve a VHDL license ; vlog Immediately reserve a Verilog license ; plus Immediately reserve a VHDL and Verilog license ; nomgc Do not look for Mentor Graphics Licenses ; nomti Do not look for Model Technology Licenses ; noqueue Do not wait in the license queue when a license isn't available ; viewsim Try for viewer license but accept simulator license(s) instead ; of queuing for viewer license ; License = plus ; Stop the simulator after a VHDL/Verilog assertion message ; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal BreakOnAssertion = 4 ; Assertion Message Format ; %S - Severity Level ; %R - Report Message ; %T - Time of assertion ; %D - Delta ; %I - Instance or Region pathname (if available) ; %% - print '%' character ; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" ; Assertion File - alternate file for storing VHDL/Verilog assertion messages ; AssertFile = assert.log ; Default radix for all windows and commands... ; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned DefaultRadix = symbolic ; VSIM Startup command ; Startup = do startup.do ; File for saving command transcript TranscriptFile = transcript ; File for saving command history ; CommandHistory = cmdhist.log ; Specify whether paths in simulator commands should be described ; in VHDL or Verilog format. ; For VHDL, PathSeparator = / ; For Verilog, PathSeparator = . ; Must not be the same character as DatasetSeparator. PathSeparator = / ; Specify the dataset separator for fully rooted contexts. ; The default is ':'. For example, sim:/top ; Must not be the same character as PathSeparator. DatasetSeparator = : ; Disable VHDL assertion messages ; IgnoreNote = 1 ; IgnoreWarning = 1 ; IgnoreError = 1 ; IgnoreFailure = 1 ; Default force kind. May be freeze, drive, deposit, or default ; or in other terms, fixed, wired, or charged. ; A value of "default" will use the signal kind to determine the ; force kind, drive for resolved signals, freeze for unresolved signals ; DefaultForceKind = freeze ; If zero, open files when elaborated; otherwise, open files on ; first read or write. Default is 0. ; DelayFileOpen = 1 ; Control VHDL files opened for write. ; 0 = Buffered, 1 = Unbuffered UnbufferedOutput = 0 ; Control the number of VHDL files open concurrently. ; This number should always be less than the current ulimit ; setting for max file descriptors. ; 0 = unlimited ConcurrentFileLimit = 40 ; Control the number of hierarchical regions displayed as ; part of a signal name shown in the Wave window. ; A value of zero tells VSIM to display the full name. ; The default is 0. ; WaveSignalNameWidth = 0 ; Turn off warnings from the std_logic_arith, std_logic_unsigned ; and std_logic_signed packages. ; StdArithNoWarnings = 1 ; Turn off warnings from the IEEE numeric_std and numeric_bit packages. ; NumericStdNoWarnings = 1 ; Control the format of the (VHDL) FOR generate statement label ; for each iteration. Do not quote it. ; The format string here must contain the conversion codes %s and %d, ; in that order, and no other conversion codes. The %s represents ; the generate_label; the %d represents the generate parameter value ; at a particular generate iteration (this is the position number if ; the generate parameter is of an enumeration type). Embedded whitespace ; is allowed (but discouraged); leading and trailing whitespace is ignored. ; Application of the format must result in a unique scope name over all ; such names in the design so that name lookup can function properly. ; GenerateFormat = %s__%d ; Specify whether checkpoint files should be compressed. ; The default is 1 (compressed). ; CheckpointCompressMode = 0 ; List of dynamically loaded objects for Verilog PLI applications ; Veriuser = veriuser.sl ; Specify default options for the restart command. Options can be one ; or more of: -force -nobreakpoint -nolist -nolog -nowave ; DefaultRestartOptions = -force ; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs ; (> 500 megabyte memory footprint). Default is disabled. ; Specify number of megabytes to lock. ; LockedMemory = 1000 ; Turn on (1) or off (0) WLF file compression. ; The default is 1 (compress WLF file). ; WLFCompress = 0 ; Specify whether to save all design hierarchy (1) in the WLF file ; or only regions containing logged signals (0). ; The default is 0 (save only regions with logged signals). ; WLFSaveAllRegions = 1 ; WLF file time limit. Limit WLF file by time, as closely as possible, ; to the specified amount of simulation time. When the limit is exceeded ; the earliest times get truncated from the file. ; If both time and size limits are specified the most restrictive is used. ; UserTimeUnits are used if time units are not specified. ; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} ; WLFTimeLimit = 0 ; WLF file size limit. Limit WLF file size, as closely as possible, ; to the specified number of megabytes. If both time and size limits ; are specified then the most restrictive is used. ; The default is 0 (no limit). ; WLFSizeLimit = 1000 ; Specify whether or not a WLF file should be deleted when the ; simulation ends. A value of 1 will cause the WLF file to be deleted. ; The default is 0 (do not delete WLF file when simulation ends). ; WLFDeleteOnQuit = 1 ; Automatic SDF compilation ; Disables automatic compilation of SDF files in flows that support it. ; Default is on, uncomment to turn off. ; NoAutoSDFCompile = 1 DelayFileOpen = 1 [lmc] [msg_system] ; Change a message severity or suppress a message. ; The format is: = [,...] ; Examples: ; note = 3009 ; warning = 3033 ; error = 3010,3016 ; fatal = 3016,3033 ; suppress = 3009,3016,3043 ; The command verror can be used to get the complete ; description of a message. ; Control transcripting of elaboration/runtime messages. ; The default is to have messages appear in the transcript and ; recorded in the wlf file (messages that are recorded in the ; wlf file can be viewed in the MsgViewer). The other settings ; are to send messages only to the transcript or only to the ; wlf file. The valid values are ; both {default} ; tran {transcript only} ; wlf {wlf file only} ; msgmode = both [Project] ; Warning -- Do not edit the project properties directly. ; Property names are dynamic in nature and property ; values have special syntax. Changing property data directly ; can result in a corrupt MPF file. All project properties ; can be modified through project window dialogs. Project_Version = 6 Project_DefaultLib = work Project_SortMethod = unused Project_Files_Count = 6 Project_File_0 = $ROOT/cpu/registers/reg_control.v Project_File_P_0 = compile_order 0 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 Project_File_1 = $ROOT/cpu/registers/reg_file.v Project_File_P_1 = compile_order 1 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 Project_File_2 = $ROOT/cpu/registers/reg_latch.v Project_File_P_2 = compile_order 2 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 Project_File_3 = $ROOT/cpu/registers/test_latch.sv Project_File_P_3 = compile_order 4 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 Project_File_4 = $ROOT/cpu/registers/test_regfile.sv Project_File_P_4 = compile_order 5 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 Project_File_5 = $ROOT/cpu/registers/test_registers.sv Project_File_P_5 = compile_order 3 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder {Top Level} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1 Project_Sim_Count = 3 Project_Sim_0 = Test registers Project_Sim_P_0 = timing default -sdfnoerror 0 -t default -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder {Top Level} +pulse_e {} additional_dus work.test_registers -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {} Project_Sim_1 = Test latch Project_Sim_P_1 = timing default -t default -sdfnoerror 0 -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder {Top Level} +pulse_e {} additional_dus work.test_latch -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {} Project_Sim_2 = Test regfile Project_Sim_P_2 = timing default -t default -sdfnoerror 0 -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder {Top Level} +pulse_e {} additional_dus work.test_regfile -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 0 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {} Project_Folder_Count = 0 Echo_Compile_Output = 0 Save_Compile_Report = 1 Project_Opt_Count = 0 ForceSoftPaths = 1 ProjectStatusDelay = 5000 VERILOG_DoubleClick = Edit VERILOG_CustomDoubleClick = SYSTEMVERILOG_DoubleClick = Edit SYSTEMVERILOG_CustomDoubleClick = VHDL_DoubleClick = Edit VHDL_CustomDoubleClick = PSL_DoubleClick = Edit PSL_CustomDoubleClick = TEXT_DoubleClick = Edit TEXT_CustomDoubleClick = SYSTEMC_DoubleClick = Edit SYSTEMC_CustomDoubleClick = TCL_DoubleClick = Edit TCL_CustomDoubleClick = MACRO_DoubleClick = Edit MACRO_CustomDoubleClick = VCD_DoubleClick = Edit VCD_CustomDoubleClick = SDF_DoubleClick = Edit SDF_CustomDoubleClick = XML_DoubleClick = Edit XML_CustomDoubleClick = LOGFILE_DoubleClick = Edit LOGFILE_CustomDoubleClick = UCDB_DoubleClick = Edit UCDB_CustomDoubleClick = UPF_DoubleClick = Edit UPF_CustomDoubleClick = PCF_DoubleClick = Edit PCF_CustomDoubleClick = PROJECT_DoubleClick = Edit PROJECT_CustomDoubleClick = VRM_DoubleClick = Edit VRM_CustomDoubleClick = DEBUGDATABASE_DoubleClick = Edit DEBUGDATABASE_CustomDoubleClick = DEBUGARCHIVE_DoubleClick = Edit DEBUGARCHIVE_CustomDoubleClick = Project_Major_Version = 10 Project_Minor_Version = 1 ================================================ FILE: cpu/registers/simulation/modelsim/wave_latch.do ================================================ onerror {resume} quietly WaveActivateNextPane {} 0 add wave -noupdate /test_latch/clk add wave -noupdate -radix hexadecimal /test_latch/db add wave -noupdate -radix hexadecimal /test_latch/db_sig add wave -noupdate /test_latch/oe_sig add wave -noupdate /test_latch/we_sig add wave -noupdate -radix hexadecimal /test_latch/reg_latch_inst/latch TreeUpdate [SetDefaultTree] WaveRestoreCursors {{Cursor 1} {2000 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 123 configure wave -valuecolwidth 72 configure wave -justifyvalue right configure wave -signalnamewidth 1 configure wave -snapdistance 10 configure wave -datasetprefix 0 configure wave -rowmargin 4 configure wave -childrowmargin 2 configure wave -gridoffset 0 configure wave -gridperiod 1 configure wave -griddelta 40 configure wave -timeline 1 configure wave -timelineunits us update WaveRestoreZoom {0 ns} {12600 ns} ================================================ FILE: cpu/registers/simulation/modelsim/wave_regfile.do ================================================ onerror {resume} quietly WaveActivateNextPane {} 0 add wave -noupdate /test_regfile/clk add wave -noupdate -radix hexadecimal /test_regfile/db_lo_ds add wave -noupdate -radix hexadecimal /test_regfile/db_lo_ds_sig add wave -noupdate -radix hexadecimal /test_regfile/db_hi_ds add wave -noupdate -radix hexadecimal /test_regfile/db_hi_ds_sig add wave -noupdate /test_regfile/reg_sel_af_sig add wave -noupdate /test_regfile/reg_sel_af2_sig add wave -noupdate /test_regfile/reg_sel_bc_sig add wave -noupdate /test_regfile/reg_sel_bc2_sig add wave -noupdate /test_regfile/reg_sel_de_sig add wave -noupdate /test_regfile/reg_sel_de2_sig add wave -noupdate /test_regfile/reg_sel_hl_sig add wave -noupdate /test_regfile/reg_sel_hl2_sig add wave -noupdate /test_regfile/reg_sel_ix_sig add wave -noupdate /test_regfile/reg_sel_iy_sig add wave -noupdate /test_regfile/reg_sel_wz_sig add wave -noupdate /test_regfile/reg_sel_sp_sig add wave -noupdate /test_regfile/reg_sel_gp_hi_sig add wave -noupdate /test_regfile/reg_sel_gp_lo_sig add wave -noupdate /test_regfile/reg_gp_oe_sig add wave -noupdate /test_regfile/reg_sel_pc_sig add wave -noupdate /test_regfile/reg_sel_ir_sig add wave -noupdate /test_regfile/reg_sel_sys_hi_sig add wave -noupdate /test_regfile/reg_sel_sys_lo_sig add wave -noupdate /test_regfile/reg_sys_oe_sig add wave -noupdate -divider Bus add wave -noupdate -radix hexadecimal /test_regfile/reg_file_inst/db_hi_as add wave -noupdate -radix hexadecimal /test_regfile/reg_file_inst/db_hi_ds add wave -noupdate -radix hexadecimal /test_regfile/reg_file_inst/db_lo_as add wave -noupdate -radix hexadecimal /test_regfile/reg_file_inst/db_lo_ds TreeUpdate [SetDefaultTree] WaveRestoreCursors {{Cursor 1} {0 ns} 0} quietly wave cursor active 0 configure wave -namecolwidth 215 configure wave -valuecolwidth 100 configure wave -justifyvalue left configure wave -signalnamewidth 0 configure wave -snapdistance 10 configure wave -datasetprefix 0 configure wave -rowmargin 4 configure wave -childrowmargin 2 configure wave -gridoffset 0 configure wave -gridperiod 1 configure wave -griddelta 40 configure wave -timeline 1 configure wave -timelineunits ps update WaveRestoreZoom {0 ns} {10400 ns} ================================================ FILE: cpu/registers/simulation/modelsim/wave_registers.do ================================================ onerror {resume} quietly WaveActivateNextPane {} 0 add wave -noupdate /test_registers/clk add wave -noupdate -expand -group {Address Side} -itemcolor Black -radix hexadecimal -childformat {{{/test_registers/db_lo_as[7]} -radix hexadecimal} {{/test_registers/db_lo_as[6]} -radix hexadecimal} {{/test_registers/db_lo_as[5]} -radix hexadecimal} {{/test_registers/db_lo_as[4]} -radix hexadecimal} {{/test_registers/db_lo_as[3]} -radix hexadecimal} {{/test_registers/db_lo_as[2]} -radix hexadecimal} {{/test_registers/db_lo_as[1]} -radix hexadecimal} {{/test_registers/db_lo_as[0]} -radix hexadecimal}} -subitemconfig {{/test_registers/db_lo_as[7]} {-height 15 -itemcolor Black -radix hexadecimal} {/test_registers/db_lo_as[6]} {-height 15 -itemcolor Black -radix hexadecimal} {/test_registers/db_lo_as[5]} {-height 15 -itemcolor Black -radix hexadecimal} {/test_registers/db_lo_as[4]} {-height 15 -itemcolor Black -radix hexadecimal} {/test_registers/db_lo_as[3]} {-height 15 -itemcolor Black -radix hexadecimal} {/test_registers/db_lo_as[2]} {-height 15 -itemcolor Black -radix hexadecimal} {/test_registers/db_lo_as[1]} {-height 15 -itemcolor Black -radix hexadecimal} {/test_registers/db_lo_as[0]} {-height 15 -itemcolor Black -radix hexadecimal}} /test_registers/db_lo_as add wave -noupdate -expand -group {Address Side} -itemcolor Black -radix hexadecimal /test_registers/db_lo_as_sig add wave -noupdate -expand -group {Address Side} -itemcolor Black -radix hexadecimal /test_registers/db_hi_as add wave -noupdate -expand -group {Address Side} -itemcolor Black -radix hexadecimal /test_registers/db_hi_as_sig add wave -noupdate -expand -group {Data Side} -itemcolor Black -radix hexadecimal /test_registers/db_lo_ds add wave -noupdate -expand -group {Data Side} -itemcolor Black -radix hexadecimal /test_registers/db_lo_ds_sig add wave -noupdate -expand -group {Data Side} -itemcolor Black -radix hexadecimal /test_registers/db_hi_ds add wave -noupdate -expand -group {Data Side} -itemcolor Black -radix hexadecimal /test_registers/db_hi_ds_sig add wave -noupdate -divider Control add wave -noupdate -itemcolor Violet /test_registers/ctl_sw_4u_sig add wave -noupdate -itemcolor Violet /test_registers/ctl_sw_4d_sig add wave -noupdate -itemcolor Violet /test_registers/reg_file_inst/reg_sw_4d_lo add wave -noupdate -itemcolor Violet /test_registers/reg_file_inst/reg_sw_4d_hi add wave -noupdate /test_registers/ctl_reg_in_hi_sig add wave -noupdate /test_registers/ctl_reg_in_lo_sig add wave -noupdate /test_registers/ctl_reg_out_hi_sig add wave -noupdate /test_registers/ctl_reg_out_lo_sig add wave -noupdate /test_registers/ctl_reg_exx_sig add wave -noupdate /test_registers/ctl_reg_ex_af_sig add wave -noupdate /test_registers/ctl_reg_ex_de_hl_sig add wave -noupdate /test_registers/ctl_reg_use_sp_sig add wave -noupdate /test_registers/ctl_reg_sel_wz_sig add wave -noupdate /test_registers/ctl_reg_sel_pc_sig add wave -noupdate /test_registers/ctl_reg_sel_ir_sig add wave -noupdate -color Coral -itemcolor Gold /test_registers/reg_sel_bc_sig add wave -noupdate -color Coral -itemcolor Gold /test_registers/reg_sel_bc2_sig add wave -noupdate -color Coral -itemcolor Gold /test_registers/reg_sel_de_sig add wave -noupdate -color Coral -itemcolor Gold /test_registers/reg_sel_de2_sig add wave -noupdate -color Coral -itemcolor Gold /test_registers/reg_sel_hl_sig add wave -noupdate -color Coral -itemcolor Gold /test_registers/reg_sel_hl2_sig add wave -noupdate -color Coral -itemcolor Gold /test_registers/reg_sel_af_sig add wave -noupdate -color Coral -itemcolor Gold /test_registers/reg_sel_af2_sig add wave -noupdate -color Coral -itemcolor Gold /test_registers/reg_sel_ix_sig add wave -noupdate -color Coral -itemcolor Gold /test_registers/reg_sel_iy_sig add wave -noupdate -color Coral -itemcolor Gold /test_registers/reg_sel_wz_sig add wave -noupdate -color Coral -itemcolor Gold /test_registers/reg_sel_pc_sig add wave -noupdate -color Coral -itemcolor Gold /test_registers/reg_sel_ir_sig add wave -noupdate -color Coral -itemcolor Gold /test_registers/reg_sel_gp_hi_sig add wave -noupdate -color Coral -itemcolor Gold /test_registers/reg_sel_gp_lo_sig add wave -noupdate -color Coral -itemcolor Gold /test_registers/reg_sel_sys_hi_sig add wave -noupdate -color Coral -itemcolor Gold /test_registers/reg_sel_sys_lo_sig TreeUpdate [SetDefaultTree] WaveRestoreCursors {{Cursor 1} {1200 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 260 configure wave -valuecolwidth 39 configure wave -justifyvalue left configure wave -signalnamewidth 0 configure wave -snapdistance 10 configure wave -datasetprefix 0 configure wave -rowmargin 4 configure wave -childrowmargin 2 configure wave -gridoffset 0 configure wave -gridperiod 1 configure wave -griddelta 40 configure wave -timeline 1 configure wave -timelineunits ps update WaveRestoreZoom {0 ns} {7800 ns} ================================================ FILE: cpu/registers/test_latch.sv ================================================ //============================================================== // Test 8-bit latch block //============================================================== `timescale 100 ns/ 100 ns module test_latch; // ----------------- CLOCKS AND RESET ----------------- // Define one full T-clock cycle delay `define T #2 bit clk = 1; initial repeat (30) #1 clk = ~clk; // ---------------------------------------------------- // Bi-directional bus with 3-state reg [7:0] db; // Drive it using these wires wire [7:0] db_sig; // Read it using these wires reg oe_sig; reg we_sig; // ----------------- TEST ------------------- `define CHECK(arg) \ assert(db_sig===arg); initial begin oe_sig = 0; we_sig = 0; // Test bidirectional data bus and leave it at Z `T db = 8'hAA; `T db = 'z; `T `CHECK(8'hz); // Write a byte into the latch `T db = 8'h55; `T we_sig = 1; `T we_sig = 0; `T db = 'z; // Read latch `T db = 'z; `T oe_sig = 1; `T `CHECK(8'h55); `T oe_sig = 0; `T $display("End of test"); end // Drive a 3-state bidirectional bus with this statement assign db_sig = db; //-------------------------------------------------------------- // Instantiate register latch //-------------------------------------------------------------- reg_latch reg_latch_inst ( .clk(clk), .oe(oe_sig) , // input oe_sig .we(we_sig) , // input we_sig .db(db_sig[7:0]) // inout [7:0] db_sig ); endmodule ================================================ FILE: cpu/registers/test_regfile.sv ================================================ //============================================================== // Test register file block (without reg. control unit) //============================================================== `timescale 100 ns/ 100 ns module test_regfile; // ----------------- CLOCKS AND RESET ----------------- // Define one full T-clock cycle delay `define T #2 bit clk = 1; initial repeat (10) #1 clk = ~clk; // ----------------- BUSES ----------------- // We have 4 Bi-directional buses that can also be 3-stated: // On the address-side, there are high and low 8-bit buses reg [7:0] db_lo_as; // Drive it using this bus wire [7:0] db_lo_as_sig; // Read it using this bus reg [7:0] db_hi_as; // Drive it using this bus wire [7:0] db_hi_as_sig; // Read it using this bus // ----------------- BUSES ----------------- // On the data-side, there are high and low 8-bit buses reg [7:0] db_lo_ds; // Drive it using this bus wire [7:0] db_lo_ds_sig; // Read it using this bus reg [7:0] db_hi_ds; // Drive it using this bus wire [7:0] db_hi_ds_sig; // Read it using this bus // ----------------- CONTROL ----------------- reg ctl_sw_4u_sig; // Bus switch #4 upstream gate reg reg_sw_4d_lo_sig; // Bus switch #4 downstream gate low byte lane reg reg_sw_4d_hi_sig; // Bus switch #4 downstream gate high byte lane // ----------------- GP REGS ----------------- reg reg_sel_af_sig; // Select AF register reg reg_sel_af2_sig; // ... reg reg_sel_bc_sig; reg reg_sel_bc2_sig; reg reg_sel_de_sig; reg reg_sel_de2_sig; reg reg_sel_hl_sig; reg reg_sel_hl2_sig; reg reg_sel_ix_sig; reg reg_sel_iy_sig; reg reg_sel_wz_sig; reg reg_sel_sp_sig; reg reg_sel_gp_hi_sig; // Select high byte of a GP register reg reg_sel_gp_lo_sig; // Select low byte of a GP register reg reg_gp_oe_sig; // Write selected GP register to the data bus // ----------------- SYSTEM REGS ----------------- reg reg_sel_pc_sig; // Select PC register reg reg_sel_ir_sig; // Select IR register reg reg_sel_sys_hi_sig; // Select high byte of a system register reg reg_sel_sys_lo_sig; // Select low byte of a system register reg reg_sys_oe_sig; // Write selected system register to the data bus // ----------------- TEST ------------------- `define CHECK(arg) \ assert(db_sig===arg); initial begin reg_sw_4d_lo_sig = 0; reg_sw_4d_hi_sig = 0; ctl_sw_4u_sig = 0; reg_sel_af_sig = 0; // Select AF register reg_sel_af2_sig = 0; // ... reg_sel_bc_sig = 0; reg_sel_bc2_sig = 0; reg_sel_de_sig = 0; reg_sel_de2_sig = 0; reg_sel_hl_sig = 0; reg_sel_hl2_sig = 0; reg_sel_ix_sig = 0; reg_sel_iy_sig = 0; reg_sel_wz_sig = 0; reg_sel_sp_sig = 0; reg_sel_gp_hi_sig = 0; // Select high byte of a GP register reg_sel_gp_lo_sig = 0; // Select low byte of a GP register reg_gp_oe_sig = 0; // Write selected GP register to the data bus reg_sel_pc_sig = 0; // Select PC register reg_sel_ir_sig = 0; // Select IR register reg_sel_sys_hi_sig = 0; // Select high byte of a system register reg_sel_sys_lo_sig = 0; // Select low byte of a system register reg_sys_oe_sig = 0; // Write selected system register to the data bus // Test bidirectional data buses and leave them at Z `T db_lo_as = 8'hAA; db_hi_as = 8'h55; db_lo_ds = 8'hCA; db_hi_ds = 8'hFE; `T db_lo_as = 'z; db_hi_as = 'z; db_lo_ds = 'z; db_hi_ds = 'z; // Store a value in a GP register and read it back `T db_lo_ds = 8'h12; db_hi_ds = 8'h34; reg_sel_gp_hi_sig = 1; reg_sel_gp_lo_sig = 1; reg_sel_af_sig = 1; `T db_lo_ds = 'z; db_hi_ds = 'z; reg_sel_af_sig = 0; `T `T reg_sel_gp_hi_sig = 1; reg_sel_gp_lo_sig = 1; reg_sel_af_sig = 1; reg_gp_oe_sig = 1; `T `T $display("End of test"); end // Drive 3-state bidirectional buses with these statements assign db_lo_as_sig = db_lo_as; assign db_hi_as_sig = db_hi_as; assign db_lo_ds_sig = db_lo_ds; assign db_hi_ds_sig = db_hi_ds; //-------------------------------------------------------------- // Instantiate register file block //-------------------------------------------------------------- reg_file reg_file_inst ( .reg_sel_sys_lo(reg_sel_sys_lo_sig) , // input reg_sel_sys_lo_sig .reg_sel_gp_lo(reg_sel_gp_lo_sig) , // input reg_sel_gp_lo_sig .reg_sel_sys_hi(reg_sel_sys_hi_sig) , // input reg_sel_sys_hi_sig .reg_sel_gp_hi(reg_sel_gp_hi_sig) , // input reg_sel_gp_hi_sig .reg_sel_ir(reg_sel_ir_sig) , // input reg_sel_ir_sig .reg_sel_pc(reg_sel_pc_sig) , // input reg_sel_pc_sig .reg_sw_4d_lo(reg_sw_4d_lo_sig) , // input reg_sw_4d_lo_sig .reg_sw_4d_hi(reg_sw_4d_hi_sig) , // input reg_sw_4d_hi_sig .ctl_sw_4u(ctl_sw_4u_sig) , // input ctl_sw_4u_sig .reg_sel_wz(reg_sel_wz_sig) , // input reg_sel_wz_sig .reg_sel_sp(reg_sel_sp_sig) , // input reg_sel_sp_sig .reg_sel_iy(reg_sel_iy_sig) , // input reg_sel_iy_sig .reg_sel_ix(reg_sel_ix_sig) , // input reg_sel_ix_sig .reg_sel_hl2(reg_sel_hl2_sig) , // input reg_sel_hl2_sig .reg_sel_hl(reg_sel_hl_sig) , // input reg_sel_hl_sig .reg_sel_de2(reg_sel_de2_sig) , // input reg_sel_de2_sig .reg_sel_de(reg_sel_de_sig) , // input reg_sel_de_sig .reg_sel_bc2(reg_sel_bc2_sig) , // input reg_sel_bc2_sig .reg_sel_bc(reg_sel_bc_sig) , // input reg_sel_bc_sig .reg_sel_af2(reg_sel_af2_sig) , // input reg_sel_af2_sig .reg_sel_af(reg_sel_af_sig) , // input reg_sel_af_sig .reg_gp_we(reg_gp_we_sig) , // input reg_gp_we_sig .reg_sys_we_lo(reg_sys_we_lo_sig) , // input reg_sys_we_lo_sig .reg_sys_we_hi(reg_sys_we_hi_sig) , // input reg_sys_we_hi_sig .ctl_reg_in_hi(ctl_reg_in_hi_sig) , // input ctl_reg_in_hi_sig .ctl_reg_in_lo(ctl_reg_in_lo_sig) , // input ctl_reg_in_lo_sig .ctl_reg_out_lo(ctl_reg_out_lo_sig) , // input ctl_reg_out_lo_sig .ctl_reg_out_hi(ctl_reg_out_hi_sig) , // input ctl_reg_out_hi_sig .clk(clk) , // input clk_sig .db_lo_ds(db_lo_ds_sig) , // inout [7:0] db_lo_ds_sig .db_hi_ds(db_hi_ds_sig) , // inout [7:0] db_hi_ds_sig .db_lo_as(db_lo_as_sig) , // inout [7:0] db_lo_as_sig .db_hi_as(db_hi_as_sig) // inout [7:0] db_hi_as_sig ); endmodule ================================================ FILE: cpu/registers/test_registers.qpf ================================================ # -------------------------------------------------------------------------- # # # Copyright (C) 1991-2013 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Altera Program License # Subscription Agreement, Altera MegaCore Function License # Agreement, or other applicable license agreement, including, # without limitation, that your use is for the sole purpose of # programming logic devices manufactured by Altera and sold by # Altera or its authorized distributors. Please refer to the # applicable agreement for further details. # # -------------------------------------------------------------------------- # # # Quartus II 64-Bit # Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition # Date created = 09:26:31 October 13, 2014 # # -------------------------------------------------------------------------- # QUARTUS_VERSION = "13.0" DATE = "09:26:31 October 13, 2014" # Revisions PROJECT_REVISION = "test_registers" ================================================ FILE: cpu/registers/test_registers.qsf ================================================ # -------------------------------------------------------------------------- # # # Copyright (C) 1991-2013 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Altera Program License # Subscription Agreement, Altera MegaCore Function License # Agreement, or other applicable license agreement, including, # without limitation, that your use is for the sole purpose of # programming logic devices manufactured by Altera and sold by # Altera or its authorized distributors. Please refer to the # applicable agreement for further details. # # -------------------------------------------------------------------------- # # # Quartus II 64-Bit # Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition # Date created = 09:26:31 October 13, 2014 # # -------------------------------------------------------------------------- # # # Notes: # # 1) The default values for assignments are stored in the file: # test_registers_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # # 2) Altera recommends that you do not modify this file. This # file is updated automatically by the Quartus II software # and any changes you make may be lost or overwritten. # # -------------------------------------------------------------------------- # set_global_assignment -name FAMILY "Cyclone II" set_global_assignment -name DEVICE EP2C20F484C7 set_global_assignment -name TOP_LEVEL_ENTITY reg_control set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:26:31 OCTOBER 13, 2014" set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name BSF_FILE reg_latch.bsf set_global_assignment -name BDF_FILE reg_latch.bdf set_global_assignment -name BDF_FILE reg_file.bdf set_global_assignment -name BDF_FILE reg_control.bdf set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name USE_CONFIGURATION_DEVICE ON set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP" set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS OFF set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top ================================================ FILE: cpu/registers/test_registers.sv ================================================ //============================================================== // Test register control and register file blocks //============================================================== `timescale 100 ns/ 100 ns module test_registers; // ----------------- CLOCKS AND RESET ----------------- // Define one full T-clock cycle delay `define T #2 bit clk = 1; initial repeat (36) #1 clk = ~clk; logic nreset = 0; // ----------------- BUSES ----------------- // We have 4 Bi-directional buses that can also be 3-stated: // On the address-side, there are high and low 8-bit buses reg [7:0] db_lo_as=8'hz; // Drive it using this bus wire [7:0] db_lo_as_sig; // Read it using this bus reg [7:0] db_hi_as=8'hz; // Drive it using this bus wire [7:0] db_hi_as_sig; // Read it using this bus // On the data-side, there are high and low 8-bit buses reg [7:0] db_lo_ds=8'hz; // Drive it using this bus wire [7:0] db_lo_ds_sig; // Read it using this bus reg [7:0] db_hi_ds=8'hz; // Drive it using this bus wire [7:0] db_hi_ds_sig; // Read it using this bus // ----------------- BUS SWITCHES ------------ logic ctl_sw_4u_sig=0; // Bus switch #4 upstream gate logic ctl_sw_4d_sig=0; // Bus switch #4 downstream gate logic ctl_reg_in_hi_sig=0; // Input to the register file high logic ctl_reg_in_lo_sig=0; // Input to the register file low logic ctl_reg_out_hi_sig=0; // Output from the register file high logic ctl_reg_out_lo_sig=0; // Output from the register file low // ----------------- CONTROL ----------------- logic [1:0] ctl_reg_gp_sel_sig=0; // Selection of a general purpose register logic [1:0] ctl_reg_gp_hilo_sig=0; // Hi/Lo selector for GP registers logic ctl_reg_gp_we_sig=0; // Write to a general purpose register logic [1:0] ctl_reg_sys_hilo_sig=0; // Hi/Lo selector for system registers logic ctl_reg_sys_we_lo_sig=0; // Write to low byte of a system register logic ctl_reg_sys_we_hi_sig=0; // Write to high byte of a system register logic ctl_reg_sys_we_sig=0; // Write to system register logic use_ixiy_sig=0; // Use IX or IY logic use_ix_sig=0; // Use IX and not IY logic nhold_clk_wait_sig=1; // Enable transitions due to nWAIT logic ctl_reg_exx_sig=0; // Exchange register banks logic ctl_reg_ex_af_sig=0; // Exchange AF banks logic ctl_reg_ex_de_hl_sig=0; // Exchange HL/DE banks logic ctl_reg_use_sp_sig=0; // Use SP register logic ctl_reg_sel_pc_sig=0; // Select PC logic ctl_reg_sel_ir_sig=0; // Select IR logic ctl_reg_sel_wz_sig=0; // Select WZ logic ctl_reg_not_pc_sig=0; // Do not select PC // ----------------- TEST ------------------- `define CHECK(arg) \ assert({db_hi_ds_sig,db_lo_ds_sig}===arg); initial begin `T nreset = 1; //------------------------------------------------------------ // Identify each 16-bit system register and check access to it `T ctl_sw_4d_sig = 1; // Use unified bus: downstream ctl_sw_4u_sig = 0; ctl_reg_in_hi_sig = 1; ctl_reg_in_lo_sig = 1; db_hi_ds = 8'h81; db_lo_ds = 8'h41; ctl_reg_sys_hilo_sig = 2'b11; ctl_reg_sys_we_hi_sig = 1; // 16-bit access ctl_reg_sys_we_lo_sig = 1; // 16-bit access ctl_reg_sel_wz_sig = 1; // WZ `T db_hi_ds = 8'h82; db_lo_ds = 8'h42; ctl_reg_sel_wz_sig = 0; // WZ off ctl_reg_sel_pc_sig = 1; // PC `T db_hi_ds = 8'h83; db_lo_ds = 8'h43; ctl_reg_sel_pc_sig = 0; // PC off ctl_reg_sel_ir_sig = 1; // IR `T db_hi_ds = 'z; db_lo_ds = 'z; ctl_reg_sel_ir_sig = 0; // IR off // Read back ctl_sw_4d_sig = 0; ctl_sw_4u_sig = 0; // Upstream ctl_reg_in_hi_sig = 0; ctl_reg_in_lo_sig = 0; ctl_reg_out_hi_sig = 1; ctl_reg_out_lo_sig = 1; ctl_reg_sys_we_hi_sig = 0; ctl_reg_sys_we_lo_sig = 0; ctl_reg_sel_wz_sig = 1; // WZ `T `CHECK(16'h8141); ctl_reg_sel_wz_sig = 0; // WZ off ctl_sw_4u_sig = 1; // Upstream ctl_reg_sel_pc_sig = 1; // PC `T `CHECK(16'h8242); ctl_reg_sel_pc_sig = 0; // PC off ctl_reg_sel_ir_sig = 1; // IR `T `CHECK(16'h8343); ctl_reg_sel_ir_sig = 0; // IR off ctl_sw_4d_sig = 0; ctl_sw_4u_sig = 0; ctl_reg_sys_hilo_sig = 2'b00; //------------------------------------------------------------ // Identify a 16-bit system register and check access to it `T ctl_reg_in_hi_sig = 1; ctl_reg_in_lo_sig = 1; ctl_reg_out_hi_sig = 0; ctl_reg_out_lo_sig = 0; ctl_reg_gp_we_sig = 1; // Write to a GP register ctl_reg_gp_hilo_sig = 2'b11;// 16-bit write db_hi_ds = 8'hAA; db_lo_ds = 8'h55; ctl_reg_gp_sel_sig = 2'b00; // AF `T db_hi_ds = 8'hAB; db_lo_ds = 8'h56; ctl_reg_gp_sel_sig = 2'b01; // BC `T db_hi_ds = 8'hAC; db_lo_ds = 8'h57; ctl_reg_gp_sel_sig = 2'b10; // DE `T db_hi_ds = 8'hAD; db_lo_ds = 8'h58; ctl_reg_gp_sel_sig = 2'b11; // HL `T db_hi_ds = 'z; db_lo_ds = 'z; // Read back ctl_reg_in_hi_sig = 0; ctl_reg_in_lo_sig = 0; ctl_reg_out_hi_sig = 1; ctl_reg_out_lo_sig = 1; ctl_reg_gp_we_sig = 0; ctl_reg_gp_sel_sig = 2'b00; // Check AF `T `CHECK(16'hAA55); ctl_reg_gp_sel_sig = 2'b01; // Check BC `T `CHECK(16'hAB56); ctl_reg_gp_sel_sig = 2'b10; // Check DE `T `CHECK(16'hAC57); ctl_reg_gp_sel_sig = 2'b11; // Check HL `T `CHECK(16'hAD58); `T $display("End of test"); end // Drive 3-state bidirectional buses with these statements assign db_lo_as_sig = db_lo_as; assign db_hi_as_sig = db_hi_as; assign db_lo_ds_sig = db_lo_ds; assign db_hi_ds_sig = db_hi_ds; // Instantiate register control block reg_control reg_control_inst ( .ctl_reg_gp_sel(ctl_reg_gp_sel_sig) , // input [1:0] ctl_reg_gp_sel_sig .ctl_reg_sys_hilo(ctl_reg_sys_hilo_sig),// input [1:0] ctl_reg_sys_hilo_sig .ctl_reg_exx(ctl_reg_exx_sig) , // input ctl_reg_exx_sig .ctl_reg_ex_af(ctl_reg_ex_af_sig) , // input ctl_reg_ex_af_sig .ctl_reg_ex_de_hl(ctl_reg_ex_de_hl_sig),// input ctl_reg_ex_de_hl_sig .ctl_reg_use_sp(ctl_reg_use_sp_sig) , // input ctl_reg_use_sp_sig .ctl_reg_gp_hilo(ctl_reg_gp_hilo_sig) , // input [1:0] ctl_reg_gp_hilo_sig .nreset(nreset) , // input nreset .ctl_reg_sel_pc(ctl_reg_sel_pc_sig) , // input ctl_reg_sel_pc_sig .ctl_reg_sel_ir(ctl_reg_sel_ir_sig) , // input ctl_reg_sel_ir_sig .ctl_reg_sel_wz(ctl_reg_sel_wz_sig) , // input ctl_reg_sel_wz_sig .ctl_reg_gp_we(ctl_reg_gp_we_sig) , // input ctl_reg_gp_we_sig .ctl_reg_not_pc(ctl_reg_not_pc_sig) , // input ctl_reg_not_pc_sig .use_ixiy(use_ixiy_sig) , // input use_ixiy_sig .use_ix(use_ix_sig) , // input use_ix_sig .ctl_reg_sys_we_lo(ctl_reg_sys_we_lo_sig),// input ctl_reg_sys_we_lo_sig .ctl_reg_sys_we_hi(ctl_reg_sys_we_hi_sig),// input ctl_reg_sys_we_hi_sig .ctl_reg_sys_we(ctl_reg_sys_we_sig) , // input ctl_reg_sys_we_sig .clk(clk) , // input clk .ctl_sw_4d (ctl_sw_4d_sig) , // input ctl_sw_4d .nhold_clk_wait(nhold_clk_wait_sig) , // input nhold_clk_wait_sig .reg_sel_bc(reg_sel_bc_sig) , // output reg_sel_bc_sig .reg_sel_bc2(reg_sel_bc2_sig) , // output reg_sel_bc2_sig .reg_sel_ix(reg_sel_ix_sig) , // output reg_sel_ix_sig .reg_sel_iy(reg_sel_iy_sig) , // output reg_sel_iy_sig .reg_sel_de(reg_sel_de_sig) , // output reg_sel_de_sig .reg_sel_hl(reg_sel_hl_sig) , // output reg_sel_hl_sig .reg_sel_de2(reg_sel_de2_sig) , // output reg_sel_de2_sig .reg_sel_hl2(reg_sel_hl2_sig) , // output reg_sel_hl2_sig .reg_sel_af(reg_sel_af_sig) , // output reg_sel_af_sig .reg_sel_af2(reg_sel_af2_sig) , // output reg_sel_af2_sig .reg_sel_wz(reg_sel_wz_sig) , // output reg_sel_wz_sig .reg_sel_pc(reg_sel_pc_sig) , // output reg_sel_pc_sig .reg_sel_ir(reg_sel_ir_sig) , // output reg_sel_ir_sig .reg_sel_sp(reg_sel_sp_sig) , // output reg_sel_sp_sig .reg_sel_gp_hi(reg_sel_gp_hi_sig) , // output reg_sel_gp_hi_sig .reg_sel_gp_lo(reg_sel_gp_lo_sig) , // output reg_sel_gp_lo_sig .reg_sel_sys_lo(reg_sel_sys_lo_sig) , // output reg_sel_sys_lo_sig .reg_sel_sys_hi(reg_sel_sys_hi_sig) , // output reg_sel_sys_hi_sig .reg_gp_we(reg_gp_we_sig) , // output reg_gp_we_sig .reg_sys_we_lo(reg_sys_we_lo_sig) , // output reg_sys_we_lo_sig .reg_sys_we_hi(reg_sys_we_hi_sig) , // output reg_sys_we_hi_sig .reg_sw_4d_lo (reg_sw_4d_lo_sig) , // output reg_sw_4d_lo_sig .reg_sw_4d_hi (reg_sw_4d_hi_sig) // output reg_sw_4d_hi_sig ); // Instantiate register file block reg_file reg_file_inst ( .reg_sel_sys_lo(reg_sel_sys_lo_sig) , // input reg_sel_sys_lo_sig .reg_sel_gp_lo(reg_sel_gp_lo_sig) , // input reg_sel_gp_lo_sig .reg_sel_sys_hi(reg_sel_sys_hi_sig) , // input reg_sel_sys_hi_sig .reg_sel_gp_hi(reg_sel_gp_hi_sig) , // input reg_sel_gp_hi_sig .reg_sel_ir(reg_sel_ir_sig) , // input reg_sel_ir_sig .reg_sel_pc(reg_sel_pc_sig) , // input reg_sel_pc_sig .reg_sw_4d_lo(reg_sw_4d_lo_sig) , // input reg_sw_4d_lo_sig .reg_sw_4d_hi(reg_sw_4d_hi_sig) , // input reg_sw_4d_hi_sig .ctl_sw_4u(ctl_sw_4u_sig) , // input ctl_sw_4u_sig .reg_sel_wz(reg_sel_wz_sig) , // input reg_sel_wz_sig .reg_sel_sp(reg_sel_sp_sig) , // input reg_sel_sp_sig .reg_sel_iy(reg_sel_iy_sig) , // input reg_sel_iy_sig .reg_sel_ix(reg_sel_ix_sig) , // input reg_sel_ix_sig .reg_sel_hl2(reg_sel_hl2_sig) , // input reg_sel_hl2_sig .reg_sel_hl(reg_sel_hl_sig) , // input reg_sel_hl_sig .reg_sel_de2(reg_sel_de2_sig) , // input reg_sel_de2_sig .reg_sel_de(reg_sel_de_sig) , // input reg_sel_de_sig .reg_sel_bc2(reg_sel_bc2_sig) , // input reg_sel_bc2_sig .reg_sel_bc(reg_sel_bc_sig) , // input reg_sel_bc_sig .reg_sel_af2(reg_sel_af2_sig) , // input reg_sel_af2_sig .reg_sel_af(reg_sel_af_sig) , // input reg_sel_af_sig .reg_gp_we(reg_gp_we_sig) , // input reg_gp_we_sig .reg_sys_we_lo(reg_sys_we_lo_sig) , // input reg_sys_we_lo_sig .reg_sys_we_hi(reg_sys_we_hi_sig) , // input reg_sys_we_hi_sig .ctl_reg_in_hi(ctl_reg_in_hi_sig) , // input ctl_reg_in_hi_sig .ctl_reg_in_lo(ctl_reg_in_lo_sig) , // input ctl_reg_in_lo_sig .ctl_reg_out_lo(ctl_reg_out_lo_sig) , // input ctl_reg_out_lo_sig .ctl_reg_out_hi(ctl_reg_out_hi_sig) , // input ctl_reg_out_hi_sig .clk(clk) , // input clk .db_lo_ds(db_lo_ds_sig) , // inout [7:0] db_lo_ds_sig .db_hi_ds(db_hi_ds_sig) , // inout [7:0] db_hi_ds_sig .db_lo_as(db_lo_as_sig) , // inout [7:0] db_lo_as_sig .db_hi_as(db_hi_as_sig) // inout [7:0] db_hi_as_sig ); endmodule ================================================ FILE: cpu/top-level-files.txt ================================================ # This is a list of A-Z80 files and their dependencies. It is used by several scripts. # To copy A-Z80 files into your project, run "export.py" script. ------ Control block ------- control/clk_delay.v control/decode_state.v control/exec_module.vh control/execute.v + control/exec_matrix.vh + control/exec_matrix_compiled.vh + control/exec_module.vh + control/exec_zero.vh + control/temp_wires.vh control/interrupts.v control/ir.v control/pin_control.v control/pla_decode.v control/resets.v control/memory_ifc.v control/sequencer.v ---------- ALU ------------- alu/alu_control.v + alu/alu_mux_4.v + alu/alu_mux_8.v alu/alu_select.v alu/alu_flags.v + alu/alu_mux_2.v + alu/alu_mux_4.v alu/alu.v + alu/alu_core.v + alu/alu_slice.v + alu/alu_bit_select.v + alu/alu_shifter_core.v + alu/alu_mux_2z.v + alu/alu_mux_3z.v + alu/alu_prep_daa.v ------ Register file ------- registers/reg_file.v + registers/reg_latch.v registers/reg_control.v ------ Address latch ------- bus/address_latch.v + bus/address_mux.v + bus/inc_dec.v + bus/inc_dec_2bit.v bus/address_pins.v --------- Misc bus --------- bus/bus_control.v bus/bus_switch.v + bus/data_switch.v + bus/data_switch_mask.v ------ I/O pin control ----- bus/data_pins.v bus/control_pins_n.v --------- Top level -------- + toplevel/z80_top_direct_n.v + toplevel/core.vh + toplevel/coremodules.vh + toplevel/globals.vh Files=49 ================================================ FILE: cpu/toplevel/core.vh ================================================ //============================================================================ // A-Z80 core, instantiates and connects all internal blocks. // // This file is included by the "z80_top_ifc_n" and "z80_top_direct" providing // interface binding and direct (no interface) binding. //============================================================================ // Include a list of top-level signal wires `include "globals.vh" // Specific to simulation, some modules in the schematics need to be pre-initialized // to avoid starting simulations with unknown values in selected flip flops. reg fpga_reset = 1; always @(posedge clk) begin fpga_reset <= 0; end // Define internal data bus partitions segmented by data bus switches wire [7:0] db0; // Segment connecting data pins and IR wire [7:0] db1; // Segment leading to the ALU wire [7:0] db2; // Segment with msb part of the register address-side interface wire [7:0] db_hi_as; // Register file data bus segment high byte wire [7:0] db_lo_as; // Register file data bus segment low byte wire [6:0] prefix; // Instruction decode PLA prefix bitfield assign prefix = { ~use_ixiy, use_ixiy, ~in_halt, in_alu, table_xx, table_cb, table_ed }; wire nM1_int; // External pins timing control assign nM1_int = !(setM1 | (fFetch & T1)); `include "coremodules.vh" // Data path within the CPU in various forms, ending with data pins data_switch sw2_( .sw_up_en(bus_sw_2u), .sw_down_en(bus_sw_2d), .db_up(db1[7:0]), .db_down(db2[7:0]) ); // Data switch SW1 with the data mask data_switch_mask sw1_( .sw_mask543_en(bus_sw_mask543_en), .sw_up_en(bus_sw_1u), .sw_down_en(bus_sw_1d), .db_up(db0[7:0]), .db_down(db1[7:0]) ); /* This SystemVerilog-style code is kept for future reference // Control block clk_delay clk_delay_( .* ); decode_state decode_state_( .* ); execute execute_( .* ); interrupts interrupts_( .*, .db(db0[4:3]) ); ir ir_( .*, .db(db0[7:0]) ); pin_control pin_control_( .* ); pla_decode pla_decode_( .* ); resets resets_( .* ); sequencer sequencer_( .* ); // ALU and ALU control, including the flags alu_control alu_control_( .*, .db(db1[7:0]), .op543({pla[104],pla[103],pla[102]}) ); alu_select alu_select_( .* ); alu_flags alu_flags_( .*, .db(db1[7:0]) ); alu alu_( .*, .db(db2[7:0]), .bsel(db0[5:3]) ); // Register file and register control reg_file reg_file_( .*, .db_hi_ds(db2[7:0]), .db_lo_ds(db1[7:0]), .db_hi_as(db_hi_as[7:0]), .db_lo_as(db_lo_as[7:0]) ); reg_control reg_control_( .* ); // Address latch and the incrementer address_latch address_latch_( .*, .abus({db_hi_as[7:0], db_lo_as[7:0]}) ); // Misc bus bus_control bus_control_( .*, .db(db0[7:0]) ); bus_switch bus_switch_( .* ); // Timing control of the external pins memory_ifc memory_ifc_( .* ); */ ================================================ FILE: cpu/toplevel/coremodules.vh ================================================ // Automatically generated by gencoremodules.py clk_delay clk_delay_( .clk (clk), .in_intr (in_intr), .nreset (nreset), .T1 (T1), .latch_wait (latch_wait), .mwait (mwait), .M1 (M1), .busrq (busrq), .setM1 (setM1), .hold_clk_iorq (hold_clk_iorq), .hold_clk_wait (hold_clk_wait), .iorq_Tw (iorq_Tw), .busack (busack), .pin_control_oe (pin_control_oe), .hold_clk_busrq (hold_clk_busrq), .nhold_clk_wait (nhold_clk_wait) ); decode_state decode_state_( .ctl_state_iy_set (ctl_state_iy_set), .ctl_state_ixiy_clr (ctl_state_ixiy_clr), .ctl_state_ixiy_we (ctl_state_ixiy_we), .ctl_state_halt_set (ctl_state_halt_set), .ctl_state_tbl_ed_set (ctl_state_tbl_ed_set), .ctl_state_tbl_cb_set (ctl_state_tbl_cb_set), .ctl_state_alu (ctl_state_alu), .clk (clk), .address_is_1 (address_is_1), .ctl_repeat_we (ctl_repeat_we), .in_intr (in_intr), .in_nmi (in_nmi), .nreset (nreset), .ctl_state_tbl_we (ctl_state_tbl_we), .nhold_clk_wait (nhold_clk_wait), .in_halt (in_halt), .table_cb (table_cb), .table_ed (table_ed), .table_xx (table_xx), .use_ix (use_ix), .use_ixiy (use_ixiy), .in_alu (in_alu), .repeat_en (repeat_en) ); execute execute_( .ctl_state_iy_set (ctl_state_iy_set), .ctl_state_ixiy_clr (ctl_state_ixiy_clr), .ctl_state_ixiy_we (ctl_state_ixiy_we), .ctl_state_halt_set (ctl_state_halt_set), .ctl_state_tbl_ed_set (ctl_state_tbl_ed_set), .ctl_state_tbl_cb_set (ctl_state_tbl_cb_set), .ctl_state_alu (ctl_state_alu), .ctl_repeat_we (ctl_repeat_we), .ctl_state_tbl_we (ctl_state_tbl_we), .ctl_iff1_iff2 (ctl_iff1_iff2), .ctl_iffx_we (ctl_iffx_we), .ctl_iffx_bit (ctl_iffx_bit), .ctl_im_we (ctl_im_we), .ctl_no_ints (ctl_no_ints), .ctl_ir_we (ctl_ir_we), .ctl_mRead (ctl_mRead), .ctl_mWrite (ctl_mWrite), .ctl_iorw (ctl_iorw), .ctl_shift_en (ctl_shift_en), .ctl_daa_oe (ctl_daa_oe), .ctl_alu_op_low (ctl_alu_op_low), .ctl_cond_short (ctl_cond_short), .ctl_alu_core_hf (ctl_alu_core_hf), .ctl_eval_cond (ctl_eval_cond), .ctl_66_oe (ctl_66_oe), .ctl_pf_sel (ctl_pf_sel), .ctl_alu_oe (ctl_alu_oe), .ctl_alu_shift_oe (ctl_alu_shift_oe), .ctl_alu_op2_oe (ctl_alu_op2_oe), .ctl_alu_res_oe (ctl_alu_res_oe), .ctl_alu_op1_oe (ctl_alu_op1_oe), .ctl_alu_bs_oe (ctl_alu_bs_oe), .ctl_alu_op1_sel_bus (ctl_alu_op1_sel_bus), .ctl_alu_op1_sel_low (ctl_alu_op1_sel_low), .ctl_alu_op1_sel_zero (ctl_alu_op1_sel_zero), .ctl_alu_op2_sel_zero (ctl_alu_op2_sel_zero), .ctl_alu_op2_sel_bus (ctl_alu_op2_sel_bus), .ctl_alu_op2_sel_lq (ctl_alu_op2_sel_lq), .ctl_alu_sel_op2_neg (ctl_alu_sel_op2_neg), .ctl_alu_sel_op2_high (ctl_alu_sel_op2_high), .ctl_alu_core_R (ctl_alu_core_R), .ctl_alu_core_V (ctl_alu_core_V), .ctl_alu_core_S (ctl_alu_core_S), .ctl_flags_oe (ctl_flags_oe), .ctl_flags_bus (ctl_flags_bus), .ctl_flags_alu (ctl_flags_alu), .ctl_flags_nf_set (ctl_flags_nf_set), .ctl_flags_cf_set (ctl_flags_cf_set), .ctl_flags_cf_cpl (ctl_flags_cf_cpl), .ctl_flags_cf_we (ctl_flags_cf_we), .ctl_flags_sz_we (ctl_flags_sz_we), .ctl_flags_xy_we (ctl_flags_xy_we), .ctl_flags_hf_we (ctl_flags_hf_we), .ctl_flags_pf_we (ctl_flags_pf_we), .ctl_flags_nf_we (ctl_flags_nf_we), .ctl_flags_cf2_we (ctl_flags_cf2_we), .ctl_flags_hf_cpl (ctl_flags_hf_cpl), .ctl_flags_use_cf2 (ctl_flags_use_cf2), .ctl_flags_hf2_we (ctl_flags_hf2_we), .ctl_flags_nf_clr (ctl_flags_nf_clr), .ctl_alu_zero_16bit (ctl_alu_zero_16bit), .ctl_flags_cf2_sel_shift (ctl_flags_cf2_sel_shift), .ctl_flags_cf2_sel_daa (ctl_flags_cf2_sel_daa), .ctl_sw_4u (ctl_sw_4u), .ctl_reg_in_hi (ctl_reg_in_hi), .ctl_reg_in_lo (ctl_reg_in_lo), .ctl_reg_out_lo (ctl_reg_out_lo), .ctl_reg_out_hi (ctl_reg_out_hi), .ctl_reg_exx (ctl_reg_exx), .ctl_reg_ex_af (ctl_reg_ex_af), .ctl_reg_ex_de_hl (ctl_reg_ex_de_hl), .ctl_reg_use_sp (ctl_reg_use_sp), .ctl_reg_sel_pc (ctl_reg_sel_pc), .ctl_reg_sel_ir (ctl_reg_sel_ir), .ctl_reg_sel_wz (ctl_reg_sel_wz), .ctl_reg_gp_we (ctl_reg_gp_we), .ctl_reg_not_pc (ctl_reg_not_pc), .ctl_reg_sys_we_lo (ctl_reg_sys_we_lo), .ctl_reg_sys_we_hi (ctl_reg_sys_we_hi), .ctl_reg_sys_we (ctl_reg_sys_we), .ctl_sw_4d (ctl_sw_4d), .ctl_reg_gp_hilo (ctl_reg_gp_hilo), .ctl_reg_gp_sel (ctl_reg_gp_sel), .ctl_reg_sys_hilo (ctl_reg_sys_hilo), .ctl_inc_cy (ctl_inc_cy), .ctl_inc_dec (ctl_inc_dec), .ctl_al_we (ctl_al_we), .ctl_inc_limit6 (ctl_inc_limit6), .ctl_bus_inc_oe (ctl_bus_inc_oe), .ctl_apin_mux (ctl_apin_mux), .ctl_apin_mux2 (ctl_apin_mux2), .ctl_bus_ff_oe (ctl_bus_ff_oe), .ctl_bus_zero_oe (ctl_bus_zero_oe), .ctl_sw_1u (ctl_sw_1u), .ctl_sw_1d (ctl_sw_1d), .ctl_sw_2u (ctl_sw_2u), .ctl_sw_2d (ctl_sw_2d), .ctl_sw_mask543_en (ctl_sw_mask543_en), .ctl_bus_db_we (ctl_bus_db_we), .ctl_bus_db_oe (ctl_bus_db_oe), .nextM (nextM), .setM1 (setM1), .fFetch (fFetch), .fMRead (fMRead), .fMWrite (fMWrite), .fIORead (fIORead), .fIOWrite (fIOWrite), .pla (pla), .in_intr (in_intr), .in_nmi (in_nmi), .in_halt (in_halt), .im1 (im1), .im2 (im2), .use_ixiy (use_ixiy), .flags_cond_true (flags_cond_true), .repeat_en (repeat_en), .flags_zf (flags_zf), .flags_nf (flags_nf), .flags_sf (flags_sf), .flags_cf (flags_cf), .M1 (M1), .M2 (M2), .M3 (M3), .M4 (M4), .M5 (M5), .T1 (T1), .T2 (T2), .T3 (T3), .T4 (T4), .T5 (T5), .T6 (T6) ); interrupts interrupts_( .ctl_iff1_iff2 (ctl_iff1_iff2), .nmi (nmi), .setM1 (setM1), .intr (intr), .ctl_iffx_we (ctl_iffx_we), .ctl_iffx_bit (ctl_iffx_bit), .ctl_im_we (ctl_im_we), .clk (clk), .ctl_no_ints (ctl_no_ints), .nreset (nreset), .db (db0[4:3]), .iff2 (iff2), .im1 (im1), .im2 (im2), .in_nmi (in_nmi), .in_intr (in_intr) ); ir ir_( .ctl_ir_we (ctl_ir_we), .clk (clk), .nreset (nreset), .nhold_clk_wait (nhold_clk_wait), .db (db0[7:0]), .opcode (opcode) ); pin_control pin_control_( .fFetch (fFetch), .fMRead (fMRead), .fMWrite (fMWrite), .fIORead (fIORead), .fIOWrite (fIOWrite), .T1 (T1), .T2 (T2), .T3 (T3), .T4 (T4), .bus_ab_pin_we (bus_ab_pin_we), .bus_db_pin_oe (bus_db_pin_oe), .bus_db_pin_re (bus_db_pin_re) ); pla_decode pla_decode_( .prefix (prefix), .opcode (opcode), .pla (pla) ); resets resets_( .reset_in (reset_in), .clk (clk), .M1 (M1), .T2 (T2), .fpga_reset (fpga_reset), .nhold_clk_wait (nhold_clk_wait), .clrpc (clrpc), .nreset (nreset) ); memory_ifc memory_ifc_( .clk (clk), .nM1_int (nM1_int), .ctl_mRead (ctl_mRead), .ctl_mWrite (ctl_mWrite), .in_intr (in_intr), .nreset (nreset), .fIORead (fIORead), .fIOWrite (fIOWrite), .setM1 (setM1), .ctl_iorw (ctl_iorw), .timings_en (timings_en), .iorq_Tw (iorq_Tw), .nhold_clk_wait (nhold_clk_wait), .nM1_out (nM1_out), .nRFSH_out (nRFSH_out), .nMREQ_out (nMREQ_out), .nRD_out (nRD_out), .nWR_out (nWR_out), .nIORQ_out (nIORQ_out), .latch_wait (latch_wait), .wait_m1 (wait_m1) ); sequencer sequencer_( .clk (clk), .nextM (nextM), .setM1 (setM1), .nreset (nreset), .hold_clk_iorq (hold_clk_iorq), .hold_clk_wait (hold_clk_wait), .hold_clk_busrq (hold_clk_busrq), .M1 (M1), .M2 (M2), .M3 (M3), .M4 (M4), .M5 (M5), .T1 (T1), .T2 (T2), .T3 (T3), .T4 (T4), .T5 (T5), .T6 (T6), .timings_en (timings_en) ); alu_control alu_control_( .alu_shift_db0 (alu_shift_db0), .alu_shift_db7 (alu_shift_db7), .ctl_shift_en (ctl_shift_en), .alu_low_gt_9 (alu_low_gt_9), .alu_high_gt_9 (alu_high_gt_9), .alu_high_eq_9 (alu_high_eq_9), .ctl_daa_oe (ctl_daa_oe), .ctl_alu_op_low (ctl_alu_op_low), .alu_parity_out (alu_parity_out), .flags_cf (flags_cf), .flags_zf (flags_zf), .flags_pf (flags_pf), .flags_sf (flags_sf), .ctl_cond_short (ctl_cond_short), .alu_vf_out (alu_vf_out), .iff2 (iff2), .ctl_alu_core_hf (ctl_alu_core_hf), .ctl_eval_cond (ctl_eval_cond), .repeat_en (repeat_en), .flags_cf_latch (flags_cf_latch), .flags_hf2 (flags_hf2), .flags_hf (flags_hf), .ctl_66_oe (ctl_66_oe), .clk (clk), .ctl_pf_sel (ctl_pf_sel), .op543 ({pla[104],pla[103],pla[102]}), .alu_shift_in (alu_shift_in), .alu_shift_right (alu_shift_right), .alu_shift_left (alu_shift_left), .shift_cf_out (shift_cf_out), .alu_parity_in (alu_parity_in), .flags_cond_true (flags_cond_true), .daa_cf_out (daa_cf_out), .pf_sel (pf_sel), .alu_op_low (alu_op_low), .alu_core_cf_in (alu_core_cf_in), .db (db1[7:0]) ); alu_select alu_select_( .ctl_alu_oe (ctl_alu_oe), .ctl_alu_shift_oe (ctl_alu_shift_oe), .ctl_alu_op2_oe (ctl_alu_op2_oe), .ctl_alu_res_oe (ctl_alu_res_oe), .ctl_alu_op1_oe (ctl_alu_op1_oe), .ctl_alu_bs_oe (ctl_alu_bs_oe), .ctl_alu_op1_sel_bus (ctl_alu_op1_sel_bus), .ctl_alu_op1_sel_low (ctl_alu_op1_sel_low), .ctl_alu_op1_sel_zero (ctl_alu_op1_sel_zero), .ctl_alu_op2_sel_zero (ctl_alu_op2_sel_zero), .ctl_alu_op2_sel_bus (ctl_alu_op2_sel_bus), .ctl_alu_op2_sel_lq (ctl_alu_op2_sel_lq), .ctl_alu_sel_op2_neg (ctl_alu_sel_op2_neg), .ctl_alu_sel_op2_high (ctl_alu_sel_op2_high), .ctl_alu_core_R (ctl_alu_core_R), .ctl_alu_core_V (ctl_alu_core_V), .ctl_alu_core_S (ctl_alu_core_S), .alu_oe (alu_oe), .alu_shift_oe (alu_shift_oe), .alu_op2_oe (alu_op2_oe), .alu_res_oe (alu_res_oe), .alu_op1_oe (alu_op1_oe), .alu_bs_oe (alu_bs_oe), .alu_op1_sel_bus (alu_op1_sel_bus), .alu_op1_sel_low (alu_op1_sel_low), .alu_op1_sel_zero (alu_op1_sel_zero), .alu_op2_sel_zero (alu_op2_sel_zero), .alu_op2_sel_bus (alu_op2_sel_bus), .alu_op2_sel_lq (alu_op2_sel_lq), .alu_sel_op2_neg (alu_sel_op2_neg), .alu_sel_op2_high (alu_sel_op2_high), .alu_core_R (alu_core_R), .alu_core_V (alu_core_V), .alu_core_S (alu_core_S) ); alu_flags alu_flags_( .ctl_flags_oe (ctl_flags_oe), .ctl_flags_bus (ctl_flags_bus), .ctl_flags_alu (ctl_flags_alu), .alu_sf_out (alu_sf_out), .alu_yf_out (alu_yf_out), .alu_xf_out (alu_xf_out), .ctl_flags_nf_set (ctl_flags_nf_set), .alu_zero (alu_zero), .shift_cf_out (shift_cf_out), .alu_core_cf_out (alu_core_cf_out), .daa_cf_out (daa_cf_out), .ctl_flags_cf_set (ctl_flags_cf_set), .ctl_flags_cf_cpl (ctl_flags_cf_cpl), .pf_sel (pf_sel), .ctl_flags_cf_we (ctl_flags_cf_we), .ctl_flags_sz_we (ctl_flags_sz_we), .ctl_flags_xy_we (ctl_flags_xy_we), .ctl_flags_hf_we (ctl_flags_hf_we), .ctl_flags_pf_we (ctl_flags_pf_we), .ctl_flags_nf_we (ctl_flags_nf_we), .ctl_flags_cf2_we (ctl_flags_cf2_we), .ctl_flags_hf_cpl (ctl_flags_hf_cpl), .ctl_flags_use_cf2 (ctl_flags_use_cf2), .ctl_flags_hf2_we (ctl_flags_hf2_we), .ctl_flags_nf_clr (ctl_flags_nf_clr), .ctl_alu_zero_16bit (ctl_alu_zero_16bit), .clk (clk), .ctl_flags_cf2_sel_shift (ctl_flags_cf2_sel_shift), .ctl_flags_cf2_sel_daa (ctl_flags_cf2_sel_daa), .nhold_clk_wait (nhold_clk_wait), .flags_sf (flags_sf), .flags_zf (flags_zf), .flags_hf (flags_hf), .flags_pf (flags_pf), .flags_cf (flags_cf), .flags_nf (flags_nf), .flags_cf_latch (flags_cf_latch), .flags_hf2 (flags_hf2), .db (db1[7:0]) ); alu alu_( .alu_core_R (alu_core_R), .alu_core_V (alu_core_V), .alu_core_S (alu_core_S), .alu_bs_oe (alu_bs_oe), .alu_parity_in (alu_parity_in), .alu_oe (alu_oe), .alu_shift_oe (alu_shift_oe), .alu_core_cf_in (alu_core_cf_in), .alu_op2_oe (alu_op2_oe), .alu_op1_oe (alu_op1_oe), .alu_res_oe (alu_res_oe), .alu_op1_sel_low (alu_op1_sel_low), .alu_op1_sel_zero (alu_op1_sel_zero), .alu_op1_sel_bus (alu_op1_sel_bus), .alu_op2_sel_zero (alu_op2_sel_zero), .alu_op2_sel_bus (alu_op2_sel_bus), .alu_op2_sel_lq (alu_op2_sel_lq), .alu_op_low (alu_op_low), .alu_shift_in (alu_shift_in), .alu_sel_op2_neg (alu_sel_op2_neg), .alu_sel_op2_high (alu_sel_op2_high), .alu_shift_left (alu_shift_left), .alu_shift_right (alu_shift_right), .clk (clk), .bsel (db0[5:3]), .alu_zero (alu_zero), .alu_parity_out (alu_parity_out), .alu_high_eq_9 (alu_high_eq_9), .alu_high_gt_9 (alu_high_gt_9), .alu_low_gt_9 (alu_low_gt_9), .alu_shift_db0 (alu_shift_db0), .alu_shift_db7 (alu_shift_db7), .alu_core_cf_out (alu_core_cf_out), .alu_sf_out (alu_sf_out), .alu_yf_out (alu_yf_out), .alu_xf_out (alu_xf_out), .alu_vf_out (alu_vf_out), .db (db2[7:0]), .test_db_high (test_db_high), .test_db_low (test_db_low) ); reg_file reg_file_( .reg_sel_sys_lo (reg_sel_sys_lo), .reg_sel_gp_lo (reg_sel_gp_lo), .reg_sel_sys_hi (reg_sel_sys_hi), .reg_sel_gp_hi (reg_sel_gp_hi), .reg_sel_ir (reg_sel_ir), .reg_sel_pc (reg_sel_pc), .ctl_sw_4u (ctl_sw_4u), .reg_sel_wz (reg_sel_wz), .reg_sel_sp (reg_sel_sp), .reg_sel_iy (reg_sel_iy), .reg_sel_ix (reg_sel_ix), .reg_sel_hl2 (reg_sel_hl2), .reg_sel_hl (reg_sel_hl), .reg_sel_de2 (reg_sel_de2), .reg_sel_de (reg_sel_de), .reg_sel_bc2 (reg_sel_bc2), .reg_sel_bc (reg_sel_bc), .reg_sel_af2 (reg_sel_af2), .reg_sel_af (reg_sel_af), .reg_gp_we (reg_gp_we), .reg_sys_we_lo (reg_sys_we_lo), .reg_sys_we_hi (reg_sys_we_hi), .ctl_reg_in_hi (ctl_reg_in_hi), .ctl_reg_in_lo (ctl_reg_in_lo), .ctl_reg_out_lo (ctl_reg_out_lo), .ctl_reg_out_hi (ctl_reg_out_hi), .clk (clk), .reg_sw_4d_lo (reg_sw_4d_lo), .reg_sw_4d_hi (reg_sw_4d_hi), .db_hi_as (db_hi_as[7:0]), .db_hi_ds (db2[7:0]), .db_lo_as (db_lo_as[7:0]), .db_lo_ds (db1[7:0]) ); reg_control reg_control_( .ctl_reg_exx (ctl_reg_exx), .ctl_reg_ex_af (ctl_reg_ex_af), .ctl_reg_ex_de_hl (ctl_reg_ex_de_hl), .ctl_reg_use_sp (ctl_reg_use_sp), .nreset (nreset), .ctl_reg_sel_pc (ctl_reg_sel_pc), .ctl_reg_sel_ir (ctl_reg_sel_ir), .ctl_reg_sel_wz (ctl_reg_sel_wz), .ctl_reg_gp_we (ctl_reg_gp_we), .ctl_reg_not_pc (ctl_reg_not_pc), .use_ixiy (use_ixiy), .use_ix (use_ix), .ctl_reg_sys_we_lo (ctl_reg_sys_we_lo), .ctl_reg_sys_we_hi (ctl_reg_sys_we_hi), .ctl_reg_sys_we (ctl_reg_sys_we), .clk (clk), .ctl_sw_4d (ctl_sw_4d), .nhold_clk_wait (nhold_clk_wait), .ctl_reg_gp_hilo (ctl_reg_gp_hilo), .ctl_reg_gp_sel (ctl_reg_gp_sel), .ctl_reg_sys_hilo (ctl_reg_sys_hilo), .reg_sel_bc (reg_sel_bc), .reg_sel_bc2 (reg_sel_bc2), .reg_sel_ix (reg_sel_ix), .reg_sel_iy (reg_sel_iy), .reg_sel_de (reg_sel_de), .reg_sel_hl (reg_sel_hl), .reg_sel_de2 (reg_sel_de2), .reg_sel_hl2 (reg_sel_hl2), .reg_sel_af (reg_sel_af), .reg_sel_af2 (reg_sel_af2), .reg_sel_wz (reg_sel_wz), .reg_sel_pc (reg_sel_pc), .reg_sel_ir (reg_sel_ir), .reg_sel_sp (reg_sel_sp), .reg_sel_gp_hi (reg_sel_gp_hi), .reg_sel_gp_lo (reg_sel_gp_lo), .reg_sel_sys_lo (reg_sel_sys_lo), .reg_sel_sys_hi (reg_sel_sys_hi), .reg_gp_we (reg_gp_we), .reg_sys_we_lo (reg_sys_we_lo), .reg_sys_we_hi (reg_sys_we_hi), .reg_sw_4d_lo (reg_sw_4d_lo), .reg_sw_4d_hi (reg_sw_4d_hi) ); address_latch address_latch_( .ctl_inc_cy (ctl_inc_cy), .ctl_inc_dec (ctl_inc_dec), .ctl_al_we (ctl_al_we), .ctl_inc_limit6 (ctl_inc_limit6), .ctl_bus_inc_oe (ctl_bus_inc_oe), .clk (clk), .ctl_apin_mux (ctl_apin_mux), .ctl_apin_mux2 (ctl_apin_mux2), .clrpc (clrpc), .nreset (nreset), .address_is_1 (address_is_1), .abus ({db_hi_as[7:0], db_lo_as[7:0]}), .address (address) ); bus_control bus_control_( .ctl_bus_ff_oe (ctl_bus_ff_oe), .ctl_bus_zero_oe (ctl_bus_zero_oe), .db (db0[7:0]) ); bus_switch bus_switch_( .ctl_sw_1u (ctl_sw_1u), .ctl_sw_1d (ctl_sw_1d), .ctl_sw_2u (ctl_sw_2u), .ctl_sw_2d (ctl_sw_2d), .ctl_sw_mask543_en (ctl_sw_mask543_en), .bus_sw_1u (bus_sw_1u), .bus_sw_1d (bus_sw_1d), .bus_sw_2u (bus_sw_2u), .bus_sw_2d (bus_sw_2d), .bus_sw_mask543_en (bus_sw_mask543_en) ); ================================================ FILE: cpu/toplevel/fuse/README ================================================ These files are part of the Fuse emulator Z80 test vectors: http://fuse-emulator.sourceforge.net/ File formats ============ tests.in -------- Each test has the format: AF BC DE HL AF' BC' DE' HL' IX IY SP PC I R IFF1 IFF2 IM specifies whether the Z80 is halted. specifies the number of tstates to run the test for, in decimal; the number actually executed may be higher, as the final instruction is allowed to complete. Then followed by lines specifying the initial memory setup. Each has the format: ... -1 eg 1234 56 78 9a -1 says to put 0x56 at 0x1234, 0x78 at 0x1235 and 0x9a at 0x1236. Finally, -1 to end the test. Blank lines may follow before the next test. tests.expected -------------- Each test output starts with the test description, followed by a list of 'events': each has the format