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For\nthe avoidance of doubt, this paragraph does not form part of the\npublic licenses.\n\nCreative Commons may be contacted at creativecommons.org.\n\n" }, { "path": "Make.rules", "content": "TEXLIB=$(TOP)/texlib\n\n# BEFORE including this file, you must define: TEXPATH\n\n\n# This only works if there is at least one tag in the git repo\n#GIT_SHOW_FORMAT=%ae %ci\nGIT_SHOW_FORMAT=%ci\nLATEXFLAGS=\"\\newcommand\\GitFileName{\"`pwd | sed -e 's|^.*rvalp/|\\\\\\textasciitilde/rvalp/|'`/\"}\\newcommand\\GitDescription{\"`git describe --long --dirty; git show -s --format='$(GIT_SHOW_FORMAT)';`\"}\\newcommand\\GitRevision{\"`git describe --long --dirty`\"}\\input{$<}\"\n\nLATEX_CLEANFILES = *.aux *.log *.dvi *.toc *.lof *.bbl *.blg *.ind *.ilg *.idx *.glo *.glg *.gls *.glsdefs *.out *.ist *.brf\n\n.SUFFIXES: .tex .pdf .eps .fig .dot .png\n\n.tex.pdf:\n\t\t( export TEXINPUTS=$(TEXPATH):$(TEXLIB)::; \\\n\t\tBIBINPUTS=${TEXINPUTS}; export BIBINPUTS; \\\n\t\tpdflatex $(LATEXFLAGS) $<; \\\n\t\tcp $@ out-$@; \\\n\t\tbibtex ${<:.tex=}; \\\n\t\tmakeindex -s $(TEXLIB)/index.ist ${<:.tex=}; \\\n\t\tpdflatex $(LATEXFLAGS) $<; \\\n\t\tcp $@ out-$@; \\\n\t\tpdflatex $(LATEXFLAGS) $<;\\\n\t\tcp $@ out-$@; )\n\n#makeglossaries ${<:.tex=}; \\\n\n.fig.eps:\n\tfig2dev -L eps $< > $@\n\n.fig.pdf:\n\tfig2dev -L pdftex $< > $@\n\n\n# Rules for converting dot files into png files\n.dot.png:\n\tdot -Tpng -o $@ $<\n\n.dot.pdf:\n\tdot -Tpdf -o $@ $<\n\n\n\n# Rules for walking a tree of Makefiles\n# Add a prefix to each directory name to make unique versions for all, clean,...\nCLEAN_DIRS=$(SUBDIRS:%=clean-%)\nALL_DIRS=$(SUBDIRS:%=all-%)\n\n.PHONY: all clean world doc $(CLEAN_DIRS) $(ALL_DIRS) \n\nall:: $(ALL_DIRS)\n\nclean:: $(CLEAN_DIRS)\n\n# for each dir, do a make all\n$(ALL_DIRS)::\n\t$(MAKE) -C $(@:all-%=%) all\n\n# for each dir, do a make clean\n$(CLEAN_DIRS)::\n\t$(MAKE) -C $(@:clean-%=%) clean\n\nworld:: clean all\n" }, { "path": "Makefile", "content": "TOP=.\n\nSUBDIRS=book\n\ninclude $(TOP)/Make.rules\n" }, { "path": "README.md", "content": "# rvalp\n\nRISC-V Assembly Language Programming\n\nThis is an attempt to create a book on RISC-V programming in assembly language.\n\nSee the Releases page for pre-made PDF versions: https://github.com/johnwinans/rvalp/releases\n\nPull requests are welcome.\n\nI will release PDFs after useful improvements from time to time into the releases area for those \nthat don't wish to build their own.\n\nYou can find the rvddt simulator mentioned in the text here: https://github.com/johnwinans/rvddt\n \nI developed this using LaTeX via texlive. LaTeX is very portable. You should \nbe able to tinker with it on most any platform. \n\nOn Ubuntu 20.04 and 18.04 LTS, loading the following packages worked for me:\n\n\tsudo apt install make \n\tsudo apt install git\n\tsudo apt install texlive-latex-extra\n\nI suspect the same (above) would work on 16.04 as well.\n\nThen clone and build this repo:\n\n git clone https://github.com/johnwinans/rvalp.git\n cd rvalp\n make world\n\n# Related Projects\n\nThe RISC-V simulator that I use to generate figures: https://github.com/johnwinans/rvddt\n\nA RISC-V simulator with more advanced features (but is also more complicated): https://github.com/johnwinans/riscv-toolchain-install-guide\n\nThe toolchain used to assemble and compile programs in this book: https://github.com/riscv/riscv-gnu-toolchain\n\n\nSee Appendix A of rvalp for the precise details on how I downloaded and build each of these tools on Linux.\n\nNote: During the great on-line COVID school year I recorded some lectures \non RISC-V that use this book as a reference. \nThese lectures appear in the following YouTube playlists:\n\n* [RISC-V Lectures From NIU CSCI 463](https://www.youtube.com/playlist?list=PL3by7evD3F53Dz2RiB47Ztp9l_piGVuus)\n* [The Whole NIU CSCI 463 Spring 2021 Playlist](https://www.youtube.com/playlist?list=PL3by7evD3F50NMukhaMqNdOt4pUHXT2Vo)\n" }, { "path": "book/.gitignore", "content": "rvalp.aux\nrvalp.brf\nrvalp.idx\nrvalp.ilg\nrvalp.ind\nrvalp.lof\nrvalp.log\nrvalp.pdf\nrvalp.toc\nrvalp.bbl\nrvalp.blg\nrvalp.out\n*.aux\nrvalp.glg\nrvalp.glo\nrvalp.gls\nrvalp.glsdefs\nrvalp.ist\n*.bak\nout-rvalp.pdf\n" }, { "path": "book/Makefile", "content": "SUBDIRS=\n#\tprograms/src\n\nTOP=..\ninclude $(TOP)/Make.rules\n\nTEXPATH=float:intro:rv32:copyright:license:elements:binary:programs/src\n\nall:: rvalp.pdf\n\nclean::\n\trm -f rvalp.pdf */*.aux $(LATEX_CLEANFILES)\n\nrvalp.pdf:: *.tex bibliography.bib\n\nspell:\n\t#find . -name \"*.tex\" -exec aspell --lang=en --mode=tex check \"{}\" \\;\n\tfind . -name \"*.tex\" -exec aspell --mode=tex check \"{}\" \\;\n" }, { "path": "book/amodes/chapter.tex", "content": "\\chapter{Addressing Modes}\n\n\nA box showing +/- 2KB regions for \\reg{gp} addressing with \nLB, LBU, SB, LH, LHU, SH, LW, and SW instructions.\n\n\\BeginTikzPicture\n\t\\draw(1.5,0) node{.data};\n\t\\draw[->] (3,0) -- (4,0);\t\t% right arrow\n\n\t\\draw(2,10) node{gp};\n\t\\draw[->] (3,10) -- (4,10);\t\t% right arrow\n\n\n%\t\\draw(0,15) node{+2KB};\n%\t\\draw(0,5) node{-2KB};\n\t\\draw[->] (6,9) -- (6,1);\t\t% up arrow\n\t\\draw[->] (6,11) -- (6,19);\t\t% down arrow\n\n\n\t\\draw(6,20) node{\\tt 0x8fff};\n\t\\draw(6,10) node{\\tt 0x8800};\n\t\\draw(6,0) node{\\tt 0x8000};\n\\EndTikzPicture\n\n" }, { "path": "book/ascii/chapter.tex", "content": "\\chapter{The ASCII Character Set}\n\\label{chapter:ascii}\n\\index{ASCII}\n\nA slightly abridged version of the Linux ``ASCII'' man(1) page.\n\n\\section{NAME}\n\nascii - ASCII character set encoded in octal, decimal, and hexadecimal\n\n\\section{DESCRIPTION}\n\n ASCII is the American Standard Code for Information Interchange. It is\n a 7-bit code. Many 8-bit codes (e.g., ISO 8859-1) contain ASCII as\n their lower half. The international counterpart of ASCII is known as\n ISO 646-IRV.\n\n The following table contains the 128 ASCII characters.\n\n C program '\\verb@\\X@' escapes are noted.\n\n\\begin{verbatim}\n Oct Dec Hex Char Oct Dec Hex Char\n ------------------------------------------------------------------------\n 000 0 00 NUL '\\0' (null character) 100 64 40 @\n 001 1 01 SOH (start of heading) 101 65 41 A\n 002 2 02 STX (start of text) 102 66 42 B\n 003 3 03 ETX (end of text) 103 67 43 C\n 004 4 04 EOT (end of transmission) 104 68 44 D\n 005 5 05 ENQ (enquiry) 105 69 45 E\n 006 6 06 ACK (acknowledge) 106 70 46 F\n 007 7 07 BEL '\\a' (bell) 107 71 47 G\n 010 8 08 BS '\\b' (backspace) 110 72 48 H\n 011 9 09 HT '\\t' (horizontal tab) 111 73 49 I\n 012 10 0A LF '\\n' (new line) 112 74 4A J\n 013 11 0B VT '\\v' (vertical tab) 113 75 4B K\n 014 12 0C FF '\\f' (form feed) 114 76 4C L\n 015 13 0D CR '\\r' (carriage ret) 115 77 4D M\n 016 14 0E SO (shift out) 116 78 4E N\n 017 15 0F SI (shift in) 117 79 4F O\n 020 16 10 DLE (data link escape) 120 80 50 P\n 021 17 11 DC1 (device control 1) 121 81 51 Q\n 022 18 12 DC2 (device control 2) 122 82 52 R\n 023 19 13 DC3 (device control 3) 123 83 53 S\n 024 20 14 DC4 (device control 4) 124 84 54 T\n 025 21 15 NAK (negative ack.) 125 85 55 U\n 026 22 16 SYN (synchronous idle) 126 86 56 V\n 027 23 17 ETB (end of trans. blk) 127 87 57 W\n 030 24 18 CAN (cancel) 130 88 58 X\n 031 25 19 EM (end of medium) 131 89 59 Y\n 032 26 1A SUB (substitute) 132 90 5A Z\n 033 27 1B ESC (escape) 133 91 5B [\n 034 28 1C FS (file separator) 134 92 5C \\ '\\\\'\n 035 29 1D GS (group separator) 135 93 5D ]\n 036 30 1E RS (record separator) 136 94 5E ^\n 037 31 1F US (unit separator) 137 95 5F _\n 040 32 20 SPACE 140 96 60 `\n 041 33 21 ! 141 97 61 a\n 042 34 22 \" 142 98 62 b\n 043 35 23 # 143 99 63 c\n 044 36 24 $ 144 100 64 d\n 045 37 25 % 145 101 65 e\n 046 38 26 & 146 102 66 f\n 047 39 27 ' 147 103 67 g\n 050 40 28 ( 150 104 68 h\n 051 41 29 ) 151 105 69 i\n 052 42 2A * 152 106 6A j\n 053 43 2B + 153 107 6B k\n 054 44 2C , 154 108 6C l\n 055 45 2D - 155 109 6D m\n 056 46 2E . 156 110 6E n\n 057 47 2F / 157 111 6F o\n 060 48 30 0 160 112 70 p\n 061 49 31 1 161 113 71 q\n 062 50 32 2 162 114 72 r\n 063 51 33 3 163 115 73 s\n 064 52 34 4 164 116 74 t\n 065 53 35 5 165 117 75 u\n 066 54 36 6 166 118 76 v\n 067 55 37 7 167 119 77 w\n 070 56 38 8 170 120 78 x\n 071 57 39 9 171 121 79 y\n 072 58 3A : 172 122 7A z\n 073 59 3B ; 173 123 7B {\n 074 60 3C < 174 124 7C |\n 075 61 3D = 175 125 7D }\n 076 62 3E > 176 126 7E ~\n 077 63 3F ? 177 127 7F DEL\n\\end{verbatim}\n\n\\subsection{Tables}\nFor convenience, below are more compact tables in hex and decimal.\n\n\\begin{verbatim}\n 2 3 4 5 6 7 30 40 50 60 70 80 90 100 110 120\n ------------- ---------------------------------\n 0: 0 @ P ` p 0: ( 2 < F P Z d n x\n 1: ! 1 A Q a q 1: ) 3 = G Q [ e o y\n 2: \" 2 B R b r 2: * 4 > H R \\ f p z\n 3: # 3 C S c s 3: ! + 5 ? I S ] g q {\n 4: $ 4 D T d t 4: \" , 6 @ J T ^ h r |\n 5: % 5 E U e u 5: # - 7 A K U _ i s }\n 6: & 6 F V f v 6: $ . 8 B L V ` j t ~\n 7: ' 7 G W g w 7: % / 9 C M W a k u DEL\n 8: ( 8 H X h x 8: & 0 : D N X b l v\n 9: ) 9 I Y i y 9: ' 1 ; E O Y c m w\n A: * : J Z j z\n B: + ; K [ k {\n C: , < L \\ l |\n D: - = M ] m }\n E: . > N ^ n ~\n F: / ? O _ o DEL\n\\end{verbatim}\n\n\\section{NOTES}\n\\subsection{History}\n\n An ascii manual page appeared in Version 7 of AT\\&T UNIX.\n\n On older terminals, the underscore code is displayed as a left arrow,\n called backarrow, the caret is displayed as an up-arrow and the \nvertical bar has a hole in the middle.\n\n Uppercase and lowercase characters differ by just one bit and the ASCII\n character 2 differs from the double quote by just one bit, too. That\n made it much easier to encode characters mechanically or with a \nnon-microcontroller-based electronic keyboard and that pairing was found on\n old teletypes.\n\n The ASCII standard was published by the United States of America \nStandards Institute (USASI) in 1968.\n\n\\section{COLOPHON}\n\n This page is part of release 4.04 of the Linux man-pages project. A\n description of the project, information about reporting bugs, and the\n latest version of this page, can be found at\n \\url{http://www.kernel.org/doc/man-pages/}.\n" }, { "path": "book/bibliography.bib", "content": "@string{IETF=\"Internet Engineering Task Force\"}\n\n@manual{rvismv1v22:2017,\n\ttitle = \"\\href{https://github.com/riscv/riscv-isa-manual}{The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Document Version 2.2}\",\n\torganization = \"\\href{https://riscv.org/}{RISC-V Foundation}\",\n\tyear = 2017,\n\tmonth = {May},\n\tnote\t\t = {Editors Andrew Waterman and Krste Asanovi\\'c}\n}\n\n@manual{rvismv2:2017,\n\ttitle = \"\\href{https://github.com/riscv/riscv-isa-manual}{The RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Document Version 1.10}\",\n\torganization = \"\\href{https://riscv.org/}{RISC-V Foundation}\",\n\tyear = 2017,\n\tmonth = {May},\n\tnote\t\t = {Editors Andrew Waterman and Krste Asanovi\\'c}\n}\n\n\n@manual{rvpsabi:2017,\n\ttitle\t\t= \"\\href{https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md}{RISC-V ELF psABI specification}\",\n\tauthor\t\t= {Palmer Dabbelt and Stefan O'Rear and Kito Cheng and Andrew Waterman and Michael Clark and Alex Bradbury and David Horner and Max Nordlund and Karsten Merker},\n\tyear\t\t= 2017\n\t\n}\n\n\n@book{riscvreader:2017,\n\ttitle\t\t\t= {The RISC-V Reader: An Open Architecture Atlas},\n\tauthor\t\t\t= {David Patterson and Andrew Waterman},\n\tpublisher\t\t= {Strawberry Canyon},\n\tmonth\t\t\t= {Nov},\n\tyear\t\t\t= 2017,\n\tnote\t\t\t= {ISBN: 978-0999249116}\n}\n\n@book{codriscv:2017,\n\ttitle\t\t\t= {Computer Organization and Design RISC-V Edition: The Hardware Software Interface},\n\tauthor\t\t\t= {David Patterson and John Hennessy},\n\tpublisher\t\t= {Morgan Kaufmann},\n\tmonth\t\t\t= {Apr},\n\tyear\t\t\t= 2017,\n\tnote\t\t\t= {ISBN: 978-0128122754}\n}\n\n@book{gcc:2017,\n\ttitle = \"\\href{https://gcc.gnu.org/onlinedocs/}{Using the GNU Compiler Collection (For GCC version 7.3.0)}\",\n\tauthor\t\t = {Richard M. Stallman and the GCC Developer Community},\n\tpublisher\t = {GNU Press},\n\taddress\t\t = {Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA},\n\tyear = 2017\n}\n\n\n@article{Decker:1985:MAT:989369.989375,\n author = {Decker, William F.},\n title = {A Modern Approach to Teaching Computer Organization and Assembly Language Programming},\n journal = {SIGCSE Bull.},\n issue_date = {December 1985},\n volume = {17},\n number = {4},\n month = {Dec},\n year = {1985},\n issn = {0097-8418},\n pages = {38--44},\n numpages = {7},\n url = {http://doi.acm.org/10.1145/989369.989375},\n doi = {10.1145/989369.989375},\n acmid = {989375},\n publisher = {ACM},\n address = {New York, NY, USA}\n}\n\n\n@manual{mcs85:1978,\n\ttitle = {MCS-85 User's Manual},\n\torganization = {Intel},\n\tmonth = {Sep},\n\tyear = 1978\n}\n\n@manual{edtasm:1978,\n\ttitle = {TRS-80 Editor/Assembler Operation and Reference Manual},\n\torganization = {Radio Shack},\n\tyear = 1978\n}\n\n@manual{mc68000:1980,\n\ttitle = {MC68000 16--bit Microprocessor User's Manual},\n\tedition\t\t = {2nd},\n\torganization = {Motorola},\n\tmonth\t\t = {Jan},\n\tyear = 1980,\n\tnote\t\t = {MC68000UM(AD2)}\n}\n@manual{ns32k:1986,\n\ttitle = {Series 32000 Databook},\n\torganization = {National Semiconductor Coprporation},\n\tyear = 1986\n}\n\n@book{assist:1983,\n\ttitle = {Assembler Language With ASSIST},\n\tauthor\t\t = {Ross A. Overbeek and W. E. Singletary},\n\tedition\t\t = {2nd},\n\tpublisher\t = {Science Research Associates, Inc.},\n\tyear = 1983\n}\n\n@manual{poo:1980,\n title\t\t\t= {IBM System/370 Principals of Operation},\n\tedition\t\t\t= {7th},\n organization\t= {IBM},\n\tmonth\t\t\t= {Mar},\n year\t\t\t= 1980\n}\n\n@manual{assembler370:1979,\n title\t\t\t= {OS/VS-DOS/VSE-VM/370 Assembler Language},\n\tedition\t\t\t= {6th},\n organization\t= {IBM},\n\tmonth\t\t\t= {Mar},\n year\t\t\t= 1979\n}\n\n\n@manual{ttl74154:1979,\n\ttitle\t\t\t= \"\\href{http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=sdls056&fileType=pdf}{SN54154, SN74154 4--line to 16--line Decoders/Demultiplexers}\",\n\torganization\t= {Texas Instruments},\n\tmonth\t\t\t= {Dec},\n\tyear\t\t\t= 1972\n}\n\n@manual{ttl74191:1979,\n\ttitle\t\t\t= \"\\href{http://www.ti.com/lit/ds/symlink/sn74ls191.pdf}{SN54190, SN54191, SN54LS190, SN54LS191, SN74190, SN74191, SN74LS190, SN74LS191 Synchronous Up/Down Counters With Down/Up Mode Control}\",\n\torganization\t= {Texas Instruments},\n\tmonth\t\t\t= {Mar},\n\tyear\t\t\t= 1988\n}\n\n\n\n@Misc{IEN137,\n author = \"Danny Cohen\",\n title = \"\\href{http://www.ietf.org/rfc/ien/ien137.txt}{IEN 137, On Holy Wars and a Plea for Peace}\",\n month = {Apr},\n year = \"1980\",\n note = \"This note discusses the Big-Endian/Little-Endian\n byte/bit-order controversy, but did not settle it. A\n decade later, David V. James in ``Multiplexed Buses:\n The Endian Wars Continue'', {\\em IEEE Micro}, {\\bf\n 10}(3), 9--21 (1990) continued the discussion.\",\n%%% URL = \"http://www.ietf.org/rfc/ien/ien137.txt\",\n}\n\n\n@misc{subtrahend,\n title = {Definition of Subtrahend},\n howpublished = {\\href{https://www.mathsisfun.com/definitions/subtrahend.html}{www.mathsisfun.com/definitions/subtrahend.html}},\n note = {Accessed: 2018-06-02}\n}\n\n@article{ieee:754,\n author={},\n journal={IEEE Std 754-2019 (Revision of IEEE 754-2008)}, \n title={IEEE Standard for Floating-Point Arithmetic}, \n year={2019},\n volume={},\n number={},\n pages={1-84},}\n\n\n@manual{zilog:1977,\n title = {Z80 Assembly Language Programming Manual},\n organization = {Zilog Inc.},\n\tmonth\t\t\t= {Jan},\n year = 1977\n}\n\n\n@book{leventhal:1979,\n title = {Z80 Assembly Language Programming},\n author = {Lance A. Leventhal},\n publisher = {Osborne/McGraw-Hill},\n year = 1979\n}\n\n" }, { "path": "book/binary/chapter.tex", "content": "\\chapter{Numbers and Storage Systems}\n\\label{chapter:numbers}\n\nThis chapter discusses how data are represented and stored in a computer.\n\nIn the context of computing, {\\em boolean} refers to a condition that can \nbe either true or false and {\\em binary} refers to the use of a base-2 \nnumeric system to represent numbers.\n\nRISC-V assembly language uses binary to represent all values, be they \nboolean or numeric. It is the context within which they are used that\ndetermines whether they are boolean or numeric.\n\n\\enote{Add some diagrams here showing bits, bytes and the MSB, \nLSB,\\ldots\\ perhaps relocated from the RV32I chapter?}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\section{Boolean Functions}\n\nBoolean functions apply on a per-bit basis.\nWhen applied to multi-bit values, each bit position is operated upon \nindependent of the other bits.\n\nRISC-V assembly language uses zero to represent {\\em false} and one \nto represent {\\em true}. In general, however, it is useful to relax \nthis and define zero {\\bf and only zero} to be {\\em false} and anything \nthat is not {\\em false} is therefore {\\em true}.%\n\\footnote{This is how {\\em true} and {\\em false} behave in C, C++, and\nmany other languages as well as the common assembly language idioms\ndiscussed in this text.}\n\nThe reason for this relaxation is to describe the common case \nwhere the CPU processes data, multiple \\gls{bit}s at-a-time.\n\nThese\ngroups have names like \\gls{byte} (8 bits), \\gls{halfword} (16 bits) \nand \\gls{fullword} (32 bits).\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{NOT}\n\nThe {\\em NOT} operator applies to a single operand and represents the \nopposite of the input.\n\\enote{Need to define unary, binary and ternary operators without \nconfusing binary operators with binary numbers.}\n\nIf the input is 1 then the output is 0. If the input is 0 then the\noutput is 1. In other words, the output value is {\\em not} that of the \ninput value.\n\nExpressing the {\\em not} function in the form of a truth table:\n\n\\begin{center}\n\\begin{tabular}{c|c}\nA & $\\overline{\\mbox{A}}$\\\\\n\\hline\n0 & 1 \\\\\n1 & 0 \\\\\n\\end{tabular}\n\\end{center}\n\nA truth table is drawn by indicating all of the possible input values on \nthe left of the vertical bar with each row displaying the output values \nthat correspond to the input for that row. The column headings are used\nto define the illustrated operation expressed using a mathematical \nnotation. The {\\em not} operation is indicated by the presence of\nan {\\em overline}.\n\nIn computer programming languages, things like an overline can not be \nefficiently expressed using a standard keyboard. Therefore it is common \nto use a notation such as that used by the C language when discussing \nthe {\\em NOT} operator in symbolic form. Specifically the tilde: `\\verb@~@'.\n\nIt is also uncommon to for programming languages to express boolean operations \non single-bit input(s). A more generalized operation is used that applies \nto a set of bits all at once. For example, performing a {\\em not} operation\nof eight bits at once can be illustrated as:\n\n\n\\begin{verbatim}\n ~ 1 1 1 1 0 1 0 1 <== A\n -----------------\n 0 0 0 0 1 0 1 0 <== output\n\\end{verbatim}\n\nIn a line of code the above might read like this: \\verb@output = ~A@\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{AND}\n\nThe boolean {\\em and} function has two or more inputs and the output is a\nsingle bit. The output is 1 if and only if all of the input values are 1.\nOtherwise it is 0.\n\nThis function works like it does in spoken language. For example\nif A is 1 {\\em and} B is 1 then the output is 1 (true).\nOtherwise the output is 0 (false). \n\nIn mathematical notion, the {\\em and} operator is expressed the same way\nas is {\\em multiplication}. That is by a raised dot between, or by \njuxtaposition of, two variable names. It is also worth noting that,\nin base-2, the {\\em and} operation actually {\\em is} multiplication!\n\n\\begin{center}\n\\begin{tabular}{cc|c}\nA & B & AB \\\\\n\\hline\n0 & 0 & 0 \\\\\n0 & 1 & 0 \\\\\n1 & 0 & 0 \\\\\n1 & 1 & 1 \\\\\n\\end{tabular}\n\\end{center}\n\nThis text will use the operator used in the C language when discussing \nthe {\\em and} operator in symbolic form. Specifically the ampersand: `\\verb@&@'.\n\nAn eight-bit example:\n\n\\begin{verbatim}\n 1 1 1 1 0 1 0 1 <== A\n & 1 0 0 1 0 0 1 1 <== B\n -----------------\n 1 0 0 1 0 0 0 1 <== output\n\\end{verbatim}\n\nIn a line of code the above might read like this: \\verb@output = A & B@\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{OR}\n\nThe boolean {\\em or} function has two or more inputs and the output is a\nsingle bit. The output is 1 if at least one of the input values are 1.\n\nThis function works like it does in spoken language. For example\nif A is 1 {\\em or} B is 1 then the output is 1 (true).\nOtherwise the output is 0 (false). \n\nIn mathematical notion, the {\\em or} operator is expressed using the plus \n($+$). \n\n\\begin{center}\n\\begin{tabular}{cc|c}\nA & B & A$+$B \\\\\n\\hline\n0 & 0 & 0 \\\\\n0 & 1 & 1 \\\\\n1 & 0 & 1 \\\\\n1 & 1 & 1 \\\\\n\\end{tabular}\n\\end{center}\n\nThis text will use the operator used in the C language when discussing\nthe {\\em or} operator in symbolic form. Specifically the pipe: `\\verb@|@'.\n\nAn eight-bit example:\n\n\\begin{verbatim}\n 1 1 1 1 0 1 0 1 <== A\n | 1 0 0 1 0 0 1 1 <== B\n -----------------\n 1 1 1 1 0 1 1 1 <== output\n\\end{verbatim}\n\nIn a line of code the above might read like this: \\verb@output = A | B@\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{XOR}\n\nThe boolean {\\em exclusive or} function has two or more inputs and the \noutput is a single bit. The output is 1 if only an odd number of inputs \nare 1. Otherwise the output will be 0.\n\nNote that when {\\em xor} is used with two inputs, the output\nis set to 1 (true) when the inputs have different values and 0 \n(false) when the inputs both have the same value.\n\nIn mathematical notion, the {\\em xor} operator is expressed using the plus\nin a circle ($\\oplus$).\n\n\\begin{center}\n\\begin{tabular}{cc|c}\nA & B & A$\\oplus{}$B \\\\\n\\hline\n0 & 0 & 0 \\\\\n0 & 1 & 1 \\\\\n1 & 0 & 1 \\\\\n1 & 1 & 0 \\\\\n\\end{tabular}\n\\end{center}\n\nThis text will use the operator used in the C language when discussing\nthe {\\em xor} operator in symbolic form. Specifically the carrot: `\\verb@^@'.\n\n\nAn eight-bit example:\n\n\\begin{verbatim}\n 1 1 1 1 0 1 0 1 <== A\n ^ 1 0 0 1 0 0 1 1 <== B\n -----------------\n 0 1 1 0 0 1 1 0 <== output\n\\end{verbatim}\n\nIn a line of code the above might read like this: \\verb@output = A ^ B@\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\section{Integers and Counting}\n\nA binary integer is constructed with only 1s and 0s in the same\nmanner as decimal numbers are constructed with values from 0 to 9.\n\nCounting in binary (base-2) uses the same basic rules as decimal (base-10). \nThe difference is when we consider that there are ten decimal digits and \nonly two binary digits. Therefore, in base-10, we must carry when adding one to \nnine (because there is no digit representing a ten) and, in base-2, we must \ncarry when adding one to one (because there is no digit representing a two.)\n\n\\autoref{Figure:integers} shows an abridged table of the decimal, binary and \nhexadecimal values ranging from $0_{10}$ to $128_{10}$.\n\n\\begin{figure}[t]\n\\begin{center}\n\\begin{tabular}{|c|c|c||c|c|c|c|c|c|c|c||c|c|}\n\\hline\n\\multicolumn{3}{|c||}{Decimal} & \\multicolumn{8}{|c||}{Binary} & \\multicolumn{2}{|c|}{Hex}\\\\\n\\hline\n$10^2$\t& $10^1$\t& $10^0$\t& $2^7$ & $2^6$ & $2^5$ & $2^4$ & $2^3$ & $2^2$ & $2^1$ & $2^0$\t\t& $16^1$ & $16^0$\t\\\\\n\\hline\n100\t\t&\t10\t\t& 1\t\t\t& 128\t& 64\t& 32\t& 16\t& 8\t\t& 4\t\t& 2\t\t& 1\t\t\t& 16\t& 1\t\t\t\\\\\n\\hline \\hline\n0\t\t&\t0\t\t&\t0\t\t& 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0\t\t& 0 & 0 \\\\\n0\t\t&\t0\t\t&\t1\t\t& 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1\t\t& 0 & 1 \\\\\n0\t\t&\t0\t\t&\t2\t\t& 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0\t\t& 0 & 2 \\\\\n0\t\t&\t0\t\t&\t3\t\t& 0 & 0 & 0 & 0 & 0 & 0 & 1 & 1\t\t& 0 & 3 \\\\\n0\t\t&\t0\t\t&\t4\t\t& 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0\t\t& 0 & 4 \\\\\n0\t\t&\t0\t\t&\t5\t\t& 0 & 0 & 0 & 0 & 0 & 1 & 0 & 1\t\t& 0 & 5 \\\\\n0\t\t&\t0\t\t&\t6\t\t& 0 & 0 & 0 & 0 & 0 & 1 & 1 & 0\t\t& 0 & 6 \\\\\n0\t\t&\t0\t\t&\t7\t\t& 0 & 0 & 0 & 0 & 0 & 1 & 1 & 1\t\t& 0 & 7 \\\\\n0\t\t&\t0\t\t&\t8\t\t& 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0\t\t& 0 & 8 \\\\\n0\t\t&\t0\t\t&\t9\t\t& 0 & 0 & 0 & 0 & 1 & 0 & 0 & 1\t\t& 0 & 9 \\\\\n0\t\t&\t1\t\t&\t0\t\t& 0 & 0 & 0 & 0 & 1 & 0 & 1 & 0\t\t& 0 & a \\\\\n0\t\t&\t1\t\t&\t1\t\t& 0 & 0 & 0 & 0 & 1 & 0 & 1 & 1\t\t& 0 & b \\\\\n0\t\t&\t1\t\t&\t2\t\t& 0 & 0 & 0 & 0 & 1 & 1 & 0 & 0\t\t& 0 & c \\\\\n0\t\t&\t1\t\t&\t3\t\t& 0 & 0 & 0 & 0 & 1 & 1 & 0 & 1\t\t& 0 & d \\\\\n0\t\t&\t1\t\t&\t4\t\t& 0 & 0 & 0 & 0 & 1 & 1 & 1 & 0\t\t& 0 & e \\\\\n0\t\t&\t1\t\t&\t5\t\t& 0 & 0 & 0 & 0 & 1 & 1 & 1 & 1\t\t& 0 & f \\\\\n0\t\t&\t1\t\t&\t6\t\t& 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0\t\t& 1 & 0 \\\\\n0\t\t&\t1\t\t&\t7\t\t& 0 & 0 & 0 & 1 & 0 & 0 & 0 & 1\t\t& 1 & 1 \\\\\n\\hline\n\\multicolumn{3}{|c||}{\\ldots} & \\multicolumn{8}{|c||}{\\ldots} & \\multicolumn{2}{|c|}{\\ldots}\\\\\n\\hline\n1 & 2 & 5\t\t& 0 & 1 & 1 & 1 & 1 & 1 & 0 & 1\t\t& 7 & d \\\\\n1 & 2 & 6\t\t& 0 & 1 & 1 & 1 & 1 & 1 & 1 & 0\t\t& 7 & e \\\\\n1 & 2 & 7\t\t& 0 & 1 & 1 & 1 & 1 & 1 & 1 & 1\t\t& 7 & f \\\\\n1 & 2 & 8\t\t& 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0\t\t& 8 & 0 \\\\\n\\hline\n\\end{tabular}\n\\end{center}\n\\captionof{figure}{Counting in decimal, binary and hexadecimal.}\n\\label{Figure:integers}\n\\end{figure}\n\nOne way to look at this table is on a per-row basis where each \n\\gls{place-value}\nis represented by the base raised to the power of the \\gls{place-value}\nposition (shown in the column headings.) \n%This is useful when converting arbitrary numeric values between bases. \nFor example to interpret the decimal value on the fourth row: \n\n\\begin{equation}\n0 \\times 10^2 + 0 \\times 10^1 + 3 \\times 10^0 = 3_{10}\n\\end{equation}\n\nInterpreting the binary value on the fourth row by converting it to decimal:\n\n\\begin{equation}\n0 \\times 2^7 + 0 \\times 2^6 +0 \\times 2^5 +0 \\times 2^4 +0 \\times 2^3 +0 \\times 2^2 + 1 \\times 2^1 + 1 \\times 2^0 = 3_{10}\n\\end{equation}\n\nInterpreting the hexadecimal value on the fourth row by converting it to decimal:\n\n\\begin{equation}\n0 \\times 16^1 + 3 \\times 16^0 = 3_{10}\n\\end{equation}\n\n\\index{Most significant bit}\\index{MSB|see {Most significant bit}}%\n\\index{Least significant bit}\\index{LSB|see {Least significant bit}}%\nWe refer to the place values with the largest exponent (the one furthest to the \nleft for any given base) as the most significant digit and the place value\nwith the lowest exponent as the least significant digit. For binary\nnumbers these are the \\acrfull{msb} and \\acrfull{lsb} respectively.%\n\\footnote{Changing the value of the MSB will have a more {\\em significant}\nimpact on the numeric value than changing the value of the LSB.} \n\n\nAnother way to look at this table is on a per-column basis. When\ntasked with drawing such a table by hand, it might be useful \nto observe that, just as in decimal, the right-most column will\ncycle through all of the values represented in the chosen base\nthen cycle back to zero and repeat. (For example, in binary this\npattern is 0-1-0-1-0-1-0-\\ldots) The next column in each base\nwill cycle in the same manner except each of the values is repeated\nas many times as is represented by the place value (in the case of \ndecimal, $10^1$ times, binary $2^1$ times, hex $16^1$ times. Again,\nthe binary numbers for this pattern are 0-0-1-1-0-0-1-1-\\ldots)\nThis continues for as many columns as are needed to represent the \nmagnitude of the desired number.\n\nAnother item worth noting is that any even binary number will always\nhave a 0 LSB and odd numbers will always have a 1 LSB.\n\nAs is customary in decimal, leading zeros are sometimes not shown \nfor readability.\n\nThe relationship between binary and hex values is also worth taking\nnote. Because $2^4 = 16$, there is a clean and simple grouping\nof 4 \\gls{bit}s to 1 \\gls{hit} (aka \\gls{nybble}). \nThere is no such relationship between binary and decimal. \n\nWriting and reading numbers in binary that are longer than 8 bits \nis cumbersome and prone to error. The simple conversion between \nbinary and hex makes hex a convenient shorthand for expressing \nbinary values in many situations. \n\nFor example, consider the following value expressed in binary, \nhexadecimal and decimal (spaced to show the relationship\nbetween binary and hex):\n\n\\begin{verbatim}\nBinary value: 0010 0111 1011 1010 1100 1100 1111 0101\nHex Value: 2 7 B A C C F 5\nDecimal Value: 666553589\n\\end{verbatim}\n\nEmpirically we can see that grouping the bits into sets of four\nallows an easy conversion to hex and expressing it as such is\n$\\frac{1}{4}$ as long as in binary while at the same time\nallowing for easy conversion back to binary.\n\nThe decimal value in this example does not easily convey a sense\nof the binary value.\n\n\\begin{tcolorbox}\nIn programming languages like the C, its derivatives and RISC-V \nassembly, numeric values are interpreted as decimal {\\bfseries unless} \nthey start with a zero (0). \nNumbers that start with 0 are interpreted as octal (base-8), \nnumbers starting with 0x are interpreted as hexadecimal and \nnumbers that start with 0b are interpreted as binary.\n\\end{tcolorbox}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{Converting Between Bases}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsubsection{From Binary to Decimal}\n\\label{section:bindec}\n\nIt is occasionally necessary to convert between decimal,\nbinary and/or hex.\n\nTo convert from binary to decimal, put the decimal value of the \\gls{place-value}s \n{\\ldots8, 4, 2, 1} over the binary digits like this:\n\n\\begin{verbatim}\nBase-2 place values: 128 64 32 16 8 4 2 1\nBinary: 0 0 0 1 1 0 1 1\nDecimal: 16 +8 +2 +1 = 27\n\\end{verbatim}\n\nNow sum the place-values that are expressed in decimal for each \nbit with the value of 1: $16+8+2+1$. The integer binary value\n$00011011_2$ represents the decimal value $27_{10}$.\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsubsection{From Binary to Hexadecimal}\n\\label{section:binhex}\n\nConversion from binary to hex involves grouping the bits into\nsets of four and then performing the same summing process as \nshown above. If there is not a multiple of four bits then\nextend the binary to the left with zeros to make it so.\n\nGrouping the bits into sets of four and summing:\n\n\\begin{verbatim}\nBase-2 place values: 8 4 2 1 8 4 2 1 8 4 2 1 8 4 2 1\nBinary: 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 0\nDecimal: 4+2 =6 8+4+ 1=13 8+ 2 =10 8+4+2 =14\n\\end{verbatim}\n\nAfter the summing, convert each decimal value to hex. The decimal\nvalues from 0--9 are the same values in hex. Because we don't have any\nmore numerals to represent the values from 10-15, we use the first 6\nletters (See the right-most column of \\autoref{Figure:integers}.)\nFortunately there are only six hex mappings involving letters. Thus \nit is reasonable to memorize them.\n\nContinuing this example:\n\n\\begin{verbatim}\nDecimal: 6 13 10 14\nHex: 6 D A E\n\\end{verbatim}\n\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsubsection{From Hexadecimal to Binary}\n\nThe four-bit mapping between binary and hex makes this\ntask as straight forward as using a look-up table to \ntranslate each \\gls{hit} (Hex digIT) it to its unique \nfour-bit pattern.\n\nPerform this task either by memorizing each of the 16 patterns \nor by converting each hit to decimal first and then converting\neach four-bit binary value to decimal using the place-value summing \nmethod discussed in \\autoref{section:bindec}.\n\nFor example:\n\n\\begin{verbatim}\nHex: 7 C\nDecimal Sum: 4+2+1=7 8+4 =12\nBinary: 0 1 1 1 1 1 0 0\n\\end{verbatim}\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsubsection{From Decimal to Binary}\n\nTo convert arbitrary decimal numbers to binary, extend the list \nof binary place values until it exceeds the value of the decimal \nnumber being converted. Then make successive subtractions of each \nof the place values that would yield a non-negative result.\n\nFor example, to convert $1234_{10}$ to binary:\n\n\n\\begin{verbatim}\nBase-2 place values: 2048-1024-512-256-128-64-32-16-8-4-2-1\n\n 0 2048 (too big)\n 1 1234 - 1024 = 210\n 0 512 (too big)\n 0 256 (too big)\n 1 210 - 128 = 82\n 1 82 - 64 = 18\n 0 32 (too big)\n 1 18 - 16 = 2\n 0 8 (too big)\n 0 4 (too big)\n 1 2 - 2 = 0\n 0 1 (too big)\n\\end{verbatim}\n\nThe answer using this notation is listed vertically\nin the left column with the \\acrshort{msb} on the top and \nthe \\acrshort{lsb} on the bottom line: $010011010010_2$.\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsubsection{From Decimal to Hex}\n\nConversion from decimal to hex can be done by using the place\nvalues for base-16 and the same math as from decimal to binary\nor by first converting the decimal value to binary and then\nfrom binary to hex by using the methods discussed above.\n\nBecause binary and hex are so closely related, performing\na conversion by way of binary is straight forward.\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{Addition of Binary Numbers}\n\nThe addition of binary numbers can be performed long-hand the\nsame way decimal addition is taught in grade school. In fact binary\naddition is easier since it only involves adding 0 or 1.\n\nThe first thing to note that in any number base $0+0=0$, $0+1=1$, and \n$1+0=1$. Since there is no ``two'' in binary (just like there is \nno ``ten'' decimal) adding $1+1$ results in a zero with a carry as\nin: $1+1=10_2$ and in: $1+1+1=11_2$. Using these five sums, any two\nbinary integers can be added.\n\n\\index{Full Adder}%\nThis truth table shows what is called a {\\em full adder}.\nA full adder is a function that can add three input bits \n(the two addends and a carry value from a ``prior column'')\nand produce the sum and carry output values.\\footnote{\nNote that the sum could be expressed in Boolean Algebra as:\n$sum = ci \\oplus{} a \\oplus{} b$}\n\n\\begin{center}\n\\begin{tabular}{|ccc|cc|}\n\\hline\n%\\multicolumn{3}{c}{input} & \\multicolumn{2}{c}{output}\\\\\n$ci$ & $a$ & $b$ & $co$ & $sum$\\\\\n\\hline\n 0 & 0 & 0 & 0 & 0 \\\\\n 0 & 0 & 1 & 0 & 1 \\\\\n 0 & 1 & 0 & 0 & 1 \\\\\n 0 & 1 & 1 & 1 & 0 \\\\\n 1 & 0 & 0 & 0 & 1 \\\\\n 1 & 0 & 1 & 1 & 0 \\\\\n 1 & 1 & 0 & 1 & 0 \\\\\n 1 & 1 & 1 & 1 & 1 \\\\\n\\hline\n\\end{tabular}\n\\end{center}\n\nAdding two unsigned binary numbers using 16 full adders:\n\n\\begin{verbatim}\n 111111 1111 <== carries\n 0110101111001111 <== addend\n + 0000011101100011 <== addend\n ------------------\n 0111001100110010 <== sum\n\\end{verbatim}\n\nNote that the carry ``into'' the LSB is zero.\n\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{Signed Numbers}\n\nThere are multiple methods used to represent signed binary integers.\nThe method used by most modern computers is called {\\em two's complement}.\n\nA two's complement number is encoded in such a manner as to simplify\nthe hardware used to add, subtract and compare integers. \n\nA simple method of thinking about two's complement numbers is to\nnegate the place value of the \\acrshort{msb}. For example, the \nnumber one is represented the same as discussed before:\n\n\\begin{verbatim}\nBase-2 place values: -128 64 32 16 8 4 2 1\nBinary: 0 0 0 0 0 0 0 1\n\\end{verbatim}\n\nThe \\acrshort{msb} of any negative number in this format will always\nbe 1. For example the value $-1_{10}$ is:\n\n\\begin{verbatim}\nBase-2 place values: -128 64 32 16 8 4 2 1\nBinary: 1 1 1 1 1 1 1 1\n\\end{verbatim}\n\n\\ldots because: $-128+64+32+16+8+4+2+1=-1$.\n\nThis format has the virtue of allowing the same addition logic discussed above to be \nused to calculate the sums of signed numbers as unsigned numbers.\n\nCalculating the signed addition: $4+5 = 9$\n\n\\begin{verbatim}\n 1 <== carries\n 000100 <== 4 = 0 + 0 + 0 + 4 + 0 + 0\n +000101 <== 5 = 0 + 0 + 0 + 4 + 0 + 1\n -------\n 001001 <== 9 = 0 + 0 + 8 + 0 + 0 + 1\n\\end{verbatim}\n\nCalculating the signed addition: $-4+ -5 = -9$\n\n\\begin{verbatim}\n 1 11 <== carries\n 111100 <== -4 = -32 + 16 + 8 + 4 + 0 + 0\n +111011 <== -5 = -32 + 16 + 8 + 0 + 2 + 1\n ---------\n 1 110111 <== -9 (with a truncation) = -32 + 16 + 4 + 2 + 1 = -9\n\\end{verbatim}\n\n\nCalculating the signed addition: $-1+1=0$\n\n\\begin{verbatim}\n -128 64 32 16 8 4 2 1 <== place value\n 1 1 1 1 1 1 1 1 <== carries\n 1 1 1 1 1 1 1 1 <== addend (-1)\n + 0 0 0 0 0 0 0 1 <== addend (1)\n ----------------------\n 1 0 0 0 0 0 0 0 0 <== sum (0 with a truncation)\n\\end{verbatim}\n\n{\\em In order for this to work, the carry out of the sum of the MSBs {\\bfseries must} be discarded.}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsubsection{Converting between Positive and Negative}\n\nChanging the sign on two's complement numbers can be described as\ninverting all of the bits (which is also known as the {\\em one's complement})\nand then add one.\n\nFor example, negating the number four:\n\n\\begin{minipage}{\\textwidth}\n\\begin{verbatim}\n -128 64 32 16 8 4 2 1\n 0 0 0 0 0 1 0 0 <== 4\n\n 1 1 <== carries\n 1 1 1 1 1 0 1 1 <== one's complement of 4\n + 0 0 0 0 0 0 0 1 <== plus 1\n ----------------------\n 1 1 1 1 1 1 0 0 <== -4\n\\end{verbatim}\n\\end{minipage}\n\nThis can be verified by adding 5 to the result and observe that\nthe sum is 1:\n\n\\begin{verbatim}\n -128 64 32 16 8 4 2 1\n 1 1 1 1 1 1 <== carries\n 1 1 1 1 1 1 0 0 <== -4\n + 0 0 0 0 0 1 0 1 <== 5\n ----------------------\n 1 0 0 0 0 0 0 0 1 <== 1 (with a truncation)\n\\end{verbatim}\n\nNote that the changing of the sign using this method is symmetric\nin that it is identical when converting from negative to positive\nand when converting from positive to negative: {\\em flip the bits and\nadd 1.}\n\nFor example, changing the value -4 to 4 to illustrate the\nreverse of the conversion above:\n\n\\begin{verbatim}\n -128 64 32 16 8 4 2 1\n 1 1 1 1 1 1 0 0 <== -4\n\n 1 1 <== carries\n 0 0 0 0 0 0 1 1 <== one's complement of -4\n + 0 0 0 0 0 0 0 1 <== plus 1\n ----------------------\n 0 0 0 0 0 1 0 0 <== 4\n\\end{verbatim}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{Subtraction of Binary Numbers}\n\n\nSubtraction%\n\\enote{This section needs more examples of subtracting \nsigned an unsigned numbers and a discussion on how \nsignedness is not relevant until the results are interpreted. \nFor example adding $-4+ -8=-12$ using two 8-bit numbers \nis the same as adding $252+248=500$ and truncating the result \nto 244.}\nof binary numbers is performed by first negating\nthe subtrahend and then adding the two numbers. Due to the\nnature of two's complement numbers this method will work for both \nsigned and unsigned numbers!\n\nObservation: Since we always have a carry-in of zero into the LSB when\nadding, we can take advantage of that fact by (ab)using that carry input\nto perform that adding the extra 1 to the subtrahend as part of\nchanging its sign in the examples below. \n\nAn example showing the subtraction of two {\\em signed} binary numbers: $-4-8 = -12$\n\n\\begin{verbatim}\n -128 64 32 16 8 4 2 1\n 1 1 1 1 1 1 0 0 <== -4 (minuend)\n - 0 0 0 0 1 0 0 0 <== 8 (subtrahend)\n ------------------------\n\n\n 1 1 1 1 1 1 1 1 1 <== carries\n 1 1 1 1 1 1 0 0 <== -4\n + 1 1 1 1 0 1 1 1 <== one's complement of 8\n ------------------------\n 1 1 1 1 1 0 1 0 0 <== -12\n\\end{verbatim}\n\n\n%An example showing the subtraction of two {\\em unsigned} binary numbers: $252+248=500$\n%\n%\\begin{verbatim}\n% 128 64 32 16 8 4 2 1\n%\n% 1 1 1 1 1 <== carries\n% 1 1 1 1 1 1 0 0 <== 252\n% + 1 1 1 1 1 0 0 0 <== 248\n% ----------------------\n% 1 1 1 1 1 0 1 0 0 < == 500 (if we do NOT truncate the MSB)\n%\\end{verbatim}\n%\n%An example showing the subtraction of two {\\em unsigned} binary numbers: $252+248=500$\n\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{Truncation}\n\\index{truncation}\n\\index{overflow}\n\\index{carry}\n\nDiscarding the carry bit that can be generated from the MSB is called {\\em truncation}.\n\nSo far we have been ignoring the carries that can come from the MSBs when adding and subtracting. \nWe have also been ignoring the potential impact of a carry causing a signed number to change \nits sign in an unexpected way.\n\nIn the examples above, truncating the results either had 1) no impact on the calculated sums\nor 2) was absolutely necessary to correct the sum in cases such as: $-4 + 5$.\n\nFor example, note what happens when we try to subtract 1 from the most \nnegative value that we can represent in a 4 bit two's complement number:\n\n\\begin{verbatim}\n -8 4 2 1\n 1 0 0 0 <== -8 (minuend)\n - 0 0 0 1 <== 1 (subtrahend)\n ------------\n\n\n 1 1 <== carries\n 1 0 0 0 <== -8\n + 1 1 1 0 <== one's complement of 1\n ----------\n 1 0 1 1 1 <== this SHOULD be -9 but with truncation it is 7 \n\\end{verbatim}\n\nThe problem with this example is that we can not represent $-9_{10}$ using a 4-bit \ntwo's complement number. \n\nGranted, if we would have used 5 bit numbers, then the ``answer'' would have fit OK.\nBut the same problem would return when trying to calculate $-16 - 1$. \nSo simply ``making more room'' does not solve this problem.\n\n%However, as calculating $-1+1=0$ has demonmstrated above, it was necessary for that\n%case to discard the carry out of the MSB to get the correct result.\n\n%In the case of calculating $-1+1=0$ the addends and result all fit into same-sized\n%(8-bit) values. When calculating $-8-1=-9$ the addends each can fit into 4-bit\n%two's complement numbers but the result would require a 5-bit number.\n\nThis is not just a problem when subtracting, nor is it just a problem with\nsigned numbers.\n\nThe same situation can happen {\\em unsigned} numbers. \nFor example:\n\n\\begin{verbatim}\n 8 4 2 1\n 1 1 1 0 0 <== carries\n 1 1 1 0 <== 14 (addend)\n + 0 0 1 1 <== 3 (addend)\n ------------\n 1 0 0 0 1 <== this SHOULD be 17 but with truncation it is 1\n\\end{verbatim}\n\n\nHow to handle such a truncation depends on whether the {\\em original} values \nbeing added are signed or unsigned.\n\nThe RV ISA refers to the discarding the carry out of the MSB after an \nadd (or subtract) of two {\\em unsigned} numbers as an {\\em unsigned overflow}%\n\\footnote{Most microprocessors refer to {\\em unsigned overflow} simply as a \n{\\em carry} condition.}\nand the situation where carries create an incorrect sign in the\nresult of adding (or subtracting) two {\\em signed} numbers as a\n{\\em signed overflow}.~\\cite[p.~13]{rvismv1v22:2017}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsubsection{Unsigned Overflow}\n\\index{overflow!unsigned}\n\nWhen adding {\\em unsigned} numbers, an overflow only occurs when there \nis a carry out of the MSB resulting in a sum that is truncated to fit \ninto the number of bits allocated to contain the result.\n\n\\autoref{sum:240+17} illustrates an unsigned overflow during addition:\n\n\\begin{figure}[H]\n\\centering\n\\begin{BVerbatim}\n 1 1 1 1 0 0 0 0 0 <== carries\n 1 1 1 1 0 0 0 0 <== 240\n + 0 0 0 1 0 0 0 1 <== 17\n---------------------\n 1 0 0 0 0 0 0 0 1 <== sum = 1\n\\end{BVerbatim}\n%{\\captionof{figure}{$240+16=0$ (overflow)}\\label{sum:240+17}}\n\\caption{$240+17=1$ (overflow)}\n\\label{sum:240+17}\n\\end{figure}\n\nSome times an overflow like this is referred to as a {\\em wrap around}\nbecause of the way that successive additions will result in a value that\nincreases until it {\\em wraps} back {\\em around} to zero and then \nreturns to increasing in value until it, again, wraps around again.\n\n\\begin{tcolorbox}\nWhen adding, {\\em unsigned overflow} occurs when ever there is a carry\n{\\em out of} the most significant bit.\n\\end{tcolorbox}\n\n\n\nWhen subtracting {\\em unsigned} numbers, an overflow only occurs when the\nsubtrahend is greater than the minuend (because in those cases the \ndifference would be negative but no negative values \ncan be represented with an unsigned binary number.)\n\n\\autoref{sum:3-4} illustrates an unsigned overflow during subtraction:\n\n\\begin{figure}[H]\n\\centering\n\\begin{BVerbatim}\n 0 0 0 0 0 0 1 1 <== 3 (minuend)\n - 0 0 0 0 0 1 0 0 <== 4 (subtrahend)\n -----------------\n\n\n 0 0 0 0 0 0 1 1 1 <== carries\n 0 0 0 0 0 0 1 1 <== 3\n + 1 1 1 1 1 0 1 1 <== one's complement of 4\n -----------------\n 1 1 1 1 1 1 1 1 <== 255 (overflow)\n\\end{BVerbatim}\n\\caption{$3-4=255$ (overflow)}\n\\label{sum:3-4}\n\\end{figure}\n\n\\begin{tcolorbox}\nWhen subtracting, {\\em unsigned overflow} occurs when ever there is {\\em not} a carry\n{\\em out of} the most significant bit (IFF the carry-in on the LSB is used to add the\nextra 1 to the subtrahend when changing its sign.)\n\\end{tcolorbox}\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsubsection{Signed Overflow}\n\\index{overflow!signed}\n\nWhen adding {\\em signed} numbers, an overflow only occurs when the two \naddends are positive and sum is negative or the addends are both negative \nand the sum is positive. \n\nWhen subtracting {\\em signed} numbers, an overflow only occurs when the\nminuend is positive and the subtrahend is negative and difference is negative\nor when the minuend is negative and the subtrahend is positive and the \ndifference is positive.%\n\\footnote{I had to look it up to remember which were which \ntoo\\ldots\\ it is: minuend - subtrahend = difference.\\cite{subtrahend}}\n\nConsider the results of the addition of two {\\em signed} numbers\nwhile looking more closely at the carry values.\n\n\\begin{figure}[H]\n\\centering\n\\begin{BVerbatim}\n 0 1 0 0 0 0 0 0 0 <== carries\n 0 1 0 0 0 0 0 0 <== 64\n + 0 1 0 0 0 0 0 0 <== 64\n---------------------\n 1 0 0 0 0 0 0 0 <== sum = -128\n\\end{BVerbatim}\n\\caption{$64+64 = -128$ (overflow)}\n\\label{sum:64+64}\n\\end{figure}\n\n\n\n\\autoref{sum:64+64} is an example of {\\em signed overflow}. As shown, the problem is \nthat the sum of two positive numbers has resulted in an obviously incorrect\nnegative result due to a carry flowing into the sign-bit in the MSB.\n\nGranted, if the same values were added using values larger than 8-bits \nthen the sum would have been correct. However, these examples assume that \nall the operations are performed on (and results stored into) 8-bit values. \nGiven any finite-number of bits, there are values that could be added such that\nan overflow occurs.\n\n\\index{truncation}\n\\autoref{sum:-128+-128} shows another overflow situation that is caused \nby the fact that there is nowhere for the carry out of the sign-bit to go. \nWe say that this result has been {\\em truncated}.\n\n\\begin{figure}[H]\n\\centering\n\\begin{BVerbatim}\n 1 0 0 0 0 0 0 0 0 <== carries\n 1 0 0 0 0 0 0 0 <== -128\n + 1 0 0 0 0 0 0 0 <== -128\n---------------------\n 0 0 0 0 0 0 0 0 <== sum = 0 \n\\end{BVerbatim}\n\\caption{$-128+-128 = 0$ (overflow)}\n\\label{sum:-128+-128}\n\\end{figure}\n\nTruncation is not necessarily a problem. Consider the truncations in\nfigures \\ref{sum:-3+-5} and \\ref{sum:-2+10}. \n\\autoref{sum:-2+10} demonstrates the importance of discarding \nthe carry from the sum of the MSBs of signed numbers when addends\ndo not have the same sign.\n\n\\begin{figure}[H]\n\\centering\n\\begin{BVerbatim}\n 1 1 1 1 1 1 1 1 0 <== carries\n 1 1 1 1 1 1 0 1 <== -3\n + 1 1 1 1 1 0 1 1 <== -5\n---------------------\n 1 1 1 1 1 0 0 0 <== sum = -8\n\\end{BVerbatim}\n\\captionof{figure}{$-3+-5 = -8$}\n\\label{sum:-3+-5}\n\\end{figure}\n\n\\begin{figure}[H]\n\\centering\n\\begin{BVerbatim}\n 1 1 1 1 1 1 1 0 0 <== carries\n 1 1 1 1 1 1 1 0 <== -2\n + 0 0 0 0 1 0 1 0 <== 10\n---------------------\n 0 0 0 0 1 0 0 0 <== sum = 8\n\\end{BVerbatim}\n\\captionof{figure}{$-2+10 = 8$}\n\\label{sum:-2+10}\n\\end{figure}\n\nJust like an unsigned number can wrap around as a result of\nsuccessive additions, a signed number can so the same thing. The\nonly difference is that signed numbers won't wrap from the maximum \nvalue back to zero, instead it will wrap from the most positive to \nthe most negative value as shown in \\autoref{sum:127+1}.\n \n\\begin{figure}[H]\n\\centering\n\\begin{BVerbatim}\n 0 1 1 1 1 1 1 1 0 <== carries\n 0 1 1 1 1 1 1 1 <== 127\n + 0 0 0 0 0 0 0 1 <== 1\n---------------------\n 1 0 0 0 0 0 0 0 <== sum = -128\n\\end{BVerbatim}\n\\captionof{figure}{$127+1 = -128$}\n\\label{sum:127+1}\n\\end{figure}\n\n\\begin{tcolorbox}\nFormally, a {\\em signed overflow} occurs when ever the carry\n{\\em into} the most significant bit is not the same as the \ncarry {\\em out of} the most significant bit. \n\\end{tcolorbox}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\section{Sign and Zero Extension}\n\n\\index{sign extension}\n\\label{SignExtension}\nDue to the nature of the two's complement encoding scheme, the following \nnumbers all represent the same value:\n\\begin{verbatim}\n 1111 <== -1\n 11111111 <== -1\n 11111111111111111111 <== -1\n 1111111111111111111111111111 <== -1\n\\end{verbatim}\nAs do these:\n\\begin{verbatim}\n 01100 <== 12\n 0000001100 <== 12\n 00000000000000000000000000000001100 <== 12\n\\end{verbatim}\n\nThe lengthening of these numbers by replicating the digits on the left\nis what is called {\\em sign extension}. \n\n\\begin{tcolorbox}\nAny signed number can have any quantity of additional MSBs added to it,\nprovided that they repeat the value of the sign bit.\n\\end{tcolorbox}\n\n\\autoref{Figure:SignExtendNegative} illustrates extending the negative sign\nbit to the left by replicating it.\nA negative number will have its \\acrshort{msb} (bit 19 in this example)\nset to 1. Extending this value to the left will set all the new bits\nto the left of it to 1 as well.\n\n\\begin{figure}[ht]\n\\centering\n\\DrawBitBoxSignExtendedPicture{32}{10100000000000000010}\n\\captionof{figure}{Sign-extending a negative integer from 20 bits to 32 bits.}\n\\label{Figure:SignExtendNegative}\n\\end{figure}\n\n\\autoref{Figure:SignExtendPositive} illustrates extending the sign bit of a\npositive number to the left by replicating it.\nA positive number will have its \\acrshort{msb} set to 0. Extending this\nvalue to the left will set all the new bits to the left of it to 0 as well.\n\n\\begin{figure}[ht]\n\\centering\n\\DrawBitBoxSignExtendedPicture{32}{01000000000000000010}\n\\captionof{figure}{Sign-extending a positive integer from 20 bits to 32 bits.}\n\\label{Figure:SignExtendPositive}\n\\end{figure}\n\n\n\\label{ZeroExtension}\nIn a similar vein, any unsigned number also may have any quantity of \nadditional MSBs added to it provided that they are all zero. This is\ncalled {\\em zero extension}. For example,\nthe following all represent the same value:\n\\begin{verbatim}\n 1111 <== 15\n 01111 <== 15\n 00000000000000000000000001111 <== 15\n\\end{verbatim}\n\n\\begin{tcolorbox}\nAny {\\em unsigned} number may be {\\em zero extended} to any size.\n\\end{tcolorbox}\n\n\\enote{Remove the sign-bit boxes from this figure?}%\n\\autoref{Figure:ZeroExtend} illustrates zero-extending a 20-bit number to the\nleft to form a 32-bit number.\n\n\\begin{figure}[ht]\n\\centering\n\\DrawBitBoxZeroExtendedPicture{32}{10000000000000000010}\n\\captionof{figure}{Zero-extending an unsigned integer from 20 bits to 32 bits.}\n\\label{Figure:ZeroExtend}\n\\end{figure}\n\n%Sign- and zero-extending binary numbers are common operations used to \n%fit a byte or halfword into a fullword.\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\section{Shifting}\n\\label{shifting}\n\nWe were all taught how to multiply and divide decimal numbers by ten\nby moving (or {\\em shifting}) the decimal point to the right or left \nrespectively. Doing the same in any other base has the same effect \nin that it will multiply or divide the number by its base.\n\n\\enote{Include decimal values in the shift diagrams.}%\nMultiplication and division are only two reasons for shifting. There\ncan be other occasions where doing so is useful.\n\nAs implemented by a CPU, shifting applies to the value in a register\nand the results stored back into a register of finite size. Therefore\na shift result will always be truncated to fit into a register.\n\n\\enote{Add some examples showing the rounding of positive and negative values.}%\nNote that when dealing with numeric values, any truncation performed \nduring a right-shift will manifest itself as rounding toward zero.\n\n\\subsection{Logical Shifting}\n\nShifting {\\em logically} to the left or right is a matter of re-aligning\nthe bits in a register and truncating the result.\n\n\\enote{Redraw these with arrows tracking the shifted bits and the truncated values}%\nTo shift left two positions:\n\n\\DrawBitBoxUnsignedPicture{10111000000000000010}\\\\\n\\DrawBitBoxUnsignedPicture{11100000000000001000}\n\nTo shift right one position:\n\n\\DrawBitBoxUnsignedPicture{10111000000000000010}\\\\\n\\DrawBitBoxUnsignedPicture{01011100000000000001}\n\n\\begin{tcolorbox}\nNote that the vacated bit positions are always filled with zero.\n\\end{tcolorbox}\n\n\\subsection{Arithmetic Shifting}\n\nSome times it is desirable to retain the value of the sign bit when\nshifting. The RISC-V ISA provides an arithmetic right shift \ninstruction for this purpose (there is no arithmetic left shift for \nthis ISA.)\n\n\\begin{tcolorbox}\nWhen shifting to the right {\\em arithmetically}, vacated bit positions are\nfilled by replicating the value of the sign bit. \n\\end{tcolorbox}\n\nAn arithmetic right shift of a negative number by 4 bit positions:\n\n\\DrawBitBoxSignedPicture{10111000000000000010}\\\\\n\\DrawBitBoxSignedPicture{11111011100000000000}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\section{Main Memory Storage}\n\nAs mentioned in \\autoref{VolatileStorage}, the main memory in a RISC-V \nsystem is byte-addressable. For that reason we will visualize it by \ndisplaying ranges of bytes displayed in hex and in \\gls{ascii}. As will \nbecome obvious, the ASCII part makes it easier to find text messages.%\n\\footnote{Most of the memory dumps in this text are generated by \\gls{rvddt}\nand are shown on a per-byte basis without any attempt to reorder their\nvalues. Some other applications used to dump memory do not dump the bytes\nin address-order! It is important to know how your software tools operate\nwhen using them to dump the contents of memory and/or files.}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{Memory Dump}\n\n\\listingRef{rvddt_memdump.out} shows a {\\em memory dump} from the rvddt\n`d' command requesting a dump starting at address \\hex{00002600}\nfor the default quantity (\\hex{100}) of bytes.\n\n\\listing{rvddt_memdump.out}{{\\tt rvddt} memory dump}\n\n\\begin{itemize}\n\\item [$\\ell$ 1] The rvddt prompt showing the dump command.\n\\item [$\\ell$ 2] From left to right. the dump is presented as the address \n\tof the first byte (\\hex{00002600}) followed by a colon, the value\n\tof the byte at address \\hex{00002600} expressed in hex, the next byte\n\t(at address \\hex{00002601}) and so on for 16 bytes. There is a \n\tdouble-space\n\tbetween the 7th and 8th bytes to help provide a visual reference for\n\tthe center to make it easy to locate bytes on the right end. For \n\texample, the byte at address \\hex{0000260c} is four bytes to the \n\tright of byte number eight (at the gap) and contains \\hex{13}.\n\tTo the right of the 16-bytes is an asterisk-enclosed set of 16 columns\n\tshowing the ASCII characters that each byte represents. If a byte\n\thas a value that corresponds to a printable character code, the character\n\twill be displayed. For any illegal/un-displayable byte values, a dot \n\tis shown to make it easier to count the columns.\n\\item [$\\ell$ 3-17] More of the same as seen on $\\ell$ 2. The address\n\tat the left can be seen to advance by $16_{10}$ (or $10_{16}$) \n\tfor each line shown.\n\\end{itemize}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{Endianness}\n\nThe choice of which end of a multi-byte value is to be stored at the\nlowest byte address is referred to as {\\em endianness.} For example,\nif a CPU were to store a \\gls{halfword} into memory, should the byte \ncontaining the \\acrfull{msb} (the {\\em big} end) go first or does \nthe byte with the \\acrfull{lsb} (the {\\em little} end) go first? \n\nOn the one hand the choice is arbitrary. On the other hand, it is \npossible that the choice could impact the performance of the system.%\n\\footnote{See\\cite{IEN137} for some history of the big/little-endian ``controversy.''}\n\nIBM mainframe CPUs and the 68000 family store their bytes in big-endian \norder. While the Intel Pentium and most embedded processors use\nlittle-endian order. \nSome CPUs are even {\\em bi-endian} in that they have instructions that\ncan change their order on the fly. \n\nThe RISC-V system uses the little-endian byte order.\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsubsection{Big-Endian}\n\\label{BigEndian}\n\\index{big-endian}\n\nUsing the contents of \\listingRef{rvddt_memdump.out}, a \\gls{bigendian}\nCPU would interpret the contents as follows:\n\n\\begin{itemize}\n\\item The 8-bit value read from address \\colorbox{c_lightblue}{\\hex{00002658}} would be \\verb@0x@{\\color{red}\\verb@76@}.\n\\item The 8-bit value read from address \\hex{00002659} would be \\hex{61}.\n\\item The 8-bit value read from address \\hex{0000265a} would be \\hex{6c}.\n\\item The 8-bit value read from address \\hex{0000265b} would be \\hex{3d}.\n\\item The 16-bit value read from address \\colorbox{c_lightblue}{\\hex{00002658}} would be \\verb@0x@{\\color{red}\\verb@76@}\\verb@61@.\n\\item The 16-bit value read from address \\hex{0000265a} would be \\hex{6c3d}.\n\\item The 32-bit value read from address \\colorbox{c_lightblue}{\\hex{00002658}} would be \\verb@0x@{\\color{red}\\verb@76@}\\verb@616c3d@.\n\\end{itemize}\n\nNotice that in a big-endian system, the {\\em\\gls{place-value}s} of the bits \ncomprising the \\verb@0x@{\\color{red}\\verb@76@}\n(located at memory address \\colorbox{c_lightblue}{\\hex{00002658}}) are \n{\\em different} depending on the number of bytes representing the value that is being read.\n\nFor example, when a 16-bit value is read from \\colorbox{c_lightblue}{\\hex{00002658}}\nthen the {\\color{red}\\verb@76@} represents \nthe binary place values: $2^{15}$ to $2^8$.\nWhen a 32-bit value is read then the {\\color{red}\\verb@76@} represents\nthe binary place values: $2^{31}$ to $2^{24}$. \nIn other words the value read from the first memory location (with the \nlowest address), of the plurality of addresses containing the complete \nvalue being read, is always placed on the {\\em left end}, into the \nMost Significant Bits. One might dare say that the {\\color{red}\\verb@76@} \nis placed at the end with the {\\em big} place values.\n\nMore examples:\n\n\\begin{itemize}\n\\item An 8-bit value read from address \\colorbox{c_lightgreen}{\\hex{00002624}} would be \\verb@0x@{\\color{red}\\verb@23@}.\n\\item An 8-bit value read from address \\hex{00002625} would be \\hex{24}.\n\\item An 8-bit value read from address \\hex{00002626} would be \\hex{81}.\n\\item An 8-bit value read from address \\hex{00002627} would be \\hex{00}.\n\\item A 16-bit value read from address \\colorbox{c_lightgreen}{\\hex{00002624}} would be \\verb@0x@{\\color{red}\\verb@23@}\\verb@24@.\n\\item A 16-bit value read from address \\hex{00002626} would be \\hex{8100}.\n\\item A 32-bit value read from address \\colorbox{c_lightgreen}{\\hex{00002624}} would be \\verb@0x@{\\color{red}\\verb@23@}\\verb@248100@.\n\\end{itemize}\n\nAgain, notice that the byte from memory address \\colorbox{c_lightgreen}{\\hex{00002624}}, \nregardless of the {\\em number} of bytes comprising the complete value being \nfetched, will always appear on the left/{\\em big} end of the final value.\n\n\n\\begin{tcolorbox}\nOn a big-endian system, the bytes in the dump are in the same order as \nthey would be used by the CPU if it were to read them as a multi-byte \nvalue.\n\\end{tcolorbox}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsubsection{Little-Endian}\n\\label{LittleEndian}\n\\index{little-endian}\n\nUsing the contents of \\listingRef{rvddt_memdump.out}, a \\gls{littleendian}\nCPU would interpret the contents as follows:\n\n\\begin{itemize}\n\\item An 8-bit value read from address \\colorbox{c_lightblue}{\\hex{00002658}} would be \\verb@0x@{\\color{red}\\verb@76@}.\n\\item An 8-bit value read from address \\hex{00002659} would be \\hex{61}.\n\\item An 8-bit value read from address \\hex{0000265a} would be \\hex{6c}.\n\\item An 8-bit value read from address \\hex{0000265b} would be \\hex{3d}.\n\\item A 16-bit value read from address \\colorbox{c_lightblue}{\\hex{00002658}} would be \\verb@0x61@{\\color{red}\\verb@76@}.\n\\item A 16-bit value read from address \\hex{0000265a} would be \\hex{3d6c}.\n\\item A 32-bit value read from address \\colorbox{c_lightblue}{\\hex{00002658}} would be \\verb@0x3d6c61@{\\color{red}\\verb@76@}.\n\\end{itemize}\n\nNotice that in a little-endian system, the {\\em\\gls{place-value}s} of the bits \ncomprising the \\verb@0x@{\\color{red}\\verb@76@}\n(located at memory address \\colorbox{c_lightblue}{\\hex{00002658}})\nare the {\\em same} regardless of the the number of bytes representing the value that is being read.\n\nUnlike the behavior of a big-endian machine, when little-endian machine \nreads a 16-bit value from \\colorbox{c_lightblue}{\\hex{00002658}} the \n{\\color{red}\\verb@76@} represents the binary place values from $2^{7}$ to $2^0$.\nWhen a 32-bit value is read then the {\\color{red}\\verb@76@} (still) represents\nthe binary place values from $2^{7}$ to $2^{0}$. \nIn other words the value read from the first memory location (with the \nlowest address), of the plurality of addresses containing the complete \nvalue being read, is always placed on the {\\em right end}, into the \nLeast Significant Bits. One might say that the {\\color{red}\\verb@76@} \nis placed at the end with the {\\em little} place values.\n\nAlso notice that it is the {\\em bytes} are what are ``reversed'' in a little-endian\nsystem ({\\em not} the hex digits.)\n\nMore examples:\n\n\\begin{itemize}\n\\item The 8-bit value read from address \\colorbox{c_lightgreen}{\\hex{00002624}} would be \\verb@0x@{\\color{red}\\verb@23@}.\n\\item The 8-bit value read from address \\hex{00002625} would be \\hex{24}.\n\\item The 8-bit value read from address \\hex{00002626} would be \\hex{81}.\n\\item The 8-bit value read from address \\hex{00002627} would be \\hex{00}.\n\\item The 16-bit value read from address \\colorbox{c_lightgreen}{\\hex{00002624}} would be \\verb@0x24@{\\color{red}\\verb@23@}.\n\\item The 16-bit value read from address \\hex{00002626} would be \\hex{0081}.\n\\item The 32-bit value read from address \\colorbox{c_lightgreen}{\\hex{00002624}} would be \\verb@0x008124@{\\color{red}\\verb@23@}.\n\\end{itemize}\n\nAs above, notice that the byte from memory address \\colorbox{c_lightgreen}{\\hex{00002624}}, \nregardless of the {\\em number} of bytes comprising the complete value being \nfetched, will always appear on the right/{\\em little} end of the final value.\n\n\n\n\\begin{tcolorbox}\nOn a little-endian system, the bytes in the dump are in reverse order as \nthey would be used by the CPU if it were to read them as a multi-byte value.\n\\end{tcolorbox}\n\n\nIn the RISC-V ISA it is noted that \n\\begin{quote}\nA minor point is that we have also found \nlittle-endian memory systems to be more natural for hardware \ndesigners. However, certain application areas, such as IP networking, operate\non big-endian data structures, and so we leave open the possibility of \nnon-standard big-endian or bi-endian systems.''\\cite[p.~6]{rvismv1v22:2017}\n\\end{quote}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{Arrays and Character Strings}\n\nWhile Endianness defines how single values are stored in memory,\nthe {\\em array} defines how multiple values are stored.\n\nAn array is a data structure comprised of an ordered set of elements.\nThis text will limit its definition of array to a plurality of\nelements that are all of the same type. Where type\nrefers to the size (number of bytes) and representation (signed,\nunsigned,\\ldots) of each element.\n\nIn an array, the elements are stored adjacent to one another such that the\naddress $e$ of any element $x[n]$ is:\n\n\\begin{equation}\ne = a + n * s\n\\end{equation}\n\nWhere $x$ is the name of the array, $n$ is the element number of interest, \n$e$ is the address of interest, $a$ is the address of the first element in \nthe array and $s$ is the size (in bytes) of each element.\n\nGiven an array $x$ containing $m$ elements, $x[0]$ is the first element of \nthe array and $x[m-1]$ is the last element of the array.%\n\\footnote{Some computing languages (C, C++, Java, C\\#, Python, Perl,\\ldots) \ndefine an array such that the first element is indexed as $x[0]$. \nWhile others (FORTRAN, MATLAB) define the first element of an \narray to be $x[1]$.}\n\nUsing this definition, and the memory dump shown in \n\\listingRef{rvddt_memdump.out}, and the knowledge that \nwe are using a little-endian machine and given that\n$a = $ \\hex{00002656} and $s = 2$, the values of the first 8 elements \nof array $x$ are:\n\n\\begin{itemize}\n\\item $x[0]$ is \\hex{0000} and is stored at \\hex{00002656}.\n\\item $x[1]$ is \\hex{6176} and is stored at \\hex{00002658}.\n\\item $x[2]$ is \\hex{3d6c} and is stored at \\hex{0000265a}.\n\\item $x[3]$ is \\hex{0000} and is stored at \\hex{0000265c}.\n\\item $x[4]$ is \\hex{0000} and is stored at \\hex{00002660}.\n\\item $x[5]$ is \\hex{0000} and is stored at \\hex{00002662}.\n\\item $x[6]$ is \\hex{8480} and is stored at \\hex{00002664}.\n\\item $x[7]$ is \\hex{412e} and is stored at \\hex{00002666}.\n\\end{itemize}\n\n\\begin{tcolorbox}\nIn general, there is no fixed rule nor notion as to how many \nelements an array has. It is up to the programmer to ensure that\nthe starting address and the number of elements in any given array\n(its size) are used properly so that data bytes outside an array\nare not accidentally used as elements.\n\\end{tcolorbox}\n\nThere is, however, a common convention used for an array of \ncharacters that is used to hold a text message \n(called a {\\em character string} or just {\\em string}).\n\nWhen an array is used to hold a string the element past the last\ncharacter in the string is set to zero. This is because 1) zero \nis not a valid printable ASCII character and 2) it simplifies\nsoftware in that knowing no more than the starting address of a\nstring is all that is needed to processes it. Without this zero\n{\\em sentinel} value (called a {\\em null} terminator), some knowledge\nof the number of characters in the string would have to otherwise \nbe conveyed to any code needing to consume or process the string.\n\nIn \\listingRef{rvddt_memdump.out}, the 5-byte long array starting \nat address \\hex{00002658} contains a string whose value can be\nexpressed as either: % \\verb@76 61 6c 3d 00@ or \\verb@\"val=\"@.\n\n\\verb@76 61 6c 3d 00@\n\nor\n\n\\verb@\"val=\"@\n\n%\\begin{itemize}\n%\\item \\verb@76 61 6c 3d 00@\n%\\item \\verb@\"val=\"@\n%\\end{itemize}\n\n\\index{ASCII}\n\\index{ASCIIZ}\nWhen the double-quoted text form is used, the GNU assembler used in \nthis text differentiates between {\\em ascii} and {\\em asciiz} strings\nsuch that an {\\em ascii} string is {\\bf not} null terminated and an\n{\\em asciiz} string {\\bf is} null terminated. \n\nThe value of providing a method to create a string that is not\nnull terminated is that a program may define a large string by \nconcatenating a number of {\\em ascii} strings together and following the \nlast with a byte of zero to null-terminate it.\n\nIt is a common mistake to create a string with a missing\nnull terminator. The result of printing such a string is that\nthe string will be printed as well as whatever random data bytes in \nmemory follow it until a byte whose value is zero is encountered \nby chance.\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{Context is Important!}\n\nData values can be interpreted differently depending on the context in \nwhich they are used. Assuming what a set of bytes is used for based on \ntheir contents can be very misleading! For example, there is a 0x76 at \naddress 0x00002658. This is a `v' is you use it as an ASCII \n(see~\\autoref{chapter:ascii}) character, a $118_{10}$ if it is an integer \nvalue and TRUE if it is a conditional.\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{Alignment}\n\n\\enote{Include the obligatory diagram showing the overlapping data types \nwhen they are all aligned.}%\nWith respect to memory and storage, {\\em \\gls{alignment}} refers to the \n{\\em location} of a data element when the address that it is stored is \na precise multiple of a power-of-2. \n\nThe primary alignments of concern are typically 2 (a halfword), \n4 (a fullword), 8 (a double word) and 16 (a quad-word) bytes.\n\nFor example, any data element that is aligned to 2-byte boundary\nmust have an (hex) address that ends in any of: 0, 2, 4, 6, 8, A, \nC or E.\nAny 4-byte aligned element must be located at an address ending\nin 0, 4, 8 or C. An 8-byte aligned element at an address ending\nwith 0 or 8, and 16-byte aligned elements must be located at\naddresses ending in zero.\n\nSuch alignments are important when exchanging data between the CPU \nand memory because the hardware implementations are optimized to\ntransfer aligned data. Therefore, aligning data used by any program\nwill reap the benefit of running faster.%\n\\footnote{Alignment of data, while important for efficient performance, \nis not mandatory for RISC-V systems.\\cite[p.~19]{rvismv1v22:2017}}\n\nAn element of data is considered to be {\\em aligned to its natural size}\nwhen its address is an exact multiple of the number of bytes used to \nrepresent the data. Note that the ISA we are concerned with {\\em only}\noperates on elements that have sizes that are powers of two.\n\nFor example, a 32-bit integer consumes one full word. If the four bytes\nare stored in main memory at an address than is a multiple of 4 then\nthe integer is considered to naturally aligned. \n\nThe same would apply to 16-bit, 64-bit, 128-bit and other such values \nas they fit into 2, 8 and 16 byte elements respectively.\n\nSome CPUs can deliver four (or more) bytes at the same time while others \nmight only be capable of delivering one or two bytes at a time. Such \ndifferences in hardware typically impact the cost and performance of a \nsystem.%\n\\footnote{The design and implementation\nchoices that determine how any given system operates are part of what is\ncalled a system's {\\em organization} and is beyond the scope of this text.\nSee~\\cite{codriscv:2017} for more information on computer organization.}\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{Instruction Alignment}\n\nThe RISC-V ISA requires that all instructions be aligned to their\nnatural boundaries.\n\nEvery possible instruction that an RV32I CPU can execute contains\nexactly 32 bits. Therefore they are always stored on a full word\nboundary. Any {\\em unaligned} instruction is {\\em illegal}.%\n\\footnote{This rule is relaxed by the C extension to allow an \ninstruction to start at any even address.\\cite[p.~5]{rvismv1v22:2017}}\n\nAn attempt to fetch an instruction from an unaligned address\nwill result in an error referred to as an alignment {\\em \\gls{exception}}.\nThis and other exceptions cause the CPU to stop executing the\ncurrent instruction and start executing a different set of instructions\nthat are prepared to handle the problem. Often an exception is\nhandled by completely stopping the program in a way that is commonly\nreferred to as a system or application {\\em crash}.\n" }, { "path": "book/binary/rvddt_memdump.out", "content": "ddt> d 0x00002600\n 00002600: 93 05 00 00 13 06 00 00 93 06 00 00 13 07 00 00 *................*\n 00002610: 93 07 00 00 93 08 d0 05 73 00 00 00 63 54 05 02 *........s...cT..*\n 00002620: 13 01 01 ff 23 24 81 00 13 04 05 00 23 26 11 00 *....#$......#&..*\n 00002630: 33 04 80 40 97 00 00 00 e7 80 40 01 23 20 85 00 *3..@......@.# ..*\n 00002640: 6f 00 00 00 6f 00 00 00 b7 87 00 00 03 a5 07 43 *o...o..........C*\n 00002650: 67 80 00 00 00 00 00 00 76 61 6c 3d 00 00 00 00 *g.......val=....*\n 00002660: 00 00 00 00 80 84 2e 41 1f 85 45 41 80 40 9a 44 *.......A..EA.@.D*\n 00002670: 4f 11 f3 c3 6e 8a 67 41 20 1b 00 00 20 1b 00 00 *O...n.gA ... ...*\n 00002680: 44 1b 00 00 14 1b 00 00 14 1b 00 00 04 1c 00 00 *D...............*\n 00002690: 44 1b 00 00 14 1b 00 00 04 1c 00 00 14 1b 00 00 *D...............*\n 000026a0: 44 1b 00 00 10 1b 00 00 10 1b 00 00 10 1b 00 00 *D...............*\n 000026b0: 04 1c 00 00 54 1f 00 00 54 1f 00 00 d4 1f 00 00 *....T...T.......*\n 000026c0: 4c 1f 00 00 4c 1f 00 00 34 20 00 00 d4 1f 00 00 *L...L...4 ......*\n 000026d0: 4c 1f 00 00 34 20 00 00 4c 1f 00 00 d4 1f 00 00 *L...4 ..L.......*\n 000026e0: 48 1f 00 00 48 1f 00 00 48 1f 00 00 34 20 00 00 *H...H...H...4 ..*\n 000026f0: 00 01 02 02 03 03 03 03 04 04 04 04 04 04 04 04 *................*\n" }, { "path": "book/colors.tex", "content": "% These are color styles used in the figures in this book.\n\\definecolor{c_lightblue}{HTML}{B0E0FF}\n\\definecolor{c_lightred}{HTML}{FFE0E0}\n\\definecolor{c_lightyellow}{HTML}{FFE060}\n\\definecolor{c_lightgreen}{HTML}{C0FFC0}\n" }, { "path": "book/copyright/chapter.tex", "content": "\\thispagestyle{plain}\n\nCopyright \\copyright\\ 2018, 2019, 2020 John Winans \n\nThis document is made available under a Creative Commons Attribution 4.0 \nInternational License. See \\autoref{license} for more information.\n\nDownload your own copy of this book from github here: \n\\url{https://github.com/johnwinans/rvalp}.\n\nThis document may contain inaccuracies or errors. The author provides no \nguarantee regarding the accuracy of this document's contents. If you \ndiscover that this document contains errors, please notify the author.\n\n\\enote{Need to say something about trademarks for things mentioned in this\ntext}\n\n\nARM\\rtm{} is a registered trademark of ARM Limited in the \nEU and other countries.\n\nIBM\\rtm{} is a trademarks or registered trademark of International Business Machines \nCorporation in the United States, other countries, or both.\n\nIntel\\rtm{} and Pentium\\rtm{} are trademarks of Intel Corporation or its subsidiaries \nin the U.S. and/or other countries.\n" }, { "path": "book/elements/chapter.tex", "content": "\\chapter{The Elements of a Assembly Language Program}\n\\label{chapter:elements}\n\n\\section{Assembly Language Statements}\n\nIntroduce the assembly language grammar. \n\\begin{itemize}\n\\item Statement = 1 line of text containing an instruction or directive.\n\\item Instruction = label, mnemonic, operands, comment.\n\\item Directive = Used to control the operation of the assembler.\n\\end{itemize}\n\n\\section{Memory Layout}\n\nIs this a good place to introduce the text, data, bss, heap and stack regions?\n\nOr does that belong in a new section/chapter that discusses addressing modes?\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\section{A Sample Program Source Listing}\n\nA simple program that illustrates how this text presents \nprogram source code is seen in \\listingRef{zero4regs.S}.\nThis program will place a zero in each of the 4 registers \nnamed x28, x29, x30 and x31.\n\n\\listing{zero4regs.S}{Setting four registers to zero.}\n\nThis program listing illustrates a number of things: \n\\begin{itemize}\n\\item Listings are identified by the name of the file within which\n\tthey are stored. This listing is from a file named: \\verb@zero4regs.S@.\n\\item The assembly language programs discussed in this text will be saved\n\tin files that end with: \\verb@.S@ (Alternately you can use \\verb@.sx@ \n\ton systems that don't understand the difference between upper and \n\tlowercase letters.\\footnote{The author of this text prefers to avoid\n\tusing such systems.})\n\\item A description of the listing's purpose appears under the name of the\n\tfile. The description of \\listingRef{zero4regs.S} is \n\t{\\em Setting four registers to zero.}\n\\item The lines of the listing are numbered on the left margin for\n\teasy reference.\n\\item An assembly program consists of lines of plain text.\n\\item The RISC-V ISA does not provide an operation that will simply \n\tset a register to a numeric value. To accomplish our goal this\n\tprogram will add zero to zero and place the sum in in each of the\n\tfour registers.\n\\item The lines that start with a dot `.' (on lines 1, 2 and 3) are \n\tcalled {\\em assembler directives} as they tell the assembler itself\n\thow we want it to translate the following {\\em assembly language instructions} \n\tinto {\\em machine language instructions.} \n\\item Line 4 shows a {\\em label} named {\\em \\_start}. The colon\n\tat the end is the indicator to the assembler that causes it to\n\trecognize the preceding characters as a label.\n\\item Lines 5-8 are the four assembly language instructions that\n\tmake up the program. Each instruction in this program\n\tconsists of four {\\em fields}. (Different instructions can have \n\ta different number of fields.) The fields on line 5 are:\n\n\t\\begin{itemize}\n\t\\item [addi] The instruction mnemonic. It indicates the operation \n\t\tthat the CPU will perform.\n\t\\item [x28] The {\\em destination} register that will receive the \n\t\tsum when the {\\em addi} instruction is finished. The names of\n\t\tthe 32 registers are expressed as x0 -- x31.\n\t\\item [x0] One of the addends of the sum operation. (The x0 register\n\t\twill always contain the value zero. It can never be changed.)\n\t\\item [0] The second addend is the number zero.\n\t\t\\item [\\# set \\ldots] Any text anywhere in a RISC-V assembly language\n\tprogram that starts with the pound-sign is ignored by the assembler.\n\t\t\tThey are used to place a {\\em comment} in the program to help\n\tthe reader better understand the motive of the programmer.\n\t\\end{itemize}\n\\end{itemize}\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\section{Running a Program With rvddt}\n\\index{rvddt}\n\nTo illustrate what a CPU does when it executes instructions this text\nwill use the \\gls{rvddt} simulator to display shows sequence of events \nand the binary values involved. This simulator supports the RV32I ISA \nand has a configurable amount of memory.%\n\\footnote{The {\\em rvddt} simulator was written to generate the listings for \nthis text. It is similar to the fancier {\\em spike} simulator. \nGiven the simplicity of the RV32I ISA, rvddt is less than 1700 lines of C++ \nand was written in one (long) afternoon.}\n\n\\listingRef{zero4regs.out} shows the operation of the four \n{\\em addi} instructions from \\listingRef{zero4regs.S} when it is executed\nin trace-mode.\n\n\\listing{zero4regs.out}{Running a program with the rvddt simulator}\n\n\\begin{itemize}\n\\item [$\\ell$ 1] This listing includes the command-line that shows how the simulator\n\twas executed to load a file containing the machine instructions (aka\n\tmachine code) from the assembler.\n\\item [$\\ell$ 2] A message from the simulator indicating that it loaded the machine\n\tcode into simulated memory at address 0.\n\\item [$\\ell$ 3] This line shows the prompt from the debugger and the command\n\t\\verb@t4@ that the user entered to request that the simulator trace \n\tthe execution of four instructions.\n\\item [$\\ell$ 4-8] Prior to executing the first instruction, the state of the\n\tCPU registers is displayed. \n\\item [$\\ell$ 4] The values in registers 0, 1, 2, 3, 4, 5, 6 and 7 are printed \n\tfrom left to right in \\gls{bigendian}, \\gls{hexadecimal} form. \n\tThe double-space gap in the middle of the line is a reference \n\tto make it easier to visually navigate across the line without being\n\tforced to count the values from the far left when seeking the value \n\tof, say, x5.\n\\item [$\\ell$ 5-7] The values of registers 8--31 are printed.\n\\item [$\\ell$ 8] The {\\em program counter} (\\reg{pc}) register is printed. \n\tIt contains the address of the instruction that the CPU will execute. \n\tAfter each instruction, the \\reg{pc} will either advance four bytes \n\tahead or be set to another value by a branch instruction as discussed above.\n\\item [$\\ell$ 9] A four-byte instruction is fetched from memory at the address\n\tin the \\reg{pc} register, is decoded and printed. From left to right\n\tthe fields shown on this line are:\n\n\t\\begin{itemize}\n\n\t\\item [00000000] The memory address from which the instruction was\n\t\tfetched. This address is displayed in \\gls{bigendian},\n\t\t\\gls{hexadecimal} form.\n\t\\item [00000e13] The machine code of the instruction displayed in \n\t\t\\gls{bigendian}, \\gls{hexadecimal} form.\n\t\\item [addi] The mnemonic for the machine instruction.\n\t\\item [x28] The \\reg{rd} field of the addi instruction. \n\t\\item [x0] The \\reg{rs1} field of the addi instruction that\n\t\tholds one of the two addends of the operation.\n\t\\item [0] The \\reg{imm} field of the addi instruction that\n\t\tholds the second of the two addends of the operation.\n\t\\item [\\# \\ldots] A simulator-generated comment that explains\n\t\twhat the instruction is doing. For this instruction it indicates \n\t\tthat \\reg{x28} will have the value zero stored into it as a result \n\t\tof performing the addition: $0+0$.\n\t\\end{itemize}\n\n\\item [$\\ell$ 10-14] These lines are printed as the prelude while tracing the\n\tsecond instruction. Lines 7 and 13 show that \\reg{x28} has changed\n\tfrom \\verb@f0f0f0f0@ to \\verb@00000000@ as a result of executing the\n\tfirst instruction and lines 8 and 14 show that the \\reg{pc} has \n\tadvanced from zero (the location of the first instruction) to \n\tfour, where the second instruction will be fetched. None of the\n\trest of the registers have changed values.\n\\item [$\\ell$ 15] The second instruction decoded executed and described. \n\tThis time register \\reg{x29} will be assigned a value.\n\\item [$\\ell$ 16-27] The third and fourth instructions are traced.\n\\item [$\\ell$ 28] Tracing has completed. The simulator prints its prompt\n\tand the user enters the `r' command to see the register state\n\tafter the fourth instruction has completed executing.\n\\item [$\\ell$ 29-33] Following the fourth instruction it can be observed\n\tthat registers \\reg{x28}, \\reg{x29}, \\reg{x30} and \\reg{x31} \n\thave been set to zero and that the \\reg{pc} has advanced from\n\tzero to four, then eight, then 12 (the hex value for 12 is c)\n\tand then to 16 (which, in hex, is 10). \n\\item [$\\ell$ 34] The simulator exit command `x' is entered by the user and\n\tthe terminal displays the shell prompt.\n\n\\end{itemize}\n" }, { "path": "book/elements/zero4regs.S", "content": "\t.text\t\t\t\t\t# put this into the text section\n\t.align\t2\t\t\t\t# align to 2^2\n\t.globl\t_start\n_start:\n\taddi x28, x0, 0\t\t# set register x28 to zero\n\taddi x29, x0, 0\t\t# set register x29 to zero\n\taddi x30, x0, 0\t\t# set register x30 to zero\n\taddi x31, x0, 0\t\t# set register x31 to zero\n" }, { "path": "book/elements/zero4regs.out", "content": "[winans@w510 src]$ ./rvddt -f ../examples/load4regs.bin\nLoading '../examples/load4regs.bin' to 0x0\nddt> t4\n x0: 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0\n x8: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0\n x16: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0\n x24: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0\n pc: 00000000\n00000000: 00000e13 addi x28, x0, 0 # x28 = 0x00000000 = 0x00000000 + 0x00000000\n x0: 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0\n x8: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0\n x16: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0\n x24: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0\n pc: 00000004\n00000004: 00000e93 addi x29, x0, 0 # x29 = 0x00000000 = 0x00000000 + 0x00000000\n x0: 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0\n x8: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0\n x16: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0\n x24: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 00000000 00000000 f0f0f0f0 f0f0f0f0\n pc: 00000008\n00000008: 00000f13 addi x30, x0, 0 # x30 = 0x00000000 = 0x00000000 + 0x00000000\n x0: 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0\n x8: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0\n x16: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0\n x24: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 00000000 00000000 00000000 f0f0f0f0\n pc: 0000000c\n0000000c: 00000f93 addi x31, x0, 0 # x31 = 0x00000000 = 0x00000000 + 0x00000000\nddt> r\n x0: 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0\n x8: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0\n x16: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0\n x24: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 00000000 00000000 00000000 00000000\n pc: 00000010\nddt> x\n[winans@w510 src]$ \n" }, { "path": "book/float/chapter.tex", "content": "\\chapter{Floating Point Numbers}\n\\label{chapter:floatingpoint}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\section{IEEE-754 Floating Point Number Representation}\n\\label{chapter::floatingpoint}\n\nThis section provides an overview of the IEEE-754 32-bit binary floating \npoint format.\\cite{ieee:754}\n\n\\begin{itemize}\n\\item Recall that the place values for integer binary numbers are:\n\\begin{verbatim}\n ... 128 64 32 16 8 4 2 1\n\\end{verbatim}\n\\item We can extend this to the right in binary similar to the way we do for \ndecimal numbers:\n\\begin{verbatim}\n ... 128 64 32 16 8 4 2 1 . 1/2 1/4 1/8 1/16 1/32 1/64 1/128 ...\n\\end{verbatim}\nThe `.' in a binary number is a binary point, not a decimal point.\n\n\\item We use scientific notation as in $2.7 \\times 10^{-47}$ to express either \nsmall fractions or large numbers when we are not concerned every last digit \nneeded to represent the entire, exact, value of a number.\n\n\\item The format of a number in scientific notation is $mantissa \\times base^{exponent}$\n\n\\item In binary we have $mantissa \\times 2^{exponent}$\n\n\\item IEEE-754 format requires binary numbers to be {\\em normalized} to \n$1.significand \\times 2^{exponent}$ where the {\\em significand}\nis the portion of the {\\em mantissa} that is to the right of the binary-point.\n\n\\begin{itemize}\n\\item The unnormalized binary value of $-2.625$ is $-10.101$\n\\item The normalized value of $-2.625$ is $-1.0101 \\times 2^1$\n\\end{itemize}\n\n\\item We need not store the `1.' part because {\\em all} normalized floating \npoint numbers will start that way. Thus we can save memory when storing\nnormalized values by inserting a `1.' to the left of significand.\n\n\n\n\\DrawBitBoxIEEEFloat{11000000001010000000000000000000}\n\n\n%{\n%\\small\n%\\setlength{\\unitlength}{.15in}\n%\\begin{picture}(32,4)(0,0)\n%\t\\put(0,1){\\line(1,0){32}}\t\t% bottom line\n%\t\\put(0,2){\\line(1,0){32}}\t\t% top line\n%\n%\t\\put(0,1){\\line(0,1){2}}\t\t% left vertical\n%\t\\put(0,2){\\makebox(1,1){\\tiny 31}}\t% left end bit number marker \n%\n%\t\\put(32,1){\\line(0,1){2}}\t\t% vertical right end \n%\t\\put(31,2){\\makebox(1,1){\\tiny 0}}\t% right end bit number marker\n%\n%\t\\put(0,0){\\makebox(1,1){\\small sign}}\n%\t\\put(1,0){\\makebox(8,1){\\small exponent}}\n%\t\\put(9,0){\\makebox(23,1){\\small significand}}\n%\n% \\put(0,1){\\makebox(1,1){1}}\t\t% sign\n%\n%\t\\put(1,1){\\line(0,1){2}}\t\t% seperator\n%\t\\put(1,2){\\makebox(1,1){\\tiny 30}}\t% bit marker\n%\n% \\put(1,1){\\makebox(1,1){1}}\t\t% exponent\n% \\put(2,1){\\makebox(1,1){0}}\n% \\put(3,1){\\makebox(1,1){0}}\n% \\put(4,1){\\makebox(1,1){0}}\n% \\put(5,1){\\makebox(1,1){0}}\n% \\put(6,1){\\makebox(1,1){0}}\n% \\put(7,1){\\makebox(1,1){0}}\n% \\put(8,1){\\makebox(1,1){0}}\n%\n%\t\\put(8,2){\\makebox(1,1){\\tiny 23}}\t% bit marker\n%\t\\put(9,1){\\line(0,1){2}}\t\t% seperator\n%\t\\put(9,2){\\makebox(1,1){\\tiny 22}}\t% bit marker\n%\n% \\put(9,1){\\makebox(1,1){0}}\n% \\put(10,1){\\makebox(1,1){1}}\n% \\put(11,1){\\makebox(1,1){0}}\n% \\put(12,1){\\makebox(1,1){1}}\n% \\put(13,1){\\makebox(1,1){0}}\n% \\put(14,1){\\makebox(1,1){0}}\n% \\put(15,1){\\makebox(1,1){0}}\n% \\put(16,1){\\makebox(1,1){0}}\n% \\put(17,1){\\makebox(1,1){0}}\n% \\put(18,1){\\makebox(1,1){0}}\n% \\put(19,1){\\makebox(1,1){0}}\n% \\put(20,1){\\makebox(1,1){0}}\n% \\put(21,1){\\makebox(1,1){0}}\n% \\put(22,1){\\makebox(1,1){0}}\n% \\put(23,1){\\makebox(1,1){0}}\n% \\put(24,1){\\makebox(1,1){0}}\n% \\put(25,1){\\makebox(1,1){0}}\n% \\put(26,1){\\makebox(1,1){0}}\n% \\put(27,1){\\makebox(1,1){0}}\n% \\put(28,1){\\makebox(1,1){0}}\n% \\put(29,1){\\makebox(1,1){0}}\n% \\put(30,1){\\makebox(1,1){0}}\n% \\put(31,1){\\makebox(1,1){0}}\n%\\end{picture}\n%}\n\n%\\item $-((1 + \\frac{1}{4} + \\frac{1}{16}) \\times 2^{128-127}) = -(1 \\frac{5}{16} \\times 2^{1}) = -(1.3125 \\times 2^{1}) = -2.625$\n\\item $-((1 + \\frac{1}{4} + \\frac{1}{16}) \\times 2^{128-127}) = -((1 + \\frac{1}{4} + \\frac{1}{16}) \\times 2^1) = -(2 + \\frac{1}{2} + \\frac{1}{8}) = -(2 + .5 + .125) = -2.625$\n\n\\item IEEE-754 formats: \n\n\\begin{tabular}{|l|l|l|}\n\\hline\n\t\t\t\t& IEEE-754 32-bit\t& IEEE-754 64-bit\t\\\\\n\\hline\nsign\t\t\t& 1 bit\t\t\t\t& 1 bit\t\t\t\\\\\nexponent\t\t& 8 bits (excess-127)\t\t\t& 11 bits (excess-1023)\t\t\\\\\nmantissa\t\t& 23 bits\t\t\t& 52 bits\t\t\\\\\nmax exponent\t& 127\t\t\t\t& 1023\t\t\t\\\\\nmin exponent\t& -126\t\t\t\t& -1022\t\t\t\\\\\n\\hline\n\\end{tabular}\n\n\\item When the exponent is all ones, the significand is all zeros, and\nthe sign is zero, the number represents positive infinity.\n\n\\item When the exponent is all ones, the significand is all zeros, and\nthe sign is one, the number represents negative infinity.\n\n\\item Observe that the binary representation of a pair of IEEE-754 numbers\n(when one or both are positive) can be compared for magnitude \nby treating them as if they are two's complement signed integers. \nThis is because an IEEE number is stored in {\\em signed magnitude} format and \ntherefore positive floating point values will grow upward and downward in the \nsame fashion as for unsigned integers and that since negative floating point \nvalues will have its MSB set, they will `appear` to be less than a positive \nfloating point value. \n\nWhen comparing two negative IEEE float values by treating them both as two's\ncomplement signed integers, the order will be reversed because IEEE float values \nwith larger (that is, increasingly negative) magnitudes will appear to decrease \nin value when interpreted as signed integers.\n\nThis works this way because excess notation is used in the format of the \nexponent and why the significand's sign bit is located on the left of \nthe exponent.\\footnote{I know this is true and was done on purpose because\nBill Cody, chairman of IEEE committee P754 that designed the IEEE-754 standard, \ntold me so personally circa 1991.}\n\n\\item Note that zero is a special case number. Recall that a normalized\nnumber has an implied 1-bit to the left of the significand\\ldots\\ which\nmeans that there is no way to represent zero!\nZero is represented by an exponent of all-zeros and a significand of \nall-zeros. This definition allows for a positive and a negative zero \nif we observe that the sign can be either 1 or 0.\n\n\\item On the number-line, numbers between zero and the smallest fraction in \neither direction are in the {\\em \\gls{underflow}} areas.\n\\enote{Need to add the standard lecture number-line diagram showing\nwhere the over/under-flow areas are and why.}\n\n\\item On the number line, numbers greater than the mantissa of all-ones and the \nlargest exponent allowed are in the {\\em \\gls{overflow}} areas.\n\n\\item Note that numbers have a higher resolution on the number line when the \nexponent is smaller.\n\n\\item The largest and smallest possible exponent values are reserved to represent\nthings requiring special cases. For example, the infinities, values representing\n``not a number'' (such as the result of dividing by zero), and for a way to represent\nvalues that are not normalized. For more information on special cases see \\cite{ieee:754}.\n\n\\end{itemize}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{Floating Point Number Accuracy}\nDue to the finite number of bits used to store the value of a floating point\nnumber, it is not possible to represent every one of the infinite values\non the real number line. The following C programs illustrate this point.\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsubsection{Powers Of Two}\nJust like the integer numbers, the powers of two that have bits to represent \nthem can be represented perfectly\\ldots\\ as can their sums (provided that the\nsignificand requires no more than 23 bits.)\n\n\\listing{powersoftwo.c}{Precise Powers of Two} \n\\listing{powersoftwo.out}{Output from {\\tt powersoftwo.c}}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsubsection{Clean Decimal Numbers}\nWhen dealing with decimal values, you will find that they don't map simply\ninto binary floating point values.\n% (the same holds true for binary integer numbers). \n\nNote how the decimal numbers are not accurately represented as they get larger.\nThe decimal number on line 10 of \\listingRef{cleandecimal.out}\ncan be perfectly represented in IEEE format. However, a problem arises in \nthe 11Th loop iteration. It is due to the fact that the\nbinary number can not be represented accurately in IEEE format. Its least\nsignificant bits were truncated in a best-effort attempt at rounding the value\noff in order to fit the value into the bits provided. This is an example of\n{\\em low order truncation}. Once this happens, the value of \\verb@x.f@ is\nno longer as precise as it could be given more bits in which to save its value.\n\n\\listing{cleandecimal.c}{Print Clean Decimal Numbers} \n\\listing{cleandecimal.out}{Output from {\\tt cleandecimal.c}}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsubsection{Accumulation of Error}\nThese rounding errors can be exaggerated when the number we multiply \nthe \\verb@x.f@ value by is, itself, something that can not be accurately \nrepresented in IEEE \nform.\\footnote{Applications requiring accurate decimal values, such as \nfinancial accounting systems, can use a packed-decimal numeric format\nto avoid unexpected oddities caused by the use of binary numbers.}\n\\enote{In a lecture one would show that one tenth is a repeating \nnon-terminating binary number that gets truncated. This discussion \nshould be reproduced here in text form.}\n\nFor example, if we multiply our \\verb@x.f@ value by $\\frac{1}{10}$ each time, \nwe can never be accurate and we start accumulating errors immediately.\n\n\\listing{erroraccumulation.c}{Accumulation of Error} \n\\listing{erroraccumulation.out}{Output from {\\tt erroraccumulation.c}}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{Reducing Error Accumulation} \nIn order to use floating point numbers in a program without causing \nexcessive rounding problems an algorithm can be redesigned such that the \naccumulation is eliminated. \nThis example is similar to the previous one, but this time we recalculate the \ndesired value from a known-accurate integer value. \nSome rounding errors remain present, but they can not accumulate.\n\n\\listing{errorcompensation.c}{Accumulation of Error} \n\\listing{errorcompensation.out}{Output from {\\tt erroraccumulation.c}}\n" }, { "path": "book/float/cleandecimal.c", "content": "#include \n#include \n#include \n\nunion floatbin\n{\n unsigned int i;\n float f;\n};\nint main()\n{\n union floatbin x, y;\n int i;\n\n x.f = 10;\n while (x.f <= 10000000000000.0)\n {\n y.f = -x.f;\n printf(\"%25.10f = %08x %25.10f = %08x\\n\", x.f, x.i, y.f, y.i);\n x.f = x.f*10.0;\n }\n}\n" }, { "path": "book/float/cleandecimal.out", "content": " 10.0000000000 = 41200000 -10.0000000000 = c1200000\n 100.0000000000 = 42c80000 -100.0000000000 = c2c80000\n 1000.0000000000 = 447a0000 -1000.0000000000 = c47a0000\n 10000.0000000000 = 461c4000 -10000.0000000000 = c61c4000\n 100000.0000000000 = 47c35000 -100000.0000000000 = c7c35000\n 1000000.0000000000 = 49742400 -1000000.0000000000 = c9742400\n 10000000.0000000000 = 4b189680 -10000000.0000000000 = cb189680\n 100000000.0000000000 = 4cbebc20 -100000000.0000000000 = ccbebc20\n 1000000000.0000000000 = 4e6e6b28 -1000000000.0000000000 = ce6e6b28\n 10000000000.0000000000 = 501502f9 -10000000000.0000000000 = d01502f9\n 99999997952.0000000000 = 51ba43b7 -99999997952.0000000000 = d1ba43b7\n 999999995904.0000000000 = 5368d4a5 -999999995904.0000000000 = d368d4a5\n 9999999827968.0000000000 = 551184e7 -9999999827968.0000000000 = d51184e7\n" }, { "path": "book/float/erroraccumulation.c", "content": "#include \n#include \n#include \n\nunion floatbin\n{\n unsigned int i;\n float f;\n};\nint main()\n{\n union floatbin x, y;\n int i;\n\n x.f = .1;\n while (x.f <= 2.0)\n {\n y.f = -x.f;\n printf(\"%25.10f = %08x %25.10f = %08x\\n\", x.f, x.i, y.f, y.i);\n x.f += .1;\n }\n}\n" }, { "path": "book/float/erroraccumulation.out", "content": "0.1000000015 = 3dcccccd -0.1000000015 = bdcccccd\n0.2000000030 = 3e4ccccd -0.2000000030 = be4ccccd\n0.3000000119 = 3e99999a -0.3000000119 = be99999a\n0.4000000060 = 3ecccccd -0.4000000060 = becccccd\n0.5000000000 = 3f000000 -0.5000000000 = bf000000\n0.6000000238 = 3f19999a -0.6000000238 = bf19999a\n0.7000000477 = 3f333334 -0.7000000477 = bf333334\n0.8000000715 = 3f4cccce -0.8000000715 = bf4cccce\n0.9000000954 = 3f666668 -0.9000000954 = bf666668\n1.0000001192 = 3f800001 -1.0000001192 = bf800001\n1.1000001431 = 3f8cccce -1.1000001431 = bf8cccce\n1.2000001669 = 3f99999b -1.2000001669 = bf99999b\n1.3000001907 = 3fa66668 -1.3000001907 = bfa66668\n1.4000002146 = 3fb33335 -1.4000002146 = bfb33335\n1.5000002384 = 3fc00002 -1.5000002384 = bfc00002\n1.6000002623 = 3fcccccf -1.6000002623 = bfcccccf\n1.7000002861 = 3fd9999c -1.7000002861 = bfd9999c\n1.8000003099 = 3fe66669 -1.8000003099 = bfe66669\n1.9000003338 = 3ff33336 -1.9000003338 = bff33336\n" }, { "path": "book/float/errorcompensation.c", "content": "#include \n#include \n#include \n\nunion floatbin \n{\n unsigned int i;\n float f;\n};\nint main()\n{\n union floatbin x, y; \n int i;\n\n i = 1;\n while (i <= 20)\n {\n x.f = i/10.0;\n y.f = -x.f;\n printf(\"%25.10f = %08x %25.10f = %08x\\n\", x.f, x.i, y.f, y.i);\n i++; \n }\n return(0); \n}\n" }, { "path": "book/float/errorcompensation.out", "content": "0.1000000015 = 3dcccccd -0.1000000015 = bdcccccd\n0.2000000030 = 3e4ccccd -0.2000000030 = be4ccccd\n0.3000000119 = 3e99999a -0.3000000119 = be99999a\n0.4000000060 = 3ecccccd -0.4000000060 = becccccd\n0.5000000000 = 3f000000 -0.5000000000 = bf000000\n0.6000000238 = 3f19999a -0.6000000238 = bf19999a\n0.6999999881 = 3f333333 -0.6999999881 = bf333333\n0.8000000119 = 3f4ccccd -0.8000000119 = bf4ccccd\n0.8999999762 = 3f666666 -0.8999999762 = bf666666\n1.0000000000 = 3f800000 -1.0000000000 = bf800000\n1.1000000238 = 3f8ccccd -1.1000000238 = bf8ccccd\n1.2000000477 = 3f99999a -1.2000000477 = bf99999a\n1.2999999523 = 3fa66666 -1.2999999523 = bfa66666\n1.3999999762 = 3fb33333 -1.3999999762 = bfb33333\n1.5000000000 = 3fc00000 -1.5000000000 = bfc00000\n1.6000000238 = 3fcccccd -1.6000000238 = bfcccccd\n1.7000000477 = 3fd9999a -1.7000000477 = bfd9999a\n1.7999999523 = 3fe66666 -1.7999999523 = bfe66666\n1.8999999762 = 3ff33333 -1.8999999762 = bff33333\n2.0000000000 = 40000000 -2.0000000000 = c0000000\n" }, { "path": "book/float/powersoftwo.c", "content": "#include \n#include \n#include \n\nunion floatbin\n{\n unsigned int i;\n float f;\n};\nint main()\n{\n union floatbin x;\n\tunion floatbin\ty;\n int i;\n x.f = 1.0;\n while (x.f > 1.0/1024.0)\n {\n y.f = -x.f;\n printf(\"%25.10f = %08x %25.10f = %08x\\n\", x.f, x.i, y.f, y.i);\n x.f = x.f/2.0;\n }\n}\n" }, { "path": "book/float/powersoftwo.out", "content": "1.0000000000 = 3f800000 -1.0000000000 = bf800000\n0.5000000000 = 3f000000 -0.5000000000 = bf000000\n0.2500000000 = 3e800000 -0.2500000000 = be800000\n0.1250000000 = 3e000000 -0.1250000000 = be000000\n0.0625000000 = 3d800000 -0.0625000000 = bd800000\n0.0312500000 = 3d000000 -0.0312500000 = bd000000\n0.0156250000 = 3c800000 -0.0156250000 = bc800000\n0.0078125000 = 3c000000 -0.0078125000 = bc000000\n0.0039062500 = 3b800000 -0.0039062500 = bb800000\n0.0019531250 = 3b000000 -0.0019531250 = bb000000\n" }, { "path": "book/glossary.tex", "content": "\\newglossaryentry{latex}\n{\n name=LaTeX,\n description={Is a mark up language specially suited\n \tfor scientific documents}\n}\n\n\\newglossaryentry{binary}\n{\n\tname=binary,\n\tdescription={Something that has two parts or states. In computing\n\t\tthese two states are represented by the numbers one and zero or\n\t\tby the conditions true and false and can be stored in one \\gls{bit}}\n}\n\\newglossaryentry{hexadecimal}\n{\n\tname=hexadecimal,\n\tdescription={A base-16 numbering system whose digits are 0123456789abcdef. \n\t\tThe hex digits (\\gls{hit}s) are not case-sensitive}\n}\n\\newglossaryentry{bit}\n{\n\tname=bit,\n\tdescription={One binary digit}\n}\n\\newglossaryentry{hit}\n{\n\tname={hit},\n\tdescription={One \\gls{hexadecimal} digit}\n}\n\\newglossaryentry{nybble}\n{\n\tname={nybble},\n\tdescription={Half of a {\\em \\gls{byte}} is a {\\em nybble}\n\t\t(sometimes spelled nibble.) Another word for {\\em \\gls{hit}}}\n}\n\\newglossaryentry{byte}\n{\n\tname=byte,\n\tdescription={A \\gls{binary} value represented by 8 \\gls{bit}s}\n}\n\\newglossaryentry{halfword}\n{\n\tname={halfword},\n\tdescription={A \\gls{binary} value represented by 16 \\gls{bit}s}\n}\n\\newglossaryentry{fullword}\n{\n\tname={fullword},\n\tdescription={A \\gls{binary} value represented by 32 \\gls{bit}s}\n}\n\\newglossaryentry{doubleword}\n{\n\tname={doubleword},\n\tdescription={A \\gls{binary} value represented by 64 \\gls{bit}s}\n}\n\\newglossaryentry{quadword}\n{\n\tname={quadword},\n\tdescription={A \\gls{binary} value represented by 128 \\gls{bit}s}\n}\n\\newglossaryentry{HighOrderBits}\n{\n\tname={high order bits},\n\tdescription={Some number of \\acrshort{msb}s}\n}\n\\newglossaryentry{LowOrderBits}\n{\n name={low order bits},\n description={Some number of \\acrshort{lsb}s}\n}\n\n\\newglossaryentry{xlen}\n{\n\tname=XLEN,\n\tdescription={The number of bits a RISC-V x integer \\gls{register}\n\t\t(such as x0). For RV32 XLEN=32, RV64 XLEN=64 and so on}\n}\n\\newglossaryentry{rv32}\n{\n\tname=RV32,\n\tdescription={Short for RISC-V 32. The number 32 refers to the \\gls{xlen}}\n}\n\\newglossaryentry{rv64}\n{\n\tname=RV64,\n\tdescription={Short for RISC-V 64. The number 64 refers to the \\gls{xlen}}\n}\n\\newglossaryentry{overflow}\n{\n\tname=overflow,\n\tdescription={The situation where the result of an addition or \n\t\tsubtraction operation is approaching positive or negative \n\t\tinfinity and exceeds the number of bits allotted to contain \n\t\tthe result. This is typically caused by high-order truncation}\n}\n\\newglossaryentry{underflow}\n{\n\tname=underflow,\n\tdescription={The situation where the result of an addition or \n\t\tsubtraction operation is approaching zero and exceeds the number \n\t\tof bits allotted to contain the result. This is typically\n caused by low-order truncation}\n}\n\n\\newglossaryentry{MachineLanguage}\n{\n\tname={machine language},\n\tdescription={The instructions that are executed by a CPU that are expressed\n\t\tin the form of \\gls{binary} values}\n}\n\\newglossaryentry{register}\n{\n\tname={register},\n\tdescription={A unit of storage inside a CPU with the capacity of \\gls{xlen} \\gls{bit}s}\n}\n\\newglossaryentry{program}\n{\n\tname={program},\n\tdescription={A ordered list of one or more instructions}\n}\n\\newglossaryentry{address}\n{\n\tname={address},\n\tdescription={A numeric value used to uniquely identify each \\gls{byte} of main memory}\n}\n\\newglossaryentry{alignment}\n{\n\tname={alignment},\n\tdescription={Refers to a range of numeric values that begin \n\t\tat a multiple of some number. Primarily used when referring to\n\t\ta memory address. For example an alignment of two refers to one\n\t\tor more addresses starting at even address and continuing onto\n\t\tsubsequent adjacent, increasing memory addresses}\n}\n\\newglossaryentry{exception}\n{\n\tname={exception},\n\tdescription={An error encountered by the CPU while executing an instruction\n\t\tthat can not be completed}\n}\n\n\\newglossaryentry{bigendian}\n{\n\tname={big-endian},\n\tdescription={A number format where the most significant values are \n\tprinted to the left of the lesser significant values. This is the\n\tmethod that everyone uses to write decimal numbers every day}\n}\n\\newglossaryentry{littleendian}\n{\n\tname={little-endian},\n\tdescription={A number format where the least significant values are \n\t\tprinted to the left of the more significant values. This is the\n\t\topposite ordering that everyone learns in grade school when learning\n\t\thow to count. For example, the \\gls{bigendian} number written as ``1234''\n\t\twould be written in little endian form as ``4321''}\n}\n\\newglossaryentry{rvddt}\n{\n\tname={rvddt},\n\tdescription={A RV32I simulator and debugging tool inspired by the \n\t\tsimplicity of the Dynamic Debugging Tool (ddt) that was part of \n\t\tthe CP/M operating system}\n}\n\\newglossaryentry{mnemonic}\n{\n\tname={mnemonic},\n\tdescription={A method used to remember something. In the case of\n\t\tassembly language, each machine instruction is given a name\n\t\tso the programmer need not memorize the binary values of each\n\t\tmachine instruction}\n}\n\\newglossaryentry{thread}\n{\n\tname={thread},\n\tdescription={An stream of instructions. When plural, it is\n\t\tused to refer to the ability of a CPU to execute multiple \n\t\tinstruction streams at the same time}\n}\n\\newglossaryentry{ascii}\n{\n\tname={ASCII},\n\tdescription={American Standard Code for Information Interchange.\n\t\tSee \\autoref{chapter:ascii}}\n}\n\\newglossaryentry{place-value}\n{\n\tname={place value},\n\tdescription={the numerical value that a digit has as a result of its {\\em position} within a number.\n\tFor example, the digit 2 in the decimal number 123 is in the ten's place and its place value is 20}\n}\n\n\n\\newacronym{hart}{hart}{Hardware Thread}\n\\newacronym{msb}{MSB}{Most Significant Bit}\n\\newacronym{lsb}{LSB}{Least Significant Bit}\n\\newacronym{isa}{ISA}{Instruction Set Architecture}\n\\newacronym{cpu}{CPU}{Central Processing Unit}\n\\newacronym{ram}{RAM}{Random Access Memory}\n\\newacronym{rom}{ROM}{Read Only Memory}\n%\\newacronym{ascii}{ASCII}{American Standard Code for Information Interchange}\n" }, { "path": "book/insnformats.tex", "content": "\n\\def\\SignBoxCornerRadius{.75mm}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\newcommand\\BeginTikzPicture{\n %\\begin{tikzpicture}[x=.4cm,y=.3cm]\n \\begin{tikzpicture}[x=.35cm,y=.3cm]\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\newcommand\\EndTikzPicture{\n \\end{tikzpicture}\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% Print the characters within a string evenly spaced at integral node positions\n%\n% #1 The number of characters in the string\n% #2 The string to print\n\\newcommand\\DrawBitstring[2]{\n\\foreach \\x in {1,...,#1}%\n\t\\draw(\\x,0) node{\\substring{#2}{\\x}{\\x}};%\n%\t\\draw(\\x,.5) node[text width = 10, text height = 1]{\\substring{#2}{\\x}{\\x}};%\tImprove vertical text alignment\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% #1 The total size\n% #2 The string to print\n% #3 The value to use when extending to left\n\\newcommand\\DrawLeftExtendedBitstring[3]{\n\t\\StrLen{#2}[\\numchars]\n\n\t\\pgfmathsetmacro\\leftpadd{int(#1-\\numchars)}\n\t\\foreach \\x in {1,...,\\leftpadd}\n \t\\draw(\\x,0) node{#3};\n\n\t\\pgfmathsetmacro\\leftpadd{int(\\leftpadd+1)}\n\t\\foreach \\x in {\\leftpadd,...,#1}\n\t\t\\pgfmathsetmacro\\ix{int(\\x-\\leftpadd+1)}\n\t\t\\draw(\\x,0) node{\\substring{#2}{\\ix}{\\ix}};\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% If the string is shorter than expected, extend with #5 to the right.\n%\n% #1 The total size\n% #2 Num chars to extend on the right\n% #3 The string to print\n% #4 The value to use when extending to left\n% #5 The value to use when extending to right\n\\newcommand\\DrawDoubleExtendedBitstring[5]{\n\t\\StrLen{#3}[\\numchars]\n\n\t\\pgfmathsetmacro\\leftpadd{int(#1-#2-\\numchars)}\n\t\\ifthenelse{1 > \\leftpadd}\n\t{}\n\t{\n\t\t\\foreach \\x in {1,...,\\leftpadd}\n \t\t\\draw(\\x,0) node{#4};\n\t}\n\n\t\\pgfmathsetmacro\\leftpadd{int(\\leftpadd+1)}\n\t\\pgfmathsetmacro\\rightpadd{int(\\leftpadd+\\numchars)}\n\t\\foreach \\x in {\\leftpadd,...,\\rightpadd}\n\t\t\\pgfmathsetmacro\\ix{int(\\x-\\leftpadd+1)}\n\t\t\\draw(\\x,0) node{\\substring{#3}{\\ix}{\\ix}};\n\n\n\t%\\pgfmathsetmacro\\rightpadd{int(\\rightpadd+1)}\n\t\\ifthenelse{\\rightpadd > #1}\t\n\t{}\n\t{\n\t\t\\foreach \\x in {\\rightpadd,...,#1}\n\t\t\t\\draw(\\x,0) node{#5};\n\t}\n}\n\n\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% Draw a box suitable to show the given number of bits in a \n% labeled box suitable for showing expanded binary numbers.\n%\n% #1 The number of characters to display\n\\newcommand\\DrawBitBox[1]{\n \\draw (.5,-.75) -- (#1+.5,-.75);\t\t% box bottom\n \\draw (.5,.75) -- (#1+.5,.75);\t\t\t% box top\n \\draw (.5,-.75) -- (.5, 1.5);\t\t\t% left end\n \\draw (#1+.5,-.75) -- (#1+.5, 1.5);\t\t% right end\n \\pgfmathsetmacro\\result{int(#1-1)}\t\t% calc high bit \n \\node at (1,1.2) {\\tiny\\result};\t\t% high bit label\n \\draw(#1,1.2) node{\\tiny0};\t\t\t\t% low bit label\n\n \\pgfmathsetmacro\\result{#1/2}\n \\node at (\\result,-1.2) {\\tiny#1};\t\t% size below the box\n\n \\pgfmathsetmacro\\result{#1/2}\n \\draw[->] (\\result+.6,-1.2) -- (#1+.5,-1.2);\n \\draw[->] (\\result-.6,-1.2) -- (.5,-1.2);\n}\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\newcommand\\DrawBitBoxUnsigned[1]{\n\t\\StrLen{#1}[\\numchars]\n\t\\DrawBitBox{\\numchars}\n\t\\DrawBitstring{\\numchars}{#1}\t\t% show the bits\n}\n\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\newcommand\\DrawBitBoxUnsignedPicture[1]{\n\t\\BeginTikzPicture\n\t\\DrawBitBoxUnsigned{#1}\n\t\\EndTikzPicture\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\newcommand\\DrawBitBoxSignedPicture[1]{\n \\BeginTikzPicture\n \\DrawBitBoxUnsigned{#1}\n\t% draw a box around the sign bit\n\t\\draw {[rounded corners=\\SignBoxCornerRadius] (1.35, -.6) -- (1.35, .6) -- (.65, .6) -- (.65, -.6) -- cycle};\n \\EndTikzPicture\n}\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% #1 The total (extended) size\n% #2 The value to use for left-side padding\n% #3 The string to extend\n\\newcommand\\DrawBitBoxLeftExtended[3]{\n\t\\StrLen{#3}[\\numchars]\n\t\\pgfmathsetmacro\\fill{int(#1-\\numchars)}\n\t\\begin{scope}[shift={(\\fill,3.5)}]\n \\DrawBitBoxUnsigned{#3}\n\n \t% XXX IFF not zero-extending then draw a box around the sign bit\n \t\\draw {[rounded corners=\\SignBoxCornerRadius] (1.35, -.6) -- (1.35, .6) -- (.65, .6) -- (.65, -.6) -- cycle};\n\t\\end{scope}\n\n\t\\DrawBitBox{#1}\n\t\\DrawDoubleExtendedBitstring{#1}{0}{#3}{#2}{x}\n\t\n \t% XXX IFF not zero-extending then draw a box around the sign bit\n \t\\draw {[rounded corners=\\SignBoxCornerRadius] (\\fill+1.35, -.6) -- (\\fill+1.35, .6) -- (\\fill+.65, .6) -- (\\fill+.65, -.6) -- cycle};\n % draw a box around the extended sign bits\n \\draw (.65, -.6) -- (.65, .6) -- (\\fill+.35, .6) -- (\\fill+.35, -.6) -- cycle;\n\n\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\newcommand\\DrawBitBoxSignExtendedPicture[2]{\n\t\\BeginTikzPicture\n\t\\DrawBitBoxLeftExtended{#1}{\\substring{#2}{1}{1}}{#2}\n \\EndTikzPicture\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\newcommand\\DrawBitBoxZeroExtendedPicture[2]{\n\t\\BeginTikzPicture\n\t\\DrawBitBoxLeftExtended{#1}{0}{#2}\n \\EndTikzPicture\n}\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% #1 Total bit length\n% #2 The string to print\n% #3 Right-side padding length\n\\newcommand\\DrawBitBoxSignLeftZeroRightExtendedPicture[3]{\n\t\\BeginTikzPicture\n\n\t\\StrLen{#2}[\\numchars]\n\t\\pgfmathsetmacro\\fill{int(#1-\\numchars-#3)}\n\t\\begin{scope}[shift={(\\fill,3.5)}]\n \\DrawBitBoxUnsigned{#2}\n % draw a box around the sign bit\n %\\draw (1.35, -.6) -- (1.35, .6) -- (.65, .6) -- (.65, -.6) -- cycle;\n \\draw {[rounded corners=\\SignBoxCornerRadius] (1.35, -.6) -- (1.35, .6) -- (.65, .6) -- (.65, -.6) -- cycle};\n\t\\end{scope}\n\n\t\\DrawBitBox{#1}\n\t\\DrawDoubleExtendedBitstring{#1}{#3}{#2}{\\substring{#2}{1}{1}}{0}\n\n\t% Box the sign bit\n \\draw {[rounded corners=\\SignBoxCornerRadius] (\\fill+1.35, -.6) -- (\\fill+1.35, .6) -- (\\fill+.65, .6) -- (\\fill+.65, -.6) -- cycle};\n\n\t\\ifthenelse{\\fill > 0}\n\t{\n \t% Box the left-extended sign bits\n \t\\draw (.65, -.6) -- (.65, .6) -- (\\fill+.35, .6) -- (\\fill+.35, -.6) -- cycle;\n\t\t% \\fill[blue!40!white] (.65, -.6) rectangle (\\fill-.25, 1.2);\n\t}\n\t{}\n\t\\ifthenelse{#3 > 0}\n\t{\n \t% Box the right-extended sign bits\n\t\t\\pgfmathsetmacro\\posn{int(\\numchars+\\fill)}\n \t\\draw (\\posn+.65, -.6) -- (\\posn+.65, .6) -- (\\posn+#3+.35, .6) -- (\\posn+#3+.35, -.6) -- cycle;\n\t}\n\t{}\n\t\n\n \\EndTikzPicture\n}\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%\n% Draw hex markers\n% #1 The number of bits in the box\n\\newcommand\\DrawHexMarkers[1]{\n\t\\pgfmathsetmacro\\num{int(#1-1)}\n\t\\foreach \\x in {4,8,...,\\num}\n\t\t\\draw [line width=.5mm] (\\x+.5,-.75) -- (\\x+.5, -.3);\n}\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% Print the characters within a string evenly spaced at integral node positions\n%\n% #1 The number of characters in the string\n% #2 The string of characters to plot\n% #3 Right-side label\n\\newcommand\\DrawInsnBitstring[3]{\n\t\\pgfmathsetmacro\\num{int(#1-1)}\n\t\\foreach \\x in {1,2,...,#1}\n \t\\draw(\\x+.25,-.3) node[text width = 10, text height = 1]{\\substring{#2}{\\x}{\\x}};\n\t\\draw(#1+1,0) node[right]{#3};\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% Draw a bit-separator line with labels at the given bit-offset (from the right)\n%\n% #1 Total box width\n% #2 The position that the separator will be drawn to the left.\n\\newcommand\\DrawInsnBoxSep[2]{\n\t\\draw (#1-#2-.5,-.75) -- (#1-#2-.5, 1.5);\n\t\\node at (#1-#2,1.2) {\\tiny#2};\n\t\\pgfmathsetmacro\\result{int(#2+1)}\n\t\\node at (#1-#2-1,1.2) {\\tiny\\result};\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% #1 total characters/width\n% #2 MSB position\n% #3 LSB position\n% #4 the segment label\n\\newcommand\\DrawInsnBoxSeg[4]{\n\t\\pgfmathsetmacro\\leftpos{int(#1-#2)}\n\t\\pgfmathsetmacro\\rightpos{int(#1-#3)}\n\n\t\\draw (\\leftpos-.5,-.75) -- (\\rightpos+.5,-.75);\t% box bottom\n\t\\draw (\\leftpos-.5,1.75) -- (\\rightpos+.5,1.75);\t% box top\n\t\\draw (\\leftpos-.5,-.75) -- (\\leftpos-.5, 2.5);\t\t% left end\n\t\\draw (\\rightpos+.5,-.75) -- (\\rightpos+.5, 2.5);\t% right end\n\t\\node at (\\leftpos,2.2) {\\tiny#2};\n\t\\draw(\\rightpos,2.2) node{\\tiny#3};\n\n\t\\pgfmathsetmacro\\posn{#1-#2+(#2-#3)/2}\n\t\\pgfmathsetmacro\\range{int(#2-#3+1)}\n\t\\node at (\\posn,1.2) {\\small#4};\t\t\t% the field label\n\n%\t\\node at (\\posn,-1.4) {\\small\\range};\t\t% the field width\n\t\\begin{scope}[shift={(0,-.7)}]\\InsnBoxFieldWidthArrow{#2}{#3}\\end{scope}\n\n%\t% arrows showing the span of the bits... meh\n% \\draw[->] (\\posn+.5,-1.4) -- (\\rightpos+.2,-1.4);\n% \\draw[->] (\\posn-.5,-1.4) -- (\\leftpos-.2,-1.4);\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\newcommand\\InsnStatement[1]{\n%\t\\textbf{\\large #1}\\\\\n%\t\\textbf{#1}\\\\\n\t{\\large #1}\n}\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\newcommand\\DrawInsnTypeB[1]{\n\t\\StrLen{#1}[\\numchars]\n\t\\begin{scope}[shift={(0,.75)}]\t\n\t\\DrawInsnBitstring{\\numchars}{#1}{\\hyperref[insnformat:btype]{B-type}}\n\t\\DrawInsnBoxSeg{\\numchars}{31}{25}{imm[12\\textbar10:5]}\n\t\\DrawInsnBoxSeg{\\numchars}{24}{20}{rs2}\n\t\\DrawInsnBoxSeg{\\numchars}{19}{15}{rs1}\n\t\\DrawInsnBoxSeg{\\numchars}{14}{12}{funct3}\n\t\\DrawInsnBoxSeg{\\numchars}{11}{7}{imm[4:1\\textbar11]}\n\t\\DrawInsnBoxSeg{\\numchars}{6}{0}{opcode}\n\n\t% add some hint bits in for imm fields\n\t\\draw {[rounded corners=\\SignBoxCornerRadius] (1.35, -.6) -- (1.35, .6) -- (.65, .6) -- (.65, -.6) -- cycle};\t% sign bit\n\t\\draw (32-7-.5, -.75) -- (32-7-.5, .1);\t\t% imm[11]\n\t\\draw (32-30-.5, -.75) -- (32-30.5, .1);\t% imm[12]\n\n\t\\end{scope}\n\n\t\\DrawHexMarkersRel{\\numchars}\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% #1 the binary encoding\n\\newcommand\\DrawInsnTypeBTikz[1]{\n\t\\BeginTikzPicture\n\t\\DrawInsnTypeB{#1}\n\t\\EndTikzPicture\n}\n\n\\newcommand\\DrawInsnTypeBPicture[2]{\n\t\\InsnStatement{#1}\\\\\n\t\\DrawInsnTypeBTikz{#2}\n}\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% #1 the binary encoding\n\\newcommand\\DrawInsnTypeU[1]{\n\t\\StrLen{#1}[\\numchars]\n\t\\begin{scope}[shift={(0,.75)}]\n\t\\DrawInsnBitstring{\\numchars}{#1}{\\hyperref[insnformat:utype]{U-type}}\n\t\\DrawInsnBoxSeg{\\numchars}{31}{12}{imm[31:12]}\n\t\\DrawInsnBoxSeg{\\numchars}{11}{7}{rd}\n\t\\DrawInsnBoxSeg{\\numchars}{6}{0}{opcode}\n\n\t% add some hint bits in for imm fields\n\t\\draw {[rounded corners=\\SignBoxCornerRadius] (1.35, -.6) -- (1.35, .6) -- (.65, .6) -- (.65, -.6) -- cycle};\t% sign bit\n\t\\end{scope}\n\n\t\\DrawHexMarkersRel{\\numchars}\n}\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% #1 the binary encoding\n\\newcommand\\DrawInsnTypeUTikz[1]{\n\t\\BeginTikzPicture\n\t\\DrawInsnTypeU{#1}\n\t\\EndTikzPicture\n}\n\n\\newcommand\\DrawInsnTypeUPicture[2]{\n\t\\InsnStatement{#1}\\\\\n\t\\DrawInsnTypeUTikz{#2}\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% #1 the binary encoding\n\\newcommand\\DrawInsnTypeJ[1]{\n\t\\StrLen{#1}[\\numchars]\n\t\\begin{scope}[shift={(0,.75)}]\t\n\t\\DrawInsnBitstring{\\numchars}{#1}{\\hyperref[insnformat:jtype]{J-type}}\n\n\t\\DrawInsnBoxSeg{\\numchars}{31}{12}{imm[20\\textbar10:1\\textbar11\\textbar19:12]}\n\t\\DrawInsnBoxSeg{\\numchars}{11}{7}{rd}\n\t\\DrawInsnBoxSeg{\\numchars}{6}{0}{opcode}\n%\t\\DrawHexMarkers{\\numchars}\n\t\\end{scope}\n\n\t% add some hint bits in for imm fields\n\t\\draw {[rounded corners=\\SignBoxCornerRadius] (1.35, .15) -- (1.35, 1.35) -- (.65, 1.35) -- (.65, .15) -- cycle};\t% sign bit\n\t\\draw (32-19-.5, 0) -- (32-19.5, .85);\t\t% imm[19:12]\n\t\\draw (32-20-.5, 0) -- (32-20.5, .85);\t\t% imm[11]\n\t\\draw (32-30-.5, 0) -- (32-30.5, .85);\t\t% imm[1:10]\n\t\\DrawHexMarkersRel{\\numchars}\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% #1 the binary encoding\n\\newcommand\\DrawInsnTypeJTikz[1]{\n\t\\BeginTikzPicture\n\t\\DrawInsnTypeJ{#1}\n%\t\\StrLen{#1}[\\numchars]\n%\t\\DrawInsnBitstring{\\numchars}{#1}{\\hyperref[insnformat:jtype]{J-type}}\n%\t\\DrawInsnBoxSeg{\\numchars}{31}{12}{imm[20\\textbar10:1\\textbar11\\textbar19:12]}\n%\t\\DrawInsnBoxSeg{\\numchars}{11}{7}{rd}\n%\t\\DrawInsnBoxSeg{\\numchars}{6}{0}{opcode}\n%\n%\t% add some hint bits in for imm fields\n%\t\\draw {[rounded corners=\\SignBoxCornerRadius] (1.35, -.6) -- (1.35, .6) -- (.65, .6) -- (.65, -.6) -- cycle};\t% sign bit\n%\t\\draw (32-19-.5, -.75) -- (32-19.5, .1);\t\t% imm[19:12]\n%\t\\draw (32-20-.5, -.75) -- (32-20.5, .1);\t\t% imm[11]\n%\t\\DrawHexMarkers{\\numchars}\n\n\t\\EndTikzPicture\n}\n\n\\newcommand\\DrawInsnTypeJPicture[2]{\n\t\\InsnStatement{#1}\\\\\n\t\\DrawInsnTypeJTikz{#2}\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% #1 the binary encoding\n\\newcommand\\DrawInsnTypeI[1]{\n\t\\StrLen{#1}[\\numchars]\n\t\\begin{scope}[shift={(0,.75)}]\t\n\t\\DrawInsnBitstring{\\numchars}{#1}{\\hyperref[insnformat:itype]{I-type}}\n\t\\DrawInsnBoxSeg{\\numchars}{31}{20}{imm[11:0]}\n\t\\DrawInsnBoxSeg{\\numchars}{19}{15}{rs1}\n\t\\DrawInsnBoxSeg{\\numchars}{14}{12}{funct3}\n\t\\DrawInsnBoxSeg{\\numchars}{11}{7}{rd}\n\t\\DrawInsnBoxSeg{\\numchars}{6}{0}{opcode}\n\n\t% add some hint bits in for imm fields\n\t\\draw {[rounded corners=\\SignBoxCornerRadius] (1.35, -.6) -- (1.35, .6) -- (.65, .6) -- (.65, -.6) -- cycle};\t% sign bit\n\t\\end{scope}\n\t\\DrawHexMarkersRel{\\numchars}\n}\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% #1 the binary encoding\n\\newcommand\\DrawInsnTypeITikz[1]{\n\t\\BeginTikzPicture\n\t\\DrawInsnTypeI{#1}\n%\t\\DrawHexMarkers{\\numchars}\n\t\\EndTikzPicture\n}\n\\newcommand\\DrawInsnTypeIPicture[2]{\n\t\\InsnStatement{#1}\\\\\n\t\\DrawInsnTypeITikz{#2}\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% #1 the binary encoding\n\\newcommand\\DrawInsnTypeS[1]{\n\t\\StrLen{#1}[\\numchars]\n\t\\begin{scope}[shift={(0,.75)}]\n\t\\DrawInsnBitstring{\\numchars}{#1}{\\hyperref[insnformat:stype]{S-type}}\n\t\\DrawInsnBoxSeg{\\numchars}{31}{25}{imm[11:5]}\n\t\\DrawInsnBoxSeg{\\numchars}{24}{20}{rs2}\n\t\\DrawInsnBoxSeg{\\numchars}{19}{15}{rs1}\n\t\\DrawInsnBoxSeg{\\numchars}{14}{12}{funct3}\n\t\\DrawInsnBoxSeg{\\numchars}{11}{7}{imm[4:0]}\n\t\\DrawInsnBoxSeg{\\numchars}{6}{0}{opcode}\n\n\t% add some hint bits in for imm fields\n\t\\draw {[rounded corners=\\SignBoxCornerRadius] (1.35, -.6) -- (1.35, .6) -- (.65, .6) -- (.65, -.6) -- cycle};\t% sign bit\n\t\\end{scope}\n\n\t\\DrawHexMarkersRel{\\numchars}\n}\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% #1 the binary encoding\n\\newcommand\\DrawInsnTypeSTikz[1]{\n\t\\BeginTikzPicture\n\t\\DrawInsnTypeS{#1}\n\t\\EndTikzPicture\n}\n\n\\newcommand\\DrawInsnTypeSPicture[2]{\n\t\\InsnStatement{#1}\\\\\n\t\\DrawInsnTypeSTikz{#2}\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% #1 the binary encoding\n\\newcommand\\DrawInsnTypeIShiftTikz[1]{\n\t\\BeginTikzPicture\n\t\\StrLen{#1}[\\numchars]\n\t\\DrawInsnBitstring{\\numchars}{#1}{\\hyperref[insnformat:rtype]{I-type}}\n\t\\DrawInsnBoxSeg{\\numchars}{31}{25}{funct7}\n\t\\DrawInsnBoxSeg{\\numchars}{24}{20}{shamt}\n\t\\DrawInsnBoxSeg{\\numchars}{19}{15}{rs1}\n\t\\DrawInsnBoxSeg{\\numchars}{14}{12}{funct3}\n\t\\DrawInsnBoxSeg{\\numchars}{11}{7}{rd}\n\t\\DrawInsnBoxSeg{\\numchars}{6}{0}{opcode}\n\n\t\\DrawHexMarkers{\\numchars}\n\t\\EndTikzPicture\n}\n\n\\newcommand\\DrawInsnTypeRShiftPicture[2]{\n\t\\InsnStatement{#1}\\\\\n\t\\DrawInsnTypeIShiftTikz{#2}\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% #1 the binary encoding\n\\newcommand\\DrawInsnTypeR[1]{\n\t\\StrLen{#1}[\\numchars]\n\t\\DrawInsnBitstring{\\numchars}{#1}{\\hyperref[insnformat:rtype]{R-type}}\n\t\\DrawInsnBoxSeg{\\numchars}{31}{25}{funct7}\n\t\\DrawInsnBoxSeg{\\numchars}{24}{20}{rs2}\n\t\\DrawInsnBoxSeg{\\numchars}{19}{15}{rs1}\n\t\\DrawInsnBoxSeg{\\numchars}{14}{12}{funct3}\n\t\\DrawInsnBoxSeg{\\numchars}{11}{7}{rd}\n\t\\DrawInsnBoxSeg{\\numchars}{6}{0}{opcode}\n\n\t\\DrawHexMarkers{\\numchars}\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% #1 the binary encoding\n\\newcommand\\DrawInsnTypeRTikz[1]{\n\t\\BeginTikzPicture\n\t\\DrawInsnTypeR{#1}\n\t\\EndTikzPicture\n}\n\n\\newcommand\\DrawInsnTypeRPicture[2]{\n\t\\InsnStatement{#1}\\\\\n\t\\DrawInsnTypeRTikz{#2}\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% #1 the binary encoding\n\\newcommand\\DrawInsnTypeFTikz[1]{\n \\BeginTikzPicture\n \\StrLen{#1}[\\numchars]\n \\DrawInsnBitstring{\\numchars}{#1}{FENCE}\n \\DrawInsnBoxSeg{\\numchars}{31}{28}{}\n \\DrawInsnBoxSeg{\\numchars}{27}{24}{pred}\n \\DrawInsnBoxSeg{\\numchars}{23}{20}{succ}\n \\DrawInsnBoxSeg{\\numchars}{19}{15}{}\n \\DrawInsnBoxSeg{\\numchars}{14}{12}{funct3}\n \\DrawInsnBoxSeg{\\numchars}{11}{7}{}\n \\DrawInsnBoxSeg{\\numchars}{6}{0}{opcode}\n\n \\DrawHexMarkers{\\numchars}\n \\EndTikzPicture\n}\n\n\\newcommand\\DrawInsnTypeFPicture[2]{\n \\InsnStatement{#1}\\\\\n \\DrawInsnTypeFTikz{#2}\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% #1 the binary encoding\n\\newcommand\\DrawInsnTypeETikz[1]{\n \\BeginTikzPicture\n\t\\StrLen{#1}[\\numchars]\n\t\\DrawInsnBitstring{\\numchars}{#1}{\\hyperref[insnformat:itype]{I-type}}\n\t\\DrawInsnBoxSeg{\\numchars}{31}{20}{}\n\t\\DrawInsnBoxSeg{\\numchars}{19}{15}{}\n\t\\DrawInsnBoxSeg{\\numchars}{14}{12}{funct3}\n\t\\DrawInsnBoxSeg{\\numchars}{11}{7}{}\n\t\\DrawInsnBoxSeg{\\numchars}{6}{0}{opcode}\n\n \\DrawHexMarkers{\\numchars}\n \\EndTikzPicture\n}\n\n\\newcommand\\DrawInsnTypeEPicture[2]{\n \\InsnStatement{#1}\\\\\n \\DrawInsnTypeETikz{#2}\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% #1 the binary encoding\n\\newcommand\\DrawInsnTypeCSTikz[1]{\n \\BeginTikzPicture\n\t\\StrLen{#1}[\\numchars]\n\t\\DrawInsnBitstring{\\numchars}{#1}{\\hyperref[insnformat:itype]{I-type}}\n\t\\DrawInsnBoxSeg{\\numchars}{31}{20}{csr}\n\t\\DrawInsnBoxSeg{\\numchars}{19}{15}{rs1}\n\t\\DrawInsnBoxSeg{\\numchars}{14}{12}{funct3}\n\t\\DrawInsnBoxSeg{\\numchars}{11}{7}{rd}\n\t\\DrawInsnBoxSeg{\\numchars}{6}{0}{opcode}\n\n \\DrawHexMarkers{\\numchars}\n \\EndTikzPicture\n}\n\n\\newcommand\\DrawInsnTypeCSPicture[2]{\n \\InsnStatement{#1}\\\\\n \\DrawInsnTypeCSTikz{#2}\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% #1 the binary encoding\n\\newcommand\\DrawInsnTypeCSITikz[1]{\n \\BeginTikzPicture\n\t\\StrLen{#1}[\\numchars]\n\t\\DrawInsnBitstring{\\numchars}{#1}{\\hyperref[insnformat:itype]{I-type}}\n\t\\DrawInsnBoxSeg{\\numchars}{31}{20}{csr}\n\t\\DrawInsnBoxSeg{\\numchars}{19}{15}{zimm}\n\t\\DrawInsnBoxSeg{\\numchars}{14}{12}{funct3}\n\t\\DrawInsnBoxSeg{\\numchars}{11}{7}{rd}\n\t\\DrawInsnBoxSeg{\\numchars}{6}{0}{opcode}\n\n \\DrawHexMarkers{\\numchars}\n \\EndTikzPicture\n}\n\n\\newcommand\\DrawInsnTypeCSIPicture[2]{\n \\InsnStatement{#1}\\\\\n \\DrawInsnTypeCSITikz{#2}\n}\n\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\n\n\\newcommand\\xTInsnStatement[4]{%\n\t\\parbox{3.5cm}{{\\sffamily\\large\\bfseries #2}\\\\\n\t\\tt#3}\\hspace{5mm}\\parbox{5cm}{\\bfseries#1}\\parbox{12cm}{#4}%\n}\n\n\\newcommand\\TInsnStatement[4]{%\n\t\\begin{tabular}{lll}\n\t\\parbox[t]{3.5cm}{{\\sffamily\\large\\bfseries #2}\\\\\n\t\\tt#3} & \\parbox[t]{5cm}{\\bfseries #1} & \\parbox[t]{12cm}{#4}\\\\\n\t\\end{tabular}\n}\n\n\\newcommand\\TDrawInsnTypeUPicture[5]{%\n\t\\TInsnStatement{#1}{#2}{#3}{#4}\\\\\n \\DrawInsnTypeUTikz{#5}%\n}\n\n\\newcommand\\TDrawInsnTypeJPicture[5]{%\n\t\\TInsnStatement{#1}{#2}{#3}{#4}\\\\\n \\DrawInsnTypeJTikz{#5}%\n}\n\n\\newcommand\\TDrawInsnTypeBPicture[5]{%\n\t\\TInsnStatement{#1}{#2}{#3}{#4}\\\\\n \\DrawInsnTypeBTikz{#5}%\n}\n\n\\newcommand\\TDrawInsnTypeIPicture[5]{%\n\t\\TInsnStatement{#1}{#2}{#3}{#4}\\\\\n \\DrawInsnTypeITikz{#5}%\n}\n\\newcommand\\TDrawInsnTypeSPicture[5]{%\n\t\\TInsnStatement{#1}{#2}{#3}{#4}\\\\\n \\DrawInsnTypeSTikz{#5}%\n}\n\\newcommand\\TDrawInsnTypeRPicture[5]{%\n\t\\TInsnStatement{#1}{#2}{#3}{#4}\\\\\n \\DrawInsnTypeRTikz{#5}%\n}\n\n\\newcommand\\TDrawInsnTypeRShiftPicture[5]{\n\t\\TInsnStatement{#1}{#2}{#3}{#4}\\\\\n\t\\DrawInsnTypeIShiftTikz{#5}\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% Draw hex markers with a baseline at zero\n% #1 The number of bits in the box\n\\newcommand\\TheHexMark[1]{\n\t\\draw [line width=.5mm] (#1+.5,0) -- (#1+.5, .4);\n}\n\n\\newcommand\\DrawHexMarkersRel[1]{\n\t\\pgfmathsetmacro\\num{int(#1-1)}\n\t\\foreach \\x in {4,8,...,\\num}\n\t\t\\draw [line width=.5mm] (\\x+.5,0) -- (\\x+.5, .4);\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% Draw an instruction box with a baseline at zero\n% #1 MSB position\n% #2 LSB position\n% #3 the segment label\n\\newcommand\\DrawInsnBoxRelTop[3]{\n\t\\pgfmathsetmacro\\leftpos{int(32-#1)}\n\t\\pgfmathsetmacro\\rightpos{int(32-#2)}\n\t\\draw (\\leftpos-.5,1.5) -- (\\rightpos+.5,1.5);\t% box top\n\t\\draw (\\leftpos-.5,0) -- (\\leftpos-.5, 1.5);\t% left end\n\t\\draw (\\rightpos+.5,0) -- (\\rightpos+.5, 1.5);\t% right end\n\t\\pgfmathsetmacro\\posn{32-#1+(#1-#2)/2}\n\t\\node at (\\posn,.75) {\\small#3};\t\t\t\t% the field label\n}\n\n% Draw only the bottom line of an instruction box with a baseline at zero\n% #1 MSB position\n% #2 LSB position\n\\newcommand\\DrawInsnBoxRelBottom[2]{\n\t\\pgfmathsetmacro\\leftpos{int(32-#1)}\n\t\\pgfmathsetmacro\\rightpos{int(32-#2)}\n\t\\draw (\\leftpos-.5,0) -- (\\rightpos+.5,0);\t\t% box bottom\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% Draw an instruction box with a baseline at zero\n% #1 MSB position\n% #2 LSB position\n% #3 the segment label\n\\newcommand\\DrawInsnBoxRel[3]{\n\t\\DrawInsnBoxRelTop{#1}{#2}{#3}\n\t\\DrawInsnBoxRelBottom{#1}{#2}\n}\n\n%\\newcommand\\DrawInsnBoxRel[3]{\n%\t\\pgfmathsetmacro\\leftpos{int(32-#1)}\n%\t\\pgfmathsetmacro\\rightpos{int(32-#2)}\n%\n%\t\\draw (\\leftpos-.5,0) -- (\\rightpos+.5,0);\t% box bottom\n%\t\\draw (\\leftpos-.5,1.5) -- (\\rightpos+.5,1.5);\t% box top\n%\t\\draw (\\leftpos-.5,0) -- (\\leftpos-.5, 1.5);\t\t% left end\n%\t\\draw (\\rightpos+.5,0) -- (\\rightpos+.5, 1.5);\t% right end\n%\n% \\pgfmathsetmacro\\posn{32-#1+(#1-#2)/2}\n% \\node at (\\posn,.75) {\\small#3}; % the field label\n%}\n\n% #1 MSB position\n% #2 LSB position\n\\newcommand\\DrawInsnBoxCastle[2]{\n\t\\pgfmathsetmacro\\leftpos{int(32-#1)}\n\t\\pgfmathsetmacro\\rightpos{int(32-#2)}\n\t\\draw (\\leftpos-.5,0) -- (\\leftpos-.5, .75);\t\t% left end\n\t\\draw (\\rightpos+.5,0) -- (\\rightpos+.5, .75);\t% right end\n\t\\node at (\\leftpos,.5) {\\tiny#1};\n\t\\ifthenelse{\\equal{#1}{#2}}\n\t{}\n\t{ \\draw(\\rightpos,.5) node{\\tiny#2}; }\n}\n\\newcommand\\DrawInsnBoxCastleRtype{\n\t\\DrawInsnBoxCastle{31}{25}\n\t\\DrawInsnBoxCastle{24}{20}\n\t\\DrawInsnBoxCastle{19}{15}\n\t\\DrawInsnBoxCastle{14}{12}\n\t\\DrawInsnBoxCastle{11}{7}\n\t\\DrawInsnBoxCastle{6}{0}\n}\n\n\\newcommand\\DrawInsnBoxCastleJtype{\n\t\\DrawInsnBoxCastle{31}{31}\n\t\\DrawInsnBoxCastle{30}{21}\n\t\\DrawInsnBoxCastle{20}{20}\n\t\\DrawInsnBoxCastle{19}{12}\n\t\\DrawInsnBoxCastle{11}{7}\n\t\\DrawInsnBoxCastle{6}{0}\n}\n\n\n\n%% Draw a B-Type instruction box\n%% #1 label\n%% #2 ...\n%\\newcommand\\DrawInsnBoxBType[6]{\n%\t\\DrawInsnBoxRel{31}{25}{#1}\n%\t\\DrawInsnBoxRel{24}{20}{#2}\n%\t\\DrawInsnBoxRel{19}{15}{#3}\n%\t\\DrawInsnBoxRel{14}{12}{#4}\n%\t\\DrawInsnBoxRel{11}{7}{#5}\n%\t\\DrawInsnBoxRel{6}{0}{#6}\n%}\n%\n%\n%\\newcommand\\DrawInsnBoxLabelsBtype{\n%\t\\DrawInsnBoxBType{imm[12\\textbar10:5]}{rs2}{rs1}{funct3}{imm[4:1\\textbar11]}{opcode}\n%%\t\\DrawInsnBoxRel{31}{25}{imm[12\\textbar10:5]}\n%%\t\\DrawInsnBoxRel{24}{20}{rs2}\n%%\t\\DrawInsnBoxRel{19}{15}{rs1}\n%%\t\\DrawInsnBoxRel{14}{12}{funct3}\n%%\t\\DrawInsnBoxRel{11}{7}{imm[4:1\\textbar11]}\n%%\t\\DrawInsnBoxRel{6}{0}{opcode}\n%\t\\draw(33,.75) node[right]{\\hyperref[insnformat:btype]{B-type}};\n%}\n%\\newcommand\\DrawInsnBoxLabelsRtype{\n%\t\\DrawInsnBoxRel{31}{25}{funct7}\n%\t\\DrawInsnBoxRel{24}{20}{rs2}\n%\t\\DrawInsnBoxRel{19}{15}{rs1}\n%\t\\DrawInsnBoxRel{14}{12}{funct3}\n%\t\\DrawInsnBoxRel{11}{7}{rd}\n%\t\\DrawInsnBoxRel{6}{0}{opcode}\n%\t\\draw(33,.75) node[right]{\\hyperref[insnformat:rtype]{R-type}};\n%}\n%\\newcommand\\DrawInsnBoxLabelsItype{\n%\t\\DrawInsnBoxRel{31}{20}{imm[11:0]}\n%\t\\DrawInsnBoxRel{19}{15}{rs1}\n%\t\\DrawInsnBoxRel{14}{12}{funct3}\n%\t\\DrawInsnBoxRel{11}{7}{rd}\n%\t\\DrawInsnBoxRel{6}{0}{opcode}\n%\t\\draw(33,.75) node[right]{\\hyperref[insnformat:itype]{I-type}};\n%}\n%\\newcommand\\DrawInsnBoxLabelsStype{\n% \\DrawInsnBoxRel{31}{25}{imm[11:5]}\n% \\DrawInsnBoxRel{24}{20}{rs2}\n% \\DrawInsnBoxRel{19}{15}{rs1}\n% \\DrawInsnBoxRel{14}{12}{funct3}\n% \\DrawInsnBoxRel{11}{7}{imm[4:0]}\n% \\DrawInsnBoxRel{6}{0}{opcode}\n%\t\\draw(33,.75) node[right]{\\hyperref[insnformat:stype]{S-type}};\n%}\n%\\newcommand\\DrawInsnBoxLabelsUtype{\n%\t\\DrawInsnBoxRel{31}{12}{imm[31:12]}\n%\t\\DrawInsnBoxRel{11}{7}{rd}\n%\t\\DrawInsnBoxRel{6}{0}{opcode}\n%\t\\draw(33,.75) node[right]{\\hyperref[insnformat:utype]{U-type}};\n%}\n%\\newcommand\\DrawInsnBoxLabelsJtype{\n%\t\\DrawInsnBoxRel{31}{12}{imm[20\\textbar10:1\\textbar11\\textbar19:12]}\n%\t\\DrawInsnBoxRel{11}{7}{rd}\n%\t\\DrawInsnBoxRel{6}{0}{opcode}\n%\t\\draw(33,.75) node[right]{\\hyperref[insnformat:jtype]{J-type}};\n%}\n%\n%\\newcommand\\XXXDrawAllInsnTypes{\n%\t\\BeginTikzPicture\n%\t\\DrawInsnBoxLabelsRtype\n%\t\\begin{scope}[shift={(0,-1.5)}]\\DrawInsnBoxLabelsItype\\end{scope}\n%\t\\begin{scope}[shift={(0,-3)}]\\DrawInsnBoxLabelsStype\\end{scope}\n%\t\\begin{scope}[shift={(0,-4.5)}]\\DrawInsnBoxLabelsBtype\\end{scope}\n%\t\\begin{scope}[shift={(0,-6)}]\\DrawInsnBoxLabelsUtype\\end{scope}\n%\t\\begin{scope}[shift={(0,-7.5)}]\\DrawInsnBoxLabelsJtype\\DrawHexMarkersRel{32}\\end{scope}\n%\n%\t\\begin{scope}[shift={(0,1.5)}]\n%\t\t\\DrawInsnBoxCastleRtype\n%\t\\end{scope}\n%\n%\t\\EndTikzPicture\n%}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% Print the characters within a string evenly spaced at integral node positions\n% #1 The string of characters to plot\n\\newcommand\\DrawBitstringX[1]{\n\t\\StrLen{#1}[\\numchars]\n\t\\pgfmathsetmacro\\num{int(\\numchars-1)}\n\t\\foreach \\x in {1,2,...,\\numchars}\n% \t\\draw(\\x,0) node{\\substring{\\strut #1}{\\x}{\\x}};\n\t\t\\draw(\\x+.25,.5) node[text width = 10, text height = 1]{\\substring{#1}{\\x}{\\x}};\n}\n\n\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% REFERENCE CARD DRAWINGS\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\n\\newcommand\\InsnSrcArgPosX{4}\t% relative to the position of the mnemonic\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% draw the instruction mnemonic and its args\n% #1 mnemonic\n% #2 args\n\\newcommand\\DrawInsnSrc[2]{\n\t\\draw node[right]{\\tt #1};\n\t\\draw(\\InsnSrcArgPosX,0) node[right]{\\tt #2};\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% Draw a I-type instruction box with the given labels\n\\newcommand\\DrawInsnOpIBox[5]{\n\t\\DrawInsnBoxRel{31}{20}{#1}\n\t\\DrawInsnBoxRel{19}{15}{#2}\n\t\\DrawInsnBoxRel{14}{12}{}\n\t\\DrawInsnBoxRel{11}{7}{#4}\n\t\\DrawInsnBoxRel{6}{0}{}\n\n\t\\begin{scope}[shift={(31-6,0)}]\\DrawBitstringX{#3}\\end{scope}\n\t\\begin{scope}[shift={(31-14,0)}]\\DrawBitstringX{#5}\\end{scope}\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% Draw a I-type instruction box with a 32-bit binary value\n\\newcommand\\DrawInsnOpIBinBox[1]{\n\t\\DrawInsnBoxRel{31}{20}{}\n\t\\DrawInsnBoxRel{19}{15}{}\n\t\\DrawInsnBoxRel{14}{12}{}\n\t\\DrawInsnBoxRel{11}{7}{}\n\t\\DrawInsnBoxRel{6}{0}{}\n\n\t\\begin{scope}[shift={(31-31,0)}]\\DrawBitstringX{#1}\\end{scope}\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% Draw a I-type w/funct7 instruction box with the given labels\n\\newcommand\\DrawInsnOpIFunctBox[6]{\n \\DrawInsnBoxRel{31}{25}{}\n \\DrawInsnBoxRel{24}{20}{#2}\n \\DrawInsnBoxRel{19}{15}{#3}\n \\DrawInsnBoxRel{14}{12}{}\n \\DrawInsnBoxRel{11}{7}{#5}\n \\DrawInsnBoxRel{6}{0}{}\n\n\t\\begin{scope}[shift={(31-6,0)}]\\DrawBitstringX{#1}\\end{scope}\n\t\\begin{scope}[shift={(31-14,0)}]\\DrawBitstringX{#4}\\end{scope}\n\t\\begin{scope}[shift={(31-31,0)}]\\DrawBitstringX{#6}\\end{scope}\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% Draw a I-type instruction box with the given labels\n\\newcommand\\DrawInsnOpBBox[6]{\n\t\\DrawInsnBoxRel{31}{25}{#1}\n\t\\DrawInsnBoxRel{24}{20}{#2}\n\t\\DrawInsnBoxRel{19}{15}{#3}\n\t\\DrawInsnBoxRel{14}{12}{}\n\t\\DrawInsnBoxRel{11}{7}{#5}\n\t\\DrawInsnBoxRel{6}{0}{}\n\n\t\\begin{scope}[shift={(31-6,0)}]\\DrawBitstringX{#4}\\end{scope}\n\t\\begin{scope}[shift={(31-14,0)}]\\DrawBitstringX{#6}\\end{scope}\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% Draw a S-type instruction box with the given labels\n\\newcommand\\DrawInsnOpSBox[6]{\n \\DrawInsnBoxRel{31}{25}{#1}\n \\DrawInsnBoxRel{24}{20}{#2}\n \\DrawInsnBoxRel{19}{15}{#3}\n \\DrawInsnBoxRel{14}{12}{}\n \\DrawInsnBoxRel{11}{7}{#5}\n \\DrawInsnBoxRel{6}{0}{}\n\n\t\\begin{scope}[shift={(31-6,0)}]\\DrawBitstringX{#6}\\end{scope}\n\t\\begin{scope}[shift={(31-14,0)}]\\DrawBitstringX{#4}\\end{scope}\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% Draw a R-type instruction box with the given labels\n\\newcommand\\DrawInsnOpRBox[6]{\n\t\\DrawInsnBoxRel{31}{25}{}\n\t\\DrawInsnBoxRel{24}{20}{#2}\n\t\\DrawInsnBoxRel{19}{15}{#3}\n\t\\DrawInsnBoxRel{14}{12}{}\n\t\\DrawInsnBoxRel{11}{7}{#5}\n\t\\DrawInsnBoxRel{6}{0}{}\n\n\t\\begin{scope}[shift={(31-6,0)}]\\DrawBitstringX{#6}\\end{scope}\n\t\\begin{scope}[shift={(31-14,0)}]\\DrawBitstringX{#4}\\end{scope}\n\t\\begin{scope}[shift={(31-31,0)}]\\DrawBitstringX{#1}\\end{scope}\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% Draw a U-type instruction box with the given labels\n\\newcommand\\DrawInsnOpUBox[3]{\n\t\\DrawInsnBoxRel{31}{12}{#1}\n\t\\DrawInsnBoxRel{11}{7}{#2}\n\t\\DrawInsnBoxRel{6}{0}{}\n\n\t\\begin{scope}[shift={(31-6,0)}]\\DrawBitstringX{#3}\\end{scope}\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% Draw a J-type instruction box with the given labels\n\\newcommand\\DrawInsnOpJBox[3]{\n\t\\DrawInsnBoxRel{31}{12}{#1}\n\t\\DrawInsnBoxRel{11}{7}{#2}\n\t\\DrawInsnBoxRel{6}{0}{}\n\n\t\\begin{scope}[shift={(31-6,0)}]\\DrawBitstringX{#3}\\end{scope}\n}\n\n\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\n\\newcommand\\InsnBoxTypePosX{32.5}\n\\newcommand\\InsnBoxMnemonicPosX{36.5}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% #1 opcode\n% #2 func3\n% #3 mnemonic\n% #4 args\n\\newcommand\\DrawInsnOpBType[4]{\n\t\\DrawInsnOpBBox{imm[12\\textbar10:5]}{rs2}{rs1}{#1}{imm[4:1\\textbar11]}{#2}\n\t\\draw(\\InsnBoxTypePosX,.75) node[right]{\\hyperref[insnformat:btype]{B-type}};\n\t\\begin{scope}[shift={(\\InsnBoxMnemonicPosX,.75)}]\\DrawInsnSrc{#3}{#4}\\end{scope}\n}\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% #1 opcode\n% #2 func3\n% #3 mnemonic\n% #4 args\n\\newcommand\\DrawInsnOpIType[4]{\n\t\\DrawInsnOpIBox{imm[11:0]}{rs1}{#1}{rd}{#2}\n\t\\draw(\\InsnBoxTypePosX,.75) node[right]{\\hyperref[insnformat:itype]{I-type}};\n\t\\begin{scope}[shift={(\\InsnBoxMnemonicPosX,.75)}]\\DrawInsnSrc{#3}{#4}\\end{scope}\n\n}\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% #1 opcode\n% #2 func3\n% #3 mnemonic\n% #4 args\n% #5 rs1/zimm\n\\newcommand\\DrawInsnOpITypeSystem[5]{\n\t\\DrawInsnOpIBox{csr[11:0]}{#5}{#1}{rd}{#2}\n\t\\draw(\\InsnBoxTypePosX,.75) node[right]{\\hyperref[insnformat:itype]{I-type}};\n\t\\begin{scope}[shift={(\\InsnBoxMnemonicPosX,.75)}]\\DrawInsnSrc{#3}{#4}\\end{scope}\n}\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% #1 opcode\n% #2 func3\n% #3 func7\n% #4 mnemonic\n% #5 args\n\\newcommand\\DrawInsnOpITypeShift[5]{\n\t\\DrawInsnOpIFunctBox{#1}{shamt}{rs1}{#2}{rd}{#3}\n\t\\draw(\\InsnBoxTypePosX,.75) node[right]{\\hyperref[insnformat:itype]{I-type}};\n\t\\begin{scope}[shift={(\\InsnBoxMnemonicPosX,.75)}]\\DrawInsnSrc{#4}{#5}\\end{scope}\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% #1 opcode\n% #2 func3\n% #3 mnemonic\n% #4 args\n\\newcommand\\DrawInsnOpSType[4]{\n\t\\DrawInsnOpSBox{imm[11:5]}{rs2}{rs1}{#2}{imm[4:0]}{#1}\n\t\\draw(\\InsnBoxTypePosX,.75) node[right]{\\hyperref[insnformat:stype]{S-type}};\n\t\\begin{scope}[shift={(\\InsnBoxMnemonicPosX,.75)}]\\DrawInsnSrc{#3}{#4}\\end{scope}\n}\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% #1 opcode\n% #2 func3\n% #3 func7\n% #4 mnemonic\n% #5 args\n\\newcommand\\DrawInsnOpRType[5]{\n\t\\DrawInsnOpRBox{#3}{rs2}{rs1}{#2}{rd}{#1}\n\t\\draw(\\InsnBoxTypePosX,.75) node[right]{\\hyperref[insnformat:rtype]{R-type}};\n\t\\begin{scope}[shift={(\\InsnBoxMnemonicPosX,.75)}]\\DrawInsnSrc{#4}{#5}\\end{scope}\n}\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% #1 opcode\n% #2 func3\n% #3 mnemonic\n% #4 args\n%\\newcommand\\DrawInsnOpFenceType[4]{\n%\t\\DrawInsnBoxRel{31}{28}{}\n%\t\\DrawInsnBoxRel{27}{24}{pred}\n%\t\\DrawInsnBoxRel{23}{20}{succ}\n%\t\\DrawInsnBoxRel{19}{15}{}\n%\t\\DrawInsnBoxRel{14}{12}{}\n%\t\\DrawInsnBoxRel{11}{7}{}\n%\t\\DrawInsnBoxRel{6}{0}{}\n%\t\\begin{scope}[shift={(\\InsnBoxMnemonicPosX,.75)}]\\DrawInsnSrc{#3}{#4}\\end{scope}\n%\n%\t\\begin{scope}[shift={(31-6,0)}]\\DrawBitstringX{#1}\\end{scope}\n%\t\\begin{scope}[shift={(31-14,0)}]\\DrawBitstringX{#2}\\end{scope}\n%\t\\begin{scope}[shift={(31-31,0)}]\\DrawBitstringX{0000}\\end{scope}\n%\n%\t\\begin{scope}[shift={(31-19,0)}]\\DrawBitstringX{00000}\\end{scope}\n%\t\\begin{scope}[shift={(31-11,0)}]\\DrawBitstringX{00000}\\end{scope}\n%}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% #1 opcode\n% #2 func12\n% #3 mnemonic\n% #4 args\n\\newcommand\\DrawInsnOpSysType[3]{\n\t\\DrawInsnOpIBinBox{#20000000000000#1}\n\t\\draw(\\InsnBoxTypePosX,.75) node[right]{\\hyperref[insnformat:itype]{I-type}};\n\t\\draw(\\InsnBoxMnemonicPosX,.75) node[right]{\\tt #3};\n}\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% #1 opcode\n% #2 mnemonic\n% #4 args\n\\newcommand\\DrawInsnOpUType[3]{\n\t\\DrawInsnOpUBox{imm[31:12]}{rd}{#1}\n\t\\draw(\\InsnBoxTypePosX,.75) node[right]{\\hyperref[insnformat:utype]{U-type}};\n\t\\begin{scope}[shift={(\\InsnBoxMnemonicPosX,.75)}]\\DrawInsnSrc{#2}{#3}\\end{scope}\n}\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% #1 opcode\n% #2 mnemonic\n% #4 args\n\\newcommand\\DrawInsnOpJType[3]{\n\t\\DrawInsnOpJBox{imm[20\\textbar10:1\\textbar11\\textbar19:12]}{rd}{#1}\n\t\\draw(\\InsnBoxTypePosX,.75) node[right]{\\hyperref[insnformat:jtype]{J-type}};\n\t\\begin{scope}[shift={(\\InsnBoxMnemonicPosX,.75)}]\\DrawInsnSrc{#2}{#3}\\end{scope}\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\n\\newcommand\\DrawAllInsnOpsU{\n\t\\begin{scope}[shift={(0,0)}]\\DrawInsnOpUType{0110111}{\\hyperref[insn:lui]{lui}}{rd,\\hyperref[imm.u:decode]{imm}}\\end{scope}\n\t\\begin{scope}[shift={(0,-1.5)}]\\DrawInsnOpUType{0010111}{\\hyperref[insn:auipc]{auipc}}{rd,\\hyperref[imm.u:decode]{imm}}\\end{scope}\n%\t\\begin{scope}[shift={(0,-1.5)}]\\DrawHexMarkersRel{32}\\end{scope}\n}\n\\newcommand\\DrawAllInsnOpsJAL{\n\t\\begin{scope}[shift={(0,0)}]\\DrawInsnOpJType{1101111}{\\hyperref[insn:jal]{jal}}{rd,\\hyperref[pcrel.21]{pcrel\\_21}}\\end{scope}\n\t\\begin{scope}[shift={(0,-1.5)}]\\DrawInsnOpIType{1100111}{000}{\\hyperref[insn:jalr]{jalr}}{rd,\\hyperref[imm.i:decode]{imm}(rs1)}\\end{scope}\n\t\\begin{scope}[shift={(0,-1.5)}]\\DrawHexMarkersRel{32}\\end{scope}\n}\n\\newcommand\\DrawAllInsnOpsBranch{\n\t\\begin{scope}[shift={(0,0)}]\\DrawInsnOpBType{1100011}{000}{\\hyperref[insn:beq]{beq}}{rs1,rs2,\\hyperref[pcrel.13]{pcrel\\_13}}\\end{scope}\n\t\\begin{scope}[shift={(0,-1.5)}]\\DrawInsnOpBType{1100011}{001}{\\hyperref[insn:bne]{bne}}{rs1,rs2,\\hyperref[pcrel.13]{pcrel\\_13}}\\end{scope}\n\t\\begin{scope}[shift={(0,-3)}]\\DrawInsnOpBType{1100011}{100}{\\hyperref[insn:blt]{blt}}{rs1,rs2,\\hyperref[pcrel.13]{pcrel\\_13}}\\end{scope}\n\t\\begin{scope}[shift={(0,-4.5)}]\\DrawInsnOpBType{1100011}{101}{\\hyperref[insn:bge]{bge}}{rs1,rs2,\\hyperref[pcrel.13]{pcrel\\_13}}\\end{scope}\n\t\\begin{scope}[shift={(0,-6)}]\\DrawInsnOpBType{1100011}{110}{\\hyperref[insn:bltu]{bltu}}{rs1,rs2,\\hyperref[pcrel.13]{pcrel\\_13}}\\end{scope}\n\t\\begin{scope}[shift={(0,-7.5)}]\\DrawInsnOpBType{1100011}{111}{\\hyperref[insn:bgeu]{bgeu}}{rs1,rs2,\\hyperref[pcrel.13]{pcrel\\_13}}\\end{scope}\n\n\t\\begin{scope}[shift={(0,-7.5)}]\\DrawHexMarkersRel{32}\\end{scope}\n}\n\\newcommand\\DrawAllInsnOpsLoad{\n\t\\begin{scope}[shift={(0,0)}]\\DrawInsnOpIType{0000011}{000}{\\hyperref[insn:lb]{lb}}{rd,\\hyperref[imm.i:decode]{imm}(rs1)}\\end{scope}\n\t\\begin{scope}[shift={(0,-1.5)}]\\DrawInsnOpIType{0000011}{001}{\\hyperref[insn:lh]{lh}}{rd,\\hyperref[imm.i:decode]{imm}(rs1)}\\end{scope}\n\t\\begin{scope}[shift={(0,-3.0)}]\\DrawInsnOpIType{0000011}{010}{\\hyperref[insn:lw]{lw}}{rd,\\hyperref[imm.i:decode]{imm}(rs1)}\\end{scope}\n\t\\begin{scope}[shift={(0,-4.5)}]\\DrawInsnOpIType{0000011}{100}{\\hyperref[insn:lbu]{lbu}}{rd,\\hyperref[imm.i:decode]{imm}(rs1)}\\end{scope}\n\t\\begin{scope}[shift={(0,-6.0)}]\\DrawInsnOpIType{0000011}{101}{\\hyperref[insn:lhu]{lhu}}{rd,\\hyperref[imm.i:decode]{imm}(rs1)}\\end{scope}\n\n\t\\begin{scope}[shift={(0,-6.0)}]\\DrawHexMarkersRel{32}\\end{scope}\n}\n\\newcommand\\DrawAllInsnOpsStore{\n\t\\begin{scope}[shift={(0,0)}]\\DrawInsnOpSType{0100011}{000}{\\hyperref[insn:sb]{sb}}{rs2,\\hyperref[imm.s:decode]{imm}(rs1)}\\end{scope}\n\t\\begin{scope}[shift={(0,-1.5)}]\\DrawInsnOpSType{0100011}{001}{\\hyperref[insn:sh]{sh}}{rs2,\\hyperref[imm.s:decode]{imm}(rs1)}\\end{scope}\n\t\\begin{scope}[shift={(0,-3.0)}]\\DrawInsnOpSType{0100011}{010}{\\hyperref[insn:sw]{sw}}{rs2,\\hyperref[imm.s:decode]{imm}(rs1)}\\end{scope}\n\n\t\\begin{scope}[shift={(0,-3.0)}]\\DrawHexMarkersRel{32}\\end{scope}\n}\n\\newcommand\\DrawAllInsnOpsALUImm{\n\t\\begin{scope}[shift={(0,0)}]\\DrawInsnOpIType{0010011}{000}{\\hyperref[insn:addi]{addi}}{rd,rs1,\\hyperref[imm.i:decode]{imm}}\\end{scope}\n\t\\begin{scope}[shift={(0,-1.5)}]\\DrawInsnOpIType{0010011}{010}{\\hyperref[insn:slti]{slti}}{rd,rs1,\\hyperref[imm.i:decode]{imm}}\\end{scope}\n\t\\begin{scope}[shift={(0,-3.0)}]\\DrawInsnOpIType{0010011}{011}{\\hyperref[insn:sltiu]{sltiu}}{rd,rs1,\\hyperref[imm.i:decode]{imm}}\\end{scope}\n\t\\begin{scope}[shift={(0,-4.5)}]\\DrawInsnOpIType{0010011}{100}{\\hyperref[insn:xori]{xori}}{rd,rs1,\\hyperref[imm.i:decode]{imm}}\\end{scope}\n\t\\begin{scope}[shift={(0,-6.0)}]\\DrawInsnOpIType{0010011}{110}{\\hyperref[insn:ori]{ori}}{rd,rs1,\\hyperref[imm.i:decode]{imm}}\\end{scope}\n\t\\begin{scope}[shift={(0,-7.5)}]\\DrawInsnOpIType{0010011}{111}{\\hyperref[insn:andi]{andi}}{rd,rs1,\\hyperref[imm.i:decode]{imm}}\\end{scope}\n\n\t\\begin{scope}[shift={(0,-7.5)}]\\DrawHexMarkersRel{32}\\end{scope}\n}\n\\newcommand\\DrawAllInsnOpsShiftImm{\n\t\\begin{scope}[shift={(0,0)}]\\DrawInsnOpITypeShift{0010011}{001}{0000000}{\\hyperref[insn:slli]{slli}}{rd,rs1,\\hyperref[shamt.i:decode]{shamt}}\\end{scope}\n\t\\begin{scope}[shift={(0,-1.5)}]\\DrawInsnOpITypeShift{0010011}{101}{0000000}{\\hyperref[insn:srli]{srli}}{rd,rs1,\\hyperref[shamt.i:decode]{shamt}}\\end{scope}\n\t\\begin{scope}[shift={(0,-3.0)}]\\DrawInsnOpITypeShift{0010011}{101}{0100000}{\\hyperref[insn:srai]{srai}}{rd,rs1,\\hyperref[shamt.i:decode]{shamt}}\\end{scope}\n\n\t\\begin{scope}[shift={(0,-3.0)}]\\DrawHexMarkersRel{32}\\end{scope}\n}\n\\newcommand\\DrawAllInsnOpsALUR{\n\t\\begin{scope}[shift={(0,0)}]\\DrawInsnOpRType{0110011}{000}{0000000}{\\hyperref[insn:add]{add}}{rd,rs1,rs2}\\end{scope}\n\t\\begin{scope}[shift={(0,-1.5)}]\\DrawInsnOpRType{0110011}{000}{0100000}{\\hyperref[insn:sub]{sub}}{rd,rs1,rs2}\\end{scope}\n\t\\begin{scope}[shift={(0,-3.0)}]\\DrawInsnOpRType{0110011}{001}{0000000}{\\hyperref[insn:sll]{sll}}{rd,rs1,rs2}\\end{scope}\n\t\\begin{scope}[shift={(0,-4.5)}]\\DrawInsnOpRType{0110011}{010}{0000000}{\\hyperref[insn:slt]{slt}}{rd,rs1,rs2}\\end{scope}\n\t\\begin{scope}[shift={(0,-6.0)}]\\DrawInsnOpRType{0110011}{011}{0000000}{\\hyperref[insn:sltu]{sltu}}{rd,rs1,rs2}\\end{scope}\n\t\\begin{scope}[shift={(0,-7.5)}]\\DrawInsnOpRType{0110011}{100}{0000000}{\\hyperref[insn:xor]{xor}}{rd,rs1,rs2}\\end{scope}\n\t\\begin{scope}[shift={(0,-9.0)}]\\DrawInsnOpRType{0110011}{101}{0000000}{\\hyperref[insn:srl]{srl}}{rd,rs1,rs2}\\end{scope}\n\t\\begin{scope}[shift={(0,-10.5)}]\\DrawInsnOpRType{0110011}{101}{0100000}{\\hyperref[insn:sra]{sra}}{rd,rs1,rs2}\\end{scope}\n\t\\begin{scope}[shift={(0,-12.0)}]\\DrawInsnOpRType{0110011}{110}{0000000}{\\hyperref[insn:or]{or}}{rd,rs1,rs2}\\end{scope}\n\t\\begin{scope}[shift={(0,-13.5)}]\\DrawInsnOpRType{0110011}{111}{0000000}{\\hyperref[insn:and]{and}}{rd,rs1,rs2}\\end{scope}\n\n\t\\begin{scope}[shift={(0,-13.5)}]\\DrawHexMarkersRel{32}\\end{scope}\n}\n\\newcommand\\DrawAllInsnOpsFence{\n\t\\begin{scope}[shift={(0,0)}]\\DrawInsnOpFenceType{0001111}{000}{\\hyperref[insn:fence]{fence}}{pred,succ}\\end{scope}\n\t%\\begin{scope}[shift={(0,0)}]\\DrawHexMarkersRel{32}\\end{scope}\n}\n\\newcommand\\DrawAllInsnOpsSim{\n\t\\begin{scope}[shift={(0,0)}]\\DrawInsnOpSysType{1110011}{000000000000}{\\hyperref[insn:ecall]{ecall}}\\end{scope}\n\t\\begin{scope}[shift={(0,-1.5)}]\\DrawInsnOpSysType{1110011}{000000000001}{\\hyperref[insn:ebreak]{ebreak}}\\end{scope}\n\t\\begin{scope}[shift={(0,-1.5)}]\\DrawHexMarkersRel{32}\\end{scope}\n}\n\n\\newcommand\\DrawAllInsnOpsSystem{\n\t\\begin{scope}[shift={(0,0)}]\\DrawInsnOpITypeSystem{1110011}{001}{\\hyperref[insn:csrrw]{csrrw}}{rd,\\hyperref[csr.i:decode]{csr},rs1}{rs1}\\end{scope}\n\t\\begin{scope}[shift={(0,-1.5)}]\\DrawInsnOpITypeSystem{1110011}{010}{\\hyperref[insn:csrrs]{csrrs}}{rd,\\hyperref[csr.i:decode]{csr},rs1}{rs1}\\end{scope}\n\t\\begin{scope}[shift={(0,-3.0)}]\\DrawInsnOpITypeSystem{1110011}{011}{\\hyperref[insn:csrrc]{csrrc}}{rd,\\hyperref[csr.i:decode]{csr},rs1}{rs1}\\end{scope}\n\t\\begin{scope}[shift={(0,-4.5)}]\\DrawInsnOpITypeSystem{1110011}{101}{\\hyperref[insn:csrrwi]{csrrwi}}{rd,\\hyperref[csr.i:decode]{csr},zimm}{zimm[4:0]}\\end{scope}\n\t\\begin{scope}[shift={(0,-6.0)}]\\DrawInsnOpITypeSystem{1110011}{110}{\\hyperref[insn:csrrsi]{csrrsi}}{rd,\\hyperref[csr.i:decode]{csr},zimm}{zimm[4:0]}\\end{scope}\n\t\\begin{scope}[shift={(0,-7.5)}]\\DrawInsnOpITypeSystem{1110011}{111}{\\hyperref[insn:csrrci]{csrrci}}{rd,\\hyperref[csr.i:decode]{csr},zimm}{zimm[4:0]}\\end{scope}\n\t\\begin{scope}[shift={(0,-7.5)}]\\DrawHexMarkersRel{32}\\end{scope}\n}\n\n\\newcommand\\DrawAllInsnOps{\n\t\\BeginTikzPicture\n\t\\begin{scope}[shift={(0,1.5)}]\\DrawInsnBoxCastleRtype\\end{scope}\n\t\\begin{scope}[shift={(0,0)}]\\DrawAllInsnOpsU\\end{scope}\n\t\\begin{scope}[shift={(0,-3.0)}]\\DrawAllInsnOpsJAL\\end{scope}\n\t\\begin{scope}[shift={(0,-6.2)}]\\DrawAllInsnOpsBranch\\end{scope}\n\t\\begin{scope}[shift={(0,-15.4)}]\\DrawAllInsnOpsLoad\\end{scope}\n\t\\begin{scope}[shift={(0,-23.1)}]\\DrawAllInsnOpsStore\\end{scope}\n\t\\begin{scope}[shift={(0,-27.8)}]\\DrawAllInsnOpsALUImm\\end{scope}\n\t\\begin{scope}[shift={(0,-37.0)}]\\DrawAllInsnOpsShiftImm\\end{scope}\n\t\\begin{scope}[shift={(0,-41.7)}]\\DrawAllInsnOpsALUR\\end{scope}\n\t\\begin{scope}[shift={(0,-57.4)}]\\DrawAllInsnOpsSim\\end{scope}\n\t\\begin{scope}[shift={(0,-60.6)}]\\DrawAllInsnOpsSystem\\end{scope}\n\n\t\\EndTikzPicture\n}\n\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% GREEN CARD VERSION OF INSN DIAGRAMS\n\n\n\\newcommand\\GCPageWidth{85.8}\n%\\newcommand\\GCPageWidth{86}\n\n% box, insn, desc, rtl\n%\\newcommand\\GCInsnEncodingPosX{0}\t\t% the box, sans-castle\n%\\newcommand\\GCInsnTypePosX{32.6}\t\t\t% R,I,U,B,...\n%\\newcommand\\GCInsnMnemonicPosX{34}\t\t% the template instruction source\n%\\newcommand\\GCInsnDescriptionPosX{47}\t% the long-form description\n%\\newcommand\\GCInsnRTLPosX{64}\t\t\t% the detailed RTL description\n\n% insn, desc, rtl, box\n\\newcommand\\GCInsnMnemonicPosX{0}\t\t% the template instruction source\n\\newcommand\\GCInsnDescriptionPosX{13}\t% the long-form description\n\\newcommand\\GCInsnRTLPosX{29.7}\t\t\t% the detailed RTL description\n\\newcommand\\GCInsnTypePosX{52.5}\t\t\t% R,I,U,B,...\n\\newcommand\\GCInsnEncodingPosX{53}\t\t% the box, sans-castle\n\n% #1 opcode\n% #2 mnemonic\n% #3 args\n% #4 description\n% #5 RTL\n\\newcommand\\DrawGCInsnOpU[5]{\n\t\\begin{scope}[shift={(\\GCInsnMnemonicPosX,.6)}]\\DrawInsnSrc{#2}{#3}\\end{scope}\n\t\\draw(\\GCInsnTypePosX,.75) node {U};\n\t\\draw(\\GCInsnDescriptionPosX,.6) node[right]{#4};\n\t\\draw(\\GCInsnRTLPosX,.6) node[right]{#5};\n\t\\begin{scope}[shift={(\\GCInsnEncodingPosX,0)}]\\DrawInsnOpUBox{imm[31:12]}{rd}{#1}\\end{scope}\n}\n\n% #1 opcode\n% #2 mnemonic\n% #3 args\n% #4 description\n% #5 RTL\n\\newcommand\\DrawGCInsnOpJ[5]{\n\t\\begin{scope}[shift={(\\GCInsnMnemonicPosX,.6)}]\\DrawInsnSrc{#2}{#3}\\end{scope}\n\t\\draw(\\GCInsnTypePosX,.75) node {J};\n\t\\draw(\\GCInsnDescriptionPosX,.6) node[right]{#4};\n\t\\draw(\\GCInsnRTLPosX,.6) node[right]{#5};\n\t\\begin{scope}[shift={(\\GCInsnEncodingPosX,0)}]\\DrawInsnOpJBox{imm[20\\textbar10:1\\textbar11\\textbar19:12]}{rd}{#1}\\end{scope}\n}\n\n% #1 opcode\n% #2 funct3\n% #3 mnemonic\n% #4 args\n% #5 description\n% #6 RTL\n\\newcommand\\DrawGCInsnOpI[6]{\n\t\\begin{scope}[shift={(\\GCInsnMnemonicPosX,.6)}]\\DrawInsnSrc{#3}{#4}\\end{scope}\n\t\\draw(\\GCInsnTypePosX,.75) node {I};\n\t\\draw(\\GCInsnDescriptionPosX,.6) node[right]{#5};\n\t\\draw(\\GCInsnRTLPosX,.6) node[right]{#6};\n\t\\begin{scope}[shift={(\\GCInsnEncodingPosX,0)}]\\DrawInsnOpIBox{imm[11:0]}{rs1}{#1}{rd}{#2}\\end{scope}\n}\n\n% #1 opcode\n% #2 funct3\n% #3 funct7\n% #4 mnemonic\n% #5 args\n% #6 description\n% #7 RTL\n\\newcommand\\DrawGCInsnOpIShift[7]{\n\t\\begin{scope}[shift={(\\GCInsnMnemonicPosX,.6)}]\\DrawInsnSrc{#4}{#5}\\end{scope}\n\t\\draw(\\GCInsnTypePosX,.75) node {I};\n\t\\draw(\\GCInsnDescriptionPosX,.6) node[right]{#6};\n\t\\draw(\\GCInsnRTLPosX,.6) node[right]{#7};\n\t\\begin{scope}[shift={(\\GCInsnEncodingPosX,0)}]\\DrawInsnOpIFunctBox{#1}{shamt}{rs1}{#2}{rd}{#3}\\end{scope}\n}\n\n% #1 opcode\n% #2 funct3\n% #3 mnemonic\n% #4 args\n% #5 csr\n% #6 description\n% #7 RTL\n\\newcommand\\DrawGCInsnOpICSR[7]{\n\t\\begin{scope}[shift={(\\GCInsnMnemonicPosX,.6)}]\\DrawInsnSrc{#3}{#4}\\end{scope}\n\t\\draw(\\GCInsnTypePosX,.75) node {I};\n\t\\draw(\\GCInsnDescriptionPosX,.6) node[right]{#6};\n\t\\draw(\\GCInsnRTLPosX,.6) node[right]{#7};\n\t\\begin{scope}[shift={(\\GCInsnEncodingPosX,0)}]\\DrawInsnOpIBox{csr[11:0]}{#5}{#1}{rd}{#2}\\end{scope}\n}\n\n% #1 opcode\n% #2 funct3\n% #3 mnemonic\n% #4 args\n% #5 description\n% #6 RTL\n\\newcommand\\DrawGCInsnOpB[6]{\n\t\\begin{scope}[shift={(\\GCInsnMnemonicPosX,.6)}]\\DrawInsnSrc{#3}{#4}\\end{scope}\n\t\\draw(\\GCInsnTypePosX,.75) node {B};\n\t\\draw(\\GCInsnDescriptionPosX,.6) node[right]{#5};\n\t\\draw(\\GCInsnRTLPosX,.6) node[right]{#6};\n\t\\begin{scope}[shift={(\\GCInsnEncodingPosX,0)}]\\DrawInsnOpBBox{imm[12\\textbar10:5]}{rs2}{rs1}{#1}{imm[4:1\\textbar11]}{#2}\\end{scope}\n}\n\n% #1 opcode\n% #2 funct3\n% #3 mnemonic\n% #4 args\n% #5 description\n% #6 RTL\n\\newcommand\\DrawGCInsnOpS[6]{\n\t\\begin{scope}[shift={(\\GCInsnMnemonicPosX,.6)}]\\DrawInsnSrc{#3}{#4}\\end{scope}\n\t\\draw(\\GCInsnTypePosX,.75) node {S};\n\t\\draw(\\GCInsnDescriptionPosX,.6) node[right]{#5};\n\t\\draw(\\GCInsnRTLPosX,.6) node[right]{#6};\n\t\\begin{scope}[shift={(\\GCInsnEncodingPosX,0)}]\\DrawInsnOpBBox{imm[11:5]}{rs2}{rs1}{#1}{imm[4:0]}{#2}\\end{scope}\n}\n\n% #1 opcode\n% #2 funct3\n% #3 funct7\n% #4 mnemonic\n% #5 args\n% #6 description\n% #7 RTL\n\\newcommand\\DrawGCInsnOpR[7]{\n\t\\begin{scope}[shift={(\\GCInsnMnemonicPosX,.6)}]\\DrawInsnSrc{#4}{#5}\\end{scope}\n\t\\draw(\\GCInsnTypePosX,.75) node {R};\n\t\\draw(\\GCInsnDescriptionPosX,.6) node[right]{#6};\n\t\\draw(\\GCInsnRTLPosX,.6) node[right]{#7};\n\t\\begin{scope}[shift={(\\GCInsnEncodingPosX,0)}]\\DrawInsnOpRBox{#3}{rs2}{rs1}{#2}{rd}{#1}\\end{scope}\n}\n\n% #1 opcode\n% #2 funct7\n% #3 mnemonic\n% #4 description\n\\newcommand\\DrawGCInsnOpSys[4]{\n\t\\begin{scope}[shift={(\\GCInsnMnemonicPosX,.6)}]\\DrawInsnSrc{#3}{}\\end{scope}\n\t\\draw(\\GCInsnTypePosX,.75) node {I};\n\t\\draw(\\GCInsnDescriptionPosX,.6) node[right]{#4};\n%\t\\draw(\\GCInsnRTLPosX,.6) node[right]{#4};\n\t\\begin{scope}[shift={(\\GCInsnEncodingPosX,0)}]\\DrawInsnOpIBinBox{#20000000000000#1}\\end{scope}\n}\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\n\n\\newcommand\\DrawGCAllInsnOpsU{\n\t\\begin{scope}[shift={(0,0)}]\\DrawGCInsnOpU{0110111}{lui}{rd,imm}{Load Upper Immediate}{\\tt rd $\\leftarrow$ imm\\_u, pc $\\leftarrow$ pc+4}\\end{scope}\n\t\\begin{scope}[shift={(0,-1.5)}]\\DrawGCInsnOpU{0010111}{auipc}{rd,imm}{Add Upper Immediate to PC}{\\tt rd $\\leftarrow$ pc + imm\\_u, pc $\\leftarrow$ pc+4}\\end{scope}\n}\n\n\\newcommand\\DrawGCAllInsnOpsJAL{\n\t\\begin{scope}[shift={(0,0)}]\\DrawGCInsnOpJ{1101111}{jal}{rd,pcrel\\_21}{Jump And Link}{\\tt rd $\\leftarrow$ pc+4, pc $\\leftarrow$ pc+imm\\_j}\\end{scope}\n\t\\begin{scope}[shift={(0,-1.5)}]\\DrawGCInsnOpI{1100111}{000}{jalr}{rd,imm(rs1)}{Jump And Link Register}{\\tt rd $\\leftarrow$ pc+4, pc $\\leftarrow$ (rs1+imm\\_i) $\\land$ $\\sim$1}\\end{scope}\n}\n\n\\newcommand\\DrawGCAllInsnOpsBranch{\n\t\\begin{scope}[shift={(0,0)}]\\DrawGCInsnOpB{1100011}{000}{beq}{rs1,rs2,pcrel\\_13}{Branch Equal}{\\tt pc $\\leftarrow$ pc + ((rs1==rs2) ?\\ imm\\_b :\\ 4)}\\end{scope}\n\t\\begin{scope}[shift={(0,-1.5)}]\\DrawGCInsnOpB{1100011}{001}{bne}{rs1,rs2,pcrel\\_13}{Branch Not Equal}{\\tt pc $\\leftarrow$ pc + ((rs1!=rs2) ?\\ imm\\_b :\\ 4)}\\end{scope}\n\t\\begin{scope}[shift={(0,-3)}]\\DrawGCInsnOpB{1100011}{100}{blt}{rs1,rs2,pcrel\\_13}{Branch Less Than}{\\tt pc $\\leftarrow$ pc + ((rs1=rs2) ?\\ imm\\_b :\\ 4)}\\end{scope}\n\t\\begin{scope}[shift={(0,-6)}]\\DrawGCInsnOpB{1100011}{110}{bltu}{rs1,rs2,pcrel\\_13}{Branch Less Than Unsigned}{\\tt pc $\\leftarrow$ pc + ((rs1=rs2) ?\\ imm\\_b :\\ 4)}\\end{scope}\n}\n\\newcommand\\DrawGCAllInsnOpsLoad{\n\t\\begin{scope}[shift={(0,0)}]\\DrawGCInsnOpI{0000011}{000}{lb}{rd,imm(rs1)}{Load Byte}{\\tt rd $\\leftarrow$ sx(m8(rs1+imm\\_i)), pc $\\leftarrow$ pc+4}\\end{scope}\n\t\\begin{scope}[shift={(0,-1.5)}]\\DrawGCInsnOpI{0000011}{001}{lh}{rd,imm(rs1)}{Load Halfword}{\\tt rd $\\leftarrow$ sx(m16(rs1+imm\\_i)), pc $\\leftarrow$ pc+4}\\end{scope}\n\t\\begin{scope}[shift={(0,-3.0)}]\\DrawGCInsnOpI{0000011}{010}{lw}{rd,imm(rs1)}{Load Word}{\\tt rd $\\leftarrow$ sx(m32(rs1+imm\\_i)), pc $\\leftarrow$ pc+4}\\end{scope}\n\t\\begin{scope}[shift={(0,-4.5)}]\\DrawGCInsnOpI{0000011}{100}{lbu}{rd,imm(rs1)}{Load Byte Unsigned}{\\tt rd $\\leftarrow$ zx(m8(rs1+imm\\_i)), pc $\\leftarrow$ pc+4}\\end{scope}\n\t\\begin{scope}[shift={(0,-6.0)}]\\DrawGCInsnOpI{0000011}{101}{lhu}{rd,imm(rs1)}{Load Halfword Unsigned}{\\tt rd $\\leftarrow$ zx(m16(rs1+imm\\_i)), pc $\\leftarrow$ pc+4}\\end{scope}\n}\n\n\\newcommand\\DrawGCAllInsnOpsALUImm{\n\t\\begin{scope}[shift={(0,0)}]\\DrawGCInsnOpI{0010011}{000}{addi}{rd,rs1,imm}{Add Immediate}{\\tt rd $\\leftarrow$ rs1 + imm\\_i, pc $\\leftarrow$ pc+4}\\end{scope}\n\t\\begin{scope}[shift={(0,-1.5)}]\\DrawGCInsnOpI{0010011}{010}{slti}{rd,rs1,imm}{Set Less Than Immediate}{\\tt rd $\\leftarrow$ (rs1 < imm\\_i) ?\\ 1 :\\ 0, pc $\\leftarrow$ pc+4}\\end{scope}\n\t\\begin{scope}[shift={(0,-3.0)}]\\DrawGCInsnOpI{0010011}{011}{sltiu}{rd,rs1,imm}{Set Less Than Immediate Unsigned}{\\tt rd $\\leftarrow$ (rs1 < imm\\_i) ?\\ 1 :\\ 0, pc $\\leftarrow$ pc+4}\\end{scope}\n\t\\begin{scope}[shift={(0,-4.5)}]\\DrawGCInsnOpI{0010011}{100}{xori}{rd,rs1,imm}{Exclusive Or Immediate}{\\tt rd $\\leftarrow$ rs1 $\\oplus$ imm\\_i, pc $\\leftarrow$ pc+4}\\end{scope}\n\t\\begin{scope}[shift={(0,-6.0)}]\\DrawGCInsnOpI{0010011}{110}{ori}{rd,rs1,imm}{Or Immediate}{\\tt rd $\\leftarrow$ rs1 $\\lor$ imm\\_i, pc $\\leftarrow$ pc+4}\\end{scope}\n\t\\begin{scope}[shift={(0,-7.5)}]\\DrawGCInsnOpI{0010011}{111}{andi}{rd,rs1,imm}{And Immediate}{\\tt rd $\\leftarrow$ rs1 $\\land$ imm\\_i, pc $\\leftarrow$ pc+4}\\end{scope}\n}\n\n% note that the S-Type insns have the same field-format as the B-type\n\\newcommand\\DrawGCAllInsnOpsStore{\n\t\\begin{scope}[shift={(0,0)}]\\DrawGCInsnOpS{0100011}{000}{sb}{rs2,imm(rs1)}{Store Byte}{\\tt m8(rs1+imm\\_s) $\\leftarrow$ rs2[7:0], pc $\\leftarrow$ pc+4}\\end{scope}\n\t\\begin{scope}[shift={(0,-1.5)}]\\DrawGCInsnOpS{0100011}{001}{sh}{rs2,imm(rs1)}{Store Halfword}{\\tt m16(rs1+imm\\_s) $\\leftarrow$ rs2[15:0], pc $\\leftarrow$ pc+4}\\end{scope}\n\t\\begin{scope}[shift={(0,-3.0)}]\\DrawGCInsnOpS{0100011}{010}{sw}{rs2,imm(rs1)}{Store Word}{\\tt m32(rs1+imm\\_s) $\\leftarrow$ rs2[31:0], pc $\\leftarrow$ pc+4}\\end{scope}\n}\n\n\\newcommand\\DrawGCAllInsnOpsALUR{\n\t\\begin{scope}[shift={(0,0)}]\\DrawGCInsnOpR{0110011}{000}{0000000}{add}{rd,rs1,rs2}{Add}{\\tt rd $\\leftarrow$ rs1 + rs2, pc $\\leftarrow$ pc+4}\\end{scope}\n\t\\begin{scope}[shift={(0,-1.5)}]\\DrawGCInsnOpR{0110011}{000}{0100000}{sub}{rd,rs1,rs2}{Subtract}{\\tt rd $\\leftarrow$ rs1 - rs2, pc $\\leftarrow$ pc+4}\\end{scope}\n\t\\begin{scope}[shift={(0,-3.0)}]\\DrawGCInsnOpR{0110011}{001}{0000000}{sll}{rd,rs1,rs2}{Shift Left Logical}{\\tt rd $\\leftarrow$ rs1 << (rs2\\%XLEN), pc $\\leftarrow$ pc+4}\\end{scope}\n\t\\begin{scope}[shift={(0,-4.5)}]\\DrawGCInsnOpR{0110011}{010}{0000000}{slt}{rd,rs1,rs2}{Set Less Than}{\\tt rd $\\leftarrow$ (rs1 < rs2) ?\\ 1 :\\ 0, pc $\\leftarrow$ pc+4}\\end{scope}\n\t\\begin{scope}[shift={(0,-6.0)}]\\DrawGCInsnOpR{0110011}{011}{0000000}{sltu}{rd,rs1,rs2}{Set Less Than Unsigned}{\\tt rd $\\leftarrow$ (rs1 < rs2) ?\\ 1 :\\ 0, pc $\\leftarrow$ pc+4}\\end{scope}\n\t\\begin{scope}[shift={(0,-7.5)}]\\DrawGCInsnOpR{0110011}{100}{0000000}{xor}{rd,rs1,rs2}{Exclusive Or}{\\tt rd $\\leftarrow$ rs1 $\\oplus$ rs2, pc $\\leftarrow$ pc+4}\\end{scope}\n\t\\begin{scope}[shift={(0,-9.0)}]\\DrawGCInsnOpR{0110011}{101}{0000000}{srl}{rd,rs1,rs2}{Shift Right Logical}{\\tt rd $\\leftarrow$ rs1 >> (rs2\\%XLEN), pc $\\leftarrow$ pc+4}\\end{scope}\n\t\\begin{scope}[shift={(0,-10.5)}]\\DrawGCInsnOpR{0110011}{101}{0100000}{sra}{rd,rs1,rs2}{Shift Right Arithmetic}{\\tt rd $\\leftarrow$ rs1 >> (rs2\\%XLEN), pc $\\leftarrow$ pc+4}\\end{scope}\n\t\\begin{scope}[shift={(0,-12.0)}]\\DrawGCInsnOpR{0110011}{110}{0000000}{or}{rd,rs1,rs2}{Or}{\\tt rd $\\leftarrow$ rs1 $\\lor$ rs2, pc $\\leftarrow$ pc+4}\\end{scope}\n\t\\begin{scope}[shift={(0,-13.5)}]\\DrawGCInsnOpR{0110011}{111}{0000000}{and}{rd,rs1,rs2}{And}{\\tt rd $\\leftarrow$ rs1 $\\land$ rs2, pc $\\leftarrow$ pc+4}\\end{scope}\n}\n\n\\newcommand\\DrawGCAllInsnOpsSystem{\n\t\\begin{scope}[shift={(0,0)}]\\DrawGCInsnOpICSR{1110011}{001}{csrrw}{rd,csr,rs1}{rs1}{Atomic Read/Write}{\\tt rd $\\leftarrow$ csr, csr $\\leftarrow$ rs1, pc $\\leftarrow$ pc+4}\\end{scope}\n\t\\begin{scope}[shift={(0,-1.5)}]\\DrawGCInsnOpICSR{1110011}{010}{csrrs}{rd,csr,rs1}{rs1}{Atomic Read and Set}{\\tt rd $\\leftarrow$ csr, csr $\\leftarrow$ csr $\\lor$ rs1, pc $\\leftarrow$ pc+4}\\end{scope}\n\t\\begin{scope}[shift={(0,-3.0)}]\\DrawGCInsnOpICSR{1110011}{011}{csrrc}{rd,csr,rs1}{rs1}{Atomic Read and Clear}{\\tt rd $\\leftarrow$ csr, csr $\\leftarrow$ csr $\\land$ $\\sim$rs1, pc $\\leftarrow$ pc+4}\\end{scope}\n\t\\begin{scope}[shift={(0,-4.5)}]\\DrawGCInsnOpICSR{1110011}{101}{csrrwi}{rd,csr,zimm}{zimm[4:0]}{Atomic Read/Write Immediate}{\\tt rd $\\leftarrow$ csr, csr $\\leftarrow$ zimm, pc $\\leftarrow$ pc+4}\\end{scope}\n\t\\begin{scope}[shift={(0,-6.0)}]\\DrawGCInsnOpICSR{1110011}{110}{csrrsi}{rd,csr,zimm}{zimm[4:0]}{Atomic Read and Set Immediate}{\\tt rd $\\leftarrow$ csr, csr $\\leftarrow$ csr $\\lor$ zimm, pc $\\leftarrow$ pc+4}\\end{scope}\n\t\\begin{scope}[shift={(0,-7.5)}]\\DrawGCInsnOpICSR{1110011}{111}{csrrci}{rd,csr,zimm}{zimm[4:0]}{Atomic Read and Clear Immediate}{\\tt rd $\\leftarrow$ csr, csr $\\leftarrow$ csr $\\land$ $\\sim$zimm, pc $\\leftarrow$ pc+4}\\end{scope}\n}\n\n\\newcommand\\DrawGCAllInsnOpsSim{\n\t\\begin{scope}[shift={(0,0)}]\\DrawGCInsnOpSys{1110011}{000000000000}{ecall}{Trap to Debugger}\\end{scope}\n\t\\begin{scope}[shift={(0,-1.5)}]\\DrawGCInsnOpSys{1110011}{000000000001}{ebreak}{Trap to Operating System}\\end{scope}\n}\n\n\\newcommand\\DrawGCAllInsnOpsShiftImm{\n\t\\begin{scope}[shift={(0,0)}]\\DrawGCInsnOpIShift{0010011}{001}{0000000}{slli}{rd,rs1,shamt}{Shift Left Logical Immediate}{\\tt rd $\\leftarrow$ rs1 << shamt\\_i, pc $\\leftarrow$ pc+4}\\end{scope}\n\t\\begin{scope}[shift={(0,-1.5)}]\\DrawGCInsnOpIShift{0010011}{101}{0000000}{srli}{rd,rs1,shamt}{Shift Right Logical Immediate}{\\tt rd $\\leftarrow$ rs1 >> shamt\\_i, pc $\\leftarrow$ pc+4}\\end{scope}\n\t\\begin{scope}[shift={(0,-3.0)}]\\DrawGCInsnOpIShift{0010011}{101}{0100000}{srai}{rd,rs1,shamt}{Shift Right Arithmetic Immediate}{\\tt rd $\\leftarrow$ rs1 >> shamt\\_i, pc $\\leftarrow$ pc+4}\\end{scope}\n}\n\n\\newcommand\\DrawGCAllInsnOpsPseudo{\n\t\\draw(0, 0) node[right]{p1};\n\t\\draw(0, -1.5) node[right]{p1};\n\t\\draw(0, -3.0) node[right]{p1};\n\t\\draw(0, -4.5) node[right]{p1};\n\t\\draw(0, -6.0) node[right]{p1};\n\t\\draw(0, -7.5) node[right]{p1};\n\t\\draw(0, -9.0) node[right]{p1};\n\t\\draw(0,-10.5) node[right]{p1};\n\t\\draw(0,-12.0) node[right]{p1};\n\t\\draw(0,-13.5) node[right]{p1};\n\t\\draw(0,-15.0) node[right]{p1};\n\t\\draw(0,-16.5) node[right]{p1};\n\t\\draw(0,-18.0) node[right]{p1};\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% a color to hilight the rows on the card\n\\definecolor{GCBarColorBG}{RGB}{200,255,200}\n\\definecolor{GCBarColorFG}{RGB}{128,220,128}\n\\definecolor{GCSlugColorFG}{RGB}{20,100,20}\n\n\\newcommand\\DrawGCAllInsnOps{\n\t\\BeginTikzPicture\n\n\t% draw color graybars\n\t\\foreach \\y in {1.5,-7.5,...,-66}%\n\t\t\\draw [draw=GCBarColorFG,fill=GCBarColorBG,thick] (0,\\y) rectangle (\\GCPageWidth,\\y-4.5);\n\n\t% draw some nybble-slugs\n\t\\foreach \\y in {-3,-7.5,...,-66}%\n\t\t\\foreach \\x in {4,8,...,30}%\n\t\t\t\\draw [line width=.5mm,draw=GCSlugColorFG] (\\x+.5+\\GCInsnEncodingPosX,\\y) -- (\\x+.5+\\GCInsnEncodingPosX, \\y+.3);%\n\n\t\\begin{scope}[shift={(\\GCInsnEncodingPosX,1.5)}]\\DrawInsnBoxCastleRtype\\end{scope}\n\n\t% add some field names in the castle\n\t\\begin{scope}[shift={(\\GCInsnEncodingPosX,1.5)}]\n\t\t\\node at (4,1.25) {\\small funct7};\n\t\t\\node at (19,1.25) {\\small funct3};\n\t\t\\node at (29,1.25) {\\small opcode};\n\t\\end{scope}\n\n\t\\draw node at (\\GCInsnMnemonicPosX+6,2.75) {\\small Instruction};\n\t\\draw node at (\\GCInsnDescriptionPosX+8,2.75) {\\small Description};\n\t\\draw node at (\\GCInsnRTLPosX+12,2.75) {\\small Operation};\n\t\\draw node at (\\GCInsnTypePosX,2.75) {\\small Type};\n\n\t%\\node [draw, rotate=90] at (0,60) {\\small RV32I Reference Card (\\href{https://github.com/johnwinans/rvalp}{https://github.com/johnwinans/rvalp})};\n\t%\\draw node[rotate=90,right] at (\\GCPageWidth+.7,-66) {\\small RV32I Reference Card};\n\t%\\draw node[rotate=90,left] at (\\GCPageWidth+.7,1.5) {\\small https://github.com/johnwinans/rvalp};\n\t\\draw node[rotate=90,right] at (-.7,-66) {\\small RV32I Reference Card};\n\t\\draw node[rotate=90,left] at (-.7,1.5) {\\small https://github.com/johnwinans/rvalp};\n\n\n\t\\begin{scope}[shift={(0,0)}]\\DrawGCAllInsnOpsU\\end{scope}\n\t\\begin{scope}[shift={(0,-3)}]\\DrawGCAllInsnOpsJAL\\end{scope}\n\t\\begin{scope}[shift={(0,-6)}]\\DrawGCAllInsnOpsBranch\\end{scope}\n\t\\begin{scope}[shift={(0,-15)}]\\DrawGCAllInsnOpsLoad\\end{scope}\n\t\\begin{scope}[shift={(0,-22.5)}]\\DrawGCAllInsnOpsStore\\end{scope}\n\t\\begin{scope}[shift={(0,-27)}]\\DrawGCAllInsnOpsALUImm\\end{scope}\n\t\\begin{scope}[shift={(0,-36)}]\\DrawGCAllInsnOpsShiftImm\\end{scope}\n\t\\begin{scope}[shift={(0,-40.5)}]\\DrawGCAllInsnOpsALUR\\end{scope}\n\t\\begin{scope}[shift={(0,-55.5)}]\\DrawGCAllInsnOpsSim\\end{scope}\n\t\\begin{scope}[shift={(0,-58.5)}]\\DrawGCAllInsnOpsSystem\\end{scope}\n\n\t% stub in some space for pseudo-instruictions to see what it might look like\n\t%\\begin{scope}[shift={(0,-67)}]\\DrawGCAllInsnOpsPseudo\\end{scope}\n\n\t% show markers to indicate where to fold it \n\t\\draw [line width=.1mm,draw=GCSlugColorFG] (29.5,1) -- (29.5, 1.5);\n\t\\draw [line width=.1mm,draw=GCSlugColorFG] (29.5,-65.5) -- (29.5, -66);\n\n\t\\EndTikzPicture\n}\n\n\n\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\n\\newcommand\\InsnBoxFieldWidthArrowVskip{.5}\n\\newcommand\\InsnBoxFieldWidthArrowHskip{.05}\n\n% #1 MSB position\n% #2 LSB position\n\\newcommand\\InsnBoxFieldWidthArrow[2]{\n\t\\pgfmathsetmacro\\leftpos{int(31-#1)}\t\t% Calculate the left end position\n\t\\pgfmathsetmacro\\wid{int(#1-#2+1)}\t\t\t% calculate the width\n\t\\begin{scope}[shift={(\\leftpos,-\\InsnBoxFieldWidthArrowVskip)}]\t% Move to left end of arrow & below origin\n \t\\pgfmathsetmacro\\result{\\wid*.5+.5}\t\t% the center position\n \t\\node at (\\result,0) {\\tiny\\wid};\t\t% draw the size number below the box\n\n\t\t\\ifthenelse{\\wid > 9}\t\t\t\t\t% make 1-9 narrower than 10-99\n\t\t{ \\pgfmathsetmacro\\Inset{0.4} }\n\t\t{ \n\t\t\t\\ifthenelse{\\wid > 1} \t\t\t\t% make 1 narrower than 2-9\n\t\t\t{ \\pgfmathsetmacro\\Inset{0.25} }\n\t\t\t{ \\pgfmathsetmacro\\Inset{0.15} }\n\t\t}\n\n\t\t% arrowsInsnBoxFieldWidthArrowHskip\n \t\\draw[->] (\\result+\\Inset,0) -- (\\wid+.5-\\InsnBoxFieldWidthArrowHskip,0);\t% arrow to the right\n \t\\draw[->] (\\result-\\Inset,0) -- (.5+\\InsnBoxFieldWidthArrowHskip,0);\t\t% arrow to the left\n\n\t\t\\pgfmathsetmacro\\x{.5}\n\t\t\\pgfmathsetmacro\\y{\\InsnBoxFieldWidthArrowVskip}\n\t\t% vertical bars at the ends of the arrows\n \t\\draw[-] (\\x,\\y) -- (\\x,-\\y*.5);\t\n\t\t\\pgfmathsetmacro\\x{(\\wid+.5}\n \t\\draw[-] (\\x,\\y) -- (\\x,-\\y*.5);\t\n\n\t\\end{scope}\n}\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\n\\newcommand\\BitBoxArrowTailInset{-.9}\n\\newcommand\\BitBoxArrowHeadInset{-16.7-\\BitBoxArrowTailInset}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% special case for R type instructions for consistency\n\\newcommand\\InsnOpRTypeDecoding{\n\n\t\\begin{scope}[shift={(0,-1.5)}]\n\t\\DrawInsnTypeR{abcdefghijklmnopqrstuvwxy1101111}\n\t\\end{scope}\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\n\\newcommand\\InsnOpJTypeDecoding{\n\n\t\\begin{scope}[shift={(0,-1.5)}]\n\n\t\\DrawInsnTypeJ{abcdefghijklmnopqrst001111101111}\n\n\t\\pgfmathsetmacro\\ArrowNorth{\\BitBoxArrowTailInset}\n\t\\pgfmathsetmacro\\ArrowSouth{\\BitBoxArrowHeadInset}\n\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](1,\\ArrowSouth);\t% 20\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](2,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](3,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](4,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](5,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](6,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](7,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](8,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](9,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](10,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](11,\\ArrowSouth);\t% sign extend\n\n\t\\draw[blue,->](1,\\ArrowNorth)to[out=270,in=90](12,\\ArrowSouth);\t\t% 20\n\t\\draw[blue,->](13,\\ArrowNorth)to[out=270,in=90](13,\\ArrowSouth);\t% 19\n\t\\draw[blue,->](14,\\ArrowNorth)to[out=270,in=90](14,\\ArrowSouth);\t% 18\n\t\\draw[blue,->](15,\\ArrowNorth)to[out=270,in=90](15,\\ArrowSouth);\t% 17\n\t\\draw[blue,->](16,\\ArrowNorth)to[out=270,in=90](16,\\ArrowSouth);\t% 16\n\t\\draw[blue,->](17,\\ArrowNorth)to[out=270,in=90](17,\\ArrowSouth);\t% 15\n\t\\draw[blue,->](18,\\ArrowNorth)to[out=270,in=90](18,\\ArrowSouth);\t% 14\n\t\\draw[blue,->](19,\\ArrowNorth)to[out=270,in=90](19,\\ArrowSouth);\t% 13\n\t\\draw[blue,->](20,\\ArrowNorth)to[out=270,in=90](20,\\ArrowSouth);\t% 12\n\n\t\\draw[blue,->](12,\\ArrowNorth)to[out=270,in=90](21,\\ArrowSouth);\t% 11\n\n\t\\draw[blue,->](2,\\ArrowNorth)to[out=270,in=90](22,\\ArrowSouth);\t\t% 10\n\t\\draw[blue,->](3,\\ArrowNorth)to[out=270,in=90](23,\\ArrowSouth);\t\t% 9\n\t\\draw[blue,->](4,\\ArrowNorth)to[out=270,in=90](24,\\ArrowSouth);\t\t% 8\n\t\\draw[blue,->](5,\\ArrowNorth)to[out=270,in=90](25,\\ArrowSouth);\t\t% 7\n\t\\draw[blue,->](6,\\ArrowNorth)to[out=270,in=90](26,\\ArrowSouth);\t\t% 6\n\t\\draw[blue,->](7,\\ArrowNorth)to[out=270,in=90](27,\\ArrowSouth);\t\t% 5\n\t\\draw[blue,->](8,\\ArrowNorth)to[out=270,in=90](28,\\ArrowSouth);\t\t% 4\n\t\\draw[blue,->](9,\\ArrowNorth)to[out=270,in=90](29,\\ArrowSouth);\t\t% 3\n\t\\draw[blue,->](10,\\ArrowNorth)to[out=270,in=90](30,\\ArrowSouth);\t% 2\n\t\\draw[blue,->](11,\\ArrowNorth)to[out=270,in=90](31,\\ArrowSouth);\t% 1\n\n\t\\draw[red,->](34,\\ArrowSouth+5)to[out=180,in=90](32,\\ArrowSouth);\t% 0 (special case)\n\t\\node at (34.5,\\ArrowSouth+5) {0};\n%\t\\draw[blue,->](32,\\ArrowSouth+1)to[out=270,in=90](32,\\ArrowSouth);\t% 0 (special case)\n%\t\\node at (32,\\ArrowSouth+2) {0};\n\n\t\\begin{scope}[shift={(0,0)}]\\DrawHexMarkersRel{32}\\end{scope}\n\t\\end{scope}\n\n\t\\begin{scope}[shift={(0,-19.75)}]\n\t\t\\begin{scope}[shift={(0,1.5)}]\n\t\t\t\\DrawInsnBoxCastle{31}{21}\n\t\t\t\\DrawInsnBoxCastle{20}{20}\n\t\t\t\\DrawInsnBoxCastle{19}{12}\n\t\t\t\\DrawInsnBoxCastle{11}{11}\n\t\t\t\\DrawInsnBoxCastle{10}{1}\n\t\t\t\\DrawInsnBoxCastle{0}{0}\n\t\t\\end{scope}\n\t\t\\DrawInsnBoxRel{31}{0}{}\n\t\t\\draw(33,.5) node[text width = 10, text height = 1, right]{imm\\_j};\n\n\t\t\\begin{scope}[shift={(0,0)}]\\DrawBitstringX{aaaaaaaaaaaamnopqrstlbcdefghijk0}\\end{scope}\n\t\t\\begin{scope}[shift={(0,0)}]\\DrawHexMarkersRel{32}\\end{scope}\n\n\t\t\\InsnBoxFieldWidthArrow{31}{21}\n\t\t\\InsnBoxFieldWidthArrow{20}{20}\n\t\t\\InsnBoxFieldWidthArrow{19}{12}\n\t\t\\InsnBoxFieldWidthArrow{11}{11}\n\t\t\\InsnBoxFieldWidthArrow{10}{1}\n\t\t\\InsnBoxFieldWidthArrow{0}{0}\n\t\\end{scope}\n}\n\n\\newcommand\\DrawInsnOpJTypeDecoding{\n\t\\BeginTikzPicture\n\t\\InsnOpJTypeDecoding\n\t\\EndTikzPicture\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\newcommand\\InsnOpBTypeDecoding{\n\n\t\\begin{scope}[shift={(0,-1.5)}]\n\n\t\\DrawInsnTypeB{abcdefg0111100011000uvwxy1100011}\n\n\t\\pgfmathsetmacro\\ArrowNorth{\\BitBoxArrowTailInset}\n\t\\pgfmathsetmacro\\ArrowSouth{\\BitBoxArrowHeadInset}\n\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](1,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](2,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](3,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](4,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](5,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](6,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](7,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](8,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](9,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](10,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](11,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](12,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](13,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](14,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](15,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](16,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](17,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](18,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](19,\\ArrowSouth);\t% sign extend\n\n\t\\draw[blue,->](1,\\ArrowNorth)to[out=270,in=90](20,\\ArrowSouth);\t\t% 12\n\n\t\\draw[blue,->](25,\\ArrowNorth)to[out=270,in=90](21,\\ArrowSouth);\t% 11\n\n\t\\draw[blue,->](2,\\ArrowNorth)to[out=270,in=90](22,\\ArrowSouth);\t\t% 10\n\t\\draw[blue,->](3,\\ArrowNorth)to[out=270,in=90](23,\\ArrowSouth);\t\t% 9\n\t\\draw[blue,->](4,\\ArrowNorth)to[out=270,in=90](24,\\ArrowSouth);\t\t% 8\n\t\\draw[blue,->](5,\\ArrowNorth)to[out=270,in=90](25,\\ArrowSouth);\t\t% 7\n\t\\draw[blue,->](6,\\ArrowNorth)to[out=270,in=90](26,\\ArrowSouth);\t\t% 6\n\t\\draw[blue,->](7,\\ArrowNorth)to[out=270,in=90](27,\\ArrowSouth);\t\t% 5\n\n\t\\draw[blue,->](21,\\ArrowNorth)to[out=270,in=90](28,\\ArrowSouth);\t% 4\n\t\\draw[blue,->](22,\\ArrowNorth)to[out=270,in=90](29,\\ArrowSouth);\t% 3\n\t\\draw[blue,->](23,\\ArrowNorth)to[out=270,in=90](30,\\ArrowSouth);\t% 2\n\t\\draw[blue,->](24,\\ArrowNorth)to[out=270,in=90](31,\\ArrowSouth);\t% 1\n\n\t\\draw[red,->](34,\\ArrowSouth+5)to[out=180,in=90](32,\\ArrowSouth);\t% 0 (special case)\n\t\\node at (34.5,\\ArrowSouth+5) {0};\n%\t\\draw[blue,->](32,\\ArrowSouth+1)to[out=270,in=90](32,\\ArrowSouth);\t% 0 (special case)\n%\t\\node at (32,\\ArrowSouth+2) {0};\n\n\t\\begin{scope}[shift={(0,0)}]\\DrawHexMarkersRel{32}\\end{scope}\n\t\\end{scope}\n\n\t\\begin{scope}[shift={(0,-19.75)}]\n\t\t\\begin{scope}[shift={(0,1.5)}]\n\t\t\t\\DrawInsnBoxCastle{31}{13}\n\t\t\t\\DrawInsnBoxCastle{12}{12}\n\t\t\t\\DrawInsnBoxCastle{11}{11}\n\t\t\t\\DrawInsnBoxCastle{10}{5}\n\t\t\t\\DrawInsnBoxCastle{4}{1}\n\t\t\t\\DrawInsnBoxCastle{0}{0}\n\t\t\\end{scope}\n\t\t\\DrawInsnBoxRel{31}{0}{}\n\t\t\\draw(33,.5) node[text width = 10, text height = 1, right]{imm\\_b};\n\n\t\t\\begin{scope}[shift={(0,0)}]\\DrawBitstringX{aaaaaaaaaaaaaaaaaaaaybcdefguvwx0}\\end{scope}\n\n\t\t\\begin{scope}[shift={(0,0)}]\\DrawHexMarkersRel{32}\\end{scope}\n\n\t\t\\InsnBoxFieldWidthArrow{31}{13}\n\t\t\\InsnBoxFieldWidthArrow{12}{12}\n\t\t\\InsnBoxFieldWidthArrow{11}{11}\n\t\t\\InsnBoxFieldWidthArrow{10}{5}\n\t\t\\InsnBoxFieldWidthArrow{4}{1}\n\t\t\\InsnBoxFieldWidthArrow{0}{0}\n\t\\end{scope}\n}\n\n\\newcommand\\DrawInsnOpBTypeDecoding{\n\t\\BeginTikzPicture\n\t\\InsnOpBTypeDecoding\n\t\\EndTikzPicture\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\newcommand\\InsnOpSTypeDecoding{\n\n\t\\begin{scope}[shift={(0,-1.5)}]\n\n\t\\DrawInsnTypeS{abcdefg0111100011000uvwxy0100011}\n\n\t\\pgfmathsetmacro\\ArrowNorth{\\BitBoxArrowTailInset}\n\t\\pgfmathsetmacro\\ArrowSouth{\\BitBoxArrowHeadInset}\n\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](1,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](2,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](3,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](4,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](5,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](6,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](7,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](8,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](9,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](10,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](11,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](12,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](13,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](14,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](15,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](16,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](17,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](18,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](19,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](20,\\ArrowSouth);\t% sign extend\n\n\t\\draw[blue,->](1,\\ArrowNorth)to[out=270,in=90](21,\\ArrowSouth);\t\t% 11\n\t\\draw[blue,->](2,\\ArrowNorth)to[out=270,in=90](22,\\ArrowSouth);\t\t% 10\n\t\\draw[blue,->](3,\\ArrowNorth)to[out=270,in=90](23,\\ArrowSouth);\t\t% 9\n\t\\draw[blue,->](4,\\ArrowNorth)to[out=270,in=90](24,\\ArrowSouth);\t\t% 8\n\t\\draw[blue,->](5,\\ArrowNorth)to[out=270,in=90](25,\\ArrowSouth);\t\t% 7\n\t\\draw[blue,->](6,\\ArrowNorth)to[out=270,in=90](26,\\ArrowSouth);\t\t% 6\n\t\\draw[blue,->](7,\\ArrowNorth)to[out=270,in=90](27,\\ArrowSouth);\t\t% 5\n\n\t\\draw[blue,->](21,\\ArrowNorth)to[out=270,in=90](28,\\ArrowSouth);\t% 4\n\t\\draw[blue,->](22,\\ArrowNorth)to[out=270,in=90](29,\\ArrowSouth);\t% 3\n\t\\draw[blue,->](23,\\ArrowNorth)to[out=270,in=90](30,\\ArrowSouth);\t% 2\n\t\\draw[blue,->](24,\\ArrowNorth)to[out=270,in=90](31,\\ArrowSouth);\t% 1\n\t\\draw[blue,->](25,\\ArrowNorth)to[out=270,in=90](32,\\ArrowSouth);\t% 0\n\n\t\\begin{scope}[shift={(0,0)}]\\DrawHexMarkersRel{32}\\end{scope}\n\t\\end{scope}\n\n\t\\begin{scope}[shift={(0,-19.75)}]\n\t\t\\begin{scope}[shift={(0,1.5)}]\n\t\t\t\\DrawInsnBoxCastle{31}{12}\n\t\t\t\\DrawInsnBoxCastle{11}{5}\n\t\t\t\\DrawInsnBoxCastle{4}{0}\n\t\t\\end{scope}\n\t\t\\DrawInsnBoxRel{31}{0}{}\n\t\t\\draw(33,.5) node[text width = 10, text height = 1, right]{imm\\_s};\n\n\t\t\\begin{scope}[shift={(0,0)}]\\DrawBitstringX{aaaaaaaaaaaaaaaaaaaaabcdefguvwxy}\\end{scope}\n\n\t\t\\begin{scope}[shift={(0,0)}]\\DrawHexMarkersRel{32}\\end{scope}\n\n\t\t\\InsnBoxFieldWidthArrow{31}{12}\n\t\t\\InsnBoxFieldWidthArrow{11}{5}\n\t\t\\InsnBoxFieldWidthArrow{4}{0}\n\t\\end{scope}\n}\n\n\\newcommand\\DrawInsnOpSTypeDecoding{\n\t\\BeginTikzPicture\n\t\\InsnOpSTypeDecoding\n\t\\EndTikzPicture\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\newcommand\\InsnOpITypeDecoding{\n\n\t\\begin{scope}[shift={(0,-1.5)}]\n\n\t\\DrawInsnTypeI{abcdefghijkl00011000001110000011}\n\n\t\\pgfmathsetmacro\\ArrowNorth{\\BitBoxArrowTailInset}\n\t\\pgfmathsetmacro\\ArrowSouth{\\BitBoxArrowHeadInset}\n\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](1,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](2,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](3,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](4,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](5,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](6,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](7,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](8,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](9,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](10,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](11,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](12,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](13,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](14,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](15,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](16,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](17,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](18,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](19,\\ArrowSouth);\t% sign extend\n\t\\draw[red,->](1,\\ArrowNorth)to[out=270,in=90](20,\\ArrowSouth);\t% sign extend\n\n\t\\draw[blue,->](1,\\ArrowNorth)to[out=270,in=90](21,\\ArrowSouth);\t\t% 11\n\t\\draw[blue,->](2,\\ArrowNorth)to[out=270,in=90](22,\\ArrowSouth);\t\t% 10\n\t\\draw[blue,->](3,\\ArrowNorth)to[out=270,in=90](23,\\ArrowSouth);\t\t% 9\n\t\\draw[blue,->](4,\\ArrowNorth)to[out=270,in=90](24,\\ArrowSouth);\t\t% 8\n\t\\draw[blue,->](5,\\ArrowNorth)to[out=270,in=90](25,\\ArrowSouth);\t\t% 7\n\t\\draw[blue,->](6,\\ArrowNorth)to[out=270,in=90](26,\\ArrowSouth);\t\t% 6\n\t\\draw[blue,->](7,\\ArrowNorth)to[out=270,in=90](27,\\ArrowSouth);\t\t% 5\n\t\\draw[blue,->](8,\\ArrowNorth)to[out=270,in=90](28,\\ArrowSouth);\t\t% 4\n\t\\draw[blue,->](9,\\ArrowNorth)to[out=270,in=90](29,\\ArrowSouth);\t\t% 3\n\t\\draw[blue,->](10,\\ArrowNorth)to[out=270,in=90](30,\\ArrowSouth);\t% 2\n\t\\draw[blue,->](11,\\ArrowNorth)to[out=270,in=90](31,\\ArrowSouth);\t% 1\n\t\\draw[blue,->](12,\\ArrowNorth)to[out=270,in=90](32,\\ArrowSouth);\t% 0\n\n\t\\begin{scope}[shift={(0,0)}]\\DrawHexMarkersRel{32}\\end{scope}\n\t\\end{scope}\n\n\t\\begin{scope}[shift={(0,-19.75)}]\n\t\t\\begin{scope}[shift={(0,1.5)}]\n\t\t\t\\DrawInsnBoxCastle{31}{12}\n\t\t\t\\DrawInsnBoxCastle{11}{0}\n\t\t\\end{scope}\n\t\t\\DrawInsnBoxRel{31}{0}{}\n\t\t\\draw(33,.5) node[text width = 10, text height = 1, right]{imm\\_i};\n\n\t\t\\begin{scope}[shift={(0,0)}]\\DrawBitstringX{aaaaaaaaaaaaaaaaaaaaabcdefghijkl}\\end{scope}\n\n\t\t\\begin{scope}[shift={(0,0)}]\\DrawHexMarkersRel{32}\\end{scope}\n\n\t\t\\InsnBoxFieldWidthArrow{31}{12}\n\t\t\\InsnBoxFieldWidthArrow{11}{0}\n\t\\end{scope}\n}\n\n\\newcommand\\DrawInsnOpITypeDecoding{\n\t\\BeginTikzPicture\n\t\\InsnOpITypeDecoding\n\t\\EndTikzPicture\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\newcommand\\InsnOpIShiftTypeDecoding{\n\n\t\\begin{scope}[shift={(0,-1.5)}]\n\n\t\\DrawInsnTypeI{0b00000hijkl00011000001110000011}\n\n\t\\pgfmathsetmacro\\ArrowNorth{\\BitBoxArrowTailInset}\n\t\\pgfmathsetmacro\\ArrowSouth{\\BitBoxArrowHeadInset}\n\t\\pgfmathsetmacro\\ZeroNodeY{\\ArrowSouth+4}\n\t\\pgfmathsetmacro\\ZeroNodeX{1}\n\n%\t\\node at (\\ZeroNodeX,\\ZeroNodeY) {0};\n%\t\\draw[red,->](\\ZeroNodeX+.5,\\ZeroNodeY)to[out=0,in=90](1,\\ArrowSouth);\t\n%\t\\draw[red,->](\\ZeroNodeX+.5,\\ZeroNodeY)to[out=0,in=90](2,\\ArrowSouth);\t\n%\t\\draw[red,->](\\ZeroNodeX+.5,\\ZeroNodeY)to[out=0,in=90](3,\\ArrowSouth);\t\n%\t\\draw[red,->](\\ZeroNodeX+.5,\\ZeroNodeY)to[out=0,in=110](4,\\ArrowSouth);\t\n%\t\\draw[red,->](\\ZeroNodeX+.5,\\ZeroNodeY)to[out=0,in=110](5,\\ArrowSouth);\t\n%\t\\draw[red,->](\\ZeroNodeX+.5,\\ZeroNodeY)to[out=0,in=110](6,\\ArrowSouth);\t\n%\t\\draw[red,->](\\ZeroNodeX+.5,\\ZeroNodeY)to[out=0,in=110](7,\\ArrowSouth);\t\n%\t\\draw[red,->](\\ZeroNodeX+.5,\\ZeroNodeY)to[out=0,in=110](8,\\ArrowSouth);\t\n%\t\\draw[red,->](\\ZeroNodeX+.5,\\ZeroNodeY)to[out=0,in=110](9,\\ArrowSouth);\t\n%\t\\draw[red,->](\\ZeroNodeX+.5,\\ZeroNodeY)to[out=0,in=110](10,\\ArrowSouth);\t\n%\t\\draw[red,->](\\ZeroNodeX+.5,\\ZeroNodeY)to[out=0,in=110](11,\\ArrowSouth);\t\n%\t\\draw[red,->](\\ZeroNodeX+.5,\\ZeroNodeY)to[out=0,in=110](12,\\ArrowSouth);\t\n%\t\\draw[red,->](\\ZeroNodeX+.5,\\ZeroNodeY)to[out=0,in=110](13,\\ArrowSouth);\t\n%\t\\draw[red,->](\\ZeroNodeX+.5,\\ZeroNodeY)to[out=0,in=110](14,\\ArrowSouth);\t\n%\t\\draw[red,->](\\ZeroNodeX+.5,\\ZeroNodeY)to[out=0,in=110](15,\\ArrowSouth);\t\n%\t\\draw[red,->](\\ZeroNodeX+.5,\\ZeroNodeY)to[out=0,in=110](16,\\ArrowSouth);\t\n%\t\\draw[red,->](\\ZeroNodeX+.5,\\ZeroNodeY)to[out=0,in=110](17,\\ArrowSouth);\t\n%\t\\draw[red,->](\\ZeroNodeX+.5,\\ZeroNodeY)to[out=0,in=110](18,\\ArrowSouth);\t\n%\t\\draw[red,->](\\ZeroNodeX+.5,\\ZeroNodeY)to[out=0,in=110](19,\\ArrowSouth);\t\n%\t\\draw[red,->](\\ZeroNodeX+.5,\\ZeroNodeY)to[out=0,in=110](20,\\ArrowSouth);\t\n%\t\\draw[red,->](\\ZeroNodeX+.5,\\ZeroNodeY)to[out=0,in=110](21,\\ArrowSouth);\t\n%\t\\draw[red,->](\\ZeroNodeX+.5,\\ZeroNodeY)to[out=0,in=110](22,\\ArrowSouth);\t\n%\t\\draw[red,->](\\ZeroNodeX+.5,\\ZeroNodeY)to[out=0,in=110](23,\\ArrowSouth);\t\n%\t\\draw[red,->](\\ZeroNodeX+.5,\\ZeroNodeY)to[out=0,in=110](24,\\ArrowSouth);\t\n%\t\\draw[red,->](\\ZeroNodeX+.5,\\ZeroNodeY)to[out=0,in=110](25,\\ArrowSouth);\t\n%\t\\draw[red,->](\\ZeroNodeX+.5,\\ZeroNodeY)to[out=0,in=110](26,\\ArrowSouth);\t\n%\t\\draw[red,->](\\ZeroNodeX+.5,\\ZeroNodeY)to[out=0,in=110](27,\\ArrowSouth);\t\n\n\t\\draw[blue,->](8,\\ArrowNorth)to[out=270,in=90](28-8,\\ArrowSouth);\t\t% 4\n\t\\draw[blue,->](9,\\ArrowNorth)to[out=270,in=90](29-8,\\ArrowSouth);\t\t% 3\n\t\\draw[blue,->](10,\\ArrowNorth)to[out=270,in=90](30-8,\\ArrowSouth);\t% 2\n\t\\draw[blue,->](11,\\ArrowNorth)to[out=270,in=90](31-8,\\ArrowSouth);\t% 1\n\t\\draw[blue,->](12,\\ArrowNorth)to[out=270,in=90](32-8,\\ArrowSouth);\t% 0\n\n\t\\draw[blue,->](2,\\ArrowNorth)to[out=270,in=90](8,\\ArrowSouth);\t\t% diff btw logical/arith\n\n\t\\begin{scope}[shift={(0,0)}]\\DrawHexMarkersRel{32}\\end{scope}\n\t\\end{scope}\n\n\t% shamt_i box\n\t\\begin{scope}[shift={(-8,-19.75)}]\n\t\t\\begin{scope}[shift={(0,1.5)}]\n\t\t\t\\DrawInsnBoxCastle{4}{0}\n\t\t\\end{scope}\n\t\t\\DrawInsnBoxRel{4}{0}{}\n\t\t\\draw(33,.5) node[text width = 10, text height = 1, right]{shamt\\_i};\n\n\t\t\\begin{scope}[shift={(27,0)}]\\DrawBitstringX{hijkl}\\end{scope}\n\n\t\t%\\begin{scope}[shift={(24,0)}]\\DrawHexMarkersRel{0}\\end{scope}\n\t\t\\begin{scope}[shift={(28,0)}]\\TheHexMark{0}\\end{scope}\n\n\t\t\\InsnBoxFieldWidthArrow{4}{0}\n\t\\end{scope}\n\n\t% logical/arith box -- this demonstrates the lack of sane coordinate standards in this file :-/ \n\t\\begin{scope}[shift={(-24,-19.75)}]\n\t\t\\begin{scope}[shift={(0,1.5)}]\n\t\t\t\\DrawInsnBoxCastle{0}{0}\n\t\t\\end{scope}\n\t\t\\DrawInsnBoxRel{0}{0}{}\n\t\t\\draw(33,.5) node[text width = 10, text height = 1, right]{srai/srli};\n\n\t\t\\begin{scope}[shift={(31,0)}]\\DrawBitstringX{b}\\end{scope}\n\n\t\t\\InsnBoxFieldWidthArrow{0}{0}\n\t\\end{scope}\n}\n\n\\newcommand\\DrawInsnOpIShiftTypeDecoding{\n\t\\BeginTikzPicture\n\t\\InsnOpIShiftTypeDecoding\n\t\\EndTikzPicture\n}\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\newcommand\\InsnOpUTypeDecoding{\n\n\t\\begin{scope}[shift={(0,-1.5)}]\n\t\\DrawInsnTypeU{abcdefghijklmnopqrst001010110111}\n\n\t\\pgfmathsetmacro\\ArrowNorth{\\BitBoxArrowTailInset}\n\t\\pgfmathsetmacro\\ArrowSouth{\\BitBoxArrowHeadInset}\n\n\t\\draw[blue,->](1,\\ArrowNorth)to[out=270,in=90](1,\\ArrowSouth);\t\t% \n\t\\draw[blue,->](2,\\ArrowNorth)to[out=270,in=90](2,\\ArrowSouth);\t\t% \n\t\\draw[blue,->](3,\\ArrowNorth)to[out=270,in=90](3,\\ArrowSouth);\t\t% \n\t\\draw[blue,->](4,\\ArrowNorth)to[out=270,in=90](4,\\ArrowSouth);\t\t% \n\t\\draw[blue,->](5,\\ArrowNorth)to[out=270,in=90](5,\\ArrowSouth);\t\t% \n\t\\draw[blue,->](6,\\ArrowNorth)to[out=270,in=90](6,\\ArrowSouth);\t\t% \n\t\\draw[blue,->](7,\\ArrowNorth)to[out=270,in=90](7,\\ArrowSouth);\t\t% \n\t\\draw[blue,->](8,\\ArrowNorth)to[out=270,in=90](8,\\ArrowSouth);\t\t% \n\t\\draw[blue,->](9,\\ArrowNorth)to[out=270,in=90](9,\\ArrowSouth);\t\t% \n\t\\draw[blue,->](10,\\ArrowNorth)to[out=270,in=90](10,\\ArrowSouth);\t% \n\t\\draw[blue,->](11,\\ArrowNorth)to[out=270,in=90](11,\\ArrowSouth);\t% \n\t\\draw[blue,->](12,\\ArrowNorth)to[out=270,in=90](12,\\ArrowSouth);\t% \n\t\\draw[blue,->](13,\\ArrowNorth)to[out=270,in=90](13,\\ArrowSouth);\t% \n\t\\draw[blue,->](14,\\ArrowNorth)to[out=270,in=90](14,\\ArrowSouth);\t% \n\t\\draw[blue,->](15,\\ArrowNorth)to[out=270,in=90](15,\\ArrowSouth);\t% \n\t\\draw[blue,->](16,\\ArrowNorth)to[out=270,in=90](16,\\ArrowSouth);\t% \n\t\\draw[blue,->](17,\\ArrowNorth)to[out=270,in=90](17,\\ArrowSouth);\t% \n\t\\draw[blue,->](18,\\ArrowNorth)to[out=270,in=90](18,\\ArrowSouth);\t% \n\t\\draw[blue,->](19,\\ArrowNorth)to[out=270,in=90](19,\\ArrowSouth);\t% \n\t\\draw[blue,->](20,\\ArrowNorth)to[out=270,in=90](20,\\ArrowSouth);\t% \n\n\t\\draw[red,->](34,\\ArrowSouth+5)to[out=180,in=90](21,\\ArrowSouth);\t% \n\t\\draw[red,->](34,\\ArrowSouth+5)to[out=180,in=90](22,\\ArrowSouth);\t% \n\t\\draw[red,->](34,\\ArrowSouth+5)to[out=180,in=90](23,\\ArrowSouth);\t% \n\t\\draw[red,->](34,\\ArrowSouth+5)to[out=180,in=90](24,\\ArrowSouth);\t% \n\t\\draw[red,->](34,\\ArrowSouth+5)to[out=180,in=90](25,\\ArrowSouth);\t% \n\t\\draw[red,->](34,\\ArrowSouth+5)to[out=180,in=90](26,\\ArrowSouth);\t% \n\t\\draw[red,->](34,\\ArrowSouth+5)to[out=180,in=90](27,\\ArrowSouth);\t% \n\t\\draw[red,->](34,\\ArrowSouth+5)to[out=180,in=90](28,\\ArrowSouth);\t% \n\t\\draw[red,->](34,\\ArrowSouth+5)to[out=180,in=90](29,\\ArrowSouth);\t% \n\t\\draw[red,->](34,\\ArrowSouth+5)to[out=180,in=90](30,\\ArrowSouth);\t% \n\t\\draw[red,->](34,\\ArrowSouth+5)to[out=180,in=90](31,\\ArrowSouth);\t% \n\t\\draw[red,->](34,\\ArrowSouth+5)to[out=180,in=90](32,\\ArrowSouth);\t% 0 (special case)\n\t\\node at (34.5,\\ArrowSouth+5) {0};\n\n\t\\begin{scope}[shift={(0,0)}]\\DrawHexMarkersRel{32}\\end{scope}\n\t\\end{scope}\n\n\t\\begin{scope}[shift={(0,-19.75)}]\n\t\t\\begin{scope}[shift={(0,1.5)}]\n\t\t\t\\DrawInsnBoxCastle{31}{12}\n\t\t\t\\DrawInsnBoxCastle{11}{0}\n\t\t\\end{scope}\n\t\t\\DrawInsnBoxRel{31}{0}{}\n\t\t\\draw(33,.5) node[text width = 10, text height = 1, right]{imm\\_u};\n\n\t\t\\begin{scope}[shift={(0,0)}]\\DrawBitstringX{abcdefghijklmnopqrst000000000000}\\end{scope}\n\n\t\t\\begin{scope}[shift={(0,0)}]\\DrawHexMarkersRel{32}\\end{scope}\n\n\t\t\\InsnBoxFieldWidthArrow{31}{12}\n\t\t\\InsnBoxFieldWidthArrow{11}{0}\n\t\\end{scope}\n}\n\\newcommand\\DrawInsnOpUTypeDecoding{\n\t\\BeginTikzPicture\n\t\\InsnOpUTypeDecoding\n\t\\EndTikzPicture\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% Draw something useful for the cover portion of the tri-fold green-card\n\\newcommand\\DrawCardTitlePage{\n\t\\draw[line width=1.5mm] (111-18,-1) -- (111+18,-1);\n\t\\draw(111,-5) node {\\textbf{\\Huge RVALP}};\n\t\\draw(111,-10) node {\\textbf{\\Huge RV32I Reference Card}};\n\t\\draw[line width=1.5mm] (111-18,-14) -- (111+18,-14);\n\t\\draw(111,-150) node {https://github.com/johnwinans/rvalp};\n\t\\draw(111,-152) node {\\small \\GitRevision};\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% Draw all the ribbons in a stack for a reference card\n\\newcommand\\DrawInsnRibbons{\n\t\\BeginTikzPicture\n\t\\begin{scope}[yscale=.75]\n\t\t\\begin{scope}[shift={(0,0)}]\\InsnOpUTypeDecoding\\end{scope}\n\t\t\\begin{scope}[shift={(0,-25)}]\\InsnOpITypeDecoding\\end{scope}\n\t\t\\begin{scope}[shift={(0,-50)}]\\InsnOpIShiftTypeDecoding\\end{scope}\n\t\t\\begin{scope}[shift={(0,-75)}]\\InsnOpSTypeDecoding\\end{scope}\n\t\t\\begin{scope}[shift={(0,-100)}]\\InsnOpBTypeDecoding\\end{scope}\n\t\t\\begin{scope}[shift={(0,-125)}]\\InsnOpJTypeDecoding\\end{scope}\n\t\t\\begin{scope}[shift={(0,-150)}]\\InsnOpRTypeDecoding\\end{scope}\n\n\t\t\\begin{scope}[shift={(0,0)}]\\DrawCardTitlePage\\end{scope}\n\t\\end{scope}\n\t\\EndTikzPicture\n}\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\n\n% print a register name in typewriter font\n\\newcommand\\reg[1]{{\\tt #1}}\n\n% print an instruction name in typewriter font\n\\newcommand\\insn[1]{{\\tt #1}}\n\n\\newcommand\\rvddt{{\\tt rvddt}}\n\n\\newcommand\\hex[1]{{\\tt 0x#1}}\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% IEEE-754 Floating Point Number\n%\n% #1 sign\n% #2 exponent\n% #3 significand\n\\newcommand\\DrawIEEEFloat[1]{\n\t\\StrLen{#1}[\\numchars]\n\t\\begin{scope}[shift={(0,.75)}]\n\t\\DrawInsnBitstring{\\numchars}{#1}{}\n \\DrawInsnBoxSeg{\\numchars}{31}{31}{sign}\n \\DrawInsnBoxSeg{\\numchars}{30}{23}{exponent}\n \\DrawInsnBoxSeg{\\numchars}{22}{0}{significand}\n \\draw {[rounded corners=\\SignBoxCornerRadius] (1.35, -.6) -- (1.35, .6) -- (.65, .6) -- (.65, -.6) -- cycle}; % sign bit\n\t\\end{scope}\n\n\t\\DrawHexMarkersRel{\\numchars}\n}\n\n\\newcommand\\DrawBitBoxIEEEFloat[1]{\n\t\\BeginTikzPicture\n\t\\begin{scope}[shift={(0,0)}]\\DrawIEEEFloat{#1}\\end{scope}\n\t\\EndTikzPicture\n}\n\n\n\n%\n%\\newcommand\\DrawInsnTypeB[1]{\n% \\StrLen{#1}[\\numchars]\n% \\begin{scope}[shift={(0,.75)}]\n% \\DrawInsnBitstring{\\numchars}{#1}{\\hyperref[insnformat:btype]{B-type}}\n% \\DrawInsnBoxSeg{\\numchars}{31}{25}{imm[12\\textbar10:5]}\n% \\DrawInsnBoxSeg{\\numchars}{24}{20}{rs2}\n% \\DrawInsnBoxSeg{\\numchars}{19}{15}{rs1}\n% \\DrawInsnBoxSeg{\\numchars}{14}{12}{funct3}\n% \\DrawInsnBoxSeg{\\numchars}{11}{7}{imm[4:1\\textbar11]}\n% \\DrawInsnBoxSeg{\\numchars}{6}{0}{opcode}\n%\n% % add some hint bits in for imm fields\n% \\draw {[rounded corners=\\SignBoxCornerRadius] (1.35, -.6) -- (1.35, .6) -- (.65, .6) -- (.65, -.6) -- cycle}; % sign bit\n% \\draw (32-7-.5, -.75) -- (32-7-.5, .1); % imm[11]\n% \\draw (32-30-.5, -.75) -- (32-30.5, .1); % imm[12]\n%\n% \\end{scope}\n%\n% \\DrawHexMarkersRel{\\numchars}\n%}\n" }, { "path": "book/insnsummary/chapter.tex", "content": "\\chapter{Instruction Set Summary}\n\n\\enote{Once the RV32I section is re-factored, it may end up turning into this.}\n\n\\TDrawInsnTypeUPicture\n{Load Upper Immediate}\n{lui rd, imm}\n{lui t0, 3}\n{\\tt%\nrd $\\leftarrow$ pc + sx(imm<<1)\\\\\npc $\\leftarrow$ pc + 4}\n{00000000000000000011001010110111}\n\n\\TDrawInsnTypeUPicture\n{Add Upper Immediate PC}\n{auipc rd, imm}\n{auipc t0, 3}\n{\\tt%\nrd $\\leftarrow$ pc + zr(imm)\\\\\npc $\\leftarrow$ pc + 4}\n{000000000000000000110010101xxxxx}\n\n\\TDrawInsnTypeJPicture\n{Jump And Link}\n{jal rd, imm}\n{jal x7, .+16}\n{\\tt%\nrd $\\leftarrow$ pc + 4\\\\\npc $\\leftarrow$ pc + sx(imm<<1)}\n{00000001000000000000001111101111}\n\n\\TDrawInsnTypeIPicture\n{Jump And Link Register}\n{jalr rd, rs1, imm}\n{jalr x1, x7, 4}\n{\\tt%\nrd $\\leftarrow$ pc + 4\\\\\npc $\\leftarrow$ (rs1 + sx(imm)) \\& \\textasciitilde{}1}\n{00000000010000111000000011100111}\n\n\\enote{These branches (and likely other insns) are not encoded properly!}\n\\TDrawInsnTypeBPicture\n{Branch Equal}\n{beq rs1, rs2, imm}\n{beq x3, x15, 2064}\n{\\tt pc $\\leftarrow$ (rs1==rs2) ? pc+sx(imm[12:1]<<1) : pc+4}\n{00000000111100011000100011100011}\n\n\\TDrawInsnTypeBPicture\n{Branch Not Equal}\n{bne rs1, rs2, imm}\n{bne x3, x15, 2064}\n{\\tt pc $\\leftarrow$ (rs1!=rs2) ? pc+sx(imm[12:1]<<1) : pc+4}\n{00000000111100011001100011100011}\n\n\\TDrawInsnTypeBPicture\n{Branch Less Than}\n{blt rs1, rs2, imm}\n{blt x3, x15, 2064}\n{\\tt pc $\\leftarrow$ (rs1=rs2) ? pc+sx(imm[12:1]<<1) : pc+4}\n{00000000111100011101100011100011}\n\n\\TDrawInsnTypeBPicture\n{Branch Less Than Unsigned}\n{bltu rs1, rs2, imm}\n{bltu x3, x15, 2064}\n{\\tt pc $\\leftarrow$ (rs1=rs2) ? pc+sx(imm[12:1]<<1) : pc+4}\n{00000000111100011111100011100011}\n\n\\TDrawInsnTypeIPicture\n{Load Byte}\n{lb rd, imm(rs1)}\n{lb x7, 4(x3)}\n{\\tt%\nrd $\\leftarrow$ sx(m8(rs1+sx(imm)))\\\\\npc $\\leftarrow$ pc+4}\n{00000000010000011000001110000011}\n\n\\TDrawInsnTypeIPicture\n{Load Halfword}\n{lh rd, imm(rs1)}\n{lh x7, 4(x3)}\n{\\tt%\nrd $\\leftarrow$ sx(m16(rs1+sx(imm)))\\\\\npc $\\leftarrow$ pc+4}\n{00000000010000011001001110000011}\n\n\\TDrawInsnTypeIPicture\n{Load Word}\n{lw rd, imm(rs1)}\n{lw x7, 4(x3)}\n{\\tt%\nrd $\\leftarrow$ sx(m32(rs1+sx(imm)))\\\\\npc $\\leftarrow$ pc+4}\n{00000000010000011010001110000011}\n\n\\TDrawInsnTypeIPicture\n{Load Byte Unsigned}\n{lbu rd, imm(rs1)}\n{lbu x7, 4(x3)}\n{\\tt%\nrd $\\leftarrow$ zx(m8(rs1+sx(imm)))\\\\\npc $\\leftarrow$ pc+4}\n{00000000010000011100001110000011}\n\n\\TDrawInsnTypeIPicture\n{Load Halfword Unsigned}\n{lhu rd, imm(rs1)}\n{lhu x7, 4(x3)}\n{\\tt%\nrd $\\leftarrow$ zx(m16(rs1+sx(imm)))\\\\\npc $\\leftarrow$ pc+4}\n{00000000010000011101001110000011}\n\n\\TDrawInsnTypeSPicture\n{Store Byte}\n{sb rs2, imm(rs1)}\n{sb x3, 19(x15)}\n{\\tt%\nm8(rs1+sx(imm)) $\\leftarrow$ rs2[7:0]\\\\\npc $\\leftarrow$ pc+4}\n{00000000111100011000100110100011}\n\n\\TDrawInsnTypeSPicture\n{Store Halfword}\n{sh rs2, imm(rs1)}\n{sh x3, 19(x15)}\n{\\tt%\nm16(rs1+sx(imm)) $\\leftarrow$ rs2[15:0]\\\\\npc $\\leftarrow$ pc+4}\n{00000000111100011001100110100011}\n\n\\TDrawInsnTypeSPicture\n{Store Word}\n{sw rs2, imm(rs1)}\n{sw x3, 19(x15)}\n{\\tt%\nm16(rs1+sx(imm)) $\\leftarrow$ rs2[31:0]\\\\\npc $\\leftarrow$ pc+4}\n{00000000111100011010100110100011}\n\n\\TDrawInsnTypeIPicture\n{Add Immediate}\n{addi rd, rs1, imm}\n{addi x1, x7, 4}\n{\\tt%\nrd $\\leftarrow$ rs1+sx(imm)\\\\\npc $\\leftarrow$ pc+4}\n{00000000010000111000000010010011}\n\n\\TDrawInsnTypeIPicture\n{Set Less Than Immediate}\n{slti rd, rs1, imm}\n{slti x1, x7, 4}\n{\\tt%\nrd $\\leftarrow$ (rs1 < sx(imm)) ? 1 : 0\\\\\npc $\\leftarrow$ pc+4}\n{00000000010000111010000010010011}\n\n\\TDrawInsnTypeIPicture\n{Set Less Than Immediate Unsigned}\n{sltiu rd, rs1, imm}\n{sltiu x1, x7, 4}\n{\\tt%\nrd $\\leftarrow$ (rs1 < sx(imm)) ? 1 : 0\\\\\npc $\\leftarrow$ pc+4}\n{00000000010000111011000010010011}\n\n\\TDrawInsnTypeIPicture\n{Exclusive Or Immediate}\n{xori rd, rs1, imm}\n{xori x1, x7, 4}\n{\\tt%\nrd $\\leftarrow$ rs1 \\^{} sx(imm)\\\\\npc $\\leftarrow$ pc+4}\n{00000000010000111100000010010011}\n\n\\TDrawInsnTypeIPicture\n{Or Immediate}\n{ori rd, rs1, imm}\n{ori x1, x7, 4}\n{\\tt%\nrd $\\leftarrow$ rs1 | sx(imm)\\\\\npc $\\leftarrow$ pc+4}\n{00000000010000111110000010010011}\n\n\\TDrawInsnTypeIPicture\n{And Immediate}\n{andi rd, rs1, imm}\n{andi x1, x7, 4}\n{\\tt%\nrd $\\leftarrow$ rs1 \\& sx(imm)\\\\\npc $\\leftarrow$ pc+4}\n{00000000010000111111000010010011}\n\n\n\\TDrawInsnTypeRShiftPicture\n{Shift Left Logical Immediate}\n{slli rd, rs1, shamt}\n{slli x7, x3, 2}\n{\\tt%\nrd $\\leftarrow$ rs1 << shamt\\\\\npc $\\leftarrow$ pc+4}\n{00000000001000011001001110100011}\n\n\n\\TDrawInsnTypeRShiftPicture\n{Shift Right Logical Immediate}\n{srli rd, rs1, shamt}\n{srli x7, x3, 2}\n{\\tt%\nrd $\\leftarrow$ rs1 >> shamt\\\\\npc $\\leftarrow$ pc+4}\n{00000000001000011101001110010011}\n\n\\TDrawInsnTypeRShiftPicture\n{Shift Right Arithmetic Immediate}\n{srai rd, rs1, shamt}\n{srai x7, x3, 2}\n{\\tt%\nrd $\\leftarrow$ rs1 >> shamt\\\\\npc $\\leftarrow$ pc+4}\n{01000000001000011101001110010011}\n\n\\TDrawInsnTypeRPicture\n{Add}\n{add rd, rs1, rs2}\n{add x7, x3, x31}\n{\\tt%\nrd $\\leftarrow$ rs1 + rs2\\\\\npc $\\leftarrow$ pc+4}\n{00000001111100011000001110110011}\n\n\\TDrawInsnTypeRPicture\n{Subtract}\n{sub rd, rs1, rs2}\n{SUB x7, x3, x31}\n{\\tt%\nrd $\\leftarrow$ rs1 - rs2\\\\\npc $\\leftarrow$ pc+4}\n{01000001111100011000001110110011}\n\n\\TDrawInsnTypeRPicture\n{Shift Left Logical}\n{sll rd, rs1, rs2}\n{sll x7, x3, x31}\n{\\tt%\nrd $\\leftarrow$ rs1 << rs2\\\\\npc $\\leftarrow$ pc+4}\n{00000001111100011001001110110011}\n\n\\TDrawInsnTypeRPicture\n{Set Less Than}\n{slt rd, rs1, rs2}\n{slt x7, x3, x31}\n{\\tt%\nrd $\\leftarrow$ rs1 < rs2) ? 1 : 0\\\\\npc $\\leftarrow$ pc+4}\n{00000001111100011010001110110011}\n\n\\TDrawInsnTypeRPicture\n{Set Less Than Unsigned}\n{sltu rd, rs1, rs2}\n{sltu x7, x3, x31}\n{\\tt%\nrd $\\leftarrow$ (rs1 < rs2) ? 1 : 0\\\\\npc $\\leftarrow$ pc+4}\n{00000001111100011011001110110011}\n\n\\TDrawInsnTypeRPicture\n{Exclusive Or}\n{xor rd, rs1, rs2}\n{xor x7, x3, x31}\n{\\tt%\nrd $\\leftarrow$ rs1 \\^{} rs2\\\\\npc $\\leftarrow$ pc+4}\n{00000001111100011100001110110011}\n\n\\TDrawInsnTypeRPicture\n{Shift Right Logical}\n{srl rd, rs1, rs2}\n{srl x7, x3, x31}\n{\\tt%\nrd $\\leftarrow$ rs1 >> rs2\\\\\npc $\\leftarrow$ pc+4}\n{00000001111100011101001110110011}\n\n\\TDrawInsnTypeRPicture\n{Shift Right Arithmetic}\n{sra rd, rs1, rs2}\n{sra x7, x3, x31}\n{\\tt%\nrd $\\leftarrow$ rs1 >> rs2\\\\\npc $\\leftarrow$ pc+4}\n{01000001111100011101001110110011}\n\n\\TDrawInsnTypeRPicture\n{Or}\n{or rd, rs1, rs2}\n{or x7, x3, x31}\n{\\tt%\nrd $\\leftarrow$ rs1 | rs2\\\\\npc $\\leftarrow$ pc+4}\n{00000001111100011101001110110011}\n\n\\TDrawInsnTypeRPicture\n{And}\n{and rd, rs1, rs2}\n{and x7, x3, x31}\n{\\tt%\nrd $\\leftarrow$ rs1 \\& rs2\\\\\npc $\\leftarrow$ pc+4}\n{00000001111100011110001110110011}\n\n%\\DrawInsnTypeFPicture{FENCE iorw, iorw}{00001111111100000000000000001111}\n%\\DrawInsnTypeFPicture{FENCE.I}{00000000000000000001000000001111}\n%\\DrawInsnTypeEPicture{ECALL}{00000000000000000000000001110011}\n%\\DrawInsnTypeEPicture{EBREAK}{00000000000100000000000001110011}\n%\\DrawInsnTypeCSPicture{CSRRW x3, 2, x15}{00000000001001111001000111110011}\n%\\DrawInsnTypeCSPicture{CSRRS x3, 2, x15}{00000000001001111010000111110011}\n%\\DrawInsnTypeCSPicture{CSRRC x3, 2, x15}{00000000001001111011000111110011}\n%\\DrawInsnTypeCSIPicture{CSRRWI x3, 2, 7}{00000000001000111101000111110011}\n%\\DrawInsnTypeCSIPicture{CSRRSI x3, 2, 7}{00000000001000111110000111110011}\n%\\DrawInsnTypeCSIPicture{CSRRCI x3, 2, 7}{00000000001000111111000111110011}\n%\\DrawInsnTypeRPicture{MUL x7, x3, x31}{00000011111100111000001110110011}\n%\\DrawInsnTypeRPicture{MULH x7, x3, x31}{00000011111100111001001110110011}\n%\\DrawInsnTypeRPicture{MULHS x7, x3, x31}{00000011111100111010001110110011}\n%\\DrawInsnTypeRPicture{MULHU x7, x3, x31}{00000011111100111011001110110011}\n%\\DrawInsnTypeRPicture{DIV x7, x3, x31}{00000011111100111100001110110011}\n%\\DrawInsnTypeRPicture{DIVU x7, x3, x31}{00000011111100111101001110110011}\n%\\DrawInsnTypeRPicture{REM x7, x3, x31}{00000011111100111110001110110011}\n%\\DrawInsnTypeRPicture{REMU x7, x3, x31}{00000011111100111111001110110011}\n" }, { "path": "book/install/chapter.tex", "content": "\\chapter{Installing a RISC-V Toolchain}\n\\label{chapter:install}\n\nAll of the software presented in this text was assembled/compiled \nusing the GNU toolchain and executed using the rvddt simulator on \na Linux (Ubuntu 20.04 LTS) operating system.\n\nThe installation instructions provided here were last tested on \non March 5, 2021.\n\nIt is expected that these tools will evolve over time. See the\nrespective documentation web sites for the latest news and options\nfor installing them.\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\section{The GNU Toolchain}\n\n\\enote{It would be good to find some Mac and Windows users to write \nand test proper variations on this section to address those systems.\nPull requests, welcome!}%\nIn order to install custom code in a location that will not cause \ninterference with other applications (and allow for easy hacking and\ncleanup), these will install the toolchain under\na private directory: \\verb@~/projects/riscv/install@. At any time\nyou can remove everything and start over by executing the following \ncommand:\n\n\\begin{tty}\nrm -rf ~/projects/riscv/install\n\\end{tty}\n\n\\begin{tcolorbox}\nBe {\\em very} careful how you type the above \\verb@rm@ command. \nIf typed incorrectly, it could irreversibly remove many of your files!\n\\end{tcolorbox}\n\nBefore building the toolchain, a number of utilities must be present on \nyour system. The following will install those that are needed:\n\n\\begin{minipage}{\\textwidth}\n\\begin{tty}\nsudo apt install autoconf automake autotools-dev curl python3 python-dev libmpc-dev \\\n libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf \\\n libtool patchutils bc zlib1g-dev libexpat-dev\n\\end{tty}\n\\end{minipage}\n\nNote that the above \\verb@apt@ command is the only operation that should\nbe performed as root. All other commands should be executed as a regular \nuser. This will eliminate the possibility of clobbering system files that \nshould not be touched when tinkering with the toolchain applications.\n\n\\enote{Discuss the choice of ilp32 as well as what the other variations \nwould do.}%\nTo download, compile and install the toolchain:\n\n\\begin{minipage}{\\textwidth}\n\\begin{tty}\nmkdir -p ~/projects/riscv\ncd ~/projects/riscv\ngit clone https://github.com/riscv/riscv-gnu-toolchain\ncd riscv-gnu-toolchain\nINS_DIR=~/projects/riscv/install/rv32i\n./configure --prefix=$INS_DIR \\\n --with-multilib-generator=\"rv32i-ilp32--;rv32imafd-ilp32--;rv32ima-ilp32--\"\nmake\n\\end{tty}\n\\end{minipage}\n\nAfter building the toolchain, make it available by putting it into\nyour PATH by adding the following to the end of your \\verb@.bashrc@ file:\n\n\\begin{tty}\nexport PATH=$PATH:$INS_DIR\n\\end{tty}\n\nFor this \\verb@PATH@ change to take place, start a new terminal or paste the\nsame \\verb@export@ command into your existing terminal.\n\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\section{rvddt}\n\nDownload and install the rvddt simulator by executing the following \ncommands.\nBuilding the rvddt example programs will verify that the GNU toolchain\nhas been built and installed properly.\n\n\\begin{minipage}{\\textwidth}\n%git clone git@github.com:johnwinans/rvddt.git\n\\begin{tty}\ncd ~/projects/riscv\ngit clone https://github.com/johnwinans/rvddt.git\ncd rvddt/src\nmake world\ncd ../examples\nmake world\n\\end{tty}\n\\end{minipage}\n\nAfter building rvddt, make it available by putting it into your PATH \nby adding the following to the end of your \\verb@.bashrc@ file:\n\n\\begin{tty}\nexport PATH=$PATH:~/projects/riscv/rvddt/src\n\\end{tty}\n\nFor this \\verb@PATH@ change to take place, start a new terminal or paste the\nsame \\verb@export@ command into your existing terminal.\n\n\nTest the rvddt build by executing one of the examples:\n\n\\begin{minipage}{\\textwidth}\n\\begin{tty}\nwinans@ux410:~/projects/riscv/rvddt/examples$ rvddt -f counter/counter.bin\nsp initialized to top of memory: 0x0000fff0\nLoading 'counter/counter.bin' to 0x0\nThis is rvddt. Enter ? for help.\nddt> ti 0 1000\n00000000: 00300293 addi x5, x0, 3 # x5 = 0x00000003 = 0x00000000 + 0x00000003\n00000004: 00000313 addi x6, x0, 0 # x6 = 0x00000000 = 0x00000000 + 0x00000000\n00000008: 00130313 addi x6, x6, 1 # x6 = 0x00000001 = 0x00000000 + 0x00000001\n0000000c: fe534ee3 blt x6, x5, -4 # pc = (0x1 < 0x3) ? 0x8 : 0x10\n00000008: 00130313 addi x6, x6, 1 # x6 = 0x00000002 = 0x00000001 + 0x00000001\n0000000c: fe534ee3 blt x6, x5, -4 # pc = (0x2 < 0x3) ? 0x8 : 0x10\n00000008: 00130313 addi x6, x6, 1 # x6 = 0x00000003 = 0x00000002 + 0x00000001\n0000000c: fe534ee3 blt x6, x5, -4 # pc = (0x3 < 0x3) ? 0x8 : 0x10\n00000010: ebreak\nddt> x\nwinans@ux410:~/projects/riscv/rvddt/examples$ \n\\end{tty}\n\\end{minipage}\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\section{qemu}\n\nYou can download and install the RV32 qemu simulator by executing \nthe following commands. \n\nAt the time of this writing (2021-06) I use release v5.0.0. \nRelease v5.2.0 has issues that confuse GDB when printing the registers \nand v6.0.0 has different CPU types that I have had trouble with when \nexecuting privileged instructions.\n\n\\begin{minipage}{\\textwidth}\n\\begin{tty}\nINS_DIR=~/projects/riscv/install/rv32i\ncd ~/projects/riscv\ngit clone git@github.com:qemu/qemu.git\ncd qemu\ngit checkout v5.0.0\n./configure --target-list=riscv32-softmmu --prefix=${INS_DIR}\nmake -j4\nmake install\n\\end{tty}\n\\end{minipage}\n\n" }, { "path": "book/intro/chapter.tex", "content": "\\chapter{Introduction}\n\\label{chapter:Introduction}\n\nAt its core, a digital computer has at least one \\acrfull{cpu}. A\nCPU executes a continuous stream of instructions called a \\gls{program}. \nThese program instructions are expressed in what is called \n\\gls{MachineLanguage}. Each machine language instruction is a \\gls{binary} value. \nIn order to provide a method to simplify the management of machine language \nprograms a symbolic mapping is provided where a \\gls{mnemonic} can be used to \nspecify each machine instruction and any of its parameters\\ldots\\ rather \nthan require that programs be expressed as a series of binary values. \nA set of mnemonics, parameters and rules for specifying their use for\nthe purpose of programming a CPU is called an {\\em Assembly Language}.\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\section{The Digital Computer}\n\nThere are different types of computers. A {\\em digital} computer is\nthe type that most people think of when they hear the word {\\em computer}.\nOther varieties of computers include {\\em analog} and {\\em quantum}.\n\nA digital computer is one that processes data represented\nusing numeric values (digits), most commonly expressed in binary\n(ones and zeros) form.\n\nThis text focuses on digital computing.\n\nA typical digital computer is composed of storage systems (memory, disc \ndrives, USB drives, etc.), a CPU (with one or more cores), input peripherals \n(a keyboard and mouse) and output peripherals (display, printer or speakers.)\n\n\\subsection{Storage Systems}\n\nComputer storage systems are used to hold the data and instructions\nfor the CPU.\n\nTypes of computer storage can be classified into two categories:\n{\\em volatile} and {\\em non-volatile}.\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsubsection{Volatile Storage}\n\\label{VolatileStorage}\n\nVolatile storage is characterized by the fact that it will lose its\ncontents (forget) any time that it is powered off.\n\n\\index{register}\nOne type of volatile storage is provided inside the CPU itself in \nsmall blocks called \\glspl{register}. These registers are used to \nhold individual data values that can be manipulated by the instructions\nthat are executed by the CPU. \n\nAnother type of volatile storage is {\\em main memory}\n(sometimes called \\acrshort{ram})\nMain memory is connected to a computer's CPU and is used to hold\nthe data and instructions that can not fit into the CPU registers.\n\nTypically, a CPU's registers can hold tens of data values while\nthe main memory can contain many billions of data values.\n\nTo keep track of the data values, each register is assigned a number and\nthe main memory is broken up into small blocks called \\gls{byte}s that \neach assigned a number called an \\gls{address} \n(an {\\em address} is often referred to as a {\\em location.}\n\nA CPU can process data in a register at a speed that can be an order \nof magnitude faster than the rate that it can process (specifically,\ntransfer data and instructions to and from) the main memory. \n\nRegister storage costs an order of magnitude more to manufacture than\nmain memory. While it is desirable to have many registers, the economics \ndictate that the vast majority of volatile computer storage be provided\nin its main memory. As a result, optimizing the copying of data between \nthe registers and main memory is a desirable trait of good programs.\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsubsection{Non-Volatile Storage}\n\nNon-volatile storage is characterized by the fact that it will {\\em NOT} \nlose its contents when it is powered off.\n\nCommon types of non-volatile storage are disc drives, \n\\acrshort{rom} flash cards and USB \ndrives. Prices can vary widely depending on size and transfer speeds.\n\nIt is typical for a computer system's non-volatile storage to operate\nmore slowly than its main memory.\n\nThis text will focus on volatile storage.\n%is not particularly concerned with non-volatile storage. \n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{CPU}\n\\index{CPU}\n\n\\enote{Add a block diagram of the CPU components described here.}\nThe \\acrshort{cpu} is a collection of registers and circuitry designed to\nmanipulate the register data and to exchange data and instructions with the \nmain memory. The instructions that are read from the main memory tell \nthe CPU to perform various mathematical and logical operations on the data \nin its registers and where to save the results of those operations.\n\n\\subsubsection{Execution Unit}\n\nThe part of a CPU that coordinates all aspects of the operations of each \ninstruction is called the {\\em execution unit.} It is what performs the transfers \nof instructions and data between the CPU and the main memory and tells the \nregisters when they are supposed to either store or recall data being transferred. \nThe execution unit also controls the ALU (Arithmetic and Logic Unit).\n\n\\subsubsection{Arithmetic and Logic Unit}\n\\index{ALU}\n\nWhen an instruction manipulates data by performing things like an {\\em addition},\n{\\em subtraction}, {\\em comparison} or other similar operations , the ALU is what\nwill calculate the sum, difference, and so on\\ldots\\ under the control of the \nexecution unit.\n\n\n\n\\subsubsection{Registers}\n\\index{register}\n\nIn the RV32 CPU there are 31 general purpose registers that each contain 32 \\gls{bit}s \n(where each bit is one \\gls{binary} digit value of one or zero) and a number \nof special-purpose registers.\nEach of the general purpose registers is given a name such as \\reg{x1}, \\reg{x2},\n\\ldots\\ on up to \\reg{x31} ({\\em general purpose} refers to the fact that the \n{\\em CPU itself} does not prescribe any particular function to any of these registers.)\nTwo important special-purpose registers are \\reg{x0} and \\reg{pc}.\n\nRegister \\reg{x0} will always represent the value zero or logical {\\em false} \nno matter what. If any instruction tries to change the value in \\reg{x0} the \noperation will fail. The need for {\\em zero} is so common that, other than the \nfact that it is hard-wired to zero, the \\reg{x0} register is made available as \nif it were otherwise a general purpose register.%\n\\footnote{Having a special \n{\\em zero} register allows the total set of instructions that the CPU can execute \nto be simplified. Thus reducing its complexity, power consumption and cost.} \n\nThe \\reg{pc} register is called the {\\em program counter}. The CPU uses it to\nremember the memory address where its program instructions are located.\n\nThe term XLEN refer to the width of an integer register in bits (either 32, 64, or 128.)\nThe number of bits in each register is defined by the \\acrfull{isa}.\n\n\\subsubsection{Harts}\n\\index{hart}\n\nAnalogous to a {\\em core} in other types of CPUs, a {\\em \\acrshort{hart}} \n(hardware \\gls{thread}) in a RISC-V CPU refers to the collection of 32 registers,\ninstruction execution unit and ALU.\\cite[p.~20]{rvismv1v22:2017}\n\nWhen more than one hart is present in a CPU, a different stream of instructions can \nbe executed on each hart all at the same time.\nPrograms that are written to take advantage of this are called {\\em multithreaded}.\n\nThis text will primarily focus on CPUs that have only one hart.\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{Peripherals}\n\nA {\\em peripheral} is a device that is not a CPU or main memory. They are \ntypically used to transfer information/data into and out of the \nmain memory.\n\nThis text is not concerned with the peripherals of a computer\nsystem other than in sections where instructions are discussed with the\npurpose of addressing the needs of a peripheral device. Such\ninstructions are used to initiate, execute and/or synchronize data transfers.\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\section{Instruction Set Architecture}\n\\index{ISA}\n\nThe catalog of rules that describes the details of the instructions \nand features that a given CPU provides is called an \\acrfull{isa}.\n\nAn ISA is typically expressed in terms of the specific meaning of\neach binary instruction that a CPU can recognize and how it will\nprocess each one.\n\nThe RISC-V ISA is defined as a set of modules. The purpose of\ndividing the ISA into modules is to allow an implementer to select which \nfeatures to incorporate into a CPU design.\\cite[p.~4]{rvismv1v22:2017}\n\nAny given RISC-V implementation must provide one of the {\\em base}\nmodules and zero or more of the {\\em extension} modules.\\cite[p.~4]{rvismv1v22:2017}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{RV Base Modules}\n\\index{RV32I}\n\nThe base modules are RV32I (32-bit general purpose), \nRV32E (32-bit embedded), RV64I (64-bit general purpose) \nand RV128I (128-bit general purpose).\\cite[p.~4]{rvismv1v22:2017}\n\nThese base modules provide the minimal functional set of integer operations\nneeded to execute a useful application. The differing bit-widths address\nthe needs of different main-memory sizes.\n\nThis text primarily focuses on the RV32I base module and how to program it.\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{Extension Modules}\n\nRISC-V extension modules may be included by an implementer interested\nin optimizing a design for one or more purposes.\\cite[p.~4]{rvismv1v22:2017}\n\n\\index{RV32M}%\n\\index{RV32A}%\n\\index{RV32F}%\n\\index{RV32D}%\n\\index{RV32Q}%\n\\index{RV32C}%\nAvailable extension modules include M (integer math), A (atomic),\nF (32-bit floating point), D (64-bit floating point), \nQ (128-bit floating point), C (compressed size instructions) and others.\n\n\\index{RV32G}%\nThe extension name {\\em G} is used to represent the combined set of IMAFD\nextensions as it is expected to be a common combination.\n\n\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\section{How the CPU Executes a Program}\n\nThe process of executing a program is continuous repeats of a series of\n\\index{instruction cycle}{\\em instruction cycles} that are each comprised\nof a {\\em fetch}, {\\em decode} and {\\em execute} phase.\n \nThe current status of a CPU hart is entirely embodied in the data values that\nare stored in its registers at any moment in time. Of particular interest\nto an executing program is the \\reg{pc} register. The \\reg{pc} contains\nthe memory address containing the instruction that the CPU is currently \nexecuting.\\footnote{In the RISC-V ISA the \\reg{pc} register points to the \n{\\em current} instruction where in most other designs, the \\reg{pc}\nregister points to the {\\em next} instruction.}\n\nFor this to work, the instructions to be executed must have been previously \nstored in adjacent main memory locations and the address of the first instruction \nplaced into the \\reg{pc} register.\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{Instruction Fetch}\n\\index{instruction fetch}\n\nIn order to {\\em fetch} an instruction from the main memory the CPU\nwill update the address in the \\reg{pc} register and then request that\nthe main memory return the value of the data stored at that address.\n\\footnote{RV32I instructions are more than one byte in size, but \nthis general description is suitable for now.}\n\n%must have a method to identify which instruction should be fetched and\n%a method to fetch it. \n\n%Given that the main memory is broken up and that each of its bytes is \n%assigned an address, the \\reg{pc} is used to hold the address of the\n%location where the next instruction to execute is located.\n\n%Given an instruction address, the CPU can request that the main memory \n%locate and return the value of the data stored there using what is called \n%a {\\em memory read} operation and then the CPU can treat that {\\em fetched}\n%value as an instruction and execute it.\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{Instruction Decode}\n\\index{instruction decode}\n\nOnce an instruction has been fetched, it must be inspected to determine what\noperation(s) are to be performed. This means inspecting the portions of the \ninstruction that dictate which registers are involved and what that, if \nanything, ALU should do.\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{Instruction Execute}\n\\index{instruction execute}\n\nTypical instructions do things like add a number to the value\ncurrently stored in one of the registers or store the contents of a\nregister into the main memory at some given address.\n\nPart of every instruction is a notion of what should be done next.\n\nMost of the time an instruction will complete by indicating that\nthe CPU should proceed to fetch and execute the instruction at the next\nlarger main memory address. In these cases the \\reg{pc} is incremented\nto point to the memory address after the current instruction.\n\nAny parameters that an instruction requires must either be part of \nthe instruction itself or read from (or stored into) one or more of the \ngeneral purpose registers.\n\nSome instructions can specify that the CPU proceed to execute an\ninstruction at an address other than the one that follows itself.\nThis class of instructions have names like {\\em jump} and {\\em branch}\nand are available in a variety of different styles.\n\nThe RISC-V ISA uses the word {\\em jump} to refer to an {\\em unconditional}\nchange in the sequential processing of instructions and the word\n{\\em branch} to refer to a {\\em conditional} change.\n\nConditional branch instructions can be used to tell the CPU to \ndo things like:\n\n\\begin{quote}\nIf the value in x8 is currently less than the value in x24 then\nproceed to the instruction at the next main memory address, otherwise\nbranch to an instruction at a different address.\n\\end{quote}\n\nThis type of instruction can therefore result in one of two different \nactions pending the result of the \ncomparison.\\footnote{This is the fundamental method used by a CPU \nto make decisions.}\n\nOnce the instruction execution phase has completed, the next instruction \ncycle will be performed using the new value in the \\reg{pc} register.\n" }, { "path": "book/license/chapter.tex", "content": "\\chapter{Attribution 4.0 International}\n\\label{license}\n\n\\begin{scriptsize}\n\nCreative Commons Corporation (\"Creative Commons\") is not a law firm and\ndoes not provide legal services or legal advice. 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Definitions}\n\n\\begin{itemize}\n \\item[a.] Adapted Material means material subject to Copyright and Similar\n Rights that is derived from or based upon the Licensed Material\n and in which the Licensed Material is translated, altered,\n arranged, transformed, or otherwise modified in a manner requiring\n permission under the Copyright and Similar Rights held by the\n Licensor. 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In all other cases the Licensor expressly\n reserves any right to collect such royalties.\n\t\\end{itemize}\n\\end{itemize}\n\n\n\\subsection*{Section 3. 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Disclaimer of Warranties and Limitation of Liability}\n\n\\begin{itemize}\n\\item[a.] UNLESS OTHERWISE SEPARATELY UNDERTAKEN BY THE LICENSOR, TO THE\n EXTENT POSSIBLE, THE LICENSOR OFFERS THE LICENSED MATERIAL AS-IS\n AND AS-AVAILABLE, AND MAKES NO REPRESENTATIONS OR WARRANTIES OF\n ANY KIND CONCERNING THE LICENSED MATERIAL, WHETHER EXPRESS,\n IMPLIED, STATUTORY, OR OTHER. THIS INCLUDES, WITHOUT LIMITATION,\n WARRANTIES OF TITLE, MERCHANTABILITY, FITNESS FOR A PARTICULAR\n PURPOSE, NON-INFRINGEMENT, ABSENCE OF LATENT OR OTHER DEFECTS,\n ACCURACY, OR THE PRESENCE OR ABSENCE OF ERRORS, WHETHER OR NOT\n KNOWN OR DISCOVERABLE. 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Term and Termination}\n\n\\begin{itemize}\n\\item[a.] This Public License applies for the term of the Copyright and\n Similar Rights licensed here. However, if You fail to comply with\n this Public License, then Your rights under this Public License\n terminate automatically.\n\n\\item[b.] Where Your right to use the Licensed Material has terminated under\n Section 6(a), it reinstates:\n\n\t\\begin{itemize}\n \\item[1.] automatically as of the date the violation is cured, provided\n it is cured within 30 days of Your discovery of the\n violation; or\n\n \\item[2.] upon express reinstatement by the Licensor.\n\t\\end{itemize}\n\n For the avoidance of doubt, this Section 6(b) does not affect any\n right the Licensor may have to seek remedies for Your violations\n of this Public License.\n\n\\item[c.] For the avoidance of doubt, the Licensor may also offer the\n Licensed Material under separate terms or conditions or stop\n distributing the Licensed Material at any time; however, doing so\n will not terminate this Public License.\n\n\\item[d.] Sections 1, 5, 6, 7, and 8 survive termination of this Public\n License.\n\\end{itemize}\n\n\n\\subsection*{Section 7. Other Terms and Conditions}\n\n\\begin{itemize}\n\\item[a.] The Licensor shall not be bound by any additional or different\n terms or conditions communicated by You unless expressly agreed.\n\n\\item[b.] Any arrangements, understandings, or agreements regarding the\n Licensed Material not stated herein are separate from and\n independent of the terms and conditions of this Public License.\n\\end{itemize}\n\n\\subsection*{Section 8. Interpretation}\n\n\\begin{itemize}\n\\item[a.] For the avoidance of doubt, this Public License does not, and\n shall not be interpreted to, reduce, limit, restrict, or impose\n conditions on any use of the Licensed Material that could lawfully\n be made without permission under this Public License.\n\n\\item[b.] To the extent possible, if any provision of this Public License is\n deemed unenforceable, it shall be automatically reformed to the\n minimum extent necessary to make it enforceable. If the provision\n cannot be reformed, it shall be severed from this Public License\n without affecting the enforceability of the remaining terms and\n conditions.\n\n\\item[c.] No term or condition of this Public License will be waived and no\n failure to comply consented to unless expressly agreed to by the\n Licensor.\n\n\\item[d.] Nothing in this Public License constitutes or may be interpreted\n as a limitation upon, or waiver of, any privileges and immunities\n that apply to the Licensor or You, including from the legal\n processes of any jurisdiction or authority.\\\\\n\\end{itemize}\n\n\\hrule\n\nCreative Commons is not a party to its public\nlicenses. Notwithstanding, Creative Commons may elect to apply one of\nits public licenses to material it publishes and in those instances\nwill be considered the Licensor. The text of the Creative Commons\npublic licenses is dedicated to the public domain under the CC0 Public\nDomain Dedication. Except for the limited purpose of indicating that\nmaterial is shared under a Creative Commons public license or as\notherwise permitted by the Creative Commons policies published at\n\\url{http://creativecommons.org/policies}, Creative Commons does not authorize the\nuse of the trademark ``Creative Commons'' or any other trademark or logo\nof Creative Commons without its prior written consent including,\nwithout limitation, in connection with any unauthorized modifications\nto any of its public licenses or any other arrangements,\nunderstandings, or agreements concerning use of licensed material. For\nthe avoidance of doubt, this paragraph does not form part of the\npublic licenses.\n\nCreative Commons may be contacted at \\url{http://creativecommons.org}.\n\n\\end{scriptsize}\n" }, { "path": "book/preamble.tex", "content": "\n\\oddsidemargin=.82in\n%\\evensidemargin=1.82in\n\\evensidemargin=1.72in\n\n%\\topmargin=-.5in\n\\headheight=12pt\n\\headsep=20pt\n\n%\\hoffset=-1.2in % for 8.5x11\n\\hoffset=-1.1in % for 8.5x11\n\n%\\voffset=-1.15in % for 8.5x11\n\\voffset=-.8in % for 8.5x11\n\n%\\textheight=9.75in % for 8.5x11\n\\textheight=9in % for 8.5x11\n%\\textheight=8.75in % for 8.5x11\n\n\\textwidth=6.1in % for 8.5x11\n%\\textwidth=6.25in % for 8.5x11\n\n\\marginparsep=7pt\n%\\marginparwidth=71pt\n%\\marginparwidth=1.25in\n%\\marginparwidth=1.5in\n\\marginparwidth=1.25in\n\\footskip=36pt\n\\marginparpush=5pt\n\n\n\\usepackage{ifthen}\n\\usepackage{stringstrings}\t% so can count characters in a string\n\\usepackage{xstring}\t\t% so can count characters in a string\n\n\\usepackage[pass]{geometry}\n\\usepackage{color} % Necessary for colored links\n\n% load makeidx BEFORE hyperref to make the index clickable\n% load makeidx AFTER hyperref if want to use showidx\n\\usepackage{makeidx}\n\\usepackage[pagebackref]{hyperref}\n\\hypersetup{\n colorlinks=true,\t%set true if you want colored links\n linkcolor=blue\t\t%choose some color if you want links to stand out\n}\n\n\\usepackage{scrextend}\t\t% so can use \\footref\n\n% don't say subsection and subsubsection in auto-references\n\\let\\subsectionautorefname\\sectionautorefname\n\\let\\subsubsectionautorefname\\sectionautorefname\n\n%\\usepackage{makeidx,showidx}\t% showidx breaks hyperref when loaded before hyperref\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% for one-sided on left margin\n\\usepackage{lineno}\n\\linenumbers\n\\setlength\\linenumbersep{.8cm}\n\n% for two-sided on inside margin\n%\\usepackage[switch*,pagewise]{lineno}\n%\\linenumbers\n%\\runningpagewiselinenumbers\n\n%\\renewcommand\\linenumberfont{\\normalfont\\tiny\\sffamily\\bfseries\\color{violet}}\n\n% lineno is screwy for displayed equations\n%\\let\\oldequation\\equation\n%\\let\\oldendequation\\endequation\n%\\renewenvironment{equation}\n% {\\linenomathNonumbers\\oldequation}\n% {\\oldendequation\\endlinenomath}\n%\n%\\setlength\\linenumbersep{6mm}\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\n\n%\\usepackage{url}\n\n\\usepackage{lastpage}\n\\usepackage{fancyhdr}\n\n\\usepackage{amsmath}\n\\numberwithin{equation}{section}\n\\usepackage{amsfonts} % I hear these are also good to load\n\\usepackage{amssymb} % I hear these are also good to load\n\n%\\usepackage{picture}\n%\\usepackage{epstopdf}\n%\\usepackage{graphicx}\n\\usepackage{epsfig}\n\\usepackage{tikz-timing}\n\\usepackage{tikz}\n%\\usepackage{timing}\n\\usepackage{float}\n\\usepackage{fancyvrb}\n\n%\\usepackage{caption}\n\\usepackage[hypcap=true]{caption}\t\t% point to top of figure rather than caption in \\hyperref\n\n\\usepackage{placeins}\n\n\\usepackage{listings}\n\n\\usepackage[toc]{glossaries}\n%\\renewcommand*{\\glsclearpage}{} \n\n\\usepackage{pifont}\n\\usepackage{layout}\n\n\\usepackage{xcolor} \n\\usepackage{textcomp} % for the trademark symbol\n\n%\\usepackage[obeyspaces]{url}\n\\usepackage{fink}\t\t\t% deprecated in favor of currfile\n%\\usepackage{currfile}\t\t% dut... doesn't emit the local include path properly\n\n\\usepackage{MyFigs}\n\n\\def\\code#1{\\url{#1}}\n\n% The exercise environment\n\\usepackage{exercise}\n\n\\renewcommand{\\ExerciseHeader}{%\n\\textbf{\\large\\ExerciseHeaderDifficulty\\ExerciseName\\ %\n\\ExerciseHeaderNB\\ExerciseHeaderTitle\\ExerciseHeaderOrigin}\\medskip}\n\n\\renewcommand{\\ExePartHeader}{%\n\\medskip\\emph{\\large\\ExePartHeaderDifficulty\\ExePartName %\n\\ExePartHeaderNB \\ExePartHeaderTitle\\\\\n}}\n\n%\\renewcommand{\\ExePartHeader}{%\n%\\medskip\\emph{\\large\\ExePartHeaderDifficulty Part \\ExePartHeaderNB %\n%\\quad \\ExePartName\\ExePartHeaderTitle}}\n\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%\\DefineVerbatimEnvironment%\n%{Code}{Verbatim}\n%{frame=single,numbers=left,numbersep=2mm,framesep=3mm}\n%%%,numbersep=2mm,frame=lines,framerule=0.8mm,framesep=5mm\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% [1] = filename to include\n% [2] = title of the code sample\n% A label will be generated as: Code:#1\n%\\newcommand{\\xxxx}[2]{%\n%\t\\label{Code:#1} %\n%\t\\VerbatimInput[frame=single,numbers=left,numbersep=2mm,framesep=3mm,label={#2}]{#1}}\n\n%\\newcommand{\\theListingFontFamily}{\\ttfamily\\small}\n\\newcommand{\\theListingFontFamily}{\\ttfamily\\footnotesize}\n%\\newcommand{\\theListingFontFamily}{\\ttfamily\\scriptsize}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% [1] = place for additional listing parameters, default: language=C\n% [2] = filepath\n% [3] = Description of the listing\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\newcommand{\\listing}[3][language=C]{%\n\t\\lstinputlisting[ %\n\t\tnumbers=left,numberstyle=\\tiny,stepnumber=1,numbersep=8pt, %\n\t\tbreaklines=true, %\n\t\tframe=single %\n\t\tshowtabs=false, %\n\t\tbasicstyle=\\theListingFontFamily, %\n\t\tshowstringspaces=false, %\n\t\ttabsize=4, %\n\t\tshowlines=true, % show all blank lines\n\t\t#1, %\n\t\tcaptionpos=t,frame=tblr,label={lst:\\detokenize{#2}},caption={{\\tt \\detokenize{#2}}\\\\\\hspace{\\textwidth}{\\small #3}}]{\\detokenize{#2}}}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\newcommand{\\listingRef}[1]{\\autoref{lst:\\detokenize{#1}}}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\lstnewenvironment{tty}\n\t{\\lstset{language=sh, %\n\t\tnumbers=left,numberstyle=\\tiny,stepnumber=1,numbersep=8pt, %\n\t\tbreaklines=true, %\n\t\tframe=single, %\n\t\tshowtabs=false, %\n\t\tbasicstyle=\\theListingFontFamily, %\n\t\tshowstringspaces=false, %\n\t\ttabsize=4, %\n\t\tshowlines=true, % show all blank lines\n\t\tbasicstyle=\\theListingFontFamily}}\n\t{}\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% A footer that shall appear on every page\n\n%\\newcommand{\\MyFoot}{{\\sf\\scriptsize Copyright \\copyright\\ 2014, 2015 John Winans. All Rights Reserved}\\\\\n%\\vspace{.05in}\n%\\scriptsize\\FooterText}\n\n\\newcommand{\\MyFoot}{\\scriptsize\\FooterText}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\pagestyle{fancy}\n\n% supress normal headings and footers\n\\fancyhf{}\n\n% heading and footing rules\n\\renewcommand{\\headrulewidth}{1pt}\n\\renewcommand{\\footrulewidth}{1pt}\n\n\n%\\def\\DiscardOneCharacter#1{}\n% Sub-footer that shows the version control version string in the lfoot defined above\n\\ifdefined\\GitFileName\n% \\newcommand{\\FooterText}{\\tt \\GitFileName \\currfilename\\\\\n \\newcommand{\\FooterText}{\\tt \\GitFileName \\finkpath\\\\\n\\GitDescription}\n\\else\n \\newcommand{\\FooterText}{\\emph{--UNKNOWN--}}\n\\fi\n\n%\\lhead{\\leftmark}\n%\\rhead{\\rightmark}\n\\fancyhead[LE]{\\leftmark}\n\\fancyhead[RO]{\\rightmark}\n\n\\newcommand{\\PageNumber}{Page \\thepage\\ of \\pageref*{LastPage}}\n%\\rfoot{Page \\thepage\\ of \\pageref{LastPage}}\n%\\lfoot{\\MyFoot}\n\n\\fancyfoot[LE,RO]{\\PageNumber}\n\\fancyfoot[RE,LO]{\\MyFoot}\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% override the plain page style so the first page of a\n% chapter still has a footer on it (but no header).\n\n\\fancypagestyle{plain}{%\n\\renewcommand{\\headrulewidth}{0pt} %\n\\fancyhf{} % clear all header and footer fields\n\\fancyfoot[LE,RO]{\\PageNumber}\n\\fancyfoot[RE,LO]{\\MyFoot}\n%\\lfoot{\\MyFoot} %\n%\\rfoot{Page \\thepage\\ of \\pageref*{LastPage}}\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\n\\setlength{\\parindent}{0pt}\n\\setlength{\\parskip}{.51em}\n\n% How deep should we enumerate the section/subsection/subsubsections\n% 3=all the way\n\\setcounter{secnumdepth}{3}\n\n% How many section-levels to show in the TOC.\n% 4=all of them\n%\\setcounter{tocdepth}{4}\n\\setcounter{tocdepth}{1}\n\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% Presentation styles for things like names links and\n% window objects in figures.\n\n% how should we present a window name\n\\newcommand{\\windowname}[1]{{\\em #1}} \n\n% How should we present the name of an object in a figure\n% that can be interacted with.\n\\newcommand{\\linkname}[1]{{\\bf #1}}\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% fix some annoying things\n\n\\newcommand{\\tm}{\\textsuperscript{TM}}\n\\newcommand{\\rtm}{\\textsuperscript{\\textregistered}}\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% A command to make a colored background box whilst in math mode:\n\\newcommand{\\MathHilight}[1]{\\colorbox{yellow}{\\ensuremath{#1}}}\n\n\\usepackage{tcolorbox}\n%\\tcbset{colback=blue!20!white}\n\\tcbset{colback=green!20!white}\n\n" }, { "path": "book/preface/chapter.tex", "content": "\\chapter{Preface}\n\\label{chapter:Preface}\n\nI set out to write this book because I couldn't find it in a single volume elsewhere.\n\nThe closest published work on this topic appear to be select portions of \n{\\em The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Document Version 2.2}\\cite{rvismv1v22:2017}, \n{The RISC-V Reader}\\cite{riscvreader:2017}, and \n{Computer Organization and Design RISC-V Edition: The Hardware Software Interface}\\cite{codriscv:2017}.\n\nThere {\\em are} some terse guides on the Internet that are suitable \nfor those who already know an assembly language. With all the (deserved) \nexcitement brewing over system organization (and the need to compress the \ntime out of university courses targeting assembly language \nprogramming~\\cite{Decker:1985:MAT:989369.989375}),\nit is no surprise that RISC-V texts for the beginning assembly programmer \nare not (yet) available.\n\nWhen I started in computing, I learned how to count in binary \nin a high school electronics course using data sheets for integrated \ncircuits such as the 74191\\cite{ttl74191:1979} and 74154\\cite{ttl74154:1979}\nprior to knowing that assembly language even existed.\n\nI learned assembly language from data sheets and texts, that are still sitting on \nmy shelves today, such as:\n\\begin{itemize}\n\\item Z80 Assembly Language Programming Manual\\cite{zilog:1977}\n\\item Z80 Assembly Language Programming\\cite{leventhal:1979}\n\\item The MCS-85 User's Manual\\cite{mcs85:1978}\n\\item The EDTASM Manual\\cite{edtasm:1978}\n\\item The MC68000 User's Manual\\cite{mc68000:1980}\n\\item Assembler Language With ASSIST\\cite{assist:1983}\n\\item IBM System/370 Principals of Operation\\cite{poo:1980}\n\\item OS/VS-DOS/VSE-VM/370 Assembler Language\\cite{assembler370:1979}\n%\\item The Series 32000 Databook\\cite{ns32k:1986}\n\\item \\ldots\\ and several others\n\\end{itemize}\n\nAll of these manuals discuss each CPU instruction in excruciating detail \nwith both a logical and narrative description. For RISC-V this is \nalso the case for the {\\em RISC-V Reader}\\cite{riscvreader:2017} and the \n{\\em Computer Organization and Design RISC-V Edition}\\cite{codriscv:2017} books\nand is also present in this text (I consider that to be the minimal \nlevel of responsibility.)\n\nWhere I hope this text will differentiate itself from the existing RISC-V \ntitles is in its attempt to address the needs of those learning assembly \nlanguage for the first time. To this end I have primed this project with \nsome of the curriculum material I created when teaching assembly language \nprogramming in the late '80s.\n" }, { "path": "book/priv/chapter.tex", "content": "\\chapter{Privileged Instructions}\n\\label{chapter:privileged}\n\n\\section{Introduction}\n\n{\\em XXX NOTE: This is a first draft of what is being detailed in the previous chapter}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\n\\subsection{CSRRW rd, csr, rs1}\n\\index{Instruction!CSRRW}\n\nThe CSRRW (Atomic Read/Write CSR) instruction atomically swaps values in \nthe CSRs and integer registers. CSRRW reads the old value of the CSR, \nzero-extends the value to XLEN bits, then writes it to integer register rd. \nThe initial value in rs1 is written to the CSR. If rd=x0, then the \ninstruction shall not read the CSR and shall not cause any of the \nside-effects that might occur on a CSR read.~\\cite[p.~22]{rvismv1v22:2017}\n\n\\DrawInsnTypeCSPicture{CSRRW x3, 2, x15}{00000000001001111001000111110011}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{CSRRS rd, csr, rs1}\n\\index{Instruction!CSRRS}\n\nThe CSRRS (Atomic Read and Set Bits in CSR) instruction reads the value \nof the CSR, zero-extends the value to XLEN bits, and writes it to integer \nregister rd. The initial value in integer register rs1 is treated as a bit \nmask that specifies bit positions to be set in the CSR. Any bit that\nis high in rs1 will cause the corresponding bit to be set in the CSR, \nif that CSR bit is writable. Other bits in the CSR are unaffected (though \nCSRs might have side effects when written).~\\cite[p.~22]{rvismv1v22:2017}\n\nIf rs1=x0, then the instruction will not write \nto the CSR at all, and so shall not cause any of the side effects that \nmight otherwise occur on a CSR write, such as raising illegal instruction \nexceptions on accesses to read-only CSRs. Note that if rs1 specifies a \nregister holding a zero value other than x0, the instruction will still \nattempt to write the unmodified value back to the CSR and will cause any \nattendant side effects.~\\cite[p.~22]{rvismv1v22:2017}\n\n\\DrawInsnTypeCSPicture{CSRRS x3, 2, x15}{00000000001001111010000111110011}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{CSRRC rd, csr, rs1}\n\\index{Instruction!CSRRC}\n\nThe CSRRC (Atomic Read and Clear Bits in CSR) instruction reads the value \nof the CSR, zero-extends the value to XLEN bits, and writes it to integer \nregister rd. The initial value in integer register rs1 is treated as a \nbit mask that specifies bit positions to be cleared in the CSR. Any bit\nthat is high in rs1 will cause the corresponding bit to be cleared in \nthe CSR, if that CSR bit is writable. Other bits in the CSR are \nunaffected.~\\cite[p.~22]{rvismv1v22:2017}\n\nIf rs1=x0, then the instruction will not write \nto the CSR at all, and so shall not cause any of the side effects that \nmight otherwise occur on a CSR write, such as raising illegal instruction \nexceptions on accesses to read-only CSRs. Note that if rs1 specifies a \nregister holding a zero value other than x0, the instruction will still \nattempt to write the unmodified value back to the CSR and will cause any \nattendant side effects.~\\cite[p.~22]{rvismv1v22:2017}\n\n\\DrawInsnTypeCSPicture{CSRRC x3, 2, x15}{00000000001001111011000111110011}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{CSRRWI rd, csr, imm}\n\\index{Instruction!CSRRWI}\n\nThis instruction is the same as CSRRW except a 5-bit unsigned (zero-extended)\nimmediate value is used rather than the value from a register.\n\n\\DrawInsnTypeCSIPicture{CSRRWI x3, 2, 7}{00000000001000111101000111110011}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{CSRRSI rd, csr, rs1}\n\\index{Instruction!CSRRSI}\n\nThis instruction is the same as CSRRS except a 5-bit unsigned (zero-extended)\nimmediate value is used rather than the value from a register.\n\nIf the uimm[4:0] field is zero, then this instruction will not\nwrite to the CSR, and shall not cause any of the side effects that \nmight otherwise occur on a CSR write. For CSRRWI, if rd=x0, then \nthe instruction shall not read the CSR and shall not cause any\nof the side-effects that might occur on a CSR \nread.~\\cite[p.~22]{rvismv1v22:2017}\n\n\\DrawInsnTypeCSIPicture{CSRRSI x3, 2, 7}{00000000001000111110000111110011}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{CSRRCI rd, csr, rs1}\n\\index{Instruction!CSRRCI}\n\nThis instruction is the same as CSRRC except a 5-bit unsigned (zero-extended)\nimmediate value is used rather than the value from a register.\n\nIf the uimm[4:0] field is zero, then this instruction will not\nwrite to the CSR, and shall not cause any of the side effects that \nmight otherwise occur on a CSR write. For CSRRWI, if rd=x0, then \nthe instruction shall not read the CSR and shall not cause any\nof the side-effects that might occur on a CSR \nread.~\\cite[p.~22]{rvismv1v22:2017}\n\n\\DrawInsnTypeCSIPicture{CSRRCI x3, 2, 7}{00000000001000111111000111110011}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\section{RV32M Standard Extension}\n\\index{RV32M}\n\n32-bit integer multiply and divide instructions.\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{MUL rd, rs1, rs2}\n\\index{Instruction!MUL}\n\nMultiply \\reg{rs1} by \\reg{rs2} and store the least significant 32-bits\nof the result in \\reg{rd}.\n\n\\DrawInsnTypeRPicture{MUL x7, x3, x31}{00000011111100111000001110110011}\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{MULH rd, rs1, rs2}\n\\index{Instruction!MULH}\n\n\\DrawInsnTypeRPicture{MULH x7, x3, x31}{00000011111100111001001110110011}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{MULHS rd, rs1, rs2}\n\\index{Instruction!MULHS}\n\n\\DrawInsnTypeRPicture{MULHS x7, x3, x31}{00000011111100111010001110110011}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{MULHU rd, rs1, rs2}\n\\index{Instruction!MULHU}\n\n\\DrawInsnTypeRPicture{MULHU x7, x3, x31}{00000011111100111011001110110011}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{DIV rd, rs1, rs2}\n\\index{Instruction!DIV}\n\n\\DrawInsnTypeRPicture{DIV x7, x3, x31}{00000011111100111100001110110011}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{DIVU rd, rs1, rs2}\n\\index{Instruction!DIVU}\n\n\\DrawInsnTypeRPicture{DIVU x7, x3, x31}{00000011111100111101001110110011}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{REM rd, rs1, rs2}\n\\index{Instruction!REM}\n\n\\DrawInsnTypeRPicture{REM x7, x3, x31}{00000011111100111110001110110011}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{REMU rd, rs1, rs2}\n\\index{Instruction!REMU}\n\n\\DrawInsnTypeRPicture{REMU x7, x3, x31}{00000011111100111111001110110011}\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\section{RV32A Standard Extension}\n\\index{RV32A}\n\n32-bit atomic operations.\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\section{RV32F Standard Extension}\n\\index{RV32F}\n\n32-bit IEEE floating point instructions.\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\section{RV32D Standard Extension}\n\\index{RV32D}\n\n64-bit IEEE floating point instructions.\n" }, { "path": "book/programs/chapter.tex", "content": "\\chapter{Writing RISC-V Programs}\n\n\\enote{Introduce the ISA register names and aliases in here?}%\nThis chapter introduces each of the RV32I instructions by developing programs \nthat demonstrate their usefulness.\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\section{Use {\\tt ebreak} to Stop \\rvddt{} Execution}\n\\index{Instruction!ebreak}\n\\label{uguide:ebreak}\n\nIt is a good idea to learn how to stop before learning how to go!\n\nThe \\insn{ebreak} instruction exists for the sole purpose of transferring control back \nto a debugging environment.\\cite[p.~24]{rvismv1v22:2017}\n\nWhen \\rvddt{} executes an \\insn{ebreak} instruction, it will immediately terminate any\nexecuting {\\em trace} or {\\em go} command currently executing and return to the\ncommand prompt without advancing the \\reg{pc} register. \n\nThe machine language encoding shows that \\insn{ebreak} has no operands.\n\n\\DrawInsnTypeEPicture{ebreak}{00000000000100000000000001110011}\n\n\\listingRef{ebreak/ebreak.out} demonstrates that since \\rvddt{} does \nnot advance the \\reg{pc} when it encounters an \\insn{ebreak} instruction, \nsubsequent {\\em trace} and/or {\\em go} commands will re-execute the same \\insn{ebreak} \nand halt the simulation again (and again). \nThis feature is intended to help prevent overzealous users from accidently \nrunning past the end of a code fragment.\\footnote{This was one of the first {\\em enhancements}\nI needed for myself \\tt:-)}\n\n\\listing{ebreak/ebreak.S}{A one-line \\insn{ebreak} program.}\n\n\\listing{ebreak/ebreak.out}{\\insn{ebreak} stopps \\rvddt{} without advancing \\reg{pc}.}\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\section{Using the \\insn{addi} Instruction}\n\\index{Instruction!addi}\n\\label{uguide:addi}\n\n\\enote{Define what constant and immediate values are somewhere.}%\nThe detailed description of how the \\insn{addi} instruction is executed\nis that it:\n\\begin{enumerate}\n\\item Sign-extends the immediate operand.\n\\item Add the sign-extended immediate operand to the contents of the \\reg{rs1} register.\n\\item Store the sum in the \\reg{rd} register.\n\\item Add four to the \\reg{pc} register (point to the next instruction.)\n\\end{enumerate}\n\nIn the following example \\reg{rs1} = \\reg{x28}, \\reg{rd} = \\reg{x29} and\nthe immediate operand is -1.\n\n\\DrawInsnTypeIPicture{addi x29, x28, -1}{11111111111111100000111010010011}\n\nDepending on the values of the fields in this instruction a number of\ndifferent operations can be performed. The most obvious is that it\ncan add things. But it can also be used to copy registers, set a \nregister to zero and even, when you need to, accomplish nothing.\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{No Operation}\n\\index{Instruction!nop}\n\nIt might seem odd but it is sometimes important to be able to execute\nan instruction that accomplishes nothing while simply advancing the \n\\reg{pc} to the next instruction. One reason for this is to fill \nunused memory between two instructions in a program.%\n\\footnote{This can happen during the evolution of one portion of code \nthat reduces in size but has to continue to fit into a system without \naltering any other code\\ldots\\ or sometimes you just need to waste \na small amount of time in a device driver.}\n\nAn instruction that accomplishes nothing is called a \\insn{nop}\n(sometimes systems call these \\insn{noop}). The name means \n{\\em no operation}. \nThe intent of a \\insn{nop} is to execute without having any side effects \nother than to advance the \\reg{pc} register.\n\nThe \\insn{addi} instruction can serve as a \\insn{nop} by coding it like this:\n\n\\DrawInsnTypeIPicture{addi x0, x0, 0}{00000000000000000000000000010011}\n\nThe result will be to add zero to zero and discard the result (because you\ncan never store a value into the x0 register.)\n\nThe RISC-V assembler provides a pseudoinstruction specifically for this \npurpose that you can use to improve the readability of your code. Note \nthat the \\insn{addi} and \\insn{nop} instructions in \\listingRef{nop/nop.S}\nare assembled into the exact same binary machine instructions\nas can be seen by comparing it to \n\\verb@objdump@ \\listingRef{nop/nop.lst}, \nand \\verb@rvddt@ \\listingRef{nop/nop.out} output.\n\n%(The \\hex{00000013} you can see are stored at addresses \\hex{0} and \\hex{4})\n%as seen by looking at the \\verb@objdump@ listing in \\listingRef{nop/nop.lst}.\n%In fact, you can see that objdump shows both instructions as a \\insn{nop}\n%while \\listingRef{nop/nop.out} shows that \\rvddt{} displays both as \n%\\verb@addi x0, x0, 0@. \n\n\\listing{nop/nop.S}{Demonstrate that \\insn{addi} can be used as a \\insn{nop}.}\n\n\\index{objdump}\n\\listing{nop/nop.lst}{Using \\insn{addi} to perform a \\insn{nop}}\n\n\\listing{nop/nop.out}{Using \\insn{addi} to perform a \\insn{nop}}\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{Copying the Contents of One Register to Another}\n\nBy adding zero to one register and storing the sum in another register\nthe \\insn{addi} instruction can be used to copy the value stored in one\nregister to another register. The following instruction will copy\nthe contents of \\reg{t4} into \\reg{t3}.\n\n\\DrawInsnTypeIPicture{addi t3, t4, 0}{00000000000011101000111000010011}\n\n\\index{Instruction!mv}\nThis is a commonly required operation. To make your intent clear\nyou may use the \\insn{mv} pseudoinstruction for this purpose. \n\n\\listingRef{mv/mv.S} shows the source of a program that is dumped in \n\\listingRef{mv/mv.lst} illustrating that the assembler has generated the\nsame machine instruction (\\hex{000e8e13} at addresses \\hex{0} and \\hex{4}) \nfor both of the instructions.\n\n\\listing{mv/mv.S}{Comparing \\insn{addi} to \\insn{mv}}\n\n\\listing{mv/mv.lst}{An objdump of an \\insn{addi} and \\insn{mv} Instruction.}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{Setting a Register to Zero}\n\nRecall that \\reg{x0} always contains the value zero. Any register\ncan be set to zero by copying the contents of \\reg{x0} using \\insn{mv} \n(aka \\insn{addi}).%\n\\footnote{There are other pseudoinstructions (such as \\insn{li}) that can also \nturn into an \\insn{addi} instruction. Objdump might display `{\\tt addi t3,x0,0}'\nas `{\\tt mv t3,x0}' or `{\\tt li t3,0}'.}\n\nFor example, to set \\reg{t3} to zero: \n\n\\DrawInsnTypeIPicture{addi t3, x0, 0}{00000000000000000000111000010011}\n\n\\listing{mvzero/mv.S}{Using \\insn{mv} (aka \\insn{addi}) to zero-out a register.}\n\n\\listingRef{mvzero/mv.out} traces the execution of the program in \n\\listingRef{mvzero/mv.S} showing how \\reg{t3} is changed from \\hex{f0f0f0f0} \n(seen on $\\ell 16$) to \\hex{00000000} (seen on $\\ell 26$.)\n\n\\listing{mvzero/mv.out}{Setting \\reg{t3} to zero.}\n\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{Adding a 12-bit Signed Value}\n\n\n\\DrawInsnTypeIPicture{addi x1, x7, 4}{00000000010000111000000010010011}\n\n\n{\\small\n\\begin{verbatim}\n addi t0, zero, 4 # t0 = 4\n addi t0, t0, 100 # t0 = 104\n\n addi t0, zero, 0x123 # t0 = 0x123\n addi t0, t0, 0xfff # t0 = 0x122 (subtract 1)\n\n addi t0, zero, 0xfff # t0 = 0xffffffff (-1) (diagram out the chaining carry)\n # refer back to the overflow/truncation discussion in binary chapter\n\n\taddi x0, x0, 0\t\t\t\t# no operation (pseudo: nop)\n\taddi rd, rs, 0\t\t\t\t# copy reg rs to rd (pseudo: mv rd, rs)\n\\end{verbatim}\n}\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\section{todo}\n\nIdeas for the order of introducing instructions.\n\n\n\\section{Other Instructions With Immediate Operands}\n\n\\label{uguide:andi}\n\\label{uguide:ori}\n\\label{uguide:xori}\n\\label{uguide:slti}\n\\label{uguide:sltiu}\n\\label{uguide:srai}\n\\label{uguide:slli}\n\\label{uguide:srli}\n{\\small\n\\begin{verbatim}\n andi\n ori\n xori\n\n slti\n sltiu\n srai\n slli\n srli\n\\end{verbatim}\n}\n\n\\section{Transferring Data Between Registers and Memory}\n\nRV is a load-store architecture. This means that the only way that the\nCPU can interact with the memory is via the {\\em load} and {\\em store}\ninstructions. All other data manipulation must be performed on register\nvalues.\n\nCopying values from memory to a register (first examples using regs set with addi):\n\\label{uguide:lb}\n\\label{uguide:lh}\n\\label{uguide:lw}\n\\label{uguide:lbu}\n\\label{uguide:lhu}\n{\\small\n\\begin{verbatim}\n lb\n lh\n lw\n lbu\n lhu\n\\end{verbatim}\n}\n\nCopying values from a register to memory:\n\\label{uguide:sb}\n\\label{uguide:sh}\n\\label{uguide:sw}\n{\\small\n\\begin{verbatim}\n sb\n sh\n sw\n\\end{verbatim}\n}\n\n\\section{RR operations}\n\\label{uguide:add}\n\\label{uguide:sub}\n\\label{uguide:and}\n\\label{uguide:or}\n\\label{uguide:sra}\n\\label{uguide:srl}\n\\label{uguide:sll}\n\\label{uguide:xor}\n\\label{uguide:sltu}\n\\label{uguide:slt}\n{\\small\n\\begin{verbatim}\n add\n sub\n and\n or\n sra\n srl\n sll\n xor\n sltu\n slt\n\\end{verbatim}\n}\n\n\n\\section{Setting registers to large values using lui with addi}\n\n\\label{uguide:lui}\n\\label{uguide:auipc}\n{\\small\n\\begin{verbatim}\n addi // useful for values from -2048 to 2047\n lui // useful for loading any multiple of 0x1000\n\n Setting a register to any other value must be done using a combo of insns:\n\n auipc // Load an address relative the the current PC (see la pseudo)\n addi\n\n lui // Load constant into into bits 31:12 (see li pseudo)\n addi // add a constant to fill in bits 11:0\n if bit 11 is set then need to +1 the lui value to compensate\n\\end{verbatim}\n}\n\n\n\\section{Labels and Branching}\n\nStart to introduce addressing here?\n\n\\label{uguide:beq}\n\\label{uguide:bne}\n\\label{uguide:blt}\n\\label{uguide:bge}\n\\label{uguide:bltu}\n\\label{uguide:bgeu}\n\\label{uguide:bgt}\n\\label{uguide:ble}\n\\label{uguide:bgtu}\n\\label{uguide:beqz}\n\\label{uguide:bnez}\n\\label{uguide:blez}\n\\label{uguide:bgez}\n\\label{uguide:bltz}\n\\label{uguide:bgtz}\n{\\small\n\\begin{verbatim}\n beq\n bne\n blt\n bge\n bltu\n bgeu\n\n bgt rs, rt, offset # pseudo for: blt rt, rs, offset (reverse the operands)\n ble rs, rt, offset # pseudo for: bge rt, rs, offset (reverse the operands)\n bgtu rs, rt, offset # pseudo for: bltu rt, rs, offset (reverse the operands)\n bleu rs, rt, offset # pseudo for: bgeu rt, rs, offset (reverse the operands)\n\n beqz rs, offset # pseudo for: beq rs, x0, offset\n bnez rs, offset # pseudo for: bne rs, x0, offset\n blez rs, offset # pseudo for: bge x0, rs, offset\n bgez rs, offset # pseudo for: bge rs, x0, offset\n bltz rs, offset # pseudo for: blt rs, x0, offset\n bgtz rs, offset # pseudo for: blt x0, rs, offset\n\\end{verbatim}\n}\n\n\n\n\\section{Jumps}\n\nIntroduce and present subroutines but not nesting until introduce stack operations.\n\n\\label{uguide:jal}\n\\label{uguide:jalr}\n{\\small\n\\begin{verbatim}\n jal\n jalr\n\\end{verbatim}\n}\n\n\n\n\\section{Pseudoinstructions}\n\n{\\small\n\\begin{verbatim}\n li rd,constant\n lui rd,(constant + 0x00000800) >> 12\n addi rd,rd,(constant & 0x00000fff)\n\n la rd,label\n auipc rd,((label-.) + 0x00000800) >> 12\n addi rd,rd,((label-(.-4)) & 0x00000fff)\n\n l{b|h|w} rd,label\n auipc rd,((label-.) + 0x00000800) >> 12\n l{b|h|w} rd,((label-(.-4)) & 0x00000fff)(rd)\n\n s{b|h|w} rd,label,rt # rt used as a temp reg for the operation (default=x6)\n auipc rt,((label-.) + 0x00000800) >> 12\n s{b|h|w} rd,((label-(.-4)) & 0x00000fff)(rt)\n\n call label auipc x1,((label-.) + 0x00000800) >> 12\n jalr x1,((label-(.-4)) & 0x00000fff)(x1)\n\n tail label,rt # rt used as a temp reg for the operation (default=x6)\n auipc rt,((label-.) + 0x00000800) >> 12\n jalr x0,((label-(.-4)) & 0x00000fff)(rt)\n\n mv rd,rs addi rd,rs,0\n \n j label jal x0,label\n jal label jal x1,label\n jr rs jalr x0,0(rs)\n jalr rs jalr x1,0(rs)\n ret jalr x0,0(x1)\n\\end{verbatim}\n}\n\n\\subsection{The {\\tt li} Pseudoinstruction}\n\nNote that the {\\tt li} pseudoinstruction includes an (effectively) conditional addition \nof 1 to the immediate operand\nin the {\\tt lui} instruction. This is because the immediate operand in the\n{\\tt addi} instruction is sign-extended before it is added to \\verb@rd@.\nIf the immediate operand to the {\\tt addi} has its most-significant-bit set to 1 then\nit will have the effect of subtracting 1 from the operand in the \\verb@lui@ instruction.\n\nConsider the case of putting the value {\\tt 0x12345800} into register {\\tt x5}:\n\n{\\small\n\\begin{verbatim}\n li x5,0x12345800\n\\end{verbatim}\n}\n{\\color{red}\nA naive (incorrect) solution might be:\n{\\small\n\\begin{verbatim}\n lui x5,0x12345 // x5 = 0x12345000\n addi x5,x5,0x800 // x5 = 0x12345000 + sx(0x800) = 0x12345000 + 0xfffff800 = 0x12344800\n\\end{verbatim}\n}\nThe result of the above code is that an incorrect value has been placed into x5. \n}\n\nTo remedy this problem, the value used in the {\\tt lui} instruction can be altered \n(by adding 1 to its operand) to compensate for the sign-extention in the {\\tt addi} \ninstruction:\n{\\small\n\\begin{verbatim}\n lui x5,0x12346 // x5 = 0x12346000 (note: this is 0x12345800 + 0x0800)\n addi x5,x5,0x800 // x5 = 0x12346000 + sx(0x800) = 0x12346000 + 0xfffff800 = 0x12345800\n\\end{verbatim}\n}\n\nKeep in mind that the {\\tt li} pseudoinstruction must {\\em only} increment the operand \nof the {\\tt lui} instruction when it is known that the operand of the subsequent \n{\\tt addi} instruction will be a negative number.\n\n\\enote{Add a ribbon diagram of this?}%\nBy adding {\\tt 0x00000800} to the immediate operand of the {\\tt lui} instruction in\nthis example, a carry-bit into bit-12 will be set to {\\tt 1} iff the value in\nbits 11-0 will be treated as a negative value in the subsequent {\\tt addi} instruction.\nIn other words, when bit-11 is set to {\\tt 1} in the immediate operand of the {\\tt li} \npseudoinstruction, the immediate operand of the {\\tt lui} instruction will be \nincremented by {\\tt 1}.\n\nConsider the case where we wish to put the value {\\tt 0x12345700} into register {\\tt x5}:\n{\\small\n\\begin{verbatim}\n lui x5,0x12345 // x5 = 0x12345000 (note that 0x12345700 + 0x0800 = 0x12345f00)\n addi x5,x5,0x700 // x5 = 0x12345000 + sx(0x700) = 0x12345000 + 0x00000700 = 0x12345700\n\\end{verbatim}\n}\nThe sign-extension in this example performed by the {\\tt addi} instruction will convert the\n{\\tt 0x700} to {\\tt 0x00000700} before the addition.\n\nObserve that {\\tt 0x12345700+0x0800 = 0x12345f00} and therefore, after shifting\nto the right, the least significant {\\tt 0xf00} is truncated, leaving {\\tt 0x12345} as \nthe immediate operand of the {\\tt lui} instruction. The addition of \n{\\tt 0x0800} in this example has no effect on the immediate operand of the {\\tt lui}\ninstruction because bit-11 in the original value {\\tt 0x12345700} is zero.\n\nA general algorithm for implementing the {\\tt li rd,constant} pseudoinstruction is:\n\n{\\small\n\\begin{verbatim}\n lui rd,(constant + 0x00000800) >> 12 \n addi rd,rd,(constant & 0x00000fff)\t\t// the 12-bit immediate is sign extended \n\\end{verbatim}\n}\n\n\\enote{Find a proper citation for this.}%\nNote that on RV64 and RV128 systems, the {\\tt lui} places the immediate operand into\nbits 31-12 and then sign-extends the result to {\\tt XLEN} bits.\n\n\n\n\n\n\n\n\n\n\\subsection{The {\\tt la} Pseudoinstruction}\n\nThe \\verb@la@ (and others that use \\verb@auipc@ such as \nthe \\verb@l{b|h|w}@, \\verb@s{b|h|w}@, \\verb@call@, and \\verb@tail@) pseudoinstructions\nalso compensate for a sign-ended negative number when adding a 12-bit immediate\noperand. The only difference is that these use a \\verb@pc@-relative addressing mode.\n\nFor example, consider the task of putting an address represented by the label \\verb@var1@\ninto register x10:\n\n{\\small\n\\begin{verbatim}\n00010040 la x10,var1\n00010048 ... # note that the la pseudoinstruction expands into 8 bytes\n...\n\n var1:\n00010900 .word 999 # a 32-bit integer constant stored in memory at address var1\n\\end{verbatim}\n}\nThe \\verb@la@ instruction in this example will expand into:\n{\\small\n\\begin{verbatim}\n00010040 auipc x10,((var1-.) + 0x00000800) >> 12\n00010044 addi x10,x10,((var1-(.-4)) & 0x00000fff)\n\\end{verbatim}\n}\n\nNote that \\verb@auipc@ will shift the immediate operand to the left 12 bits and then\nadd that to the \\verb@pc@ register (see \\autoref{insn:auipc}.)\n\nThe assembler will calculate the value of \\verb@(var1-.)@ by subtracting the address\nrepresented by the label \\verb@var1@ from the address of the current instruction \n(which is expressed as '.') resulting in the number of bytes from the current instruction\nto the target label\\ldots{} which is \\verb@0x000008c0@.\n\nTherefore the expanded pseudoinstruction example will become:\n{\\small\n\\begin{verbatim}\n00010040 auipc x10,((0x00010900 - 0x00010040) + 0x00000800) >> 12\n00010044 addi x10,x10,((0x00010900 - (0x00010044 - 4)) & 0x00000fff) # note the extra -4 here!\n\\end{verbatim}\n}\nAfter performing the subtractions, it will reduce to this:\n{\\small\n\\begin{verbatim}\n00010040 auipc x10,(0x000008c0 + 0x00000800) >> 12\n00010044 addi x10,x10,(0x000008c0 & 0x00000fff)\n\\end{verbatim}\n}\nContinuing to reduce the math operations we get:\n{\\small\n\\begin{verbatim}\n00010040 auipc x10,0x00001 # 0x000008c0 + 0x00000800 = 0x000010c0\n00010044 addi x10,x10,0x8c0\n\\end{verbatim}\n}\n\nNote that the \\verb@la@ pseudoinstruction exhibits the same sort of technique as \nthe \\verb@li@ in that\nif/when the immediate operand of the \\verb@addi@ instruction has its most significant \nbit set then the operand in the \\verb@auipc@ has to be incremented by 1 to compensate.\n\n\n\n\n\n\n\n\n\\section{Relocation}\n \nBecause expressions that refer to constants and address labels are common in \nassembly language programs, a shorthand notation is available for calculating \nthe pairs of values that are used in the implementation of things like the \n\\verb@li@ and \\verb@la@ pseudoinstructions (that have to be written to \ncompensate for the sign-extension that will take place in the immediate operand \nthat appears in instructions like \\verb@addi@ and \\verb@jalr@.)\n\n\\subsection{Absolute Addresses}\n\nTo refer to an absolute value, the following operators can be used:\n{\\small\n\\begin{verbatim}\n %hi(constant) // becomes: (constant + 0x00000800) >> 12\n %lo(constant) // becomes: (constant & 0x00000fff)\n\\end{verbatim}\n}\n\nThus, the \\verb@li@ pseudoinstruction can, therefore, be expressed like this:\n\n{\\small\n\\begin{verbatim}\n li rd,constant lui rd,%hi(constant)\n addi rd,rd,%lo(constant)\n\\end{verbatim}\n}\n\n\n\n\\subsection{PC-Relative Addresses}\n\nThe following can be used for PC-relative addresses:\n{\\small\n\\begin{verbatim}\n %pcrel_hi(symbol) // becomes: ((symbol-.) + 0x0800) >> 12\n %pcrel_lo(lab) // becomes: ((symbol-lab) & 0x00000fff)\n\\end{verbatim}\n}\n\nNote the subtlety involved with the \\verb@lab@ on \\verb@%pcrel_lo@. It is needed to \ndetermine the address of the instruction that contains the corresponding \\verb@%pcrel_hi@.\n(The label \\verb@lab@ MUST be on a line that used a \\verb@%pcrel_hi()@ or get an \nerror from the assembler.)\n\nThus, the \\verb@la rd,label@ pseudoinstruction can be expressed like this:\n{\\small\n\\begin{verbatim}\nxxx: auipc rd,%pcrel_hi(label)\n addi rd,rd,%pcrel_lo(xxx) // the xxx tells pcrel_lo where to find the matching pcrel_hi\n\\end{verbatim}\n}\n\nExamples of using the \\verb@auipc@ \\& \\verb@addi@ together with \\verb@%pcrel_hi()@ and\n\\verb@%pcrel_lo()@:\n\n{\\small\n\\begin{verbatim}\nxxx: auipc t1,%pcrel_hi(yyy) // ((yyy-.) + 0x0800) >> 12\n addi t1,t1,%pcrel_lo(xxx) // ((yyy-xxx) & 0x00000fff)\n...\nyyy: // the address: yyy is saved into t1 above\n...\n\\end{verbatim}\n}\n\n\nReferencing the same \\verb@%pcrel_hi@ in multiple subsequent uses of \\verb@%pcrel_lo@ is legal:\n{\\small\n\\begin{verbatim}\nlabel: auipc t1,%pcrel_hi(symbol)\n addi t2,t1,%pcrel_lo(label) // t2 = symbol\n addi t3,t1,%pcrel_lo(label) // t3 = symbol\n lw t4,%pcrel_lo(label)(t1) // t4 = fetch value from memory at 'symbol'\n addi t4,t4,123 // t4 = t4 + 123\n sw t4,%pcrel_lo(label)(t1) // store t4 back into memory at 'symbol'\n\\end{verbatim}\n}\n\n\n\n\n\n\\section{Relaxation}\n\n%\\enote{I'm not sure I want to get into the details of how this is done. Just assume it works.}%\nIn the simplest of terms, {\\em Relaxation} refers to the ability of the \nlinker (not the compiler!) to determine if/when the instructions that\nwere generated with the \\verb@xxx_hi@ and \\verb@xxx_lo@ operators are\nunneeded (and thus waste execution time and memory) and can therefore\nbe removed.\n\nHowever, doing so is not trivial as it will result in moving things around \nin memory, possibly changing the values of address labels in the \nalready-assembled program! Therefore, while the motivation for \nrexation is obvious, the process of implementing it is non-trivial.\n\nSee: \\url{https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md}\n" }, { "path": "book/programs/src/.gitignore", "content": "*.bin\n" }, { "path": "book/programs/src/Make.rules", "content": "\nARCH=riscv32-unknown-elf\n\nCC=$(ARCH)-gcc\nAS=$(ARCH)-as\nLD=$(ARCH)-ld\nOBJCOPY=$(ARCH)-objcopy\nOBJDUMP=$(ARCH)-objdump\nSIZE=$(ARCH)-size\n\n#LDFLAGS+=-nostdlib -Wl,-Ttext=0x0,-Tdata=0x8000\nLDFLAGS+=-nostdlib -Wl,-Ttext=0x0\n\nCFLAGS+=-ffreestanding -fno-pic\nCFLAGS+=-march=rv32i -mabi=ilp32\nCFLAGS+=-Wl,--no-relax\t\t\t# see: https://github.com/riscv/riscv-gcc/issues/120\n\nASFLAGS+=$(CFLAGS)\n\nCLEAN_DIRS=$(SUBDIRS:%=clean-%)\nALL_DIRS=$(SUBDIRS:%=all-%)\n\n.PHONY: all clean world $(CLEAN_DIRS) $(ALL_DIRS)\n\n\n%.bin : %\n\t$(OBJCOPY) $< -O binary $@\n\n%.lst : %\n\t$(OBJDUMP) -dr $< | grep -v '^$$' > $<.lst\n\n% : %.o\n\t$(LINK.c) $(LDFLAGS) -o $@ $^ $(LDLIBS)\n\t$(SIZE) -x -A $@\n\n%.s: %.c\n\t$(COMPILE.c) -S -o $@ $<\n\n%.srec: %\n\t$(OBJCOPY) $< -O srec $@ \n\n\n\n\nall:: $(ALL_DIRS)\n\nclean:: $(CLEAN_DIRS)\n\n$(ALL_DIRS)::\n\t$(MAKE) -C $(@:all-%=%) all\n\n$(CLEAN_DIRS)::\n\t$(MAKE) -C $(@:clean-%=%) clean\n\nworld:: clean all\n" }, { "path": "book/programs/src/Makefile", "content": "\nSUBDIRS=\\\n\tnop\\\n\tli\\\n\tmv\\\n\tmvzero\\\n\tebreak\n\nTOP=.\ninclude $(TOP)/Make.rules\n" }, { "path": "book/programs/src/mvzero/.gitignore", "content": "mv\n" }, { "path": "book/programs/src/mvzero/Makefile", "content": "\nPROG=mv\n\nall:: $(PROG).out $(PROG).lst\n\n$(PROG).out:: $(PROG).bin\n\t./run.sh > $@ 2>&1\n\n$(PROG).bin:: $(PROG)\n\nclean::\n\trm -f $(PROG) *.o *.lst *.bin *.srec *.out\n\nTOP=..\ninclude $(TOP)/Make.rules\n\n\n\n" }, { "path": "book/programs/src/mvzero/mv.S", "content": "\t.text\t\t\t\t# put this into the text section\n\t.align\t2\t\t\t# align to a multiple of 4\n\t.globl\t_start\n\n_start:\n\tmv\t\tt3, x0\t\t# t3 = 0\n\n\tebreak\n" }, { "path": "book/programs/src/mvzero/mv.lst", "content": "mv: file format elf32-littleriscv\nDisassembly of section .text:\n00000000 <_start>:\n 0:\t00000e13 \tli\tt3,0\n 4:\t00100073 \tebreak\n" }, { "path": "book/programs/src/mvzero/mv.out", "content": "$ rvddt -f mv.bin\nsp initialized to top of memory: 0x0000fff0\nLoading 'mv.bin' to 0x0\nThis is rvddt. Enter ? for help.\nddt> a\nddt> d 0 16\n 00000000: 13 0e 00 00 73 00 10 00 a5 a5 a5 a5 a5 a5 a5 a5 *....s...........*\nddt> t 0 1000\n zero x0 00000000 ra x1 f0f0f0f0 sp x2 0000fff0 gp x3 f0f0f0f0\n tp x4 f0f0f0f0 t0 x5 f0f0f0f0 t1 x6 f0f0f0f0 t2 x7 f0f0f0f0\n s0 x8 f0f0f0f0 s1 x9 f0f0f0f0 a0 x10 f0f0f0f0 a1 x11 f0f0f0f0\n a2 x12 f0f0f0f0 a3 x13 f0f0f0f0 a4 x14 f0f0f0f0 a5 x15 f0f0f0f0\n a6 x16 f0f0f0f0 a7 x17 f0f0f0f0 s2 x18 f0f0f0f0 s3 x19 f0f0f0f0\n s4 x20 f0f0f0f0 s5 x21 f0f0f0f0 s6 x22 f0f0f0f0 s7 x23 f0f0f0f0\n s8 x24 f0f0f0f0 s9 x25 f0f0f0f0 s10 x26 f0f0f0f0 s11 x27 f0f0f0f0\n t3 x28 f0f0f0f0 t4 x29 f0f0f0f0 t5 x30 f0f0f0f0 t6 x31 f0f0f0f0\n pc 00000000\n00000000: 00000e13 addi t3, zero, 0 # t3 = 0x00000000 = 0x00000000 + 0x00000000\n zero x0 00000000 ra x1 f0f0f0f0 sp x2 0000fff0 gp x3 f0f0f0f0\n tp x4 f0f0f0f0 t0 x5 f0f0f0f0 t1 x6 f0f0f0f0 t2 x7 f0f0f0f0\n s0 x8 f0f0f0f0 s1 x9 f0f0f0f0 a0 x10 f0f0f0f0 a1 x11 f0f0f0f0\n a2 x12 f0f0f0f0 a3 x13 f0f0f0f0 a4 x14 f0f0f0f0 a5 x15 f0f0f0f0\n a6 x16 f0f0f0f0 a7 x17 f0f0f0f0 s2 x18 f0f0f0f0 s3 x19 f0f0f0f0\n s4 x20 f0f0f0f0 s5 x21 f0f0f0f0 s6 x22 f0f0f0f0 s7 x23 f0f0f0f0\n s8 x24 f0f0f0f0 s9 x25 f0f0f0f0 s10 x26 f0f0f0f0 s11 x27 f0f0f0f0\n t3 x28 00000000 t4 x29 f0f0f0f0 t5 x30 f0f0f0f0 t6 x31 f0f0f0f0\n pc 00000004\n00000004: ebreak\nddt> x\n" }, { "path": "book/programs/src/mvzero/run.sh", "content": "prompt=\"$\" \ncmd=\"rvddt -f mv.bin\"\necho \"$prompt $cmd\"\n$cmd <=rs2) ? @\\hyperref[imm.b:decode]{imm\\_b}\\verb@ : 4@)}\\\\\n\\hline\nbgeu & rs1, rs2, \\hyperref[pcrel.13]{pcrel\\_13} & \\hyperref[insnformat:btype]{B} & \\hyperref[insn:bgeu]{Branch Greater or Equal Unsigned} & {\\tt pc $\\leftarrow$ pc + (\\verb@(rs1>=rs2) ? @\\hyperref[imm.b:decode]{imm\\_b}\\verb@ : 4@)}\\\\\n\\hline\nblt & rs1, rs2, \\hyperref[pcrel.13]{pcrel\\_13} & \\hyperref[insnformat:btype]{B} & \\hyperref[insn:blt]{Branch Less Than} & {\\tt pc $\\leftarrow$ pc + (\\verb@(rs1> (rs2\\%\\hyperref[XLEN]{XLEN}), pc $\\leftarrow$ pc+4}\\\\\n\\hline\nsrai & rd, rs1, shamt & \\hyperref[insnformat:itype]{I} & \\hyperref[insn:srai]{Shift Right Arithmetic Immediate} & {\\tt rd $\\leftarrow$ rs1 >> \\hyperref[shamt.i:decode]{shamt\\_i}, pc $\\leftarrow$ pc+4}\\\\\n\\hline\nsrl & rd, rs1, rs2 & \\hyperref[insnformat:rtype]{R} & \\hyperref[insn:srl]{Shift Right Logical} & {\\tt rd $\\leftarrow$ rs1 >> (rs2\\%\\hyperref[XLEN]{XLEN}), pc $\\leftarrow$ pc+4}\\\\\n\\hline\nsrli & rd, rs1, shamt & \\hyperref[insnformat:itype]{I} & \\hyperref[insn:srli]{Shift Right Logical Immediate} & {\\tt rd $\\leftarrow$ rs1 >> \\hyperref[shamt.i:decode]{shamt\\_i}, pc $\\leftarrow$ pc+4}\\\\\n\\hline\nsub & rd, rs1, rs2 & \\hyperref[insnformat:rtype]{R} & \\hyperref[insn:sub]{Subtract} & {\\tt rd $\\leftarrow$ rs1 - rs2, pc $\\leftarrow$ pc+4}\\\\\n\\hline\nsw & rs2, imm(rs1) & \\hyperref[insnformat:stype]{S} & \\hyperref[insn:sw]{Store Word} & {\\tt \\hyperref[memory:m32]{m32}(rs1+\\hyperref[imm.s:decode]{imm\\_s}) $\\leftarrow$ rs2[31:0], pc $\\leftarrow$ pc+4}\\\\\n\\hline\nxor & rd, rs1, rs2 & \\hyperref[insnformat:rtype]{R} & \\hyperref[insn:xor]{Exclusive Or} & {\\tt rd $\\leftarrow$ rs1 $\\oplus$ rs2, pc $\\leftarrow$ pc+4}\\\\\n\\hline\nxori & rd, rs1, imm & \\hyperref[insnformat:itype]{I} & \\hyperref[insn:xori]{Exclusive Or Immediate} & {\\tt rd $\\leftarrow$ rs1 $\\oplus$ \\hyperref[imm.i:decode]{imm\\_i}, pc $\\leftarrow$ pc+4}\\\\\n\\hline\n\\end{tabular}\n}%\n\\newpage\n{\\Large RV32I Base Instruction Set Encoding}~\\cite[p.~104]{rvismv1v22:2017}\n\n%\\DrawAllInsnTypes\n\\DrawAllInsnOps\n\\newpage%\n\\thispagestyle{empty}%\n%\\newgeometry{left=1.3in,width=8.1in,height=13in,top=1in,bottom=0in}%\n\\newgeometry{left=0in,width=8in,height=10.5in,vmargin=0in,hmargin=0in,layouthoffset=1.35in,layoutvoffset=1in}%\n%\\resizebox{8in}{!}{\\rotatebox{90}{\\DrawAllInsnOps}}\n%\\resizebox{8in}{!}{\\rotatebox{90}{\\DrawGCAllInsnOps}}\n\\resizebox{8in}{10.7in}{\\rotatebox{90}{\\DrawGCAllInsnOps}}\n\n\\newpage%\n\\thispagestyle{empty}%\n\\resizebox{8in}{!}{\n\\rotatebox{-90}{\n\\DrawInsnRibbons\n}\n}\n\\restoregeometry\n" }, { "path": "book/rv32/base.tex", "content": "\n\\section{RV32I Base Instruction Set}\n\\index{RV32I}\n\n\\enote{Migrate all te details into the programming chapter and\nreduce this section to the obligatory reference chapter.}%\n\\Gls{rv32}I refers to the basic 32-bit integer instructions.\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{LUI rd, imm}\n\\index{Instruction!LUI}\n\nLoad Upper Immediate.\n\n\\verb@rd@ $\\leftarrow$ \\verb@zr(imm)@\n\nCopy the immediate value into bits 31:12 of the destination register and\nplace zeros into bits 11:0.\nWhen XLEN is 64 or 128, the immediate value is sign-extended to the left.\n\n\\input{insn/lui.tex}\n\n\n%Instruction Format and Example:\n%\n%\\DrawInsnTypeUPicture{LUI t0, 3}{00000000000000000011001010110111}\n%\n%\\begin{verbatim}\n%00010074: 000032b7 lui x5, 0x3 // x5 = 0x3000\n% reg 0: 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 00003000 f0f0f0f0 f0f0f0f0\n% reg 8: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0\n% reg 16: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0\n% reg 24: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0\n% pc: 00010078\n%\\end{verbatim}\n%\n%\\DrawInsnTypeUPicture{LUI t0, 0xfffff}{11111111111111111111001010110111}\n%\n%\\begin{verbatim}\n%00010078: fffff2b7 lui x5, 0xfffff // x5 = 0xfffff000\n% reg 0: 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 fffff000 f0f0f0f0 f0f0f0f0\n% reg 8: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0\n% reg 16: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0\n% reg 24: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0\n% pc: 0001007c\n%\\end{verbatim}\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{AUIPC rd, imm}\n\\index{Instruction!AUIPC}\n\nAdd Upper Immediate to PC.\n\n\\verb@rd@ $\\leftarrow$ \\verb@pc + zr(imm)@\n\nCreate a signed 32-bit value by zero-extending imm[31:12] to the \nright (see \\autoref{extension:zr}) and add this value to the \n\\reg{pc} register, placing the result into \\reg{rd}.\n\nWhen XLEN is 64 or 128, the immediate value is also sign-extended \nto the left prior to being added to the \\reg{pc} register.\n\n\\DrawInsnTypeUPicture{AUIPC t0, 3}{00000000000000000011001010110111}\n\\begin{verbatim}\n0001007c: 00003297 auipc x5, 0x3 // x5 = 0x1307c = 0x1007c + 0x3000\n reg 0: 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 0001307c f0f0f0f0 f0f0f0f0\n reg 8: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0\n reg 16: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0\n reg 24: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0\n pc: 00010080\n\\end{verbatim}\n\n\\DrawInsnTypeUPicture{AUIPC t0, 0x81000}{10000001000000000000001010110111}\n\\begin{verbatim}\n00010080: 81000297 auipc x5, 0x81000 // x5 = 0x81010080 = 0x10080 + 0x81000000\n reg 0: 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 81010080 f0f0f0f0 f0f0f0f0\n reg 8: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0\n reg 16: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0\n reg 24: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0\n pc: 00010084\n\\end{verbatim}\n\n\nThe AUIPC instruction supports two-instruction sequences to access arbitrary \noffsets from the PC for both control-flow transfers and data accesses. \nThe combination of an AUIPC and the 12-bit immediate in a JALR can transfer \ncontrol to any 32-bit PC-relative address, while an AUIPC plus the 12-bit \nimmediate offset in regular load or store instructions can access any 32-bit \nPC-relative data address.~\\cite[p.~14]{rvismv1v22:2017}\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{JAL rd, imm}\n\\index{Instruction!JAL}\n\nJump and link.\n\n\\verb@rd@ $\\leftarrow$ \\verb@pc + 4@\\\\\n\\verb@pc@ $\\leftarrow$ \\verb@pc + sx(imm<<1)@\n\nThis instruction saves the address of the next instruction\nthat would otherwise execute (located at \\reg{pc}+4) into \n\\reg{rd} and then adds immediate value to the \\reg{pc} causing\nan unconditional branch to take place.\n\nThe standard software conventions for calling subroutines\nuse \\reg{x1} as the return address (\\reg{rd} register in this \ncase).~\\cite[p.~16]{rvismv1v22:2017}\n\n\nEncoding:\n\n\\DrawInsnTypeJPicture{JAL x7, .+16}{00000001000000000000001111101111}\n\nimm demultiplexed value = $00000000000000001000_2 \\ll 1 = 16_{10}$\n\n\nState of registers before execution:\n\npc = 0x11114444\n\nState of registers after execution:\n\npc = 0x11114454\nx7 = 0x11114448\n\nJAL provides a method to call a subroutine using a pc-relative address.\n\n\n\\DrawInsnTypeJPicture{JAL x7, .-16}{11111111000111111111001111101111}\n\nimm demultiplexed value = $11111111111111111000_2 \\ll 1 = -16_{10}$\n\nState of registers before execution:\n\npc = 0x11114444\n\nState of registers after execution:\n\npc = 0x11114434\nx7 = 0x11114448\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{JALR rd, rs1, imm}\n\\index{Instruction!JALR}\n\nJump and link register.\n\n\\verb@rd@ $\\leftarrow$ \\verb@pc + 4@\\\\\n\\verb@pc@ $\\leftarrow$ \\verb@(rs1 + sx(imm)) & ~1@\n\nThis instruction saves the address of the next instruction\nthat would otherwise execute (located at \\reg{pc}+4) into \n\\reg{rd} and then adds the immediate value to the \\reg{rs1} \nregister and stores the sum into the \\reg{pc} register causing\nan unconditional branch to take place.\n\nNote that the branch target address is calculated by \nsign-extending the imm[11:0] bits from the instruction, \nadding it to the \\reg{rs1} register and {\\em then} the \nLSB of the sum is to zero and the result is stored into the \n\\reg{pc} register.\nThe discarding of the LSB allows the branch to refer to any \neven address.\n\nThe standard software conventions for calling subroutines\nuse \\reg{x1} as the return address (\\reg{rd} register in this \ncase).~\\cite[p.~16]{rvismv1v22:2017}\n\n\nEncoding:\n\n\\DrawInsnTypeIPicture{JALR x1, x7, 4}{00000000010000111000000011100111}\n\nBefore:\n\npc = 0x11114444\\\\\nx7 = 0x44444444\n\nAfter\n\npc = 0x5555888c\\\\\nx1 = 0x11114448\n\nJALR provides a method to call a subroutine using a base-displacement address.\n\n\\DrawInsnTypeIPicture{JALR x1, x0, 5}{00000000010100000000000011100111}\n\nNote that the least significant bit in the result of rs1+imm is \ndiscarded/set to zero before the result is saved in the pc.\n \npc = 0x11114444\n\nAfter\n\npc = 0x00000004\\\\\nx1 = 0x11114448\n\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{BEQ rs1, rs2, imm}\n\\index{Instruction!BEQ}\n\nBranch if equal.\n\n\\verb@pc@ $\\leftarrow$ \\verb@(rs1 == rs2) ? pc+sx(imm[12:1]<<1) : pc+4@\n\nEncoding:\n\n\\DrawInsnTypeBPicture{BEQ x3, x15, 2064}{00000000111100011000100011100011}\n\nimm[12:1] = $010000001000_2 = 1032_{10}$\\\\\nimm = $2064_{10}$\\\\\nfunct3 = $000_2$\\\\\nrs1 = x3\\\\\nrs2 = x15\n\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{BNE rs1, rs2, imm}\n\\index{Instruction!BNE}\n\nBranch if Not Equal.\n\n\\verb@pc@ $\\leftarrow$ \\verb@(rs1 != rs2) ? pc+sx(imm[12:1]<<1) : pc+4@\n\nEncoding:\n\n\\DrawInsnTypeBPicture{BNE x3, x15, 2064}{00000000111100011001100011100011}\n\nimm[12:1] = $010000001000_2 = 1032_{10}$\\\\\nimm = $2064_{10}$\\\\\nfunct3 = $001_2$\\\\\nrs1 = x3\\\\\nrs2 = x15\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{BLT rs1, rs2, imm}\n\\index{Instruction!BLT}\n\nBranch if Less Than.\n\n\\verb@pc@ $\\leftarrow$ \\verb@(rs1 < rs2) ? pc+sx(imm[12:1]<<1) : pc+4@\n\nEncoding:\n\n\\DrawInsnTypeBPicture{BLT x3, x15, 2064}{00000000111100011100100011100011}\n\nimm[12:1] = $010000001000_2 = 1032_{10}$\\\\\nimm = $2064_{10}$\\\\\nfunct3 = $100_2$\\\\\nrs1 = x3\\\\\nrs2 = x15\n\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{BGE rs1, rs2, imm}\n\\index{Instruction!BGE}\n\nBranch if Greater or Equal.\n\n\\verb@pc@ $\\leftarrow$ \\verb@(rs1 >= rs2) ? pc+sx(imm[12:1]<<1) : pc+4@\n\nEncoding:\n\n\\DrawInsnTypeBPicture{BGE x3, x15, 2064}{00000000111100011101100011100011}\n\nimm[12:1] = $010000001000_2 = 1032_{10}$\\\\\nimm = $2064_{10}$\\\\\nfunct3 = $101_2$\\\\\nrs1 = x3\\\\\nrs2 = x15\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{BLTU rs1, rs2, imm}\n\\index{Instruction!BLTU}\n\nBranch if Less Than Unsigned.\n\n\\verb@pc@ $\\leftarrow$ \\verb@(rs1 < rs2) ? pc+sx(imm[12:1]<<1) : pc+4@\n\nEncoding:\n\n\\DrawInsnTypeBPicture{BLTU x3, x15, 2064}{00000000111100011110100011100011}\n\nimm[12:1] = $010000001000_2 = 1032_{10}$\\\\\nimm = $2064_{10}$\\\\\nfunct3 = $110_2$\\\\\nrs1 = x3\\\\\nrs2 = x15\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{BGEU rs1, rs2, imm}\n\\index{Instruction!BGEU}\n\nBranch if Greater or Equal Unsigned.\n\n\\verb@pc@ $\\leftarrow$ \\verb@(rs1 >= rs2) ? pc+sx(imm[12:1]<<1) : pc+4@\n\nEncoding:\n\n\\DrawInsnTypeBPicture{BGEU x3, x15, 2064}{00000000111100011111100011100011}\n\\enote{use symbols in branch examples}\n\nimm[12:1] = $010000001000_2 = 1032_{10}$\\\\\nimm = $2064_{10}$\\\\\nfunct3 = $111_2$\\\\\nrs1 = x3\\\\\nrs2 = x15\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{LB rd, imm(rs1)}\n\\index{Instruction!LB}\n\nLoad byte.\n\n\\verb@rd@ $\\leftarrow$ \\verb@sx(m8(rs1+sx(imm)))@\\\\\n\\verb@pc@ $\\leftarrow$ \\verb@pc+4@\n\nLoad an 8-bit value from memory at address \\verb@rs1+imm@, then \nsign-extend it to 32 bits before storing it in \\verb@rd@\n\n\nEncoding:\n\n\\DrawInsnTypeIPicture{LB x7, 4(x3)}{00000000010000011000001110000011}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{LH rd, imm(rs1)}\n\\index{Instruction!LH}\n\nLoad halfword.\n\n\\verb@rd@ $\\leftarrow$ \\verb@sx(m16(rs1+sx(imm)))@\\\\\n\\verb@pc@ $\\leftarrow$ \\verb@pc+4@\n\nLoad a 16-bit value from memory at address \\verb@rs1+imm@, then \nsign-extend it to 32 bits before storing it in \\verb@rd@\n\n\nEncoding:\n\n\\DrawInsnTypeIPicture{LH x7, 4(x3)}{00000000010000011001001110000011}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{LW rd, imm(rs1)}\n\\index{Instruction!LW}\n\nLoad word.\n\n\\verb@rd@ $\\leftarrow$ \\verb@sx(m32(rs1+sx(imm)))@\\\\\n\\verb@pc@ $\\leftarrow$ \\verb@pc+4@\n\nLoad a 32-bit value from memory at address \\verb@rs1+imm@, then \nstore it in \\verb@rd@\n\nEncoding:\n\n\\DrawInsnTypeIPicture{LW x7, 4(x3)}{00000000010000011010001110000011}\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{LBU rd, imm(rs1)}\n\\index{Instruction!LBU}\n\nLoad byte unsigned.\n\n\\verb@rd@ $\\leftarrow$ \\verb@zx(m8(rs1+sx(imm)))@\\\\\n\\verb@pc@ $\\leftarrow$ \\verb@pc+4@\n\nLoad an 8-bit value from memory at address \\verb@rs1+imm@, then \nzero-extend it to 32 bits before storing it in \\verb@rd@\n\nEncoding:\n\n\\DrawInsnTypeIPicture{LBU x7, 4(x3)}{00000000010000011100001110000011}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{LHU rd, imm(rs1)}\n\\index{Instruction!LHU}\n\nLoad halfword unsigned.\n\n\\verb@rd@ $\\leftarrow$ \\verb@zx(m16(rs1+sx(imm)))@\\\\\n\\verb@pc@ $\\leftarrow$ \\verb@pc+4@\n\nLoad an 16-bit value from memory at address \\verb@rs1+imm@, then \nzero-extend it to 32 bits before storing it in \\verb@rd@\n\nEncoding:\n\n\\DrawInsnTypeIPicture{LHU x7, 4(x3)}{00000000010000011101001110000011}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{SB rs2, imm(rs1)}\n\\index{Instruction!SB}\n\nStore Byte.\n\n\\verb@m8(rs1+sx(imm))@ $\\leftarrow$ \\verb@rs2[7:0]@\\\\\n\\verb@pc@ $\\leftarrow$ \\verb@pc+4@\n\nStore the 8-bit value in \\verb@rs2[7:0]@ into memory at \naddress \\verb@rs1+imm@.\n\nEncoding:\n\n\\DrawInsnTypeSPicture{SB x3, 19(x15)}{00000000111100011000100110100011}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{SH rs2, imm(rs1)}\n\\index{Instruction!SH}\n\nStore Halfword.\n\n\\verb@m16(rs1+sx(imm))@ $\\leftarrow$ \\verb@rs2[15:0]@\\\\\n\\verb@pc@ $\\leftarrow$ \\verb@pc+4@\n\nStore the 16-bit value in \\verb@rs2[15:0]@ into memory at \naddress \\verb@rs1+imm@.\n\n\nEncoding:\n\n\\DrawInsnTypeSPicture{SH x3, 19(x15)}{00000000111100011001100110100011}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{SW rs2, imm(rs1)}\n\\index{Instruction!SW}\n\nStore Word\n\n\\verb@m16(rs1+sx(imm))@ $\\leftarrow$ \\verb@rs2[31:0]@\\\\\n\\verb@pc@ $\\leftarrow$ \\verb@pc+4@\n\nStore the 32-bit value in \\verb@rs2@ into memory at address \\verb@rs1+imm@.\n\nEncoding:\n\n\\DrawInsnTypeSPicture{SW x3, 19(x15)}{00000000111100011010100110100011}\n\nShow pos \\& neg imm examples.\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{ADDI rd, rs1, imm}\n\\index{Instruction!ADDI}\n\nAdd Immediate\n\n\\verb@rd@ $\\leftarrow$ \\verb@rs1+sx(imm)@\\\\\n\\verb@pc@ $\\leftarrow$ \\verb@pc+4@\n\nEncoding:\n\n\\DrawInsnTypeIPicture{ADDI x1, x7, 4}{00000000010000111000000010010011}\n\nBefore:\n\nx7 = 0x11111111\n\nAfter:\n\nx1 = 0x11111115\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{SLTI rd, rs1, imm}\n\\index{Instruction!SLTI}\n\nSet LessThan Immediate\n\n\\verb@rd@ $\\leftarrow$ \\verb@(rs1 < sx(imm)) ? 1 : 0@\\\\\n\\verb@pc@ $\\leftarrow$ \\verb@pc+4@\n\nIf the sign-extended immediate value is less than the value\nin the \\reg{rs1} register then the value 1 is stored in the \n\\reg{rd} register. Otherwise the value 0 is stored in the\n\\reg{rd} register. \n\nEncoding:\n\n\\DrawInsnTypeIPicture{SLTI x1, x7, 4}{00000000010000111010000010010011}\n\nBefore:\n\nx7 = 0x11111111\n\nAfter:\n\nx1 = 0x00000000\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{SLTIU rd, rs1, imm}\n\\index{Instruction!SLTIU}\n\nSet LessThan Immediate Unsigned\n\n\\verb@rd@ $\\leftarrow$ \\verb@(rs1 < sx(imm)) ? 1 : 0@\\\\\n\\verb@pc@ $\\leftarrow$ \\verb@pc+4@\n\nIf the sign-extended immediate value is less than the value\nin the \\reg{rs1} register then the value 1 is stored in the \n\\reg{rd} register. Otherwise the value 0 is stored in the\n\\reg{rd} register. Both the immediate and \\reg{rs1} register\nvalues are treated as unsigned numbers for the purposes of the \ncomparison.\\footnote{The immediate value is first sign-extended to\nXLEN bits then treated as an unsigned number.\\cite[p.~14]{rvismv1v22:2017}}\n\n\nEncoding:\n\n\\DrawInsnTypeIPicture{SLTIU x1, x7, 4}{00000000010000111011000010010011}\n\nBefore:\n\nx7 = 0x81111111\n\nAfter:\n\nx1 = 0x00000001\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{XORI rd, rs1, imm}\n\\index{Instruction!XORI}\n\nExclusive Or Immediate\n\n\\verb@rd@ $\\leftarrow$ \\verb@rs1 ^ sx(imm)@\\\\\n\\verb@pc@ $\\leftarrow$ \\verb@pc+4@\n\nThe logical XOR of the sign-extended immediate value and the value \nin the \\reg{rs1} register is stored in the \\reg{rd} register.\n\nEncoding:\n\n\\DrawInsnTypeIPicture{XORI x1, x7, 4}{00000000010000111100000010010011}\n\nBefore:\n\nx7 = 0x81111111\n\nAfter:\n\nx1 = 0x81111115\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{ORI rd, rs1, imm}\n\\index{Instruction!ORI}\n\nOr Immediate\n\n\\verb@rd@ $\\leftarrow$ \\verb@rs1 | sx(imm)@\\\\\n\\verb@pc@ $\\leftarrow$ \\verb@pc+4@\n\nThe logical OR of the sign-extended immediate value and the value \nin the \\reg{rs1} register is stored in the \\reg{rd} register.\n\nEncoding:\n\n\\DrawInsnTypeIPicture{ORI x1, x7, 4}{00000000010000111110000010010011}\n\nBefore:\n\nx7 = 0x81111111\n\nAfter:\n\nx1 = 0x81111115\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{ANDI rd, rs1, imm}\n\\index{Instruction!ANDI}\n\nAnd Immediate\n\n\\verb@rd@ $\\leftarrow$ \\verb@rs1 & sx(imm)@\\\\\n\\verb@pc@ $\\leftarrow$ \\verb@pc+4@\n\nThe logical AND of the sign-extended immediate value and the value \nin the \\reg{rs1} register is stored in the \\reg{rd} register.\n\n\nEncoding:\n\n\\DrawInsnTypeIPicture{ANDI x1, x7, 4}{00000000010000111111000010010011}\n\nBefore:\n\nx7 = 0x81111111\n\nAfter:\n\nx1 = 0x81111115\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{SLLI rd, rs1, shamt}\n\\index{Instruction!SLLI}\n\nShift Left Logical Immediate\n\n\\verb@rd@ $\\leftarrow$ \\verb@rs1 << shamt@\\\\\n\\verb@pc@ $\\leftarrow$ \\verb@pc+4@\n\n\nSLLI is a logical left shift operation (zeros are shifted\ninto the lower bits). The value in rs1 shifted left shamt\nnumber of bits and the result placed into rd.~\\cite[p.~14]{rvismv1v22:2017}\n\nEncoding:\n\n\\DrawInsnTypeRShiftPicture{SLLI x7, x3, 2}{00000000001000011001001110100011}\n\nx3 = 0x81111111\n\nAfter:\n\nx7 = 0x04444444\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{SRLI rd, rs1, shamt}\n\\index{Instruction!SRLI}\n\nShift Right Logical Immediate\n\n\\verb@rd@ $\\leftarrow$ \\verb@rs1 >> shamt@\\\\\n\\verb@pc@ $\\leftarrow$ \\verb@pc+4@\n\nSRLI is a logical right shift operation (zeros are shifted\ninto the higher bits). The value in rs1 shifted right shamt\nnumber of bits and the result placed into rd.~\\cite[p.~14]{rvismv1v22:2017}\n\n\nEncoding:\n\n\\DrawInsnTypeRShiftPicture{SRLI x7, x3, 2}{00000000001000011101001110010011}\n\nx3 = 0x81111111\n\nAfter:\n\nx7 = 0x20444444\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{SRAI rd, rs1, shamt}\n\\index{Instruction!SRAI}\n\nShift Right Arithmetic Immediate\n\n\\verb@rd@ $\\leftarrow$ \\verb@rs1 >> shamt@\\\\\n\\verb@pc@ $\\leftarrow$ \\verb@pc+4@\n\nSRAI is a logical right shift operation (zeros are shifted\ninto the higher bits). The value in rs1 shifted right shamt\nnumber of bits and the result placed into rd.~\\cite[p.~14]{rvismv1v22:2017}\n\nEncoding:\n\n\\DrawInsnTypeRShiftPicture{SRAI x7, x3, 2}{01000000001000011101001110010011}\n\nx3 = 0x81111111\n\nAfter:\n\nx7 = 0xe0444444\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{ADD rd, rs1, rs2}\n\\index{Instruction!ADD}\n\nAdd \n\n\\verb@rd@ $\\leftarrow$ \\verb@rs1 + rs2@\\\\\n\\verb@pc@ $\\leftarrow$ \\verb@pc+4@\n\nADD performs addition. Overflows are ignored and the low 32 bits of \nthe result are written to rd.~\\cite[p.~15]{rvismv1v22:2017}\n\nEncoding:\n\n\\DrawInsnTypeRPicture{ADD x7, x3, x31}{00000001111100011000001110110011}\n\nx3 = 0x81111111\nx31 = 0x22222222\n\nAfter:\n\nx7 = 0xa3333333\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{SUB rd, rs1, rs2}\n\\index{Instruction!SUB}\n\nSubtract\n\n\\verb@rd@ $\\leftarrow$ \\verb@rs1 - rs2@\\\\\n\\verb@pc@ $\\leftarrow$ \\verb@pc+4@\n\nSUB performs subtraction. Underflows are ignored and the low 32 bits of \nthe result are written to rd.~\\cite[p.~15]{rvismv1v22:2017}\n\nEncoding:\n\n\\DrawInsnTypeRPicture{SUB x7, x3, x31}{01000001111100011000001110110011}\n\nx3 = 0x83333333\nx31 = 0x01111111\n\nAfter:\n\nx7 = 0x82222222\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{SLL rd, rs1, rs2}\n\\index{Instruction!SLL}\n\nShift Left Logical\n\n\\verb@rd@ $\\leftarrow$ \\verb@rs1 << rs2@\\\\\n\\verb@pc@ $\\leftarrow$ \\verb@pc+4@\n\nSLL performs a logical left shift on the value in register rs1 by \nthe shift amount held in the lower 5 bits of register rs2.~\\cite[p.~15]{rvismv1v22:2017}\n\nEncoding:\n\n\\DrawInsnTypeRPicture{SLL x7, x3, x31}{00000001111100011001001110110011}\n\nx3 = 0x83333333\\\\\nx31 = 0x00000002\n\nAfter:\n\nx7 = 0x0ccccccc\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{SLT rd, rs1, rs2}\n\\index{Instruction!SLT}\n\nSet Less Than\n\n\\verb@rd@ $\\leftarrow$ \\verb@(rs1 < rs2) ? 1 : 0@\\\\\n\\verb@pc@ $\\leftarrow$ \\verb@pc+4@\n\nSLT performs a signed compare, writing 1 to \\reg{rd} if \\reg{rs1} $<$ \\reg{rs2}, 0 \notherwise.~\\cite[p.~15]{rvismv1v22:2017}\n\nEncoding:\n\n\\DrawInsnTypeRPicture{SLT x7, x3, x31}{00000001111100011010001110110011}\n\nx3 = 0x83333333\\\\\nx31 = 0x00000002\n\nAfter:\n\nx7 = 0x00000001\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{SLTU rd, rs1, rs2}\n\\index{Instruction!SLTU}\n\nSet Less Than Unsigned \n\n\\verb@rd@ $\\leftarrow$ \\verb@(rs1 < rs2) ? 1 : 0@\\\\\n\\verb@pc@ $\\leftarrow$ \\verb@pc+4@\n\nSLTU performs an unsigned compare, writing 1 to \\reg{rd} if \\reg{rs1} $<$ \\reg{rs2}, 0 otherwise. \nNote, SLTU rd, x0, rs2 sets \\reg{rd} to 1 if \\reg{rs2} is not equal to zero, otherwise \nsets \\reg{rd} to zero (assembler pseudoinstruction \\verb@SNEZ rd, rs@).~\\cite[p.~15]{rvismv1v22:2017}\n\nEncoding:\n\n\\DrawInsnTypeRPicture{SLTU x7, x3, x31}{00000001111100011011001110110011}\n\nx3 = 0x83333333\\\\\nx31 = 0x00000002\n\nAfter:\n\nx7 = 0x00000000\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{XOR rd, rs1, rs2}\n\\index{Instruction!XOR}\n\nExclusive Or\n\n\\verb@rd@ $\\leftarrow$ \\verb@rs1 ^ rs2@\\\\\n\\verb@pc@ $\\leftarrow$ \\verb@pc+4@\n\nXOR performs a bit-wise exclusive or on rs1 and rs2. \nThe result is stored on rd.\n\nEncoding:\n\n\\DrawInsnTypeRPicture{XOR x7, x3, x31}{00000001111100011100001110110011}\n\nx3 = 0x83333333\\\\\nx31 = 0x1888ffff\n\nAfter:\n\nx7 = 0x9bbbcccc\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{SRL rd, rs1, rs2}\n\\index{Instruction!SRL}\n\nShift Right Logical\n\n\\verb@rd@ $\\leftarrow$ \\verb@rs1 >> rs2@\\\\\n\\verb@pc@ $\\leftarrow$ \\verb@pc+4@\n\nSRL performs a logical right shift on the value in register rs1 by \nthe shift amount held in the lower 5 bits of \nregister rs2.~\\cite[p.~15]{rvismv1v22:2017}\n\nEncoding:\n\n\\DrawInsnTypeRPicture{SRL x7, x3, x31}{00000001111100011101001110110011}\n\nx3 = 0x83333333\\\\\nx31 = 0x00000010\n\nAfter:\n\nx7 = 0x00008333\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{SRA rd, rs1, rs2}\n\\index{Instruction!SRA}\n\nShift Right Arithmetic\n\n\\verb@rd@ $\\leftarrow$ \\verb@rs1 >> rs2@\\\\\n\\verb@pc@ $\\leftarrow$ \\verb@pc+4@\n\nSRA performs an arithmetic right shift (the original sign bit is copied \ninto the vacated upper bits) on the value in register rs1 by the shift \namount held in the lower 5 bits of \nregister rs2.~\\cite[p.~14,~15]{rvismv1v22:2017}\n\nEncoding:\n\n\\DrawInsnTypeRPicture{SRA x7, x3, x31}{01000001111100011101001110110011}\n\nx3 = 0x83333333\\\\\nx31 = 0x00000010\n\nAfter:\n\nx7 = 0xffff8333\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{OR rd, rs1, rs2}\n\\index{Instruction!OR}\n\nOr \n\n\\verb@rd@ $\\leftarrow$ \\verb@rs1 | rs2@\\\\\n\\verb@pc@ $\\leftarrow$ \\verb@pc+4@\n\nOR is a logical operation that performs a bit-wise OR on \nregister rs1 and rs2 and then places the result \nin rd.~\\cite[p.~14]{rvismv1v22:2017}\n\nEncoding:\n\n\\DrawInsnTypeRPicture{OR x7, x3, x31}{00000001111100011101001110110011}\n\nx3 = 0x83333333\\\\\nx31 = 0x00000440\n\nAfter:\n\nx7 = 0x83333773\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{AND rd, rs1, rs2}\n\\index{Instruction!AND}\n\nAnd\n\n\\verb@rd@ $\\leftarrow$ \\verb@rs1 & rs2@\\\\\n\\verb@pc@ $\\leftarrow$ \\verb@pc+4@\n\nAND is a logical operation that performs a bit-wise AND on \nregister rs1 and rs2 and then places the result \nin rd.~\\cite[p.~14]{rvismv1v22:2017}\n\nEncoding:\n\n\\DrawInsnTypeRPicture{AND x7, x3, x31}{00000001111100011110001110110011}\n\nx3 = 0x83333333\\\\\nx31 = 0x00000fe2\n\nAfter:\n\nx7 = 0x00000322\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{FENCE predecessor, successor}\n\\index{Instruction!FENCE}\n\n\\enote{Which of the i, o, r and w goes into each bit? See what gas does.}%\nThe FENCE instruction is used to order device I/O and memory accesses as \nviewed by other RISC-V harts and external devices or co-processors. Any \ncombination of device input (I), device output (O), memory reads (R), \nand memory writes (W) may be ordered with respect to any combination\nof the same. Informally, no other RISC-V hart or external device can \nobserve any operation in the successor set following a FENCE before any \noperation in the predecessor set preceding the FENCE. The execution \nenvironment will define what I/O operations are possible, and in particular, \nwhich load and store instructions might be treated and ordered as device \ninput and device output operations respectively rather than memory reads \nand writes. For example, memory-mapped I/O devices will typically be \naccessed with uncached loads and stores that are ordered using the I and O\n bits rather than the R and W bits. Instruction-set extensions might \nalso describe new coprocessor I/O instructions that will also be ordered \nusing the I and O bits in a FENCE.~\\cite[p.~21]{rvismv1v22:2017}\n\nOperation:\n\n\\verb@pc@ $\\leftarrow$ \\verb@pc+4@\n\nEncoding:\n\n\\DrawInsnTypeFPicture{FENCE iorw, iorw}{00001111111100000000000000001111}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{FENCE.I}\n\\index{Instruction!FENCE.I}\n\nThe FENCE.I instruction is used to synchronize the instruction and \ndata streams. RISC-V does not guarantee that stores to instruction \nmemory will be made visible to instruction fetches on the same\nRISC-V hart until a FENCE.I instruction is executed. A FENCE.I \ninstruction only ensures that a subsequent instruction fetch on \na RISC-V hart will see any previous data stores already visible to \nthe same RISC-V hart. FENCE.I does not ensure that other RISC-V harts' \ninstruction fetches will observe the local hart's stores in a \nmultiprocessor system. To make a store to instruction memory\nvisible to all RISC-V harts, the writing hart has to execute a \ndata FENCE before requesting that all remote RISC-V harts execute \na FENCE.I.~\\cite[p.~21]{rvismv1v22:2017}\n\nOperation:\n\n\\verb@pc@ $\\leftarrow$ \\verb@pc+4@\n\nEncoding:\n\n\\DrawInsnTypeFPicture{FENCE.I}{00000000000000000001000000001111}\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{ECALL}\n\\index{Instruction!ECALL}\n\nThe ECALL instruction is used to make a request to the supporting \nexecution environment, which is usually an operating system. The ABI \nfor the system will define how parameters for the environment\nrequest are passed, but usually these will be in defined locations \nin the integer register file.~\\cite[p.~24]{rvismv1v22:2017}\n\n\\DrawInsnTypeEPicture{ECALL}{00000000000000000000000001110011}\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{EBREAK}\n\\index{Instruction!EBREAK}\n\nThe EBREAK instruction is used by debuggers to cause control to be \ntransferred back to a debugging environment.~\\cite[p.~24]{rvismv1v22:2017}\n\n\\DrawInsnTypeEPicture{EBREAK}{00000000000100000000000001110011}\n\n\n" }, { "path": "book/rv32/chapter.tex", "content": "\n\\newcommand\\instructionHeader[1]{{\\large\\tt \\string#1}}\n\n\\chapter{RV32 Machine Instructions}\n\\label{chapter:RV32}\n\\index{RV32}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\section{Conventions and Terminology}\n\nWhen discussing instructions, the following abbreviations/notations are used:\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{XLEN}\n\\label{XLEN}\n\n\nXLEN represents the bit-length of an \\reg{x} register in the machine architecture.\nPossible values are 32, 64 and 128.\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{sx(val)}\n\\label{extension:sx}\n\nSign extend {\\em val} to the left.\n\nThis is used to convert a signed integer value expressed using some number of \nbits to a larger number of bits by adding more bits to the left. In doing so, \nthe sign will be preserved. In this case {\\em val} represents the least \n\\acrshort{msb}s of the value. \n\nFor more on sign-extension see \\autoref{SignExtension}.\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{zx(val)}\n\\label{extension:zx}\n\nZero extend {\\em val} to the left.\n\nThis is used to convert an unsigned integer value expressed using some number of \nbits to a larger number of bits by adding more bits to the left. In doing so, \nthe new bits added will all be set to zero. As is the case with \\verb@sx(val)@,\n{\\em val} represents the \\acrshort{lsb}s of the final value. \n\nFor more on zero-extension see \\autoref{ZeroExtension}.\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{zr(val)}\n\\label{extension:zr}\n\nZero extend {\\em val} to the right.\n\nSome times a binary value is encoded such that a set of bits represented\nby {\\em val} are used to represent the \\acrshort{msb}s of some longer (more bits) \nvalue. \nIn this case it is necessary to append zeros to the right to convert \\verb@val@ to \nthe longer value.\n\n\\autoref{Figure:ZeroRightExtend} illustrates converting a 20-bit {\\em val} to\na 32-bit fullword.\n\n\\begin{figure}[ht]\n\\centering\n\\DrawBitBoxSignLeftZeroRightExtendedPicture{32}{01000000000000000010}{12}\n\\captionof{figure}{Zero-extending an integer to the right from 20 bits to 32 bits.}\n\\label{Figure:ZeroRightExtend}\n\\end{figure}\n\n%\\begin{figure}[ht]\n%\\centering\n%\\parbox{.7\\linewidth}{\n%\\DrawBitBoxUnsignedPicture{01000000000000000010}\\\\\n%\\DrawBitBoxUnsignedPicture{01000000000000000010000000000000}\n%}\n%\\captionof{figure}{Zero-extending an integer to the right from 20 bits to 32 bits.}\n%\\label{Figure:ZeroRightExtend}\n%\\end{figure}\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{Sign Extended Left and Zero Extend Right}\n\\label{extension:slzr}\n\nSome instructions such as the J-type (see \\autoref{insnformat:jtype}) include\nimmediate operands that are extended in both directions.\n\n\\autoref{Figure:slzrPositive} and \\autoref{Figure:slzrNegative}\nillustrates zero-extending a 20-bit negative number one bit to the right \nand sign-extending it 11 bits to the left:\n\n\\begin{figure}[ht]\n\\centering\n\\DrawBitBoxSignLeftZeroRightExtendedPicture{32}{01000100011101001001}{1}\n\\captionof{figure}{Sign-extending a positive 20-bit number \n11 bits to the left and one bit to the right.}\n\\label{Figure:slzrPositive}\n\\end{figure}\n\n\\begin{figure}[ht]\n\\centering\n\\DrawBitBoxSignLeftZeroRightExtendedPicture{32}{11000100011101001001}{1}\n\\captionof{figure}{Sign-extending a negative 20-bit number \n11 bits to the left and one bit to the right.}\n\\label{Figure:slzrNegative}\n\\end{figure}\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{m8(addr)}\n\\label{memory:m8}\n\nThe contents of an 8-bit value in memory at address {\\em addr}.\n\nGiven the contents of the memory dump shown in \n\\autoref{Figure:SampleMemoryContents}, \n\\verb@m8(0x42)@ refers to the memory location at address \\verb@42@$_{16}$ \nthat currently contains the 8-bit value \\verb@fc@$_{16}$.\n\nThe \\verb@m@$_n$\\verb@(addr)@ notation can be used to refer to memory that is being \nread or written depending on the context. \n\nWhen memory is being written, the following notation is used to indicate that \nthe least significant 8 bis of {\\em source} will be is written into memory at \nthe address {\\em addr}:\n\n\\verb@m8(addr)@ $\\leftarrow$ \\verb@source@\n\nWhen memory is being read, the following notation is used to indicate that the \n8 bit value at the address {\\em addr} will be read and stored into {\\em dest}:\n\n\\verb@dest@ $\\leftarrow$ \\verb@m8(addr)@ \n\nNote that {\\em source} and {\\em dest} are typically registers.\n \n\n\\begin{figure}[ht]\n\\centering\n\\begin{BVerbatim}\n\n\n00000030 2f 20 72 65 61 64 20 61 20 62 69 6e 61 72 79 20\n00000040 66 69 fc 65 20 66 69 6c 6c 65 64 20 77 69 74 68\n00000050 20 72 76 33 32 49 20 69 6e 73 74 72 75 63 74 69\n00000060 6f 6e 73 20 61 6e 64 20 66 65 65 64 20 74 68 65\n\\end{BVerbatim}\n\\captionof{figure}{Sample memory contents.}\n\\label{Figure:SampleMemoryContents}\n\\end{figure}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{m16(addr)}\n\\label{memory:m16}\n\nThe contents of an 16-bit little-endian value in memory at address {\\em addr}.\n\nGiven the contents of the memory dump shown in \n\\autoref{Figure:SampleMemoryContents}, \n\\verb@m16(0x42)@ refers to the memory location at address \\verb@42@$_{16}$\nthat currently contains \\verb@65fc@$_{16}$. See also~\\autoref{memory:m8}.\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{m32(addr)}\n\\label{memory:m32}\n\nThe contents of an 32-bit little-endian value in memory at address {\\em addr}.\n\nGiven the contents of the memory dump shown in\n\\autoref{Figure:SampleMemoryContents},\n\\verb@m32(0x42)@ refers to the memory location at address \\verb@42@$_{16}$\nthat currently contains \\verb@662065fc@$_{16}$.\nSee also~\\autoref{memory:m8}.\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{m64(addr)}\n\nThe contents of an 64-bit little-endian value in memory at address {\\em addr}.\n\nGiven the contents of the memory dump shown in \n\\autoref{Figure:SampleMemoryContents}, \n\\verb@m64(0x42)@ refers to the memory location at address \\verb@42@$_{16}$\nthat currently contains \\verb@656c6c69662065fc@$_{16}$.\nSee also~\\autoref{memory:m8}.\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{m128(addr)}\n\nThe contents of an 128-bit little-endian value in memory at \naddress {\\em addr}.\n\nGiven the contents of the memory dump shown in \n\\autoref{Figure:SampleMemoryContents}, \n\\verb@m128(0x42)@ refers to the memory location at address \\verb@42@$_{16}$\nthat currently contains \\verb@7220687469772064656c6c69662065fc@$_{16}$.\nSee also~\\autoref{memory:m8}.\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{.+offset}\n\nThe address of the current instruction plus a numeric offset.\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{.-offset}\n\nThe address of the current instruction minus a numeric offset.\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{pcrel\\_13}\n\\label{pcrel.13}\n\nAn address that is within $[-4096..4094]$ $[$\\verb@-0x1000..0x0ffe@$]$ of the current instruction location.\nThese addresses are typically expressed in assembly source code by using labels.\nSee \\autoref{insnformat:btype} for examples.\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{pcrel\\_21}\n\\label{pcrel.21}\n\nAn address that is within $[-1048576..1048574]$ $[$\\verb@-0x100000..0x0ffffe@$]$ of the current instruction \nlocation. \nThese addresses are typically expressed in assembly source code by using labels.\nSee \\autoref{insnformat:jtype} for an example.\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{pc}\n\nThe current value of the program counter.\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{rd}\n\nAn x-register used to store the result of instruction.\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{rs1}\n\nAn x-register value used as a source operand for an instruction.\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{rs2}\n\nAn x-register value used as a source operand for an instruction.\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{imm}\n\nAn immediate numeric operand. The word {\\em immediate} refers\nto the fact that the operand is stored within an instruction.\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{rsN[h:l]}\n\nThe value of bits from {\\em h} through {\\em l} of x-register rsN.\nFor example: rs1[15:0] refers to the contents of \nthe 16 \\acrshort{lsb}s of rs1.\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\section{Addressing Modes}\n\nimmediate, register, base-displacement, pc-relative\n\\enote{Write this section.}\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\section{Instruction Encoding Formats}\n\\label{section:EncodingFormats}\n\n\n%XXX Show and discuss a stack of formats explaining how the unnatural ordering\n%of the {\\em imm} fields reduces the number of possible locations that \n%the hardware has to be prepared to {\\em look} for various bits. For example,\n%the opcode, rd, rs1, rs1, func3 and the sign bit (when used) are all always \n%in the same position. Also note that imm[19:12] and imm[10:5] can only be \n%found in one place. imm[4:0] can only be found in one of two places\\ldots\n\n\n\nThis document concerns itself with the RISC-V instruction formats shown \nin \\autoref{Figure:riscvFormats}.\n\n%\\autoref{Figure:riscvFormats} Shows the RISC-V instruction formats.\n\n\\begin{figure}[ht]\n\\DrawInsnTypeUTikz{00000000000000000000000000000000}\\\\\n\\DrawInsnTypeJTikz{00000000000000000000000000000000}\\\\\n\\DrawInsnTypeRTikz{00000000000000000000000000000000}\n\\DrawInsnTypeITikz{00000000000000000000000000000000}\\\\\n\\DrawInsnTypeIShiftTikz{00000000000000000000000000000000}\\\\\n\\DrawInsnTypeSTikz{00000000000000000000000000000000}\\\\\n\\DrawInsnTypeBTikz{00000000000000000000000000000000}\\\\\n\\captionof{figure}{RISC-V instruction formats.}\n\\label{Figure:riscvFormats}\n\\end{figure}\n\nThe method/format of the instructions has been designed with an eye on \nthe ease of future manufacture of the machine that will execute them. It is \neasier to build a machine if it does not have to accommodate many different \nways to perform the same task. The result is that a machine can be \nbuilt with fewer gates, consumes less power, and can run faster than\nif it were built when a priority is on how a user might prefer to decode\nthe same instructions from a hex dump.\n\nObserve that all instructions have their opcode in bits 0-6 and when they\ninclude an \\verb@rd@ register it will be specified in bits 7-11, \nan \\verb@rs1@ register in bits 15-19, an \\verb@rs2@ register in bits 20-24,\nand so on. This has a seemingly strange impact on the placement of any \nimmediate operands.\n\nWhen immediate operands are present in an instruction, they are placed in\nthe remaining unused bits. However, they are organized such that\nthe sign bit is {\\em always} in bit 31 and the remaining bits placed so\nas to minimize the number of places any given bit is located in different\ninstructions. \n\nFor example, consider immediate operand bits 12-19. In the U-type format\nthey are in bit positions 12-19. In the J-type format they are also in positions\n12-19. In the J-type format immediate operand bits 1-10 are in the same \ninstruction bit positions as they are in the I-type format and immediate\noperand bits 5-10 are in the same positions as they are in the B-type and\nS-type formats.\n\nWhile this is inconvenient for anyone looking at a memory hexdump, it does\nmake sense when considering the impact of this choice on the number of\ngates needed to implement circuitry to extract the immediate operands. \n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{U Type}\n\\label{insnformat:utype}\n\nThe U-Type format is used for instructions that use a 20-bit immediate operand \nand an \\verb@rd@ destination register.\n \n%\\DrawInsnTypeUTikz{11010110000000000011001010110111}\n\nThe \\reg{rd} field contains an \\reg{x} register number to be set to a value that\ndepends on the instruction.\n\n%The imm field \n%contains a 20-bit value that will be converted into \\Gls{xlen} bits by \n%using the {\\em imm} operand for bits 31:12 and then sign-extending it \n%to the left\\footnote{When XLEN is larger than 32.} and zero-extending \n%the LSBs as discussed in \\autoref{extension:zr}.\n\nIf \\Gls{xlen}=32 then the {\\em imm} value will extracted from the instruction\nand converted as shown in \\autoref{Figure:u_type_decode} to form the\n\\verb@imm_u@ value.\n\n\\begin{figure}[ht]\n\\centering\n\\DrawInsnOpUTypeDecoding\n\\captionof{figure}{Decoding a U-type instruction.}\n\\label{Figure:u_type_decode}\n\\label{imm.u:decode}\n\\index{imm\\protect\\_u}\n\\end{figure}\n\nNotice that the 20-bits of the imm field are mapped in the same order and \nin the same relative position that they appear in the instruction when \nthey are used to create the value of the immediate operand. \nLeaving the imm bits on the left, in the ``upper bits'' of the \\verb@imm_u@ \nvalue suggests a rationale for the name of this format.\n\n\\begin{itemize}\n\\item\\instructionHeader{lui\\ \\ \\ rd,imm}\n\\label{insn:lui}\n\nSet register \\verb@rd@ to the \\verb@imm_u@ value as shown in \\autoref{Figure:u_type_decode}. \n\nFor example: \\verb@lui x23,0x12345@ will result in setting register \\verb@x23@ to \nthe value \\verb@0x12345000@.\n\n\\item\\instructionHeader{auipc rd,imm}\n\\label{insn:auipc}\n\nAdd the address of the instruction to the \\verb@imm_u@ value as \nshown \\autoref{Figure:u_type_decode} and store the result in register \\verb@rd@.\n\nFor example, if the instruction \\verb@auipc x22,0x10001@ is executed from\nmemory address \\verb@0x800012f4@ then register \\verb@x22@ will be set to \n\\verb@0x900022f4@.\n\\end{itemize}\n\n\nIf \\Gls{xlen}=64 then the \\verb@imm_u@ value in this example will be converted \nto the same two's complement integer value by extending the sign-bit \nfurther to the left.\n\n\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{J Type}\n\\label{insnformat:jtype}\n\nThe J-type instruction format is used to encode the \\verb@jal@ instruction \nwith an immediate value that determines the jump target address.\nIt is similar to the U-type, but the bits in the immediate operand are \narranged in a different order.\n\n%\\DrawInsnTypeJTikz{00111001001110000001001111101111}\n\nNote that the \\verb@imm_j@ value is \n%expressed in the instruction as a target address that is converted to \nan even 21-bit value in the range of \n$[-1048576..1048574]$ $[$\\verb@-0x100000..0x0ffffe@$]$ representing a \\verb@pc@-relative offset to the \ntarget address. \n\n%In the J-type format the 20 {\\em imm} bits are arranged such \n%that they represent the ``lower'' portion of the immediate value. Unlike \n%the U-type instructions, the J-type requires the bits to be re-ordered \n%and shifted to the right before they are used.\n%\\footnote{The reason that the J-type \n%bits are reordered like this is because it simplifies the implementation of \n%hardware as discussed in \\autoref{section:EncodingFormats}.}\n\n%The example above shows that the bit positions in the {\\em imm} field \n%description. We see that the 20 {\\em imm} bits are re-ordered according to: \n%[20\\textbar10:1\\textbar11\\textbar19:12]. \n%This means that the \\acrshort{msb} of the {\\em imm} field is to be placed \n%into bit 20 of the immediate integer value ultimately used by the instruction \n%when it is converted into \\Gls{xlen} bits. \n%The next bit to the right in the {\\em imm} field is to be placed into bit 10 of \n%the immediate value and so on.\n\n%After the {\\em imm} bits are re-positioned into bits 20:1 of the immediate value\n%being constructed, a zero-bit will be added to the \\acrshort{lsb} \n%and the value in bit-position 20 will be replicated to sign-extend the \n%value to \\Gls{xlen} bits as discussed in \\autoref{extension:slzr}.\n\nIf \\Gls{xlen}=32 then the {\\em imm} value will extracted from the \ninstruction and converted as shown in \\autoref{Figure:j_type_decode} to\nform the \\verb@imm_j@ value.\n\n\\begin{figure}[ht]\n\\centering\n\\DrawInsnOpJTypeDecoding\n\\captionof{figure}{Decoding a J-type instruction.}\n\\label{Figure:j_type_decode}\n\\label{imm.j:decode}\n\\index{imm\\protect\\_j}\n\\end{figure}\n\n\n%\\DrawBitBoxSignLeftZeroRightExtendedPicture{32}{01000000110111001001}{1}\n%\n%A J-type example with a negative imm field:\n%\n%\\DrawInsnTypeJTikz{10111001001110000001001111101111}\n%\n%If \\Gls{xlen}=32 then the {\\em imm} field in this example will be converted as \n%shown below.\n%\n%\\DrawBitBoxSignLeftZeroRightExtendedPicture{32}{11000000110111001001}{1}\n\nThe J-type format is used by the Jump And Link instruction that calculates \nthe target address by adding \\verb@imm_j@ to the current program \ncounter. Since no instruction can be placed at an odd address the 20-bit \nimm value is zero-extended to the right to represent a 21-bit signed offset \ncapable of expressing a wider range of target addresses than the 20-bit \nimm value alone.\n\n\\begin{itemize}\n\\item\\instructionHeader{jal\\ \\ \\ rd,pcrel\\_21}\n\\label{insn:jal}\n\nSet register \\verb@rd@ to the address of the next instruction that would \notherwise be executed (the address of the \\verb@jal@ instruction + 4) and then\njump to the address given by the sum of the \\verb@pc@ register and the \n\\verb@imm_j@ value as decoded from the instruction shown in \n\\autoref{imm.j:decode}.\n\nNote that \\verb@pcrel_21@ is expressed in the instruction as a target address \nor label that is converted to a 21-bit value representing a \\verb@pc@-relative \noffset to the target address. \nFor example, consider the \\verb@jal@ instructions in the following code:\n\n\\begin{verbatim}\n00000010: 000002ef jal x5,0x10 # jump to self (address 0x10)\n00000014: 008002ef jal x5,0x1c # jump to address 0x1c\n00000018: 00100073 ebreak \n0000001c: 00100073 ebreak \n\\end{verbatim}\n\nThe instruction at address \\verb@0x10@ has a target address of \\verb@0x10@\nand the \\verb@imm_j@ is zero because offset from the ``current instruction''\nto the target is zero.\n\nThe instruction at address \\verb@0x14@ has a target address of \\verb@0x1c@\nand the \\verb@imm_j@ is \\verb@0x08@ because \\verb@0x1c - 0x14 = 0x08@.\n\nSee also \\autoref{insnformat:btype}.\n\n\\end{itemize}\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{R Type}\n\\label{insnformat:rtype}\n\\DrawInsnTypeRTikz{01000001111100011000001110110011}\n\nThe R-type instructions are used for operations that set a destination \nregister \\verb@rd@ to the result of an arithmetic, logical or shift operation\napplied to source registers \\verb@rs1@ and \\verb@rs2@.\n\nNote that instruction bit 30 (part of the the \\verb@funct7@ field) \nis used to select between the \\verb@add@ and \\verb@sub@ instructions \nas well as to select between \\verb@srl@ and \\verb@sra@.\n\n\\begin{itemize}\n\\item\\instructionHeader{add\\ \\ \\ rd,rs1,rs2}\n\\label{insn:add}\n\nSet register \\verb@rd@ to \\verb@rs1 + rs2@.\n\nNote that the value of \\verb@funct7@ must be zero for this instruction.\n(The value of \\verb@funct7@ is how the \\verb@add@ instruction is differentiated \nfrom the \\verb@sub@ instruction.)\n\n\\item\\instructionHeader{and\\ \\ \\ rd,rs1,rs2}\n\\label{insn:and}\n\nSet register \\verb@rd@ to the bitwise \\verb@and@ of \\verb@rs1@ and \\verb@rs2@.\n\nFor example, if \\verb@x17@ = \\verb@0x55551111@ and \\verb@x18@ = \\verb@0xff00ff00@\nthen the instruction \\verb@and x12,x17,x18@ will set \\verb@x12@ to the\nvalue \\verb@0x55001100@.\n\n\\item\\instructionHeader{or\\ \\ \\ \\ rd,rs1,rs2}\n\\label{insn:or}\n\nSet register \\verb@rd@ to the bitwise \\verb@or@ of \\verb@rs1@ and \\verb@rs2@.\n\nFor example, if \\verb@x17@ = \\verb@0x55551111@ and \\verb@x18@ = \\verb@0xff00ff00@\nthen the instruction \\verb@or x12,x17,x18@ will set \\verb@x12@ to the\nvalue \\verb@0xff55ff11@.\n\n\\item\\instructionHeader{sll\\ \\ \\ rd,rs1,rs2}\n\\label{insn:sll}\n\nShift \\verb@rs1@ left by the number of bits specified in the least significant\n5 bits of \\verb@rs2@ and store the result in \\verb@rd@.\\footnote{\\label{shift:xlen}\nWhen XLEN is 64 or 128, the shift distance will be given by the least-significant \n6 or 7 bits of {\\tt rs2} respectively. \nFor more information on how shifting works, see \\autoref{shifting}.}\n\nFor example, if \\verb@x17@ = \\verb@0x12345678@ and \\verb@x18@ = \\verb@0x08@\nthen the instruction \\verb@sll x12,x17,x18@ will set \\verb@x12@ to the\nvalue \\verb@0x34567800@.\n\n\\item\\instructionHeader{slt\\ \\ \\ rd,rs1,rs2}\n\\label{insn:slt}\n\nIf the signed integer value in \\verb@rs1@ is less than the\nsigned integer value in \\verb@rs2@ then set \\verb@rd@ to \\verb@1@.\nOtherwise, set \\verb@rd@ to \\verb@0@.\n\nFor example, if \\verb@x17@ = \\verb@0x12345678@ and \\verb@x18@ = \\verb@0x0000ffff@\nthen the instruction \\verb@slt x12,x17,x18@ will set \\verb@x12@ to the\nvalue \\verb@0x00000000@.\n\nIf \\verb@x17@ = \\verb@0x82345678@ and \\verb@x18@ = \\verb@0x0000ffff@\nthen the instruction \\verb@slt x12,x17,x18@ will set \\verb@x12@ to the\nvalue \\verb@0x00000001@.\n\n\\item\\instructionHeader{sltu\\ \\ rd,rs1,rs2}\n\\label{insn:sltu}\n\nIf the unsigned integer value in \\verb@rs1@ is less than the\nunsigned integer value in \\verb@rs2@ then set \\verb@rd@ to \\verb@1@.\nOtherwise, set \\verb@rd@ to \\verb@0@.\n\nFor example, if \\verb@x17@ = \\verb@0x12345678@ and \\verb@x18@ = \\verb@0x0000ffff@\nthen the instruction \\verb@sltu x12,x17,x18@ will set \\verb@x12@ to the\nvalue \\verb@0x00000000@.\n\nIf \\verb@x17@ = \\verb@0x12345678@ and \\verb@x18@ = \\verb@0x8000ffff@\nthen the instruction \\verb@sltu x12,x17,x18@ will set \\verb@x12@ to the\nvalue \\verb@0x00000001@.\n\n\\item\\instructionHeader{sra\\ \\ \\ rd,rs1,rs2}\n\\label{insn:sra}\n\nArithmetic-shift \\verb@rs1@ right by the number of bits given in the least-significant \n5 bits of the \\verb@rs2@ register and store the result in \n\\verb@rd@.\\footref{shift:xlen}\n\nFor example, if \\verb@x17@ = \\verb@0x87654321@ and \\verb@x18@ = \\verb@0x08@\nthen the instruction \\verb@sra x12,x17,x18@ will set \\verb@x12@ to the\nvalue \\verb@0xff876543@.\n\nIf \\verb@x17@ = \\verb@0x76543210@ and \\verb@x18@ = \\verb@0x08@\nthen the instruction \\verb@sra x12,x17,x18@ will set \\verb@x12@ to the\nvalue \\verb@0x00765432@.\n\nNote that the value of \\verb@funct7@ must be zero for this instruction.\n(The value of \\verb@funct7@ is how the \\verb@sra@ instruction is differentiated \nfrom the \\verb@srl@ instruction.)\n\n\\item\\instructionHeader{srl\\ \\ \\ rd,rs1,rs2}\n\\label{insn:srl}\n\nLogic-shift \\verb@rs1@ right by the number of bits given in the least-significant \n5 bits of the \\verb@rs2@ register and store the result in \n\\verb@rd@.\\footref{shift:xlen}\n\nFor example, if \\verb@x17@ = \\verb@0x87654321@ and \\verb@x18@ = \\verb@0x08@\nthen the instruction \\verb@srl x12,x17,x18@ will set \\verb@x12@ to the\nvalue \\verb@0x00876543@.\n\nIf \\verb@x17@ = \\verb@0x76543210@ and \\verb@x18@ = \\verb@0x08@\nthen the instruction \\verb@srl x12,x17,x18@ will set \\verb@x12@ to the\nvalue \\verb@0x00765432@.\n\nNote that the value of \\verb@funct7@ must be \\verb@0b0100000@ for this instruction.\n(The value of \\verb@funct7@ is how the \\verb@srl@ instruction is differentiated \nfrom the \\verb@sra@ instruction.)\n\n\\item\\instructionHeader{sub\\ \\ \\ rd,rs1,rs2}\n\\label{insn:sub}\n\nSet register \\verb@rd@ to \\verb@rs1 - rs2@.\n\nNote that the value of \\verb@funct7@ must be \\verb@0b0100000@ for this instruction.\n(The value of \\verb@funct7@ is how the \\verb@sub@ instruction is differentiated \nfrom the \\verb@add@ instruction.)\n\n\\item\\instructionHeader{xor\\ \\ \\ rd,rs1,rs2}\n\\label{insn:xor}\n\nSet register \\verb@rd@ to the bitwise \\verb@xor@ of \\verb@rs1@ and \\verb@rs2@.\n\nFor example, if \\verb@x17@ = \\verb@0x55551111@ and \\verb@x18@ = \\verb@0xff00ff00@\nthen the instruction \\verb@xor x12,x17,x18@ will set \\verb@x12@ to the\nvalue \\verb@0xaa55ee11@.\n\n\\end{itemize}\n\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{I Type}\n\\label{insnformat:itype}\n%\\DrawInsnTypeITikz{00000000010000011000001110000011}\n\nThe I-type instruction format is used to encode instructions with a\nsigned 12-bit immediate operand with a range of $[-2048..2047]$,\nan \\verb@rd@ register, and an \\verb@rs1@ register.\n\nIf \\Gls{xlen}=32 then the 12-bit {\\em imm} value example will extracted from \nthe instruction and converted as shown in \\autoref{Figure:i_type_decode}\nto form the \\verb@imm_i@ value.\n\n\\begin{figure}[ht]\n\\centering\n\\DrawInsnOpITypeDecoding\n\\captionof{figure}{Decoding an I-type Instruction.}\n\\label{Figure:i_type_decode}\n\\label{imm.i:decode}\n\\index{imm\\protect\\_i}\n\\end{figure}\n\nA special case of the I-type is used for shift-immediate instructions \nwhere the imm field is used to represent the number of bit positions \nto shift as shown in \\autoref{Figure:shamt_i_type_decode}.\nIn this variation, the least significant five bits of the imm field are \nextracted to form the \\verb@shamt_i@ \nvalue.\\footnote{When XLEN is 64 or 128, the {\\tt shamt\\_i} field will \nconsist of 6 or 7 bits respectively.}\n\nNote also that bit 30 (the imm instruction field bit labeled `\\verb@b@') is used to select \nbetween arithmetic and logical shifting.\n\n\\begin{figure}[ht]\n\\centering\n\\DrawInsnOpIShiftTypeDecoding\n\\captionof{figure}{Decoding an I-type Shift Instruction.}\n\\label{Figure:shamt_i_type_decode}\n\\label{shamt.i:decode}\n\\index{shamt\\protect\\_i}\n\\end{figure}\n\n\n\\begin{figure}[ht]\n\\centering\n\\begin{verbatim}\n 00002640: 6f 00 00 00 6f 00 00 00 b7 87 00 00 03 a5 07 43 *o...o..........C*\n 00002650: 67 80 00 00 00 00 00 00 76 61 6c 3d 00 00 00 00 *g.......val=....*\n 00002660: 00 00 00 00 80 84 2e 41 1f 85 45 41 80 40 9a 44 *.......A..EA.@.D*\n 00002670: 4f 11 f3 c3 6e 8a 67 41 20 1b 00 00 20 1b 00 00 *O...n.gA ... ...*\n 00002680: 44 1b 00 00 14 1b 00 00 14 1b 00 00 04 1c 00 00 *D...............*\n\\end{verbatim}\n\\captionof{figure}{An Example Memory Dump.}\n\\label{Figure:imm:memory:dump}\n\\end{figure}\n\n\n\\begin{itemize}\n\\item\\instructionHeader{addi\\ \\ rd,rs1,imm}\n\\label{insn:addi}\n\nSet register \\verb@rd@ to \\verb@rs1 + imm_i@.\n\n\\item\\instructionHeader{andi\\ \\ rd,rs1,imm}\n\\label{insn:andi}\n\nSet register \\verb@rd@ to the bitwise \\verb@and@ of \\verb@rs1@ and \\verb@imm_i@.\n\nFor example, if \\verb@x17@ = \\verb@0x55551111@ then the instruction \n\\verb@andi x12,x17,0x0ff@ will set \\verb@x12@ to the value \\verb@0x00000011@.\n\nRecall that \\verb@imm@ is sign-extended. \nTherefore if \\verb@x17@ = \\verb@0x55551111@ then the instruction \n\\verb@andi x12,x17,0x800@ will set \\verb@x12@ to the value \\verb@0x55551000@.\n\n\\item\\instructionHeader{jalr\\ \\ rd,imm(rs1)}\n\\label{insn:jalr}\n\nSet register \\verb@rd@ to the address of the next instruction that would \notherwise be executed (the address of the \\verb@jalr@ instruction + 4) and then \njump to an address given by the sum of the \\verb@rs1@ register and the \n\\verb@imm_i@ value as decoded from the instruction shown in \\autoref{imm.i:decode}.\n\nNote that the \\verb@pc@ register can never refer to an odd address. \nThis instruction will explicitly set the \\acrshort{lsb} to zero regardless\nof the value of the value of the calculated target address.\n\n\\item\\instructionHeader{lb\\ \\ \\ \\ rd,imm(rs1)}\n\\label{insn:lb}\n\nSet register \\verb@rd@ to the value of the sign-extended byte fetched from \nthe memory address given by the sum of \\verb@rs1@ and \\verb@imm_i@.\n\nFor example, given the memory contents shown in \\autoref{Figure:imm:memory:dump},\nif register \\verb@x13@ = \\verb@0x00002650@ then the instruction\n\\verb@lb x12,1(x13)@ will set \\verb@x12@ to the value \\verb@0xffffff80@.\n\n\\item\\instructionHeader{lbu\\ \\ \\ rd,imm(rs1)}\n\\label{insn:lbu}\n\nSet register \\verb@rd@ to the value of the zero-extended byte fetched from \nthe memory address given by the sum of \\verb@rs1@ and \\verb@imm_i@.\n\nFor example, given the memory contents shown in \\autoref{Figure:imm:memory:dump},\nif register \\verb@x13@ = \\verb@0x00002650@ then the instruction\n\\verb@lbu x12,1(x13)@ will set \\verb@x12@ to the value \\verb@0x00000080@.\n\n\\item\\instructionHeader{lh\\ \\ \\ \\ rd,imm(rs1)}\n\\label{insn:lh}\n\nSet register \\verb@rd@ to the value of the sign-extended 16-bit little-endian \nhalf-word value fetched from the memory address given by the sum \nof \\verb@rs1@ and \\verb@imm_i@.\n\nFor example, given the memory contents shown in \\autoref{Figure:imm:memory:dump},\nif register \\verb@x13@ = \\verb@0x00002650@ then the instruction\n\\verb@lh x12,-2(x13)@ will set \\verb@x12@ to the value \\verb@0x00004307@.\n\nIf register \\verb@x13@ = \\verb@0x00002650@ then the instruction\n\\verb@lh x12,-8(x13)@ will set \\verb@x12@ to the value \\verb@0xffff87b7@.\n\n\\item\\instructionHeader{lhu\\ \\ \\ rd,imm(rs1)}\n\\label{insn:lhu}\n\nSet register \\verb@rd@ to the value of the zero-extended 16-bit little-endian \nhalf-word value fetched from the memory address given by the sum \nof \\verb@rs1@ and \\verb@imm_i@.\n\nFor example, given the memory contents shown in \\autoref{Figure:imm:memory:dump},\nif register \\verb@x13@ = \\verb@0x00002650@ then the instruction\n\\verb@lhu x12,-2(x13)@ will set \\verb@x12@ to the value \\verb@0x00004307@.\n\nIf register \\verb@x13@ = \\verb@0x00002650@ then the instruction\n\\verb@lhu x12,-8(x13)@ will set \\verb@x12@ to the value \\verb@0x000087b7@.\n\n\\item\\instructionHeader{lw\\ \\ \\ \\ rd,imm(rs1)}\n\\label{insn:lw}\n\nSet register \\verb@rd@ to the value of the sign-extended 32-bit little-endian \nword value fetched from the memory address given by the sum \nof \\verb@rs1@ and \\verb@imm_i@.\n\nFor example, given the memory contents shown in \\autoref{Figure:imm:memory:dump},\nif register \\verb@x13@ = \\verb@0x00002650@ then the instruction\n\\verb@lw x12,-4(x13)@ will set \\verb@x12@ to the value \\verb@4307a503@.\n\n\n\\item\\instructionHeader{ori\\ \\ \\ rd,rs1,imm}\n\\label{insn:ori}\n\nSet register \\verb@rd@ to the bitwise \\verb@or@ of \\verb@rs1@ and \\verb@imm_i@.\n\nFor example, if \\verb@x17@ = \\verb@0x55551111@ then the instruction \n\\verb@ori x12,x17,0x0ff@ will set \\verb@x12@ to the value \\verb@0x555511ff@.\n\nRecall that \\verb@imm@ is sign-extended.\nTherefore if \\verb@x17@ = \\verb@0x55551111@ then the instruction \n\\verb@ori x12,x17,0x800@ will set \\verb@x12@ to the value \\verb@0xfffff911@.\n\n\\item\\instructionHeader{slli\\ \\ rd,rs1,imm}\n\\label{insn:slli}\n\nShift \\verb@rs1@ left by the number of bits specified in \\verb@shamt_i@ \n(as shown in \\autoref{shamt.i:decode})\nand store the result in \\verb@rd@.\\footnote{\\label{shifti:xlen}\nWhen XLEN is 64 or 128, the shift distance will be given by the least-significant \n6 or 7 bits of the imm field respectively. \nFor more information on how shifting works, see \\autoref{shifting}.}\n\nFor example, if \\verb@x17@ = \\verb@0x12345678@ then the instruction \n\\verb@slli x12,x17,4@ will set \\verb@x12@ to the value \\verb@0x23456780@.\n\n\\item\\instructionHeader{slti\\ \\ rd,rs1,imm}\n\\label{insn:slti}\n\nIf the signed integer value in \\verb@rs1@ is less than the\nsigned integer value in \\verb@imm_i@ then set \\verb@rd@ to \\verb@1@.\nOtherwise, set \\verb@rd@ to \\verb@0@.\n\n\\item\\instructionHeader{sltiu\\ rd,rs1,imm}\n\\label{insn:sltiu}\n\nIf the unsigned integer value in \\verb@rs1@ is less than the\nunsigned integer value in \\verb@imm_i@ then set \\verb@rd@ to \\verb@1@.\nOtherwise, set \\verb@rd@ to \\verb@0@.\n\nNote that \\verb@imm_i@ is always created by sign-extending the \\verb@imm@ value \nas shown in \\autoref{imm.i:decode} even though it is then later used as an unsigned \ninteger for the purposes of comparing its magnitude to the unsigned value in rs1. \nTherefore, this instruction provides a method to compare \\verb@rs1@ to a value \nin the ranges of \n$[\\text{\\tt 0}..\\text{\\tt 0x7ff}]$ and $[\\text{\\tt 0xfffff800}..\\text{\\tt 0xffffffff}]$.\n\n\\item\\instructionHeader{srai\\ \\ rd,rs1,imm}\n\\label{insn:srai}\n\nArithmetic-shift \\verb@rs1@ right by the number of bits specified in \\verb@shamt_i@ \n(as shown in \\autoref{shamt.i:decode})\nand store the result in \\verb@rd@.\\footref{shifti:xlen}\n\nFor example, if \\verb@x17@ = \\verb@0x87654321@ then the instruction \n\\verb@srai x12,x17,4@ will set \\verb@x12@ to the value \\verb@0xf8765432@.\n\nNote that the value of bit 30 must be 1 for this instruction.\n(The value of bit 30 is how the \\verb@srai@ instruction is differentiated \nfrom the \\verb@srli@ instruction.)\n\n\\item\\instructionHeader{srli\\ \\ rd,rs1,imm}\n\\label{insn:srli}\n\nLogic-shift \\verb@rs1@ right by the number of bits specified in \\verb@shamt_i@ \n(as shown in \\autoref{shamt.i:decode})\nand store the result in \\verb@rd@.\\footref{shifti:xlen}\n\nFor example, if \\verb@x17@ = \\verb@0x87654321@ then the instruction \n\\verb@srli x12,x17,4@ will set \\verb@x12@ to the value \\verb@0x08765432@.\n\nNote that the value of bit 30 must be 0 for this instruction.\n(The value of bit 30 is how the \\verb@srli@ instruction is differentiated \nfrom the \\verb@srai@ instruction.)\n\n\\item\\instructionHeader{xori\\ \\ rd,rs1,imm}\n\\label{insn:xori}\n\nSet register \\verb@rd@ to the bitwise \\verb@xor@ of \\verb@rs1@ and \\verb@imm_i@.\n\nFor example, if \\verb@x17@ = \\verb@0x55551111@ then the instruction \n\\verb@xori x12,x17,0x0ff@ will set \\verb@x12@ to the value \\verb@0x555511ee@.\n\nRecall that \\verb@imm@ is sign-extended.\nTherefore if \\verb@x17@ = \\verb@0x55551111@ then \n\\verb@xori x12,x17,0x800@ will set \\verb@x12@ to the value \\verb@0xaaaae911@.\n\n\\end{itemize}\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{S Type}\n\\label{insnformat:stype}\n%\\DrawInsnTypeSTikz{00000000111100011000100110100011}\n\nThe S-type instruction format is used to encode instructions with a\nsigned 12-bit immediate operand with a range of $[-2048..2047]$,\nan \\verb@rs1@ register, and an \\verb@rs2@ register.\n\nIf \\Gls{xlen}=32 then the 12-bit {\\em imm} value example will extracted \nfrom the instruction and converted as shown \\autoref{Figure:imm_s_type_decode}\nto form the \\verb@imm_s@ value.\n\n\\begin{figure}[ht]\n\\centering\n\\DrawInsnOpSTypeDecoding\n\\captionof{figure}{Decoding an S-type Instruction.}\n\\label{Figure:imm_s_type_decode}\n\\label{imm.s:decode}\n\\index{imm\\protect\\_s}\n\\end{figure}\n\n\\begin{itemize}\n\\item\\instructionHeader{sb\\ \\ \\ \\ rs2,imm(rs1)}\n\\label{insn:sb}\n\nSet the byte of memory at the address given by the sum of \\verb@rs1@ and \n\\verb@imm_s@ to the 8 \\acrshort{lsb}s of \\verb@rs2@.\n\nFor example, given the memory contents shown in \\autoref{Figure:imm:memory:dump},\nif registers \\verb@x13@ = \\verb@0x00002650@ and \\verb@x12@ = \\verb@0x12345678@\nthen the instruction \\verb@sb x12,1(x13)@ will change the memory byte at address \n\\verb@0x00002651@ from \\verb@0x80@ to \\verb@0x78@ resulting in:\n\n\\begin{verbatim}\n 00002640: 6f 00 00 00 6f 00 00 00 b7 87 00 00 03 a5 07 43 *o...o..........C*\n 00002650: 67 78 00 00 00 00 00 00 76 61 6c 3d 00 00 00 00 *gx......val=....*\n 00002660: 00 00 00 00 80 84 2e 41 1f 85 45 41 80 40 9a 44 *.......A..EA.@.D*\n 00002670: 4f 11 f3 c3 6e 8a 67 41 20 1b 00 00 20 1b 00 00 *O...n.gA ... ...*\n 00002680: 44 1b 00 00 14 1b 00 00 14 1b 00 00 04 1c 00 00 *D...............*\n\\end{verbatim}\n\n\\item\\instructionHeader{sh\\ \\ \\ \\ rs2,imm(rs1)}\n\\label{insn:sh}\n\nSet the 16-bit half-word of memory at the address given by the sum of \\verb@rs1@ and \n\\verb@imm_s@ to the 16 \\acrshort{lsb}s of \\verb@rs2@.\n\nFor example, given the memory contents shown in \\autoref{Figure:imm:memory:dump},\nif registers \\verb@x13@ = \\verb@0x00002650@ and \\verb@x12@ = \\verb@0x12345678@\nthen the instruction \\verb@sh x12,2(x13)@ will change the memory half-word at \naddress \\verb@0x00002652@ from \\verb@0x0000@ to \\verb@0x5678@ resulting in:\n\n\\begin{verbatim}\n 00002640: 6f 00 00 00 6f 00 00 00 b7 87 00 00 03 a5 07 43 *o...o..........C*\n 00002650: 67 80 78 56 00 00 00 00 76 61 6c 3d 00 00 00 00 *g.xV....val=....*\n 00002660: 00 00 00 00 80 84 2e 41 1f 85 45 41 80 40 9a 44 *.......A..EA.@.D*\n 00002670: 4f 11 f3 c3 6e 8a 67 41 20 1b 00 00 20 1b 00 00 *O...n.gA ... ...*\n 00002680: 44 1b 00 00 14 1b 00 00 14 1b 00 00 04 1c 00 00 *D...............*\n\\end{verbatim}\n\n\\item\\instructionHeader{sw\\ \\ \\ \\ rs2,imm(rs1)}\n\\label{insn:sw}\n\nStore the 32-bit value in \\verb@rs2@ into the memory at the address given \nby the sum of \\verb@rs1@ and \\verb@imm_s@.\n\nFor example, given the memory contents shown in \\autoref{Figure:imm:memory:dump},\nif registers \\verb@x13@ = \\verb@0x00002650@ and \\verb@x12@ = \\verb@0x12345678@\nthen the instruction \\verb@sw x12,0(x13)@ will change the memory word at address \n\\verb@0x00002650@ from \\verb@0x00008067@ to \\verb@0x12345678@ resulting in:\n\n\\begin{verbatim}\n 00002640: 6f 00 00 00 6f 00 00 00 b7 87 00 00 03 a5 07 43 *o...o..........C*\n 00002650: 78 56 34 12 00 00 00 00 76 61 6c 3d 00 00 00 00 *xV4.....val=....*\n 00002660: 00 00 00 00 80 84 2e 41 1f 85 45 41 80 40 9a 44 *.......A..EA.@.D*\n 00002670: 4f 11 f3 c3 6e 8a 67 41 20 1b 00 00 20 1b 00 00 *O...n.gA ... ...*\n 00002680: 44 1b 00 00 14 1b 00 00 14 1b 00 00 04 1c 00 00 *D...............*\n\\end{verbatim}\n\n\\end{itemize}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{B Type}\n\\label{insnformat:btype}\n%\\DrawInsnTypeBTikz{00000000111100011000100011100011}\n\nThe B-type instruction format is used for branch instructions that \nrequire an even immediate value that is used to determine the\nbranch target address as an offset from the current instruction's\naddress. \n\nIf \\Gls{xlen}=32 then the 12-bit {\\em imm} value example will extracted from \nthe instruction and converted as shown in \\autoref{Figure:imm_b_type_decode}\nto form the \\verb@imm_b@ value.\n\n\\begin{figure}[ht]\n\\centering\n\\DrawInsnOpBTypeDecoding\n\\captionof{figure}{Decoding a B-type Instruction.}\n\\label{Figure:imm_b_type_decode}\n\\label{imm.b:decode}\n\\index{imm\\protect\\_b}\n\\end{figure}\n\nNote that \\verb@imm_b@ is expressed in the instruction as a target \naddress that is converted to an even 13-bit value in the range of \n$[-4096..4094]$ $[$\\verb@-0x1000..0x0ffe@$]$ representing a \\verb@pc@-relative offset to the\ntarget address. For example, consider the branch instructions in\nthe following code:\n\n\\begin{verbatim}\n00000000: 00520063 beq x4,x5,0x0 # branches to self (address 0x0)\n00000004: 00520463 beq x4,x5,0xc # branches to address 0xc\n00000008: fe520ce3 beq x4,x5,0x0 # branches to address 0x0\n0000000c: 00100073 ebreak \n\\end{verbatim}\n\nThe instruction at address \\verb@0x0@ has a target address of zero and\n\\verb@imm_b@ is zero because the offset from the ``current instruction''\nto the target is zero.\\footnote{This is in contrast to many other\ninstruction sets with {\\tt pc}-relative addressing modes that express\na branch target offset from the ``next instruction.''}\n\nThe instruction at address \\verb@0x4@ has a target address of \\verb@0xc@\nand it has an \\verb@imm_b@ of \\verb@0x08@ because \\verb@0x4 + 0x08 = 0x0c@.\n\nThe instruction at address \\verb@0x8@ has a target address of zero and\n\\verb@imm_b@ is \\verb@0xfffffff8@ (-8) because \\verb@0x8 + 0xfffffff8 = 0x0@.\n\n\\begin{itemize}\n\\item\\instructionHeader{beq\\ \\ \\ rs1,rs2,pcrel\\_13}\n\\label{insn:beq}\n\nIf \\verb@rs1@ is equal to \\verb@rs2@ then add \\verb@imm_b@ to the \n\\verb@pc@ register.\n\n\\item\\instructionHeader{bge\\ \\ \\ rs1,rs2,pcrel\\_13}\n\\label{insn:bge}\n\nIf the signed value in \\verb@rs1@ is greater than or equal to the \nsigned value in \\verb@rs2@ then add \\verb@imm_b@ to the \n\\verb@pc@ register.\n\n\\item\\instructionHeader{bgeu\\ \\ rs1,rs2,pcrel\\_13}\n\\label{insn:bgeu}\n\nIf the unsigned value in \\verb@rs1@ is greater than or equal to the \nunsigned value in \\verb@rs2@ then add \\verb@imm_b@ to the \n\\verb@pc@ register.\n\n\\item\\instructionHeader{blt\\ \\ \\ rs1,rs2,pcrel\\_13}\n\\label{insn:blt}\n\nIf the signed value in \\verb@rs1@ is less than the \nsigned value in \\verb@rs2@ then add \\verb@imm_b@ to the \n\\verb@pc@ register.\n\n\\item\\instructionHeader{bltu\\ \\ rs1,rs2,pcrel\\_13}\n\\label{insn:bltu}\n\nIf the unsigned value in \\verb@rs1@ is less than the \nunsigned value in \\verb@rs2@ then add \\verb@imm_b@ to the \n\\verb@pc@ register.\n\n\\item\\instructionHeader{bne\\ \\ \\ rs1,rs2,pcrel\\_13}\n\\label{insn:bne}\n\nIf \\verb@rs1@ is not equal to \\verb@rs2@ then add \\verb@imm_b@ to the \n\\verb@pc@ register.\n\n\\end{itemize}\n\n%\\label{insn:bgt}\n%\\label{insn:ble}\n%\\label{insn:bgtu}\n%\\label{insn:beqz}\n%\\label{insn:bnez}\n%\\label{insn:blez}\n%\\label{insn:bgez}\n%\\label{insn:bltz}\n%\\label{insn:bgtz}\n\n\n%Control and Status Register Instructions\n%\\label{insn:csrrw}\n%\\label{insn:csrrs}\n%\\label{insn:csrrc}\n%\\label{insn:csrrwi}\n%\\label{insn:csrrsi}\n%\\label{insn:csrrci}\n\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\section{CPU Registers}\n\\label{cpuregs}\n\nThe registers are names x0 through x31 and have aliases suited to their \nconventional use. The following table describes each register. \n\nNote \n\\enote{Need to add a section that discusses the calling conventions} \nthat the calling calling convention specifies that only some \nof the registers are to be saved by functions if they alter their contents.\nThe idea being that accessing memory is time-consuming and that by\nclassifying some registers as ``temporary'' (not saved by any function\nthat alter its contents) it is possible to carefully implement a function\nwith less need to store register values on the stack in order to use them\nto perform the operations of the function.\n\nThe lack of grouping the temporary and saved registers is due to the\nfact that the E extension %\\cite{XXX}\nonly has the first 16 registers\nand some of the instructions in the C extension %See \\autoref{rv32:c}\ncan only refer to the first 16 registers.\n\n\n\\begin{center}\n\\begin{tabular}{|l|l|l|l|}\n\\hline\nReg\t\t& ABI/Alias\t& Description\t\t\t\t\t\t& Saved\t\t\\\\\n\\hline\n\\hline\n\\verb@x0@\t\t&\t\\verb@zero@\t\t& Hard-wired zero\t\t\t\t\t&\t\t\t\\\\\n\\verb@x1@\t\t&\t\\verb@ra@\t\t& Return address\t\t\t\t\t& \t\t\t\\\\\n\\verb@x2@\t\t&\t\\verb@sp@\t\t& Stack pointer\t\t\t\t\t\t& yes\t\t\\\\\n\\verb@x3@\t\t&\t\\verb@gp@\t\t& Global pointer\t\t\t\t\t&\t\t\t\\\\\n\\verb@x4@\t\t&\t\\verb@tp@\t\t& Thread pointer\t\t\t\t\t&\t\t\t\\\\\n\\verb@x5@\t\t&\t\\verb@t0@\t\t& Temporary/alternate link register\t&\t\t\t\\\\\n\\verb@x6-7@\t\t&\t\\verb@t1-2@\t\t& Temporaries\t\t\t\t\t\t&\t\t\t\\\\\n\\verb@x8@\t\t&\t\\verb@s0/fp@\t& Saved register/frame pointer\t\t& yes\t\t\\\\\n\\verb@x9@\t\t&\t\\verb@s1@\t\t& Saved register\t\t\t\t\t& yes\t\t\\\\\n\\verb@x10-11@\t&\t\\verb@a0-1@\t\t& Function arguments/return value\t& \t\t\t\\\\\n\\verb@x12-17@\t&\t\\verb@a2-7@\t\t& Function arguments\t\t\t\t& \t\t\t\\\\\n\\verb@x18-27@\t&\t\\verb@s2-11@\t& Saved registers\t\t\t\t\t& yes\t\t\\\\\n\\verb@x28-31@\t&\t\\verb@t3-6@\t\t& Temporaries\t\t\t\t\t\t&\t\t\t\\\\\n\\hline\n\\end{tabular}\n\\end{center}\n\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\section{memory}\n\nNote that RISC-V is a little-endian machine. \n\nAll instructions must be naturally aligned to their 4-byte \nboundaries.~\\cite[p.~5]{rvismv1v22:2017}\n\nIf a RISC-V processor implements the C (compressed) extension then \ninstructions may be aligned to 2-byte \nboundaries.\\cite[p.~68]{rvismv1v22:2017}\n\nData alignment is not necessary but unaligned data can be inefficient. \nAccessing unaligned data using any of the load or store instructions can \nalso prevent a memory access from operating \natomically.~\\cite[p.19]{rvismv1v22:2017}\n%See also \\autoref{RV32A}.\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\n%\\input{base.tex}\n\n" }, { "path": "book/rv32/insn/lui.tex", "content": "\\DrawInsnTypeUPicture{LUI t0, 3}{00000000000000000011001010110111}\n\n\\begin{verbatim}\n00010074: 000032b7 lui x5, 0x3 // x5 = 0x3000\n reg 0: 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 00003000 f0f0f0f0 f0f0f0f0\n reg 8: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0\n reg 16: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0\n reg 24: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0\n pc: 00010078\n\\end{verbatim}\n\n\\DrawInsnTypeUPicture{LUI t0, 0xfffff}{11111111111111111111001010110111}\n\n\\begin{verbatim}\n00010078: fffff2b7 lui x5, 0xfffff // x5 = 0xfffff000\n reg 0: 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 fffff000 f0f0f0f0 f0f0f0f0\n reg 8: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0\n reg 16: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0\n reg 24: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0\n pc: 0001007c\n\\end{verbatim}\n" }, { "path": "book/rv32m/chapter.tex", "content": "\\chapter{RV32M Standard Extension}\n\\label{chapter:rv32m}\n\\index{RV32M}\n\n\\section{Introduction}\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\n\n32-bit integer multiply and divide instructions.\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{MUL rd, rs1, rs2}\n\\index{Instruction!MUL}\n\nMultiply \\reg{rs1} by \\reg{rs2} and store the least significant 32-bits\nof the result in \\reg{rd}.\n\n\\DrawInsnTypeRPicture{MUL x7, x3, x31}{00000011111100111000001110110011}\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{MULH rd, rs1, rs2}\n\\index{Instruction!MULH}\n\n\\DrawInsnTypeRPicture{MULH x7, x3, x31}{00000011111100111001001110110011}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{MULHS rd, rs1, rs2}\n\\index{Instruction!MULHS}\n\n\\DrawInsnTypeRPicture{MULHS x7, x3, x31}{00000011111100111010001110110011}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{MULHU rd, rs1, rs2}\n\\index{Instruction!MULHU}\n\n\\DrawInsnTypeRPicture{MULHU x7, x3, x31}{00000011111100111011001110110011}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{DIV rd, rs1, rs2}\n\\index{Instruction!DIV}\n\n\\DrawInsnTypeRPicture{DIV x7, x3, x31}{00000011111100111100001110110011}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{DIVU rd, rs1, rs2}\n\\index{Instruction!DIVU}\n\n\\DrawInsnTypeRPicture{DIVU x7, x3, x31}{00000011111100111101001110110011}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{REM rd, rs1, rs2}\n\\index{Instruction!REM}\n\n\\DrawInsnTypeRPicture{REM x7, x3, x31}{00000011111100111110001110110011}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\subsection{REMU rd, rs1, rs2}\n\\index{Instruction!REMU}\n\n\\DrawInsnTypeRPicture{REMU x7, x3, x31}{00000011111100111111001110110011}\n" }, { "path": "book/rvalp.tex", "content": "%\\documentclass[oneside,draft,letterpaper]{book}\n%\\documentclass[letterpaper]{book}\n\\documentclass[oneside,letterpaper]{book}\n\n\n\\input{preamble}\n\\input{colors}\n\\input{insnformats}\n\n\\usepackage{ENote}\n\n%\\usepackage{showframe}\n\n\\hypersetup{\n\tpdfauthor={John Winans},\n\tpdftitle={RISC-V Assembly Language Programming (Draft \\GitRevision{})},\n\tpdfkeywords={RISC-V} {Assembler}\n}\n\n\\makeindex\n\n%\\makeglossaries\n\\makenoidxglossaries\n\\include{glossary}\n\n%\\includeonly{refcard/chapter}\n\n\\begin{document}\n\\include{indexrefs}\t\t% The see-references for the index\n\n% Why does this (apparently) have to go here????\n\\newlength{\\fullwidth}\n\\setlength{\\fullwidth}{\\the\\textwidth}\n\\addtolength{\\fullwidth}{\\the\\marginparsep}\n\\addtolength{\\fullwidth}{\\the\\marginparwidth}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\frontmatter\n\n\\title{RISC-V\\\\Assembly Language Programming\\\\{\\normalsize (Draft \\GitRevision{})}}\n\\author{John Winans\\\\ \\href{mailto:jwinans@niu.edu}{\\sf jwinans@niu.edu}}\n%\\date{May }\n\n\\maketitle\n\n\\include{copyright/chapter}\n\\tableofcontents\n%\\listoffigures\n\n\\setlength{\\parskip}{10pt}\n\n\\include{preface/chapter}\n\\mainmatter\n\n%\\include{preface/chapter}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\n% there should be one include here for each chapter\n\n%\\part{Introduction}\n\n\\include{intro/chapter}\n\\include{binary/chapter}\n\\include{elements/chapter}\n\\include{programs/chapter}\n\\include{rv32/chapter}\n\n%\\include{priv/chapter}\n%\\include{rv32m/chapter}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% These 'chapters' are lettered rather than numbered\n\n\\appendix\n%\\include{insnsummary/chapter}\t % no longer neded with expanded refcard\n\\include{install/chapter}\n%\\include{toolchain/chapter}\n\\include{float/chapter}\n\\include{ascii/chapter}\n\\include{license/chapter}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\backmatter\n% putting a chapter here causes it to be unnumbered\n\n\\bibliography{bibliography}\n\\addcontentsline{toc}{chapter}{Bibliography}\n\\nocite{*} % force all bib items to file appear even if not cited\n%\\bibliographystyle{alpha}\n\\bibliographystyle{ieeetr}\n\n%\\phantomsection\n\\glsaddall\n\\printnoidxglossaries\n%\\printglossary\n\n\n\\phantomsection\n\\addcontentsline{toc}{chapter}{\\indexname}\n\\printindex\n\n\\include{refcard/chapter}\n\n\\end{document}\n" }, { "path": "book/toolchain/chapter.tex", "content": "\\chapter{Using The RISC-V GNU Toolchain}\n\nThis chapter discusses using the GNU toolchain elements to\nexperiment with the material in this book.\n\nSee \\autoref{chapter:install} if you do not already have the \nGNU crosscompiler toolchain available on your system.\n\n\nDiscuss the choice of ilp32 as well as what the other variations would do.\n\nDiscuss rv32im and note that the details are found in \\autoref{chapter:RV32}.\n\nDiscuss installing and using one of the RISC-V simulators \nhere.\n\nDescribe the pre-processor, compiler, assembler and linker.\n\nSource, object, and binary files\n\nAssembly syntax (label: mnemonic op1, op2, op3 \\# comment).\n\ntext, data, bss, stack\n\nLabels and scope.\n\nForward \\& backward references to throw-away labels.\n\nThe entry address of an application.\n\n.s file contain assembler code.\n.S (or .sx) files contain assembler code that must be preprocessed.~\\cite[p.~29]{gcc:2017}\n\nPre-processing conditional assembly using \\#if.\n\nBuilding with \\verb@-mabi=ilp32 -march=rv32i -mno-fdiv -mno-div@ to match\nthe config options on the toolchain. \n\nLinker scripts.\n\nMakefiles\n\nobjdump\n\nnm\n\nhexdump -C\n" }, { "path": "texlib/ENote.sty", "content": "\\NeedsTeXFormat{LaTeX2e}\n\\ProvidesPackage{ENote}\n [2002/03/23 v1\n John Winans's editor notes facilities%\n ]\n%\n% A simple way to provide book-editor notes that can be \n% automatically turned off.\n%\n%\\newcommand{\\enote}[1]{\\marginpar{\\raggedright\\small\\sffamily \\ding{209} Note: \\vskip 3pt \\hrule \\vskip 1pt \\scriptsize\\slshape #1 \\vskip 1pt \\hrule}}\n%\\newcommand{\\enote}[1]{\\mbox{}\\marginpar{\\raggedright\\small\\sffamily Editor's Note: \\vskip 3pt \\hrule \\vskip 1pt \\scriptsize\\slshape #1 \\vskip 1pt \\hrule}}\n\\newcommand{\\enote}[1]{\\mbox{}\\marginpar{\\raggedright\\small\\sffamily \\ding{253} Fix Me:\\vskip 3pt \\hrule \\vskip 1pt \\scriptsize\\slshape #1 \\vskip 1pt \\hrule}}\n\n\\newcommand{\\marginwarn}[1]{\\mbox{}\\marginpar{\\raggedright\\small\\sffamily Warning: \\vskip 3pt \\hrule \\vskip 1pt \\scriptsize\\slshape #1 \\vskip 1pt \\hrule}}\n\n\\newcommand{\\margingood}[1]{\\mbox{}\\marginpar{\\raggedright\\small\\sffamily Handy Tip: \\vskip 3pt \\hrule \\vskip 1pt \\scriptsize\\slshape #1 \\vskip 1pt \\hrule}}\n\n\\newcommand{\\marginnote}[1]{\\mbox{}\\marginpar{\\raggedright\\small\\sffamily Note: \\vskip 3pt \\hrule \\vskip 1pt \\scriptsize\\slshape #1 \\vskip 1pt \\hrule}}\n\n\\newcommand\\markbad{\\ding{209} }\n\\newcommand\\markgood{\\ding{253} }\n\n\\newcommand\\dmarginwarn[1]{\\mbox{}\\marginpar{\\fbox{\\parbox{\\marginparwidth}{\\raggedright\\markbad #1}}}}\n\\newcommand\\dmargingood[1]{\\mbox{}\\marginpar{\\fbox{\\parbox{\\marginparwidth}{\\raggedright\\markgood #1}}}}\n\n\\endinput\n" }, { "path": "texlib/MyFigs.sty", "content": "\\NeedsTeXFormat{LaTeX2e}\n\\ProvidesPackage{MyFigs}\n [2002/03/23 v1\n John Winans's graphic figure includer facilities%\n ]\n%\n% #1 = file name\n% #2 = caption\n% #3 = label\n%\n\\newenvironment{EpsFig}[3]{%\n\t\\begin{figure} \\begin{center} \\includegraphics[]{#1} \\end{center} \\caption{#2} \\label{#3}}%\n\t{\\end{figure}}\n\\newenvironment{EpsFig1}[3]{%\n\t\\begin{figure} \\includegraphics[width=\\textwidth]{#1} \\caption{#2} \\label{#3}}%\n\t{\\end{figure}}\n\n\\newenvironment{EpsFig2}[3]{%\n\t\\begin{figure} \\includegraphics[width=\\fullwidth]{#1} \\caption{#2} \\label{#3}}%\n\t{\\end{figure}}\n\n\\newenvironment{EpsFigRot}[3]{%\n\t\\begin{sidewaysfigure}\\epsfig{height=\\MySidewaysFigWidth,file=#1} \\caption{#2} \\label{#3}}%\n\t{\\end{sidewaysfigure}}\n\n\n% #1 = file name\n% #2 = caption\n% #3 = includegraphics parms\n\\newcommand{\\GraphicFigFloating}[3]{%\n\t\\begin{figure} \\begin{center} \\includegraphics[#3]{#1} \\end{center} \\caption{#2} \\label{detokenize{Graphic:#2}}%\n\t\\end{figure}}\n\n\\newcommand{\\GraphicFig}[3]{%\n\t\\begin{minipage}{\\textwidth} \\begin{center} \\includegraphics[#3]{#1} \\captionof{figure}{#2}\\label{detokenize{Graphic:#1}} \\end{center} \\end{minipage}%\n\t}\n\n\\newcommand{\\xGraphicFig}[3]{%\n\t\\begin{center} \\includegraphics[#3]{#1} \\captionof{figure}{#2}\\label{detokenize{Graphic:#1}} \\end{center} %\n\t}\n\n\\newcommand{\\GraphicFigRef}[1]{%\n\t\\autoref{detokenize{Graphic:#1}}%\n\t}\n\n\n\\endinput\n" }, { "path": "texlib/MyVerbatim.sty", "content": "\\NeedsTeXFormat{LaTeX2e}\n\\ProvidesPackage{MyVerbatim}\n [2002/03/23 v1\n John Winans's verbatim facilities%\n ]\n\\newlength{\\bvwidth}\n\\setlength{\\bvwidth}{\\textwidth}\n%\\addtolength{\\bvwidth}{\\marginparsep}\n%\\addtolength{\\bvwidth}{\\marginparwidth}\n%\\addtolength{\\bvwidth}{-7pt}\n\\addtolength{\\bvwidth}{-1pt}\n\n% A low quality boxed verbatim environment\n%\\newenvironment{boxedverbatim}%\n% {\\VerbatimEnvironment \\begin{Sbox}\\begin{minipage}{\\bvwidth}\\footnotesize\\begin{Verbatim}}%\n% {\\end{Verbatim}\\end{minipage}\\end{Sbox} \\setlength{\\fboxsep}{1mm}\\noindent\\fbox{\\TheSbox}}\n\n% A figure-generating boxed verbatim environment\n%\n% #1: Filename\n% #2: Caption\n% #3: Label\n\\newcommand\\VFTitle{X}\n\\newcommand\\VFCaption{X}\n\\newcommand\\VFLabel{X}\n\n% \\begin{Code}{The Title}\n% xxx\n% \\end{Code}\n\\newenvironment{Code}[1]{%\n\t\\renewcommand\\VFTitle{#1}%\n\t\\VerbatimEnvironment%\n\t\\begin{Sbox}\\begin{minipage}{\\bvwidth}\\footnotesize\\begin{Verbatim}}%\n\t{\\end{Verbatim}\\end{minipage}\\end{Sbox} \\bigskip\\noindent\\setlength{\\fboxsep}{.5mm}\\framebox[\\bvwidth][l]{\\textsf{\\small\\bfseries\\VFTitle}}\\\\\n\t\\framebox[\\bvwidth][l]{\\TheSbox}\\bigskip}\n\n% This only exists so that we can show a Code environment within one\n\\newenvironment{CodeAlt}[1]{%\n\t\\renewcommand\\VFTitle{#1}%\n\t\\VerbatimEnvironment%\n\t\\begin{Sbox}\\begin{minipage}{\\bvwidth}\\footnotesize\\begin{Verbatim}}%\n\t{\\end{Verbatim}\\end{minipage}\\end{Sbox} \\bigskip\\noindent\\setlength{\\fboxsep}{.5mm}\\framebox[\\bvwidth][l]{\\textsf{\\small\\bfseries\\VFTitle}}\\\\\n\t\\framebox[\\bvwidth][l]{\\TheSbox}\\bigskip}\n\n\\newenvironment{CodeFig}[3]{%\n \\renewcommand\\VFTitle{#1}%\n \\renewcommand\\VFCaption{#2}%\n \\renewcommand\\VFLabel{#3}%\n \\VerbatimEnvironment%\n \\begin{Sbox}\\begin{minipage}{\\bvwidth}\\footnotesize\\begin{Verbatim}}%\n {\\end{Verbatim}\\end{minipage}\\end{Sbox} \\setlength{\\fboxsep}{.5mm}\\begin{figure}[ht]\\framebox[\\bvwidth][l]{\\textsf{\\small\\bfseries\\VFTitle}}\\\\\n \\framebox[\\bvwidth][l]{\\TheSbox}\\caption{\\VFCaption}\\label{\\VFLabel}\\end{figure}}\n\n% This only exists so that we can show a CodeFig environment within one\n\\newenvironment{CodeFigAlt}[3]{%\n \\renewcommand\\VFTitle{#1}%\n \\renewcommand\\VFCaption{#2}%\n \\renewcommand\\VFLabel{#3}%\n \\VerbatimEnvironment%\n \\begin{Sbox}\\begin{minipage}{\\bvwidth}\\footnotesize\\begin{Verbatim}}%\n {\\end{Verbatim}\\end{minipage}\\end{Sbox} \\setlength{\\fboxsep}{.5mm}\\begin{figure}[ht]\\framebox[\\bvwidth][l]{\\textsf{\\small\\bfseries\\VFTitle}}\\\\\n \\framebox[\\bvwidth][l]{\\TheSbox}\\caption{\\VFCaption}\\label{\\VFLabel}\\end{figure}}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\\newenvironment{CodeFigB}[2]{%\n \\renewcommand\\VFCaption{#1}%\n \\renewcommand\\VFLabel{#2}%\n \\VerbatimEnvironment%\n \\begin{Sbox}\\begin{minipage}{\\bvwidth}\\footnotesize\\begin{Verbatim}}%\n {\\end{Verbatim}\\end{minipage}\\end{Sbox} \\setlength{\\fboxsep}{.5mm}\\begin{figure}[ht]\\framebox[\\bvwidth][l]{\\TheSbox}\\caption{\\VFCaption}\\label{\\VFLabel}\\end{figure}}\n\n\\newenvironment{CodeFigBAlt}[2]{%\n \\renewcommand\\VFCaption{#1}%\n \\renewcommand\\VFLabel{#2}%\n \\VerbatimEnvironment%\n \\begin{Sbox}\\begin{minipage}{\\bvwidth}\\footnotesize\\begin{Verbatim}}%\n {\\end{Verbatim}\\end{minipage}\\end{Sbox} \\setlength{\\fboxsep}{.5mm}\\begin{figure}[ht]\\framebox[\\bvwidth][l]{\\TheSbox}\\caption{\\VFCaption}\\label{\\VFLabel}\\end{figure}}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%\n% Define verbatim things each with their own type.\n%\n\n\\newcommand\\email{\\begingroup \\urlstyle{sf}\\Url}\n\\newcommand\\filename{\\begingroup \\urlstyle{sf}\\Url}\n\\newcommand\\code{\\begingroup \\urlstyle{tt}\\Url}\n\n\\endinput\n" }, { "path": "texlib/index.ist", "content": "% Style for makeindex\n% This style simply adds a bolded letter for each part of the alphabet\nheading_prefix\t\"{\\\\bfseries \"\nheading_suffix\t\"\\\\hfil}\\\\nopagebreak\\n\"\nheadings_flag\t1\n" } ]