Repository: johnwinans/rvalp Branch: master Commit: aa309812b30d Files: 56 Total size: 391.0 KB Directory structure: gitextract_vt1ez9jz/ ├── .gitignore ├── LICENSE ├── Make.rules ├── Makefile ├── README.md ├── book/ │ ├── .gitignore │ ├── Makefile │ ├── amodes/ │ │ └── chapter.tex │ ├── ascii/ │ │ └── chapter.tex │ ├── bibliography.bib │ ├── binary/ │ │ ├── chapter.tex │ │ └── rvddt_memdump.out │ ├── colors.tex │ ├── copyright/ │ │ └── chapter.tex │ ├── elements/ │ │ ├── chapter.tex │ │ ├── zero4regs.S │ │ └── zero4regs.out │ ├── float/ │ │ ├── chapter.tex │ │ ├── cleandecimal.c │ │ ├── cleandecimal.out │ │ ├── erroraccumulation.c │ │ ├── erroraccumulation.out │ │ ├── errorcompensation.c │ │ ├── errorcompensation.out │ │ ├── powersoftwo.c │ │ └── powersoftwo.out │ ├── glossary.tex │ ├── insnformats.tex │ ├── insnsummary/ │ │ └── chapter.tex │ ├── install/ │ │ └── chapter.tex │ ├── intro/ │ │ └── chapter.tex │ ├── license/ │ │ └── chapter.tex │ ├── preamble.tex │ ├── preface/ │ │ └── chapter.tex │ ├── priv/ │ │ └── chapter.tex │ ├── programs/ │ │ ├── chapter.tex │ │ └── src/ │ │ ├── .gitignore │ │ ├── Make.rules │ │ ├── Makefile │ │ └── mvzero/ │ │ ├── .gitignore │ │ ├── Makefile │ │ ├── mv.S │ │ ├── mv.lst │ │ ├── mv.out │ │ └── run.sh │ ├── refcard/ │ │ └── chapter.tex │ ├── rv32/ │ │ ├── base.tex │ │ ├── chapter.tex │ │ └── insn/ │ │ └── lui.tex │ ├── rv32m/ │ │ └── chapter.tex │ ├── rvalp.tex │ └── toolchain/ │ └── chapter.tex └── texlib/ ├── ENote.sty ├── MyFigs.sty ├── MyVerbatim.sty └── index.ist ================================================ FILE CONTENTS ================================================ ================================================ FILE: .gitignore ================================================ *.swp ================================================ FILE: LICENSE ================================================ Attribution 4.0 International ======================================================================= Creative Commons Corporation ("Creative Commons") is not a law firm and does not provide legal services or legal advice. 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Creative Commons may be contacted at creativecommons.org. ================================================ FILE: Make.rules ================================================ TEXLIB=$(TOP)/texlib # BEFORE including this file, you must define: TEXPATH # This only works if there is at least one tag in the git repo #GIT_SHOW_FORMAT=%ae %ci GIT_SHOW_FORMAT=%ci LATEXFLAGS="\newcommand\GitFileName{"`pwd | sed -e 's|^.*rvalp/|\\\textasciitilde/rvalp/|'`/"}\newcommand\GitDescription{"`git describe --long --dirty; git show -s --format='$(GIT_SHOW_FORMAT)';`"}\newcommand\GitRevision{"`git describe --long --dirty`"}\input{$<}" LATEX_CLEANFILES = *.aux *.log *.dvi *.toc *.lof *.bbl *.blg *.ind *.ilg *.idx *.glo *.glg *.gls *.glsdefs *.out *.ist *.brf .SUFFIXES: .tex .pdf .eps .fig .dot .png .tex.pdf: ( export TEXINPUTS=$(TEXPATH):$(TEXLIB)::; \ BIBINPUTS=${TEXINPUTS}; export BIBINPUTS; \ pdflatex $(LATEXFLAGS) $<; \ cp $@ out-$@; \ bibtex ${<:.tex=}; \ makeindex -s $(TEXLIB)/index.ist ${<:.tex=}; \ pdflatex $(LATEXFLAGS) $<; \ cp $@ out-$@; \ pdflatex $(LATEXFLAGS) $<;\ cp $@ out-$@; ) #makeglossaries ${<:.tex=}; \ .fig.eps: fig2dev -L eps $< > $@ .fig.pdf: fig2dev -L pdftex $< > $@ # Rules for converting dot files into png files .dot.png: dot -Tpng -o $@ $< .dot.pdf: dot -Tpdf -o $@ $< # Rules for walking a tree of Makefiles # Add a prefix to each directory name to make unique versions for all, clean,... CLEAN_DIRS=$(SUBDIRS:%=clean-%) ALL_DIRS=$(SUBDIRS:%=all-%) .PHONY: all clean world doc $(CLEAN_DIRS) $(ALL_DIRS) all:: $(ALL_DIRS) clean:: $(CLEAN_DIRS) # for each dir, do a make all $(ALL_DIRS):: $(MAKE) -C $(@:all-%=%) all # for each dir, do a make clean $(CLEAN_DIRS):: $(MAKE) -C $(@:clean-%=%) clean world:: clean all ================================================ FILE: Makefile ================================================ TOP=. SUBDIRS=book include $(TOP)/Make.rules ================================================ FILE: README.md ================================================ # rvalp RISC-V Assembly Language Programming This is an attempt to create a book on RISC-V programming in assembly language. See the Releases page for pre-made PDF versions: https://github.com/johnwinans/rvalp/releases Pull requests are welcome. I will release PDFs after useful improvements from time to time into the releases area for those that don't wish to build their own. You can find the rvddt simulator mentioned in the text here: https://github.com/johnwinans/rvddt I developed this using LaTeX via texlive. LaTeX is very portable. You should be able to tinker with it on most any platform. On Ubuntu 20.04 and 18.04 LTS, loading the following packages worked for me: sudo apt install make sudo apt install git sudo apt install texlive-latex-extra I suspect the same (above) would work on 16.04 as well. Then clone and build this repo: git clone https://github.com/johnwinans/rvalp.git cd rvalp make world # Related Projects The RISC-V simulator that I use to generate figures: https://github.com/johnwinans/rvddt A RISC-V simulator with more advanced features (but is also more complicated): https://github.com/johnwinans/riscv-toolchain-install-guide The toolchain used to assemble and compile programs in this book: https://github.com/riscv/riscv-gnu-toolchain See Appendix A of rvalp for the precise details on how I downloaded and build each of these tools on Linux. Note: During the great on-line COVID school year I recorded some lectures on RISC-V that use this book as a reference. These lectures appear in the following YouTube playlists: * [RISC-V Lectures From NIU CSCI 463](https://www.youtube.com/playlist?list=PL3by7evD3F53Dz2RiB47Ztp9l_piGVuus) * [The Whole NIU CSCI 463 Spring 2021 Playlist](https://www.youtube.com/playlist?list=PL3by7evD3F50NMukhaMqNdOt4pUHXT2Vo) ================================================ FILE: book/.gitignore ================================================ rvalp.aux rvalp.brf rvalp.idx rvalp.ilg rvalp.ind rvalp.lof rvalp.log rvalp.pdf rvalp.toc rvalp.bbl rvalp.blg rvalp.out *.aux rvalp.glg rvalp.glo rvalp.gls rvalp.glsdefs rvalp.ist *.bak out-rvalp.pdf ================================================ FILE: book/Makefile ================================================ SUBDIRS= # programs/src TOP=.. include $(TOP)/Make.rules TEXPATH=float:intro:rv32:copyright:license:elements:binary:programs/src all:: rvalp.pdf clean:: rm -f rvalp.pdf */*.aux $(LATEX_CLEANFILES) rvalp.pdf:: *.tex bibliography.bib spell: #find . -name "*.tex" -exec aspell --lang=en --mode=tex check "{}" \; find . -name "*.tex" -exec aspell --mode=tex check "{}" \; ================================================ FILE: book/amodes/chapter.tex ================================================ \chapter{Addressing Modes} A box showing +/- 2KB regions for \reg{gp} addressing with LB, LBU, SB, LH, LHU, SH, LW, and SW instructions. \BeginTikzPicture \draw(1.5,0) node{.data}; \draw[->] (3,0) -- (4,0); % right arrow \draw(2,10) node{gp}; \draw[->] (3,10) -- (4,10); % right arrow % \draw(0,15) node{+2KB}; % \draw(0,5) node{-2KB}; \draw[->] (6,9) -- (6,1); % up arrow \draw[->] (6,11) -- (6,19); % down arrow \draw(6,20) node{\tt 0x8fff}; \draw(6,10) node{\tt 0x8800}; \draw(6,0) node{\tt 0x8000}; \EndTikzPicture ================================================ FILE: book/ascii/chapter.tex ================================================ \chapter{The ASCII Character Set} \label{chapter:ascii} \index{ASCII} A slightly abridged version of the Linux ``ASCII'' man(1) page. \section{NAME} ascii - ASCII character set encoded in octal, decimal, and hexadecimal \section{DESCRIPTION} ASCII is the American Standard Code for Information Interchange. It is a 7-bit code. Many 8-bit codes (e.g., ISO 8859-1) contain ASCII as their lower half. The international counterpart of ASCII is known as ISO 646-IRV. The following table contains the 128 ASCII characters. C program '\verb@\X@' escapes are noted. \begin{verbatim} Oct Dec Hex Char Oct Dec Hex Char ------------------------------------------------------------------------ 000 0 00 NUL '\0' (null character) 100 64 40 @ 001 1 01 SOH (start of heading) 101 65 41 A 002 2 02 STX (start of text) 102 66 42 B 003 3 03 ETX (end of text) 103 67 43 C 004 4 04 EOT (end of transmission) 104 68 44 D 005 5 05 ENQ (enquiry) 105 69 45 E 006 6 06 ACK (acknowledge) 106 70 46 F 007 7 07 BEL '\a' (bell) 107 71 47 G 010 8 08 BS '\b' (backspace) 110 72 48 H 011 9 09 HT '\t' (horizontal tab) 111 73 49 I 012 10 0A LF '\n' (new line) 112 74 4A J 013 11 0B VT '\v' (vertical tab) 113 75 4B K 014 12 0C FF '\f' (form feed) 114 76 4C L 015 13 0D CR '\r' (carriage ret) 115 77 4D M 016 14 0E SO (shift out) 116 78 4E N 017 15 0F SI (shift in) 117 79 4F O 020 16 10 DLE (data link escape) 120 80 50 P 021 17 11 DC1 (device control 1) 121 81 51 Q 022 18 12 DC2 (device control 2) 122 82 52 R 023 19 13 DC3 (device control 3) 123 83 53 S 024 20 14 DC4 (device control 4) 124 84 54 T 025 21 15 NAK (negative ack.) 125 85 55 U 026 22 16 SYN (synchronous idle) 126 86 56 V 027 23 17 ETB (end of trans. blk) 127 87 57 W 030 24 18 CAN (cancel) 130 88 58 X 031 25 19 EM (end of medium) 131 89 59 Y 032 26 1A SUB (substitute) 132 90 5A Z 033 27 1B ESC (escape) 133 91 5B [ 034 28 1C FS (file separator) 134 92 5C \ '\\' 035 29 1D GS (group separator) 135 93 5D ] 036 30 1E RS (record separator) 136 94 5E ^ 037 31 1F US (unit separator) 137 95 5F _ 040 32 20 SPACE 140 96 60 ` 041 33 21 ! 141 97 61 a 042 34 22 " 142 98 62 b 043 35 23 # 143 99 63 c 044 36 24 $ 144 100 64 d 045 37 25 % 145 101 65 e 046 38 26 & 146 102 66 f 047 39 27 ' 147 103 67 g 050 40 28 ( 150 104 68 h 051 41 29 ) 151 105 69 i 052 42 2A * 152 106 6A j 053 43 2B + 153 107 6B k 054 44 2C , 154 108 6C l 055 45 2D - 155 109 6D m 056 46 2E . 156 110 6E n 057 47 2F / 157 111 6F o 060 48 30 0 160 112 70 p 061 49 31 1 161 113 71 q 062 50 32 2 162 114 72 r 063 51 33 3 163 115 73 s 064 52 34 4 164 116 74 t 065 53 35 5 165 117 75 u 066 54 36 6 166 118 76 v 067 55 37 7 167 119 77 w 070 56 38 8 170 120 78 x 071 57 39 9 171 121 79 y 072 58 3A : 172 122 7A z 073 59 3B ; 173 123 7B { 074 60 3C < 174 124 7C | 075 61 3D = 175 125 7D } 076 62 3E > 176 126 7E ~ 077 63 3F ? 177 127 7F DEL \end{verbatim} \subsection{Tables} For convenience, below are more compact tables in hex and decimal. \begin{verbatim} 2 3 4 5 6 7 30 40 50 60 70 80 90 100 110 120 ------------- --------------------------------- 0: 0 @ P ` p 0: ( 2 < F P Z d n x 1: ! 1 A Q a q 1: ) 3 = G Q [ e o y 2: " 2 B R b r 2: * 4 > H R \ f p z 3: # 3 C S c s 3: ! + 5 ? I S ] g q { 4: $ 4 D T d t 4: " , 6 @ J T ^ h r | 5: % 5 E U e u 5: # - 7 A K U _ i s } 6: & 6 F V f v 6: $ . 8 B L V ` j t ~ 7: ' 7 G W g w 7: % / 9 C M W a k u DEL 8: ( 8 H X h x 8: & 0 : D N X b l v 9: ) 9 I Y i y 9: ' 1 ; E O Y c m w A: * : J Z j z B: + ; K [ k { C: , < L \ l | D: - = M ] m } E: . > N ^ n ~ F: / ? O _ o DEL \end{verbatim} \section{NOTES} \subsection{History} An ascii manual page appeared in Version 7 of AT\&T UNIX. On older terminals, the underscore code is displayed as a left arrow, called backarrow, the caret is displayed as an up-arrow and the vertical bar has a hole in the middle. Uppercase and lowercase characters differ by just one bit and the ASCII character 2 differs from the double quote by just one bit, too. That made it much easier to encode characters mechanically or with a non-microcontroller-based electronic keyboard and that pairing was found on old teletypes. The ASCII standard was published by the United States of America Standards Institute (USASI) in 1968. \section{COLOPHON} This page is part of release 4.04 of the Linux man-pages project. A description of the project, information about reporting bugs, and the latest version of this page, can be found at \url{http://www.kernel.org/doc/man-pages/}. ================================================ FILE: book/bibliography.bib ================================================ @string{IETF="Internet Engineering Task Force"} @manual{rvismv1v22:2017, title = "\href{https://github.com/riscv/riscv-isa-manual}{The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Document Version 2.2}", organization = "\href{https://riscv.org/}{RISC-V Foundation}", year = 2017, month = {May}, note = {Editors Andrew Waterman and Krste Asanovi\'c} } @manual{rvismv2:2017, title = "\href{https://github.com/riscv/riscv-isa-manual}{The RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Document Version 1.10}", organization = "\href{https://riscv.org/}{RISC-V Foundation}", year = 2017, month = {May}, note = {Editors Andrew Waterman and Krste Asanovi\'c} } @manual{rvpsabi:2017, title = "\href{https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md}{RISC-V ELF psABI specification}", author = {Palmer Dabbelt and Stefan O'Rear and Kito Cheng and Andrew Waterman and Michael Clark and Alex Bradbury and David Horner and Max Nordlund and Karsten Merker}, year = 2017 } @book{riscvreader:2017, title = {The RISC-V Reader: An Open Architecture Atlas}, author = {David Patterson and Andrew Waterman}, publisher = {Strawberry Canyon}, month = {Nov}, year = 2017, note = {ISBN: 978-0999249116} } @book{codriscv:2017, title = {Computer Organization and Design RISC-V Edition: The Hardware Software Interface}, author = {David Patterson and John Hennessy}, publisher = {Morgan Kaufmann}, month = {Apr}, year = 2017, note = {ISBN: 978-0128122754} } @book{gcc:2017, title = "\href{https://gcc.gnu.org/onlinedocs/}{Using the GNU Compiler Collection (For GCC version 7.3.0)}", author = {Richard M. Stallman and the GCC Developer Community}, publisher = {GNU Press}, address = {Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA}, year = 2017 } @article{Decker:1985:MAT:989369.989375, author = {Decker, William F.}, title = {A Modern Approach to Teaching Computer Organization and Assembly Language Programming}, journal = {SIGCSE Bull.}, issue_date = {December 1985}, volume = {17}, number = {4}, month = {Dec}, year = {1985}, issn = {0097-8418}, pages = {38--44}, numpages = {7}, url = {http://doi.acm.org/10.1145/989369.989375}, doi = {10.1145/989369.989375}, acmid = {989375}, publisher = {ACM}, address = {New York, NY, USA} } @manual{mcs85:1978, title = {MCS-85 User's Manual}, organization = {Intel}, month = {Sep}, year = 1978 } @manual{edtasm:1978, title = {TRS-80 Editor/Assembler Operation and Reference Manual}, organization = {Radio Shack}, year = 1978 } @manual{mc68000:1980, title = {MC68000 16--bit Microprocessor User's Manual}, edition = {2nd}, organization = {Motorola}, month = {Jan}, year = 1980, note = {MC68000UM(AD2)} } @manual{ns32k:1986, title = {Series 32000 Databook}, organization = {National Semiconductor Coprporation}, year = 1986 } @book{assist:1983, title = {Assembler Language With ASSIST}, author = {Ross A. Overbeek and W. E. Singletary}, edition = {2nd}, publisher = {Science Research Associates, Inc.}, year = 1983 } @manual{poo:1980, title = {IBM System/370 Principals of Operation}, edition = {7th}, organization = {IBM}, month = {Mar}, year = 1980 } @manual{assembler370:1979, title = {OS/VS-DOS/VSE-VM/370 Assembler Language}, edition = {6th}, organization = {IBM}, month = {Mar}, year = 1979 } @manual{ttl74154:1979, title = "\href{http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=sdls056&fileType=pdf}{SN54154, SN74154 4--line to 16--line Decoders/Demultiplexers}", organization = {Texas Instruments}, month = {Dec}, year = 1972 } @manual{ttl74191:1979, title = "\href{http://www.ti.com/lit/ds/symlink/sn74ls191.pdf}{SN54190, SN54191, SN54LS190, SN54LS191, SN74190, SN74191, SN74LS190, SN74LS191 Synchronous Up/Down Counters With Down/Up Mode Control}", organization = {Texas Instruments}, month = {Mar}, year = 1988 } @Misc{IEN137, author = "Danny Cohen", title = "\href{http://www.ietf.org/rfc/ien/ien137.txt}{IEN 137, On Holy Wars and a Plea for Peace}", month = {Apr}, year = "1980", note = "This note discusses the Big-Endian/Little-Endian byte/bit-order controversy, but did not settle it. A decade later, David V. James in ``Multiplexed Buses: The Endian Wars Continue'', {\em IEEE Micro}, {\bf 10}(3), 9--21 (1990) continued the discussion.", %%% URL = "http://www.ietf.org/rfc/ien/ien137.txt", } @misc{subtrahend, title = {Definition of Subtrahend}, howpublished = {\href{https://www.mathsisfun.com/definitions/subtrahend.html}{www.mathsisfun.com/definitions/subtrahend.html}}, note = {Accessed: 2018-06-02} } @article{ieee:754, author={}, journal={IEEE Std 754-2019 (Revision of IEEE 754-2008)}, title={IEEE Standard for Floating-Point Arithmetic}, year={2019}, volume={}, number={}, pages={1-84},} @manual{zilog:1977, title = {Z80 Assembly Language Programming Manual}, organization = {Zilog Inc.}, month = {Jan}, year = 1977 } @book{leventhal:1979, title = {Z80 Assembly Language Programming}, author = {Lance A. Leventhal}, publisher = {Osborne/McGraw-Hill}, year = 1979 } ================================================ FILE: book/binary/chapter.tex ================================================ \chapter{Numbers and Storage Systems} \label{chapter:numbers} This chapter discusses how data are represented and stored in a computer. In the context of computing, {\em boolean} refers to a condition that can be either true or false and {\em binary} refers to the use of a base-2 numeric system to represent numbers. RISC-V assembly language uses binary to represent all values, be they boolean or numeric. It is the context within which they are used that determines whether they are boolean or numeric. \enote{Add some diagrams here showing bits, bytes and the MSB, LSB,\ldots\ perhaps relocated from the RV32I chapter?} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \section{Boolean Functions} Boolean functions apply on a per-bit basis. When applied to multi-bit values, each bit position is operated upon independent of the other bits. RISC-V assembly language uses zero to represent {\em false} and one to represent {\em true}. In general, however, it is useful to relax this and define zero {\bf and only zero} to be {\em false} and anything that is not {\em false} is therefore {\em true}.% \footnote{This is how {\em true} and {\em false} behave in C, C++, and many other languages as well as the common assembly language idioms discussed in this text.} The reason for this relaxation is to describe the common case where the CPU processes data, multiple \gls{bit}s at-a-time. These groups have names like \gls{byte} (8 bits), \gls{halfword} (16 bits) and \gls{fullword} (32 bits). %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{NOT} The {\em NOT} operator applies to a single operand and represents the opposite of the input. \enote{Need to define unary, binary and ternary operators without confusing binary operators with binary numbers.} If the input is 1 then the output is 0. If the input is 0 then the output is 1. In other words, the output value is {\em not} that of the input value. Expressing the {\em not} function in the form of a truth table: \begin{center} \begin{tabular}{c|c} A & $\overline{\mbox{A}}$\\ \hline 0 & 1 \\ 1 & 0 \\ \end{tabular} \end{center} A truth table is drawn by indicating all of the possible input values on the left of the vertical bar with each row displaying the output values that correspond to the input for that row. The column headings are used to define the illustrated operation expressed using a mathematical notation. The {\em not} operation is indicated by the presence of an {\em overline}. In computer programming languages, things like an overline can not be efficiently expressed using a standard keyboard. Therefore it is common to use a notation such as that used by the C language when discussing the {\em NOT} operator in symbolic form. Specifically the tilde: `\verb@~@'. It is also uncommon to for programming languages to express boolean operations on single-bit input(s). A more generalized operation is used that applies to a set of bits all at once. For example, performing a {\em not} operation of eight bits at once can be illustrated as: \begin{verbatim} ~ 1 1 1 1 0 1 0 1 <== A ----------------- 0 0 0 0 1 0 1 0 <== output \end{verbatim} In a line of code the above might read like this: \verb@output = ~A@ %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{AND} The boolean {\em and} function has two or more inputs and the output is a single bit. The output is 1 if and only if all of the input values are 1. Otherwise it is 0. This function works like it does in spoken language. For example if A is 1 {\em and} B is 1 then the output is 1 (true). Otherwise the output is 0 (false). In mathematical notion, the {\em and} operator is expressed the same way as is {\em multiplication}. That is by a raised dot between, or by juxtaposition of, two variable names. It is also worth noting that, in base-2, the {\em and} operation actually {\em is} multiplication! \begin{center} \begin{tabular}{cc|c} A & B & AB \\ \hline 0 & 0 & 0 \\ 0 & 1 & 0 \\ 1 & 0 & 0 \\ 1 & 1 & 1 \\ \end{tabular} \end{center} This text will use the operator used in the C language when discussing the {\em and} operator in symbolic form. Specifically the ampersand: `\verb@&@'. An eight-bit example: \begin{verbatim} 1 1 1 1 0 1 0 1 <== A & 1 0 0 1 0 0 1 1 <== B ----------------- 1 0 0 1 0 0 0 1 <== output \end{verbatim} In a line of code the above might read like this: \verb@output = A & B@ %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{OR} The boolean {\em or} function has two or more inputs and the output is a single bit. The output is 1 if at least one of the input values are 1. This function works like it does in spoken language. For example if A is 1 {\em or} B is 1 then the output is 1 (true). Otherwise the output is 0 (false). In mathematical notion, the {\em or} operator is expressed using the plus ($+$). \begin{center} \begin{tabular}{cc|c} A & B & A$+$B \\ \hline 0 & 0 & 0 \\ 0 & 1 & 1 \\ 1 & 0 & 1 \\ 1 & 1 & 1 \\ \end{tabular} \end{center} This text will use the operator used in the C language when discussing the {\em or} operator in symbolic form. Specifically the pipe: `\verb@|@'. An eight-bit example: \begin{verbatim} 1 1 1 1 0 1 0 1 <== A | 1 0 0 1 0 0 1 1 <== B ----------------- 1 1 1 1 0 1 1 1 <== output \end{verbatim} In a line of code the above might read like this: \verb@output = A | B@ %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{XOR} The boolean {\em exclusive or} function has two or more inputs and the output is a single bit. The output is 1 if only an odd number of inputs are 1. Otherwise the output will be 0. Note that when {\em xor} is used with two inputs, the output is set to 1 (true) when the inputs have different values and 0 (false) when the inputs both have the same value. In mathematical notion, the {\em xor} operator is expressed using the plus in a circle ($\oplus$). \begin{center} \begin{tabular}{cc|c} A & B & A$\oplus{}$B \\ \hline 0 & 0 & 0 \\ 0 & 1 & 1 \\ 1 & 0 & 1 \\ 1 & 1 & 0 \\ \end{tabular} \end{center} This text will use the operator used in the C language when discussing the {\em xor} operator in symbolic form. Specifically the carrot: `\verb@^@'. An eight-bit example: \begin{verbatim} 1 1 1 1 0 1 0 1 <== A ^ 1 0 0 1 0 0 1 1 <== B ----------------- 0 1 1 0 0 1 1 0 <== output \end{verbatim} In a line of code the above might read like this: \verb@output = A ^ B@ %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \section{Integers and Counting} A binary integer is constructed with only 1s and 0s in the same manner as decimal numbers are constructed with values from 0 to 9. Counting in binary (base-2) uses the same basic rules as decimal (base-10). The difference is when we consider that there are ten decimal digits and only two binary digits. Therefore, in base-10, we must carry when adding one to nine (because there is no digit representing a ten) and, in base-2, we must carry when adding one to one (because there is no digit representing a two.) \autoref{Figure:integers} shows an abridged table of the decimal, binary and hexadecimal values ranging from $0_{10}$ to $128_{10}$. \begin{figure}[t] \begin{center} \begin{tabular}{|c|c|c||c|c|c|c|c|c|c|c||c|c|} \hline \multicolumn{3}{|c||}{Decimal} & \multicolumn{8}{|c||}{Binary} & \multicolumn{2}{|c|}{Hex}\\ \hline $10^2$ & $10^1$ & $10^0$ & $2^7$ & $2^6$ & $2^5$ & $2^4$ & $2^3$ & $2^2$ & $2^1$ & $2^0$ & $16^1$ & $16^0$ \\ \hline 100 & 10 & 1 & 128 & 64 & 32 & 16 & 8 & 4 & 2 & 1 & 16 & 1 \\ \hline \hline 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\ 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 1 \\ 0 & 0 & 2 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 2 \\ 0 & 0 & 3 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 1 & 0 & 3 \\ 0 & 0 & 4 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 4 \\ 0 & 0 & 5 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 1 & 0 & 5 \\ 0 & 0 & 6 & 0 & 0 & 0 & 0 & 0 & 1 & 1 & 0 & 0 & 6 \\ 0 & 0 & 7 & 0 & 0 & 0 & 0 & 0 & 1 & 1 & 1 & 0 & 7 \\ 0 & 0 & 8 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 8 \\ 0 & 0 & 9 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 1 & 0 & 9 \\ 0 & 1 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 1 & 0 & 0 & a \\ 0 & 1 & 1 & 0 & 0 & 0 & 0 & 1 & 0 & 1 & 1 & 0 & b \\ 0 & 1 & 2 & 0 & 0 & 0 & 0 & 1 & 1 & 0 & 0 & 0 & c \\ 0 & 1 & 3 & 0 & 0 & 0 & 0 & 1 & 1 & 0 & 1 & 0 & d \\ 0 & 1 & 4 & 0 & 0 & 0 & 0 & 1 & 1 & 1 & 0 & 0 & e \\ 0 & 1 & 5 & 0 & 0 & 0 & 0 & 1 & 1 & 1 & 1 & 0 & f \\ 0 & 1 & 6 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 1 & 0 \\ 0 & 1 & 7 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 1 & 1 & 1 \\ \hline \multicolumn{3}{|c||}{\ldots} & \multicolumn{8}{|c||}{\ldots} & \multicolumn{2}{|c|}{\ldots}\\ \hline 1 & 2 & 5 & 0 & 1 & 1 & 1 & 1 & 1 & 0 & 1 & 7 & d \\ 1 & 2 & 6 & 0 & 1 & 1 & 1 & 1 & 1 & 1 & 0 & 7 & e \\ 1 & 2 & 7 & 0 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 7 & f \\ 1 & 2 & 8 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 8 & 0 \\ \hline \end{tabular} \end{center} \captionof{figure}{Counting in decimal, binary and hexadecimal.} \label{Figure:integers} \end{figure} One way to look at this table is on a per-row basis where each \gls{place-value} is represented by the base raised to the power of the \gls{place-value} position (shown in the column headings.) %This is useful when converting arbitrary numeric values between bases. For example to interpret the decimal value on the fourth row: \begin{equation} 0 \times 10^2 + 0 \times 10^1 + 3 \times 10^0 = 3_{10} \end{equation} Interpreting the binary value on the fourth row by converting it to decimal: \begin{equation} 0 \times 2^7 + 0 \times 2^6 +0 \times 2^5 +0 \times 2^4 +0 \times 2^3 +0 \times 2^2 + 1 \times 2^1 + 1 \times 2^0 = 3_{10} \end{equation} Interpreting the hexadecimal value on the fourth row by converting it to decimal: \begin{equation} 0 \times 16^1 + 3 \times 16^0 = 3_{10} \end{equation} \index{Most significant bit}\index{MSB|see {Most significant bit}}% \index{Least significant bit}\index{LSB|see {Least significant bit}}% We refer to the place values with the largest exponent (the one furthest to the left for any given base) as the most significant digit and the place value with the lowest exponent as the least significant digit. For binary numbers these are the \acrfull{msb} and \acrfull{lsb} respectively.% \footnote{Changing the value of the MSB will have a more {\em significant} impact on the numeric value than changing the value of the LSB.} Another way to look at this table is on a per-column basis. When tasked with drawing such a table by hand, it might be useful to observe that, just as in decimal, the right-most column will cycle through all of the values represented in the chosen base then cycle back to zero and repeat. (For example, in binary this pattern is 0-1-0-1-0-1-0-\ldots) The next column in each base will cycle in the same manner except each of the values is repeated as many times as is represented by the place value (in the case of decimal, $10^1$ times, binary $2^1$ times, hex $16^1$ times. Again, the binary numbers for this pattern are 0-0-1-1-0-0-1-1-\ldots) This continues for as many columns as are needed to represent the magnitude of the desired number. Another item worth noting is that any even binary number will always have a 0 LSB and odd numbers will always have a 1 LSB. As is customary in decimal, leading zeros are sometimes not shown for readability. The relationship between binary and hex values is also worth taking note. Because $2^4 = 16$, there is a clean and simple grouping of 4 \gls{bit}s to 1 \gls{hit} (aka \gls{nybble}). There is no such relationship between binary and decimal. Writing and reading numbers in binary that are longer than 8 bits is cumbersome and prone to error. The simple conversion between binary and hex makes hex a convenient shorthand for expressing binary values in many situations. For example, consider the following value expressed in binary, hexadecimal and decimal (spaced to show the relationship between binary and hex): \begin{verbatim} Binary value: 0010 0111 1011 1010 1100 1100 1111 0101 Hex Value: 2 7 B A C C F 5 Decimal Value: 666553589 \end{verbatim} Empirically we can see that grouping the bits into sets of four allows an easy conversion to hex and expressing it as such is $\frac{1}{4}$ as long as in binary while at the same time allowing for easy conversion back to binary. The decimal value in this example does not easily convey a sense of the binary value. \begin{tcolorbox} In programming languages like the C, its derivatives and RISC-V assembly, numeric values are interpreted as decimal {\bfseries unless} they start with a zero (0). Numbers that start with 0 are interpreted as octal (base-8), numbers starting with 0x are interpreted as hexadecimal and numbers that start with 0b are interpreted as binary. \end{tcolorbox} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{Converting Between Bases} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsubsection{From Binary to Decimal} \label{section:bindec} It is occasionally necessary to convert between decimal, binary and/or hex. To convert from binary to decimal, put the decimal value of the \gls{place-value}s {\ldots8, 4, 2, 1} over the binary digits like this: \begin{verbatim} Base-2 place values: 128 64 32 16 8 4 2 1 Binary: 0 0 0 1 1 0 1 1 Decimal: 16 +8 +2 +1 = 27 \end{verbatim} Now sum the place-values that are expressed in decimal for each bit with the value of 1: $16+8+2+1$. The integer binary value $00011011_2$ represents the decimal value $27_{10}$. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsubsection{From Binary to Hexadecimal} \label{section:binhex} Conversion from binary to hex involves grouping the bits into sets of four and then performing the same summing process as shown above. If there is not a multiple of four bits then extend the binary to the left with zeros to make it so. Grouping the bits into sets of four and summing: \begin{verbatim} Base-2 place values: 8 4 2 1 8 4 2 1 8 4 2 1 8 4 2 1 Binary: 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 0 Decimal: 4+2 =6 8+4+ 1=13 8+ 2 =10 8+4+2 =14 \end{verbatim} After the summing, convert each decimal value to hex. The decimal values from 0--9 are the same values in hex. Because we don't have any more numerals to represent the values from 10-15, we use the first 6 letters (See the right-most column of \autoref{Figure:integers}.) Fortunately there are only six hex mappings involving letters. Thus it is reasonable to memorize them. Continuing this example: \begin{verbatim} Decimal: 6 13 10 14 Hex: 6 D A E \end{verbatim} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsubsection{From Hexadecimal to Binary} The four-bit mapping between binary and hex makes this task as straight forward as using a look-up table to translate each \gls{hit} (Hex digIT) it to its unique four-bit pattern. Perform this task either by memorizing each of the 16 patterns or by converting each hit to decimal first and then converting each four-bit binary value to decimal using the place-value summing method discussed in \autoref{section:bindec}. For example: \begin{verbatim} Hex: 7 C Decimal Sum: 4+2+1=7 8+4 =12 Binary: 0 1 1 1 1 1 0 0 \end{verbatim} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsubsection{From Decimal to Binary} To convert arbitrary decimal numbers to binary, extend the list of binary place values until it exceeds the value of the decimal number being converted. Then make successive subtractions of each of the place values that would yield a non-negative result. For example, to convert $1234_{10}$ to binary: \begin{verbatim} Base-2 place values: 2048-1024-512-256-128-64-32-16-8-4-2-1 0 2048 (too big) 1 1234 - 1024 = 210 0 512 (too big) 0 256 (too big) 1 210 - 128 = 82 1 82 - 64 = 18 0 32 (too big) 1 18 - 16 = 2 0 8 (too big) 0 4 (too big) 1 2 - 2 = 0 0 1 (too big) \end{verbatim} The answer using this notation is listed vertically in the left column with the \acrshort{msb} on the top and the \acrshort{lsb} on the bottom line: $010011010010_2$. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsubsection{From Decimal to Hex} Conversion from decimal to hex can be done by using the place values for base-16 and the same math as from decimal to binary or by first converting the decimal value to binary and then from binary to hex by using the methods discussed above. Because binary and hex are so closely related, performing a conversion by way of binary is straight forward. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{Addition of Binary Numbers} The addition of binary numbers can be performed long-hand the same way decimal addition is taught in grade school. In fact binary addition is easier since it only involves adding 0 or 1. The first thing to note that in any number base $0+0=0$, $0+1=1$, and $1+0=1$. Since there is no ``two'' in binary (just like there is no ``ten'' decimal) adding $1+1$ results in a zero with a carry as in: $1+1=10_2$ and in: $1+1+1=11_2$. Using these five sums, any two binary integers can be added. \index{Full Adder}% This truth table shows what is called a {\em full adder}. A full adder is a function that can add three input bits (the two addends and a carry value from a ``prior column'') and produce the sum and carry output values.\footnote{ Note that the sum could be expressed in Boolean Algebra as: $sum = ci \oplus{} a \oplus{} b$} \begin{center} \begin{tabular}{|ccc|cc|} \hline %\multicolumn{3}{c}{input} & \multicolumn{2}{c}{output}\\ $ci$ & $a$ & $b$ & $co$ & $sum$\\ \hline 0 & 0 & 0 & 0 & 0 \\ 0 & 0 & 1 & 0 & 1 \\ 0 & 1 & 0 & 0 & 1 \\ 0 & 1 & 1 & 1 & 0 \\ 1 & 0 & 0 & 0 & 1 \\ 1 & 0 & 1 & 1 & 0 \\ 1 & 1 & 0 & 1 & 0 \\ 1 & 1 & 1 & 1 & 1 \\ \hline \end{tabular} \end{center} Adding two unsigned binary numbers using 16 full adders: \begin{verbatim} 111111 1111 <== carries 0110101111001111 <== addend + 0000011101100011 <== addend ------------------ 0111001100110010 <== sum \end{verbatim} Note that the carry ``into'' the LSB is zero. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{Signed Numbers} There are multiple methods used to represent signed binary integers. The method used by most modern computers is called {\em two's complement}. A two's complement number is encoded in such a manner as to simplify the hardware used to add, subtract and compare integers. A simple method of thinking about two's complement numbers is to negate the place value of the \acrshort{msb}. For example, the number one is represented the same as discussed before: \begin{verbatim} Base-2 place values: -128 64 32 16 8 4 2 1 Binary: 0 0 0 0 0 0 0 1 \end{verbatim} The \acrshort{msb} of any negative number in this format will always be 1. For example the value $-1_{10}$ is: \begin{verbatim} Base-2 place values: -128 64 32 16 8 4 2 1 Binary: 1 1 1 1 1 1 1 1 \end{verbatim} \ldots because: $-128+64+32+16+8+4+2+1=-1$. This format has the virtue of allowing the same addition logic discussed above to be used to calculate the sums of signed numbers as unsigned numbers. Calculating the signed addition: $4+5 = 9$ \begin{verbatim} 1 <== carries 000100 <== 4 = 0 + 0 + 0 + 4 + 0 + 0 +000101 <== 5 = 0 + 0 + 0 + 4 + 0 + 1 ------- 001001 <== 9 = 0 + 0 + 8 + 0 + 0 + 1 \end{verbatim} Calculating the signed addition: $-4+ -5 = -9$ \begin{verbatim} 1 11 <== carries 111100 <== -4 = -32 + 16 + 8 + 4 + 0 + 0 +111011 <== -5 = -32 + 16 + 8 + 0 + 2 + 1 --------- 1 110111 <== -9 (with a truncation) = -32 + 16 + 4 + 2 + 1 = -9 \end{verbatim} Calculating the signed addition: $-1+1=0$ \begin{verbatim} -128 64 32 16 8 4 2 1 <== place value 1 1 1 1 1 1 1 1 <== carries 1 1 1 1 1 1 1 1 <== addend (-1) + 0 0 0 0 0 0 0 1 <== addend (1) ---------------------- 1 0 0 0 0 0 0 0 0 <== sum (0 with a truncation) \end{verbatim} {\em In order for this to work, the carry out of the sum of the MSBs {\bfseries must} be discarded.} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsubsection{Converting between Positive and Negative} Changing the sign on two's complement numbers can be described as inverting all of the bits (which is also known as the {\em one's complement}) and then add one. For example, negating the number four: \begin{minipage}{\textwidth} \begin{verbatim} -128 64 32 16 8 4 2 1 0 0 0 0 0 1 0 0 <== 4 1 1 <== carries 1 1 1 1 1 0 1 1 <== one's complement of 4 + 0 0 0 0 0 0 0 1 <== plus 1 ---------------------- 1 1 1 1 1 1 0 0 <== -4 \end{verbatim} \end{minipage} This can be verified by adding 5 to the result and observe that the sum is 1: \begin{verbatim} -128 64 32 16 8 4 2 1 1 1 1 1 1 1 <== carries 1 1 1 1 1 1 0 0 <== -4 + 0 0 0 0 0 1 0 1 <== 5 ---------------------- 1 0 0 0 0 0 0 0 1 <== 1 (with a truncation) \end{verbatim} Note that the changing of the sign using this method is symmetric in that it is identical when converting from negative to positive and when converting from positive to negative: {\em flip the bits and add 1.} For example, changing the value -4 to 4 to illustrate the reverse of the conversion above: \begin{verbatim} -128 64 32 16 8 4 2 1 1 1 1 1 1 1 0 0 <== -4 1 1 <== carries 0 0 0 0 0 0 1 1 <== one's complement of -4 + 0 0 0 0 0 0 0 1 <== plus 1 ---------------------- 0 0 0 0 0 1 0 0 <== 4 \end{verbatim} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{Subtraction of Binary Numbers} Subtraction% \enote{This section needs more examples of subtracting signed an unsigned numbers and a discussion on how signedness is not relevant until the results are interpreted. For example adding $-4+ -8=-12$ using two 8-bit numbers is the same as adding $252+248=500$ and truncating the result to 244.} of binary numbers is performed by first negating the subtrahend and then adding the two numbers. Due to the nature of two's complement numbers this method will work for both signed and unsigned numbers! Observation: Since we always have a carry-in of zero into the LSB when adding, we can take advantage of that fact by (ab)using that carry input to perform that adding the extra 1 to the subtrahend as part of changing its sign in the examples below. An example showing the subtraction of two {\em signed} binary numbers: $-4-8 = -12$ \begin{verbatim} -128 64 32 16 8 4 2 1 1 1 1 1 1 1 0 0 <== -4 (minuend) - 0 0 0 0 1 0 0 0 <== 8 (subtrahend) ------------------------ 1 1 1 1 1 1 1 1 1 <== carries 1 1 1 1 1 1 0 0 <== -4 + 1 1 1 1 0 1 1 1 <== one's complement of 8 ------------------------ 1 1 1 1 1 0 1 0 0 <== -12 \end{verbatim} %An example showing the subtraction of two {\em unsigned} binary numbers: $252+248=500$ % %\begin{verbatim} % 128 64 32 16 8 4 2 1 % % 1 1 1 1 1 <== carries % 1 1 1 1 1 1 0 0 <== 252 % + 1 1 1 1 1 0 0 0 <== 248 % ---------------------- % 1 1 1 1 1 0 1 0 0 < == 500 (if we do NOT truncate the MSB) %\end{verbatim} % %An example showing the subtraction of two {\em unsigned} binary numbers: $252+248=500$ %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{Truncation} \index{truncation} \index{overflow} \index{carry} Discarding the carry bit that can be generated from the MSB is called {\em truncation}. So far we have been ignoring the carries that can come from the MSBs when adding and subtracting. We have also been ignoring the potential impact of a carry causing a signed number to change its sign in an unexpected way. In the examples above, truncating the results either had 1) no impact on the calculated sums or 2) was absolutely necessary to correct the sum in cases such as: $-4 + 5$. For example, note what happens when we try to subtract 1 from the most negative value that we can represent in a 4 bit two's complement number: \begin{verbatim} -8 4 2 1 1 0 0 0 <== -8 (minuend) - 0 0 0 1 <== 1 (subtrahend) ------------ 1 1 <== carries 1 0 0 0 <== -8 + 1 1 1 0 <== one's complement of 1 ---------- 1 0 1 1 1 <== this SHOULD be -9 but with truncation it is 7 \end{verbatim} The problem with this example is that we can not represent $-9_{10}$ using a 4-bit two's complement number. Granted, if we would have used 5 bit numbers, then the ``answer'' would have fit OK. But the same problem would return when trying to calculate $-16 - 1$. So simply ``making more room'' does not solve this problem. %However, as calculating $-1+1=0$ has demonmstrated above, it was necessary for that %case to discard the carry out of the MSB to get the correct result. %In the case of calculating $-1+1=0$ the addends and result all fit into same-sized %(8-bit) values. When calculating $-8-1=-9$ the addends each can fit into 4-bit %two's complement numbers but the result would require a 5-bit number. This is not just a problem when subtracting, nor is it just a problem with signed numbers. The same situation can happen {\em unsigned} numbers. For example: \begin{verbatim} 8 4 2 1 1 1 1 0 0 <== carries 1 1 1 0 <== 14 (addend) + 0 0 1 1 <== 3 (addend) ------------ 1 0 0 0 1 <== this SHOULD be 17 but with truncation it is 1 \end{verbatim} How to handle such a truncation depends on whether the {\em original} values being added are signed or unsigned. The RV ISA refers to the discarding the carry out of the MSB after an add (or subtract) of two {\em unsigned} numbers as an {\em unsigned overflow}% \footnote{Most microprocessors refer to {\em unsigned overflow} simply as a {\em carry} condition.} and the situation where carries create an incorrect sign in the result of adding (or subtracting) two {\em signed} numbers as a {\em signed overflow}.~\cite[p.~13]{rvismv1v22:2017} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsubsection{Unsigned Overflow} \index{overflow!unsigned} When adding {\em unsigned} numbers, an overflow only occurs when there is a carry out of the MSB resulting in a sum that is truncated to fit into the number of bits allocated to contain the result. \autoref{sum:240+17} illustrates an unsigned overflow during addition: \begin{figure}[H] \centering \begin{BVerbatim} 1 1 1 1 0 0 0 0 0 <== carries 1 1 1 1 0 0 0 0 <== 240 + 0 0 0 1 0 0 0 1 <== 17 --------------------- 1 0 0 0 0 0 0 0 1 <== sum = 1 \end{BVerbatim} %{\captionof{figure}{$240+16=0$ (overflow)}\label{sum:240+17}} \caption{$240+17=1$ (overflow)} \label{sum:240+17} \end{figure} Some times an overflow like this is referred to as a {\em wrap around} because of the way that successive additions will result in a value that increases until it {\em wraps} back {\em around} to zero and then returns to increasing in value until it, again, wraps around again. \begin{tcolorbox} When adding, {\em unsigned overflow} occurs when ever there is a carry {\em out of} the most significant bit. \end{tcolorbox} When subtracting {\em unsigned} numbers, an overflow only occurs when the subtrahend is greater than the minuend (because in those cases the difference would be negative but no negative values can be represented with an unsigned binary number.) \autoref{sum:3-4} illustrates an unsigned overflow during subtraction: \begin{figure}[H] \centering \begin{BVerbatim} 0 0 0 0 0 0 1 1 <== 3 (minuend) - 0 0 0 0 0 1 0 0 <== 4 (subtrahend) ----------------- 0 0 0 0 0 0 1 1 1 <== carries 0 0 0 0 0 0 1 1 <== 3 + 1 1 1 1 1 0 1 1 <== one's complement of 4 ----------------- 1 1 1 1 1 1 1 1 <== 255 (overflow) \end{BVerbatim} \caption{$3-4=255$ (overflow)} \label{sum:3-4} \end{figure} \begin{tcolorbox} When subtracting, {\em unsigned overflow} occurs when ever there is {\em not} a carry {\em out of} the most significant bit (IFF the carry-in on the LSB is used to add the extra 1 to the subtrahend when changing its sign.) \end{tcolorbox} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsubsection{Signed Overflow} \index{overflow!signed} When adding {\em signed} numbers, an overflow only occurs when the two addends are positive and sum is negative or the addends are both negative and the sum is positive. When subtracting {\em signed} numbers, an overflow only occurs when the minuend is positive and the subtrahend is negative and difference is negative or when the minuend is negative and the subtrahend is positive and the difference is positive.% \footnote{I had to look it up to remember which were which too\ldots\ it is: minuend - subtrahend = difference.\cite{subtrahend}} Consider the results of the addition of two {\em signed} numbers while looking more closely at the carry values. \begin{figure}[H] \centering \begin{BVerbatim} 0 1 0 0 0 0 0 0 0 <== carries 0 1 0 0 0 0 0 0 <== 64 + 0 1 0 0 0 0 0 0 <== 64 --------------------- 1 0 0 0 0 0 0 0 <== sum = -128 \end{BVerbatim} \caption{$64+64 = -128$ (overflow)} \label{sum:64+64} \end{figure} \autoref{sum:64+64} is an example of {\em signed overflow}. As shown, the problem is that the sum of two positive numbers has resulted in an obviously incorrect negative result due to a carry flowing into the sign-bit in the MSB. Granted, if the same values were added using values larger than 8-bits then the sum would have been correct. However, these examples assume that all the operations are performed on (and results stored into) 8-bit values. Given any finite-number of bits, there are values that could be added such that an overflow occurs. \index{truncation} \autoref{sum:-128+-128} shows another overflow situation that is caused by the fact that there is nowhere for the carry out of the sign-bit to go. We say that this result has been {\em truncated}. \begin{figure}[H] \centering \begin{BVerbatim} 1 0 0 0 0 0 0 0 0 <== carries 1 0 0 0 0 0 0 0 <== -128 + 1 0 0 0 0 0 0 0 <== -128 --------------------- 0 0 0 0 0 0 0 0 <== sum = 0 \end{BVerbatim} \caption{$-128+-128 = 0$ (overflow)} \label{sum:-128+-128} \end{figure} Truncation is not necessarily a problem. Consider the truncations in figures \ref{sum:-3+-5} and \ref{sum:-2+10}. \autoref{sum:-2+10} demonstrates the importance of discarding the carry from the sum of the MSBs of signed numbers when addends do not have the same sign. \begin{figure}[H] \centering \begin{BVerbatim} 1 1 1 1 1 1 1 1 0 <== carries 1 1 1 1 1 1 0 1 <== -3 + 1 1 1 1 1 0 1 1 <== -5 --------------------- 1 1 1 1 1 0 0 0 <== sum = -8 \end{BVerbatim} \captionof{figure}{$-3+-5 = -8$} \label{sum:-3+-5} \end{figure} \begin{figure}[H] \centering \begin{BVerbatim} 1 1 1 1 1 1 1 0 0 <== carries 1 1 1 1 1 1 1 0 <== -2 + 0 0 0 0 1 0 1 0 <== 10 --------------------- 0 0 0 0 1 0 0 0 <== sum = 8 \end{BVerbatim} \captionof{figure}{$-2+10 = 8$} \label{sum:-2+10} \end{figure} Just like an unsigned number can wrap around as a result of successive additions, a signed number can so the same thing. The only difference is that signed numbers won't wrap from the maximum value back to zero, instead it will wrap from the most positive to the most negative value as shown in \autoref{sum:127+1}. \begin{figure}[H] \centering \begin{BVerbatim} 0 1 1 1 1 1 1 1 0 <== carries 0 1 1 1 1 1 1 1 <== 127 + 0 0 0 0 0 0 0 1 <== 1 --------------------- 1 0 0 0 0 0 0 0 <== sum = -128 \end{BVerbatim} \captionof{figure}{$127+1 = -128$} \label{sum:127+1} \end{figure} \begin{tcolorbox} Formally, a {\em signed overflow} occurs when ever the carry {\em into} the most significant bit is not the same as the carry {\em out of} the most significant bit. \end{tcolorbox} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \section{Sign and Zero Extension} \index{sign extension} \label{SignExtension} Due to the nature of the two's complement encoding scheme, the following numbers all represent the same value: \begin{verbatim} 1111 <== -1 11111111 <== -1 11111111111111111111 <== -1 1111111111111111111111111111 <== -1 \end{verbatim} As do these: \begin{verbatim} 01100 <== 12 0000001100 <== 12 00000000000000000000000000000001100 <== 12 \end{verbatim} The lengthening of these numbers by replicating the digits on the left is what is called {\em sign extension}. \begin{tcolorbox} Any signed number can have any quantity of additional MSBs added to it, provided that they repeat the value of the sign bit. \end{tcolorbox} \autoref{Figure:SignExtendNegative} illustrates extending the negative sign bit to the left by replicating it. A negative number will have its \acrshort{msb} (bit 19 in this example) set to 1. Extending this value to the left will set all the new bits to the left of it to 1 as well. \begin{figure}[ht] \centering \DrawBitBoxSignExtendedPicture{32}{10100000000000000010} \captionof{figure}{Sign-extending a negative integer from 20 bits to 32 bits.} \label{Figure:SignExtendNegative} \end{figure} \autoref{Figure:SignExtendPositive} illustrates extending the sign bit of a positive number to the left by replicating it. A positive number will have its \acrshort{msb} set to 0. Extending this value to the left will set all the new bits to the left of it to 0 as well. \begin{figure}[ht] \centering \DrawBitBoxSignExtendedPicture{32}{01000000000000000010} \captionof{figure}{Sign-extending a positive integer from 20 bits to 32 bits.} \label{Figure:SignExtendPositive} \end{figure} \label{ZeroExtension} In a similar vein, any unsigned number also may have any quantity of additional MSBs added to it provided that they are all zero. This is called {\em zero extension}. For example, the following all represent the same value: \begin{verbatim} 1111 <== 15 01111 <== 15 00000000000000000000000001111 <== 15 \end{verbatim} \begin{tcolorbox} Any {\em unsigned} number may be {\em zero extended} to any size. \end{tcolorbox} \enote{Remove the sign-bit boxes from this figure?}% \autoref{Figure:ZeroExtend} illustrates zero-extending a 20-bit number to the left to form a 32-bit number. \begin{figure}[ht] \centering \DrawBitBoxZeroExtendedPicture{32}{10000000000000000010} \captionof{figure}{Zero-extending an unsigned integer from 20 bits to 32 bits.} \label{Figure:ZeroExtend} \end{figure} %Sign- and zero-extending binary numbers are common operations used to %fit a byte or halfword into a fullword. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \section{Shifting} \label{shifting} We were all taught how to multiply and divide decimal numbers by ten by moving (or {\em shifting}) the decimal point to the right or left respectively. Doing the same in any other base has the same effect in that it will multiply or divide the number by its base. \enote{Include decimal values in the shift diagrams.}% Multiplication and division are only two reasons for shifting. There can be other occasions where doing so is useful. As implemented by a CPU, shifting applies to the value in a register and the results stored back into a register of finite size. Therefore a shift result will always be truncated to fit into a register. \enote{Add some examples showing the rounding of positive and negative values.}% Note that when dealing with numeric values, any truncation performed during a right-shift will manifest itself as rounding toward zero. \subsection{Logical Shifting} Shifting {\em logically} to the left or right is a matter of re-aligning the bits in a register and truncating the result. \enote{Redraw these with arrows tracking the shifted bits and the truncated values}% To shift left two positions: \DrawBitBoxUnsignedPicture{10111000000000000010}\\ \DrawBitBoxUnsignedPicture{11100000000000001000} To shift right one position: \DrawBitBoxUnsignedPicture{10111000000000000010}\\ \DrawBitBoxUnsignedPicture{01011100000000000001} \begin{tcolorbox} Note that the vacated bit positions are always filled with zero. \end{tcolorbox} \subsection{Arithmetic Shifting} Some times it is desirable to retain the value of the sign bit when shifting. The RISC-V ISA provides an arithmetic right shift instruction for this purpose (there is no arithmetic left shift for this ISA.) \begin{tcolorbox} When shifting to the right {\em arithmetically}, vacated bit positions are filled by replicating the value of the sign bit. \end{tcolorbox} An arithmetic right shift of a negative number by 4 bit positions: \DrawBitBoxSignedPicture{10111000000000000010}\\ \DrawBitBoxSignedPicture{11111011100000000000} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \section{Main Memory Storage} As mentioned in \autoref{VolatileStorage}, the main memory in a RISC-V system is byte-addressable. For that reason we will visualize it by displaying ranges of bytes displayed in hex and in \gls{ascii}. As will become obvious, the ASCII part makes it easier to find text messages.% \footnote{Most of the memory dumps in this text are generated by \gls{rvddt} and are shown on a per-byte basis without any attempt to reorder their values. Some other applications used to dump memory do not dump the bytes in address-order! It is important to know how your software tools operate when using them to dump the contents of memory and/or files.} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{Memory Dump} \listingRef{rvddt_memdump.out} shows a {\em memory dump} from the rvddt `d' command requesting a dump starting at address \hex{00002600} for the default quantity (\hex{100}) of bytes. \listing{rvddt_memdump.out}{{\tt rvddt} memory dump} \begin{itemize} \item [$\ell$ 1] The rvddt prompt showing the dump command. \item [$\ell$ 2] From left to right. the dump is presented as the address of the first byte (\hex{00002600}) followed by a colon, the value of the byte at address \hex{00002600} expressed in hex, the next byte (at address \hex{00002601}) and so on for 16 bytes. There is a double-space between the 7th and 8th bytes to help provide a visual reference for the center to make it easy to locate bytes on the right end. For example, the byte at address \hex{0000260c} is four bytes to the right of byte number eight (at the gap) and contains \hex{13}. To the right of the 16-bytes is an asterisk-enclosed set of 16 columns showing the ASCII characters that each byte represents. If a byte has a value that corresponds to a printable character code, the character will be displayed. For any illegal/un-displayable byte values, a dot is shown to make it easier to count the columns. \item [$\ell$ 3-17] More of the same as seen on $\ell$ 2. The address at the left can be seen to advance by $16_{10}$ (or $10_{16}$) for each line shown. \end{itemize} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{Endianness} The choice of which end of a multi-byte value is to be stored at the lowest byte address is referred to as {\em endianness.} For example, if a CPU were to store a \gls{halfword} into memory, should the byte containing the \acrfull{msb} (the {\em big} end) go first or does the byte with the \acrfull{lsb} (the {\em little} end) go first? On the one hand the choice is arbitrary. On the other hand, it is possible that the choice could impact the performance of the system.% \footnote{See\cite{IEN137} for some history of the big/little-endian ``controversy.''} IBM mainframe CPUs and the 68000 family store their bytes in big-endian order. While the Intel Pentium and most embedded processors use little-endian order. Some CPUs are even {\em bi-endian} in that they have instructions that can change their order on the fly. The RISC-V system uses the little-endian byte order. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsubsection{Big-Endian} \label{BigEndian} \index{big-endian} Using the contents of \listingRef{rvddt_memdump.out}, a \gls{bigendian} CPU would interpret the contents as follows: \begin{itemize} \item The 8-bit value read from address \colorbox{c_lightblue}{\hex{00002658}} would be \verb@0x@{\color{red}\verb@76@}. \item The 8-bit value read from address \hex{00002659} would be \hex{61}. \item The 8-bit value read from address \hex{0000265a} would be \hex{6c}. \item The 8-bit value read from address \hex{0000265b} would be \hex{3d}. \item The 16-bit value read from address \colorbox{c_lightblue}{\hex{00002658}} would be \verb@0x@{\color{red}\verb@76@}\verb@61@. \item The 16-bit value read from address \hex{0000265a} would be \hex{6c3d}. \item The 32-bit value read from address \colorbox{c_lightblue}{\hex{00002658}} would be \verb@0x@{\color{red}\verb@76@}\verb@616c3d@. \end{itemize} Notice that in a big-endian system, the {\em\gls{place-value}s} of the bits comprising the \verb@0x@{\color{red}\verb@76@} (located at memory address \colorbox{c_lightblue}{\hex{00002658}}) are {\em different} depending on the number of bytes representing the value that is being read. For example, when a 16-bit value is read from \colorbox{c_lightblue}{\hex{00002658}} then the {\color{red}\verb@76@} represents the binary place values: $2^{15}$ to $2^8$. When a 32-bit value is read then the {\color{red}\verb@76@} represents the binary place values: $2^{31}$ to $2^{24}$. In other words the value read from the first memory location (with the lowest address), of the plurality of addresses containing the complete value being read, is always placed on the {\em left end}, into the Most Significant Bits. One might dare say that the {\color{red}\verb@76@} is placed at the end with the {\em big} place values. More examples: \begin{itemize} \item An 8-bit value read from address \colorbox{c_lightgreen}{\hex{00002624}} would be \verb@0x@{\color{red}\verb@23@}. \item An 8-bit value read from address \hex{00002625} would be \hex{24}. \item An 8-bit value read from address \hex{00002626} would be \hex{81}. \item An 8-bit value read from address \hex{00002627} would be \hex{00}. \item A 16-bit value read from address \colorbox{c_lightgreen}{\hex{00002624}} would be \verb@0x@{\color{red}\verb@23@}\verb@24@. \item A 16-bit value read from address \hex{00002626} would be \hex{8100}. \item A 32-bit value read from address \colorbox{c_lightgreen}{\hex{00002624}} would be \verb@0x@{\color{red}\verb@23@}\verb@248100@. \end{itemize} Again, notice that the byte from memory address \colorbox{c_lightgreen}{\hex{00002624}}, regardless of the {\em number} of bytes comprising the complete value being fetched, will always appear on the left/{\em big} end of the final value. \begin{tcolorbox} On a big-endian system, the bytes in the dump are in the same order as they would be used by the CPU if it were to read them as a multi-byte value. \end{tcolorbox} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsubsection{Little-Endian} \label{LittleEndian} \index{little-endian} Using the contents of \listingRef{rvddt_memdump.out}, a \gls{littleendian} CPU would interpret the contents as follows: \begin{itemize} \item An 8-bit value read from address \colorbox{c_lightblue}{\hex{00002658}} would be \verb@0x@{\color{red}\verb@76@}. \item An 8-bit value read from address \hex{00002659} would be \hex{61}. \item An 8-bit value read from address \hex{0000265a} would be \hex{6c}. \item An 8-bit value read from address \hex{0000265b} would be \hex{3d}. \item A 16-bit value read from address \colorbox{c_lightblue}{\hex{00002658}} would be \verb@0x61@{\color{red}\verb@76@}. \item A 16-bit value read from address \hex{0000265a} would be \hex{3d6c}. \item A 32-bit value read from address \colorbox{c_lightblue}{\hex{00002658}} would be \verb@0x3d6c61@{\color{red}\verb@76@}. \end{itemize} Notice that in a little-endian system, the {\em\gls{place-value}s} of the bits comprising the \verb@0x@{\color{red}\verb@76@} (located at memory address \colorbox{c_lightblue}{\hex{00002658}}) are the {\em same} regardless of the the number of bytes representing the value that is being read. Unlike the behavior of a big-endian machine, when little-endian machine reads a 16-bit value from \colorbox{c_lightblue}{\hex{00002658}} the {\color{red}\verb@76@} represents the binary place values from $2^{7}$ to $2^0$. When a 32-bit value is read then the {\color{red}\verb@76@} (still) represents the binary place values from $2^{7}$ to $2^{0}$. In other words the value read from the first memory location (with the lowest address), of the plurality of addresses containing the complete value being read, is always placed on the {\em right end}, into the Least Significant Bits. One might say that the {\color{red}\verb@76@} is placed at the end with the {\em little} place values. Also notice that it is the {\em bytes} are what are ``reversed'' in a little-endian system ({\em not} the hex digits.) More examples: \begin{itemize} \item The 8-bit value read from address \colorbox{c_lightgreen}{\hex{00002624}} would be \verb@0x@{\color{red}\verb@23@}. \item The 8-bit value read from address \hex{00002625} would be \hex{24}. \item The 8-bit value read from address \hex{00002626} would be \hex{81}. \item The 8-bit value read from address \hex{00002627} would be \hex{00}. \item The 16-bit value read from address \colorbox{c_lightgreen}{\hex{00002624}} would be \verb@0x24@{\color{red}\verb@23@}. \item The 16-bit value read from address \hex{00002626} would be \hex{0081}. \item The 32-bit value read from address \colorbox{c_lightgreen}{\hex{00002624}} would be \verb@0x008124@{\color{red}\verb@23@}. \end{itemize} As above, notice that the byte from memory address \colorbox{c_lightgreen}{\hex{00002624}}, regardless of the {\em number} of bytes comprising the complete value being fetched, will always appear on the right/{\em little} end of the final value. \begin{tcolorbox} On a little-endian system, the bytes in the dump are in reverse order as they would be used by the CPU if it were to read them as a multi-byte value. \end{tcolorbox} In the RISC-V ISA it is noted that \begin{quote} A minor point is that we have also found little-endian memory systems to be more natural for hardware designers. However, certain application areas, such as IP networking, operate on big-endian data structures, and so we leave open the possibility of non-standard big-endian or bi-endian systems.''\cite[p.~6]{rvismv1v22:2017} \end{quote} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{Arrays and Character Strings} While Endianness defines how single values are stored in memory, the {\em array} defines how multiple values are stored. An array is a data structure comprised of an ordered set of elements. This text will limit its definition of array to a plurality of elements that are all of the same type. Where type refers to the size (number of bytes) and representation (signed, unsigned,\ldots) of each element. In an array, the elements are stored adjacent to one another such that the address $e$ of any element $x[n]$ is: \begin{equation} e = a + n * s \end{equation} Where $x$ is the name of the array, $n$ is the element number of interest, $e$ is the address of interest, $a$ is the address of the first element in the array and $s$ is the size (in bytes) of each element. Given an array $x$ containing $m$ elements, $x[0]$ is the first element of the array and $x[m-1]$ is the last element of the array.% \footnote{Some computing languages (C, C++, Java, C\#, Python, Perl,\ldots) define an array such that the first element is indexed as $x[0]$. While others (FORTRAN, MATLAB) define the first element of an array to be $x[1]$.} Using this definition, and the memory dump shown in \listingRef{rvddt_memdump.out}, and the knowledge that we are using a little-endian machine and given that $a = $ \hex{00002656} and $s = 2$, the values of the first 8 elements of array $x$ are: \begin{itemize} \item $x[0]$ is \hex{0000} and is stored at \hex{00002656}. \item $x[1]$ is \hex{6176} and is stored at \hex{00002658}. \item $x[2]$ is \hex{3d6c} and is stored at \hex{0000265a}. \item $x[3]$ is \hex{0000} and is stored at \hex{0000265c}. \item $x[4]$ is \hex{0000} and is stored at \hex{00002660}. \item $x[5]$ is \hex{0000} and is stored at \hex{00002662}. \item $x[6]$ is \hex{8480} and is stored at \hex{00002664}. \item $x[7]$ is \hex{412e} and is stored at \hex{00002666}. \end{itemize} \begin{tcolorbox} In general, there is no fixed rule nor notion as to how many elements an array has. It is up to the programmer to ensure that the starting address and the number of elements in any given array (its size) are used properly so that data bytes outside an array are not accidentally used as elements. \end{tcolorbox} There is, however, a common convention used for an array of characters that is used to hold a text message (called a {\em character string} or just {\em string}). When an array is used to hold a string the element past the last character in the string is set to zero. This is because 1) zero is not a valid printable ASCII character and 2) it simplifies software in that knowing no more than the starting address of a string is all that is needed to processes it. Without this zero {\em sentinel} value (called a {\em null} terminator), some knowledge of the number of characters in the string would have to otherwise be conveyed to any code needing to consume or process the string. In \listingRef{rvddt_memdump.out}, the 5-byte long array starting at address \hex{00002658} contains a string whose value can be expressed as either: % \verb@76 61 6c 3d 00@ or \verb@"val="@. \verb@76 61 6c 3d 00@ or \verb@"val="@ %\begin{itemize} %\item \verb@76 61 6c 3d 00@ %\item \verb@"val="@ %\end{itemize} \index{ASCII} \index{ASCIIZ} When the double-quoted text form is used, the GNU assembler used in this text differentiates between {\em ascii} and {\em asciiz} strings such that an {\em ascii} string is {\bf not} null terminated and an {\em asciiz} string {\bf is} null terminated. The value of providing a method to create a string that is not null terminated is that a program may define a large string by concatenating a number of {\em ascii} strings together and following the last with a byte of zero to null-terminate it. It is a common mistake to create a string with a missing null terminator. The result of printing such a string is that the string will be printed as well as whatever random data bytes in memory follow it until a byte whose value is zero is encountered by chance. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{Context is Important!} Data values can be interpreted differently depending on the context in which they are used. Assuming what a set of bytes is used for based on their contents can be very misleading! For example, there is a 0x76 at address 0x00002658. This is a `v' is you use it as an ASCII (see~\autoref{chapter:ascii}) character, a $118_{10}$ if it is an integer value and TRUE if it is a conditional. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{Alignment} \enote{Include the obligatory diagram showing the overlapping data types when they are all aligned.}% With respect to memory and storage, {\em \gls{alignment}} refers to the {\em location} of a data element when the address that it is stored is a precise multiple of a power-of-2. The primary alignments of concern are typically 2 (a halfword), 4 (a fullword), 8 (a double word) and 16 (a quad-word) bytes. For example, any data element that is aligned to 2-byte boundary must have an (hex) address that ends in any of: 0, 2, 4, 6, 8, A, C or E. Any 4-byte aligned element must be located at an address ending in 0, 4, 8 or C. An 8-byte aligned element at an address ending with 0 or 8, and 16-byte aligned elements must be located at addresses ending in zero. Such alignments are important when exchanging data between the CPU and memory because the hardware implementations are optimized to transfer aligned data. Therefore, aligning data used by any program will reap the benefit of running faster.% \footnote{Alignment of data, while important for efficient performance, is not mandatory for RISC-V systems.\cite[p.~19]{rvismv1v22:2017}} An element of data is considered to be {\em aligned to its natural size} when its address is an exact multiple of the number of bytes used to represent the data. Note that the ISA we are concerned with {\em only} operates on elements that have sizes that are powers of two. For example, a 32-bit integer consumes one full word. If the four bytes are stored in main memory at an address than is a multiple of 4 then the integer is considered to naturally aligned. The same would apply to 16-bit, 64-bit, 128-bit and other such values as they fit into 2, 8 and 16 byte elements respectively. Some CPUs can deliver four (or more) bytes at the same time while others might only be capable of delivering one or two bytes at a time. Such differences in hardware typically impact the cost and performance of a system.% \footnote{The design and implementation choices that determine how any given system operates are part of what is called a system's {\em organization} and is beyond the scope of this text. See~\cite{codriscv:2017} for more information on computer organization.} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{Instruction Alignment} The RISC-V ISA requires that all instructions be aligned to their natural boundaries. Every possible instruction that an RV32I CPU can execute contains exactly 32 bits. Therefore they are always stored on a full word boundary. Any {\em unaligned} instruction is {\em illegal}.% \footnote{This rule is relaxed by the C extension to allow an instruction to start at any even address.\cite[p.~5]{rvismv1v22:2017}} An attempt to fetch an instruction from an unaligned address will result in an error referred to as an alignment {\em \gls{exception}}. This and other exceptions cause the CPU to stop executing the current instruction and start executing a different set of instructions that are prepared to handle the problem. Often an exception is handled by completely stopping the program in a way that is commonly referred to as a system or application {\em crash}. ================================================ FILE: book/binary/rvddt_memdump.out ================================================ ddt> d 0x00002600 00002600: 93 05 00 00 13 06 00 00 93 06 00 00 13 07 00 00 *................* 00002610: 93 07 00 00 93 08 d0 05 73 00 00 00 63 54 05 02 *........s...cT..* 00002620: 13 01 01 ff 23 24 81 00 13 04 05 00 23 26 11 00 *....#$......#&..* 00002630: 33 04 80 40 97 00 00 00 e7 80 40 01 23 20 85 00 *3..@......@.# ..* 00002640: 6f 00 00 00 6f 00 00 00 b7 87 00 00 03 a5 07 43 *o...o..........C* 00002650: 67 80 00 00 00 00 00 00 76 61 6c 3d 00 00 00 00 *g.......val=....* 00002660: 00 00 00 00 80 84 2e 41 1f 85 45 41 80 40 9a 44 *.......A..EA.@.D* 00002670: 4f 11 f3 c3 6e 8a 67 41 20 1b 00 00 20 1b 00 00 *O...n.gA ... ...* 00002680: 44 1b 00 00 14 1b 00 00 14 1b 00 00 04 1c 00 00 *D...............* 00002690: 44 1b 00 00 14 1b 00 00 04 1c 00 00 14 1b 00 00 *D...............* 000026a0: 44 1b 00 00 10 1b 00 00 10 1b 00 00 10 1b 00 00 *D...............* 000026b0: 04 1c 00 00 54 1f 00 00 54 1f 00 00 d4 1f 00 00 *....T...T.......* 000026c0: 4c 1f 00 00 4c 1f 00 00 34 20 00 00 d4 1f 00 00 *L...L...4 ......* 000026d0: 4c 1f 00 00 34 20 00 00 4c 1f 00 00 d4 1f 00 00 *L...4 ..L.......* 000026e0: 48 1f 00 00 48 1f 00 00 48 1f 00 00 34 20 00 00 *H...H...H...4 ..* 000026f0: 00 01 02 02 03 03 03 03 04 04 04 04 04 04 04 04 *................* ================================================ FILE: book/colors.tex ================================================ % These are color styles used in the figures in this book. \definecolor{c_lightblue}{HTML}{B0E0FF} \definecolor{c_lightred}{HTML}{FFE0E0} \definecolor{c_lightyellow}{HTML}{FFE060} \definecolor{c_lightgreen}{HTML}{C0FFC0} ================================================ FILE: book/copyright/chapter.tex ================================================ \thispagestyle{plain} Copyright \copyright\ 2018, 2019, 2020 John Winans This document is made available under a Creative Commons Attribution 4.0 International License. See \autoref{license} for more information. Download your own copy of this book from github here: \url{https://github.com/johnwinans/rvalp}. This document may contain inaccuracies or errors. The author provides no guarantee regarding the accuracy of this document's contents. If you discover that this document contains errors, please notify the author. \enote{Need to say something about trademarks for things mentioned in this text} ARM\rtm{} is a registered trademark of ARM Limited in the EU and other countries. IBM\rtm{} is a trademarks or registered trademark of International Business Machines Corporation in the United States, other countries, or both. Intel\rtm{} and Pentium\rtm{} are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. ================================================ FILE: book/elements/chapter.tex ================================================ \chapter{The Elements of a Assembly Language Program} \label{chapter:elements} \section{Assembly Language Statements} Introduce the assembly language grammar. \begin{itemize} \item Statement = 1 line of text containing an instruction or directive. \item Instruction = label, mnemonic, operands, comment. \item Directive = Used to control the operation of the assembler. \end{itemize} \section{Memory Layout} Is this a good place to introduce the text, data, bss, heap and stack regions? Or does that belong in a new section/chapter that discusses addressing modes? %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \section{A Sample Program Source Listing} A simple program that illustrates how this text presents program source code is seen in \listingRef{zero4regs.S}. This program will place a zero in each of the 4 registers named x28, x29, x30 and x31. \listing{zero4regs.S}{Setting four registers to zero.} This program listing illustrates a number of things: \begin{itemize} \item Listings are identified by the name of the file within which they are stored. This listing is from a file named: \verb@zero4regs.S@. \item The assembly language programs discussed in this text will be saved in files that end with: \verb@.S@ (Alternately you can use \verb@.sx@ on systems that don't understand the difference between upper and lowercase letters.\footnote{The author of this text prefers to avoid using such systems.}) \item A description of the listing's purpose appears under the name of the file. The description of \listingRef{zero4regs.S} is {\em Setting four registers to zero.} \item The lines of the listing are numbered on the left margin for easy reference. \item An assembly program consists of lines of plain text. \item The RISC-V ISA does not provide an operation that will simply set a register to a numeric value. To accomplish our goal this program will add zero to zero and place the sum in in each of the four registers. \item The lines that start with a dot `.' (on lines 1, 2 and 3) are called {\em assembler directives} as they tell the assembler itself how we want it to translate the following {\em assembly language instructions} into {\em machine language instructions.} \item Line 4 shows a {\em label} named {\em \_start}. The colon at the end is the indicator to the assembler that causes it to recognize the preceding characters as a label. \item Lines 5-8 are the four assembly language instructions that make up the program. Each instruction in this program consists of four {\em fields}. (Different instructions can have a different number of fields.) The fields on line 5 are: \begin{itemize} \item [addi] The instruction mnemonic. It indicates the operation that the CPU will perform. \item [x28] The {\em destination} register that will receive the sum when the {\em addi} instruction is finished. The names of the 32 registers are expressed as x0 -- x31. \item [x0] One of the addends of the sum operation. (The x0 register will always contain the value zero. It can never be changed.) \item [0] The second addend is the number zero. \item [\# set \ldots] Any text anywhere in a RISC-V assembly language program that starts with the pound-sign is ignored by the assembler. They are used to place a {\em comment} in the program to help the reader better understand the motive of the programmer. \end{itemize} \end{itemize} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \section{Running a Program With rvddt} \index{rvddt} To illustrate what a CPU does when it executes instructions this text will use the \gls{rvddt} simulator to display shows sequence of events and the binary values involved. This simulator supports the RV32I ISA and has a configurable amount of memory.% \footnote{The {\em rvddt} simulator was written to generate the listings for this text. It is similar to the fancier {\em spike} simulator. Given the simplicity of the RV32I ISA, rvddt is less than 1700 lines of C++ and was written in one (long) afternoon.} \listingRef{zero4regs.out} shows the operation of the four {\em addi} instructions from \listingRef{zero4regs.S} when it is executed in trace-mode. \listing{zero4regs.out}{Running a program with the rvddt simulator} \begin{itemize} \item [$\ell$ 1] This listing includes the command-line that shows how the simulator was executed to load a file containing the machine instructions (aka machine code) from the assembler. \item [$\ell$ 2] A message from the simulator indicating that it loaded the machine code into simulated memory at address 0. \item [$\ell$ 3] This line shows the prompt from the debugger and the command \verb@t4@ that the user entered to request that the simulator trace the execution of four instructions. \item [$\ell$ 4-8] Prior to executing the first instruction, the state of the CPU registers is displayed. \item [$\ell$ 4] The values in registers 0, 1, 2, 3, 4, 5, 6 and 7 are printed from left to right in \gls{bigendian}, \gls{hexadecimal} form. The double-space gap in the middle of the line is a reference to make it easier to visually navigate across the line without being forced to count the values from the far left when seeking the value of, say, x5. \item [$\ell$ 5-7] The values of registers 8--31 are printed. \item [$\ell$ 8] The {\em program counter} (\reg{pc}) register is printed. It contains the address of the instruction that the CPU will execute. After each instruction, the \reg{pc} will either advance four bytes ahead or be set to another value by a branch instruction as discussed above. \item [$\ell$ 9] A four-byte instruction is fetched from memory at the address in the \reg{pc} register, is decoded and printed. From left to right the fields shown on this line are: \begin{itemize} \item [00000000] The memory address from which the instruction was fetched. This address is displayed in \gls{bigendian}, \gls{hexadecimal} form. \item [00000e13] The machine code of the instruction displayed in \gls{bigendian}, \gls{hexadecimal} form. \item [addi] The mnemonic for the machine instruction. \item [x28] The \reg{rd} field of the addi instruction. \item [x0] The \reg{rs1} field of the addi instruction that holds one of the two addends of the operation. \item [0] The \reg{imm} field of the addi instruction that holds the second of the two addends of the operation. \item [\# \ldots] A simulator-generated comment that explains what the instruction is doing. For this instruction it indicates that \reg{x28} will have the value zero stored into it as a result of performing the addition: $0+0$. \end{itemize} \item [$\ell$ 10-14] These lines are printed as the prelude while tracing the second instruction. Lines 7 and 13 show that \reg{x28} has changed from \verb@f0f0f0f0@ to \verb@00000000@ as a result of executing the first instruction and lines 8 and 14 show that the \reg{pc} has advanced from zero (the location of the first instruction) to four, where the second instruction will be fetched. None of the rest of the registers have changed values. \item [$\ell$ 15] The second instruction decoded executed and described. This time register \reg{x29} will be assigned a value. \item [$\ell$ 16-27] The third and fourth instructions are traced. \item [$\ell$ 28] Tracing has completed. The simulator prints its prompt and the user enters the `r' command to see the register state after the fourth instruction has completed executing. \item [$\ell$ 29-33] Following the fourth instruction it can be observed that registers \reg{x28}, \reg{x29}, \reg{x30} and \reg{x31} have been set to zero and that the \reg{pc} has advanced from zero to four, then eight, then 12 (the hex value for 12 is c) and then to 16 (which, in hex, is 10). \item [$\ell$ 34] The simulator exit command `x' is entered by the user and the terminal displays the shell prompt. \end{itemize} ================================================ FILE: book/elements/zero4regs.S ================================================ .text # put this into the text section .align 2 # align to 2^2 .globl _start _start: addi x28, x0, 0 # set register x28 to zero addi x29, x0, 0 # set register x29 to zero addi x30, x0, 0 # set register x30 to zero addi x31, x0, 0 # set register x31 to zero ================================================ FILE: book/elements/zero4regs.out ================================================ [winans@w510 src]$ ./rvddt -f ../examples/load4regs.bin Loading '../examples/load4regs.bin' to 0x0 ddt> t4 x0: 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 x8: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 x16: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 x24: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 pc: 00000000 00000000: 00000e13 addi x28, x0, 0 # x28 = 0x00000000 = 0x00000000 + 0x00000000 x0: 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 x8: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 x16: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 x24: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0 pc: 00000004 00000004: 00000e93 addi x29, x0, 0 # x29 = 0x00000000 = 0x00000000 + 0x00000000 x0: 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 x8: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 x16: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 x24: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 00000000 00000000 f0f0f0f0 f0f0f0f0 pc: 00000008 00000008: 00000f13 addi x30, x0, 0 # x30 = 0x00000000 = 0x00000000 + 0x00000000 x0: 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 x8: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 x16: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 x24: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 00000000 00000000 00000000 f0f0f0f0 pc: 0000000c 0000000c: 00000f93 addi x31, x0, 0 # x31 = 0x00000000 = 0x00000000 + 0x00000000 ddt> r x0: 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 x8: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 x16: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 x24: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 00000000 00000000 00000000 00000000 pc: 00000010 ddt> x [winans@w510 src]$ ================================================ FILE: book/float/chapter.tex ================================================ \chapter{Floating Point Numbers} \label{chapter:floatingpoint} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \section{IEEE-754 Floating Point Number Representation} \label{chapter::floatingpoint} This section provides an overview of the IEEE-754 32-bit binary floating point format.\cite{ieee:754} \begin{itemize} \item Recall that the place values for integer binary numbers are: \begin{verbatim} ... 128 64 32 16 8 4 2 1 \end{verbatim} \item We can extend this to the right in binary similar to the way we do for decimal numbers: \begin{verbatim} ... 128 64 32 16 8 4 2 1 . 1/2 1/4 1/8 1/16 1/32 1/64 1/128 ... \end{verbatim} The `.' in a binary number is a binary point, not a decimal point. \item We use scientific notation as in $2.7 \times 10^{-47}$ to express either small fractions or large numbers when we are not concerned every last digit needed to represent the entire, exact, value of a number. \item The format of a number in scientific notation is $mantissa \times base^{exponent}$ \item In binary we have $mantissa \times 2^{exponent}$ \item IEEE-754 format requires binary numbers to be {\em normalized} to $1.significand \times 2^{exponent}$ where the {\em significand} is the portion of the {\em mantissa} that is to the right of the binary-point. \begin{itemize} \item The unnormalized binary value of $-2.625$ is $-10.101$ \item The normalized value of $-2.625$ is $-1.0101 \times 2^1$ \end{itemize} \item We need not store the `1.' part because {\em all} normalized floating point numbers will start that way. Thus we can save memory when storing normalized values by inserting a `1.' to the left of significand. \DrawBitBoxIEEEFloat{11000000001010000000000000000000} %{ %\small %\setlength{\unitlength}{.15in} %\begin{picture}(32,4)(0,0) % \put(0,1){\line(1,0){32}} % bottom line % \put(0,2){\line(1,0){32}} % top line % % \put(0,1){\line(0,1){2}} % left vertical % \put(0,2){\makebox(1,1){\tiny 31}} % left end bit number marker % % \put(32,1){\line(0,1){2}} % vertical right end % \put(31,2){\makebox(1,1){\tiny 0}} % right end bit number marker % % \put(0,0){\makebox(1,1){\small sign}} % \put(1,0){\makebox(8,1){\small exponent}} % \put(9,0){\makebox(23,1){\small significand}} % % \put(0,1){\makebox(1,1){1}} % sign % % \put(1,1){\line(0,1){2}} % seperator % \put(1,2){\makebox(1,1){\tiny 30}} % bit marker % % \put(1,1){\makebox(1,1){1}} % exponent % \put(2,1){\makebox(1,1){0}} % \put(3,1){\makebox(1,1){0}} % \put(4,1){\makebox(1,1){0}} % \put(5,1){\makebox(1,1){0}} % \put(6,1){\makebox(1,1){0}} % \put(7,1){\makebox(1,1){0}} % \put(8,1){\makebox(1,1){0}} % % \put(8,2){\makebox(1,1){\tiny 23}} % bit marker % \put(9,1){\line(0,1){2}} % seperator % \put(9,2){\makebox(1,1){\tiny 22}} % bit marker % % \put(9,1){\makebox(1,1){0}} % \put(10,1){\makebox(1,1){1}} % \put(11,1){\makebox(1,1){0}} % \put(12,1){\makebox(1,1){1}} % \put(13,1){\makebox(1,1){0}} % \put(14,1){\makebox(1,1){0}} % \put(15,1){\makebox(1,1){0}} % \put(16,1){\makebox(1,1){0}} % \put(17,1){\makebox(1,1){0}} % \put(18,1){\makebox(1,1){0}} % \put(19,1){\makebox(1,1){0}} % \put(20,1){\makebox(1,1){0}} % \put(21,1){\makebox(1,1){0}} % \put(22,1){\makebox(1,1){0}} % \put(23,1){\makebox(1,1){0}} % \put(24,1){\makebox(1,1){0}} % \put(25,1){\makebox(1,1){0}} % \put(26,1){\makebox(1,1){0}} % \put(27,1){\makebox(1,1){0}} % \put(28,1){\makebox(1,1){0}} % \put(29,1){\makebox(1,1){0}} % \put(30,1){\makebox(1,1){0}} % \put(31,1){\makebox(1,1){0}} %\end{picture} %} %\item $-((1 + \frac{1}{4} + \frac{1}{16}) \times 2^{128-127}) = -(1 \frac{5}{16} \times 2^{1}) = -(1.3125 \times 2^{1}) = -2.625$ \item $-((1 + \frac{1}{4} + \frac{1}{16}) \times 2^{128-127}) = -((1 + \frac{1}{4} + \frac{1}{16}) \times 2^1) = -(2 + \frac{1}{2} + \frac{1}{8}) = -(2 + .5 + .125) = -2.625$ \item IEEE-754 formats: \begin{tabular}{|l|l|l|} \hline & IEEE-754 32-bit & IEEE-754 64-bit \\ \hline sign & 1 bit & 1 bit \\ exponent & 8 bits (excess-127) & 11 bits (excess-1023) \\ mantissa & 23 bits & 52 bits \\ max exponent & 127 & 1023 \\ min exponent & -126 & -1022 \\ \hline \end{tabular} \item When the exponent is all ones, the significand is all zeros, and the sign is zero, the number represents positive infinity. \item When the exponent is all ones, the significand is all zeros, and the sign is one, the number represents negative infinity. \item Observe that the binary representation of a pair of IEEE-754 numbers (when one or both are positive) can be compared for magnitude by treating them as if they are two's complement signed integers. This is because an IEEE number is stored in {\em signed magnitude} format and therefore positive floating point values will grow upward and downward in the same fashion as for unsigned integers and that since negative floating point values will have its MSB set, they will `appear` to be less than a positive floating point value. When comparing two negative IEEE float values by treating them both as two's complement signed integers, the order will be reversed because IEEE float values with larger (that is, increasingly negative) magnitudes will appear to decrease in value when interpreted as signed integers. This works this way because excess notation is used in the format of the exponent and why the significand's sign bit is located on the left of the exponent.\footnote{I know this is true and was done on purpose because Bill Cody, chairman of IEEE committee P754 that designed the IEEE-754 standard, told me so personally circa 1991.} \item Note that zero is a special case number. Recall that a normalized number has an implied 1-bit to the left of the significand\ldots\ which means that there is no way to represent zero! Zero is represented by an exponent of all-zeros and a significand of all-zeros. This definition allows for a positive and a negative zero if we observe that the sign can be either 1 or 0. \item On the number-line, numbers between zero and the smallest fraction in either direction are in the {\em \gls{underflow}} areas. \enote{Need to add the standard lecture number-line diagram showing where the over/under-flow areas are and why.} \item On the number line, numbers greater than the mantissa of all-ones and the largest exponent allowed are in the {\em \gls{overflow}} areas. \item Note that numbers have a higher resolution on the number line when the exponent is smaller. \item The largest and smallest possible exponent values are reserved to represent things requiring special cases. For example, the infinities, values representing ``not a number'' (such as the result of dividing by zero), and for a way to represent values that are not normalized. For more information on special cases see \cite{ieee:754}. \end{itemize} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{Floating Point Number Accuracy} Due to the finite number of bits used to store the value of a floating point number, it is not possible to represent every one of the infinite values on the real number line. The following C programs illustrate this point. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsubsection{Powers Of Two} Just like the integer numbers, the powers of two that have bits to represent them can be represented perfectly\ldots\ as can their sums (provided that the significand requires no more than 23 bits.) \listing{powersoftwo.c}{Precise Powers of Two} \listing{powersoftwo.out}{Output from {\tt powersoftwo.c}} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsubsection{Clean Decimal Numbers} When dealing with decimal values, you will find that they don't map simply into binary floating point values. % (the same holds true for binary integer numbers). Note how the decimal numbers are not accurately represented as they get larger. The decimal number on line 10 of \listingRef{cleandecimal.out} can be perfectly represented in IEEE format. However, a problem arises in the 11Th loop iteration. It is due to the fact that the binary number can not be represented accurately in IEEE format. Its least significant bits were truncated in a best-effort attempt at rounding the value off in order to fit the value into the bits provided. This is an example of {\em low order truncation}. Once this happens, the value of \verb@x.f@ is no longer as precise as it could be given more bits in which to save its value. \listing{cleandecimal.c}{Print Clean Decimal Numbers} \listing{cleandecimal.out}{Output from {\tt cleandecimal.c}} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsubsection{Accumulation of Error} These rounding errors can be exaggerated when the number we multiply the \verb@x.f@ value by is, itself, something that can not be accurately represented in IEEE form.\footnote{Applications requiring accurate decimal values, such as financial accounting systems, can use a packed-decimal numeric format to avoid unexpected oddities caused by the use of binary numbers.} \enote{In a lecture one would show that one tenth is a repeating non-terminating binary number that gets truncated. This discussion should be reproduced here in text form.} For example, if we multiply our \verb@x.f@ value by $\frac{1}{10}$ each time, we can never be accurate and we start accumulating errors immediately. \listing{erroraccumulation.c}{Accumulation of Error} \listing{erroraccumulation.out}{Output from {\tt erroraccumulation.c}} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{Reducing Error Accumulation} In order to use floating point numbers in a program without causing excessive rounding problems an algorithm can be redesigned such that the accumulation is eliminated. This example is similar to the previous one, but this time we recalculate the desired value from a known-accurate integer value. Some rounding errors remain present, but they can not accumulate. \listing{errorcompensation.c}{Accumulation of Error} \listing{errorcompensation.out}{Output from {\tt erroraccumulation.c}} ================================================ FILE: book/float/cleandecimal.c ================================================ #include #include #include union floatbin { unsigned int i; float f; }; int main() { union floatbin x, y; int i; x.f = 10; while (x.f <= 10000000000000.0) { y.f = -x.f; printf("%25.10f = %08x %25.10f = %08x\n", x.f, x.i, y.f, y.i); x.f = x.f*10.0; } } ================================================ FILE: book/float/cleandecimal.out ================================================ 10.0000000000 = 41200000 -10.0000000000 = c1200000 100.0000000000 = 42c80000 -100.0000000000 = c2c80000 1000.0000000000 = 447a0000 -1000.0000000000 = c47a0000 10000.0000000000 = 461c4000 -10000.0000000000 = c61c4000 100000.0000000000 = 47c35000 -100000.0000000000 = c7c35000 1000000.0000000000 = 49742400 -1000000.0000000000 = c9742400 10000000.0000000000 = 4b189680 -10000000.0000000000 = cb189680 100000000.0000000000 = 4cbebc20 -100000000.0000000000 = ccbebc20 1000000000.0000000000 = 4e6e6b28 -1000000000.0000000000 = ce6e6b28 10000000000.0000000000 = 501502f9 -10000000000.0000000000 = d01502f9 99999997952.0000000000 = 51ba43b7 -99999997952.0000000000 = d1ba43b7 999999995904.0000000000 = 5368d4a5 -999999995904.0000000000 = d368d4a5 9999999827968.0000000000 = 551184e7 -9999999827968.0000000000 = d51184e7 ================================================ FILE: book/float/erroraccumulation.c ================================================ #include #include #include union floatbin { unsigned int i; float f; }; int main() { union floatbin x, y; int i; x.f = .1; while (x.f <= 2.0) { y.f = -x.f; printf("%25.10f = %08x %25.10f = %08x\n", x.f, x.i, y.f, y.i); x.f += .1; } } ================================================ FILE: book/float/erroraccumulation.out ================================================ 0.1000000015 = 3dcccccd -0.1000000015 = bdcccccd 0.2000000030 = 3e4ccccd -0.2000000030 = be4ccccd 0.3000000119 = 3e99999a -0.3000000119 = be99999a 0.4000000060 = 3ecccccd -0.4000000060 = becccccd 0.5000000000 = 3f000000 -0.5000000000 = bf000000 0.6000000238 = 3f19999a -0.6000000238 = bf19999a 0.7000000477 = 3f333334 -0.7000000477 = bf333334 0.8000000715 = 3f4cccce -0.8000000715 = bf4cccce 0.9000000954 = 3f666668 -0.9000000954 = bf666668 1.0000001192 = 3f800001 -1.0000001192 = bf800001 1.1000001431 = 3f8cccce -1.1000001431 = bf8cccce 1.2000001669 = 3f99999b -1.2000001669 = bf99999b 1.3000001907 = 3fa66668 -1.3000001907 = bfa66668 1.4000002146 = 3fb33335 -1.4000002146 = bfb33335 1.5000002384 = 3fc00002 -1.5000002384 = bfc00002 1.6000002623 = 3fcccccf -1.6000002623 = bfcccccf 1.7000002861 = 3fd9999c -1.7000002861 = bfd9999c 1.8000003099 = 3fe66669 -1.8000003099 = bfe66669 1.9000003338 = 3ff33336 -1.9000003338 = bff33336 ================================================ FILE: book/float/errorcompensation.c ================================================ #include #include #include union floatbin { unsigned int i; float f; }; int main() { union floatbin x, y; int i; i = 1; while (i <= 20) { x.f = i/10.0; y.f = -x.f; printf("%25.10f = %08x %25.10f = %08x\n", x.f, x.i, y.f, y.i); i++; } return(0); } ================================================ FILE: book/float/errorcompensation.out ================================================ 0.1000000015 = 3dcccccd -0.1000000015 = bdcccccd 0.2000000030 = 3e4ccccd -0.2000000030 = be4ccccd 0.3000000119 = 3e99999a -0.3000000119 = be99999a 0.4000000060 = 3ecccccd -0.4000000060 = becccccd 0.5000000000 = 3f000000 -0.5000000000 = bf000000 0.6000000238 = 3f19999a -0.6000000238 = bf19999a 0.6999999881 = 3f333333 -0.6999999881 = bf333333 0.8000000119 = 3f4ccccd -0.8000000119 = bf4ccccd 0.8999999762 = 3f666666 -0.8999999762 = bf666666 1.0000000000 = 3f800000 -1.0000000000 = bf800000 1.1000000238 = 3f8ccccd -1.1000000238 = bf8ccccd 1.2000000477 = 3f99999a -1.2000000477 = bf99999a 1.2999999523 = 3fa66666 -1.2999999523 = bfa66666 1.3999999762 = 3fb33333 -1.3999999762 = bfb33333 1.5000000000 = 3fc00000 -1.5000000000 = bfc00000 1.6000000238 = 3fcccccd -1.6000000238 = bfcccccd 1.7000000477 = 3fd9999a -1.7000000477 = bfd9999a 1.7999999523 = 3fe66666 -1.7999999523 = bfe66666 1.8999999762 = 3ff33333 -1.8999999762 = bff33333 2.0000000000 = 40000000 -2.0000000000 = c0000000 ================================================ FILE: book/float/powersoftwo.c ================================================ #include #include #include union floatbin { unsigned int i; float f; }; int main() { union floatbin x; union floatbin y; int i; x.f = 1.0; while (x.f > 1.0/1024.0) { y.f = -x.f; printf("%25.10f = %08x %25.10f = %08x\n", x.f, x.i, y.f, y.i); x.f = x.f/2.0; } } ================================================ FILE: book/float/powersoftwo.out ================================================ 1.0000000000 = 3f800000 -1.0000000000 = bf800000 0.5000000000 = 3f000000 -0.5000000000 = bf000000 0.2500000000 = 3e800000 -0.2500000000 = be800000 0.1250000000 = 3e000000 -0.1250000000 = be000000 0.0625000000 = 3d800000 -0.0625000000 = bd800000 0.0312500000 = 3d000000 -0.0312500000 = bd000000 0.0156250000 = 3c800000 -0.0156250000 = bc800000 0.0078125000 = 3c000000 -0.0078125000 = bc000000 0.0039062500 = 3b800000 -0.0039062500 = bb800000 0.0019531250 = 3b000000 -0.0019531250 = bb000000 ================================================ FILE: book/glossary.tex ================================================ \newglossaryentry{latex} { name=LaTeX, description={Is a mark up language specially suited for scientific documents} } \newglossaryentry{binary} { name=binary, description={Something that has two parts or states. In computing these two states are represented by the numbers one and zero or by the conditions true and false and can be stored in one \gls{bit}} } \newglossaryentry{hexadecimal} { name=hexadecimal, description={A base-16 numbering system whose digits are 0123456789abcdef. The hex digits (\gls{hit}s) are not case-sensitive} } \newglossaryentry{bit} { name=bit, description={One binary digit} } \newglossaryentry{hit} { name={hit}, description={One \gls{hexadecimal} digit} } \newglossaryentry{nybble} { name={nybble}, description={Half of a {\em \gls{byte}} is a {\em nybble} (sometimes spelled nibble.) Another word for {\em \gls{hit}}} } \newglossaryentry{byte} { name=byte, description={A \gls{binary} value represented by 8 \gls{bit}s} } \newglossaryentry{halfword} { name={halfword}, description={A \gls{binary} value represented by 16 \gls{bit}s} } \newglossaryentry{fullword} { name={fullword}, description={A \gls{binary} value represented by 32 \gls{bit}s} } \newglossaryentry{doubleword} { name={doubleword}, description={A \gls{binary} value represented by 64 \gls{bit}s} } \newglossaryentry{quadword} { name={quadword}, description={A \gls{binary} value represented by 128 \gls{bit}s} } \newglossaryentry{HighOrderBits} { name={high order bits}, description={Some number of \acrshort{msb}s} } \newglossaryentry{LowOrderBits} { name={low order bits}, description={Some number of \acrshort{lsb}s} } \newglossaryentry{xlen} { name=XLEN, description={The number of bits a RISC-V x integer \gls{register} (such as x0). For RV32 XLEN=32, RV64 XLEN=64 and so on} } \newglossaryentry{rv32} { name=RV32, description={Short for RISC-V 32. The number 32 refers to the \gls{xlen}} } \newglossaryentry{rv64} { name=RV64, description={Short for RISC-V 64. The number 64 refers to the \gls{xlen}} } \newglossaryentry{overflow} { name=overflow, description={The situation where the result of an addition or subtraction operation is approaching positive or negative infinity and exceeds the number of bits allotted to contain the result. This is typically caused by high-order truncation} } \newglossaryentry{underflow} { name=underflow, description={The situation where the result of an addition or subtraction operation is approaching zero and exceeds the number of bits allotted to contain the result. This is typically caused by low-order truncation} } \newglossaryentry{MachineLanguage} { name={machine language}, description={The instructions that are executed by a CPU that are expressed in the form of \gls{binary} values} } \newglossaryentry{register} { name={register}, description={A unit of storage inside a CPU with the capacity of \gls{xlen} \gls{bit}s} } \newglossaryentry{program} { name={program}, description={A ordered list of one or more instructions} } \newglossaryentry{address} { name={address}, description={A numeric value used to uniquely identify each \gls{byte} of main memory} } \newglossaryentry{alignment} { name={alignment}, description={Refers to a range of numeric values that begin at a multiple of some number. Primarily used when referring to a memory address. For example an alignment of two refers to one or more addresses starting at even address and continuing onto subsequent adjacent, increasing memory addresses} } \newglossaryentry{exception} { name={exception}, description={An error encountered by the CPU while executing an instruction that can not be completed} } \newglossaryentry{bigendian} { name={big-endian}, description={A number format where the most significant values are printed to the left of the lesser significant values. This is the method that everyone uses to write decimal numbers every day} } \newglossaryentry{littleendian} { name={little-endian}, description={A number format where the least significant values are printed to the left of the more significant values. This is the opposite ordering that everyone learns in grade school when learning how to count. For example, the \gls{bigendian} number written as ``1234'' would be written in little endian form as ``4321''} } \newglossaryentry{rvddt} { name={rvddt}, description={A RV32I simulator and debugging tool inspired by the simplicity of the Dynamic Debugging Tool (ddt) that was part of the CP/M operating system} } \newglossaryentry{mnemonic} { name={mnemonic}, description={A method used to remember something. In the case of assembly language, each machine instruction is given a name so the programmer need not memorize the binary values of each machine instruction} } \newglossaryentry{thread} { name={thread}, description={An stream of instructions. When plural, it is used to refer to the ability of a CPU to execute multiple instruction streams at the same time} } \newglossaryentry{ascii} { name={ASCII}, description={American Standard Code for Information Interchange. See \autoref{chapter:ascii}} } \newglossaryentry{place-value} { name={place value}, description={the numerical value that a digit has as a result of its {\em position} within a number. For example, the digit 2 in the decimal number 123 is in the ten's place and its place value is 20} } \newacronym{hart}{hart}{Hardware Thread} \newacronym{msb}{MSB}{Most Significant Bit} \newacronym{lsb}{LSB}{Least Significant Bit} \newacronym{isa}{ISA}{Instruction Set Architecture} \newacronym{cpu}{CPU}{Central Processing Unit} \newacronym{ram}{RAM}{Random Access Memory} \newacronym{rom}{ROM}{Read Only Memory} %\newacronym{ascii}{ASCII}{American Standard Code for Information Interchange} ================================================ FILE: book/insnformats.tex ================================================ \def\SignBoxCornerRadius{.75mm} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \newcommand\BeginTikzPicture{ %\begin{tikzpicture}[x=.4cm,y=.3cm] \begin{tikzpicture}[x=.35cm,y=.3cm] } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \newcommand\EndTikzPicture{ \end{tikzpicture} } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Print the characters within a string evenly spaced at integral node positions % % #1 The number of characters in the string % #2 The string to print \newcommand\DrawBitstring[2]{ \foreach \x in {1,...,#1}% \draw(\x,0) node{\substring{#2}{\x}{\x}};% % \draw(\x,.5) node[text width = 10, text height = 1]{\substring{#2}{\x}{\x}};% Improve vertical text alignment } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % #1 The total size % #2 The string to print % #3 The value to use when extending to left \newcommand\DrawLeftExtendedBitstring[3]{ \StrLen{#2}[\numchars] \pgfmathsetmacro\leftpadd{int(#1-\numchars)} \foreach \x in {1,...,\leftpadd} \draw(\x,0) node{#3}; \pgfmathsetmacro\leftpadd{int(\leftpadd+1)} \foreach \x in {\leftpadd,...,#1} \pgfmathsetmacro\ix{int(\x-\leftpadd+1)} \draw(\x,0) node{\substring{#2}{\ix}{\ix}}; } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % If the string is shorter than expected, extend with #5 to the right. % % #1 The total size % #2 Num chars to extend on the right % #3 The string to print % #4 The value to use when extending to left % #5 The value to use when extending to right \newcommand\DrawDoubleExtendedBitstring[5]{ \StrLen{#3}[\numchars] \pgfmathsetmacro\leftpadd{int(#1-#2-\numchars)} \ifthenelse{1 > \leftpadd} {} { \foreach \x in {1,...,\leftpadd} \draw(\x,0) node{#4}; } \pgfmathsetmacro\leftpadd{int(\leftpadd+1)} \pgfmathsetmacro\rightpadd{int(\leftpadd+\numchars)} \foreach \x in {\leftpadd,...,\rightpadd} \pgfmathsetmacro\ix{int(\x-\leftpadd+1)} \draw(\x,0) node{\substring{#3}{\ix}{\ix}}; %\pgfmathsetmacro\rightpadd{int(\rightpadd+1)} \ifthenelse{\rightpadd > #1} {} { \foreach \x in {\rightpadd,...,#1} \draw(\x,0) node{#5}; } } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Draw a box suitable to show the given number of bits in a % labeled box suitable for showing expanded binary numbers. % % #1 The number of characters to display \newcommand\DrawBitBox[1]{ \draw (.5,-.75) -- (#1+.5,-.75); % box bottom \draw (.5,.75) -- (#1+.5,.75); % box top \draw (.5,-.75) -- (.5, 1.5); % left end \draw (#1+.5,-.75) -- (#1+.5, 1.5); % right end \pgfmathsetmacro\result{int(#1-1)} % calc high bit \node at (1,1.2) {\tiny\result}; % high bit label \draw(#1,1.2) node{\tiny0}; % low bit label \pgfmathsetmacro\result{#1/2} \node at (\result,-1.2) {\tiny#1}; % size below the box \pgfmathsetmacro\result{#1/2} \draw[->] (\result+.6,-1.2) -- (#1+.5,-1.2); \draw[->] (\result-.6,-1.2) -- (.5,-1.2); } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \newcommand\DrawBitBoxUnsigned[1]{ \StrLen{#1}[\numchars] \DrawBitBox{\numchars} \DrawBitstring{\numchars}{#1} % show the bits } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \newcommand\DrawBitBoxUnsignedPicture[1]{ \BeginTikzPicture \DrawBitBoxUnsigned{#1} \EndTikzPicture } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \newcommand\DrawBitBoxSignedPicture[1]{ \BeginTikzPicture \DrawBitBoxUnsigned{#1} % draw a box around the sign bit \draw {[rounded corners=\SignBoxCornerRadius] (1.35, -.6) -- (1.35, .6) -- (.65, .6) -- (.65, -.6) -- cycle}; \EndTikzPicture } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % #1 The total (extended) size % #2 The value to use for left-side padding % #3 The string to extend \newcommand\DrawBitBoxLeftExtended[3]{ \StrLen{#3}[\numchars] \pgfmathsetmacro\fill{int(#1-\numchars)} \begin{scope}[shift={(\fill,3.5)}] \DrawBitBoxUnsigned{#3} % XXX IFF not zero-extending then draw a box around the sign bit \draw {[rounded corners=\SignBoxCornerRadius] (1.35, -.6) -- (1.35, .6) -- (.65, .6) -- (.65, -.6) -- cycle}; \end{scope} \DrawBitBox{#1} \DrawDoubleExtendedBitstring{#1}{0}{#3}{#2}{x} % XXX IFF not zero-extending then draw a box around the sign bit \draw {[rounded corners=\SignBoxCornerRadius] (\fill+1.35, -.6) -- (\fill+1.35, .6) -- (\fill+.65, .6) -- (\fill+.65, -.6) -- cycle}; % draw a box around the extended sign bits \draw (.65, -.6) -- (.65, .6) -- (\fill+.35, .6) -- (\fill+.35, -.6) -- cycle; } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \newcommand\DrawBitBoxSignExtendedPicture[2]{ \BeginTikzPicture \DrawBitBoxLeftExtended{#1}{\substring{#2}{1}{1}}{#2} \EndTikzPicture } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \newcommand\DrawBitBoxZeroExtendedPicture[2]{ \BeginTikzPicture \DrawBitBoxLeftExtended{#1}{0}{#2} \EndTikzPicture } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % #1 Total bit length % #2 The string to print % #3 Right-side padding length \newcommand\DrawBitBoxSignLeftZeroRightExtendedPicture[3]{ \BeginTikzPicture \StrLen{#2}[\numchars] \pgfmathsetmacro\fill{int(#1-\numchars-#3)} \begin{scope}[shift={(\fill,3.5)}] \DrawBitBoxUnsigned{#2} % draw a box around the sign bit %\draw (1.35, -.6) -- (1.35, .6) -- (.65, .6) -- (.65, -.6) -- cycle; \draw {[rounded corners=\SignBoxCornerRadius] (1.35, -.6) -- (1.35, .6) -- (.65, .6) -- (.65, -.6) -- cycle}; \end{scope} \DrawBitBox{#1} \DrawDoubleExtendedBitstring{#1}{#3}{#2}{\substring{#2}{1}{1}}{0} % Box the sign bit \draw {[rounded corners=\SignBoxCornerRadius] (\fill+1.35, -.6) -- (\fill+1.35, .6) -- (\fill+.65, .6) -- (\fill+.65, -.6) -- cycle}; \ifthenelse{\fill > 0} { % Box the left-extended sign bits \draw (.65, -.6) -- (.65, .6) -- (\fill+.35, .6) -- (\fill+.35, -.6) -- cycle; % \fill[blue!40!white] (.65, -.6) rectangle (\fill-.25, 1.2); } {} \ifthenelse{#3 > 0} { % Box the right-extended sign bits \pgfmathsetmacro\posn{int(\numchars+\fill)} \draw (\posn+.65, -.6) -- (\posn+.65, .6) -- (\posn+#3+.35, .6) -- (\posn+#3+.35, -.6) -- cycle; } {} \EndTikzPicture } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % % Draw hex markers % #1 The number of bits in the box \newcommand\DrawHexMarkers[1]{ \pgfmathsetmacro\num{int(#1-1)} \foreach \x in {4,8,...,\num} \draw [line width=.5mm] (\x+.5,-.75) -- (\x+.5, -.3); } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Print the characters within a string evenly spaced at integral node positions % % #1 The number of characters in the string % #2 The string of characters to plot % #3 Right-side label \newcommand\DrawInsnBitstring[3]{ \pgfmathsetmacro\num{int(#1-1)} \foreach \x in {1,2,...,#1} \draw(\x+.25,-.3) node[text width = 10, text height = 1]{\substring{#2}{\x}{\x}}; \draw(#1+1,0) node[right]{#3}; } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Draw a bit-separator line with labels at the given bit-offset (from the right) % % #1 Total box width % #2 The position that the separator will be drawn to the left. \newcommand\DrawInsnBoxSep[2]{ \draw (#1-#2-.5,-.75) -- (#1-#2-.5, 1.5); \node at (#1-#2,1.2) {\tiny#2}; \pgfmathsetmacro\result{int(#2+1)} \node at (#1-#2-1,1.2) {\tiny\result}; } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % #1 total characters/width % #2 MSB position % #3 LSB position % #4 the segment label \newcommand\DrawInsnBoxSeg[4]{ \pgfmathsetmacro\leftpos{int(#1-#2)} \pgfmathsetmacro\rightpos{int(#1-#3)} \draw (\leftpos-.5,-.75) -- (\rightpos+.5,-.75); % box bottom \draw (\leftpos-.5,1.75) -- (\rightpos+.5,1.75); % box top \draw (\leftpos-.5,-.75) -- (\leftpos-.5, 2.5); % left end \draw (\rightpos+.5,-.75) -- (\rightpos+.5, 2.5); % right end \node at (\leftpos,2.2) {\tiny#2}; \draw(\rightpos,2.2) node{\tiny#3}; \pgfmathsetmacro\posn{#1-#2+(#2-#3)/2} \pgfmathsetmacro\range{int(#2-#3+1)} \node at (\posn,1.2) {\small#4}; % the field label % \node at (\posn,-1.4) {\small\range}; % the field width \begin{scope}[shift={(0,-.7)}]\InsnBoxFieldWidthArrow{#2}{#3}\end{scope} % % arrows showing the span of the bits... meh % \draw[->] (\posn+.5,-1.4) -- (\rightpos+.2,-1.4); % \draw[->] (\posn-.5,-1.4) -- (\leftpos-.2,-1.4); } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \newcommand\InsnStatement[1]{ % \textbf{\large #1}\\ % \textbf{#1}\\ {\large #1} } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \newcommand\DrawInsnTypeB[1]{ \StrLen{#1}[\numchars] \begin{scope}[shift={(0,.75)}] \DrawInsnBitstring{\numchars}{#1}{\hyperref[insnformat:btype]{B-type}} \DrawInsnBoxSeg{\numchars}{31}{25}{imm[12\textbar10:5]} \DrawInsnBoxSeg{\numchars}{24}{20}{rs2} \DrawInsnBoxSeg{\numchars}{19}{15}{rs1} \DrawInsnBoxSeg{\numchars}{14}{12}{funct3} \DrawInsnBoxSeg{\numchars}{11}{7}{imm[4:1\textbar11]} \DrawInsnBoxSeg{\numchars}{6}{0}{opcode} % add some hint bits in for imm fields \draw {[rounded corners=\SignBoxCornerRadius] (1.35, -.6) -- (1.35, .6) -- (.65, .6) -- (.65, -.6) -- cycle}; % sign bit \draw (32-7-.5, -.75) -- (32-7-.5, .1); % imm[11] \draw (32-30-.5, -.75) -- (32-30.5, .1); % imm[12] \end{scope} \DrawHexMarkersRel{\numchars} } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % #1 the binary encoding \newcommand\DrawInsnTypeBTikz[1]{ \BeginTikzPicture \DrawInsnTypeB{#1} \EndTikzPicture } \newcommand\DrawInsnTypeBPicture[2]{ \InsnStatement{#1}\\ \DrawInsnTypeBTikz{#2} } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % #1 the binary encoding \newcommand\DrawInsnTypeU[1]{ \StrLen{#1}[\numchars] \begin{scope}[shift={(0,.75)}] \DrawInsnBitstring{\numchars}{#1}{\hyperref[insnformat:utype]{U-type}} \DrawInsnBoxSeg{\numchars}{31}{12}{imm[31:12]} \DrawInsnBoxSeg{\numchars}{11}{7}{rd} \DrawInsnBoxSeg{\numchars}{6}{0}{opcode} % add some hint bits in for imm fields \draw {[rounded corners=\SignBoxCornerRadius] (1.35, -.6) -- (1.35, .6) -- (.65, .6) -- (.65, -.6) -- cycle}; % sign bit \end{scope} \DrawHexMarkersRel{\numchars} } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % #1 the binary encoding \newcommand\DrawInsnTypeUTikz[1]{ \BeginTikzPicture \DrawInsnTypeU{#1} \EndTikzPicture } \newcommand\DrawInsnTypeUPicture[2]{ \InsnStatement{#1}\\ \DrawInsnTypeUTikz{#2} } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % #1 the binary encoding \newcommand\DrawInsnTypeJ[1]{ \StrLen{#1}[\numchars] \begin{scope}[shift={(0,.75)}] \DrawInsnBitstring{\numchars}{#1}{\hyperref[insnformat:jtype]{J-type}} \DrawInsnBoxSeg{\numchars}{31}{12}{imm[20\textbar10:1\textbar11\textbar19:12]} \DrawInsnBoxSeg{\numchars}{11}{7}{rd} \DrawInsnBoxSeg{\numchars}{6}{0}{opcode} % \DrawHexMarkers{\numchars} \end{scope} % add some hint bits in for imm fields \draw {[rounded corners=\SignBoxCornerRadius] (1.35, .15) -- (1.35, 1.35) -- (.65, 1.35) -- (.65, .15) -- cycle}; % sign bit \draw (32-19-.5, 0) -- (32-19.5, .85); % imm[19:12] \draw (32-20-.5, 0) -- (32-20.5, .85); % imm[11] \draw (32-30-.5, 0) -- (32-30.5, .85); % imm[1:10] \DrawHexMarkersRel{\numchars} } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % #1 the binary encoding \newcommand\DrawInsnTypeJTikz[1]{ \BeginTikzPicture \DrawInsnTypeJ{#1} % \StrLen{#1}[\numchars] % \DrawInsnBitstring{\numchars}{#1}{\hyperref[insnformat:jtype]{J-type}} % \DrawInsnBoxSeg{\numchars}{31}{12}{imm[20\textbar10:1\textbar11\textbar19:12]} % \DrawInsnBoxSeg{\numchars}{11}{7}{rd} % \DrawInsnBoxSeg{\numchars}{6}{0}{opcode} % % % add some hint bits in for imm fields % \draw {[rounded corners=\SignBoxCornerRadius] (1.35, -.6) -- (1.35, .6) -- (.65, .6) -- (.65, -.6) -- cycle}; % sign bit % \draw (32-19-.5, -.75) -- (32-19.5, .1); % imm[19:12] % \draw (32-20-.5, -.75) -- (32-20.5, .1); % imm[11] % \DrawHexMarkers{\numchars} \EndTikzPicture } \newcommand\DrawInsnTypeJPicture[2]{ \InsnStatement{#1}\\ \DrawInsnTypeJTikz{#2} } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % #1 the binary encoding \newcommand\DrawInsnTypeI[1]{ \StrLen{#1}[\numchars] \begin{scope}[shift={(0,.75)}] \DrawInsnBitstring{\numchars}{#1}{\hyperref[insnformat:itype]{I-type}} \DrawInsnBoxSeg{\numchars}{31}{20}{imm[11:0]} \DrawInsnBoxSeg{\numchars}{19}{15}{rs1} \DrawInsnBoxSeg{\numchars}{14}{12}{funct3} \DrawInsnBoxSeg{\numchars}{11}{7}{rd} \DrawInsnBoxSeg{\numchars}{6}{0}{opcode} % add some hint bits in for imm fields \draw {[rounded corners=\SignBoxCornerRadius] (1.35, -.6) -- (1.35, .6) -- (.65, .6) -- (.65, -.6) -- cycle}; % sign bit \end{scope} \DrawHexMarkersRel{\numchars} } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % #1 the binary encoding \newcommand\DrawInsnTypeITikz[1]{ \BeginTikzPicture \DrawInsnTypeI{#1} % \DrawHexMarkers{\numchars} \EndTikzPicture } \newcommand\DrawInsnTypeIPicture[2]{ \InsnStatement{#1}\\ \DrawInsnTypeITikz{#2} } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % #1 the binary encoding \newcommand\DrawInsnTypeS[1]{ \StrLen{#1}[\numchars] \begin{scope}[shift={(0,.75)}] \DrawInsnBitstring{\numchars}{#1}{\hyperref[insnformat:stype]{S-type}} \DrawInsnBoxSeg{\numchars}{31}{25}{imm[11:5]} \DrawInsnBoxSeg{\numchars}{24}{20}{rs2} \DrawInsnBoxSeg{\numchars}{19}{15}{rs1} \DrawInsnBoxSeg{\numchars}{14}{12}{funct3} \DrawInsnBoxSeg{\numchars}{11}{7}{imm[4:0]} \DrawInsnBoxSeg{\numchars}{6}{0}{opcode} % add some hint bits in for imm fields \draw {[rounded corners=\SignBoxCornerRadius] (1.35, -.6) -- (1.35, .6) -- (.65, .6) -- (.65, -.6) -- cycle}; % sign bit \end{scope} \DrawHexMarkersRel{\numchars} } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % #1 the binary encoding \newcommand\DrawInsnTypeSTikz[1]{ \BeginTikzPicture \DrawInsnTypeS{#1} \EndTikzPicture } \newcommand\DrawInsnTypeSPicture[2]{ \InsnStatement{#1}\\ \DrawInsnTypeSTikz{#2} } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % #1 the binary encoding \newcommand\DrawInsnTypeIShiftTikz[1]{ \BeginTikzPicture \StrLen{#1}[\numchars] \DrawInsnBitstring{\numchars}{#1}{\hyperref[insnformat:rtype]{I-type}} \DrawInsnBoxSeg{\numchars}{31}{25}{funct7} \DrawInsnBoxSeg{\numchars}{24}{20}{shamt} \DrawInsnBoxSeg{\numchars}{19}{15}{rs1} \DrawInsnBoxSeg{\numchars}{14}{12}{funct3} \DrawInsnBoxSeg{\numchars}{11}{7}{rd} \DrawInsnBoxSeg{\numchars}{6}{0}{opcode} \DrawHexMarkers{\numchars} \EndTikzPicture } \newcommand\DrawInsnTypeRShiftPicture[2]{ \InsnStatement{#1}\\ \DrawInsnTypeIShiftTikz{#2} } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % #1 the binary encoding \newcommand\DrawInsnTypeR[1]{ \StrLen{#1}[\numchars] \DrawInsnBitstring{\numchars}{#1}{\hyperref[insnformat:rtype]{R-type}} \DrawInsnBoxSeg{\numchars}{31}{25}{funct7} \DrawInsnBoxSeg{\numchars}{24}{20}{rs2} \DrawInsnBoxSeg{\numchars}{19}{15}{rs1} \DrawInsnBoxSeg{\numchars}{14}{12}{funct3} \DrawInsnBoxSeg{\numchars}{11}{7}{rd} \DrawInsnBoxSeg{\numchars}{6}{0}{opcode} \DrawHexMarkers{\numchars} } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % #1 the binary encoding \newcommand\DrawInsnTypeRTikz[1]{ \BeginTikzPicture \DrawInsnTypeR{#1} \EndTikzPicture } \newcommand\DrawInsnTypeRPicture[2]{ \InsnStatement{#1}\\ \DrawInsnTypeRTikz{#2} } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % #1 the binary encoding \newcommand\DrawInsnTypeFTikz[1]{ \BeginTikzPicture \StrLen{#1}[\numchars] \DrawInsnBitstring{\numchars}{#1}{FENCE} \DrawInsnBoxSeg{\numchars}{31}{28}{} \DrawInsnBoxSeg{\numchars}{27}{24}{pred} \DrawInsnBoxSeg{\numchars}{23}{20}{succ} \DrawInsnBoxSeg{\numchars}{19}{15}{} \DrawInsnBoxSeg{\numchars}{14}{12}{funct3} \DrawInsnBoxSeg{\numchars}{11}{7}{} \DrawInsnBoxSeg{\numchars}{6}{0}{opcode} \DrawHexMarkers{\numchars} \EndTikzPicture } \newcommand\DrawInsnTypeFPicture[2]{ \InsnStatement{#1}\\ \DrawInsnTypeFTikz{#2} } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % #1 the binary encoding \newcommand\DrawInsnTypeETikz[1]{ \BeginTikzPicture \StrLen{#1}[\numchars] \DrawInsnBitstring{\numchars}{#1}{\hyperref[insnformat:itype]{I-type}} \DrawInsnBoxSeg{\numchars}{31}{20}{} \DrawInsnBoxSeg{\numchars}{19}{15}{} \DrawInsnBoxSeg{\numchars}{14}{12}{funct3} \DrawInsnBoxSeg{\numchars}{11}{7}{} \DrawInsnBoxSeg{\numchars}{6}{0}{opcode} \DrawHexMarkers{\numchars} \EndTikzPicture } \newcommand\DrawInsnTypeEPicture[2]{ \InsnStatement{#1}\\ \DrawInsnTypeETikz{#2} } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % #1 the binary encoding \newcommand\DrawInsnTypeCSTikz[1]{ \BeginTikzPicture \StrLen{#1}[\numchars] \DrawInsnBitstring{\numchars}{#1}{\hyperref[insnformat:itype]{I-type}} \DrawInsnBoxSeg{\numchars}{31}{20}{csr} \DrawInsnBoxSeg{\numchars}{19}{15}{rs1} \DrawInsnBoxSeg{\numchars}{14}{12}{funct3} \DrawInsnBoxSeg{\numchars}{11}{7}{rd} \DrawInsnBoxSeg{\numchars}{6}{0}{opcode} \DrawHexMarkers{\numchars} \EndTikzPicture } \newcommand\DrawInsnTypeCSPicture[2]{ \InsnStatement{#1}\\ \DrawInsnTypeCSTikz{#2} } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % #1 the binary encoding \newcommand\DrawInsnTypeCSITikz[1]{ \BeginTikzPicture \StrLen{#1}[\numchars] \DrawInsnBitstring{\numchars}{#1}{\hyperref[insnformat:itype]{I-type}} \DrawInsnBoxSeg{\numchars}{31}{20}{csr} \DrawInsnBoxSeg{\numchars}{19}{15}{zimm} \DrawInsnBoxSeg{\numchars}{14}{12}{funct3} \DrawInsnBoxSeg{\numchars}{11}{7}{rd} \DrawInsnBoxSeg{\numchars}{6}{0}{opcode} \DrawHexMarkers{\numchars} \EndTikzPicture } \newcommand\DrawInsnTypeCSIPicture[2]{ \InsnStatement{#1}\\ \DrawInsnTypeCSITikz{#2} } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \newcommand\xTInsnStatement[4]{% \parbox{3.5cm}{{\sffamily\large\bfseries #2}\\ \tt#3}\hspace{5mm}\parbox{5cm}{\bfseries#1}\parbox{12cm}{#4}% } \newcommand\TInsnStatement[4]{% \begin{tabular}{lll} \parbox[t]{3.5cm}{{\sffamily\large\bfseries #2}\\ \tt#3} & \parbox[t]{5cm}{\bfseries #1} & \parbox[t]{12cm}{#4}\\ \end{tabular} } \newcommand\TDrawInsnTypeUPicture[5]{% \TInsnStatement{#1}{#2}{#3}{#4}\\ \DrawInsnTypeUTikz{#5}% } \newcommand\TDrawInsnTypeJPicture[5]{% \TInsnStatement{#1}{#2}{#3}{#4}\\ \DrawInsnTypeJTikz{#5}% } \newcommand\TDrawInsnTypeBPicture[5]{% \TInsnStatement{#1}{#2}{#3}{#4}\\ \DrawInsnTypeBTikz{#5}% } \newcommand\TDrawInsnTypeIPicture[5]{% \TInsnStatement{#1}{#2}{#3}{#4}\\ \DrawInsnTypeITikz{#5}% } \newcommand\TDrawInsnTypeSPicture[5]{% \TInsnStatement{#1}{#2}{#3}{#4}\\ \DrawInsnTypeSTikz{#5}% } \newcommand\TDrawInsnTypeRPicture[5]{% \TInsnStatement{#1}{#2}{#3}{#4}\\ \DrawInsnTypeRTikz{#5}% } \newcommand\TDrawInsnTypeRShiftPicture[5]{ \TInsnStatement{#1}{#2}{#3}{#4}\\ \DrawInsnTypeIShiftTikz{#5} } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Draw hex markers with a baseline at zero % #1 The number of bits in the box \newcommand\TheHexMark[1]{ \draw [line width=.5mm] (#1+.5,0) -- (#1+.5, .4); } \newcommand\DrawHexMarkersRel[1]{ \pgfmathsetmacro\num{int(#1-1)} \foreach \x in {4,8,...,\num} \draw [line width=.5mm] (\x+.5,0) -- (\x+.5, .4); } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Draw an instruction box with a baseline at zero % #1 MSB position % #2 LSB position % #3 the segment label \newcommand\DrawInsnBoxRelTop[3]{ \pgfmathsetmacro\leftpos{int(32-#1)} \pgfmathsetmacro\rightpos{int(32-#2)} \draw (\leftpos-.5,1.5) -- (\rightpos+.5,1.5); % box top \draw (\leftpos-.5,0) -- (\leftpos-.5, 1.5); % left end \draw (\rightpos+.5,0) -- (\rightpos+.5, 1.5); % right end \pgfmathsetmacro\posn{32-#1+(#1-#2)/2} \node at (\posn,.75) {\small#3}; % the field label } % Draw only the bottom line of an instruction box with a baseline at zero % #1 MSB position % #2 LSB position \newcommand\DrawInsnBoxRelBottom[2]{ \pgfmathsetmacro\leftpos{int(32-#1)} \pgfmathsetmacro\rightpos{int(32-#2)} \draw (\leftpos-.5,0) -- (\rightpos+.5,0); % box bottom } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Draw an instruction box with a baseline at zero % #1 MSB position % #2 LSB position % #3 the segment label \newcommand\DrawInsnBoxRel[3]{ \DrawInsnBoxRelTop{#1}{#2}{#3} \DrawInsnBoxRelBottom{#1}{#2} } %\newcommand\DrawInsnBoxRel[3]{ % \pgfmathsetmacro\leftpos{int(32-#1)} % \pgfmathsetmacro\rightpos{int(32-#2)} % % \draw (\leftpos-.5,0) -- (\rightpos+.5,0); % box bottom % \draw (\leftpos-.5,1.5) -- (\rightpos+.5,1.5); % box top % \draw (\leftpos-.5,0) -- (\leftpos-.5, 1.5); % left end % \draw (\rightpos+.5,0) -- (\rightpos+.5, 1.5); % right end % % \pgfmathsetmacro\posn{32-#1+(#1-#2)/2} % \node at (\posn,.75) {\small#3}; % the field label %} % #1 MSB position % #2 LSB position \newcommand\DrawInsnBoxCastle[2]{ \pgfmathsetmacro\leftpos{int(32-#1)} \pgfmathsetmacro\rightpos{int(32-#2)} \draw (\leftpos-.5,0) -- (\leftpos-.5, .75); % left end \draw (\rightpos+.5,0) -- (\rightpos+.5, .75); % right end \node at (\leftpos,.5) {\tiny#1}; \ifthenelse{\equal{#1}{#2}} {} { \draw(\rightpos,.5) node{\tiny#2}; } } \newcommand\DrawInsnBoxCastleRtype{ \DrawInsnBoxCastle{31}{25} \DrawInsnBoxCastle{24}{20} \DrawInsnBoxCastle{19}{15} \DrawInsnBoxCastle{14}{12} \DrawInsnBoxCastle{11}{7} \DrawInsnBoxCastle{6}{0} } \newcommand\DrawInsnBoxCastleJtype{ \DrawInsnBoxCastle{31}{31} \DrawInsnBoxCastle{30}{21} \DrawInsnBoxCastle{20}{20} \DrawInsnBoxCastle{19}{12} \DrawInsnBoxCastle{11}{7} \DrawInsnBoxCastle{6}{0} } %% Draw a B-Type instruction box %% #1 label %% #2 ... %\newcommand\DrawInsnBoxBType[6]{ % \DrawInsnBoxRel{31}{25}{#1} % \DrawInsnBoxRel{24}{20}{#2} % \DrawInsnBoxRel{19}{15}{#3} % \DrawInsnBoxRel{14}{12}{#4} % \DrawInsnBoxRel{11}{7}{#5} % \DrawInsnBoxRel{6}{0}{#6} %} % % %\newcommand\DrawInsnBoxLabelsBtype{ % \DrawInsnBoxBType{imm[12\textbar10:5]}{rs2}{rs1}{funct3}{imm[4:1\textbar11]}{opcode} %% \DrawInsnBoxRel{31}{25}{imm[12\textbar10:5]} %% \DrawInsnBoxRel{24}{20}{rs2} %% \DrawInsnBoxRel{19}{15}{rs1} %% \DrawInsnBoxRel{14}{12}{funct3} %% \DrawInsnBoxRel{11}{7}{imm[4:1\textbar11]} %% \DrawInsnBoxRel{6}{0}{opcode} % \draw(33,.75) node[right]{\hyperref[insnformat:btype]{B-type}}; %} %\newcommand\DrawInsnBoxLabelsRtype{ % \DrawInsnBoxRel{31}{25}{funct7} % \DrawInsnBoxRel{24}{20}{rs2} % \DrawInsnBoxRel{19}{15}{rs1} % \DrawInsnBoxRel{14}{12}{funct3} % \DrawInsnBoxRel{11}{7}{rd} % \DrawInsnBoxRel{6}{0}{opcode} % \draw(33,.75) node[right]{\hyperref[insnformat:rtype]{R-type}}; %} %\newcommand\DrawInsnBoxLabelsItype{ % \DrawInsnBoxRel{31}{20}{imm[11:0]} % \DrawInsnBoxRel{19}{15}{rs1} % \DrawInsnBoxRel{14}{12}{funct3} % \DrawInsnBoxRel{11}{7}{rd} % \DrawInsnBoxRel{6}{0}{opcode} % \draw(33,.75) node[right]{\hyperref[insnformat:itype]{I-type}}; %} %\newcommand\DrawInsnBoxLabelsStype{ % \DrawInsnBoxRel{31}{25}{imm[11:5]} % \DrawInsnBoxRel{24}{20}{rs2} % \DrawInsnBoxRel{19}{15}{rs1} % \DrawInsnBoxRel{14}{12}{funct3} % \DrawInsnBoxRel{11}{7}{imm[4:0]} % \DrawInsnBoxRel{6}{0}{opcode} % \draw(33,.75) node[right]{\hyperref[insnformat:stype]{S-type}}; %} %\newcommand\DrawInsnBoxLabelsUtype{ % \DrawInsnBoxRel{31}{12}{imm[31:12]} % \DrawInsnBoxRel{11}{7}{rd} % \DrawInsnBoxRel{6}{0}{opcode} % \draw(33,.75) node[right]{\hyperref[insnformat:utype]{U-type}}; %} %\newcommand\DrawInsnBoxLabelsJtype{ % \DrawInsnBoxRel{31}{12}{imm[20\textbar10:1\textbar11\textbar19:12]} % \DrawInsnBoxRel{11}{7}{rd} % \DrawInsnBoxRel{6}{0}{opcode} % \draw(33,.75) node[right]{\hyperref[insnformat:jtype]{J-type}}; %} % %\newcommand\XXXDrawAllInsnTypes{ % \BeginTikzPicture % \DrawInsnBoxLabelsRtype % \begin{scope}[shift={(0,-1.5)}]\DrawInsnBoxLabelsItype\end{scope} % \begin{scope}[shift={(0,-3)}]\DrawInsnBoxLabelsStype\end{scope} % \begin{scope}[shift={(0,-4.5)}]\DrawInsnBoxLabelsBtype\end{scope} % \begin{scope}[shift={(0,-6)}]\DrawInsnBoxLabelsUtype\end{scope} % \begin{scope}[shift={(0,-7.5)}]\DrawInsnBoxLabelsJtype\DrawHexMarkersRel{32}\end{scope} % % \begin{scope}[shift={(0,1.5)}] % \DrawInsnBoxCastleRtype % \end{scope} % % \EndTikzPicture %} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Print the characters within a string evenly spaced at integral node positions % #1 The string of characters to plot \newcommand\DrawBitstringX[1]{ \StrLen{#1}[\numchars] \pgfmathsetmacro\num{int(\numchars-1)} \foreach \x in {1,2,...,\numchars} % \draw(\x,0) node{\substring{\strut #1}{\x}{\x}}; \draw(\x+.25,.5) node[text width = 10, text height = 1]{\substring{#1}{\x}{\x}}; } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % REFERENCE CARD DRAWINGS %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \newcommand\InsnSrcArgPosX{4} % relative to the position of the mnemonic %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % draw the instruction mnemonic and its args % #1 mnemonic % #2 args \newcommand\DrawInsnSrc[2]{ \draw node[right]{\tt #1}; \draw(\InsnSrcArgPosX,0) node[right]{\tt #2}; } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Draw a I-type instruction box with the given labels \newcommand\DrawInsnOpIBox[5]{ \DrawInsnBoxRel{31}{20}{#1} \DrawInsnBoxRel{19}{15}{#2} \DrawInsnBoxRel{14}{12}{} \DrawInsnBoxRel{11}{7}{#4} \DrawInsnBoxRel{6}{0}{} \begin{scope}[shift={(31-6,0)}]\DrawBitstringX{#3}\end{scope} \begin{scope}[shift={(31-14,0)}]\DrawBitstringX{#5}\end{scope} } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Draw a I-type instruction box with a 32-bit binary value \newcommand\DrawInsnOpIBinBox[1]{ \DrawInsnBoxRel{31}{20}{} \DrawInsnBoxRel{19}{15}{} \DrawInsnBoxRel{14}{12}{} \DrawInsnBoxRel{11}{7}{} \DrawInsnBoxRel{6}{0}{} \begin{scope}[shift={(31-31,0)}]\DrawBitstringX{#1}\end{scope} } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Draw a I-type w/funct7 instruction box with the given labels \newcommand\DrawInsnOpIFunctBox[6]{ \DrawInsnBoxRel{31}{25}{} \DrawInsnBoxRel{24}{20}{#2} \DrawInsnBoxRel{19}{15}{#3} \DrawInsnBoxRel{14}{12}{} \DrawInsnBoxRel{11}{7}{#5} \DrawInsnBoxRel{6}{0}{} \begin{scope}[shift={(31-6,0)}]\DrawBitstringX{#1}\end{scope} \begin{scope}[shift={(31-14,0)}]\DrawBitstringX{#4}\end{scope} \begin{scope}[shift={(31-31,0)}]\DrawBitstringX{#6}\end{scope} } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Draw a I-type instruction box with the given labels \newcommand\DrawInsnOpBBox[6]{ \DrawInsnBoxRel{31}{25}{#1} \DrawInsnBoxRel{24}{20}{#2} \DrawInsnBoxRel{19}{15}{#3} \DrawInsnBoxRel{14}{12}{} \DrawInsnBoxRel{11}{7}{#5} \DrawInsnBoxRel{6}{0}{} \begin{scope}[shift={(31-6,0)}]\DrawBitstringX{#4}\end{scope} \begin{scope}[shift={(31-14,0)}]\DrawBitstringX{#6}\end{scope} } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Draw a S-type instruction box with the given labels \newcommand\DrawInsnOpSBox[6]{ \DrawInsnBoxRel{31}{25}{#1} \DrawInsnBoxRel{24}{20}{#2} \DrawInsnBoxRel{19}{15}{#3} \DrawInsnBoxRel{14}{12}{} \DrawInsnBoxRel{11}{7}{#5} \DrawInsnBoxRel{6}{0}{} \begin{scope}[shift={(31-6,0)}]\DrawBitstringX{#6}\end{scope} \begin{scope}[shift={(31-14,0)}]\DrawBitstringX{#4}\end{scope} } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Draw a R-type instruction box with the given labels \newcommand\DrawInsnOpRBox[6]{ \DrawInsnBoxRel{31}{25}{} \DrawInsnBoxRel{24}{20}{#2} \DrawInsnBoxRel{19}{15}{#3} \DrawInsnBoxRel{14}{12}{} \DrawInsnBoxRel{11}{7}{#5} \DrawInsnBoxRel{6}{0}{} \begin{scope}[shift={(31-6,0)}]\DrawBitstringX{#6}\end{scope} \begin{scope}[shift={(31-14,0)}]\DrawBitstringX{#4}\end{scope} \begin{scope}[shift={(31-31,0)}]\DrawBitstringX{#1}\end{scope} } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Draw a U-type instruction box with the given labels \newcommand\DrawInsnOpUBox[3]{ \DrawInsnBoxRel{31}{12}{#1} \DrawInsnBoxRel{11}{7}{#2} \DrawInsnBoxRel{6}{0}{} \begin{scope}[shift={(31-6,0)}]\DrawBitstringX{#3}\end{scope} } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Draw a J-type instruction box with the given labels \newcommand\DrawInsnOpJBox[3]{ \DrawInsnBoxRel{31}{12}{#1} \DrawInsnBoxRel{11}{7}{#2} \DrawInsnBoxRel{6}{0}{} \begin{scope}[shift={(31-6,0)}]\DrawBitstringX{#3}\end{scope} } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \newcommand\InsnBoxTypePosX{32.5} \newcommand\InsnBoxMnemonicPosX{36.5} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % #1 opcode % #2 func3 % #3 mnemonic % #4 args \newcommand\DrawInsnOpBType[4]{ \DrawInsnOpBBox{imm[12\textbar10:5]}{rs2}{rs1}{#1}{imm[4:1\textbar11]}{#2} \draw(\InsnBoxTypePosX,.75) node[right]{\hyperref[insnformat:btype]{B-type}}; \begin{scope}[shift={(\InsnBoxMnemonicPosX,.75)}]\DrawInsnSrc{#3}{#4}\end{scope} } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % #1 opcode % #2 func3 % #3 mnemonic % #4 args \newcommand\DrawInsnOpIType[4]{ \DrawInsnOpIBox{imm[11:0]}{rs1}{#1}{rd}{#2} \draw(\InsnBoxTypePosX,.75) node[right]{\hyperref[insnformat:itype]{I-type}}; \begin{scope}[shift={(\InsnBoxMnemonicPosX,.75)}]\DrawInsnSrc{#3}{#4}\end{scope} } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % #1 opcode % #2 func3 % #3 mnemonic % #4 args % #5 rs1/zimm \newcommand\DrawInsnOpITypeSystem[5]{ \DrawInsnOpIBox{csr[11:0]}{#5}{#1}{rd}{#2} \draw(\InsnBoxTypePosX,.75) node[right]{\hyperref[insnformat:itype]{I-type}}; \begin{scope}[shift={(\InsnBoxMnemonicPosX,.75)}]\DrawInsnSrc{#3}{#4}\end{scope} } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % #1 opcode % #2 func3 % #3 func7 % #4 mnemonic % #5 args \newcommand\DrawInsnOpITypeShift[5]{ \DrawInsnOpIFunctBox{#1}{shamt}{rs1}{#2}{rd}{#3} \draw(\InsnBoxTypePosX,.75) node[right]{\hyperref[insnformat:itype]{I-type}}; \begin{scope}[shift={(\InsnBoxMnemonicPosX,.75)}]\DrawInsnSrc{#4}{#5}\end{scope} } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % #1 opcode % #2 func3 % #3 mnemonic % #4 args \newcommand\DrawInsnOpSType[4]{ \DrawInsnOpSBox{imm[11:5]}{rs2}{rs1}{#2}{imm[4:0]}{#1} \draw(\InsnBoxTypePosX,.75) node[right]{\hyperref[insnformat:stype]{S-type}}; \begin{scope}[shift={(\InsnBoxMnemonicPosX,.75)}]\DrawInsnSrc{#3}{#4}\end{scope} } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % #1 opcode % #2 func3 % #3 func7 % #4 mnemonic % #5 args \newcommand\DrawInsnOpRType[5]{ \DrawInsnOpRBox{#3}{rs2}{rs1}{#2}{rd}{#1} \draw(\InsnBoxTypePosX,.75) node[right]{\hyperref[insnformat:rtype]{R-type}}; \begin{scope}[shift={(\InsnBoxMnemonicPosX,.75)}]\DrawInsnSrc{#4}{#5}\end{scope} } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % #1 opcode % #2 func3 % #3 mnemonic % #4 args %\newcommand\DrawInsnOpFenceType[4]{ % \DrawInsnBoxRel{31}{28}{} % \DrawInsnBoxRel{27}{24}{pred} % \DrawInsnBoxRel{23}{20}{succ} % \DrawInsnBoxRel{19}{15}{} % \DrawInsnBoxRel{14}{12}{} % \DrawInsnBoxRel{11}{7}{} % \DrawInsnBoxRel{6}{0}{} % \begin{scope}[shift={(\InsnBoxMnemonicPosX,.75)}]\DrawInsnSrc{#3}{#4}\end{scope} % % \begin{scope}[shift={(31-6,0)}]\DrawBitstringX{#1}\end{scope} % \begin{scope}[shift={(31-14,0)}]\DrawBitstringX{#2}\end{scope} % \begin{scope}[shift={(31-31,0)}]\DrawBitstringX{0000}\end{scope} % % \begin{scope}[shift={(31-19,0)}]\DrawBitstringX{00000}\end{scope} % \begin{scope}[shift={(31-11,0)}]\DrawBitstringX{00000}\end{scope} %} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % #1 opcode % #2 func12 % #3 mnemonic % #4 args \newcommand\DrawInsnOpSysType[3]{ \DrawInsnOpIBinBox{#20000000000000#1} \draw(\InsnBoxTypePosX,.75) node[right]{\hyperref[insnformat:itype]{I-type}}; \draw(\InsnBoxMnemonicPosX,.75) node[right]{\tt #3}; } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % #1 opcode % #2 mnemonic % #4 args \newcommand\DrawInsnOpUType[3]{ \DrawInsnOpUBox{imm[31:12]}{rd}{#1} \draw(\InsnBoxTypePosX,.75) node[right]{\hyperref[insnformat:utype]{U-type}}; \begin{scope}[shift={(\InsnBoxMnemonicPosX,.75)}]\DrawInsnSrc{#2}{#3}\end{scope} } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % #1 opcode % #2 mnemonic % #4 args \newcommand\DrawInsnOpJType[3]{ \DrawInsnOpJBox{imm[20\textbar10:1\textbar11\textbar19:12]}{rd}{#1} \draw(\InsnBoxTypePosX,.75) node[right]{\hyperref[insnformat:jtype]{J-type}}; \begin{scope}[shift={(\InsnBoxMnemonicPosX,.75)}]\DrawInsnSrc{#2}{#3}\end{scope} } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \newcommand\DrawAllInsnOpsU{ \begin{scope}[shift={(0,0)}]\DrawInsnOpUType{0110111}{\hyperref[insn:lui]{lui}}{rd,\hyperref[imm.u:decode]{imm}}\end{scope} \begin{scope}[shift={(0,-1.5)}]\DrawInsnOpUType{0010111}{\hyperref[insn:auipc]{auipc}}{rd,\hyperref[imm.u:decode]{imm}}\end{scope} % \begin{scope}[shift={(0,-1.5)}]\DrawHexMarkersRel{32}\end{scope} } \newcommand\DrawAllInsnOpsJAL{ \begin{scope}[shift={(0,0)}]\DrawInsnOpJType{1101111}{\hyperref[insn:jal]{jal}}{rd,\hyperref[pcrel.21]{pcrel\_21}}\end{scope} \begin{scope}[shift={(0,-1.5)}]\DrawInsnOpIType{1100111}{000}{\hyperref[insn:jalr]{jalr}}{rd,\hyperref[imm.i:decode]{imm}(rs1)}\end{scope} \begin{scope}[shift={(0,-1.5)}]\DrawHexMarkersRel{32}\end{scope} } \newcommand\DrawAllInsnOpsBranch{ \begin{scope}[shift={(0,0)}]\DrawInsnOpBType{1100011}{000}{\hyperref[insn:beq]{beq}}{rs1,rs2,\hyperref[pcrel.13]{pcrel\_13}}\end{scope} \begin{scope}[shift={(0,-1.5)}]\DrawInsnOpBType{1100011}{001}{\hyperref[insn:bne]{bne}}{rs1,rs2,\hyperref[pcrel.13]{pcrel\_13}}\end{scope} \begin{scope}[shift={(0,-3)}]\DrawInsnOpBType{1100011}{100}{\hyperref[insn:blt]{blt}}{rs1,rs2,\hyperref[pcrel.13]{pcrel\_13}}\end{scope} \begin{scope}[shift={(0,-4.5)}]\DrawInsnOpBType{1100011}{101}{\hyperref[insn:bge]{bge}}{rs1,rs2,\hyperref[pcrel.13]{pcrel\_13}}\end{scope} \begin{scope}[shift={(0,-6)}]\DrawInsnOpBType{1100011}{110}{\hyperref[insn:bltu]{bltu}}{rs1,rs2,\hyperref[pcrel.13]{pcrel\_13}}\end{scope} \begin{scope}[shift={(0,-7.5)}]\DrawInsnOpBType{1100011}{111}{\hyperref[insn:bgeu]{bgeu}}{rs1,rs2,\hyperref[pcrel.13]{pcrel\_13}}\end{scope} \begin{scope}[shift={(0,-7.5)}]\DrawHexMarkersRel{32}\end{scope} } \newcommand\DrawAllInsnOpsLoad{ \begin{scope}[shift={(0,0)}]\DrawInsnOpIType{0000011}{000}{\hyperref[insn:lb]{lb}}{rd,\hyperref[imm.i:decode]{imm}(rs1)}\end{scope} \begin{scope}[shift={(0,-1.5)}]\DrawInsnOpIType{0000011}{001}{\hyperref[insn:lh]{lh}}{rd,\hyperref[imm.i:decode]{imm}(rs1)}\end{scope} \begin{scope}[shift={(0,-3.0)}]\DrawInsnOpIType{0000011}{010}{\hyperref[insn:lw]{lw}}{rd,\hyperref[imm.i:decode]{imm}(rs1)}\end{scope} \begin{scope}[shift={(0,-4.5)}]\DrawInsnOpIType{0000011}{100}{\hyperref[insn:lbu]{lbu}}{rd,\hyperref[imm.i:decode]{imm}(rs1)}\end{scope} \begin{scope}[shift={(0,-6.0)}]\DrawInsnOpIType{0000011}{101}{\hyperref[insn:lhu]{lhu}}{rd,\hyperref[imm.i:decode]{imm}(rs1)}\end{scope} \begin{scope}[shift={(0,-6.0)}]\DrawHexMarkersRel{32}\end{scope} } \newcommand\DrawAllInsnOpsStore{ \begin{scope}[shift={(0,0)}]\DrawInsnOpSType{0100011}{000}{\hyperref[insn:sb]{sb}}{rs2,\hyperref[imm.s:decode]{imm}(rs1)}\end{scope} \begin{scope}[shift={(0,-1.5)}]\DrawInsnOpSType{0100011}{001}{\hyperref[insn:sh]{sh}}{rs2,\hyperref[imm.s:decode]{imm}(rs1)}\end{scope} \begin{scope}[shift={(0,-3.0)}]\DrawInsnOpSType{0100011}{010}{\hyperref[insn:sw]{sw}}{rs2,\hyperref[imm.s:decode]{imm}(rs1)}\end{scope} \begin{scope}[shift={(0,-3.0)}]\DrawHexMarkersRel{32}\end{scope} } \newcommand\DrawAllInsnOpsALUImm{ \begin{scope}[shift={(0,0)}]\DrawInsnOpIType{0010011}{000}{\hyperref[insn:addi]{addi}}{rd,rs1,\hyperref[imm.i:decode]{imm}}\end{scope} \begin{scope}[shift={(0,-1.5)}]\DrawInsnOpIType{0010011}{010}{\hyperref[insn:slti]{slti}}{rd,rs1,\hyperref[imm.i:decode]{imm}}\end{scope} \begin{scope}[shift={(0,-3.0)}]\DrawInsnOpIType{0010011}{011}{\hyperref[insn:sltiu]{sltiu}}{rd,rs1,\hyperref[imm.i:decode]{imm}}\end{scope} \begin{scope}[shift={(0,-4.5)}]\DrawInsnOpIType{0010011}{100}{\hyperref[insn:xori]{xori}}{rd,rs1,\hyperref[imm.i:decode]{imm}}\end{scope} \begin{scope}[shift={(0,-6.0)}]\DrawInsnOpIType{0010011}{110}{\hyperref[insn:ori]{ori}}{rd,rs1,\hyperref[imm.i:decode]{imm}}\end{scope} \begin{scope}[shift={(0,-7.5)}]\DrawInsnOpIType{0010011}{111}{\hyperref[insn:andi]{andi}}{rd,rs1,\hyperref[imm.i:decode]{imm}}\end{scope} \begin{scope}[shift={(0,-7.5)}]\DrawHexMarkersRel{32}\end{scope} } \newcommand\DrawAllInsnOpsShiftImm{ \begin{scope}[shift={(0,0)}]\DrawInsnOpITypeShift{0010011}{001}{0000000}{\hyperref[insn:slli]{slli}}{rd,rs1,\hyperref[shamt.i:decode]{shamt}}\end{scope} \begin{scope}[shift={(0,-1.5)}]\DrawInsnOpITypeShift{0010011}{101}{0000000}{\hyperref[insn:srli]{srli}}{rd,rs1,\hyperref[shamt.i:decode]{shamt}}\end{scope} \begin{scope}[shift={(0,-3.0)}]\DrawInsnOpITypeShift{0010011}{101}{0100000}{\hyperref[insn:srai]{srai}}{rd,rs1,\hyperref[shamt.i:decode]{shamt}}\end{scope} \begin{scope}[shift={(0,-3.0)}]\DrawHexMarkersRel{32}\end{scope} } \newcommand\DrawAllInsnOpsALUR{ \begin{scope}[shift={(0,0)}]\DrawInsnOpRType{0110011}{000}{0000000}{\hyperref[insn:add]{add}}{rd,rs1,rs2}\end{scope} \begin{scope}[shift={(0,-1.5)}]\DrawInsnOpRType{0110011}{000}{0100000}{\hyperref[insn:sub]{sub}}{rd,rs1,rs2}\end{scope} \begin{scope}[shift={(0,-3.0)}]\DrawInsnOpRType{0110011}{001}{0000000}{\hyperref[insn:sll]{sll}}{rd,rs1,rs2}\end{scope} \begin{scope}[shift={(0,-4.5)}]\DrawInsnOpRType{0110011}{010}{0000000}{\hyperref[insn:slt]{slt}}{rd,rs1,rs2}\end{scope} \begin{scope}[shift={(0,-6.0)}]\DrawInsnOpRType{0110011}{011}{0000000}{\hyperref[insn:sltu]{sltu}}{rd,rs1,rs2}\end{scope} \begin{scope}[shift={(0,-7.5)}]\DrawInsnOpRType{0110011}{100}{0000000}{\hyperref[insn:xor]{xor}}{rd,rs1,rs2}\end{scope} \begin{scope}[shift={(0,-9.0)}]\DrawInsnOpRType{0110011}{101}{0000000}{\hyperref[insn:srl]{srl}}{rd,rs1,rs2}\end{scope} \begin{scope}[shift={(0,-10.5)}]\DrawInsnOpRType{0110011}{101}{0100000}{\hyperref[insn:sra]{sra}}{rd,rs1,rs2}\end{scope} \begin{scope}[shift={(0,-12.0)}]\DrawInsnOpRType{0110011}{110}{0000000}{\hyperref[insn:or]{or}}{rd,rs1,rs2}\end{scope} \begin{scope}[shift={(0,-13.5)}]\DrawInsnOpRType{0110011}{111}{0000000}{\hyperref[insn:and]{and}}{rd,rs1,rs2}\end{scope} \begin{scope}[shift={(0,-13.5)}]\DrawHexMarkersRel{32}\end{scope} } \newcommand\DrawAllInsnOpsFence{ \begin{scope}[shift={(0,0)}]\DrawInsnOpFenceType{0001111}{000}{\hyperref[insn:fence]{fence}}{pred,succ}\end{scope} %\begin{scope}[shift={(0,0)}]\DrawHexMarkersRel{32}\end{scope} } \newcommand\DrawAllInsnOpsSim{ \begin{scope}[shift={(0,0)}]\DrawInsnOpSysType{1110011}{000000000000}{\hyperref[insn:ecall]{ecall}}\end{scope} \begin{scope}[shift={(0,-1.5)}]\DrawInsnOpSysType{1110011}{000000000001}{\hyperref[insn:ebreak]{ebreak}}\end{scope} \begin{scope}[shift={(0,-1.5)}]\DrawHexMarkersRel{32}\end{scope} } \newcommand\DrawAllInsnOpsSystem{ \begin{scope}[shift={(0,0)}]\DrawInsnOpITypeSystem{1110011}{001}{\hyperref[insn:csrrw]{csrrw}}{rd,\hyperref[csr.i:decode]{csr},rs1}{rs1}\end{scope} \begin{scope}[shift={(0,-1.5)}]\DrawInsnOpITypeSystem{1110011}{010}{\hyperref[insn:csrrs]{csrrs}}{rd,\hyperref[csr.i:decode]{csr},rs1}{rs1}\end{scope} \begin{scope}[shift={(0,-3.0)}]\DrawInsnOpITypeSystem{1110011}{011}{\hyperref[insn:csrrc]{csrrc}}{rd,\hyperref[csr.i:decode]{csr},rs1}{rs1}\end{scope} \begin{scope}[shift={(0,-4.5)}]\DrawInsnOpITypeSystem{1110011}{101}{\hyperref[insn:csrrwi]{csrrwi}}{rd,\hyperref[csr.i:decode]{csr},zimm}{zimm[4:0]}\end{scope} \begin{scope}[shift={(0,-6.0)}]\DrawInsnOpITypeSystem{1110011}{110}{\hyperref[insn:csrrsi]{csrrsi}}{rd,\hyperref[csr.i:decode]{csr},zimm}{zimm[4:0]}\end{scope} \begin{scope}[shift={(0,-7.5)}]\DrawInsnOpITypeSystem{1110011}{111}{\hyperref[insn:csrrci]{csrrci}}{rd,\hyperref[csr.i:decode]{csr},zimm}{zimm[4:0]}\end{scope} \begin{scope}[shift={(0,-7.5)}]\DrawHexMarkersRel{32}\end{scope} } \newcommand\DrawAllInsnOps{ \BeginTikzPicture \begin{scope}[shift={(0,1.5)}]\DrawInsnBoxCastleRtype\end{scope} \begin{scope}[shift={(0,0)}]\DrawAllInsnOpsU\end{scope} \begin{scope}[shift={(0,-3.0)}]\DrawAllInsnOpsJAL\end{scope} \begin{scope}[shift={(0,-6.2)}]\DrawAllInsnOpsBranch\end{scope} \begin{scope}[shift={(0,-15.4)}]\DrawAllInsnOpsLoad\end{scope} \begin{scope}[shift={(0,-23.1)}]\DrawAllInsnOpsStore\end{scope} \begin{scope}[shift={(0,-27.8)}]\DrawAllInsnOpsALUImm\end{scope} \begin{scope}[shift={(0,-37.0)}]\DrawAllInsnOpsShiftImm\end{scope} \begin{scope}[shift={(0,-41.7)}]\DrawAllInsnOpsALUR\end{scope} \begin{scope}[shift={(0,-57.4)}]\DrawAllInsnOpsSim\end{scope} \begin{scope}[shift={(0,-60.6)}]\DrawAllInsnOpsSystem\end{scope} \EndTikzPicture } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % GREEN CARD VERSION OF INSN DIAGRAMS \newcommand\GCPageWidth{85.8} %\newcommand\GCPageWidth{86} % box, insn, desc, rtl %\newcommand\GCInsnEncodingPosX{0} % the box, sans-castle %\newcommand\GCInsnTypePosX{32.6} % R,I,U,B,... %\newcommand\GCInsnMnemonicPosX{34} % the template instruction source %\newcommand\GCInsnDescriptionPosX{47} % the long-form description %\newcommand\GCInsnRTLPosX{64} % the detailed RTL description % insn, desc, rtl, box \newcommand\GCInsnMnemonicPosX{0} % the template instruction source \newcommand\GCInsnDescriptionPosX{13} % the long-form description \newcommand\GCInsnRTLPosX{29.7} % the detailed RTL description \newcommand\GCInsnTypePosX{52.5} % R,I,U,B,... \newcommand\GCInsnEncodingPosX{53} % the box, sans-castle % #1 opcode % #2 mnemonic % #3 args % #4 description % #5 RTL \newcommand\DrawGCInsnOpU[5]{ \begin{scope}[shift={(\GCInsnMnemonicPosX,.6)}]\DrawInsnSrc{#2}{#3}\end{scope} \draw(\GCInsnTypePosX,.75) node {U}; \draw(\GCInsnDescriptionPosX,.6) node[right]{#4}; \draw(\GCInsnRTLPosX,.6) node[right]{#5}; \begin{scope}[shift={(\GCInsnEncodingPosX,0)}]\DrawInsnOpUBox{imm[31:12]}{rd}{#1}\end{scope} } % #1 opcode % #2 mnemonic % #3 args % #4 description % #5 RTL \newcommand\DrawGCInsnOpJ[5]{ \begin{scope}[shift={(\GCInsnMnemonicPosX,.6)}]\DrawInsnSrc{#2}{#3}\end{scope} \draw(\GCInsnTypePosX,.75) node {J}; \draw(\GCInsnDescriptionPosX,.6) node[right]{#4}; \draw(\GCInsnRTLPosX,.6) node[right]{#5}; \begin{scope}[shift={(\GCInsnEncodingPosX,0)}]\DrawInsnOpJBox{imm[20\textbar10:1\textbar11\textbar19:12]}{rd}{#1}\end{scope} } % #1 opcode % #2 funct3 % #3 mnemonic % #4 args % #5 description % #6 RTL \newcommand\DrawGCInsnOpI[6]{ \begin{scope}[shift={(\GCInsnMnemonicPosX,.6)}]\DrawInsnSrc{#3}{#4}\end{scope} \draw(\GCInsnTypePosX,.75) node {I}; \draw(\GCInsnDescriptionPosX,.6) node[right]{#5}; \draw(\GCInsnRTLPosX,.6) node[right]{#6}; \begin{scope}[shift={(\GCInsnEncodingPosX,0)}]\DrawInsnOpIBox{imm[11:0]}{rs1}{#1}{rd}{#2}\end{scope} } % #1 opcode % #2 funct3 % #3 funct7 % #4 mnemonic % #5 args % #6 description % #7 RTL \newcommand\DrawGCInsnOpIShift[7]{ \begin{scope}[shift={(\GCInsnMnemonicPosX,.6)}]\DrawInsnSrc{#4}{#5}\end{scope} \draw(\GCInsnTypePosX,.75) node {I}; \draw(\GCInsnDescriptionPosX,.6) node[right]{#6}; \draw(\GCInsnRTLPosX,.6) node[right]{#7}; \begin{scope}[shift={(\GCInsnEncodingPosX,0)}]\DrawInsnOpIFunctBox{#1}{shamt}{rs1}{#2}{rd}{#3}\end{scope} } % #1 opcode % #2 funct3 % #3 mnemonic % #4 args % #5 csr % #6 description % #7 RTL \newcommand\DrawGCInsnOpICSR[7]{ \begin{scope}[shift={(\GCInsnMnemonicPosX,.6)}]\DrawInsnSrc{#3}{#4}\end{scope} \draw(\GCInsnTypePosX,.75) node {I}; \draw(\GCInsnDescriptionPosX,.6) node[right]{#6}; \draw(\GCInsnRTLPosX,.6) node[right]{#7}; \begin{scope}[shift={(\GCInsnEncodingPosX,0)}]\DrawInsnOpIBox{csr[11:0]}{#5}{#1}{rd}{#2}\end{scope} } % #1 opcode % #2 funct3 % #3 mnemonic % #4 args % #5 description % #6 RTL \newcommand\DrawGCInsnOpB[6]{ \begin{scope}[shift={(\GCInsnMnemonicPosX,.6)}]\DrawInsnSrc{#3}{#4}\end{scope} \draw(\GCInsnTypePosX,.75) node {B}; \draw(\GCInsnDescriptionPosX,.6) node[right]{#5}; \draw(\GCInsnRTLPosX,.6) node[right]{#6}; \begin{scope}[shift={(\GCInsnEncodingPosX,0)}]\DrawInsnOpBBox{imm[12\textbar10:5]}{rs2}{rs1}{#1}{imm[4:1\textbar11]}{#2}\end{scope} } % #1 opcode % #2 funct3 % #3 mnemonic % #4 args % #5 description % #6 RTL \newcommand\DrawGCInsnOpS[6]{ \begin{scope}[shift={(\GCInsnMnemonicPosX,.6)}]\DrawInsnSrc{#3}{#4}\end{scope} \draw(\GCInsnTypePosX,.75) node {S}; \draw(\GCInsnDescriptionPosX,.6) node[right]{#5}; \draw(\GCInsnRTLPosX,.6) node[right]{#6}; \begin{scope}[shift={(\GCInsnEncodingPosX,0)}]\DrawInsnOpBBox{imm[11:5]}{rs2}{rs1}{#1}{imm[4:0]}{#2}\end{scope} } % #1 opcode % #2 funct3 % #3 funct7 % #4 mnemonic % #5 args % #6 description % #7 RTL \newcommand\DrawGCInsnOpR[7]{ \begin{scope}[shift={(\GCInsnMnemonicPosX,.6)}]\DrawInsnSrc{#4}{#5}\end{scope} \draw(\GCInsnTypePosX,.75) node {R}; \draw(\GCInsnDescriptionPosX,.6) node[right]{#6}; \draw(\GCInsnRTLPosX,.6) node[right]{#7}; \begin{scope}[shift={(\GCInsnEncodingPosX,0)}]\DrawInsnOpRBox{#3}{rs2}{rs1}{#2}{rd}{#1}\end{scope} } % #1 opcode % #2 funct7 % #3 mnemonic % #4 description \newcommand\DrawGCInsnOpSys[4]{ \begin{scope}[shift={(\GCInsnMnemonicPosX,.6)}]\DrawInsnSrc{#3}{}\end{scope} \draw(\GCInsnTypePosX,.75) node {I}; \draw(\GCInsnDescriptionPosX,.6) node[right]{#4}; % \draw(\GCInsnRTLPosX,.6) node[right]{#4}; \begin{scope}[shift={(\GCInsnEncodingPosX,0)}]\DrawInsnOpIBinBox{#20000000000000#1}\end{scope} } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \newcommand\DrawGCAllInsnOpsU{ \begin{scope}[shift={(0,0)}]\DrawGCInsnOpU{0110111}{lui}{rd,imm}{Load Upper Immediate}{\tt rd $\leftarrow$ imm\_u, pc $\leftarrow$ pc+4}\end{scope} \begin{scope}[shift={(0,-1.5)}]\DrawGCInsnOpU{0010111}{auipc}{rd,imm}{Add Upper Immediate to PC}{\tt rd $\leftarrow$ pc + imm\_u, pc $\leftarrow$ pc+4}\end{scope} } \newcommand\DrawGCAllInsnOpsJAL{ \begin{scope}[shift={(0,0)}]\DrawGCInsnOpJ{1101111}{jal}{rd,pcrel\_21}{Jump And Link}{\tt rd $\leftarrow$ pc+4, pc $\leftarrow$ pc+imm\_j}\end{scope} \begin{scope}[shift={(0,-1.5)}]\DrawGCInsnOpI{1100111}{000}{jalr}{rd,imm(rs1)}{Jump And Link Register}{\tt rd $\leftarrow$ pc+4, pc $\leftarrow$ (rs1+imm\_i) $\land$ $\sim$1}\end{scope} } \newcommand\DrawGCAllInsnOpsBranch{ \begin{scope}[shift={(0,0)}]\DrawGCInsnOpB{1100011}{000}{beq}{rs1,rs2,pcrel\_13}{Branch Equal}{\tt pc $\leftarrow$ pc + ((rs1==rs2) ?\ imm\_b :\ 4)}\end{scope} \begin{scope}[shift={(0,-1.5)}]\DrawGCInsnOpB{1100011}{001}{bne}{rs1,rs2,pcrel\_13}{Branch Not Equal}{\tt pc $\leftarrow$ pc + ((rs1!=rs2) ?\ imm\_b :\ 4)}\end{scope} \begin{scope}[shift={(0,-3)}]\DrawGCInsnOpB{1100011}{100}{blt}{rs1,rs2,pcrel\_13}{Branch Less Than}{\tt pc $\leftarrow$ pc + ((rs1=rs2) ?\ imm\_b :\ 4)}\end{scope} \begin{scope}[shift={(0,-6)}]\DrawGCInsnOpB{1100011}{110}{bltu}{rs1,rs2,pcrel\_13}{Branch Less Than Unsigned}{\tt pc $\leftarrow$ pc + ((rs1=rs2) ?\ imm\_b :\ 4)}\end{scope} } \newcommand\DrawGCAllInsnOpsLoad{ \begin{scope}[shift={(0,0)}]\DrawGCInsnOpI{0000011}{000}{lb}{rd,imm(rs1)}{Load Byte}{\tt rd $\leftarrow$ sx(m8(rs1+imm\_i)), pc $\leftarrow$ pc+4}\end{scope} \begin{scope}[shift={(0,-1.5)}]\DrawGCInsnOpI{0000011}{001}{lh}{rd,imm(rs1)}{Load Halfword}{\tt rd $\leftarrow$ sx(m16(rs1+imm\_i)), pc $\leftarrow$ pc+4}\end{scope} \begin{scope}[shift={(0,-3.0)}]\DrawGCInsnOpI{0000011}{010}{lw}{rd,imm(rs1)}{Load Word}{\tt rd $\leftarrow$ sx(m32(rs1+imm\_i)), pc $\leftarrow$ pc+4}\end{scope} \begin{scope}[shift={(0,-4.5)}]\DrawGCInsnOpI{0000011}{100}{lbu}{rd,imm(rs1)}{Load Byte Unsigned}{\tt rd $\leftarrow$ zx(m8(rs1+imm\_i)), pc $\leftarrow$ pc+4}\end{scope} \begin{scope}[shift={(0,-6.0)}]\DrawGCInsnOpI{0000011}{101}{lhu}{rd,imm(rs1)}{Load Halfword Unsigned}{\tt rd $\leftarrow$ zx(m16(rs1+imm\_i)), pc $\leftarrow$ pc+4}\end{scope} } \newcommand\DrawGCAllInsnOpsALUImm{ \begin{scope}[shift={(0,0)}]\DrawGCInsnOpI{0010011}{000}{addi}{rd,rs1,imm}{Add Immediate}{\tt rd $\leftarrow$ rs1 + imm\_i, pc $\leftarrow$ pc+4}\end{scope} \begin{scope}[shift={(0,-1.5)}]\DrawGCInsnOpI{0010011}{010}{slti}{rd,rs1,imm}{Set Less Than Immediate}{\tt rd $\leftarrow$ (rs1 < imm\_i) ?\ 1 :\ 0, pc $\leftarrow$ pc+4}\end{scope} \begin{scope}[shift={(0,-3.0)}]\DrawGCInsnOpI{0010011}{011}{sltiu}{rd,rs1,imm}{Set Less Than Immediate Unsigned}{\tt rd $\leftarrow$ (rs1 < imm\_i) ?\ 1 :\ 0, pc $\leftarrow$ pc+4}\end{scope} \begin{scope}[shift={(0,-4.5)}]\DrawGCInsnOpI{0010011}{100}{xori}{rd,rs1,imm}{Exclusive Or Immediate}{\tt rd $\leftarrow$ rs1 $\oplus$ imm\_i, pc $\leftarrow$ pc+4}\end{scope} \begin{scope}[shift={(0,-6.0)}]\DrawGCInsnOpI{0010011}{110}{ori}{rd,rs1,imm}{Or Immediate}{\tt rd $\leftarrow$ rs1 $\lor$ imm\_i, pc $\leftarrow$ pc+4}\end{scope} \begin{scope}[shift={(0,-7.5)}]\DrawGCInsnOpI{0010011}{111}{andi}{rd,rs1,imm}{And Immediate}{\tt rd $\leftarrow$ rs1 $\land$ imm\_i, pc $\leftarrow$ pc+4}\end{scope} } % note that the S-Type insns have the same field-format as the B-type \newcommand\DrawGCAllInsnOpsStore{ \begin{scope}[shift={(0,0)}]\DrawGCInsnOpS{0100011}{000}{sb}{rs2,imm(rs1)}{Store Byte}{\tt m8(rs1+imm\_s) $\leftarrow$ rs2[7:0], pc $\leftarrow$ pc+4}\end{scope} \begin{scope}[shift={(0,-1.5)}]\DrawGCInsnOpS{0100011}{001}{sh}{rs2,imm(rs1)}{Store Halfword}{\tt m16(rs1+imm\_s) $\leftarrow$ rs2[15:0], pc $\leftarrow$ pc+4}\end{scope} \begin{scope}[shift={(0,-3.0)}]\DrawGCInsnOpS{0100011}{010}{sw}{rs2,imm(rs1)}{Store Word}{\tt m32(rs1+imm\_s) $\leftarrow$ rs2[31:0], pc $\leftarrow$ pc+4}\end{scope} } \newcommand\DrawGCAllInsnOpsALUR{ \begin{scope}[shift={(0,0)}]\DrawGCInsnOpR{0110011}{000}{0000000}{add}{rd,rs1,rs2}{Add}{\tt rd $\leftarrow$ rs1 + rs2, pc $\leftarrow$ pc+4}\end{scope} \begin{scope}[shift={(0,-1.5)}]\DrawGCInsnOpR{0110011}{000}{0100000}{sub}{rd,rs1,rs2}{Subtract}{\tt rd $\leftarrow$ rs1 - rs2, pc $\leftarrow$ pc+4}\end{scope} \begin{scope}[shift={(0,-3.0)}]\DrawGCInsnOpR{0110011}{001}{0000000}{sll}{rd,rs1,rs2}{Shift Left Logical}{\tt rd $\leftarrow$ rs1 << (rs2\%XLEN), pc $\leftarrow$ pc+4}\end{scope} \begin{scope}[shift={(0,-4.5)}]\DrawGCInsnOpR{0110011}{010}{0000000}{slt}{rd,rs1,rs2}{Set Less Than}{\tt rd $\leftarrow$ (rs1 < rs2) ?\ 1 :\ 0, pc $\leftarrow$ pc+4}\end{scope} \begin{scope}[shift={(0,-6.0)}]\DrawGCInsnOpR{0110011}{011}{0000000}{sltu}{rd,rs1,rs2}{Set Less Than Unsigned}{\tt rd $\leftarrow$ (rs1 < rs2) ?\ 1 :\ 0, pc $\leftarrow$ pc+4}\end{scope} \begin{scope}[shift={(0,-7.5)}]\DrawGCInsnOpR{0110011}{100}{0000000}{xor}{rd,rs1,rs2}{Exclusive Or}{\tt rd $\leftarrow$ rs1 $\oplus$ rs2, pc $\leftarrow$ pc+4}\end{scope} \begin{scope}[shift={(0,-9.0)}]\DrawGCInsnOpR{0110011}{101}{0000000}{srl}{rd,rs1,rs2}{Shift Right Logical}{\tt rd $\leftarrow$ rs1 >> (rs2\%XLEN), pc $\leftarrow$ pc+4}\end{scope} \begin{scope}[shift={(0,-10.5)}]\DrawGCInsnOpR{0110011}{101}{0100000}{sra}{rd,rs1,rs2}{Shift Right Arithmetic}{\tt rd $\leftarrow$ rs1 >> (rs2\%XLEN), pc $\leftarrow$ pc+4}\end{scope} \begin{scope}[shift={(0,-12.0)}]\DrawGCInsnOpR{0110011}{110}{0000000}{or}{rd,rs1,rs2}{Or}{\tt rd $\leftarrow$ rs1 $\lor$ rs2, pc $\leftarrow$ pc+4}\end{scope} \begin{scope}[shift={(0,-13.5)}]\DrawGCInsnOpR{0110011}{111}{0000000}{and}{rd,rs1,rs2}{And}{\tt rd $\leftarrow$ rs1 $\land$ rs2, pc $\leftarrow$ pc+4}\end{scope} } \newcommand\DrawGCAllInsnOpsSystem{ \begin{scope}[shift={(0,0)}]\DrawGCInsnOpICSR{1110011}{001}{csrrw}{rd,csr,rs1}{rs1}{Atomic Read/Write}{\tt rd $\leftarrow$ csr, csr $\leftarrow$ rs1, pc $\leftarrow$ pc+4}\end{scope} \begin{scope}[shift={(0,-1.5)}]\DrawGCInsnOpICSR{1110011}{010}{csrrs}{rd,csr,rs1}{rs1}{Atomic Read and Set}{\tt rd $\leftarrow$ csr, csr $\leftarrow$ csr $\lor$ rs1, pc $\leftarrow$ pc+4}\end{scope} \begin{scope}[shift={(0,-3.0)}]\DrawGCInsnOpICSR{1110011}{011}{csrrc}{rd,csr,rs1}{rs1}{Atomic Read and Clear}{\tt rd $\leftarrow$ csr, csr $\leftarrow$ csr $\land$ $\sim$rs1, pc $\leftarrow$ pc+4}\end{scope} \begin{scope}[shift={(0,-4.5)}]\DrawGCInsnOpICSR{1110011}{101}{csrrwi}{rd,csr,zimm}{zimm[4:0]}{Atomic Read/Write Immediate}{\tt rd $\leftarrow$ csr, csr $\leftarrow$ zimm, pc $\leftarrow$ pc+4}\end{scope} \begin{scope}[shift={(0,-6.0)}]\DrawGCInsnOpICSR{1110011}{110}{csrrsi}{rd,csr,zimm}{zimm[4:0]}{Atomic Read and Set Immediate}{\tt rd $\leftarrow$ csr, csr $\leftarrow$ csr $\lor$ zimm, pc $\leftarrow$ pc+4}\end{scope} \begin{scope}[shift={(0,-7.5)}]\DrawGCInsnOpICSR{1110011}{111}{csrrci}{rd,csr,zimm}{zimm[4:0]}{Atomic Read and Clear Immediate}{\tt rd $\leftarrow$ csr, csr $\leftarrow$ csr $\land$ $\sim$zimm, pc $\leftarrow$ pc+4}\end{scope} } \newcommand\DrawGCAllInsnOpsSim{ \begin{scope}[shift={(0,0)}]\DrawGCInsnOpSys{1110011}{000000000000}{ecall}{Trap to Debugger}\end{scope} \begin{scope}[shift={(0,-1.5)}]\DrawGCInsnOpSys{1110011}{000000000001}{ebreak}{Trap to Operating System}\end{scope} } \newcommand\DrawGCAllInsnOpsShiftImm{ \begin{scope}[shift={(0,0)}]\DrawGCInsnOpIShift{0010011}{001}{0000000}{slli}{rd,rs1,shamt}{Shift Left Logical Immediate}{\tt rd $\leftarrow$ rs1 << shamt\_i, pc $\leftarrow$ pc+4}\end{scope} \begin{scope}[shift={(0,-1.5)}]\DrawGCInsnOpIShift{0010011}{101}{0000000}{srli}{rd,rs1,shamt}{Shift Right Logical Immediate}{\tt rd $\leftarrow$ rs1 >> shamt\_i, pc $\leftarrow$ pc+4}\end{scope} \begin{scope}[shift={(0,-3.0)}]\DrawGCInsnOpIShift{0010011}{101}{0100000}{srai}{rd,rs1,shamt}{Shift Right Arithmetic Immediate}{\tt rd $\leftarrow$ rs1 >> shamt\_i, pc $\leftarrow$ pc+4}\end{scope} } \newcommand\DrawGCAllInsnOpsPseudo{ \draw(0, 0) node[right]{p1}; \draw(0, -1.5) node[right]{p1}; \draw(0, -3.0) node[right]{p1}; \draw(0, -4.5) node[right]{p1}; \draw(0, -6.0) node[right]{p1}; \draw(0, -7.5) node[right]{p1}; \draw(0, -9.0) node[right]{p1}; \draw(0,-10.5) node[right]{p1}; \draw(0,-12.0) node[right]{p1}; \draw(0,-13.5) node[right]{p1}; \draw(0,-15.0) node[right]{p1}; \draw(0,-16.5) node[right]{p1}; \draw(0,-18.0) node[right]{p1}; } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % a color to hilight the rows on the card \definecolor{GCBarColorBG}{RGB}{200,255,200} \definecolor{GCBarColorFG}{RGB}{128,220,128} \definecolor{GCSlugColorFG}{RGB}{20,100,20} \newcommand\DrawGCAllInsnOps{ \BeginTikzPicture % draw color graybars \foreach \y in {1.5,-7.5,...,-66}% \draw [draw=GCBarColorFG,fill=GCBarColorBG,thick] (0,\y) rectangle (\GCPageWidth,\y-4.5); % draw some nybble-slugs \foreach \y in {-3,-7.5,...,-66}% \foreach \x in {4,8,...,30}% \draw [line width=.5mm,draw=GCSlugColorFG] (\x+.5+\GCInsnEncodingPosX,\y) -- (\x+.5+\GCInsnEncodingPosX, \y+.3);% \begin{scope}[shift={(\GCInsnEncodingPosX,1.5)}]\DrawInsnBoxCastleRtype\end{scope} % add some field names in the castle \begin{scope}[shift={(\GCInsnEncodingPosX,1.5)}] \node at (4,1.25) {\small funct7}; \node at (19,1.25) {\small funct3}; \node at (29,1.25) {\small opcode}; \end{scope} \draw node at (\GCInsnMnemonicPosX+6,2.75) {\small Instruction}; \draw node at (\GCInsnDescriptionPosX+8,2.75) {\small Description}; \draw node at (\GCInsnRTLPosX+12,2.75) {\small Operation}; \draw node at (\GCInsnTypePosX,2.75) {\small Type}; %\node [draw, rotate=90] at (0,60) {\small RV32I Reference Card (\href{https://github.com/johnwinans/rvalp}{https://github.com/johnwinans/rvalp})}; %\draw node[rotate=90,right] at (\GCPageWidth+.7,-66) {\small RV32I Reference Card}; %\draw node[rotate=90,left] at (\GCPageWidth+.7,1.5) {\small https://github.com/johnwinans/rvalp}; \draw node[rotate=90,right] at (-.7,-66) {\small RV32I Reference Card}; \draw node[rotate=90,left] at (-.7,1.5) {\small https://github.com/johnwinans/rvalp}; \begin{scope}[shift={(0,0)}]\DrawGCAllInsnOpsU\end{scope} \begin{scope}[shift={(0,-3)}]\DrawGCAllInsnOpsJAL\end{scope} \begin{scope}[shift={(0,-6)}]\DrawGCAllInsnOpsBranch\end{scope} \begin{scope}[shift={(0,-15)}]\DrawGCAllInsnOpsLoad\end{scope} \begin{scope}[shift={(0,-22.5)}]\DrawGCAllInsnOpsStore\end{scope} \begin{scope}[shift={(0,-27)}]\DrawGCAllInsnOpsALUImm\end{scope} \begin{scope}[shift={(0,-36)}]\DrawGCAllInsnOpsShiftImm\end{scope} \begin{scope}[shift={(0,-40.5)}]\DrawGCAllInsnOpsALUR\end{scope} \begin{scope}[shift={(0,-55.5)}]\DrawGCAllInsnOpsSim\end{scope} \begin{scope}[shift={(0,-58.5)}]\DrawGCAllInsnOpsSystem\end{scope} % stub in some space for pseudo-instruictions to see what it might look like %\begin{scope}[shift={(0,-67)}]\DrawGCAllInsnOpsPseudo\end{scope} % show markers to indicate where to fold it \draw [line width=.1mm,draw=GCSlugColorFG] (29.5,1) -- (29.5, 1.5); \draw [line width=.1mm,draw=GCSlugColorFG] (29.5,-65.5) -- (29.5, -66); \EndTikzPicture } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \newcommand\InsnBoxFieldWidthArrowVskip{.5} \newcommand\InsnBoxFieldWidthArrowHskip{.05} % #1 MSB position % #2 LSB position \newcommand\InsnBoxFieldWidthArrow[2]{ \pgfmathsetmacro\leftpos{int(31-#1)} % Calculate the left end position \pgfmathsetmacro\wid{int(#1-#2+1)} % calculate the width \begin{scope}[shift={(\leftpos,-\InsnBoxFieldWidthArrowVskip)}] % Move to left end of arrow & below origin \pgfmathsetmacro\result{\wid*.5+.5} % the center position \node at (\result,0) {\tiny\wid}; % draw the size number below the box \ifthenelse{\wid > 9} % make 1-9 narrower than 10-99 { \pgfmathsetmacro\Inset{0.4} } { \ifthenelse{\wid > 1} % make 1 narrower than 2-9 { \pgfmathsetmacro\Inset{0.25} } { \pgfmathsetmacro\Inset{0.15} } } % arrowsInsnBoxFieldWidthArrowHskip \draw[->] (\result+\Inset,0) -- (\wid+.5-\InsnBoxFieldWidthArrowHskip,0); % arrow to the right \draw[->] (\result-\Inset,0) -- (.5+\InsnBoxFieldWidthArrowHskip,0); % arrow to the left \pgfmathsetmacro\x{.5} \pgfmathsetmacro\y{\InsnBoxFieldWidthArrowVskip} % vertical bars at the ends of the arrows \draw[-] (\x,\y) -- (\x,-\y*.5); \pgfmathsetmacro\x{(\wid+.5} \draw[-] (\x,\y) -- (\x,-\y*.5); \end{scope} } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \newcommand\BitBoxArrowTailInset{-.9} \newcommand\BitBoxArrowHeadInset{-16.7-\BitBoxArrowTailInset} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % special case for R type instructions for consistency \newcommand\InsnOpRTypeDecoding{ \begin{scope}[shift={(0,-1.5)}] \DrawInsnTypeR{abcdefghijklmnopqrstuvwxy1101111} \end{scope} } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \newcommand\InsnOpJTypeDecoding{ \begin{scope}[shift={(0,-1.5)}] \DrawInsnTypeJ{abcdefghijklmnopqrst001111101111} \pgfmathsetmacro\ArrowNorth{\BitBoxArrowTailInset} \pgfmathsetmacro\ArrowSouth{\BitBoxArrowHeadInset} \draw[red,->](1,\ArrowNorth)to[out=270,in=90](1,\ArrowSouth); % 20 \draw[red,->](1,\ArrowNorth)to[out=270,in=90](2,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](3,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](4,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](5,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](6,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](7,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](8,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](9,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](10,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](11,\ArrowSouth); % sign extend \draw[blue,->](1,\ArrowNorth)to[out=270,in=90](12,\ArrowSouth); % 20 \draw[blue,->](13,\ArrowNorth)to[out=270,in=90](13,\ArrowSouth); % 19 \draw[blue,->](14,\ArrowNorth)to[out=270,in=90](14,\ArrowSouth); % 18 \draw[blue,->](15,\ArrowNorth)to[out=270,in=90](15,\ArrowSouth); % 17 \draw[blue,->](16,\ArrowNorth)to[out=270,in=90](16,\ArrowSouth); % 16 \draw[blue,->](17,\ArrowNorth)to[out=270,in=90](17,\ArrowSouth); % 15 \draw[blue,->](18,\ArrowNorth)to[out=270,in=90](18,\ArrowSouth); % 14 \draw[blue,->](19,\ArrowNorth)to[out=270,in=90](19,\ArrowSouth); % 13 \draw[blue,->](20,\ArrowNorth)to[out=270,in=90](20,\ArrowSouth); % 12 \draw[blue,->](12,\ArrowNorth)to[out=270,in=90](21,\ArrowSouth); % 11 \draw[blue,->](2,\ArrowNorth)to[out=270,in=90](22,\ArrowSouth); % 10 \draw[blue,->](3,\ArrowNorth)to[out=270,in=90](23,\ArrowSouth); % 9 \draw[blue,->](4,\ArrowNorth)to[out=270,in=90](24,\ArrowSouth); % 8 \draw[blue,->](5,\ArrowNorth)to[out=270,in=90](25,\ArrowSouth); % 7 \draw[blue,->](6,\ArrowNorth)to[out=270,in=90](26,\ArrowSouth); % 6 \draw[blue,->](7,\ArrowNorth)to[out=270,in=90](27,\ArrowSouth); % 5 \draw[blue,->](8,\ArrowNorth)to[out=270,in=90](28,\ArrowSouth); % 4 \draw[blue,->](9,\ArrowNorth)to[out=270,in=90](29,\ArrowSouth); % 3 \draw[blue,->](10,\ArrowNorth)to[out=270,in=90](30,\ArrowSouth); % 2 \draw[blue,->](11,\ArrowNorth)to[out=270,in=90](31,\ArrowSouth); % 1 \draw[red,->](34,\ArrowSouth+5)to[out=180,in=90](32,\ArrowSouth); % 0 (special case) \node at (34.5,\ArrowSouth+5) {0}; % \draw[blue,->](32,\ArrowSouth+1)to[out=270,in=90](32,\ArrowSouth); % 0 (special case) % \node at (32,\ArrowSouth+2) {0}; \begin{scope}[shift={(0,0)}]\DrawHexMarkersRel{32}\end{scope} \end{scope} \begin{scope}[shift={(0,-19.75)}] \begin{scope}[shift={(0,1.5)}] \DrawInsnBoxCastle{31}{21} \DrawInsnBoxCastle{20}{20} \DrawInsnBoxCastle{19}{12} \DrawInsnBoxCastle{11}{11} \DrawInsnBoxCastle{10}{1} \DrawInsnBoxCastle{0}{0} \end{scope} \DrawInsnBoxRel{31}{0}{} \draw(33,.5) node[text width = 10, text height = 1, right]{imm\_j}; \begin{scope}[shift={(0,0)}]\DrawBitstringX{aaaaaaaaaaaamnopqrstlbcdefghijk0}\end{scope} \begin{scope}[shift={(0,0)}]\DrawHexMarkersRel{32}\end{scope} \InsnBoxFieldWidthArrow{31}{21} \InsnBoxFieldWidthArrow{20}{20} \InsnBoxFieldWidthArrow{19}{12} \InsnBoxFieldWidthArrow{11}{11} \InsnBoxFieldWidthArrow{10}{1} \InsnBoxFieldWidthArrow{0}{0} \end{scope} } \newcommand\DrawInsnOpJTypeDecoding{ \BeginTikzPicture \InsnOpJTypeDecoding \EndTikzPicture } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \newcommand\InsnOpBTypeDecoding{ \begin{scope}[shift={(0,-1.5)}] \DrawInsnTypeB{abcdefg0111100011000uvwxy1100011} \pgfmathsetmacro\ArrowNorth{\BitBoxArrowTailInset} \pgfmathsetmacro\ArrowSouth{\BitBoxArrowHeadInset} \draw[red,->](1,\ArrowNorth)to[out=270,in=90](1,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](2,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](3,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](4,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](5,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](6,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](7,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](8,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](9,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](10,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](11,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](12,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](13,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](14,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](15,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](16,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](17,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](18,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](19,\ArrowSouth); % sign extend \draw[blue,->](1,\ArrowNorth)to[out=270,in=90](20,\ArrowSouth); % 12 \draw[blue,->](25,\ArrowNorth)to[out=270,in=90](21,\ArrowSouth); % 11 \draw[blue,->](2,\ArrowNorth)to[out=270,in=90](22,\ArrowSouth); % 10 \draw[blue,->](3,\ArrowNorth)to[out=270,in=90](23,\ArrowSouth); % 9 \draw[blue,->](4,\ArrowNorth)to[out=270,in=90](24,\ArrowSouth); % 8 \draw[blue,->](5,\ArrowNorth)to[out=270,in=90](25,\ArrowSouth); % 7 \draw[blue,->](6,\ArrowNorth)to[out=270,in=90](26,\ArrowSouth); % 6 \draw[blue,->](7,\ArrowNorth)to[out=270,in=90](27,\ArrowSouth); % 5 \draw[blue,->](21,\ArrowNorth)to[out=270,in=90](28,\ArrowSouth); % 4 \draw[blue,->](22,\ArrowNorth)to[out=270,in=90](29,\ArrowSouth); % 3 \draw[blue,->](23,\ArrowNorth)to[out=270,in=90](30,\ArrowSouth); % 2 \draw[blue,->](24,\ArrowNorth)to[out=270,in=90](31,\ArrowSouth); % 1 \draw[red,->](34,\ArrowSouth+5)to[out=180,in=90](32,\ArrowSouth); % 0 (special case) \node at (34.5,\ArrowSouth+5) {0}; % \draw[blue,->](32,\ArrowSouth+1)to[out=270,in=90](32,\ArrowSouth); % 0 (special case) % \node at (32,\ArrowSouth+2) {0}; \begin{scope}[shift={(0,0)}]\DrawHexMarkersRel{32}\end{scope} \end{scope} \begin{scope}[shift={(0,-19.75)}] \begin{scope}[shift={(0,1.5)}] \DrawInsnBoxCastle{31}{13} \DrawInsnBoxCastle{12}{12} \DrawInsnBoxCastle{11}{11} \DrawInsnBoxCastle{10}{5} \DrawInsnBoxCastle{4}{1} \DrawInsnBoxCastle{0}{0} \end{scope} \DrawInsnBoxRel{31}{0}{} \draw(33,.5) node[text width = 10, text height = 1, right]{imm\_b}; \begin{scope}[shift={(0,0)}]\DrawBitstringX{aaaaaaaaaaaaaaaaaaaaybcdefguvwx0}\end{scope} \begin{scope}[shift={(0,0)}]\DrawHexMarkersRel{32}\end{scope} \InsnBoxFieldWidthArrow{31}{13} \InsnBoxFieldWidthArrow{12}{12} \InsnBoxFieldWidthArrow{11}{11} \InsnBoxFieldWidthArrow{10}{5} \InsnBoxFieldWidthArrow{4}{1} \InsnBoxFieldWidthArrow{0}{0} \end{scope} } \newcommand\DrawInsnOpBTypeDecoding{ \BeginTikzPicture \InsnOpBTypeDecoding \EndTikzPicture } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \newcommand\InsnOpSTypeDecoding{ \begin{scope}[shift={(0,-1.5)}] \DrawInsnTypeS{abcdefg0111100011000uvwxy0100011} \pgfmathsetmacro\ArrowNorth{\BitBoxArrowTailInset} \pgfmathsetmacro\ArrowSouth{\BitBoxArrowHeadInset} \draw[red,->](1,\ArrowNorth)to[out=270,in=90](1,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](2,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](3,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](4,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](5,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](6,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](7,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](8,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](9,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](10,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](11,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](12,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](13,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](14,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](15,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](16,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](17,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](18,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](19,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](20,\ArrowSouth); % sign extend \draw[blue,->](1,\ArrowNorth)to[out=270,in=90](21,\ArrowSouth); % 11 \draw[blue,->](2,\ArrowNorth)to[out=270,in=90](22,\ArrowSouth); % 10 \draw[blue,->](3,\ArrowNorth)to[out=270,in=90](23,\ArrowSouth); % 9 \draw[blue,->](4,\ArrowNorth)to[out=270,in=90](24,\ArrowSouth); % 8 \draw[blue,->](5,\ArrowNorth)to[out=270,in=90](25,\ArrowSouth); % 7 \draw[blue,->](6,\ArrowNorth)to[out=270,in=90](26,\ArrowSouth); % 6 \draw[blue,->](7,\ArrowNorth)to[out=270,in=90](27,\ArrowSouth); % 5 \draw[blue,->](21,\ArrowNorth)to[out=270,in=90](28,\ArrowSouth); % 4 \draw[blue,->](22,\ArrowNorth)to[out=270,in=90](29,\ArrowSouth); % 3 \draw[blue,->](23,\ArrowNorth)to[out=270,in=90](30,\ArrowSouth); % 2 \draw[blue,->](24,\ArrowNorth)to[out=270,in=90](31,\ArrowSouth); % 1 \draw[blue,->](25,\ArrowNorth)to[out=270,in=90](32,\ArrowSouth); % 0 \begin{scope}[shift={(0,0)}]\DrawHexMarkersRel{32}\end{scope} \end{scope} \begin{scope}[shift={(0,-19.75)}] \begin{scope}[shift={(0,1.5)}] \DrawInsnBoxCastle{31}{12} \DrawInsnBoxCastle{11}{5} \DrawInsnBoxCastle{4}{0} \end{scope} \DrawInsnBoxRel{31}{0}{} \draw(33,.5) node[text width = 10, text height = 1, right]{imm\_s}; \begin{scope}[shift={(0,0)}]\DrawBitstringX{aaaaaaaaaaaaaaaaaaaaabcdefguvwxy}\end{scope} \begin{scope}[shift={(0,0)}]\DrawHexMarkersRel{32}\end{scope} \InsnBoxFieldWidthArrow{31}{12} \InsnBoxFieldWidthArrow{11}{5} \InsnBoxFieldWidthArrow{4}{0} \end{scope} } \newcommand\DrawInsnOpSTypeDecoding{ \BeginTikzPicture \InsnOpSTypeDecoding \EndTikzPicture } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \newcommand\InsnOpITypeDecoding{ \begin{scope}[shift={(0,-1.5)}] \DrawInsnTypeI{abcdefghijkl00011000001110000011} \pgfmathsetmacro\ArrowNorth{\BitBoxArrowTailInset} \pgfmathsetmacro\ArrowSouth{\BitBoxArrowHeadInset} \draw[red,->](1,\ArrowNorth)to[out=270,in=90](1,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](2,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](3,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](4,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](5,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](6,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](7,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](8,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](9,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](10,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](11,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](12,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](13,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](14,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](15,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](16,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](17,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](18,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](19,\ArrowSouth); % sign extend \draw[red,->](1,\ArrowNorth)to[out=270,in=90](20,\ArrowSouth); % sign extend \draw[blue,->](1,\ArrowNorth)to[out=270,in=90](21,\ArrowSouth); % 11 \draw[blue,->](2,\ArrowNorth)to[out=270,in=90](22,\ArrowSouth); % 10 \draw[blue,->](3,\ArrowNorth)to[out=270,in=90](23,\ArrowSouth); % 9 \draw[blue,->](4,\ArrowNorth)to[out=270,in=90](24,\ArrowSouth); % 8 \draw[blue,->](5,\ArrowNorth)to[out=270,in=90](25,\ArrowSouth); % 7 \draw[blue,->](6,\ArrowNorth)to[out=270,in=90](26,\ArrowSouth); % 6 \draw[blue,->](7,\ArrowNorth)to[out=270,in=90](27,\ArrowSouth); % 5 \draw[blue,->](8,\ArrowNorth)to[out=270,in=90](28,\ArrowSouth); % 4 \draw[blue,->](9,\ArrowNorth)to[out=270,in=90](29,\ArrowSouth); % 3 \draw[blue,->](10,\ArrowNorth)to[out=270,in=90](30,\ArrowSouth); % 2 \draw[blue,->](11,\ArrowNorth)to[out=270,in=90](31,\ArrowSouth); % 1 \draw[blue,->](12,\ArrowNorth)to[out=270,in=90](32,\ArrowSouth); % 0 \begin{scope}[shift={(0,0)}]\DrawHexMarkersRel{32}\end{scope} \end{scope} \begin{scope}[shift={(0,-19.75)}] \begin{scope}[shift={(0,1.5)}] \DrawInsnBoxCastle{31}{12} \DrawInsnBoxCastle{11}{0} \end{scope} \DrawInsnBoxRel{31}{0}{} \draw(33,.5) node[text width = 10, text height = 1, right]{imm\_i}; \begin{scope}[shift={(0,0)}]\DrawBitstringX{aaaaaaaaaaaaaaaaaaaaabcdefghijkl}\end{scope} \begin{scope}[shift={(0,0)}]\DrawHexMarkersRel{32}\end{scope} \InsnBoxFieldWidthArrow{31}{12} \InsnBoxFieldWidthArrow{11}{0} \end{scope} } \newcommand\DrawInsnOpITypeDecoding{ \BeginTikzPicture \InsnOpITypeDecoding \EndTikzPicture } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \newcommand\InsnOpIShiftTypeDecoding{ \begin{scope}[shift={(0,-1.5)}] \DrawInsnTypeI{0b00000hijkl00011000001110000011} \pgfmathsetmacro\ArrowNorth{\BitBoxArrowTailInset} \pgfmathsetmacro\ArrowSouth{\BitBoxArrowHeadInset} \pgfmathsetmacro\ZeroNodeY{\ArrowSouth+4} \pgfmathsetmacro\ZeroNodeX{1} % \node at (\ZeroNodeX,\ZeroNodeY) {0}; % \draw[red,->](\ZeroNodeX+.5,\ZeroNodeY)to[out=0,in=90](1,\ArrowSouth); % \draw[red,->](\ZeroNodeX+.5,\ZeroNodeY)to[out=0,in=90](2,\ArrowSouth); % \draw[red,->](\ZeroNodeX+.5,\ZeroNodeY)to[out=0,in=90](3,\ArrowSouth); % \draw[red,->](\ZeroNodeX+.5,\ZeroNodeY)to[out=0,in=110](4,\ArrowSouth); % \draw[red,->](\ZeroNodeX+.5,\ZeroNodeY)to[out=0,in=110](5,\ArrowSouth); % \draw[red,->](\ZeroNodeX+.5,\ZeroNodeY)to[out=0,in=110](6,\ArrowSouth); % \draw[red,->](\ZeroNodeX+.5,\ZeroNodeY)to[out=0,in=110](7,\ArrowSouth); % \draw[red,->](\ZeroNodeX+.5,\ZeroNodeY)to[out=0,in=110](8,\ArrowSouth); % \draw[red,->](\ZeroNodeX+.5,\ZeroNodeY)to[out=0,in=110](9,\ArrowSouth); % \draw[red,->](\ZeroNodeX+.5,\ZeroNodeY)to[out=0,in=110](10,\ArrowSouth); % \draw[red,->](\ZeroNodeX+.5,\ZeroNodeY)to[out=0,in=110](11,\ArrowSouth); % \draw[red,->](\ZeroNodeX+.5,\ZeroNodeY)to[out=0,in=110](12,\ArrowSouth); % \draw[red,->](\ZeroNodeX+.5,\ZeroNodeY)to[out=0,in=110](13,\ArrowSouth); % \draw[red,->](\ZeroNodeX+.5,\ZeroNodeY)to[out=0,in=110](14,\ArrowSouth); % \draw[red,->](\ZeroNodeX+.5,\ZeroNodeY)to[out=0,in=110](15,\ArrowSouth); % \draw[red,->](\ZeroNodeX+.5,\ZeroNodeY)to[out=0,in=110](16,\ArrowSouth); % \draw[red,->](\ZeroNodeX+.5,\ZeroNodeY)to[out=0,in=110](17,\ArrowSouth); % \draw[red,->](\ZeroNodeX+.5,\ZeroNodeY)to[out=0,in=110](18,\ArrowSouth); % \draw[red,->](\ZeroNodeX+.5,\ZeroNodeY)to[out=0,in=110](19,\ArrowSouth); % \draw[red,->](\ZeroNodeX+.5,\ZeroNodeY)to[out=0,in=110](20,\ArrowSouth); % \draw[red,->](\ZeroNodeX+.5,\ZeroNodeY)to[out=0,in=110](21,\ArrowSouth); % \draw[red,->](\ZeroNodeX+.5,\ZeroNodeY)to[out=0,in=110](22,\ArrowSouth); % \draw[red,->](\ZeroNodeX+.5,\ZeroNodeY)to[out=0,in=110](23,\ArrowSouth); % \draw[red,->](\ZeroNodeX+.5,\ZeroNodeY)to[out=0,in=110](24,\ArrowSouth); % \draw[red,->](\ZeroNodeX+.5,\ZeroNodeY)to[out=0,in=110](25,\ArrowSouth); % \draw[red,->](\ZeroNodeX+.5,\ZeroNodeY)to[out=0,in=110](26,\ArrowSouth); % \draw[red,->](\ZeroNodeX+.5,\ZeroNodeY)to[out=0,in=110](27,\ArrowSouth); \draw[blue,->](8,\ArrowNorth)to[out=270,in=90](28-8,\ArrowSouth); % 4 \draw[blue,->](9,\ArrowNorth)to[out=270,in=90](29-8,\ArrowSouth); % 3 \draw[blue,->](10,\ArrowNorth)to[out=270,in=90](30-8,\ArrowSouth); % 2 \draw[blue,->](11,\ArrowNorth)to[out=270,in=90](31-8,\ArrowSouth); % 1 \draw[blue,->](12,\ArrowNorth)to[out=270,in=90](32-8,\ArrowSouth); % 0 \draw[blue,->](2,\ArrowNorth)to[out=270,in=90](8,\ArrowSouth); % diff btw logical/arith \begin{scope}[shift={(0,0)}]\DrawHexMarkersRel{32}\end{scope} \end{scope} % shamt_i box \begin{scope}[shift={(-8,-19.75)}] \begin{scope}[shift={(0,1.5)}] \DrawInsnBoxCastle{4}{0} \end{scope} \DrawInsnBoxRel{4}{0}{} \draw(33,.5) node[text width = 10, text height = 1, right]{shamt\_i}; \begin{scope}[shift={(27,0)}]\DrawBitstringX{hijkl}\end{scope} %\begin{scope}[shift={(24,0)}]\DrawHexMarkersRel{0}\end{scope} \begin{scope}[shift={(28,0)}]\TheHexMark{0}\end{scope} \InsnBoxFieldWidthArrow{4}{0} \end{scope} % logical/arith box -- this demonstrates the lack of sane coordinate standards in this file :-/ \begin{scope}[shift={(-24,-19.75)}] \begin{scope}[shift={(0,1.5)}] \DrawInsnBoxCastle{0}{0} \end{scope} \DrawInsnBoxRel{0}{0}{} \draw(33,.5) node[text width = 10, text height = 1, right]{srai/srli}; \begin{scope}[shift={(31,0)}]\DrawBitstringX{b}\end{scope} \InsnBoxFieldWidthArrow{0}{0} \end{scope} } \newcommand\DrawInsnOpIShiftTypeDecoding{ \BeginTikzPicture \InsnOpIShiftTypeDecoding \EndTikzPicture } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \newcommand\InsnOpUTypeDecoding{ \begin{scope}[shift={(0,-1.5)}] \DrawInsnTypeU{abcdefghijklmnopqrst001010110111} \pgfmathsetmacro\ArrowNorth{\BitBoxArrowTailInset} \pgfmathsetmacro\ArrowSouth{\BitBoxArrowHeadInset} \draw[blue,->](1,\ArrowNorth)to[out=270,in=90](1,\ArrowSouth); % \draw[blue,->](2,\ArrowNorth)to[out=270,in=90](2,\ArrowSouth); % \draw[blue,->](3,\ArrowNorth)to[out=270,in=90](3,\ArrowSouth); % \draw[blue,->](4,\ArrowNorth)to[out=270,in=90](4,\ArrowSouth); % \draw[blue,->](5,\ArrowNorth)to[out=270,in=90](5,\ArrowSouth); % \draw[blue,->](6,\ArrowNorth)to[out=270,in=90](6,\ArrowSouth); % \draw[blue,->](7,\ArrowNorth)to[out=270,in=90](7,\ArrowSouth); % \draw[blue,->](8,\ArrowNorth)to[out=270,in=90](8,\ArrowSouth); % \draw[blue,->](9,\ArrowNorth)to[out=270,in=90](9,\ArrowSouth); % \draw[blue,->](10,\ArrowNorth)to[out=270,in=90](10,\ArrowSouth); % \draw[blue,->](11,\ArrowNorth)to[out=270,in=90](11,\ArrowSouth); % \draw[blue,->](12,\ArrowNorth)to[out=270,in=90](12,\ArrowSouth); % \draw[blue,->](13,\ArrowNorth)to[out=270,in=90](13,\ArrowSouth); % \draw[blue,->](14,\ArrowNorth)to[out=270,in=90](14,\ArrowSouth); % \draw[blue,->](15,\ArrowNorth)to[out=270,in=90](15,\ArrowSouth); % \draw[blue,->](16,\ArrowNorth)to[out=270,in=90](16,\ArrowSouth); % \draw[blue,->](17,\ArrowNorth)to[out=270,in=90](17,\ArrowSouth); % \draw[blue,->](18,\ArrowNorth)to[out=270,in=90](18,\ArrowSouth); % \draw[blue,->](19,\ArrowNorth)to[out=270,in=90](19,\ArrowSouth); % \draw[blue,->](20,\ArrowNorth)to[out=270,in=90](20,\ArrowSouth); % \draw[red,->](34,\ArrowSouth+5)to[out=180,in=90](21,\ArrowSouth); % \draw[red,->](34,\ArrowSouth+5)to[out=180,in=90](22,\ArrowSouth); % \draw[red,->](34,\ArrowSouth+5)to[out=180,in=90](23,\ArrowSouth); % \draw[red,->](34,\ArrowSouth+5)to[out=180,in=90](24,\ArrowSouth); % \draw[red,->](34,\ArrowSouth+5)to[out=180,in=90](25,\ArrowSouth); % \draw[red,->](34,\ArrowSouth+5)to[out=180,in=90](26,\ArrowSouth); % \draw[red,->](34,\ArrowSouth+5)to[out=180,in=90](27,\ArrowSouth); % \draw[red,->](34,\ArrowSouth+5)to[out=180,in=90](28,\ArrowSouth); % \draw[red,->](34,\ArrowSouth+5)to[out=180,in=90](29,\ArrowSouth); % \draw[red,->](34,\ArrowSouth+5)to[out=180,in=90](30,\ArrowSouth); % \draw[red,->](34,\ArrowSouth+5)to[out=180,in=90](31,\ArrowSouth); % \draw[red,->](34,\ArrowSouth+5)to[out=180,in=90](32,\ArrowSouth); % 0 (special case) \node at (34.5,\ArrowSouth+5) {0}; \begin{scope}[shift={(0,0)}]\DrawHexMarkersRel{32}\end{scope} \end{scope} \begin{scope}[shift={(0,-19.75)}] \begin{scope}[shift={(0,1.5)}] \DrawInsnBoxCastle{31}{12} \DrawInsnBoxCastle{11}{0} \end{scope} \DrawInsnBoxRel{31}{0}{} \draw(33,.5) node[text width = 10, text height = 1, right]{imm\_u}; \begin{scope}[shift={(0,0)}]\DrawBitstringX{abcdefghijklmnopqrst000000000000}\end{scope} \begin{scope}[shift={(0,0)}]\DrawHexMarkersRel{32}\end{scope} \InsnBoxFieldWidthArrow{31}{12} \InsnBoxFieldWidthArrow{11}{0} \end{scope} } \newcommand\DrawInsnOpUTypeDecoding{ \BeginTikzPicture \InsnOpUTypeDecoding \EndTikzPicture } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Draw something useful for the cover portion of the tri-fold green-card \newcommand\DrawCardTitlePage{ \draw[line width=1.5mm] (111-18,-1) -- (111+18,-1); \draw(111,-5) node {\textbf{\Huge RVALP}}; \draw(111,-10) node {\textbf{\Huge RV32I Reference Card}}; \draw[line width=1.5mm] (111-18,-14) -- (111+18,-14); \draw(111,-150) node {https://github.com/johnwinans/rvalp}; \draw(111,-152) node {\small \GitRevision}; } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Draw all the ribbons in a stack for a reference card \newcommand\DrawInsnRibbons{ \BeginTikzPicture \begin{scope}[yscale=.75] \begin{scope}[shift={(0,0)}]\InsnOpUTypeDecoding\end{scope} \begin{scope}[shift={(0,-25)}]\InsnOpITypeDecoding\end{scope} \begin{scope}[shift={(0,-50)}]\InsnOpIShiftTypeDecoding\end{scope} \begin{scope}[shift={(0,-75)}]\InsnOpSTypeDecoding\end{scope} \begin{scope}[shift={(0,-100)}]\InsnOpBTypeDecoding\end{scope} \begin{scope}[shift={(0,-125)}]\InsnOpJTypeDecoding\end{scope} \begin{scope}[shift={(0,-150)}]\InsnOpRTypeDecoding\end{scope} \begin{scope}[shift={(0,0)}]\DrawCardTitlePage\end{scope} \end{scope} \EndTikzPicture } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % print a register name in typewriter font \newcommand\reg[1]{{\tt #1}} % print an instruction name in typewriter font \newcommand\insn[1]{{\tt #1}} \newcommand\rvddt{{\tt rvddt}} \newcommand\hex[1]{{\tt 0x#1}} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % IEEE-754 Floating Point Number % % #1 sign % #2 exponent % #3 significand \newcommand\DrawIEEEFloat[1]{ \StrLen{#1}[\numchars] \begin{scope}[shift={(0,.75)}] \DrawInsnBitstring{\numchars}{#1}{} \DrawInsnBoxSeg{\numchars}{31}{31}{sign} \DrawInsnBoxSeg{\numchars}{30}{23}{exponent} \DrawInsnBoxSeg{\numchars}{22}{0}{significand} \draw {[rounded corners=\SignBoxCornerRadius] (1.35, -.6) -- (1.35, .6) -- (.65, .6) -- (.65, -.6) -- cycle}; % sign bit \end{scope} \DrawHexMarkersRel{\numchars} } \newcommand\DrawBitBoxIEEEFloat[1]{ \BeginTikzPicture \begin{scope}[shift={(0,0)}]\DrawIEEEFloat{#1}\end{scope} \EndTikzPicture } % %\newcommand\DrawInsnTypeB[1]{ % \StrLen{#1}[\numchars] % \begin{scope}[shift={(0,.75)}] % \DrawInsnBitstring{\numchars}{#1}{\hyperref[insnformat:btype]{B-type}} % \DrawInsnBoxSeg{\numchars}{31}{25}{imm[12\textbar10:5]} % \DrawInsnBoxSeg{\numchars}{24}{20}{rs2} % \DrawInsnBoxSeg{\numchars}{19}{15}{rs1} % \DrawInsnBoxSeg{\numchars}{14}{12}{funct3} % \DrawInsnBoxSeg{\numchars}{11}{7}{imm[4:1\textbar11]} % \DrawInsnBoxSeg{\numchars}{6}{0}{opcode} % % % add some hint bits in for imm fields % \draw {[rounded corners=\SignBoxCornerRadius] (1.35, -.6) -- (1.35, .6) -- (.65, .6) -- (.65, -.6) -- cycle}; % sign bit % \draw (32-7-.5, -.75) -- (32-7-.5, .1); % imm[11] % \draw (32-30-.5, -.75) -- (32-30.5, .1); % imm[12] % % \end{scope} % % \DrawHexMarkersRel{\numchars} %} ================================================ FILE: book/insnsummary/chapter.tex ================================================ \chapter{Instruction Set Summary} \enote{Once the RV32I section is re-factored, it may end up turning into this.} \TDrawInsnTypeUPicture {Load Upper Immediate} {lui rd, imm} {lui t0, 3} {\tt% rd $\leftarrow$ pc + sx(imm<<1)\\ pc $\leftarrow$ pc + 4} {00000000000000000011001010110111} \TDrawInsnTypeUPicture {Add Upper Immediate PC} {auipc rd, imm} {auipc t0, 3} {\tt% rd $\leftarrow$ pc + zr(imm)\\ pc $\leftarrow$ pc + 4} {000000000000000000110010101xxxxx} \TDrawInsnTypeJPicture {Jump And Link} {jal rd, imm} {jal x7, .+16} {\tt% rd $\leftarrow$ pc + 4\\ pc $\leftarrow$ pc + sx(imm<<1)} {00000001000000000000001111101111} \TDrawInsnTypeIPicture {Jump And Link Register} {jalr rd, rs1, imm} {jalr x1, x7, 4} {\tt% rd $\leftarrow$ pc + 4\\ pc $\leftarrow$ (rs1 + sx(imm)) \& \textasciitilde{}1} {00000000010000111000000011100111} \enote{These branches (and likely other insns) are not encoded properly!} \TDrawInsnTypeBPicture {Branch Equal} {beq rs1, rs2, imm} {beq x3, x15, 2064} {\tt pc $\leftarrow$ (rs1==rs2) ? pc+sx(imm[12:1]<<1) : pc+4} {00000000111100011000100011100011} \TDrawInsnTypeBPicture {Branch Not Equal} {bne rs1, rs2, imm} {bne x3, x15, 2064} {\tt pc $\leftarrow$ (rs1!=rs2) ? pc+sx(imm[12:1]<<1) : pc+4} {00000000111100011001100011100011} \TDrawInsnTypeBPicture {Branch Less Than} {blt rs1, rs2, imm} {blt x3, x15, 2064} {\tt pc $\leftarrow$ (rs1=rs2) ? pc+sx(imm[12:1]<<1) : pc+4} {00000000111100011101100011100011} \TDrawInsnTypeBPicture {Branch Less Than Unsigned} {bltu rs1, rs2, imm} {bltu x3, x15, 2064} {\tt pc $\leftarrow$ (rs1=rs2) ? pc+sx(imm[12:1]<<1) : pc+4} {00000000111100011111100011100011} \TDrawInsnTypeIPicture {Load Byte} {lb rd, imm(rs1)} {lb x7, 4(x3)} {\tt% rd $\leftarrow$ sx(m8(rs1+sx(imm)))\\ pc $\leftarrow$ pc+4} {00000000010000011000001110000011} \TDrawInsnTypeIPicture {Load Halfword} {lh rd, imm(rs1)} {lh x7, 4(x3)} {\tt% rd $\leftarrow$ sx(m16(rs1+sx(imm)))\\ pc $\leftarrow$ pc+4} {00000000010000011001001110000011} \TDrawInsnTypeIPicture {Load Word} {lw rd, imm(rs1)} {lw x7, 4(x3)} {\tt% rd $\leftarrow$ sx(m32(rs1+sx(imm)))\\ pc $\leftarrow$ pc+4} {00000000010000011010001110000011} \TDrawInsnTypeIPicture {Load Byte Unsigned} {lbu rd, imm(rs1)} {lbu x7, 4(x3)} {\tt% rd $\leftarrow$ zx(m8(rs1+sx(imm)))\\ pc $\leftarrow$ pc+4} {00000000010000011100001110000011} \TDrawInsnTypeIPicture {Load Halfword Unsigned} {lhu rd, imm(rs1)} {lhu x7, 4(x3)} {\tt% rd $\leftarrow$ zx(m16(rs1+sx(imm)))\\ pc $\leftarrow$ pc+4} {00000000010000011101001110000011} \TDrawInsnTypeSPicture {Store Byte} {sb rs2, imm(rs1)} {sb x3, 19(x15)} {\tt% m8(rs1+sx(imm)) $\leftarrow$ rs2[7:0]\\ pc $\leftarrow$ pc+4} {00000000111100011000100110100011} \TDrawInsnTypeSPicture {Store Halfword} {sh rs2, imm(rs1)} {sh x3, 19(x15)} {\tt% m16(rs1+sx(imm)) $\leftarrow$ rs2[15:0]\\ pc $\leftarrow$ pc+4} {00000000111100011001100110100011} \TDrawInsnTypeSPicture {Store Word} {sw rs2, imm(rs1)} {sw x3, 19(x15)} {\tt% m16(rs1+sx(imm)) $\leftarrow$ rs2[31:0]\\ pc $\leftarrow$ pc+4} {00000000111100011010100110100011} \TDrawInsnTypeIPicture {Add Immediate} {addi rd, rs1, imm} {addi x1, x7, 4} {\tt% rd $\leftarrow$ rs1+sx(imm)\\ pc $\leftarrow$ pc+4} {00000000010000111000000010010011} \TDrawInsnTypeIPicture {Set Less Than Immediate} {slti rd, rs1, imm} {slti x1, x7, 4} {\tt% rd $\leftarrow$ (rs1 < sx(imm)) ? 1 : 0\\ pc $\leftarrow$ pc+4} {00000000010000111010000010010011} \TDrawInsnTypeIPicture {Set Less Than Immediate Unsigned} {sltiu rd, rs1, imm} {sltiu x1, x7, 4} {\tt% rd $\leftarrow$ (rs1 < sx(imm)) ? 1 : 0\\ pc $\leftarrow$ pc+4} {00000000010000111011000010010011} \TDrawInsnTypeIPicture {Exclusive Or Immediate} {xori rd, rs1, imm} {xori x1, x7, 4} {\tt% rd $\leftarrow$ rs1 \^{} sx(imm)\\ pc $\leftarrow$ pc+4} {00000000010000111100000010010011} \TDrawInsnTypeIPicture {Or Immediate} {ori rd, rs1, imm} {ori x1, x7, 4} {\tt% rd $\leftarrow$ rs1 | sx(imm)\\ pc $\leftarrow$ pc+4} {00000000010000111110000010010011} \TDrawInsnTypeIPicture {And Immediate} {andi rd, rs1, imm} {andi x1, x7, 4} {\tt% rd $\leftarrow$ rs1 \& sx(imm)\\ pc $\leftarrow$ pc+4} {00000000010000111111000010010011} \TDrawInsnTypeRShiftPicture {Shift Left Logical Immediate} {slli rd, rs1, shamt} {slli x7, x3, 2} {\tt% rd $\leftarrow$ rs1 << shamt\\ pc $\leftarrow$ pc+4} {00000000001000011001001110100011} \TDrawInsnTypeRShiftPicture {Shift Right Logical Immediate} {srli rd, rs1, shamt} {srli x7, x3, 2} {\tt% rd $\leftarrow$ rs1 >> shamt\\ pc $\leftarrow$ pc+4} {00000000001000011101001110010011} \TDrawInsnTypeRShiftPicture {Shift Right Arithmetic Immediate} {srai rd, rs1, shamt} {srai x7, x3, 2} {\tt% rd $\leftarrow$ rs1 >> shamt\\ pc $\leftarrow$ pc+4} {01000000001000011101001110010011} \TDrawInsnTypeRPicture {Add} {add rd, rs1, rs2} {add x7, x3, x31} {\tt% rd $\leftarrow$ rs1 + rs2\\ pc $\leftarrow$ pc+4} {00000001111100011000001110110011} \TDrawInsnTypeRPicture {Subtract} {sub rd, rs1, rs2} {SUB x7, x3, x31} {\tt% rd $\leftarrow$ rs1 - rs2\\ pc $\leftarrow$ pc+4} {01000001111100011000001110110011} \TDrawInsnTypeRPicture {Shift Left Logical} {sll rd, rs1, rs2} {sll x7, x3, x31} {\tt% rd $\leftarrow$ rs1 << rs2\\ pc $\leftarrow$ pc+4} {00000001111100011001001110110011} \TDrawInsnTypeRPicture {Set Less Than} {slt rd, rs1, rs2} {slt x7, x3, x31} {\tt% rd $\leftarrow$ rs1 < rs2) ? 1 : 0\\ pc $\leftarrow$ pc+4} {00000001111100011010001110110011} \TDrawInsnTypeRPicture {Set Less Than Unsigned} {sltu rd, rs1, rs2} {sltu x7, x3, x31} {\tt% rd $\leftarrow$ (rs1 < rs2) ? 1 : 0\\ pc $\leftarrow$ pc+4} {00000001111100011011001110110011} \TDrawInsnTypeRPicture {Exclusive Or} {xor rd, rs1, rs2} {xor x7, x3, x31} {\tt% rd $\leftarrow$ rs1 \^{} rs2\\ pc $\leftarrow$ pc+4} {00000001111100011100001110110011} \TDrawInsnTypeRPicture {Shift Right Logical} {srl rd, rs1, rs2} {srl x7, x3, x31} {\tt% rd $\leftarrow$ rs1 >> rs2\\ pc $\leftarrow$ pc+4} {00000001111100011101001110110011} \TDrawInsnTypeRPicture {Shift Right Arithmetic} {sra rd, rs1, rs2} {sra x7, x3, x31} {\tt% rd $\leftarrow$ rs1 >> rs2\\ pc $\leftarrow$ pc+4} {01000001111100011101001110110011} \TDrawInsnTypeRPicture {Or} {or rd, rs1, rs2} {or x7, x3, x31} {\tt% rd $\leftarrow$ rs1 | rs2\\ pc $\leftarrow$ pc+4} {00000001111100011101001110110011} \TDrawInsnTypeRPicture {And} {and rd, rs1, rs2} {and x7, x3, x31} {\tt% rd $\leftarrow$ rs1 \& rs2\\ pc $\leftarrow$ pc+4} {00000001111100011110001110110011} %\DrawInsnTypeFPicture{FENCE iorw, iorw}{00001111111100000000000000001111} %\DrawInsnTypeFPicture{FENCE.I}{00000000000000000001000000001111} %\DrawInsnTypeEPicture{ECALL}{00000000000000000000000001110011} %\DrawInsnTypeEPicture{EBREAK}{00000000000100000000000001110011} %\DrawInsnTypeCSPicture{CSRRW x3, 2, x15}{00000000001001111001000111110011} %\DrawInsnTypeCSPicture{CSRRS x3, 2, x15}{00000000001001111010000111110011} %\DrawInsnTypeCSPicture{CSRRC x3, 2, x15}{00000000001001111011000111110011} %\DrawInsnTypeCSIPicture{CSRRWI x3, 2, 7}{00000000001000111101000111110011} %\DrawInsnTypeCSIPicture{CSRRSI x3, 2, 7}{00000000001000111110000111110011} %\DrawInsnTypeCSIPicture{CSRRCI x3, 2, 7}{00000000001000111111000111110011} %\DrawInsnTypeRPicture{MUL x7, x3, x31}{00000011111100111000001110110011} %\DrawInsnTypeRPicture{MULH x7, x3, x31}{00000011111100111001001110110011} %\DrawInsnTypeRPicture{MULHS x7, x3, x31}{00000011111100111010001110110011} %\DrawInsnTypeRPicture{MULHU x7, x3, x31}{00000011111100111011001110110011} %\DrawInsnTypeRPicture{DIV x7, x3, x31}{00000011111100111100001110110011} %\DrawInsnTypeRPicture{DIVU x7, x3, x31}{00000011111100111101001110110011} %\DrawInsnTypeRPicture{REM x7, x3, x31}{00000011111100111110001110110011} %\DrawInsnTypeRPicture{REMU x7, x3, x31}{00000011111100111111001110110011} ================================================ FILE: book/install/chapter.tex ================================================ \chapter{Installing a RISC-V Toolchain} \label{chapter:install} All of the software presented in this text was assembled/compiled using the GNU toolchain and executed using the rvddt simulator on a Linux (Ubuntu 20.04 LTS) operating system. The installation instructions provided here were last tested on on March 5, 2021. It is expected that these tools will evolve over time. See the respective documentation web sites for the latest news and options for installing them. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \section{The GNU Toolchain} \enote{It would be good to find some Mac and Windows users to write and test proper variations on this section to address those systems. Pull requests, welcome!}% In order to install custom code in a location that will not cause interference with other applications (and allow for easy hacking and cleanup), these will install the toolchain under a private directory: \verb@~/projects/riscv/install@. At any time you can remove everything and start over by executing the following command: \begin{tty} rm -rf ~/projects/riscv/install \end{tty} \begin{tcolorbox} Be {\em very} careful how you type the above \verb@rm@ command. If typed incorrectly, it could irreversibly remove many of your files! \end{tcolorbox} Before building the toolchain, a number of utilities must be present on your system. The following will install those that are needed: \begin{minipage}{\textwidth} \begin{tty} sudo apt install autoconf automake autotools-dev curl python3 python-dev libmpc-dev \ libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf \ libtool patchutils bc zlib1g-dev libexpat-dev \end{tty} \end{minipage} Note that the above \verb@apt@ command is the only operation that should be performed as root. All other commands should be executed as a regular user. This will eliminate the possibility of clobbering system files that should not be touched when tinkering with the toolchain applications. \enote{Discuss the choice of ilp32 as well as what the other variations would do.}% To download, compile and install the toolchain: \begin{minipage}{\textwidth} \begin{tty} mkdir -p ~/projects/riscv cd ~/projects/riscv git clone https://github.com/riscv/riscv-gnu-toolchain cd riscv-gnu-toolchain INS_DIR=~/projects/riscv/install/rv32i ./configure --prefix=$INS_DIR \ --with-multilib-generator="rv32i-ilp32--;rv32imafd-ilp32--;rv32ima-ilp32--" make \end{tty} \end{minipage} After building the toolchain, make it available by putting it into your PATH by adding the following to the end of your \verb@.bashrc@ file: \begin{tty} export PATH=$PATH:$INS_DIR \end{tty} For this \verb@PATH@ change to take place, start a new terminal or paste the same \verb@export@ command into your existing terminal. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \section{rvddt} Download and install the rvddt simulator by executing the following commands. Building the rvddt example programs will verify that the GNU toolchain has been built and installed properly. \begin{minipage}{\textwidth} %git clone git@github.com:johnwinans/rvddt.git \begin{tty} cd ~/projects/riscv git clone https://github.com/johnwinans/rvddt.git cd rvddt/src make world cd ../examples make world \end{tty} \end{minipage} After building rvddt, make it available by putting it into your PATH by adding the following to the end of your \verb@.bashrc@ file: \begin{tty} export PATH=$PATH:~/projects/riscv/rvddt/src \end{tty} For this \verb@PATH@ change to take place, start a new terminal or paste the same \verb@export@ command into your existing terminal. Test the rvddt build by executing one of the examples: \begin{minipage}{\textwidth} \begin{tty} winans@ux410:~/projects/riscv/rvddt/examples$ rvddt -f counter/counter.bin sp initialized to top of memory: 0x0000fff0 Loading 'counter/counter.bin' to 0x0 This is rvddt. Enter ? for help. ddt> ti 0 1000 00000000: 00300293 addi x5, x0, 3 # x5 = 0x00000003 = 0x00000000 + 0x00000003 00000004: 00000313 addi x6, x0, 0 # x6 = 0x00000000 = 0x00000000 + 0x00000000 00000008: 00130313 addi x6, x6, 1 # x6 = 0x00000001 = 0x00000000 + 0x00000001 0000000c: fe534ee3 blt x6, x5, -4 # pc = (0x1 < 0x3) ? 0x8 : 0x10 00000008: 00130313 addi x6, x6, 1 # x6 = 0x00000002 = 0x00000001 + 0x00000001 0000000c: fe534ee3 blt x6, x5, -4 # pc = (0x2 < 0x3) ? 0x8 : 0x10 00000008: 00130313 addi x6, x6, 1 # x6 = 0x00000003 = 0x00000002 + 0x00000001 0000000c: fe534ee3 blt x6, x5, -4 # pc = (0x3 < 0x3) ? 0x8 : 0x10 00000010: ebreak ddt> x winans@ux410:~/projects/riscv/rvddt/examples$ \end{tty} \end{minipage} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \section{qemu} You can download and install the RV32 qemu simulator by executing the following commands. At the time of this writing (2021-06) I use release v5.0.0. Release v5.2.0 has issues that confuse GDB when printing the registers and v6.0.0 has different CPU types that I have had trouble with when executing privileged instructions. \begin{minipage}{\textwidth} \begin{tty} INS_DIR=~/projects/riscv/install/rv32i cd ~/projects/riscv git clone git@github.com:qemu/qemu.git cd qemu git checkout v5.0.0 ./configure --target-list=riscv32-softmmu --prefix=${INS_DIR} make -j4 make install \end{tty} \end{minipage} ================================================ FILE: book/intro/chapter.tex ================================================ \chapter{Introduction} \label{chapter:Introduction} At its core, a digital computer has at least one \acrfull{cpu}. A CPU executes a continuous stream of instructions called a \gls{program}. These program instructions are expressed in what is called \gls{MachineLanguage}. Each machine language instruction is a \gls{binary} value. In order to provide a method to simplify the management of machine language programs a symbolic mapping is provided where a \gls{mnemonic} can be used to specify each machine instruction and any of its parameters\ldots\ rather than require that programs be expressed as a series of binary values. A set of mnemonics, parameters and rules for specifying their use for the purpose of programming a CPU is called an {\em Assembly Language}. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \section{The Digital Computer} There are different types of computers. A {\em digital} computer is the type that most people think of when they hear the word {\em computer}. Other varieties of computers include {\em analog} and {\em quantum}. A digital computer is one that processes data represented using numeric values (digits), most commonly expressed in binary (ones and zeros) form. This text focuses on digital computing. A typical digital computer is composed of storage systems (memory, disc drives, USB drives, etc.), a CPU (with one or more cores), input peripherals (a keyboard and mouse) and output peripherals (display, printer or speakers.) \subsection{Storage Systems} Computer storage systems are used to hold the data and instructions for the CPU. Types of computer storage can be classified into two categories: {\em volatile} and {\em non-volatile}. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsubsection{Volatile Storage} \label{VolatileStorage} Volatile storage is characterized by the fact that it will lose its contents (forget) any time that it is powered off. \index{register} One type of volatile storage is provided inside the CPU itself in small blocks called \glspl{register}. These registers are used to hold individual data values that can be manipulated by the instructions that are executed by the CPU. Another type of volatile storage is {\em main memory} (sometimes called \acrshort{ram}) Main memory is connected to a computer's CPU and is used to hold the data and instructions that can not fit into the CPU registers. Typically, a CPU's registers can hold tens of data values while the main memory can contain many billions of data values. To keep track of the data values, each register is assigned a number and the main memory is broken up into small blocks called \gls{byte}s that each assigned a number called an \gls{address} (an {\em address} is often referred to as a {\em location.} A CPU can process data in a register at a speed that can be an order of magnitude faster than the rate that it can process (specifically, transfer data and instructions to and from) the main memory. Register storage costs an order of magnitude more to manufacture than main memory. While it is desirable to have many registers, the economics dictate that the vast majority of volatile computer storage be provided in its main memory. As a result, optimizing the copying of data between the registers and main memory is a desirable trait of good programs. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsubsection{Non-Volatile Storage} Non-volatile storage is characterized by the fact that it will {\em NOT} lose its contents when it is powered off. Common types of non-volatile storage are disc drives, \acrshort{rom} flash cards and USB drives. Prices can vary widely depending on size and transfer speeds. It is typical for a computer system's non-volatile storage to operate more slowly than its main memory. This text will focus on volatile storage. %is not particularly concerned with non-volatile storage. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{CPU} \index{CPU} \enote{Add a block diagram of the CPU components described here.} The \acrshort{cpu} is a collection of registers and circuitry designed to manipulate the register data and to exchange data and instructions with the main memory. The instructions that are read from the main memory tell the CPU to perform various mathematical and logical operations on the data in its registers and where to save the results of those operations. \subsubsection{Execution Unit} The part of a CPU that coordinates all aspects of the operations of each instruction is called the {\em execution unit.} It is what performs the transfers of instructions and data between the CPU and the main memory and tells the registers when they are supposed to either store or recall data being transferred. The execution unit also controls the ALU (Arithmetic and Logic Unit). \subsubsection{Arithmetic and Logic Unit} \index{ALU} When an instruction manipulates data by performing things like an {\em addition}, {\em subtraction}, {\em comparison} or other similar operations , the ALU is what will calculate the sum, difference, and so on\ldots\ under the control of the execution unit. \subsubsection{Registers} \index{register} In the RV32 CPU there are 31 general purpose registers that each contain 32 \gls{bit}s (where each bit is one \gls{binary} digit value of one or zero) and a number of special-purpose registers. Each of the general purpose registers is given a name such as \reg{x1}, \reg{x2}, \ldots\ on up to \reg{x31} ({\em general purpose} refers to the fact that the {\em CPU itself} does not prescribe any particular function to any of these registers.) Two important special-purpose registers are \reg{x0} and \reg{pc}. Register \reg{x0} will always represent the value zero or logical {\em false} no matter what. If any instruction tries to change the value in \reg{x0} the operation will fail. The need for {\em zero} is so common that, other than the fact that it is hard-wired to zero, the \reg{x0} register is made available as if it were otherwise a general purpose register.% \footnote{Having a special {\em zero} register allows the total set of instructions that the CPU can execute to be simplified. Thus reducing its complexity, power consumption and cost.} The \reg{pc} register is called the {\em program counter}. The CPU uses it to remember the memory address where its program instructions are located. The term XLEN refer to the width of an integer register in bits (either 32, 64, or 128.) The number of bits in each register is defined by the \acrfull{isa}. \subsubsection{Harts} \index{hart} Analogous to a {\em core} in other types of CPUs, a {\em \acrshort{hart}} (hardware \gls{thread}) in a RISC-V CPU refers to the collection of 32 registers, instruction execution unit and ALU.\cite[p.~20]{rvismv1v22:2017} When more than one hart is present in a CPU, a different stream of instructions can be executed on each hart all at the same time. Programs that are written to take advantage of this are called {\em multithreaded}. This text will primarily focus on CPUs that have only one hart. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{Peripherals} A {\em peripheral} is a device that is not a CPU or main memory. They are typically used to transfer information/data into and out of the main memory. This text is not concerned with the peripherals of a computer system other than in sections where instructions are discussed with the purpose of addressing the needs of a peripheral device. Such instructions are used to initiate, execute and/or synchronize data transfers. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \section{Instruction Set Architecture} \index{ISA} The catalog of rules that describes the details of the instructions and features that a given CPU provides is called an \acrfull{isa}. An ISA is typically expressed in terms of the specific meaning of each binary instruction that a CPU can recognize and how it will process each one. The RISC-V ISA is defined as a set of modules. The purpose of dividing the ISA into modules is to allow an implementer to select which features to incorporate into a CPU design.\cite[p.~4]{rvismv1v22:2017} Any given RISC-V implementation must provide one of the {\em base} modules and zero or more of the {\em extension} modules.\cite[p.~4]{rvismv1v22:2017} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{RV Base Modules} \index{RV32I} The base modules are RV32I (32-bit general purpose), RV32E (32-bit embedded), RV64I (64-bit general purpose) and RV128I (128-bit general purpose).\cite[p.~4]{rvismv1v22:2017} These base modules provide the minimal functional set of integer operations needed to execute a useful application. The differing bit-widths address the needs of different main-memory sizes. This text primarily focuses on the RV32I base module and how to program it. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{Extension Modules} RISC-V extension modules may be included by an implementer interested in optimizing a design for one or more purposes.\cite[p.~4]{rvismv1v22:2017} \index{RV32M}% \index{RV32A}% \index{RV32F}% \index{RV32D}% \index{RV32Q}% \index{RV32C}% Available extension modules include M (integer math), A (atomic), F (32-bit floating point), D (64-bit floating point), Q (128-bit floating point), C (compressed size instructions) and others. \index{RV32G}% The extension name {\em G} is used to represent the combined set of IMAFD extensions as it is expected to be a common combination. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \section{How the CPU Executes a Program} The process of executing a program is continuous repeats of a series of \index{instruction cycle}{\em instruction cycles} that are each comprised of a {\em fetch}, {\em decode} and {\em execute} phase. The current status of a CPU hart is entirely embodied in the data values that are stored in its registers at any moment in time. Of particular interest to an executing program is the \reg{pc} register. The \reg{pc} contains the memory address containing the instruction that the CPU is currently executing.\footnote{In the RISC-V ISA the \reg{pc} register points to the {\em current} instruction where in most other designs, the \reg{pc} register points to the {\em next} instruction.} For this to work, the instructions to be executed must have been previously stored in adjacent main memory locations and the address of the first instruction placed into the \reg{pc} register. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{Instruction Fetch} \index{instruction fetch} In order to {\em fetch} an instruction from the main memory the CPU will update the address in the \reg{pc} register and then request that the main memory return the value of the data stored at that address. \footnote{RV32I instructions are more than one byte in size, but this general description is suitable for now.} %must have a method to identify which instruction should be fetched and %a method to fetch it. %Given that the main memory is broken up and that each of its bytes is %assigned an address, the \reg{pc} is used to hold the address of the %location where the next instruction to execute is located. %Given an instruction address, the CPU can request that the main memory %locate and return the value of the data stored there using what is called %a {\em memory read} operation and then the CPU can treat that {\em fetched} %value as an instruction and execute it. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{Instruction Decode} \index{instruction decode} Once an instruction has been fetched, it must be inspected to determine what operation(s) are to be performed. This means inspecting the portions of the instruction that dictate which registers are involved and what that, if anything, ALU should do. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{Instruction Execute} \index{instruction execute} Typical instructions do things like add a number to the value currently stored in one of the registers or store the contents of a register into the main memory at some given address. Part of every instruction is a notion of what should be done next. Most of the time an instruction will complete by indicating that the CPU should proceed to fetch and execute the instruction at the next larger main memory address. In these cases the \reg{pc} is incremented to point to the memory address after the current instruction. Any parameters that an instruction requires must either be part of the instruction itself or read from (or stored into) one or more of the general purpose registers. Some instructions can specify that the CPU proceed to execute an instruction at an address other than the one that follows itself. This class of instructions have names like {\em jump} and {\em branch} and are available in a variety of different styles. The RISC-V ISA uses the word {\em jump} to refer to an {\em unconditional} change in the sequential processing of instructions and the word {\em branch} to refer to a {\em conditional} change. Conditional branch instructions can be used to tell the CPU to do things like: \begin{quote} If the value in x8 is currently less than the value in x24 then proceed to the instruction at the next main memory address, otherwise branch to an instruction at a different address. \end{quote} This type of instruction can therefore result in one of two different actions pending the result of the comparison.\footnote{This is the fundamental method used by a CPU to make decisions.} Once the instruction execution phase has completed, the next instruction cycle will be performed using the new value in the \reg{pc} register. ================================================ FILE: book/license/chapter.tex ================================================ \chapter{Attribution 4.0 International} \label{license} \begin{scriptsize} Creative Commons Corporation ("Creative Commons") is not a law firm and does not provide legal services or legal advice. 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Creative Commons may be contacted at \url{http://creativecommons.org}. \end{scriptsize} ================================================ FILE: book/preamble.tex ================================================ \oddsidemargin=.82in %\evensidemargin=1.82in \evensidemargin=1.72in %\topmargin=-.5in \headheight=12pt \headsep=20pt %\hoffset=-1.2in % for 8.5x11 \hoffset=-1.1in % for 8.5x11 %\voffset=-1.15in % for 8.5x11 \voffset=-.8in % for 8.5x11 %\textheight=9.75in % for 8.5x11 \textheight=9in % for 8.5x11 %\textheight=8.75in % for 8.5x11 \textwidth=6.1in % for 8.5x11 %\textwidth=6.25in % for 8.5x11 \marginparsep=7pt %\marginparwidth=71pt %\marginparwidth=1.25in %\marginparwidth=1.5in \marginparwidth=1.25in \footskip=36pt \marginparpush=5pt \usepackage{ifthen} \usepackage{stringstrings} % so can count characters in a string \usepackage{xstring} % so can count characters in a string \usepackage[pass]{geometry} \usepackage{color} % Necessary for colored links % load makeidx BEFORE hyperref to make the index clickable % load makeidx AFTER hyperref if want to use showidx \usepackage{makeidx} \usepackage[pagebackref]{hyperref} \hypersetup{ colorlinks=true, %set true if you want colored links linkcolor=blue %choose some color if you want links to stand out } \usepackage{scrextend} % so can use \footref % don't say subsection and subsubsection in auto-references \let\subsectionautorefname\sectionautorefname \let\subsubsectionautorefname\sectionautorefname %\usepackage{makeidx,showidx} % showidx breaks hyperref when loaded before hyperref %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % for one-sided on left margin \usepackage{lineno} \linenumbers \setlength\linenumbersep{.8cm} % for two-sided on inside margin %\usepackage[switch*,pagewise]{lineno} %\linenumbers %\runningpagewiselinenumbers %\renewcommand\linenumberfont{\normalfont\tiny\sffamily\bfseries\color{violet}} % lineno is screwy for displayed equations %\let\oldequation\equation %\let\oldendequation\endequation %\renewenvironment{equation} % {\linenomathNonumbers\oldequation} % {\oldendequation\endlinenomath} % %\setlength\linenumbersep{6mm} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %\usepackage{url} \usepackage{lastpage} \usepackage{fancyhdr} \usepackage{amsmath} \numberwithin{equation}{section} \usepackage{amsfonts} % I hear these are also good to load \usepackage{amssymb} % I hear these are also good to load %\usepackage{picture} %\usepackage{epstopdf} %\usepackage{graphicx} \usepackage{epsfig} \usepackage{tikz-timing} \usepackage{tikz} %\usepackage{timing} \usepackage{float} \usepackage{fancyvrb} %\usepackage{caption} \usepackage[hypcap=true]{caption} % point to top of figure rather than caption in \hyperref \usepackage{placeins} \usepackage{listings} \usepackage[toc]{glossaries} %\renewcommand*{\glsclearpage}{} \usepackage{pifont} \usepackage{layout} \usepackage{xcolor} \usepackage{textcomp} % for the trademark symbol %\usepackage[obeyspaces]{url} \usepackage{fink} % deprecated in favor of currfile %\usepackage{currfile} % dut... doesn't emit the local include path properly \usepackage{MyFigs} \def\code#1{\url{#1}} % The exercise environment \usepackage{exercise} \renewcommand{\ExerciseHeader}{% \textbf{\large\ExerciseHeaderDifficulty\ExerciseName\ % \ExerciseHeaderNB\ExerciseHeaderTitle\ExerciseHeaderOrigin}\medskip} \renewcommand{\ExePartHeader}{% \medskip\emph{\large\ExePartHeaderDifficulty\ExePartName % \ExePartHeaderNB \ExePartHeaderTitle\\ }} %\renewcommand{\ExePartHeader}{% %\medskip\emph{\large\ExePartHeaderDifficulty Part \ExePartHeaderNB % %\quad \ExePartName\ExePartHeaderTitle}} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %\DefineVerbatimEnvironment% %{Code}{Verbatim} %{frame=single,numbers=left,numbersep=2mm,framesep=3mm} %%%,numbersep=2mm,frame=lines,framerule=0.8mm,framesep=5mm %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % [1] = filename to include % [2] = title of the code sample % A label will be generated as: Code:#1 %\newcommand{\xxxx}[2]{% % \label{Code:#1} % % \VerbatimInput[frame=single,numbers=left,numbersep=2mm,framesep=3mm,label={#2}]{#1}} %\newcommand{\theListingFontFamily}{\ttfamily\small} \newcommand{\theListingFontFamily}{\ttfamily\footnotesize} %\newcommand{\theListingFontFamily}{\ttfamily\scriptsize} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % [1] = place for additional listing parameters, default: language=C % [2] = filepath % [3] = Description of the listing %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \newcommand{\listing}[3][language=C]{% \lstinputlisting[ % numbers=left,numberstyle=\tiny,stepnumber=1,numbersep=8pt, % breaklines=true, % frame=single % showtabs=false, % basicstyle=\theListingFontFamily, % showstringspaces=false, % tabsize=4, % showlines=true, % show all blank lines #1, % captionpos=t,frame=tblr,label={lst:\detokenize{#2}},caption={{\tt \detokenize{#2}}\\\hspace{\textwidth}{\small #3}}]{\detokenize{#2}}} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \newcommand{\listingRef}[1]{\autoref{lst:\detokenize{#1}}} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \lstnewenvironment{tty} {\lstset{language=sh, % numbers=left,numberstyle=\tiny,stepnumber=1,numbersep=8pt, % breaklines=true, % frame=single, % showtabs=false, % basicstyle=\theListingFontFamily, % showstringspaces=false, % tabsize=4, % showlines=true, % show all blank lines basicstyle=\theListingFontFamily}} {} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % A footer that shall appear on every page %\newcommand{\MyFoot}{{\sf\scriptsize Copyright \copyright\ 2014, 2015 John Winans. All Rights Reserved}\\ %\vspace{.05in} %\scriptsize\FooterText} \newcommand{\MyFoot}{\scriptsize\FooterText} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \pagestyle{fancy} % supress normal headings and footers \fancyhf{} % heading and footing rules \renewcommand{\headrulewidth}{1pt} \renewcommand{\footrulewidth}{1pt} %\def\DiscardOneCharacter#1{} % Sub-footer that shows the version control version string in the lfoot defined above \ifdefined\GitFileName % \newcommand{\FooterText}{\tt \GitFileName \currfilename\\ \newcommand{\FooterText}{\tt \GitFileName \finkpath\\ \GitDescription} \else \newcommand{\FooterText}{\emph{--UNKNOWN--}} \fi %\lhead{\leftmark} %\rhead{\rightmark} \fancyhead[LE]{\leftmark} \fancyhead[RO]{\rightmark} \newcommand{\PageNumber}{Page \thepage\ of \pageref*{LastPage}} %\rfoot{Page \thepage\ of \pageref{LastPage}} %\lfoot{\MyFoot} \fancyfoot[LE,RO]{\PageNumber} \fancyfoot[RE,LO]{\MyFoot} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % override the plain page style so the first page of a % chapter still has a footer on it (but no header). \fancypagestyle{plain}{% \renewcommand{\headrulewidth}{0pt} % \fancyhf{} % clear all header and footer fields \fancyfoot[LE,RO]{\PageNumber} \fancyfoot[RE,LO]{\MyFoot} %\lfoot{\MyFoot} % %\rfoot{Page \thepage\ of \pageref*{LastPage}} } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \setlength{\parindent}{0pt} \setlength{\parskip}{.51em} % How deep should we enumerate the section/subsection/subsubsections % 3=all the way \setcounter{secnumdepth}{3} % How many section-levels to show in the TOC. % 4=all of them %\setcounter{tocdepth}{4} \setcounter{tocdepth}{1} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % Presentation styles for things like names links and % window objects in figures. % how should we present a window name \newcommand{\windowname}[1]{{\em #1}} % How should we present the name of an object in a figure % that can be interacted with. \newcommand{\linkname}[1]{{\bf #1}} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % fix some annoying things \newcommand{\tm}{\textsuperscript{TM}} \newcommand{\rtm}{\textsuperscript{\textregistered}} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % A command to make a colored background box whilst in math mode: \newcommand{\MathHilight}[1]{\colorbox{yellow}{\ensuremath{#1}}} \usepackage{tcolorbox} %\tcbset{colback=blue!20!white} \tcbset{colback=green!20!white} ================================================ FILE: book/preface/chapter.tex ================================================ \chapter{Preface} \label{chapter:Preface} I set out to write this book because I couldn't find it in a single volume elsewhere. The closest published work on this topic appear to be select portions of {\em The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Document Version 2.2}\cite{rvismv1v22:2017}, {The RISC-V Reader}\cite{riscvreader:2017}, and {Computer Organization and Design RISC-V Edition: The Hardware Software Interface}\cite{codriscv:2017}. There {\em are} some terse guides on the Internet that are suitable for those who already know an assembly language. With all the (deserved) excitement brewing over system organization (and the need to compress the time out of university courses targeting assembly language programming~\cite{Decker:1985:MAT:989369.989375}), it is no surprise that RISC-V texts for the beginning assembly programmer are not (yet) available. When I started in computing, I learned how to count in binary in a high school electronics course using data sheets for integrated circuits such as the 74191\cite{ttl74191:1979} and 74154\cite{ttl74154:1979} prior to knowing that assembly language even existed. I learned assembly language from data sheets and texts, that are still sitting on my shelves today, such as: \begin{itemize} \item Z80 Assembly Language Programming Manual\cite{zilog:1977} \item Z80 Assembly Language Programming\cite{leventhal:1979} \item The MCS-85 User's Manual\cite{mcs85:1978} \item The EDTASM Manual\cite{edtasm:1978} \item The MC68000 User's Manual\cite{mc68000:1980} \item Assembler Language With ASSIST\cite{assist:1983} \item IBM System/370 Principals of Operation\cite{poo:1980} \item OS/VS-DOS/VSE-VM/370 Assembler Language\cite{assembler370:1979} %\item The Series 32000 Databook\cite{ns32k:1986} \item \ldots\ and several others \end{itemize} All of these manuals discuss each CPU instruction in excruciating detail with both a logical and narrative description. For RISC-V this is also the case for the {\em RISC-V Reader}\cite{riscvreader:2017} and the {\em Computer Organization and Design RISC-V Edition}\cite{codriscv:2017} books and is also present in this text (I consider that to be the minimal level of responsibility.) Where I hope this text will differentiate itself from the existing RISC-V titles is in its attempt to address the needs of those learning assembly language for the first time. To this end I have primed this project with some of the curriculum material I created when teaching assembly language programming in the late '80s. ================================================ FILE: book/priv/chapter.tex ================================================ \chapter{Privileged Instructions} \label{chapter:privileged} \section{Introduction} {\em XXX NOTE: This is a first draft of what is being detailed in the previous chapter} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{CSRRW rd, csr, rs1} \index{Instruction!CSRRW} The CSRRW (Atomic Read/Write CSR) instruction atomically swaps values in the CSRs and integer registers. CSRRW reads the old value of the CSR, zero-extends the value to XLEN bits, then writes it to integer register rd. The initial value in rs1 is written to the CSR. If rd=x0, then the instruction shall not read the CSR and shall not cause any of the side-effects that might occur on a CSR read.~\cite[p.~22]{rvismv1v22:2017} \DrawInsnTypeCSPicture{CSRRW x3, 2, x15}{00000000001001111001000111110011} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{CSRRS rd, csr, rs1} \index{Instruction!CSRRS} The CSRRS (Atomic Read and Set Bits in CSR) instruction reads the value of the CSR, zero-extends the value to XLEN bits, and writes it to integer register rd. The initial value in integer register rs1 is treated as a bit mask that specifies bit positions to be set in the CSR. Any bit that is high in rs1 will cause the corresponding bit to be set in the CSR, if that CSR bit is writable. Other bits in the CSR are unaffected (though CSRs might have side effects when written).~\cite[p.~22]{rvismv1v22:2017} If rs1=x0, then the instruction will not write to the CSR at all, and so shall not cause any of the side effects that might otherwise occur on a CSR write, such as raising illegal instruction exceptions on accesses to read-only CSRs. Note that if rs1 specifies a register holding a zero value other than x0, the instruction will still attempt to write the unmodified value back to the CSR and will cause any attendant side effects.~\cite[p.~22]{rvismv1v22:2017} \DrawInsnTypeCSPicture{CSRRS x3, 2, x15}{00000000001001111010000111110011} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{CSRRC rd, csr, rs1} \index{Instruction!CSRRC} The CSRRC (Atomic Read and Clear Bits in CSR) instruction reads the value of the CSR, zero-extends the value to XLEN bits, and writes it to integer register rd. The initial value in integer register rs1 is treated as a bit mask that specifies bit positions to be cleared in the CSR. Any bit that is high in rs1 will cause the corresponding bit to be cleared in the CSR, if that CSR bit is writable. Other bits in the CSR are unaffected.~\cite[p.~22]{rvismv1v22:2017} If rs1=x0, then the instruction will not write to the CSR at all, and so shall not cause any of the side effects that might otherwise occur on a CSR write, such as raising illegal instruction exceptions on accesses to read-only CSRs. Note that if rs1 specifies a register holding a zero value other than x0, the instruction will still attempt to write the unmodified value back to the CSR and will cause any attendant side effects.~\cite[p.~22]{rvismv1v22:2017} \DrawInsnTypeCSPicture{CSRRC x3, 2, x15}{00000000001001111011000111110011} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{CSRRWI rd, csr, imm} \index{Instruction!CSRRWI} This instruction is the same as CSRRW except a 5-bit unsigned (zero-extended) immediate value is used rather than the value from a register. \DrawInsnTypeCSIPicture{CSRRWI x3, 2, 7}{00000000001000111101000111110011} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{CSRRSI rd, csr, rs1} \index{Instruction!CSRRSI} This instruction is the same as CSRRS except a 5-bit unsigned (zero-extended) immediate value is used rather than the value from a register. If the uimm[4:0] field is zero, then this instruction will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on a CSR write. For CSRRWI, if rd=x0, then the instruction shall not read the CSR and shall not cause any of the side-effects that might occur on a CSR read.~\cite[p.~22]{rvismv1v22:2017} \DrawInsnTypeCSIPicture{CSRRSI x3, 2, 7}{00000000001000111110000111110011} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{CSRRCI rd, csr, rs1} \index{Instruction!CSRRCI} This instruction is the same as CSRRC except a 5-bit unsigned (zero-extended) immediate value is used rather than the value from a register. If the uimm[4:0] field is zero, then this instruction will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on a CSR write. For CSRRWI, if rd=x0, then the instruction shall not read the CSR and shall not cause any of the side-effects that might occur on a CSR read.~\cite[p.~22]{rvismv1v22:2017} \DrawInsnTypeCSIPicture{CSRRCI x3, 2, 7}{00000000001000111111000111110011} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \section{RV32M Standard Extension} \index{RV32M} 32-bit integer multiply and divide instructions. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{MUL rd, rs1, rs2} \index{Instruction!MUL} Multiply \reg{rs1} by \reg{rs2} and store the least significant 32-bits of the result in \reg{rd}. \DrawInsnTypeRPicture{MUL x7, x3, x31}{00000011111100111000001110110011} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{MULH rd, rs1, rs2} \index{Instruction!MULH} \DrawInsnTypeRPicture{MULH x7, x3, x31}{00000011111100111001001110110011} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{MULHS rd, rs1, rs2} \index{Instruction!MULHS} \DrawInsnTypeRPicture{MULHS x7, x3, x31}{00000011111100111010001110110011} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{MULHU rd, rs1, rs2} \index{Instruction!MULHU} \DrawInsnTypeRPicture{MULHU x7, x3, x31}{00000011111100111011001110110011} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{DIV rd, rs1, rs2} \index{Instruction!DIV} \DrawInsnTypeRPicture{DIV x7, x3, x31}{00000011111100111100001110110011} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{DIVU rd, rs1, rs2} \index{Instruction!DIVU} \DrawInsnTypeRPicture{DIVU x7, x3, x31}{00000011111100111101001110110011} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{REM rd, rs1, rs2} \index{Instruction!REM} \DrawInsnTypeRPicture{REM x7, x3, x31}{00000011111100111110001110110011} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{REMU rd, rs1, rs2} \index{Instruction!REMU} \DrawInsnTypeRPicture{REMU x7, x3, x31}{00000011111100111111001110110011} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \section{RV32A Standard Extension} \index{RV32A} 32-bit atomic operations. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \section{RV32F Standard Extension} \index{RV32F} 32-bit IEEE floating point instructions. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \section{RV32D Standard Extension} \index{RV32D} 64-bit IEEE floating point instructions. ================================================ FILE: book/programs/chapter.tex ================================================ \chapter{Writing RISC-V Programs} \enote{Introduce the ISA register names and aliases in here?}% This chapter introduces each of the RV32I instructions by developing programs that demonstrate their usefulness. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \section{Use {\tt ebreak} to Stop \rvddt{} Execution} \index{Instruction!ebreak} \label{uguide:ebreak} It is a good idea to learn how to stop before learning how to go! The \insn{ebreak} instruction exists for the sole purpose of transferring control back to a debugging environment.\cite[p.~24]{rvismv1v22:2017} When \rvddt{} executes an \insn{ebreak} instruction, it will immediately terminate any executing {\em trace} or {\em go} command currently executing and return to the command prompt without advancing the \reg{pc} register. The machine language encoding shows that \insn{ebreak} has no operands. \DrawInsnTypeEPicture{ebreak}{00000000000100000000000001110011} \listingRef{ebreak/ebreak.out} demonstrates that since \rvddt{} does not advance the \reg{pc} when it encounters an \insn{ebreak} instruction, subsequent {\em trace} and/or {\em go} commands will re-execute the same \insn{ebreak} and halt the simulation again (and again). This feature is intended to help prevent overzealous users from accidently running past the end of a code fragment.\footnote{This was one of the first {\em enhancements} I needed for myself \tt:-)} \listing{ebreak/ebreak.S}{A one-line \insn{ebreak} program.} \listing{ebreak/ebreak.out}{\insn{ebreak} stopps \rvddt{} without advancing \reg{pc}.} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \section{Using the \insn{addi} Instruction} \index{Instruction!addi} \label{uguide:addi} \enote{Define what constant and immediate values are somewhere.}% The detailed description of how the \insn{addi} instruction is executed is that it: \begin{enumerate} \item Sign-extends the immediate operand. \item Add the sign-extended immediate operand to the contents of the \reg{rs1} register. \item Store the sum in the \reg{rd} register. \item Add four to the \reg{pc} register (point to the next instruction.) \end{enumerate} In the following example \reg{rs1} = \reg{x28}, \reg{rd} = \reg{x29} and the immediate operand is -1. \DrawInsnTypeIPicture{addi x29, x28, -1}{11111111111111100000111010010011} Depending on the values of the fields in this instruction a number of different operations can be performed. The most obvious is that it can add things. But it can also be used to copy registers, set a register to zero and even, when you need to, accomplish nothing. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{No Operation} \index{Instruction!nop} It might seem odd but it is sometimes important to be able to execute an instruction that accomplishes nothing while simply advancing the \reg{pc} to the next instruction. One reason for this is to fill unused memory between two instructions in a program.% \footnote{This can happen during the evolution of one portion of code that reduces in size but has to continue to fit into a system without altering any other code\ldots\ or sometimes you just need to waste a small amount of time in a device driver.} An instruction that accomplishes nothing is called a \insn{nop} (sometimes systems call these \insn{noop}). The name means {\em no operation}. The intent of a \insn{nop} is to execute without having any side effects other than to advance the \reg{pc} register. The \insn{addi} instruction can serve as a \insn{nop} by coding it like this: \DrawInsnTypeIPicture{addi x0, x0, 0}{00000000000000000000000000010011} The result will be to add zero to zero and discard the result (because you can never store a value into the x0 register.) The RISC-V assembler provides a pseudoinstruction specifically for this purpose that you can use to improve the readability of your code. Note that the \insn{addi} and \insn{nop} instructions in \listingRef{nop/nop.S} are assembled into the exact same binary machine instructions as can be seen by comparing it to \verb@objdump@ \listingRef{nop/nop.lst}, and \verb@rvddt@ \listingRef{nop/nop.out} output. %(The \hex{00000013} you can see are stored at addresses \hex{0} and \hex{4}) %as seen by looking at the \verb@objdump@ listing in \listingRef{nop/nop.lst}. %In fact, you can see that objdump shows both instructions as a \insn{nop} %while \listingRef{nop/nop.out} shows that \rvddt{} displays both as %\verb@addi x0, x0, 0@. \listing{nop/nop.S}{Demonstrate that \insn{addi} can be used as a \insn{nop}.} \index{objdump} \listing{nop/nop.lst}{Using \insn{addi} to perform a \insn{nop}} \listing{nop/nop.out}{Using \insn{addi} to perform a \insn{nop}} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{Copying the Contents of One Register to Another} By adding zero to one register and storing the sum in another register the \insn{addi} instruction can be used to copy the value stored in one register to another register. The following instruction will copy the contents of \reg{t4} into \reg{t3}. \DrawInsnTypeIPicture{addi t3, t4, 0}{00000000000011101000111000010011} \index{Instruction!mv} This is a commonly required operation. To make your intent clear you may use the \insn{mv} pseudoinstruction for this purpose. \listingRef{mv/mv.S} shows the source of a program that is dumped in \listingRef{mv/mv.lst} illustrating that the assembler has generated the same machine instruction (\hex{000e8e13} at addresses \hex{0} and \hex{4}) for both of the instructions. \listing{mv/mv.S}{Comparing \insn{addi} to \insn{mv}} \listing{mv/mv.lst}{An objdump of an \insn{addi} and \insn{mv} Instruction.} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{Setting a Register to Zero} Recall that \reg{x0} always contains the value zero. Any register can be set to zero by copying the contents of \reg{x0} using \insn{mv} (aka \insn{addi}).% \footnote{There are other pseudoinstructions (such as \insn{li}) that can also turn into an \insn{addi} instruction. Objdump might display `{\tt addi t3,x0,0}' as `{\tt mv t3,x0}' or `{\tt li t3,0}'.} For example, to set \reg{t3} to zero: \DrawInsnTypeIPicture{addi t3, x0, 0}{00000000000000000000111000010011} \listing{mvzero/mv.S}{Using \insn{mv} (aka \insn{addi}) to zero-out a register.} \listingRef{mvzero/mv.out} traces the execution of the program in \listingRef{mvzero/mv.S} showing how \reg{t3} is changed from \hex{f0f0f0f0} (seen on $\ell 16$) to \hex{00000000} (seen on $\ell 26$.) \listing{mvzero/mv.out}{Setting \reg{t3} to zero.} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{Adding a 12-bit Signed Value} \DrawInsnTypeIPicture{addi x1, x7, 4}{00000000010000111000000010010011} {\small \begin{verbatim} addi t0, zero, 4 # t0 = 4 addi t0, t0, 100 # t0 = 104 addi t0, zero, 0x123 # t0 = 0x123 addi t0, t0, 0xfff # t0 = 0x122 (subtract 1) addi t0, zero, 0xfff # t0 = 0xffffffff (-1) (diagram out the chaining carry) # refer back to the overflow/truncation discussion in binary chapter addi x0, x0, 0 # no operation (pseudo: nop) addi rd, rs, 0 # copy reg rs to rd (pseudo: mv rd, rs) \end{verbatim} } %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \section{todo} Ideas for the order of introducing instructions. \section{Other Instructions With Immediate Operands} \label{uguide:andi} \label{uguide:ori} \label{uguide:xori} \label{uguide:slti} \label{uguide:sltiu} \label{uguide:srai} \label{uguide:slli} \label{uguide:srli} {\small \begin{verbatim} andi ori xori slti sltiu srai slli srli \end{verbatim} } \section{Transferring Data Between Registers and Memory} RV is a load-store architecture. This means that the only way that the CPU can interact with the memory is via the {\em load} and {\em store} instructions. All other data manipulation must be performed on register values. Copying values from memory to a register (first examples using regs set with addi): \label{uguide:lb} \label{uguide:lh} \label{uguide:lw} \label{uguide:lbu} \label{uguide:lhu} {\small \begin{verbatim} lb lh lw lbu lhu \end{verbatim} } Copying values from a register to memory: \label{uguide:sb} \label{uguide:sh} \label{uguide:sw} {\small \begin{verbatim} sb sh sw \end{verbatim} } \section{RR operations} \label{uguide:add} \label{uguide:sub} \label{uguide:and} \label{uguide:or} \label{uguide:sra} \label{uguide:srl} \label{uguide:sll} \label{uguide:xor} \label{uguide:sltu} \label{uguide:slt} {\small \begin{verbatim} add sub and or sra srl sll xor sltu slt \end{verbatim} } \section{Setting registers to large values using lui with addi} \label{uguide:lui} \label{uguide:auipc} {\small \begin{verbatim} addi // useful for values from -2048 to 2047 lui // useful for loading any multiple of 0x1000 Setting a register to any other value must be done using a combo of insns: auipc // Load an address relative the the current PC (see la pseudo) addi lui // Load constant into into bits 31:12 (see li pseudo) addi // add a constant to fill in bits 11:0 if bit 11 is set then need to +1 the lui value to compensate \end{verbatim} } \section{Labels and Branching} Start to introduce addressing here? \label{uguide:beq} \label{uguide:bne} \label{uguide:blt} \label{uguide:bge} \label{uguide:bltu} \label{uguide:bgeu} \label{uguide:bgt} \label{uguide:ble} \label{uguide:bgtu} \label{uguide:beqz} \label{uguide:bnez} \label{uguide:blez} \label{uguide:bgez} \label{uguide:bltz} \label{uguide:bgtz} {\small \begin{verbatim} beq bne blt bge bltu bgeu bgt rs, rt, offset # pseudo for: blt rt, rs, offset (reverse the operands) ble rs, rt, offset # pseudo for: bge rt, rs, offset (reverse the operands) bgtu rs, rt, offset # pseudo for: bltu rt, rs, offset (reverse the operands) bleu rs, rt, offset # pseudo for: bgeu rt, rs, offset (reverse the operands) beqz rs, offset # pseudo for: beq rs, x0, offset bnez rs, offset # pseudo for: bne rs, x0, offset blez rs, offset # pseudo for: bge x0, rs, offset bgez rs, offset # pseudo for: bge rs, x0, offset bltz rs, offset # pseudo for: blt rs, x0, offset bgtz rs, offset # pseudo for: blt x0, rs, offset \end{verbatim} } \section{Jumps} Introduce and present subroutines but not nesting until introduce stack operations. \label{uguide:jal} \label{uguide:jalr} {\small \begin{verbatim} jal jalr \end{verbatim} } \section{Pseudoinstructions} {\small \begin{verbatim} li rd,constant lui rd,(constant + 0x00000800) >> 12 addi rd,rd,(constant & 0x00000fff) la rd,label auipc rd,((label-.) + 0x00000800) >> 12 addi rd,rd,((label-(.-4)) & 0x00000fff) l{b|h|w} rd,label auipc rd,((label-.) + 0x00000800) >> 12 l{b|h|w} rd,((label-(.-4)) & 0x00000fff)(rd) s{b|h|w} rd,label,rt # rt used as a temp reg for the operation (default=x6) auipc rt,((label-.) + 0x00000800) >> 12 s{b|h|w} rd,((label-(.-4)) & 0x00000fff)(rt) call label auipc x1,((label-.) + 0x00000800) >> 12 jalr x1,((label-(.-4)) & 0x00000fff)(x1) tail label,rt # rt used as a temp reg for the operation (default=x6) auipc rt,((label-.) + 0x00000800) >> 12 jalr x0,((label-(.-4)) & 0x00000fff)(rt) mv rd,rs addi rd,rs,0 j label jal x0,label jal label jal x1,label jr rs jalr x0,0(rs) jalr rs jalr x1,0(rs) ret jalr x0,0(x1) \end{verbatim} } \subsection{The {\tt li} Pseudoinstruction} Note that the {\tt li} pseudoinstruction includes an (effectively) conditional addition of 1 to the immediate operand in the {\tt lui} instruction. This is because the immediate operand in the {\tt addi} instruction is sign-extended before it is added to \verb@rd@. If the immediate operand to the {\tt addi} has its most-significant-bit set to 1 then it will have the effect of subtracting 1 from the operand in the \verb@lui@ instruction. Consider the case of putting the value {\tt 0x12345800} into register {\tt x5}: {\small \begin{verbatim} li x5,0x12345800 \end{verbatim} } {\color{red} A naive (incorrect) solution might be: {\small \begin{verbatim} lui x5,0x12345 // x5 = 0x12345000 addi x5,x5,0x800 // x5 = 0x12345000 + sx(0x800) = 0x12345000 + 0xfffff800 = 0x12344800 \end{verbatim} } The result of the above code is that an incorrect value has been placed into x5. } To remedy this problem, the value used in the {\tt lui} instruction can be altered (by adding 1 to its operand) to compensate for the sign-extention in the {\tt addi} instruction: {\small \begin{verbatim} lui x5,0x12346 // x5 = 0x12346000 (note: this is 0x12345800 + 0x0800) addi x5,x5,0x800 // x5 = 0x12346000 + sx(0x800) = 0x12346000 + 0xfffff800 = 0x12345800 \end{verbatim} } Keep in mind that the {\tt li} pseudoinstruction must {\em only} increment the operand of the {\tt lui} instruction when it is known that the operand of the subsequent {\tt addi} instruction will be a negative number. \enote{Add a ribbon diagram of this?}% By adding {\tt 0x00000800} to the immediate operand of the {\tt lui} instruction in this example, a carry-bit into bit-12 will be set to {\tt 1} iff the value in bits 11-0 will be treated as a negative value in the subsequent {\tt addi} instruction. In other words, when bit-11 is set to {\tt 1} in the immediate operand of the {\tt li} pseudoinstruction, the immediate operand of the {\tt lui} instruction will be incremented by {\tt 1}. Consider the case where we wish to put the value {\tt 0x12345700} into register {\tt x5}: {\small \begin{verbatim} lui x5,0x12345 // x5 = 0x12345000 (note that 0x12345700 + 0x0800 = 0x12345f00) addi x5,x5,0x700 // x5 = 0x12345000 + sx(0x700) = 0x12345000 + 0x00000700 = 0x12345700 \end{verbatim} } The sign-extension in this example performed by the {\tt addi} instruction will convert the {\tt 0x700} to {\tt 0x00000700} before the addition. Observe that {\tt 0x12345700+0x0800 = 0x12345f00} and therefore, after shifting to the right, the least significant {\tt 0xf00} is truncated, leaving {\tt 0x12345} as the immediate operand of the {\tt lui} instruction. The addition of {\tt 0x0800} in this example has no effect on the immediate operand of the {\tt lui} instruction because bit-11 in the original value {\tt 0x12345700} is zero. A general algorithm for implementing the {\tt li rd,constant} pseudoinstruction is: {\small \begin{verbatim} lui rd,(constant + 0x00000800) >> 12 addi rd,rd,(constant & 0x00000fff) // the 12-bit immediate is sign extended \end{verbatim} } \enote{Find a proper citation for this.}% Note that on RV64 and RV128 systems, the {\tt lui} places the immediate operand into bits 31-12 and then sign-extends the result to {\tt XLEN} bits. \subsection{The {\tt la} Pseudoinstruction} The \verb@la@ (and others that use \verb@auipc@ such as the \verb@l{b|h|w}@, \verb@s{b|h|w}@, \verb@call@, and \verb@tail@) pseudoinstructions also compensate for a sign-ended negative number when adding a 12-bit immediate operand. The only difference is that these use a \verb@pc@-relative addressing mode. For example, consider the task of putting an address represented by the label \verb@var1@ into register x10: {\small \begin{verbatim} 00010040 la x10,var1 00010048 ... # note that the la pseudoinstruction expands into 8 bytes ... var1: 00010900 .word 999 # a 32-bit integer constant stored in memory at address var1 \end{verbatim} } The \verb@la@ instruction in this example will expand into: {\small \begin{verbatim} 00010040 auipc x10,((var1-.) + 0x00000800) >> 12 00010044 addi x10,x10,((var1-(.-4)) & 0x00000fff) \end{verbatim} } Note that \verb@auipc@ will shift the immediate operand to the left 12 bits and then add that to the \verb@pc@ register (see \autoref{insn:auipc}.) The assembler will calculate the value of \verb@(var1-.)@ by subtracting the address represented by the label \verb@var1@ from the address of the current instruction (which is expressed as '.') resulting in the number of bytes from the current instruction to the target label\ldots{} which is \verb@0x000008c0@. Therefore the expanded pseudoinstruction example will become: {\small \begin{verbatim} 00010040 auipc x10,((0x00010900 - 0x00010040) + 0x00000800) >> 12 00010044 addi x10,x10,((0x00010900 - (0x00010044 - 4)) & 0x00000fff) # note the extra -4 here! \end{verbatim} } After performing the subtractions, it will reduce to this: {\small \begin{verbatim} 00010040 auipc x10,(0x000008c0 + 0x00000800) >> 12 00010044 addi x10,x10,(0x000008c0 & 0x00000fff) \end{verbatim} } Continuing to reduce the math operations we get: {\small \begin{verbatim} 00010040 auipc x10,0x00001 # 0x000008c0 + 0x00000800 = 0x000010c0 00010044 addi x10,x10,0x8c0 \end{verbatim} } Note that the \verb@la@ pseudoinstruction exhibits the same sort of technique as the \verb@li@ in that if/when the immediate operand of the \verb@addi@ instruction has its most significant bit set then the operand in the \verb@auipc@ has to be incremented by 1 to compensate. \section{Relocation} Because expressions that refer to constants and address labels are common in assembly language programs, a shorthand notation is available for calculating the pairs of values that are used in the implementation of things like the \verb@li@ and \verb@la@ pseudoinstructions (that have to be written to compensate for the sign-extension that will take place in the immediate operand that appears in instructions like \verb@addi@ and \verb@jalr@.) \subsection{Absolute Addresses} To refer to an absolute value, the following operators can be used: {\small \begin{verbatim} %hi(constant) // becomes: (constant + 0x00000800) >> 12 %lo(constant) // becomes: (constant & 0x00000fff) \end{verbatim} } Thus, the \verb@li@ pseudoinstruction can, therefore, be expressed like this: {\small \begin{verbatim} li rd,constant lui rd,%hi(constant) addi rd,rd,%lo(constant) \end{verbatim} } \subsection{PC-Relative Addresses} The following can be used for PC-relative addresses: {\small \begin{verbatim} %pcrel_hi(symbol) // becomes: ((symbol-.) + 0x0800) >> 12 %pcrel_lo(lab) // becomes: ((symbol-lab) & 0x00000fff) \end{verbatim} } Note the subtlety involved with the \verb@lab@ on \verb@%pcrel_lo@. It is needed to determine the address of the instruction that contains the corresponding \verb@%pcrel_hi@. (The label \verb@lab@ MUST be on a line that used a \verb@%pcrel_hi()@ or get an error from the assembler.) Thus, the \verb@la rd,label@ pseudoinstruction can be expressed like this: {\small \begin{verbatim} xxx: auipc rd,%pcrel_hi(label) addi rd,rd,%pcrel_lo(xxx) // the xxx tells pcrel_lo where to find the matching pcrel_hi \end{verbatim} } Examples of using the \verb@auipc@ \& \verb@addi@ together with \verb@%pcrel_hi()@ and \verb@%pcrel_lo()@: {\small \begin{verbatim} xxx: auipc t1,%pcrel_hi(yyy) // ((yyy-.) + 0x0800) >> 12 addi t1,t1,%pcrel_lo(xxx) // ((yyy-xxx) & 0x00000fff) ... yyy: // the address: yyy is saved into t1 above ... \end{verbatim} } Referencing the same \verb@%pcrel_hi@ in multiple subsequent uses of \verb@%pcrel_lo@ is legal: {\small \begin{verbatim} label: auipc t1,%pcrel_hi(symbol) addi t2,t1,%pcrel_lo(label) // t2 = symbol addi t3,t1,%pcrel_lo(label) // t3 = symbol lw t4,%pcrel_lo(label)(t1) // t4 = fetch value from memory at 'symbol' addi t4,t4,123 // t4 = t4 + 123 sw t4,%pcrel_lo(label)(t1) // store t4 back into memory at 'symbol' \end{verbatim} } \section{Relaxation} %\enote{I'm not sure I want to get into the details of how this is done. Just assume it works.}% In the simplest of terms, {\em Relaxation} refers to the ability of the linker (not the compiler!) to determine if/when the instructions that were generated with the \verb@xxx_hi@ and \verb@xxx_lo@ operators are unneeded (and thus waste execution time and memory) and can therefore be removed. However, doing so is not trivial as it will result in moving things around in memory, possibly changing the values of address labels in the already-assembled program! Therefore, while the motivation for rexation is obvious, the process of implementing it is non-trivial. See: \url{https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md} ================================================ FILE: book/programs/src/.gitignore ================================================ *.bin ================================================ FILE: book/programs/src/Make.rules ================================================ ARCH=riscv32-unknown-elf CC=$(ARCH)-gcc AS=$(ARCH)-as LD=$(ARCH)-ld OBJCOPY=$(ARCH)-objcopy OBJDUMP=$(ARCH)-objdump SIZE=$(ARCH)-size #LDFLAGS+=-nostdlib -Wl,-Ttext=0x0,-Tdata=0x8000 LDFLAGS+=-nostdlib -Wl,-Ttext=0x0 CFLAGS+=-ffreestanding -fno-pic CFLAGS+=-march=rv32i -mabi=ilp32 CFLAGS+=-Wl,--no-relax # see: https://github.com/riscv/riscv-gcc/issues/120 ASFLAGS+=$(CFLAGS) CLEAN_DIRS=$(SUBDIRS:%=clean-%) ALL_DIRS=$(SUBDIRS:%=all-%) .PHONY: all clean world $(CLEAN_DIRS) $(ALL_DIRS) %.bin : % $(OBJCOPY) $< -O binary $@ %.lst : % $(OBJDUMP) -dr $< | grep -v '^$$' > $<.lst % : %.o $(LINK.c) $(LDFLAGS) -o $@ $^ $(LDLIBS) $(SIZE) -x -A $@ %.s: %.c $(COMPILE.c) -S -o $@ $< %.srec: % $(OBJCOPY) $< -O srec $@ all:: $(ALL_DIRS) clean:: $(CLEAN_DIRS) $(ALL_DIRS):: $(MAKE) -C $(@:all-%=%) all $(CLEAN_DIRS):: $(MAKE) -C $(@:clean-%=%) clean world:: clean all ================================================ FILE: book/programs/src/Makefile ================================================ SUBDIRS=\ nop\ li\ mv\ mvzero\ ebreak TOP=. include $(TOP)/Make.rules ================================================ FILE: book/programs/src/mvzero/.gitignore ================================================ mv ================================================ FILE: book/programs/src/mvzero/Makefile ================================================ PROG=mv all:: $(PROG).out $(PROG).lst $(PROG).out:: $(PROG).bin ./run.sh > $@ 2>&1 $(PROG).bin:: $(PROG) clean:: rm -f $(PROG) *.o *.lst *.bin *.srec *.out TOP=.. include $(TOP)/Make.rules ================================================ FILE: book/programs/src/mvzero/mv.S ================================================ .text # put this into the text section .align 2 # align to a multiple of 4 .globl _start _start: mv t3, x0 # t3 = 0 ebreak ================================================ FILE: book/programs/src/mvzero/mv.lst ================================================ mv: file format elf32-littleriscv Disassembly of section .text: 00000000 <_start>: 0: 00000e13 li t3,0 4: 00100073 ebreak ================================================ FILE: book/programs/src/mvzero/mv.out ================================================ $ rvddt -f mv.bin sp initialized to top of memory: 0x0000fff0 Loading 'mv.bin' to 0x0 This is rvddt. Enter ? for help. ddt> a ddt> d 0 16 00000000: 13 0e 00 00 73 00 10 00 a5 a5 a5 a5 a5 a5 a5 a5 *....s...........* ddt> t 0 1000 zero x0 00000000 ra x1 f0f0f0f0 sp x2 0000fff0 gp x3 f0f0f0f0 tp x4 f0f0f0f0 t0 x5 f0f0f0f0 t1 x6 f0f0f0f0 t2 x7 f0f0f0f0 s0 x8 f0f0f0f0 s1 x9 f0f0f0f0 a0 x10 f0f0f0f0 a1 x11 f0f0f0f0 a2 x12 f0f0f0f0 a3 x13 f0f0f0f0 a4 x14 f0f0f0f0 a5 x15 f0f0f0f0 a6 x16 f0f0f0f0 a7 x17 f0f0f0f0 s2 x18 f0f0f0f0 s3 x19 f0f0f0f0 s4 x20 f0f0f0f0 s5 x21 f0f0f0f0 s6 x22 f0f0f0f0 s7 x23 f0f0f0f0 s8 x24 f0f0f0f0 s9 x25 f0f0f0f0 s10 x26 f0f0f0f0 s11 x27 f0f0f0f0 t3 x28 f0f0f0f0 t4 x29 f0f0f0f0 t5 x30 f0f0f0f0 t6 x31 f0f0f0f0 pc 00000000 00000000: 00000e13 addi t3, zero, 0 # t3 = 0x00000000 = 0x00000000 + 0x00000000 zero x0 00000000 ra x1 f0f0f0f0 sp x2 0000fff0 gp x3 f0f0f0f0 tp x4 f0f0f0f0 t0 x5 f0f0f0f0 t1 x6 f0f0f0f0 t2 x7 f0f0f0f0 s0 x8 f0f0f0f0 s1 x9 f0f0f0f0 a0 x10 f0f0f0f0 a1 x11 f0f0f0f0 a2 x12 f0f0f0f0 a3 x13 f0f0f0f0 a4 x14 f0f0f0f0 a5 x15 f0f0f0f0 a6 x16 f0f0f0f0 a7 x17 f0f0f0f0 s2 x18 f0f0f0f0 s3 x19 f0f0f0f0 s4 x20 f0f0f0f0 s5 x21 f0f0f0f0 s6 x22 f0f0f0f0 s7 x23 f0f0f0f0 s8 x24 f0f0f0f0 s9 x25 f0f0f0f0 s10 x26 f0f0f0f0 s11 x27 f0f0f0f0 t3 x28 00000000 t4 x29 f0f0f0f0 t5 x30 f0f0f0f0 t6 x31 f0f0f0f0 pc 00000004 00000004: ebreak ddt> x ================================================ FILE: book/programs/src/mvzero/run.sh ================================================ prompt="$" cmd="rvddt -f mv.bin" echo "$prompt $cmd" $cmd <=rs2) ? @\hyperref[imm.b:decode]{imm\_b}\verb@ : 4@)}\\ \hline bgeu & rs1, rs2, \hyperref[pcrel.13]{pcrel\_13} & \hyperref[insnformat:btype]{B} & \hyperref[insn:bgeu]{Branch Greater or Equal Unsigned} & {\tt pc $\leftarrow$ pc + (\verb@(rs1>=rs2) ? @\hyperref[imm.b:decode]{imm\_b}\verb@ : 4@)}\\ \hline blt & rs1, rs2, \hyperref[pcrel.13]{pcrel\_13} & \hyperref[insnformat:btype]{B} & \hyperref[insn:blt]{Branch Less Than} & {\tt pc $\leftarrow$ pc + (\verb@(rs1> (rs2\%\hyperref[XLEN]{XLEN}), pc $\leftarrow$ pc+4}\\ \hline srai & rd, rs1, shamt & \hyperref[insnformat:itype]{I} & \hyperref[insn:srai]{Shift Right Arithmetic Immediate} & {\tt rd $\leftarrow$ rs1 >> \hyperref[shamt.i:decode]{shamt\_i}, pc $\leftarrow$ pc+4}\\ \hline srl & rd, rs1, rs2 & \hyperref[insnformat:rtype]{R} & \hyperref[insn:srl]{Shift Right Logical} & {\tt rd $\leftarrow$ rs1 >> (rs2\%\hyperref[XLEN]{XLEN}), pc $\leftarrow$ pc+4}\\ \hline srli & rd, rs1, shamt & \hyperref[insnformat:itype]{I} & \hyperref[insn:srli]{Shift Right Logical Immediate} & {\tt rd $\leftarrow$ rs1 >> \hyperref[shamt.i:decode]{shamt\_i}, pc $\leftarrow$ pc+4}\\ \hline sub & rd, rs1, rs2 & \hyperref[insnformat:rtype]{R} & \hyperref[insn:sub]{Subtract} & {\tt rd $\leftarrow$ rs1 - rs2, pc $\leftarrow$ pc+4}\\ \hline sw & rs2, imm(rs1) & \hyperref[insnformat:stype]{S} & \hyperref[insn:sw]{Store Word} & {\tt \hyperref[memory:m32]{m32}(rs1+\hyperref[imm.s:decode]{imm\_s}) $\leftarrow$ rs2[31:0], pc $\leftarrow$ pc+4}\\ \hline xor & rd, rs1, rs2 & \hyperref[insnformat:rtype]{R} & \hyperref[insn:xor]{Exclusive Or} & {\tt rd $\leftarrow$ rs1 $\oplus$ rs2, pc $\leftarrow$ pc+4}\\ \hline xori & rd, rs1, imm & \hyperref[insnformat:itype]{I} & \hyperref[insn:xori]{Exclusive Or Immediate} & {\tt rd $\leftarrow$ rs1 $\oplus$ \hyperref[imm.i:decode]{imm\_i}, pc $\leftarrow$ pc+4}\\ \hline \end{tabular} }% \newpage {\Large RV32I Base Instruction Set Encoding}~\cite[p.~104]{rvismv1v22:2017} %\DrawAllInsnTypes \DrawAllInsnOps \newpage% \thispagestyle{empty}% %\newgeometry{left=1.3in,width=8.1in,height=13in,top=1in,bottom=0in}% \newgeometry{left=0in,width=8in,height=10.5in,vmargin=0in,hmargin=0in,layouthoffset=1.35in,layoutvoffset=1in}% %\resizebox{8in}{!}{\rotatebox{90}{\DrawAllInsnOps}} %\resizebox{8in}{!}{\rotatebox{90}{\DrawGCAllInsnOps}} \resizebox{8in}{10.7in}{\rotatebox{90}{\DrawGCAllInsnOps}} \newpage% \thispagestyle{empty}% \resizebox{8in}{!}{ \rotatebox{-90}{ \DrawInsnRibbons } } \restoregeometry ================================================ FILE: book/rv32/base.tex ================================================ \section{RV32I Base Instruction Set} \index{RV32I} \enote{Migrate all te details into the programming chapter and reduce this section to the obligatory reference chapter.}% \Gls{rv32}I refers to the basic 32-bit integer instructions. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{LUI rd, imm} \index{Instruction!LUI} Load Upper Immediate. \verb@rd@ $\leftarrow$ \verb@zr(imm)@ Copy the immediate value into bits 31:12 of the destination register and place zeros into bits 11:0. When XLEN is 64 or 128, the immediate value is sign-extended to the left. \input{insn/lui.tex} %Instruction Format and Example: % %\DrawInsnTypeUPicture{LUI t0, 3}{00000000000000000011001010110111} % %\begin{verbatim} %00010074: 000032b7 lui x5, 0x3 // x5 = 0x3000 % reg 0: 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 00003000 f0f0f0f0 f0f0f0f0 % reg 8: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 % reg 16: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 % reg 24: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 % pc: 00010078 %\end{verbatim} % %\DrawInsnTypeUPicture{LUI t0, 0xfffff}{11111111111111111111001010110111} % %\begin{verbatim} %00010078: fffff2b7 lui x5, 0xfffff // x5 = 0xfffff000 % reg 0: 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 fffff000 f0f0f0f0 f0f0f0f0 % reg 8: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 % reg 16: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 % reg 24: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 % pc: 0001007c %\end{verbatim} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{AUIPC rd, imm} \index{Instruction!AUIPC} Add Upper Immediate to PC. \verb@rd@ $\leftarrow$ \verb@pc + zr(imm)@ Create a signed 32-bit value by zero-extending imm[31:12] to the right (see \autoref{extension:zr}) and add this value to the \reg{pc} register, placing the result into \reg{rd}. When XLEN is 64 or 128, the immediate value is also sign-extended to the left prior to being added to the \reg{pc} register. \DrawInsnTypeUPicture{AUIPC t0, 3}{00000000000000000011001010110111} \begin{verbatim} 0001007c: 00003297 auipc x5, 0x3 // x5 = 0x1307c = 0x1007c + 0x3000 reg 0: 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 0001307c f0f0f0f0 f0f0f0f0 reg 8: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 reg 16: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 reg 24: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 pc: 00010080 \end{verbatim} \DrawInsnTypeUPicture{AUIPC t0, 0x81000}{10000001000000000000001010110111} \begin{verbatim} 00010080: 81000297 auipc x5, 0x81000 // x5 = 0x81010080 = 0x10080 + 0x81000000 reg 0: 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 81010080 f0f0f0f0 f0f0f0f0 reg 8: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 reg 16: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 reg 24: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 pc: 00010084 \end{verbatim} The AUIPC instruction supports two-instruction sequences to access arbitrary offsets from the PC for both control-flow transfers and data accesses. The combination of an AUIPC and the 12-bit immediate in a JALR can transfer control to any 32-bit PC-relative address, while an AUIPC plus the 12-bit immediate offset in regular load or store instructions can access any 32-bit PC-relative data address.~\cite[p.~14]{rvismv1v22:2017} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{JAL rd, imm} \index{Instruction!JAL} Jump and link. \verb@rd@ $\leftarrow$ \verb@pc + 4@\\ \verb@pc@ $\leftarrow$ \verb@pc + sx(imm<<1)@ This instruction saves the address of the next instruction that would otherwise execute (located at \reg{pc}+4) into \reg{rd} and then adds immediate value to the \reg{pc} causing an unconditional branch to take place. The standard software conventions for calling subroutines use \reg{x1} as the return address (\reg{rd} register in this case).~\cite[p.~16]{rvismv1v22:2017} Encoding: \DrawInsnTypeJPicture{JAL x7, .+16}{00000001000000000000001111101111} imm demultiplexed value = $00000000000000001000_2 \ll 1 = 16_{10}$ State of registers before execution: pc = 0x11114444 State of registers after execution: pc = 0x11114454 x7 = 0x11114448 JAL provides a method to call a subroutine using a pc-relative address. \DrawInsnTypeJPicture{JAL x7, .-16}{11111111000111111111001111101111} imm demultiplexed value = $11111111111111111000_2 \ll 1 = -16_{10}$ State of registers before execution: pc = 0x11114444 State of registers after execution: pc = 0x11114434 x7 = 0x11114448 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{JALR rd, rs1, imm} \index{Instruction!JALR} Jump and link register. \verb@rd@ $\leftarrow$ \verb@pc + 4@\\ \verb@pc@ $\leftarrow$ \verb@(rs1 + sx(imm)) & ~1@ This instruction saves the address of the next instruction that would otherwise execute (located at \reg{pc}+4) into \reg{rd} and then adds the immediate value to the \reg{rs1} register and stores the sum into the \reg{pc} register causing an unconditional branch to take place. Note that the branch target address is calculated by sign-extending the imm[11:0] bits from the instruction, adding it to the \reg{rs1} register and {\em then} the LSB of the sum is to zero and the result is stored into the \reg{pc} register. The discarding of the LSB allows the branch to refer to any even address. The standard software conventions for calling subroutines use \reg{x1} as the return address (\reg{rd} register in this case).~\cite[p.~16]{rvismv1v22:2017} Encoding: \DrawInsnTypeIPicture{JALR x1, x7, 4}{00000000010000111000000011100111} Before: pc = 0x11114444\\ x7 = 0x44444444 After pc = 0x5555888c\\ x1 = 0x11114448 JALR provides a method to call a subroutine using a base-displacement address. \DrawInsnTypeIPicture{JALR x1, x0, 5}{00000000010100000000000011100111} Note that the least significant bit in the result of rs1+imm is discarded/set to zero before the result is saved in the pc. pc = 0x11114444 After pc = 0x00000004\\ x1 = 0x11114448 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{BEQ rs1, rs2, imm} \index{Instruction!BEQ} Branch if equal. \verb@pc@ $\leftarrow$ \verb@(rs1 == rs2) ? pc+sx(imm[12:1]<<1) : pc+4@ Encoding: \DrawInsnTypeBPicture{BEQ x3, x15, 2064}{00000000111100011000100011100011} imm[12:1] = $010000001000_2 = 1032_{10}$\\ imm = $2064_{10}$\\ funct3 = $000_2$\\ rs1 = x3\\ rs2 = x15 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{BNE rs1, rs2, imm} \index{Instruction!BNE} Branch if Not Equal. \verb@pc@ $\leftarrow$ \verb@(rs1 != rs2) ? pc+sx(imm[12:1]<<1) : pc+4@ Encoding: \DrawInsnTypeBPicture{BNE x3, x15, 2064}{00000000111100011001100011100011} imm[12:1] = $010000001000_2 = 1032_{10}$\\ imm = $2064_{10}$\\ funct3 = $001_2$\\ rs1 = x3\\ rs2 = x15 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{BLT rs1, rs2, imm} \index{Instruction!BLT} Branch if Less Than. \verb@pc@ $\leftarrow$ \verb@(rs1 < rs2) ? pc+sx(imm[12:1]<<1) : pc+4@ Encoding: \DrawInsnTypeBPicture{BLT x3, x15, 2064}{00000000111100011100100011100011} imm[12:1] = $010000001000_2 = 1032_{10}$\\ imm = $2064_{10}$\\ funct3 = $100_2$\\ rs1 = x3\\ rs2 = x15 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{BGE rs1, rs2, imm} \index{Instruction!BGE} Branch if Greater or Equal. \verb@pc@ $\leftarrow$ \verb@(rs1 >= rs2) ? pc+sx(imm[12:1]<<1) : pc+4@ Encoding: \DrawInsnTypeBPicture{BGE x3, x15, 2064}{00000000111100011101100011100011} imm[12:1] = $010000001000_2 = 1032_{10}$\\ imm = $2064_{10}$\\ funct3 = $101_2$\\ rs1 = x3\\ rs2 = x15 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{BLTU rs1, rs2, imm} \index{Instruction!BLTU} Branch if Less Than Unsigned. \verb@pc@ $\leftarrow$ \verb@(rs1 < rs2) ? pc+sx(imm[12:1]<<1) : pc+4@ Encoding: \DrawInsnTypeBPicture{BLTU x3, x15, 2064}{00000000111100011110100011100011} imm[12:1] = $010000001000_2 = 1032_{10}$\\ imm = $2064_{10}$\\ funct3 = $110_2$\\ rs1 = x3\\ rs2 = x15 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{BGEU rs1, rs2, imm} \index{Instruction!BGEU} Branch if Greater or Equal Unsigned. \verb@pc@ $\leftarrow$ \verb@(rs1 >= rs2) ? pc+sx(imm[12:1]<<1) : pc+4@ Encoding: \DrawInsnTypeBPicture{BGEU x3, x15, 2064}{00000000111100011111100011100011} \enote{use symbols in branch examples} imm[12:1] = $010000001000_2 = 1032_{10}$\\ imm = $2064_{10}$\\ funct3 = $111_2$\\ rs1 = x3\\ rs2 = x15 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{LB rd, imm(rs1)} \index{Instruction!LB} Load byte. \verb@rd@ $\leftarrow$ \verb@sx(m8(rs1+sx(imm)))@\\ \verb@pc@ $\leftarrow$ \verb@pc+4@ Load an 8-bit value from memory at address \verb@rs1+imm@, then sign-extend it to 32 bits before storing it in \verb@rd@ Encoding: \DrawInsnTypeIPicture{LB x7, 4(x3)}{00000000010000011000001110000011} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{LH rd, imm(rs1)} \index{Instruction!LH} Load halfword. \verb@rd@ $\leftarrow$ \verb@sx(m16(rs1+sx(imm)))@\\ \verb@pc@ $\leftarrow$ \verb@pc+4@ Load a 16-bit value from memory at address \verb@rs1+imm@, then sign-extend it to 32 bits before storing it in \verb@rd@ Encoding: \DrawInsnTypeIPicture{LH x7, 4(x3)}{00000000010000011001001110000011} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{LW rd, imm(rs1)} \index{Instruction!LW} Load word. \verb@rd@ $\leftarrow$ \verb@sx(m32(rs1+sx(imm)))@\\ \verb@pc@ $\leftarrow$ \verb@pc+4@ Load a 32-bit value from memory at address \verb@rs1+imm@, then store it in \verb@rd@ Encoding: \DrawInsnTypeIPicture{LW x7, 4(x3)}{00000000010000011010001110000011} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{LBU rd, imm(rs1)} \index{Instruction!LBU} Load byte unsigned. \verb@rd@ $\leftarrow$ \verb@zx(m8(rs1+sx(imm)))@\\ \verb@pc@ $\leftarrow$ \verb@pc+4@ Load an 8-bit value from memory at address \verb@rs1+imm@, then zero-extend it to 32 bits before storing it in \verb@rd@ Encoding: \DrawInsnTypeIPicture{LBU x7, 4(x3)}{00000000010000011100001110000011} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{LHU rd, imm(rs1)} \index{Instruction!LHU} Load halfword unsigned. \verb@rd@ $\leftarrow$ \verb@zx(m16(rs1+sx(imm)))@\\ \verb@pc@ $\leftarrow$ \verb@pc+4@ Load an 16-bit value from memory at address \verb@rs1+imm@, then zero-extend it to 32 bits before storing it in \verb@rd@ Encoding: \DrawInsnTypeIPicture{LHU x7, 4(x3)}{00000000010000011101001110000011} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{SB rs2, imm(rs1)} \index{Instruction!SB} Store Byte. \verb@m8(rs1+sx(imm))@ $\leftarrow$ \verb@rs2[7:0]@\\ \verb@pc@ $\leftarrow$ \verb@pc+4@ Store the 8-bit value in \verb@rs2[7:0]@ into memory at address \verb@rs1+imm@. Encoding: \DrawInsnTypeSPicture{SB x3, 19(x15)}{00000000111100011000100110100011} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{SH rs2, imm(rs1)} \index{Instruction!SH} Store Halfword. \verb@m16(rs1+sx(imm))@ $\leftarrow$ \verb@rs2[15:0]@\\ \verb@pc@ $\leftarrow$ \verb@pc+4@ Store the 16-bit value in \verb@rs2[15:0]@ into memory at address \verb@rs1+imm@. Encoding: \DrawInsnTypeSPicture{SH x3, 19(x15)}{00000000111100011001100110100011} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{SW rs2, imm(rs1)} \index{Instruction!SW} Store Word \verb@m16(rs1+sx(imm))@ $\leftarrow$ \verb@rs2[31:0]@\\ \verb@pc@ $\leftarrow$ \verb@pc+4@ Store the 32-bit value in \verb@rs2@ into memory at address \verb@rs1+imm@. Encoding: \DrawInsnTypeSPicture{SW x3, 19(x15)}{00000000111100011010100110100011} Show pos \& neg imm examples. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{ADDI rd, rs1, imm} \index{Instruction!ADDI} Add Immediate \verb@rd@ $\leftarrow$ \verb@rs1+sx(imm)@\\ \verb@pc@ $\leftarrow$ \verb@pc+4@ Encoding: \DrawInsnTypeIPicture{ADDI x1, x7, 4}{00000000010000111000000010010011} Before: x7 = 0x11111111 After: x1 = 0x11111115 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{SLTI rd, rs1, imm} \index{Instruction!SLTI} Set LessThan Immediate \verb@rd@ $\leftarrow$ \verb@(rs1 < sx(imm)) ? 1 : 0@\\ \verb@pc@ $\leftarrow$ \verb@pc+4@ If the sign-extended immediate value is less than the value in the \reg{rs1} register then the value 1 is stored in the \reg{rd} register. Otherwise the value 0 is stored in the \reg{rd} register. Encoding: \DrawInsnTypeIPicture{SLTI x1, x7, 4}{00000000010000111010000010010011} Before: x7 = 0x11111111 After: x1 = 0x00000000 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{SLTIU rd, rs1, imm} \index{Instruction!SLTIU} Set LessThan Immediate Unsigned \verb@rd@ $\leftarrow$ \verb@(rs1 < sx(imm)) ? 1 : 0@\\ \verb@pc@ $\leftarrow$ \verb@pc+4@ If the sign-extended immediate value is less than the value in the \reg{rs1} register then the value 1 is stored in the \reg{rd} register. Otherwise the value 0 is stored in the \reg{rd} register. Both the immediate and \reg{rs1} register values are treated as unsigned numbers for the purposes of the comparison.\footnote{The immediate value is first sign-extended to XLEN bits then treated as an unsigned number.\cite[p.~14]{rvismv1v22:2017}} Encoding: \DrawInsnTypeIPicture{SLTIU x1, x7, 4}{00000000010000111011000010010011} Before: x7 = 0x81111111 After: x1 = 0x00000001 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{XORI rd, rs1, imm} \index{Instruction!XORI} Exclusive Or Immediate \verb@rd@ $\leftarrow$ \verb@rs1 ^ sx(imm)@\\ \verb@pc@ $\leftarrow$ \verb@pc+4@ The logical XOR of the sign-extended immediate value and the value in the \reg{rs1} register is stored in the \reg{rd} register. Encoding: \DrawInsnTypeIPicture{XORI x1, x7, 4}{00000000010000111100000010010011} Before: x7 = 0x81111111 After: x1 = 0x81111115 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{ORI rd, rs1, imm} \index{Instruction!ORI} Or Immediate \verb@rd@ $\leftarrow$ \verb@rs1 | sx(imm)@\\ \verb@pc@ $\leftarrow$ \verb@pc+4@ The logical OR of the sign-extended immediate value and the value in the \reg{rs1} register is stored in the \reg{rd} register. Encoding: \DrawInsnTypeIPicture{ORI x1, x7, 4}{00000000010000111110000010010011} Before: x7 = 0x81111111 After: x1 = 0x81111115 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{ANDI rd, rs1, imm} \index{Instruction!ANDI} And Immediate \verb@rd@ $\leftarrow$ \verb@rs1 & sx(imm)@\\ \verb@pc@ $\leftarrow$ \verb@pc+4@ The logical AND of the sign-extended immediate value and the value in the \reg{rs1} register is stored in the \reg{rd} register. Encoding: \DrawInsnTypeIPicture{ANDI x1, x7, 4}{00000000010000111111000010010011} Before: x7 = 0x81111111 After: x1 = 0x81111115 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{SLLI rd, rs1, shamt} \index{Instruction!SLLI} Shift Left Logical Immediate \verb@rd@ $\leftarrow$ \verb@rs1 << shamt@\\ \verb@pc@ $\leftarrow$ \verb@pc+4@ SLLI is a logical left shift operation (zeros are shifted into the lower bits). The value in rs1 shifted left shamt number of bits and the result placed into rd.~\cite[p.~14]{rvismv1v22:2017} Encoding: \DrawInsnTypeRShiftPicture{SLLI x7, x3, 2}{00000000001000011001001110100011} x3 = 0x81111111 After: x7 = 0x04444444 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{SRLI rd, rs1, shamt} \index{Instruction!SRLI} Shift Right Logical Immediate \verb@rd@ $\leftarrow$ \verb@rs1 >> shamt@\\ \verb@pc@ $\leftarrow$ \verb@pc+4@ SRLI is a logical right shift operation (zeros are shifted into the higher bits). The value in rs1 shifted right shamt number of bits and the result placed into rd.~\cite[p.~14]{rvismv1v22:2017} Encoding: \DrawInsnTypeRShiftPicture{SRLI x7, x3, 2}{00000000001000011101001110010011} x3 = 0x81111111 After: x7 = 0x20444444 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{SRAI rd, rs1, shamt} \index{Instruction!SRAI} Shift Right Arithmetic Immediate \verb@rd@ $\leftarrow$ \verb@rs1 >> shamt@\\ \verb@pc@ $\leftarrow$ \verb@pc+4@ SRAI is a logical right shift operation (zeros are shifted into the higher bits). The value in rs1 shifted right shamt number of bits and the result placed into rd.~\cite[p.~14]{rvismv1v22:2017} Encoding: \DrawInsnTypeRShiftPicture{SRAI x7, x3, 2}{01000000001000011101001110010011} x3 = 0x81111111 After: x7 = 0xe0444444 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{ADD rd, rs1, rs2} \index{Instruction!ADD} Add \verb@rd@ $\leftarrow$ \verb@rs1 + rs2@\\ \verb@pc@ $\leftarrow$ \verb@pc+4@ ADD performs addition. Overflows are ignored and the low 32 bits of the result are written to rd.~\cite[p.~15]{rvismv1v22:2017} Encoding: \DrawInsnTypeRPicture{ADD x7, x3, x31}{00000001111100011000001110110011} x3 = 0x81111111 x31 = 0x22222222 After: x7 = 0xa3333333 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{SUB rd, rs1, rs2} \index{Instruction!SUB} Subtract \verb@rd@ $\leftarrow$ \verb@rs1 - rs2@\\ \verb@pc@ $\leftarrow$ \verb@pc+4@ SUB performs subtraction. Underflows are ignored and the low 32 bits of the result are written to rd.~\cite[p.~15]{rvismv1v22:2017} Encoding: \DrawInsnTypeRPicture{SUB x7, x3, x31}{01000001111100011000001110110011} x3 = 0x83333333 x31 = 0x01111111 After: x7 = 0x82222222 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{SLL rd, rs1, rs2} \index{Instruction!SLL} Shift Left Logical \verb@rd@ $\leftarrow$ \verb@rs1 << rs2@\\ \verb@pc@ $\leftarrow$ \verb@pc+4@ SLL performs a logical left shift on the value in register rs1 by the shift amount held in the lower 5 bits of register rs2.~\cite[p.~15]{rvismv1v22:2017} Encoding: \DrawInsnTypeRPicture{SLL x7, x3, x31}{00000001111100011001001110110011} x3 = 0x83333333\\ x31 = 0x00000002 After: x7 = 0x0ccccccc %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{SLT rd, rs1, rs2} \index{Instruction!SLT} Set Less Than \verb@rd@ $\leftarrow$ \verb@(rs1 < rs2) ? 1 : 0@\\ \verb@pc@ $\leftarrow$ \verb@pc+4@ SLT performs a signed compare, writing 1 to \reg{rd} if \reg{rs1} $<$ \reg{rs2}, 0 otherwise.~\cite[p.~15]{rvismv1v22:2017} Encoding: \DrawInsnTypeRPicture{SLT x7, x3, x31}{00000001111100011010001110110011} x3 = 0x83333333\\ x31 = 0x00000002 After: x7 = 0x00000001 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{SLTU rd, rs1, rs2} \index{Instruction!SLTU} Set Less Than Unsigned \verb@rd@ $\leftarrow$ \verb@(rs1 < rs2) ? 1 : 0@\\ \verb@pc@ $\leftarrow$ \verb@pc+4@ SLTU performs an unsigned compare, writing 1 to \reg{rd} if \reg{rs1} $<$ \reg{rs2}, 0 otherwise. Note, SLTU rd, x0, rs2 sets \reg{rd} to 1 if \reg{rs2} is not equal to zero, otherwise sets \reg{rd} to zero (assembler pseudoinstruction \verb@SNEZ rd, rs@).~\cite[p.~15]{rvismv1v22:2017} Encoding: \DrawInsnTypeRPicture{SLTU x7, x3, x31}{00000001111100011011001110110011} x3 = 0x83333333\\ x31 = 0x00000002 After: x7 = 0x00000000 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{XOR rd, rs1, rs2} \index{Instruction!XOR} Exclusive Or \verb@rd@ $\leftarrow$ \verb@rs1 ^ rs2@\\ \verb@pc@ $\leftarrow$ \verb@pc+4@ XOR performs a bit-wise exclusive or on rs1 and rs2. The result is stored on rd. Encoding: \DrawInsnTypeRPicture{XOR x7, x3, x31}{00000001111100011100001110110011} x3 = 0x83333333\\ x31 = 0x1888ffff After: x7 = 0x9bbbcccc %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{SRL rd, rs1, rs2} \index{Instruction!SRL} Shift Right Logical \verb@rd@ $\leftarrow$ \verb@rs1 >> rs2@\\ \verb@pc@ $\leftarrow$ \verb@pc+4@ SRL performs a logical right shift on the value in register rs1 by the shift amount held in the lower 5 bits of register rs2.~\cite[p.~15]{rvismv1v22:2017} Encoding: \DrawInsnTypeRPicture{SRL x7, x3, x31}{00000001111100011101001110110011} x3 = 0x83333333\\ x31 = 0x00000010 After: x7 = 0x00008333 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{SRA rd, rs1, rs2} \index{Instruction!SRA} Shift Right Arithmetic \verb@rd@ $\leftarrow$ \verb@rs1 >> rs2@\\ \verb@pc@ $\leftarrow$ \verb@pc+4@ SRA performs an arithmetic right shift (the original sign bit is copied into the vacated upper bits) on the value in register rs1 by the shift amount held in the lower 5 bits of register rs2.~\cite[p.~14,~15]{rvismv1v22:2017} Encoding: \DrawInsnTypeRPicture{SRA x7, x3, x31}{01000001111100011101001110110011} x3 = 0x83333333\\ x31 = 0x00000010 After: x7 = 0xffff8333 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{OR rd, rs1, rs2} \index{Instruction!OR} Or \verb@rd@ $\leftarrow$ \verb@rs1 | rs2@\\ \verb@pc@ $\leftarrow$ \verb@pc+4@ OR is a logical operation that performs a bit-wise OR on register rs1 and rs2 and then places the result in rd.~\cite[p.~14]{rvismv1v22:2017} Encoding: \DrawInsnTypeRPicture{OR x7, x3, x31}{00000001111100011101001110110011} x3 = 0x83333333\\ x31 = 0x00000440 After: x7 = 0x83333773 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{AND rd, rs1, rs2} \index{Instruction!AND} And \verb@rd@ $\leftarrow$ \verb@rs1 & rs2@\\ \verb@pc@ $\leftarrow$ \verb@pc+4@ AND is a logical operation that performs a bit-wise AND on register rs1 and rs2 and then places the result in rd.~\cite[p.~14]{rvismv1v22:2017} Encoding: \DrawInsnTypeRPicture{AND x7, x3, x31}{00000001111100011110001110110011} x3 = 0x83333333\\ x31 = 0x00000fe2 After: x7 = 0x00000322 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{FENCE predecessor, successor} \index{Instruction!FENCE} \enote{Which of the i, o, r and w goes into each bit? See what gas does.}% The FENCE instruction is used to order device I/O and memory accesses as viewed by other RISC-V harts and external devices or co-processors. Any combination of device input (I), device output (O), memory reads (R), and memory writes (W) may be ordered with respect to any combination of the same. Informally, no other RISC-V hart or external device can observe any operation in the successor set following a FENCE before any operation in the predecessor set preceding the FENCE. The execution environment will define what I/O operations are possible, and in particular, which load and store instructions might be treated and ordered as device input and device output operations respectively rather than memory reads and writes. For example, memory-mapped I/O devices will typically be accessed with uncached loads and stores that are ordered using the I and O bits rather than the R and W bits. Instruction-set extensions might also describe new coprocessor I/O instructions that will also be ordered using the I and O bits in a FENCE.~\cite[p.~21]{rvismv1v22:2017} Operation: \verb@pc@ $\leftarrow$ \verb@pc+4@ Encoding: \DrawInsnTypeFPicture{FENCE iorw, iorw}{00001111111100000000000000001111} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{FENCE.I} \index{Instruction!FENCE.I} The FENCE.I instruction is used to synchronize the instruction and data streams. RISC-V does not guarantee that stores to instruction memory will be made visible to instruction fetches on the same RISC-V hart until a FENCE.I instruction is executed. A FENCE.I instruction only ensures that a subsequent instruction fetch on a RISC-V hart will see any previous data stores already visible to the same RISC-V hart. FENCE.I does not ensure that other RISC-V harts' instruction fetches will observe the local hart's stores in a multiprocessor system. To make a store to instruction memory visible to all RISC-V harts, the writing hart has to execute a data FENCE before requesting that all remote RISC-V harts execute a FENCE.I.~\cite[p.~21]{rvismv1v22:2017} Operation: \verb@pc@ $\leftarrow$ \verb@pc+4@ Encoding: \DrawInsnTypeFPicture{FENCE.I}{00000000000000000001000000001111} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{ECALL} \index{Instruction!ECALL} The ECALL instruction is used to make a request to the supporting execution environment, which is usually an operating system. The ABI for the system will define how parameters for the environment request are passed, but usually these will be in defined locations in the integer register file.~\cite[p.~24]{rvismv1v22:2017} \DrawInsnTypeEPicture{ECALL}{00000000000000000000000001110011} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{EBREAK} \index{Instruction!EBREAK} The EBREAK instruction is used by debuggers to cause control to be transferred back to a debugging environment.~\cite[p.~24]{rvismv1v22:2017} \DrawInsnTypeEPicture{EBREAK}{00000000000100000000000001110011} ================================================ FILE: book/rv32/chapter.tex ================================================ \newcommand\instructionHeader[1]{{\large\tt \string#1}} \chapter{RV32 Machine Instructions} \label{chapter:RV32} \index{RV32} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \section{Conventions and Terminology} When discussing instructions, the following abbreviations/notations are used: %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{XLEN} \label{XLEN} XLEN represents the bit-length of an \reg{x} register in the machine architecture. Possible values are 32, 64 and 128. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{sx(val)} \label{extension:sx} Sign extend {\em val} to the left. This is used to convert a signed integer value expressed using some number of bits to a larger number of bits by adding more bits to the left. In doing so, the sign will be preserved. In this case {\em val} represents the least \acrshort{msb}s of the value. For more on sign-extension see \autoref{SignExtension}. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{zx(val)} \label{extension:zx} Zero extend {\em val} to the left. This is used to convert an unsigned integer value expressed using some number of bits to a larger number of bits by adding more bits to the left. In doing so, the new bits added will all be set to zero. As is the case with \verb@sx(val)@, {\em val} represents the \acrshort{lsb}s of the final value. For more on zero-extension see \autoref{ZeroExtension}. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{zr(val)} \label{extension:zr} Zero extend {\em val} to the right. Some times a binary value is encoded such that a set of bits represented by {\em val} are used to represent the \acrshort{msb}s of some longer (more bits) value. In this case it is necessary to append zeros to the right to convert \verb@val@ to the longer value. \autoref{Figure:ZeroRightExtend} illustrates converting a 20-bit {\em val} to a 32-bit fullword. \begin{figure}[ht] \centering \DrawBitBoxSignLeftZeroRightExtendedPicture{32}{01000000000000000010}{12} \captionof{figure}{Zero-extending an integer to the right from 20 bits to 32 bits.} \label{Figure:ZeroRightExtend} \end{figure} %\begin{figure}[ht] %\centering %\parbox{.7\linewidth}{ %\DrawBitBoxUnsignedPicture{01000000000000000010}\\ %\DrawBitBoxUnsignedPicture{01000000000000000010000000000000} %} %\captionof{figure}{Zero-extending an integer to the right from 20 bits to 32 bits.} %\label{Figure:ZeroRightExtend} %\end{figure} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{Sign Extended Left and Zero Extend Right} \label{extension:slzr} Some instructions such as the J-type (see \autoref{insnformat:jtype}) include immediate operands that are extended in both directions. \autoref{Figure:slzrPositive} and \autoref{Figure:slzrNegative} illustrates zero-extending a 20-bit negative number one bit to the right and sign-extending it 11 bits to the left: \begin{figure}[ht] \centering \DrawBitBoxSignLeftZeroRightExtendedPicture{32}{01000100011101001001}{1} \captionof{figure}{Sign-extending a positive 20-bit number 11 bits to the left and one bit to the right.} \label{Figure:slzrPositive} \end{figure} \begin{figure}[ht] \centering \DrawBitBoxSignLeftZeroRightExtendedPicture{32}{11000100011101001001}{1} \captionof{figure}{Sign-extending a negative 20-bit number 11 bits to the left and one bit to the right.} \label{Figure:slzrNegative} \end{figure} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{m8(addr)} \label{memory:m8} The contents of an 8-bit value in memory at address {\em addr}. Given the contents of the memory dump shown in \autoref{Figure:SampleMemoryContents}, \verb@m8(0x42)@ refers to the memory location at address \verb@42@$_{16}$ that currently contains the 8-bit value \verb@fc@$_{16}$. The \verb@m@$_n$\verb@(addr)@ notation can be used to refer to memory that is being read or written depending on the context. When memory is being written, the following notation is used to indicate that the least significant 8 bis of {\em source} will be is written into memory at the address {\em addr}: \verb@m8(addr)@ $\leftarrow$ \verb@source@ When memory is being read, the following notation is used to indicate that the 8 bit value at the address {\em addr} will be read and stored into {\em dest}: \verb@dest@ $\leftarrow$ \verb@m8(addr)@ Note that {\em source} and {\em dest} are typically registers. \begin{figure}[ht] \centering \begin{BVerbatim} 00000030 2f 20 72 65 61 64 20 61 20 62 69 6e 61 72 79 20 00000040 66 69 fc 65 20 66 69 6c 6c 65 64 20 77 69 74 68 00000050 20 72 76 33 32 49 20 69 6e 73 74 72 75 63 74 69 00000060 6f 6e 73 20 61 6e 64 20 66 65 65 64 20 74 68 65 \end{BVerbatim} \captionof{figure}{Sample memory contents.} \label{Figure:SampleMemoryContents} \end{figure} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{m16(addr)} \label{memory:m16} The contents of an 16-bit little-endian value in memory at address {\em addr}. Given the contents of the memory dump shown in \autoref{Figure:SampleMemoryContents}, \verb@m16(0x42)@ refers to the memory location at address \verb@42@$_{16}$ that currently contains \verb@65fc@$_{16}$. See also~\autoref{memory:m8}. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{m32(addr)} \label{memory:m32} The contents of an 32-bit little-endian value in memory at address {\em addr}. Given the contents of the memory dump shown in \autoref{Figure:SampleMemoryContents}, \verb@m32(0x42)@ refers to the memory location at address \verb@42@$_{16}$ that currently contains \verb@662065fc@$_{16}$. See also~\autoref{memory:m8}. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{m64(addr)} The contents of an 64-bit little-endian value in memory at address {\em addr}. Given the contents of the memory dump shown in \autoref{Figure:SampleMemoryContents}, \verb@m64(0x42)@ refers to the memory location at address \verb@42@$_{16}$ that currently contains \verb@656c6c69662065fc@$_{16}$. See also~\autoref{memory:m8}. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{m128(addr)} The contents of an 128-bit little-endian value in memory at address {\em addr}. Given the contents of the memory dump shown in \autoref{Figure:SampleMemoryContents}, \verb@m128(0x42)@ refers to the memory location at address \verb@42@$_{16}$ that currently contains \verb@7220687469772064656c6c69662065fc@$_{16}$. See also~\autoref{memory:m8}. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{.+offset} The address of the current instruction plus a numeric offset. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{.-offset} The address of the current instruction minus a numeric offset. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{pcrel\_13} \label{pcrel.13} An address that is within $[-4096..4094]$ $[$\verb@-0x1000..0x0ffe@$]$ of the current instruction location. These addresses are typically expressed in assembly source code by using labels. See \autoref{insnformat:btype} for examples. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{pcrel\_21} \label{pcrel.21} An address that is within $[-1048576..1048574]$ $[$\verb@-0x100000..0x0ffffe@$]$ of the current instruction location. These addresses are typically expressed in assembly source code by using labels. See \autoref{insnformat:jtype} for an example. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{pc} The current value of the program counter. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{rd} An x-register used to store the result of instruction. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{rs1} An x-register value used as a source operand for an instruction. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{rs2} An x-register value used as a source operand for an instruction. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{imm} An immediate numeric operand. The word {\em immediate} refers to the fact that the operand is stored within an instruction. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{rsN[h:l]} The value of bits from {\em h} through {\em l} of x-register rsN. For example: rs1[15:0] refers to the contents of the 16 \acrshort{lsb}s of rs1. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \section{Addressing Modes} immediate, register, base-displacement, pc-relative \enote{Write this section.} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \section{Instruction Encoding Formats} \label{section:EncodingFormats} %XXX Show and discuss a stack of formats explaining how the unnatural ordering %of the {\em imm} fields reduces the number of possible locations that %the hardware has to be prepared to {\em look} for various bits. For example, %the opcode, rd, rs1, rs1, func3 and the sign bit (when used) are all always %in the same position. Also note that imm[19:12] and imm[10:5] can only be %found in one place. imm[4:0] can only be found in one of two places\ldots This document concerns itself with the RISC-V instruction formats shown in \autoref{Figure:riscvFormats}. %\autoref{Figure:riscvFormats} Shows the RISC-V instruction formats. \begin{figure}[ht] \DrawInsnTypeUTikz{00000000000000000000000000000000}\\ \DrawInsnTypeJTikz{00000000000000000000000000000000}\\ \DrawInsnTypeRTikz{00000000000000000000000000000000} \DrawInsnTypeITikz{00000000000000000000000000000000}\\ \DrawInsnTypeIShiftTikz{00000000000000000000000000000000}\\ \DrawInsnTypeSTikz{00000000000000000000000000000000}\\ \DrawInsnTypeBTikz{00000000000000000000000000000000}\\ \captionof{figure}{RISC-V instruction formats.} \label{Figure:riscvFormats} \end{figure} The method/format of the instructions has been designed with an eye on the ease of future manufacture of the machine that will execute them. It is easier to build a machine if it does not have to accommodate many different ways to perform the same task. The result is that a machine can be built with fewer gates, consumes less power, and can run faster than if it were built when a priority is on how a user might prefer to decode the same instructions from a hex dump. Observe that all instructions have their opcode in bits 0-6 and when they include an \verb@rd@ register it will be specified in bits 7-11, an \verb@rs1@ register in bits 15-19, an \verb@rs2@ register in bits 20-24, and so on. This has a seemingly strange impact on the placement of any immediate operands. When immediate operands are present in an instruction, they are placed in the remaining unused bits. However, they are organized such that the sign bit is {\em always} in bit 31 and the remaining bits placed so as to minimize the number of places any given bit is located in different instructions. For example, consider immediate operand bits 12-19. In the U-type format they are in bit positions 12-19. In the J-type format they are also in positions 12-19. In the J-type format immediate operand bits 1-10 are in the same instruction bit positions as they are in the I-type format and immediate operand bits 5-10 are in the same positions as they are in the B-type and S-type formats. While this is inconvenient for anyone looking at a memory hexdump, it does make sense when considering the impact of this choice on the number of gates needed to implement circuitry to extract the immediate operands. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{U Type} \label{insnformat:utype} The U-Type format is used for instructions that use a 20-bit immediate operand and an \verb@rd@ destination register. %\DrawInsnTypeUTikz{11010110000000000011001010110111} The \reg{rd} field contains an \reg{x} register number to be set to a value that depends on the instruction. %The imm field %contains a 20-bit value that will be converted into \Gls{xlen} bits by %using the {\em imm} operand for bits 31:12 and then sign-extending it %to the left\footnote{When XLEN is larger than 32.} and zero-extending %the LSBs as discussed in \autoref{extension:zr}. If \Gls{xlen}=32 then the {\em imm} value will extracted from the instruction and converted as shown in \autoref{Figure:u_type_decode} to form the \verb@imm_u@ value. \begin{figure}[ht] \centering \DrawInsnOpUTypeDecoding \captionof{figure}{Decoding a U-type instruction.} \label{Figure:u_type_decode} \label{imm.u:decode} \index{imm\protect\_u} \end{figure} Notice that the 20-bits of the imm field are mapped in the same order and in the same relative position that they appear in the instruction when they are used to create the value of the immediate operand. Leaving the imm bits on the left, in the ``upper bits'' of the \verb@imm_u@ value suggests a rationale for the name of this format. \begin{itemize} \item\instructionHeader{lui\ \ \ rd,imm} \label{insn:lui} Set register \verb@rd@ to the \verb@imm_u@ value as shown in \autoref{Figure:u_type_decode}. For example: \verb@lui x23,0x12345@ will result in setting register \verb@x23@ to the value \verb@0x12345000@. \item\instructionHeader{auipc rd,imm} \label{insn:auipc} Add the address of the instruction to the \verb@imm_u@ value as shown \autoref{Figure:u_type_decode} and store the result in register \verb@rd@. For example, if the instruction \verb@auipc x22,0x10001@ is executed from memory address \verb@0x800012f4@ then register \verb@x22@ will be set to \verb@0x900022f4@. \end{itemize} If \Gls{xlen}=64 then the \verb@imm_u@ value in this example will be converted to the same two's complement integer value by extending the sign-bit further to the left. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{J Type} \label{insnformat:jtype} The J-type instruction format is used to encode the \verb@jal@ instruction with an immediate value that determines the jump target address. It is similar to the U-type, but the bits in the immediate operand are arranged in a different order. %\DrawInsnTypeJTikz{00111001001110000001001111101111} Note that the \verb@imm_j@ value is %expressed in the instruction as a target address that is converted to an even 21-bit value in the range of $[-1048576..1048574]$ $[$\verb@-0x100000..0x0ffffe@$]$ representing a \verb@pc@-relative offset to the target address. %In the J-type format the 20 {\em imm} bits are arranged such %that they represent the ``lower'' portion of the immediate value. Unlike %the U-type instructions, the J-type requires the bits to be re-ordered %and shifted to the right before they are used. %\footnote{The reason that the J-type %bits are reordered like this is because it simplifies the implementation of %hardware as discussed in \autoref{section:EncodingFormats}.} %The example above shows that the bit positions in the {\em imm} field %description. We see that the 20 {\em imm} bits are re-ordered according to: %[20\textbar10:1\textbar11\textbar19:12]. %This means that the \acrshort{msb} of the {\em imm} field is to be placed %into bit 20 of the immediate integer value ultimately used by the instruction %when it is converted into \Gls{xlen} bits. %The next bit to the right in the {\em imm} field is to be placed into bit 10 of %the immediate value and so on. %After the {\em imm} bits are re-positioned into bits 20:1 of the immediate value %being constructed, a zero-bit will be added to the \acrshort{lsb} %and the value in bit-position 20 will be replicated to sign-extend the %value to \Gls{xlen} bits as discussed in \autoref{extension:slzr}. If \Gls{xlen}=32 then the {\em imm} value will extracted from the instruction and converted as shown in \autoref{Figure:j_type_decode} to form the \verb@imm_j@ value. \begin{figure}[ht] \centering \DrawInsnOpJTypeDecoding \captionof{figure}{Decoding a J-type instruction.} \label{Figure:j_type_decode} \label{imm.j:decode} \index{imm\protect\_j} \end{figure} %\DrawBitBoxSignLeftZeroRightExtendedPicture{32}{01000000110111001001}{1} % %A J-type example with a negative imm field: % %\DrawInsnTypeJTikz{10111001001110000001001111101111} % %If \Gls{xlen}=32 then the {\em imm} field in this example will be converted as %shown below. % %\DrawBitBoxSignLeftZeroRightExtendedPicture{32}{11000000110111001001}{1} The J-type format is used by the Jump And Link instruction that calculates the target address by adding \verb@imm_j@ to the current program counter. Since no instruction can be placed at an odd address the 20-bit imm value is zero-extended to the right to represent a 21-bit signed offset capable of expressing a wider range of target addresses than the 20-bit imm value alone. \begin{itemize} \item\instructionHeader{jal\ \ \ rd,pcrel\_21} \label{insn:jal} Set register \verb@rd@ to the address of the next instruction that would otherwise be executed (the address of the \verb@jal@ instruction + 4) and then jump to the address given by the sum of the \verb@pc@ register and the \verb@imm_j@ value as decoded from the instruction shown in \autoref{imm.j:decode}. Note that \verb@pcrel_21@ is expressed in the instruction as a target address or label that is converted to a 21-bit value representing a \verb@pc@-relative offset to the target address. For example, consider the \verb@jal@ instructions in the following code: \begin{verbatim} 00000010: 000002ef jal x5,0x10 # jump to self (address 0x10) 00000014: 008002ef jal x5,0x1c # jump to address 0x1c 00000018: 00100073 ebreak 0000001c: 00100073 ebreak \end{verbatim} The instruction at address \verb@0x10@ has a target address of \verb@0x10@ and the \verb@imm_j@ is zero because offset from the ``current instruction'' to the target is zero. The instruction at address \verb@0x14@ has a target address of \verb@0x1c@ and the \verb@imm_j@ is \verb@0x08@ because \verb@0x1c - 0x14 = 0x08@. See also \autoref{insnformat:btype}. \end{itemize} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{R Type} \label{insnformat:rtype} \DrawInsnTypeRTikz{01000001111100011000001110110011} The R-type instructions are used for operations that set a destination register \verb@rd@ to the result of an arithmetic, logical or shift operation applied to source registers \verb@rs1@ and \verb@rs2@. Note that instruction bit 30 (part of the the \verb@funct7@ field) is used to select between the \verb@add@ and \verb@sub@ instructions as well as to select between \verb@srl@ and \verb@sra@. \begin{itemize} \item\instructionHeader{add\ \ \ rd,rs1,rs2} \label{insn:add} Set register \verb@rd@ to \verb@rs1 + rs2@. Note that the value of \verb@funct7@ must be zero for this instruction. (The value of \verb@funct7@ is how the \verb@add@ instruction is differentiated from the \verb@sub@ instruction.) \item\instructionHeader{and\ \ \ rd,rs1,rs2} \label{insn:and} Set register \verb@rd@ to the bitwise \verb@and@ of \verb@rs1@ and \verb@rs2@. For example, if \verb@x17@ = \verb@0x55551111@ and \verb@x18@ = \verb@0xff00ff00@ then the instruction \verb@and x12,x17,x18@ will set \verb@x12@ to the value \verb@0x55001100@. \item\instructionHeader{or\ \ \ \ rd,rs1,rs2} \label{insn:or} Set register \verb@rd@ to the bitwise \verb@or@ of \verb@rs1@ and \verb@rs2@. For example, if \verb@x17@ = \verb@0x55551111@ and \verb@x18@ = \verb@0xff00ff00@ then the instruction \verb@or x12,x17,x18@ will set \verb@x12@ to the value \verb@0xff55ff11@. \item\instructionHeader{sll\ \ \ rd,rs1,rs2} \label{insn:sll} Shift \verb@rs1@ left by the number of bits specified in the least significant 5 bits of \verb@rs2@ and store the result in \verb@rd@.\footnote{\label{shift:xlen} When XLEN is 64 or 128, the shift distance will be given by the least-significant 6 or 7 bits of {\tt rs2} respectively. For more information on how shifting works, see \autoref{shifting}.} For example, if \verb@x17@ = \verb@0x12345678@ and \verb@x18@ = \verb@0x08@ then the instruction \verb@sll x12,x17,x18@ will set \verb@x12@ to the value \verb@0x34567800@. \item\instructionHeader{slt\ \ \ rd,rs1,rs2} \label{insn:slt} If the signed integer value in \verb@rs1@ is less than the signed integer value in \verb@rs2@ then set \verb@rd@ to \verb@1@. Otherwise, set \verb@rd@ to \verb@0@. For example, if \verb@x17@ = \verb@0x12345678@ and \verb@x18@ = \verb@0x0000ffff@ then the instruction \verb@slt x12,x17,x18@ will set \verb@x12@ to the value \verb@0x00000000@. If \verb@x17@ = \verb@0x82345678@ and \verb@x18@ = \verb@0x0000ffff@ then the instruction \verb@slt x12,x17,x18@ will set \verb@x12@ to the value \verb@0x00000001@. \item\instructionHeader{sltu\ \ rd,rs1,rs2} \label{insn:sltu} If the unsigned integer value in \verb@rs1@ is less than the unsigned integer value in \verb@rs2@ then set \verb@rd@ to \verb@1@. Otherwise, set \verb@rd@ to \verb@0@. For example, if \verb@x17@ = \verb@0x12345678@ and \verb@x18@ = \verb@0x0000ffff@ then the instruction \verb@sltu x12,x17,x18@ will set \verb@x12@ to the value \verb@0x00000000@. If \verb@x17@ = \verb@0x12345678@ and \verb@x18@ = \verb@0x8000ffff@ then the instruction \verb@sltu x12,x17,x18@ will set \verb@x12@ to the value \verb@0x00000001@. \item\instructionHeader{sra\ \ \ rd,rs1,rs2} \label{insn:sra} Arithmetic-shift \verb@rs1@ right by the number of bits given in the least-significant 5 bits of the \verb@rs2@ register and store the result in \verb@rd@.\footref{shift:xlen} For example, if \verb@x17@ = \verb@0x87654321@ and \verb@x18@ = \verb@0x08@ then the instruction \verb@sra x12,x17,x18@ will set \verb@x12@ to the value \verb@0xff876543@. If \verb@x17@ = \verb@0x76543210@ and \verb@x18@ = \verb@0x08@ then the instruction \verb@sra x12,x17,x18@ will set \verb@x12@ to the value \verb@0x00765432@. Note that the value of \verb@funct7@ must be zero for this instruction. (The value of \verb@funct7@ is how the \verb@sra@ instruction is differentiated from the \verb@srl@ instruction.) \item\instructionHeader{srl\ \ \ rd,rs1,rs2} \label{insn:srl} Logic-shift \verb@rs1@ right by the number of bits given in the least-significant 5 bits of the \verb@rs2@ register and store the result in \verb@rd@.\footref{shift:xlen} For example, if \verb@x17@ = \verb@0x87654321@ and \verb@x18@ = \verb@0x08@ then the instruction \verb@srl x12,x17,x18@ will set \verb@x12@ to the value \verb@0x00876543@. If \verb@x17@ = \verb@0x76543210@ and \verb@x18@ = \verb@0x08@ then the instruction \verb@srl x12,x17,x18@ will set \verb@x12@ to the value \verb@0x00765432@. Note that the value of \verb@funct7@ must be \verb@0b0100000@ for this instruction. (The value of \verb@funct7@ is how the \verb@srl@ instruction is differentiated from the \verb@sra@ instruction.) \item\instructionHeader{sub\ \ \ rd,rs1,rs2} \label{insn:sub} Set register \verb@rd@ to \verb@rs1 - rs2@. Note that the value of \verb@funct7@ must be \verb@0b0100000@ for this instruction. (The value of \verb@funct7@ is how the \verb@sub@ instruction is differentiated from the \verb@add@ instruction.) \item\instructionHeader{xor\ \ \ rd,rs1,rs2} \label{insn:xor} Set register \verb@rd@ to the bitwise \verb@xor@ of \verb@rs1@ and \verb@rs2@. For example, if \verb@x17@ = \verb@0x55551111@ and \verb@x18@ = \verb@0xff00ff00@ then the instruction \verb@xor x12,x17,x18@ will set \verb@x12@ to the value \verb@0xaa55ee11@. \end{itemize} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{I Type} \label{insnformat:itype} %\DrawInsnTypeITikz{00000000010000011000001110000011} The I-type instruction format is used to encode instructions with a signed 12-bit immediate operand with a range of $[-2048..2047]$, an \verb@rd@ register, and an \verb@rs1@ register. If \Gls{xlen}=32 then the 12-bit {\em imm} value example will extracted from the instruction and converted as shown in \autoref{Figure:i_type_decode} to form the \verb@imm_i@ value. \begin{figure}[ht] \centering \DrawInsnOpITypeDecoding \captionof{figure}{Decoding an I-type Instruction.} \label{Figure:i_type_decode} \label{imm.i:decode} \index{imm\protect\_i} \end{figure} A special case of the I-type is used for shift-immediate instructions where the imm field is used to represent the number of bit positions to shift as shown in \autoref{Figure:shamt_i_type_decode}. In this variation, the least significant five bits of the imm field are extracted to form the \verb@shamt_i@ value.\footnote{When XLEN is 64 or 128, the {\tt shamt\_i} field will consist of 6 or 7 bits respectively.} Note also that bit 30 (the imm instruction field bit labeled `\verb@b@') is used to select between arithmetic and logical shifting. \begin{figure}[ht] \centering \DrawInsnOpIShiftTypeDecoding \captionof{figure}{Decoding an I-type Shift Instruction.} \label{Figure:shamt_i_type_decode} \label{shamt.i:decode} \index{shamt\protect\_i} \end{figure} \begin{figure}[ht] \centering \begin{verbatim} 00002640: 6f 00 00 00 6f 00 00 00 b7 87 00 00 03 a5 07 43 *o...o..........C* 00002650: 67 80 00 00 00 00 00 00 76 61 6c 3d 00 00 00 00 *g.......val=....* 00002660: 00 00 00 00 80 84 2e 41 1f 85 45 41 80 40 9a 44 *.......A..EA.@.D* 00002670: 4f 11 f3 c3 6e 8a 67 41 20 1b 00 00 20 1b 00 00 *O...n.gA ... ...* 00002680: 44 1b 00 00 14 1b 00 00 14 1b 00 00 04 1c 00 00 *D...............* \end{verbatim} \captionof{figure}{An Example Memory Dump.} \label{Figure:imm:memory:dump} \end{figure} \begin{itemize} \item\instructionHeader{addi\ \ rd,rs1,imm} \label{insn:addi} Set register \verb@rd@ to \verb@rs1 + imm_i@. \item\instructionHeader{andi\ \ rd,rs1,imm} \label{insn:andi} Set register \verb@rd@ to the bitwise \verb@and@ of \verb@rs1@ and \verb@imm_i@. For example, if \verb@x17@ = \verb@0x55551111@ then the instruction \verb@andi x12,x17,0x0ff@ will set \verb@x12@ to the value \verb@0x00000011@. Recall that \verb@imm@ is sign-extended. Therefore if \verb@x17@ = \verb@0x55551111@ then the instruction \verb@andi x12,x17,0x800@ will set \verb@x12@ to the value \verb@0x55551000@. \item\instructionHeader{jalr\ \ rd,imm(rs1)} \label{insn:jalr} Set register \verb@rd@ to the address of the next instruction that would otherwise be executed (the address of the \verb@jalr@ instruction + 4) and then jump to an address given by the sum of the \verb@rs1@ register and the \verb@imm_i@ value as decoded from the instruction shown in \autoref{imm.i:decode}. Note that the \verb@pc@ register can never refer to an odd address. This instruction will explicitly set the \acrshort{lsb} to zero regardless of the value of the value of the calculated target address. \item\instructionHeader{lb\ \ \ \ rd,imm(rs1)} \label{insn:lb} Set register \verb@rd@ to the value of the sign-extended byte fetched from the memory address given by the sum of \verb@rs1@ and \verb@imm_i@. For example, given the memory contents shown in \autoref{Figure:imm:memory:dump}, if register \verb@x13@ = \verb@0x00002650@ then the instruction \verb@lb x12,1(x13)@ will set \verb@x12@ to the value \verb@0xffffff80@. \item\instructionHeader{lbu\ \ \ rd,imm(rs1)} \label{insn:lbu} Set register \verb@rd@ to the value of the zero-extended byte fetched from the memory address given by the sum of \verb@rs1@ and \verb@imm_i@. For example, given the memory contents shown in \autoref{Figure:imm:memory:dump}, if register \verb@x13@ = \verb@0x00002650@ then the instruction \verb@lbu x12,1(x13)@ will set \verb@x12@ to the value \verb@0x00000080@. \item\instructionHeader{lh\ \ \ \ rd,imm(rs1)} \label{insn:lh} Set register \verb@rd@ to the value of the sign-extended 16-bit little-endian half-word value fetched from the memory address given by the sum of \verb@rs1@ and \verb@imm_i@. For example, given the memory contents shown in \autoref{Figure:imm:memory:dump}, if register \verb@x13@ = \verb@0x00002650@ then the instruction \verb@lh x12,-2(x13)@ will set \verb@x12@ to the value \verb@0x00004307@. If register \verb@x13@ = \verb@0x00002650@ then the instruction \verb@lh x12,-8(x13)@ will set \verb@x12@ to the value \verb@0xffff87b7@. \item\instructionHeader{lhu\ \ \ rd,imm(rs1)} \label{insn:lhu} Set register \verb@rd@ to the value of the zero-extended 16-bit little-endian half-word value fetched from the memory address given by the sum of \verb@rs1@ and \verb@imm_i@. For example, given the memory contents shown in \autoref{Figure:imm:memory:dump}, if register \verb@x13@ = \verb@0x00002650@ then the instruction \verb@lhu x12,-2(x13)@ will set \verb@x12@ to the value \verb@0x00004307@. If register \verb@x13@ = \verb@0x00002650@ then the instruction \verb@lhu x12,-8(x13)@ will set \verb@x12@ to the value \verb@0x000087b7@. \item\instructionHeader{lw\ \ \ \ rd,imm(rs1)} \label{insn:lw} Set register \verb@rd@ to the value of the sign-extended 32-bit little-endian word value fetched from the memory address given by the sum of \verb@rs1@ and \verb@imm_i@. For example, given the memory contents shown in \autoref{Figure:imm:memory:dump}, if register \verb@x13@ = \verb@0x00002650@ then the instruction \verb@lw x12,-4(x13)@ will set \verb@x12@ to the value \verb@4307a503@. \item\instructionHeader{ori\ \ \ rd,rs1,imm} \label{insn:ori} Set register \verb@rd@ to the bitwise \verb@or@ of \verb@rs1@ and \verb@imm_i@. For example, if \verb@x17@ = \verb@0x55551111@ then the instruction \verb@ori x12,x17,0x0ff@ will set \verb@x12@ to the value \verb@0x555511ff@. Recall that \verb@imm@ is sign-extended. Therefore if \verb@x17@ = \verb@0x55551111@ then the instruction \verb@ori x12,x17,0x800@ will set \verb@x12@ to the value \verb@0xfffff911@. \item\instructionHeader{slli\ \ rd,rs1,imm} \label{insn:slli} Shift \verb@rs1@ left by the number of bits specified in \verb@shamt_i@ (as shown in \autoref{shamt.i:decode}) and store the result in \verb@rd@.\footnote{\label{shifti:xlen} When XLEN is 64 or 128, the shift distance will be given by the least-significant 6 or 7 bits of the imm field respectively. For more information on how shifting works, see \autoref{shifting}.} For example, if \verb@x17@ = \verb@0x12345678@ then the instruction \verb@slli x12,x17,4@ will set \verb@x12@ to the value \verb@0x23456780@. \item\instructionHeader{slti\ \ rd,rs1,imm} \label{insn:slti} If the signed integer value in \verb@rs1@ is less than the signed integer value in \verb@imm_i@ then set \verb@rd@ to \verb@1@. Otherwise, set \verb@rd@ to \verb@0@. \item\instructionHeader{sltiu\ rd,rs1,imm} \label{insn:sltiu} If the unsigned integer value in \verb@rs1@ is less than the unsigned integer value in \verb@imm_i@ then set \verb@rd@ to \verb@1@. Otherwise, set \verb@rd@ to \verb@0@. Note that \verb@imm_i@ is always created by sign-extending the \verb@imm@ value as shown in \autoref{imm.i:decode} even though it is then later used as an unsigned integer for the purposes of comparing its magnitude to the unsigned value in rs1. Therefore, this instruction provides a method to compare \verb@rs1@ to a value in the ranges of $[\text{\tt 0}..\text{\tt 0x7ff}]$ and $[\text{\tt 0xfffff800}..\text{\tt 0xffffffff}]$. \item\instructionHeader{srai\ \ rd,rs1,imm} \label{insn:srai} Arithmetic-shift \verb@rs1@ right by the number of bits specified in \verb@shamt_i@ (as shown in \autoref{shamt.i:decode}) and store the result in \verb@rd@.\footref{shifti:xlen} For example, if \verb@x17@ = \verb@0x87654321@ then the instruction \verb@srai x12,x17,4@ will set \verb@x12@ to the value \verb@0xf8765432@. Note that the value of bit 30 must be 1 for this instruction. (The value of bit 30 is how the \verb@srai@ instruction is differentiated from the \verb@srli@ instruction.) \item\instructionHeader{srli\ \ rd,rs1,imm} \label{insn:srli} Logic-shift \verb@rs1@ right by the number of bits specified in \verb@shamt_i@ (as shown in \autoref{shamt.i:decode}) and store the result in \verb@rd@.\footref{shifti:xlen} For example, if \verb@x17@ = \verb@0x87654321@ then the instruction \verb@srli x12,x17,4@ will set \verb@x12@ to the value \verb@0x08765432@. Note that the value of bit 30 must be 0 for this instruction. (The value of bit 30 is how the \verb@srli@ instruction is differentiated from the \verb@srai@ instruction.) \item\instructionHeader{xori\ \ rd,rs1,imm} \label{insn:xori} Set register \verb@rd@ to the bitwise \verb@xor@ of \verb@rs1@ and \verb@imm_i@. For example, if \verb@x17@ = \verb@0x55551111@ then the instruction \verb@xori x12,x17,0x0ff@ will set \verb@x12@ to the value \verb@0x555511ee@. Recall that \verb@imm@ is sign-extended. Therefore if \verb@x17@ = \verb@0x55551111@ then \verb@xori x12,x17,0x800@ will set \verb@x12@ to the value \verb@0xaaaae911@. \end{itemize} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{S Type} \label{insnformat:stype} %\DrawInsnTypeSTikz{00000000111100011000100110100011} The S-type instruction format is used to encode instructions with a signed 12-bit immediate operand with a range of $[-2048..2047]$, an \verb@rs1@ register, and an \verb@rs2@ register. If \Gls{xlen}=32 then the 12-bit {\em imm} value example will extracted from the instruction and converted as shown \autoref{Figure:imm_s_type_decode} to form the \verb@imm_s@ value. \begin{figure}[ht] \centering \DrawInsnOpSTypeDecoding \captionof{figure}{Decoding an S-type Instruction.} \label{Figure:imm_s_type_decode} \label{imm.s:decode} \index{imm\protect\_s} \end{figure} \begin{itemize} \item\instructionHeader{sb\ \ \ \ rs2,imm(rs1)} \label{insn:sb} Set the byte of memory at the address given by the sum of \verb@rs1@ and \verb@imm_s@ to the 8 \acrshort{lsb}s of \verb@rs2@. For example, given the memory contents shown in \autoref{Figure:imm:memory:dump}, if registers \verb@x13@ = \verb@0x00002650@ and \verb@x12@ = \verb@0x12345678@ then the instruction \verb@sb x12,1(x13)@ will change the memory byte at address \verb@0x00002651@ from \verb@0x80@ to \verb@0x78@ resulting in: \begin{verbatim} 00002640: 6f 00 00 00 6f 00 00 00 b7 87 00 00 03 a5 07 43 *o...o..........C* 00002650: 67 78 00 00 00 00 00 00 76 61 6c 3d 00 00 00 00 *gx......val=....* 00002660: 00 00 00 00 80 84 2e 41 1f 85 45 41 80 40 9a 44 *.......A..EA.@.D* 00002670: 4f 11 f3 c3 6e 8a 67 41 20 1b 00 00 20 1b 00 00 *O...n.gA ... ...* 00002680: 44 1b 00 00 14 1b 00 00 14 1b 00 00 04 1c 00 00 *D...............* \end{verbatim} \item\instructionHeader{sh\ \ \ \ rs2,imm(rs1)} \label{insn:sh} Set the 16-bit half-word of memory at the address given by the sum of \verb@rs1@ and \verb@imm_s@ to the 16 \acrshort{lsb}s of \verb@rs2@. For example, given the memory contents shown in \autoref{Figure:imm:memory:dump}, if registers \verb@x13@ = \verb@0x00002650@ and \verb@x12@ = \verb@0x12345678@ then the instruction \verb@sh x12,2(x13)@ will change the memory half-word at address \verb@0x00002652@ from \verb@0x0000@ to \verb@0x5678@ resulting in: \begin{verbatim} 00002640: 6f 00 00 00 6f 00 00 00 b7 87 00 00 03 a5 07 43 *o...o..........C* 00002650: 67 80 78 56 00 00 00 00 76 61 6c 3d 00 00 00 00 *g.xV....val=....* 00002660: 00 00 00 00 80 84 2e 41 1f 85 45 41 80 40 9a 44 *.......A..EA.@.D* 00002670: 4f 11 f3 c3 6e 8a 67 41 20 1b 00 00 20 1b 00 00 *O...n.gA ... ...* 00002680: 44 1b 00 00 14 1b 00 00 14 1b 00 00 04 1c 00 00 *D...............* \end{verbatim} \item\instructionHeader{sw\ \ \ \ rs2,imm(rs1)} \label{insn:sw} Store the 32-bit value in \verb@rs2@ into the memory at the address given by the sum of \verb@rs1@ and \verb@imm_s@. For example, given the memory contents shown in \autoref{Figure:imm:memory:dump}, if registers \verb@x13@ = \verb@0x00002650@ and \verb@x12@ = \verb@0x12345678@ then the instruction \verb@sw x12,0(x13)@ will change the memory word at address \verb@0x00002650@ from \verb@0x00008067@ to \verb@0x12345678@ resulting in: \begin{verbatim} 00002640: 6f 00 00 00 6f 00 00 00 b7 87 00 00 03 a5 07 43 *o...o..........C* 00002650: 78 56 34 12 00 00 00 00 76 61 6c 3d 00 00 00 00 *xV4.....val=....* 00002660: 00 00 00 00 80 84 2e 41 1f 85 45 41 80 40 9a 44 *.......A..EA.@.D* 00002670: 4f 11 f3 c3 6e 8a 67 41 20 1b 00 00 20 1b 00 00 *O...n.gA ... ...* 00002680: 44 1b 00 00 14 1b 00 00 14 1b 00 00 04 1c 00 00 *D...............* \end{verbatim} \end{itemize} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{B Type} \label{insnformat:btype} %\DrawInsnTypeBTikz{00000000111100011000100011100011} The B-type instruction format is used for branch instructions that require an even immediate value that is used to determine the branch target address as an offset from the current instruction's address. If \Gls{xlen}=32 then the 12-bit {\em imm} value example will extracted from the instruction and converted as shown in \autoref{Figure:imm_b_type_decode} to form the \verb@imm_b@ value. \begin{figure}[ht] \centering \DrawInsnOpBTypeDecoding \captionof{figure}{Decoding a B-type Instruction.} \label{Figure:imm_b_type_decode} \label{imm.b:decode} \index{imm\protect\_b} \end{figure} Note that \verb@imm_b@ is expressed in the instruction as a target address that is converted to an even 13-bit value in the range of $[-4096..4094]$ $[$\verb@-0x1000..0x0ffe@$]$ representing a \verb@pc@-relative offset to the target address. For example, consider the branch instructions in the following code: \begin{verbatim} 00000000: 00520063 beq x4,x5,0x0 # branches to self (address 0x0) 00000004: 00520463 beq x4,x5,0xc # branches to address 0xc 00000008: fe520ce3 beq x4,x5,0x0 # branches to address 0x0 0000000c: 00100073 ebreak \end{verbatim} The instruction at address \verb@0x0@ has a target address of zero and \verb@imm_b@ is zero because the offset from the ``current instruction'' to the target is zero.\footnote{This is in contrast to many other instruction sets with {\tt pc}-relative addressing modes that express a branch target offset from the ``next instruction.''} The instruction at address \verb@0x4@ has a target address of \verb@0xc@ and it has an \verb@imm_b@ of \verb@0x08@ because \verb@0x4 + 0x08 = 0x0c@. The instruction at address \verb@0x8@ has a target address of zero and \verb@imm_b@ is \verb@0xfffffff8@ (-8) because \verb@0x8 + 0xfffffff8 = 0x0@. \begin{itemize} \item\instructionHeader{beq\ \ \ rs1,rs2,pcrel\_13} \label{insn:beq} If \verb@rs1@ is equal to \verb@rs2@ then add \verb@imm_b@ to the \verb@pc@ register. \item\instructionHeader{bge\ \ \ rs1,rs2,pcrel\_13} \label{insn:bge} If the signed value in \verb@rs1@ is greater than or equal to the signed value in \verb@rs2@ then add \verb@imm_b@ to the \verb@pc@ register. \item\instructionHeader{bgeu\ \ rs1,rs2,pcrel\_13} \label{insn:bgeu} If the unsigned value in \verb@rs1@ is greater than or equal to the unsigned value in \verb@rs2@ then add \verb@imm_b@ to the \verb@pc@ register. \item\instructionHeader{blt\ \ \ rs1,rs2,pcrel\_13} \label{insn:blt} If the signed value in \verb@rs1@ is less than the signed value in \verb@rs2@ then add \verb@imm_b@ to the \verb@pc@ register. \item\instructionHeader{bltu\ \ rs1,rs2,pcrel\_13} \label{insn:bltu} If the unsigned value in \verb@rs1@ is less than the unsigned value in \verb@rs2@ then add \verb@imm_b@ to the \verb@pc@ register. \item\instructionHeader{bne\ \ \ rs1,rs2,pcrel\_13} \label{insn:bne} If \verb@rs1@ is not equal to \verb@rs2@ then add \verb@imm_b@ to the \verb@pc@ register. \end{itemize} %\label{insn:bgt} %\label{insn:ble} %\label{insn:bgtu} %\label{insn:beqz} %\label{insn:bnez} %\label{insn:blez} %\label{insn:bgez} %\label{insn:bltz} %\label{insn:bgtz} %Control and Status Register Instructions %\label{insn:csrrw} %\label{insn:csrrs} %\label{insn:csrrc} %\label{insn:csrrwi} %\label{insn:csrrsi} %\label{insn:csrrci} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \section{CPU Registers} \label{cpuregs} The registers are names x0 through x31 and have aliases suited to their conventional use. The following table describes each register. Note \enote{Need to add a section that discusses the calling conventions} that the calling calling convention specifies that only some of the registers are to be saved by functions if they alter their contents. The idea being that accessing memory is time-consuming and that by classifying some registers as ``temporary'' (not saved by any function that alter its contents) it is possible to carefully implement a function with less need to store register values on the stack in order to use them to perform the operations of the function. The lack of grouping the temporary and saved registers is due to the fact that the E extension %\cite{XXX} only has the first 16 registers and some of the instructions in the C extension %See \autoref{rv32:c} can only refer to the first 16 registers. \begin{center} \begin{tabular}{|l|l|l|l|} \hline Reg & ABI/Alias & Description & Saved \\ \hline \hline \verb@x0@ & \verb@zero@ & Hard-wired zero & \\ \verb@x1@ & \verb@ra@ & Return address & \\ \verb@x2@ & \verb@sp@ & Stack pointer & yes \\ \verb@x3@ & \verb@gp@ & Global pointer & \\ \verb@x4@ & \verb@tp@ & Thread pointer & \\ \verb@x5@ & \verb@t0@ & Temporary/alternate link register & \\ \verb@x6-7@ & \verb@t1-2@ & Temporaries & \\ \verb@x8@ & \verb@s0/fp@ & Saved register/frame pointer & yes \\ \verb@x9@ & \verb@s1@ & Saved register & yes \\ \verb@x10-11@ & \verb@a0-1@ & Function arguments/return value & \\ \verb@x12-17@ & \verb@a2-7@ & Function arguments & \\ \verb@x18-27@ & \verb@s2-11@ & Saved registers & yes \\ \verb@x28-31@ & \verb@t3-6@ & Temporaries & \\ \hline \end{tabular} \end{center} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \section{memory} Note that RISC-V is a little-endian machine. All instructions must be naturally aligned to their 4-byte boundaries.~\cite[p.~5]{rvismv1v22:2017} If a RISC-V processor implements the C (compressed) extension then instructions may be aligned to 2-byte boundaries.\cite[p.~68]{rvismv1v22:2017} Data alignment is not necessary but unaligned data can be inefficient. Accessing unaligned data using any of the load or store instructions can also prevent a memory access from operating atomically.~\cite[p.19]{rvismv1v22:2017} %See also \autoref{RV32A}. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %\input{base.tex} ================================================ FILE: book/rv32/insn/lui.tex ================================================ \DrawInsnTypeUPicture{LUI t0, 3}{00000000000000000011001010110111} \begin{verbatim} 00010074: 000032b7 lui x5, 0x3 // x5 = 0x3000 reg 0: 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 00003000 f0f0f0f0 f0f0f0f0 reg 8: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 reg 16: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 reg 24: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 pc: 00010078 \end{verbatim} \DrawInsnTypeUPicture{LUI t0, 0xfffff}{11111111111111111111001010110111} \begin{verbatim} 00010078: fffff2b7 lui x5, 0xfffff // x5 = 0xfffff000 reg 0: 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 fffff000 f0f0f0f0 f0f0f0f0 reg 8: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 reg 16: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 reg 24: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 pc: 0001007c \end{verbatim} ================================================ FILE: book/rv32m/chapter.tex ================================================ \chapter{RV32M Standard Extension} \label{chapter:rv32m} \index{RV32M} \section{Introduction} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 32-bit integer multiply and divide instructions. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{MUL rd, rs1, rs2} \index{Instruction!MUL} Multiply \reg{rs1} by \reg{rs2} and store the least significant 32-bits of the result in \reg{rd}. \DrawInsnTypeRPicture{MUL x7, x3, x31}{00000011111100111000001110110011} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{MULH rd, rs1, rs2} \index{Instruction!MULH} \DrawInsnTypeRPicture{MULH x7, x3, x31}{00000011111100111001001110110011} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{MULHS rd, rs1, rs2} \index{Instruction!MULHS} \DrawInsnTypeRPicture{MULHS x7, x3, x31}{00000011111100111010001110110011} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{MULHU rd, rs1, rs2} \index{Instruction!MULHU} \DrawInsnTypeRPicture{MULHU x7, x3, x31}{00000011111100111011001110110011} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{DIV rd, rs1, rs2} \index{Instruction!DIV} \DrawInsnTypeRPicture{DIV x7, x3, x31}{00000011111100111100001110110011} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{DIVU rd, rs1, rs2} \index{Instruction!DIVU} \DrawInsnTypeRPicture{DIVU x7, x3, x31}{00000011111100111101001110110011} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{REM rd, rs1, rs2} \index{Instruction!REM} \DrawInsnTypeRPicture{REM x7, x3, x31}{00000011111100111110001110110011} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{REMU rd, rs1, rs2} \index{Instruction!REMU} \DrawInsnTypeRPicture{REMU x7, x3, x31}{00000011111100111111001110110011} ================================================ FILE: book/rvalp.tex ================================================ %\documentclass[oneside,draft,letterpaper]{book} %\documentclass[letterpaper]{book} \documentclass[oneside,letterpaper]{book} \input{preamble} \input{colors} \input{insnformats} \usepackage{ENote} %\usepackage{showframe} \hypersetup{ pdfauthor={John Winans}, pdftitle={RISC-V Assembly Language Programming (Draft \GitRevision{})}, pdfkeywords={RISC-V} {Assembler} } \makeindex %\makeglossaries \makenoidxglossaries \include{glossary} %\includeonly{refcard/chapter} \begin{document} \include{indexrefs} % The see-references for the index % Why does this (apparently) have to go here???? \newlength{\fullwidth} \setlength{\fullwidth}{\the\textwidth} \addtolength{\fullwidth}{\the\marginparsep} \addtolength{\fullwidth}{\the\marginparwidth} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \frontmatter \title{RISC-V\\Assembly Language Programming\\{\normalsize (Draft \GitRevision{})}} \author{John Winans\\ \href{mailto:jwinans@niu.edu}{\sf jwinans@niu.edu}} %\date{May } \maketitle \include{copyright/chapter} \tableofcontents %\listoffigures \setlength{\parskip}{10pt} \include{preface/chapter} \mainmatter %\include{preface/chapter} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % there should be one include here for each chapter %\part{Introduction} \include{intro/chapter} \include{binary/chapter} \include{elements/chapter} \include{programs/chapter} \include{rv32/chapter} %\include{priv/chapter} %\include{rv32m/chapter} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % These 'chapters' are lettered rather than numbered \appendix %\include{insnsummary/chapter} % no longer neded with expanded refcard \include{install/chapter} %\include{toolchain/chapter} \include{float/chapter} \include{ascii/chapter} \include{license/chapter} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \backmatter % putting a chapter here causes it to be unnumbered \bibliography{bibliography} \addcontentsline{toc}{chapter}{Bibliography} \nocite{*} % force all bib items to file appear even if not cited %\bibliographystyle{alpha} \bibliographystyle{ieeetr} %\phantomsection \glsaddall \printnoidxglossaries %\printglossary \phantomsection \addcontentsline{toc}{chapter}{\indexname} \printindex \include{refcard/chapter} \end{document} ================================================ FILE: book/toolchain/chapter.tex ================================================ \chapter{Using The RISC-V GNU Toolchain} This chapter discusses using the GNU toolchain elements to experiment with the material in this book. See \autoref{chapter:install} if you do not already have the GNU crosscompiler toolchain available on your system. Discuss the choice of ilp32 as well as what the other variations would do. Discuss rv32im and note that the details are found in \autoref{chapter:RV32}. Discuss installing and using one of the RISC-V simulators here. Describe the pre-processor, compiler, assembler and linker. Source, object, and binary files Assembly syntax (label: mnemonic op1, op2, op3 \# comment). text, data, bss, stack Labels and scope. Forward \& backward references to throw-away labels. The entry address of an application. .s file contain assembler code. .S (or .sx) files contain assembler code that must be preprocessed.~\cite[p.~29]{gcc:2017} Pre-processing conditional assembly using \#if. Building with \verb@-mabi=ilp32 -march=rv32i -mno-fdiv -mno-div@ to match the config options on the toolchain. Linker scripts. Makefiles objdump nm hexdump -C ================================================ FILE: texlib/ENote.sty ================================================ \NeedsTeXFormat{LaTeX2e} \ProvidesPackage{ENote} [2002/03/23 v1 John Winans's editor notes facilities% ] % % A simple way to provide book-editor notes that can be % automatically turned off. % %\newcommand{\enote}[1]{\marginpar{\raggedright\small\sffamily \ding{209} Note: \vskip 3pt \hrule \vskip 1pt \scriptsize\slshape #1 \vskip 1pt \hrule}} %\newcommand{\enote}[1]{\mbox{}\marginpar{\raggedright\small\sffamily Editor's Note: \vskip 3pt \hrule \vskip 1pt \scriptsize\slshape #1 \vskip 1pt \hrule}} \newcommand{\enote}[1]{\mbox{}\marginpar{\raggedright\small\sffamily \ding{253} Fix Me:\vskip 3pt \hrule \vskip 1pt \scriptsize\slshape #1 \vskip 1pt \hrule}} \newcommand{\marginwarn}[1]{\mbox{}\marginpar{\raggedright\small\sffamily Warning: \vskip 3pt \hrule \vskip 1pt \scriptsize\slshape #1 \vskip 1pt \hrule}} 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\label{#3}}% {\end{figure}} \newenvironment{EpsFig1}[3]{% \begin{figure} \includegraphics[width=\textwidth]{#1} \caption{#2} \label{#3}}% {\end{figure}} \newenvironment{EpsFig2}[3]{% \begin{figure} \includegraphics[width=\fullwidth]{#1} \caption{#2} \label{#3}}% {\end{figure}} \newenvironment{EpsFigRot}[3]{% \begin{sidewaysfigure}\epsfig{height=\MySidewaysFigWidth,file=#1} \caption{#2} \label{#3}}% {\end{sidewaysfigure}} % #1 = file name % #2 = caption % #3 = includegraphics parms \newcommand{\GraphicFigFloating}[3]{% \begin{figure} \begin{center} \includegraphics[#3]{#1} \end{center} \caption{#2} \label{detokenize{Graphic:#2}}% \end{figure}} \newcommand{\GraphicFig}[3]{% \begin{minipage}{\textwidth} \begin{center} \includegraphics[#3]{#1} \captionof{figure}{#2}\label{detokenize{Graphic:#1}} \end{center} \end{minipage}% } \newcommand{\xGraphicFig}[3]{% \begin{center} \includegraphics[#3]{#1} \captionof{figure}{#2}\label{detokenize{Graphic:#1}} \end{center} % } \newcommand{\GraphicFigRef}[1]{% \autoref{detokenize{Graphic:#1}}% } \endinput ================================================ FILE: texlib/MyVerbatim.sty ================================================ \NeedsTeXFormat{LaTeX2e} \ProvidesPackage{MyVerbatim} [2002/03/23 v1 John Winans's verbatim facilities% ] \newlength{\bvwidth} \setlength{\bvwidth}{\textwidth} %\addtolength{\bvwidth}{\marginparsep} %\addtolength{\bvwidth}{\marginparwidth} %\addtolength{\bvwidth}{-7pt} \addtolength{\bvwidth}{-1pt} % A low quality boxed verbatim environment %\newenvironment{boxedverbatim}% % {\VerbatimEnvironment \begin{Sbox}\begin{minipage}{\bvwidth}\footnotesize\begin{Verbatim}}% % {\end{Verbatim}\end{minipage}\end{Sbox} \setlength{\fboxsep}{1mm}\noindent\fbox{\TheSbox}} % A figure-generating boxed verbatim environment % % #1: Filename % #2: Caption % #3: Label \newcommand\VFTitle{X} \newcommand\VFCaption{X} \newcommand\VFLabel{X} % \begin{Code}{The Title} % xxx % \end{Code} \newenvironment{Code}[1]{% \renewcommand\VFTitle{#1}% \VerbatimEnvironment% \begin{Sbox}\begin{minipage}{\bvwidth}\footnotesize\begin{Verbatim}}% {\end{Verbatim}\end{minipage}\end{Sbox} \bigskip\noindent\setlength{\fboxsep}{.5mm}\framebox[\bvwidth][l]{\textsf{\small\bfseries\VFTitle}}\\ \framebox[\bvwidth][l]{\TheSbox}\bigskip} % This only exists so that we can show a Code environment within one \newenvironment{CodeAlt}[1]{% \renewcommand\VFTitle{#1}% \VerbatimEnvironment% \begin{Sbox}\begin{minipage}{\bvwidth}\footnotesize\begin{Verbatim}}% {\end{Verbatim}\end{minipage}\end{Sbox} \bigskip\noindent\setlength{\fboxsep}{.5mm}\framebox[\bvwidth][l]{\textsf{\small\bfseries\VFTitle}}\\ \framebox[\bvwidth][l]{\TheSbox}\bigskip} \newenvironment{CodeFig}[3]{% \renewcommand\VFTitle{#1}% \renewcommand\VFCaption{#2}% \renewcommand\VFLabel{#3}% \VerbatimEnvironment% \begin{Sbox}\begin{minipage}{\bvwidth}\footnotesize\begin{Verbatim}}% {\end{Verbatim}\end{minipage}\end{Sbox} \setlength{\fboxsep}{.5mm}\begin{figure}[ht]\framebox[\bvwidth][l]{\textsf{\small\bfseries\VFTitle}}\\ \framebox[\bvwidth][l]{\TheSbox}\caption{\VFCaption}\label{\VFLabel}\end{figure}} % This only exists so that we can show a CodeFig environment within one \newenvironment{CodeFigAlt}[3]{% \renewcommand\VFTitle{#1}% \renewcommand\VFCaption{#2}% \renewcommand\VFLabel{#3}% \VerbatimEnvironment% \begin{Sbox}\begin{minipage}{\bvwidth}\footnotesize\begin{Verbatim}}% {\end{Verbatim}\end{minipage}\end{Sbox} \setlength{\fboxsep}{.5mm}\begin{figure}[ht]\framebox[\bvwidth][l]{\textsf{\small\bfseries\VFTitle}}\\ \framebox[\bvwidth][l]{\TheSbox}\caption{\VFCaption}\label{\VFLabel}\end{figure}} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \newenvironment{CodeFigB}[2]{% \renewcommand\VFCaption{#1}% \renewcommand\VFLabel{#2}% \VerbatimEnvironment% \begin{Sbox}\begin{minipage}{\bvwidth}\footnotesize\begin{Verbatim}}% {\end{Verbatim}\end{minipage}\end{Sbox} \setlength{\fboxsep}{.5mm}\begin{figure}[ht]\framebox[\bvwidth][l]{\TheSbox}\caption{\VFCaption}\label{\VFLabel}\end{figure}} \newenvironment{CodeFigBAlt}[2]{% \renewcommand\VFCaption{#1}% \renewcommand\VFLabel{#2}% \VerbatimEnvironment% \begin{Sbox}\begin{minipage}{\bvwidth}\footnotesize\begin{Verbatim}}% {\end{Verbatim}\end{minipage}\end{Sbox} \setlength{\fboxsep}{.5mm}\begin{figure}[ht]\framebox[\bvwidth][l]{\TheSbox}\caption{\VFCaption}\label{\VFLabel}\end{figure}} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % % Define verbatim things each with their own type. % \newcommand\email{\begingroup \urlstyle{sf}\Url} \newcommand\filename{\begingroup \urlstyle{sf}\Url} \newcommand\code{\begingroup \urlstyle{tt}\Url} \endinput ================================================ FILE: texlib/index.ist ================================================ % Style for makeindex % This style simply adds a bolded letter for each part of the alphabet heading_prefix "{\\bfseries " heading_suffix "\\hfil}\\nopagebreak\n" headings_flag 1