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\\0V\\0i\\0s\\0i\\0\\x62\\0i\\0l\\0i\\0t\\0y\\0\\0\\0\\x2\\xe3\\0\\0\\x1\\x87\\0\\0\\0\\x14\\0\\0\\0\\x14\\0\\0\\0\\x2\\0\\0\\x6@\\0\\0\\0\\x63\\xfc\\x1\\0\\0\\0\\x1\\xfb\\0\\0\\0\\b\\0M\\0\\x65\\0n\\0u\\x1\\0\\0\\0\\0\\0\\0\\x6@\\0\\0\\0\\0\\0\\xff\\xff\\xff\\0\\0\\0\\x3\\0\\0\\x4\\xf4\\0\\0\\0\\xd6\\xfc\\x1\\0\\0\\0\\x3\\xfb\\0\\0\\0\\f\\0O\\0u\\0t\\0p\\0u\\0t\\x1\\0\\0\\x1L\\0\\0\\x3&\\0\\0\\0P\\0\\xff\\xff\\xff\\xfb\\0\\0\\0\\x18\\0\\x43\\0o\\0n\\0t\\0\\x65\\0x\\0t\\0 \\0H\\0\\x65\\0l\\0p\\x1\\0\\0\\x4v\\0\\0\\x1\\xca\\0\\0\\0P\\0\\xff\\xff\\xff\\xfb\\0\\0\\0\\x1c\\0\\x41\\0\\x64\\0\\x64\\0r\\0\\x65\\0s\\0s\\0 \\0\\x45\\0\\x64\\0i\\0t\\0o\\0r\\0\\0\\0\\0\\0\\xff\\xff\\xff\\xff\\0\\0\\x1*\\0\\xff\\xff\\xff\\0\\0\\x4\\xf4\\0\\0\\x3Y\\0\\0\\0\\x4\\0\\0\\0\\x4\\0\\0\\0\\x1\\0\\0\\0\\x2\\xfc\\0\\0\\0\\0)\r\nDesign\\Geometry=@ByteArray(\\x1\\xd9\\xd0\\xcb\\0\\x1\\0\\0\\xff\\xff\\xff\\xf8\\xff\\xff\\xff\\xf8\\0\\0\\x6G\\0\\0\\x4\\xb7\\0\\0\\x1 \\0\\0\\0\\xe3\\0\\0\\x5\\x1f\\0\\0\\x3\\xe2\\0\\0\\0\\0\\x2\\0)\r\nDesign\\WindowPosition=@Point(-8 -8)\r\nDesign\\ConfigurationVisibility=true\r\nDesign\\SystemDetailsVisibility=true\r\nDesign\\ConnectionVisibility=true\r\nDesign\\InstanceVisibility=true\r\nDesign\\AdHocVisibility=false\r\nDesign\\AddressVisibility=false\r\nDesign\\InterfaceVisibility=true\r\nDesign\\LibraryVisibility=true\r\nDesign\\OutputVisibility=true\r\nDesign\\ContextHelpVisibility=true\r\nDesign\\PreviewVisibility=true\r\nCurrentWorkspace=Default\r\n" }, { "path": "Administrative/releaseFiles/Library/tut.fi/global.communication/iptlm/1.1/TLMW.1.1.xml", "content": "\nCommunity Guidelines
\r\n\r\n Issues should be reported at Kactus2 project Github\r\n\t\thttps://github.com/kactus2/kactus2dev\r\n
\r\n\r\n Otherwise support is provided by email: kactus2@tuni.fi\r\n
\r\n\r\n When contributing to Kactus2, you should see the wiki at the project management site.\r\n It will guide on essentials like building with Visual Studio and plugin development.\r\n Contributions to Kactus2 core, the IP-XACTmodels library, and the plugins provided by Tampere University will not make to\r\n a release unless we accept them and you agree to transfer the copyrights of the changes to Tampere University.\r\n
\r\nWhen creating a plugin, you may keep it closed or open source, and the copyright stays with you.
\r\n\r\n\r\n" }, { "path": "Help/componenteditor/addressblock.html", "content": "\n\n\n \n \nAddress block editor
\n\n Address block editor is used to edit the details of an address block and the registers\n contained within it.\n
\n\n Name is a mandatory identifier for the address block. The name must\n be unique within all the address blocks of the containing memory map.\n
\n\n Display name is an optional and used for a more user-friendly identifier.\n
\n\n Description is an optional field for textual description of the address block.\n
\n\n Base address is mandatory and specifies the starting address for the address\n block in address unit bits.\n
\n\n Range is mandatory and specifies the size of the block in address units bits.\n
\n\n Width is mandatory and defines the data width of a row in the address block.\n The width value is given in bits.\n
\n\n\t\n Is present is optional and allows enabling/disabling of a address block\n presence in a memory map. Value 1 indicates that the address block\n is present in the memory map whereas value 0 marks the address block to be\n treated as if it does not exist. Is present can be given as a SystemVerilog expression,\n but it must evaluate to 1 or 0.
\n\t\n\n
\n Usage is a mandatory value to specify the usage of the address block and\n may have one of the following values:\n
\n- \n
- Memory The address block is ROM, RAM or write-only memory as defined\n by access. Registers and register files within will be considered virtual. \n
- Register The address block range may contain registers. \n
- Reserved The address block is reserved for other usage and shall not\n contain registers or register files. \n
\n Access is optional and specifies the accessability of the address block.\n The possible values are:\n
\n- \n
- read-write. Both read and write transactions may have an effect on this \n address block. \n
- read-only. Only read transactions are allowed in this address block. \n
- write-only. Only write transactions are allowed in this address block. \n
- read-writeOnce. Read actions and the first write action may have an effect\n on this address block. \n
- writeOnce. Only the first write action affects the contents of this address\n block. \n
\n Volatile is optional and indicates whether the stored value may change without\n the master's write operation or not.\n
\n\nRegisters table
\n\n The register table enables the user to define registers for the address block,\n with each row representing a single register. Each register must also contain at\n least one bit field.\n
\n\n\n Name is a mandatory identifier for the register.
\n\n Offset is mandatory and specifies the location of the register from\n the start of the containing address block expressed as number of addressing\n units. The actual address of the register is the sum of address block's\n base address and the register offset. E.g. if the base address is 'h100 and\n the register offset is 'h4, the register's address is 'h104. Offset can be given\n as a SystemVerilog expression.\n
\n\n Size is mandatory and defines the number of data bits the register\n contains. Size must be less than or equal to the width of the containing address\n block.\n
\n\n Dimension is optional and assigns an array dimension to the register.\n The register will be repeated in the address block as many times as\n indicated by the dimension value. By default, the dimension is presumed to be 0.\n Dimension 0 means that the register is not an array and will appear exactly\n once.\n
\n\n Volatile is optional and indicates whether the register value may\n change without a write operation to it, i.e. by an interrupt event, or not.\n
\n\n Access is optional and specifies the accessibility of the register.\n The possible values are:\n
\n- \n
- read-write. Both read and write transactions may have an effect on this \n register. \n
- read-only. Only read transactions are allowed in this register. \n
- write-only. Only write transactions are allowed in this register. \n
- read-writeOnce. Both read and write transactions may have an effect on this\n register. Only the first write transaction, after an event that caused the\n reset value of the register to be loaded, may affet the contents of the register,\n and read transactions return a value related to the values in the register. \n
- writeOnce. Only the first write transaction affects the contents of the \n register. \n
\n Is present is optional and allows enabling/disabling of a register\n presence in an address block. Value 1 indicates that the register\n is present in the address block whereas value 0 marks the register to be\n treated as if it does not exist. Is present can be given as a SystemVerilog expression,\n but it must evaluate to 1 or 0.
\n\n Description is an optional field for textual description of the register.\n
\n\n\tRegister files table
\n\n The register files table enables the user to define register files for the\n\t\taddress block where each row represents a single register file.\n\t\tRegister files are used to group together registers.\n
\n\n\n Name is a mandatory identifier for the register file.
\n\n Offset is mandatory and specifies the location of the register file from\n the start of the containing address block expressed as number of addressing\n units. Offset can be given as a SystemVerilog expression.\n
\n\n\t Range is mandatory and specifies the size of the register file in address\n\t unit bits.\n
\n\n Dimension is optional and assigns an array dimension to the register file.\n The register file will be repeated in the address block as many times as\n indicated by the dimension value. By default, the dimension is presumed to be 0.\n Dimension 0 means that the register file is not an array and will appear exactly\n once.\n
\n\n\t\n Is present is optional and allows enabling/disabling of a register file\n presence in an address block. Value 1 indicates that the register file\n is present in the address block whereas value 0 marks the register to be\n treated as if it does not exist. Is present can be given as a SystemVerilog expression,\n but it must evaluate to 1 or 0.
\n\n Description is an optional field for textual description of the register file.\n
\n\n\n" }, { "path": "Help/componenteditor/addressblock2022.html", "content": "\n\n\n \n \nAddress block editor
\n\n Address block editor is used to edit the details of an address block and the registers\n contained within it.\n
\n\n Name is a mandatory identifier for the address block. The name must\n be unique within all the address blocks of the containing memory map.\n
\n\n Display name is an optional and used for a more user-friendly identifier.\n
\n\n Short description is an optional field for compact description of the address block.\n
\n\n Description is an optional field for textual description of the address block.\n
\n\n Base address is mandatory and specifies the starting address for the address\n block in address unit bits.\n
\n\n Range is mandatory and specifies the size of the block in address units bits.\n
\n\n Width is mandatory and defines the data width of a row in the address block.\n The width value is given in bits.\n
\n\n\n Usage is a mandatory value to specify the usage of the address block and\n may have one of the following values:\n
\n- \n
- \n Memory The address block is ROM, RAM or write-only memory as defined\n by access policies. Registers and register files within will be considered virtual.\n \n
- \n Register The address block range may contain registers.\n \n
- \n Reserved The address block is reserved for other usage and shall not\n contain registers or register files.\n \n
\n Volatile is optional and indicates whether the stored value may change without\n the master's write operation or not.\n
\n \n\n Access policies are optional and specify the accessability of the address block data for different operating modes,\n specified by mode references. If no mode reference is present, then the access policy applies to all modes not already \n referenced by other access policies (i.e. only one access policy without mode references may exist).\n \n The possible access values for an access policy are:\n
\n- \n
- \n read-write. Both read and write transactions may have an effect on this \n address block.\n \n
- \n read-only. Only read transactions are allowed in this address block.\n \n
- \n write-only. Only write transactions are allowed in this address block.\n \n
- \n read-writeOnce. Read actions and the first write action may have an effect\n on this address block.\n \n
- \n writeOnce. Only the first write action affects the contents of this address\n block.\n \n
Registers table
\n\n The register table enables the user to define registers for the address block,\n with each row representing a single register. Each register must also contain at\n least one bit field.\n
\n\n\n Name is a mandatory identifier for the register.
\n\n Offset is mandatory and specifies the location of the register from\n the start of the containing address block expressed as number of addressing\n units. The actual address of the register is the sum of address block's\n base address and the register offset. E.g. if the base address is 'h100 and\n the register offset is 'h4, the register's address is 'h104. Offset can be given\n as a SystemVerilog expression.\n
\n\n Size is mandatory and defines the number of data bits the register\n contains. Size must be less than or equal to the width of the containing address block.\n
\n\n Dimension is optional and assigns an array dimension to the register.\n The register will be repeated in the address block as many times as\n indicated by the dimension value. If empty (default) or 1, the register will appear\n exactly once.\n
\n\n Volatile is optional and indicates whether the register value may\n change without a write operation to it, i.e. by an interrupt event, or not.\n
\n\n Access is optional and specifies the accessibility of the register by modifying\n the first access policy of the register. If multiple access policies exist, then the access value \n cannot be edited here and must be edited for each access policy separately in the register editor. \n If no access policy exists, then one will be created for the register when the access is edited here.\n\n The possible access values are:\n
\n- \n
- read-write. Both read and write transactions may have an effect on this \n register. \n
- read-only. Only read transactions are allowed in this register. \n
- write-only. Only write transactions are allowed in this register. \n
- read-writeOnce. Both read and write transactions may have an effect on this\n register. Only the first write transaction, after an event that caused the\n reset value of the register to be loaded, may affet the contents of the register,\n and read transactions return a value related to the values in the register. \n
- writeOnce. Only the first write transaction affects the contents of the \n register. \n
\n Description is an optional field for textual description of the register.\n
\n\n\tRegister files table
\n\n The register files table enables the user to define register files for the\n\t\taddress block where each row represents a single register file.\n\t\tRegister files are used to group together registers.\n
\n\n\n Name is a mandatory identifier for the register file.
\n\n Offset is mandatory and specifies the location of the register file from\n the start of the containing address block expressed as number of addressing\n units. Offset can be given as a SystemVerilog expression.\n
\n\n\t Range is mandatory and specifies the size of the register file in address\n\t unit bits.\n
\n\n Dimension is optional and assigns an array dimension to the register file.\n The register file will be repeated in the address block as many times as\n indicated by the dimension value. If empty (default) or 1, the register file will appear\n exactly once.\n
\n\n\n Description is an optional field for textual description of the register file.\n
\n\n\n" }, { "path": "Help/componenteditor/addressspace.html", "content": "\n\n \n \n \nAddress space editor
\n\n Address space editor can be used to edit the details of an\n address space within component. Address space defines a\n logical address space seen by a master bus interface. It can be\n split into smaller sgements.\n
\n\n On the left side are the editor fields that can be used to set\n the details of an address space. The right side contains a\n visualization displaying the address space in its current state and\n\t automatically updates on changes.\n\t It displays how the segments are positioned within the address space. \n\t Mismatches, e.g. sum of segment ranges being greater than address block range, can \n be easily spotted from the visualization.\n
\n\t\n\t Name is a mandatory identifier for the address space.\n
\n\n Display name is an optional and used for a more user-friendly identifier.\n
\n\n Description is an optional field for textual description of the address space.\t\t\n
\n\n Addressable unit bits (AUB) specifies the number of bits each address increment contains, \n e.g. 8 bits or 32 bits. The AUB is mandatory if the address space contains a local memory map.\n
\n\n Range is the size of the address space expressed as addressable units, i.e. the number of\n separate addresses.\n
\n\n Width is the data width of a row in bits. It defines the maximum size for a single transfer.\n
\n\t\n Is present is optional and allows enabling/disabling of a address space\n presence in a component. Value 1 indicates that the address space\n is present in the component whereas value 0 marks the address space to be\n treated as if it does not exist. Is present can be given as a SystemVerilog expression,\n but it must evaluate to 1 or 0.
\n\t\n
\n Master interface binding shows the master bus interfaces bound to the address space. \n\t The binding can be set in the bus interface editor.\n
\n\t\nSegments
\n\n Segments editor can be used to describe sections of the address space, i.e. split it into smaller\n segments.\n
\n\t\n\t Name is a mandatory identifier for the segment.\n
\n\n Offset is mandatory and defines the starting address of the segment in address unit bits.\n\t
\n\t\n\t\tRange is mandatory and defines the size of the segment in address unit bits.\n
\n\t\t\n Is present is optional and allows enabling/disabling of a segment\n presence in an address space. Value 1 indicates that the segment\n is present in the address space whereas value 0 marks the segment to be\n treated as if it does not exist. Is present can be given as a SystemVerilog expression,\n but it must evaluate to 1 or 0.
\n\t\n\t
\n Description is an optional field for textual description of the segment.\t\t\n
\n\nLocal memory map
\n\n Local memory map is optional but some processors require specifying a memory map that is local\n to the component. It consists of address blocks similarly to the memory map of a slave\n bus interface.\n\t Hence, the address blocks can contain either memory or registers, and registers can contain bit fields.\n
\n\n Local memory map is useful for storing the programmer's view to interrupts registers, timers,\n and other local things. The overall address space of a component is a concatenation of local memory map\n (e.g. timers) and the memory maps of other units (e.g. registers of accelerator A, registers of\n accelerator B etc.)\n
\n\t\n \n\n" }, { "path": "Help/componenteditor/addressspace2022.html", "content": "\n\n \n \n \nAddress space editor
\n\n Address space editor can be used to edit the details of an\n address space within component. Address space defines a\n logical address space seen by a initiator bus interface. It can be\n split into smaller sgements.\n
\n\n On the left side are the editor fields that can be used to set\n the details of an address space. The right side contains a\n visualization displaying the address space in its current state and\n\t automatically updates on changes.\n\t It displays how the segments are positioned within the address space. \n\t Mismatches, e.g. sum of segment ranges being greater than address block range, can \n be easily spotted from the visualization.\n
\n\t\n\t Name is a mandatory identifier for the address space.\n
\n\n Display name is an optional and used for a more user-friendly identifier.\n
\n\n Short description is an optional field for a short, textual description of the address space.\t\t\n
\n\n Description is an optional field for textual description of the address space.\t\t\n
\n\n Addressable unit bits (AUB) specifies the number of bits each address increment contains, \n e.g. 8 bits or 32 bits. The AUB is mandatory if the address space contains a local memory map.\n
\n\n Range is the size of the address space expressed as addressable units, i.e. the number of\n separate addresses.\n
\n\n Width is the data width of a row in bits. It defines the maximum size for a single transfer.\n
\n\n Initiator interface binding shows the initiator bus interfaces bound to the address space. \n\t The binding can be set in the bus interface editor.\n
\n\t\nSegments
\n\n Segments editor can be used to describe sections of the address space, i.e. split it into smaller\n segments.\n
\n\t\n\t Name is a mandatory identifier for the segment.\n
\n\n Offset is mandatory and defines the starting address of the segment in address unit bits.\n\t
\n\t\n\t\tRange is mandatory and defines the size of the segment in address unit bits.\n
\n\t\n Description is an optional field for textual description of the segment.\t\t\n
\n\nLocal memory map
\n\n Local memory map is optional but some processors require specifying a memory map that is local\n to the component. It consists of address blocks similarly to the memory map of a target\n bus interface.\n\t Hence, the address blocks can contain either memory or registers, and registers can contain bit fields.\n
\n\n Local memory map is useful for storing the programmer's view to interrupts registers, timers,\n and other local things. The overall address space of a component is a concatenation of local memory map\n (e.g. timers) and the memory maps of other units (e.g. registers of accelerator A, registers of\n accelerator B etc.)\n
\n\t\n \n\n" }, { "path": "Help/componenteditor/addressspaces.html", "content": "\n\n \n \n \nAddress spaces editor
\n\n Address spaces editor contains the summary of the address spaces\n of the component. This editor can be used to add and remove\n address spaces to the containing component. \n
\n\n Address space defines the addressable memory space that can be accessed through\n\t a master bus interface. It is the programmer's view to the rest of the system.\n
Note: Address spaces are actually instance-specific concepts (what other units are \n there and what are their addresses) rather than component-specific. Nevertheless, IP-XACT standard \n defines address space inside a component, although it is seldom a reusable element.\n
\n\t Name is a mandatory identifier for the address space.\n
\n\n Addressable unit bits specifies the number of bits each address increment contains, \n e.g. 8 bits or 32 bits. The AUB is mandatory if the address space contains a local memory map. \n\t AUB is 8 by default.\n
\n\n Range is mandatory and defines the size of the address space in addressable units. In other \n words, it is the number of separate addresses in the address space.\n
\n\n Width is mandatory and defines the data width of a row in bits thus\n\t defining the maximum size for a single transfer.\n
\n\n Master interface binding shows the master bus interfaces bound to the address space. \n\t The binding can be set in the bus interface editor.\n
\n\t\n\t\n Is present is optional and allows enabling/disabling of a address space\n presence in a component. Value 1 indicates that the address space\n is present in the component whereas value 0 marks the address space to be\n treated as if it does not exist. Is present can be given as a SystemVerilog expression,\n but it must evaluate to 1 or 0.
\n\t\n\t\n\t
\n Description is an optional field for textual description of the address space.\t\t\n
\n\n Address spaces editor contains a context menu (right mouse button) providing following options:\n
\n- \n
- Add new address space (Add row) \n
- Remove address space (Remove row) \n
- Clear the selected cells \n
- Copy the contents of the selected cells to clipboard \n
- Paste the contents of the clipboard to the selected cells \n
- Import a csv-file to the editor \n
- Export the contents of the editor to a csv-file \n
\n\t
\n\t\tEXAMPLE. The address space AS0 defines the available address space of the whole system\n\t\twhen accessed through bus interface MainIF. This is what the component CPU0 requires\n\t\tof the system, but the components connected to MainIF may be different.\n\t\t
\n\t\t![\"addr](\"../images/addr_space.png\")
\n
Address spaces editor
\n\n Address spaces editor contains the summary of the address spaces\n of the component. This editor can be used to add and remove\n address spaces to the containing component. \n
\n\n Address space defines the addressable memory space that can be accessed through\n\t a master bus interface. It is the programmer's view to the rest of the system.\n
Note: Address spaces are actually instance-specific concepts (what other units are \n there and what are their addresses) rather than component-specific. Nevertheless, IP-XACT standard \n defines address space inside a component, although it is seldom a reusable element.\n
\n\t Name is a mandatory identifier for the address space.\n
\n\n Addressable unit bits specifies the number of bits each address increment contains, \n e.g. 8 bits or 32 bits. The AUB is mandatory if the address space contains a local memory map. \n\t AUB is 8 by default.\n
\n\n Range is mandatory and defines the size of the address space in addressable units. In other \n words, it is the number of separate addresses in the address space.\n
\n\n Width is mandatory and defines the data width of a row in bits thus\n\t defining the maximum size for a single transfer.\n
\n\n Initiator interface binding shows the initiator bus interfaces bound to the address space. \n\t The binding can be set in the bus interface editor.\n
\n\t\n\t\n Description is an optional field for textual description of the address space.\t\t\n
\n\n Address spaces editor contains a context menu (right mouse button) providing following options:\n
\n- \n
- Add new address space (Add row) \n
- Remove address space (Remove row) \n
- Clear the selected cells \n
- Copy the contents of the selected cells to clipboard \n
- Paste the contents of the clipboard to the selected cells \n
- Import a csv-file to the editor \n
- Export the contents of the editor to a csv-file \n
\n\t
\n\t\tEXAMPLE. The address space AS0 defines the available address space of the whole system\n\t\twhen accessed through bus interface MainIF. This is what the component CPU0 requires\n\t\tof the system, but the components connected to MainIF may be different.\n\t\t
\n\t\t\n
API interface editor
\n\n
\n This is Kactus2 extension
Each API interface has a\n mandatory name. Display name is optional and\n typically a few words providing a more detailed and/or\n user-friendly name for display. Optional description\n contains a textual description of the interface.\n
\n Optional API definition is an XML document that captures\n the interface properties. It lists all the function calls, their\n parameters, and return values. You can type the VLNV or\n drag-drop an API definition from the library.\n
\n\n Details section includes dependency which is\n either 'provider' or 'requester'. A provider means that\n this SW components implements the API and other SW components\n call its functions. Requester means that this SW\n components calls functions defined in the API and some other SW\n component must implement (provide) them.\n
\n \n\n" }, { "path": "Help/componenteditor/apiinterfaces.html", "content": "\n\n \n \n \nAPI interfaces editor
\n\n This is Kactus2 extension
API interface\n (application programming interface) means the protocol that SW\n components use to communicate, in practice it is set of function\n calls. Purpose is to increase portability by abstacting the\n details of underlying HW. These are a lower level concept than\n COM interfaces and cannot appear in HW components. API\n interfaces make rather tight coupling between SW components, and\n often both the sender and receiver are mapped on the same CPU.\n COM interfaces are meant for communication between application\n modules, whereas API interfaces are mainly between application\n and platform (OS, drivers) and inside the platform.
\n For example, a SW component could have API interfaces 'lower'\n and 'upper'. It requests the 'lower' one, DMA driver,\n i.e. calls its functions. At the same, this component 'provides'\n the 'upper' interface, MCAPI, i.e. other SW components can call\n its functions.
![\"screen_cap\"](\"../images/api_interfaces.png\"\n)
\n
Bus interface editor
\n\n Bus interface editor is used to edit the details of a single\n bus interface. A bus interface is used to group ports\n together to form an interface that fulfills the requirements\n for a bus protocol. The editor has two tabs: the\n general tab which is used to set the details of\n the bus interface, and the port maps tab which is used to\n group the ports to the bus interface.\n
\n\t\n\t Name is a mandatory identifier for the bus interface.\n
\n\n Display name is an optional and used for a more user-friendly identifier.\n
\n\n Description is an optional field for textual description of the bus interface.\t\t\n
\n\nGeneral settings
\n\n Interface mode is mandatory and has 7 possible choices:\n
\n- \n
- Master for initiating transactions. \n
- Slave for responding to transactions. \n
- System for defining interfaces not belonging to either master or slave interface modes.\n They are categorized by a system group instead. \n
- MirroredMaster is the mirrored version of a master interface. \n
- MirroredSlave is the mirrored version of a slave interface. \n
- MirroredSystem is the mirrored version of a system interface. \n
- Monitor for verification. \n
\n Settings below the general section are mode-specific and change when the mode changes.\n The different modes are detailed in their respective sections below. \n
\n\n Addressable unit size defines how many bits are included in the least addressable unit of the bus \n interface. The default setting is byte addressable (8 bits).\n
\n\n Bit steering='on' implies that the interface is able to dynamically align data on different byte \n channels in case of addressable interfaces. The default setting when the bit steering is not set is off.\n Bit steering is not allowed in mirrored-master, system or mirrored-system interface modes.\n
\n\n Endianness indicates whether the interface is 'big-endian' or 'little-endian' (default).\n
\n\n Connection required indicates that when instantiated in a design, this interface must be connected \n to some other interface and cannot be left unconnected.\n
\n\nMaster
\n\n Address space defines the address space available for transactions on\n the bus interface. Address space is optional, but, if defined, \n base address becomes mandatory as well.\n
\n\n Base address is defines the starting address of the address space. Typically\n base address is 0.\n
\n\nMirrored master
\n\n\t\tMirrored master has no mode-specific options.\n\t
\n\t\nSlave
\nA slave bus interface may have access to a memory map or a master bus interface.\n Access to a master bus interface is called a transparent bridge. Access is \n optional, but mutually exclusive i.e. a slave bus interface may only access a memory map, \n a transparent bridge or neither.\n
\n\n Memory map is optional and defines the memory map accessible through\n the bus interface. If a memory map has been defined, transparent bridge\n cannot be defined.\n
\n\n Transparent bridge(s) are optional and define the master bus interface(s) that\n all transactions to this bus interface are directed out of. \n If transparent bridges have been defined, memory map cannot be defined.\n
\n \n\n File set references define the associated file sets for the slave bus\n interface. For example, the file set could contain the interface implementation or\n a software driver.\n
\n \nMirrored slave
\n\n Remap address defines an address offset for the slave bus interface\n conneted to this interface. Remap addressis optional,\n but, if defined, range becomes mandatory as well.\n
\n \n\n Range defines the address range available for the connected slave bus interface.\n
\n\nSystem and mirrored system
\n\n System group defines the group this bus interface is part of. The available system\n groups are defined in the referenced bus definition (see below).\n
\n \nMonitor
\n\n Interface mode is mandatory and defines the interface mode the monitor can be connected to.\n
\n\n Group defines the group this bus interface is part of when system or\n mirrored system interface mode is selected. For other modes group has no effect.\n
\n \nBus definition
\n\n Bus definition is mandatory and contains a VLNV-reference to the bus definition\n document that defines the qualities that the bus interface must meet.\n
\n\nAbstraction definition
\n\n Abstraction definition contains an optional VLNV-reference to \n the abstraction definition document that defines the logical signals\n on the bus. If multiple abstraction definitions are defined, view references\n\t specify which view(s) the abstraction is applied to. All views are considered,\n\t if the view reference is empty.\n\t
\n\t\n\t Port maps on the other tab define how the logical signals in the abstraction\n\t definition are connected to the physical ports on the component.\n
\nParameters
\n\n Parameters are optional and can specify any parameter data value(s) specific for this bus interface.\n For more information on parameters, see the component parameter editor.\n
\n \n\n" }, { "path": "Help/componenteditor/businterfacegeneral2022.html", "content": "\n\n \n \n \nBus interface editor
\n\n Bus interface editor is used to edit the details of a single\n bus interface. A bus interface is used to group ports\n together to form an interface that fulfills the requirements\n for a bus protocol. The editor has two tabs: the\n general tab which is used to set the details of\n the bus interface, and the port maps tab which is used to\n group the ports to the bus interface.\n
\n\t\n\t Name is a mandatory identifier for the bus interface.\n
\n\n Display name is an optional and used for a more user-friendly identifier.\n
\n\n Short description is an optional field for compact description of the bus interface.\n
\n\n Description is an optional field for textual description of the bus interface.\t\t\n
\n\nGeneral settings
\n\n Interface mode is mandatory and has 7 possible choices:\n
\n- \n
- Initiator for initiating transactions. \n
- Target for responding to transactions. \n
- System for defining interfaces not belonging to either initiator or target interface modes.\n They are categorized by a system group instead. \n
- MirroredInitiator is the mirrored version of an initiator interface. \n
- MirroredTarget is the mirrored version of a target interface. \n
- MirroredSystem is the mirrored version of a system interface. \n
- Monitor for verification. \n
\n Settings below the general section are mode-specific and change when the mode changes.\n The different modes are detailed in their respective sections below. \n
\n\n Addressable unit size defines how many bits are included in the least addressable unit of the bus \n interface. The default setting is byte addressable (8 bits).\n
\n\n Bit steering evaluating to value '1' implies that the interface is able to dynamically align data on different byte \n channels in case of addressable interfaces. The default setting when the bit steering is not set is 0.\n Bit steering is not allowed in mirrored-initiator, system or mirrored-system interface modes.\n
\n\n Endianness indicates whether the interface is 'big-endian' or 'little-endian' (default).\n
\n\n Connection required indicates that when instantiated in a design, this interface must be connected \n to some other interface and cannot be left unconnected.\n
\n\nInitiator
\n\n Address space defines the address space available for transactions on\n the bus interface. Address space is optional, but, if defined, \n base address becomes mandatory as well.\n
\n\n Base address is defines the starting address of the address space. Typically\n base address is 0.\n
\n\nMirrored initiator
\n\n\t\tMirrored initiator has no mode-specific options.\n\t
\n\t\nTarget
\nA target bus interface may have access to a memory map or an initiator bus interface.\n Access to a initiator bus interface is called a transparent bridge. Access is \n optional, but mutually exclusive i.e. a target bus interface may only access a memory map, \n a transparent bridge or neither.\n
\n\n Memory map is optional and defines the memory map accessible through\n the bus interface. If a memory map has been defined, transparent bridge\n cannot be defined.\n
\n\n Transparent bridge(s) are optional and define the initiator bus interface(s) that\n all transactions to this bus interface are directed out of. \n If transparent bridges have been defined, memory map cannot be defined.\n
\n\n File set references define the associated file sets for the target bus\n interface. For example, the file set could contain the interface implementation or\n a software driver.\n
\n \nMirrored target
\n\n Remap address defines an address offset for the target bus interface\n conneted to this interface. Remap addressis optional,\n but, if defined, range becomes mandatory as well.\n
\n \n\n Range defines the address range available for the connected target bus interface.\n
\n\nSystem and mirrored system
\n\n System group defines the group this bus interface is part of. The available system\n groups are defined in the referenced bus definition (see below).\n
\n \nMonitor
\n\n Interface mode is mandatory and defines the interface mode the monitor can be connected to.\n
\n\n Group defines the group this bus interface is part of when system or\n mirrored system interface mode is selected. For other modes group has no effect.\n
\n \nBus definition
\n\n Bus definition is mandatory and contains a VLNV-reference to the bus definition\n document that defines the qualities that the bus interface must meet.\n
\n\nAbstraction definition
\n\n Abstraction definition contains an optional VLNV-reference to \n the abstraction definition document that defines the logical signals\n on the bus. If multiple abstraction definitions are defined, view references\n\t specify which view(s) the abstraction is applied to. All views are considered,\n\t if the view reference is empty.\n\t
\n\t\n\t Port maps on the other tab define how the logical signals in the abstraction\n\t definition are connected to the physical ports on the component.\n
\nParameters
\n\n Parameters are optional and can specify any parameter data value(s) specific for this bus interface.\n For more information on parameters, see the component parameter editor.\n
\n \n\n" }, { "path": "Help/componenteditor/businterfaces.html", "content": "\n\n \n \n \nBus interfaces editor
\n\n The bus interfaces editor displays a summary of the bus\n interfaces of a component. A bus interface groups\n ports together to form an interface that fulfills\n requirements for a bus protocol. Connecting two matching\n interfaces means connecting multiple ports (up to tens or even\n hundreds of bits) together very easily. This editor is used to\n add and remove bus interfaces in a component\n\t
\n\t ![\"interface_example\"](\"../images/portmap.png\")
\n
\n Bus interface has a mandatory name and optional textual description.\n
\n\n Bus definition and abstraction definition columns display the VLNV-identifiers of the\n IP-XACT documents that define qualities of the interface. These\n fields must be set in the bus interface-specific editor.\n
\n\n Interface mode has 7 different choices (3 modes and 2\n flavors of each, plus 1 extra):\n
\n- \n
- 1. Master initiates transactions, e.g. a write or read. \n\t A master may have an address space which captures the programmer's view of the system. \n \n
- 2. Slave responds to transactions, e.g. accepts the written value or provides the read value.\n\t A slave may have a memory map which captures information about the accessible registers inside this component. \n \n
- 3. System can be used for some interfaces that do not fit into the master or slave category. \n \n
- 4-6. Mirrored master, mirrored slave, mirrored system are the mirrored versions of the\n\t above modes.\n\t They have similar ports as normal interfaces, but the directions of the ports are reversed. \n\t For example, if a master interface has data \n output, then a mirrored master has data as input.\n\t It is not allowed to connect to mirrored interfaces together. \n\t The main usage of mirrored interfaces is at bus interconnects, such as AMBA AHB/APB or HIBI,\n\t since they allow constructing a memory map of the whole system, whereas regular IP \n components mainly utilize direct interfaces. \n \n
- 7. Monitor is an interface that can be used for verification process. \n\t It gathers data from other interfaces, i.e. non-intrusive observation and hence all logical port are inputs \n
\n IP-XACT allows three kinds of connections\n
\n- \n
- Direct master to slave: Point-to-point connection. Complex cases require using bus interconnect\n component containing bridge(s), such as multillayer AHB bus. \n \n
- Direct-mirrored: master to mirrored master, mirrored slave to slave, system to mirrored system. \n Point-to-point connection. Complex cases require using bus interconnect component containing \n channel(s) \n \n
- Monitor: any type except monitor to monitor. Many monitors can be connected to single interface \n
\n
\n EXAMPLE. Component Sender writes data through its master interface MIF to\n mirrored master interface MMIF in interconnect. On the receiving side,\n interconnect's mirrored slave interface MSIF writes the data to\n Receiver's slave interface SIF. \n
\n ![\"interfaces_example\"](\"../images/busInterfaces.png\")
\n
Bus interfaces editor
\n\n The bus interfaces editor displays a summary of the bus\n interfaces of a component. A bus interface groups\n ports together to form an interface that fulfills\n requirements for a bus protocol. Connecting two matching\n interfaces means connecting multiple ports (up to tens or even\n hundreds of bits) together very easily. This editor is used to\n add and remove bus interfaces in a component\n\t
\n\t ![\"interface_example\"](\"../images/portmap2022.png\")
\n
\n Bus interface has a mandatory name and optional textual description.\n
\n\n Bus definition and abstraction definition columns display the VLNV-identifiers of the\n IP-XACT documents that define qualities of the interface. These\n fields must be set in the bus interface-specific editor.\n
\n\n Interface mode has 7 different choices (3 modes and 2\n flavors of each, plus 1 extra):\n
\n- \n
- 1. Initiator initiates transactions, e.g. a write or read. \n\t An initiator may have an address space which captures the programmer's view of the system. \n \n
- 2. Target responds to transactions, e.g. accepts the written value or provides the read value.\n\t A target may have a memory map which captures information about the accessible registers inside this component. \n \n
- 3. System can be used for some interfaces that do not fit into the initiator or target category. \n \n
- 4-6. Mirrored initiator, mirrored target, mirrored system are the mirrored versions of the\n\t above modes.\n\t They have similar ports as normal interfaces, but the directions of the ports are reversed. \n\t For example, if an initiator interface has data \n output, then a mirrored initiator has data as input.\n\t It is not allowed to connect to mirrored interfaces together. \n\t The main usage of mirrored interfaces is at bus interconnects, such as AMBA AHB/APB or HIBI,\n\t since they allow constructing a memory map of the whole system, whereas regular IP \n components mainly utilize direct interfaces. \n \n
- 7. Monitor is an interface that can be used for verification process. \n\t It gathers data from other interfaces, i.e. non-intrusive observation and hence all logical port are inputs \n
\n IP-XACT allows three kinds of connections\n
\n- \n
- Direct initiator to target: Point-to-point connection. Complex cases require using bus interconnect\n component containing bridge(s), such as multillayer AHB bus. \n \n
- Direct-mirrored: initiator to mirrored initiator, mirrored target to target, system to mirrored system. \n Point-to-point connection. Complex cases require using bus interconnect component containing \n channel(s) \n \n
- Monitor: any type except monitor to monitor. Many monitors can be connected to single interface \n
\n
\n EXAMPLE. Component Sender writes data through its initiator interface IIF to\n mirrored initiator interface MIIF in interconnect. On the receiving side,\n interconnect's mirrored target interface MTIF writes the data to\n Receiver's target interface TIF. \n
\n ![\"interfaces_example\"](\"../images/busInterfaces2022.png\")
\n
Channels editor
\n\n Channels editor provides a summary of the channels contained in\n the bus component. Channel is used within a bus\n component to describe which bus interfaces are connected\n together. This editor can be used to add, edit and remove\n channels.\n
\n\n\t Name is a mandatory identifier for the channel.\n
\n\n Display name is an optional and used for a more user-friendly identifier.\n
\n\n Interface references contain the names of the mirrored bus interfaces \n that are grouped to the same channel. All the bus interfaces in the group are\n interconnected. \n
\n\n Description is an optional field for textual description of the channel.\t\t\n
\n\n
\n\t The figure below illustrates the connections between mirrored bus interfaces. All four\n mirrored bus interfaces are included in the same channel.\n\t
\n\t ![\"A](\"../images/ChannelVisualization.png\")
\n
Channels editor
\n\n Channels editor provides a summary of the channels contained in\n the bus component. Channel is used within a bus\n component to describe which bus interfaces are connected\n together. This editor can be used to add, edit and remove\n channels.\n
\n\n\t Name is a mandatory identifier for the channel.\n
\n\n Display name is an optional and used for a more user-friendly identifier.\n
\n\n Interface references contain the names of the mirrored bus interfaces \n that are grouped to the same channel. All the bus interfaces in the group are\n interconnected. \n
\n\n Short description is an optional field for compact description of the channel.\n
\n\n Description is an optional field for textual description of the channel.\t\t\n
\n\n
\n\t The figure below illustrates the connections between mirrored bus interfaces. All four\n mirrored bus interfaces are included in the same channel.\n\t
\n\t
\n
Choices editor
\n\n The choices editor lists the configuration elements of the component. A choice provides a set of \n possible values for parameters, module parameters and other configurable elements within the \n containing component.\n
\n\n Choices are identified by a mandatory name in the Choice list.\n
\n\n Each choice must have at least one enumeration defined. An enumeration has \n\t a mandatory value, an optional text to display instead \n of the value and an optional description. When the value of e.g. a parameter refers to the\n choice, the possible model parameter value is selected from the set of enumerations in that choice.\n
\n\n\t
\n EXAMPLE. The choice is used to limit the possible parameter values to 8, 16 or 32 (bits).
\n ![\"screen](\"../images/choiceExample.png\")
\n\t
COM interface editor
\n\n This is Kactus2 extension
Each interface has a mandatory\n name. Display name is optional and typically a few\n words providing a more detailed and/or user-friendly name for\n display. Optional description contains a textual\n description of the interface.\n
\n Optional COM definition is a XML document that captures\n the interface properties, similarly to bus interfaces in regular\n HW components. You can type the VLNV or drag-drop a COM\n definition from the library.\n
\n\n Details are settings that are specific to selected COM\n definition. Optional transfer type denotes what kind of\n data is transmitted through the interface. The allowed values\n depend on the selected COM definition, e.g. in MCAPI they are\n 'message', 'packet', and 'scalar'. At least MCAPI has also a\n Direction (in, out, inout).\n
\n\n Property values define values for the parameters as\n name-value pairs. For example in MCAPI, each endpoint must have\n a 'port_id'.\n
\n \n\n" }, { "path": "Help/componenteditor/cominterfaces.html", "content": "\n\n \n \n \nCOM interfaces editor
\n\n This is Kactus2 extension
COM interface means\n that component supports an optional \"high-level\" communication\n mechanism, such as MCAPI. Purpose is to increase portability by\n abstacting the details of communication. COM interfaces are\n connected together in system view of the Kactus. Usually,\n these interfaces a part of a SW component, but some HW\n components can support them also. COM interfaces makes only\n loose coupling between SW components, and consequently the\n receiver can be mapped on different CPU than sender. COM\n interfaces are meant for communication between application\n modules, whereas API interfaces are mainly between application\n and platform (OS, drivers) and inside the platform.\n
\n Each interface has a mandatory name and direction\n (in, out, inout). Optional COM definition is an XML\n document that captures the interface properties, similarly to\n bus interfaces in regular HW components. Note that this\n information is just shown here and can be edited on interface\n editor. Optional transfer type denotes what kind of data\n is transmitted through the interface. The allowed values depend\n on the selected COM definition.\n
\n\n For example, a SW component could have an input COM interface\n 'data_in' and output called 'result_out'. Then depending of how\n the channels are conencted in system design, the imput data can\n come from, say, UART or CPU. Similarly, the result can be\n directed to, say, memory or VGA. Here both interfaces correspond\n to MCAPI endpoints and transmit 'MCAPI messages'.
\n
Component instantiation editor
\r\n\r\n Component instantiation defines how a specific component instance is associated with a view.\r\n This editor can be used to edit the details of a component instantiation.\r\n
\r\n\r\n\t Name is a mandatory identifier for the component instantiation.\r\n
\r\n\r\n Display name is an optional and used for a more user-friendly identifier.\r\n
\r\n\r\n Description is an optional field for textual description of the component instantiation.\t\t\r\n
\r\nImplementation details
\r\n\r\n Language specifies the HDL used for a specific instantiation, for example, verilog or vhdl. \n\t\tStrict determines if the language shall be strictly enforced.\r\n
\r\n\r\n Library specifies the library name in which the model should be compiled.\r\n
\r\n\r\n Package describes the VHDL package containing the interface of the model. Defaults to the component \r\n VLNV name concatenated with the postfix _cmp_pkg, which stands for component package.\r\n
\r\n\r\n Module name describes the Verilog, SystemVerilog or SystemC module name or the VHDL entity name.\r\n Defaults to the component VLNV name.\r\n
\r\n\r\n Architecture describes the VHDL architecture name. Defaults to rtl.\r\n
\r\n\r\n Configuration describes the Verilog, SystemVerilog or VHDL configuration name. Defaults to the \r\n design configuration VLNV name of the design configuration referenced in the view, or to the component \r\n VLNV name concatenated with the postfix _rtl_cfg.\r\n
\r\n\t\r\nFile set references
\r\n\r\n File set references is an optional list of file set names that are associated with the\r\n\t\tcomponent instance. For example, the file set containing the RTL implementation file(s)\r\n\t\tof the module detailed in Implementation details could be referenced.\r\n
\r\n\r\nDefault file build commands
\r\n\r\n Default file build commands is a list of build options for the file sets \r\n referenced in the containing view.\r\n
\r\n\r\n File type defines which files are build by the given command.\r\n
\r\n\r\n Build command defines how to build the files within the file set by e.g. \n\t\trunning 'gcc' for C files or 'vcom' for VHDL.\r\n
\r\n\r\n Flags define the command line options for the command e.g. '-Wall'.\r\n
\r\n\r\n Replace default flags selects whether the given flags override the flags \n\t\tdefined in the target file or are they \r\n appended to them. Replace default flags can be given as an expression, \n\t\tbut it must evaluate to 1 or 0.\r\n
\r\n\r\n The defult file build commands contains a context menu, with the following functionalities:\r\n
\r\n- \r\n
- Add new build command (Add row) \r\n
- Remove build command (Remove row) \r\n
- Clear the selected cells \r\n
- Copy the contents of the selected cells to clipboard \r\n
- Paste the contents of the clipboard to the selected cells \r\n
Module parameters
\r\n\r\n Module parameters editor can be used to add, remove and modify module parameters. Module parameters are \r\n often used in HDL to configure component instances. They represent e.g VHDL generics and Verilog \r\n parameters.\r\n
\r\n\r\n All columns of the editor are editable. Double-clicking an empty space adds a new row.\r\n
\r\n\r\n Name column is mandatory. Display name provides a more user-friendly name for the module \r\n parameter. Description is free text for further details.\r\n
\r\n\t\r\n Legal data type depends on the language of the model. For example in VHDL this could be 'integer' \r\n or 'std_logic', whereas in C-language int or 'char*' could be used. \r\n\t
\r\n\r\n Type is an optional constraint for the type to which the module parameter value resolves. \r\n Possible types are:\r\n
\r\n- \r\n
- bit indicates that the value shall resolve to a System Verilog bit, which by default is \r\n resolved to a 1-bit value, unless a vector size has been specified. \r\n\r\n
- byte indicates that the value shall resolve to a System Verilog byte, which is resolved to an \r\n 8-bit integer value. \r\n\r\n
- shortint indicates that the value shall resolve to a System Verilog shortint, which is resolved \r\n to a 16-bit integer value. \r\n\t\t\r\n\t\t
- int indicates that the value shall resolve to a System Verilog int, which is resolved to a \r\n 32-bit integer value. \r\n\t\t\r\n\t\t
- longint indicates that the value shall resolve to a System Verilog longint, which is resolved \r\n to a 64-bit integer value. \r\n\t\t\r\n\t\t
- shortreal indicates that the value shall resolve to a System Verilog shorint, which is resolved \r\n to a 32-bit floating point value. Both standard and scientific format (e.g 0.002 and 2e-3) are supported. \r\n This type applies also to minimum value and maximum value. \r\n\t\t\r\n\t\t
- real indicates that the value shall resolve to a System Verilog shortreal, which is resolved \r\n to a 64-bit floating point value. Both standard and scientific format (e.g. 0.002 and 2e-3) are supported. \r\n This type applies also to minimum value and maximum value. \r\n\t\t\r\n\t\t
- string indicates that the value shall contain text. \r\n
\r\n Value contains the mandatory default value of the module parameter. This value can be overridden in \r\n a design that instantiates this component. The value is given in SystemVerilog format and may be given as \r\n an expression. Any other text must be enclosed within quotes e.g. \"Any text\".\r\n
\r\n\r\n By selecting a choice, the user can restrict the allowed module parameter values to a set of \r\n predefined values. Possible values are defined in the choices of the containing component.\r\n
\r\n\r\n Minimum value and maximum value define the lower and upper boundary for the module parameter \r\n value. If the selected type is bit or string, these fields have no effect.\r\n
\r\n\t\r\n\t OO usage specifies how this model parameter is used. Default is 'non-typed' since such parameters \r\n are found in all languages, i.e. all VHDL types are non-typed. 'Typed' parameters appear in \r\n object-oriented languages, i.e. in C++.\r\n
\r\n\r\n Resolve specifies the configuration of the model parameter. Possible resolve values are:\r\n
\r\n- \r\n
- immediate indicates that the the value is defined within the containing component. The value \r\n cannot be overridden by the user or a generator in design configuration. This is the default value \r\n\r\n
- user indicates that the user can override the default value in design configuration. Generators \r\n are not allowed to change the value. \r\n\r\n
- generated indicates that the a generator can override the default value in design configuration.\r\n \r\n
\r\n Bit vector left and bit vector right define the left and right bounds of the bit vector.\r\n These are valid only for a bit type parameter. A valid bit vector requires both the left and the right bit \r\n vector values.\r\n
\r\n\r\n Array left and Array right specify the left and right sides of array dimension for the \r\n parameter in an output language e.g. Verilog. Both of these are vendor attributes. The values can be given \r\n as an expression, but they must resolve into a decimal number. In order to get a valid array, both \r\n array left and array right values must be given.\r\n
\r\n\t\r\n\t Usage count displays the number of references made to this module parameter. Selecting the usage \r\n count of a module parameter displays a reference analysis for it. The usage count can not be changed \r\n manually.\r\n\t
\r\n\r\n Module parameters editor contains a context menu (rigth mouse button) that has the following options:\r\n
\r\n- \r\n
- Add new module parameter (Add row) \r\n
- Remove module parameter (Remove row) \r\n
- Clear the selected cells \r\n
- Copy the contents of the selected cells to clipboard \r\n
- Paste the contents of the clipboard to the selected cells \r\n
Parameters
\r\n\r\n Parameters are optional and can specify any parameter data value(s) specific for this component instantiation.\r\n These parameters do not have direct connection to HDL, but may be used to configure IP-XACT elements, including the module parameters.\r\n For more information on parameters, see the component parameter editor.\r\n
\r\n\r\n \r\n\r\n" }, { "path": "Help/componenteditor/componentInstantiation2022.html", "content": "\n\n \n \n \n
Component instantiation editor
\n\n Component instantiation defines how a specific component instance is associated with a view.\n This editor can be used to edit the details of a component instantiation.\n
\n\n\t Name is a mandatory identifier for the component instantiation.\n
\n\n Display name is an optional and used for a more user-friendly identifier.\n
\n\n Short description is an optional field for a short description of the component instantiation.\t\t\n
\n\n Description is an optional field for textual description of the component instantiation.\t\t\n
\nImplementation details
\n\n Language specifies the HDL used for a specific instantiation, for example, verilog or vhdl. \n\t\tStrict determines if the language shall be strictly enforced.\n
\n\n Library specifies the library name in which the model should be compiled.\n
\n\n Package describes the VHDL package containing the interface of the model. Defaults to the component \n VLNV name concatenated with the postfix _cmp_pkg, which stands for component package.\n
\n\n Module name describes the Verilog, SystemVerilog or SystemC module name or the VHDL entity name.\n Defaults to the component VLNV name.\n
\n\n Architecture describes the VHDL architecture name. Defaults to rtl.\n
\n\n Configuration describes the Verilog, SystemVerilog or VHDL configuration name. Defaults to the \n design configuration VLNV name of the design configuration referenced in the view, or to the component \n VLNV name concatenated with the postfix _rtl_cfg.\n
\n\t\nFile set references
\n\n File set references is an optional list of file set names that are associated with the\n\t\tcomponent instance. For example, the file set containing the RTL implementation file(s)\n\t\tof the module detailed in Implementation details could be referenced.\n
\n\nDefault file build commands
\n\n Default file build commands is a list of build options for the file sets \n referenced in the containing view.\n
\n\n File type defines which files are build by the given command.\n
\n\n Build command defines how to build the files within the file set by e.g. \n\t\trunning 'gcc' for C files or 'vcom' for VHDL.\n
\n\n Flags define the command line options for the command e.g. '-Wall'.\n
\n\n Replace default flags selects whether the given flags override the flags \n\t\tdefined in the target file or are they \n appended to them. Replace default flags can be given as an expression, \n\t\tbut it must evaluate to 1 or 0.\n
\n\n The defult file build commands contains a context menu, with the following functionalities:\n
\n- \n
- Add new build command (Add row) \n
- Remove build command (Remove row) \n
- Clear the selected cells \n
- Copy the contents of the selected cells to clipboard \n
- Paste the contents of the clipboard to the selected cells \n
Module parameters
\n\n Module parameters editor can be used to add, remove and modify module parameters. Module parameters are \n often used in HDL to configure component instances. They represent e.g VHDL generics and Verilog \n parameters.\n
\n\n All columns of the editor are editable. Double-clicking an empty space adds a new row.\n
\n\n Name column is mandatory. Display name provides a more user-friendly name for the module \n parameter. Description is free text for further details.\n
\n\t\n Legal data type depends on the language of the model. For example in VHDL this could be 'integer' \n or 'std_logic', whereas in C-language int or 'char*' could be used. \n\t
\n\n Type is an optional constraint for the type to which the module parameter value resolves. \n Possible types are:\n
\n- \n
- bit indicates that the value shall resolve to a System Verilog bit, which by default is \n resolved to a 1-bit value, unless a vector size has been specified. \n\n
- byte indicates that the value shall resolve to a System Verilog byte, which is resolved to an \n 8-bit integer value. \n\n
- shortint indicates that the value shall resolve to a System Verilog shortint, which is resolved \n to a 16-bit integer value. \n\t\t\n\t\t
- int indicates that the value shall resolve to a System Verilog int, which is resolved to a \n 32-bit integer value. \n\t\t\n\t\t
- longint indicates that the value shall resolve to a System Verilog longint, which is resolved \n to a 64-bit integer value. \n\t\t\n\t\t
- shortreal indicates that the value shall resolve to a System Verilog shorint, which is resolved \n to a 32-bit floating point value. Both standard and scientific format (e.g 0.002 and 2e-3) are supported. \n This type applies also to minimum value and maximum value. \n\t\t\n\t\t
- real indicates that the value shall resolve to a System Verilog shortreal, which is resolved \n to a 64-bit floating point value. Both standard and scientific format (e.g. 0.002 and 2e-3) are supported. \n This type applies also to minimum value and maximum value. \n\t\t\n\t\t
- string indicates that the value shall contain text. \n
\n Value contains the mandatory default value of the module parameter. This value can be overridden in \n a design that instantiates this component. The value is given in SystemVerilog format and may be given as \n an expression. Any other text must be enclosed within quotes e.g. \"Any text\".\n
\n\n By selecting a choice, the user can restrict the allowed module parameter values to a set of \n predefined values. Possible values are defined in the choices of the containing component.\n
\n\n Minimum value and maximum value define the lower and upper boundary for the module parameter \n value. If the selected type is bit or string, these fields have no effect.\n
\n\t\n\t OO usage specifies how this model parameter is used. Default is 'non-typed' since such parameters \n are found in all languages, i.e. all VHDL types are non-typed. 'Typed' parameters appear in \n object-oriented languages, i.e. in C++. 'Runtime' parameters are parameters, whose value is set at run-time.\n
\n\n Resolve specifies the configuration of the model parameter. Possible resolve values are:\n
\n- \n
- immediate indicates that the the value is defined within the containing component. The value \n cannot be overridden by the user or a generator in design configuration. This is the default value \n\n
- user indicates that the user can override the default value in design configuration. Generators \n are not allowed to change the value. \n\n
- generated indicates that the a generator can override the default value in design configuration.\n \n
\n Bit vector left and bit vector right define the left and right bounds of the bit vector.\n These are valid only for a bit type parameter. A valid bit vector requires both the left and the right bit \n vector values.\n
\n\n Array left and Array right specify the left and right sides of array dimension for the \n parameter in an output language e.g. Verilog. Both of these are vendor attributes. The values can be given \n as an expression, but they must resolve into a decimal number. In order to get a valid array, both \n array left and array right values must be given.\n
\n\t\n\t Usage count displays the number of references made to this module parameter. Selecting the usage \n count of a module parameter displays a reference analysis for it. The usage count can not be changed \n manually.\n\t
\n\n Module parameters editor contains a context menu (rigth mouse button) that has the following options:\n
\n- \n
- Add new module parameter (Add row) \n
- Remove module parameter (Remove row) \n
- Clear the selected cells \n
- Copy the contents of the selected cells to clipboard \n
- Paste the contents of the clipboard to the selected cells \n
Parameters
\n\n Parameters are optional and can specify any parameter data value(s) specific for this component instantiation.\n These parameters do not have direct connection to HDL, but may be used to configure IP-XACT elements, including the module parameters.\n For more information on parameters, see the component parameter editor.\n
\n\n \n\n" }, { "path": "Help/componenteditor/componentInstantiations.html", "content": "\n\n \n \n \n
Component instantiations editor
\n\n Component instantiations define how a specific component instance is associated with a view.\n This editor can be used to add and remove component instantiations.\n
\n\n Each component instantiation contains a mandatory, unique name, a display name and a \n textual description to identify the component instantiations.\n
\n\n Language specifies the HDL used for a specific instantiation, for example, verilog or vhdl.\n
\n\n Component instantiations editor contains a context menu (right mouse button) providing following options:\n
\n- \n
- Add new instantiation (Add row) \n
- Remove instantiation (Remove row) \n
- Clear the selected cells \n
- Copy the contents of the selected cells to clipboard \n
- Paste the contents of the clipboard to the selected cells \n
Component
\n\nAn IP-XACT component describes data of any component, both flat and hierarchical, hardware and software. Most importantly it describes components external interface, such as ports and parameters, but also internal features, such as remap state and memory maps. On the other hand, many properties are parametrizable, and thus tied to the external interface.
\n\nA component may also refer to non-IP-XACT files, such as HDL source files and documentation. Thus components are vital for integration with non-IP-XACT tools and formats.
\n\n\n" }, { "path": "Help/componenteditor/cpu.html", "content": "\n\n \n \n \nCPU editor
\n\n The cpu editor can be used to edit the details of a cpu within a component.\n
\n\t\n\t Name is a mandatory identifier for the cpu.\n
\n\n Display name is an optional and used for a more user-friendly identifier.\n
\n\n Description is an optional field for textual description of the cpu.\t\t\n
\n \nGeneral settings
\n\n\n Is present is optional and allows the enabling/disabling of a cpu presence \n in the component. Value 1 indicates that the cpu is present in the \n component whereas value 0 marks the cpu to be treated as if it does not exist. \n Is present can be given as a SystemVerilog expression, but it must evaluate to 1 or 0.\n
\n\n\n Address spaces specify the logical address space(s) of the cpu.\n When a master bus interface\n of a component references the same address spaces, there's a\n link link between the programmable core and the interface. This\n information helps in generating a board support\n package (BSP) and picking appropriate programmable components\n into system design. CPU definition should not be repeated on a\n higher level component (one that instantiates a CPU).\n
\n\n \n\n" }, { "path": "Help/componenteditor/cpu2022.html", "content": "\n\n \n \n \nCPU editor
\n\n The cpu editor can be used to edit the details of a cpu within a component.\n
\n\t\n\t Name is a mandatory identifier for the cpu.\n
\n\n Display name is an optional and used for a more user-friendly identifier.\n
\n\n Short description is an optional field for compact description of the cpu.\n
\n\n Description is an optional field for textual description of the cpu.\t\t\n
\n \nGeneral settings
\n\n\n Memory map is mandatory and maps the address space defined by range and \n width to a memory map in the component.\n
\n\n\n Range is mandatory and defines the address range in the memory map\n accessible by the cpu.\n
\n \n\n Width is mandatory and defines the bit width of a row in the memory\n map for the cpu.\n
\n\n\n Address unit bits (AUB) is an optinal field that defines the number \n of data bits each address increment in the address space contains. \n The default setting for a cpu address space is byte addressable (8 bits).\n
\n\nRegions
\n\n Regions editor can be used to describe sections of the address space available\n for the cpu by splitting it into smaller regions.\n
\n\n\n\t Name is a mandatory identifier for the region.\n
\n\n Display name is an optional and used for a more user-friendly identifier.\n
\n\n Short description is an optional field for compact description of the region.\n
\n\n Offset is mandatory and defines the starting address of the region in address unit bits.\n\t
\n\t\n\t\tRange is mandatory and defines the size of the region in address unit bits.\n
\n\n Description is an optional field for textual description of the region.\t\t\n
\n\n\n Regions editor provides a context menu (right mouse button) with\n the following options:\n
\n- \n
- Add new region (Add row) \n
- Remove region (Remove row) \n
- Clear the selected cells \n
- Copy the contents of the selected cells to clipboard \n
- Paste the contents of the clipboard to the selected cells \n
- Copy selected element to clipboard (Copy elements) \n
- Paste the element from the clipboard (Paste elements) \t \n
- Import a csv-file to the editor \n
- Export the contents of the editor to a csv-file \n
CPUs editor
\n\n The cpus editor lists the programmable cores the component\n contains. This way the tools can recognize them and distinguish\n from hardwired components. One component can have multiple cores.\n
\n\t\n\t Name is a mandatory identifier for the cpu.\n
\n\n Display name is an optional and used for a more user-friendly identifier.\n
\n\n\t Address space references specify the logical address space of the cpu. \n When a master bus interface of a component references the same address \n spaces, there's a link link between the programmable core and the interface.\n This information helps in generating a board support\n package (BSP) and picking appropriate programmable components\n into system design. CPU definition should not be repeated on a\n higher level component (one that instantiates a CPU).\n
\n\t\n Description is an optional field for textual description of the cpu.\t\t\n
\n\n Cpus editor provides a context menu (right mouse button) with\n the following options:\n
\n- \n
- Add new cpu (Add row) \n
- Remove cpu (Remove row) \n
- Clear the selected cells \n
- Copy the contents of the selected cells to clipboard \n
- Paste the contents of the clipboard to the selected cells \n
- Import a csv-file to the editor \n
- Export the contents of the editor to a csv-file \n
\n
\n EXAMPLE.\n Example SoC has two CPUs and both refer to an address space. \n The first CPU is bound to a master bus interface through address space \n AS0 whereas the second has only a local memory map in AS1. \n Consequently, cpuA has access to the global address space of \n the master bus interface and cpuB does not.
\n ![\"example\"](\"../images/cpus.png\")
\n
CPUs editor
\n\n The cpus editor lists the programmable cores the component\n contains. This way the tools can recognize them and distinguish\n from hardwired components. One component can have multiple cores.\n
\n\t\n\t Name is a mandatory identifier for the cpu.\n
\n\n Display name is an optional and used for a more user-friendly identifier.\n
\n\n Short description is an optional field for compact description of the cpu.\n
\n\n Memory map reference is mandatory and maps the address space defined \n by range and width to a memory map in the component.\n
\n\n Range is mandatory and defines the address range in the memory\n map accessible by the cpu.\n
\n\n Width is mandatory and defines the bit width of a row in the memory\n map for the cpu.\n
\n\n Address unit bits (AUB) is an optinal field that defines the number \n of data bits each address increment in the address space contains. \n The default setting for a cpu address space is byte addressable (8 bits).\n
\n\t\n Description is an optional field for textual description of the cpu.\t\t\n
\n\n Cpus editor provides a context menu (right mouse button) with\n the following options:\n
\n- \n
- Add new cpu (Add row) \n
- Remove cpu (Remove row) \n
- Clear the selected cells \n
- Copy the contents of the selected cells to clipboard \n
- Paste the contents of the clipboard to the selected cells \n
- Import a csv-file to the editor \n
- Export the contents of the editor to a csv-file \n
\n
\n EXAMPLE.\n Example SoC has two CPUs and both refer to a memory map. \n The first memory map is bound to an initiator bus interface using\n a subspace map whereas the second has only a memory map with registers. \n Consequently, cpuA has access to the global address space of the \n initiator bus interface and cpuB does not.
\n ![\"example\"](\"../images/cpus22.png\")
\n
Design configuration instantiation editor
\n\n Design configuration instantiations detail how a specific design configuration instance is \n associated with a view. This editor can be used to edit the details of a single design configuration \n instantiation.\n
\n\n\t Name is a mandatory identifier for the design configuration instantiation.\n
\n\n Display name is an optional and used for a more user-friendly identifier.\n
\n\n Description is an optional field for textual description of the design configuration instantiation.\t\t\n
\n\n Design configuration reference specifies the used design configuration.\n
\n\n Configurable element values\n are instance-specific configuration options. It shows all the design configuration parameters.\n The value can be set to override the default value in the design configuration.\n The value is editable only, if the parameter resolve-property is set to 'user' or 'generated' within\n the design configuration. By default parameters that cannot be \n edited are filtered out, but will be shown when Show immediate values is selected.\n
\n\n Parameters are optional and can specify any parameter data value(s) specific for this design configuration instantiation.\n For more information on parameters, see the component parameter editor.\n
\n \n\n" }, { "path": "Help/componenteditor/designConfigurationInstantiation2022.html", "content": "\n\n \n \n \nDesign configuration instantiation editor
\n\n Design configuration instantiations detail how a specific design configuration instance is \n associated with a view. This editor can be used to edit the details of a single design configuration \n instantiation.\n
\n\n\t Name is a mandatory identifier for the design configuration instantiation.\n
\n\n Display name is an optional and used for a more user-friendly identifier.\n
\n\n Short description is an optional field for compact description of the design configuration instantiation.\n
\n\n Description is an optional field for textual description of the design configuration instantiation.\t\t\n
\n\n Design configuration reference specifies the used design configuration.\n
\n\n Configurable element values\n are instance-specific configuration options. It shows all the design configuration parameters.\n The value can be set to override the default value in the design configuration.\n The value is editable only, if the parameter resolve-property is set to 'user' or 'generated' within\n the design configuration. By default parameters that cannot be \n edited are filtered out, but will be shown when Show immediate values is selected.\n
\n\n Parameters are optional and can specify any parameter data value(s) specific for this design configuration instantiation.\n For more information on parameters, see the component parameter editor.\n
\n \n\n" }, { "path": "Help/componenteditor/designConfigurationInstantiations.html", "content": "\n\n \n \n \nDesign configuration instantiations editor
\n\n Design configuration instantiations detail how a specific design configuration instance is \n associated with a view. This editor can be used to add and remove design configuration \n instantiations.\n
\n\n Each design configuration instantiation contains a mandatory, unique name, a \n display name and a textual description to identify the design configuration instantiations.\n
\n\n Design configuration reference specifies the used design configuration.\n
\n\n Design configuration instantiations editor contains a context menu (right mouse button) providing \n following options:\n
\n- \n
- Add new instantiation (Add row) \n
- Remove instantiation (Remove row) \n
- Clear the selected cells \n
- Copy the contents of the selected cells to clipboard \n
- Paste the contents of the clipboard to the selected cells \n
Design instantiation editor
\n\n Design instantiations specify how a specific design instance is associated with a view. This editor \n can be used to edit the details of a single design instantiation.\n
\n\n\t Name is a mandatory identifier for the design instantiation.\n
\n\n Display name is an optional and used for a more user-friendly identifier.\n
\n\n Description is an optional field for textual description of the design instantiation.\t\t\n
\n\n Design reference details the design description and configuration values applied to it.\n
\n\n Configurable element values\n are instance-specific configuration options. It shows all the design parameters.\n The value can be set to override the default value in the design.\n The value is editable only, if the parameter resolve-property is set to 'user' or 'generated' within\n the design. By default parameters that cannot be \n edited are filtered out, but will be shown when Show immediate values is selected.\n
\n \n\n" }, { "path": "Help/componenteditor/designInstantiation2022.html", "content": "\n\n \n \n \nDesign instantiation editor
\n\n Design instantiations specify how a specific design instance is associated with a view. This editor \n can be used to edit the details of a single design instantiation.\n
\n\n\t Name is a mandatory identifier for the design instantiation.\n
\n\n Display name is an optional and used for a more user-friendly identifier.\n
\n\n Short description is an optional field for compact description of the design instantiation.\n
\n\n Description is an optional field for textual description of the design instantiation.\t\t\n
\n\n Design reference details the design description and configuration values applied to it.\n
\n\n Configurable element values\n are instance-specific configuration options. It shows all the design parameters.\n The value can be set to override the default value in the design.\n The value is editable only, if the parameter resolve-property is set to 'user' or 'generated' within\n the design. By default parameters that cannot be \n edited are filtered out, but will be shown when Show immediate values is selected.\n
\n \n\n" }, { "path": "Help/componenteditor/designInstantiations.html", "content": "\n\n \n \n \nDesign instantiations editor
\n\n Design instantiations specify how a specific design instance is associated with a view. This \n editor can be used to add and remove design instantiations.\n
\n\n Each design instantiation contains a mandatory, unique name, a display name and a \n textual description to identify the design instantiations.\n
\n\n Design reference details the design description and configuration values applied to it.\n
\n\n Design instantiations editor contains a context menu (right mouse button) providing following options:\n
\n- \n
- Add new instantiation (Add row) \n
- Remove instantiation (Remove row) \n
- Clear the selected cells \n
- Copy the contents of the selected cells to clipboard \n
- Paste the contents of the clipboard to the selected cells \n
Field editor
\n\n\n The field editor is used to edit the details of a field. For example user may\n define enumerated values that define the legal bit patterns of the field.\n
\n\n\n Name is a mandatory identifier for the field. The name must be unique\n within all the fields of the containing register.\n
\n\n Display name is an optional and used for a more user-friendly identifier.\n
\n\n Description is an optional field for textual description of the field.\n
\n\nField definition
\n\n Offset is mandatory and describes the starting bit of the field within\n the containing register.\n
\n\n Width is mandatory and speficies how many bits are included in the field.\n
\n\n Is present is optional and enables/disables a field presence in a\n register. Value 1 indicates that the field is present in the register\n whereas value 0 marks the field to be treated as if it does not exist. Is\n present can be given as a SystemVerilog expression, but it must evaluate to 1 or\n 0.\n
\n\n Field ID is optional identifier for the field. Fields can be referenced\n in indirect interfaces using this identifier.\n
\n\nField constraints
\n\n Volatile is optional and indicates that the field may change its value\n without write operations.\n
\n\n Access is optional and specifies the accessability of the field. The\n possible values are:\n
\n- \n
- read-write. Both read and write transactions may have an effect on this \n field. Write transactions may affect the contents of the field, and read\n transactions return a value related to the field. \n
- read-only. A read transaction to this field returns a value related\n to the value in the field. A write transaction to this field has undefined\n results. \n
- write-only. A write transaction to this address affects the contents of the\n field. A read transaction to this field has undefined results. \n
- read-writeOnce. Both read and write transactions may have an effect on this\n field. Only the first write transaction may affect the contents of the field,\n and read transactions return a value related to the values in the field. \n
- writeOnce. Only the first write transaction affects the contents of this\n field. \n
\n Modified write value is optional and describes how the data in the field\n is manipulated on a write operation. The basic operation without any setting is\n to store the written value 'as is'. Moreover, both bitwise and field-wise set/clear/toggle\n is also possible. The possible values are:\n
\n- \n
- oneToClear. Each written '1' bit will assign the corresponding bit to '0'. \n
- oneToSet. Each written '1' bit will assign the corresponding bit to '1'. \n
- oneToToggle. Each written '1' bit will toggle the corresponding bit. \n
- zeroToClear, zeroToSet, zeroToToggle. Similar to previous ones, except that\n written '0' bit triggers the action. \n
- clear. Each write operation will clear all bits in the field to '0'. \n
- set. Each write operation will set all bits in the field to '1'. \n
- modify. Indicates that after a write operation, all bits in the field\n can be modified. \n
- ' ' (empty setting). Indicates that the value written to a field\n is the value stored in the field. This is the default value. \n
\n Read action is optional and specifies if some action happens to the field\n after a read operation. By default the field is unmodified. The possible\n values are:\n
\n- \n
- clear. All bits in the field are cleared to '0' after a read operation. \n
- set. All bits in the field are set to '1' after a read operation. \n
- modify. Indicates that the bits of the field are modified in some\n way after a read operation. \n
- ' ' (empty setting). Indicates that the field is not modified\n after a read operation. This is the default. \n
\n Testable is optional and specifies if the field is testable by an\n automated register test.\n
\n\n Test constraint is optional and specifies the constaints for the automated\n tests for the field. The possible values are:\n
\n- \n
- unConstrained. There are no constraints for the written or read data. This\n is the default setting. \n
- Restore. The field value must be restored to its original value before\n accessing another register. \n
- WriteAsRead. The data written to a field must be same that was read\n previously from the field \n
- ReadOnly. Indicates that the field can only be read. \n
\n The write value constraints are used to define what are the legal values\n user may write to a field. The possible values are:\n
- \n
- No constraints. Indicates that there are no constraints to values to be written. \n
- Write as read. Inidcates that only legal values to be written are the same\n that were previously read from the field. \n
- Use enumerated values. Indicates that the defined enumerated values are the\n only legal values that can be written. \n
- Set minimum and maximum limits. Indicates that the minimum and maximum limits\n can be set for the value written to the field. \n
Resets
\n\t\n\t\tResets describe the reset values of the field. Each reset has the following subelements:\n\t\t
- \n\t\t\t
- Reset type reference. Identifies the defined reset. This should correspond to a\n\t\t\t\tuser-defined reset type element. Default value is HARD, and only one reset can be defined as that. \n\t\t\t
- Reset value is mandatory and defines the actual reset value on reset. Reset value uses\n\t\t\t\tSystemVerilog syntax for binary values. The number of bits must be equal to the field size. \n\t\t\t
- Reset mask is optional and defines the bits that have a known reset value. Bit\n\t\t\t\tvalue of 1 means that the corresponding bit has a known reset value whereas 0 means that\n\t\t\t\tthe value is unknown. Reset mask uses SystemVerilog syntax for binary values e.g. 'b1011,\n\t\t\t\t4'b1011, and 4'b10_11 are all valid values. The number of bits must be equal to the field size. \n\t\t
Enumerations table
\n\n The enumerated values table enables the defining of bit patterns that can be identified\n by a name. This can be used to define the legal bit patterns for a field or to define\n some default settings to help configuration of the field.\n
\n\n\n Each enumeration contains a unique name of the enumeration (mandatory), an\n optional display name and description.\n
\n\n Value defines the value to assign to the specified name (mandatory).\n
\n\n Usage defines the software access condition under which this name value pair\n is valid. Possible values are: read, write and read-write.\n
\n\n\n" }, { "path": "Help/componenteditor/field2022.html", "content": "\n\n\n \n \nField editor
\n\n\n The field editor is used to edit the details of a field. For example user may \n define enumerated values that define the legal bit patterns of the field.\n
\n\n\n Name is a mandatory identifier for the field. The name must be unique\n within all the fields of the containing register.\n
\n\n Display name is an optional and used for a more user-friendly identifier.\n
\n\n Short description is an optional field for compact description of the field.\n
\n\n Description is an optional field for textual description of the field.\n
\n\nField definition
\n\n Offset is mandatory and describes the starting bit of the field within\n the containing register.\n
\n\n Width is mandatory and speficies how many bits are included in the field.\n
\n\n Volatile is optional and indicates that the field may change its value\n without write operations.\n
\n\n \n\tResets
\n\t\n Resets describe the reset values of the field. Each reset has the following subelements:\n\t\t
- \n
- Reset type reference. Identifies the defined reset. This should correspond to a\n\t\t\t\tuser-defined reset type element. Default value is HARD, and only one reset can be defined as that. \n
- Reset value is mandatory and defines the actual reset value on reset. Reset value uses\n\t\t\t\tSystemVerilog syntax for binary values. The number of bits must be equal to the field size. \n
- Reset mask is optional and defines the bits that have a known reset value. Bit\n\t\t\t\tvalue of 1 means that the corresponding bit has a known reset value whereas 0 means that\n\t\t\t\tthe value is unknown. Reset mask uses SystemVerilog syntax for binary values e.g. 'b1011,\n\t\t\t\t4'b1011, and 4'b10_11 are all valid values. The number of bits must be equal to the field size. \n
Enumerations table
\n\n The enumerated values table enables the defining of bit patterns that can be identified\n by a name. This can be used to define the legal bit patterns for a field or to define\n some default settings to help configuration of the field.\n
\n \n\n Each enumeration contains a unique name of the enumeration (mandatory), an\n optional display name and description.\n
\n\n Value defines the value to assign to the specified name (mandatory).\n
\n\n Usage defines the software access condition under which this name value pair\n is valid. Possible values are: read, write and read-write.\n
\n\nField access policies table
\n\nField access policies define field access properties for different operating modes.
\n\n\n Mode(s) contains references to component modes. It is optional, and defines for which \n component modes the field access policy is active. If a field access policy contains no mode references, \n it is active for all component modes not already referenced by other field access policies \n (i.e. only one field access policy without mode references may exist).\n\n A field access policy is active, if it references an active mode and has the highest priority\n (i.e. the lowest priority value) among the field access policies of the field.\n
\n\n Access is optional and specifies the accessability of the field when that field \n access policy is active. The possible values are:\n
\n- \n
- read-write. Both read and write transactions may have an effect on this \n field. Write transactions may affect the contents of the field, and read\n transactions return a value related to the field. \n
- read-only. A read transaction to this field returns a value related\n to the value in the field. A write transaction to this field has undefined\n results. \n
- write-only. A write transaction to this address affects the contents of the\n field. A read transaction to this field has undefined results. \n
- read-writeOnce. Both read and write transactions may have an effect on this\n field. Only the first write transaction may affect the contents of the field,\n and read transactions return a value related to the values in the field. \n
- writeOnce. Only the first write transaction affects the contents of this\n field. \n
\n Read action is optional and specifies if some action happens to the field\n after a read operation. By default the field is unmodified. The possible\n values are:\n
\n- \n
- clear. All bits in the field are cleared to '0' after a read operation. \n
- set. All bits in the field are set to '1' after a read operation. \n
- modify. Indicates that the bits of the field are modified in some\n way after a read operation. \n
- ' ' (empty setting). Indicates that the field is not modified\n after a read operation. This is the default. \n
\n Read response is optional and describes the expected read value of the field in a \n certain mode. If not present, then the reset value is expected to be read.\n
\n\n Testable is optional and specifies if the field is testable by an\n automated register test.\n
\n\n Test constraint is optional and specifies the constaints for the automated\n tests for the field. Can be set only when testable is set to true. The possible values are:\n
\n- \n
- unConstrained. There are no constraints for the written or read data. This\n is the default setting. \n
- Restore. The field value must be restored to its original value before\n accessing another register. \n
- WriteAsRead. The data written to a field must be same that was read\n previously from the field \n
- ReadOnly. Indicates that the field can only be read. \n
\n Reserved is optional and indicates if the field is reserved for other use.\n
\n\n\n Modified write value is optional and describes how the data in the field\n is manipulated on a write operation. The basic operation without any setting is\n to store the written value 'as is'. Moreover, both bitwise and field-wise set/clear/toggle\n is also possible. The possible values are:\n
\n- \n
- oneToClear. Each written '1' bit will assign the corresponding bit to '0'. \n
- oneToSet. Each written '1' bit will assign the corresponding bit to '1'. \n
- oneToToggle. Each written '1' bit will toggle the corresponding bit. \n
- zeroToClear, zeroToSet, zeroToToggle. Similar to previous ones, except that\n written '0' bit triggers the action. \n
- clear. Each write operation will clear all bits in the field to '0'. \n
- set. Each write operation will set all bits in the field to '1'. \n
- modify. Indicates that after a write operation, all bits in the field\n can be modified. \n
- ' ' (empty setting). Indicates that the value written to a field\n is the value stored in the field. This is the default value. \n
\n The write value constraints are used to define what are the legal values\n user may write to a field. The possible values are:\n
- \n
- No constraints. Indicates that there are no constraints to values to be written. \n
- Write as read. Inidcates that only legal values to be written are the same\n that were previously read from the field. \n
- Use enumerated values. Indicates that the defined enumerated values are the\n only legal values that can be written. \n
- Set minimum and maximum limits. Indicates that the minimum and maximum limits\n can be set for the value written to the field. \n
File editor
\n\n File editor can be used to edit the details of a single file within a file set.\n
\n\n\n Name field contains the relative file path from the containing component XML-file to this file.\n The name can be changed in the file set editor.\n
\n\n Description shows a used given description regarding the currently active file.\n
\n\n File types list specifies the type of the file. File type can be used i.e. when specifying\n build commands for a group of files. A file can have multiple file types. \n
\n\nGeneral options
\n\n Logical name specifies e.g. a VHDL library where the VHDL-file will be compiled to.
\n Generators can override logical name defines if the logical name can be \n overridden by another process.\n
\n File is structural RTL indicates if the file contains only a structural\n Register Transfer Level (RTL) description i.e. no behavioral code.\n
\n\n File is include file indicates if the file is an include file e.g. C-header file.\n
\n\n File contains external declarations can be used to indicate that the file contains \n external declarations and is needed by other files in this file set.\n
\n\nBuild command
\n\n Target file specifies a path to the file that is derived from this file when build process is \n run. A new file path can be entered or an existing file can be searched with \"Browse...\".\n
\n\n Build command can be used to define a build command and flags specific to this file.\n\t For example, a C-source file could have a build command 'gcc' with flags '-O2'.\n
\n\n Flags can either replace default flags (e.g. those specified for this file type) \n in the build script or be appended to them. The value can be given as an \n expression, but must evaluate to 1 or 0.\n
\n\nExternal dependencies and defines
\n\n Exported names contains a list names defined within the file that can be \n\t referenced externally.\n
\n\n Image types contains a list of the current files relations to executable image types in \n the design.\n
\n\n Dependent directories contains a list of directory paths containing (include) files on which the \n file depends.\n
\n\t\n\n" }, { "path": "Help/componenteditor/fileset.html", "content": "\n\n \n \n \nFile set editor
\n\n File set editor can be used to edit the details of a single file set. These file sets can be used to \n group files together to be referenced by other sections of a component.\n
\n\n Name is a mandatory identifier for the file set.\n
\n\n Display name is an optional and used for a more user-friendly identifier.\n
\n\n Description is an optional field for textual description of the file set.\n
\n\n Group identifier can be used to describe the function or purpose of the file set with a single\n unbounded word. Group identifiers can contain several identifiers and the number of possible \n identifiers is not limited. However, the editor suggests the following options:\n
\n- \n
- diagnostics \n
- documentation \n
- projectFiles \n
- simulation \n
- sourceFiles \n
Files
\n\n Files editor lists the files contained within the file set.\n\t
\n\t\n Each file has a file name identifying the file. The name is mandatory and it is \n\t determined automatically from the file path.\n
\n\n File path is mandatory and defined as relative to the component XML-file, \n\t as an absolute path or as an external URI. If an URI is used, the schema must be explicitly \n\t defined (e.g. http://...).\n
\n\n File type is mandatory and helps categorize the file and links files to their build command (see below). \n\t A file can have more than one type.\n
\n\n Description is a freely formatted text describing a single file.\n
\n\n New files can be added by creating new rows, browsing the files using the context menu option described below\n or by drag-dropping the files onto the editor. If the order of files is important for e.g. compilation then \n the files should be listed in the required order. The order of the files can be changed by dragging the rows.\n
\n\n The files box also contains a context menu (right mouse button) that has the following options:\n
\n- \n
- Add new files to the file set by browsing the file system (Add file(s)...) \n
- Add new file to the file set (Add row) \n
- Remove file from file set (Remove row) \n
- Clear the selected cells \n
- Copy the contents of the selected cells to clipboard \n
- Paste the contents of the clipboard to the selected cells \n
- Import a csv-file to the editor \n
- Export the contents of the editor to a csv-file \t \n
Default build commands
\n\n Default build command defines how to build the files within the file set by e.g. running gcc\n for C files or vcom for VHDL.\n
\n\n File type defines which files are build by the given command.\n
\n\n Flags define the command line options for the command e.g. -Wall.\n
\n\n The defined command can either replace default flags defined in the target file or be \n appended to it. The value can be given as an expression, but must evaluate to 1 or 0.\n
\n\nDependent directories
\n\n Dependent directories can specify a freetext list of paths to directories on which this file\n set depends, e.g. directories of include files.\n
\n\n \n" }, { "path": "Help/componenteditor/fileset2022.html", "content": "\n\n \n \n \nFile set editor
\n\n File set editor can be used to edit the details of a single file set. These file sets can be used to \n group files together to be referenced by other sections of a component.\n
\n\n Name is a mandatory identifier for the file set.\n
\n\n Display name is an optional and used for a more user-friendly identifier.\n
\n\n Short description is an optional field for compact description of the file set.\n
\n\n Description is an optional field for textual description of the file set.\n
\n\n Group identifier can be used to describe the function or purpose of the file set with a single\n unbounded word. Group identifiers can contain several identifiers and the number of possible \n identifiers is not limited. However, the editor suggests the following options:\n
\n- \n
- diagnostics \n
- documentation \n
- projectFiles \n
- simulation \n
- sourceFiles \n
Files
\n\n Files editor lists the files contained within the file set.\n\t
\n\t\n Each file has a file name identifying the file. The name is mandatory and it is \n\t determined automatically from the file path.\n
\n\n File path is mandatory and defined as relative to the component XML-file, \n\t as an absolute path or as an external URI. If an URI is used, the schema must be explicitly \n\t defined (e.g. http://...).\n
\n\n File type is mandatory and helps categorize the file and links files to their build command (see below). \n\t A file can have more than one type.\n
\n\n Description is a freely formatted text describing a single file.\n
\n\n New files can be added by creating new rows, browsing the files using the context menu option described below\n or by drag-dropping the files onto the editor. If the order of files is important for e.g. compilation then \n the files should be listed in the required order. The order of the files can be changed by dragging the rows.\n
\n\n The files box also contains a context menu (right mouse button) that has the following options:\n
\n- \n
- Add new files to the file set by browsing the file system (Add file(s)...) \n
- Add new file to the file set (Add row) \n
- Remove file from file set (Remove row) \n
- Clear the selected cells \n
- Copy the contents of the selected cells to clipboard \n
- Paste the contents of the clipboard to the selected cells \n
- Import a csv-file to the editor \n
- Export the contents of the editor to a csv-file \t \n
Default build commands
\n\n Default build command defines how to build the files within the file set by e.g. running gcc\n for C files or vcom for VHDL.\n
\n\n File type defines which files are build by the given command.\n
\n\n Flags define the command line options for the command e.g. -Wall.\n
\n\n The defined command can either replace default flags defined in the target file or be \n appended to it. The value can be given as an expression, but must evaluate to 1 or 0.\n
\n\nDependent directories
\n\n Dependent directories can specify a freetext list of paths to directories on which this file\n set depends, e.g. directories of include files.\n
\n\n \n" }, { "path": "Help/componenteditor/filesets.html", "content": "\n\n \n \n \nFile sets editor
\n\n File sets editor contains a summary table regarding each file set within the component. \n This table can be used to add and remove file sets.\n
\n\t\n Name is a mandatory identifier for the file set.\n
\n\n\t Group identifiers are optional and can be used to describe the function or purpose of \n\t the file with a single word. Group identifiers can contain multiple identifiers and \n\t the possible words are not limited. However, the editor suggests the following options:\n\t
- \n\t
- diagnostics \n\t
- documentation \n\t
- projectFiles \n\t
- simulation \n\t
- sourceFiles \n\t
\n Description is optional field for detailed description of the file set.\n\t
\n\n Right clicking an item in the editor provides a context menu that can be used to:\n
\n- \n
- Add a new file set to the component (Add row) \n
- Remove a file set (Remove row) \n
- Clear the selected cells \n
- Copy the contents of the selected cells to clipboard \n
- Paste the contents of the clipboard to the selected cells \n
- Import a csv-file to the editor \n
- Export the contents of the editor to a csv-file \n
File dependencies
\n\n
![\"Kactus-extension\"](\"../images/appicon.png\")
\n\t\n
\n Below the file sets editor is a dependency table to display the dependencies between the \n files within all the file sets. File dependencies are typically introduced by include \n\t directives (e.g. in C) or instantiation of other modules (e.g. sub-modules in Verilog).\n\t Kactus2 uses plugins to automatically analyse dependencies based on the file types.\n
\n\t\n Status shows if the file has changed since the last dependency analysis.\n
\n\n\t Path identifies the file.\n
\n\n\t Filesets shows the fileset(s) containing the file.\n
\n\n\t # column is used create custom dependencies. The first left-click on the mouse \n\t starts the dependency from the file on the clicked line and the second click ends the \n\t dependency to the file on the line. The first file is now dependent on the second file.\n
\n\n\t Dependencies show the dependencies for the file. A file dependent on another has a \n\t round end point of the arrow on the line whereas the required file has an arrow head on the \n\t line. Automatically created dependencies are denoted in black and user created dependencies\n\t in magenta. A file can have arbitrary number of depenedencies. Clicking on the arrow shows \n\t additional information about the dependency in the Dependency Information below.\n\t
\n\t \nFile set source directories
\n \t\n Kactus2 will search the directories defined here for files to be automatically\n added into the component file sets.\n
\n\n\tDependency information
\n \t\n Description displays the description of the file dependency.\n
\n\n\t Bidirectional indicates that both of the files are dependent on each other.\n
\n\n\t Locked can be set to protect the depencendy from being changed without explicitly\n\t re-opening the lock.\n
\n\t\n\t Reverse Direction changes the dependent and prerequisite file relation to the\n\t opposite of the current state.\n\t
\n\n
\n EXAMPLE. The names of filesets do not need to be same as directories\n (vhdlSource vs. vhd/) but they can be (e.g. syn).
\n ![\"screen](\"../images/filesets.png\")
\n
General editor
\n\n General editor contains the general information of a component.\n
\n\n VLNV-identifier and the file path to the xml-file are\n shown on top. These fields cannot be modified after\n creation. Changes require that the component must be saved as\n new component with new VLNV.\n
\n\t\n\t\tCompatibility shows the component IP-XACT revision compatibility.\n\t
\n\t\n\t\tDescription text box can store a textual description of the component.\n\t
\n\t \n\tKactus attributes
\n\n
\n\t\n
\n Kactus attributes help to classify and categorize one's\n IPs. They are Kactus2-specific extension to the IP-XACT standard\n and describe the level (single IP vs. system), implementation\n style, and whether modification is allowed. Only the\n implementation style applies for SW components.
\n
| Attribute name | \n\tAttribute value | \n\tValue description | \n\t
|---|---|---|
| Product hierarchy | \n\tProduct | \n\tWhole product, which may contain multiple boards and\n\t computers. | \n\t
| Board | \n\tRepresents circuit board, e.g. develoment- or final\n\t hardware platform. | \n\t|
| Chip | \n\tRepresents a physical chip i.e. some specific\n\t FPGA-chip. | \n\t|
| SoC | \n\tA system on chip, set of intercconected IPs. | \n\t|
| IP | \n\tA single IP-block (which might be hierarchical) | \n\t|
| Flat | \n\t\tDoes not fit into any other category. | \n\t|
| Firmness | Template | Used as\n\t a base for creating new components, but must not be used as\n\t such. It should be copied and then saved with new VLNV. | \n\t
| Mutable | \n\tComponent is fully modifiable. | \n\t|
| Fixed | Component cannot be configured in any way\n\t and it is frozen to it's final state. | \n\t|
| Implementation (cannot be modified\n\t after creation) | HW | Hardware\n\t implementation, such as VHDL or Verilog | \n\t
| SW | \n\tSoftware implementation, such as C | \n\t|
| SYS | Contains information about the SW component\n\t mapping to the underlying HW platform. | \n\t
\n\t\tTags is an optional set of user-defined categorizations for the component. \n\t\tEach tag has a name and a color. Tags can be used to filter items in the IP-XACT library\n\t\tview.\n\t
\n\t\n\tCopyright information
\t\n\n
\n\t\n
\n Author is an optional field for the author of the component.\n
\n\t\n\n License is an optional field for identifying the license applicable to the component.\n
\n\t\t\n\t\t\n\tXML header
\n\n XML header shows and allows editing the comment lines in\n the beginning of XML file, i.e. those inside tags <!-- and\n -->.\n
\n\t\n\t\n\tComponent preview
\n\n Component preview box on the right of the editor displays how the component will look like when\n instantiated in a design. The preview displays the bus interfaces of the component and also the\n ports that are marked as ad-hoc.\n
\n \n\n" }, { "path": "Help/componenteditor/general2022.html", "content": "\n\n \n \n \nGeneral editor
\n\n General editor contains the general information of a component.\n
\n\n VLNV-identifier and the file path to the xml-file are\n shown on top. These fields cannot be modified after\n creation. Changes require that the component must be saved as\n new component with new VLNV.\n
\n\t\n\t\tCompatibility shows the component IP-XACT revision compatibility.\n\t
\n\n Display name is an optional field and used for a more user-friendly identifier.\n
\n\n Short description is an optional field for compact description of the component.\n
\n\t\n\t\tDescription text box can store a textual description of the component.\n\t
\n\t \n\tKactus attributes
\n\n
\n\t\n
\n Kactus attributes help to classify and categorize one's\n IPs. They are Kactus2-specific extension to the IP-XACT standard\n and describe the level (single IP vs. system), implementation\n style, and whether modification is allowed. Only the\n implementation style applies for SW components.
\n
| Attribute name | \n\tAttribute value | \n\tValue description | \n\t
|---|---|---|
| Product hierarchy | \n\tProduct | \n\tWhole product, which may contain multiple boards and\n\t computers. | \n\t
| Board | \n\tRepresents circuit board, e.g. develoment- or final\n\t hardware platform. | \n\t|
| Chip | \n\tRepresents a physical chip i.e. some specific\n\t FPGA-chip. | \n\t|
| SoC | \n\tA system on chip, set of intercconected IPs. | \n\t|
| IP | \n\tA single IP-block (which might be hierarchical) | \n\t|
| Flat | \n\t\tDoes not fit into any other category. | \n\t|
| Firmness | Template | Used as\n\t a base for creating new components, but must not be used as\n\t such. It should be copied and then saved with new VLNV. | \n\t
| Mutable | \n\tComponent is fully modifiable. | \n\t|
| Fixed | Component cannot be configured in any way\n\t and it is frozen to it's final state. | \n\t|
| Implementation (cannot be modified\n\t after creation) | HW | Hardware\n\t implementation, such as VHDL or Verilog | \n\t
| SW | \n\tSoftware implementation, such as C | \n\t|
| SYS | Contains information about the SW component\n\t mapping to the underlying HW platform. | \n\t
\n\t\tTags is an optional set of user-defined categorizations for the component. \n\t\tEach tag has a name and a color. Tags can be used to filter items in the IP-XACT library\n\t\tview.\n\t
\n\t\n\tCopyright information
\t\n\n
\n\t\n
\n Author is an optional field for the author of the component.\n
\n\t\n\n License is an optional field for identifying the license applicable to the component.\n
\n\t\t\n\t\t\n\tXML header
\n\n XML header shows and allows editing the comment lines in\n the beginning of XML file, i.e. those inside tags <!-- and\n -->.\n
\n\t\n\tValidation
\n\n\t\t\n
\n\n\tComponent preview
\n\n Component preview box on the right of the editor displays how the component will look like when\n instantiated in a design. The preview displays the bus interfaces of the component and also the\n ports that are marked as ad-hoc.\n
\n \n\n" }, { "path": "Help/componenteditor/indirectInterface.html", "content": "\n\n\n \n \nIndirect interface editor
\n\n\n Indirect interface editor is used to edit the details of a single indirect interface. \n An indirect interface defines access to memory maps that are not directly \n accessible through a standard bus interface. The indirect memory map\n is either a memory map within the containing component or accessed through\n a master bus interface of this component using a transparent bridge.\n
\n\n\n Name is a mandatory identifier for the indirect interface. The name must be unique\n within all the indirect interface of the containing component.\n
\n\n Display name is an optional and used for a more user-friendly identifier.\n
\n\n Description is an optional field for textual description of the indirect interface.\n
\n \nGeneral
\n\n\n Indirect address field is mandatory and defines the bit field used for\n addressing in the indirect interface.\n
\n\n Indirect data field is mandatory and defines the bit field used for\n data in read/write operations in the indirect interface.\n
\n\n Bits in Lau is optional and defines the number of bits addressable by\n the least significant address bit.\n
\n\n Endianness is optional and indicates whether the interface is 'big-endian' or \n 'little-endian' (default).\n
\n\nIndirect access target
\n\n Memory map defines the indirectly accessible memory map for \n the indirect interface. If a memory map has been defined,\n transparent bridges must be left empty.\n
\n\n Transparent bridge(s) define the master bus interface(s) that\n all transactions through this indirect interface are directed out of. \n If transparent bridges have been defined, memory map must be left empty.\n
\n\nParameters
\n\n Parameters are optional and can specify any parameter data value(s) specific for this indirect interface.\n For more information on parameters, see the component parameter editor.\n
\n\n\n\n" }, { "path": "Help/componenteditor/indirectInterface2022.html", "content": "\n\n\n \n \nIndirect interface editor
\n\n\n Indirect interface editor is used to edit the details of a single indirect interface. \n An indirect interface defines access to memory maps that are not directly \n accessible through a standard bus interface. The indirect memory map\n is either a memory map within the containing component or accessed through\n a master bus interface of this component using a transparent bridge.\n
\n\n\n Name is a mandatory identifier for the indirect interface. The name must be unique\n within all the indirect interface of the containing component.\n
\n\n Display name is an optional and used for a more user-friendly identifier.\n
\n\n Short description is an optional field for compact description of the indirect interface.\n
\n\n Description is an optional field for textual description of the indirect interface.\n
\n \nGeneral
\n\n\n Indirect address field is mandatory and defines the bit field used for\n addressing in the indirect interface.\n
\n\n Indirect data field is mandatory and defines the bit field used for\n data in read/write operations in the indirect interface.\n
\n\n Bits in Lau is optional and defines the number of bits addressable by\n the least significant address bit.\n
\n\n Endianness is optional and indicates whether the interface is 'big-endian' or \n 'little-endian' (default).\n
\n\nIndirect access target
\n\n Memory map defines the indirectly accessible memory map for \n the indirect interface. If a memory map has been defined,\n transparent bridges must be left empty.\n
\n\n Transparent bridge(s) define the master bus interface(s) that\n all transactions through this indirect interface are directed out of. \n If transparent bridges have been defined, memory map must be left empty.\n
\n\nParameters
\n\n Parameters are optional and can specify any parameter data value(s) specific for this indirect interface.\n For more information on parameters, see the component parameter editor.\n
\n\n\n\n" }, { "path": "Help/componenteditor/indirectInterfaces.html", "content": "\n\n\n \n \nIndirect interfaces editor
\n\n\n Indirect interfaces editor contains the summary of the indirect interfaces\n of the component. An indirect interface is used to define access to\n memory maps that are not directly accessible through a bus interface.\n This editor can be used to add and remove indirect interfaces to the containing component. \n
\n\n\n Name is a mandatory identifier for the indirect interface. The name must be unique\n within all the indirect interface of the containing component.\n
\n\n Display name is an optional and used for a more user-friendly identifier.\n
\n\n Indirect address field is mandatory and defines the bit field used for\n addressing in the indirect interface. A field ID must be defined for\n\t\tthe field to be considered a valid option here.\n
\n\n Indirect data field is mandatory and defines the bit field used for\n data in read/write operations in the indirect interface.\n\t\tA field ID must be defined for the field to be considered a valid option here.\n
\n\n Memory map defines the indirectly accessible memory map for \n the indirect interface. If a memory map has been defined,\n transparent bridges must be left empty.\n
\n\n Transparent bridges define the master bus interface(s) that\n all transactions through this indirect interface are directed out of. \n If transparent bridges have been defined, memory map must be left empty.\n Transparent bridges are shown here, but must be edited in the \n editor of the respective indirect interface.\n
\n\n Description is an optional field for textual description of the indirect interface.\n
\n\n
\n EXAMPLE 1. The memory map MM0 is accessible through slave bus interface accessIF.\n Indirect interface II0 identifies bitfields data and address in registers r0 and\n r1 which are used to access memory map MM1. The access to memory map\n MM1 occurs at the memory location defined by the content of the address field and\n the content of the field data is either written into register r6 in a write operation\n or read from r6 into field data in a read operation. \n
\n ![\"addr](\"../images/indirectMemoryMap.png\")
\n
\n EXAMPLE 2. The memory map MM0 is accessible through slave bus interface accessIF.\n Indirect interface II0 identifies bitfields data and address in registers r0 and\n r1 which are used to access other components through master bus interface outIF. \n
\n ![\"addr](\"../images/indirectBridge.png\")
\n
Instantiations editor
\n\n Instantiations editor provides a summary of the different\n\t instantiations of the component. Instantiations are\n\t used in views to represent different aspects\n\t of the view. Instantiations contain a mandatory, unique name, a display name and a textual\n description to identify the instantiations.\n\t This editor can be used to add and remove instantiations.\n\t
\n\t\n\t\n\t A component instantiation describes the details of instantiating the component in a hardware \n description language, for example, verilog or vhdl. This editor can be used to add and remove \n component instantiations.\n\t
\n\t\n\n A design configuration instantiation details how a specific design configuration instance is \n associated with a view. This editor can be used to add and remove design configuration \n instantiations.\n
Design configuration reference specifies the used design configuration.\n
\n A design instantiation specifies how a specific design instance is associated with a view. This \n editor can be used to add and remove design instantiations.\n
Design reference details the design description and configuration values applied to it.\n
\n The editor contains a context menu that contains following options:\n
\n- \n
- Add a new instantiation (Add row) \n
- Remove an instantiation (Remove row) \n
- Clear the selected cells \n
- Copy the contents of the selected cells to clipboard \n
- Paste the contents of the clipboard to the selected cells \n
- Import a csv-file to the editor \n
- Export the contents of the editor to a csv-file \n
\n\n \n\n" }, { "path": "Help/componenteditor/memorymap.html", "content": "\n\n\n \n \n
Memory map editor
\n\n Memory map editor can be used to edit the details of a memory map.\n
\n\n Memory maps visualization is shown on the right of the editor. The visualization\n can be expandped and minimized by clicking the expand arrow\n ![\"expand\"](\"../images/triangle_arrow_right.png\"){kind=icon}
\n and the minimize arrow\n ![\"minimize\"](\"../images/triangle_arrow_down.png\"){kind=icon}
. Selecting any part\n of the visualization will open the editor set for that item. The visualization can\n be resized by dragging the border between the editor and the visualization. Holding\n Ctrl-key while scrolling with the mouse wheel increases/decreases the width of the\n items.\n
\n Name is a mandatory identifier for the memory map.\n
\n\n Display name is an optional and used for a more user-friendly identifier.\n
\n\n Description is an optional field for textual description of the memory map.\n
\n\n Address unit bits (AUB) defines the number of data bits each address increment\n of the memory map contains, e.g. 8b or 32b. The default setting for a memory map\n is byte addressable (8 bits). E.g. if AUB=8, then 32-bit registers are at addresses\n 0x0, 0x4, 0x8... If AUB=32, they are in addresses 0x0, 0x1, 0x2... AUB is the unit\n for base addresses and ranges within the address map.
\n\n\t\t
\n Is present is optional and allows enabling/disabling of a memory map\n presence in a component. Value 1 indicates that the memory map\n is present in the component whereas value 0 marks the memory map to be\n treated as if it does not exist. Is present can be given as a SystemVerilog expression,\n but it must evaluate to 1 or 0.
\n\t\t\n\n Remap state identifies the name of the remap state for which the optional\n memory map elements are active. Memory maps are labeled with a default remap\n state, while memory remaps must be given a remap state. For more information\n on the remap states, see the remap states editor.\n
\n\n\n Slave interface binding shows which slave bus interfaces are used to access\n the memory map. The binding can only be set in the bus interface editor, but is\n shown here for convenience.\n
\n\nAddress blocks table
\n\n Address block specifies a single contiguous block, either a set of registers\n or a block of memory. Registers within the address block are further divided\n into bit fields. (IP-XACT allows bank or subspaceMap elements\n within the address block, but they are not yet supported by Kactus2 (v3.3,\n December 2016)).\n
\n\n Name is a mandatory identifier for the address block.\n
\n\n Base address is mandatory and specifies the starting address for the address block.\n It is expressed as address unit bits as defined in the containing memory map,\n\t\te.g. 8 or 32 bits.
\n\n Range is mandatory and specifies the size of the block in address unit bits.\n
\n\n\n Width is mandatory and specifies the data width in bits of a row in the\n\t\taddress block. It sets the\n maximum allowed size of a single transfer and also defines the maximum size of a\n single register. Register can be smaller but not wider than the value.\n
\n\n Usage is optional and is used to categorize the usage of the address block. The\n possible values are:\n
\n- \n
- Memory specifies the address block as memory.\n\t\tA memory address block cannot contain registers. \n
- Register specifies the entire address block to contain registers. \n
- Reserved specifies the entire address block as reserved for usage\n\t\tthat is unknown to IP-XACT. A reserved address block cannot include registers. \n
\n Access is optional and is used to specify the accessibility of the address block.\n\t\tThe possible values are:\n
\n- \n
- read-write. Both read and write transactions may have an effect on this address\n block. \n
- read-only. Only read transactions are allowed in this register. \n
- write-only. Only write transactions are allowed in this register. \n
- read-writeOnce. Read actions are allowed and the first write action may have\n an effect on this address block. \n
- writeOnce. Only the first write action affects the contents of this address\n block. \n
\n Volatile is optional and indicates that the stored value may change without master's\n write operation. For example, the timer value gets updated automatically and master\n must always issue a read to get the latest value.\n
\n\n\t\n Is present is optional and allows enabling/disabling of a address block\n presence in a memory map. Value 1 indicates that the address block\n is present in the memory map whereas value 0 marks the memory map to be\n treated as if it does not exist. Is present can be given as a SystemVerilog expression,\n but it must evaluate to 1 or 0.
\n\t\n\n
\n Description is an optional field for textual description of the address block.\n
\n\nSubspace maps table
\n\n\n Name is a mandatory identifier for the subspace map.\n
\n\n Base address is mandatory and specifies the starting address for the subspace\n map in address unit bits. The range is equal to the referenced address\n space or segment.\n
\n\n Master interface is a mandatory identifier for the bridged master bus interface\n that is accessed by the subspace map.\n
\n\n Segment is an optional reference to a segment within the\n referenced master bus interface. If a segment is defined,\n the access is limited to the specified segment instead of the whole\n address space.\n
\n\n Is present is optional and allows enabling/disabling of a subspace map\n presence in a memory map. Value 1 indicates that the subspace map\n is present in the memory map whereas value 0 marks the subspace map to be\n treated as if it does not exist. Is present can be given as a SystemVerilog expression,\n but it must evaluate to 1 or 0.\n
\n\n\n
\n EXAMPLE 1. A simple IP could have 1 memory map, 1 address block inside it, and three\n 32-bit registers: ctrl, data_in, and data_out. Ctrl allows both read and write accesses,\n data_in is write-only, and data_out is read-only. The lower part of ctrl register\n is divided into two 8-bit fields and designer can describe how they are used. The\n upper bits are not used. Data registers do not have field definitions.\n
\n
\n Number of Addresss unit bits(AUB) of the memory map is set to 8 bits. There are\n 3 registers with identical size (32b), Hence, range = 12 = 3 * 32/AUB = 3 * 32/8\n = 3 * 4. Let's assume base address=0x100. Since address block has 12 Bytes in total,\n it reserves the (byte) addresses 0x100-0x10B. It is good to set the width of the\n address block 32 b so that full register can be accessed at once. Smaller accesses\n (e.g. 1 byte at a time) are also allowed.\n
\n ![\"screen_cap_of_mem_map_visualization\"](\"../images/mem_map_visualization.png\")
\n
\n EXAMPLE 2. An opaque bridge provides access from a slave interface\n to a master interface through a specific memory region i.e. a subspace map.\n The address space and any memory maps connected to the master interface\n remain obscured (opaque) behind the subspace map.\n
\n
\n The slave bus interface accessIF provides access to memory map MM0 which contains\n an address block ab0 and a subspace map ssm0. The subspace map refers master bus\n interface outIF indicating that any access to memory locations within ssm0 are redirected\n out of bus interface outIF. The subspace map size will match the address space AS0 range\n (or segment range, if segment is specified) referenced in master interface outIF.\n Any interface connected to accessIF will have visibility only to ab0 and ssm0 within the\n memory map MM0 and no visibility to AS0 while still being able to transfer data to\n components connected to outIF.\n
\n ![\"subspace](\"../images/subspace_map.png\")
\n
Memory map editor
\n\n Memory map editor can be used to edit the details of a memory map.\n
\n\n Memory maps visualization is shown on the right of the editor. The visualization\n can be expandped and minimized by clicking the expand arrow\n \n and the minimize arrow\n . Selecting any part\n of the visualization will open the editor set for that item. The visualization can\n be resized by dragging the border between the editor and the visualization. Holding\n Ctrl-key while scrolling with the mouse wheel increases/decreases the width of the\n items.\n
\n Name is a mandatory identifier for the memory map.\n
\n\n Display name is an optional and used for a more user-friendly identifier.\n
\n\n Short description is an optional field for compact description of the memory map.\n
\n\n Description is an optional field for textual description of the memory map.\n
\n\n Address unit bits (AUB) defines the number of data bits each address increment\n of the memory map contains, e.g. 8b or 32b. The default setting for a memory map\n is byte addressable (8 bits). E.g. if AUB=8, then 32-bit registers are at addresses\n 0x0, 0x4, 0x8... If AUB=32, they are in addresses 0x0, 0x1, 0x2... AUB is the unit\n for base addresses and ranges within the address map.\n
\n\n Target interface binding shows which target bus interfaces are used to access\n the memory map. The binding can only be set in the bus interface editor, but is\n shown here for convenience.\n
\n \n\n Mode references identify operating modes for which a memory remap is active. Memory maps do not contain mode references,\n while memory remaps must be given at least one mode reference paired with a priority value. Each mode reference\n value must be unique within the containing memory map, while priorities do not have such limitations.\n
\n\nAddress blocks table
\n\n Address block specifies a single contiguous block, either a set of registers\n or a block of memory. Registers within the address block are further divided\n into bit fields.\n
\n\n Name is a mandatory identifier for the address block.\n
\n\n Base address is mandatory and specifies the starting address for the address block.\n It is expressed as address unit bits as defined in the containing memory map,\n\t\te.g. 8 or 32 bits.\n
\n\n Range is mandatory and specifies the size of the block in address unit bits.\n
\n\n Width is mandatory and specifies the data width in bits of a row in the\n\t\taddress block. It sets the\n maximum allowed size of a single transfer and also defines the maximum size of a\n single register. Register can be smaller but not wider than the value.\n
\n\n Usage is optional and is used to categorize the usage of the address block. The\n possible values are:\n
\n- \n
- Memory specifies the address block as memory.\n\t\tA memory address block cannot contain registers. \n
- Register specifies the entire address block to contain registers. \n
- Reserved specifies the entire address block as reserved for usage\n\t\tthat is unknown to IP-XACT. A reserved address block cannot include registers. \n
\n Access is optional and specifies the accessibility of the address block by modifying\n the first access policy of the address block. If multiple access policies exist, then the access value \n cannot be edited here and must be edited for each access policy separately in the address block editor. \n If no access policy exists, then one will be created for the address block when the access value is \n edited here. The possible access values are:\n
\n- \n
- read-write. Both read and write transactions may have an effect on this address\n block. \n
- read-only. Only read transactions are allowed in this register. \n
- write-only. Only write transactions are allowed in this register. \n
- read-writeOnce. Read actions are allowed and the first write action may have\n an effect on this address block. \n
- writeOnce. Only the first write action affects the contents of this address\n block. \n
\n Volatile is optional and indicates that the stored value may change without initiator's\n write operation. For example, the timer value gets updated automatically and initiator\n must always issue a read to get the latest value.\n
\n\n Description is an optional field for textual description of the address block.\n
\n\nSubspace maps table
\n\n\n Name is a mandatory identifier for the subspace map.\n
\n\n Base address is mandatory and specifies the starting address for the subspace\n map in address unit bits. The range is equal to the referenced address\n space or segment.\n
\n\n Initiator interface is a mandatory identifier for the bridged initiator bus interface\n that is accessed by the subspace map.\n
\n\n Segment is an optional reference to a segment within the\n referenced initiator bus interface. If a segment is defined,\n the access is limited to the specified segment instead of the whole\n address space.\n
\n\n Description is an optional field for textual description of the subspace map.\n
\n\n\n
\n EXAMPLE 1. A simple IP could have 1 memory map, 1 address block inside it, and three\n 32-bit registers: ctrl, data_in, and data_out. Ctrl allows both read and write accesses,\n data_in is write-only, and data_out is read-only. The lower part of ctrl register\n is divided into two 8-bit fields and designer can describe how they are used. The\n upper bits are not used. Data registers do not have field definitions.\n
\n
\n Number of Addresss unit bits(AUB) of the memory map is set to 8 bits. There are\n 3 registers with identical size (32b), Hence, range = 12 = 3 * 32/AUB = 3 * 32/8\n = 3 * 4. Let's assume base address=0x100. Since address block has 12 Bytes in total,\n it reserves the (byte) addresses 0x100-0x10B. It is good to set the width of the\n address block 32 b so that full register can be accessed at once. Smaller accesses\n (e.g. 1 byte at a time) are also allowed.\n
\n \n
\n EXAMPLE 2. An opaque bridge provides access from a target interface\n to an initiator interface through a specific memory region i.e. a subspace map.\n The address space and any memory maps connected to the initiator interface\n remain obscured (opaque) behind the subspace map.\n
\n
\n The target bus interface accessIF provides access to memory map MM0 which contains\n an address block ab0 and a subspace map ssm0. The subspace map refers initiator bus\n interface outIF indicating that any access to memory locations within ssm0 are redirected\n out of bus interface outIF. The subspace map size will match the address space AS0 range\n (or segment range, if segment is specified) referenced in initiator interface outIF.\n Any interface connected to accessIF will have visibility only to ab0 and ssm0 within the\n memory map MM0 and no visibility to AS0 while still being able to transfer data to\n components connected to outIF.\n
\n \n
Memory maps editor
\n\n Memory maps editor contains the summary of the memory maps and memory remaps contained in the\n component and can be used to add, remove and edit them.\n
\n\t\n Memory maps visualization is shown on the right of the editor. The visualization can be expandped\n and minimized by clicking the expand arrow \n and the minimize arrow . Selecting any part\n of the visualization will open the editor set for that item. The visualization can be resized by dragging \n\t\tthe border between the editor and the visualization.\n\t\tHolding Ctrl-key while scrolling with the mouse wheel increases/decreases the width of the items.\n\t
\n\t Memory map specifies the addressable area seen through a slave bus interface, e.g. the data and\n control register.
\n Memory remap describes additional memory map items that are mapped on the referencing slave \n\t bus interface in a specific remap state. If multiple memory remaps or remap state \n\t attributes are active, then the first memory remap listed shall be selected.\n
\nMemory map
\n\n Name is a mandatory identifier for the memory map.
\n\t \t \t \n\t\n Remap state is always 'default' for memory maps and cannot be changed. It applies only to memory\n\t remaps.
\n\t \n\t
\n Address unit bits (AUB) defines the number of data bits each address increment of the memory map\n contains, e.g. 8b or 32b. The default setting for a memory maps is byte addressable (8 bits).\n\t E.g. if AUB=8,\n then 32-bit registers are at addresses 0x0, 0x4, 0x8... If AUB=32, they are in addresses 0x0, 0x1, 0x2...\n AUB is the unit for base addresses and ranges within the address map.
\n\t\n\t \n Slave interface binding shows which slave bus interfaces are used to access the memory map.\n\t The binding can only be set in the bus interface editor, but is shown here for convenience.
\n \n\t\n Is present is optional and allows enabling/disabling of a memory map\n presence in a component. Value 1 indicates that the memory map\n is present in the component whereas value 0 marks the memory map to be\n treated as if it does not exist. Is present can be given as a SystemVerilog expression,\n but it must evaluate to 1 or 0.
\n\t\n\t\n\t Description is an optional field for textual description of the memory map.\n\n
Memory remap
\n\n Name is a mandatory identifier for the memory remap.
\n\t Memory remaps use the address unit bits and interface binding of the parent memory map.
\n Remap state identifies the name of the remap state for which the optional memory remap\n elements are active. See remap states for further information on remap states. \n\t Description is an optional field for textual description of the memory remap.\n
\n\t\nContext menu
\n\n Memory maps editor contains a context menu (right mouse button)\n providing following options:\n
\n- \n
- Add new memory map (Add memory map) \n
- Add a new memory remap to the selected memory map (Add memory remap) \n
- Remove memory map (Remove row) \n
- Clear the selected cells \n
- Copy the contents of the selected cells to clipboard \n
- Paste the contents of the clipboard to the selected cells \n
- Copy selected element to clipboard (Copy elements) \n
- Paste the element from the clipboard along with its sub-elements (Paste elements) \t \n
- Import a csv-file to the editor \n
- Export the contents of the editor to a csv-file \n
\n
\n EXAMPLE. Component AccelA has two memory maps MM0 and MM1 that are accessible through\n bus interface RegsIF. MM0 defines the hardware registers for read/write operations and\n MM1 provides a random-access memory block.\n
\n\n ![\"mem](\"../images/mem_map.png\")
\n
Memory maps editor
\n\n Memory maps editor contains the summary of the memory maps and memory remaps contained in the\n component and can be used to add, remove and edit them.\n
\n\t\n Memory maps visualization is shown on the right of the editor. The visualization can be expandped\n and minimized by clicking the expand arrow \n and the minimize arrow . Selecting any part\n of the visualization will open the editor set for that item. The visualization can be resized by dragging \n the border between the editor and the visualization.\n Holding Ctrl-key while scrolling with the mouse wheel increases/decreases the width of the items.\n\t
\n\t Memory map specifies the addressable area seen through a target bus interface, e.g. the data and\n control register.\n
\n\n Memory remap describes additional memory map items that are mapped on the referencing target \n\t bus interface in a specific mode. If multiple memory remaps or mode \n\t attributes are active, then the first memory remap listed shall be selected.\n
\n \nMemory map
\n\n Name is a mandatory identifier for the memory map.\n
\n\t \t \t \n\t\n Mode reference applies only to memory remaps and can be edited in the memory remap editor.\n
\n \t \n\t\n Address unit bits (AUB) defines the number of data bits each address increment of the memory map\n contains, e.g. 8b or 32b. The default setting for a memory maps is byte addressable (8 bits).\n\t E.g. if AUB=8,\n then 32-bit registers are at addresses 0x0, 0x4, 0x8... If AUB=32, they are in addresses 0x0, 0x1, 0x2...\n AUB is the unit for base addresses and ranges within the address map.\n
\n\t \n\n Target interface binding shows which target bus interfaces are used to access the memory map.\n The binding can only be set in the bus interface editor, but is shown here for convenience.\n
\n \n\t\n\t Description is an optional field for textual description of the memory map.\n
\n\nMemory remap
\n\n Name is a mandatory identifier for the memory remap.\n
\n\n\t Memory remaps use the address unit bits and interface binding of the parent memory map.\n
\n \n\n Mode reference identifies the name of the mode reference for which the optional memory remap\n element is active. Displays the mode reference value, if only one exists, otherwise the displayed value is either '[multiple]' or 'None'.\n The mode references can be edited in the memory remap editor. \n
\n\n\t\n Description is an optional field for textual description of the memory remap.\n
\n\t\nContext menu
\n\n Memory maps editor contains a context menu (right mouse button)\n providing following options:\n
\n- \n
- Add new memory map (Add memory map) \n
- Add a new memory remap to the selected memory map (Add memory remap) \n
- Remove memory map (Remove row) \n
- Clear the selected cells \n
- Copy the contents of the selected cells to clipboard \n
- Paste the contents of the clipboard to the selected cells \n
- Copy selected element to clipboard (Copy elements) \n
- Paste the element from the clipboard along with its sub-elements (Paste elements) \t \n
- Import a csv-file to the editor \n
- Export the contents of the editor to a csv-file \n
\n
\n EXAMPLE. Component AccelA has two memory maps MM0 and MM1 that are accessible through\n bus interface RegsIF. MM0 defines the hardware registers for read/write operations and\n MM1 provides a random-access memory block.\n
\n\n \n
Mode editor
\n\n The mode editor can be used to edit the details of a component mode.\n
\n\t\n\t Name is a mandatory identifier for the mode.\n
\n\n Display name is an optional and used for a more user-friendly identifier.\n
\n\n Short description is an optional field for compact description of the mode.\n
\n\n Description is an optional field for textual description of the mode.\t\t\n
\n\nCondition
\n\n The condition defines when the mode is active. If the condition expression evaluates\n to true, the component is operating in the defined mode. The condition may depend\n on run-time value of a port, register field and other modes. The expression accepts\n the following special functions:\n
- \n
- $ipxact_port_value( [port slice name] ) \n
- $ipxact_field_value( [field slice name] ) \n
- $ipxact_mode_condition( [mode name] ) \n
Condition ports
\n\n The condition ports can be referenced in the condition to check for their value\n in the mode. \n
\n\t\n\t Name is a mandatory identifier for the port reference.\n
\n\n\t Physical port is a mandatory and identifies the port in the \n component whose value may be checked in the condition.\n
\n \n\n Left and right bounds are optional for selecting a range of\n bits in the port. If no indices are defined, the whole port is selected.\n
\n\n Description is an optional field for textual description of the port.\t\t\n
\n\nCondition fields
\n\n The condition fields can be referenced in the condition to check for their bit\n pattern in the mode. \n
\n\t\n\t Name is a mandatory identifier for the field reference.\n
\n\n\t Field is a mandatory and identifies the field in the \n component whose bit pattern may be checked in the condition.\n
\n\n Leftmost bit and rightmost bit are optional for selecting a range of\n bits in the field. If no indices are defined, the whole field is selected.\n
\n\n Description is an optional field for textual description of the port.\t\t\n
\n\n\n
\n EXAMPLE. The mode named reset is active when the value of the bit 0 in the physical port\n button_in i.e. button_in[0:0] is equal to 1. \n
\n
\n ![\"Example](\"../images/modeExample.png\")
\n
Modes editor
\n\n The modes editor lists the operating modes of the component.\n
\n\t\n\t Name is a mandatory identifier for the mode.\n
\n\n Display name is an optional and used for a more user-friendly identifier.\n
\n\n Short description is an optional field for compact description of the mode.\n
\n\t\n Description is an optional field for textual description of the cpu.\t\t\n
\n\n Modes editor provides a context menu (right mouse button) with\n the following options:\n
\n- \n
- Add new mode (Add row) \n
- Remove mode (Remove row) \n
- Clear the selected cells \n
- Copy the contents of the selected cells to clipboard \n
- Paste the contents of the clipboard to the selected cells \n
- Import a csv-file to the editor \n
- Export the contents of the editor to a csv-file \n
Other clock drivers editor
\n\n Other clock drivers-editor shows the clocks within the component\n that are not directly associated with a top-level port. This\n kind of clocks could be i.e. virtual clocks or generated clocks.\n
\n\n The mandatory clock name identifies the other clock driver.\n
\n\n Clock source is optional and defines the physical path and name of the clock generation cell. \n E.g. a component instantiated in VHDL and its output, like 'i_clkGen/clk1'. The waveform of the clock signal \n has 4 parameters. Time units are either ps (picosecond) or ns (nanosecond).\n
\n\n Clock period defines the length of one cycle of clock pulse, e.g. 10 ns.\n
\n\n Pulse offset describes the time delay from start of the cycle to the first transition.\n
\n\n Pulse value defines the logic value which the first transition is made to, either 0 or 1.\n
\n\n Pulse duration specifies how long the value defined in pulse value is held, e.g. 5 ns.\n
\n\n Other clock drivers editor provides a context menu (right mouse\n button) with the following options:\n
\n- \n
- Add new clock (Add row) \n
- Remove clock (Remove row) \n
- Clear the selected cells \n
- Copy the contents of the selected cells to clipboard \n
- Paste the contents of the clipboard to the selected cells \n
- Import a csv-file to the editor \n
- Export the contents of the editor to a csv-file \n
\n
\n EXAMPLE. Component Foo has a regular clock input port ClkIn and two additional\n clock sources clk0 and clk1 generated by instantiation clk_gen.\n
\n\n ![](\"../images/clk_drivers.png\")
\n
Parameters editor
\r\n\r\n Parameters editor can be used to add, remove and modify\r\n parameters of a component. Parameters are name-value pairs to\r\n configure or hold information related to the containing\r\n component. Note that these are not equivalent of VHDL generics or\r\n\t Verilog parameters.\r\n\t In the columns, f(x) means that the value can be given as an expression.\r\n
\r\n\r\n Each parameter contains a mandatory name and an optional\r\n display name for more user-friendly identifier. \r\n\t Description is free text for further details.\r\n
\r\n\r\n Type is an optional constraint for the type to which the parameter value resolves. \r\n Possible types are:\r\n
\r\n- \r\n
- bit indicates that the value shall resolve to a System Verilog bit,\r\n\t\twhich by default is resolved to a 1-bit value, unless a vector size has been \r\n\t\tspecified. \r\n\r\n
- byte indicates that the value shall resolve to a System Verilog byte,\r\n\t\twhich is resolved to an 8-bit integer value. \r\n\r\n
- shortint indicates that the value shall resolve to a System Verilog shortint,\r\n\t\twhich is resolved to a 16-bit integer value. \r\n\t\t\r\n\t\t
- int indicates that the value shall resolve to a System Verilog int, which\r\n\t\tis resolved to a 32-bit integer value. \r\n\t\t\r\n\t\t
- longint indicates that the value shall resolve to a System Verilog longint,\r\n\t\twhich is resolved to a 64-bit integer value. \r\n\t\t\r\n\t\t
- shortreal indicates that the value shall resolve to a System Verilog\r\n\t\tshortint, which is resolved to a 32-bit floating point value. Both standard and \r\n\t\tscientific format (e.g 0.002 and 2e-3) are supported. This type applies also to\r\n\t\tminimum value and maximum value. \r\n\t\t\r\n\t\t
- real indicates that the value shall resolve to a System Verilog real,\r\n\t\twhich is resolved to a 64-bit floating point value. Both standard and scientific \r\n\t\tformat (e.g. 0.002 and 2e-3) are supported. This type applies also to \r\n\t\tminimum value and maximum value. \r\n\t\t\r\n\t\t
- string indicates that the value shall contain any text. \r\n
\r\n Value contains the mandatory default value of the parameter. This \r\n\t value can be overridden in a design that instantiates this component.\r\n\t The value is given in SystemVerilog format and may be given as an expression.\r\n Any other text must be enclosed within quotes e.g. \"Any text\".\r\n
\r\n\t\r\n By selecting a choice, the user can restrict the allowed parameter \r\n\t values to a set of predefined values. Possible values are defined in the\r\n\t choices of the containing component.\r\n
\r\n\r\n Minimum value and maximum value define the lower and upper\r\n boundary for the parameter value. If the selected type is bit or \r\n\t string, these fields have no effect.\r\n
\r\n\r\n Resolve specifies the configuration of the parameter. \r\n Possible resolve values are:\r\n
\r\n- \r\n
- immediate indicates that the the value is defined\r\n within the containing component. The value cannot be overridden\r\n by the user or a generator in design configuration. This is the \r\n\t\tdefault value, when no resolve has been set. \r\n\r\n
- user indicates that the user can override the\r\n default value in design configuration. Generators are not \r\n allowed to change the value. \r\n\r\n
- generated indicates that a generator can\r\n override the default value in a design configuration. \r\n
\r\n Bit vector left and bit vector right define the boundaries of a bit vector.\r\n These values can only be set to bit type parameters.\r\n
\r\n\r\n Array left and Array right specify the left and right sides of array\r\n dimension for the parameter in an output language e.g. Verilog. Both of these are\r\n vendor attributes. The values can be given as an expression, but must resolve to\r\n a decimal number. In order to get a valid array, both Array left and\r\n Array right must be given.\r\n
\r\n\t\r\n\t Usage count displays the number of references made to this parameter. Selecting \r\n the usage count opens a reference analysis of the parameter. The usage count is automatically \r\n updated to display the number of references made to the parameter.\r\n
\r\n\r\n Parameters editor contains a context menu (right mouse button)\r\n that provides following options:\r\n
\r\n- \r\n
- Add new parameter (Add row) \r\n
- Remove parameter (Remove row) \r\n
- Clear the selected cells \r\n
- Copy the contents of the selected cells to clipboard \r\n
- Paste the contents of the clipboard to the selected cells \r\n
- Import a csv-file to the editor \r\n
- Export the contents of the editor to a csv-file \r\n
Port maps editor
\n\n User can map the logical signals of a bus interface to the physical ports of the component.\n The physical ports are located in the top table, while the logical signals and port maps are located in\n the bottom table.\n
\n\nCreating a port map
\n- \n
- \n Drag & Drop. A physical port can be dragged over a logical signal to create a\n port map connecting the selected physical port to the selected logical signal. Multiple physical ports\n can be dragged simultaneously to the selected logical signal to create multiple port maps.\n \n
- \n Selecting a port. A physical port can be selected for the logical signal from the\n physical port column. This creates a port map connecting the selected physical port to the logical\n signal.\n \n
- \n Context menu. Right clicking on a logical port opens a context menu, through which it is\n possible to create a new port map. This port map can then be filled with the desired data.\n \n
- \n Auto connect. Creates a single port map for each logical signal that does not have a port map.\n A suitable physical port is selected by matching the direction, type, size and the name of the logical\n signal to physical ports. If Physical port prefix has been set, physical ports starting with the\n given string will be prioritized in the connections. For example using prefix \"master\" will connect\n logical port 'CLK' to physical port 'master_clk' over ports 'clk', 'slave_clk' etc.\n \n
Removing a port map
\n- \n
- \n Context menu. A port map can be removed throught the context menu. Right click on the\n selected port map to open the menu. From there, select remove port map.\n
Opening the context menu on a logical signal allows the removing of all the port maps\n connected to the logical signal.\n \n - \n Remove all. Clicking the Remove all button removes all the port maps from this bus\n interface.\n \n
Physical port filters
\n- \n
- \n Name allows regular expressions to filter ports not matching the given expression.\n \n
- \n Type selects whether to display wire ports or transactional ports.\n \n
- \n Direction allows the selection of a port direction and filtering all the other ports with\n different directions.\n \n
- \n Connected ports can also be hidden through option Hide connected. By default, this filter is on,\n but can be changed.\n \n
Port maps
\n\n The port maps table consists of both the logical signals and the port maps referencing\n logical signals. The table is constructed as a tree, where the port maps are child items of a logical\n signal. Values for columns with an f(x) symbol can be given as expressions.\n
If a logical signal has been referenced only once in the port maps of the bus interface, information\n of the port map is displayed on the same row as the logical signal.\n
If a single physical port is referenced in all the port maps referencing the logical signal, the\n physical port name is displayed on the same row as the logical signal. If multiple port maps referencing\n the same logical signal contain different physical ports, the name is displayed as [multiple].\n
\n The logical signal of a port map can be changed from the logical port column. This moves the\n selected port map from its current position to the selected logical signal.\n
The physical port can be changed from the physical port column.\n
\n A port map can be defined by giving ranges for the logical and physical sides. These ranges determine how\n many and which bits are connected between the port and signal. These can be defined in the columns for the\n logical left, logical right, physical left and physical right.\n
\n\n Requirement informs the user of the port map requirement of the logical signal. The requirement is\n set in the abstraction definition of a bus definition, and cannot be edited here. The possible values are:\n
\n- \n
- \n Illegal. Logical signal may not be refereneced in a port map.\n \n
- \n Required. Logical signal must be referenced in a port map.\n \n
- \n Optional. The default value. Port maps can be created referencing the logical signal.\n \n
\n Tie off displays the possible logical tie off of the port map. A port map must contain either a\n reference to a physical port, or a logical tie off. The logical tie off indicates thate the physical\n connection for this logical port is the specified value.\n
\n\n Informative specifies that the portMap is used only for information purposes.\n
\n\n Invert specifies that connections to the physical port are logically inverted.\n
\n\nPort maps context menu (right mouse button)
\n- \n
- \n Add port map (logical signal / port map). Add a port map to the selected logical signal.\n \n
- \n Remove port map (port map). Remove the selected port map.\n \n
- \n Remove all port maps (logical signal). Remove all the port maps referencing the selected\n logical signal.\n \n
- \n Auto connect (port map). Automatically tries to connect the selected port by locating a suitable\n physical port matching the direction, type, size and the name of the logical signal to physical ports.\n \n
- \n Expand all. Show the port maps connected to each logical signal.\n \n
- \n Collapse all. Hide the port maps connected to each logical signal.\n \n
\n
Details
\n\n The port maps tab of a bus interface editor is used to group the physical ports of the containing component\n to the logical signals listed in the associated abstraction definition.\n
\n\n The lower table contains the logical signals that were defined in the associated\n abstraction definition. The upper table contains a list of the physical ports in the\n component. The bottom table displays the mappings between logical signals and physical ports. The mapped\n physical ports are removed from the physical ports table unless Hide connected ports is unchecked.\n
\n\t\n The port directions are shown using the following icons:\n
- \n
![](\"../images/input.png\")
in \n ![](\"../images/output.png\")
out \n ![](\"../images/inout.png\")
inout \n\t\t\t![](\"../images/phantom.png\")
phantom \n
\n Picture below depicts how the physical ports between two component instances are connected through their\n bus interfaces.
![\"The](\"../images/PortmapVisualization.png\"\n)
The physical ports of the component\n A are on the left and those of component B on the right. Logical signals are in the middle and the lines\n denote port mappings. For example component A has mapped its port 'comm_out' to the logical signal 'COMM'\n and component B has mapped its port comm_in to it. When user connects these interfaces together in a\n design, the physical ports get connected.\n
\n All ports of the component do not need to be mapped in the interface nor do all the logical signals of the\n abstraction definition need to be associated with a physical port. Abstraction definition defines the\n directions of the signals in different interface modes thus making it possible to validate connections so\n that two output ports are not accidentally connected to each other. In the figure above the abstraction\n definition could have defined the DATA signal to have direction out in master interfaces and in at slave\n interfaces.\n
\n A vectored physical port can be sliced to connect only part of it by assigning left and right bounds in the\n mapping table. Picture below depicts how a part of the physical port can be connected.\n
![\"Connecting](\"../images/portSlicingVisualization.png\"\n)
\n
Port maps editor
\n\n User can map the logical signals of a bus interface to the physical ports of the component.\n The physical ports are located in the top table, while the logical signals and port maps are located in\n the bottom table.\n
\n\nCreating a port map
\n- \n
- \n Drag & Drop. A physical port can be dragged over a logical signal to create a\n port map connecting the selected physical port to the selected logical signal. Multiple physical ports\n can be dragged simultaneously to the selected logical signal to create multiple port maps.\n \n
- \n Selecting a port. A physical port can be selected for the logical signal from the\n physical port column. This creates a port map connecting the selected physical port to the logical\n signal.\n \n
- \n Context menu. Right clicking on a logical port opens a context menu, through which it is\n possible to create a new port map. This port map can then be filled with the desired data.\n \n
- \n Auto connect. Creates a single port map for each logical signal that does not have a port map.\n A suitable physical port is selected by matching the direction, type, size and the name of the logical\n signal to physical ports. If Physical port prefix has been set, physical ports starting with the\n given string will be prioritized in the connections. For example using prefix \"initiator\" will connect\n logical port 'CLK' to physical port 'initiator_clk' over ports 'clk', 'target_clk' etc.\n \n
Removing a port map
\n- \n
- \n Context menu. A port map can be removed throught the context menu. Right click on the\n selected port map to open the menu. From there, select remove port map.\n
Opening the context menu on a logical signal allows the removing of all the port maps\n connected to the logical signal.\n \n - \n Remove all. Clicking the Remove all button removes all the port maps from this bus\n interface.\n \n
Physical port filters
\n- \n
- \n Name allows regular expressions to filter ports not matching the given expression.\n \n
- \n Type selects whether to display wire ports or transactional ports.\n \n
- \n Direction allows the selection of a port direction and filtering all the other ports with\n different directions.\n \n
- \n Connected ports can also be hidden through option Hide connected. By default, this filter is on,\n but can be changed.\n \n
Port maps
\n\n The port maps table consists of both the logical signals and the port maps referencing\n logical signals. The table is constructed as a tree, where the port maps are child items of a logical\n signal. Values for columns with an f(x) symbol can be given as expressions.\n
If a logical signal has been referenced only once in the port maps of the bus interface, information\n of the port map is displayed on the same row as the logical signal.\n
If a single physical port is referenced in all the port maps referencing the logical signal, the\n physical port name is displayed on the same row as the logical signal. If multiple port maps referencing\n the same logical signal contain different physical ports, the name is displayed as [multiple].\n
\n The logical signal of a port map can be changed from the logical port column. This moves the\n selected port map from its current position to the selected logical signal.\n
The physical port can be changed from the physical port column.\n
\n A port map can be defined by giving ranges for the logical and physical sides. These ranges determine how\n many and which bits are connected between the port and signal. These can be defined in the columns for the\n logical left, logical right, physical left and physical right.\n
\n\n Requirement informs the user of the port map requirement of the logical signal. The requirement is\n set in the abstraction definition of a bus definition, and cannot be edited here. The possible values are:\n
\n- \n
- \n Illegal. Logical signal may not be refereneced in a port map.\n \n
- \n Required. Logical signal must be referenced in a port map.\n \n
- \n Optional. The default value. Port maps can be created referencing the logical signal.\n \n
\n Tie off displays the possible logical tie off of the port map. A port map must contain either a\n reference to a physical port, or a logical tie off. The logical tie off indicates thate the physical\n connection for this logical port is the specified value.\n
\n\n Informative specifies that the portMap is used only for information purposes.\n
\n\n Invert specifies that connections to the physical port are logically inverted.\n
\n\nPort maps context menu (right mouse button)
\n- \n
- \n Add port map (logical signal / port map). Add a port map to the selected logical signal.\n \n
- \n Remove port map (port map). Remove the selected port map.\n \n
- \n Remove all port maps (logical signal). Remove all the port maps referencing the selected\n logical signal.\n \n
- \n Auto connect (port map). Automatically tries to connect the selected port by locating a suitable\n physical port matching the direction, type, size and the name of the logical signal to physical ports.\n \n
- \n Expand all. Show the port maps connected to each logical signal.\n \n
- \n Collapse all. Hide the port maps connected to each logical signal.\n \n
\n
Details
\n\n The port maps tab of a bus interface editor is used to group the physical ports of the containing component\n to the logical signals listed in the associated abstraction definition.\n
\n\n The lower table contains the logical signals that were defined in the associated\n abstraction definition. The upper table contains a list of the physical ports in the\n component. The bottom table displays the mappings between logical signals and physical ports. The mapped\n physical ports are removed from the physical ports table unless Hide connected ports is unchecked.\n
\n\t\n The port directions are shown using the following icons:\n
- \n
- in \n
- out \n
- inout \n\t\t\t
- phantom \n
\n Picture below depicts how the physical ports between two component instances are connected through their\n bus interfaces (note: in this picture the interface mode names used are of the old 2014 standard).
\n ![\"The](\"../images/PortmapVisualization.png\")
\n The physical ports of the component A are on the left and those of component B on the right. Logical signals are in the middle and the lines\n denote port mappings. For example component A has mapped its port 'comm_out' to the logical signal 'COMM'\n and component B has mapped its port comm_in to it. When user connects these interfaces together in a\n design, the physical ports get connected.\n
\n All ports of the component do not need to be mapped in the interface nor do all the logical signals of the\n abstraction definition need to be associated with a physical port. Abstraction definition defines the\n directions of the signals in different interface modes thus making it possible to validate connections so\n that two output ports are not accidentally connected to each other. In the figure above the abstraction\n definition could have defined the DATA signal to have direction out in initiator interfaces and in at target \n interfaces.\n
\n A vectored physical port can be sliced to connect only part of it by assigning left and right bounds in the\n mapping table. Picture below depicts how a part of the physical port can be connected.\n
\n
Ports editor
\n\n Ports editor provides a table containing all the ports of a component. This editor is used\n to view, add, remove and edit the ports. The port details can be edited in the Wires and\n Transactionals section.\n
\n\n Port name is a unique identifier and must match the name of the port in the implementation language.\n
\n\n Type shows the kind of the port. The type is set when the port is created and cannot be changed here.\n
\n- \n
- wire port carries binary value(s) and are used in RTL. \n
- transactional port is used for all other kind of ports, especially in TLM. \n
\n Port tags column displays the optional tags for a port. These can be used to group ports together \n to, for example, create bus interfaces.\n\t\t\n
\n Ad-hoc column is a Kactus2-specific extension which is used in the graphical user interface of a\n hierarchical design. Ad-hoc determines whether the port is shown as an ad-hoc port when the component is\n instantiated in a design.\n \n
\n Description is an optional free text for further details.\n
\n\n Ports editor provides a context menu (right mouse button) that contains following options:\n
\n- \n
- Add new wire port (Add wire) \n
- Add new transactional port (Add transactional) \n
- Remove port (Remove row) \n
- Clear the selected cells \n
- Copy the contents of the selected cells to clipboard \n
- Paste the contents of the clipboard to the selected cells \n
Power domains editor
\n\n The power domains editor lists the applicable power domains of the \n component. \n
\n\t\n\t Name is a mandatory identifier for the power domain.\n
\n\n Display name is an optional and used for a more user-friendly identifier.\n
\n\n Always on is optional and determines if the power domain \n is always powered on (value 1) or not (value 0).\n Always on can be given as a SystemVerilog expression, but it must evaluate to 1 or 0.\n
\n\n Subdomain of is optional and defines this power domain as a part of\n another power domain.\n
\n\n Short description is an optional field for compact description of the power domain.\n
\n\t\n Description is an optional field for textual description of the power domain.\t\t\n
\n\n Power domains editor provides a context menu (right mouse button) with\n the following options:\n
\n- \n
- Add new power domain (Add row) \n
- Remove power domain (Remove row) \n
- Clear the selected cells \n
- Copy the contents of the selected cells to clipboard \n
- Paste the contents of the clipboard to the selected cells \n
- Import a csv-file to the editor \n
- Export the contents of the editor to a csv-file \n
Register editor
\n\n Register editor is used to edit the details of a single register and the possible \n\t bit fields within the register. A bit field may contain just one bit, \n\t the whole register or something in between. \n
\n\t\n\t\n\t Name is a mandatory identifier for the register. The name must be unique within \n\t\tall the registers of the containing address block.\n
\n\n Display name is an optional field and used for a more user-friendly identifier.\n
\n\n Description is an optional field for textual description of the register.\t\t\n
\n\n\n Offset is a mandatory value to specify the location of the register from the start of the\n containing address block expressed as address units.
\n\n Size is mandatory and defines the number of data bits the register contains. \n Size must be less or equal to the width of the containing address block.\n
\n\n Dimension is optional and assigns an array dimension to the register. \n The register will be repeated in the\n address block as many times as indicated by the dimension value. An empty dimension (default)\n or a dimension with value 1 means that the register is not an array and will appear exactly once.\n
\n\n\t Is present is optional and allows the enabling/disabling of a register presence \n\t\tin an address block. Value 1 indicates that the register is present in the \n\t\taddress block whereas value 0 marks the register \n to be treated as if it does not exist. Is present can be given as a SystemVerilog expression, but \n it must evaluate to 1 or 0.\n
\n\n Volatile is optional and indicates whether the register value may change without \n\t a write operation to it.\n
\n\n Access is optional and specifies the accessability of the register.\n\t The possible values are:\n
\n- \n
- read-write. Both read and write transactions may have an effect on this register. \n
- read-only. Only read transactions are allowed in this register. \n
- write-only. Only write transactions are allowed in this register. \n
- read-writeOnce. Both read and write transactions may have an effect on this register. Only the\n first write transaction, after an event that caused the reset value of the register to be loaded, may\n affet the contents of the register, and read transactions return a value related to the values in the\n register. \n
- writeOnce. Only the first write transaction affects the contents of the register. \n
Fields table
\n\n The fields table enables the user to define the register bit fields.\n\t A register must contain at least one field.\n
\n\n\t Name is a mandatory identifier for the field.\n
\n\n Offset is a mandatory value to specify the starting bit of the field \n\t within the register.\n
\n\n Width is a mandatory value to specify how many bits are included in the field.\n
\n\n\t\tResets defines the reset values of the field. The reset values must be edited in the field editor.\n\t\tIf a field only has one reset value, it is displayed here. If a field contains multiple reset values, they\n\t\tare displayed with a [multiple] tag. A tooltip provides basic information on the resets, displaying the reset type and value.\n
\n\n Access is optional and specifies the accessibility of the field. The possible values are:\n
\n- \n
- read-write. Both read and write transactions may have an effect on this field. Write\n transactions may affect the contents of the field, and read transactions return a value related to\n the field. \n
- read-only. A read transaction to this field returns a value related to the value in the field.\n A write transaction to this field has undefined results. \n
- write-only. A write transaction to this address affects the contents of the field. A read\n transaction to this field has undefined results. \n
- read-writeOnce. Both read and write transactions may have an effect on this field. Only the\n first write transaction may affect the contents of the field, and read transactions return a value\n related to the values in the field. \n
- writeOnce. Only the first write transaction affects the contents of this field. \n
\n Modified write value is optional anddescribes how the data in the field \n\t\tis manipulated on a write operation. \n The basic operation without any setting is to store the written value 'as is'. Moreover, both bitwise \n and field-wise set/clear/toggle is also possbile. The possible values are:\n
\n- \n
- oneToClear. Each written '1' bit will assign the corresponding bit to '0'. \n
- oneToSet. Each written '1' bit will assign the corresponding bit to '1'. \n
- oneToToggle. Each written '1' bit will toggle the corresponding bit. \n
- zeroToClear, zeroToSet, zeroToToggle. Similar to previous ones, except that written '0' bit\n triggers the action. \n
- clear. Each write operation will clear all bits in the field to '0'. \n
- set. Each write operation will set all bits in the field to '1'. \n
- modify. Indicates that after a write operation all bits in the field can be modified. \n
- ' ' (empty setting). Indicates that the value written to a field is the value stored in the\n field. This is the default. \n
\n Read action specifies if some action happens to the\n field after a read operation. By default the register is\n unmodified. The possible values are:\n
\n- \n
- clear. All bits in the field are cleared to '0' after a read operation. \n
- set. All bits in the field are set to '1' after a read operation. \n
- modify. Indicates that the bits in the field are modified in some way after a read operation. \n
- ' ' (empty setting). Indicates that field is not modified after a read operation. This is\n the default. \n
\n Testable is optional and specifies if the field is testable by an automated register test.\n
\n\n Test constraint is optional and specifies the constraints for the automated tests for the field. \n The possible constraint values are:\n
\n- \n
- unConstrained. There are no constrains for the written or read data. This is the default\n setting. \n
- restore. The field value must be restored to its original value before accessing another\n register. \n
- writeAsRead. The data written to a field must be the same that was read previously from the\n field. \n
- readOnly. Indicates that the field can only be read. \n
\n Is present is optional and enables/disables a field's presence in a register. Value 1 indicates that the field \n is present in the register whereas value 0 marks the field to be treated as if it did not exist. Is \n present can be given as a SystemVerilog expression, but it must evaluate to 1 or 0.\n
\n\n\t\tDescription is an optional field for textual description of the field.\n \n\n" }, { "path": "Help/componenteditor/register2022.html", "content": "\n\n
\n \n \nRegister editor
\n\n Register editor is used to edit the details of a single register and the possible \n\t bit fields within the register. A bit field may contain just one bit, \n\t the whole register or something in between. \n
\n\t\n\n Name is a mandatory identifier for the register. The name must be unique within \n all the registers of the containing address block.\n
\n\n Display name is an optional and used for a more user-friendly identifier.\n
\n\n Short description is an optional field for compact description of the register.\n
\n\n Description is an optional field for textual description of the register.\t\t\n
\n\n\n Offset is a mandatory value to specify the location of the register from the start of the\n containing address block expressed as address units.
\n\n Size is mandatory and defines the number of data bits the register contains. \n Size must be less or equal to the width of the containing address block.\n
\n\n Dimension is optional and assigns an array dimension to the register. \n\t The register will be repeated in the\n address block as many times as indicated by the dimension value. An empty dimension (default)\n or a dimension with value 1 means that the register is not an array and will appear exactly once.\n
\n\n Volatile is optional and indicates whether the register value may change without \n\t a write operation to it.\n
\n\n Access policies are optional and specify the accessability of the register data for different operating modes,\n specified by mode references. If no mode reference is present, then the access policy applies to all modes not already \n referenced by other access policies (i.e. only one access policy without mode references may exist).\n \n The possible access values for an access policy are:\n
\n- \n
- read-write. Both read and write transactions may have an effect on this register. \n
- read-only. Only read transactions are allowed in this register. \n
- write-only. Only write transactions are allowed in this register. \n
- read-writeOnce. Both read and write transactions may have an effect on this register. Only the\n first write transaction, after an event that caused the reset value of the register to be loaded, may\n affect the contents of the register, and read transactions return a value related to the values in the\n register. \n
- writeOnce. Only the first write transaction affects the contents of the register. \n
Fields table
\n\n The fields table enables the user to define the register bit fields.\n A register must contain at least one field.\n
\n\n\t Name is a mandatory identifier for the field.\n
\n\n Offset is a mandatory value to specify the starting bit of the field \n\t within the register.\n
\n\n Width is a mandatory value to specify how many bits are included in the field.\n
\n\n Resets defines the reset values of the field. The reset values must be edited in the field editor.\n If a field only has one reset value, it is displayed here. If a field contains multiple reset values, they\n are displayed with a [multiple] tag. A tooltip provides basic information on the resets, displaying the reset type and value.\n
\n\n Volatile is optional and indicates whether the field value may change without \n\t a write operation to it.\n
\n\n Access modifies the first field access policy of the field. If multiple field access policy exists, then the access \n cannot be edited here and must be edited for each field access policy separately in the field editor. \n If no field access policy exists, then one will be created for the field when the access is edited here. The possible access values are:\n
\n- \n
- \n read-write. Both read and write transactions may have an effect on this field. Write\n transactions may affect the contents of the field, and read transactions return a value related to\n the field.\n \n
- \n read-only. A read transaction to this field returns a value related to the value in the field.\n A write transaction to this field has undefined results.\n \n
- \n write-only. A write transaction to this address affects the contents of the field. A read\n transaction to this field has undefined results.\n \n
- \n read-writeOnce. Both read and write transactions may have an effect on this field. Only the\n first write transaction may affect the contents of the field, and read transactions return a value\n related to the values in the field.\n \n
- \n writeOnce. Only the first write transaction affects the contents of this field.\n \n
\n\t\t Description is an optional field for textual description of the field.\n
\n \n\n" }, { "path": "Help/componenteditor/registerFile.html", "content": "\n\n \n \n \nRegister file editor
\n\n Register file editor is used to edit the details of a single register file and the \n\t registers and register files within the register file.\n
\n\t\n\t\n\t Name is a mandatory identifier for the register file. The name must be unique within \n\t\t all the registers or register files of the containing address block or register file.\n
\n\n Display name is an optional and used for a more user-friendly identifier.\n
\n\n Description is an optional field for textual description of the register file.\t\t\n
\n\n\n Offset is a mandatory value to specify the location of the register file from the start of the\n containing address block or register file expressed as address units.\n
\n\n Range is mandatory and specifies the size of the register file in address units bits.\n
\n\n Dimension is optional and assigns an array dimension to the register file. \n\t The register file will be repeated in the containing \n address block or register file as many times as indicated by the dimension value. An empty dimension (default)\n or a dimension with value 1 means that the register file is not an array and will appear exactly once.\n
\n\n\t Is present is optional and allows the enabling/disabling of a register file presence \n in a containing address block or register file. Value 1 indicates that the register file is present in the \n containing element whereas value 0 marks the register file \n to be treated as if it does not exist. Is present can be given as a SystemVerilog expression, but \n it must evaluate to 1 or 0.\n
\n\n Access is optional and specifies the accessability of the register file.\n\t The possible values are:\n
\n- \n
- read-write. Both read and write transactions may have an effect on this register file. \n
- read-only. Only read transactions are allowed in this register file. \n
- write-only. Only write transactions are allowed in this register file. \n
- read-writeOnce. Both read and write transactions may have an effect on this register file. Only the\n first write transaction, after an event that caused the reset value of the register file to be loaded, may\n affet the contents of the register file, and read transactions return a value related to the values in the\n register file. \n
- writeOnce. Only the first write transaction affects the contents of the register file. \n
Registers table
\n\n The registers table enables the user to define and edit registers of the register file.\n
\n\n\t Name is a mandatory identifier for the register.\n
\n\n Offset is a mandatory value to specify the location of the register \n\t within the register file expressed as address units.\n
\n\n Size is mandatory and defines the number of data bits the register contains. \n Size must be less or equal to the width of the containing address block.\n
\n\n Dimension is optional and assigns an array dimension to the register. \n The register will be repeated in the containing\n register file as many times as indicated by the dimension value. An empty dimension (default)\n or a dimension with value 1 means that the register is not an array and will appear exactly once.\n
\n\n Volatile is optional and indicates whether the register value may change without \n a write operation to it.\n
\n\n Access is optional and specifies the accessability of the register.\n\t The possible values are:\n
\n- \n
- read-write. Both read and write transactions may have an effect on this register. \n
- read-only. Only read transactions are allowed in this register. \n
- write-only. Only write transactions are allowed in this register. \n
- read-writeOnce. Both read and write transactions may have an effect on this register. Only the\n first write transaction, after an event that caused the reset value of the register to be loaded, may\n affet the contents of the register, and read transactions return a value related to the values in the\n register. \n
- writeOnce. Only the first write transaction affects the contents of the register. \n
\n Is present is optional and enables/disables a register's presence in the register file. Value 1 indicates that the register \n is present in the register file whereas value 0 marks the register to be treated as if it did not exist. Is \n present can be given as a SystemVerilog expression, but it must evaluate to 1 or 0.\n
\n\n\t\t Description is an optional field for textual description of the register.\n
\n\nRegister files table
\n\n The register files table enables the user to define and edit register files within the register file.\n
\n\n\t Name is a mandatory identifier for the register file.\n
\n\n Offset is a mandatory value to specify the location of the register file \n\t within the containing register file expressed as address units.\n
\n\n Range is mandatory and specifies the size of the register file in address units bits.\n
\n\n Dimension is optional and assigns an array dimension to the register file. \n The register file will be repeated in the\n containing register file as many times as indicated by the dimension value. An empty dimension (default)\n or a dimension with value 1 means that the register file is not an array and will appear exactly once.\n
\n\n Is present is optional and enables/disables a register's presence in the register file. Value 1 indicates that the register \n is present in the register file whereas value 0 marks the register to be treated as if it did not exist. Is \n present can be given as a SystemVerilog expression, but it must evaluate to 1 or 0.\n
\n\n\t\t Description is an optional field for textual description of the register.\n
\n \n\n" }, { "path": "Help/componenteditor/registerFile2022.html", "content": "\n\n \n \n \nRegister file editor
\n\n Register file editor is used to edit the details of a single register file and the \n\t registers and register files within the register file.\n
\n\t\n\t\n\t Name is a mandatory identifier for the register file. The name must be unique within \n\t\t all the registers or register files of the containing address block or register file.\n
\n\n Display name is an optional and used for a more user-friendly identifier.\n
\n\n Short description is a compact description of the register file.\n
\n\n Description is an optional field for textual description of the register file.\t\t\n
\n\n\n Offset is a mandatory value to specify the location of the register file from the start of the\n containing address block or register file expressed as address units.\n
\n\n Range is mandatory and specifies the size of the register file in address units bits.\n
\n\n Dimension is optional and assigns an array dimension to the register file. \n\t The register file will be repeated in the containing \n address block or register file as many times as indicated by the dimension value. An empty dimension (default)\n or a dimension with value 1 means that the register file is not an array and will appear exactly once.\n
\n\n Access policies are optional and specify the accessability of the register file data for different operating modes,\n specified by mode references. If no mode reference is present, then the access policy applies to all modes not already \n referenced by other access policies (i.e. only one access policy without mode references may exist).\n \n The possible access values for an access policy are:\n
\n- \n
- read-write. Both read and write transactions may have an effect on this register file. \n
- read-only. Only read transactions are allowed in this register file. \n
- write-only. Only write transactions are allowed in this register file. \n
- read-writeOnce. Both read and write transactions may have an effect on this register file. Only the\n first write transaction, after an event that caused the reset value of the register file to be loaded, may\n affect the contents of the register file, and read transactions return a value related to the values in the\n register file. \n
- writeOnce. Only the first write transaction affects the contents of the register file. \n
Registers table
\n\n The registers table enables the user to define and edit registers of the register file.\n
\n\n\t Name is a mandatory identifier for the register.\n
\n\n Offset is a mandatory value to specify the location of the register \n\t within the register file expressed as address units.\n
\n\n Size is mandatory and defines the number of data bits the register contains. \n Size must be less or equal to the width of the containing address block.\n
\n\n Dimension is optional and assigns an array dimension to the register. \n The register will be repeated in the containing\n register file as many times as indicated by the dimension value. An empty dimension (default)\n or a dimension with value 1 means that the register is not an array and will appear exactly once.\n
\n\n Volatile is optional and indicates whether the register value may change without \n a write operation to it.\n
\n\n Access is optional and specifies the accessibility of the register by modifying\n the first access policy of the register. If multiple access policies exist, then the access value \n cannot be edited here and must be edited for each access policy separately in the register editor. \n If no access policy exists, then one will be created for the register when the access is edited here.\n \n The possible access values are:\n
\n- \n
- read-write. Both read and write transactions may have an effect on this \n register. \n
- read-only. Only read transactions are allowed in this register. \n
- write-only. Only write transactions are allowed in this register. \n
- read-writeOnce. Both read and write transactions may have an effect on this\n register. Only the first write transaction, after an event that caused the\n reset value of the register to be loaded, may affet the contents of the register,\n and read transactions return a value related to the values in the register. \n
- writeOnce. Only the first write transaction affects the contents of the \n register. \n
\n\t\t Description is an optional field for textual description of the register.\n
\n\nRegister files table
\n\n The register files table enables the user to define and edit register files within the register file.\n
\n\n\t Name is a mandatory identifier for the register file.\n
\n\n Offset is a mandatory value to specify the location of the register file \n\t within the containing register file expressed as address units.\n
\n\n Range is mandatory and specifies the size of the register file in address units bits.\n
\n\n Dimension is optional and assigns an array dimension to the register file. \n The register file will be repeated in the\n containing register file as many times as indicated by the dimension value. An empty dimension (default)\n or a dimension with value 1 means that the register file is not an array and will appear exactly once.\n
\n\n\t\t Description is an optional field for textual description of the register.\n
\n \n\n" }, { "path": "Help/componenteditor/remapStates.html", "content": "\n\n \n \n \nRemap states editor
\n\n The Remap states editor displays a summary of the remap states of a component.\n
\n\t\n\t Name is a mandatory identifier for the remap state.\n
\n\n Display name is an optional and used for a more user-friendly identifier.\n
\n\n Description is an optional field for textual description of the remap state.\t\t\n
\n \n\n Right clicking an item in the editor provides a context menu that can be used to:\n
\n- \n
- Add a new remap state to the component (Add row). \n
- Remove a remap state from the component (Remove row). \n
- Clear the selected cells (Clear). \n
- Copy the contents of the selected cells to clipboard (Copy). \n
- Paste the contents of the clipboard to the selected cells (Paste). \n
Reset types editor
\n\n\n The Reset types editor is used to edit the details of a reset type.\n\t\tThe reset types describe any user-defined reset types referenced within field reset elements.\n\t\tThe default reset type for a field is HARD, and should be treated as pre-defined.\n
\n\n\n Name is a mandatory identifier for the reset type.\n\t\tThe name must be unique, and can not be the pre-defined default value HARD.\n
\n\n Display name is an optional and used for a more user-friendly identifier.\n
\n\n Description is an optional field for textual description of the reset type.\n
\n\n\n" }, { "path": "Help/componenteditor/resetTypes2022.html", "content": "\n\n\n \n \nReset types editor
\n\n\n The Reset types editor is used to edit the details of a reset type.\n\t\tThe reset types describe any user-defined reset types referenced within field reset elements.\n\t\tThe default reset type for a field is HARD, and should be treated as pre-defined.\n
\n\n\n Name is a mandatory identifier for the reset type.\n\t\tThe name must be unique, and can not be the pre-defined default value HARD.\n
\n\n Display name is an optional and used for a more user-friendly identifier.\n
\n\n Short description is an optional field for compact description of the reset type.\n
\n\n Description is an optional field for textual description of the reset type.\n
\n\n\n" }, { "path": "Help/componenteditor/singleRemapState.html", "content": "\n\n \n \n \nSingle remap state editor
\n\n Remap state editor is used to edit the details of a single remap state.\n A remap state defines a conditional state which\n is conditioned by a remap port.\n A remap state element does not specify the remapping addresses. Instead, they\n are defined by the memory remap element (in a memory map element),\n\t and its state attribute refers the remap state by name.\n
\n\t\n\t Name is a mandatory identifier for the remap state.\n
\n\n Display name is an optional and used for a more user-friendly identifier.\n
\n\n Description is an optional field for textual description of the remap state.\t\t\n
\n\t\n\tRemap State Condition
\n\n In addition to the name group, a remap state contains a remap state condition,\n which is specified with the remap port elements. These elements make up the\n condition for this remap state. All elements must be true for the remap state to\n be enabled.\n
\n\n Port contains the names of the selected remap ports. These remap ports are\n selected among the components ports. No port can be selected twice.\n
\n\n Left bound shows the left bound value of the selected port.\n This value cannot be given, as it is read using the selected port. Together with\n the value of the right bound column, this value is used to calculate the width of the port.\n
\n\n Right bound shows the right bound value of the selected port.\n This value cannot be given, as it is read using the selected port. Together with\n the value of the left bound column, this value is used to calculate the width of the port.\n
\n\n Value contains the value necessary so the specified port activates the\n remap state. Depending on the width of the port, the remap condition value may be given as a single\n expression for the whole port, or as separate expressions for each bit of the port. A port with a width of 1\n is only allowed to receive a single expression.\n
\n \n\n" }, { "path": "Help/componenteditor/subspacemap.html", "content": "\n\n\n \n \nSubspace map editor
\n\n Subspace map editor is used to edit the details of a subspace map. Subspaces\n are used for opaque bridges to define access from a memory map to an\n address space of a master interface.\n
\n\n Name is a mandatory identifier for the subspace map.\n
\n\n Display name is an optional and used for a more user-friendly identifier.\n
\n\n Description is an optional field for textual description of the subspace map.\n
\n\n\n Base address is mandatory and specifies the starting address for the subspace\n map in address unit bits. The range is equal to the referenced address\n space or segment.\n
\n\n\n MasterRef is a mandatory identifier for the bridged master bus interface\n that is accessed by the subspace map.\n
\n\n SegmentRef is an optional reference to a segment within the\n referenced master bus interface. If a segment is defined,\n the access is limited to the specified segment instead of the whole\n address space.\n
\n \t\n Is present is optional and allows enabling/disabling of a subspace map\n presence in a memory map. Value 1 indicates that the subspace map\n is present in the memory map whereas value 0 marks the subspace map to be\n treated as if it does not exist. Is present can be given as a SystemVerilog expression,\n but it must evaluate to 1 or 0.\n
\n\n\n" }, { "path": "Help/componenteditor/subspacemap2022.html", "content": "\n\n\n \n \nSubspace map editor
\n\n Subspace map editor is used to edit the details of a subspace map. Subspaces\n are used for opaque bridges to define access from a memory map to an\n address space of a initiator interface.\n
\n\n Name is a mandatory identifier for the subspace map.\n
\n\n Display name is an optional and used for a more user-friendly identifier.\n
\n\n Short description is an optional field for compact description of the subspace map.\n
\n\n Description is an optional field for textual description of the subspace map.\n
\n\n\n Base address is mandatory and specifies the starting address for the subspace\n map in address unit bits. The range is equal to the referenced address\n space or segment.\n
\n\n\n Initiator reference is a mandatory identifier for the bridged initiator bus interface\n that is accessed by the subspace map.\n
\n\n SegmentRef is an optional reference to a segment within the\n referenced initiator bus interface. If a segment is defined,\n the access is limited to the specified segment instead of the whole\n address space.\n
\n\n\n" }, { "path": "Help/componenteditor/swproperties.html", "content": "\n\n \n \n \nSoftware properties editor
\n\n This is Kactus2 extension
These allow defining\n parameters for software. The usage is similar to model\n parameters, first define the available parameters and then\n give them actual values upon component instantiation. However,\n these are separated, since other tools do not have such concept\n and that might lead confusion which are HW parameters and and\n which are SW parameters.
\n Each SW property has mandatory name and type\n (string, integer, IP address). Moreover, sometimes the value\n definition is required on each instance. Optional\n default value is used, if instance does not specify the\n value. Textual desciption is also optional.\n
\n\n For example, MCAPI nodes necessiate that user sets the 'node_id'\n which is done through SW property. Similarly, some SW may need\n the IP address of itself or other device and it can be also set\n here.\n
\n \n\n" }, { "path": "Help/componenteditor/systemview.html", "content": "\n\n \n \n \nSystem view editor
\n\n This is Kactus2 extension
\n Each system view has a mandatory name. Display\n name is optional and typically a few words providing a more\n detailed and/or user-friendly name for display. Optional\n description contains a textual description of the\n interface.\n
Hierarchy reference is the VLNV of system design\n which also a Kactus-extension. It captures the mapping\n informationand is saved in its own XML file. You can type the VLNV\n or drag-drop a SW design from the library. Note that a system view\n is always hierarchical, unlike regular view.\n
\n \n\n" }, { "path": "Help/componenteditor/systemviews.html", "content": "\n\n \n \n \nSystem views editor
\n\n This is Kactus2 extension
System view is a\n usually associated with a component including multiple CPUs. It\n is hierarchical reference to system design which is also\n a Kactus-extension and defines the mapping of SW onto HW\n resources. One component, such as multiprocessor SoC (MPSoC),\n can have multiple system views, i.e. multiple stored mappings,\n and hence it is easy to switch between them. System design\n defines how SW is mapped onto CPUs and it shows all HW\n components that include a CPU definition. Mapping is\n necessary if there are multiple CPUs or HW accelerators that\n support the optional COM interfaces.\n
\n Each system view has mandatory name and hierarchy\n reference. Note that the latter cannot be edited here, but\n in view's own editor. Note also that a system view is always\n hierarchical, unlike regular view.Display name is\n optional and typically a few words providing a more detailed\n and/or user-friendly name for display. Optional\n description contains a textual description of the\n interface.\n
\n\n
EXAMPLE. A product includes two programmable CPUS: Nios on FPGA\n and a regular PC. One system design performs the application\n mapping so that discrete cosine transfrom (dct) is executed on PC\n whereas the main function H.263 video encoder is on\n Nios. Communication between these is done using MCAPI endpoints\n and channels. Therefore Nios also includes the MCAPI SW component.\n We notice that interface symbols are different in COM interfaces\n (main - dct) and API interfaces (main - mcapi). Note also that\n system design shows CPUs together although they appear on\n different levels of product's hiearchy.
Transactional ports editor
\n\n Transactional ports editor provides a table containing all the transactional ports of a component.\n This editor is used to add, remove and edit the transactional ports.\n
\n\n Port name is a unique identifier and must match the name of the port in the implementation language.\n For example, the ports listed in the VHDL entity declaration are listed here.\n
\n\n Width specifies the data width in bits. Can be given as an expression.\n
\n\n Initiative defines the type of access. Initiative has four options:\n
\n- \n
- requires defines an initiative requirement of the port. \n
- provides defines a provider port for initiative. \n
- both defines the type of access as both requires and provides. \n
- phantom for ports that exist on the IP-XACT component but not on the implementation. \n
\n Kind defines the ports type. Kind has four options, in addition to a custom type.\n
- \n
- tlm_port should only be used for TLM1 notation \n
- tlm_socket \n
- simple_socket \n
- multi_socket \n
\n Protocol characterizes the information transportation method of the port. Currently not supported\n in Kactus2.\n
\n\n The port type is optional together with a type definition that an optional language specific\n reference to where the type is defined, e.g. package or header file. In SystemC, the type definition is \n\t\tthe include file name, e.g. 'systemc.h'. The type definition has no effect if type is not set. \n\t\tThe type can be applied to specific view(s) or all views.\n
\n\n Array left and array right are optional and define the indices of an array port. The values\n can be given as an equation, but it must resolve into a decimal number. If either left or right value is\n given, the port is considered to be of an array type.\n
\n\n Port tags column displays the optional tags for a port. These can be used to group ports together \n to, for example, create bus interfaces.\n\t\t\n
\n Max connections and Min connections define the number of legal connections that can be made\n to this port. Max connceionts indicates the maximum number of supported connections, while\n Min connections indicates the minimum number of supported connections. These values can be given\n as expressions.\n
\n\t\n\t Ad-hoc column is a Kactus2-specific extension which is used in the graphical user interface of a\n hierarchical design. Ad-hoc determines whether the port is shown as an ad-hoc port when the component is\n instantiated in a design.\n\t \n\t
\n Description is an optional free text for further details.\n
\n\n Transactional ports editor provides a context menu (right mouse button) that contains following options:\n
\n- \n
- Add new port (Add row) \n
- Remove port (Remove row) \n
- Clear the selected cells \n
- Copy the contents of the selected cells to clipboard \n
- Paste the contents of the clipboard to the selected cells \n
- New Bus Interface creates a new bus interface in the component using the currently selected ports \n
- Import a csv-file to the editor \n
- Export the contents of the editor to a csv-file \n
View editor
\n\n View specifies a representation level of a component, e.g. there might be different views for \n simulation and synthesis. This editor is used to edit the details of single view.\n
\n\t\n\t Name is a mandatory identifier for the view.\n
\n\n Display name is an optional and used for a more user-friendly identifier.\n
\n\n Description is an optional field for textual description of the view.\t\t\n
\n\t\nEnvironment identifiers
\n\n Environment identifiers is optional textual information about how this view is deployed in \n different tool environments.\n
\n\n\t\tLanguage indicates this view may be compatible with a particular tool, but only if that \n language is supported in that tool, e.g., different versions of some simulators may support two or \n more languages.\n
\n\n Tool indicates that this view contains tool-information, e.g., HDL models that use \n simulator-specific extensions. This should contain tool name and company name, separated by dots\n e.g. 'designcompiler.designcompany.com'. Alternatively, the tool can have a generic value\n such as '*Simulation' or '*Synthesis'.\n
\n\n VendorSpecific can further qualify tool and language compatibility, e.g. if some \n appropriate simulator mode must be enabled. \n
\n\t\nInstantiations
\n\n Component instantiation is optional and specifies the component instantiation\n\t\tcontaining all the implementation details for the component with this view. For convenience, \n details of the component instantiation are shown in the view editor if a component instantiation \n\t\thas been selected. \n\t\tFor more information on the component instantiation, see the component instantiation editor.\n
\n\n Design configuration instantiation is optional and specifies the referenced design configuration \n instantiation. For convenience, the referenced design configuration is shown in the view \n\t\teditor if a design configuration instantiation has been selected.\n\t\tWhen this view is active, this design configuration should be used to\n\t\tconfigure the component structure. \n\t\tFor more information on the design configuration instantiation, see the design configuration \n instantiation editor.\n
\n\n Design instantiation is optional and specifies the referenced design instantiation. \t\t\n\t\tFor convenience, the referenced design is shown in the view \n\t\teditor if a design instantiation has been selected.\n\t\tWhen this view is active, this design should be used to\n\t\tdescribe the component structure. \n\t\tFor more information on the design instantiation, see the design instantiation editor.\n
\n \n \n\n" }, { "path": "Help/componenteditor/view2022.html", "content": "\n\n \n \n \nView editor
\n\n View specifies a representation level of a component, e.g. there might be different views for \n simulation and synthesis. This editor is used to edit the details of single view.\n
\n\t\n\t Name is a mandatory identifier for the view.\n
\n\n Display name is an optional and used for a more user-friendly identifier.\n
\n\n Short description is an optional field for compact description of the view.\n
\n\n Description is an optional field for textual description of the view.\t\t\n
\n\t\nEnvironment identifiers
\n\n Environment identifiers is optional textual information about how this view is deployed in \n different tool environments.\n
\n\n\t\tLanguage indicates this view may be compatible with a particular tool, but only if that \n language is supported in that tool, e.g., different versions of some simulators may support two or \n more languages.\n
\n\n Tool indicates that this view contains tool-information, e.g., HDL models that use \n simulator-specific extensions. This should contain tool name and company name, separated by dots\n e.g. 'designcompiler.designcompany.com'. Alternatively, the tool can have a generic value\n such as '*Simulation' or '*Synthesis'.\n
\n\n VendorSpecific can further qualify tool and language compatibility, e.g. if some \n appropriate simulator mode must be enabled. \n
\n\t\nInstantiations
\n\n Component instantiation is optional and specifies the component instantiation\n\t\tcontaining all the implementation details for the component with this view. For convenience, \n details of the component instantiation are shown in the view editor if a component instantiation \n\t\thas been selected. \n\t\tFor more information on the component instantiation, see the component instantiation editor.\n
\n\n Design configuration instantiation is optional and specifies the referenced design configuration \n instantiation. For convenience, the referenced design configuration is shown in the view \n\t\teditor if a design configuration instantiation has been selected.\n\t\tWhen this view is active, this design configuration should be used to\n\t\tconfigure the component structure. \n\t\tFor more information on the design configuration instantiation, see the design configuration \n instantiation editor.\n
\n\n Design instantiation is optional and specifies the referenced design instantiation. \t\t\n\t\tFor convenience, the referenced design is shown in the view \n\t\teditor if a design instantiation has been selected.\n\t\tWhen this view is active, this design should be used to\n\t\tdescribe the component structure. \n\t\tFor more information on the design instantiation, see the design instantiation editor.\n
\n \n \n\n" }, { "path": "Help/componenteditor/views.html", "content": "\n\n \n \n \nViews editor
\n\n Views editor provides a summary of the views of the\n component. The editor can be used to add and remove views.\n
\n\n A view specifies a representation level of a component,\n e.g. there might be different views for simulation and\n synthesis. A component can have multiple views and one of them \n is selected as active when component is instantiated in a design.\n
\n\n Name is a mandatory identifier for the view.\n
\n\n View type is automatically determined by the view definition. \n A non-hierarchical view defines an independent one-level representation of \n the component. A hierarchical view implies there is a design \n describing the sub-components that together compose this component.\n
\n\n Description is an optional field for textual description of the view.\n
\n\n The editor contains a context menu that contains following options:\n
\n- \n
- Add new view (Add row) \n
- Remove view (Remove row) \n
- Clear the selected cells \n
- Copy the contents of the selected cells to clipboard \n
- Paste the contents of the clipboard to the selected cells \n
- Import a csv-file to the editor \n
- Export the contents of the editor to a csv-file \n
\n
\n A view specifies the instantiations composing the representation of the\n component. Implementation specific details such as filesets and module \n parameters are defined in a component instantiation whereas\n design instantiation and design configuration instantiation\n are used to identify the design describing the internal structure of\n the component. A view can define any combination of the three\n different instantiations.\n
\n ![\"view's](\"../images/view.png\")
\n
Wire ports editor
\n\n Wire ports editor provides a table containing all the wire ports of a component. This editor is used\n to add, remove and edit the wire ports.\n
\n\n Port name is a unique identifier and must match the name of the port in the implementation language.\n For example, the ports listed in the VHDL entity declaration are listed here.\n
\n\n Direction has four options:\n
\n- \n
- in for input ports. \n
- out for output ports. \n
- inout for bidirectional and tri-state ports. \n
- phantom for ports that exist on the IP-XACT component but not on the implementation.\n \n
\n Left and right bounds define the indices of a vectored port. The width of the port is\n higher bound - lower bound + 1, e.g. 3 downto 0 requires 4 bits. For scalar ports\n left bound = right bound. If either left bound or right bound is an expression, width cannot be set\n manually.\n
\n\n The port type is optional together with a type definition that an optional language specific\n reference to where the type is defined, e.g. package or header file. Typical values in VHDL are 'std_logic'\n for scalar ports (i.e. 1 bit) and 'std_logic_vector' for vectored ports (multibit). In VHDL, 'std_logic'\n types are defined in 'IEEE.std_logic_1164.all' ('all' means that the whole package is included). In\n SystemC, the type definition is the include file name, e.g. 'systemc.h'. The type definition has no effect\n if type is not set. The type can be applied to specific view(s) or all views.\n
\n\n Default value is optional and can be used to assign a value for an unconnected (input) port. This is\n used, for example, when generating a structural top-level VHDL for the hierarchical component where some\n input ports are not connected to any other port in the design.\n
\n\n Array left and array right are optional and define the indices of an array port. The values\n can be given as an equation, but must resolve into a decimal number. If either left or right value is\n given, the port is considered to be of an array type.\n
\n\n Port tags column displays the optional tags for a port. These can be used to group ports together \n to, for example, create bus interfaces.\n\t\t\n
\n Ad-hoc column is a Kactus2-specific extension which is used in the graphical user interface of a\n hierarchical design. Ad-hoc determines whether the port is shown as an ad-hoc port when the component is\n instantiated in a design.\n\t \n
EXAMPLE: The component instances are drawn as rectangles and their external interfaces are drawn to the\n edges of the rectangle. There are different symbols for different directions. The example instance in\n figure has 5 bus interfaces: clk, led, rst_n, from_hibi and pkt_codec. Each interface includes 1 or\n multiple ports, and the interface definition has its own VLNV. Moreover, user can select that some ports\n are shown as Ad-hoc, e.g. if they are not necessarily associated in any bus interface. Example\n figure displays 2 ad-hoc ports: rx_av_in and led_out.\n
![\"Component](\"../images/adHocPorts.PNG\")
\n
\n Description is an optional free text for further details.\n
\n\n Wire ports editor provides a context menu (right mouse button) that contains following options:\n
\n- \n
- Add new port (Add row) \n
- Remove port (Remove row) \n
- Clear the selected cells \n
- Copy the contents of the selected cells to clipboard \n
- Paste the contents of the clipboard to the selected cells \n
- New Bus Interface creates a new bus interface in the component\n using the currently selected ports \n
- Import a csv-file to the editor \n
- Export the contents of the editor to a csv-file \n
\n
\n EXAMPLE. The figure shows the relation between VHDL source code and the port editor. The names, directions,\n and bounds are obvious. Width is derived from the bounds, if given, but otherwise set to 1 to denote a\n scalar port. The type of the ports is std_logic for clk and rst_n, and std_logic_vector for data_in and\n data_out. For data_out, the type is defined only for view flat. In other ports no view is defined so the\n same type is applied for all views (not shown in the figure below). The type definition is\n IEEE.std_logic_1164.all for each port.\n\t
\n ![\"VHDL](\"../images/ports.png\")
\n
Abstraction Definition
\n\n
\n An abstraction definition can also be linked with a bus definition to provide additional validation\n for bus connections. Abstraction definition defines what logical signals must be present in the bus\n interface in order for the bus connection with such abstraction definition to be valid. A logical\n signal can be either a wire signal or a transactional signal.\n
\n\n\n Logical signal editor contains a context menu (right mouse button) that provides following options:\n
\n- \n
- Add master signal interface mode \n
- Add slave signal interface mode \n
- Add system signal interface mode \n
- Add all unconnected system signals from the bus definition system group \n
- Reset extended ports to reload the signals that have been extended from the extended abstraction definition \n
- Add new logical signal (Add row) \n
- Remove logical signal (Remove row) \n
- Clear the selected cells \n
- Copy the contents of the selected cells to clipboard \n
- Paste the contents of the clipboard to the selected cells \n
- Import a csv-file to the editor \n
- Export the contents of the editor to a csv-file \n
Extended abstraction definition
\n\n Allows the creation of a family of interconnectable abstraction definitions. The extending abstraction\n definition must have a bus type that extends the bus type of the extended abstraction definition. The\n logical signals of the extended abstraction definition can be used and the following elements can be\n edited:\n
- \n
- Presence \n
- Width \n
- Default value \n
- Driver \n
- System group \n
Logical signal properties
\n\n Name is a mandatory unique identifier for the logical signal.\n
\n\n\n Mode defines for which interface mode the settings apply.\n
\n- \n
- \n master defines constraints for this signal when present in a master bus interface.\n \n
- \n slave defines constraints for this signal when present in a slave bus interface.\n \n
- \n system defines constraints for this signal when present in a system bus interface with a\n matching group name.\n \n
\n Presence is an optional restriction for the logical signal presence in a bus interface. It can\n have one of the following three values:\n
\n- \n
- \n required indicates that the logical signal must appear in the connected bus interface.\n \n
- \n illegal indicates that the logical signal must not appear in the connected bus interface.\n \n
- \n optional does not apply any restrictions. This is the default value.\n \n
\n Qualifier is an optional indicator for what kind of information the the signal carries. It can\n have one of the following five values:\n
\n- \n
- \n address indicates that the signal carries address information.\n \n
- \n data indicates that the signal carries data.\n \n
- \n empty indicates that the signal may carry any information.\n \n
\n System group helps identify the system interface the signal belongs to. System group is\n mandatory for system mode and illegal for other modes.\n
\n\n Description is an optional free text for further details.\n
\n\nWire properties
\n\n Direction is an optional restriction for the logical signal direction in the connected bus\n interface. Direction can have one of the following values:\n
\n- \n
- \n in\n \n
- \n out\n \n
- \n inout\n \n
\n Width is an optional definition of the number of bits in the logical signal. If not specified,\n the number of bits in the connected physical port is used.\n
\n\n Default value is an optional value that is applied when the logical signal is not connected in\n a connected bus interface.\n
\n\n Driver is an optional setting for defining what kind of a driver the logical signal requires in\n a complete design. The possible values are the following:\n
\n- \n
- \n any indicates that any logical signal or value is valid for driving the signal. This is the\n default value.\n \n
- \n clock indicates that a repeating waveform is required.\n \n
- \n singleshot indicates that a non-repeating waveform is required.\n \n
- \n none indicates that no driver is required.\n \n
\n Wire ports have additional values for Qualifier:\n
\n- \n
- \n address indicates that the signal carries address information.\n \n
- \n data indicates that the signal carries data.\n \n
- \n clock indicates that the signal is a repeating clock signal for the bus interface.\n \n
- \n reset indicates that the signal is a reset signal for the bus interface and is used to set\n the interface into a know valid state.\n \n
Transactional properties
\n\n Initiative optional definition of the access type. Initiative can have any of the folowing\n values:\n
\n- \n
- \n requires\n \n
- \n provides\n \n
- \n requires/provides\n \n
\n Kind specifies the type of the transactional port. It can be one of the following values, though\n tlm_port should be used for TLM1 notation, while others whould be used for TLM2:\n
\n- \n
- \n tlm_port\n \n
- \n tlm_socket\n \n
- \n simple_socket\n \n
- \n multi_socket\n \n
- \n custom name\n \n
\n Bus width specifies the data width in bits.\n
\n\n Protocol type characterizes the communication protocol. Type can be one of these values:\n
\n- \n
- \n tlm\n \n
- \n custom\n \n
\n Protocol can contain a payload specifying the way information is transported. Payload has the\n following sub elements:\n
\n- \n
- \n Name, specifying the payload's name.\n \n
- \n Type mandatory specification of typing. Can have either of the two values:\n
- \n
- \n generic\n \n
- \n specific\n \n
\n - \n Extension determines an extension for the payload.\n \n
Abstraction Definition
\n\n
\n An abstraction definition can also be linked with a bus definition to provide additional validation\n for bus connections. Abstraction definition defines what logical signals must be present in the bus\n interface in order for the bus connection with such abstraction definition to be valid. A logical\n signal can be either a wire signal or a transactional signal.\n
\n\n\n Logical signal editor contains a context menu (right mouse button) that provides following options:\n
\n- \n
- Add initiator signal interface mode \n
- Add target signal interface mode \n
- Add system signal interface mode \n
- Add all unconnected system signals from the bus definition system group \n
- Reset extended ports to reload the signals that have been extended from the extended abstraction definition \n
- Add new logical signal (Add row) \n
- Remove logical signal (Remove row) \n
- Clear the selected cells \n
- Copy the contents of the selected cells to clipboard \n
- Paste the contents of the clipboard to the selected cells \n
- Import a csv-file to the editor \n
- Export the contents of the editor to a csv-file \n
Extended abstraction definition
\n\n Allows the creation of a family of interconnectable abstraction definitions. The extending abstraction\n definition must have a bus type that extends the bus type of the extended abstraction definition. The\n logical signals of the extended abstraction definition can be used and the following elements can be\n edited:\n
- \n
- Presence \n
- Width \n
- Default value \n
- Driver \n
- System group \n
Logical signal properties
\n\n Name is a mandatory unique identifier for the logical signal.\n
\n\n\n Mode defines for which interface mode the settings apply.\n
\n- \n
- \n initiator defines constraints for this signal when present in an initiator bus interface.\n \n
- \n target defines constraints for this signal when present in a target bus interface.\n \n
- \n system defines constraints for this signal when present in a system bus interface with a\n matching group name.\n \n
\n Presence is an optional restriction for the logical signal presence in a bus interface. It can\n have one of the following three values:\n
\n- \n
- \n required indicates that the logical signal must appear in the connected bus interface.\n \n
- \n illegal indicates that the logical signal must not appear in the connected bus interface.\n \n
- \n optional does not apply any restrictions. This is the default value.\n \n
\n Qualifier is an optional indicator for what kind of information the the signal carries. It can\n have any combination of the following values:\n
\n- \n
- \n address indicates that the signal carries address information.\n \n
- \n data indicates that the signal carries data.\n \n
- \n clock indicates that the signal carries clock information.\n \n
- \n reset indicates that the signal is a reset signal for the bus interface and is used to set\n the interface into a know valid state. The reset level can also be specified either as low or high or undefined.\n \n
- \n valid indicates that the data on the interface is currently valid.\n \n
- \n interrupt indicates that the signal carries reset interrupt information.\n \n
- \n clock enable indicates that the signal carries clock enable information. Clock enable level can be set in a similar manner as reset level.\n \n
- \n power enable indicates that the signal carries power enable information. Power enable level can be set in a similar manner as reset level.\n \n
- \n opcode indicates that the signal carries opcode information.\n \n
- \n protection indicates that the signal carries protection or security information.\n \n
- \n flow control indicates that the signal carries flow control information. Additionally, the flow type can be specified.\n \n
- \n user indicates that the signal carries user-defined information.\n \n
- \n request indicates that the signal carries request information.\n \n
- \n response indicates that the signal carries response information.\n \n
\n Port match specifies that the ports on both sides of the connection need to be present if set to true.\n
\n\n\n System group helps identify the system interface the signal belongs to. System group is\n mandatory for system mode and illegal for other modes.\n
\n\n Description is an optional free text for further details.\n
\n\nWire properties
\n\n Direction is an optional restriction for the logical signal direction in the connected bus\n interface. Direction can have one of the following values:\n
\n- \n
- \n in\n \n
- \n out\n \n
- \n inout\n \n
\n Width is an optional definition of the number of bits in the logical signal. If not specified,\n the number of bits in the connected physical port is used.\n
\n\n Default value is an optional value that is applied when the logical signal is not connected in\n a connected bus interface.\n
\n\n Driver is an optional setting for defining what kind of a driver the logical signal requires in\n a complete design. The possible values are the following:\n
\n- \n
- \n any indicates that any logical signal or value is valid for driving the signal. This is the\n default value.\n \n
- \n clock indicates that a repeating waveform is required.\n \n
- \n singleshot indicates that a non-repeating waveform is required.\n \n
- \n none indicates that no driver is required.\n \n
Transactional properties
\n\n Initiative optional definition of the access type. Initiative can have any of the folowing\n values:\n
\n- \n
- \n requires\n \n
- \n provides\n \n
- \n requires/provides\n \n
\n Kind specifies the type of the transactional port. It can be one of the following values, though\n tlm_port should be used for TLM1 notation, while others whould be used for TLM2:\n
\n- \n
- \n tlm_port\n \n
- \n tlm_socket\n \n
- \n simple_socket\n \n
- \n multi_socket\n \n
- \n custom name\n \n
\n Bus width specifies the data width in bits.\n
\n\n Protocol type characterizes the communication protocol. Type can be one of these values:\n
\n- \n
- \n tlm\n \n
- \n custom\n \n
\n Protocol can contain a payload specifying the way information is transported. Payload has the\n following sub elements:\n
\n- \n
- \n Name, specifying the payload's name.\n \n
- \n Type mandatory specification of typing. Can have either of the two values:\n
- \n
- \n generic\n \n
- \n specific\n \n
\n - \n Extension determines an extension for the payload.\n \n
API Definition
\r\n\r\n API definitions are used to define API dependencies between SW components in more detail.\r\n API definition wraps an SW library or other API to offer more thorough validation for or\r\n both software and system designs and to provide context-sensitive content assistance in\r\n the code editor. API definition consists of three types of information:\r\n
\r\n\r\n COM definition reference can be used to reference a COM definition in order to\r\n use its transfer types and properties in the function definitions so that the content\r\n assist in the code editor can give more detailed assistance.\r\n
\r\n\r\n Data types define all data types the API makes available for use in the code.\r\n
\r\n\r\n Functions list is filled with all functions that the API contains. For each\r\n function, all its parameters are defined in detail, including any restrictions that\r\n depend on the referenced COM definition.\r\n
\r\n\r\n\r\n" }, { "path": "Help/definitions/busdefinition.html", "content": "\r\n\r\n \r\n\r\n\r\nBus Definition
\r\n\r\n Bus definitions are used to define bus connections in HW designs. Each bus interface of a component\r\n must refer to a bus definition and connected bus interfaces must refer to the same bus definition.\r\n\r\n
\r\n Allow direct connections defines if a bus interface can be directly connected to\r\n a non-mirrored bus interface. If unselected, a bus interface can be connected only to\r\n a mirrored bus interface of the same type e.g. master to mirrored-master and system to mirrored-system.\r\n
\r\n\r\n\r\n Support broadcast defines if a bus interface can be directly connected to more\r\n than one opposing interface i.e. supports one-to-many connections.\r\n Notice that bridges and mirrored connections are possible even when broadcasts are not supported.\r\n
\r\n\r\n\r\n Addressable bus defines if the bus has addressing information and\r\n a memory map can be traced through a bus interface.\r\n
\r\n\r\n\r\n Max masters on bus defines the maximum number of master bus interfaces connected to\r\n the bus. If unspecified, the number of masters is unbound.\r\n
\r\n\r\n\r\n Max slaves on bus defines the maximum number of slaves bus interfaces connected to\r\n the bus. If unspecified, the number of slaves is unbound.\r\n
\r\n\r\n\r\n System group names defines the group names available for signals with the system mode.\r\n In bus interface the selected system group limits the logical signals to those with the\r\n matching system group name.\r\n
\r\n\r\n\r\n Description is a text that describes further details, such as the purpose of the bus\r\n and link to the specification.\r\n
\r\n\r\n Extended bus definition allows the creation of a family of interconnectable bus definitions.\r\n The following values of the bus interface are set to match the extended bus interface:\r\n
\r\n- \r\n
- Allow non-mirrored connections \r\n
- Support broadcast \r\n
- Addressable bus \r\n
- \r\n System group names are modified to include the names given in the extended bus interface.\r\n These cannot be removed or renamed in the bus definition.\r\n \r\n
- In addition, a placeholder for the description is given from the extended bus definition. \r\n
Bus Definition
\n\n Bus definitions are used to define bus connections in HW designs. Each bus interface of a component\n must refer to a bus definition and connected bus interfaces must refer to the same bus definition.\n \n
\n Display name is a short descriptive text for the bus definition. Can be used as an\n identifier in GUI applications, for instance.\n
\n \n\n Short description is a compact description of the bus definition.\n
\n\n\n Description is a text that describes further details, such as the purpose of the bus\n and link to the specification.\n
\n \n\n Allow direct connections defines if a bus interface can be directly connected to\n a non-mirrored bus interface. If unselected, a bus interface can be connected only to\n a mirrored bus interface of the same type e.g. initiator to mirrored-initiator and system to mirrored-system.\n
\n\n\n Support broadcast defines if a bus interface can be directly connected to more\n than one opposing interface i.e. supports one-to-many connections.\n Notice that bridges and mirrored connections are possible even when broadcasts are not supported.\n
\n\n\n Addressable bus defines if the bus has addressing information and\n a memory map can be traced through a bus interface.\n
\n\n\n Max initiators on bus defines the maximum number of initiator bus interfaces connected to\n the bus. If unspecified, the number of initiators is unbound.\n
\n\n\n Max targets on bus defines the maximum number of target bus interfaces connected to\n the bus. If unspecified, the number of targets is unbound.\n
\n\n\n System group names defines the group names available for signals with the system mode.\n In bus interface the selected system group limits the logical signals to those with the\n matching system group name.\n
\n\n\n Extended bus definition allows the creation of a family of interconnectable bus definitions.\n The following values of the bus interface are set to match the extended bus interface:\n
\n- \n
- Allow non-mirrored connections \n
- Support broadcast \n
- Addressable bus \n
- \n System group names are modified to include the names given in the extended bus interface.\n These cannot be removed or renamed in the bus definition.\n \n
- In addition, a placeholder for the description is given from the extended bus definition. \n
Catalog
\n\n Catalogs are used to group together IP-XACT documents that are somehow related.\n For example, a catalog could list all the IP-XACT documents i.e. components,\n designs and design configurations required in composing a specific\n product. Catalogs can also include other catalogs.\n
\n\n Description is an optional field for textual description of the catalog.\n
\n\nCatalog files
\n\n Catalog files lists the IP-XACT document files contained within catalog. All the\n files are categorized according to the document type i.e. Components and\n Designs are listed in separate sections. Items can be added by drag-dropping\n from the IP-XACT library or creating new rows from the context menu (right mouse\n button).\n
\n\n Vendor, Library, Name and Version together identify the IP-XACT\n document in the catalog.\n
\n\n Path is mandatory and defines the path to the IP-XACT document XML file.\n Path must be defined as relative to the catalog XML-file, as an absolute path or\n as an external URI. If an URI is used, the schema must be explicitly defined (e.g.\n http://...).\n
\n\n The Catalog files editor also contains a context menu (right mouse button) that\n has the following options:\n
\n- \n
- Opens the selected item (Catalog, Component or Bus) in separate editor. (Open) \n
- Add new file to the catalog (Add row) \n
- Remove file from catalog (Remove row) \n
- Cut the selected cell content to clipboard(Cut) \n
- Copy the contents of the selected cells to clipboard \n
- Paste the contents of the clipboard to the selected cells \n
- Clear the selected cells \n
- Expand all categories to show all files (Expand all) \n
- Collapse all categories to hide all files (Collapse all) \n
Catalog
\n\n Catalogs are used to group together IP-XACT documents that are somehow related.\n For example, a catalog could list all the IP-XACT documents i.e. components,\n designs and design configurations required in composing a specific\n product. Catalogs can also include other catalogs.\n
\n\n Display name is a short descriptive text for the catalog. Can be used as an\n identifier in GUI applications, for instance.\n
\n\n Short description is a compact description of the catalog.\n
\n\n Description is an optional field for textual description of the catalog.\n
\n\nCatalog files
\n\n Catalog files lists the IP-XACT document files contained within catalog. All the\n files are categorized according to the document type i.e. Components and\n Designs are listed in separate sections. Items can be added by drag-dropping\n from the IP-XACT library or creating new rows from the context menu (right mouse\n button).\n
\n\n Vendor, Library, Name and Version together identify the IP-XACT\n document in the catalog.\n
\n\n Path is mandatory and defines the path to the IP-XACT document XML file.\n Path must be defined as relative to the catalog XML-file, as an absolute path or\n as an external URI. If an URI is used, the schema must be explicitly defined (e.g.\n http://...).\n
\n\n The Catalog files editor also contains a context menu (right mouse button) that\n has the following options:\n
\n- \n
- Opens the selected item (Catalog, Component or Bus) in separate editor. (Open) \n
- Add new file to the catalog (Add row) \n
- Remove file from catalog (Remove row) \n
- Cut the selected cell content to clipboard(Cut) \n
- Copy the contents of the selected cells to clipboard \n
- Paste the contents of the clipboard to the selected cells \n
- Clear the selected cells \n
- Expand all categories to show all files (Expand all) \n
- Collapse all categories to hide all files (Collapse all) \n
COM Definition
\r\n\r\n COM definitions are used to define more strictly the connections that relate to higher-level communication between HW/SW components in a system design.\r\n\t\tCOM definition consists of two types of information: transfer types and properties.\r\n
\r\n\t\r\n\t Transfer types is an enumeration of possible data types that define what kind of data can be communicated between components via connections that are based on this COM definition.\r\n\t The used transfer type for each COM interface in a component is selected in the component editor.\r\n\t
\r\n\t\r\n\t Properties offer a way to define certain variables whose value must be set for each COM interface.\r\n\t Properties can be either required or optional. COM definition defines the data type and default value for each of the properties.\r\n\t
\r\n\r\n\r\n" }, { "path": "Help/general/colors.html", "content": "\n\n \n \n \nColors
\n\n In Kactus2, elements that are currently in an invalid\n\tstate are displayed in red. Mandatory fields have lemon chiffon background. Disabled fields have light grey background.\n
\n\n Likewise, in console error messages are displayed in red and regular messages are displayed in \n blue.\n
\n \n" }, { "path": "Help/general/defaultApplication.html", "content": " \n\n\n \nDefault Application
\n\nYou may select the default application for each file type within Kactus2. For instance, this could be the default text editor for makefiles.
\n\n- \n
- Open settings. \n
- Select Environment variables. \n
- Double click to create a new row, set the name for the new variable, and set field value as the path to the program. \n
\n\n![\"EnvironmentVariables\"](\"../images/EnvironmentVariables.png\")
\n\n
- \n
- Open settings. \n
- Select File Types. \n
- Go to the row of the desired file type. Set field Executed with as the variable in format $(VARIABLE_NAME). \n
- You may also opt to edit the file type within the built-in text editor of Kactus2, although this should be considered mostly as a fall-back. \n
\n\n![\"FileTypes\"](\"../images/FileTypes.png\")
\n\r\n\n"
},
{
"path": "Help/general/expressions.html",
"content": " \r\n\r\n
Expressions
\r\n\r\nMany fields within Kactus2 accept expresions as their input value for easy\r\nand fast configuration. The function sign f(x) is used to identify\r\nthese fields. The input should conform to the SystemVerilog\r\nsyntax to be acceptable.\r\n
\r\n\r\nConstant values
\r\n\r\nConstant numeric values can be given as decimal values (e.g. 15) or by explicitly\r\ndefining the base (e.g. 'h0F for 15 in hexadecimal). The possible bases are\r\n'b (binary), 'o (octal), \r\n'd (decimal) and 'h (hexadecimal).\r\nAlso fractional numbers (e.g. 0.25) can be used where applicable.\r\nOther numeric formats, e.g. 0x000F and 0b0010, will not be accepted.\r\n
\r\n\r\n\r\nString values must be given within double quotes e.g. \"This is a string value\".\r\n
\r\n\r\n\r\nBoolean true and false are accepted and will be interpret as 1 and 0, respectively.\r\n
\r\n\t\r\nOperations
\r\nKactus2 supports the following operations:
\r\n| Operator(s) | \r\n\tDescription | \r\n\tExample | \t \r\n\t
|---|---|---|
| +,-,*,/ | \r\n\tBasic arithmetic operations | \r\n\t2*4 (8) | \r\n\t
| &&,|| | \r\n\tBasic logical operations: AND,OR | \r\n\t1 || 0 (true) | \r\n\t
| &,|,^,~ | \r\n\tBitwise logical operations: AND,OR,XOR,NOT | \r\n\t4'b0011 & 4'b0110 (2) | \r\n\t
| <<,>> | \r\n\tShift operations | \r\n\t4'b0011 << 1 (6) | \r\n\t
| ** | \r\n\tPower operation | \r\n\t2**4 (16) | \r\n\t
| <,>,<=,>=,==,!= | \r\n\tComparison of two values | \r\n\t4 >= 2 (true) | \r\n\t
| ==,!= | \r\n\tComparison of string values | \r\n\t\"abc\" != \"bcd\" (true) | \r\n\t
| $clog2() | \r\n\tCeiling of logarithm of base 2 | \r\n\t$clog(9) (4) | \r\n\t
| $exp() | \r\nExponential function | \r\n$exp(2) (0.135335) | \r\n
| $pow() | \r\nPower function | \r\n$pow(2, 4) (16) | \r\n
| $sqrt() | \r\nSquare root | \r\n$sqrt(9) (3) | \r\n
| ?: | \r\n\tConditional (ternary) operator | \r\n\t1?2:0 (2) | \r\n\t
Library Navigation
\n\nHow to access IP-XACT documents and open them for editors.
\n \nVLNV Tree
\n\nDocuments are sorted to VLNV tree based on the VLNV tuple of a document.
\n\n- \n
- Select VLNV tree. \n
- Browse to the desired document, double click to open. \n
- Right click for context menu. The additional options include opening and creating designs. \n
- The external interfaces and ad-hoc ports are illustrated in the preview. \n
![\"VLNVtree\"](\"../images/VLNVtree.png\")
\n\nHierarchy Navigation
\n\nDocuments are sorted to hierarchy display based on their position in designs and sub designs.
\n\n- \n
- Select hierarchy. \n
- Hierarchical components are expandable, displaying the associated designs and the components that have instances in the design. \n
- Hierarchical navigation is recursive, so that a design within a design is also expandable. \n
- This column displays how many instances in the design use the component. \n
![\"ProtectionLocation\"](\"../images/HierarchyNavigation.png\")
\n\n\nLibrary Filters
\n\nYou may limit the number of displayed IP-XACT documents using filters:
\n\n- \n
- Hide/show filters \n
- Only documents which type is checked are displayed. Advanced stands for designs and design configurations. \n
- Hide documents that do not match the implementation. For instance, unchecking HW hides all hardware components and buses. \n
- Hide components that do not match any checked hierarchy level. \n
- Hide components that do not match any checked firmness level. \n
- Hide documents that have no errors or do have errors. \n
- Hide documents that do not have the tags listed here. \n
![\"Filters\"](\"../images/LibraryFilter.png\")
\n\n\n"
},
{
"path": "Help/general/shortcuts.html",
"content": "\n\n \n\n\n Kactus2 shortcuts
\n\t\n Kactus2 uses the following shortcuts.\n
\n| Key sequence | \n\tDescription | \n\t
|---|---|
| CTRL + L | \n\tLock/Unlock document. | \n\t
| CTRL + {Z, X, C, V, A} | \n\tUsual shortcuts for editing | \n\t
| F2 | \n\tEdit item. | \n\t
| CTRL + TAB | \n\tMove to the next tab. | \n\t
| CTRL + SHIFT + Tab | \n\tMove to the previous tab. | \n\t
| SHIFT + RETURN | \n\tAdd a row to table. | \n\t
| SHIFT + DEL | \n\tRemove selected row(s) from table. | \n\t
Toolbars and views
\nToolbars
\n\n The Kactus2 main window contains a toolbar at the top and sidebars on both sides. The toolbar contains actions for\n performing common actions within the Kactus2.\n
\n\n The toolbar adapts to the size of the window. If the window gets too small for the\n toolbar, two buttons for scrolling left and right will be made visible.\n Scrolling can also be done by using the mouse wheel.\n
\n\n The toolbar hides actions that are not available in the current environment. For example,\n generators are not show when no component or design has been selected.\n
\n\n UI views can be docked to a sidebar. Multiple views can be docked\n to the same sidebar and the active view can be hidden by clicking its icon in the sidebar, or changed \n by clicking the icon of another view.\n
\nThe toolbar groups
\n\n The File group contains functions for controlling the files of the component.\n
- \n
- \n
![](\"../images/file-new.png\")
New. Creates a new component, design, system,\n bus, COM definition or API definition.\n
\n \n - \n
![](\"../images/file-save.png\")
Save. Saves the active document with its\n current name and location. Activates when a document has been edited.\n \n - \n
![](\"../images/file-save-as.png\")
Save As. Saves the document with a new name\n and location.\n \n - \n
![](\"../images/file-save_all.png\")
Save all. Saves all open documents.\n \n - \n
![](\"../images/file-print.png\")
Print. Prints the currently open design.\n \n - \n
![](\"../images/export.png\")
Export image. Export an image of the currently open\n design document. Possible image formats are SVG, JPG and PNG.\n \n - \n
![](\"../images/import.png\")
Import File to Component. Imports elements from a\n source file e.g. VHDL or verilog to the active component.\n \n
\n
\n
\n
\n
\n
\n The Library group contains functions for maintaining the IP-XACT libraries used by the Kactus2.\n
- \n
- \n
![](\"../images/library-config.png\")
Configure libraries. Select the\n libraries used in Kactus2. The libraries can be set as default and active.\n \n - \n
![](\"../images/library-refresh.png\")
Refresh libraries. Refresh the currently\n active libraries.\n \n - \n
![](\"../images/checkIntegrity.png\")
View Library Integrity Report. Shows\n\t\t\ta report of errors within all library items. This operation may take a long time with\n\t\t\tlarge libraries.\n \n
\n
\n
\n The Protection group shows the current documents editability. The lock status can be changed with\n this button.\n
- \n
- \n
![](\"../images/protection-locked.png\")
Locked. While locked, no changes can be\n made to the document.\n \n - \n
![](\"../images/protection-unlocked.png\")
Unlocked. While unlocked, the documents\n can be edited and saved.\n \n
\n
\n The Generation group shows all the available generator plugins underneath Run generator:\n
- \n
- \n
![](\"../images/automation.png\")
Run generator\n Runs a chosen generator for the active component. If the active document is a design, all component\n instances are included in documentation generation.\n \n
\n The Diagram Tools group consist of tools related to the design editors of Kactus2. This group is only\n visible to the HW, SW and system design editors.\n
- \n
- \n
![](\"../images/diagram-add-column.png\")
\n Add Column. Creates a new column to the design. In HW design, the type of the possible\n items in the new column can be customized.\n \n - \n
![](\"../images/tool-select.png\")
\n Select Tool. Allows the selection of items within the HW design. Information regarding the\n selected item is show on the different editors of the des.\n \n - \n
![](\"../images/tool-interconnection.png\")
\n Interconnection Tool. Allows the creation of interconnections between the interfaces of\n component instances. After selecting the starting point, the possible ending points for the\n connection are highlighted in the design. An interconnection cannot be dragged from the starting\n point to the ending point. Both points must be selected separately.\n \n - \n
![](\"../images/tool-interface.png\")
\n Interface Tool. Draft interfaces can be to the component containing the currently opening\n design. These interfaces must be placed within columns allowing interface items.\n \n - \n
![](\"../images/tool-drafting.png\")
\n Drafting Tool. Allows the creation of draft component instances and interfaces. The drafted\n component instances must be placed in columns allowing component instances. Interfaces can be\n placed either into the component containing the design, or any of the drafted component instances.\n \n - \n
![](\"../images/tool-toggle_offpage.png\")
\n Toggle Off-Page Tool. Changes the selected connections from regular to off-page, and from\n off-page to regular. Off-page connections are displayed as squares near an interface, and the\n connected point is displayed when an off-page point is selected.\n \n - \n
![](\"../images/balloon.png\")
\n Sticky Note Tool. Create notes regarding the currently open design. Notes can be associated\n with an item contained within the design. This can be achieved through the button located at the\n top right corner of the note.\n \n
\n
\n
\n
\n
\n
\n
\n The Filtering Tools group has actions for filtering and adjusting the visualization of the memory\n\tlayout for current component hierarchy. Available only in the Memory Designer.\n
- \n\t\t
- \n
![](\"../images/filterSegments.png\")
\n Filter Segments. Show/hide the segments within the address spaces.\n \n\t\t\t - \n
![](\"../images/filterAddressBlocks.png\")
\n Filter Address Blocks. Show/hide the address blocks within the memory maps.\n \n\t\t\t - \n
![](\"../images/filterRegisters.png\")
\n Filter Registers. Show/hide the registers within the address blocks.\n \n\t\t\t - \n
![](\"../images/filterFields.png\")
\n Filter Fields. Show/hide the bit fields within the registers.\n \n\t\t\t - \n
![](\"../images/addressSpaceFilter.png\")
\n Address Space Filter. Show/hide the address space items on the path\n\t\t\t\tfrom the furthest address space to the connected memory maps.\n \n\t\t\t - \n
![](\"../images/filterUnconnectedMemoryItems.png\")
\n Unconnected items filter Show/hide unconnected memory items.\n \n\t\t\t - \n
![](\"../images/compressMemoryItems.png\")
\n Compress Memory Items. Minimize the vertical space taken by the\n\t\t\t\tmemory items. When disabled, the item height is relative to the contained address range.\n \n\t\t\t - \n
![](\"../images/compressFields.png\")
\n Compress Field Items. Minimize the horizontal space taken by the bit field items.\n \n - \n
![](\"../images/extendFields.png\")
\n Extend Field Items. Extend the horizontal space taken by the bit field items.\n\t\t\t\tThis ensures the full name is visible for every item.\n \n
\n\t\t\t
\n\t\t\t
\n\t\t\t
\n
\n
\n\t\t\t
\n\t\t\t
\n\t\t\t
\n
\n The View group has actions for defining the view of the current design. Visible Windows -button\n is always available.\n
- \n
- \n
![](\"../images/view-zoom_in.png\")
Zoom In. Enlarge the display of the active\n design.\n \n - \n
![](\"../images/view-zoom_out.png\")
Zoom Out. Reduce the display of the active\n design.\n \n - \n
![](\"../images/view-zoom_original.png\")
Original 1:1 Zoom. Return the display\n to original size.\n \n - \n
![](\"../images/view-fit_best.png\")
Fit Document to View. Fit the currently\n active document to the available view.\n \n - \n
![](\"../images/dockSelect.png\")
Visible Windows. Allows changing the\n visibilities of the available windows.\n \n - \n
![](\"../images/visibility.png\")
Visibilities. Change the visibilities of\n design items.\n \n
\n
\n
\n
\n
\n
\n The Configuration group contains actions related to configuring the currently open document.\n
- \n
- \n
![](\"../images/viewConfiguration.png\")
View Configuration. Configure the views used\n in the currently open document. The items are constructed recursively, so that the contained items\n within a component with a hierarchical view are displayed below said item. This allows the display\n of all the items contained within the currently active document.\n \n - \n
![](\"../images/memoryDesigner.png\")
Open Memory Designer. Opens a view of the memory\n layout of the underlying component hierarchy. Available only in Hardware Design view.\n \n
\n
\n The Workspace group shows the currently selected workspace.\n
- \n
- \n
![](\"../images/workspace.png\")
Workspace. Select, delete or create other \n workspaces. Only non-active, non-default workspaces can be deleted.\n \n
\n The System group contains actions related to the whole system.\n
- \n
- \n
![](\"../images/settings-general.png\")
Settings. Displays the available settings\n for Kactus2.\n \n - \n
![](\"../images/system-help.png\")
Help. Opens the Kactus2 manual.\n \n - \n
![](\"../images/system-about.png\")
About. Shows information about Kactus2.\n \n - \n
![](\"../images/system-exit.png\")
Exit. Exit Kactus2.\n \n
\n
\n
\n
Views
\n\n Views are used to present additional data regarding the currently open document.\n
\nCommon
\n\n Views that can be displayed regardless of the currently open document:\n
- \n
- \n Context Help displays help of the currently open document or editor.\n \n
- \n IP-XACT Library shows the used libraries of Kactus2. See\n library navigation.\n \n
- \n Output displays data of the actions performed by Kactus2.\n \n
Vendor Extensions
\n\n Vendor Extensions are used to edit the user defined extensions. Depending on the currently\n active editor, either the extensions of the current document or the active element are displayed.\n
\nDesign
\n\n Views that are related to design documents, both HW and system.\n
- \n
- \n Connection Editor displays data of the currently active interconnection. See\n interconnection,\n ad-hoc connection,\n api connection or\n com connection.\n \n
- \n Component Instance Details displays details of the active component instance. See\n component instance,\n HW mapping instance,\n SW component instance.\n \n
- \n Design Configuration Details allows the editing of the design details. The current\n design configuration can be changed, and the view configuration allows the\n editing of the active views for the contained component instances.\n \n
- \n Interface Editor displays data related to the currently active interface:\n
- \n
- \n Bus interface contains data of the bus type, abstraction type, the\n interface mode and the contained port maps.\n \n
- \n API interface displays the API type of the interface and its\n dependency direction.\n \n
- \n COM interface details the COM type, transfer type and\n direction of the interface, as well as allowing editing of its property values.\n \n
\n
HW design
\n\n Views for displaying details only related to a HW design.\n
- \n
- \n Ad hoc port editor allows the editing of ad hoc ports. The port names and directions are displayed, and\n port visibility can be enabled or disabled.\n \n
- \n Design parameters displays the parameters of the parameters associated with the current\n design. See parameters.\n \n
System design
\n\n Views for displaying details related only to a system design.\n
- \n
- \n HW Mapping Details allows the editing of the referenced HW component and selecting the\n referenced active view. Additional functions for handling the SW are also provided.\n \n
Workspaces
\n\nWorkspaces allow you to customize the sizes, locations, and visibilities of widgets for specific situations.
\n\n- \n
- Click workspace button on the top ribbon for workspace menu. \n
- You may select an existing workspace here. \n
- Creating new ones and deleting existing ones are supported. \n
- Insert the name for the new workspace on creation. \n
![\"CreateWorkSpace\"](\"../images/CreateWorkSpace.png\")
\n\nYou may also customize what is seen in the component editor, while using a workspace:
\n\n- \n
- Open settings. \n
- Select Component Editor Visibilities. \n
- Choose the workspace which you wish to customize. \n
- Unchecking/checking items hides/shows the component editor section on the row in the hierarchy level of the given column. \nFor instance, you may decide that product level components do not need to show sections for external interfaces. \n
- By clicking a row or a column header, the whole row or column is checked/unchecked. As another example, you may \ndecide that since this workspace is reserved for software work, it does not need other clock drivers. \n
![\"ComponentVisibilities\"](\"../images/ComponentVisibilities.png\")
\n\nYou may also customize design editors by dragging and closing the side widgets. For instance, in the image below, \nthe design configuration details widget has been detached to a floating window. You may reopen closed widgets with the visible \nwindows menu highlighted in the image.
\n\n\n\n![\"desgConfOnly\"](\"../images/WidgetsVisibility.png\")
\n\n\n"
},
{
"path": "Help/gettingStarted/accessingDocuments.html",
"content": " \n\n\n \n Step 2: Accessing Documents
\n\n- \n
- Select VLNV tree. \n
- Browse to the desired document, double click to open. \n
- Right click for context menu. The additional options include opening and creating designs. \n
- The external interfaces and ad-hoc ports are illustrated in preview. \n
- You need to open protection (ctrl + L) to modify the document. It is protected again with the same button or hotkey, or when protection of another document is opened. \n
The next step is creating documents.
\n
The previous step was configuring a library.
\n\n\n\n
![\"ProtectionLocation\"](\"../images/protection-location.png\")
\nStep 1: Configuring Library
\n\nKactus2 library settings determine, which folders are scanned for components and other IP-XACT documents.
\n- \r\n
- Click the configure library button on the top ribbon. \n
- Click the plus button to add new location by browsing the file system. \n
- Select the root folder of the documents as the library path. \n
- Make sure it is both active and default. \n
- Click OK. \n
- If any readable IP-XACT documents were found, they will show up under Library items. \n
Any new documents will be placed under the default location.
\n\nThe existing documents are scanned from all active locations.
\n\nThe next step is accessing documents.
\r\n\r\n![\"AddLibrary\"](\"../images/AddLibrary.png\")
\n\r\n\n"
},
{
"path": "Help/gettingStarted/creatingDocuments.html",
"content": " \n\n
Step 3: Creating Documents
\n\nA new document is required for new IP as well as for IP lacking IP-XACT packaging.
\n- \n
- Click the new button on the top ribbon. \n
- Select a document type. Detailed descriptions are in their corresponding sections in the manual.\n
- \n
- Bus Definition determines constraints for bus connections. \n
- Catalog groups IP-XACT documents. \n
- HW Component describes a hardware IP with behavioral functionality. \n
- HW Design describes an IP that instantiates and connects other hardware IPs. \n
- SW Component is used to group software source files and set their build rules. \n
- SW Design describes an IP that instantiates and connects other software IPs. \n
- System describes an IP that instantiates and connects software IPs and maps them to hardware IPs. \n
- API definition describes external functions provided by software components. \n
- COM Definition determines constraints for interprocess connections. \n
\n - In case of HW component or HW design, you may select hierarchy level and firmness. See more details in the component section of the manual. \n
- Type VLNV tuple for the document:\n
- \n
- Vendor identifies the owner. To ensure uniqueness, it should be their internet domain name in left-to-right order (e.g., tut.fi not fi.tut). \n
- Library is used to group documents, and thus should reflect the type of the IP-XACT document. This field is auto-filled with the selected hierarchy level, but you may replace it with something more accurate. \n
- The name should be self-explanatory. \n
- Technically, another version means another document. \n
\n - Select a directory for the new document. Default location is constructed from the VLNV. It is based on the location of the default library, which was chosen in step 1. \n
- Click OK. If you are creating a component, this will open the component creation wizard. If you are not importing any existing IP, close it by clicking Finish. \n
The previous step was accessing documents.
\n\n![\"CreatingDocument\"](\"../images/CreatingDocument.png\")
\n\n\n"
},
{
"path": "Help/hwdesign/adhocconnection.html",
"content": "\r\n
Ad-hoc Connection
\r\n\r\n\t\tAd-hoc connections define the ad-hoc connections for the component instances\r\n\t\tin the design. They are only used to connect individual physical ports\r\n whereas interconnections connect multiple ports grouped in the bus interfaces.\r\n
\r\n\t\r\nConnection Editor
\r\n\r\n The Connection Editor shows the properties of the selected connection.\r\n
\r\n\t\tA connection has a mandatory name and an optional description.\r\n\t\tBy default, the connection is named by the connected instances and ports.\r\n\t\tThe name also forms the basis for signal naming in the generated HDL.\r\n
\r\n\r\n The connected ports are shown at the bottom. Left Bound and Right Bound can be used\r\n to select the port bits in the connection. For example, a 2-bit port 'chip_select' could be connected\r\n to two different instances where the first is connected to the lower bit of 'chip_select'\r\n (chip_select[0:0]) and the second to the higher bit of 'chip_select' (chip_select[1:1]).\r\n
\r\n\r\n\r\n" }, { "path": "Help/hwdesign/adhocinterface.html", "content": "\r\r \r\r\rAd-hoc Interface
\r\r See Ad hoc Port.\r
\r\r\r" }, { "path": "Help/hwdesign/adhocport.html", "content": "\r\n\r\n \r\n\r\n\r\nAd-hoc Port
\r\n\r\n Ad hoc Port Details shows the selected port name, direction\r\n and bounds as defined in the containing component.\r\n
\r\n\r\n Tied value can be set\r\n to connect a port to a constant value e.g. 0 for unsed input. The value can be given\r\n as an expression, but it must resolve into a bit value compatible with the port\r\n width. Tied value is valid only for in/inout ports of a component instance and out/inout\r\n ports of the top-level component.\r\n\t
\r\n\r\n\t\tAd-hoc ports can be re-positioned by drag-dropping.\r\n\t
\r\n\r\n\r\n" }, { "path": "Help/hwdesign/businterface.html", "content": "\r\r \r\r\rBus Interface
\r\r See Bus Interface.\r
\r\r\r" }, { "path": "Help/hwdesign/busport.html", "content": "\n\n \n\n\nBus Interface
\n\n Bus Interfaces provide the connection points for the components. The access\n details are defined within the containing component, but the connections are defined\n in the design. Only compatible bus interfaces can be connected. The bus interface\n mode is indicated using the following colors:\n
\n\n ![](\"../images/interface_colors.png\")
\n
\n\t\tBus interfaces can be re-positioned by drag-dropping.\n\t
\nInterface Editor
\n\n The Interface Editor shows the selected bus interface bus definition, abstraction\n definition, name, interface mode and description as\n defined in the containing component. They are only editable if the bus interface\n is a draft. Otherwise all changes must be made in the containing component.\n
\n\n Port maps shows the mapping of logical ports on the bus to the physical ports\n in the containing component.
\n\n Exclude can be set to exclude the logical port from the port maps of the\n bus interface within this design.\n
\n\n\n" }, { "path": "Help/hwdesign/busport2022.html", "content": "\n\n \n\n\nBus Interface
\n\n Bus Interfaces provide the connection points for the components. The access\n details are defined within the containing component, but the connections are defined\n in the design. Only compatible bus interfaces can be connected. The bus interface\n mode is indicated using the following colors:\n
\n\n ![](\"../images/interface_colors2022.png\")
\n
\n\t\tBus interfaces can be re-positioned by drag-dropping.\n\t
\nInterface Editor
\n\n The Interface Editor shows the selected bus interface bus definition, abstraction\n definition, name, interface mode and description as\n defined in the containing component. They are only editable if the bus interface\n is a draft. Otherwise all changes must be made in the containing component.\n
\n\n Port maps shows the mapping of logical ports on the bus to the physical ports\n in the containing component.
\n\n Exclude can be set to exclude the logical port from the port maps of the\n bus interface within this design.\n
\n\n\n" }, { "path": "Help/hwdesign/connection.html", "content": "\r\n\r\n \r\n\r\n\r\nInterconnection
\r\n\r\t\tInterconnections define the connections for the component instances\r\t\tin the design.\r\n
\r\t\r\nConnection Editor
\r\n\r\n The Connection Editor shows the properties of the selected connection.\r
\r\t\tBus type VLNV and Abstraction type VLNV show the Bus Definition and\r\t\tthe Abstraction Definition that define the communication protocol on the bus.\r\t
\r\t\tA connection has a mandatory name and an optional description.\r\t\tBy default, the connection is named by the connected instances and interfaces.\r\t\tThe name also forms the basis for signal naming in the generated HDL.\r\n
\r\n\r\n Connected physical ports shows the physical ports as they are connected in\r\n the port maps of the connected bus interfaces and to which port(s) they are connected\r\n on the opposing end through the connection.\r\n
\r\n\r\n\r\n" }, { "path": "Help/hwdesign/hwdesign.html", "content": "\r\n\r\n \r\n\r\n\r\nHardware Design
\r\n\r\n A design describes the structure of a hardware component by instantiating other components from the \r\n library and connecting them. \r\n
\r\n\r\n The design area in the center is divided into typed columns to create cleaner\r\n layouts. There are four column types: 'Components', 'IO', 'Buses', and 'Custom'. Only items with matching\r\n types can be placed on a column. New columns can be created using the Add Column button in the \r\n toolbar. The column and its allowed types can edited by double-clicking the column header. \r\n The column order can be changed by drag-dropping the columns by the header.\r\n
\r\n\r\n New component instances can be added by by drag-dropping components from\r\n the library into the design area. If dropped on an existing instance, the component will\r\n\t\treplace the exisiting instance. Similarly, two existing instances can be swapped by holding the ALT-key\r\n\t\twhile drag-dropping one on the other.
\r\n ![](\"../images/hierarchy.png\")
A hierarchy icon is shown on the top right corner of the instance,\r\n if it has a design of its own. Double-clicking the instance opens the design. If the component\r\n does not have a design, the Component Editor is opened instead. Both options are also available\r\n by right-clicking the instance. All the bus interfaces in the component will be\r\n shown on the component instance and can be connected to other instances by creating an\r\n interconnection with the Interconnection Tool. \r\n Instances can be copy-pasted within the design or into other designs.\r\n Selecting an item in the design shows more details in the windows on the right.\r\n
Design Parameters
\r\n\r\n The Design is configurable through a set of parameters. Parameters are name-value \r\n pairs that can be referenced in e.g. configurable element values of the component instances\r\n to propagate the same value to every instance.\r\n For detailed information on parameters, see the parameters-section in the Component Editor.\r\n
\r\n\r\nAd-hoc Visibility
\r\n\r\n The Ad-hoc Visibility window is always visible in the design. It lists all the physical ports on the \r\n selected component instance. If no instance is selected, the ports of the top-level component are\r\n listed instead. Setting the ad-hoc option for a port shows the individual port on the \r\n component instance symbol or in the IO column, if it is a top-level port.\r\n
\r\n\r\nDesign Configuration Details
\r\n\r\n The Design Configuration Details window is always visible in the design. A design configuration \r\n contains additional information about an IP-XACT design. Each design can have multiple configurations. \r\n Design configuration defines what are the active views of the component instances in the design.\r\n While not explicitly mandatory, each component instance used in the design should have an active view defined. \r\n Connecting hierarchical draft bus interfaces to component instance bus interfaces require that an active view is \r\n defined for that component instance.\r\n
\r\n \r\n\r\nToolbar
\r\n \r\n\r\n Generation group has the tools for automatic generation of e.g. VHDL, Verilog, synthesis and \r\n simulation scripts, and HTML documentation.\r\n
\r\n\r\n Diagram tools has all the design-specific actions including adding columns, connections and\r\n IO pads. Individual connections can be changed to off-page for cleaner diagrams with \r\n Toggle Off-Page Tool. Preliminary components can be designed with the Drafting Tool.\r\n
\r\n\r\n View has the tools for zooming in and out in the design. Zooming is also possible by holding\r\n the Ctrl-key while scrolling with the mouse wheel. Visible Windows controls what information\r\n is shown i.e. IP-XACT library, component preview, context help and design specific windows on the right.\r\n Visibility control allows selection whether design details, such as 'sticky notes', are shown \r\n or not.\r\n
\r\n\r\n Workspaces store the window layout and visibilty settings. It is handy for quickly changing the \r\n layout depending on purpose, e.g. design editing vs. component packetization.\r\n
\r\n \r\n\r\n\r\n" }, { "path": "Help/hwdesign/hwinstance.html", "content": "\r\n\r\n \r\n\r\n\r\nComponent Instance
\r\n\r\nComponent Instance Details
\r\n\r\n Component Instance Details window shows the properties of the selected HW component.\r\n
\r\n\r\n Component VLNV shows the component identifier and cannot be changed.\r\n
\r\n\r\n Name is mandatory and used to identify the component instance. The name is\r\n also be used in the generated HDL. \r\n
\r\n\r\n Display name is an optional means of providing a user-friendly name for the instance. \r\n If defined, it is shown on the component instead of the name.\r\n
\r\n\r\n Description is an optional field for providing design specific details about the component instance.\r\n
\r\n\r\n Parameters are instance-specific configuration options and shows all the component \r\n parameters. The value can be set to override the default value\r\n in the component. The value is editable only, if the parameter resolve-property\r\n is set to 'user' or 'generated' within the component. By default parameters that cannot be \r\n edited are filtered out, but will be shown when Show immediate values is selected.\r\n
\r\n\r\n Module parameters are language-specific configuration options (equivalent of VHDL\r\n generics or Verilog parameters) similar to parameters. The element value can be set \r\n to override the default value in the component.\r\n
\r\n\r\nAd-hoc Visibility
\r\n\r\n The Ad-hoc visibility window shows all the physical ports on the selected component.\r\n Component symbols show all the bus interfaces by default, but individual\r\n ports will be shown only, if they are marked as ad-hoc.\r\n
\r\n\r\nDesign configuration
\r\n\r\n The design configuration is additional information about an IP-XACT design.\r\n Each design can have multiple configurations. Design configuration defines what\r\n is the active view of a component instance within the design.\r\n
\r\n\r\n\r\n" }, { "path": "Help/hwdesign/hwinstance2022.html", "content": "\n\n \n\n\nComponent Instance
\n\nComponent Instance Details
\n\n Component Instance Details window shows the properties of the selected HW component.\n
\n\n Component VLNV shows the component identifier and cannot be changed.\n
\n\n Name is mandatory and used to identify the component instance. The name is\n also be used in the generated HDL. \n
\n\n Display name is an optional means of providing a user-friendly name for the instance. \n If defined, it is shown on the component instead of the name.\n
\n\n Description is an optional field for providing design specific details about the component instance.\n
\n\n Power domains editor is used to create and edit references to external power domains of the design component\n and internal power domains of the component instance component.\n
\n\n Parameters are instance-specific configuration options and shows all the component \n parameters. The value can be set to override the default value\n in the component. The value is editable only, if the parameter resolve-property\n is set to 'user' or 'generated' within the component. By default parameters that cannot be \n edited are filtered out, but will be shown when Show immediate values is selected.\n
\n\n Module parameters are language-specific configuration options (equivalent of VHDL\n generics or Verilog parameters) similar to parameters. The element value can be set \n to override the default value in the component.\n
\n\nAd-hoc Visibility
\n\n The Ad-hoc visibility window shows all the physical ports on the selected component.\n Component symbols show all the bus interfaces by default, but individual\n ports will be shown only, if they are marked as ad-hoc.\n
\n\nDesign configuration
\n\n The design configuration is additional information about an IP-XACT design.\n Each design can have multiple configurations. Design configuration defines what\n is the active view of a component instance within the design.\n
\n\n\n" }, { "path": "Help/hwdesign/interconnectgenerator.html", "content": "\n\n \n\n\nInterconnect generator
\n\n Kactus2 features a generator for generating interconnect components to connect IP blocks in a given design. To launch the generator, press the button \n in the configuration tools section, while a design is open: \n
\n ![](\"../images/icn-generator-button.png\")
\n \n
Overview
\n\n The interconnect generator can create IP-XACT models for interconnect components using either transparent bridges or channels for addressing. \n RTL code generation (verilog) is supported for selected abstraction definitions and interconnect types. The RTL code relies on PULP open source libraries \n for the functional RTL.\n
\n\nGenerator dialog
\nInterconnect component VLNV editor
\n\n
![](\"../images/icn-component-vlnv-editor.png\")
\n \n VLNV editor is used to define the VLNV for the interconnect component. The generated IP-XACT document will be placed in the default library with a path derived from the VLNV.\n
\n\nInterconnect Component Configuration
\n\n
![](\"../images/icn-component-configuration.png\")
\n \n The interconnect component requires that an abstraction definition is selected for the bus interfaces that are generated. The abstraction definition should generally match the \n wanted interconnect type, such as AXI4 or OBI. The listed abstraction definition options are abstraction definitions in use by the bus interfaces of the component instances in the design.\n
\n\nGenerate RTL (experimental)
\n\n
![](\"../images/icn-dialog-generate-rtl.png\")
\n \n Apart from IP-XACT component description, a verilog RTL file can be automatically generated for supported configurations. RTL file generation is still experimental and requires that interconnect \n uses a compatible abstraction definition. Currently supported abstraction definitions are TUNI authored AXI4(LITE) and OBI abstractions. RTL generation is recommended for channel-type \n interconnect components, but bridges are also supported with limited address mapping capabilities. RTL generation also requires that the Verilog generator plugin is enabled. Generated RTL code \n needs bit width information for address and data widths. This information can be automatically extracted from selected abstraction definition, more information in the Interconnect component parameters section below.\n
\n\n The RTL file is generated to the interconnect component IP-XACT model location and the generated RTL can also be added to a file set by checking the \"Add to fileset\" checkbox and providing \n a name for the fileset.\n
\n\nInterconnect component parameters
\n\n
![](\"../images/icn-dialog-parameters.png\")
\n \n It is possible to define parameters for the interconnect component. Some parameters are automatically created for RTL generation. These are the address and data bit widths. To automatically\n extract widths, they must be parameterized in the selected abstraction definition. The disabled fields (grey background) in the screenshot above are automatically extracted width parameters. \n If no width parameters are found, then they are automatically created with default names ADDR_WIDTH and DATA_WIDTH. Whether the parameters were extracted or created, they cannot be removed \n during interconnect generation and only the value field can be edited.\n
\n\n Address ports in abstraction definition should use the address width \n parameter as the port width, and have address qualifier set. The same applies to data ports and data widths. As an example, below is a screenshot from TUNI AXI4LITE abstraction \n definition:\n
\n\n
![](\"../images/icn-dialog-addr-data-widths.png\")
\n\n Interconnect mode
\n\n
![](\"../images/icn-dialog-modes.png\")
\n \n Interconnect modes select which type of component is created: one using transparent bridges as the internal mapping, or one that uses a channel. Address mapping is currently only available for \n channel-based interconnect components.\n
\n\nInstances to connect
\n\n
![](\"../images/icn-dialog-instances.png\")
\n \n The Instances to connect section consists of a list where component instances found in the design can be selected to be connected to the interconnect component. Instance interfaces to connect \n can be selected with the round checkboxes. \n
\n\n For both bridge mode and channel mode, at least one initiator/master-adjacent and one target/slave-adjacent interface must be selected. Here, initiator-adjacent refers to an interface, which can be connected \n to a mirrored initiator/master interface of the interconnect component if channel mode is selected, or a target/slave interface if bridge mode is selected. Target-adjacent refers to an interface that can be \n connected to a mirrored target/slave interface if channel mode is selected, or an initiator/master interface if bridge mode is selected.\n
\n\n If channel mode is selected, it is possible to address-map the selected interfaces using the Start and Range editors. These editors accept IP-XACT expressions and parameters defined \n in the parameter editor (see above).\n
\n\n\n" }, { "path": "Help/index.html", "content": "\r\n\r\n \r\n\r\n\r\nKactus2 Manual
\r\n\r\n To access the manual topics, see the contents window (Right click on the menu bar).\r\n
\r\n\r\nSummary
\r\n\r\n\r\n Kactus2 is a toolset for designing embedded products, especially FPGA-based\r\n MP-SoCs. The aim is easier IP reusabilility and integration for both hardware and\r\n software. The tool is based on IEEE 1685-2014 \"IP-XACT\" standard.\r\n
\r\n \r\nWhat you can do with Kactus2
\r\n \r\nSee this page.
\r\n \r\nExamples
\r\n\r\n Example IPs are available in GitHub at \r\n\t\thttps://github.com/kactus2/ipxactexamplelib.\r\n
\r\n \r\nTutorials
\r\n\r\n Video tutorials are available in Youtube at \r\n\t\thttps://www.youtube.com/channel/UCsilC6PiJ8tH5ltGxL5M8VA.\r\n
\r\n\r\n\r\n" }, { "path": "Help/kactus2help.qhcp", "content": "\r\nMemory Design
\r\r Memory design displays all the address spaces and memory maps from the associated HW design. These are\r constructed from the component instances and their contained components. Connections made between the bus\r interfaces in the HW design are displayed here as connections between the address space referenced by the\r connected master bus interface and the memory map referenced by the connected slave interface.
\r Initially the memory design is shown at the most simple level, all the items and connections are condensed\r and both the sub memory items and bridge connections are hidden. These can all be expanded and shown\r through the buttons on the Filtering Tools group in the tool bar.\r
\r Address spaces are displayed in green on the left side of the view. The address spaces are constructed\r using the address spaces of the instanced components in the associated HW design. The address spaces can\r contain address segments.\r
\r\r Memory maps are displayed in blue on the right side of the view. The memory maps are constructed using the\r memory maps of the instanced components in the associated HW design. The memory maps can contain address\r blocks, registers and register fields.\r
\r\r The memory items are displayed as rectangular items containing information regarding the memory item.\r
- \r
- Name displays the name of the memory item. If the item has a display name, it is shown\r instead of the real name. \r
- Instance name displays the name of the component instance containing the memory item.\r The instance name is displayed only for the address spaces and memory maps. \r
- Base address displays the modified base address of the memory item. Displayed at the\r top corner of the item. \r
- Last address displays the modified last address of the memory item. Displayed at the\r bottom corner of the item. \r
\r Connections are featured as lines between the connected items, with the connection range displayed on\r both sides of the connection. Connections and the connected memory items are arrayd so that the ranges of\r the memory items and their sub memory items match.\r
\r\r Connections are divided into different classes:\r
- \r
- Regular connections. These are regular connections between an address space and a memory\r map. \r
- Bridge connections. Bridges are displayed as a connection between a master bus interface\r and another, bridged master bus interface. These connections are displayed in green, with a\r modified connection line. \r
- Local memory map connections. Local memory maps are displayed as connections between an\r address space and its local memory map. These are displayed in blue, with a modified connection\r line. \r
\r Overlapping connections are displayed in red. with the overlapping range areas displayed next to the\r connections.\r
\r\r All the sub memory items can be enabled or disabled through the use of buttons in the tool bar. This allows\r the user to display only the required information. Additionally, field items can be extended to display\r their full name. This can be achieved by pressing the button for extending the field items, or by pressing\r ALT together with using the mouse wheel.
\r The bridged connections are initially hidden, but they can be viewed through the use of Address Space\r Filter button.
\r As the memory items are initially displayed as compressed, it is possible to display them in full. This\r can be achieved through the Compress Memory Items button.\r
API Connection
\r\n\r\n This is Kactus2 extension
\r API connections define tight coupling of software component instances\r\t\tin the design. API interfaces are connected mainly between application and the platform (OS, drivers)\r\n in contrast to COM connections that are used for communication between application modules.\r\n
Connection Editor
\r\n\r\n The Connection Editor shows the properties of the selected API connection.\r
\r\t\tAPI type VLNV shows the API Definition that defines the communication protocol through\r the API.\r\t
\r\t\tAn API connection has a mandatory name and an optional description.\r\t\tBy default, the connection is named by the connected instances and interfaces.\r\n
\r\n\r\n\r\n" }, { "path": "Help/swsysdesign/comconnection.html", "content": "\r\n\r\n \r\n\r\n\r\nCOM Connection
\r\n\r\n This is Kactus2 extension
\r\n COM connections define the loose coupling of software component instances\r\t\tin the design. COM connections are mainly used for communication between application modules,\r\n in contrast to API interfaces that are used between application and the platform (OS, drivers).\r\n
Connection Editor
\r\n\r\n The Connection Editor shows the properties of the selected COM connection.\r
\r\t\tCOM type VLNV shows the COM Definition that defines the communication protocol.\r\t
\r\t\tA COM connection has a mandatory name and an optional description.\r\t\tBy default, the connection is named by the connected instances and interfaces.\r\n
\r\n\r\n\r\n" }, { "path": "Help/swsysdesign/hwmappinginstance.html", "content": "\r\n\r\n \r\n\r\n\r\nHW Mapping Instance
\r\n\r\n This is Kactus2 extension
\r\n This instance represents a HW component instance that can be used as a platform\r\n for running software i.e. it has at least one CPU element defined. HW mapping instances are\r\n automatically searched within the selected HW design hierarchy and shown in system design.\r\n Software components can be mapped on the platform by drag-dropping.\r\n
Component Instance Details
\r\n\r\n Component Instance Details window shows the properties of the selected HW mapping instance.\r\n
\r\n\r\n Component VLNV shows the component identifier and cannot be changed.\r\n
\r\n\r\n Name is mandatory and used to identify the instance.\r\n
\r\n\r\n Display name is an optional means of providing a user-friendly name for the instance. \r\n If defined, it is shown on the component instead of the name.\r\n
\r\n\r\n Description is an optional field for providing design specific details about the instance.\r\n
\r\n\r\n\t\tProperty values allow specifying parameters as name-value pairs.\r\n
\r\n\r\n\r\n" }, { "path": "Help/swsysdesign/swdesign.html", "content": "\r\n\r\n\r\n \r\n \r\n\tSW Design
\r\n\r\n This is Kactus2 extension
User can describe the structure of SW\r\n similarly ot HW design. All SW instantiated in one SW\r\n design will be executes on a single CPU. The mapping of SW\r\n design onto CPU HW is done in a system design.\r\n
\r\n Select SW components from the library and connect\r\n them.
Instead of interfaces and ports, SW\r\n components have API interfaces. There are two modes, a SW\r\n component can request an API (i.e. make calls to API\r\n functions) or provide it (i.e. implement the API\r\n functions). Connections are allowed only when interfaces match\r\n or if either interface is 'UNSET' (no API VLNV associated with\r\n it).\r\n
SW Component Instance
\r\n\t\r\n This is Kactus2 extension \r\n
Reusable piece of SW that is instantiated as a part of SW\r\n design. Each instance has a mandatory name, and\r\n optionally a display name and textual description.\r\n\t
\r\n\t\tFile set reference refers to a file set of the top component\r\n of the design that is to be used in conjunction with the instance.\r\n\t
\r\n\r\n\t\r\n\t\tProperty values allow specifying parameters as name-value pairs.\r\n\t
\r\n\r\n\r\n" }, { "path": "Help/swsysdesign/systemdesign.html", "content": "\r\n\r\n \r\n\r\n\r\nSystem Design
\r\n\r\n This is Kactus2 extension
\r\n A system design describes the software mapping on hardware resources. \r\n Software components can be mapped on hardware accelerators and\r\n CPUs, and connected using COM and API connections.\r\n
\r\n The design area in the center is divided into typed columns to create cleaner\r\n layouts. New columns can be created using the Add Column button in the \r\n toolbar. The column name can edited by double-clicking the column header. \r\n The column order can be changed by drag-dropping the columns by the header.\r\n
\r\n\r\n New software component instances can be added by by drag-dropping \r\n components from the library into the design area. Hardware components\r\n cannot be added directly, they must be defined in the underlying hardware design.
\r\n Double-clicking the instance opens the design.\r\n Selecting an item in the design shows more details in the windows on the right.\r\n
Design Configuration Details
\r\n\r\n The Design Configuration Details window is always visible in the design. A design configuration \r\n contains additional information about an the design. Each design can have multiple configurations. \r\n Design configuration defines what are the active views of the component instances in the design.\r\n
\r\n\r\nHW Mapping Details
\r\n\r\n The HW Mapping Details window is always visible in the system design. An HW component reference \r\n defines the top level hardware component for which the system design applies. \r\n HW component view defines the view containing the hardware design that is used as\r\n a platform for the system. Changes to the component reference and view must be confirmed by selecting\r\n Apply. Revert can be used to change back to the previous component configuration.\r\n
\r\n\r\n\r\n" }, { "path": "Help/swsysdesign/undefinedconnection.html", "content": "\r\n\r\n \r\n\r\n\r\nUndefined Connection
\r\n\r\n This connection has no defined type yet. Setting the connection endpoint to\r\n COM or API interface will automatically change the connection to the corresponding connection type.\r\n
\r\n\r\n\r\n" }, { "path": "Help/welcome.html", "content": "\r\n\r\n \r\n\r\n\r\nWelcome to Kactus2
\r\n\r\n This window will give context-sensitive guidance during your use of Kactus2.\r\n
\r\n\r\n Getting started section\r\n\t\twill guide you through the basic setup for configuring your IP-XACT library\r\n\t\tand accessing documents in the library.\r\n
\t \r\n\t\r\n ![](\"images/system-help.png\")
The help content can be browsed at any time\r\n\t\tby clicking the Help button in the toolbar.\r\n
What you can do with Kactus2
\n\nPackage IPs for reuse and exchange
\n\n- \n
- Import your existing IPs as IP-XACT components \n
- Create new IP-XACT components and generate their HDL module headers \n
- Reuse IP-XACT files from any standard compatible vendor \n
- Reuse the IPs in your designs and connect them with wires and busses \n
Create HW designs with hierarchy
\n\n- \n
- Create multilevel hierarchies, where a design has multiple sub-designs \n
- Configure component instances in designs, including the sub-designs \n
- Use generator plugins to create HDL with wiring and parameterization \n
Integrate HW and SW
\n\n- \n
- Use memory designer to preview memory maps and address spaces in your hierarchy \n
- Package software to IP-XACT components and map them to hardware \n
- Generate makefiles that build executables with rules defined in IP-XACT components \n
What you cannot do with Kactus2
\n- \n
- Behavioral logic: Neither Kactus2 nor IP-XACT handles module implementations \n
- Synthesis or simulation: These require tools that are specificly created for the purpose \n
![\"Kactus2](\"images/kactus2_flow.png\")
\n\n\n"
},
{
"path": "IPXACTmodels/AbstractionDefinition/AbstractionDefinition.cpp",
"content": "//-----------------------------------------------------------------------------\r\n// File: AbstractionDefinition.cpp\r\n//-----------------------------------------------------------------------------\r\n// Project: Kactus 2\r\n// Author: Esko Pekkarinen\r\n// Date: 10.08.2015\r\n//\r\n// Description:\r\n// Implementation for ipxact:busDefinition element.\r\n//-----------------------------------------------------------------------------\r\n\r\n#include \"AbstractionDefinition.h\"\r\n\r\n#include