Repository: karthisugumar/CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
Branch: master
Commit: 4afea5de1596
Files: 114
Total size: 1.7 MB

Directory structure:
gitextract_4n1buft_/

├── .gitattributes
├── README.md
├── rtl/
│   ├── FA.sv
│   ├── GLB_cluster.sv
│   ├── HA.sv
│   ├── HMNoC_cluster.sv
│   ├── HMNoC_cluster_east.sv
│   ├── HMNoC_cluster_west.sv
│   ├── HMNoC_top.sv
│   ├── MAC.sv
│   ├── PE.sv
│   ├── PE_cluster.sv
│   ├── SPad.sv
│   ├── circular_buffer.sv
│   ├── glb_iact.sv
│   ├── glb_psum.sv
│   ├── glb_weight.sv
│   ├── lookup_mux4.sv
│   ├── misc/
│   │   ├── FA.sv
│   │   ├── HA.sv
│   │   ├── circular_buffer.sv
│   │   ├── mux_4x1.sv
│   │   └── switch.sv
│   ├── mux2.sv
│   ├── mux_4x1.sv
│   ├── phase_1/
│   │   ├── GLB_cluster.sv
│   │   ├── HMNoC_cluster.sv
│   │   ├── PE.sv
│   │   ├── PE_cluster.sv
│   │   ├── SPad.sv
│   │   ├── glb_iact.sv
│   │   ├── glb_psum.sv
│   │   ├── glb_weight.sv
│   │   ├── router_cluster.sv
│   │   ├── router_iact.sv
│   │   ├── router_psum.sv
│   │   └── router_weight.sv
│   ├── phase_2/
│   │   ├── HMNoC_cluster_east.sv
│   │   ├── HMNoC_cluster_west.sv
│   │   ├── HMNoC_top.sv
│   │   ├── router.sv
│   │   └── router_cluster.sv
│   ├── phase_3/
│   │   ├── router.sv
│   │   ├── router_cluster.sv
│   │   └── router_network4.sv
│   ├── router.sv
│   ├── router_cluster.sv
│   ├── router_east.sv
│   ├── router_iact.sv
│   ├── router_network4.sv
│   ├── router_psum.sv
│   ├── router_weight.sv
│   └── switch.sv
├── synth/
│   ├── HMNoC_cluster.vds
│   ├── HMNoC_cluster_utilization_synth.rpt
│   ├── HMNoC_top.vds
│   ├── HMNoC_top_utilization_synth.rpt
│   └── constraints_1.xdc
└── testbench/
    ├── GLB_cluster_tb.sv
    ├── HMNoC_1_tb.sv
    ├── HMNoC_cluster_west_tb.sv
    ├── MAC_tb.sv
    ├── PE_cluster_tb.sv
    ├── PE_tb.sv
    ├── SPad_tb.sv
    ├── act_5x5.txt
    ├── act_7x7.txt
    ├── adder_tb.sv
    ├── glb_iact_tb.sv
    ├── kernel_3x3.txt
    ├── kernel_5x5.txt
    ├── phase_1/
    │   ├── GLB_cluster_tb.sv
    │   ├── HMNoC_1_tb.sv
    │   ├── PE_cluster_tb.sv
    │   ├── PE_tb.sv
    │   ├── router_cluster_5x5_tb.sv
    │   ├── router_cluster_tb.sv
    │   ├── router_iact.sv
    │   ├── router_iact_tb.sv
    │   ├── router_psum_tb.sv
    │   ├── router_weight.sv
    │   └── router_weight_tb.sv
    ├── phase_2/
    │   ├── HMNoC_cluster_west_tb.sv
    │   ├── router_cluster_new_tb.sv
    │   ├── router_cluster_pe_cluster_5x5_tb.sv
    │   ├── router_cluster_pe_cluster_tb.sv
    │   ├── router_east_tb.sv
    │   ├── router_pe_4_clusters_5x5_tb.sv
    │   └── router_pe_4_clusters_tb.sv
    ├── phase_3/
    │   ├── router_broadcast_tb.sv
    │   ├── router_multicast_tb.sv
    │   ├── router_pe_4_clusters_5x5_tb.sv
    │   ├── router_pe_4_clusters_tb.sv
    │   └── router_unicast_tb.sv
    ├── psum_3x3.txt
    ├── router_act.sv
    ├── router_broadcast_tb.sv
    ├── router_cluster_5x5_tb.sv
    ├── router_cluster_new_tb.sv
    ├── router_cluster_pe_cluster_5x5_tb.sv
    ├── router_cluster_pe_cluster_tb.sv
    ├── router_cluster_tb.sv
    ├── router_east_tb.sv
    ├── router_glb_tb.sv
    ├── router_iact.sv
    ├── router_iact_tb.sv
    ├── router_multicast_tb.sv
    ├── router_pe_4_clusters_5x5_tb.sv
    ├── router_pe_4_clusters_tb.sv
    ├── router_psum_tb.sv
    ├── router_unicast_tb.sv
    ├── router_weight.sv
    ├── router_weight_tb.sv
    └── switch_tb.sv

================================================
FILE CONTENTS
================================================

================================================
FILE: .gitattributes
================================================
# Auto detect text files and perform LF normalization
* text=auto


================================================
FILE: README.md
================================================
### UCSD CSE 240D Fall '19

# Hierarchical Mesh NoC - Eyeriss v2
## A SystemVerilog implementation of Row-Stationary dataflow based on Eyeriss and Hierarchical Mesh NoC based on the [Eyeriss v2 CNN accelerator](https://arxiv.org/abs/1807.07928).

This repository contains the SystemVerilog source code developed as part of the final project for the course "Accelerator Design for Deep Learning" at UCSD. Eyeriss is a popular CNN accelerator that showcased dataflow-based architectures using systolic arrays. The project implemented is inspired by the RS dataflow from the original Eyeriss paper and the Hierarchical Mesh NoC Architecture from the follow-up paper Eyeriss v2. 

![Image of top-level Architecture](https://github.com/karthisugumar/CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2/blob/master/images/Eyeriss_scaled_down_top.PNG)

### Prerequisites
#### Simulation requires a Verilog/SystemVerilog syntheis software package. Xilinx's Vivado Suite is recommended (available for free at the [Xilinx downloads webpage](https://www.xilinx.com/support/download.html))

### File structure

- **images/** - Figures used in report
  
- **synth/** - synthesis folder
  - *.xdc* file to specify timing constraints - clock period, waveform shape (can also be used to include jitter, uncertainty, false paths etc for more accurate STA)
  - *.vds* files contain synthesis log
  - *.rpt* files contain area utlization report
  
- **rtl/** - Contains SystemVerilog models of all components designed
  - **misc/** - combinational logic blocks for miscellaneous tasks
  - **phase_1/** - Focus on demonstration of a convolution operation through a single grouped cluster of PEs, routers and GLBs
  - **phase_2/** - Scaled-up design with 4 grouped clusters. Has new routers with provisions for direction control and configuration
  - **phase_3/** - Exploration of router design for data reuse opportunities - Unicast, Multicast, Broadcast
    
- **synth/** - constraints and reports directory - synthesis results containing top level and clusterized reports for timing and area utilization

- **testbench/** - Contains all testbenches, verification code, and experiments. 
  - **phase_1/, phase_2/, phase_3/** - Contains testbenches specific to each design phase
  
- **waveforms/** - directory containing simulation output graphs
  - *4_Convs.PNG* - parallel convolution output of 4 PE clusters
  - *conv_3x3.PNG* - convolution with 3x3 kernel size
  - *conv_5x5.PNG* - convolution with 5x5 kernel size
  - *conv_out.PNG* - phase_1 convolution output


================================================
FILE: rtl/FA.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 11/27/2019 07:43:21 AM
// Design Name: 
// Module Name: FA
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module FA( input A_in,
			input B_in,
			input C_in,
			output logic S_out,
			output logic C_out
    );
	
	assign {C_out, S_out} = A_in + B_in + C_in;
	
endmodule


================================================
FILE: rtl/GLB_cluster.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/01/2019 01:18:56 PM
// Design Name: 
// Module Name: GLB_cluster
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module GLB_cluster 
			#( 
			parameter DATA_BITWIDTH = 16,
			parameter ADDR_BITWIDTH = 10,
			parameter NUM_GLB_IACT = 1,
			parameter NUM_GLB_PSUM = 1,
			parameter NUM_GLB_WGHT = 1
			)
		   ( input clk,
			 input reset,
			 
			 input read_req_iact, 
			 input read_req_psum,
			 input read_req_wght,
			 
			 input write_en_iact, 
			 input write_en_psum,
			 input write_en_wght,
			 
			 input [ADDR_BITWIDTH-1 : 0] r_addr_iact,
			 input [ADDR_BITWIDTH-1 : 0] r_addr_psum,
			 input [ADDR_BITWIDTH-1 : 0] r_addr_wght,
			 
			 input [ADDR_BITWIDTH-1 : 0] w_addr_iact,
			 input [ADDR_BITWIDTH-1 : 0] w_addr_psum,
			 input [ADDR_BITWIDTH-1 : 0] w_addr_wght,
			 
			 input [DATA_BITWIDTH-1 : 0] w_data_iact,
			 input [DATA_BITWIDTH-1 : 0] w_data_psum,
			 input [DATA_BITWIDTH-1 : 0] w_data_wght,
			 
			 output logic [DATA_BITWIDTH-1 : 0] r_data_iact,
			 output logic [DATA_BITWIDTH-1 : 0] r_data_psum,
			 output logic [DATA_BITWIDTH-1 : 0] r_data_wght
			);
			
			//Instantiate iact global buffer
			generate
			genvar i;
			for(i=0; i<NUM_GLB_IACT; i++) 
				begin:glb_iact_gen
					glb_iact	#( .ADDR_BITWIDTH(ADDR_BITWIDTH),
								 .DATA_BITWIDTH(DATA_BITWIDTH)
								)
					glb_iact_inst ( .clk(clk), 
									.reset(reset),
									.read_req(read_req_iact),
									.write_en(write_en_iact), 
									.r_addr(r_addr_iact), 
									.w_data(w_data_iact),
									.r_data(r_data_iact), 
									.w_addr(w_addr_iact)
									);
				end
			endgenerate
			
			
			//Instantiate psum global buffer
			generate
			genvar j;
			for(j=0; j<NUM_GLB_PSUM; j++) 
				begin:glb_psum_gen
					glb_psum #( .ADDR_BITWIDTH(ADDR_BITWIDTH),
							.DATA_BITWIDTH(DATA_BITWIDTH)
							) 
					glb_psum_inst ( .clk(clk), 
									.reset(reset), 
									.read_req(read_req_psum),
									.write_en(write_en_psum), 
									.r_addr(r_addr_psum), 
									.w_data(w_data_psum),
									.r_data(r_data_psum), 
									.w_addr(w_addr_psum)
									);
				end
			endgenerate
	
			//Instantiate weight global buffer
			generate
			genvar k;
			for(k=0; k<NUM_GLB_WGHT; k++) 
				begin:glb_wght_gen
					glb_weight #( .ADDR_BITWIDTH(ADDR_BITWIDTH),
							.DATA_BITWIDTH(DATA_BITWIDTH)
							) 
					glb_weight_inst ( .clk(clk), 
									.reset(reset), 
									.read_req(read_req_wght),
									.write_en(write_en_wght), 
									.r_addr(r_addr_wght), 
									.w_data(w_data_wght),
									.r_data(r_data_wght), 
									.w_addr(w_addr_wght)
									);
				end
			endgenerate
endmodule


================================================
FILE: rtl/HA.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 11/27/2019 07:30:57 AM
// Design Name: 
// Module Name: HA
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module HA( input A_in,
		   input B_in,
		   output logic S_out,
		   output logic C_out
    );
	
	assign {C_out,S_out} = A_in + B_in;
	
endmodule


================================================
FILE: rtl/HMNoC_cluster.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/04/2019 06:59:19 AM
// Design Name: 
// Module Name: HMNoC_cluster
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module HMNoC_cluster#(
	
	parameter DATA_BITWIDTH = 16,
	parameter ADDR_BITWIDTH = 10,
	
	parameter DATA_WIDTH = 16,
    parameter ADDR_WIDTH = 9,
	
	// GLB Cluster parameters. This TestBench uses only 1 of each
    parameter NUM_GLB_IACT = 1,
    parameter NUM_GLB_PSUM = 1,
	parameter NUM_GLB_WGHT = 1,
	
	parameter ADDR_BITWIDTH_GLB = 10,
	parameter ADDR_BITWIDTH_SPAD = 9,
	
	parameter NUM_ROUTER_PSUM = 1,
	parameter NUM_ROUTER_IACT = 1,
	parameter NUM_ROUTER_WGHT = 1,
			
	parameter int kernel_size = 3,
    parameter int act_size = 5,
	
	parameter int X_dim = 3,
    parameter int Y_dim = 3,
	
	parameter W_READ_ADDR = 0, 
    parameter A_READ_ADDR = 0,
    
    parameter W_LOAD_ADDR = 0,  
    parameter A_LOAD_ADDR = 0,
	
	parameter PSUM_READ_ADDR = 0,
	parameter PSUM_LOAD_ADDR = 0
	)
	(
    input clk,
    input reset,
	
	input start,

	output load_done,
	
	//logic for GLB cluster
	input read_req_psum,

    input write_en_iact,
	input write_en_wght,

	input load_spad_ctrl_wght,
	input load_spad_ctrl_iact,
		
    input [ADDR_BITWIDTH-1 : 0] r_addr_psum,
	output logic [DATA_BITWIDTH-1 : 0] r_data_psum,
	
    input [ADDR_BITWIDTH-1 : 0] w_addr_iact,
    input [ADDR_BITWIDTH-1 : 0] w_addr_psum,
	input [ADDR_BITWIDTH-1 : 0] w_addr_wght,

    input [DATA_BITWIDTH-1 : 0] w_data_iact,
    input [DATA_BITWIDTH-1 : 0] w_data_psum,
	input [DATA_BITWIDTH-1 : 0] w_data_wght
	
	);
//	logic [DATA_WIDTH-1:0] act_in;
//    logic [DATA_WIDTH-1:0] filt_in;

//	logic load_en_wght, load_en_act;
  
    
//		logic [DATA_BITWIDTH-1 : 0] r_data_spad_psum[0:kernel_size-1];	
	
	
	//GLB cluster initialization
	GLB_cluster 
			#(	.DATA_BITWIDTH(DATA_BITWIDTH),
				.ADDR_BITWIDTH(ADDR_BITWIDTH),
				.NUM_GLB_IACT(NUM_GLB_IACT),
				.NUM_GLB_PSUM(NUM_GLB_PSUM),
				.NUM_GLB_WGHT(NUM_GLB_WGHT)
			)
	GLB_cluster_0
			(
				.clk(clk),   //TestBench/Controller
				.reset(reset),  //TestBench/Controller
				
				//Signals for reading from GLB
				.read_req_iact(router_cluster_0.read_req_glb_iact),
				.read_req_psum(read_req_psum), //Read by testbench/controller
				.read_req_wght(router_cluster_0.read_req_glb_wght),
				
			    .r_data_iact(router_cluster_0.r_data_glb_iact),
			    .r_data_psum(r_data_psum), //Read by testbench/controller
				.r_data_wght(router_cluster_0.r_data_glb_wght),
				
				.r_addr_iact(router_cluster_0.r_addr_glb_iact),
			    .r_addr_psum(r_addr_psum), //testbench for reading final psums
				.r_addr_wght(router_cluster_0.r_addr_glb_wght),

				
				//Signals for writing to GLB
			    .w_addr_iact(w_addr_iact), //testbench for writing
			    .w_addr_psum(router_cluster_0.w_addr_glb_psum),
				.w_addr_wght(w_addr_wght), //testbench for writing
 
			    .w_data_iact(w_data_iact), //testbench for writing
			    .w_data_psum(router_cluster_0.w_data_glb_psum),
				.w_data_wght(w_data_wght), //testbench for writing

				.write_en_iact(write_en_iact), //testbench for writing
				.write_en_psum(router_cluster_0.write_en_glb_psum),
				.write_en_wght(write_en_wght) //testbench for writing
			
			);

			
	
	//Router Cluster Instantiation
	router_cluster#(.DATA_BITWIDTH(DATA_BITWIDTH),
	                .ADDR_BITWIDTH_GLB(ADDR_BITWIDTH_GLB),
	                .ADDR_BITWIDTH_SPAD(ADDR_BITWIDTH_SPAD),

	                .kernel_size(kernel_size),
	                .act_size(act_size),

	                .NUM_ROUTER_PSUM(NUM_ROUTER_PSUM),
	                .NUM_ROUTER_IACT(NUM_ROUTER_IACT),
	                .NUM_ROUTER_WGHT(NUM_ROUTER_WGHT),

	                .A_READ_ADDR(A_READ_ADDR), 
	                .A_LOAD_ADDR(A_LOAD_ADDR),

	                .W_READ_ADDR(W_READ_ADDR), 
	                .W_LOAD_ADDR(W_LOAD_ADDR),

	                .PSUM_READ_ADDR(PSUM_READ_ADDR),
	                .PSUM_LOAD_ADDR(PSUM_LOAD_ADDR)
					)
	router_cluster_0
					(
					.clk(clk),  //TestBench/Controller
					.reset(reset),  //TestBench/Controller
					
					//Signals for activation router
					.r_data_glb_iact(GLB_cluster_0.r_data_iact),
					.r_addr_glb_iact(GLB_cluster_0.r_addr_iact),
					.read_req_glb_iact(GLB_cluster_0.read_req_iact),

					.w_data_spad_iact(pe_cluster_0.act_in),
					.load_en_spad_iact(pe_cluster_0.load_en_act),
					
					.load_spad_ctrl_iact(load_spad_ctrl_iact), //TestBench/Controller
					
					
					//Signals for weight router
					.r_data_glb_wght(GLB_cluster_0.r_data_wght),
					.r_addr_glb_wght(GLB_cluster_0.r_addr_wght),
					.read_req_glb_wght(GLB_cluster_0.read_req_wght),
					
					.w_data_spad_wght(pe_cluster_0.filt_in),
					.load_en_spad_wght(pe_cluster_0.load_en_wght),

					.load_spad_ctrl_wght(load_spad_ctrl_wght), //TestBench/Controller

					
					//Signals for psum router
					.r_data_spad_psum(pe_cluster_0.pe_out),
					
					.w_addr_glb_psum(GLB_cluster_0.w_addr_psum),
					.write_en_glb_psum(GLB_cluster_0.write_en_psum),
					.w_data_glb_psum(GLB_cluster_0.w_data_psum),
					
					.write_psum_ctrl(pe_cluster_0.compute_done) //Connected to compute done of PE
					);
	

//Declarations for PE_cluster
				

	
//PE_cluster Instantiation
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_0
    			(
					.clk(clk), 	   //TestBench/Controller
				    .reset(reset), //TestBench/Controller
					.start(start), //TestBench/Controller
					
				    .act_in(router_cluster_0.w_data_spad_iact),
					.filt_in(router_cluster_0.w_data_spad_wght),
					
					.load_en_wght(router_cluster_0.load_en_spad_wght),
					.load_en_act(router_cluster_0.load_en_spad_iact),
					
                    .pe_out(router_cluster_0.r_data_spad_psum),
					.compute_done(router_cluster_0.write_psum_ctrl),
					.load_done(load_done) //TestBench/Controller
    			);
				

endmodule


================================================
FILE: rtl/HMNoC_cluster_east.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/10/2019 02:47:05 PM
// Design Name: 
// Module Name: HMNoC_cluster_east
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module HMNoC_cluster_east
	#(
		parameter DATA_BITWIDTH = 16,
		parameter ADDR_BITWIDTH = 10,
		
		parameter DATA_WIDTH = 16,
		parameter ADDR_WIDTH = 9,
		
		// GLB Cluster parameters. This TestBench uses only 1 of each
		parameter NUM_GLB_IACT = 1,
		parameter NUM_GLB_PSUM = 1,
		parameter NUM_GLB_WGHT = 1,
		
		parameter ADDR_BITWIDTH_GLB = 10,
		parameter ADDR_BITWIDTH_SPAD = 9,
		
		parameter NUM_ROUTER_PSUM = 1,
		parameter NUM_ROUTER_IACT = 1,
		parameter NUM_ROUTER_WGHT = 1,
				
		parameter int kernel_size = 3,
		parameter int act_size = 5,
		
		parameter int X_dim = 3,
		parameter int Y_dim = 3,
		
		parameter W_READ_ADDR = 0, 
		parameter A_READ_ADDR = 0,
		
		parameter W_LOAD_ADDR = 0,  
		parameter A_LOAD_ADDR = 0,
		
		parameter PSUM_READ_ADDR = 0,
		parameter PSUM_LOAD_ADDR = 0
	
    )
	(	
		input clk,
		input reset,
		
		//PE Cluster Interface
		input start,
		output load_done,
		
		input load_en_wght,
		input load_en_act,
		
        output [DATA_WIDTH-1:0] pe_out[X_dim-1:0],
		output compute_done,
		
		
		//GLB Cluster Interface

		input write_en_iact,
		input write_en_wght,
		
		input [DATA_WIDTH-1:0] w_data_iact,
		input [ADDR_WIDTH-1:0] w_addr_iact,
		
		input [DATA_WIDTH-1:0] w_data_wght,
		input [ADDR_WIDTH-1:0] w_addr_wght,
		
		input [ADDR_WIDTH-1:0] w_addr_psum,		
				
		output [DATA_WIDTH-1:0] r_data_psum,
		input [ADDR_WIDTH-1:0] r_addr_psum,
	
		input read_req_iact,
		input read_req_psum,
		input read_req_wght,
		
		input [ADDR_WIDTH-1:0] r_addr_iact,
		input [ADDR_WIDTH-1:0] r_addr_wght,
		

		
		//WGHT Router Ports
		input [3:0] router_mode_wght,
		
		//Interface with North
		//Source ports
		input [DATA_WIDTH-1:0] north_data_i_wght,
		input north_enable_i_wght,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] north_data_o_wght,
		output logic north_enable_o_wght,
		
		
		//Interface with South
		//Source ports
		input [DATA_WIDTH-1:0] south_data_i_wght,
		input south_enable_i_wght,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] south_data_o_wght,
		output logic south_enable_o_wght,
		
		
		//Interface with West
		//Source ports
		input [DATA_WIDTH-1:0] west_data_i_wght,
		input west_enable_i_wght,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] west_data_o_wght,
		output logic west_enable_o_wght,
		
		
		//Interface with East - Devices
		//Source ports
//		input [DATA_WIDTH-1:0] east_data_i_wght,
		input east_enable_i_wght,
		
		//Destination ports
//		output logic [DATA_WIDTH-1:0] east_data_o_wght,
		output logic east_enable_o_wght,
		
	//IACT Router Ports
		input [3:0] router_mode_iact,
		
		//Interface with North
		//Source ports
		input [DATA_WIDTH-1:0] north_data_i_iact,
		input north_enable_i_iact,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] north_data_o_iact,
		output logic north_enable_o_iact,
		
		
		//Interface with South
		//Source ports
		input [DATA_WIDTH-1:0] south_data_i_iact,
		input south_enable_i_iact,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] south_data_o_iact,
		output logic south_enable_o_iact,
		
		
		//Interface with West
		//Source ports
		input [DATA_WIDTH-1:0] west_data_i_iact,
		input west_enable_i_iact,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] west_data_o_iact,
		output logic west_enable_o_iact,
		
		
		//Interface with East - Devices
		//Source ports
//		input [DATA_WIDTH-1:0] east_data_i_iact,
		input east_enable_i_iact,
		
		//Destination ports
//		output logic [DATA_WIDTH-1:0] east_data_o_iact,
		output logic east_enable_o_iact,
		
	
	//PSUM Router Ports
		input [3:0] router_mode_psum,
		
		//Interface with North
		//Source ports
		input [DATA_WIDTH-1:0] north_data_i_psum,
		input north_enable_i_psum,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] north_data_o_psum,
		output logic north_enable_o_psum,
		
		
		//Interface with South
		//Source ports
		input [DATA_WIDTH-1:0] south_data_i_psum,
		input south_enable_i_psum,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] south_data_o_psum,
		output logic south_enable_o_psum,
		
		
		//Interface with West
		//Source ports
		input [DATA_WIDTH-1:0] west_data_i_psum,
		input west_enable_i_psum,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] west_data_o_psum,
		output logic west_enable_o_psum,
		
		//Interface with East - Devices
		//Source ports
		input [DATA_WIDTH-1:0] east_data_i_psum,
		input east_enable_i_psum,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] east_data_o_psum,
		output logic east_enable_o_psum
	
	);
	
	
	//Logic for Direction
		enum logic [3:0] {ALL=0, NORTH=1, SOUTH=2, WEST=3, EAST=4,
						EASTNORTH=5, EASTSOUTH=6, EASTWEST=7,
						WESTNORTH=8, WESTSOUTH=9, WESTEAST=10} direction;
						
						
						
		//GLB cluster initialization
	GLB_cluster 
			#(	.DATA_BITWIDTH(DATA_BITWIDTH),
				.ADDR_BITWIDTH(ADDR_BITWIDTH),
				.NUM_GLB_IACT(NUM_GLB_IACT),
				.NUM_GLB_PSUM(NUM_GLB_PSUM),
				.NUM_GLB_WGHT(NUM_GLB_WGHT)
			)
	GLB_cluster_0
			(
				.clk(clk),   //TestBench/Controller
				.reset(reset),  //TestBench/Controller
				
				//Signals for reading from GLB
				.read_req_iact(read_req_iact),
				.read_req_psum(read_req_psum), //Read by testbench/controller
				.read_req_wght(read_req_wght),
				
			    .r_data_iact(router_cluster_0.east_data_i_iact),
			    .r_data_psum(r_data_psum), //Read by testbench/controller
				.r_data_wght(router_cluster_0.east_data_i_wght),
				
				.r_addr_iact(r_addr_iact),
			    .r_addr_psum(r_addr_psum), //testbench for reading final psums
				.r_addr_wght(r_addr_wght),

				
				//Signals for writing to GLB
			    .w_addr_iact(w_addr_iact), //testbench for writing
			    .w_addr_psum(w_addr_psum),
				.w_addr_wght(w_addr_wght), //testbench for writing
 
			    .w_data_iact(w_data_iact), //testbench for writing
			    .w_data_psum(router_cluster_0.east_data_o_psum),
				.w_data_wght(w_data_wght), //testbench for writing

				.write_en_iact(write_en_iact), //testbench for writing
				.write_en_psum(router_cluster_0.east_enable_o_psum),
				.write_en_wght(write_en_wght) //testbench for writing
			
			);
			
	
	
	
		router_cluster
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_cluster_0
		(
		
		//Ports for WGHT router
			.router_mode_wght(router_mode_wght), //TB*
			
			//Interface with North
			//Source ports
			.north_data_i_wght(north_data_i_wght),
			.north_enable_i_wght(north_enable_i_wght),
			
			//Destination ports
			.north_data_o_wght(north_data_o_wght),
			.north_enable_o_wght(north_enable_o_wght),
			
			
			//Interface with South
			//Source ports
			.south_data_i_wght(south_data_i_wght),
			.south_enable_i_wght(south_enable_i_wght),
			
			//Destination ports
			.south_data_o_wght(south_data_o_wght),
			.south_enable_o_wght(south_enable_o_wght),
			
			
			//Interface with West
			//Source ports
			.west_data_i_wght(west_data_i_wght), //GLB_cluster
			.west_enable_i_wght(west_enable_i_wght),
			
			//Destination ports
			.west_data_o_wght(pwest_data_o_wght),  //PE_cluster
			.west_enable_o_wght(west_enable_o_wght),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_wght(GLB_cluster_0.r_data_wght),
			.east_enable_i_wght(east_enable_i_wght),
	        
			//Destination ports
	        .east_data_o_wght(east_data_o_wght),
            .east_enable_o_wght(east_enable_o_wght),
			
		////////////////////////////////////////////
			
		//Ports for IACT router
			.router_mode_iact(router_mode_iact),  //TB*
			
			//Interface with North
			//Source ports
			.north_data_i_iact(north_data_i_iact),
			.north_enable_i_iact(north_enable_i_iact),
			
			//Destination ports
			.north_data_o_iact(north_data_o_iact),
			.north_enable_o_iact(north_enable_o_iact),
			
			
			//Interface with South
			//Source ports
			.south_data_i_iact(south_data_i_iact),
			.south_enable_i_iact(south_enable_i_iact),
			
			//Destination ports
			.south_data_o_iact(south_data_o_iact),
			.south_enable_o_iact(south_enable_o_iact),
			
			
			//Interface with West
			//Source ports
			.west_data_i_iact(west_data_i_iact),   //GLB_cluster
			.west_enable_i_iact(west_enable_i_iact),
			
			//Destination ports
			.west_data_o_iact(west_data_o_iact),  //PE_cluster
			.west_enable_o_iact(west_enable_o_iact),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_iact(GLB_cluster_0.r_data_iact),
			.east_enable_i_iact(east_enable_i_iact),
	        
			//Destination ports
	        .east_data_o_iact(pe_cluster_0.act_in),
            .east_enable_o_iact(east_enable_o_iact),
			
			
		////////////////////////////////////////////
			
		//Ports for PSUM router
			.router_mode_psum(router_mode_psum),
			
			//Interface with North
			//Source ports
			.north_data_i_psum(north_data_i_psum),
			.north_enable_i_psum(north_enable_i_psum),
			
			//Destination ports
			.north_data_o_psum(north_data_o_psum),
			.north_enable_o_psum(north_enable_o_psum),
			
			
			//Interface with South
			//Source ports
			.south_data_i_psum(south_data_i_psum),
			.south_enable_i_psum(south_enable_i_psum),
			
			//Destination ports
			.south_data_o_psum(south_data_o_psum),
			.south_enable_o_psum(south_enable_o_psum),
			
			
			//Interface with West
			//Source ports
			.west_data_i_psum(west_data_i_psum), //PE_cluster
			.west_enable_i_psum(west_enable_i_psum),
			
			//Destination ports
			.west_data_o_psum(west_data_o_psum), //GLB_cluster
			.west_enable_o_psum(west_enable_o_psum), //GLB_cluster
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_psum(east_data_i_psum),
			.east_enable_i_psum(east_enable_i_psum),
	        
			//Destination ports
	        .east_data_o_psum(GLB_cluster_0.w_data_psum),
            .east_enable_o_psum(GLB_cluster_0.write_en_psum)	
	);
	

	
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_0
    			(
					.clk(clk),
				    .reset(reset),
				    .act_in(router_cluster_0.east_data_o_iact),
				    .filt_in(router_cluster_0.east_data_o_wght),
					.load_en_wght(load_en_wght),
					.load_en_act(load_en_act),
					.start(start),
                    .pe_out(pe_out),
					.compute_done(compute_done),
					.load_done(load_done)
    			);

	
endmodule


================================================
FILE: rtl/HMNoC_cluster_west.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/10/2019 11:42:17 AM
// Design Name: 
// Module Name: HMNoC_cluster_new
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module HMNoC_cluster_west
	#(
		parameter DATA_BITWIDTH = 16,
		parameter ADDR_BITWIDTH = 10,
		
		parameter DATA_WIDTH = 16,
		parameter ADDR_WIDTH = 9,
		
		// GLB Cluster parameters. This TestBench uses only 1 of each
		parameter NUM_GLB_IACT = 1,
		parameter NUM_GLB_PSUM = 1,
		parameter NUM_GLB_WGHT = 1,
		
		parameter ADDR_BITWIDTH_GLB = 10,
		parameter ADDR_BITWIDTH_SPAD = 9,
		
		parameter NUM_ROUTER_PSUM = 1,
		parameter NUM_ROUTER_IACT = 1,
		parameter NUM_ROUTER_WGHT = 1,
				
		parameter int kernel_size = 3,
		parameter int act_size = 5,
		
		parameter int X_dim = 3,
		parameter int Y_dim = 3,
		
		parameter W_READ_ADDR = 0, 
		parameter A_READ_ADDR = 0,
		
		parameter W_LOAD_ADDR = 0,  
		parameter A_LOAD_ADDR = 0,
		
		parameter PSUM_READ_ADDR = 0,
		parameter PSUM_LOAD_ADDR = 0
	
    )
	(	
		input clk,
		input reset,
		
		//PE Cluster Interface
		input start,
		output load_done,
		
		input load_en_wght,
		input load_en_act,
		
        output [DATA_WIDTH-1:0] pe_out[X_dim-1:0],
		output compute_done,
		
		
		//GLB Cluster Interface

		input write_en_iact,
		input write_en_wght,
		
		input [DATA_WIDTH-1:0] w_data_iact,
		input [ADDR_WIDTH-1:0] w_addr_iact,
		
		input [DATA_WIDTH-1:0] w_data_wght,
		input [ADDR_WIDTH-1:0] w_addr_wght,
		
		input [ADDR_WIDTH-1:0] w_addr_psum,		
				
		output [DATA_WIDTH-1:0] r_data_psum,
		input [ADDR_WIDTH-1:0] r_addr_psum,
	
		input read_req_iact,
		input read_req_psum,
		input read_req_wght,
		
		input [ADDR_WIDTH-1:0] r_addr_iact,
		input [ADDR_WIDTH-1:0] r_addr_wght,
		

		
		//WGHT Router Ports
		input [3:0] router_mode_wght,
		
		//Interface with North
		//Source ports
		input [DATA_WIDTH-1:0] north_data_i_wght,
		input north_enable_i_wght,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] north_data_o_wght,
		output logic north_enable_o_wght,
		
		
		//Interface with South
		//Source ports
		input [DATA_WIDTH-1:0] south_data_i_wght,
		input south_enable_i_wght,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] south_data_o_wght,
		output logic south_enable_o_wght,
		
		
		//Interface with West
		//Source ports
//		input [DATA_WIDTH-1:0] west_data_i_wght,
		input west_enable_i_wght,
		
		//Destination ports
//		output logic [DATA_WIDTH-1:0] west_data_o_wght,
		output logic west_enable_o_wght,
		
		
		//Interface with East - Devices
		//Source ports
		input [DATA_WIDTH-1:0] east_data_i_wght,
		input east_enable_i_wght,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] east_data_o_wght,
		output logic east_enable_o_wght,
		
	//IACT Router Ports
		input [3:0] router_mode_iact,
		
		//Interface with North
		//Source ports
		input [DATA_WIDTH-1:0] north_data_i_iact,
		input north_enable_i_iact,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] north_data_o_iact,
		output logic north_enable_o_iact,
		
		
		//Interface with South
		//Source ports
		input [DATA_WIDTH-1:0] south_data_i_iact,
		input south_enable_i_iact,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] south_data_o_iact,
		output logic south_enable_o_iact,
		
		
		//Interface with West
		//Source ports
//		input [DATA_WIDTH-1:0] west_data_i_iact,
		input west_enable_i_iact,
		
		//Destination ports
//		output logic [DATA_WIDTH-1:0] west_data_o_iact,
		output logic west_enable_o_iact,
		
		
		//Interface with East - Devices
		//Source ports
		input [DATA_WIDTH-1:0] east_data_i_iact,
		input east_enable_i_iact,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] east_data_o_iact,
		output logic east_enable_o_iact,
		
	
	//PSUM Router Ports
		input [3:0] router_mode_psum,
		
		//Interface with North
		//Source ports
		input [DATA_WIDTH-1:0] north_data_i_psum,
		input north_enable_i_psum,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] north_data_o_psum,
		output logic north_enable_o_psum,
		
		
		//Interface with South
		//Source ports
		input [DATA_WIDTH-1:0] south_data_i_psum,
		input south_enable_i_psum,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] south_data_o_psum,
		output logic south_enable_o_psum,
		
		
		//Interface with West
		//Source ports
		input [DATA_WIDTH-1:0] west_data_i_psum,
		input west_enable_i_psum,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] west_data_o_psum,
		output logic west_enable_o_psum,
		
		//Interface with East - Devices
		//Source ports
		input [DATA_WIDTH-1:0] east_data_i_psum,
		input east_enable_i_psum,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] east_data_o_psum,
		output logic east_enable_o_psum
	
	);
	
	
	//Logic for Direction
		enum logic [3:0] {ALL=0, NORTH=1, SOUTH=2, WEST=3, EAST=4,
						EASTNORTH=5, EASTSOUTH=6, EASTWEST=7,
						WESTNORTH=8, WESTSOUTH=9, WESTEAST=10} direction;
						
						
						
		//GLB cluster initialization
	GLB_cluster 
			#(	.DATA_BITWIDTH(DATA_BITWIDTH),
				.ADDR_BITWIDTH(ADDR_BITWIDTH),
				.NUM_GLB_IACT(NUM_GLB_IACT),
				.NUM_GLB_PSUM(NUM_GLB_PSUM),
				.NUM_GLB_WGHT(NUM_GLB_WGHT)
			)
	GLB_cluster_0
			(
				.clk(clk),   //TestBench/Controller
				.reset(reset),  //TestBench/Controller
				
				//Signals for reading from GLB
				.read_req_iact(read_req_iact),
				.read_req_psum(read_req_psum), //Read by testbench/controller
				.read_req_wght(read_req_wght),
				
			    .r_data_iact(router_cluster_0.west_data_i_iact),
			    .r_data_psum(r_data_psum), //Read by testbench/controller
				.r_data_wght(router_cluster_0.west_data_i_wght),
				
				.r_addr_iact(r_addr_iact),
			    .r_addr_psum(r_addr_psum), //testbench for reading final psums
				.r_addr_wght(r_addr_wght),

				
				//Signals for writing to GLB
			    .w_addr_iact(w_addr_iact), //testbench for writing
			    .w_addr_psum(w_addr_psum),
				.w_addr_wght(w_addr_wght), //testbench for writing
 
			    .w_data_iact(w_data_iact), //testbench for writing
			    .w_data_psum(router_cluster_0.west_data_o_psum),
				.w_data_wght(w_data_wght), //testbench for writing

				.write_en_iact(write_en_iact), //testbench for writing
				.write_en_psum(router_cluster_0.west_enable_o_psum),
				.write_en_wght(write_en_wght) //testbench for writing
			
			);
			
	
	
	
		router_cluster
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_cluster_0
		(
		
		//Ports for WGHT router
			.router_mode_wght(router_mode_wght), //TB*
			
			//Interface with North
			//Source ports
			.north_data_i_wght(north_data_i_wght),
			.north_enable_i_wght(north_enable_i_wght),
			
			//Destination ports
			.north_data_o_wght(north_data_o_wght),
			.north_enable_o_wght(north_enable_o_wght),
			
			
			//Interface with South
			//Source ports
			.south_data_i_wght(south_data_i_wght),
			.south_enable_i_wght(south_enable_i_wght),
			
			//Destination ports
			.south_data_o_wght(south_data_o_wght),
			.south_enable_o_wght(south_enable_o_wght),
			
			
			//Interface with West
			//Source ports
			.west_data_i_wght(GLB_cluster_0.r_data_wght), //GLB_cluster
			.west_enable_i_wght(west_enable_i_wght),
			
			//Destination ports
			.west_data_o_wght(pe_cluster_0.filt_in),  //PE_cluster
			.west_enable_o_wght(west_enable_o_wght),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_wght(east_data_i_wght),
			.east_enable_i_wght(east_enable_i_wght),
	        
			//Destination ports
	        .east_data_o_wght(east_data_o_wght),
            .east_enable_o_wght(east_enable_o_wght),
			
		////////////////////////////////////////////
			
		//Ports for IACT router
			.router_mode_iact(router_mode_iact),  //TB*
			
			//Interface with North
			//Source ports
			.north_data_i_iact(north_data_i_iact),
			.north_enable_i_iact(north_enable_i_iact),
			
			//Destination ports
			.north_data_o_iact(north_data_o_iact),
			.north_enable_o_iact(north_enable_o_iact),
			
			
			//Interface with South
			//Source ports
			.south_data_i_iact(south_data_i_iact),
			.south_enable_i_iact(south_enable_i_iact),
			
			//Destination ports
			.south_data_o_iact(south_data_o_iact),
			.south_enable_o_iact(south_enable_o_iact),
			
			
			//Interface with West
			//Source ports
			.west_data_i_iact(GLB_cluster_0.r_data_iact),   //GLB_cluster
			.west_enable_i_iact(west_enable_i_iact),
			
			//Destination ports
			.west_data_o_iact(pe_cluster_0.act_in),  //PE_cluster
			.west_enable_o_iact(west_enable_o_iact),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_iact(east_data_i_iact),
			.east_enable_i_iact(east_enable_i_iact),
	        
			//Destination ports
	        .east_data_o_iact(east_data_o_iact),
            .east_enable_o_iact(east_enable_o_iact),
			
			
		////////////////////////////////////////////
			
		//Ports for PSUM router
			.router_mode_psum(router_mode_psum),
			
			//Interface with North
			//Source ports
			.north_data_i_psum(north_data_i_psum),
			.north_enable_i_psum(north_enable_i_psum),
			
			//Destination ports
			.north_data_o_psum(north_data_o_psum),
			.north_enable_o_psum(north_enable_o_psum),
			
			
			//Interface with South
			//Source ports
			.south_data_i_psum(south_data_i_psum),
			.south_enable_i_psum(south_enable_i_psum),
			
			//Destination ports
			.south_data_o_psum(south_data_o_psum),
			.south_enable_o_psum(south_enable_o_psum),
			
			
			//Interface with West
			//Source ports
			.west_data_i_psum(west_data_i_psum), //PE_cluster
			.west_enable_i_psum(west_enable_i_psum),
			
			//Destination ports
			.west_data_o_psum(GLB_cluster_0.w_data_psum), //GLB_cluster
			.west_enable_o_psum(GLB_cluster_0.write_en_psum), //GLB_cluster
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_psum(east_data_i_psum),
			.east_enable_i_psum(east_enable_i_psum),
	        
			//Destination ports
	        .east_data_o_psum(east_data_o_psum),
            .east_enable_o_psum(east_enable_o_psum)	
	);
	

	
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_0
    			(
					.clk(clk),
				    .reset(reset),
				    .act_in(router_cluster_0.west_data_o_iact),
				    .filt_in(router_cluster_0.west_data_o_wght),
					.load_en_wght(load_en_wght),
					.load_en_act(load_en_act),
					.start(start),
                    .pe_out(pe_out),
					.compute_done(compute_done),
					.load_done(load_done)
    			);

	
	
endmodule


================================================
FILE: rtl/HMNoC_top.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/10/2019 03:22:12 PM
// Design Name: 
// Module Name: HMNoC_top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module HMNoC_top
	#(
		parameter DATA_BITWIDTH = 16,
		parameter ADDR_BITWIDTH = 10,
		
		parameter DATA_WIDTH = 16,
		parameter ADDR_WIDTH = 9,
		
		// GLB Cluster parameters. This TestBench uses only 1 of each
		parameter NUM_GLB_IACT = 1,
		parameter NUM_GLB_PSUM = 1,
		parameter NUM_GLB_WGHT = 1,
		
		parameter ADDR_BITWIDTH_GLB = 10,
		parameter ADDR_BITWIDTH_SPAD = 9,
		
		parameter NUM_ROUTER_PSUM = 1,
		parameter NUM_ROUTER_IACT = 1,
		parameter NUM_ROUTER_WGHT = 1,
				
		parameter int kernel_size = 3,
		parameter int act_size = 5,
		
		parameter int X_dim = 3,
		parameter int Y_dim = 3,
		
		parameter W_READ_ADDR = 0, 
		parameter A_READ_ADDR = 0,
		
		parameter W_LOAD_ADDR = 0,  
		parameter A_LOAD_ADDR = 0,
		
		parameter PSUM_READ_ADDR = 0,
		parameter PSUM_LOAD_ADDR = 0

    )
	(
		input clk,
		input reset,
		
		//PE Cluster Interface
		input start,
		output load_done,
		
		input load_en_wght,
		input load_en_act,
		
        output [DATA_WIDTH-1:0] pe_out[X_dim-1:0],
		output compute_done,
		
		
		//GLB Cluster Interface

		input write_en_iact,
		input write_en_wght,
		
		input [DATA_WIDTH-1:0] w_data_iact,
		input [ADDR_WIDTH-1:0] w_addr_iact,
		
		input [DATA_WIDTH-1:0] w_data_wght,
		input [ADDR_WIDTH-1:0] w_addr_wght,
		
		input [ADDR_WIDTH-1:0] w_addr_psum,		
				
		output [DATA_WIDTH-1:0] r_data_psum,
		input [ADDR_WIDTH-1:0] r_addr_psum,
	
		input read_req_iact,
		input read_req_psum,
		input read_req_wght,
		
		input [ADDR_WIDTH-1:0] r_addr_iact,
		input [ADDR_WIDTH-1:0] r_addr_wght,
		

		
		//WGHT Router Ports
		input [3:0] router_mode_wght,
		input [3:0] router_mode_iact,
		input [3:0] router_mode_psum
	);
	
	
	//Instantiation of NORTH WEST Cluster
	HMNoC_cluster_west 
		#(
			.DATA_BITWIDTH(DATA_BITWIDTH),
			.ADDR_BITWIDTH(ADDR_BITWIDTH),
			
			.DATA_WIDTH(DATA_WIDTH),
			.ADDR_WIDTH(ADDR_WIDTH),
			
			.NUM_GLB_IACT(NUM_GLB_IACT),
			.NUM_GLB_PSUM(NUM_GLB_PSUM),
			.NUM_GLB_WGHT(NUM_GLB_WGHT),

			.kernel_size(kernel_size),
			.act_size(act_size),
			
			.X_dim(X_dim),
			.Y_dim(Y_dim)
		)
	HMNoC_cluster_west_0 ///NORTH WEST Cluster
		(
			.clk(clk),   //TestBench/Controller
			.reset(reset),  //TestBench/Controller
			
			//Signals for reading from GLB
			.read_req_iact(read_req_iact),
			.read_req_psum(read_req_psum), //Read by testbench/controller
			.read_req_wght(read_req_wght),
			
//			.r_data_iact(router_cluster_0.r_data_glb_iact),
			.r_data_psum(r_data_psum), //Read by testbench/controller
//			.r_data_wght(router_cluster_0.r_data_glb_wght),
			
			.r_addr_iact(r_addr_iact),
			.r_addr_psum(r_addr_psum), //testbench for reading final psums
			.r_addr_wght(r_addr_wght),

			//Signals for writing to GLB
			.w_addr_iact(w_addr_iact), //testbench for writing
			.w_addr_psum(w_addr_psum),
			.w_addr_wght(w_addr_wght), //testbench for writing

			.w_data_iact(w_data_iact), //testbench for writing
//			.w_data_psum(router_cluster_0.w_data_glb_psum),
			.w_data_wght(w_data_wght), //testbench for writing

			.write_en_iact(write_en_iact), //testbench for writing
//			.write_en_psum(router_cluster_0.write_en_glb_psum),
			.write_en_wght(write_en_wght), //testbench for writing
				
				
	
			//Ports for WGHT router
			.router_mode_wght(router_mode_wght), //TB*
			
			//Interface with North
			//Source ports
			.north_data_i_wght(),
			.north_enable_i_wght(),
			
			//Destination ports
			.north_data_o_wght(),
			.north_enable_o_wght(),
			
			
			//Interface with South
			//Source ports
			.south_data_i_wght(HMNoC_cluster_west_1.north_data_o_wght),
			.south_enable_i_wght(HMNoC_cluster_west_1.north_enable_o_wght),
			
			//Destination ports
			.south_data_o_wght(HMNoC_cluster_west_1.north_data_i_wght),
			.south_enable_o_wght(HMNoC_cluster_west_1.north_enable_i_wght),
			
			
			//Interface with West
			//Source ports
//			.west_data_i_wght(GLB_cluster_0.r_data_wght), //GLB_cluster
			.west_enable_i_wght(west_enable_i_wght),
			
			//Destination ports
//			.west_data_o_wght(pe_cluster_0.filt_in),  //PE_cluster
			.west_enable_o_wght(west_enable_o_wght),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_wght(HMNoC_cluster_east_0.west_data_o_wght),
			.east_enable_i_wght(HMNoC_cluster_east_0.west_enable_o_wght),
	        
			//Destination ports
	        .east_data_o_wght(HMNoC_cluster_east_0.west_data_i_wght),
            .east_enable_o_wght(HMNoC_cluster_east_0.west_enable_i_wght),
			
		////////////////////////////////////////////
			
		//Ports for IACT router
			.router_mode_iact(router_mode_iact),  //TB*
			
			//Interface with North
			//Source ports
			.north_data_i_iact(),
			.north_enable_i_iact(),
			
			//Destination ports
			.north_data_o_iact(),
			.north_enable_o_iact(),
			
			
			//Interface with South
			//Source ports
			.south_data_i_iact(HMNoC_cluster_west_1.north_data_o_iact),
			.south_enable_i_iact(HMNoC_cluster_west_1.north_enable_o_iact),
			
			//Destination ports
			.south_data_o_iact(HMNoC_cluster_west_1.north_data_i_iact),
			.south_enable_o_iact(HMNoC_cluster_west_1.north_enable_i_iact),
			
			
			//Interface with West
			//Source ports
//			.west_data_i_iact(GLB_cluster_0.r_data_iact),   //GLB_cluster
			.west_enable_i_iact(west_enable_i_iact),
			
			//Destination ports
//			.west_data_o_iact(pe_cluster_0.act_in),  //PE_cluster
			.west_enable_o_iact(west_enable_o_iact),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_iact(HMNoC_cluster_east_0.west_data_o_iact),
			.east_enable_i_iact(HMNoC_cluster_east_0.west_enable_o_iact),
	        
			//Destination ports
	        .east_data_o_iact(HMNoC_cluster_east_0.west_data_i_iact),
            .east_enable_o_iact(HMNoC_cluster_east_0.west_enable_i_iact),
			
			
		////////////////////////////////////////////
			
		//Ports for PSUM router
			.router_mode_psum(router_mode_psum),
			
			//Interface with North
			//Source ports
			.north_data_i_psum(),
			.north_enable_i_psum(),
			
			//Destination ports
			.north_data_o_psum(),
			.north_enable_o_psum(),
			
			
			//Interface with South
			//Source ports
			.south_data_i_psum(HMNoC_cluster_west_1.north_data_o_psum),
			.south_enable_i_psum(HMNoC_cluster_west_1.north_enable_o_psum),
			
			//Destination ports
			.south_data_o_psum(HMNoC_cluster_west_1.north_data_i_psum),
			.south_enable_o_psum(HMNoC_cluster_west_1.north_enable_i_psum),
			
			
			//Interface with West
			//Source ports
			.west_data_i_psum(west_data_i_psum), //PE_cluster
			.west_enable_i_psum(west_enable_i_psum),
			
			//Destination ports
//			.west_data_o_psum(GLB_cluster_0.w_data_psum), //GLB_cluster
//			.west_enable_o_psum(GLB_cluster_0.write_en_psum), //GLB_cluster
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_psum(HMNoC_cluster_east_0.west_data_o_psum),
			.east_enable_i_psum(HMNoC_cluster_east_0.west_enable_o_psum),
	        
			//Destination ports
	        .east_data_o_psum(HMNoC_cluster_east_0.west_data_i_psum),
            .east_enable_o_psum(HMNoC_cluster_east_0.west_enable_i_psum),
			
			
			
			//PE Cluster
			.load_en_wght(load_en_wght),
			.load_en_act(load_en_act),
			.start(start),
			.pe_out(pe_out),
			.compute_done(compute_done),
			.load_done(load_done)
		);
		
		
		
		
	//Instantiation of SOUTH WEST Cluster
	HMNoC_cluster_west 
		#(
			.DATA_BITWIDTH(DATA_BITWIDTH),
			.ADDR_BITWIDTH(ADDR_BITWIDTH),
			
			.DATA_WIDTH(DATA_WIDTH),
			.ADDR_WIDTH(ADDR_WIDTH),
			
			.NUM_GLB_IACT(NUM_GLB_IACT),
			.NUM_GLB_PSUM(NUM_GLB_PSUM),
			.NUM_GLB_WGHT(NUM_GLB_WGHT),

			.kernel_size(kernel_size),
			.act_size(act_size),
			
			.X_dim(X_dim),
			.Y_dim(Y_dim)
		)
	HMNoC_cluster_west_1 ///SOUTH WEST Cluster
		(
			.clk(clk),   //TestBench/Controller
			.reset(reset),  //TestBench/Controller
			
			//Signals for reading from GLB
			.read_req_iact(),
			.read_req_psum(), //Read by testbench/controller
			.read_req_wght(),
			
//			.r_data_iact(router_cluster_0.r_data_glb_iact),
			.r_data_psum(), //Read by testbench/controller
//			.r_data_wght(router_cluster_0.r_data_glb_wght),
			
			.r_addr_iact(),
			.r_addr_psum(), //testbench for reading final psums
			.r_addr_wght(),

			//Signals for writing to GLB
			.w_addr_iact(), //testbench for writing
			.w_addr_psum(),
			.w_addr_wght(), //testbench for writing

			.w_data_iact(), //testbench for writing
//			.w_data_psum(router_cluster_0.w_data_glb_psum),
			.w_data_wght(), //testbench for writing

			.write_en_iact(), //testbench for writing
//			.write_en_psum(router_cluster_0.write_en_glb_psum),
			.write_en_wght(), //testbench for writing
				
				
	
			//Ports for WGHT router
			.router_mode_wght(), //TB*
			
			//Interface with North
			//Source ports
			.north_data_i_wght(HMNoC_cluster_west_0.south_data_o_wght),
			.north_enable_i_wght(HMNoC_cluster_west_0.south_enable_o_wght),
			
			//Destination ports
			.north_data_o_wght(HMNoC_cluster_west_0.south_data_i_wght),
			.north_enable_o_wght(HMNoC_cluster_west_0.south_enable_i_wght),
			
			
			//Interface with South
			//Source ports
			.south_data_i_wght(),
			.south_enable_i_wght(),
			
			//Destination ports
			.south_data_o_wght(),
			.south_enable_o_wght(),
			
			
			//Interface with West
			//Source ports
//			.west_data_i_wght(GLB_cluster_0.r_data_wght), //GLB_cluster
			.west_enable_i_wght(),
			
			//Destination ports
//			.west_data_o_wght(pe_cluster_0.filt_in),  //PE_cluster
			.west_enable_o_wght(),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_wght(HMNoC_cluster_east_1.west_data_o_wght),
			.east_enable_i_wght(HMNoC_cluster_east_1.west_enable_o_wght),
	        
			//Destination ports
	        .east_data_o_wght(HMNoC_cluster_east_1.west_data_i_wght),
            .east_enable_o_wght(HMNoC_cluster_east_1.west_enable_i_wght),
			
		////////////////////////////////////////////
			
		//Ports for IACT router
			.router_mode_iact(),  //TB*
			
			//Interface with North
			//Source ports
			.north_data_i_iact(HMNoC_cluster_west_0.south_data_o_iact),
			.north_enable_i_iact(HMNoC_cluster_west_0.south_enable_o_iact),
			
			//Destination ports
			.north_data_o_iact(HMNoC_cluster_west_0.south_data_i_iact),
			.north_enable_o_iact(HMNoC_cluster_west_0.south_enable_i_iact),
			
			
			//Interface with South
			//Source ports
			.south_data_i_iact(),
			.south_enable_i_iact(),

			//Destination ports
			.south_data_o_iact(),
			.south_enable_o_iact(),


			//Interface with West
			//Source ports
//			.west_data_i_iact(GLB_cluster_0.r_data_iact),   //GLB_cluster
			.west_enable_i_iact(),
			
			//Destination ports
//			.west_data_o_iact(pe_cluster_0.act_in),  //PE_cluster
			.west_enable_o_iact(),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_iact(),
			.east_enable_i_iact(),
	        
			//Destination ports
	        .east_data_o_iact(),
            .east_enable_o_iact(),
			
			
		////////////////////////////////////////////
			
		//Ports for PSUM router
			.router_mode_psum(),
			
			//Interface with North
			//Source ports
			.north_data_i_psum(HMNoC_cluster_west_0.south_data_o_psum),
			.north_enable_i_psum(HMNoC_cluster_west_0.south_enable_o_psum),
			
			//Destination ports
			.north_data_o_psum(HMNoC_cluster_west_0.south_data_i_psum),
			.north_enable_o_psum(HMNoC_cluster_west_0.south_enable_i_psum),
			
			
			//Interface with South
			//Source ports
			.south_data_i_psum(),
			.south_enable_i_psum(),
			
			//Destination ports
			.south_data_o_psum(),
			.south_enable_o_psum(),
			
			
			//Interface with West
			//Source ports
			.west_data_i_psum(), //PE_cluster
			.west_enable_i_psum(),
			
			//Destination ports
//			.west_data_o_psum(GLB_cluster_0.w_data_psum), //GLB_cluster
//			.west_enable_o_psum(GLB_cluster_0.write_en_psum), //GLB_cluster
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_psum(HMNoC_cluster_east_1.west_data_o_psum),
			.east_enable_i_psum(HMNoC_cluster_east_1.west_enable_o_psum),
	        
			//Destination ports
	        .east_data_o_psum(HMNoC_cluster_east_1.west_data_i_psum),
            .east_enable_o_psum(HMNoC_cluster_east_1.west_enable_i_psum),
			
			
			
			//PE Cluster
			.load_en_wght(),
			.load_en_act(),
			.start(),
			.pe_out(),
			.compute_done(),
			.load_done()
		);
		
		
		
	//Instantiation of NORTH_EAST Cluster
	HMNoC_cluster_east 
		#(
			.DATA_BITWIDTH(DATA_BITWIDTH),
			.ADDR_BITWIDTH(ADDR_BITWIDTH),
			
			.DATA_WIDTH(DATA_WIDTH),
			.ADDR_WIDTH(ADDR_WIDTH),
			
			.NUM_GLB_IACT(NUM_GLB_IACT),
			.NUM_GLB_PSUM(NUM_GLB_PSUM),
			.NUM_GLB_WGHT(NUM_GLB_WGHT),

			.kernel_size(kernel_size),
			.act_size(act_size),
			
			.X_dim(X_dim),
			.Y_dim(Y_dim)
		)
	HMNoC_cluster_east_0 
		(
			.clk(clk),   //TestBench/Controller
			.reset(reset),  //TestBench/Controller
			
			//Signals for reading from GLB
			.read_req_iact(),
			.read_req_psum(), //Read by testbench/controller
			.read_req_wght(),
			
//			.r_data_iact(router_cluster_0.r_data_glb_iact),
			.r_data_psum(), //Read by testbench/controller
//			.r_data_wght(router_cluster_0.r_data_glb_wght),
			
			.r_addr_iact(),
			.r_addr_psum(), //testbench for reading final psums
			.r_addr_wght(),

			//Signals for writing to GLB
			.w_addr_iact(), //testbench for writing
			.w_addr_psum(),
			.w_addr_wght(), //testbench for writing

			.w_data_iact(), //testbench for writing
//			.w_data_psum(router_cluster_0.w_data_glb_psum),
			.w_data_wght(), //testbench for writing

			.write_en_iact(), //testbench for writing
//			.write_en_psum(router_cluster_0.write_en_glb_psum),
			.write_en_wght(), //testbench for writing
				
				
	
			//Ports for WGHT router
			.router_mode_wght(), //TB*
			
			//Interface with North
			//Source ports
			.north_data_i_wght(),
			.north_enable_i_wght(),
			
			//Destination ports
			.north_data_o_wght(),
			.north_enable_o_wght(),
			
			
			//Interface with South
			//Source ports
			.south_data_i_wght(HMNoC_cluster_east_1.north_data_o_wght),
			.south_enable_i_wght(HMNoC_cluster_east_1.north_enable_o_wght),
			
			//Destination ports
			.south_data_o_wght(HMNoC_cluster_east_1.north_data_i_wght),
			.south_enable_o_wght(HMNoC_cluster_east_1.north_enable_i_wght),
			
			
			//Interface with West
			//Source ports
			.west_data_i_wght(HMNoC_cluster_west_0.east_data_o_wght), //GLB_cluster
			.west_enable_i_wght(HMNoC_cluster_west_0.east_enable_o_wght),
			
			//Destination ports
			.west_data_o_wght(HMNoC_cluster_west_0.east_data_i_wght),  //PE_cluster
			.west_enable_o_wght(HMNoC_cluster_west_0.east_enable_i_wght),
			
			
			//Interface with East - Devices
			//Source ports
//			.east_data_i_wght(east_data_i_wght),
			.east_enable_i_wght(),
	        
			//Destination ports
//	        .east_data_o_wght(east_data_o_wght),
            .east_enable_o_wght(),
			
		////////////////////////////////////////////
			
		//Ports for IACT router
			.router_mode_iact(),  //TB*
			
			//Interface with North
			//Source ports
			.north_data_i_iact(),
			.north_enable_i_iact(),
			
			//Destination ports
			.north_data_o_iact(),
			.north_enable_o_iact(),
			
			
			//Interface with South
			//Source ports
			.south_data_i_iact(HMNoC_cluster_east_1.north_data_o_iact),
			.south_enable_i_iact(HMNoC_cluster_east_1.north_enable_o_iact),
			
			//Destination ports
			.south_data_o_iact(HMNoC_cluster_east_1.north_data_i_iact),
			.south_enable_o_iact(HMNoC_cluster_east_1.north_enable_i_iact),
			
			
			//Interface with West
			//Source ports
			.west_data_i_iact(HMNoC_cluster_west_0.east_data_o_iact),   //GLB_cluster
			.west_enable_i_iact(HMNoC_cluster_west_0.east_enable_o_iact),
			
			//Destination ports
			.west_data_o_iact(HMNoC_cluster_west_0.east_data_i_iact),  //PE_cluster
			.west_enable_o_iact(HMNoC_cluster_west_0.east_enable_i_iact),
			
			
			//Interface with East - Devices
			//Source ports
//			.east_data_i_iact(east_data_i_iact),
			.east_enable_i_iact(),
	        
			//Destination ports
//	        .east_data_o_iact(east_data_o_iact),
            .east_enable_o_iact(),
		

		////////////////////////////////////////////
			
		//Ports for PSUM router
			.router_mode_psum(),
			
			//Interface with North
			//Source ports
			.north_data_i_psum(),
			.north_enable_i_psum(),
			
			//Destination ports
			.north_data_o_psum(),
			.north_enable_o_psum(),
			
			
			//Interface with South
			//Source ports
			.south_data_i_psum(HMNoC_cluster_east_1.north_data_i_psum),
			.south_enable_i_psum(HMNoC_cluster_east_1.north_enable_i_psum),
			
			//Destination ports
			.south_data_o_psum(HMNoC_cluster_east_1.north_data_o_psum),
			.south_enable_o_psum(HMNoC_cluster_east_1.north_enable_o_psum),
			
			
			//Interface with West
			//Source ports
			.west_data_i_psum(HMNoC_cluster_west_0.east_data_o_psum), //PE_cluster
			.west_enable_i_psum(HMNoC_cluster_west_0.east_enable_o_psum),
			
			//Destination ports
			.west_data_o_psum(HMNoC_cluster_west_0.east_data_i_psum), //GLB_cluster
			.west_enable_o_psum(HMNoC_cluster_west_0.east_enable_i_psum), //GLB_cluster
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_psum(),
			.east_enable_i_psum(),
	        
			//Destination ports
//	        .east_data_o_psum(east_data_o_psum),
//            .east_enable_o_psum(east_enable_o_psum),
			
			
			
			//PE Cluster
			.load_en_wght(),
			.load_en_act(),
			.start(),
			.pe_out(),
			.compute_done(),
			.load_done()
		);
		
	
		//Instantiation of SOUTH_EAST Cluster
	HMNoC_cluster_east 
		#(
			.DATA_BITWIDTH(DATA_BITWIDTH),
			.ADDR_BITWIDTH(ADDR_BITWIDTH),
			
			.DATA_WIDTH(DATA_WIDTH),
			.ADDR_WIDTH(ADDR_WIDTH),
			
			.NUM_GLB_IACT(NUM_GLB_IACT),
			.NUM_GLB_PSUM(NUM_GLB_PSUM),
			.NUM_GLB_WGHT(NUM_GLB_WGHT),

			.kernel_size(kernel_size),
			.act_size(act_size),
			
			.X_dim(X_dim),
			.Y_dim(Y_dim)
		)
	HMNoC_cluster_east_1 
		(
			.clk(clk),   //TestBench/Controller
			.reset(reset),  //TestBench/Controller
			
			//Signals for reading from GLB
			.read_req_iact(),
			.read_req_psum(), //Read by testbench/controller
			.read_req_wght(),
			
//			.r_data_iact(router_cluster_0.r_data_glb_iact),
			.r_data_psum(), //Read by testbench/controller
//			.r_data_wght(router_cluster_0.r_data_glb_wght),
			
			.r_addr_iact(),
			.r_addr_psum(), //testbench for reading final psums
			.r_addr_wght(),

			//Signals for writing to GLB
			.w_addr_iact(), //testbench for writing
			.w_addr_psum(),
			.w_addr_wght(), //testbench for writing

			.w_data_iact(), //testbench for writing
//			.w_data_psum(router_cluster_0.w_data_glb_psum),
			.w_data_wght(), //testbench for writing

			.write_en_iact(), //testbench for writing
//			.write_en_psum(router_cluster_0.write_en_glb_psum),
			.write_en_wght(), //testbench for writing
				
				
	
			//Ports for WGHT router
			.router_mode_wght(), //TB*
			
			//Interface with North
			//Source ports
			.north_data_i_wght(HMNoC_cluster_east_0.south_data_o_wght),
			.north_enable_i_wght(HMNoC_cluster_east_0.south_enable_o_wght),
			
			//Destination ports
			.north_data_o_wght(HMNoC_cluster_east_0.south_data_i_wght),
			.north_enable_o_wght(HMNoC_cluster_east_0.south_enable_i_wght),
			
			
			//Interface with South
			//Source ports
			.south_data_i_wght(),
			.south_enable_i_wght(),
			
			//Destination ports
			.south_data_o_wght(),
			.south_enable_o_wght(),
			
			
			//Interface with West
			//Source ports
			.west_data_i_wght(HMNoC_cluster_west_1.east_data_o_wght), //GLB_cluster
			.west_enable_i_wght(HMNoC_cluster_west_1.east_enable_o_wght),
			
			//Destination ports
			.west_data_o_wght(HMNoC_cluster_west_1.east_data_i_wght),  //PE_cluster
			.west_enable_o_wght(HMNoC_cluster_west_1.east_enable_i_wght),
			
			
			//Interface with East - Devices
			//Source ports
//			.east_data_i_wght(east_data_i_wght),
			.east_enable_i_wght(),
	        
			//Destination ports
//	        .east_data_o_wght(east_data_o_wght),
            .east_enable_o_wght(),
			
		////////////////////////////////////////////
			
		//Ports for IACT router
			.router_mode_iact(router_mode_iact),  //TB*
			
			//Interface with North
			//Source ports
			.north_data_i_iact(HMNoC_cluster_east_0.south_data_o_iact),
			.north_enable_i_iact(HMNoC_cluster_east_0.south_enable_o_iact),
			
			//Destination ports
			.north_data_o_iact(HMNoC_cluster_east_0.south_data_i_iact),
			.north_enable_o_iact(HMNoC_cluster_east_0.south_enable_i_iact),
			
			
			//Interface with South
			//Source ports
			.south_data_i_iact(),
			.south_enable_i_iact(),
			
			//Destination ports
			.south_data_o_iact(),
			.south_enable_o_iact(),
			
			
			//Interface with West
			//Source ports
			.west_data_i_iact(HMNoC_cluster_west_1.east_data_o_iact),   //GLB_cluster
			.west_enable_i_iact(HMNoC_cluster_west_1.east_enable_o_iact),
			
			//Destination ports
			.west_data_o_iact(HMNoC_cluster_west_1.east_data_i_iact),  //PE_cluster
			.west_enable_o_iact(HMNoC_cluster_west_1.east_enable_i_iact),
			
			
			//Interface with East - Devices
			//Source ports
//			.east_data_i_iact(east_data_i_iact),
			.east_enable_i_iact(),
	        
			//Destination ports
//	        .east_data_o_iact(east_data_o_iact),
            .east_enable_o_iact(),
			
			
		////////////////////////////////////////////
			
		//Ports for PSUM router
			.router_mode_psum(),
			
			//Interface with North
			//Source ports
			.north_data_i_psum(HMNoC_cluster_east_0.south_data_o_psum),
			.north_enable_i_psum(HMNoC_cluster_east_0.south_enable_o_psum),
			
			//Destination ports
			.north_data_o_psum(HMNoC_cluster_east_0.south_data_i_psum),
			.north_enable_o_psum(HMNoC_cluster_east_0.south_enable_i_psum),
			
			
			//Interface with South
			//Source ports
			.south_data_i_psum(),
			.south_enable_i_psum(),
			
			//Destination ports
			.south_data_o_psum(),
			.south_enable_o_psum(),
			
			
			//Interface with West
			//Source ports
			.west_data_i_psum(HMNoC_cluster_west_1.east_data_o_psum), //PE_cluster
			.west_enable_i_psum(HMNoC_cluster_west_1.east_enable_o_psum),
			
			//Destination ports
			.west_data_o_psum(HMNoC_cluster_west_1.east_data_i_psum), //GLB_cluster
			.west_enable_o_psum(HMNoC_cluster_west_1.east_enable_i_psum), //GLB_cluster
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_psum(),
			.east_enable_i_psum(),
	        
			//Destination ports
//	        .east_data_o_psum(east_data_o_psum),
//            .east_enable_o_psum(east_enable_o_psum),
			
			
			
			//PE Cluster
			.load_en_wght(),
			.load_en_act(),
			.start(),
			.pe_out(),
			.compute_done(),
			.load_done()
		);
		
		
endmodule


================================================
FILE: rtl/MAC.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 11/27/2019 09:39:19 AM
// Design Name: 
// Module Name: MAC
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module MAC #( parameter IN_BITWIDTH = 16,
			  parameter OUT_BITWIDTH = 2*IN_BITWIDTH )
			( input [IN_BITWIDTH-1 : 0] a_in,
			  input [IN_BITWIDTH-1 : 0] w_in,
			  input [IN_BITWIDTH-1 : 0] sum_in,
			  input en, clk,
			  output logic [OUT_BITWIDTH-1 : 0] out
			);
	
	logic [OUT_BITWIDTH-1:0] mult_out;
	
	always@(posedge clk) begin
		if(en) begin
			mult_out = a_in * w_in;
			out <= mult_out + sum_in;
		end
	end
	
endmodule


================================================
FILE: rtl/PE.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 11/27/2019 07:20:21 AM
// Design Name: 
// Module Name: PE
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module PE #( parameter DATA_WIDTH = 16,
			 parameter ADDR_WIDTH = 9,
			 
			 parameter W_READ_ADDR = 0,     //Weights READ address
			 parameter A_READ_ADDR = 100,   //Activations READ address
			 
			 parameter W_LOAD_ADDR = 0,     //Weights LOAD address
			 parameter A_LOAD_ADDR = 100,   //Activations LOAD address
			 
			 parameter PSUM_ADDR = 500,
			 
			 parameter int kernel_size = 3,
			 parameter int act_size = 5 )
			 
		   ( input clk, reset,
			 input [DATA_WIDTH-1:0] act_in,
			 input [DATA_WIDTH-1:0] filt_in,
//			 input load_en,
			 input load_en_wght, load_en_act,
			 input start,
			 output logic [DATA_WIDTH-1:0] pe_out,
			 output logic compute_done,
			 output logic load_done
    );
	

	
	enum logic [2:0] {IDLE=3'b000, READ_W=3'b001, READ_A=3'b010, COMPUTE=3'b011,
					  WRITE=3'b100, LOAD_W=3'b101, LOAD_A=3'b110} state;
	
// ScratchPad Instantiation
	logic read_en, write_en;
	logic [ADDR_WIDTH-1:0] w_addr, r_addr;
	logic [DATA_WIDTH-1:0] r_data, w_data;
	
	SPad spad_pe0 ( .clk(clk), .reset(reset), 
					.read_req(read_en),
					.write_en(write_en), 
					.r_addr(r_addr), 
					.w_addr(w_addr),
					.w_data(w_data),
					.r_data(r_data)
					);
					

	logic [DATA_WIDTH-1:0] psum_reg;
	logic [DATA_WIDTH-1:0] sum_in;
	logic sum_in_mux_sel;
	
	logic [DATA_WIDTH-1:0] act_in_reg;
	logic [DATA_WIDTH-1:0] filt_in_reg;
	
	logic mac_en;
	//MAC Instantiation
	
	MAC  #( .IN_BITWIDTH(DATA_WIDTH),
			     .OUT_BITWIDTH(DATA_WIDTH) )
	mac_0
				( .a_in(act_in_reg),
				  .w_in(filt_in_reg),
				  .sum_in(sum_in),
				  .en(mac_en),
				  .clk(clk),
				  .out(psum_reg)
				);
			
	mux2 #( .WIDTH(DATA_WIDTH) ) mux2_0 ( .a_in(psum_reg), 
										.b_in(16'b0), 
										.sel(sum_in_mux_sel), 
										.out(sum_in) 
										);
	
	
	logic [7:0] filt_count;
	logic [2:0] iter;
	
	// FSM for PE
	always@(posedge clk) begin
//		$display("State: %s", state.name());
		if(reset) begin
			//Initialize registers
			filt_count <= 0;
			sum_in_mux_sel = 0;
			
			//Initialize scratchpad inputs
			w_addr <= W_READ_ADDR;
			r_addr <= W_READ_ADDR;
			w_data <= 0;
			write_en <= 0;
			read_en <= 0;
			compute_done <= 0;
			mac_en <= 0;
			iter <= 0;
			load_done <= 0;
			state <= IDLE;
		end
		else begin
			case(state)
				IDLE:begin
					if(start) begin
						if(iter == (act_size-kernel_size+1) ) begin
							iter <= 0;
							state <= IDLE;
						end else begin
							r_addr <= A_READ_ADDR + iter*act_size;
							filt_count <= 0;
							sum_in_mux_sel = 0;
							read_en <= 1;
							state <= READ_W;
						end
					end else begin
/* 						if(load_en) begin
							
							w_addr <= W_LOAD_ADDR;  //***Loading of weights starts at index 0***
							
							w_data <= filt_in;
							write_en <= 1;
							filt_count <= 0;
							state <= LOAD_W; */
						if(load_en_wght) begin
							w_addr <= W_LOAD_ADDR;  //***Loading of weights starts at index 0***
							w_data <= filt_in;
							write_en <= 1;
							filt_count <= 0;
							state <= LOAD_W;
						end else if(load_en_act) begin
							write_en <= 1;
							w_addr <= A_LOAD_ADDR; // *** Loading of activations starts at 100 ***
							w_data <= act_in;
							state <= LOAD_A;
						end else begin
							load_done <= 0;
							write_en <= 0;
							compute_done <= 0;
							state <= IDLE;
						end
					end
				end
				
				READ_W:begin
					filt_in_reg <= r_data;
					read_en <= 1;
					filt_count <= filt_count + 1;
					
//					$display("Weight read: %d from address: %d", r_data, r_addr);
//					$display("Read Enable: %d", read_en);
					
					state <= READ_A;
				end
				
				READ_A:begin
//					$display("Act read: %d from address: %d", r_data, r_addr);
//					$display("Read Enable: %d", read_en);
					act_in_reg <= r_data;
					read_en <= 1;
					r_addr <= W_READ_ADDR + filt_count;
					mac_en <= 1;
					state <= COMPUTE;
				end
					
				COMPUTE:begin
//				$display("Weight in reg: %d  |  Act in reg: %d", filt_in_reg, act_in_reg);
//				$display("MAC out: %d", psum_reg);
				
					mac_en <= 0;
					if(filt_count == kernel_size) begin
						act_in_reg <= r_data;
						read_en <= 0;
						w_addr <= PSUM_ADDR + iter;
						write_en <= 1;
						state <= WRITE;
					end else begin
						if(filt_count == 0) begin
							sum_in_mux_sel = 0;
						end else begin
							sum_in_mux_sel = 1;	
						end
						r_addr <= A_READ_ADDR + filt_count + iter*act_size;
						state <= READ_W;
					end
				end
				
				WRITE:begin
					w_data <= psum_reg;
					r_addr <= W_READ_ADDR;
					read_en <= 1;
					iter <= iter + 1;
					compute_done <= 1;
					state <= IDLE;
				end
				
				LOAD_W:begin
//				$display("Weight write: %d to address: %d", filt_in, w_addr);
//				$display("Write Enable: %d", write_en);					
/* 					if(filt_count == (kernel_size**2-1)) begin
						
						w_addr <= A_LOAD_ADDR; // *** Loading of activations starts at 100 ***
						
						w_data <= act_in;
						filt_count <= 0;
						state <= LOAD_A; */
					if(filt_count == (kernel_size**2-1)) begin
						filt_count <= 0;
						load_done <= 1;
						state <= IDLE;
					end else begin
						w_data <= filt_in;
						w_addr <= w_addr + 1;
						filt_count <= filt_count + 1;
						state <= LOAD_W;
					end
				end
				
				LOAD_A:begin
//				$display("Act write: %d to address: %d", act_in,  w_addr);
//				$display("Write Enable: %d", write_en);			
					if(filt_count == (act_size**2-1)) begin
						write_en <= 0;
						read_en <= 1;
						r_addr <= W_READ_ADDR;
						load_done <= 1;
						state <= IDLE;
					end else begin
						w_data <= act_in;
						w_addr <= w_addr + 1;
						filt_count <= filt_count + 1;
						state <= LOAD_A;
					end
				end
			endcase
		end
	end
						
	assign pe_out = psum_reg;

endmodule


================================================
FILE: rtl/PE_cluster.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 11/29/2019 09:11:06 PM
// Design Name: 
// Module Name: PE_cluster
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module PE_cluster #(parameter DATA_WIDTH = 16,
					parameter ADDR_WIDTH = 9,
					
					parameter int X_dim = 5,
					parameter int Y_dim = 3,
   
					parameter int kernel_size = 3,
					parameter int act_size = 5,
					
					parameter W_READ_ADDR = 0,  
					parameter A_READ_ADDR = 100,
					
					parameter W_LOAD_ADDR = 0,  
					parameter A_LOAD_ADDR = 100,
					
					parameter PSUM_ADDR = 500
					)
					( 
					input clk, reset,
					input [DATA_WIDTH-1:0] act_in,
					input [DATA_WIDTH-1:0] filt_in,
//					input load_en, 
					input load_en_wght, load_en_act,
					input start,
					output logic [DATA_WIDTH-1:0] pe_out[0 : X_dim-1],
					output logic compute_done,
					output logic load_done
					
		//extra 
		//			output logic [DATA_WIDTH-1:0] psum_out[0 : X_dim*Y_dim-1]
					);
		
		logic [DATA_WIDTH-1:0] psum_out[0 : X_dim*Y_dim-1];
		
		logic cluster_done[0 : X_dim*Y_dim-1];
		logic cluster_load_done[0 : X_dim*Y_dim-1];
		
		generate
		genvar i;
		for(i=0; i<X_dim; i++) 
			begin:gen_X
				genvar j;
				for(j=0; j<Y_dim; j++)
					begin:gen_Y
					
						PE #( 	.DATA_WIDTH(DATA_WIDTH),
								.ADDR_WIDTH(ADDR_WIDTH),
								.kernel_size(kernel_size),
								.act_size(act_size),
								.W_READ_ADDR(W_READ_ADDR + kernel_size*j),  
								.A_READ_ADDR(A_READ_ADDR + act_size*j + i),
								.W_LOAD_ADDR(W_LOAD_ADDR),  
								.A_LOAD_ADDR(A_LOAD_ADDR),
								.PSUM_ADDR(PSUM_ADDR)
							)
						pe (	
								.clk(clk),
								.reset(reset),
								.act_in(act_in),
								.filt_in(filt_in),
//								.load_en(load_en),
								.load_en_wght(load_en_wght),
								.load_en_act(load_en_act),
								.start(start),
								.pe_out(psum_out[i*Y_dim+j]),
								.compute_done(cluster_done[i*Y_dim+j]),
								.load_done(cluster_load_done[i*Y_dim+j])
							);
					
					end
			end
		endgenerate
		
		
/*  		virtual class psum_adder_class #(parameter X_dim, parameter Y_dim, parameter DATA_WIDTH);
			static function logic [DATA_WIDTH-1 : 0] psum_adder 
				(
					input logic [DATA_WIDTH-1:0] psum_out[X_dim*Y_dim-1 : 0]
				);
				begin
					psum_adder = {(DATA_WIDTH){1'b0}};
					for(int i=0; i<Y_dim; i++) begin
						psum_adder = psum_adder + psum_out[Y_dim*X_dim+i];
					end
				end
			endfunction
		endclass  */
					
		


 			function logic [DATA_WIDTH-1 : 0] psum_adder 
				(
					input logic [DATA_WIDTH-1:0] psum_out[0 : X_dim*Y_dim-1],
					input logic [3:0] X_dim,
					input logic [3:0] Y_dim
				);
				begin
					psum_adder = {(DATA_WIDTH){1'b0}};
					for(int i=0; i<Y_dim; i++) begin
						psum_adder = psum_adder + psum_out[Y_dim*X_dim+i];
					end
				end
			endfunction
				
				
				
/* 		always@(posedge clk) begin
			if(reset) begin
				for(int i=0; i<X_dim; i++) begin
					pe_out[i] <= 0;
				end
			end else begin
				for(int i=0; i<X_dim; i++) begin
					pe_out[i] <= psum_adder_class#
									(.X_dim(i),
									 .Y_dim(Y_dim),
									 .DATA_WIDTH(DATA_WIDTH)
									)
									::psum_adder(psum_out);
				end
			end
			
		end */
		
		
		// Add partial sums and register at pe_out
		always@(posedge clk) begin
			if(reset) begin
				for(int i=0; i<X_dim; i++) begin
					pe_out[i] <= 0;
				end
			end else begin
				for(int i=0; i<X_dim; i++) begin
					pe_out[i] <= psum_adder(psum_out,i,Y_dim);
				end
			end
			
		end
		
		
		assign compute_done = cluster_done[0];
		assign load_done = cluster_load_done[0];
		
	//	assign pe_out[X_dim-1:0] = psum_out[X_dim*Y_dim-1 : 0]
			  
endmodule
				   
				   
				   
				   
				   
				   
				   
				   
				   
				   

================================================
FILE: rtl/SPad.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 11/27/2019 10:35:28 AM
// Design Name: 
// Module Name: SPad
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module SPad #( parameter DATA_BITWIDTH = 16,
			 parameter ADDR_BITWIDTH = 9 )
		   ( input clk,
			 input reset,
			 input read_req,
			 input write_en,
			 input [ADDR_BITWIDTH-1 : 0] r_addr,
			 input [ADDR_BITWIDTH-1 : 0] w_addr,
			 input [DATA_BITWIDTH-1 : 0] w_data,
			 output logic [DATA_BITWIDTH-1 : 0] r_data
    );
	
	logic [DATA_BITWIDTH-1 : 0] mem [0 : (1 << ADDR_BITWIDTH) - 1]; 
		// default - 512(2^9) 16-bit memory. Total size = 1kB 
	logic [DATA_BITWIDTH-1 : 0] data;
	
	always@(posedge clk)
		begin : READ
			if(reset)
				data <= 0;
			else
			begin
				if(read_req) begin
					data <= mem[r_addr];
//					$display("Read Address to SPad:%d",r_addr);
				end else begin
					data <= 10101;
				end
			end
		end
	
	assign r_data = data;
	
	always@(posedge clk)
		begin : WRITE
		
    		
 			$display("\t\t\t\t\t Current Status:\n \
				 \t mem[0]:%d", mem[0],
				" | mem[1]:%d", mem[1],
				" | mem[2]:%d", mem[2],
				" | mem[3]:%d", mem[3],
				" | mem[4]:%d", mem[4],
				" | mem[5]:%d", mem[5],
				" | mem[8]:%d", mem[8],
				" | mem[24]:%d\n", mem[24],
				" \t\t\t\t\t mem[100]:%d", mem[100],
				" | mem[101]:%d", mem[101],
				" | mem[102]:%d", mem[102],
				" | mem[103]:%d", mem[103],
				" | mem[104]:%d", mem[104],
				" | mem[105]:%d\n", mem[105],
				" | mem[124]:%d\n", mem[124],
				" | mem[148]:%d\n", mem[148],
				" \t\t\t\t\t psum:%d", mem[500],
				" | psum:%d", mem[501],
				" | psum:%d", mem[502],
				" | psum:%d", mem[503],
				" | psum:%d", mem[504]
				); 
				 
			if(write_en && !reset) begin
				mem[w_addr] <= w_data;
			end
		end
	
endmodule


================================================
FILE: rtl/circular_buffer.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/08/2019 04:33:37 PM
// Design Name: 
// Module Name: circular_buffer
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module circular_buffer#(
	parameter BUFFER_SIZE = 8,
	parameter DATA_SIZE = 16
    )
	( 
	input clk,
	input reset,
	
	input [DATA_SIZE-1:0] data_i,
	input read_en_i,
	input write_en_i,
	
	output [DATA_SIZE-1:0] data_o,
	output logic full_o,
	output logic empty_o
//	output logic on_off_o
	);
	
	localparam [31:0] POINTER_SIZE = $clog2(BUFFER_SIZE);
	
	logic [DATA_SIZE-1:0] mem[BUFFER_SIZE-1:0];
	
	logic [POINTER_SIZE-1:0] read_ptr;
	logic [POINTER_SIZE-1:0] write_ptr;
	
	logic [POINTER_SIZE-1:0] read_ptr_next;
	logic [POINTER_SIZE-1:0] write_ptr_next;
	
	logic full_next;
	logic empty_next;
	logic on_off_next;
	
	logic [POINTER_SIZE:0] num_flits;
	logic [POINTER_SIZE:0] num_flits_next;	
	
	
	always_ff@(posedge clk) begin
		if(reset) begin
			read_ptr <= 0;
			write_ptr <= 0;
			full_o <= 0;
			empty_o <= 0;
//			on_off_o <= 0;
		end else begin
			read_ptr <= read_ptr_next;
			write_ptr <= write_ptr_next;
			
			full_o <= full_next;
			empty_o <= empty_next;
			
//			on_off_o <= on_off_next;
			
			if((!read_en_i & write_en_i & !full_o) | (read_en_i & write_en_i))
				mem[write_ptr] <= data_i;
		end
	end
	
	
	always_comb begin
		data_o = mem[read_ptr];
		unique
		if(read_en_i & !write_en_i & !empty_o)
		begin: read_not_empty
			read_ptr_next = incr_ptr(read_ptr);
			write_ptr_next = write_ptr;
			full_next = 0;
			update_empty();
			num_flits_next = num_flits - 1;
		end
		
		else if(!read_en_i & write_en_i & !full_o)
		begin:write_not_full
			read_ptr_next = read_ptr;
			write_ptr_next = incr_ptr(write_ptr);
			update_full();
			num_flits_next = num_flits + 1;
		end
		
		else if(read_en_i & write_en_i & !empty_o)
		begin:read_write_not_empty
			read_ptr_next = incr_ptr(read_ptr);
			write_ptr_next = incr_ptr(write_ptr);
			full_next = full_o;
			empty_next = empty_o;
			num_flits_next = num_flits;
		end
		else
		begin:idle
			read_ptr_next = read_ptr;
			write_ptr_next = write_ptr;
			full_next = full_o;
			empty_next = empty_o;
			num_flits_next = num_flits;
		end
		
//		begin:update_
		
	end
	
	function logic [POINTER_SIZE-1:0] incr_ptr (
							input logic [POINTER_SIZE-1:0] ptr );
		if(ptr == BUFFER_SIZE-1)
			incr_ptr = 0;
		else
			incr_ptr = ptr + 1;
	endfunction
	
	function void update_empty();
		if(read_ptr_next == write_ptr)
			empty_next = 1;
		else
			empty_next = 0;
	endfunction
	
	function void update_full();
		if(write_ptr_next == read_ptr)
			full_next = 1;
		else
			full_next = 0;
	endfunction
	
endmodule


================================================
FILE: rtl/glb_iact.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/01/2019 12:56:24 PM
// Design Name: 
// Module Name: glb_iact
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module glb_iact #( parameter DATA_BITWIDTH = 16,
			 parameter ADDR_BITWIDTH = 10 )
		   ( input clk,
			 input reset,
			 input read_req,
			 input write_en,
			 input [ADDR_BITWIDTH-1 : 0] r_addr,
			 input [ADDR_BITWIDTH-1 : 0] w_addr,
			 input [DATA_BITWIDTH-1 : 0] w_data,
			 output logic [DATA_BITWIDTH-1 : 0] r_data
    );
	
	logic [DATA_BITWIDTH-1 : 0] mem [0 : (1 << ADDR_BITWIDTH) - 1]; 
		// default - 1024(2^10) 16-bit memory. Total size = 2kB 
	logic [DATA_BITWIDTH-1 : 0] data;
	
	always@(posedge clk)
		begin : READ
			if(reset)
				data = 0;
			else
			begin
				if(read_req) begin
					data = mem[r_addr];
//					$display("Read Address to SPad:%d",r_addr);
				end else begin
					data = 10101; //Random default value to verify model
				end
			end
		end
	
	assign r_data = data;
	
	always@(posedge clk)
		begin : WRITE	
			if(write_en && !reset) begin
				mem[w_addr] = w_data;
			end
		end
	
endmodule



================================================
FILE: rtl/glb_psum.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/01/2019 01:13:40 PM
// Design Name: 
// Module Name: glb_psum
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module glb_psum #( parameter DATA_BITWIDTH = 16,
			 parameter ADDR_BITWIDTH = 10 )
		   ( input clk,
			 input reset,
			 input read_req,
			 input write_en,
			 input [ADDR_BITWIDTH-1 : 0] r_addr,
			 input [ADDR_BITWIDTH-1 : 0] w_addr,
			 input [DATA_BITWIDTH-1 : 0] w_data,
			 output logic [DATA_BITWIDTH-1 : 0] r_data
    );
	
	logic [DATA_BITWIDTH-1 : 0] mem [0 : (1 << ADDR_BITWIDTH) - 1]; 
		// default - 1024(2^10) 16-bit memory. Total size = 2kB 
	logic [DATA_BITWIDTH-1 : 0] data;
	
	always@(posedge clk)
		begin : READ
			if(reset)
				data = 0;
			else
			begin
				if(read_req) begin
					data = mem[r_addr];
//					$display("Read Address to SPad:%d",r_addr);
				end else begin
					data = 10101; //Random default value to verify model
				end
			end
		end
	
	assign r_data = data;
	
	always@(posedge clk)
		begin : WRITE
		
/* 				$display("\t\t\t\t\t Current Status in glb_psum:\n \
				 \t psum[0]:%d", mem[0],
				" | psum[1]:%d", mem[1],
				" | psum[2]:%d", mem[2],
				" | psum[3]:%d", mem[3],
				" | psum[4]:%d", mem[4],
				" | psum[5]:%d", mem[5],
				" | psum[6]:%d", mem[6],
				" | psum[7]:%d", mem[7],
				" | psum[8]:%d", mem[8],
				" | psum[9]:%d", mem[9]
				);
			
			$display("WriteEn: %d\n",write_en);
			$display("Write Data: %d\n",w_data);
			$display("Write Addr: %d\n\n\n",w_addr); */
			
			if(write_en && !reset) begin
				mem[w_addr] = w_data;
			end
		end
	
endmodule



================================================
FILE: rtl/glb_weight.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/01/2019 04:07:04 PM
// Design Name: 
// Module Name: glb_weight
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module glb_weight #( parameter DATA_BITWIDTH = 16,
			 parameter ADDR_BITWIDTH = 10 )
		   ( input clk,
			 input reset,
			 input read_req,
			 input write_en,
			 input [ADDR_BITWIDTH-1 : 0] r_addr,
			 input [ADDR_BITWIDTH-1 : 0] w_addr,
			 input [DATA_BITWIDTH-1 : 0] w_data,
			 output logic [DATA_BITWIDTH-1 : 0] r_data
    );
	
	logic [DATA_BITWIDTH-1 : 0] mem [0 : (1 << ADDR_BITWIDTH) - 1]; 
		// default - 1024(2^10) 16-bit memory. Total size = 2kB 
	logic [DATA_BITWIDTH-1 : 0] data;
	
	always@(posedge clk)
		begin : READ
			if(reset)
				data = 0;
			else
			begin
				if(read_req) begin
					data = mem[r_addr];
//					$display("Read Address to SPad:%d",r_addr);
				end else begin
					data = 10101; //Random default value to verify model
				end
			end
		end
	
	assign r_data = data;
	
	always@(posedge clk)
		begin : WRITE	
			if(write_en && !reset) begin
				mem[w_addr] = w_data;
			end
		end
	
endmodule


================================================
FILE: rtl/lookup_mux4.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/09/2019 07:41:07 AM
// Design Name: 
// Module Name: lookup_mux4
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module lookup_mux4
	(
	input [3:0] in,
	output logic [1:0] out
    );
	
	always_comb begin
		unique if(in == 4'b0000)
			out = 0;
		else if(in == 4'b0010)
			out = 1;
		else if(in == 4'b0100)
			out = 2;
		else if(in == 4'b1000)
			out = 3;
	end
endmodule


================================================
FILE: rtl/misc/FA.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 11/27/2019 07:43:21 AM
// Design Name: 
// Module Name: FA
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module FA( input A_in,
			input B_in,
			input C_in,
			output logic S_out,
			output logic C_out
    );
	
	assign {C_out, S_out} = A_in + B_in + C_in;
	
endmodule


================================================
FILE: rtl/misc/HA.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 11/27/2019 07:30:57 AM
// Design Name: 
// Module Name: HA
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module HA( input A_in,
		   input B_in,
		   output logic S_out,
		   output logic C_out
    );
	
	assign {C_out,S_out} = A_in + B_in;
	
endmodule


================================================
FILE: rtl/misc/circular_buffer.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/08/2019 04:33:37 PM
// Design Name: 
// Module Name: circular_buffer
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module circular_buffer#(
	parameter BUFFER_SIZE = 8,
	parameter DATA_SIZE = 16
    )
	( 
	input clk,
	input reset,
	
	input [DATA_SIZE-1:0] data_i,
	input read_en_i,
	input write_en_i,
	
	output [DATA_SIZE-1:0] data_o,
	output logic full_o,
	output logic empty_o
//	output logic on_off_o
	);
	
	localparam [31:0] POINTER_SIZE = $clog2(BUFFER_SIZE);
	
	logic [DATA_SIZE-1:0] mem[BUFFER_SIZE-1:0];
	
	logic [POINTER_SIZE-1:0] read_ptr;
	logic [POINTER_SIZE-1:0] write_ptr;
	
	logic [POINTER_SIZE-1:0] read_ptr_next;
	logic [POINTER_SIZE-1:0] write_ptr_next;
	
	logic full_next;
	logic empty_next;
	logic on_off_next;
	
	logic [POINTER_SIZE:0] num_flits;
	logic [POINTER_SIZE:0] num_flits_next;	
	
	
	always_ff@(posedge clk) begin
		if(reset) begin
			read_ptr <= 0;
			write_ptr <= 0;
			full_o <= 0;
			empty_o <= 0;
//			on_off_o <= 0;
		end else begin
			read_ptr <= read_ptr_next;
			write_ptr <= write_ptr_next;
			
			full_o <= full_next;
			empty_o <= empty_next;
			
//			on_off_o <= on_off_next;
			
			if((!read_en_i & write_en_i & !full_o) | (read_en_i & write_en_i))
				mem[write_ptr] <= data_i;
		end
	end
	
	
	always_comb begin
		data_o = mem[read_ptr];
		unique
		if(read_en_i & !write_en_i & !empty_o)
		begin: read_not_empty
			read_ptr_next = incr_ptr(read_ptr);
			write_ptr_next = write_ptr;
			full_next = 0;
			update_empty();
			num_flits_next = num_flits - 1;
		end
		
		else if(!read_en_i & write_en_i & !full_o)
		begin:write_not_full
			read_ptr_next = read_ptr;
			write_ptr_next = incr_ptr(write_ptr);
			update_full();
			num_flits_next = num_flits + 1;
		end
		
		else if(read_en_i & write_en_i & !empty_o)
		begin:read_write_not_empty
			read_ptr_next = incr_ptr(read_ptr);
			write_ptr_next = incr_ptr(write_ptr);
			full_next = full_o;
			empty_next = empty_o;
			num_flits_next = num_flits;
		end
		else
		begin:idle
			read_ptr_next = read_ptr;
			write_ptr_next = write_ptr;
			full_next = full_o;
			empty_next = empty_o;
			num_flits_next = num_flits;
		end
		
//		begin:update_
		
	end
	
	function logic [POINTER_SIZE-1:0] incr_ptr (
							input logic [POINTER_SIZE-1:0] ptr );
		if(ptr == BUFFER_SIZE-1)
			incr_ptr = 0;
		else
			incr_ptr = ptr + 1;
	endfunction
	
	function void update_empty();
		if(read_ptr_next == write_ptr)
			empty_next = 1;
		else
			empty_next = 0;
	endfunction
	
	function void update_full();
		if(write_ptr_next == read_ptr)
			full_next = 1;
		else
			full_next = 0;
	endfunction
	
endmodule


================================================
FILE: rtl/misc/mux_4x1.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/09/2019 07:22:05 AM
// Design Name: 
// Module Name: mux_4x1
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module mux_4x1 #(parameter DATA_WIDTH=16)
	(
		input [DATA_WIDTH-1:0] a,
		input [DATA_WIDTH-1:0] b,
		input [DATA_WIDTH-1:0] c,
		input [DATA_WIDTH-1:0] d,
		
		input [1:0] sel,
		
		output logic [DATA_WIDTH-1:0] out
    );
	
		assign out = sel[1] ? (sel[0] ? d : c) : (sel[0] ? b : a) ;
		
endmodule


================================================
FILE: rtl/misc/switch.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/09/2019 08:10:01 AM
// Design Name: 
// Module Name: switch
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module switch
	#(
		parameter DATA_WIDTH = 16
	)
	(
		input [DATA_WIDTH-1:0] a,
		input [DATA_WIDTH-1:0] b,
		input [DATA_WIDTH-1:0] c,
		input [DATA_WIDTH-1:0] d,
		input [3:0] sel,

		output logic [DATA_WIDTH-1:0] out
	);
	
		logic [1:0] s;
		
		lookup_mux4 lookup_0 ( .in(sel), .out(s) );
		mux_4x1 mux_0 ( .sel(s), .a(a), .b(b), .c(c), .d(d), .out(out) );
	
endmodule


================================================
FILE: rtl/mux2.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 11/28/2019 01:14:05 AM
// Design Name: 
// Module Name: mux_2_1
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module mux2 #( parameter WIDTH = 16)
	(
    input [WIDTH-1:0] a_in,
    input [WIDTH-1:0] b_in,
    input sel,
    output [WIDTH-1:0] out
    );
	
	assign out = sel ? a_in : b_in;
	
endmodule


================================================
FILE: rtl/mux_4x1.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/09/2019 07:22:05 AM
// Design Name: 
// Module Name: mux_4x1
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module mux_4x1 #(parameter DATA_WIDTH=16)
	(
		input [DATA_WIDTH-1:0] a,
		input [DATA_WIDTH-1:0] b,
		input [DATA_WIDTH-1:0] c,
		input [DATA_WIDTH-1:0] d,
		
		input [1:0] sel,
		
		output logic [DATA_WIDTH-1:0] out
    );
	
		assign out = sel[1] ? (sel[0] ? d : c) : (sel[0] ? b : a) ;
		
endmodule


================================================
FILE: rtl/phase_1/GLB_cluster.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/01/2019 01:18:56 PM
// Design Name: 
// Module Name: GLB_cluster
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module GLB_cluster 
			#( 
			parameter DATA_BITWIDTH = 16,
			parameter ADDR_BITWIDTH = 10,
			parameter NUM_GLB_IACT = 1,
			parameter NUM_GLB_PSUM = 1,
			parameter NUM_GLB_WGHT = 1
			)
		   ( input clk,
			 input reset,
			 
			 input read_req_iact, 
			 input read_req_psum,
			 input read_req_wght,
			 
			 input write_en_iact, 
			 input write_en_psum,
			 input write_en_wght,
			 
			 input [ADDR_BITWIDTH-1 : 0] r_addr_iact,
			 input [ADDR_BITWIDTH-1 : 0] r_addr_psum,
			 input [ADDR_BITWIDTH-1 : 0] r_addr_wght,
			 
			 input [ADDR_BITWIDTH-1 : 0] w_addr_iact,
			 input [ADDR_BITWIDTH-1 : 0] w_addr_psum,
			 input [ADDR_BITWIDTH-1 : 0] w_addr_wght,
			 
			 input [DATA_BITWIDTH-1 : 0] w_data_iact,
			 input [DATA_BITWIDTH-1 : 0] w_data_psum,
			 input [DATA_BITWIDTH-1 : 0] w_data_wght,
			 
			 output logic [DATA_BITWIDTH-1 : 0] r_data_iact,
			 output logic [DATA_BITWIDTH-1 : 0] r_data_psum,
			 output logic [DATA_BITWIDTH-1 : 0] r_data_wght
			);
			
			//Instantiate iact global buffer
			generate
			genvar i;
			for(i=0; i<NUM_GLB_IACT; i++) 
				begin:glb_iact_gen
					glb_iact	#( .ADDR_BITWIDTH(ADDR_BITWIDTH),
								 .DATA_BITWIDTH(DATA_BITWIDTH)
								)
					glb_iact_inst ( .clk(clk), 
									.reset(reset),
									.read_req(read_req_iact),
									.write_en(write_en_iact), 
									.r_addr(r_addr_iact), 
									.w_data(w_data_iact),
									.r_data(r_data_iact), 
									.w_addr(w_addr_iact)
									);
				end
			endgenerate
			
			
			//Instantiate psum global buffer
			generate
			genvar j;
			for(j=0; j<NUM_GLB_PSUM; j++) 
				begin:glb_psum_gen
					glb_psum #( .ADDR_BITWIDTH(ADDR_BITWIDTH),
							.DATA_BITWIDTH(DATA_BITWIDTH)
							) 
					glb_psum_inst ( .clk(clk), 
									.reset(reset), 
									.read_req(read_req_psum),
									.write_en(write_en_psum), 
									.r_addr(r_addr_psum), 
									.w_data(w_data_psum),
									.r_data(r_data_psum), 
									.w_addr(w_addr_psum)
									);
				end
			endgenerate
	
			//Instantiate weight global buffer
			generate
			genvar k;
			for(k=0; k<NUM_GLB_WGHT; k++) 
				begin:glb_wght_gen
					glb_weight #( .ADDR_BITWIDTH(ADDR_BITWIDTH),
							.DATA_BITWIDTH(DATA_BITWIDTH)
							) 
					glb_weight_inst ( .clk(clk), 
									.reset(reset), 
									.read_req(read_req_wght),
									.write_en(write_en_wght), 
									.r_addr(r_addr_wght), 
									.w_data(w_data_wght),
									.r_data(r_data_wght), 
									.w_addr(w_addr_wght)
									);
				end
			endgenerate
endmodule


================================================
FILE: rtl/phase_1/HMNoC_cluster.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/04/2019 06:59:19 AM
// Design Name: 
// Module Name: HMNoC_cluster
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module HMNoC_cluster#(
	
	parameter DATA_BITWIDTH = 16,
	parameter ADDR_BITWIDTH = 10,
	
	parameter DATA_WIDTH = 16,
    parameter ADDR_WIDTH = 9,
	
	// GLB Cluster parameters. This TestBench uses only 1 of each
    parameter NUM_GLB_IACT = 1,
    parameter NUM_GLB_PSUM = 1,
	parameter NUM_GLB_WGHT = 1,
	
	parameter ADDR_BITWIDTH_GLB = 10,
	parameter ADDR_BITWIDTH_SPAD = 9,
	
	parameter NUM_ROUTER_PSUM = 1,
	parameter NUM_ROUTER_IACT = 1,
	parameter NUM_ROUTER_WGHT = 1,
			
	parameter int kernel_size = 3,
    parameter int act_size = 5,
	
	parameter int X_dim = 3,
    parameter int Y_dim = 3,
	
	parameter W_READ_ADDR = 0, 
    parameter A_READ_ADDR = 0,
    
    parameter W_LOAD_ADDR = 0,  
    parameter A_LOAD_ADDR = 0,
	
	parameter PSUM_READ_ADDR = 0,
	parameter PSUM_LOAD_ADDR = 0
	)
	(
    input clk,
    input reset,
	
	input start,

	output load_done,
	
	//logic for GLB cluster
	input read_req_psum,

    input write_en_iact,
	input write_en_wght,

	input load_spad_ctrl_wght,
	input load_spad_ctrl_iact,
		
    input [ADDR_BITWIDTH-1 : 0] r_addr_psum,
	output logic [DATA_BITWIDTH-1 : 0] r_data_psum,
	
    input [ADDR_BITWIDTH-1 : 0] w_addr_iact,
    input [ADDR_BITWIDTH-1 : 0] w_addr_psum,
	input [ADDR_BITWIDTH-1 : 0] w_addr_wght,

    input [DATA_BITWIDTH-1 : 0] w_data_iact,
    input [DATA_BITWIDTH-1 : 0] w_data_psum,
	input [DATA_BITWIDTH-1 : 0] w_data_wght
	
	);
//	logic [DATA_WIDTH-1:0] act_in;
//    logic [DATA_WIDTH-1:0] filt_in;

//	logic load_en_wght, load_en_act;
  
    
//		logic [DATA_BITWIDTH-1 : 0] r_data_spad_psum[0:kernel_size-1];	
	
	
	//GLB cluster initialization
	GLB_cluster 
			#(	.DATA_BITWIDTH(DATA_BITWIDTH),
				.ADDR_BITWIDTH(ADDR_BITWIDTH),
				.NUM_GLB_IACT(NUM_GLB_IACT),
				.NUM_GLB_PSUM(NUM_GLB_PSUM),
				.NUM_GLB_WGHT(NUM_GLB_WGHT)
			)
	GLB_cluster_0
			(
				.clk(clk),   //TestBench/Controller
				.reset(reset),  //TestBench/Controller
				
				//Signals for reading from GLB
				.read_req_iact(router_cluster_0.read_req_glb_iact),
				.read_req_psum(read_req_psum), //Read by testbench/controller
				.read_req_wght(router_cluster_0.read_req_glb_wght),
				
			    .r_data_iact(router_cluster_0.r_data_glb_iact),
			    .r_data_psum(r_data_psum), //Read by testbench/controller
				.r_data_wght(router_cluster_0.r_data_glb_wght),
				
				.r_addr_iact(router_cluster_0.r_addr_glb_iact),
			    .r_addr_psum(r_addr_psum), //testbench for reading final psums
				.r_addr_wght(router_cluster_0.r_addr_glb_wght),

				
				//Signals for writing to GLB
			    .w_addr_iact(w_addr_iact), //testbench for writing
			    .w_addr_psum(router_cluster_0.w_addr_glb_psum),
				.w_addr_wght(w_addr_wght), //testbench for writing
 
			    .w_data_iact(w_data_iact), //testbench for writing
			    .w_data_psum(router_cluster_0.w_data_glb_psum),
				.w_data_wght(w_data_wght), //testbench for writing

				.write_en_iact(write_en_iact), //testbench for writing
				.write_en_psum(router_cluster_0.write_en_glb_psum),
				.write_en_wght(write_en_wght) //testbench for writing
			
			);

			
	
	//Router Cluster Instantiation
	router_cluster#(.DATA_BITWIDTH(DATA_BITWIDTH),
	                .ADDR_BITWIDTH_GLB(ADDR_BITWIDTH_GLB),
	                .ADDR_BITWIDTH_SPAD(ADDR_BITWIDTH_SPAD),

	                .kernel_size(kernel_size),
	                .act_size(act_size),

	                .NUM_ROUTER_PSUM(NUM_ROUTER_PSUM),
	                .NUM_ROUTER_IACT(NUM_ROUTER_IACT),
	                .NUM_ROUTER_WGHT(NUM_ROUTER_WGHT),

	                .A_READ_ADDR(A_READ_ADDR), 
	                .A_LOAD_ADDR(A_LOAD_ADDR),

	                .W_READ_ADDR(W_READ_ADDR), 
	                .W_LOAD_ADDR(W_LOAD_ADDR),

	                .PSUM_READ_ADDR(PSUM_READ_ADDR),
	                .PSUM_LOAD_ADDR(PSUM_LOAD_ADDR)
					)
	router_cluster_0
					(
					.clk(clk),  //TestBench/Controller
					.reset(reset),  //TestBench/Controller
					
					//Signals for activation router
					.r_data_glb_iact(GLB_cluster_0.r_data_iact),
					.r_addr_glb_iact(GLB_cluster_0.r_addr_iact),
					.read_req_glb_iact(GLB_cluster_0.read_req_iact),

					.w_data_spad_iact(pe_cluster_0.act_in),
					.load_en_spad_iact(pe_cluster_0.load_en_act),
					
					.load_spad_ctrl_iact(load_spad_ctrl_iact), //TestBench/Controller
					
					
					//Signals for weight router
					.r_data_glb_wght(GLB_cluster_0.r_data_wght),
					.r_addr_glb_wght(GLB_cluster_0.r_addr_wght),
					.read_req_glb_wght(GLB_cluster_0.read_req_wght),
					
					.w_data_spad_wght(pe_cluster_0.filt_in),
					.load_en_spad_wght(pe_cluster_0.load_en_wght),

					.load_spad_ctrl_wght(load_spad_ctrl_wght), //TestBench/Controller

					
					//Signals for psum router
					.r_data_spad_psum(pe_cluster_0.pe_out),
					
					.w_addr_glb_psum(GLB_cluster_0.w_addr_psum),
					.write_en_glb_psum(GLB_cluster_0.write_en_psum),
					.w_data_glb_psum(GLB_cluster_0.w_data_psum),
					
					.write_psum_ctrl(pe_cluster_0.compute_done) //Connected to compute done of PE
					);
	

//Declarations for PE_cluster
				

	
//PE_cluster Instantiation
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_0
    			(
					.clk(clk), 	   //TestBench/Controller
				    .reset(reset), //TestBench/Controller
					.start(start), //TestBench/Controller
					
				    .act_in(router_cluster_0.w_data_spad_iact),
					.filt_in(router_cluster_0.w_data_spad_wght),
					
					.load_en_wght(router_cluster_0.load_en_spad_wght),
					.load_en_act(router_cluster_0.load_en_spad_iact),
					
                    .pe_out(router_cluster_0.r_data_spad_psum),
					.compute_done(router_cluster_0.write_psum_ctrl),
					.load_done(load_done) //TestBench/Controller
    			);
				

endmodule


================================================
FILE: rtl/phase_1/PE.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 11/27/2019 07:20:21 AM
// Design Name: 
// Module Name: PE
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module PE #( parameter DATA_WIDTH = 16,
			 parameter ADDR_WIDTH = 9,
			 
			 parameter W_READ_ADDR = 0,     //Weights READ address
			 parameter A_READ_ADDR = 100,   //Activations READ address
			 
			 parameter W_LOAD_ADDR = 0,     //Weights LOAD address
			 parameter A_LOAD_ADDR = 100,   //Activations LOAD address
			 
			 parameter PSUM_ADDR = 500,
			 
			 parameter int kernel_size = 3,
			 parameter int act_size = 5 )
			 
		   ( input clk, reset,
			 input [DATA_WIDTH-1:0] act_in,
			 input [DATA_WIDTH-1:0] filt_in,
//			 input load_en,
			 input load_en_wght, load_en_act,
			 input start,
			 output logic [DATA_WIDTH-1:0] pe_out,
			 output logic compute_done,
			 output logic load_done
    );
	

	
	enum logic [2:0] {IDLE=3'b000, READ_W=3'b001, READ_A=3'b010, COMPUTE=3'b011,
					  WRITE=3'b100, LOAD_W=3'b101, LOAD_A=3'b110} state;
	
// ScratchPad Instantiation
	logic read_en, write_en;
	logic [ADDR_WIDTH-1:0] w_addr, r_addr;
	logic [DATA_WIDTH-1:0] r_data, w_data;
	
	SPad spad_pe0 ( .clk(clk), .reset(reset), 
					.read_req(read_en),
					.write_en(write_en), 
					.r_addr(r_addr), 
					.w_addr(w_addr),
					.w_data(w_data),
					.r_data(r_data)
					);
					

	logic [DATA_WIDTH-1:0] psum_reg;
	logic [DATA_WIDTH-1:0] sum_in;
	logic sum_in_mux_sel;
	
	logic [DATA_WIDTH-1:0] act_in_reg;
	logic [DATA_WIDTH-1:0] filt_in_reg;
	
	logic mac_en;
	//MAC Instantiation
	
	MAC  #( .IN_BITWIDTH(DATA_WIDTH),
			     .OUT_BITWIDTH(DATA_WIDTH) )
	mac_0
				( .a_in(act_in_reg),
				  .w_in(filt_in_reg),
				  .sum_in(sum_in),
				  .en(mac_en),
				  .clk(clk),
				  .out(psum_reg)
				);
			
	mux2 #( .WIDTH(DATA_WIDTH) ) mux2_0 ( .a_in(psum_reg), 
										.b_in(16'b0), 
										.sel(sum_in_mux_sel), 
										.out(sum_in) 
										);
	
	
	logic [7:0] filt_count;
	logic [2:0] iter;
	
	// FSM for PE
	always@(posedge clk) begin
//		$display("State: %s", state.name());
		if(reset) begin
			//Initialize registers
			filt_count <= 0;
			sum_in_mux_sel = 0;
			
			//Initialize scratchpad inputs
			w_addr <= W_READ_ADDR;
			r_addr <= W_READ_ADDR;
			w_data <= 0;
			write_en <= 0;
			read_en <= 0;
			compute_done <= 0;
			mac_en <= 0;
			iter <= 0;
			load_done <= 0;
			state <= IDLE;
		end
		else begin
			case(state)
				IDLE:begin
					if(start) begin
						if(iter == (act_size-kernel_size+1) ) begin
							iter <= 0;
							state <= IDLE;
						end else begin
							r_addr <= A_READ_ADDR + iter*act_size;
							filt_count <= 0;
							sum_in_mux_sel = 0;
							read_en <= 1;
							state <= READ_W;
						end
					end else begin
/* 						if(load_en) begin
							
							w_addr <= W_LOAD_ADDR;  //***Loading of weights starts at index 0***
							
							w_data <= filt_in;
							write_en <= 1;
							filt_count <= 0;
							state <= LOAD_W; */
						if(load_en_wght) begin
							w_addr <= W_LOAD_ADDR;  //***Loading of weights starts at index 0***
							w_data <= filt_in;
							write_en <= 1;
							filt_count <= 0;
							state <= LOAD_W;
						end else if(load_en_act) begin
							write_en <= 1;
							w_addr <= A_LOAD_ADDR; // *** Loading of activations starts at 100 ***
							w_data <= act_in;
							state <= LOAD_A;
						end else begin
							load_done <= 0;
							write_en <= 0;
							compute_done <= 0;
							state <= IDLE;
						end
					end
				end
				
				READ_W:begin
					filt_in_reg <= r_data;
					read_en <= 1;
					filt_count <= filt_count + 1;
					
//					$display("Weight read: %d from address: %d", r_data, r_addr);
//					$display("Read Enable: %d", read_en);
					
					state <= READ_A;
				end
				
				READ_A:begin
//					$display("Act read: %d from address: %d", r_data, r_addr);
//					$display("Read Enable: %d", read_en);
					act_in_reg <= r_data;
					read_en <= 1;
					r_addr <= W_READ_ADDR + filt_count;
					mac_en <= 1;
					state <= COMPUTE;
				end
					
				COMPUTE:begin
//				$display("Weight in reg: %d  |  Act in reg: %d", filt_in_reg, act_in_reg);
//				$display("MAC out: %d", psum_reg);
				
					mac_en <= 0;
					if(filt_count == kernel_size) begin
						act_in_reg <= r_data;
						read_en <= 0;
						w_addr <= PSUM_ADDR + iter;
						write_en <= 1;
						state <= WRITE;
					end else begin
						if(filt_count == 0) begin
							sum_in_mux_sel = 0;
						end else begin
							sum_in_mux_sel = 1;	
						end
						r_addr <= A_READ_ADDR + filt_count + iter*act_size;
						state <= READ_W;
					end
				end
				
				WRITE:begin
					w_data <= psum_reg;
					r_addr <= W_READ_ADDR;
					read_en <= 1;
					iter <= iter + 1;
					compute_done <= 1;
					state <= IDLE;
				end
				
				LOAD_W:begin
//				$display("Weight write: %d to address: %d", filt_in, w_addr);
//				$display("Write Enable: %d", write_en);					
/* 					if(filt_count == (kernel_size**2-1)) begin
						
						w_addr <= A_LOAD_ADDR; // *** Loading of activations starts at 100 ***
						
						w_data <= act_in;
						filt_count <= 0;
						state <= LOAD_A; */
					if(filt_count == (kernel_size**2-1)) begin
						filt_count <= 0;
						load_done <= 1;
						state <= IDLE;
					end else begin
						w_data <= filt_in;
						w_addr <= w_addr + 1;
						filt_count <= filt_count + 1;
						state <= LOAD_W;
					end
				end
				
				LOAD_A:begin
//				$display("Act write: %d to address: %d", act_in,  w_addr);
//				$display("Write Enable: %d", write_en);			
					if(filt_count == (act_size**2-1)) begin
						write_en <= 0;
						read_en <= 1;
						r_addr <= W_READ_ADDR;
						load_done <= 1;
						state <= IDLE;
					end else begin
						w_data <= act_in;
						w_addr <= w_addr + 1;
						filt_count <= filt_count + 1;
						state <= LOAD_A;
					end
				end
			endcase
		end
	end
						
	assign pe_out = psum_reg;

endmodule


================================================
FILE: rtl/phase_1/PE_cluster.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 11/29/2019 09:11:06 PM
// Design Name: 
// Module Name: PE_cluster
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module PE_cluster #(parameter DATA_WIDTH = 16,
					parameter ADDR_WIDTH = 9,
					
					parameter int X_dim = 5,
					parameter int Y_dim = 3,
   
					parameter int kernel_size = 3,
					parameter int act_size = 5,
					
					parameter W_READ_ADDR = 0,  
					parameter A_READ_ADDR = 100,
					
					parameter W_LOAD_ADDR = 0,  
					parameter A_LOAD_ADDR = 100,
					
					parameter PSUM_ADDR = 500
					)
					( 
					input clk, reset,
					input [DATA_WIDTH-1:0] act_in,
					input [DATA_WIDTH-1:0] filt_in,
//					input load_en, 
					input load_en_wght, load_en_act,
					input start,
					output logic [DATA_WIDTH-1:0] pe_out[0 : X_dim-1],
					output logic compute_done,
					output logic load_done
					
		//extra 
		//			output logic [DATA_WIDTH-1:0] psum_out[0 : X_dim*Y_dim-1]
					);
		
		logic [DATA_WIDTH-1:0] psum_out[0 : X_dim*Y_dim-1];
		
		logic cluster_done[0 : X_dim*Y_dim-1];
		logic cluster_load_done[0 : X_dim*Y_dim-1];
		
		generate
		genvar i;
		for(i=0; i<X_dim; i++) 
			begin:gen_X
				genvar j;
				for(j=0; j<Y_dim; j++)
					begin:gen_Y
					
						PE #( 	.DATA_WIDTH(DATA_WIDTH),
								.ADDR_WIDTH(ADDR_WIDTH),
								.kernel_size(kernel_size),
								.act_size(act_size),
								.W_READ_ADDR(W_READ_ADDR + kernel_size*j),  
								.A_READ_ADDR(A_READ_ADDR + act_size*j + i),
								.W_LOAD_ADDR(W_LOAD_ADDR),  
								.A_LOAD_ADDR(A_LOAD_ADDR),
								.PSUM_ADDR(PSUM_ADDR)
							)
						pe (	
								.clk(clk),
								.reset(reset),
								.act_in(act_in),
								.filt_in(filt_in),
//								.load_en(load_en),
								.load_en_wght(load_en_wght),
								.load_en_act(load_en_act),
								.start(start),
								.pe_out(psum_out[i*Y_dim+j]),
								.compute_done(cluster_done[i*Y_dim+j]),
								.load_done(cluster_load_done[i*Y_dim+j])
							);
					
					end
			end
		endgenerate
		
		
/*  		virtual class psum_adder_class #(parameter X_dim, parameter Y_dim, parameter DATA_WIDTH);
			static function logic [DATA_WIDTH-1 : 0] psum_adder 
				(
					input logic [DATA_WIDTH-1:0] psum_out[X_dim*Y_dim-1 : 0]
				);
				begin
					psum_adder = {(DATA_WIDTH){1'b0}};
					for(int i=0; i<Y_dim; i++) begin
						psum_adder = psum_adder + psum_out[Y_dim*X_dim+i];
					end
				end
			endfunction
		endclass  */
					
		


 			function logic [DATA_WIDTH-1 : 0] psum_adder 
				(
					input logic [DATA_WIDTH-1:0] psum_out[0 : X_dim*Y_dim-1],
					input logic [3:0] X_dim,
					input logic [3:0] Y_dim
				);
				begin
					psum_adder = {(DATA_WIDTH){1'b0}};
					for(int i=0; i<Y_dim; i++) begin
						psum_adder = psum_adder + psum_out[Y_dim*X_dim+i];
					end
				end
			endfunction
				
				
				
/* 		always@(posedge clk) begin
			if(reset) begin
				for(int i=0; i<X_dim; i++) begin
					pe_out[i] <= 0;
				end
			end else begin
				for(int i=0; i<X_dim; i++) begin
					pe_out[i] <= psum_adder_class#
									(.X_dim(i),
									 .Y_dim(Y_dim),
									 .DATA_WIDTH(DATA_WIDTH)
									)
									::psum_adder(psum_out);
				end
			end
			
		end */
		
		
		// Add partial sums and register at pe_out
		always@(posedge clk) begin
			if(reset) begin
				for(int i=0; i<X_dim; i++) begin
					pe_out[i] <= 0;
				end
			end else begin
				for(int i=0; i<X_dim; i++) begin
					pe_out[i] <= psum_adder(psum_out,i,Y_dim);
				end
			end
			
		end
		
		
		assign compute_done = cluster_done[0];
		assign load_done = cluster_load_done[0];
		
	//	assign pe_out[X_dim-1:0] = psum_out[X_dim*Y_dim-1 : 0]
			  
endmodule
				   
				   
				   
				   
				   
				   
				   
				   
				   
				   

================================================
FILE: rtl/phase_1/SPad.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 11/27/2019 10:35:28 AM
// Design Name: 
// Module Name: SPad
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module SPad #( parameter DATA_BITWIDTH = 16,
			 parameter ADDR_BITWIDTH = 9 )
		   ( input clk,
			 input reset,
			 input read_req,
			 input write_en,
			 input [ADDR_BITWIDTH-1 : 0] r_addr,
			 input [ADDR_BITWIDTH-1 : 0] w_addr,
			 input [DATA_BITWIDTH-1 : 0] w_data,
			 output logic [DATA_BITWIDTH-1 : 0] r_data
    );
	
	logic [DATA_BITWIDTH-1 : 0] mem [0 : (1 << ADDR_BITWIDTH) - 1]; 
		// default - 512(2^9) 16-bit memory. Total size = 1kB 
	logic [DATA_BITWIDTH-1 : 0] data;
	
	always@(posedge clk)
		begin : READ
			if(reset)
				data <= 0;
			else
			begin
				if(read_req) begin
					data <= mem[r_addr];
//					$display("Read Address to SPad:%d",r_addr);
				end else begin
					data <= 10101;
				end
			end
		end
	
	assign r_data = data;
	
	always@(posedge clk)
		begin : WRITE
		
    		
 			$display("\t\t\t\t\t Current Status:\n \
				 \t mem[0]:%d", mem[0],
				" | mem[1]:%d", mem[1],
				" | mem[2]:%d", mem[2],
				" | mem[3]:%d", mem[3],
				" | mem[4]:%d", mem[4],
				" | mem[5]:%d", mem[5],
				" | mem[8]:%d", mem[8],
				" | mem[24]:%d\n", mem[24],
				" \t\t\t\t\t mem[100]:%d", mem[100],
				" | mem[101]:%d", mem[101],
				" | mem[102]:%d", mem[102],
				" | mem[103]:%d", mem[103],
				" | mem[104]:%d", mem[104],
				" | mem[105]:%d\n", mem[105],
				" | mem[124]:%d\n", mem[124],
				" | mem[148]:%d\n", mem[148],
				" \t\t\t\t\t psum:%d", mem[500],
				" | psum:%d", mem[501],
				" | psum:%d", mem[502],
				" | psum:%d", mem[503],
				" | psum:%d", mem[504]
				); 
				 
			if(write_en && !reset) begin
				mem[w_addr] <= w_data;
			end
		end
	
endmodule


================================================
FILE: rtl/phase_1/glb_iact.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/01/2019 12:56:24 PM
// Design Name: 
// Module Name: glb_iact
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module glb_iact #( parameter DATA_BITWIDTH = 16,
			 parameter ADDR_BITWIDTH = 10 )
		   ( input clk,
			 input reset,
			 input read_req,
			 input write_en,
			 input [ADDR_BITWIDTH-1 : 0] r_addr,
			 input [ADDR_BITWIDTH-1 : 0] w_addr,
			 input [DATA_BITWIDTH-1 : 0] w_data,
			 output logic [DATA_BITWIDTH-1 : 0] r_data
    );
	
	logic [DATA_BITWIDTH-1 : 0] mem [0 : (1 << ADDR_BITWIDTH) - 1]; 
		// default - 1024(2^10) 16-bit memory. Total size = 2kB 
	logic [DATA_BITWIDTH-1 : 0] data;
	
	always@(posedge clk)
		begin : READ
			if(reset)
				data = 0;
			else
			begin
				if(read_req) begin
					data = mem[r_addr];
//					$display("Read Address to SPad:%d",r_addr);
				end else begin
					data = 10101; //Random default value to verify model
				end
			end
		end
	
	assign r_data = data;
	
	always@(posedge clk)
		begin : WRITE	
			if(write_en && !reset) begin
				mem[w_addr] = w_data;
			end
		end
	
endmodule



================================================
FILE: rtl/phase_1/glb_psum.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/01/2019 01:13:40 PM
// Design Name: 
// Module Name: glb_psum
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module glb_psum #( parameter DATA_BITWIDTH = 16,
			 parameter ADDR_BITWIDTH = 10 )
		   ( input clk,
			 input reset,
			 input read_req,
			 input write_en,
			 input [ADDR_BITWIDTH-1 : 0] r_addr,
			 input [ADDR_BITWIDTH-1 : 0] w_addr,
			 input [DATA_BITWIDTH-1 : 0] w_data,
			 output logic [DATA_BITWIDTH-1 : 0] r_data
    );
	
	logic [DATA_BITWIDTH-1 : 0] mem [0 : (1 << ADDR_BITWIDTH) - 1]; 
		// default - 1024(2^10) 16-bit memory. Total size = 2kB 
	logic [DATA_BITWIDTH-1 : 0] data;
	
	always@(posedge clk)
		begin : READ
			if(reset)
				data = 0;
			else
			begin
				if(read_req) begin
					data = mem[r_addr];
//					$display("Read Address to SPad:%d",r_addr);
				end else begin
					data = 10101; //Random default value to verify model
				end
			end
		end
	
	assign r_data = data;
	
	always@(posedge clk)
		begin : WRITE
		
/* 				$display("\t\t\t\t\t Current Status in glb_psum:\n \
				 \t psum[0]:%d", mem[0],
				" | psum[1]:%d", mem[1],
				" | psum[2]:%d", mem[2],
				" | psum[3]:%d", mem[3],
				" | psum[4]:%d", mem[4],
				" | psum[5]:%d", mem[5],
				" | psum[6]:%d", mem[6],
				" | psum[7]:%d", mem[7],
				" | psum[8]:%d", mem[8],
				" | psum[9]:%d", mem[9]
				);
			
			$display("WriteEn: %d\n",write_en);
			$display("Write Data: %d\n",w_data);
			$display("Write Addr: %d\n\n\n",w_addr); */
			
			if(write_en && !reset) begin
				mem[w_addr] = w_data;
			end
		end
	
endmodule



================================================
FILE: rtl/phase_1/glb_weight.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/01/2019 04:07:04 PM
// Design Name: 
// Module Name: glb_weight
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module glb_weight #( parameter DATA_BITWIDTH = 16,
			 parameter ADDR_BITWIDTH = 10 )
		   ( input clk,
			 input reset,
			 input read_req,
			 input write_en,
			 input [ADDR_BITWIDTH-1 : 0] r_addr,
			 input [ADDR_BITWIDTH-1 : 0] w_addr,
			 input [DATA_BITWIDTH-1 : 0] w_data,
			 output logic [DATA_BITWIDTH-1 : 0] r_data
    );
	
	logic [DATA_BITWIDTH-1 : 0] mem [0 : (1 << ADDR_BITWIDTH) - 1]; 
		// default - 1024(2^10) 16-bit memory. Total size = 2kB 
	logic [DATA_BITWIDTH-1 : 0] data;
	
	always@(posedge clk)
		begin : READ
			if(reset)
				data = 0;
			else
			begin
				if(read_req) begin
					data = mem[r_addr];
//					$display("Read Address to SPad:%d",r_addr);
				end else begin
					data = 10101; //Random default value to verify model
				end
			end
		end
	
	assign r_data = data;
	
	always@(posedge clk)
		begin : WRITE	
			if(write_en && !reset) begin
				mem[w_addr] = w_data;
			end
		end
	
endmodule


================================================
FILE: rtl/phase_1/router_cluster.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/03/2019 02:24:04 PM
// Design Name: 
// Module Name: router_cluster
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_cluster#(

			parameter DATA_BITWIDTH = 16,
			parameter ADDR_BITWIDTH_GLB = 10,
			parameter ADDR_BITWIDTH_SPAD = 9,
			
			parameter kernel_size = 3,
	        parameter act_size = 5,
					
			parameter NUM_ROUTER_PSUM = 1,
			parameter NUM_ROUTER_IACT = 1,
			parameter NUM_ROUTER_WGHT = 1,
			
			parameter A_READ_ADDR =100, 
            parameter A_LOAD_ADDR = 0,
			
			parameter W_READ_ADDR = 0, 
            parameter W_LOAD_ADDR = 0,
			
			parameter PSUM_READ_ADDR = 0,
			parameter PSUM_LOAD_ADDR = 0
			)
		   ( input clk,
			 input reset,
			 
			 //Signals for Activation Router
			 input [DATA_BITWIDTH-1 : 0] r_data_glb_iact,
			 input load_spad_ctrl_iact,
			 
			 output logic [ADDR_BITWIDTH_GLB-1 : 0] r_addr_glb_iact,
			 output logic read_req_glb_iact,
			 
			 output logic [DATA_BITWIDTH-1 : 0] w_data_spad_iact,
			 output logic load_en_spad_iact,
			 
			 
			 //Signals for Weight Router
			 input [DATA_BITWIDTH-1 : 0] r_data_glb_wght,
			 input load_spad_ctrl_wght,
			 
			 output logic [ADDR_BITWIDTH_GLB-1 : 0] r_addr_glb_wght,
			 output logic read_req_glb_wght,

			 output logic [DATA_BITWIDTH-1 : 0] w_data_spad_wght,
			 output logic load_en_spad_wght,
			 
			 
			 //Signals for psum router
			 input [DATA_BITWIDTH-1 : 0] r_data_spad_psum[0:kernel_size-1],
			 input write_psum_ctrl, //connected to compute_done of pe_cluster
			 
			 output logic [ADDR_BITWIDTH_GLB-1 : 0] w_addr_glb_psum,
			 output logic write_en_glb_psum,
			 output logic [DATA_BITWIDTH-1 : 0] w_data_glb_psum
			 );
			
			//Instantiate iact router
			generate
			genvar i;
			for(i=0; i<NUM_ROUTER_IACT; i++) 
				begin:router_iact_gen
					router_iact #(.DATA_BITWIDTH(DATA_BITWIDTH),
									.ADDR_BITWIDTH_GLB(ADDR_BITWIDTH_GLB),
									.ADDR_BITWIDTH_SPAD(ADDR_BITWIDTH_SPAD),

									.kernel_size(kernel_size),
									.act_size(act_size),
									
									.A_READ_ADDR(A_READ_ADDR), 
									.A_LOAD_ADDR(A_LOAD_ADDR)
								)
					router_iact_0
								(	.clk(clk),
									.reset(reset),
									
									.r_data_glb_iact(r_data_glb_iact),

									.r_addr_glb_iact(r_addr_glb_iact),
									.read_req_glb_iact(read_req_glb_iact),
									
									.w_data_spad(w_data_spad_iact),
									.load_en_spad(load_en_spad_iact),
									
									//Input from control unit to load weights to spad
									.load_spad_ctrl(load_spad_ctrl_iact)
								);	
				end
			endgenerate
			
						//Instantiate weight router
			generate
			genvar k;
			for(k=0; k<NUM_ROUTER_WGHT; k++) 
				begin:router_weight_gen
					router_weight #(.DATA_BITWIDTH(DATA_BITWIDTH),
									.ADDR_BITWIDTH_GLB(ADDR_BITWIDTH_GLB),
									.ADDR_BITWIDTH_SPAD(ADDR_BITWIDTH_SPAD),

									.kernel_size(kernel_size),
									.act_size(act_size),
									
									.W_READ_ADDR(W_READ_ADDR), 
									.W_LOAD_ADDR(W_LOAD_ADDR)
								)
					router_weight_0
								(	.clk(clk),
									.reset(reset),
									
									.r_data_glb_wght(r_data_glb_wght),

									.r_addr_glb_wght(r_addr_glb_wght),
									.read_req_glb_wght(read_req_glb_wght),
									
									.w_data_spad(w_data_spad_wght),
									.load_en_spad(load_en_spad_wght),
									
									//Input from control unit to load weights to spad
									.load_spad_ctrl(load_spad_ctrl_wght)
								);	
				end
			endgenerate
			
						//Instantiate iact router
			generate
			genvar j;
			for(j=0; j<NUM_ROUTER_PSUM; j++) 
				begin:router_psum_gen
					router_psum #(.DATA_BITWIDTH(DATA_BITWIDTH),
									.ADDR_BITWIDTH_GLB(ADDR_BITWIDTH_GLB),
									.ADDR_BITWIDTH_SPAD(ADDR_BITWIDTH_SPAD),

									.kernel_size(kernel_size),
									.act_size(act_size),
									
									.PSUM_LOAD_ADDR(PSUM_LOAD_ADDR)
								)
					router_psum_0
								(	.clk(clk),
									.reset(reset),
									
									.r_data_spad_psum(r_data_spad_psum[0:kernel_size-1]),

									.w_addr_glb_psum(w_addr_glb_psum),
									.write_en_glb_psum(write_en_glb_psum),
									
									.w_data_glb_psum(w_data_glb_psum),

									//Input from control unit to load weights to spad
									.write_psum_ctrl(write_psum_ctrl)
								);	
				end
			endgenerate
			
endmodule


================================================
FILE: rtl/phase_1/router_iact.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/02/2019 03:12:11 PM
// Design Name: 
// Module Name: router_act
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_iact #( parameter DATA_BITWIDTH = 16,
						parameter ADDR_BITWIDTH_GLB = 10,
						parameter ADDR_BITWIDTH_SPAD = 9,
						
						parameter int X_dim = 5,
                        parameter int Y_dim = 3,
                        parameter int kernel_size = 3,
                        parameter int act_size = 5,
						
						parameter A_READ_ADDR =100, 
                        parameter A_LOAD_ADDR = 0
					)
					
					(	input clk,
						input reset,
						
						//for reading glb
						input [DATA_BITWIDTH-1 : 0] r_data_glb_iact,
						output logic [ADDR_BITWIDTH_GLB-1 : 0] r_addr_glb_iact,
						output logic read_req_glb_iact,
						
						//for writing to spad
						output logic [DATA_BITWIDTH-1 : 0] w_data_spad,
						output logic load_en_spad,
						
						//Input from control unit to load weights to spad
						input load_spad_ctrl
			
					);
				
					
		enum logic [2:0] {IDLE=3'b000, READ_GLB=3'b001, WRITE_SPAD=3'b010, READ_GLB_0=3'b011} state;
		
		logic [4:0] filt_count;
		
		always@(posedge clk) begin
//			$display("State: %s", state.name());
			if(reset) begin
				read_req_glb_iact <= 0;
				r_addr_glb_iact <= 0;
				load_en_spad <= 0;
				filt_count <= 0;
				state <= IDLE;
			end else begin
				case(state)
					IDLE:begin
						if(load_spad_ctrl) begin
							read_req_glb_iact <= 1;
							r_addr_glb_iact <= A_READ_ADDR;
							state <= READ_GLB;
						end else begin
							read_req_glb_iact = 0;
							load_en_spad = 0;
							state <= IDLE;
						end
					end
					
					READ_GLB:begin
						
						filt_count <= filt_count + 1;
						r_addr_glb_iact <= r_addr_glb_iact + 1;
						w_data_spad <= r_data_glb_iact;
						state <= WRITE_SPAD;
					end
					
					WRITE_SPAD:begin
						load_en_spad <= 1;
						if(filt_count == (act_size**2)) begin
							w_data_spad <= r_data_glb_iact;
							filt_count <= 0;
							r_addr_glb_iact <= A_READ_ADDR;
							
							state <= IDLE;
						end else begin
							w_data_spad <= r_data_glb_iact;
							filt_count <= filt_count + 1;
							r_addr_glb_iact <= r_addr_glb_iact + 1;
							state <= WRITE_SPAD;
						end
					end
				endcase
			end
		end
 
endmodule



================================================
FILE: rtl/phase_1/router_psum.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/03/2019 11:22:43 AM
// Design Name: 
// Module Name: router_psum
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_psum #( parameter DATA_BITWIDTH = 16,
						parameter ADDR_BITWIDTH_GLB = 10,
						parameter ADDR_BITWIDTH_SPAD = 9,
						
						parameter int X_dim = 5,
                        parameter int Y_dim = 3,
                        parameter int kernel_size = 3,
                        parameter int act_size = 5,
						
//						parameter A_READ_ADDR =100, 
                        
//                        parameter A_LOAD_ADDR = 0,
						
						parameter PSUM_READ_ADDR = 0,
						parameter PSUM_LOAD_ADDR = 0
					)
					
					(	input clk,
						input reset,
						
						//for reading glb
						input [DATA_BITWIDTH-1 : 0] r_data_spad_psum[0:kernel_size-1],
						output logic [ADDR_BITWIDTH_GLB-1 : 0] w_addr_glb_psum,
						output logic write_en_glb_psum,
						
						//for writing to spad
						output logic [DATA_BITWIDTH-1 : 0] w_data_glb_psum,
//						output logic load_en_spad,
						
						//Input from PE cluster to write psums to glb
						input write_psum_ctrl
			
					);
				
					
		enum logic [2:0] {IDLE=3'b000, WRITE_GLB=3'b001, READ_PSUM=3'b010} state;
		
		logic [4:0] psum_count;
		logic [DATA_BITWIDTH-1 : 0] pe_psum[0:kernel_size-1];
		logic [2:0] iter;
		
		always@(posedge clk) begin
//			$display("State of router_psum: %s", state.name());
			if(reset) begin
				w_addr_glb_psum <= PSUM_LOAD_ADDR;
				psum_count <= 0;
				write_en_glb_psum <= 0;
				iter <= 0;
				state <= IDLE;
			end else begin
				case(state)
					IDLE:begin
						if(write_psum_ctrl) begin
							//write_en_glb_psum <= 1;
							state <= READ_PSUM;
						end else begin
							psum_count <= 0;
							write_en_glb_psum <= 0;
							w_addr_glb_psum <= PSUM_LOAD_ADDR;
							state <= IDLE;
						end
					end
					
					READ_PSUM:begin
						pe_psum <= r_data_spad_psum;
//						$display("Psum read in router:%d",pe_psum[0:kernel_size-1]);
						psum_count <= 0;
						state <= WRITE_GLB;
					end
					
					WRITE_GLB:begin
						write_en_glb_psum <= 1;
//						$display("Psum written to address %d; Iter is %d",w_addr_glb_psum, iter);
						if(psum_count == (kernel_size-1)) begin
							w_data_glb_psum <= pe_psum[psum_count];
							psum_count <= 0;
							w_addr_glb_psum <= w_addr_glb_psum + 1;
							iter <= iter + 1;
							state <= IDLE;
						end else begin
							w_data_glb_psum <= pe_psum[psum_count];
							psum_count <= psum_count + 1;
							
							if(psum_count == (kernel_size-1)) begin
								state <= IDLE;
							end else if(psum_count == 0) begin
								w_addr_glb_psum <= PSUM_LOAD_ADDR+iter*kernel_size;
								state <= WRITE_GLB;
							end else begin
								w_addr_glb_psum <= w_addr_glb_psum + 1;
								state <= WRITE_GLB;
							end
							
						end
					end
				endcase
			end
		end
 
endmodule


================================================
FILE: rtl/phase_1/router_weight.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/01/2019 03:50:08 PM
// Design Name: 
// Module Name: router_weight
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_weight #( parameter DATA_BITWIDTH = 16,
						parameter ADDR_BITWIDTH_GLB = 10,
						parameter ADDR_BITWIDTH_SPAD = 9,
						
						parameter int X_dim = 5,
                        parameter int Y_dim = 3,
                        parameter int kernel_size = 3,
                        parameter int act_size = 5,
						
						parameter W_READ_ADDR = 0, 
                        
                        parameter W_LOAD_ADDR = 0
					)
					
					(	input clk,
						input reset,
						
						//for reading glb
						input [DATA_BITWIDTH-1 : 0] r_data_glb_wght,
						output logic [ADDR_BITWIDTH_GLB-1 : 0] r_addr_glb_wght,
						output logic read_req_glb_wght,
						
						//for writing to spad
						output logic [DATA_BITWIDTH-1 : 0] w_data_spad,
						output logic load_en_spad,
						
						//Input from control unit to load weights to spad
						input load_spad_ctrl
			
					);
				
					
		enum logic [2:0] {IDLE=3'b000, READ_GLB=3'b001, WRITE_SPAD=3'b010, READ_GLB_0=3'b011} state;
		
		logic [4:0] filt_count;
		
		always@(posedge clk) begin
//			$display("State: %s", state.name());
			if(reset) begin
				read_req_glb_wght <= 0;
				r_addr_glb_wght <= 0;
				load_en_spad <= 0;
				filt_count <= 0;
				state <= IDLE;
			end else begin
				case(state)
					IDLE:begin
						if(load_spad_ctrl) begin
							read_req_glb_wght <= 1;
							r_addr_glb_wght <= W_READ_ADDR;
							state <= READ_GLB;
						end else begin
							read_req_glb_wght = 0;
							load_en_spad <= 0;
							state <= IDLE;
						end
					end
					
					READ_GLB:begin
						
						filt_count <= filt_count + 1;
						r_addr_glb_wght <= r_addr_glb_wght + 1;
						w_data_spad <= r_data_glb_wght;
						state <= WRITE_SPAD;
					end
					
					WRITE_SPAD:begin
						load_en_spad <= 1;
						if(filt_count == (kernel_size**2)) begin
							w_data_spad <= r_data_glb_wght;
							filt_count <= 0;
							r_addr_glb_wght <= W_READ_ADDR;
							
							state <= IDLE;
						end else begin
							w_data_spad <= r_data_glb_wght;
							filt_count <= filt_count + 1;
							r_addr_glb_wght <= r_addr_glb_wght + 1;
							state <= WRITE_SPAD;
						end
					end
				endcase
			end
		end
 
endmodule


================================================
FILE: rtl/phase_2/HMNoC_cluster_east.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/10/2019 02:47:05 PM
// Design Name: 
// Module Name: HMNoC_cluster_east
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module HMNoC_cluster_east
	#(
		parameter DATA_BITWIDTH = 16,
		parameter ADDR_BITWIDTH = 10,
		
		parameter DATA_WIDTH = 16,
		parameter ADDR_WIDTH = 9,
		
		// GLB Cluster parameters. This TestBench uses only 1 of each
		parameter NUM_GLB_IACT = 1,
		parameter NUM_GLB_PSUM = 1,
		parameter NUM_GLB_WGHT = 1,
		
		parameter ADDR_BITWIDTH_GLB = 10,
		parameter ADDR_BITWIDTH_SPAD = 9,
		
		parameter NUM_ROUTER_PSUM = 1,
		parameter NUM_ROUTER_IACT = 1,
		parameter NUM_ROUTER_WGHT = 1,
				
		parameter int kernel_size = 3,
		parameter int act_size = 5,
		
		parameter int X_dim = 3,
		parameter int Y_dim = 3,
		
		parameter W_READ_ADDR = 0, 
		parameter A_READ_ADDR = 0,
		
		parameter W_LOAD_ADDR = 0,  
		parameter A_LOAD_ADDR = 0,
		
		parameter PSUM_READ_ADDR = 0,
		parameter PSUM_LOAD_ADDR = 0
	
    )
	(	
		input clk,
		input reset,
		
		//PE Cluster Interface
		input start,
		output load_done,
		
		input load_en_wght,
		input load_en_act,
		
        output [DATA_WIDTH-1:0] pe_out[X_dim-1:0],
		output compute_done,
		
		
		//GLB Cluster Interface

		input write_en_iact,
		input write_en_wght,
		
		input [DATA_WIDTH-1:0] w_data_iact,
		input [ADDR_WIDTH-1:0] w_addr_iact,
		
		input [DATA_WIDTH-1:0] w_data_wght,
		input [ADDR_WIDTH-1:0] w_addr_wght,
		
		input [ADDR_WIDTH-1:0] w_addr_psum,		
				
		output [DATA_WIDTH-1:0] r_data_psum,
		input [ADDR_WIDTH-1:0] r_addr_psum,
	
		input read_req_iact,
		input read_req_psum,
		input read_req_wght,
		
		input [ADDR_WIDTH-1:0] r_addr_iact,
		input [ADDR_WIDTH-1:0] r_addr_wght,
		

		
		//WGHT Router Ports
		input [3:0] router_mode_wght,
		
		//Interface with North
		//Source ports
		input [DATA_WIDTH-1:0] north_data_i_wght,
		input north_enable_i_wght,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] north_data_o_wght,
		output logic north_enable_o_wght,
		
		
		//Interface with South
		//Source ports
		input [DATA_WIDTH-1:0] south_data_i_wght,
		input south_enable_i_wght,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] south_data_o_wght,
		output logic south_enable_o_wght,
		
		
		//Interface with West
		//Source ports
		input [DATA_WIDTH-1:0] west_data_i_wght,
		input west_enable_i_wght,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] west_data_o_wght,
		output logic west_enable_o_wght,
		
		
		//Interface with East - Devices
		//Source ports
//		input [DATA_WIDTH-1:0] east_data_i_wght,
		input east_enable_i_wght,
		
		//Destination ports
//		output logic [DATA_WIDTH-1:0] east_data_o_wght,
		output logic east_enable_o_wght,
		
	//IACT Router Ports
		input [3:0] router_mode_iact,
		
		//Interface with North
		//Source ports
		input [DATA_WIDTH-1:0] north_data_i_iact,
		input north_enable_i_iact,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] north_data_o_iact,
		output logic north_enable_o_iact,
		
		
		//Interface with South
		//Source ports
		input [DATA_WIDTH-1:0] south_data_i_iact,
		input south_enable_i_iact,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] south_data_o_iact,
		output logic south_enable_o_iact,
		
		
		//Interface with West
		//Source ports
		input [DATA_WIDTH-1:0] west_data_i_iact,
		input west_enable_i_iact,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] west_data_o_iact,
		output logic west_enable_o_iact,
		
		
		//Interface with East - Devices
		//Source ports
//		input [DATA_WIDTH-1:0] east_data_i_iact,
		input east_enable_i_iact,
		
		//Destination ports
//		output logic [DATA_WIDTH-1:0] east_data_o_iact,
		output logic east_enable_o_iact,
		
	
	//PSUM Router Ports
		input [3:0] router_mode_psum,
		
		//Interface with North
		//Source ports
		input [DATA_WIDTH-1:0] north_data_i_psum,
		input north_enable_i_psum,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] north_data_o_psum,
		output logic north_enable_o_psum,
		
		
		//Interface with South
		//Source ports
		input [DATA_WIDTH-1:0] south_data_i_psum,
		input south_enable_i_psum,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] south_data_o_psum,
		output logic south_enable_o_psum,
		
		
		//Interface with West
		//Source ports
		input [DATA_WIDTH-1:0] west_data_i_psum,
		input west_enable_i_psum,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] west_data_o_psum,
		output logic west_enable_o_psum,
		
		//Interface with East - Devices
		//Source ports
		input [DATA_WIDTH-1:0] east_data_i_psum,
		input east_enable_i_psum,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] east_data_o_psum,
		output logic east_enable_o_psum
	
	);
	
	
	//Logic for Direction
		enum logic [3:0] {ALL=0, NORTH=1, SOUTH=2, WEST=3, EAST=4,
						EASTNORTH=5, EASTSOUTH=6, EASTWEST=7,
						WESTNORTH=8, WESTSOUTH=9, WESTEAST=10} direction;
						
						
						
		//GLB cluster initialization
	GLB_cluster 
			#(	.DATA_BITWIDTH(DATA_BITWIDTH),
				.ADDR_BITWIDTH(ADDR_BITWIDTH),
				.NUM_GLB_IACT(NUM_GLB_IACT),
				.NUM_GLB_PSUM(NUM_GLB_PSUM),
				.NUM_GLB_WGHT(NUM_GLB_WGHT)
			)
	GLB_cluster_0
			(
				.clk(clk),   //TestBench/Controller
				.reset(reset),  //TestBench/Controller
				
				//Signals for reading from GLB
				.read_req_iact(read_req_iact),
				.read_req_psum(read_req_psum), //Read by testbench/controller
				.read_req_wght(read_req_wght),
				
			    .r_data_iact(router_cluster_0.east_data_i_iact),
			    .r_data_psum(r_data_psum), //Read by testbench/controller
				.r_data_wght(router_cluster_0.east_data_i_wght),
				
				.r_addr_iact(r_addr_iact),
			    .r_addr_psum(r_addr_psum), //testbench for reading final psums
				.r_addr_wght(r_addr_wght),

				
				//Signals for writing to GLB
			    .w_addr_iact(w_addr_iact), //testbench for writing
			    .w_addr_psum(w_addr_psum),
				.w_addr_wght(w_addr_wght), //testbench for writing
 
			    .w_data_iact(w_data_iact), //testbench for writing
			    .w_data_psum(router_cluster_0.east_data_o_psum),
				.w_data_wght(w_data_wght), //testbench for writing

				.write_en_iact(write_en_iact), //testbench for writing
				.write_en_psum(router_cluster_0.east_enable_o_psum),
				.write_en_wght(write_en_wght) //testbench for writing
			
			);
			
	
	
	
		router_cluster
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_cluster_0
		(
		
		//Ports for WGHT router
			.router_mode_wght(router_mode_wght), //TB*
			
			//Interface with North
			//Source ports
			.north_data_i_wght(north_data_i_wght),
			.north_enable_i_wght(north_enable_i_wght),
			
			//Destination ports
			.north_data_o_wght(north_data_o_wght),
			.north_enable_o_wght(north_enable_o_wght),
			
			
			//Interface with South
			//Source ports
			.south_data_i_wght(south_data_i_wght),
			.south_enable_i_wght(south_enable_i_wght),
			
			//Destination ports
			.south_data_o_wght(south_data_o_wght),
			.south_enable_o_wght(south_enable_o_wght),
			
			
			//Interface with West
			//Source ports
			.west_data_i_wght(west_data_i_wght), //GLB_cluster
			.west_enable_i_wght(west_enable_i_wght),
			
			//Destination ports
			.west_data_o_wght(pwest_data_o_wght),  //PE_cluster
			.west_enable_o_wght(west_enable_o_wght),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_wght(GLB_cluster_0.r_data_wght),
			.east_enable_i_wght(east_enable_i_wght),
	        
			//Destination ports
	        .east_data_o_wght(east_data_o_wght),
            .east_enable_o_wght(east_enable_o_wght),
			
		////////////////////////////////////////////
			
		//Ports for IACT router
			.router_mode_iact(router_mode_iact),  //TB*
			
			//Interface with North
			//Source ports
			.north_data_i_iact(north_data_i_iact),
			.north_enable_i_iact(north_enable_i_iact),
			
			//Destination ports
			.north_data_o_iact(north_data_o_iact),
			.north_enable_o_iact(north_enable_o_iact),
			
			
			//Interface with South
			//Source ports
			.south_data_i_iact(south_data_i_iact),
			.south_enable_i_iact(south_enable_i_iact),
			
			//Destination ports
			.south_data_o_iact(south_data_o_iact),
			.south_enable_o_iact(south_enable_o_iact),
			
			
			//Interface with West
			//Source ports
			.west_data_i_iact(west_data_i_iact),   //GLB_cluster
			.west_enable_i_iact(west_enable_i_iact),
			
			//Destination ports
			.west_data_o_iact(west_data_o_iact),  //PE_cluster
			.west_enable_o_iact(west_enable_o_iact),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_iact(GLB_cluster_0.r_data_iact),
			.east_enable_i_iact(east_enable_i_iact),
	        
			//Destination ports
	        .east_data_o_iact(pe_cluster_0.act_in),
            .east_enable_o_iact(east_enable_o_iact),
			
			
		////////////////////////////////////////////
			
		//Ports for PSUM router
			.router_mode_psum(router_mode_psum),
			
			//Interface with North
			//Source ports
			.north_data_i_psum(north_data_i_psum),
			.north_enable_i_psum(north_enable_i_psum),
			
			//Destination ports
			.north_data_o_psum(north_data_o_psum),
			.north_enable_o_psum(north_enable_o_psum),
			
			
			//Interface with South
			//Source ports
			.south_data_i_psum(south_data_i_psum),
			.south_enable_i_psum(south_enable_i_psum),
			
			//Destination ports
			.south_data_o_psum(south_data_o_psum),
			.south_enable_o_psum(south_enable_o_psum),
			
			
			//Interface with West
			//Source ports
			.west_data_i_psum(west_data_i_psum), //PE_cluster
			.west_enable_i_psum(west_enable_i_psum),
			
			//Destination ports
			.west_data_o_psum(west_data_o_psum), //GLB_cluster
			.west_enable_o_psum(west_enable_o_psum), //GLB_cluster
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_psum(east_data_i_psum),
			.east_enable_i_psum(east_enable_i_psum),
	        
			//Destination ports
	        .east_data_o_psum(GLB_cluster_0.w_data_psum),
            .east_enable_o_psum(GLB_cluster_0.write_en_psum)	
	);
	

	
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_0
    			(
					.clk(clk),
				    .reset(reset),
				    .act_in(router_cluster_0.east_data_o_iact),
				    .filt_in(router_cluster_0.east_data_o_wght),
					.load_en_wght(load_en_wght),
					.load_en_act(load_en_act),
					.start(start),
                    .pe_out(pe_out),
					.compute_done(compute_done),
					.load_done(load_done)
    			);

	
endmodule


================================================
FILE: rtl/phase_2/HMNoC_cluster_west.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/10/2019 11:42:17 AM
// Design Name: 
// Module Name: HMNoC_cluster_new
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module HMNoC_cluster_west
	#(
		parameter DATA_BITWIDTH = 16,
		parameter ADDR_BITWIDTH = 10,
		
		parameter DATA_WIDTH = 16,
		parameter ADDR_WIDTH = 9,
		
		// GLB Cluster parameters. This TestBench uses only 1 of each
		parameter NUM_GLB_IACT = 1,
		parameter NUM_GLB_PSUM = 1,
		parameter NUM_GLB_WGHT = 1,
		
		parameter ADDR_BITWIDTH_GLB = 10,
		parameter ADDR_BITWIDTH_SPAD = 9,
		
		parameter NUM_ROUTER_PSUM = 1,
		parameter NUM_ROUTER_IACT = 1,
		parameter NUM_ROUTER_WGHT = 1,
				
		parameter int kernel_size = 3,
		parameter int act_size = 5,
		
		parameter int X_dim = 3,
		parameter int Y_dim = 3,
		
		parameter W_READ_ADDR = 0, 
		parameter A_READ_ADDR = 0,
		
		parameter W_LOAD_ADDR = 0,  
		parameter A_LOAD_ADDR = 0,
		
		parameter PSUM_READ_ADDR = 0,
		parameter PSUM_LOAD_ADDR = 0
	
    )
	(	
		input clk,
		input reset,
		
		//PE Cluster Interface
		input start,
		output load_done,
		
		input load_en_wght,
		input load_en_act,
		
        output [DATA_WIDTH-1:0] pe_out[X_dim-1:0],
		output compute_done,
		
		
		//GLB Cluster Interface

		input write_en_iact,
		input write_en_wght,
		
		input [DATA_WIDTH-1:0] w_data_iact,
		input [ADDR_WIDTH-1:0] w_addr_iact,
		
		input [DATA_WIDTH-1:0] w_data_wght,
		input [ADDR_WIDTH-1:0] w_addr_wght,
		
		input [ADDR_WIDTH-1:0] w_addr_psum,		
				
		output [DATA_WIDTH-1:0] r_data_psum,
		input [ADDR_WIDTH-1:0] r_addr_psum,
	
		input read_req_iact,
		input read_req_psum,
		input read_req_wght,
		
		input [ADDR_WIDTH-1:0] r_addr_iact,
		input [ADDR_WIDTH-1:0] r_addr_wght,
		

		
		//WGHT Router Ports
		input [3:0] router_mode_wght,
		
		//Interface with North
		//Source ports
		input [DATA_WIDTH-1:0] north_data_i_wght,
		input north_enable_i_wght,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] north_data_o_wght,
		output logic north_enable_o_wght,
		
		
		//Interface with South
		//Source ports
		input [DATA_WIDTH-1:0] south_data_i_wght,
		input south_enable_i_wght,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] south_data_o_wght,
		output logic south_enable_o_wght,
		
		
		//Interface with West
		//Source ports
//		input [DATA_WIDTH-1:0] west_data_i_wght,
		input west_enable_i_wght,
		
		//Destination ports
//		output logic [DATA_WIDTH-1:0] west_data_o_wght,
		output logic west_enable_o_wght,
		
		
		//Interface with East - Devices
		//Source ports
		input [DATA_WIDTH-1:0] east_data_i_wght,
		input east_enable_i_wght,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] east_data_o_wght,
		output logic east_enable_o_wght,
		
	//IACT Router Ports
		input [3:0] router_mode_iact,
		
		//Interface with North
		//Source ports
		input [DATA_WIDTH-1:0] north_data_i_iact,
		input north_enable_i_iact,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] north_data_o_iact,
		output logic north_enable_o_iact,
		
		
		//Interface with South
		//Source ports
		input [DATA_WIDTH-1:0] south_data_i_iact,
		input south_enable_i_iact,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] south_data_o_iact,
		output logic south_enable_o_iact,
		
		
		//Interface with West
		//Source ports
//		input [DATA_WIDTH-1:0] west_data_i_iact,
		input west_enable_i_iact,
		
		//Destination ports
//		output logic [DATA_WIDTH-1:0] west_data_o_iact,
		output logic west_enable_o_iact,
		
		
		//Interface with East - Devices
		//Source ports
		input [DATA_WIDTH-1:0] east_data_i_iact,
		input east_enable_i_iact,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] east_data_o_iact,
		output logic east_enable_o_iact,
		
	
	//PSUM Router Ports
		input [3:0] router_mode_psum,
		
		//Interface with North
		//Source ports
		input [DATA_WIDTH-1:0] north_data_i_psum,
		input north_enable_i_psum,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] north_data_o_psum,
		output logic north_enable_o_psum,
		
		
		//Interface with South
		//Source ports
		input [DATA_WIDTH-1:0] south_data_i_psum,
		input south_enable_i_psum,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] south_data_o_psum,
		output logic south_enable_o_psum,
		
		
		//Interface with West
		//Source ports
		input [DATA_WIDTH-1:0] west_data_i_psum,
		input west_enable_i_psum,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] west_data_o_psum,
		output logic west_enable_o_psum,
		
		//Interface with East - Devices
		//Source ports
		input [DATA_WIDTH-1:0] east_data_i_psum,
		input east_enable_i_psum,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] east_data_o_psum,
		output logic east_enable_o_psum
	
	);
	
	
	//Logic for Direction
		enum logic [3:0] {ALL=0, NORTH=1, SOUTH=2, WEST=3, EAST=4,
						EASTNORTH=5, EASTSOUTH=6, EASTWEST=7,
						WESTNORTH=8, WESTSOUTH=9, WESTEAST=10} direction;
						
						
						
		//GLB cluster initialization
	GLB_cluster 
			#(	.DATA_BITWIDTH(DATA_BITWIDTH),
				.ADDR_BITWIDTH(ADDR_BITWIDTH),
				.NUM_GLB_IACT(NUM_GLB_IACT),
				.NUM_GLB_PSUM(NUM_GLB_PSUM),
				.NUM_GLB_WGHT(NUM_GLB_WGHT)
			)
	GLB_cluster_0
			(
				.clk(clk),   //TestBench/Controller
				.reset(reset),  //TestBench/Controller
				
				//Signals for reading from GLB
				.read_req_iact(read_req_iact),
				.read_req_psum(read_req_psum), //Read by testbench/controller
				.read_req_wght(read_req_wght),
				
			    .r_data_iact(router_cluster_0.west_data_i_iact),
			    .r_data_psum(r_data_psum), //Read by testbench/controller
				.r_data_wght(router_cluster_0.west_data_i_wght),
				
				.r_addr_iact(r_addr_iact),
			    .r_addr_psum(r_addr_psum), //testbench for reading final psums
				.r_addr_wght(r_addr_wght),

				
				//Signals for writing to GLB
			    .w_addr_iact(w_addr_iact), //testbench for writing
			    .w_addr_psum(w_addr_psum),
				.w_addr_wght(w_addr_wght), //testbench for writing
 
			    .w_data_iact(w_data_iact), //testbench for writing
			    .w_data_psum(router_cluster_0.west_data_o_psum),
				.w_data_wght(w_data_wght), //testbench for writing

				.write_en_iact(write_en_iact), //testbench for writing
				.write_en_psum(router_cluster_0.west_enable_o_psum),
				.write_en_wght(write_en_wght) //testbench for writing
			
			);
			
	
	
	
		router_cluster
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_cluster_0
		(
		
		//Ports for WGHT router
			.router_mode_wght(router_mode_wght), //TB*
			
			//Interface with North
			//Source ports
			.north_data_i_wght(north_data_i_wght),
			.north_enable_i_wght(north_enable_i_wght),
			
			//Destination ports
			.north_data_o_wght(north_data_o_wght),
			.north_enable_o_wght(north_enable_o_wght),
			
			
			//Interface with South
			//Source ports
			.south_data_i_wght(south_data_i_wght),
			.south_enable_i_wght(south_enable_i_wght),
			
			//Destination ports
			.south_data_o_wght(south_data_o_wght),
			.south_enable_o_wght(south_enable_o_wght),
			
			
			//Interface with West
			//Source ports
			.west_data_i_wght(GLB_cluster_0.r_data_wght), //GLB_cluster
			.west_enable_i_wght(west_enable_i_wght),
			
			//Destination ports
			.west_data_o_wght(pe_cluster_0.filt_in),  //PE_cluster
			.west_enable_o_wght(west_enable_o_wght),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_wght(east_data_i_wght),
			.east_enable_i_wght(east_enable_i_wght),
	        
			//Destination ports
	        .east_data_o_wght(east_data_o_wght),
            .east_enable_o_wght(east_enable_o_wght),
			
		////////////////////////////////////////////
			
		//Ports for IACT router
			.router_mode_iact(router_mode_iact),  //TB*
			
			//Interface with North
			//Source ports
			.north_data_i_iact(north_data_i_iact),
			.north_enable_i_iact(north_enable_i_iact),
			
			//Destination ports
			.north_data_o_iact(north_data_o_iact),
			.north_enable_o_iact(north_enable_o_iact),
			
			
			//Interface with South
			//Source ports
			.south_data_i_iact(south_data_i_iact),
			.south_enable_i_iact(south_enable_i_iact),
			
			//Destination ports
			.south_data_o_iact(south_data_o_iact),
			.south_enable_o_iact(south_enable_o_iact),
			
			
			//Interface with West
			//Source ports
			.west_data_i_iact(GLB_cluster_0.r_data_iact),   //GLB_cluster
			.west_enable_i_iact(west_enable_i_iact),
			
			//Destination ports
			.west_data_o_iact(pe_cluster_0.act_in),  //PE_cluster
			.west_enable_o_iact(west_enable_o_iact),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_iact(east_data_i_iact),
			.east_enable_i_iact(east_enable_i_iact),
	        
			//Destination ports
	        .east_data_o_iact(east_data_o_iact),
            .east_enable_o_iact(east_enable_o_iact),
			
			
		////////////////////////////////////////////
			
		//Ports for PSUM router
			.router_mode_psum(router_mode_psum),
			
			//Interface with North
			//Source ports
			.north_data_i_psum(north_data_i_psum),
			.north_enable_i_psum(north_enable_i_psum),
			
			//Destination ports
			.north_data_o_psum(north_data_o_psum),
			.north_enable_o_psum(north_enable_o_psum),
			
			
			//Interface with South
			//Source ports
			.south_data_i_psum(south_data_i_psum),
			.south_enable_i_psum(south_enable_i_psum),
			
			//Destination ports
			.south_data_o_psum(south_data_o_psum),
			.south_enable_o_psum(south_enable_o_psum),
			
			
			//Interface with West
			//Source ports
			.west_data_i_psum(west_data_i_psum), //PE_cluster
			.west_enable_i_psum(west_enable_i_psum),
			
			//Destination ports
			.west_data_o_psum(GLB_cluster_0.w_data_psum), //GLB_cluster
			.west_enable_o_psum(GLB_cluster_0.write_en_psum), //GLB_cluster
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_psum(east_data_i_psum),
			.east_enable_i_psum(east_enable_i_psum),
	        
			//Destination ports
	        .east_data_o_psum(east_data_o_psum),
            .east_enable_o_psum(east_enable_o_psum)	
	);
	

	
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_0
    			(
					.clk(clk),
				    .reset(reset),
				    .act_in(router_cluster_0.west_data_o_iact),
				    .filt_in(router_cluster_0.west_data_o_wght),
					.load_en_wght(load_en_wght),
					.load_en_act(load_en_act),
					.start(start),
                    .pe_out(pe_out),
					.compute_done(compute_done),
					.load_done(load_done)
    			);

	
	
endmodule


================================================
FILE: rtl/phase_2/HMNoC_top.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/10/2019 03:22:12 PM
// Design Name: 
// Module Name: HMNoC_top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module HMNoC_top
	#(
		parameter DATA_BITWIDTH = 16,
		parameter ADDR_BITWIDTH = 10,
		
		parameter DATA_WIDTH = 16,
		parameter ADDR_WIDTH = 9,
		
		// GLB Cluster parameters. This TestBench uses only 1 of each
		parameter NUM_GLB_IACT = 1,
		parameter NUM_GLB_PSUM = 1,
		parameter NUM_GLB_WGHT = 1,
		
		parameter ADDR_BITWIDTH_GLB = 10,
		parameter ADDR_BITWIDTH_SPAD = 9,
		
		parameter NUM_ROUTER_PSUM = 1,
		parameter NUM_ROUTER_IACT = 1,
		parameter NUM_ROUTER_WGHT = 1,
				
		parameter int kernel_size = 3,
		parameter int act_size = 5,
		
		parameter int X_dim = 3,
		parameter int Y_dim = 3,
		
		parameter W_READ_ADDR = 0, 
		parameter A_READ_ADDR = 0,
		
		parameter W_LOAD_ADDR = 0,  
		parameter A_LOAD_ADDR = 0,
		
		parameter PSUM_READ_ADDR = 0,
		parameter PSUM_LOAD_ADDR = 0

    )
	(
		input clk,
		input reset,
		
		//PE Cluster Interface
		input start,
		output load_done,
		
		input load_en_wght,
		input load_en_act,
		
        output [DATA_WIDTH-1:0] pe_out[X_dim-1:0],
		output compute_done,
		
		
		//GLB Cluster Interface

		input write_en_iact,
		input write_en_wght,
		
		input [DATA_WIDTH-1:0] w_data_iact,
		input [ADDR_WIDTH-1:0] w_addr_iact,
		
		input [DATA_WIDTH-1:0] w_data_wght,
		input [ADDR_WIDTH-1:0] w_addr_wght,
		
		input [ADDR_WIDTH-1:0] w_addr_psum,		
				
		output [DATA_WIDTH-1:0] r_data_psum,
		input [ADDR_WIDTH-1:0] r_addr_psum,
	
		input read_req_iact,
		input read_req_psum,
		input read_req_wght,
		
		input [ADDR_WIDTH-1:0] r_addr_iact,
		input [ADDR_WIDTH-1:0] r_addr_wght,
		

		
		//WGHT Router Ports
		input [3:0] router_mode_wght,
		input [3:0] router_mode_iact,
		input [3:0] router_mode_psum
	);
	
	
	//Instantiation of NORTH WEST Cluster
	HMNoC_cluster_west 
		#(
			.DATA_BITWIDTH(DATA_BITWIDTH),
			.ADDR_BITWIDTH(ADDR_BITWIDTH),
			
			.DATA_WIDTH(DATA_WIDTH),
			.ADDR_WIDTH(ADDR_WIDTH),
			
			.NUM_GLB_IACT(NUM_GLB_IACT),
			.NUM_GLB_PSUM(NUM_GLB_PSUM),
			.NUM_GLB_WGHT(NUM_GLB_WGHT),

			.kernel_size(kernel_size),
			.act_size(act_size),
			
			.X_dim(X_dim),
			.Y_dim(Y_dim)
		)
	HMNoC_cluster_west_0 ///NORTH WEST Cluster
		(
			.clk(clk),   //TestBench/Controller
			.reset(reset),  //TestBench/Controller
			
			//Signals for reading from GLB
			.read_req_iact(read_req_iact),
			.read_req_psum(read_req_psum), //Read by testbench/controller
			.read_req_wght(read_req_wght),
			
//			.r_data_iact(router_cluster_0.r_data_glb_iact),
			.r_data_psum(r_data_psum), //Read by testbench/controller
//			.r_data_wght(router_cluster_0.r_data_glb_wght),
			
			.r_addr_iact(r_addr_iact),
			.r_addr_psum(r_addr_psum), //testbench for reading final psums
			.r_addr_wght(r_addr_wght),

			//Signals for writing to GLB
			.w_addr_iact(w_addr_iact), //testbench for writing
			.w_addr_psum(w_addr_psum),
			.w_addr_wght(w_addr_wght), //testbench for writing

			.w_data_iact(w_data_iact), //testbench for writing
//			.w_data_psum(router_cluster_0.w_data_glb_psum),
			.w_data_wght(w_data_wght), //testbench for writing

			.write_en_iact(write_en_iact), //testbench for writing
//			.write_en_psum(router_cluster_0.write_en_glb_psum),
			.write_en_wght(write_en_wght), //testbench for writing
				
				
	
			//Ports for WGHT router
			.router_mode_wght(router_mode_wght), //TB*
			
			//Interface with North
			//Source ports
			.north_data_i_wght(),
			.north_enable_i_wght(),
			
			//Destination ports
			.north_data_o_wght(),
			.north_enable_o_wght(),
			
			
			//Interface with South
			//Source ports
			.south_data_i_wght(HMNoC_cluster_west_1.north_data_o_wght),
			.south_enable_i_wght(HMNoC_cluster_west_1.north_enable_o_wght),
			
			//Destination ports
			.south_data_o_wght(HMNoC_cluster_west_1.north_data_i_wght),
			.south_enable_o_wght(HMNoC_cluster_west_1.north_enable_i_wght),
			
			
			//Interface with West
			//Source ports
//			.west_data_i_wght(GLB_cluster_0.r_data_wght), //GLB_cluster
			.west_enable_i_wght(west_enable_i_wght),
			
			//Destination ports
//			.west_data_o_wght(pe_cluster_0.filt_in),  //PE_cluster
			.west_enable_o_wght(west_enable_o_wght),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_wght(HMNoC_cluster_east_0.west_data_o_wght),
			.east_enable_i_wght(HMNoC_cluster_east_0.west_enable_o_wght),
	        
			//Destination ports
	        .east_data_o_wght(HMNoC_cluster_east_0.west_data_i_wght),
            .east_enable_o_wght(HMNoC_cluster_east_0.west_enable_i_wght),
			
		////////////////////////////////////////////
			
		//Ports for IACT router
			.router_mode_iact(router_mode_iact),  //TB*
			
			//Interface with North
			//Source ports
			.north_data_i_iact(),
			.north_enable_i_iact(),
			
			//Destination ports
			.north_data_o_iact(),
			.north_enable_o_iact(),
			
			
			//Interface with South
			//Source ports
			.south_data_i_iact(HMNoC_cluster_west_1.north_data_o_iact),
			.south_enable_i_iact(HMNoC_cluster_west_1.north_enable_o_iact),
			
			//Destination ports
			.south_data_o_iact(HMNoC_cluster_west_1.north_data_i_iact),
			.south_enable_o_iact(HMNoC_cluster_west_1.north_enable_i_iact),
			
			
			//Interface with West
			//Source ports
//			.west_data_i_iact(GLB_cluster_0.r_data_iact),   //GLB_cluster
			.west_enable_i_iact(west_enable_i_iact),
			
			//Destination ports
//			.west_data_o_iact(pe_cluster_0.act_in),  //PE_cluster
			.west_enable_o_iact(west_enable_o_iact),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_iact(HMNoC_cluster_east_0.west_data_o_iact),
			.east_enable_i_iact(HMNoC_cluster_east_0.west_enable_o_iact),
	        
			//Destination ports
	        .east_data_o_iact(HMNoC_cluster_east_0.west_data_i_iact),
            .east_enable_o_iact(HMNoC_cluster_east_0.west_enable_i_iact),
			
			
		////////////////////////////////////////////
			
		//Ports for PSUM router
			.router_mode_psum(router_mode_psum),
			
			//Interface with North
			//Source ports
			.north_data_i_psum(),
			.north_enable_i_psum(),
			
			//Destination ports
			.north_data_o_psum(),
			.north_enable_o_psum(),
			
			
			//Interface with South
			//Source ports
			.south_data_i_psum(HMNoC_cluster_west_1.north_data_o_psum),
			.south_enable_i_psum(HMNoC_cluster_west_1.north_enable_o_psum),
			
			//Destination ports
			.south_data_o_psum(HMNoC_cluster_west_1.north_data_i_psum),
			.south_enable_o_psum(HMNoC_cluster_west_1.north_enable_i_psum),
			
			
			//Interface with West
			//Source ports
			.west_data_i_psum(west_data_i_psum), //PE_cluster
			.west_enable_i_psum(west_enable_i_psum),
			
			//Destination ports
//			.west_data_o_psum(GLB_cluster_0.w_data_psum), //GLB_cluster
//			.west_enable_o_psum(GLB_cluster_0.write_en_psum), //GLB_cluster
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_psum(HMNoC_cluster_east_0.west_data_o_psum),
			.east_enable_i_psum(HMNoC_cluster_east_0.west_enable_o_psum),
	        
			//Destination ports
	        .east_data_o_psum(HMNoC_cluster_east_0.west_data_i_psum),
            .east_enable_o_psum(HMNoC_cluster_east_0.west_enable_i_psum),
			
			
			
			//PE Cluster
			.load_en_wght(load_en_wght),
			.load_en_act(load_en_act),
			.start(start),
			.pe_out(pe_out),
			.compute_done(compute_done),
			.load_done(load_done)
		);
		
		
		
		
	//Instantiation of SOUTH WEST Cluster
	HMNoC_cluster_west 
		#(
			.DATA_BITWIDTH(DATA_BITWIDTH),
			.ADDR_BITWIDTH(ADDR_BITWIDTH),
			
			.DATA_WIDTH(DATA_WIDTH),
			.ADDR_WIDTH(ADDR_WIDTH),
			
			.NUM_GLB_IACT(NUM_GLB_IACT),
			.NUM_GLB_PSUM(NUM_GLB_PSUM),
			.NUM_GLB_WGHT(NUM_GLB_WGHT),

			.kernel_size(kernel_size),
			.act_size(act_size),
			
			.X_dim(X_dim),
			.Y_dim(Y_dim)
		)
	HMNoC_cluster_west_1 ///SOUTH WEST Cluster
		(
			.clk(clk),   //TestBench/Controller
			.reset(reset),  //TestBench/Controller
			
			//Signals for reading from GLB
			.read_req_iact(),
			.read_req_psum(), //Read by testbench/controller
			.read_req_wght(),
			
//			.r_data_iact(router_cluster_0.r_data_glb_iact),
			.r_data_psum(), //Read by testbench/controller
//			.r_data_wght(router_cluster_0.r_data_glb_wght),
			
			.r_addr_iact(),
			.r_addr_psum(), //testbench for reading final psums
			.r_addr_wght(),

			//Signals for writing to GLB
			.w_addr_iact(), //testbench for writing
			.w_addr_psum(),
			.w_addr_wght(), //testbench for writing

			.w_data_iact(), //testbench for writing
//			.w_data_psum(router_cluster_0.w_data_glb_psum),
			.w_data_wght(), //testbench for writing

			.write_en_iact(), //testbench for writing
//			.write_en_psum(router_cluster_0.write_en_glb_psum),
			.write_en_wght(), //testbench for writing
				
				
	
			//Ports for WGHT router
			.router_mode_wght(), //TB*
			
			//Interface with North
			//Source ports
			.north_data_i_wght(HMNoC_cluster_west_0.south_data_o_wght),
			.north_enable_i_wght(HMNoC_cluster_west_0.south_enable_o_wght),
			
			//Destination ports
			.north_data_o_wght(HMNoC_cluster_west_0.south_data_i_wght),
			.north_enable_o_wght(HMNoC_cluster_west_0.south_enable_i_wght),
			
			
			//Interface with South
			//Source ports
			.south_data_i_wght(),
			.south_enable_i_wght(),
			
			//Destination ports
			.south_data_o_wght(),
			.south_enable_o_wght(),
			
			
			//Interface with West
			//Source ports
//			.west_data_i_wght(GLB_cluster_0.r_data_wght), //GLB_cluster
			.west_enable_i_wght(),
			
			//Destination ports
//			.west_data_o_wght(pe_cluster_0.filt_in),  //PE_cluster
			.west_enable_o_wght(),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_wght(HMNoC_cluster_east_1.west_data_o_wght),
			.east_enable_i_wght(HMNoC_cluster_east_1.west_enable_o_wght),
	        
			//Destination ports
	        .east_data_o_wght(HMNoC_cluster_east_1.west_data_i_wght),
            .east_enable_o_wght(HMNoC_cluster_east_1.west_enable_i_wght),
			
		////////////////////////////////////////////
			
		//Ports for IACT router
			.router_mode_iact(),  //TB*
			
			//Interface with North
			//Source ports
			.north_data_i_iact(HMNoC_cluster_west_0.south_data_o_iact),
			.north_enable_i_iact(HMNoC_cluster_west_0.south_enable_o_iact),
			
			//Destination ports
			.north_data_o_iact(HMNoC_cluster_west_0.south_data_i_iact),
			.north_enable_o_iact(HMNoC_cluster_west_0.south_enable_i_iact),
			
			
			//Interface with South
			//Source ports
			.south_data_i_iact(),
			.south_enable_i_iact(),

			//Destination ports
			.south_data_o_iact(),
			.south_enable_o_iact(),


			//Interface with West
			//Source ports
//			.west_data_i_iact(GLB_cluster_0.r_data_iact),   //GLB_cluster
			.west_enable_i_iact(),
			
			//Destination ports
//			.west_data_o_iact(pe_cluster_0.act_in),  //PE_cluster
			.west_enable_o_iact(),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_iact(),
			.east_enable_i_iact(),
	        
			//Destination ports
	        .east_data_o_iact(),
            .east_enable_o_iact(),
			
			
		////////////////////////////////////////////
			
		//Ports for PSUM router
			.router_mode_psum(),
			
			//Interface with North
			//Source ports
			.north_data_i_psum(HMNoC_cluster_west_0.south_data_o_psum),
			.north_enable_i_psum(HMNoC_cluster_west_0.south_enable_o_psum),
			
			//Destination ports
			.north_data_o_psum(HMNoC_cluster_west_0.south_data_i_psum),
			.north_enable_o_psum(HMNoC_cluster_west_0.south_enable_i_psum),
			
			
			//Interface with South
			//Source ports
			.south_data_i_psum(),
			.south_enable_i_psum(),
			
			//Destination ports
			.south_data_o_psum(),
			.south_enable_o_psum(),
			
			
			//Interface with West
			//Source ports
			.west_data_i_psum(), //PE_cluster
			.west_enable_i_psum(),
			
			//Destination ports
//			.west_data_o_psum(GLB_cluster_0.w_data_psum), //GLB_cluster
//			.west_enable_o_psum(GLB_cluster_0.write_en_psum), //GLB_cluster
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_psum(HMNoC_cluster_east_1.west_data_o_psum),
			.east_enable_i_psum(HMNoC_cluster_east_1.west_enable_o_psum),
	        
			//Destination ports
	        .east_data_o_psum(HMNoC_cluster_east_1.west_data_i_psum),
            .east_enable_o_psum(HMNoC_cluster_east_1.west_enable_i_psum),
			
			
			
			//PE Cluster
			.load_en_wght(),
			.load_en_act(),
			.start(),
			.pe_out(),
			.compute_done(),
			.load_done()
		);
		
		
		
	//Instantiation of NORTH_EAST Cluster
	HMNoC_cluster_east 
		#(
			.DATA_BITWIDTH(DATA_BITWIDTH),
			.ADDR_BITWIDTH(ADDR_BITWIDTH),
			
			.DATA_WIDTH(DATA_WIDTH),
			.ADDR_WIDTH(ADDR_WIDTH),
			
			.NUM_GLB_IACT(NUM_GLB_IACT),
			.NUM_GLB_PSUM(NUM_GLB_PSUM),
			.NUM_GLB_WGHT(NUM_GLB_WGHT),

			.kernel_size(kernel_size),
			.act_size(act_size),
			
			.X_dim(X_dim),
			.Y_dim(Y_dim)
		)
	HMNoC_cluster_east_0 
		(
			.clk(clk),   //TestBench/Controller
			.reset(reset),  //TestBench/Controller
			
			//Signals for reading from GLB
			.read_req_iact(),
			.read_req_psum(), //Read by testbench/controller
			.read_req_wght(),
			
//			.r_data_iact(router_cluster_0.r_data_glb_iact),
			.r_data_psum(), //Read by testbench/controller
//			.r_data_wght(router_cluster_0.r_data_glb_wght),
			
			.r_addr_iact(),
			.r_addr_psum(), //testbench for reading final psums
			.r_addr_wght(),

			//Signals for writing to GLB
			.w_addr_iact(), //testbench for writing
			.w_addr_psum(),
			.w_addr_wght(), //testbench for writing

			.w_data_iact(), //testbench for writing
//			.w_data_psum(router_cluster_0.w_data_glb_psum),
			.w_data_wght(), //testbench for writing

			.write_en_iact(), //testbench for writing
//			.write_en_psum(router_cluster_0.write_en_glb_psum),
			.write_en_wght(), //testbench for writing
				
				
	
			//Ports for WGHT router
			.router_mode_wght(), //TB*
			
			//Interface with North
			//Source ports
			.north_data_i_wght(),
			.north_enable_i_wght(),
			
			//Destination ports
			.north_data_o_wght(),
			.north_enable_o_wght(),
			
			
			//Interface with South
			//Source ports
			.south_data_i_wght(HMNoC_cluster_east_1.north_data_o_wght),
			.south_enable_i_wght(HMNoC_cluster_east_1.north_enable_o_wght),
			
			//Destination ports
			.south_data_o_wght(HMNoC_cluster_east_1.north_data_i_wght),
			.south_enable_o_wght(HMNoC_cluster_east_1.north_enable_i_wght),
			
			
			//Interface with West
			//Source ports
			.west_data_i_wght(HMNoC_cluster_west_0.east_data_o_wght), //GLB_cluster
			.west_enable_i_wght(HMNoC_cluster_west_0.east_enable_o_wght),
			
			//Destination ports
			.west_data_o_wght(HMNoC_cluster_west_0.east_data_i_wght),  //PE_cluster
			.west_enable_o_wght(HMNoC_cluster_west_0.east_enable_i_wght),
			
			
			//Interface with East - Devices
			//Source ports
//			.east_data_i_wght(east_data_i_wght),
			.east_enable_i_wght(),
	        
			//Destination ports
//	        .east_data_o_wght(east_data_o_wght),
            .east_enable_o_wght(),
			
		////////////////////////////////////////////
			
		//Ports for IACT router
			.router_mode_iact(),  //TB*
			
			//Interface with North
			//Source ports
			.north_data_i_iact(),
			.north_enable_i_iact(),
			
			//Destination ports
			.north_data_o_iact(),
			.north_enable_o_iact(),
			
			
			//Interface with South
			//Source ports
			.south_data_i_iact(HMNoC_cluster_east_1.north_data_o_iact),
			.south_enable_i_iact(HMNoC_cluster_east_1.north_enable_o_iact),
			
			//Destination ports
			.south_data_o_iact(HMNoC_cluster_east_1.north_data_i_iact),
			.south_enable_o_iact(HMNoC_cluster_east_1.north_enable_i_iact),
			
			
			//Interface with West
			//Source ports
			.west_data_i_iact(HMNoC_cluster_west_0.east_data_o_iact),   //GLB_cluster
			.west_enable_i_iact(HMNoC_cluster_west_0.east_enable_o_iact),
			
			//Destination ports
			.west_data_o_iact(HMNoC_cluster_west_0.east_data_i_iact),  //PE_cluster
			.west_enable_o_iact(HMNoC_cluster_west_0.east_enable_i_iact),
			
			
			//Interface with East - Devices
			//Source ports
//			.east_data_i_iact(east_data_i_iact),
			.east_enable_i_iact(),
	        
			//Destination ports
//	        .east_data_o_iact(east_data_o_iact),
            .east_enable_o_iact(),
		

		////////////////////////////////////////////
			
		//Ports for PSUM router
			.router_mode_psum(),
			
			//Interface with North
			//Source ports
			.north_data_i_psum(),
			.north_enable_i_psum(),
			
			//Destination ports
			.north_data_o_psum(),
			.north_enable_o_psum(),
			
			
			//Interface with South
			//Source ports
			.south_data_i_psum(HMNoC_cluster_east_1.north_data_i_psum),
			.south_enable_i_psum(HMNoC_cluster_east_1.north_enable_i_psum),
			
			//Destination ports
			.south_data_o_psum(HMNoC_cluster_east_1.north_data_o_psum),
			.south_enable_o_psum(HMNoC_cluster_east_1.north_enable_o_psum),
			
			
			//Interface with West
			//Source ports
			.west_data_i_psum(HMNoC_cluster_west_0.east_data_o_psum), //PE_cluster
			.west_enable_i_psum(HMNoC_cluster_west_0.east_enable_o_psum),
			
			//Destination ports
			.west_data_o_psum(HMNoC_cluster_west_0.east_data_i_psum), //GLB_cluster
			.west_enable_o_psum(HMNoC_cluster_west_0.east_enable_i_psum), //GLB_cluster
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_psum(),
			.east_enable_i_psum(),
	        
			//Destination ports
//	        .east_data_o_psum(east_data_o_psum),
//            .east_enable_o_psum(east_enable_o_psum),
			
			
			
			//PE Cluster
			.load_en_wght(),
			.load_en_act(),
			.start(),
			.pe_out(),
			.compute_done(),
			.load_done()
		);
		
	
		//Instantiation of SOUTH_EAST Cluster
	HMNoC_cluster_east 
		#(
			.DATA_BITWIDTH(DATA_BITWIDTH),
			.ADDR_BITWIDTH(ADDR_BITWIDTH),
			
			.DATA_WIDTH(DATA_WIDTH),
			.ADDR_WIDTH(ADDR_WIDTH),
			
			.NUM_GLB_IACT(NUM_GLB_IACT),
			.NUM_GLB_PSUM(NUM_GLB_PSUM),
			.NUM_GLB_WGHT(NUM_GLB_WGHT),

			.kernel_size(kernel_size),
			.act_size(act_size),
			
			.X_dim(X_dim),
			.Y_dim(Y_dim)
		)
	HMNoC_cluster_east_1 
		(
			.clk(clk),   //TestBench/Controller
			.reset(reset),  //TestBench/Controller
			
			//Signals for reading from GLB
			.read_req_iact(),
			.read_req_psum(), //Read by testbench/controller
			.read_req_wght(),
			
//			.r_data_iact(router_cluster_0.r_data_glb_iact),
			.r_data_psum(), //Read by testbench/controller
//			.r_data_wght(router_cluster_0.r_data_glb_wght),
			
			.r_addr_iact(),
			.r_addr_psum(), //testbench for reading final psums
			.r_addr_wght(),

			//Signals for writing to GLB
			.w_addr_iact(), //testbench for writing
			.w_addr_psum(),
			.w_addr_wght(), //testbench for writing

			.w_data_iact(), //testbench for writing
//			.w_data_psum(router_cluster_0.w_data_glb_psum),
			.w_data_wght(), //testbench for writing

			.write_en_iact(), //testbench for writing
//			.write_en_psum(router_cluster_0.write_en_glb_psum),
			.write_en_wght(), //testbench for writing
				
				
	
			//Ports for WGHT router
			.router_mode_wght(), //TB*
			
			//Interface with North
			//Source ports
			.north_data_i_wght(HMNoC_cluster_east_0.south_data_o_wght),
			.north_enable_i_wght(HMNoC_cluster_east_0.south_enable_o_wght),
			
			//Destination ports
			.north_data_o_wght(HMNoC_cluster_east_0.south_data_i_wght),
			.north_enable_o_wght(HMNoC_cluster_east_0.south_enable_i_wght),
			
			
			//Interface with South
			//Source ports
			.south_data_i_wght(),
			.south_enable_i_wght(),
			
			//Destination ports
			.south_data_o_wght(),
			.south_enable_o_wght(),
			
			
			//Interface with West
			//Source ports
			.west_data_i_wght(HMNoC_cluster_west_1.east_data_o_wght), //GLB_cluster
			.west_enable_i_wght(HMNoC_cluster_west_1.east_enable_o_wght),
			
			//Destination ports
			.west_data_o_wght(HMNoC_cluster_west_1.east_data_i_wght),  //PE_cluster
			.west_enable_o_wght(HMNoC_cluster_west_1.east_enable_i_wght),
			
			
			//Interface with East - Devices
			//Source ports
//			.east_data_i_wght(east_data_i_wght),
			.east_enable_i_wght(),
	        
			//Destination ports
//	        .east_data_o_wght(east_data_o_wght),
            .east_enable_o_wght(),
			
		////////////////////////////////////////////
			
		//Ports for IACT router
			.router_mode_iact(router_mode_iact),  //TB*
			
			//Interface with North
			//Source ports
			.north_data_i_iact(HMNoC_cluster_east_0.south_data_o_iact),
			.north_enable_i_iact(HMNoC_cluster_east_0.south_enable_o_iact),
			
			//Destination ports
			.north_data_o_iact(HMNoC_cluster_east_0.south_data_i_iact),
			.north_enable_o_iact(HMNoC_cluster_east_0.south_enable_i_iact),
			
			
			//Interface with South
			//Source ports
			.south_data_i_iact(),
			.south_enable_i_iact(),
			
			//Destination ports
			.south_data_o_iact(),
			.south_enable_o_iact(),
			
			
			//Interface with West
			//Source ports
			.west_data_i_iact(HMNoC_cluster_west_1.east_data_o_iact),   //GLB_cluster
			.west_enable_i_iact(HMNoC_cluster_west_1.east_enable_o_iact),
			
			//Destination ports
			.west_data_o_iact(HMNoC_cluster_west_1.east_data_i_iact),  //PE_cluster
			.west_enable_o_iact(HMNoC_cluster_west_1.east_enable_i_iact),
			
			
			//Interface with East - Devices
			//Source ports
//			.east_data_i_iact(east_data_i_iact),
			.east_enable_i_iact(),
	        
			//Destination ports
//	        .east_data_o_iact(east_data_o_iact),
            .east_enable_o_iact(),
			
			
		////////////////////////////////////////////
			
		//Ports for PSUM router
			.router_mode_psum(),
			
			//Interface with North
			//Source ports
			.north_data_i_psum(HMNoC_cluster_east_0.south_data_o_psum),
			.north_enable_i_psum(HMNoC_cluster_east_0.south_enable_o_psum),
			
			//Destination ports
			.north_data_o_psum(HMNoC_cluster_east_0.south_data_i_psum),
			.north_enable_o_psum(HMNoC_cluster_east_0.south_enable_i_psum),
			
			
			//Interface with South
			//Source ports
			.south_data_i_psum(),
			.south_enable_i_psum(),
			
			//Destination ports
			.south_data_o_psum(),
			.south_enable_o_psum(),
			
			
			//Interface with West
			//Source ports
			.west_data_i_psum(HMNoC_cluster_west_1.east_data_o_psum), //PE_cluster
			.west_enable_i_psum(HMNoC_cluster_west_1.east_enable_o_psum),
			
			//Destination ports
			.west_data_o_psum(HMNoC_cluster_west_1.east_data_i_psum), //GLB_cluster
			.west_enable_o_psum(HMNoC_cluster_west_1.east_enable_i_psum), //GLB_cluster
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_psum(),
			.east_enable_i_psum(),
	        
			//Destination ports
//	        .east_data_o_psum(east_data_o_psum),
//            .east_enable_o_psum(east_enable_o_psum),
			
			
			
			//PE Cluster
			.load_en_wght(),
			.load_en_act(),
			.start(),
			.pe_out(),
			.compute_done(),
			.load_done()
		);
		
		
endmodule


================================================
FILE: rtl/phase_2/router.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/10/2019 03:39:07 AM
// Design Name: 
// Module Name: router
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

module router
	#(
		parameter DATA_WIDTH = 16
	)
	(
		input [3:0] router_mode,
		
		//Interface with North
		//Source ports
		input [DATA_WIDTH-1:0] north_data_i,
		input north_enable_i,
//		output logic north_ready_o,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] north_data_o,
		output logic north_enable_o,
//		input north_ready_i,
		
		
		//Interface with South
		//Source ports
		input [DATA_WIDTH-1:0] south_data_i,
		input south_enable_i,
//		output logic south_ready_o,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] south_data_o,
		output logic south_enable_o,
//		input south_ready_i,
		
		
		//Interface with West
		//Source ports
		input [DATA_WIDTH-1:0] west_data_i,
		input west_enable_i,
//		output logic west_ready_o,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] west_data_o,
		output logic west_enable_o,
//		input west_ready_i,
		
		
		//Interface with East - Devices
		//Source ports
		input [DATA_WIDTH-1:0] east_data_i,
		input east_enable_i,
//		output logic east_ready_o,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] east_data_o,
		output logic east_enable_o
//		input east_ready_i
    );
	
	logic [DATA_WIDTH-1:0] data_out;
	enum logic [3:0] {ALL=0, NORTH=1, SOUTH=2, WEST=3, EAST=4,
						EASTNORTH=5, EASTSOUTH=6, EASTWEST=7,
						WESTNORTH=8, WESTSOUTH=9, WESTEAST=10} direction;
	
	//Logic for selecting data_out based on enable
	always_comb
		begin:data_switch
			unique if(north_enable_i)
				data_out = north_data_i;
			else if(south_enable_i)
				data_out = south_data_i;
			else if(west_enable_i)
				data_out = west_data_i;
			else if(east_enable_i)
				data_out = east_data_i;
			else
				data_out = 10101; //Default value for verification
		end
	
	//Logic for data out in destination ports based on routing_mode
	always_comb
		begin: routing_logic
			case(router_mode)
				ALL:begin
					north_data_o = data_out;
					north_enable_o = 1;
					
					south_data_o = data_out;
					south_enable_o = 1;
					
					west_data_o = data_out;
					west_enable_o = 1;
					
					east_data_o = data_out;
					east_enable_o = 1;
				end
				
				NORTH:begin
					north_data_o = data_out;
					south_data_o = 'X;
					east_data_o = 'X;
					west_data_o = 'X;
					
					north_enable_o = 1;
					south_enable_o = 0;
					west_enable_o = 0;
					east_enable_o = 0;
				end
				
				SOUTH:begin
					south_data_o = data_out;
					north_data_o = 'X;
					east_data_o = 'X;
					west_data_o = 'X;
					
					north_enable_o = 0;
					south_enable_o = 1;
					west_enable_o = 0;
					east_enable_o = 0;
				end
				
				WEST:begin
					west_data_o = data_out;
					south_data_o = 'X;
					east_data_o = 'X;
					north_data_o = 'X;
					
					north_enable_o = 0;
					south_enable_o = 0;
					west_enable_o = 1;
					east_enable_o = 0;
				end
				
				EAST:begin
					east_data_o = data_out;
					south_data_o = 'X;
					north_data_o = 'X;
					west_data_o = 'X;
					
					north_enable_o = 0;
					south_enable_o = 0;
					west_enable_o = 0;
					east_enable_o = 1;
				end
				
				//Two Directions - Used for storing in PE cluster and routing
				//With East as compute unit
				EASTNORTH:begin
					east_data_o = data_out;
					north_data_o = data_out;
					south_data_o = 'X;
					west_data_o = 'X;
					
					north_enable_o = 1;
					south_enable_o = 0;
					west_enable_o = 0;
					east_enable_o = 1;
				end
				
				EASTSOUTH:begin
					east_data_o = data_out;
					south_data_o = data_out;
					north_data_o = 'X;
					west_data_o = 'X;
					
					north_enable_o = 0;
					south_enable_o = 1;
					west_enable_o = 0;
					east_enable_o = 1;
				end
				
				EASTWEST:begin
					east_data_o = data_out;
					west_data_o = data_out;
					south_data_o = 'X;
					north_data_o = 'X;
					
					north_enable_o = 0;
					south_enable_o = 0;
					west_enable_o = 1;
					east_enable_o = 1;
				end
				
				//With West as compute unit
				WESTNORTH:begin
					west_data_o = data_out;
					north_data_o = data_out;
					south_data_o = 'X;
					east_data_o = 'X;
					
					north_enable_o = 1;
					south_enable_o = 0;
					west_enable_o = 1;
					east_enable_o = 0;
				end
				
				WESTSOUTH:begin
					west_data_o = data_out;
					south_data_o = data_out;
					north_data_o = 'X;
					east_data_o = 'X;
					
					north_enable_o = 0;
					south_enable_o = 1;
					west_enable_o = 1;
					east_enable_o = 0;
				end
				
				WESTEAST:begin
					west_data_o = data_out;
					east_data_o = data_out;
					south_data_o = 'X;
					north_data_o = 'X;
					
					north_enable_o = 0;
					south_enable_o = 0;
					west_enable_o = 1;
					east_enable_o = 1;
				end
				
				default: begin
					north_data_o = 'X;
					east_data_o = 'X;
					south_data_o = 'X;
					west_data_o = 'X;
					
					north_enable_o = 0;
					south_enable_o = 0;
					west_enable_o = 0;
					east_enable_o = 0;
				end
			endcase
		end

endmodule


================================================
FILE: rtl/phase_2/router_cluster.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/03/2019 02:24:04 PM
// Design Name: 
// Module Name: router_cluster
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_cluster	
	#(
		parameter DATA_WIDTH = 16
	)
	(
	
	//WGHT Router Ports
		input [3:0] router_mode_wght,
		
		//Interface with North
		//Source ports
		input [DATA_WIDTH-1:0] north_data_i_wght,
		input north_enable_i_wght,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] north_data_o_wght,
		output logic north_enable_o_wght,
		
		
		//Interface with South
		//Source ports
		input [DATA_WIDTH-1:0] south_data_i_wght,
		input south_enable_i_wght,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] south_data_o_wght,
		output logic south_enable_o_wght,
		
		
		//Interface with West
		//Source ports
		input [DATA_WIDTH-1:0] west_data_i_wght,
		input west_enable_i_wght,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] west_data_o_wght,
		output logic west_enable_o_wght,
		
		
		//Interface with East - Devices
		//Source ports
		input [DATA_WIDTH-1:0] east_data_i_wght,
		input east_enable_i_wght,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] east_data_o_wght,
		output logic east_enable_o_wght,
		
	//IACT Router Ports
		input [3:0] router_mode_iact,
		
		//Interface with North
		//Source ports
		input [DATA_WIDTH-1:0] north_data_i_iact,
		input north_enable_i_iact,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] north_data_o_iact,
		output logic north_enable_o_iact,
		
		
		//Interface with South
		//Source ports
		input [DATA_WIDTH-1:0] south_data_i_iact,
		input south_enable_i_iact,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] south_data_o_iact,
		output logic south_enable_o_iact,
		
		
		//Interface with West
		//Source ports
		input [DATA_WIDTH-1:0] west_data_i_iact,
		input west_enable_i_iact,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] west_data_o_iact,
		output logic west_enable_o_iact,
		
		
		//Interface with East - Devices
		//Source ports
		input [DATA_WIDTH-1:0] east_data_i_iact,
		input east_enable_i_iact,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] east_data_o_iact,
		output logic east_enable_o_iact,
		
	
	//PSUM Router Ports
		input [3:0] router_mode_psum,
		
		//Interface with North
		//Source ports
		input [DATA_WIDTH-1:0] north_data_i_psum,
		input north_enable_i_psum,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] north_data_o_psum,
		output logic north_enable_o_psum,
		
		
		//Interface with South
		//Source ports
		input [DATA_WIDTH-1:0] south_data_i_psum,
		input south_enable_i_psum,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] south_data_o_psum,
		output logic south_enable_o_psum,
		
		
		//Interface with West
		//Source ports
		input [DATA_WIDTH-1:0] west_data_i_psum,
		input west_enable_i_psum,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] west_data_o_psum,
		output logic west_enable_o_psum,
		
		
		//Interface with East - Devices
		//Source ports
		input [DATA_WIDTH-1:0] east_data_i_psum,
		input east_enable_i_psum,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] east_data_o_psum,
		output logic east_enable_o_psum
	);
	
	
	
	router
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_wght
		(
			.router_mode(router_mode_wght),
			
			//Interface with North
			//Source ports
			.north_data_i(north_data_i_wght),
			.north_enable_i(north_enable_i_wght),
			
			//Destination ports
			.north_data_o(north_data_o_wght),
			.north_enable_o(north_enable_o_wght),
			
			
			//Interface with South
			//Source ports
			.south_data_i(south_data_i_wght),
			.south_enable_i(south_enable_i_wght),
			
			//Destination ports
			.south_data_o(south_data_o_wght),
			.south_enable_o(south_enable_o_wght),
			
			
			//Interface with West
			//Source ports
			.west_data_i(west_data_i_wght),
			.west_enable_i(west_enable_i_wght),
			
			//Destination ports
			.west_data_o(west_data_o_wght),
			.west_enable_o(west_enable_o_wght),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i(east_data_i_wght),
			.east_enable_i(east_enable_i_wght),
	        
			//Destination ports
	        .east_data_o(east_data_o_wght),
            .east_enable_o(east_enable_o_wght)
	);
	
	
	router
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_iact
		(
			.router_mode(router_mode_iact),
			
			//Interface with North
			//Source ports
			.north_data_i(north_data_i_iact),
			.north_enable_i(north_enable_i_iact),
			
			//Destination ports
			.north_data_o(north_data_o_iact),
			.north_enable_o(north_enable_o_iact),
			
			
			//Interface with South
			//Source ports
			.south_data_i(south_data_i_iact),
			.south_enable_i(south_enable_i_iact),
			
			//Destination ports
			.south_data_o(south_data_o_iact),
			.south_enable_o(south_enable_o_iact),
			
			
			//Interface with West
			//Source ports
			.west_data_i(west_data_i_iact),
			.west_enable_i(west_enable_i_iact),
			
			//Destination ports
			.west_data_o(west_data_o_iact),
			.west_enable_o(west_enable_o_iact),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i(east_data_i_iact),
			.east_enable_i(east_enable_i_iact),
	        
			//Destination ports
	        .east_data_o(east_data_o_iact),
            .east_enable_o(east_enable_o_iact)
	);
	
	
	router
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_psum
		(
			.router_mode(router_mode_psum),
			
			//Interface with North
			//Source ports
			.north_data_i(north_data_i_psum),
			.north_enable_i(north_enable_i_psum),
			
			//Destination ports
			.north_data_o(north_data_o_psum),
			.north_enable_o(north_enable_o_psum),
			
			
			//Interface with South
			//Source ports
			.south_data_i(south_data_i_psum),
			.south_enable_i(south_enable_i_psum),
			
			//Destination ports
			.south_data_o(south_data_o_psum),
			.south_enable_o(south_enable_o_psum),
			
			
			//Interface with West
			//Source ports
			.west_data_i(west_data_i_psum),
			.west_enable_i(west_enable_i_psum),
			
			//Destination ports
			.west_data_o(west_data_o_psum),
			.west_enable_o(west_enable_o_psum),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i(east_data_i_psum),
			.east_enable_i(east_enable_i_psum),
	        
			//Destination ports
	        .east_data_o(east_data_o_psum),
            .east_enable_o(east_enable_o_psum)
	);
	
	
endmodule


================================================
FILE: rtl/phase_3/router.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/10/2019 03:39:07 AM
// Design Name: 
// Module Name: router
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

module router
	#(
		parameter DATA_WIDTH = 16
	)
	(
		input [3:0] router_mode,
		
		//Interface with North
		//Source ports
		input [DATA_WIDTH-1:0] north_data_i,
		input north_enable_i,
//		output logic north_ready_o,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] north_data_o,
		output logic north_enable_o,
//		input north_ready_i,
		
		
		//Interface with South
		//Source ports
		input [DATA_WIDTH-1:0] south_data_i,
		input south_enable_i,
//		output logic south_ready_o,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] south_data_o,
		output logic south_enable_o,
//		input south_ready_i,
		
		
		//Interface with West
		//Source ports
		input [DATA_WIDTH-1:0] west_data_i,
		input west_enable_i,
//		output logic west_ready_o,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] west_data_o,
		output logic west_enable_o,
//		input west_ready_i,
		
		
		//Interface with East - Devices
		//Source ports
		input [DATA_WIDTH-1:0] east_data_i,
		input east_enable_i,
//		output logic east_ready_o,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] east_data_o,
		output logic east_enable_o
//		input east_ready_i
    );
	
	logic [DATA_WIDTH-1:0] data_out;
	enum logic [3:0] {ALL=0, NORTH=1, SOUTH=2, WEST=3, EAST=4,
						EASTNORTH=5, EASTSOUTH=6, EASTWEST=7,
						WESTNORTH=8, WESTSOUTH=9, WESTEAST=10} direction;
	
	//Logic for selecting data_out based on enable
	always_comb
		begin:data_switch
			unique if(north_enable_i)
				data_out = north_data_i;
			else if(south_enable_i)
				data_out = south_data_i;
			else if(west_enable_i)
				data_out = west_data_i;
			else if(east_enable_i)
				data_out = east_data_i;
			else
				data_out = 10101; //Default value for verification
		end
	
	//Logic for data out in destination ports based on routing_mode
	always_comb
		begin: routing_logic
			case(router_mode)
				ALL:begin
					north_data_o = data_out;
					north_enable_o = 1;
					
					south_data_o = data_out;
					south_enable_o = 1;
					
					west_data_o = data_out;
					west_enable_o = 1;
					
					east_data_o = data_out;
					east_enable_o = 1;
				end
				
				NORTH:begin
					north_data_o = data_out;
					south_data_o = 'X;
					east_data_o = 'X;
					west_data_o = 'X;
					
					north_enable_o = 1;
					south_enable_o = 0;
					west_enable_o = 0;
					east_enable_o = 0;
				end
				
				SOUTH:begin
					south_data_o = data_out;
					north_data_o = 'X;
					east_data_o = 'X;
					west_data_o = 'X;
					
					north_enable_o = 0;
					south_enable_o = 1;
					west_enable_o = 0;
					east_enable_o = 0;
				end
				
				WEST:begin
					west_data_o = data_out;
					south_data_o = 'X;
					east_data_o = 'X;
					north_data_o = 'X;
					
					north_enable_o = 0;
					south_enable_o = 0;
					west_enable_o = 1;
					east_enable_o = 0;
				end
				
				EAST:begin
					east_data_o = data_out;
					south_data_o = 'X;
					north_data_o = 'X;
					west_data_o = 'X;
					
					north_enable_o = 0;
					south_enable_o = 0;
					west_enable_o = 0;
					east_enable_o = 1;
				end
				
				//Two Directions - Used for storing in PE cluster and routing
				//With East as compute unit
				EASTNORTH:begin
					east_data_o = data_out;
					north_data_o = data_out;
					south_data_o = 'X;
					west_data_o = 'X;
					
					north_enable_o = 1;
					south_enable_o = 0;
					west_enable_o = 0;
					east_enable_o = 1;
				end
				
				EASTSOUTH:begin
					east_data_o = data_out;
					south_data_o = data_out;
					north_data_o = 'X;
					west_data_o = 'X;
					
					north_enable_o = 0;
					south_enable_o = 1;
					west_enable_o = 0;
					east_enable_o = 1;
				end
				
				EASTWEST:begin
					east_data_o = data_out;
					west_data_o = data_out;
					south_data_o = 'X;
					north_data_o = 'X;
					
					north_enable_o = 0;
					south_enable_o = 0;
					west_enable_o = 1;
					east_enable_o = 1;
				end
				
				//With West as compute unit
				WESTNORTH:begin
					west_data_o = data_out;
					north_data_o = data_out;
					south_data_o = 'X;
					east_data_o = 'X;
					
					north_enable_o = 1;
					south_enable_o = 0;
					west_enable_o = 1;
					east_enable_o = 0;
				end
				
				WESTSOUTH:begin
					west_data_o = data_out;
					south_data_o = data_out;
					north_data_o = 'X;
					east_data_o = 'X;
					
					north_enable_o = 0;
					south_enable_o = 1;
					west_enable_o = 1;
					east_enable_o = 0;
				end
				
				WESTEAST:begin
					west_data_o = data_out;
					east_data_o = data_out;
					south_data_o = 'X;
					north_data_o = 'X;
					
					north_enable_o = 0;
					south_enable_o = 0;
					west_enable_o = 1;
					east_enable_o = 1;
				end
				
				default: begin
					north_data_o = 'X;
					east_data_o = 'X;
					south_data_o = 'X;
					west_data_o = 'X;
					
					north_enable_o = 0;
					south_enable_o = 0;
					west_enable_o = 0;
					east_enable_o = 0;
				end
			endcase
		end

endmodule


================================================
FILE: rtl/phase_3/router_cluster.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/03/2019 02:24:04 PM
// Design Name: 
// Module Name: router_cluster
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_cluster	
	#(
		parameter DATA_WIDTH = 16
	)
	(
	
	//WGHT Router Ports
		input [3:0] router_mode_wght,
		
		//Interface with North
		//Source ports
		input [DATA_WIDTH-1:0] north_data_i_wght,
		input north_enable_i_wght,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] north_data_o_wght,
		output logic north_enable_o_wght,
		
		
		//Interface with South
		//Source ports
		input [DATA_WIDTH-1:0] south_data_i_wght,
		input south_enable_i_wght,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] south_data_o_wght,
		output logic south_enable_o_wght,
		
		
		//Interface with West
		//Source ports
		input [DATA_WIDTH-1:0] west_data_i_wght,
		input west_enable_i_wght,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] west_data_o_wght,
		output logic west_enable_o_wght,
		
		
		//Interface with East - Devices
		//Source ports
		input [DATA_WIDTH-1:0] east_data_i_wght,
		input east_enable_i_wght,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] east_data_o_wght,
		output logic east_enable_o_wght,
		
	//IACT Router Ports
		input [3:0] router_mode_iact,
		
		//Interface with North
		//Source ports
		input [DATA_WIDTH-1:0] north_data_i_iact,
		input north_enable_i_iact,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] north_data_o_iact,
		output logic north_enable_o_iact,
		
		
		//Interface with South
		//Source ports
		input [DATA_WIDTH-1:0] south_data_i_iact,
		input south_enable_i_iact,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] south_data_o_iact,
		output logic south_enable_o_iact,
		
		
		//Interface with West
		//Source ports
		input [DATA_WIDTH-1:0] west_data_i_iact,
		input west_enable_i_iact,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] west_data_o_iact,
		output logic west_enable_o_iact,
		
		
		//Interface with East - Devices
		//Source ports
		input [DATA_WIDTH-1:0] east_data_i_iact,
		input east_enable_i_iact,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] east_data_o_iact,
		output logic east_enable_o_iact,
		
	
	//PSUM Router Ports
		input [3:0] router_mode_psum,
		
		//Interface with North
		//Source ports
		input [DATA_WIDTH-1:0] north_data_i_psum,
		input north_enable_i_psum,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] north_data_o_psum,
		output logic north_enable_o_psum,
		
		
		//Interface with South
		//Source ports
		input [DATA_WIDTH-1:0] south_data_i_psum,
		input south_enable_i_psum,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] south_data_o_psum,
		output logic south_enable_o_psum,
		
		
		//Interface with West
		//Source ports
		input [DATA_WIDTH-1:0] west_data_i_psum,
		input west_enable_i_psum,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] west_data_o_psum,
		output logic west_enable_o_psum,
		
		
		//Interface with East - Devices
		//Source ports
		input [DATA_WIDTH-1:0] east_data_i_psum,
		input east_enable_i_psum,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] east_data_o_psum,
		output logic east_enable_o_psum
	);
	
	
	
	router
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_wght
		(
			.router_mode(router_mode_wght),
			
			//Interface with North
			//Source ports
			.north_data_i(north_data_i_wght),
			.north_enable_i(north_enable_i_wght),
			
			//Destination ports
			.north_data_o(north_data_o_wght),
			.north_enable_o(north_enable_o_wght),
			
			
			//Interface with South
			//Source ports
			.south_data_i(south_data_i_wght),
			.south_enable_i(south_enable_i_wght),
			
			//Destination ports
			.south_data_o(south_data_o_wght),
			.south_enable_o(south_enable_o_wght),
			
			
			//Interface with West
			//Source ports
			.west_data_i(west_data_i_wght),
			.west_enable_i(west_enable_i_wght),
			
			//Destination ports
			.west_data_o(west_data_o_wght),
			.west_enable_o(west_enable_o_wght),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i(east_data_i_wght),
			.east_enable_i(east_enable_i_wght),
	        
			//Destination ports
	        .east_data_o(east_data_o_wght),
            .east_enable_o(east_enable_o_wght)
	);
	
	
	router
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_iact
		(
			.router_mode(router_mode_iact),
			
			//Interface with North
			//Source ports
			.north_data_i(north_data_i_iact),
			.north_enable_i(north_enable_i_iact),
			
			//Destination ports
			.north_data_o(north_data_o_iact),
			.north_enable_o(north_enable_o_iact),
			
			
			//Interface with South
			//Source ports
			.south_data_i(south_data_i_iact),
			.south_enable_i(south_enable_i_iact),
			
			//Destination ports
			.south_data_o(south_data_o_iact),
			.south_enable_o(south_enable_o_iact),
			
			
			//Interface with West
			//Source ports
			.west_data_i(west_data_i_iact),
			.west_enable_i(west_enable_i_iact),
			
			//Destination ports
			.west_data_o(west_data_o_iact),
			.west_enable_o(west_enable_o_iact),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i(east_data_i_iact),
			.east_enable_i(east_enable_i_iact),
	        
			//Destination ports
	        .east_data_o(east_data_o_iact),
            .east_enable_o(east_enable_o_iact)
	);
	
	
	router
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_psum
		(
			.router_mode(router_mode_psum),
			
			//Interface with North
			//Source ports
			.north_data_i(north_data_i_psum),
			.north_enable_i(north_enable_i_psum),
			
			//Destination ports
			.north_data_o(north_data_o_psum),
			.north_enable_o(north_enable_o_psum),
			
			
			//Interface with South
			//Source ports
			.south_data_i(south_data_i_psum),
			.south_enable_i(south_enable_i_psum),
			
			//Destination ports
			.south_data_o(south_data_o_psum),
			.south_enable_o(south_enable_o_psum),
			
			
			//Interface with West
			//Source ports
			.west_data_i(west_data_i_psum),
			.west_enable_i(west_enable_i_psum),
			
			//Destination ports
			.west_data_o(west_data_o_psum),
			.west_enable_o(west_enable_o_psum),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i(east_data_i_psum),
			.east_enable_i(east_enable_i_psum),
	        
			//Destination ports
	        .east_data_o(east_data_o_psum),
            .east_enable_o(east_enable_o_psum)
	);
	
	
endmodule


================================================
FILE: rtl/phase_3/router_network4.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/13/2019 05:43:25 AM
// Design Name: 
// Module Name: router_network4
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_network4
	#(
		parameter DATA_WIDTH = 16
	)
	(
	
	
		///////////////      ROUTER WEST 0      ///////////////////////////////////

	input [3:0] router_mode_west_0,
	
	//Interface with West
	//Source ports
	input [DATA_WIDTH-1:0] west_data_i_west_0,
	input west_enable_i_west_0,
	
	//Destination ports
	output [DATA_WIDTH-1:0] west_data_o_west_0,
	output west_enable_o_west_0,


	
		
		///////////////      ROUTER WEST 1     ///////////////////////////////////
	
	input [3:0] router_mode_west_1,
	
	
	//Interface with West
	//Source ports
	input [DATA_WIDTH-1:0] west_data_i_west_1,
	input west_enable_i_west_1,
	
	//Destination ports
	output [DATA_WIDTH-1:0] west_data_o_west_1,
	output west_enable_o_west_1,

	
	
	
		///////////////      ROUTER EAST 0    ///////////////////////////////////
	
	input [3:0] router_mode_east_0,
	
	
	//Interface with East
	//Source ports
	input [DATA_WIDTH-1:0] east_data_i_east_0,
	input east_enable_i_east_0,

	//Destination ports
	output [DATA_WIDTH-1:0] east_data_o_east_0,
	output east_enable_o_east_0,
	
	
		///////////////      ROUTER EAST 1     ///////////////////////////////////
	
	input [3:0] router_mode_east_1,
	
	
	//Interface with East
	//Source ports
	input [DATA_WIDTH-1:0] east_data_i_east_1,
	input east_enable_i_east_1,

	//Destination ports
	output [DATA_WIDTH-1:0] east_data_o_east_1,
	output east_enable_o_east_1


	);


	
	router 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_west_0
		(
			.router_mode(router_mode_west_0),
			
			
			//Interface with North
			//Source ports
			.north_data_i(),
			.north_enable_i(),
			
			//Destination ports
			.north_data_o(),
			.north_enable_o(),
			
			
			//Interface with South
			//Source ports
			.south_data_i(router_west_1.north_data_o),
			.south_enable_i(router_west_1.north_enable_o),
			
			//Destination ports
			.south_data_o(router_west_1.north_data_i),
			.south_enable_o(router_west_1.north_enable_i),
			
			
			//Interface with West
			//Source ports
			.west_data_i(west_data_i_west_0),
			.west_enable_i(west_enable_i_west_0),
			
			//Destination ports
			.west_data_o(west_data_o_west_0),
			.west_enable_o(west_enable_o_west_0),
			
			
			//Interface with East
			//Source ports
			.east_data_i(router_east_0.west_data_o),
			.east_enable_i(router_east_0.west_enable_o),
	        
			//Destination ports
	        .east_data_o(router_east_0.west_data_i),
            .east_enable_o(router_east_0.west_enable_i)
		);
	
	

	
	router 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_west_1
		(
			.router_mode(router_mode_west_1),
			
			
			//Interface with North
			//Source ports
			.north_data_i(router_west_0.south_data_o),
			.north_enable_i(router_west_0.south_enable_o),
			
			//Destination ports
			.north_data_o(router_west_0.south_data_i),
			.north_enable_o(router_west_0.south_enable_i),
			
			
			//Interface with South
			//Source ports
			.south_data_i(),
			.south_enable_i(),
			
			//Destination ports
			.south_data_o(),
			.south_enable_o(),
			
			
			//Interface with West
			//Source ports
			.west_data_i(west_data_i_west_1),
			.west_enable_i(west_enable_i_west_1),
			
			//Destination ports
			.west_data_o(west_data_o_west_1),
			.west_enable_o(west_enable_o_west_1),
			
			
			//Interface with East
			//Source ports
			.east_data_i(router_east_1.west_data_o),
			.east_enable_i(router_east_1.west_enable_o),
	        
			//Destination ports
	        .east_data_o(router_east_1.west_data_i),
            .east_enable_o(router_east_1.west_enable_i)
		);
		
	
	

	
	
	router 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_east_0
		(
			.router_mode(router_mode_east_0),
			
			
			//Interface with North
			//Source ports
			.north_data_i(),
			.north_enable_i(),
			
			//Destination ports
			.north_data_o(),
			.north_enable_o(),
			
			
			//Interface with South
			//Source ports
			.south_data_i(router_east_1.north_data_o),
			.south_enable_i(router_east_1.north_enable_o),
			
			//Destination ports
			.south_data_o(router_east_1.north_data_i),
			.south_enable_o(router_east_1.north_enable_i),
			
			
			//Interface with West
			//Source ports
			.west_data_i(router_west_0.east_data_o),
			.west_enable_i(router_west_0.east_enable_o),
			
			//Destination ports
			.west_data_o(router_west_0.east_data_i),
			.west_enable_o(router_west_0.east_enable_i),
			
			
			//Interface with East
			//Source ports
			.east_data_i(east_data_i_east_0),
			.east_enable_i(east_enable_i_east_0),
	        
			//Destination ports
	        .east_data_o(east_data_o_east_0),
            .east_enable_o(east_enable_o_east_0)
		);
		
		
		

	router 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_east_1
		(
			.router_mode(router_mode_east_1),
			
			
			//Interface with North
			//Source ports
			.north_data_i(router_east_0.south_data_o),
			.north_enable_i(router_east_0.south_enable_o),
			
			//Destination ports
			.north_data_o(router_east_0.south_data_i),
			.north_enable_o(router_east_0.south_enable_i),
			
			
			//Interface with South
			//Source ports
			.south_data_i(),
			.south_enable_i(),
			
			//Destination ports
			.south_data_o(),
			.south_enable_o(),
			
			
			//Interface with West
			//Source ports
			.west_data_i(router_west_1.east_data_o),
			.west_enable_i(router_west_1.east_enable_o),
			
			//Destination ports
			.west_data_o(router_west_1.east_data_i),
			.west_enable_o(router_west_1.east_enable_i),
			
			
			//Interface with East
			//Source ports
			.east_data_i(east_data_i_east_1),
			.east_enable_i(east_enable_i_east_1),
	        
			//Destination ports
	        .east_data_o(east_data_o_east_1),
            .east_enable_o(east_enable_o_east_1)
		);
		
endmodule


================================================
FILE: rtl/router.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/10/2019 03:39:07 AM
// Design Name: 
// Module Name: router
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

module router
	#(
		parameter DATA_WIDTH = 16
	)
	(
		input [3:0] router_mode,
		
		//Interface with North
		//Source ports
		input [DATA_WIDTH-1:0] north_data_i,
		input north_enable_i,
//		output logic north_ready_o,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] north_data_o,
		output logic north_enable_o,
//		input north_ready_i,
		
		
		//Interface with South
		//Source ports
		input [DATA_WIDTH-1:0] south_data_i,
		input south_enable_i,
//		output logic south_ready_o,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] south_data_o,
		output logic south_enable_o,
//		input south_ready_i,
		
		
		//Interface with West
		//Source ports
		input [DATA_WIDTH-1:0] west_data_i,
		input west_enable_i,
//		output logic west_ready_o,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] west_data_o,
		output logic west_enable_o,
//		input west_ready_i,
		
		
		//Interface with East - Devices
		//Source ports
		input [DATA_WIDTH-1:0] east_data_i,
		input east_enable_i,
//		output logic east_ready_o,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] east_data_o,
		output logic east_enable_o
//		input east_ready_i
    );
	
	logic [DATA_WIDTH-1:0] data_out;
	enum logic [3:0] {ALL=0, NORTH=1, SOUTH=2, WEST=3, EAST=4,
						EASTNORTH=5, EASTSOUTH=6, EASTWEST=7,
						WESTNORTH=8, WESTSOUTH=9, WESTEAST=10} direction;
	
	//Logic for selecting data_out based on enable
	always_comb
		begin:data_switch
			unique if(north_enable_i)
				data_out = north_data_i;
			else if(south_enable_i)
				data_out = south_data_i;
			else if(west_enable_i)
				data_out = west_data_i;
			else if(east_enable_i)
				data_out = east_data_i;
			else
				data_out = 10101; //Default value for verification
		end
	
	//Logic for data out in destination ports based on routing_mode
	always_comb
		begin: routing_logic
			case(router_mode)
				ALL:begin
					north_data_o = data_out;
					north_enable_o = 1;
					
					south_data_o = data_out;
					south_enable_o = 1;
					
					west_data_o = data_out;
					west_enable_o = 1;
					
					east_data_o = data_out;
					east_enable_o = 1;
				end
				
				NORTH:begin
					north_data_o = data_out;
					south_data_o = 'X;
					east_data_o = 'X;
					west_data_o = 'X;
					
					north_enable_o = 1;
					south_enable_o = 0;
					west_enable_o = 0;
					east_enable_o = 0;
				end
				
				SOUTH:begin
					south_data_o = data_out;
					north_data_o = 'X;
					east_data_o = 'X;
					west_data_o = 'X;
					
					north_enable_o = 0;
					south_enable_o = 1;
					west_enable_o = 0;
					east_enable_o = 0;
				end
				
				WEST:begin
					west_data_o = data_out;
					south_data_o = 'X;
					east_data_o = 'X;
					north_data_o = 'X;
					
					north_enable_o = 0;
					south_enable_o = 0;
					west_enable_o = 1;
					east_enable_o = 0;
				end
				
				EAST:begin
					east_data_o = data_out;
					south_data_o = 'X;
					north_data_o = 'X;
					west_data_o = 'X;
					
					north_enable_o = 0;
					south_enable_o = 0;
					west_enable_o = 0;
					east_enable_o = 1;
				end
				
				//Two Directions - Used for storing in PE cluster and routing
				//With East as compute unit
				EASTNORTH:begin
					east_data_o = data_out;
					north_data_o = data_out;
					south_data_o = 'X;
					west_data_o = 'X;
					
					north_enable_o = 1;
					south_enable_o = 0;
					west_enable_o = 0;
					east_enable_o = 1;
				end
				
				EASTSOUTH:begin
					east_data_o = data_out;
					south_data_o = data_out;
					north_data_o = 'X;
					west_data_o = 'X;
					
					north_enable_o = 0;
					south_enable_o = 1;
					west_enable_o = 0;
					east_enable_o = 1;
				end
				
				EASTWEST:begin
					east_data_o = data_out;
					west_data_o = data_out;
					south_data_o = 'X;
					north_data_o = 'X;
					
					north_enable_o = 0;
					south_enable_o = 0;
					west_enable_o = 1;
					east_enable_o = 1;
				end
				
				//With West as compute unit
				WESTNORTH:begin
					west_data_o = data_out;
					north_data_o = data_out;
					south_data_o = 'X;
					east_data_o = 'X;
					
					north_enable_o = 1;
					south_enable_o = 0;
					west_enable_o = 1;
					east_enable_o = 0;
				end
				
				WESTSOUTH:begin
					west_data_o = data_out;
					south_data_o = data_out;
					north_data_o = 'X;
					east_data_o = 'X;
					
					north_enable_o = 0;
					south_enable_o = 1;
					west_enable_o = 1;
					east_enable_o = 0;
				end
				
				WESTEAST:begin
					west_data_o = data_out;
					east_data_o = data_out;
					south_data_o = 'X;
					north_data_o = 'X;
					
					north_enable_o = 0;
					south_enable_o = 0;
					west_enable_o = 1;
					east_enable_o = 1;
				end
				
				default: begin
					north_data_o = 'X;
					east_data_o = 'X;
					south_data_o = 'X;
					west_data_o = 'X;
					
					north_enable_o = 0;
					south_enable_o = 0;
					west_enable_o = 0;
					east_enable_o = 0;
				end
			endcase
		end

endmodule


================================================
FILE: rtl/router_cluster.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/03/2019 02:24:04 PM
// Design Name: 
// Module Name: router_cluster
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_cluster	
	#(
		parameter DATA_WIDTH = 16
	)
	(
	
	//WGHT Router Ports
		input [3:0] router_mode_wght,
		
		//Interface with North
		//Source ports
		input [DATA_WIDTH-1:0] north_data_i_wght,
		input north_enable_i_wght,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] north_data_o_wght,
		output logic north_enable_o_wght,
		
		
		//Interface with South
		//Source ports
		input [DATA_WIDTH-1:0] south_data_i_wght,
		input south_enable_i_wght,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] south_data_o_wght,
		output logic south_enable_o_wght,
		
		
		//Interface with West
		//Source ports
		input [DATA_WIDTH-1:0] west_data_i_wght,
		input west_enable_i_wght,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] west_data_o_wght,
		output logic west_enable_o_wght,
		
		
		//Interface with East - Devices
		//Source ports
		input [DATA_WIDTH-1:0] east_data_i_wght,
		input east_enable_i_wght,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] east_data_o_wght,
		output logic east_enable_o_wght,
		
	//IACT Router Ports
		input [3:0] router_mode_iact,
		
		//Interface with North
		//Source ports
		input [DATA_WIDTH-1:0] north_data_i_iact,
		input north_enable_i_iact,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] north_data_o_iact,
		output logic north_enable_o_iact,
		
		
		//Interface with South
		//Source ports
		input [DATA_WIDTH-1:0] south_data_i_iact,
		input south_enable_i_iact,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] south_data_o_iact,
		output logic south_enable_o_iact,
		
		
		//Interface with West
		//Source ports
		input [DATA_WIDTH-1:0] west_data_i_iact,
		input west_enable_i_iact,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] west_data_o_iact,
		output logic west_enable_o_iact,
		
		
		//Interface with East - Devices
		//Source ports
		input [DATA_WIDTH-1:0] east_data_i_iact,
		input east_enable_i_iact,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] east_data_o_iact,
		output logic east_enable_o_iact,
		
	
	//PSUM Router Ports
		input [3:0] router_mode_psum,
		
		//Interface with North
		//Source ports
		input [DATA_WIDTH-1:0] north_data_i_psum,
		input north_enable_i_psum,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] north_data_o_psum,
		output logic north_enable_o_psum,
		
		
		//Interface with South
		//Source ports
		input [DATA_WIDTH-1:0] south_data_i_psum,
		input south_enable_i_psum,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] south_data_o_psum,
		output logic south_enable_o_psum,
		
		
		//Interface with West
		//Source ports
		input [DATA_WIDTH-1:0] west_data_i_psum,
		input west_enable_i_psum,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] west_data_o_psum,
		output logic west_enable_o_psum,
		
		
		//Interface with East - Devices
		//Source ports
		input [DATA_WIDTH-1:0] east_data_i_psum,
		input east_enable_i_psum,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] east_data_o_psum,
		output logic east_enable_o_psum
	);
	
	
	
	router
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_wght
		(
			.router_mode(router_mode_wght),
			
			//Interface with North
			//Source ports
			.north_data_i(north_data_i_wght),
			.north_enable_i(north_enable_i_wght),
			
			//Destination ports
			.north_data_o(north_data_o_wght),
			.north_enable_o(north_enable_o_wght),
			
			
			//Interface with South
			//Source ports
			.south_data_i(south_data_i_wght),
			.south_enable_i(south_enable_i_wght),
			
			//Destination ports
			.south_data_o(south_data_o_wght),
			.south_enable_o(south_enable_o_wght),
			
			
			//Interface with West
			//Source ports
			.west_data_i(west_data_i_wght),
			.west_enable_i(west_enable_i_wght),
			
			//Destination ports
			.west_data_o(west_data_o_wght),
			.west_enable_o(west_enable_o_wght),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i(east_data_i_wght),
			.east_enable_i(east_enable_i_wght),
	        
			//Destination ports
	        .east_data_o(east_data_o_wght),
            .east_enable_o(east_enable_o_wght)
	);
	
	
	router
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_iact
		(
			.router_mode(router_mode_iact),
			
			//Interface with North
			//Source ports
			.north_data_i(north_data_i_iact),
			.north_enable_i(north_enable_i_iact),
			
			//Destination ports
			.north_data_o(north_data_o_iact),
			.north_enable_o(north_enable_o_iact),
			
			
			//Interface with South
			//Source ports
			.south_data_i(south_data_i_iact),
			.south_enable_i(south_enable_i_iact),
			
			//Destination ports
			.south_data_o(south_data_o_iact),
			.south_enable_o(south_enable_o_iact),
			
			
			//Interface with West
			//Source ports
			.west_data_i(west_data_i_iact),
			.west_enable_i(west_enable_i_iact),
			
			//Destination ports
			.west_data_o(west_data_o_iact),
			.west_enable_o(west_enable_o_iact),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i(east_data_i_iact),
			.east_enable_i(east_enable_i_iact),
	        
			//Destination ports
	        .east_data_o(east_data_o_iact),
            .east_enable_o(east_enable_o_iact)
	);
	
	
	router
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_psum
		(
			.router_mode(router_mode_psum),
			
			//Interface with North
			//Source ports
			.north_data_i(north_data_i_psum),
			.north_enable_i(north_enable_i_psum),
			
			//Destination ports
			.north_data_o(north_data_o_psum),
			.north_enable_o(north_enable_o_psum),
			
			
			//Interface with South
			//Source ports
			.south_data_i(south_data_i_psum),
			.south_enable_i(south_enable_i_psum),
			
			//Destination ports
			.south_data_o(south_data_o_psum),
			.south_enable_o(south_enable_o_psum),
			
			
			//Interface with West
			//Source ports
			.west_data_i(west_data_i_psum),
			.west_enable_i(west_enable_i_psum),
			
			//Destination ports
			.west_data_o(west_data_o_psum),
			.west_enable_o(west_enable_o_psum),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i(east_data_i_psum),
			.east_enable_i(east_enable_i_psum),
	        
			//Destination ports
	        .east_data_o(east_data_o_psum),
            .east_enable_o(east_enable_o_psum)
	);
	
	
endmodule


================================================
FILE: rtl/router_east.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/09/2019 04:48:15 AM
// Design Name: 
// Module Name: router_east
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

//typedef struct packed {
//
//} 

//Defining Names for routing directions
//`define ALL 0
//`define NORTH 1
//`define SOUTH 2
//`define WEST 3
//`define EAST 4


module router_east
	#(
		parameter DATA_WIDTH = 16
	)
	(
		input [3:0] router_mode,
		
		//Interface with North
		//Source ports
		input [DATA_WIDTH-1:0] north_data_i,
		input north_enable_i,
//		output logic north_ready_o,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] north_data_o,
		output logic north_enable_o,
//		input north_ready_i,
		
		
		//Interface with South
		//Source ports
		input [DATA_WIDTH-1:0] south_data_i,
		input south_enable_i,
//		output logic south_ready_o,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] south_data_o,
		output logic south_enable_o,
//		input south_ready_i,
		
		
		//Interface with West
		//Source ports
		input [DATA_WIDTH-1:0] west_data_i,
		input west_enable_i,
//		output logic west_ready_o,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] west_data_o,
		output logic west_enable_o,
//		input west_ready_i,
		
		
		//Interface with East - Devices
		//Source ports
		input [DATA_WIDTH-1:0] east_data_i,
		input east_enable_i,
//		output logic east_ready_o,
		
		//Destination ports
		output logic [DATA_WIDTH-1:0] east_data_o,
		output logic east_enable_o
//		input east_ready_i
    );
	
	logic [DATA_WIDTH-1:0] data_out;
	enum logic [3:0] {ALL=0, NORTH=1, SOUTH=2, WEST=3, EAST=4,
						EASTNORTH=5, EASTSOUTH=6, EASTWEST=7,
						WESTNORTH=8, WESTSOUTH=9, WESTEAST=10} direction;
	
	//Logic for selecting data_out based on enable
	always_comb
		begin:data_switch
			unique if(north_enable_i)
				data_out = north_data_i;
			else if(south_enable_i)
				data_out = south_data_i;
			else if(west_enable_i)
				data_out = west_data_i;
			else if(east_enable_i)
				data_out = east_data_i;
			else
				data_out = 10101; //Default value for verification
		end
	
	//Logic for data out in destination ports based on routing_mode
	always_comb
		begin: routing_logic
			case(router_mode)
				ALL:begin
					north_data_o = data_out;
					north_enable_o = 1;
					
					south_data_o = data_out;
					south_enable_o = 1;
					
					west_data_o = data_out;
					west_enable_o = 1;
					
					east_data_o = data_out;
					east_enable_o = 1;
				end
				
				NORTH:begin
					north_data_o = data_out;
					north_enable_o = 1;
					south_enable_o = 0;
					west_enable_o = 0;
					east_enable_o = 0;
				end
				
				SOUTH:begin
					south_data_o = data_out;
					north_enable_o = 0;
					south_enable_o = 1;
					west_enable_o = 0;
					east_enable_o = 0;
				end
				
				WEST:begin
					west_data_o = data_out;
					north_enable_o = 0;
					south_enable_o = 0;
					west_enable_o = 1;
					east_enable_o = 0;
				end
				
				EAST:begin
					east_data_o = data_out;
					north_enable_o = 0;
					south_enable_o = 0;
					west_enable_o = 0;
					east_enable_o = 1;
				end
				
				//Two Directions - Used for storing in PE cluster and routing
				//With East as compute unit
				EASTNORTH:begin
					east_data_o = data_out;
					north_data_o = data_out;
					north_enable_o = 1;
					south_enable_o = 0;
					west_enable_o = 0;
					east_enable_o = 1;
				end
				
				EASTSOUTH:begin
					east_data_o = data_out;
					south_data_o = data_out;
					north_enable_o = 0;
					south_enable_o = 1;
					west_enable_o = 0;
					east_enable_o = 1;
				end
				
				EASTWEST:begin
					east_data_o = data_out;
					west_data_o = data_out;
					north_enable_o = 0;
					south_enable_o = 0;
					west_enable_o = 1;
					east_enable_o = 1;
				end
				
				//With West as compute unit
				WESTNORTH:begin
					west_data_o = data_out;
					north_data_o = data_out;
					north_enable_o = 1;
					south_enable_o = 0;
					west_enable_o = 1;
					east_enable_o = 0;
				end
				
				WESTSOUTH:begin
					west_data_o = data_out;
					south_data_o = data_out;
					north_enable_o = 0;
					south_enable_o = 1;
					west_enable_o = 1;
					east_enable_o = 0;
				end
				
				WESTEAST:begin
					west_data_o = data_out;
					east_data_o = data_out;
					north_enable_o = 0;
					south_enable_o = 0;
					west_enable_o = 1;
					east_enable_o = 1;
				end
			endcase
		end
		
	
	
endmodule


================================================
FILE: rtl/router_iact.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/02/2019 03:12:11 PM
// Design Name: 
// Module Name: router_act
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_iact #( parameter DATA_BITWIDTH = 16,
						parameter ADDR_BITWIDTH_GLB = 10,
						parameter ADDR_BITWIDTH_SPAD = 9,
						
						parameter int X_dim = 5,
                        parameter int Y_dim = 3,
                        parameter int kernel_size = 3,
                        parameter int act_size = 5,
						
						parameter A_READ_ADDR =100, 
                        parameter A_LOAD_ADDR = 0
					)
					
					(	input clk,
						input reset,
						
						//for reading glb
						input [DATA_BITWIDTH-1 : 0] r_data_glb_iact,
						output logic [ADDR_BITWIDTH_GLB-1 : 0] r_addr_glb_iact,
						output logic read_req_glb_iact,
						
						//for writing to spad
						output logic [DATA_BITWIDTH-1 : 0] w_data_spad,
						output logic load_en_spad,
						
						//Input from control unit to load weights to spad
						input load_spad_ctrl
			
					);
				
					
		enum logic [2:0] {IDLE=3'b000, READ_GLB=3'b001, WRITE_SPAD=3'b010, READ_GLB_0=3'b011} state;
		
		logic [4:0] filt_count;
		
		always@(posedge clk) begin
//			$display("State: %s", state.name());
			if(reset) begin
				read_req_glb_iact <= 0;
				r_addr_glb_iact <= 0;
				load_en_spad <= 0;
				filt_count <= 0;
				state <= IDLE;
			end else begin
				case(state)
					IDLE:begin
						if(load_spad_ctrl) begin
							read_req_glb_iact <= 1;
							r_addr_glb_iact <= A_READ_ADDR;
							state <= READ_GLB;
						end else begin
							read_req_glb_iact = 0;
							load_en_spad = 0;
							state <= IDLE;
						end
					end
					
					READ_GLB:begin
						
						filt_count <= filt_count + 1;
						r_addr_glb_iact <= r_addr_glb_iact + 1;
						w_data_spad <= r_data_glb_iact;
						state <= WRITE_SPAD;
					end
					
					WRITE_SPAD:begin
						load_en_spad <= 1;
						if(filt_count == (act_size**2)) begin
							w_data_spad <= r_data_glb_iact;
							filt_count <= 0;
							r_addr_glb_iact <= A_READ_ADDR;
							
							state <= IDLE;
						end else begin
							w_data_spad <= r_data_glb_iact;
							filt_count <= filt_count + 1;
							r_addr_glb_iact <= r_addr_glb_iact + 1;
							state <= WRITE_SPAD;
						end
					end
				endcase
			end
		end
 
endmodule



================================================
FILE: rtl/router_network4.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/13/2019 05:43:25 AM
// Design Name: 
// Module Name: router_network4
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_network4
	#(
		parameter DATA_WIDTH = 16
	)
	(
	
		///////////////      ROUTER WEST 0      ///////////////////////////////////

	input [3:0] router_mode_west_0,
	
	//Interface with West
	//Source ports
	input [DATA_WIDTH-1:0] west_data_i_west_0,
	input west_enable_i_west_0,
	
	//Destination ports
	output [DATA_WIDTH-1:0] west_data_o_west_0,
	output west_enable_o_west_0,


	
		
		///////////////      ROUTER WEST 1     ///////////////////////////////////
	
	input [3:0] router_mode_west_1,
	
	
	//Interface with West
	//Source ports
	input [DATA_WIDTH-1:0] west_data_i_west_1,
	input west_enable_i_west_1,
	
	//Destination ports
	output [DATA_WIDTH-1:0] west_data_o_west_1,
	output west_enable_o_west_1,

	
	
	
		///////////////      ROUTER EAST 0    ///////////////////////////////////
	
	input [3:0] router_mode_east_0,
	
	
	//Interface with East
	//Source ports
	input [DATA_WIDTH-1:0] east_data_i_east_0,
	input east_enable_i_east_0,

	//Destination ports
	output [DATA_WIDTH-1:0] east_data_o_east_0,
	output east_enable_o_east_0,
	
	
		///////////////      ROUTER EAST 1     ///////////////////////////////////
	
	input [3:0] router_mode_east_1,
	
	
	//Interface with East
	//Source ports
	input [DATA_WIDTH-1:0] east_data_i_east_1,
	input east_enable_i_east_1,

	//Destination ports
	output [DATA_WIDTH-1:0] east_data_o_east_1,
	output east_enable_o_east_1


	);


	
	router 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_west_0
		(
			.router_mode(router_mode_west_0),
			
			
			//Interface with North
			//Source ports
			.north_data_i(),
			.north_enable_i(),
			
			//Destination ports
			.north_data_o(),
			.north_enable_o(),
			
			
			//Interface with South
			//Source ports
			.south_data_i(router_west_1.north_data_o),
			.south_enable_i(router_west_1.north_enable_o),
			
			//Destination ports
			.south_data_o(router_west_1.north_data_i),
			.south_enable_o(router_west_1.north_enable_i),
			
			
			//Interface with West
			//Source ports
			.west_data_i(west_data_i_west_0),
			.west_enable_i(west_enable_i_west_0),
			
			//Destination ports
			.west_data_o(west_data_o_west_0),
			.west_enable_o(west_enable_o_west_0),
			
			
			//Interface with East
			//Source ports
			.east_data_i(router_east_0.west_data_o),
			.east_enable_i(router_east_0.west_enable_o),
	        
			//Destination ports
	        .east_data_o(router_east_0.west_data_i),
            .east_enable_o(router_east_0.west_enable_i)
		);
	
	

	
	router 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_west_1
		(
			.router_mode(router_mode_west_1),
			
			
			//Interface with North
			//Source ports
			.north_data_i(router_west_0.south_data_o),
			.north_enable_i(router_west_0.south_enable_o),
			
			//Destination ports
			.north_data_o(router_west_0.south_data_i),
			.north_enable_o(router_west_0.south_enable_i),
			
			
			//Interface with South
			//Source ports
			.south_data_i(),
			.south_enable_i(),
			
			//Destination ports
			.south_data_o(),
			.south_enable_o(),
			
			
			//Interface with West
			//Source ports
			.west_data_i(west_data_i_west_1),
			.west_enable_i(west_enable_i_west_1),
			
			//Destination ports
			.west_data_o(west_data_o_west_1),
			.west_enable_o(west_enable_o_west_1),
			
			
			//Interface with East
			//Source ports
			.east_data_i(router_east_1.west_data_o),
			.east_enable_i(router_east_1.west_enable_o),
	        
			//Destination ports
	        .east_data_o(router_east_1.west_data_i),
            .east_enable_o(router_east_1.west_enable_i)
		);
		
	
	

	
	
	router 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_east_0
		(
			.router_mode(router_mode_east_0),
			
			
			//Interface with North
			//Source ports
			.north_data_i(),
			.north_enable_i(),
			
			//Destination ports
			.north_data_o(),
			.north_enable_o(),
			
			
			//Interface with South
			//Source ports
			.south_data_i(router_east_1.north_data_o),
			.south_enable_i(router_east_1.north_enable_o),
			
			//Destination ports
			.south_data_o(router_east_1.north_data_i),
			.south_enable_o(router_east_1.north_enable_i),
			
			
			//Interface with West
			//Source ports
			.west_data_i(router_west_0.east_data_o),
			.west_enable_i(router_west_0.east_enable_o),
			
			//Destination ports
			.west_data_o(router_west_0.east_data_i),
			.west_enable_o(router_west_0.east_enable_i),
			
			
			//Interface with East
			//Source ports
			.east_data_i(east_data_i_east_0),
			.east_enable_i(east_enable_i_east_0),
	        
			//Destination ports
	        .east_data_o(east_data_o_east_0),
            .east_enable_o(east_enable_o_east_0)
		);
		
		
		

	router 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_east_1
		(
			.router_mode(router_mode_east_1),
			
			
			//Interface with North
			//Source ports
			.north_data_i(router_east_0.south_data_o),
			.north_enable_i(router_east_0.south_enable_o),
			
			//Destination ports
			.north_data_o(router_east_0.south_data_i),
			.north_enable_o(router_east_0.south_enable_i),
			
			
			//Interface with South
			//Source ports
			.south_data_i(),
			.south_enable_i(),
			
			//Destination ports
			.south_data_o(),
			.south_enable_o(),
			
			
			//Interface with West
			//Source ports
			.west_data_i(router_west_1.east_data_o),
			.west_enable_i(router_west_1.east_enable_o),
			
			//Destination ports
			.west_data_o(router_west_1.east_data_i),
			.west_enable_o(router_west_1.east_enable_i),
			
			
			//Interface with East
			//Source ports
			.east_data_i(east_data_i_east_1),
			.east_enable_i(east_enable_i_east_1),
	        
			//Destination ports
	        .east_data_o(east_data_o_east_1),
            .east_enable_o(east_enable_o_east_1)
		);
		
endmodule


================================================
FILE: rtl/router_psum.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/03/2019 11:22:43 AM
// Design Name: 
// Module Name: router_psum
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_psum #( parameter DATA_BITWIDTH = 16,
						parameter ADDR_BITWIDTH_GLB = 10,
						parameter ADDR_BITWIDTH_SPAD = 9,
						
						parameter int X_dim = 5,
                        parameter int Y_dim = 3,
                        parameter int kernel_size = 3,
                        parameter int act_size = 5,
						
//						parameter A_READ_ADDR =100, 
                        
//                        parameter A_LOAD_ADDR = 0,
						
						parameter PSUM_READ_ADDR = 0,
						parameter PSUM_LOAD_ADDR = 0
					)
					
					(	input clk,
						input reset,
						
						//for reading glb
						input [DATA_BITWIDTH-1 : 0] r_data_spad_psum[0:kernel_size-1],
						output logic [ADDR_BITWIDTH_GLB-1 : 0] w_addr_glb_psum,
						output logic write_en_glb_psum,
						
						//for writing to spad
						output logic [DATA_BITWIDTH-1 : 0] w_data_glb_psum,
//						output logic load_en_spad,
						
						//Input from PE cluster to write psums to glb
						input write_psum_ctrl
			
					);
				
					
		enum logic [2:0] {IDLE=3'b000, WRITE_GLB=3'b001, READ_PSUM=3'b010} state;
		
		logic [4:0] psum_count;
		logic [DATA_BITWIDTH-1 : 0] pe_psum[0:kernel_size-1];
		logic [2:0] iter;
		
		always@(posedge clk) begin
//			$display("State of router_psum: %s", state.name());
			if(reset) begin
				w_addr_glb_psum <= PSUM_LOAD_ADDR;
				psum_count <= 0;
				write_en_glb_psum <= 0;
				iter <= 0;
				state <= IDLE;
			end else begin
				case(state)
					IDLE:begin
						if(write_psum_ctrl) begin
							//write_en_glb_psum <= 1;
							state <= READ_PSUM;
						end else begin
							psum_count <= 0;
							write_en_glb_psum <= 0;
							w_addr_glb_psum <= PSUM_LOAD_ADDR;
							state <= IDLE;
						end
					end
					
					READ_PSUM:begin
						pe_psum <= r_data_spad_psum;
//						$display("Psum read in router:%d",pe_psum[0:kernel_size-1]);
						psum_count <= 0;
						state <= WRITE_GLB;
					end
					
					WRITE_GLB:begin
						write_en_glb_psum <= 1;
//						$display("Psum written to address %d; Iter is %d",w_addr_glb_psum, iter);
						if(psum_count == (kernel_size-1)) begin
							w_data_glb_psum <= pe_psum[psum_count];
							psum_count <= 0;
							w_addr_glb_psum <= w_addr_glb_psum + 1;
							iter <= iter + 1;
							state <= IDLE;
						end else begin
							w_data_glb_psum <= pe_psum[psum_count];
							psum_count <= psum_count + 1;
							
							if(psum_count == (kernel_size-1)) begin
								state <= IDLE;
							end else if(psum_count == 0) begin
								w_addr_glb_psum <= PSUM_LOAD_ADDR+iter*kernel_size;
								state <= WRITE_GLB;
							end else begin
								w_addr_glb_psum <= w_addr_glb_psum + 1;
								state <= WRITE_GLB;
							end
							
						end
					end
				endcase
			end
		end
 
endmodule


================================================
FILE: rtl/router_weight.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/01/2019 03:50:08 PM
// Design Name: 
// Module Name: router_weight
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_weight #( parameter DATA_BITWIDTH = 16,
						parameter ADDR_BITWIDTH_GLB = 10,
						parameter ADDR_BITWIDTH_SPAD = 9,
						
						parameter int X_dim = 5,
                        parameter int Y_dim = 3,
                        parameter int kernel_size = 3,
                        parameter int act_size = 5,
						
						parameter W_READ_ADDR = 0, 
                        
                        parameter W_LOAD_ADDR = 0
					)
					
					(	input clk,
						input reset,
						
						//for reading glb
						input [DATA_BITWIDTH-1 : 0] r_data_glb_wght,
						output logic [ADDR_BITWIDTH_GLB-1 : 0] r_addr_glb_wght,
						output logic read_req_glb_wght,
						
						//for writing to spad
						output logic [DATA_BITWIDTH-1 : 0] w_data_spad,
						output logic load_en_spad,
						
						//Input from control unit to load weights to spad
						input load_spad_ctrl
			
					);
				
					
		enum logic [2:0] {IDLE=3'b000, READ_GLB=3'b001, WRITE_SPAD=3'b010, READ_GLB_0=3'b011} state;
		
		logic [4:0] filt_count;
		
		always@(posedge clk) begin
//			$display("State: %s", state.name());
			if(reset) begin
				read_req_glb_wght <= 0;
				r_addr_glb_wght <= 0;
				load_en_spad <= 0;
				filt_count <= 0;
				state <= IDLE;
			end else begin
				case(state)
					IDLE:begin
						if(load_spad_ctrl) begin
							read_req_glb_wght <= 1;
							r_addr_glb_wght <= W_READ_ADDR;
							state <= READ_GLB;
						end else begin
							read_req_glb_wght = 0;
							load_en_spad <= 0;
							state <= IDLE;
						end
					end
					
					READ_GLB:begin
						
						filt_count <= filt_count + 1;
						r_addr_glb_wght <= r_addr_glb_wght + 1;
						w_data_spad <= r_data_glb_wght;
						state <= WRITE_SPAD;
					end
					
					WRITE_SPAD:begin
						load_en_spad <= 1;
						if(filt_count == (kernel_size**2)) begin
							w_data_spad <= r_data_glb_wght;
							filt_count <= 0;
							r_addr_glb_wght <= W_READ_ADDR;
							
							state <= IDLE;
						end else begin
							w_data_spad <= r_data_glb_wght;
							filt_count <= filt_count + 1;
							r_addr_glb_wght <= r_addr_glb_wght + 1;
							state <= WRITE_SPAD;
						end
					end
				endcase
			end
		end
 
endmodule


================================================
FILE: rtl/switch.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/09/2019 08:10:01 AM
// Design Name: 
// Module Name: switch
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module switch
	#(
		parameter DATA_WIDTH = 16
	)
	(
		input [DATA_WIDTH-1:0] a,
		input [DATA_WIDTH-1:0] b,
		input [DATA_WIDTH-1:0] c,
		input [DATA_WIDTH-1:0] d,
		input [3:0] sel,

		output logic [DATA_WIDTH-1:0] out
	);
	
		logic [1:0] s;
		
		lookup_mux4 lookup_0 ( .in(sel), .out(s) );
		mux_4x1 mux_0 ( .sel(s), .a(a), .b(b), .c(c), .d(d), .out(out) );
	
endmodule


================================================
FILE: synth/HMNoC_cluster.vds
================================================
#-----------------------------------------------------------
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec  6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
# Start of session at: Fri Dec 13 10:48:13 2019
# Process ID: 19164
# Current directory: D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.runs/synth_1
# Command line: vivado.exe -log HMNoC_cluster.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source HMNoC_cluster.tcl
# Log file: D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.runs/synth_1/HMNoC_cluster.vds
# Journal file: D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.runs/synth_1\vivado.jou
#-----------------------------------------------------------
source HMNoC_cluster.tcl -notrace
Command: synth_design -top HMNoC_cluster -part xczu7ev-ffvf1517-1LV-i
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xczu7ev'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xczu7ev'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 17176 
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 362.254 ; gain = 80.500
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'HMNoC_cluster' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:23]
	Parameter DATA_BITWIDTH bound to: 16 - type: integer 
	Parameter ADDR_BITWIDTH bound to: 10 - type: integer 
	Parameter DATA_WIDTH bound to: 16 - type: integer 
	Parameter ADDR_WIDTH bound to: 9 - type: integer 
	Parameter NUM_GLB_IACT bound to: 1 - type: integer 
	Parameter NUM_GLB_PSUM bound to: 1 - type: integer 
	Parameter NUM_GLB_WGHT bound to: 1 - type: integer 
	Parameter ADDR_BITWIDTH_GLB bound to: 10 - type: integer 
	Parameter ADDR_BITWIDTH_SPAD bound to: 9 - type: integer 
	Parameter NUM_ROUTER_PSUM bound to: 1 - type: integer 
	Parameter NUM_ROUTER_IACT bound to: 1 - type: integer 
	Parameter NUM_ROUTER_WGHT bound to: 1 - type: integer 
	Parameter kernel_size bound to: 32'sb00000000000000000000000000000011 
	Parameter act_size bound to: 32'sb00000000000000000000000000000101 
	Parameter X_dim bound to: 32'sb00000000000000000000000000000011 
	Parameter Y_dim bound to: 32'sb00000000000000000000000000000011 
	Parameter W_READ_ADDR bound to: 0 - type: integer 
	Parameter A_READ_ADDR bound to: 0 - type: integer 
	Parameter W_LOAD_ADDR bound to: 0 - type: integer 
	Parameter A_LOAD_ADDR bound to: 0 - type: integer 
	Parameter PSUM_READ_ADDR bound to: 0 - type: integer 
	Parameter PSUM_LOAD_ADDR bound to: 0 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'GLB_cluster' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/GLB_cluster.sv:23]
	Parameter DATA_BITWIDTH bound to: 16 - type: integer 
	Parameter ADDR_BITWIDTH bound to: 10 - type: integer 
	Parameter NUM_GLB_IACT bound to: 1 - type: integer 
	Parameter NUM_GLB_PSUM bound to: 1 - type: integer 
	Parameter NUM_GLB_WGHT bound to: 1 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'glb_iact' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:23]
	Parameter DATA_BITWIDTH bound to: 16 - type: integer 
	Parameter ADDR_BITWIDTH bound to: 10 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'glb_iact' (1#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:23]
INFO: [Synth 8-6157] synthesizing module 'glb_psum' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_psum.sv:23]
	Parameter DATA_BITWIDTH bound to: 16 - type: integer 
	Parameter ADDR_BITWIDTH bound to: 10 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'glb_psum' (2#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_psum.sv:23]
INFO: [Synth 8-6157] synthesizing module 'glb_weight' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_weight.sv:23]
	Parameter DATA_BITWIDTH bound to: 16 - type: integer 
	Parameter ADDR_BITWIDTH bound to: 10 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'glb_weight' (3#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_weight.sv:23]
INFO: [Synth 8-6155] done synthesizing module 'GLB_cluster' (4#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/GLB_cluster.sv:23]
WARNING: [Synth 8-6104] Input port 'r_data_glb_iact' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:114]
WARNING: [Synth 8-6104] Input port 'r_data_glb_wght' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:116]
INFO: [Synth 8-6157] synthesizing module 'router_cluster' [D:/Fall 19/CSE 240D/Project/Vivado/src/router_old/router_cluster.sv:23]
	Parameter DATA_BITWIDTH bound to: 16 - type: integer 
	Parameter ADDR_BITWIDTH_GLB bound to: 10 - type: integer 
	Parameter ADDR_BITWIDTH_SPAD bound to: 9 - type: integer 
	Parameter kernel_size bound to: 3 - type: integer 
	Parameter act_size bound to: 5 - type: integer 
	Parameter NUM_ROUTER_PSUM bound to: 1 - type: integer 
	Parameter NUM_ROUTER_IACT bound to: 1 - type: integer 
	Parameter NUM_ROUTER_WGHT bound to: 1 - type: integer 
	Parameter A_READ_ADDR bound to: 0 - type: integer 
	Parameter A_LOAD_ADDR bound to: 0 - type: integer 
	Parameter W_READ_ADDR bound to: 0 - type: integer 
	Parameter W_LOAD_ADDR bound to: 0 - type: integer 
	Parameter PSUM_READ_ADDR bound to: 0 - type: integer 
	Parameter PSUM_LOAD_ADDR bound to: 0 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'router_iact' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/imports/new/router_iact.sv:23]
	Parameter DATA_BITWIDTH bound to: 16 - type: integer 
	Parameter ADDR_BITWIDTH_GLB bound to: 10 - type: integer 
	Parameter ADDR_BITWIDTH_SPAD bound to: 9 - type: integer 
	Parameter X_dim bound to: 32'sb00000000000000000000000000000101 
	Parameter Y_dim bound to: 32'sb00000000000000000000000000000011 
	Parameter kernel_size bound to: 3 - type: integer 
	Parameter act_size bound to: 5 - type: integer 
	Parameter A_READ_ADDR bound to: 0 - type: integer 
	Parameter A_LOAD_ADDR bound to: 0 - type: integer 
INFO: [Synth 8-155] case statement is not full and has no default [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/imports/new/router_iact.sv:67]
INFO: [Synth 8-6155] done synthesizing module 'router_iact' (5#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/imports/new/router_iact.sv:23]
INFO: [Synth 8-6157] synthesizing module 'router_weight' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router_weight.sv:23]
	Parameter DATA_BITWIDTH bound to: 16 - type: integer 
	Parameter ADDR_BITWIDTH_GLB bound to: 10 - type: integer 
	Parameter ADDR_BITWIDTH_SPAD bound to: 9 - type: integer 
	Parameter X_dim bound to: 32'sb00000000000000000000000000000101 
	Parameter Y_dim bound to: 32'sb00000000000000000000000000000011 
	Parameter kernel_size bound to: 3 - type: integer 
	Parameter act_size bound to: 5 - type: integer 
	Parameter W_READ_ADDR bound to: 0 - type: integer 
	Parameter W_LOAD_ADDR bound to: 0 - type: integer 
INFO: [Synth 8-155] case statement is not full and has no default [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router_weight.sv:68]
INFO: [Synth 8-6155] done synthesizing module 'router_weight' (6#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router_weight.sv:23]
INFO: [Synth 8-6157] synthesizing module 'router_psum' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router_psum.sv:23]
	Parameter DATA_BITWIDTH bound to: 16 - type: integer 
	Parameter ADDR_BITWIDTH_GLB bound to: 10 - type: integer 
	Parameter ADDR_BITWIDTH_SPAD bound to: 9 - type: integer 
	Parameter X_dim bound to: 32'sb00000000000000000000000000000101 
	Parameter Y_dim bound to: 32'sb00000000000000000000000000000011 
	Parameter kernel_size bound to: 3 - type: integer 
	Parameter act_size bound to: 5 - type: integer 
	Parameter PSUM_READ_ADDR bound to: 0 - type: integer 
	Parameter PSUM_LOAD_ADDR bound to: 0 - type: integer 
INFO: [Synth 8-155] case statement is not full and has no default [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router_psum.sv:73]
INFO: [Synth 8-6155] done synthesizing module 'router_psum' (7#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router_psum.sv:23]
INFO: [Synth 8-6155] done synthesizing module 'router_cluster' (8#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/router_old/router_cluster.sv:23]
WARNING: [Synth 8-6104] Input port 'r_addr_iact' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:168]
WARNING: [Synth 8-6104] Input port 'read_req_iact' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:169]
WARNING: [Synth 8-6104] Input port 'act_in' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:171]
WARNING: [Synth 8-6104] Input port 'load_en_act' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:172]
WARNING: [Synth 8-6104] Input port 'r_addr_wght' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:179]
WARNING: [Synth 8-6104] Input port 'read_req_wght' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:180]
WARNING: [Synth 8-6104] Input port 'filt_in' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:182]
WARNING: [Synth 8-6104] Input port 'load_en_wght' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:183]
WARNING: [Synth 8-6104] Input port 'w_addr_psum' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:191]
WARNING: [Synth 8-6104] Input port 'write_en_psum' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:192]
WARNING: [Synth 8-6104] Input port 'w_data_psum' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:193]
INFO: [Synth 8-6157] synthesizing module 'PE_cluster' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE_cluster.sv:23]
	Parameter DATA_WIDTH bound to: 16 - type: integer 
	Parameter ADDR_WIDTH bound to: 9 - type: integer 
	Parameter X_dim bound to: 32'sb00000000000000000000000000000011 
	Parameter Y_dim bound to: 32'sb00000000000000000000000000000011 
	Parameter kernel_size bound to: 32'sb00000000000000000000000000000011 
	Parameter act_size bound to: 32'sb00000000000000000000000000000101 
	Parameter W_READ_ADDR bound to: 0 - type: integer 
	Parameter A_READ_ADDR bound to: 100 - type: integer 
	Parameter W_LOAD_ADDR bound to: 0 - type: integer 
	Parameter A_LOAD_ADDR bound to: 100 - type: integer 
	Parameter PSUM_ADDR bound to: 500 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'PE' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:23]
	Parameter DATA_WIDTH bound to: 16 - type: integer 
	Parameter ADDR_WIDTH bound to: 9 - type: integer 
	Parameter W_READ_ADDR bound to: 0 - type: integer 
	Parameter A_READ_ADDR bound to: 100 - type: integer 
	Parameter W_LOAD_ADDR bound to: 0 - type: integer 
	Parameter A_LOAD_ADDR bound to: 100 - type: integer 
	Parameter PSUM_ADDR bound to: 500 - type: integer 
	Parameter kernel_size bound to: 32'sb00000000000000000000000000000011 
	Parameter act_size bound to: 32'sb00000000000000000000000000000101 
INFO: [Synth 8-6157] synthesizing module 'SPad' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/SPad.sv:23]
	Parameter DATA_BITWIDTH bound to: 16 - type: integer 
	Parameter ADDR_BITWIDTH bound to: 9 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'SPad' (9#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/SPad.sv:23]
INFO: [Synth 8-6157] synthesizing module 'MAC' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/MAC.sv:23]
	Parameter IN_BITWIDTH bound to: 16 - type: integer 
	Parameter OUT_BITWIDTH bound to: 16 - type: integer 
WARNING: [Synth 8-6014] Unused sequential element mult_out_reg was removed.  [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/MAC.sv:36]
INFO: [Synth 8-6155] done synthesizing module 'MAC' (10#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/MAC.sv:23]
INFO: [Synth 8-6157] synthesizing module 'mux2' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/mux2.sv:23]
	Parameter WIDTH bound to: 16 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'mux2' (11#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/mux2.sv:23]
INFO: [Synth 8-155] case statement is not full and has no default [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:120]
INFO: [Synth 8-6155] done synthesizing module 'PE' (12#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:23]
INFO: [Synth 8-6157] synthesizing module 'PE__parameterized0' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:23]
	Parameter DATA_WIDTH bound to: 16 - type: integer 
	Parameter ADDR_WIDTH bound to: 9 - type: integer 
	Parameter W_READ_ADDR bound to: 3 - type: integer 
	Parameter A_READ_ADDR bound to: 105 - type: integer 
	Parameter W_LOAD_ADDR bound to: 0 - type: integer 
	Parameter A_LOAD_ADDR bound to: 100 - type: integer 
	Parameter PSUM_ADDR bound to: 500 - type: integer 
	Parameter kernel_size bound to: 32'sb00000000000000000000000000000011 
	Parameter act_size bound to: 32'sb00000000000000000000000000000101 
INFO: [Synth 8-155] case statement is not full and has no default [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:120]
INFO: [Synth 8-6155] done synthesizing module 'PE__parameterized0' (12#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:23]
INFO: [Synth 8-6157] synthesizing module 'PE__parameterized1' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:23]
	Parameter DATA_WIDTH bound to: 16 - type: integer 
	Parameter ADDR_WIDTH bound to: 9 - type: integer 
	Parameter W_READ_ADDR bound to: 6 - type: integer 
	Parameter A_READ_ADDR bound to: 110 - type: integer 
	Parameter W_LOAD_ADDR bound to: 0 - type: integer 
	Parameter A_LOAD_ADDR bound to: 100 - type: integer 
	Parameter PSUM_ADDR bound to: 500 - type: integer 
	Parameter kernel_size bound to: 32'sb00000000000000000000000000000011 
	Parameter act_size bound to: 32'sb00000000000000000000000000000101 
INFO: [Synth 8-155] case statement is not full and has no default [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:120]
INFO: [Synth 8-6155] done synthesizing module 'PE__parameterized1' (12#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:23]
INFO: [Synth 8-6157] synthesizing module 'PE__parameterized2' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:23]
	Parameter DATA_WIDTH bound to: 16 - type: integer 
	Parameter ADDR_WIDTH bound to: 9 - type: integer 
	Parameter W_READ_ADDR bound to: 0 - type: integer 
	Parameter A_READ_ADDR bound to: 101 - type: integer 
	Parameter W_LOAD_ADDR bound to: 0 - type: integer 
	Parameter A_LOAD_ADDR bound to: 100 - type: integer 
	Parameter PSUM_ADDR bound to: 500 - type: integer 
	Parameter kernel_size bound to: 32'sb00000000000000000000000000000011 
	Parameter act_size bound to: 32'sb00000000000000000000000000000101 
INFO: [Synth 8-155] case statement is not full and has no default [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:120]
INFO: [Synth 8-6155] done synthesizing module 'PE__parameterized2' (12#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:23]
INFO: [Synth 8-6157] synthesizing module 'PE__parameterized3' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:23]
	Parameter DATA_WIDTH bound to: 16 - type: integer 
	Parameter ADDR_WIDTH bound to: 9 - type: integer 
	Parameter W_READ_ADDR bound to: 3 - type: integer 
	Parameter A_READ_ADDR bound to: 106 - type: integer 
	Parameter W_LOAD_ADDR bound to: 0 - type: integer 
	Parameter A_LOAD_ADDR bound to: 100 - type: integer 
	Parameter PSUM_ADDR bound to: 500 - type: integer 
	Parameter kernel_size bound to: 32'sb00000000000000000000000000000011 
	Parameter act_size bound to: 32'sb00000000000000000000000000000101 
INFO: [Synth 8-155] case statement is not full and has no default [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:120]
INFO: [Synth 8-6155] done synthesizing module 'PE__parameterized3' (12#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:23]
INFO: [Synth 8-6157] synthesizing module 'PE__parameterized4' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:23]
	Parameter DATA_WIDTH bound to: 16 - type: integer 
	Parameter ADDR_WIDTH bound to: 9 - type: integer 
	Parameter W_READ_ADDR bound to: 6 - type: integer 
	Parameter A_READ_ADDR bound to: 111 - type: integer 
	Parameter W_LOAD_ADDR bound to: 0 - type: integer 
	Parameter A_LOAD_ADDR bound to: 100 - type: integer 
	Parameter PSUM_ADDR bound to: 500 - type: integer 
	Parameter kernel_size bound to: 32'sb00000000000000000000000000000011 
	Parameter act_size bound to: 32'sb00000000000000000000000000000101 
INFO: [Synth 8-155] case statement is not full and has no default [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:120]
INFO: [Synth 8-6155] done synthesizing module 'PE__parameterized4' (12#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:23]
INFO: [Synth 8-6157] synthesizing module 'PE__parameterized5' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:23]
	Parameter DATA_WIDTH bound to: 16 - type: integer 
	Parameter ADDR_WIDTH bound to: 9 - type: integer 
	Parameter W_READ_ADDR bound to: 0 - type: integer 
	Parameter A_READ_ADDR bound to: 102 - type: integer 
	Parameter W_LOAD_ADDR bound to: 0 - type: integer 
	Parameter A_LOAD_ADDR bound to: 100 - type: integer 
	Parameter PSUM_ADDR bound to: 500 - type: integer 
	Parameter kernel_size bound to: 32'sb00000000000000000000000000000011 
	Parameter act_size bound to: 32'sb00000000000000000000000000000101 
INFO: [Synth 8-155] case statement is not full and has no default [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:120]
INFO: [Synth 8-6155] done synthesizing module 'PE__parameterized5' (12#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:23]
INFO: [Synth 8-6157] synthesizing module 'PE__parameterized6' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:23]
	Parameter DATA_WIDTH bound to: 16 - type: integer 
	Parameter ADDR_WIDTH bound to: 9 - type: integer 
	Parameter W_READ_ADDR bound to: 3 - type: integer 
	Parameter A_READ_ADDR bound to: 107 - type: integer 
	Parameter W_LOAD_ADDR bound to: 0 - type: integer 
	Parameter A_LOAD_ADDR bound to: 100 - type: integer 
	Parameter PSUM_ADDR bound to: 500 - type: integer 
	Parameter kernel_size bound to: 32'sb00000000000000000000000000000011 
	Parameter act_size bound to: 32'sb00000000000000000000000000000101 
INFO: [Synth 8-155] case statement is not full and has no default [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:120]
INFO: [Synth 8-6155] done synthesizing module 'PE__parameterized6' (12#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:23]
INFO: [Synth 8-6157] synthesizing module 'PE__parameterized7' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:23]
	Parameter DATA_WIDTH bound to: 16 - type: integer 
	Parameter ADDR_WIDTH bound to: 9 - type: integer 
	Parameter W_READ_ADDR bound to: 6 - type: integer 
	Parameter A_READ_ADDR bound to: 112 - type: integer 
	Parameter W_LOAD_ADDR bound to: 0 - type: integer 
	Parameter A_LOAD_ADDR bound to: 100 - type: integer 
	Parameter PSUM_ADDR bound to: 500 - type: integer 
	Parameter kernel_size bound to: 32'sb00000000000000000000000000000011 
	Parameter act_size bound to: 32'sb00000000000000000000000000000101 
INFO: [Synth 8-155] case statement is not full and has no default [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:120]
INFO: [Synth 8-6155] done synthesizing module 'PE__parameterized7' (12#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:23]
INFO: [Synth 8-6155] done synthesizing module 'PE_cluster' (13#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE_cluster.sv:23]
WARNING: [Synth 8-6104] Input port 'r_data_spad_psum' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:226]
WARNING: [Synth 8-6104] Input port 'r_data_spad_psum' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:226]
WARNING: [Synth 8-6104] Input port 'r_data_spad_psum' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:226]
WARNING: [Synth 8-6104] Input port 'write_psum_ctrl' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:227]
INFO: [Synth 8-6155] done synthesizing module 'HMNoC_cluster' (14#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:23]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_addr_psum[9]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_addr_psum[8]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_addr_psum[7]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_addr_psum[6]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_addr_psum[5]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_addr_psum[4]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_addr_psum[3]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_addr_psum[2]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_addr_psum[1]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_addr_psum[0]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_data_psum[15]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_data_psum[14]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_data_psum[13]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_data_psum[12]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_data_psum[11]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_data_psum[10]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_data_psum[9]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_data_psum[8]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_data_psum[7]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_data_psum[6]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_data_psum[5]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_data_psum[4]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_data_psum[3]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_data_psum[2]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_data_psum[1]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_data_psum[0]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 433.207 ; gain = 151.453
---------------------------------------------------------------------------------

Report Check Netlist: 
+------+------------------+-------+---------+-------+------------------+
|      |Item              |Errors |Warnings |Status |Description       |
+------+------------------+-------+---------+-------+------------------+
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:read_req_iact to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:read_req_wght to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:write_en_psum to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:r_addr_iact[9] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:r_addr_iact[8] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:r_addr_iact[7] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:r_addr_iact[6] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:r_addr_iact[5] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:r_addr_iact[4] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:r_addr_iact[3] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:r_addr_iact[2] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:r_addr_iact[1] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:r_addr_iact[0] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:r_addr_wght[9] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:r_addr_wght[8] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:r_addr_wght[7] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:r_addr_wght[6] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:r_addr_wght[5] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:r_addr_wght[4] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:r_addr_wght[3] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:r_addr_wght[2] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:r_addr_wght[1] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:r_addr_wght[0] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_addr_psum[9] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_addr_psum[8] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_addr_psum[7] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_addr_psum[6] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_addr_psum[5] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_addr_psum[4] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_addr_psum[3] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_addr_psum[2] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_addr_psum[1] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_addr_psum[0] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[15] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[14] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[13] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[12] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[11] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[10] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[9] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[8] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[7] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[6] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[5] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[4] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[3] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[2] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[1] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[0] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:104]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_glb_iact[15] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_glb_iact[14] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_glb_iact[13] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_glb_iact[12] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_glb_iact[11] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_glb_iact[10] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_glb_iact[9] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_glb_iact[8] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_glb_iact[7] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_glb_iact[6] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_glb_iact[5] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_glb_iact[4] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_glb_iact[3] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_glb_iact[2] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_glb_iact[1] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_glb_iact[0] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_glb_wght[15] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_glb_wght[14] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_glb_wght[13] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_glb_wght[12] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_glb_wght[11] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_glb_wght[10] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_glb_wght[9] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_glb_wght[8] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_glb_wght[7] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_glb_wght[6] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_glb_wght[5] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_glb_wght[4] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_glb_wght[3] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_glb_wght[2] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_glb_wght[1] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_glb_wght[0] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_spad_psum[0][15] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_spad_psum[0][14] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_spad_psum[0][13] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_spad_psum[0][12] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_spad_psum[0][11] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_spad_psum[0][10] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_spad_psum[0][9] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_spad_psum[0][8] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_spad_psum[0][7] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_spad_psum[0][6] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_spad_psum[0][5] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_spad_psum[0][4] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_spad_psum[0][3] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_spad_psum[0][2] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_spad_psum[0][1] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_spad_psum[0][0] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_spad_psum[1][15] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_spad_psum[1][14] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:r_data_spad_psum[1][13] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster.sv:161]
INFO: [Common 17-14] Message 'Synth 8-3295' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 433.207 ; gain = 151.453
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 433.207 ; gain = 151.453
---------------------------------------------------------------------------------
INFO: [Device 21-403] Loading part xczu7ev-ffvf1517-1LV-i
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/constrs_1/new/constraints_1.xdc]
Finished Parsing XDC File [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/constrs_1/new/constraints_1.xdc]
Completed Processing XDC Constraints

Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1532.438 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1532.438 ; gain = 0.000
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.088 . Memory (MB): peak = 1532.438 ; gain = 0.000
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:14 ; elapsed = 00:00:21 . Memory (MB): peak = 1532.438 ; gain = 1250.684
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xczu7ev-ffvf1517-1LV-i
INFO: [Synth 8-6742] Reading net delay rules and data
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:14 ; elapsed = 00:00:21 . Memory (MB): peak = 1532.438 ; gain = 1250.684
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:21 . Memory (MB): peak = 1532.438 ; gain = 1250.684
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'router_iact'
INFO: [Synth 8-5544] ROM "load_en_spad" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "state" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'router_weight'
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "state" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "pe_psum" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "w_addr_glb_psum" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "iter" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "state" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "w_data_glb_psum" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "filt_count" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "sum_in_mux_sel" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "sum_in_mux_sel" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "w_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "w_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "r_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "load_done" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "filt_count" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "sum_in_mux_sel" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "sum_in_mux_sel" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "w_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "w_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "r_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "load_done" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "filt_count" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "sum_in_mux_sel" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "sum_in_mux_sel" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "w_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "w_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "r_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "load_done" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "filt_count" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "sum_in_mux_sel" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "sum_in_mux_sel" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "w_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "w_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "r_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "load_done" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "filt_count" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "sum_in_mux_sel" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "sum_in_mux_sel" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "w_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "w_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "r_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "load_done" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "filt_count" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "sum_in_mux_sel" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "sum_in_mux_sel" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "w_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "w_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "r_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "load_done" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "filt_count" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "sum_in_mux_sel" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "sum_in_mux_sel" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "w_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "w_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "r_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "load_done" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "filt_count" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "sum_in_mux_sel" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "sum_in_mux_sel" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "w_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "w_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "r_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "load_done" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "filt_count" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "sum_in_mux_sel" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "sum_in_mux_sel" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "w_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "w_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "r_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "load_done" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                    IDLE |                               00 |                              000
                READ_GLB |                               01 |                              001
              WRITE_SPAD |                               10 |                              010
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'router_iact'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                    IDLE |                               00 |                              000
                READ_GLB |                               01 |                              001
              WRITE_SPAD |                               10 |                              010
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'router_weight'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1532.438 ; gain = 1250.684
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start RTL Component Statistics 
---------------------------------------------------------------------------------
Detailed RTL Component Info : 
+---Adders : 
	   3 Input     16 Bit       Adders := 3     
	   2 Input     10 Bit       Adders := 3     
	   2 Input      9 Bit       Adders := 24    
	   2 Input      8 Bit       Adders := 9     
	   2 Input      5 Bit       Adders := 3     
	   2 Input      3 Bit       Adders := 10    
+---Registers : 
	               16 Bit    Registers := 57    
	               10 Bit    Registers := 3     
	                9 Bit    Registers := 18    
	                8 Bit    Registers := 18    
	                5 Bit    Registers := 3     
	                3 Bit    Registers := 39    
	                1 Bit    Registers := 59    
+---RAMs : 
	              16K Bit         RAMs := 3     
	               8K Bit         RAMs := 9     
+---Muxes : 
	   3 Input     16 Bit        Muxes := 13    
	   2 Input     16 Bit        Muxes := 19    
	   2 Input     14 Bit        Muxes := 12    
	   2 Input     10 Bit        Muxes := 4     
	   3 Input     10 Bit        Muxes := 3     
	   4 Input     10 Bit        Muxes := 1     
	   8 Input      9 Bit        Muxes := 18    
	   2 Input      8 Bit        Muxes := 9     
	   8 Input      8 Bit        Muxes := 9     
	   2 Input      7 Bit        Muxes := 9     
	   2 Input      5 Bit        Muxes := 4     
	   3 Input      5 Bit        Muxes := 2     
	   4 Input      5 Bit        Muxes := 1     
	   2 Input      3 Bit        Muxes := 28    
	   4 Input      3 Bit        Muxes := 10    
	   8 Input      3 Bit        Muxes := 9     
	   3 Input      2 Bit        Muxes := 2     
	   2 Input      2 Bit        Muxes := 5     
	   2 Input      1 Bit        Muxes := 99    
	   3 Input      1 Bit        Muxes := 16    
	   4 Input      1 Bit        Muxes := 6     
	   5 Input      1 Bit        Muxes := 1     
	   8 Input      1 Bit        Muxes := 135   
	   9 Input      1 Bit        Muxes := 18    
---------------------------------------------------------------------------------
Finished RTL Component Statistics 
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Hierarchical Component Statistics 
---------------------------------------------------------------------------------
Hierarchical RTL Component report 
Module glb_iact 
Detailed RTL Component Info : 
+---Registers : 
	               16 Bit    Registers := 1     
+---RAMs : 
	              16K Bit         RAMs := 1     
+---Muxes : 
	   3 Input     16 Bit        Muxes := 1     
	   2 Input     14 Bit        Muxes := 1     
Module glb_psum 
Detailed RTL Component Info : 
+---Registers : 
	               16 Bit    Registers := 1     
+---RAMs : 
	              16K Bit         RAMs := 1     
+---Muxes : 
	   3 Input     16 Bit        Muxes := 1     
	   2 Input     14 Bit        Muxes := 1     
Module glb_weight 
Detailed RTL Component Info : 
+---Registers : 
	               16 Bit    Registers := 1     
+---RAMs : 
	              16K Bit         RAMs := 1     
+---Muxes : 
	   3 Input     16 Bit        Muxes := 1     
	   2 Input     14 Bit        Muxes := 1     
Module router_iact 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     10 Bit       Adders := 1     
	   2 Input      5 Bit       Adders := 1     
+---Registers : 
	               16 Bit    Registers := 1     
	               10 Bit    Registers := 1     
	                5 Bit    Registers := 1     
	                1 Bit    Registers := 2     
+---Muxes : 
	   2 Input     10 Bit        Muxes := 1     
	   3 Input     10 Bit        Muxes := 1     
	   2 Input      5 Bit        Muxes := 1     
	   3 Input      5 Bit        Muxes := 1     
	   3 Input      2 Bit        Muxes := 1     
	   2 Input      2 Bit        Muxes := 2     
	   2 Input      1 Bit        Muxes := 1     
	   3 Input      1 Bit        Muxes := 8     
Module router_weight 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     10 Bit       Adders := 1     
	   2 Input      5 Bit       Adders := 1     
+---Registers : 
	               16 Bit    Registers := 1     
	               10 Bit    Registers := 1     
	                5 Bit    Registers := 1     
	                1 Bit    Registers := 2     
+---Muxes : 
	   2 Input     10 Bit        Muxes := 1     
	   3 Input     10 Bit        Muxes := 1     
	   2 Input      5 Bit        Muxes := 1     
	   3 Input      5 Bit        Muxes := 1     
	   3 Input      2 Bit        Muxes := 1     
	   2 Input      2 Bit        Muxes := 2     
	   2 Input      1 Bit        Muxes := 1     
	   3 Input      1 Bit        Muxes := 8     
Module router_psum 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     10 Bit       Adders := 1     
	   2 Input      5 Bit       Adders := 1     
	   2 Input      3 Bit       Adders := 1     
+---Registers : 
	               16 Bit    Registers := 4     
	               10 Bit    Registers := 1     
	                5 Bit    Registers := 1     
	                3 Bit    Registers := 3     
	                1 Bit    Registers := 1     
+---Muxes : 
	   3 Input     16 Bit        Muxes := 1     
	   2 Input     16 Bit        Muxes := 1     
	   2 Input     10 Bit        Muxes := 2     
	   4 Input     10 Bit        Muxes := 1     
	   3 Input     10 Bit        Muxes := 1     
	   2 Input      5 Bit        Muxes := 2     
	   4 Input      5 Bit        Muxes := 1     
	   2 Input      3 Bit        Muxes := 1     
	   4 Input      3 Bit        Muxes := 1     
	   2 Input      2 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 7     
	   4 Input      1 Bit        Muxes := 6     
	   5 Input      1 Bit        Muxes := 1     
Module SPad 
Detailed RTL Component Info : 
+---Registers : 
	               16 Bit    Registers := 1     
+---RAMs : 
	               8K Bit         RAMs := 1     
+---Muxes : 
	   3 Input     16 Bit        Muxes := 1     
	   2 Input     14 Bit        Muxes := 1     
Module MAC 
Detailed RTL Component Info : 
+---Registers : 
	               16 Bit    Registers := 1     
Module mux2 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input     16 Bit        Muxes := 1     
Module PE 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      9 Bit       Adders := 2     
	   2 Input      8 Bit       Adders := 1     
	   2 Input      3 Bit       Adders := 1     
+---Registers : 
	               16 Bit    Registers := 3     
	                9 Bit    Registers := 2     
	                8 Bit    Registers := 2     
	                3 Bit    Registers := 4     
	                1 Bit    Registers := 6     
+---Muxes : 
	   2 Input     16 Bit        Muxes := 1     
	   8 Input      9 Bit        Muxes := 2     
	   2 Input      8 Bit        Muxes := 1     
	   8 Input      8 Bit        Muxes := 1     
	   2 Input      7 Bit        Muxes := 1     
	   8 Input      3 Bit        Muxes := 1     
	   4 Input      3 Bit        Muxes := 1     
	   2 Input      3 Bit        Muxes := 3     
	   8 Input      1 Bit        Muxes := 15    
	   2 Input      1 Bit        Muxes := 10    
	   9 Input      1 Bit        Muxes := 2     
Module PE__parameterized0 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      9 Bit       Adders := 3     
	   2 Input      8 Bit       Adders := 1     
	   2 Input      3 Bit       Adders := 1     
+---Registers : 
	               16 Bit    Registers := 3     
	                9 Bit    Registers := 2     
	                8 Bit    Registers := 2     
	                3 Bit    Registers := 4     
	                1 Bit    Registers := 6     
+---Muxes : 
	   2 Input     16 Bit        Muxes := 1     
	   8 Input      9 Bit        Muxes := 2     
	   2 Input      8 Bit        Muxes := 1     
	   8 Input      8 Bit        Muxes := 1     
	   2 Input      7 Bit        Muxes := 1     
	   8 Input      3 Bit        Muxes := 1     
	   4 Input      3 Bit        Muxes := 1     
	   2 Input      3 Bit        Muxes := 3     
	   8 Input      1 Bit        Muxes := 15    
	   2 Input      1 Bit        Muxes := 10    
	   9 Input      1 Bit        Muxes := 2     
Module PE__parameterized1 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      9 Bit       Adders := 3     
	   2 Input      8 Bit       Adders := 1     
	   2 Input      3 Bit       Adders := 1     
+---Registers : 
	               16 Bit    Registers := 3     
	                9 Bit    Registers := 2     
	                8 Bit    Registers := 2     
	                3 Bit    Registers := 4     
	                1 Bit    Registers := 6     
+---Muxes : 
	   2 Input     16 Bit        Muxes := 1     
	   8 Input      9 Bit        Muxes := 2     
	   2 Input      8 Bit        Muxes := 1     
	   8 Input      8 Bit        Muxes := 1     
	   2 Input      7 Bit        Muxes := 1     
	   8 Input      3 Bit        Muxes := 1     
	   4 Input      3 Bit        Muxes := 1     
	   2 Input      3 Bit        Muxes := 3     
	   8 Input      1 Bit        Muxes := 15    
	   2 Input      1 Bit        Muxes := 10    
	   9 Input      1 Bit        Muxes := 2     
Module PE__parameterized2 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      9 Bit       Adders := 2     
	   2 Input      8 Bit       Adders := 1     
	   2 Input      3 Bit       Adders := 1     
+---Registers : 
	               16 Bit    Registers := 3     
	                9 Bit    Registers := 2     
	                8 Bit    Registers := 2     
	                3 Bit    Registers := 4     
	                1 Bit    Registers := 6     
+---Muxes : 
	   2 Input     16 Bit        Muxes := 1     
	   8 Input      9 Bit        Muxes := 2     
	   2 Input      8 Bit        Muxes := 1     
	   8 Input      8 Bit        Muxes := 1     
	   2 Input      7 Bit        Muxes := 1     
	   8 Input      3 Bit        Muxes := 1     
	   4 Input      3 Bit        Muxes := 1     
	   2 Input      3 Bit        Muxes := 3     
	   8 Input      1 Bit        Muxes := 15    
	   2 Input      1 Bit        Muxes := 10    
	   9 Input      1 Bit        Muxes := 2     
Module PE__parameterized3 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      9 Bit       Adders := 3     
	   2 Input      8 Bit       Adders := 1     
	   2 Input      3 Bit       Adders := 1     
+---Registers : 
	               16 Bit    Registers := 3     
	                9 Bit    Registers := 2     
	                8 Bit    Registers := 2     
	                3 Bit    Registers := 4     
	                1 Bit    Registers := 6     
+---Muxes : 
	   2 Input     16 Bit        Muxes := 1     
	   8 Input      9 Bit        Muxes := 2     
	   2 Input      8 Bit        Muxes := 1     
	   8 Input      8 Bit        Muxes := 1     
	   2 Input      7 Bit        Muxes := 1     
	   8 Input      3 Bit        Muxes := 1     
	   4 Input      3 Bit        Muxes := 1     
	   2 Input      3 Bit        Muxes := 3     
	   8 Input      1 Bit        Muxes := 15    
	   2 Input      1 Bit        Muxes := 10    
	   9 Input      1 Bit        Muxes := 2     
Module PE__parameterized4 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      9 Bit       Adders := 3     
	   2 Input      8 Bit       Adders := 1     
	   2 Input      3 Bit       Adders := 1     
+---Registers : 
	               16 Bit    Registers := 3     
	                9 Bit    Registers := 2     
	                8 Bit    Registers := 2     
	                3 Bit    Registers := 4     
	                1 Bit    Registers := 6     
+---Muxes : 
	   2 Input     16 Bit        Muxes := 1     
	   8 Input      9 Bit        Muxes := 2     
	   2 Input      8 Bit        Muxes := 1     
	   8 Input      8 Bit        Muxes := 1     
	   2 Input      7 Bit        Muxes := 1     
	   8 Input      3 Bit        Muxes := 1     
	   4 Input      3 Bit        Muxes := 1     
	   2 Input      3 Bit        Muxes := 3     
	   8 Input      1 Bit        Muxes := 15    
	   2 Input      1 Bit        Muxes := 10    
	   9 Input      1 Bit        Muxes := 2     
Module PE__parameterized5 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      9 Bit       Adders := 2     
	   2 Input      8 Bit       Adders := 1     
	   2 Input      3 Bit       Adders := 1     
+---Registers : 
	               16 Bit    Registers := 3     
	                9 Bit    Registers := 2     
	                8 Bit    Registers := 2     
	                3 Bit    Registers := 4     
	                1 Bit    Registers := 6     
+---Muxes : 
	   2 Input     16 Bit        Muxes := 1     
	   8 Input      9 Bit        Muxes := 2     
	   2 Input      8 Bit        Muxes := 1     
	   8 Input      8 Bit        Muxes := 1     
	   2 Input      7 Bit        Muxes := 1     
	   8 Input      3 Bit        Muxes := 1     
	   4 Input      3 Bit        Muxes := 1     
	   2 Input      3 Bit        Muxes := 3     
	   8 Input      1 Bit        Muxes := 15    
	   2 Input      1 Bit        Muxes := 10    
	   9 Input      1 Bit        Muxes := 2     
Module PE__parameterized6 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      9 Bit       Adders := 3     
	   2 Input      8 Bit       Adders := 1     
	   2 Input      3 Bit       Adders := 1     
+---Registers : 
	               16 Bit    Registers := 3     
	                9 Bit    Registers := 2     
	                8 Bit    Registers := 2     
	                3 Bit    Registers := 4     
	                1 Bit    Registers := 6     
+---Muxes : 
	   2 Input     16 Bit        Muxes := 1     
	   8 Input      9 Bit        Muxes := 2     
	   2 Input      8 Bit        Muxes := 1     
	   8 Input      8 Bit        Muxes := 1     
	   2 Input      7 Bit        Muxes := 1     
	   8 Input      3 Bit        Muxes := 1     
	   4 Input      3 Bit        Muxes := 1     
	   2 Input      3 Bit        Muxes := 3     
	   8 Input      1 Bit        Muxes := 15    
	   2 Input      1 Bit        Muxes := 10    
	   9 Input      1 Bit        Muxes := 2     
Module PE__parameterized7 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      9 Bit       Adders := 3     
	   2 Input      8 Bit       Adders := 1     
	   2 Input      3 Bit       Adders := 1     
+---Registers : 
	               16 Bit    Registers := 3     
	                9 Bit    Registers := 2     
	                8 Bit    Registers := 2     
	                3 Bit    Registers := 4     
	                1 Bit    Registers := 6     
+---Muxes : 
	   2 Input     16 Bit        Muxes := 1     
	   8 Input      9 Bit        Muxes := 2     
	   2 Input      8 Bit        Muxes := 1     
	   8 Input      8 Bit        Muxes := 1     
	   2 Input      7 Bit        Muxes := 1     
	   8 Input      3 Bit        Muxes := 1     
	   4 Input      3 Bit        Muxes := 1     
	   2 Input      3 Bit        Muxes := 3     
	   8 Input      1 Bit        Muxes := 15    
	   2 Input      1 Bit        Muxes := 10    
	   9 Input      1 Bit        Muxes := 2     
Module PE_cluster 
Detailed RTL Component Info : 
+---Adders : 
	   3 Input     16 Bit       Adders := 3     
+---Registers : 
	               16 Bit    Registers := 3     
---------------------------------------------------------------------------------
Finished RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 1728 (col length:144)
BRAMs: 624 (col length: RAMB18 144 RAMB36 72)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
Warning: Parallel synthesis criteria is not met 
INFO: [Synth 8-4471] merging register 'gen_X[0].gen_Y[0].pe/iter_reg[2:0]' into 'gen_X[0].gen_Y[0].pe/iter_reg[2:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:115]
INFO: [Synth 8-4471] merging register 'gen_X[0].gen_Y[0].pe/filt_count_reg[7:0]' into 'gen_X[0].gen_Y[0].pe/filt_count_reg[7:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:104]
INFO: [Synth 8-4471] merging register 'gen_X[0].gen_Y[0].pe/iter_reg[2:0]' into 'gen_X[0].gen_Y[0].pe/iter_reg[2:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:115]
INFO: [Synth 8-4471] merging register 'gen_X[0].gen_Y[1].pe/iter_reg[2:0]' into 'gen_X[0].gen_Y[1].pe/iter_reg[2:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:115]
INFO: [Synth 8-4471] merging register 'gen_X[0].gen_Y[1].pe/filt_count_reg[7:0]' into 'gen_X[0].gen_Y[1].pe/filt_count_reg[7:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:104]
INFO: [Synth 8-4471] merging register 'gen_X[0].gen_Y[1].pe/iter_reg[2:0]' into 'gen_X[0].gen_Y[1].pe/iter_reg[2:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:115]
INFO: [Synth 8-4471] merging register 'gen_X[0].gen_Y[2].pe/iter_reg[2:0]' into 'gen_X[0].gen_Y[2].pe/iter_reg[2:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:115]
INFO: [Synth 8-4471] merging register 'gen_X[0].gen_Y[2].pe/filt_count_reg[7:0]' into 'gen_X[0].gen_Y[2].pe/filt_count_reg[7:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:104]
INFO: [Synth 8-4471] merging register 'gen_X[0].gen_Y[2].pe/iter_reg[2:0]' into 'gen_X[0].gen_Y[2].pe/iter_reg[2:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:115]
INFO: [Synth 8-4471] merging register 'gen_X[1].gen_Y[0].pe/iter_reg[2:0]' into 'gen_X[1].gen_Y[0].pe/iter_reg[2:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:115]
INFO: [Synth 8-4471] merging register 'gen_X[1].gen_Y[0].pe/filt_count_reg[7:0]' into 'gen_X[1].gen_Y[0].pe/filt_count_reg[7:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:104]
INFO: [Synth 8-4471] merging register 'gen_X[1].gen_Y[0].pe/iter_reg[2:0]' into 'gen_X[1].gen_Y[0].pe/iter_reg[2:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:115]
INFO: [Synth 8-4471] merging register 'gen_X[1].gen_Y[1].pe/iter_reg[2:0]' into 'gen_X[1].gen_Y[1].pe/iter_reg[2:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:115]
INFO: [Synth 8-4471] merging register 'gen_X[1].gen_Y[1].pe/filt_count_reg[7:0]' into 'gen_X[1].gen_Y[1].pe/filt_count_reg[7:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:104]
INFO: [Synth 8-4471] merging register 'gen_X[1].gen_Y[1].pe/iter_reg[2:0]' into 'gen_X[1].gen_Y[1].pe/iter_reg[2:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:115]
INFO: [Synth 8-4471] merging register 'gen_X[1].gen_Y[2].pe/iter_reg[2:0]' into 'gen_X[1].gen_Y[2].pe/iter_reg[2:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:115]
INFO: [Synth 8-4471] merging register 'gen_X[1].gen_Y[2].pe/filt_count_reg[7:0]' into 'gen_X[1].gen_Y[2].pe/filt_count_reg[7:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:104]
INFO: [Synth 8-4471] merging register 'gen_X[1].gen_Y[2].pe/iter_reg[2:0]' into 'gen_X[1].gen_Y[2].pe/iter_reg[2:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:115]
INFO: [Synth 8-4471] merging register 'gen_X[2].gen_Y[0].pe/iter_reg[2:0]' into 'gen_X[2].gen_Y[0].pe/iter_reg[2:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:115]
INFO: [Synth 8-4471] merging register 'gen_X[2].gen_Y[0].pe/filt_count_reg[7:0]' into 'gen_X[2].gen_Y[0].pe/filt_count_reg[7:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:104]
INFO: [Synth 8-4471] merging register 'gen_X[2].gen_Y[0].pe/iter_reg[2:0]' into 'gen_X[2].gen_Y[0].pe/iter_reg[2:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:115]
INFO: [Synth 8-4471] merging register 'gen_X[2].gen_Y[1].pe/iter_reg[2:0]' into 'gen_X[2].gen_Y[1].pe/iter_reg[2:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:115]
INFO: [Synth 8-4471] merging register 'gen_X[2].gen_Y[1].pe/filt_count_reg[7:0]' into 'gen_X[2].gen_Y[1].pe/filt_count_reg[7:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:104]
INFO: [Synth 8-4471] merging register 'gen_X[2].gen_Y[1].pe/iter_reg[2:0]' into 'gen_X[2].gen_Y[1].pe/iter_reg[2:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:115]
INFO: [Synth 8-4471] merging register 'gen_X[2].gen_Y[2].pe/iter_reg[2:0]' into 'gen_X[2].gen_Y[2].pe/iter_reg[2:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:115]
INFO: [Synth 8-4471] merging register 'gen_X[2].gen_Y[2].pe/filt_count_reg[7:0]' into 'gen_X[2].gen_Y[2].pe/filt_count_reg[7:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:104]
INFO: [Synth 8-4471] merging register 'gen_X[2].gen_Y[2].pe/iter_reg[2:0]' into 'gen_X[2].gen_Y[2].pe/iter_reg[2:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:115]
INFO: [Synth 8-5544] ROM "gen_X[0].gen_Y[0].pe/iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_X[0].gen_Y[0].pe/filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_X[0].gen_Y[1].pe/iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_X[0].gen_Y[1].pe/filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_X[0].gen_Y[2].pe/iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_X[0].gen_Y[2].pe/filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_X[1].gen_Y[0].pe/iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_X[1].gen_Y[0].pe/filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_X[1].gen_Y[1].pe/iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_X[1].gen_Y[1].pe/filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_X[1].gen_Y[2].pe/iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_X[1].gen_Y[2].pe/filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_X[2].gen_Y[0].pe/iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_X[2].gen_Y[0].pe/filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_X[2].gen_Y[1].pe/iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_X[2].gen_Y[1].pe/filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_X[2].gen_Y[2].pe/iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_X[2].gen_Y[2].pe/filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "gen_X[0].gen_Y[0].pe/filt_count" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "gen_X[0].gen_Y[0].pe/state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "gen_X[0].gen_Y[0].pe/state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "gen_X[0].gen_Y[0].pe/state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "gen_X[0].gen_Y[0].pe/r_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "gen_X[0].gen_Y[0].pe/w_addr" won't be mapped to RAM because it is too sparse
INFO: [Common 17-14] Message 'Synth 8-5546' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-5544] ROM "gen_X[0].gen_Y[0].pe/iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_X[0].gen_Y[0].pe/filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_X[0].gen_Y[1].pe/iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_X[0].gen_Y[1].pe/filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_X[0].gen_Y[2].pe/iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_X[0].gen_Y[2].pe/filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_X[1].gen_Y[0].pe/iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_X[1].gen_Y[0].pe/filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_X[1].gen_Y[1].pe/iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_X[1].gen_Y[1].pe/filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_X[1].gen_Y[2].pe/iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_X[1].gen_Y[2].pe/filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_X[2].gen_Y[0].pe/iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_X[2].gen_Y[0].pe/filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_X[2].gen_Y[1].pe/iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_X[2].gen_Y[1].pe/filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_X[2].gen_Y[2].pe/iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "gen_X[2].gen_Y[2].pe/filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
DSP Report: Generating DSP gen_X[0].gen_Y[2].pe/mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register gen_X[0].gen_Y[2].pe/filt_in_reg_reg is absorbed into DSP gen_X[0].gen_Y[2].pe/mac_0/out_reg.
DSP Report: register gen_X[0].gen_Y[2].pe/act_in_reg_reg is absorbed into DSP gen_X[0].gen_Y[2].pe/mac_0/out_reg.
DSP Report: register gen_X[0].gen_Y[2].pe/mac_0/out_reg is absorbed into DSP gen_X[0].gen_Y[2].pe/mac_0/out_reg.
DSP Report: operator gen_X[0].gen_Y[2].pe/mac_0/out0 is absorbed into DSP gen_X[0].gen_Y[2].pe/mac_0/out_reg.
DSP Report: operator gen_X[0].gen_Y[2].pe/mac_0/out1 is absorbed into DSP gen_X[0].gen_Y[2].pe/mac_0/out_reg.
DSP Report: Generating DSP gen_X[0].gen_Y[1].pe/mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register gen_X[0].gen_Y[1].pe/filt_in_reg_reg is absorbed into DSP gen_X[0].gen_Y[1].pe/mac_0/out_reg.
DSP Report: register gen_X[0].gen_Y[1].pe/act_in_reg_reg is absorbed into DSP gen_X[0].gen_Y[1].pe/mac_0/out_reg.
DSP Report: register gen_X[0].gen_Y[1].pe/mac_0/out_reg is absorbed into DSP gen_X[0].gen_Y[1].pe/mac_0/out_reg.
DSP Report: operator gen_X[0].gen_Y[1].pe/mac_0/out0 is absorbed into DSP gen_X[0].gen_Y[1].pe/mac_0/out_reg.
DSP Report: operator gen_X[0].gen_Y[1].pe/mac_0/out1 is absorbed into DSP gen_X[0].gen_Y[1].pe/mac_0/out_reg.
DSP Report: Generating DSP gen_X[0].gen_Y[0].pe/mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register gen_X[0].gen_Y[0].pe/filt_in_reg_reg is absorbed into DSP gen_X[0].gen_Y[0].pe/mac_0/out_reg.
DSP Report: register gen_X[0].gen_Y[0].pe/act_in_reg_reg is absorbed into DSP gen_X[0].gen_Y[0].pe/mac_0/out_reg.
DSP Report: register gen_X[0].gen_Y[0].pe/mac_0/out_reg is absorbed into DSP gen_X[0].gen_Y[0].pe/mac_0/out_reg.
DSP Report: operator gen_X[0].gen_Y[0].pe/mac_0/out0 is absorbed into DSP gen_X[0].gen_Y[0].pe/mac_0/out_reg.
DSP Report: operator gen_X[0].gen_Y[0].pe/mac_0/out1 is absorbed into DSP gen_X[0].gen_Y[0].pe/mac_0/out_reg.
DSP Report: Generating DSP pe_out_reg[0], operation Mode is: (PCIN+(A:0x0):B+C)'.
DSP Report: register pe_out_reg[0] is absorbed into DSP pe_out_reg[0].
DSP Report: operator psum_adder_return is absorbed into DSP pe_out_reg[0].
DSP Report: Generating DSP gen_X[1].gen_Y[2].pe/mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register gen_X[1].gen_Y[2].pe/filt_in_reg_reg is absorbed into DSP gen_X[1].gen_Y[2].pe/mac_0/out_reg.
DSP Report: register gen_X[1].gen_Y[2].pe/act_in_reg_reg is absorbed into DSP gen_X[1].gen_Y[2].pe/mac_0/out_reg.
DSP Report: register gen_X[1].gen_Y[2].pe/mac_0/out_reg is absorbed into DSP gen_X[1].gen_Y[2].pe/mac_0/out_reg.
DSP Report: operator gen_X[1].gen_Y[2].pe/mac_0/out0 is absorbed into DSP gen_X[1].gen_Y[2].pe/mac_0/out_reg.
DSP Report: operator gen_X[1].gen_Y[2].pe/mac_0/out1 is absorbed into DSP gen_X[1].gen_Y[2].pe/mac_0/out_reg.
DSP Report: Generating DSP gen_X[1].gen_Y[1].pe/mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register gen_X[1].gen_Y[1].pe/filt_in_reg_reg is absorbed into DSP gen_X[1].gen_Y[1].pe/mac_0/out_reg.
DSP Report: register gen_X[1].gen_Y[1].pe/act_in_reg_reg is absorbed into DSP gen_X[1].gen_Y[1].pe/mac_0/out_reg.
DSP Report: register gen_X[1].gen_Y[1].pe/mac_0/out_reg is absorbed into DSP gen_X[1].gen_Y[1].pe/mac_0/out_reg.
DSP Report: operator gen_X[1].gen_Y[1].pe/mac_0/out0 is absorbed into DSP gen_X[1].gen_Y[1].pe/mac_0/out_reg.
DSP Report: operator gen_X[1].gen_Y[1].pe/mac_0/out1 is absorbed into DSP gen_X[1].gen_Y[1].pe/mac_0/out_reg.
DSP Report: Generating DSP gen_X[1].gen_Y[0].pe/mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register gen_X[1].gen_Y[0].pe/filt_in_reg_reg is absorbed into DSP gen_X[1].gen_Y[0].pe/mac_0/out_reg.
DSP Report: register gen_X[1].gen_Y[0].pe/act_in_reg_reg is absorbed into DSP gen_X[1].gen_Y[0].pe/mac_0/out_reg.
DSP Report: register gen_X[1].gen_Y[0].pe/mac_0/out_reg is absorbed into DSP gen_X[1].gen_Y[0].pe/mac_0/out_reg.
DSP Report: operator gen_X[1].gen_Y[0].pe/mac_0/out0 is absorbed into DSP gen_X[1].gen_Y[0].pe/mac_0/out_reg.
DSP Report: operator gen_X[1].gen_Y[0].pe/mac_0/out1 is absorbed into DSP gen_X[1].gen_Y[0].pe/mac_0/out_reg.
DSP Report: Generating DSP pe_out_reg[1], operation Mode is: (PCIN+(A:0x0):B+C)'.
DSP Report: register pe_out_reg[1] is absorbed into DSP pe_out_reg[1].
DSP Report: operator psum_adder0_return is absorbed into DSP pe_out_reg[1].
DSP Report: Generating DSP gen_X[2].gen_Y[2].pe/mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register gen_X[2].gen_Y[2].pe/filt_in_reg_reg is absorbed into DSP gen_X[2].gen_Y[2].pe/mac_0/out_reg.
DSP Report: register gen_X[2].gen_Y[2].pe/act_in_reg_reg is absorbed into DSP gen_X[2].gen_Y[2].pe/mac_0/out_reg.
DSP Report: register gen_X[2].gen_Y[2].pe/mac_0/out_reg is absorbed into DSP gen_X[2].gen_Y[2].pe/mac_0/out_reg.
DSP Report: operator gen_X[2].gen_Y[2].pe/mac_0/out0 is absorbed into DSP gen_X[2].gen_Y[2].pe/mac_0/out_reg.
DSP Report: operator gen_X[2].gen_Y[2].pe/mac_0/out1 is absorbed into DSP gen_X[2].gen_Y[2].pe/mac_0/out_reg.
DSP Report: Generating DSP gen_X[2].gen_Y[1].pe/mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register gen_X[2].gen_Y[1].pe/filt_in_reg_reg is absorbed into DSP gen_X[2].gen_Y[1].pe/mac_0/out_reg.
DSP Report: register gen_X[2].gen_Y[1].pe/act_in_reg_reg is absorbed into DSP gen_X[2].gen_Y[1].pe/mac_0/out_reg.
DSP Report: register gen_X[2].gen_Y[1].pe/mac_0/out_reg is absorbed into DSP gen_X[2].gen_Y[1].pe/mac_0/out_reg.
DSP Report: operator gen_X[2].gen_Y[1].pe/mac_0/out0 is absorbed into DSP gen_X[2].gen_Y[1].pe/mac_0/out_reg.
DSP Report: operator gen_X[2].gen_Y[1].pe/mac_0/out1 is absorbed into DSP gen_X[2].gen_Y[1].pe/mac_0/out_reg.
DSP Report: Generating DSP gen_X[2].gen_Y[0].pe/mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register gen_X[2].gen_Y[0].pe/filt_in_reg_reg is absorbed into DSP gen_X[2].gen_Y[0].pe/mac_0/out_reg.
DSP Report: register gen_X[2].gen_Y[0].pe/act_in_reg_reg is absorbed into DSP gen_X[2].gen_Y[0].pe/mac_0/out_reg.
DSP Report: register gen_X[2].gen_Y[0].pe/mac_0/out_reg is absorbed into DSP gen_X[2].gen_Y[0].pe/mac_0/out_reg.
DSP Report: operator gen_X[2].gen_Y[0].pe/mac_0/out0 is absorbed into DSP gen_X[2].gen_Y[0].pe/mac_0/out_reg.
DSP Report: operator gen_X[2].gen_Y[0].pe/mac_0/out1 is absorbed into DSP gen_X[2].gen_Y[0].pe/mac_0/out_reg.
DSP Report: Generating DSP pe_out_reg[2], operation Mode is: (PCIN+(A:0x0):B+C)'.
DSP Report: register pe_out_reg[2] is absorbed into DSP pe_out_reg[2].
DSP Report: operator psum_adder1_return is absorbed into DSP pe_out_reg[2].
INFO: [Synth 8-4471] merging register 'router_cluster_0/router_psum_gen[0].router_psum_0/iter_reg[2:0]' into 'router_cluster_0/router_psum_gen[0].router_psum_0/iter_reg[2:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router_psum.sv:70]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_addr_psum[9]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_addr_psum[8]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_addr_psum[7]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_addr_psum[6]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_addr_psum[5]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_addr_psum[4]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_addr_psum[3]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_addr_psum[2]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_addr_psum[1]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_addr_psum[0]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_data_psum[15]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_data_psum[14]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_data_psum[13]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_data_psum[12]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_data_psum[11]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_data_psum[10]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_data_psum[9]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_data_psum[8]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_data_psum[7]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_data_psum[6]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_data_psum[5]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_data_psum[4]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_data_psum[3]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_data_psum[2]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_data_psum[1]
WARNING: [Synth 8-3331] design HMNoC_cluster has unconnected port w_data_psum[0]
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\router_cluster_0/router_psum_gen[0].router_psum_0/state_reg[2] )
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:29 ; elapsed = 00:00:37 . Memory (MB): peak = 1532.438 ; gain = 1250.684
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------

Distributed RAM: Preliminary Mapping  Report (see note below)
+--------------+-------------------------------------------------------+-----------+----------------------+-------------------------------+
|Module Name   | RTL Object                                            | Inference | Size (Depth x Width) | Primitives                    | 
+--------------+-------------------------------------------------------+-----------+----------------------+-------------------------------+
|HMNoC_cluster | pe_cluster_0/gen_X[0].gen_Y[2].pe/spad_pe0/mem_reg    | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster | pe_cluster_0/gen_X[0].gen_Y[1].pe/spad_pe0/mem_reg    | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster | pe_cluster_0/gen_X[0].gen_Y[0].pe/spad_pe0/mem_reg    | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster | pe_cluster_0/gen_X[1].gen_Y[2].pe/spad_pe0/mem_reg    | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster | pe_cluster_0/gen_X[1].gen_Y[1].pe/spad_pe0/mem_reg    | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster | pe_cluster_0/gen_X[1].gen_Y[0].pe/spad_pe0/mem_reg    | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster | pe_cluster_0/gen_X[2].gen_Y[2].pe/spad_pe0/mem_reg    | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster | pe_cluster_0/gen_X[2].gen_Y[1].pe/spad_pe0/mem_reg    | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster | pe_cluster_0/gen_X[2].gen_Y[0].pe/spad_pe0/mem_reg    | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster | GLB_cluster_0/glb_iact_gen[0].glb_iact_inst/mem_reg   | Implied   | 1 K x 16             | RAM64X1D x 32  RAM64M8 x 32   | 
|HMNoC_cluster | GLB_cluster_0/glb_psum_gen[0].glb_psum_inst/mem_reg   | Implied   | 1 K x 16             | RAM64X1D x 32  RAM64M8 x 32   | 
|HMNoC_cluster | GLB_cluster_0/glb_wght_gen[0].glb_weight_inst/mem_reg | Implied   | 1 K x 16             | RAM64X1D x 32  RAM64M8 x 32   | 
+--------------+-------------------------------------------------------+-----------+----------------------+-------------------------------+

Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.

DSP: Preliminary Mapping  Report (see note below)
+------------+----------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|Module Name | DSP Mapping          | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | 
+------------+----------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|PE_cluster  | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE_cluster  | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE_cluster  | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE_cluster  | (PCIN+(A:0x0):B+C)'  | 30     | 16     | 16     | -      | -1     | 0    | 0    | 0    | -    | -     | 0    | 1    | 
|PE_cluster  | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE_cluster  | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE_cluster  | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE_cluster  | (PCIN+(A:0x0):B+C)'  | 30     | 16     | 16     | -      | -1     | 0    | 0    | 0    | -    | -     | 0    | 1    | 
|PE_cluster  | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE_cluster  | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE_cluster  | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE_cluster  | (PCIN+(A:0x0):B+C)'  | 30     | 16     | 16     | -      | -1     | 0    | 0    | 0    | -    | -     | 0    | 1    | 
+------------+----------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+

Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:38 ; elapsed = 00:00:50 . Memory (MB): peak = 1973.750 ; gain = 1691.996
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:47 ; elapsed = 00:00:58 . Memory (MB): peak = 2127.305 ; gain = 1845.551
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------

Distributed RAM: Final Mapping  Report
+--------------+-------------------------------------------------------+-----------+----------------------+-------------------------------+
|Module Name   | RTL Object                                            | Inference | Size (Depth x Width) | Primitives                    | 
+--------------+-------------------------------------------------------+-----------+----------------------+-------------------------------+
|HMNoC_cluster | pe_cluster_0/gen_X[0].gen_Y[2].pe/spad_pe0/mem_reg    | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster | pe_cluster_0/gen_X[0].gen_Y[1].pe/spad_pe0/mem_reg    | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster | pe_cluster_0/gen_X[0].gen_Y[0].pe/spad_pe0/mem_reg    | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster | pe_cluster_0/gen_X[1].gen_Y[2].pe/spad_pe0/mem_reg    | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster | pe_cluster_0/gen_X[1].gen_Y[1].pe/spad_pe0/mem_reg    | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster | pe_cluster_0/gen_X[1].gen_Y[0].pe/spad_pe0/mem_reg    | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster | pe_cluster_0/gen_X[2].gen_Y[2].pe/spad_pe0/mem_reg    | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster | pe_cluster_0/gen_X[2].gen_Y[1].pe/spad_pe0/mem_reg    | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster | pe_cluster_0/gen_X[2].gen_Y[0].pe/spad_pe0/mem_reg    | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster | GLB_cluster_0/glb_iact_gen[0].glb_iact_inst/mem_reg   | Implied   | 1 K x 16             | RAM64X1D x 32  RAM64M8 x 32   | 
|HMNoC_cluster | GLB_cluster_0/glb_psum_gen[0].glb_psum_inst/mem_reg   | Implied   | 1 K x 16             | RAM64X1D x 32  RAM64M8 x 32   | 
|HMNoC_cluster | GLB_cluster_0/glb_wght_gen[0].glb_weight_inst/mem_reg | Implied   | 1 K x 16             | RAM64X1D x 32  RAM64M8 x 32   | 
+--------------+-------------------------------------------------------+-----------+----------------------+-------------------------------+

---------------------------------------------------------------------------------
Finished ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:49 ; elapsed = 00:01:01 . Memory (MB): peak = 2128.727 ; gain = 1846.973
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:50 ; elapsed = 00:01:02 . Memory (MB): peak = 2128.727 ; gain = 1846.973
---------------------------------------------------------------------------------

Report Check Netlist: 
+------+------------------+-------+---------+-------+------------------+
|      |Item              |Errors |Warnings |Status |Description       |
+------+------------------+-------+---------+-------+------------------+
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:50 ; elapsed = 00:01:02 . Memory (MB): peak = 2128.727 ; gain = 1846.973
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:51 ; elapsed = 00:01:03 . Memory (MB): peak = 2128.727 ; gain = 1846.973
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:51 ; elapsed = 00:01:03 . Memory (MB): peak = 2128.727 ; gain = 1846.973
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:51 ; elapsed = 00:01:03 . Memory (MB): peak = 2128.727 ; gain = 1846.973
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:51 ; elapsed = 00:01:03 . Memory (MB): peak = 2128.727 ; gain = 1846.973
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------

Report BlackBoxes: 
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+

Report Cell Usage: 
+------+------------------+------+
|      |Cell              |Count |
+------+------------------+------+
|1     |BUFG              |     1|
|2     |DSP_ALU           |    12|
|3     |DSP_A_B_DATA      |     9|
|4     |DSP_A_B_DATA_1    |     3|
|5     |DSP_C_DATA        |    12|
|6     |DSP_MULTIPLIER    |     9|
|7     |DSP_MULTIPLIER_1  |     3|
|8     |DSP_M_DATA        |    12|
|9     |DSP_OUTPUT        |    12|
|10    |DSP_PREADD        |    12|
|11    |DSP_PREADD_DATA   |     9|
|12    |DSP_PREADD_DATA_1 |     3|
|13    |LUT1              |   174|
|14    |LUT2              |   134|
|15    |LUT3              |   138|
|16    |LUT4              |   256|
|17    |LUT5              |   258|
|18    |LUT6              |  1088|
|19    |MUXF7             |   132|
|20    |MUXF8             |    21|
|21    |RAM64M8           |   240|
|22    |RAM64X1D          |   240|
|23    |FDRE              |   793|
|24    |FDSE              |    24|
|25    |IBUF              |    70|
|26    |OBUF              |    17|
+------+------------------+------+

Report Instance Areas: 
+------+-------------------------------------------+------------------------------------------------------------+------+
|      |Instance                                   |Module                                                      |Cells |
+------+-------------------------------------------+------------------------------------------------------------+------+
|1     |top                                        |                                                            |  3682|
|2     |  GLB_cluster_0                            |GLB_cluster                                                 |   600|
|3     |    \glb_iact_gen[0].glb_iact_inst         |glb_iact                                                    |   200|
|4     |    \glb_psum_gen[0].glb_psum_inst         |glb_psum                                                    |   200|
|5     |    \glb_wght_gen[0].glb_weight_inst       |glb_weight                                                  |   200|
|6     |  pe_cluster_0                             |PE_cluster                                                  |  2566|
|7     |    \pe_out_reg[0]                         |\pe_cluster_0/pe_out_reg[0]_funnel                          |     8|
|8     |    \pe_out_reg[1]                         |\pe_cluster_0/pe_out_reg[0]_funnel__1                       |     8|
|9     |    \pe_out_reg[2]                         |\pe_cluster_0/pe_out_reg[0]_funnel__2                       |     8|
|10    |    \gen_X[0].gen_Y[0].pe                  |PE                                                          |   288|
|11    |      mac_0                                |MAC_14                                                      |    30|
|12    |        out_reg                            |\pe_cluster_0/gen_X[0].gen_Y[2].pe/mac_0/out_reg_funnel__2  |     8|
|13    |      spad_pe0                             |SPad_15                                                     |   105|
|14    |    \gen_X[0].gen_Y[1].pe                  |PE__parameterized0                                          |   280|
|15    |      mac_0                                |MAC_12                                                      |    30|
|16    |        out_reg                            |\pe_cluster_0/gen_X[0].gen_Y[2].pe/mac_0/out_reg_funnel__1  |     8|
|17    |      spad_pe0                             |SPad_13                                                     |   105|
|18    |    \gen_X[0].gen_Y[2].pe                  |PE__parameterized1                                          |   284|
|19    |      mac_0                                |MAC_10                                                      |    30|
|20    |        out_reg                            |\pe_cluster_0/gen_X[0].gen_Y[2].pe/mac_0/out_reg_funnel     |     8|
|21    |      spad_pe0                             |SPad_11                                                     |   105|
|22    |    \gen_X[1].gen_Y[0].pe                  |PE__parameterized2                                          |   276|
|23    |      mac_0                                |MAC_8                                                       |    30|
|24    |        out_reg                            |\pe_cluster_0/gen_X[0].gen_Y[2].pe/mac_0/out_reg_funnel__5  |     8|
|25    |      spad_pe0                             |SPad_9                                                      |   105|
|26    |    \gen_X[1].gen_Y[1].pe                  |PE__parameterized3                                          |   284|
|27    |      mac_0                                |MAC_6                                                       |    30|
|28    |        out_reg                            |\pe_cluster_0/gen_X[0].gen_Y[2].pe/mac_0/out_reg_funnel__4  |     8|
|29    |      spad_pe0                             |SPad_7                                                      |   105|
|30    |    \gen_X[1].gen_Y[2].pe                  |PE__parameterized4                                          |   285|
|31    |      mac_0                                |MAC_4                                                       |    30|
|32    |        out_reg                            |\pe_cluster_0/gen_X[0].gen_Y[2].pe/mac_0/out_reg_funnel__3  |     8|
|33    |      spad_pe0                             |SPad_5                                                      |   105|
|34    |    \gen_X[2].gen_Y[0].pe                  |PE__parameterized5                                          |   279|
|35    |      mac_0                                |MAC_2                                                       |    30|
|36    |        out_reg                            |\pe_cluster_0/gen_X[0].gen_Y[2].pe/mac_0/out_reg_funnel__8  |     8|
|37    |      spad_pe0                             |SPad_3                                                      |   105|
|38    |    \gen_X[2].gen_Y[1].pe                  |PE__parameterized6                                          |   284|
|39    |      mac_0                                |MAC_0                                                       |    30|
|40    |        out_reg                            |\pe_cluster_0/gen_X[0].gen_Y[2].pe/mac_0/out_reg_funnel__7  |     8|
|41    |      spad_pe0                             |SPad_1                                                      |   105|
|42    |    \gen_X[2].gen_Y[2].pe                  |PE__parameterized7                                          |   282|
|43    |      mac_0                                |MAC                                                         |    30|
|44    |        out_reg                            |\pe_cluster_0/gen_X[0].gen_Y[2].pe/mac_0/out_reg_funnel__6  |     8|
|45    |      spad_pe0                             |SPad                                                        |   105|
|46    |  router_cluster_0                         |router_cluster                                              |   264|
|47    |    \router_iact_gen[0].router_iact_0      |router_iact                                                 |    62|
|48    |    \router_psum_gen[0].router_psum_0      |router_psum                                                 |   140|
|49    |    \router_weight_gen[0].router_weight_0  |router_weight                                               |    62|
+------+-------------------------------------------+------------------------------------------------------------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:51 ; elapsed = 00:01:03 . Memory (MB): peak = 2128.727 ; gain = 1846.973
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 26 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:39 ; elapsed = 00:00:49 . Memory (MB): peak = 2128.727 ; gain = 747.742
Synthesis Optimization Complete : Time (s): cpu = 00:00:51 ; elapsed = 00:01:03 . Memory (MB): peak = 2128.727 ; gain = 1846.973
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Netlist 29-17] Analyzing 716 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2134.805 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 563 instances were transformed.
  BUFG => BUFGCE: 1 instances
  DSP48E2 => DSP48E2 (DSP_ALU, DSP_A_B_DATA, DSP_C_DATA, DSP_MULTIPLIER, DSP_M_DATA, DSP_OUTPUT, DSP_PREADD_DATA, DSP_PREADD): 12 instances
  IBUF => IBUF (IBUFCTRL, INBUF): 70 instances
  RAM64M8 => RAM64M8 (RAMD64E, RAMD64E, RAMD64E, RAMD64E, RAMD64E, RAMD64E, RAMD64E, RAMD64E): 240 instances
  RAM64X1D => RAM64X1D (RAMD64E, RAMD64E): 240 instances

INFO: [Common 17-83] Releasing license: Synthesis
265 Infos, 170 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:09 . Memory (MB): peak = 2134.805 ; gain = 1853.051
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2134.805 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint 'D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.runs/synth_1/HMNoC_cluster.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file HMNoC_cluster_utilization_synth.rpt -pb HMNoC_cluster_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Fri Dec 13 10:49:32 2019...


================================================
FILE: synth/HMNoC_cluster_utilization_synth.rpt
================================================
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec  6 23:38:27 MST 2018
| Date         : Fri Dec 13 10:49:32 2019
| Host         : Karthi running 64-bit major release  (build 9200)
| Command      : report_utilization -file HMNoC_cluster_utilization_synth.rpt -pb HMNoC_cluster_utilization_synth.pb
| Design       : HMNoC_cluster
| Device       : xczu7evffvf1517-1LV
| Design State : Synthesized
---------------------------------------------------------------------------------------------------------------------

Utilization Design Information

Table of Contents
-----------------
1. CLB Logic
1.1 Summary of Registers by Type
2. BLOCKRAM
3. ARITHMETIC
4. I/O
5. CLOCK
6. ADVANCED
7. CONFIGURATION
8. Primitives
9. Black Boxes
10. Instantiated Netlists

1. CLB Logic
------------

+----------------------------+------+-------+-----------+-------+
|          Site Type         | Used | Fixed | Available | Util% |
+----------------------------+------+-------+-----------+-------+
| CLB LUTs*                  | 4196 |     0 |    230400 |  1.82 |
|   LUT as Logic             | 1796 |     0 |    230400 |  0.78 |
|   LUT as Memory            | 2400 |     0 |    101760 |  2.36 |
|     LUT as Distributed RAM | 2400 |     0 |           |       |
|     LUT as Shift Register  |    0 |     0 |           |       |
| CLB Registers              |  817 |     0 |    460800 |  0.18 |
|   Register as Flip Flop    |  817 |     0 |    460800 |  0.18 |
|   Register as Latch        |    0 |     0 |    460800 |  0.00 |
| CARRY8                     |    0 |     0 |     28800 |  0.00 |
| F7 Muxes                   |  132 |     0 |    115200 |  0.11 |
| F8 Muxes                   |   21 |     0 |     57600 |  0.04 |
| F9 Muxes                   |    0 |     0 |     28800 |  0.00 |
+----------------------------+------+-------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.


1.1 Summary of Registers by Type
--------------------------------

+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0     |            _ |           - |            - |
| 0     |            _ |           - |          Set |
| 0     |            _ |           - |        Reset |
| 0     |            _ |         Set |            - |
| 0     |            _ |       Reset |            - |
| 0     |          Yes |           - |            - |
| 0     |          Yes |           - |          Set |
| 0     |          Yes |           - |        Reset |
| 24    |          Yes |         Set |            - |
| 793   |          Yes |       Reset |            - |
+-------+--------------+-------------+--------------+


2. BLOCKRAM
-----------

+----------------+------+-------+-----------+-------+
|    Site Type   | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| Block RAM Tile |    0 |     0 |       312 |  0.00 |
|   RAMB36/FIFO* |    0 |     0 |       312 |  0.00 |
|   RAMB18       |    0 |     0 |       624 |  0.00 |
| URAM           |    0 |     0 |        96 |  0.00 |
+----------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E2 or one FIFO18E2. However, if a FIFO18E2 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E2


3. ARITHMETIC
-------------

+----------------+------+-------+-----------+-------+
|    Site Type   | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| DSPs           |   12 |     0 |      1728 |  0.69 |
|   DSP48E2 only |   12 |       |           |       |
+----------------+------+-------+-----------+-------+


4. I/O
------

+------------+------+-------+-----------+-------+
|  Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
| Bonded IOB |   87 |     0 |       464 | 18.75 |
+------------+------+-------+-----------+-------+


5. CLOCK
--------

+----------------------+------+-------+-----------+-------+
|       Site Type      | Used | Fixed | Available | Util% |
+----------------------+------+-------+-----------+-------+
| GLOBAL CLOCK BUFFERs |    1 |     0 |       544 |  0.18 |
|   BUFGCE             |    1 |     0 |       208 |  0.48 |
|   BUFGCE_DIV         |    0 |     0 |        32 |  0.00 |
|   BUFG_GT            |    0 |     0 |       144 |  0.00 |
|   BUFG_PS            |    0 |     0 |        96 |  0.00 |
|   BUFGCTRL*          |    0 |     0 |        64 |  0.00 |
| PLL                  |    0 |     0 |        16 |  0.00 |
| MMCM                 |    0 |     0 |         8 |  0.00 |
+----------------------+------+-------+-----------+-------+
* Note: Each used BUFGCTRL counts as two global buffer resources. This table does not include global clocking resources, only buffer cell usage. See the Clock Utilization Report (report_clock_utilization) for detailed accounting of global clocking resource availability.


6. ADVANCED
-----------

+-----------------+------+-------+-----------+-------+
|    Site Type    | Used | Fixed | Available | Util% |
+-----------------+------+-------+-----------+-------+
| GTHE4_CHANNEL   |    0 |     0 |        24 |  0.00 |
| GTHE4_COMMON    |    0 |     0 |         6 |  0.00 |
| OBUFDS_GTE4     |    0 |     0 |        12 |  0.00 |
| OBUFDS_GTE4_ADV |    0 |     0 |        12 |  0.00 |
| PCIE40E4        |    0 |     0 |         2 |  0.00 |
| PS8             |    0 |     0 |         1 |  0.00 |
| SYSMONE4        |    0 |     0 |         1 |  0.00 |
| VCU             |    0 |     0 |         1 |  0.00 |
+-----------------+------+-------+-----------+-------+


7. CONFIGURATION
----------------

+-------------+------+-------+-----------+-------+
|  Site Type  | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2     |    0 |     0 |         4 |  0.00 |
| DNA_PORTE2  |    0 |     0 |         1 |  0.00 |
| EFUSE_USR   |    0 |     0 |         1 |  0.00 |
| FRAME_ECCE4 |    0 |     0 |         1 |  0.00 |
| ICAPE3      |    0 |     0 |         2 |  0.00 |
| MASTER_JTAG |    0 |     0 |         1 |  0.00 |
| STARTUPE3   |    0 |     0 |         1 |  0.00 |
+-------------+------+-------+-----------+-------+


8. Primitives
-------------

+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| RAMD64E  | 2400 |                 CLB |
| LUT6     | 1088 |                 CLB |
| FDRE     |  793 |            Register |
| LUT5     |  258 |                 CLB |
| LUT4     |  256 |                 CLB |
| LUT1     |  174 |                 CLB |
| LUT3     |  138 |                 CLB |
| LUT2     |  134 |                 CLB |
| MUXF7    |  132 |                 CLB |
| INBUF    |   70 |                 I/O |
| IBUFCTRL |   70 |              Others |
| FDSE     |   24 |            Register |
| MUXF8    |   21 |                 CLB |
| OBUF     |   17 |                 I/O |
| DSP48E2  |   12 |          Arithmetic |
| BUFGCE   |    1 |               Clock |
+----------+------+---------------------+


9. Black Boxes
--------------

+----------+------+
| Ref Name | Used |
+----------+------+


10. Instantiated Netlists
-------------------------

+----------+------+
| Ref Name | Used |
+----------+------+




================================================
FILE: synth/HMNoC_top.vds
================================================
#-----------------------------------------------------------
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec  6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
# Start of session at: Fri Dec 13 11:06:45 2019
# Process ID: 21196
# Current directory: D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.runs/synth_1
# Command line: vivado.exe -log HMNoC_top.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source HMNoC_top.tcl
# Log file: D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.runs/synth_1/HMNoC_top.vds
# Journal file: D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.runs/synth_1\vivado.jou
#-----------------------------------------------------------
source HMNoC_top.tcl -notrace
Command: synth_design -top HMNoC_top -part xczu7ev-ffvf1517-1LV-i
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xczu7ev'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xczu7ev'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 21496 
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 362.484 ; gain = 101.301
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'HMNoC_top' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
	Parameter DATA_BITWIDTH bound to: 16 - type: integer 
	Parameter ADDR_BITWIDTH bound to: 10 - type: integer 
	Parameter DATA_WIDTH bound to: 16 - type: integer 
	Parameter ADDR_WIDTH bound to: 9 - type: integer 
	Parameter NUM_GLB_IACT bound to: 1 - type: integer 
	Parameter NUM_GLB_PSUM bound to: 1 - type: integer 
	Parameter NUM_GLB_WGHT bound to: 1 - type: integer 
	Parameter ADDR_BITWIDTH_GLB bound to: 10 - type: integer 
	Parameter ADDR_BITWIDTH_SPAD bound to: 9 - type: integer 
	Parameter NUM_ROUTER_PSUM bound to: 1 - type: integer 
	Parameter NUM_ROUTER_IACT bound to: 1 - type: integer 
	Parameter NUM_ROUTER_WGHT bound to: 1 - type: integer 
	Parameter kernel_size bound to: 32'sb00000000000000000000000000000011 
	Parameter act_size bound to: 32'sb00000000000000000000000000000101 
	Parameter X_dim bound to: 32'sb00000000000000000000000000000011 
	Parameter Y_dim bound to: 32'sb00000000000000000000000000000011 
	Parameter W_READ_ADDR bound to: 0 - type: integer 
	Parameter A_READ_ADDR bound to: 0 - type: integer 
	Parameter W_LOAD_ADDR bound to: 0 - type: integer 
	Parameter A_LOAD_ADDR bound to: 0 - type: integer 
	Parameter PSUM_READ_ADDR bound to: 0 - type: integer 
	Parameter PSUM_LOAD_ADDR bound to: 0 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'HMNoC_cluster_west' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:23]
	Parameter DATA_BITWIDTH bound to: 16 - type: integer 
	Parameter ADDR_BITWIDTH bound to: 10 - type: integer 
	Parameter DATA_WIDTH bound to: 16 - type: integer 
	Parameter ADDR_WIDTH bound to: 9 - type: integer 
	Parameter NUM_GLB_IACT bound to: 1 - type: integer 
	Parameter NUM_GLB_PSUM bound to: 1 - type: integer 
	Parameter NUM_GLB_WGHT bound to: 1 - type: integer 
	Parameter ADDR_BITWIDTH_GLB bound to: 10 - type: integer 
	Parameter ADDR_BITWIDTH_SPAD bound to: 9 - type: integer 
	Parameter NUM_ROUTER_PSUM bound to: 1 - type: integer 
	Parameter NUM_ROUTER_IACT bound to: 1 - type: integer 
	Parameter NUM_ROUTER_WGHT bound to: 1 - type: integer 
	Parameter kernel_size bound to: 32'sb00000000000000000000000000000011 
	Parameter act_size bound to: 32'sb00000000000000000000000000000101 
	Parameter X_dim bound to: 32'sb00000000000000000000000000000011 
	Parameter Y_dim bound to: 32'sb00000000000000000000000000000011 
	Parameter W_READ_ADDR bound to: 0 - type: integer 
	Parameter A_READ_ADDR bound to: 0 - type: integer 
	Parameter W_LOAD_ADDR bound to: 0 - type: integer 
	Parameter A_LOAD_ADDR bound to: 0 - type: integer 
	Parameter PSUM_READ_ADDR bound to: 0 - type: integer 
	Parameter PSUM_LOAD_ADDR bound to: 0 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'GLB_cluster' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/GLB_cluster.sv:23]
	Parameter DATA_BITWIDTH bound to: 16 - type: integer 
	Parameter ADDR_BITWIDTH bound to: 10 - type: integer 
	Parameter NUM_GLB_IACT bound to: 1 - type: integer 
	Parameter NUM_GLB_PSUM bound to: 1 - type: integer 
	Parameter NUM_GLB_WGHT bound to: 1 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'glb_iact' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:23]
	Parameter DATA_BITWIDTH bound to: 16 - type: integer 
	Parameter ADDR_BITWIDTH bound to: 10 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'glb_iact' (1#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:23]
INFO: [Synth 8-6157] synthesizing module 'glb_psum' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_psum.sv:23]
	Parameter DATA_BITWIDTH bound to: 16 - type: integer 
	Parameter ADDR_BITWIDTH bound to: 10 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'glb_psum' (2#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_psum.sv:23]
INFO: [Synth 8-6157] synthesizing module 'glb_weight' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_weight.sv:23]
	Parameter DATA_BITWIDTH bound to: 16 - type: integer 
	Parameter ADDR_BITWIDTH bound to: 10 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'glb_weight' (3#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_weight.sv:23]
INFO: [Synth 8-6155] done synthesizing module 'GLB_cluster' (4#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/GLB_cluster.sv:23]
WARNING: [Synth 8-6104] Input port 'west_data_i_iact' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:253]
WARNING: [Synth 8-6104] Input port 'west_data_i_wght' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:255]
INFO: [Synth 8-6157] synthesizing module 'router_cluster' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router_cluster.sv:23]
	Parameter DATA_WIDTH bound to: 16 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'router' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router.sv:22]
	Parameter DATA_WIDTH bound to: 16 - type: integer 
INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router.sv:85]
INFO: [Synth 8-6155] done synthesizing module 'router' (5#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router.sv:22]
INFO: [Synth 8-6155] done synthesizing module 'router_cluster' (6#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router_cluster.sv:23]
WARNING: [Synth 8-6104] Input port 'filt_in' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:316]
WARNING: [Synth 8-6104] Input port 'act_in' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:360]
WARNING: [Synth 8-6104] Input port 'w_data_psum' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:405]
WARNING: [Synth 8-6104] Input port 'write_en_psum' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:406]
INFO: [Synth 8-6157] synthesizing module 'PE_cluster' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE_cluster.sv:23]
	Parameter DATA_WIDTH bound to: 16 - type: integer 
	Parameter ADDR_WIDTH bound to: 9 - type: integer 
	Parameter X_dim bound to: 32'sb00000000000000000000000000000011 
	Parameter Y_dim bound to: 32'sb00000000000000000000000000000011 
	Parameter kernel_size bound to: 32'sb00000000000000000000000000000011 
	Parameter act_size bound to: 32'sb00000000000000000000000000000101 
	Parameter W_READ_ADDR bound to: 0 - type: integer 
	Parameter A_READ_ADDR bound to: 100 - type: integer 
	Parameter W_LOAD_ADDR bound to: 0 - type: integer 
	Parameter A_LOAD_ADDR bound to: 100 - type: integer 
	Parameter PSUM_ADDR bound to: 500 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'PE' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:23]
	Parameter DATA_WIDTH bound to: 16 - type: integer 
	Parameter ADDR_WIDTH bound to: 9 - type: integer 
	Parameter W_READ_ADDR bound to: 0 - type: integer 
	Parameter A_READ_ADDR bound to: 100 - type: integer 
	Parameter W_LOAD_ADDR bound to: 0 - type: integer 
	Parameter A_LOAD_ADDR bound to: 100 - type: integer 
	Parameter PSUM_ADDR bound to: 500 - type: integer 
	Parameter kernel_size bound to: 32'sb00000000000000000000000000000011 
	Parameter act_size bound to: 32'sb00000000000000000000000000000101 
INFO: [Synth 8-6157] synthesizing module 'SPad' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/SPad.sv:23]
	Parameter DATA_BITWIDTH bound to: 16 - type: integer 
	Parameter ADDR_BITWIDTH bound to: 9 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'SPad' (7#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/SPad.sv:23]
INFO: [Synth 8-6157] synthesizing module 'MAC' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/MAC.sv:23]
	Parameter IN_BITWIDTH bound to: 16 - type: integer 
	Parameter OUT_BITWIDTH bound to: 16 - type: integer 
WARNING: [Synth 8-6014] Unused sequential element mult_out_reg was removed.  [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/MAC.sv:36]
INFO: [Synth 8-6155] done synthesizing module 'MAC' (8#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/MAC.sv:23]
INFO: [Synth 8-6157] synthesizing module 'mux2' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/mux2.sv:23]
	Parameter WIDTH bound to: 16 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'mux2' (9#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/mux2.sv:23]
INFO: [Synth 8-155] case statement is not full and has no default [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:120]
INFO: [Synth 8-6155] done synthesizing module 'PE' (10#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:23]
INFO: [Synth 8-6157] synthesizing module 'PE__parameterized0' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:23]
	Parameter DATA_WIDTH bound to: 16 - type: integer 
	Parameter ADDR_WIDTH bound to: 9 - type: integer 
	Parameter W_READ_ADDR bound to: 3 - type: integer 
	Parameter A_READ_ADDR bound to: 105 - type: integer 
	Parameter W_LOAD_ADDR bound to: 0 - type: integer 
	Parameter A_LOAD_ADDR bound to: 100 - type: integer 
	Parameter PSUM_ADDR bound to: 500 - type: integer 
	Parameter kernel_size bound to: 32'sb00000000000000000000000000000011 
	Parameter act_size bound to: 32'sb00000000000000000000000000000101 
INFO: [Synth 8-155] case statement is not full and has no default [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:120]
INFO: [Synth 8-6155] done synthesizing module 'PE__parameterized0' (10#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:23]
INFO: [Synth 8-6157] synthesizing module 'PE__parameterized1' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:23]
	Parameter DATA_WIDTH bound to: 16 - type: integer 
	Parameter ADDR_WIDTH bound to: 9 - type: integer 
	Parameter W_READ_ADDR bound to: 6 - type: integer 
	Parameter A_READ_ADDR bound to: 110 - type: integer 
	Parameter W_LOAD_ADDR bound to: 0 - type: integer 
	Parameter A_LOAD_ADDR bound to: 100 - type: integer 
	Parameter PSUM_ADDR bound to: 500 - type: integer 
	Parameter kernel_size bound to: 32'sb00000000000000000000000000000011 
	Parameter act_size bound to: 32'sb00000000000000000000000000000101 
INFO: [Synth 8-155] case statement is not full and has no default [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:120]
INFO: [Synth 8-6155] done synthesizing module 'PE__parameterized1' (10#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:23]
INFO: [Synth 8-6157] synthesizing module 'PE__parameterized2' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:23]
	Parameter DATA_WIDTH bound to: 16 - type: integer 
	Parameter ADDR_WIDTH bound to: 9 - type: integer 
	Parameter W_READ_ADDR bound to: 0 - type: integer 
	Parameter A_READ_ADDR bound to: 101 - type: integer 
	Parameter W_LOAD_ADDR bound to: 0 - type: integer 
	Parameter A_LOAD_ADDR bound to: 100 - type: integer 
	Parameter PSUM_ADDR bound to: 500 - type: integer 
	Parameter kernel_size bound to: 32'sb00000000000000000000000000000011 
	Parameter act_size bound to: 32'sb00000000000000000000000000000101 
INFO: [Synth 8-155] case statement is not full and has no default [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:120]
INFO: [Synth 8-6155] done synthesizing module 'PE__parameterized2' (10#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:23]
INFO: [Synth 8-6157] synthesizing module 'PE__parameterized3' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:23]
	Parameter DATA_WIDTH bound to: 16 - type: integer 
	Parameter ADDR_WIDTH bound to: 9 - type: integer 
	Parameter W_READ_ADDR bound to: 3 - type: integer 
	Parameter A_READ_ADDR bound to: 106 - type: integer 
	Parameter W_LOAD_ADDR bound to: 0 - type: integer 
	Parameter A_LOAD_ADDR bound to: 100 - type: integer 
	Parameter PSUM_ADDR bound to: 500 - type: integer 
	Parameter kernel_size bound to: 32'sb00000000000000000000000000000011 
	Parameter act_size bound to: 32'sb00000000000000000000000000000101 
INFO: [Synth 8-155] case statement is not full and has no default [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:120]
INFO: [Synth 8-6155] done synthesizing module 'PE__parameterized3' (10#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:23]
INFO: [Synth 8-6157] synthesizing module 'PE__parameterized4' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:23]
	Parameter DATA_WIDTH bound to: 16 - type: integer 
	Parameter ADDR_WIDTH bound to: 9 - type: integer 
	Parameter W_READ_ADDR bound to: 6 - type: integer 
	Parameter A_READ_ADDR bound to: 111 - type: integer 
	Parameter W_LOAD_ADDR bound to: 0 - type: integer 
	Parameter A_LOAD_ADDR bound to: 100 - type: integer 
	Parameter PSUM_ADDR bound to: 500 - type: integer 
	Parameter kernel_size bound to: 32'sb00000000000000000000000000000011 
	Parameter act_size bound to: 32'sb00000000000000000000000000000101 
INFO: [Synth 8-155] case statement is not full and has no default [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:120]
INFO: [Synth 8-6155] done synthesizing module 'PE__parameterized4' (10#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:23]
INFO: [Synth 8-6157] synthesizing module 'PE__parameterized5' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:23]
	Parameter DATA_WIDTH bound to: 16 - type: integer 
	Parameter ADDR_WIDTH bound to: 9 - type: integer 
	Parameter W_READ_ADDR bound to: 0 - type: integer 
	Parameter A_READ_ADDR bound to: 102 - type: integer 
	Parameter W_LOAD_ADDR bound to: 0 - type: integer 
	Parameter A_LOAD_ADDR bound to: 100 - type: integer 
	Parameter PSUM_ADDR bound to: 500 - type: integer 
	Parameter kernel_size bound to: 32'sb00000000000000000000000000000011 
	Parameter act_size bound to: 32'sb00000000000000000000000000000101 
INFO: [Synth 8-155] case statement is not full and has no default [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:120]
INFO: [Synth 8-6155] done synthesizing module 'PE__parameterized5' (10#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:23]
INFO: [Synth 8-6157] synthesizing module 'PE__parameterized6' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:23]
	Parameter DATA_WIDTH bound to: 16 - type: integer 
	Parameter ADDR_WIDTH bound to: 9 - type: integer 
	Parameter W_READ_ADDR bound to: 3 - type: integer 
	Parameter A_READ_ADDR bound to: 107 - type: integer 
	Parameter W_LOAD_ADDR bound to: 0 - type: integer 
	Parameter A_LOAD_ADDR bound to: 100 - type: integer 
	Parameter PSUM_ADDR bound to: 500 - type: integer 
	Parameter kernel_size bound to: 32'sb00000000000000000000000000000011 
	Parameter act_size bound to: 32'sb00000000000000000000000000000101 
INFO: [Synth 8-155] case statement is not full and has no default [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:120]
INFO: [Synth 8-6155] done synthesizing module 'PE__parameterized6' (10#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:23]
INFO: [Synth 8-6157] synthesizing module 'PE__parameterized7' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:23]
	Parameter DATA_WIDTH bound to: 16 - type: integer 
	Parameter ADDR_WIDTH bound to: 9 - type: integer 
	Parameter W_READ_ADDR bound to: 6 - type: integer 
	Parameter A_READ_ADDR bound to: 112 - type: integer 
	Parameter W_LOAD_ADDR bound to: 0 - type: integer 
	Parameter A_LOAD_ADDR bound to: 100 - type: integer 
	Parameter PSUM_ADDR bound to: 500 - type: integer 
	Parameter kernel_size bound to: 32'sb00000000000000000000000000000011 
	Parameter act_size bound to: 32'sb00000000000000000000000000000101 
INFO: [Synth 8-155] case statement is not full and has no default [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:120]
INFO: [Synth 8-6155] done synthesizing module 'PE__parameterized7' (10#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:23]
INFO: [Synth 8-6155] done synthesizing module 'PE_cluster' (11#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE_cluster.sv:23]
WARNING: [Synth 8-3848] Net west_data_o_psum in module/entity HMNoC_cluster_west does not have driver. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:213]
WARNING: [Synth 8-3848] Net west_enable_o_psum in module/entity HMNoC_cluster_west does not have driver. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:214]
INFO: [Synth 8-6155] done synthesizing module 'HMNoC_cluster_west' (12#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:23]
WARNING: [Synth 8-6104] Input port 'north_data_i_wght' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:177]
WARNING: [Synth 8-6104] Input port 'north_enable_i_wght' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:178]
WARNING: [Synth 8-6104] Input port 'west_data_i_wght' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:197]
WARNING: [Synth 8-6104] Input port 'west_enable_i_wght' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:198]
WARNING: [Synth 8-6104] Input port 'north_data_i_iact' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:221]
WARNING: [Synth 8-6104] Input port 'north_enable_i_iact' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:222]
WARNING: [Synth 8-6104] Input port 'west_data_i_iact' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:241]
WARNING: [Synth 8-6104] Input port 'west_enable_i_iact' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:242]
WARNING: [Synth 8-6104] Input port 'north_data_i_psum' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:266]
WARNING: [Synth 8-6104] Input port 'north_enable_i_psum' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:267]
WARNING: [Synth 8-6104] Input port 'west_data_i_psum' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:286]
WARNING: [Synth 8-6104] Input port 'west_enable_i_psum' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:287]
WARNING: [Synth 8-6104] Input port 'south_data_i_wght' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:364]
WARNING: [Synth 8-6104] Input port 'south_enable_i_wght' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:365]
WARNING: [Synth 8-6104] Input port 'west_data_i_wght' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:394]
WARNING: [Synth 8-6104] Input port 'west_enable_i_wght' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:395]
WARNING: [Synth 8-6104] Input port 'south_data_i_iact' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:408]
WARNING: [Synth 8-6104] Input port 'south_enable_i_iact' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:409]
WARNING: [Synth 8-6104] Input port 'south_data_i_psum' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:453]
WARNING: [Synth 8-6104] Input port 'south_enable_i_psum' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:454]
WARNING: [Synth 8-6104] Input port 'west_data_i_psum' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:483]
WARNING: [Synth 8-6104] Input port 'west_enable_i_psum' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:484]
INFO: [Synth 8-6157] synthesizing module 'HMNoC_cluster_east' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_east.sv:23]
	Parameter DATA_BITWIDTH bound to: 16 - type: integer 
	Parameter ADDR_BITWIDTH bound to: 10 - type: integer 
	Parameter DATA_WIDTH bound to: 16 - type: integer 
	Parameter ADDR_WIDTH bound to: 9 - type: integer 
	Parameter NUM_GLB_IACT bound to: 1 - type: integer 
	Parameter NUM_GLB_PSUM bound to: 1 - type: integer 
	Parameter NUM_GLB_WGHT bound to: 1 - type: integer 
	Parameter ADDR_BITWIDTH_GLB bound to: 10 - type: integer 
	Parameter ADDR_BITWIDTH_SPAD bound to: 9 - type: integer 
	Parameter NUM_ROUTER_PSUM bound to: 1 - type: integer 
	Parameter NUM_ROUTER_IACT bound to: 1 - type: integer 
	Parameter NUM_ROUTER_WGHT bound to: 1 - type: integer 
	Parameter kernel_size bound to: 32'sb00000000000000000000000000000011 
	Parameter act_size bound to: 32'sb00000000000000000000000000000101 
	Parameter X_dim bound to: 32'sb00000000000000000000000000000011 
	Parameter Y_dim bound to: 32'sb00000000000000000000000000000011 
	Parameter W_READ_ADDR bound to: 0 - type: integer 
	Parameter A_READ_ADDR bound to: 0 - type: integer 
	Parameter W_LOAD_ADDR bound to: 0 - type: integer 
	Parameter A_LOAD_ADDR bound to: 0 - type: integer 
	Parameter PSUM_READ_ADDR bound to: 0 - type: integer 
	Parameter PSUM_LOAD_ADDR bound to: 0 - type: integer 
WARNING: [Synth 8-6104] Input port 'east_data_i_iact' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_east.sv:253]
WARNING: [Synth 8-6104] Input port 'east_data_i_wght' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_east.sv:255]
WARNING: [Synth 8-689] width (1) of port connection 'west_data_o_wght' does not match port width (16) of module 'router_cluster' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_east.sv:316]
WARNING: [Synth 8-689] width (1) of port connection 'east_data_o_wght' does not match port width (16) of module 'router_cluster' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_east.sv:326]
WARNING: [Synth 8-6104] Input port 'act_in' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_east.sv:370]
WARNING: [Synth 8-6104] Input port 'w_data_psum' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_east.sv:415]
WARNING: [Synth 8-6104] Input port 'write_en_psum' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_east.sv:416]
WARNING: [Synth 8-3848] Net east_data_o_psum in module/entity HMNoC_cluster_east does not have driver. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_east.sv:222]
WARNING: [Synth 8-3848] Net east_enable_o_psum in module/entity HMNoC_cluster_east does not have driver. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_east.sv:223]
INFO: [Synth 8-6155] done synthesizing module 'HMNoC_cluster_east' (13#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_east.sv:23]
WARNING: [Synth 8-6104] Input port 'north_data_i_wght' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:570]
WARNING: [Synth 8-6104] Input port 'north_enable_i_wght' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:571]
WARNING: [Synth 8-6104] Input port 'east_data_i_wght' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:580]
WARNING: [Synth 8-6104] Input port 'east_enable_i_wght' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:581]
WARNING: [Synth 8-6104] Input port 'north_data_i_iact' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:614]
WARNING: [Synth 8-6104] Input port 'north_enable_i_iact' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:615]
WARNING: [Synth 8-6104] Input port 'east_data_i_iact' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:624]
WARNING: [Synth 8-6104] Input port 'east_enable_i_iact' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:625]
WARNING: [Synth 8-6104] Input port 'east_data_i_psum' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:669]
WARNING: [Synth 8-6104] Input port 'east_enable_i_psum' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:670]
WARNING: [Synth 8-6104] Input port 'south_data_i_wght' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:755]
WARNING: [Synth 8-6104] Input port 'south_enable_i_wght' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:756]
WARNING: [Synth 8-6104] Input port 'east_data_i_wght' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:775]
WARNING: [Synth 8-6104] Input port 'east_enable_i_wght' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:776]
WARNING: [Synth 8-6104] Input port 'south_data_i_iact' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:799]
WARNING: [Synth 8-6104] Input port 'south_enable_i_iact' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:800]
WARNING: [Synth 8-6104] Input port 'east_data_i_iact' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:819]
WARNING: [Synth 8-6104] Input port 'east_enable_i_iact' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:820]
WARNING: [Synth 8-6104] Input port 'south_data_i_psum' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:844]
WARNING: [Synth 8-6104] Input port 'south_enable_i_psum' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:845]
WARNING: [Synth 8-6104] Input port 'east_data_i_psum' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:864]
WARNING: [Synth 8-6104] Input port 'east_enable_i_psum' has an internal driver [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:865]
WARNING: [Synth 8-3848] Net west_enable_i_wght in module/entity HMNoC_top does not have driver. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:184]
WARNING: [Synth 8-3848] Net west_enable_i_iact in module/entity HMNoC_top does not have driver. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:228]
WARNING: [Synth 8-3848] Net west_data_i_psum in module/entity HMNoC_top does not have driver. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:272]
WARNING: [Synth 8-3848] Net west_enable_i_psum in module/entity HMNoC_top does not have driver. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:273]
INFO: [Synth 8-6155] done synthesizing module 'HMNoC_top' (14#1) [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
WARNING: [Synth 8-3331] design HMNoC_cluster_east has unconnected port east_data_o_psum[15]
WARNING: [Synth 8-3331] design HMNoC_cluster_east has unconnected port east_data_o_psum[14]
WARNING: [Synth 8-3331] design HMNoC_cluster_east has unconnected port east_data_o_psum[13]
WARNING: [Synth 8-3331] design HMNoC_cluster_east has unconnected port east_data_o_psum[12]
WARNING: [Synth 8-3331] design HMNoC_cluster_east has unconnected port east_data_o_psum[11]
WARNING: [Synth 8-3331] design HMNoC_cluster_east has unconnected port east_data_o_psum[10]
WARNING: [Synth 8-3331] design HMNoC_cluster_east has unconnected port east_data_o_psum[9]
WARNING: [Synth 8-3331] design HMNoC_cluster_east has unconnected port east_data_o_psum[8]
WARNING: [Synth 8-3331] design HMNoC_cluster_east has unconnected port east_data_o_psum[7]
WARNING: [Synth 8-3331] design HMNoC_cluster_east has unconnected port east_data_o_psum[6]
WARNING: [Synth 8-3331] design HMNoC_cluster_east has unconnected port east_data_o_psum[5]
WARNING: [Synth 8-3331] design HMNoC_cluster_east has unconnected port east_data_o_psum[4]
WARNING: [Synth 8-3331] design HMNoC_cluster_east has unconnected port east_data_o_psum[3]
WARNING: [Synth 8-3331] design HMNoC_cluster_east has unconnected port east_data_o_psum[2]
WARNING: [Synth 8-3331] design HMNoC_cluster_east has unconnected port east_data_o_psum[1]
WARNING: [Synth 8-3331] design HMNoC_cluster_east has unconnected port east_data_o_psum[0]
WARNING: [Synth 8-3331] design HMNoC_cluster_east has unconnected port east_enable_o_psum
WARNING: [Synth 8-3331] design HMNoC_cluster_west has unconnected port west_data_o_psum[15]
WARNING: [Synth 8-3331] design HMNoC_cluster_west has unconnected port west_data_o_psum[14]
WARNING: [Synth 8-3331] design HMNoC_cluster_west has unconnected port west_data_o_psum[13]
WARNING: [Synth 8-3331] design HMNoC_cluster_west has unconnected port west_data_o_psum[12]
WARNING: [Synth 8-3331] design HMNoC_cluster_west has unconnected port west_data_o_psum[11]
WARNING: [Synth 8-3331] design HMNoC_cluster_west has unconnected port west_data_o_psum[10]
WARNING: [Synth 8-3331] design HMNoC_cluster_west has unconnected port west_data_o_psum[9]
WARNING: [Synth 8-3331] design HMNoC_cluster_west has unconnected port west_data_o_psum[8]
WARNING: [Synth 8-3331] design HMNoC_cluster_west has unconnected port west_data_o_psum[7]
WARNING: [Synth 8-3331] design HMNoC_cluster_west has unconnected port west_data_o_psum[6]
WARNING: [Synth 8-3331] design HMNoC_cluster_west has unconnected port west_data_o_psum[5]
WARNING: [Synth 8-3331] design HMNoC_cluster_west has unconnected port west_data_o_psum[4]
WARNING: [Synth 8-3331] design HMNoC_cluster_west has unconnected port west_data_o_psum[3]
WARNING: [Synth 8-3331] design HMNoC_cluster_west has unconnected port west_data_o_psum[2]
WARNING: [Synth 8-3331] design HMNoC_cluster_west has unconnected port west_data_o_psum[1]
WARNING: [Synth 8-3331] design HMNoC_cluster_west has unconnected port west_data_o_psum[0]
WARNING: [Synth 8-3331] design HMNoC_cluster_west has unconnected port west_enable_o_psum
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 435.688 ; gain = 174.504
---------------------------------------------------------------------------------

Report Check Netlist: 
+------+------------------+-------+---------+-------+------------------+
|      |Item              |Errors |Warnings |Status |Description       |
+------+------------------+-------+---------+-------+------------------+
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:write_en_psum to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:243]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[15] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:243]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[14] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:243]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[13] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:243]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[12] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:243]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[11] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:243]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[10] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:243]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[9] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:243]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[8] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:243]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[7] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:243]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[6] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:243]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[5] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:243]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[4] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:243]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[3] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:243]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[2] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:243]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[1] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:243]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[0] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:243]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:west_data_i_wght[15] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:284]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:west_data_i_wght[14] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:284]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:west_data_i_wght[13] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:284]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:west_data_i_wght[12] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:284]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:west_data_i_wght[11] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:284]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:west_data_i_wght[10] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:284]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:west_data_i_wght[9] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:284]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:west_data_i_wght[8] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:284]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:west_data_i_wght[7] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:284]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:west_data_i_wght[6] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:284]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:west_data_i_wght[5] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:284]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:west_data_i_wght[4] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:284]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:west_data_i_wght[3] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:284]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:west_data_i_wght[2] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:284]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:west_data_i_wght[1] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:284]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:west_data_i_wght[0] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:284]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:west_data_i_iact[15] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:284]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:west_data_i_iact[14] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:284]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:west_data_i_iact[13] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:284]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:west_data_i_iact[12] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:284]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:west_data_i_iact[11] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:284]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:west_data_i_iact[10] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:284]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:west_data_i_iact[9] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:284]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:west_data_i_iact[8] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:284]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:west_data_i_iact[7] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:284]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:west_data_i_iact[6] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:284]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:west_data_i_iact[5] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:284]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:west_data_i_iact[4] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:284]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:west_data_i_iact[3] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:284]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:west_data_i_iact[2] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:284]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:west_data_i_iact[1] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:284]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:west_data_i_iact[0] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:284]
WARNING: [Synth 8-3295] tying undriven pin pe_cluster_0:act_in[15] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:431]
WARNING: [Synth 8-3295] tying undriven pin pe_cluster_0:act_in[14] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:431]
WARNING: [Synth 8-3295] tying undriven pin pe_cluster_0:act_in[13] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:431]
WARNING: [Synth 8-3295] tying undriven pin pe_cluster_0:act_in[12] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:431]
WARNING: [Synth 8-3295] tying undriven pin pe_cluster_0:act_in[11] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:431]
WARNING: [Synth 8-3295] tying undriven pin pe_cluster_0:act_in[10] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:431]
WARNING: [Synth 8-3295] tying undriven pin pe_cluster_0:act_in[9] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:431]
WARNING: [Synth 8-3295] tying undriven pin pe_cluster_0:act_in[8] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:431]
WARNING: [Synth 8-3295] tying undriven pin pe_cluster_0:act_in[7] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:431]
WARNING: [Synth 8-3295] tying undriven pin pe_cluster_0:act_in[6] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:431]
WARNING: [Synth 8-3295] tying undriven pin pe_cluster_0:act_in[5] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:431]
WARNING: [Synth 8-3295] tying undriven pin pe_cluster_0:act_in[4] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:431]
WARNING: [Synth 8-3295] tying undriven pin pe_cluster_0:act_in[3] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:431]
WARNING: [Synth 8-3295] tying undriven pin pe_cluster_0:act_in[2] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:431]
WARNING: [Synth 8-3295] tying undriven pin pe_cluster_0:act_in[1] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:431]
WARNING: [Synth 8-3295] tying undriven pin pe_cluster_0:act_in[0] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:431]
WARNING: [Synth 8-3295] tying undriven pin pe_cluster_0:filt_in[15] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:431]
WARNING: [Synth 8-3295] tying undriven pin pe_cluster_0:filt_in[14] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:431]
WARNING: [Synth 8-3295] tying undriven pin pe_cluster_0:filt_in[13] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:431]
WARNING: [Synth 8-3295] tying undriven pin pe_cluster_0:filt_in[12] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:431]
WARNING: [Synth 8-3295] tying undriven pin pe_cluster_0:filt_in[11] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:431]
WARNING: [Synth 8-3295] tying undriven pin pe_cluster_0:filt_in[10] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:431]
WARNING: [Synth 8-3295] tying undriven pin pe_cluster_0:filt_in[9] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:431]
WARNING: [Synth 8-3295] tying undriven pin pe_cluster_0:filt_in[8] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:431]
WARNING: [Synth 8-3295] tying undriven pin pe_cluster_0:filt_in[7] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:431]
WARNING: [Synth 8-3295] tying undriven pin pe_cluster_0:filt_in[6] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:431]
WARNING: [Synth 8-3295] tying undriven pin pe_cluster_0:filt_in[5] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:431]
WARNING: [Synth 8-3295] tying undriven pin pe_cluster_0:filt_in[4] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:431]
WARNING: [Synth 8-3295] tying undriven pin pe_cluster_0:filt_in[3] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:431]
WARNING: [Synth 8-3295] tying undriven pin pe_cluster_0:filt_in[2] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:431]
WARNING: [Synth 8-3295] tying undriven pin pe_cluster_0:filt_in[1] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:431]
WARNING: [Synth 8-3295] tying undriven pin pe_cluster_0:filt_in[0] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_west.sv:431]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:write_en_psum to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_east.sv:243]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[15] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_east.sv:243]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[14] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_east.sv:243]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[13] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_east.sv:243]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[12] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_east.sv:243]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[11] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_east.sv:243]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[10] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_east.sv:243]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[9] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_east.sv:243]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[8] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_east.sv:243]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[7] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_east.sv:243]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[6] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_east.sv:243]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[5] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_east.sv:243]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[4] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_east.sv:243]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[3] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_east.sv:243]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[2] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_east.sv:243]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[1] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_east.sv:243]
WARNING: [Synth 8-3295] tying undriven pin GLB_cluster_0:w_data_psum[0] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_east.sv:243]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:east_data_i_wght[15] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_east.sv:284]
WARNING: [Synth 8-3295] tying undriven pin router_cluster_0:east_data_i_wght[14] to constant 0 [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_cluster_east.sv:284]
INFO: [Common 17-14] Message 'Synth 8-3295' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 435.688 ; gain = 174.504
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 435.688 ; gain = 174.504
---------------------------------------------------------------------------------
INFO: [Device 21-403] Loading part xczu7ev-ffvf1517-1LV-i
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/constrs_1/new/constraints_1.xdc]
Finished Parsing XDC File [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/constrs_1/new/constraints_1.xdc]
Completed Processing XDC Constraints

Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1546.910 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1546.910 ; gain = 0.000
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.278 . Memory (MB): peak = 1546.910 ; gain = 0.000
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1546.910 ; gain = 1285.727
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xczu7ev-ffvf1517-1LV-i
INFO: [Synth 8-6742] Reading net delay rules and data
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1546.910 ; gain = 1285.727
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1546.910 ; gain = 1285.727
---------------------------------------------------------------------------------
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "filt_count" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "sum_in_mux_sel" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "sum_in_mux_sel" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "w_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "w_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "r_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "load_done" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "filt_count" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "sum_in_mux_sel" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "sum_in_mux_sel" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "w_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "w_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "r_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "load_done" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "filt_count" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "sum_in_mux_sel" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "sum_in_mux_sel" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "w_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "w_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "r_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "load_done" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "filt_count" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "sum_in_mux_sel" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "sum_in_mux_sel" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "w_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "w_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "r_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "load_done" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "filt_count" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "sum_in_mux_sel" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "sum_in_mux_sel" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "w_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "w_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "r_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "load_done" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "filt_count" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "sum_in_mux_sel" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "sum_in_mux_sel" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "w_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "w_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "r_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "load_done" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "filt_count" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "sum_in_mux_sel" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "sum_in_mux_sel" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "w_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "w_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "r_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "load_done" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "filt_count" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "sum_in_mux_sel" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "sum_in_mux_sel" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "w_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "w_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "r_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "load_done" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "filt_count" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "sum_in_mux_sel" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "sum_in_mux_sel" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "w_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "w_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "r_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "load_done" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 1546.910 ; gain = 1285.727
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start RTL Component Statistics 
---------------------------------------------------------------------------------
Detailed RTL Component Info : 
+---Adders : 
	   3 Input     16 Bit       Adders := 12    
	   2 Input      9 Bit       Adders := 96    
	   2 Input      8 Bit       Adders := 36    
	   2 Input      3 Bit       Adders := 36    
+---Registers : 
	               16 Bit    Registers := 204   
	                9 Bit    Registers := 72    
	                8 Bit    Registers := 72    
	                3 Bit    Registers := 144   
	                1 Bit    Registers := 216   
+---RAMs : 
	              16K Bit         RAMs := 12    
	               8K Bit         RAMs := 36    
+---Muxes : 
	   3 Input     16 Bit        Muxes := 48    
	   2 Input     16 Bit        Muxes := 72    
	   2 Input     14 Bit        Muxes := 48    
	   8 Input      9 Bit        Muxes := 72    
	   2 Input      8 Bit        Muxes := 36    
	   8 Input      8 Bit        Muxes := 36    
	   2 Input      7 Bit        Muxes := 36    
	   8 Input      3 Bit        Muxes := 36    
	   4 Input      3 Bit        Muxes := 36    
	   2 Input      3 Bit        Muxes := 108   
	  12 Input      1 Bit        Muxes := 48    
	   8 Input      1 Bit        Muxes := 540   
	   2 Input      1 Bit        Muxes := 360   
	   9 Input      1 Bit        Muxes := 72    
---------------------------------------------------------------------------------
Finished RTL Component Statistics 
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Hierarchical Component Statistics 
---------------------------------------------------------------------------------
Hierarchical RTL Component report 
Module glb_iact 
Detailed RTL Component Info : 
+---Registers : 
	               16 Bit    Registers := 1     
+---RAMs : 
	              16K Bit         RAMs := 1     
+---Muxes : 
	   3 Input     16 Bit        Muxes := 1     
	   2 Input     14 Bit        Muxes := 1     
Module glb_psum 
Detailed RTL Component Info : 
+---Registers : 
	               16 Bit    Registers := 1     
+---RAMs : 
	              16K Bit         RAMs := 1     
+---Muxes : 
	   3 Input     16 Bit        Muxes := 1     
	   2 Input     14 Bit        Muxes := 1     
Module glb_weight 
Detailed RTL Component Info : 
+---Registers : 
	               16 Bit    Registers := 1     
+---RAMs : 
	              16K Bit         RAMs := 1     
+---Muxes : 
	   3 Input     16 Bit        Muxes := 1     
	   2 Input     14 Bit        Muxes := 1     
Module router 
Detailed RTL Component Info : 
+---Muxes : 
	  12 Input      1 Bit        Muxes := 4     
Module SPad 
Detailed RTL Component Info : 
+---Registers : 
	               16 Bit    Registers := 1     
+---RAMs : 
	               8K Bit         RAMs := 1     
+---Muxes : 
	   3 Input     16 Bit        Muxes := 1     
	   2 Input     14 Bit        Muxes := 1     
Module MAC 
Detailed RTL Component Info : 
+---Registers : 
	               16 Bit    Registers := 1     
Module mux2 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input     16 Bit        Muxes := 1     
Module PE 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      9 Bit       Adders := 2     
	   2 Input      8 Bit       Adders := 1     
	   2 Input      3 Bit       Adders := 1     
+---Registers : 
	               16 Bit    Registers := 3     
	                9 Bit    Registers := 2     
	                8 Bit    Registers := 2     
	                3 Bit    Registers := 4     
	                1 Bit    Registers := 6     
+---Muxes : 
	   2 Input     16 Bit        Muxes := 1     
	   8 Input      9 Bit        Muxes := 2     
	   2 Input      8 Bit        Muxes := 1     
	   8 Input      8 Bit        Muxes := 1     
	   2 Input      7 Bit        Muxes := 1     
	   8 Input      3 Bit        Muxes := 1     
	   4 Input      3 Bit        Muxes := 1     
	   2 Input      3 Bit        Muxes := 3     
	   8 Input      1 Bit        Muxes := 15    
	   2 Input      1 Bit        Muxes := 10    
	   9 Input      1 Bit        Muxes := 2     
Module PE__parameterized0 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      9 Bit       Adders := 3     
	   2 Input      8 Bit       Adders := 1     
	   2 Input      3 Bit       Adders := 1     
+---Registers : 
	               16 Bit    Registers := 3     
	                9 Bit    Registers := 2     
	                8 Bit    Registers := 2     
	                3 Bit    Registers := 4     
	                1 Bit    Registers := 6     
+---Muxes : 
	   2 Input     16 Bit        Muxes := 1     
	   8 Input      9 Bit        Muxes := 2     
	   2 Input      8 Bit        Muxes := 1     
	   8 Input      8 Bit        Muxes := 1     
	   2 Input      7 Bit        Muxes := 1     
	   8 Input      3 Bit        Muxes := 1     
	   4 Input      3 Bit        Muxes := 1     
	   2 Input      3 Bit        Muxes := 3     
	   8 Input      1 Bit        Muxes := 15    
	   2 Input      1 Bit        Muxes := 10    
	   9 Input      1 Bit        Muxes := 2     
Module PE__parameterized1 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      9 Bit       Adders := 3     
	   2 Input      8 Bit       Adders := 1     
	   2 Input      3 Bit       Adders := 1     
+---Registers : 
	               16 Bit    Registers := 3     
	                9 Bit    Registers := 2     
	                8 Bit    Registers := 2     
	                3 Bit    Registers := 4     
	                1 Bit    Registers := 6     
+---Muxes : 
	   2 Input     16 Bit        Muxes := 1     
	   8 Input      9 Bit        Muxes := 2     
	   2 Input      8 Bit        Muxes := 1     
	   8 Input      8 Bit        Muxes := 1     
	   2 Input      7 Bit        Muxes := 1     
	   8 Input      3 Bit        Muxes := 1     
	   4 Input      3 Bit        Muxes := 1     
	   2 Input      3 Bit        Muxes := 3     
	   8 Input      1 Bit        Muxes := 15    
	   2 Input      1 Bit        Muxes := 10    
	   9 Input      1 Bit        Muxes := 2     
Module PE__parameterized2 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      9 Bit       Adders := 2     
	   2 Input      8 Bit       Adders := 1     
	   2 Input      3 Bit       Adders := 1     
+---Registers : 
	               16 Bit    Registers := 3     
	                9 Bit    Registers := 2     
	                8 Bit    Registers := 2     
	                3 Bit    Registers := 4     
	                1 Bit    Registers := 6     
+---Muxes : 
	   2 Input     16 Bit        Muxes := 1     
	   8 Input      9 Bit        Muxes := 2     
	   2 Input      8 Bit        Muxes := 1     
	   8 Input      8 Bit        Muxes := 1     
	   2 Input      7 Bit        Muxes := 1     
	   8 Input      3 Bit        Muxes := 1     
	   4 Input      3 Bit        Muxes := 1     
	   2 Input      3 Bit        Muxes := 3     
	   8 Input      1 Bit        Muxes := 15    
	   2 Input      1 Bit        Muxes := 10    
	   9 Input      1 Bit        Muxes := 2     
Module PE__parameterized3 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      9 Bit       Adders := 3     
	   2 Input      8 Bit       Adders := 1     
	   2 Input      3 Bit       Adders := 1     
+---Registers : 
	               16 Bit    Registers := 3     
	                9 Bit    Registers := 2     
	                8 Bit    Registers := 2     
	                3 Bit    Registers := 4     
	                1 Bit    Registers := 6     
+---Muxes : 
	   2 Input     16 Bit        Muxes := 1     
	   8 Input      9 Bit        Muxes := 2     
	   2 Input      8 Bit        Muxes := 1     
	   8 Input      8 Bit        Muxes := 1     
	   2 Input      7 Bit        Muxes := 1     
	   8 Input      3 Bit        Muxes := 1     
	   4 Input      3 Bit        Muxes := 1     
	   2 Input      3 Bit        Muxes := 3     
	   8 Input      1 Bit        Muxes := 15    
	   2 Input      1 Bit        Muxes := 10    
	   9 Input      1 Bit        Muxes := 2     
Module PE__parameterized4 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      9 Bit       Adders := 3     
	   2 Input      8 Bit       Adders := 1     
	   2 Input      3 Bit       Adders := 1     
+---Registers : 
	               16 Bit    Registers := 3     
	                9 Bit    Registers := 2     
	                8 Bit    Registers := 2     
	                3 Bit    Registers := 4     
	                1 Bit    Registers := 6     
+---Muxes : 
	   2 Input     16 Bit        Muxes := 1     
	   8 Input      9 Bit        Muxes := 2     
	   2 Input      8 Bit        Muxes := 1     
	   8 Input      8 Bit        Muxes := 1     
	   2 Input      7 Bit        Muxes := 1     
	   8 Input      3 Bit        Muxes := 1     
	   4 Input      3 Bit        Muxes := 1     
	   2 Input      3 Bit        Muxes := 3     
	   8 Input      1 Bit        Muxes := 15    
	   2 Input      1 Bit        Muxes := 10    
	   9 Input      1 Bit        Muxes := 2     
Module PE__parameterized5 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      9 Bit       Adders := 2     
	   2 Input      8 Bit       Adders := 1     
	   2 Input      3 Bit       Adders := 1     
+---Registers : 
	               16 Bit    Registers := 3     
	                9 Bit    Registers := 2     
	                8 Bit    Registers := 2     
	                3 Bit    Registers := 4     
	                1 Bit    Registers := 6     
+---Muxes : 
	   2 Input     16 Bit        Muxes := 1     
	   8 Input      9 Bit        Muxes := 2     
	   2 Input      8 Bit        Muxes := 1     
	   8 Input      8 Bit        Muxes := 1     
	   2 Input      7 Bit        Muxes := 1     
	   8 Input      3 Bit        Muxes := 1     
	   4 Input      3 Bit        Muxes := 1     
	   2 Input      3 Bit        Muxes := 3     
	   8 Input      1 Bit        Muxes := 15    
	   2 Input      1 Bit        Muxes := 10    
	   9 Input      1 Bit        Muxes := 2     
Module PE__parameterized6 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      9 Bit       Adders := 3     
	   2 Input      8 Bit       Adders := 1     
	   2 Input      3 Bit       Adders := 1     
+---Registers : 
	               16 Bit    Registers := 3     
	                9 Bit    Registers := 2     
	                8 Bit    Registers := 2     
	                3 Bit    Registers := 4     
	                1 Bit    Registers := 6     
+---Muxes : 
	   2 Input     16 Bit        Muxes := 1     
	   8 Input      9 Bit        Muxes := 2     
	   2 Input      8 Bit        Muxes := 1     
	   8 Input      8 Bit        Muxes := 1     
	   2 Input      7 Bit        Muxes := 1     
	   8 Input      3 Bit        Muxes := 1     
	   4 Input      3 Bit        Muxes := 1     
	   2 Input      3 Bit        Muxes := 3     
	   8 Input      1 Bit        Muxes := 15    
	   2 Input      1 Bit        Muxes := 10    
	   9 Input      1 Bit        Muxes := 2     
Module PE__parameterized7 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      9 Bit       Adders := 3     
	   2 Input      8 Bit       Adders := 1     
	   2 Input      3 Bit       Adders := 1     
+---Registers : 
	               16 Bit    Registers := 3     
	                9 Bit    Registers := 2     
	                8 Bit    Registers := 2     
	                3 Bit    Registers := 4     
	                1 Bit    Registers := 6     
+---Muxes : 
	   2 Input     16 Bit        Muxes := 1     
	   8 Input      9 Bit        Muxes := 2     
	   2 Input      8 Bit        Muxes := 1     
	   8 Input      8 Bit        Muxes := 1     
	   2 Input      7 Bit        Muxes := 1     
	   8 Input      3 Bit        Muxes := 1     
	   4 Input      3 Bit        Muxes := 1     
	   2 Input      3 Bit        Muxes := 3     
	   8 Input      1 Bit        Muxes := 15    
	   2 Input      1 Bit        Muxes := 10    
	   9 Input      1 Bit        Muxes := 2     
Module PE_cluster__hierPathDup__1 
Detailed RTL Component Info : 
+---Adders : 
	   3 Input     16 Bit       Adders := 3     
+---Registers : 
	               16 Bit    Registers := 3     
Module PE_cluster__hierPathDup__3 
Detailed RTL Component Info : 
+---Adders : 
	   3 Input     16 Bit       Adders := 3     
+---Registers : 
	               16 Bit    Registers := 3     
Module PE_cluster 
Detailed RTL Component Info : 
+---Adders : 
	   3 Input     16 Bit       Adders := 3     
+---Registers : 
	               16 Bit    Registers := 3     
Module PE_cluster__hierPathDup__2 
Detailed RTL Component Info : 
+---Adders : 
	   3 Input     16 Bit       Adders := 3     
+---Registers : 
	               16 Bit    Registers := 3     
---------------------------------------------------------------------------------
Finished RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 1728 (col length:144)
BRAMs: 624 (col length: RAMB18 144 RAMB36 72)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
Warning: Parallel synthesis criteria is not met 
INFO: [Synth 8-4471] merging register 'iter_reg[2:0]' into 'iter_reg[2:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:115]
INFO: [Synth 8-4471] merging register 'filt_count_reg[7:0]' into 'filt_count_reg[7:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:104]
INFO: [Synth 8-4471] merging register 'iter_reg[2:0]' into 'iter_reg[2:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:115]
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "filt_count" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "r_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "w_addr" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "sum_in_mux_sel" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "w_addr" won't be mapped to RAM because it is too sparse
DSP Report: Generating DSP mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register filt_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register act_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register mac_0/out_reg is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out0 is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out1 is absorbed into DSP mac_0/out_reg.
INFO: [Synth 8-4471] merging register 'iter_reg[2:0]' into 'iter_reg[2:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:115]
INFO: [Synth 8-4471] merging register 'filt_count_reg[7:0]' into 'filt_count_reg[7:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:104]
INFO: [Synth 8-4471] merging register 'iter_reg[2:0]' into 'iter_reg[2:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:115]
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "filt_count" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "state" won't be mapped to RAM because it is too sparse
INFO: [Common 17-14] Message 'Synth 8-5546' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
DSP Report: Generating DSP mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register filt_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register act_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register mac_0/out_reg is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out0 is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out1 is absorbed into DSP mac_0/out_reg.
INFO: [Synth 8-4471] merging register 'iter_reg[2:0]' into 'iter_reg[2:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:115]
INFO: [Synth 8-4471] merging register 'filt_count_reg[7:0]' into 'filt_count_reg[7:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:104]
INFO: [Synth 8-4471] merging register 'iter_reg[2:0]' into 'iter_reg[2:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:115]
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
DSP Report: Generating DSP mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register filt_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register act_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register mac_0/out_reg is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out0 is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out1 is absorbed into DSP mac_0/out_reg.
INFO: [Synth 8-4471] merging register 'iter_reg[2:0]' into 'iter_reg[2:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:115]
INFO: [Synth 8-4471] merging register 'filt_count_reg[7:0]' into 'filt_count_reg[7:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:104]
INFO: [Synth 8-4471] merging register 'iter_reg[2:0]' into 'iter_reg[2:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:115]
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
DSP Report: Generating DSP mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register filt_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register act_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register mac_0/out_reg is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out0 is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out1 is absorbed into DSP mac_0/out_reg.
INFO: [Synth 8-4471] merging register 'iter_reg[2:0]' into 'iter_reg[2:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:115]
INFO: [Synth 8-4471] merging register 'filt_count_reg[7:0]' into 'filt_count_reg[7:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:104]
INFO: [Synth 8-4471] merging register 'iter_reg[2:0]' into 'iter_reg[2:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:115]
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
DSP Report: Generating DSP mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register filt_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register act_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register mac_0/out_reg is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out0 is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out1 is absorbed into DSP mac_0/out_reg.
INFO: [Synth 8-4471] merging register 'iter_reg[2:0]' into 'iter_reg[2:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:115]
INFO: [Synth 8-4471] merging register 'filt_count_reg[7:0]' into 'filt_count_reg[7:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:104]
INFO: [Synth 8-4471] merging register 'iter_reg[2:0]' into 'iter_reg[2:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:115]
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
DSP Report: Generating DSP mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register filt_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register act_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register mac_0/out_reg is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out0 is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out1 is absorbed into DSP mac_0/out_reg.
INFO: [Synth 8-4471] merging register 'iter_reg[2:0]' into 'iter_reg[2:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:115]
INFO: [Synth 8-4471] merging register 'filt_count_reg[7:0]' into 'filt_count_reg[7:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:104]
INFO: [Synth 8-4471] merging register 'iter_reg[2:0]' into 'iter_reg[2:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:115]
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
DSP Report: Generating DSP mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register filt_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register act_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register mac_0/out_reg is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out0 is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out1 is absorbed into DSP mac_0/out_reg.
INFO: [Synth 8-4471] merging register 'iter_reg[2:0]' into 'iter_reg[2:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:115]
INFO: [Synth 8-4471] merging register 'filt_count_reg[7:0]' into 'filt_count_reg[7:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:104]
INFO: [Synth 8-4471] merging register 'iter_reg[2:0]' into 'iter_reg[2:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:115]
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
DSP Report: Generating DSP mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register filt_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register act_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register mac_0/out_reg is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out0 is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out1 is absorbed into DSP mac_0/out_reg.
INFO: [Synth 8-4471] merging register 'iter_reg[2:0]' into 'iter_reg[2:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:115]
INFO: [Synth 8-4471] merging register 'filt_count_reg[7:0]' into 'filt_count_reg[7:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:104]
INFO: [Synth 8-4471] merging register 'iter_reg[2:0]' into 'iter_reg[2:0]' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/PE.sv:115]
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
DSP Report: Generating DSP mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register filt_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register act_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register mac_0/out_reg is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out0 is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out1 is absorbed into DSP mac_0/out_reg.
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
DSP Report: Generating DSP mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register filt_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register act_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register mac_0/out_reg is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out0 is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out1 is absorbed into DSP mac_0/out_reg.
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
DSP Report: Generating DSP mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register filt_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register act_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register mac_0/out_reg is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out0 is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out1 is absorbed into DSP mac_0/out_reg.
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
DSP Report: Generating DSP mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register filt_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register act_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register mac_0/out_reg is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out0 is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out1 is absorbed into DSP mac_0/out_reg.
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
DSP Report: Generating DSP mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register filt_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register act_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register mac_0/out_reg is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out0 is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out1 is absorbed into DSP mac_0/out_reg.
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
DSP Report: Generating DSP mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register filt_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register act_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register mac_0/out_reg is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out0 is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out1 is absorbed into DSP mac_0/out_reg.
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
DSP Report: Generating DSP mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register filt_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register act_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register mac_0/out_reg is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out0 is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out1 is absorbed into DSP mac_0/out_reg.
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
DSP Report: Generating DSP mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register filt_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register act_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register mac_0/out_reg is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out0 is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out1 is absorbed into DSP mac_0/out_reg.
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
DSP Report: Generating DSP mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register filt_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register act_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register mac_0/out_reg is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out0 is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out1 is absorbed into DSP mac_0/out_reg.
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
DSP Report: Generating DSP mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register filt_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register act_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register mac_0/out_reg is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out0 is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out1 is absorbed into DSP mac_0/out_reg.
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
DSP Report: Generating DSP mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register filt_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register act_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register mac_0/out_reg is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out0 is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out1 is absorbed into DSP mac_0/out_reg.
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
DSP Report: Generating DSP mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register filt_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register act_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register mac_0/out_reg is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out0 is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out1 is absorbed into DSP mac_0/out_reg.
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
DSP Report: Generating DSP mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register filt_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register act_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register mac_0/out_reg is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out0 is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out1 is absorbed into DSP mac_0/out_reg.
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
DSP Report: Generating DSP mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register filt_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register act_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register mac_0/out_reg is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out0 is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out1 is absorbed into DSP mac_0/out_reg.
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
DSP Report: Generating DSP mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register filt_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register act_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register mac_0/out_reg is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out0 is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out1 is absorbed into DSP mac_0/out_reg.
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
DSP Report: Generating DSP mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register filt_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register act_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register mac_0/out_reg is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out0 is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out1 is absorbed into DSP mac_0/out_reg.
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
DSP Report: Generating DSP mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register filt_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register act_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register mac_0/out_reg is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out0 is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out1 is absorbed into DSP mac_0/out_reg.
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
DSP Report: Generating DSP mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register filt_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register act_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register mac_0/out_reg is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out0 is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out1 is absorbed into DSP mac_0/out_reg.
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
DSP Report: Generating DSP mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register filt_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register act_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register mac_0/out_reg is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out0 is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out1 is absorbed into DSP mac_0/out_reg.
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
DSP Report: Generating DSP mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register filt_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register act_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register mac_0/out_reg is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out0 is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out1 is absorbed into DSP mac_0/out_reg.
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
DSP Report: Generating DSP mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register filt_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register act_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register mac_0/out_reg is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out0 is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out1 is absorbed into DSP mac_0/out_reg.
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
DSP Report: Generating DSP mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register filt_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register act_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register mac_0/out_reg is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out0 is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out1 is absorbed into DSP mac_0/out_reg.
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
DSP Report: Generating DSP mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register filt_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register act_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register mac_0/out_reg is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out0 is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out1 is absorbed into DSP mac_0/out_reg.
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
DSP Report: Generating DSP mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register filt_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register act_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register mac_0/out_reg is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out0 is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out1 is absorbed into DSP mac_0/out_reg.
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
DSP Report: Generating DSP mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register filt_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register act_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register mac_0/out_reg is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out0 is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out1 is absorbed into DSP mac_0/out_reg.
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
DSP Report: Generating DSP mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register filt_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register act_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register mac_0/out_reg is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out0 is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out1 is absorbed into DSP mac_0/out_reg.
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
DSP Report: Generating DSP mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register filt_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register act_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register mac_0/out_reg is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out0 is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out1 is absorbed into DSP mac_0/out_reg.
INFO: [Synth 8-5544] ROM "filt_count" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "iter" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
DSP Report: Generating DSP mac_0/out_reg, operation Mode is: (P or (C:0x0))+A2*B2.
DSP Report: register filt_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register act_in_reg_reg is absorbed into DSP mac_0/out_reg.
DSP Report: register mac_0/out_reg is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out0 is absorbed into DSP mac_0/out_reg.
DSP Report: operator mac_0/out1 is absorbed into DSP mac_0/out_reg.
WARNING: [Synth 8-3331] design HMNoC_cluster_east has unconnected port east_data_o_psum[15]
WARNING: [Synth 8-3331] design HMNoC_cluster_east has unconnected port east_data_o_psum[14]
WARNING: [Synth 8-3331] design HMNoC_cluster_east has unconnected port east_data_o_psum[13]
WARNING: [Synth 8-3331] design HMNoC_cluster_east has unconnected port east_data_o_psum[12]
WARNING: [Synth 8-3331] design HMNoC_cluster_east has unconnected port east_data_o_psum[11]
WARNING: [Synth 8-3331] design HMNoC_cluster_east has unconnected port east_data_o_psum[10]
WARNING: [Synth 8-3331] design HMNoC_cluster_east has unconnected port east_data_o_psum[9]
WARNING: [Synth 8-3331] design HMNoC_cluster_east has unconnected port east_data_o_psum[8]
WARNING: [Synth 8-3331] design HMNoC_cluster_east has unconnected port east_data_o_psum[7]
WARNING: [Synth 8-3331] design HMNoC_cluster_east has unconnected port east_data_o_psum[6]
WARNING: [Synth 8-3331] design HMNoC_cluster_east has unconnected port east_data_o_psum[5]
WARNING: [Synth 8-3331] design HMNoC_cluster_east has unconnected port east_data_o_psum[4]
WARNING: [Synth 8-3331] design HMNoC_cluster_east has unconnected port east_data_o_psum[3]
WARNING: [Synth 8-3331] design HMNoC_cluster_east has unconnected port east_data_o_psum[2]
WARNING: [Synth 8-3331] design HMNoC_cluster_east has unconnected port east_data_o_psum[1]
WARNING: [Synth 8-3331] design HMNoC_cluster_east has unconnected port east_data_o_psum[0]
WARNING: [Synth 8-3331] design HMNoC_cluster_east has unconnected port east_enable_o_psum
WARNING: [Synth 8-3331] design HMNoC_cluster_east__hierPathDup__1 has unconnected port east_data_o_psum[15]
WARNING: [Synth 8-3331] design HMNoC_cluster_east__hierPathDup__1 has unconnected port east_data_o_psum[14]
WARNING: [Synth 8-3331] design HMNoC_cluster_east__hierPathDup__1 has unconnected port east_data_o_psum[13]
WARNING: [Synth 8-3331] design HMNoC_cluster_east__hierPathDup__1 has unconnected port east_data_o_psum[12]
WARNING: [Synth 8-3331] design HMNoC_cluster_east__hierPathDup__1 has unconnected port east_data_o_psum[11]
WARNING: [Synth 8-3331] design HMNoC_cluster_east__hierPathDup__1 has unconnected port east_data_o_psum[10]
WARNING: [Synth 8-3331] design HMNoC_cluster_east__hierPathDup__1 has unconnected port east_data_o_psum[9]
WARNING: [Synth 8-3331] design HMNoC_cluster_east__hierPathDup__1 has unconnected port east_data_o_psum[8]
WARNING: [Synth 8-3331] design HMNoC_cluster_east__hierPathDup__1 has unconnected port east_data_o_psum[7]
WARNING: [Synth 8-3331] design HMNoC_cluster_east__hierPathDup__1 has unconnected port east_data_o_psum[6]
WARNING: [Synth 8-3331] design HMNoC_cluster_east__hierPathDup__1 has unconnected port east_data_o_psum[5]
WARNING: [Synth 8-3331] design HMNoC_cluster_east__hierPathDup__1 has unconnected port east_data_o_psum[4]
WARNING: [Synth 8-3331] design HMNoC_cluster_east__hierPathDup__1 has unconnected port east_data_o_psum[3]
WARNING: [Synth 8-3331] design HMNoC_cluster_east__hierPathDup__1 has unconnected port east_data_o_psum[2]
WARNING: [Synth 8-3331] design HMNoC_cluster_east__hierPathDup__1 has unconnected port east_data_o_psum[1]
WARNING: [Synth 8-3331] design HMNoC_cluster_east__hierPathDup__1 has unconnected port east_data_o_psum[0]
WARNING: [Synth 8-3331] design HMNoC_cluster_east__hierPathDup__1 has unconnected port east_enable_o_psum
WARNING: [Synth 8-3331] design HMNoC_cluster_west__hierPathDup__1 has unconnected port west_data_o_psum[15]
WARNING: [Synth 8-3331] design HMNoC_cluster_west__hierPathDup__1 has unconnected port west_data_o_psum[14]
WARNING: [Synth 8-3331] design HMNoC_cluster_west__hierPathDup__1 has unconnected port west_data_o_psum[13]
WARNING: [Synth 8-3331] design HMNoC_cluster_west__hierPathDup__1 has unconnected port west_data_o_psum[12]
WARNING: [Synth 8-3331] design HMNoC_cluster_west__hierPathDup__1 has unconnected port west_data_o_psum[11]
WARNING: [Synth 8-3331] design HMNoC_cluster_west__hierPathDup__1 has unconnected port west_data_o_psum[10]
WARNING: [Synth 8-3331] design HMNoC_cluster_west__hierPathDup__1 has unconnected port west_data_o_psum[9]
WARNING: [Synth 8-3331] design HMNoC_cluster_west__hierPathDup__1 has unconnected port west_data_o_psum[8]
WARNING: [Synth 8-3331] design HMNoC_cluster_west__hierPathDup__1 has unconnected port west_data_o_psum[7]
WARNING: [Synth 8-3331] design HMNoC_cluster_west__hierPathDup__1 has unconnected port west_data_o_psum[6]
WARNING: [Synth 8-3331] design HMNoC_cluster_west__hierPathDup__1 has unconnected port west_data_o_psum[5]
WARNING: [Synth 8-3331] design HMNoC_cluster_west__hierPathDup__1 has unconnected port west_data_o_psum[4]
WARNING: [Synth 8-3331] design HMNoC_cluster_west__hierPathDup__1 has unconnected port west_data_o_psum[3]
WARNING: [Synth 8-3331] design HMNoC_cluster_west__hierPathDup__1 has unconnected port west_data_o_psum[2]
WARNING: [Synth 8-3331] design HMNoC_cluster_west__hierPathDup__1 has unconnected port west_data_o_psum[1]
WARNING: [Synth 8-3331] design HMNoC_cluster_west__hierPathDup__1 has unconnected port west_data_o_psum[0]
WARNING: [Synth 8-3331] design HMNoC_cluster_west__hierPathDup__1 has unconnected port west_enable_o_psum
WARNING: [Synth 8-3331] design HMNoC_cluster_west has unconnected port west_data_o_psum[15]
WARNING: [Synth 8-3331] design HMNoC_cluster_west has unconnected port west_data_o_psum[14]
WARNING: [Synth 8-3331] design HMNoC_cluster_west has unconnected port west_data_o_psum[13]
WARNING: [Synth 8-3331] design HMNoC_cluster_west has unconnected port west_data_o_psum[12]
WARNING: [Synth 8-3331] design HMNoC_cluster_west has unconnected port west_data_o_psum[11]
WARNING: [Synth 8-3331] design HMNoC_cluster_west has unconnected port west_data_o_psum[10]
WARNING: [Synth 8-3331] design HMNoC_cluster_west has unconnected port west_data_o_psum[9]
WARNING: [Synth 8-3331] design HMNoC_cluster_west has unconnected port west_data_o_psum[8]
WARNING: [Synth 8-3331] design HMNoC_cluster_west has unconnected port west_data_o_psum[7]
WARNING: [Synth 8-3331] design HMNoC_cluster_west has unconnected port west_data_o_psum[6]
WARNING: [Synth 8-3331] design HMNoC_cluster_west has unconnected port west_data_o_psum[5]
WARNING: [Synth 8-3331] design HMNoC_cluster_west has unconnected port west_data_o_psum[4]
WARNING: [Synth 8-3331] design HMNoC_cluster_west has unconnected port west_data_o_psum[3]
WARNING: [Synth 8-3331] design HMNoC_cluster_west has unconnected port west_data_o_psum[2]
WARNING: [Synth 8-3331] design HMNoC_cluster_west has unconnected port west_data_o_psum[1]
INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-3886] merging instance 'HMNoC_cluster_east_1/GLB_cluster_0/glb_iact_gen[0].glb_iact_inst/data_reg[0]' (FDR) to 'HMNoC_cluster_east_1/GLB_cluster_0/glb_iact_gen[0].glb_iact_inst/data_reg[13]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (HMNoC_cluster_east_1/\GLB_cluster_0/glb_iact_gen[0].glb_iact_inst/data_reg[1] )
INFO: [Synth 8-3886] merging instance 'HMNoC_cluster_east_1/GLB_cluster_0/glb_iact_gen[0].glb_iact_inst/data_reg[2]' (FDR) to 'HMNoC_cluster_east_1/GLB_cluster_0/glb_iact_gen[0].glb_iact_inst/data_reg[13]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (HMNoC_cluster_east_1/\GLB_cluster_0/glb_iact_gen[0].glb_iact_inst/data_reg[3] )
INFO: [Synth 8-3886] merging instance 'HMNoC_cluster_east_1/GLB_cluster_0/glb_iact_gen[0].glb_iact_inst/data_reg[4]' (FDR) to 'HMNoC_cluster_east_1/GLB_cluster_0/glb_iact_gen[0].glb_iact_inst/data_reg[13]'
INFO: [Synth 8-3886] merging instance 'HMNoC_cluster_east_1/GLB_cluster_0/glb_iact_gen[0].glb_iact_inst/data_reg[5]' (FDR) to 'HMNoC_cluster_east_1/GLB_cluster_0/glb_iact_gen[0].glb_iact_inst/data_reg[13]'
INFO: [Synth 8-3886] merging instance 'HMNoC_cluster_east_1/GLB_cluster_0/glb_iact_gen[0].glb_iact_inst/data_reg[6]' (FDR) to 'HMNoC_cluster_east_1/GLB_cluster_0/glb_iact_gen[0].glb_iact_inst/data_reg[13]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (HMNoC_cluster_east_1/\GLB_cluster_0/glb_iact_gen[0].glb_iact_inst/data_reg[7] )
INFO: [Synth 8-3886] merging instance 'HMNoC_cluster_east_1/GLB_cluster_0/glb_iact_gen[0].glb_iact_inst/data_reg[8]' (FDR) to 'HMNoC_cluster_east_1/GLB_cluster_0/glb_iact_gen[0].glb_iact_inst/data_reg[13]'
INFO: [Synth 8-3886] merging instance 'HMNoC_cluster_east_1/GLB_cluster_0/glb_iact_gen[0].glb_iact_inst/data_reg[9]' (FDR) to 'HMNoC_cluster_east_1/GLB_cluster_0/glb_iact_gen[0].glb_iact_inst/data_reg[13]'
INFO: [Synth 8-3886] merging instance 'HMNoC_cluster_east_1/GLB_cluster_0/glb_iact_gen[0].glb_iact_inst/data_reg[10]' (FDR) to 'HMNoC_cluster_east_1/GLB_cluster_0/glb_iact_gen[0].glb_iact_inst/data_reg[13]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (HMNoC_cluster_east_1/\GLB_cluster_0/glb_iact_gen[0].glb_iact_inst/data_reg[11] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (HMNoC_cluster_east_1/\GLB_cluster_0/glb_iact_gen[0].glb_iact_inst/data_reg[12] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (HMNoC_cluster_east_1/\GLB_cluster_0/glb_iact_gen[0].glb_iact_inst/data_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (HMNoC_cluster_east_1/\GLB_cluster_0/glb_iact_gen[0].glb_iact_inst/data_reg[15] )
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 1st driver pin 'HMNoC_cluster_west_1/GLB_cluster_0/glb_iact_gen[0].glb_iact_inst/data_reg[15]/Q' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:42]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 2nd driver pin 'GND' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:42]
CRITICAL WARNING: [Synth 8-6858] multi-driven net Q is connected to at least one constant driver which has been preserved, other driver is ignored [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:42]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 1st driver pin 'HMNoC_cluster_west_1/GLB_cluster_0/glb_iact_gen[0].glb_iact_inst/data_reg[14]/Q' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:42]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 2nd driver pin 'GND' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:42]
CRITICAL WARNING: [Synth 8-6858] multi-driven net Q is connected to at least one constant driver which has been preserved, other driver is ignored [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:42]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 1st driver pin 'HMNoC_cluster_west_1/GLB_cluster_0/glb_iact_gen[0].glb_iact_inst/data_reg[12]/Q' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:42]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 2nd driver pin 'GND' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:42]
CRITICAL WARNING: [Synth 8-6858] multi-driven net Q is connected to at least one constant driver which has been preserved, other driver is ignored [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:42]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 1st driver pin 'HMNoC_cluster_west_1/GLB_cluster_0/glb_iact_gen[0].glb_iact_inst/data_reg[11]/Q' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:42]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 2nd driver pin 'GND' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:42]
CRITICAL WARNING: [Synth 8-6858] multi-driven net Q is connected to at least one constant driver which has been preserved, other driver is ignored [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:42]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 1st driver pin 'HMNoC_cluster_west_1/GLB_cluster_0/glb_iact_gen[0].glb_iact_inst/data_reg[7]/Q' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:42]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 2nd driver pin 'GND' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:42]
CRITICAL WARNING: [Synth 8-6858] multi-driven net Q is connected to at least one constant driver which has been preserved, other driver is ignored [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:42]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 1st driver pin 'HMNoC_cluster_west_1/GLB_cluster_0/glb_iact_gen[0].glb_iact_inst/data_reg[3]/Q' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:42]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 2nd driver pin 'GND' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:42]
CRITICAL WARNING: [Synth 8-6858] multi-driven net Q is connected to at least one constant driver which has been preserved, other driver is ignored [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:42]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 1st driver pin 'HMNoC_cluster_west_1/GLB_cluster_0/glb_iact_gen[0].glb_iact_inst/data_reg[1]/Q' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:42]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 2nd driver pin 'GND' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:42]
CRITICAL WARNING: [Synth 8-6858] multi-driven net Q is connected to at least one constant driver which has been preserved, other driver is ignored [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:42]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 1st driver pin 'HMNoC_cluster_west_1/GLB_cluster_0/glb_wght_gen[0].glb_weight_inst/data_reg[15]/Q' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_weight.sv:42]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 2nd driver pin 'GND' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_weight.sv:42]
CRITICAL WARNING: [Synth 8-6858] multi-driven net Q is connected to at least one constant driver which has been preserved, other driver is ignored [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_weight.sv:42]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 1st driver pin 'HMNoC_cluster_west_1/GLB_cluster_0/glb_wght_gen[0].glb_weight_inst/data_reg[14]/Q' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_weight.sv:42]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 2nd driver pin 'GND' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_weight.sv:42]
CRITICAL WARNING: [Synth 8-6858] multi-driven net Q is connected to at least one constant driver which has been preserved, other driver is ignored [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_weight.sv:42]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 1st driver pin 'HMNoC_cluster_west_1/GLB_cluster_0/glb_wght_gen[0].glb_weight_inst/data_reg[12]/Q' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_weight.sv:42]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 2nd driver pin 'GND' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_weight.sv:42]
CRITICAL WARNING: [Synth 8-6858] multi-driven net Q is connected to at least one constant driver which has been preserved, other driver is ignored [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_weight.sv:42]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 1st driver pin 'HMNoC_cluster_west_1/GLB_cluster_0/glb_wght_gen[0].glb_weight_inst/data_reg[11]/Q' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_weight.sv:42]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 2nd driver pin 'GND' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_weight.sv:42]
CRITICAL WARNING: [Synth 8-6858] multi-driven net Q is connected to at least one constant driver which has been preserved, other driver is ignored [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_weight.sv:42]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 1st driver pin 'HMNoC_cluster_west_1/GLB_cluster_0/glb_wght_gen[0].glb_weight_inst/data_reg[7]/Q' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_weight.sv:42]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 2nd driver pin 'GND' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_weight.sv:42]
CRITICAL WARNING: [Synth 8-6858] multi-driven net Q is connected to at least one constant driver which has been preserved, other driver is ignored [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_weight.sv:42]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 1st driver pin 'HMNoC_cluster_west_1/GLB_cluster_0/glb_wght_gen[0].glb_weight_inst/data_reg[3]/Q' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_weight.sv:42]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 2nd driver pin 'GND' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_weight.sv:42]
CRITICAL WARNING: [Synth 8-6858] multi-driven net Q is connected to at least one constant driver which has been preserved, other driver is ignored [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_weight.sv:42]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 1st driver pin 'HMNoC_cluster_west_1/GLB_cluster_0/glb_wght_gen[0].glb_weight_inst/data_reg[1]/Q' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_weight.sv:42]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 2nd driver pin 'GND' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_weight.sv:42]
CRITICAL WARNING: [Synth 8-6858] multi-driven net Q is connected to at least one constant driver which has been preserved, other driver is ignored [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_weight.sv:42]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 1st driver pin 'HMNoC_cluster_east_0/GLB_cluster_0/glb_iact_gen[0].glb_iact_inst/data_reg[15]/Q' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:42]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 2nd driver pin 'GND' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:42]
CRITICAL WARNING: [Synth 8-6858] multi-driven net Q is connected to at least one constant driver which has been preserved, other driver is ignored [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:42]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 1st driver pin 'HMNoC_cluster_east_0/GLB_cluster_0/glb_iact_gen[0].glb_iact_inst/data_reg[14]/Q' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:42]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 2nd driver pin 'GND' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:42]
CRITICAL WARNING: [Synth 8-6858] multi-driven net Q is connected to at least one constant driver which has been preserved, other driver is ignored [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:42]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 1st driver pin 'HMNoC_cluster_east_0/GLB_cluster_0/glb_iact_gen[0].glb_iact_inst/data_reg[12]/Q' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:42]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 2nd driver pin 'GND' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:42]
CRITICAL WARNING: [Synth 8-6858] multi-driven net Q is connected to at least one constant driver which has been preserved, other driver is ignored [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:42]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 1st driver pin 'HMNoC_cluster_east_0/GLB_cluster_0/glb_iact_gen[0].glb_iact_inst/data_reg[11]/Q' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:42]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 2nd driver pin 'GND' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:42]
CRITICAL WARNING: [Synth 8-6858] multi-driven net Q is connected to at least one constant driver which has been preserved, other driver is ignored [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:42]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 1st driver pin 'HMNoC_cluster_east_0/GLB_cluster_0/glb_iact_gen[0].glb_iact_inst/data_reg[7]/Q' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:42]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 2nd driver pin 'GND' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:42]
CRITICAL WARNING: [Synth 8-6858] multi-driven net Q is connected to at least one constant driver which has been preserved, other driver is ignored [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:42]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 1st driver pin 'HMNoC_cluster_east_0/GLB_cluster_0/glb_iact_gen[0].glb_iact_inst/data_reg[3]/Q' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:42]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 2nd driver pin 'GND' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:42]
CRITICAL WARNING: [Synth 8-6858] multi-driven net Q is connected to at least one constant driver which has been preserved, other driver is ignored [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:42]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 1st driver pin 'HMNoC_cluster_east_0/GLB_cluster_0/glb_iact_gen[0].glb_iact_inst/data_reg[1]/Q' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:42]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin Q with 2nd driver pin 'GND' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:42]
CRITICAL WARNING: [Synth 8-6858] multi-driven net Q is connected to at least one constant driver which has been preserved, other driver is ignored [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/glb_iact.sv:42]
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:35 ; elapsed = 00:00:40 . Memory (MB): peak = 1546.910 ; gain = 1285.727
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------

Distributed RAM: Preliminary Mapping  Report (see note below)
+----------------------------------+-------------------------------------------------------+-----------+----------------------+-------------------------------+
|Module Name                       | RTL Object                                            | Inference | Size (Depth x Width) | Primitives                    | 
+----------------------------------+-------------------------------------------------------+-----------+----------------------+-------------------------------+
|HMNoC_cluster_west_0/pe_cluster_0 | gen_X[0].gen_Y[0].pe/spad_pe0/mem_reg                 | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster_west_0/pe_cluster_0 | gen_X[0].gen_Y[1].pe/spad_pe0/mem_reg                 | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster_west_0/pe_cluster_0 | gen_X[0].gen_Y[2].pe/spad_pe0/mem_reg                 | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster_west_0/pe_cluster_0 | gen_X[1].gen_Y[0].pe/spad_pe0/mem_reg                 | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster_west_0/pe_cluster_0 | gen_X[1].gen_Y[1].pe/spad_pe0/mem_reg                 | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster_west_0/pe_cluster_0 | gen_X[1].gen_Y[2].pe/spad_pe0/mem_reg                 | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster_west_0/pe_cluster_0 | gen_X[2].gen_Y[0].pe/spad_pe0/mem_reg                 | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster_west_0/pe_cluster_0 | gen_X[2].gen_Y[1].pe/spad_pe0/mem_reg                 | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster_west_0/pe_cluster_0 | gen_X[2].gen_Y[2].pe/spad_pe0/mem_reg                 | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster_west_0              | GLB_cluster_0/glb_iact_gen[0].glb_iact_inst/mem_reg   | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster_west_0              | GLB_cluster_0/glb_psum_gen[0].glb_psum_inst/mem_reg   | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster_west_0              | GLB_cluster_0/glb_wght_gen[0].glb_weight_inst/mem_reg | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster_east_0              | GLB_cluster_0/glb_wght_gen[0].glb_weight_inst/mem_reg | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster_east_1              | GLB_cluster_0/glb_wght_gen[0].glb_weight_inst/mem_reg | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
+----------------------------------+-------------------------------------------------------+-----------+----------------------+-------------------------------+

Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.

DSP: Preliminary Mapping  Report (see note below)
+------------+----------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|Module Name | DSP Mapping          | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | 
+------------+----------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|PE          | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE          | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE          | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE          | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE          | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE          | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE          | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE          | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE          | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE          | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE          | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE          | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE          | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE          | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE          | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE          | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE          | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE          | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE          | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE          | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE          | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE          | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE          | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE          | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE          | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE          | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE          | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE          | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE          | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE          | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE          | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE          | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE          | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE          | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE          | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
|PE          | (P or (C:0x0))+A2*B2 | 16     | 16     | 16     | -      | 16     | 1    | 1    | 0    | -    | -     | 0    | 1    | 
+------------+----------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+

Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:44 ; elapsed = 00:00:52 . Memory (MB): peak = 1987.973 ; gain = 1726.789
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
      : HMNoC_cluster_west_0/\router_cluster_0/router_psum/data_out_inferred /data3[15]
      : HMNoC_cluster_west_0/east_data_i_psum_inferred__0/out[15]
      : HMNoC_cluster_west_0/east_data_i_psum_inferred__0/in0[15]
      : HMNoC_cluster_west_0/east_data_i_psum_inferred/out[15]
      : HMNoC_cluster_west_0/east_data_i_psum_inferred/in0[15]
      : HMNoC_cluster_west_0/east_data_i_psum0[15]
      : east_data_i_psum_inferred__0/out[15]
      : east_data_i_psum_inferred__0/in0[15]
      : east_data_i_psum_inferred/out[15]
      : east_data_i_psum_inferred/in0[15]
      : HMNoC_cluster_east_0/west_data_o_psum[15]
      : HMNoC_cluster_east_0/west_data_o_psum_inferred__0/out[15]
      : HMNoC_cluster_east_0/west_data_o_psum_inferred__0/in0[15]
      : HMNoC_cluster_east_0/west_data_o_psum_inferred/out[15]
      : HMNoC_cluster_east_0/west_data_o_psum_inferred/in0[15]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_psum_inferred__0 /out[15]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_psum_inferred__0 /in0[15]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_psum_inferred /out[15]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_psum_inferred /in0[15]
      : HMNoC_cluster_east_0/\router_cluster_0/router_psum/data_out_inferred /out0[15]
      : HMNoC_cluster_east_0/\router_cluster_0/router_psum/data_out_inferred /data2[15]
      : HMNoC_cluster_east_0/west_data_i_psum_inferred__0/out[15]
      : HMNoC_cluster_east_0/west_data_i_psum_inferred__0/in0[15]
      : HMNoC_cluster_east_0/west_data_i_psum_inferred/out[15]
      : HMNoC_cluster_east_0/west_data_i_psum_inferred/in0[15]
      : HMNoC_cluster_east_0/west_data_i_psum0[15]
      : west_data_i_psum_inferred__0/out[15]
      : west_data_i_psum_inferred__0/in0[15]
      : west_data_i_psum_inferred/out[15]
      : west_data_i_psum_inferred/in0[15]
      : HMNoC_cluster_west_0/east_data_o_psum[15]
      : HMNoC_cluster_west_0/east_data_o_psum_inferred__0/out[15]
      : HMNoC_cluster_west_0/east_data_o_psum_inferred__0/in0[15]
      : HMNoC_cluster_west_0/east_data_o_psum_inferred/out[15]
      : HMNoC_cluster_west_0/east_data_o_psum_inferred/in0[15]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_psum_inferred__0 /out[15]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_psum_inferred__0 /in0[15]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_psum_inferred /out[15]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_psum_inferred /in0[15]
      : HMNoC_cluster_west_0/\router_cluster_0/router_psum/data_out_inferred /out0[15]
      : HMNoC_cluster_east_0/\router_cluster_0/router_psum/data_out_inferred /data1[15]
      : HMNoC_cluster_east_0/south_data_i_psum_inferred__0/out[15]
      : HMNoC_cluster_east_0/south_data_i_psum_inferred__0/in0[15]
      : HMNoC_cluster_east_0/south_data_i_psum_inferred/out[15]
      : HMNoC_cluster_east_0/south_data_i_psum_inferred/in0[15]
      : HMNoC_cluster_east_0/south_data_i_psum0[15]
      : south_data_i_psum_inferred__2/out[15]
      : south_data_i_psum_inferred__2/in0[15]
      : south_data_i_psum_inferred__1/out[15]
      : south_data_i_psum_inferred__1/in0[15]
      : HMNoC_cluster_east_1/north_data_o_psum[15]
      : HMNoC_cluster_east_1/north_data_o_psum_inferred__0/out[15]
      : HMNoC_cluster_east_1/north_data_o_psum_inferred__0/in0[15]
      : HMNoC_cluster_east_1/north_data_o_psum_inferred/out[15]
      : HMNoC_cluster_east_1/north_data_o_psum_inferred/in0[15]
      : HMNoC_cluster_east_1/north_data_o_psum0[15]
      : north_data_o_psum_inferred__2/out[15]
      : north_data_o_psum_inferred__2/in0[15]
      : north_data_o_psum_inferred__1/out[15]
      : north_data_o_psum_inferred__1/in0[15]
      : HMNoC_cluster_east_0/south_data_o_psum[15]
      : HMNoC_cluster_east_0/south_data_o_psum_inferred__0/out[15]
      : HMNoC_cluster_east_0/south_data_o_psum_inferred__0/in0[15]
      : HMNoC_cluster_east_0/south_data_o_psum_inferred/out[15]
      : HMNoC_cluster_east_0/south_data_o_psum_inferred/in0[15]
      : HMNoC_cluster_east_0/\router_cluster_0/router_psum/data_out_inferred /out0[15]
      : HMNoC_cluster_west_0/\router_cluster_0/router_psum/data_out_inferred /data3[14]
      : HMNoC_cluster_west_0/east_data_i_psum_inferred__0/out[14]
      : HMNoC_cluster_west_0/east_data_i_psum_inferred__0/in0[14]
      : HMNoC_cluster_west_0/east_data_i_psum_inferred/out[14]
      : HMNoC_cluster_west_0/east_data_i_psum_inferred/in0[14]
      : HMNoC_cluster_west_0/east_data_i_psum0[14]
      : east_data_i_psum_inferred__0/out[14]
      : east_data_i_psum_inferred__0/in0[14]
      : east_data_i_psum_inferred/out[14]
      : east_data_i_psum_inferred/in0[14]
      : HMNoC_cluster_east_0/west_data_o_psum[14]
      : HMNoC_cluster_east_0/west_data_o_psum_inferred__0/out[14]
      : HMNoC_cluster_east_0/west_data_o_psum_inferred__0/in0[14]
      : HMNoC_cluster_east_0/west_data_o_psum_inferred/out[14]
      : HMNoC_cluster_east_0/west_data_o_psum_inferred/in0[14]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_psum_inferred__0 /out[14]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_psum_inferred__0 /in0[14]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_psum_inferred /out[14]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_psum_inferred /in0[14]
      : HMNoC_cluster_east_0/\router_cluster_0/router_psum/data_out_inferred /out0[14]
      : HMNoC_cluster_east_0/\router_cluster_0/router_psum/data_out_inferred /data2[14]
      : HMNoC_cluster_east_0/west_data_i_psum_inferred__0/out[14]
      : HMNoC_cluster_east_0/west_data_i_psum_inferred__0/in0[14]
      : HMNoC_cluster_east_0/west_data_i_psum_inferred/out[14]
      : HMNoC_cluster_east_0/west_data_i_psum_inferred/in0[14]
      : HMNoC_cluster_east_0/west_data_i_psum0[14]
      : west_data_i_psum_inferred__0/out[14]
      : west_data_i_psum_inferred__0/in0[14]
      : west_data_i_psum_inferred/out[14]
      : west_data_i_psum_inferred/in0[14]
      : HMNoC_cluster_west_0/east_data_o_psum[14]
      : HMNoC_cluster_west_0/east_data_o_psum_inferred__0/out[14]
      : HMNoC_cluster_west_0/east_data_o_psum_inferred__0/in0[14]
      : HMNoC_cluster_west_0/east_data_o_psum_inferred/out[14]
      : HMNoC_cluster_west_0/east_data_o_psum_inferred/in0[14]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_psum_inferred__0 /out[14]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_psum_inferred__0 /in0[14]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_psum_inferred /out[14]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_psum_inferred /in0[14]
      : HMNoC_cluster_west_0/\router_cluster_0/router_psum/data_out_inferred /out0[14]
      : HMNoC_cluster_east_0/\router_cluster_0/router_psum/data_out_inferred /data1[14]
      : HMNoC_cluster_east_0/south_data_i_psum_inferred__0/out[14]
      : HMNoC_cluster_east_0/south_data_i_psum_inferred__0/in0[14]
      : HMNoC_cluster_east_0/south_data_i_psum_inferred/out[14]
      : HMNoC_cluster_east_0/south_data_i_psum_inferred/in0[14]
      : HMNoC_cluster_east_0/south_data_i_psum0[14]
      : south_data_i_psum_inferred__2/out[14]
      : south_data_i_psum_inferred__2/in0[14]
      : south_data_i_psum_inferred__1/out[14]
      : south_data_i_psum_inferred__1/in0[14]
      : HMNoC_cluster_east_1/north_data_o_psum[14]
      : HMNoC_cluster_east_1/north_data_o_psum_inferred__0/out[14]
      : HMNoC_cluster_east_1/north_data_o_psum_inferred__0/in0[14]
      : HMNoC_cluster_east_1/north_data_o_psum_inferred/out[14]
      : HMNoC_cluster_east_1/north_data_o_psum_inferred/in0[14]
      : HMNoC_cluster_east_1/north_data_o_psum0[14]
      : north_data_o_psum_inferred__2/out[14]
      : north_data_o_psum_inferred__2/in0[14]
      : north_data_o_psum_inferred__1/out[14]
      : north_data_o_psum_inferred__1/in0[14]
      : HMNoC_cluster_east_0/south_data_o_psum[14]
      : HMNoC_cluster_east_0/south_data_o_psum_inferred__0/out[14]
      : HMNoC_cluster_east_0/south_data_o_psum_inferred__0/in0[14]
      : HMNoC_cluster_east_0/south_data_o_psum_inferred/out[14]
      : HMNoC_cluster_east_0/south_data_o_psum_inferred/in0[14]
      : HMNoC_cluster_east_0/\router_cluster_0/router_psum/data_out_inferred /out0[14]
      : HMNoC_cluster_west_0/\router_cluster_0/router_wght/data_out_inferred /data1[15]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred__0/out[15]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred__0/in0[15]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred/out[15]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred/in0[15]
      : HMNoC_cluster_west_0/south_data_i_wght0[15]
      : south_data_i_wght_inferred__0/out[15]
      : south_data_i_wght_inferred__0/in0[15]
      : south_data_i_wght_inferred/out[15]
      : south_data_i_wght_inferred/in0[15]
      : HMNoC_cluster_west_1/north_data_o_wght[15]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred__0/out[15]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred__0/in0[15]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred/out[15]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred/in0[15]
      : HMNoC_cluster_west_1/\router_cluster_0/router_wght/data_out_inferred /out0[15]
      : HMNoC_cluster_west_1/\router_cluster_0/router_wght/data_out_inferred /data0[15]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred__0/out[15]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred__0/in0[15]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred/out[15]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred/in0[15]
      : HMNoC_cluster_west_1/north_data_i_wght0[15]
      : north_data_i_wght_inferred__0/out[15]
      : north_data_i_wght_inferred__0/in0[15]
      : north_data_i_wght_inferred/out[15]
      : north_data_i_wght_inferred/in0[15]
      : HMNoC_cluster_west_0/south_data_o_wght[15]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred__0/out[15]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred__0/in0[15]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred/out[15]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred/in0[15]
      : HMNoC_cluster_west_0/\router_cluster_0/router_wght/data_out_inferred /out0[15]
      : HMNoC_cluster_west_0/\router_cluster_0/router_iact/data_out_inferred /data3[15]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred__0 /out[15]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred__0 /in0[15]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred /out[15]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred /in0[15]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred__0/out[15]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred__0/in0[15]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred/out[15]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred/in0[15]
      : HMNoC_cluster_west_0/east_data_i_iact0[15]
      : east_data_i_iact_inferred__0/out[15]
      : east_data_i_iact_inferred__0/in0[15]
      : east_data_i_iact_inferred/out[15]
      : east_data_i_iact_inferred/in0[15]
      : HMNoC_cluster_east_0/west_data_o_iact[15]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred__0/out[15]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred__0/in0[15]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred/out[15]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred/in0[15]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred__0 /out[15]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred__0 /in0[15]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred /out[15]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred /in0[15]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /out0[15]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /data2[15]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred__0 /out[15]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred__0 /in0[15]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred /out[15]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred /in0[15]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred__0/out[15]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred__0/in0[15]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred/out[15]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred/in0[15]
      : HMNoC_cluster_east_0/west_data_i_iact0[15]
      : west_data_i_iact_inferred__0/out[15]
      : west_data_i_iact_inferred__0/in0[15]
      : west_data_i_iact_inferred/out[15]
      : west_data_i_iact_inferred/in0[15]
      : HMNoC_cluster_west_0/east_data_o_iact[15]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred__0/out[15]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred__0/in0[15]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred/out[15]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred/in0[15]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred__0 /out[15]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred__0 /in0[15]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred /out[15]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred /in0[15]
      : HMNoC_cluster_west_0/\router_cluster_0/router_iact/data_out_inferred /out0[15]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /data2[15]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred__0 /out[15]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred__0 /in0[15]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred /out[15]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred /in0[15]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred__0/out[15]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred__0/in0[15]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred/out[15]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred/in0[15]
      : HMNoC_cluster_east_1/west_data_i_iact[15]
      : east_data_o_iact_inferred__2/out[15]
      : east_data_o_iact_inferred__2/in0[15]
      : east_data_o_iact_inferred__1/out[15]
      : east_data_o_iact_inferred__1/in0[15]
      : HMNoC_cluster_west_1/east_data_o_iact0[15]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred__0/out[15]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred__0/in0[15]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred/out[15]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred/in0[15]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred__0 /out[15]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred__0 /in0[15]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred /out[15]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred /in0[15]
      : HMNoC_cluster_west_1/\router_cluster_0/router_iact/data_out_inferred /out0[15]
      : HMNoC_cluster_west_1/\router_cluster_0/router_iact/data_out_inferred /data3[15]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred__0 /out[15]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred__0 /in0[15]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred /out[15]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred /in0[15]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred__0/out[15]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred__0/in0[15]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred/out[15]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred/in0[15]
      : HMNoC_cluster_west_1/east_data_i_iact0[15]
      : east_data_i_iact_inferred__2/out[15]
      : east_data_i_iact_inferred__2/in0[15]
      : east_data_i_iact_inferred__1/out[15]
      : east_data_i_iact_inferred__1/in0[15]
      : HMNoC_cluster_east_1/west_data_o_iact[15]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred__0/out[15]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred__0/in0[15]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred/out[15]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred/in0[15]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred__0 /out[15]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred__0 /in0[15]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred /out[15]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred /in0[15]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /out0[15]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /data1[15]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred__0/out[15]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred__0/in0[15]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred/out[15]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred/in0[15]
      : HMNoC_cluster_east_0/south_data_i_iact0[15]
      : south_data_i_iact_inferred__2/out[15]
      : south_data_i_iact_inferred__2/in0[15]
      : south_data_i_iact_inferred__1/out[15]
      : south_data_i_iact_inferred__1/in0[15]
      : HMNoC_cluster_east_1/north_data_o_iact[15]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred__0/out[15]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred__0/in0[15]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred/out[15]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred/in0[15]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /out0[15]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /data0[15]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred__0/out[15]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred__0/in0[15]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred/out[15]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred/in0[15]
      : HMNoC_cluster_east_1/north_data_i_iact0[15]
      : north_data_i_iact_inferred__2/out[15]
      : north_data_i_iact_inferred__2/in0[15]
      : north_data_i_iact_inferred__1/out[15]
      : north_data_i_iact_inferred__1/in0[15]
      : HMNoC_cluster_east_0/south_data_o_iact[15]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred__0/out[15]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred__0/in0[15]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred/out[15]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred/in0[15]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /out0[15]
      : HMNoC_cluster_west_0/\router_cluster_0/router_wght/data_out_inferred /data1[14]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred__0/out[14]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred__0/in0[14]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred/out[14]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred/in0[14]
      : HMNoC_cluster_west_0/south_data_i_wght0[14]
      : south_data_i_wght_inferred__0/out[14]
      : south_data_i_wght_inferred__0/in0[14]
      : south_data_i_wght_inferred/out[14]
      : south_data_i_wght_inferred/in0[14]
      : HMNoC_cluster_west_1/north_data_o_wght[14]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred__0/out[14]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred__0/in0[14]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred/out[14]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred/in0[14]
      : HMNoC_cluster_west_1/\router_cluster_0/router_wght/data_out_inferred /out0[14]
      : HMNoC_cluster_west_1/\router_cluster_0/router_wght/data_out_inferred /data0[14]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred__0/out[14]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred__0/in0[14]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred/out[14]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred/in0[14]
      : HMNoC_cluster_west_1/north_data_i_wght0[14]
      : north_data_i_wght_inferred__0/out[14]
      : north_data_i_wght_inferred__0/in0[14]
      : north_data_i_wght_inferred/out[14]
      : north_data_i_wght_inferred/in0[14]
      : HMNoC_cluster_west_0/south_data_o_wght[14]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred__0/out[14]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred__0/in0[14]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred/out[14]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred/in0[14]
      : HMNoC_cluster_west_0/\router_cluster_0/router_wght/data_out_inferred /out0[14]
      : HMNoC_cluster_west_0/\router_cluster_0/router_iact/data_out_inferred /data3[14]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred__0 /out[14]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred__0 /in0[14]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred /out[14]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred /in0[14]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred__0/out[14]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred__0/in0[14]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred/out[14]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred/in0[14]
      : HMNoC_cluster_west_0/east_data_i_iact0[14]
      : east_data_i_iact_inferred__0/out[14]
      : east_data_i_iact_inferred__0/in0[14]
      : east_data_i_iact_inferred/out[14]
      : east_data_i_iact_inferred/in0[14]
      : HMNoC_cluster_east_0/west_data_o_iact[14]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred__0/out[14]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred__0/in0[14]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred/out[14]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred/in0[14]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred__0 /out[14]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred__0 /in0[14]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred /out[14]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred /in0[14]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /out0[14]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /data2[14]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred__0 /out[14]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred__0 /in0[14]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred /out[14]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred /in0[14]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred__0/out[14]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred__0/in0[14]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred/out[14]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred/in0[14]
      : HMNoC_cluster_east_0/west_data_i_iact0[14]
      : west_data_i_iact_inferred__0/out[14]
      : west_data_i_iact_inferred__0/in0[14]
      : west_data_i_iact_inferred/out[14]
      : west_data_i_iact_inferred/in0[14]
      : HMNoC_cluster_west_0/east_data_o_iact[14]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred__0/out[14]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred__0/in0[14]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred/out[14]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred/in0[14]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred__0 /out[14]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred__0 /in0[14]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred /out[14]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred /in0[14]
      : HMNoC_cluster_west_0/\router_cluster_0/router_iact/data_out_inferred /out0[14]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /data2[14]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred__0 /out[14]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred__0 /in0[14]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred /out[14]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred /in0[14]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred__0/out[14]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred__0/in0[14]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred/out[14]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred/in0[14]
      : HMNoC_cluster_east_1/west_data_i_iact[14]
      : east_data_o_iact_inferred__2/out[14]
      : east_data_o_iact_inferred__2/in0[14]
      : east_data_o_iact_inferred__1/out[14]
      : east_data_o_iact_inferred__1/in0[14]
      : HMNoC_cluster_west_1/east_data_o_iact0[14]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred__0/out[14]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred__0/in0[14]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred/out[14]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred/in0[14]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred__0 /out[14]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred__0 /in0[14]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred /out[14]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred /in0[14]
      : HMNoC_cluster_west_1/\router_cluster_0/router_iact/data_out_inferred /out0[14]
      : HMNoC_cluster_west_1/\router_cluster_0/router_iact/data_out_inferred /data3[14]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred__0 /out[14]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred__0 /in0[14]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred /out[14]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred /in0[14]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred__0/out[14]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred__0/in0[14]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred/out[14]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred/in0[14]
      : HMNoC_cluster_west_1/east_data_i_iact0[14]
      : east_data_i_iact_inferred__2/out[14]
      : east_data_i_iact_inferred__2/in0[14]
      : east_data_i_iact_inferred__1/out[14]
      : east_data_i_iact_inferred__1/in0[14]
      : HMNoC_cluster_east_1/west_data_o_iact[14]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred__0/out[14]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred__0/in0[14]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred/out[14]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred/in0[14]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred__0 /out[14]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred__0 /in0[14]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred /out[14]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred /in0[14]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /out0[14]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /data1[14]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred__0/out[14]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred__0/in0[14]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred/out[14]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred/in0[14]
      : HMNoC_cluster_east_0/south_data_i_iact0[14]
      : south_data_i_iact_inferred__2/out[14]
      : south_data_i_iact_inferred__2/in0[14]
      : south_data_i_iact_inferred__1/out[14]
      : south_data_i_iact_inferred__1/in0[14]
      : HMNoC_cluster_east_1/north_data_o_iact[14]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred__0/out[14]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred__0/in0[14]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred/out[14]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred/in0[14]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /out0[14]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /data0[14]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred__0/out[14]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred__0/in0[14]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred/out[14]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred/in0[14]
      : HMNoC_cluster_east_1/north_data_i_iact0[14]
      : north_data_i_iact_inferred__2/out[14]
      : north_data_i_iact_inferred__2/in0[14]
      : north_data_i_iact_inferred__1/out[14]
      : north_data_i_iact_inferred__1/in0[14]
      : HMNoC_cluster_east_0/south_data_o_iact[14]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred__0/out[14]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred__0/in0[14]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred/out[14]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred/in0[14]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /out0[14]
      : HMNoC_cluster_west_0/\router_cluster_0/router_wght/data_out_inferred /data1[13]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred__0/out[13]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred__0/in0[13]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred/out[13]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred/in0[13]
      : HMNoC_cluster_west_0/south_data_i_wght0[13]
      : south_data_i_wght_inferred__0/out[13]
      : south_data_i_wght_inferred__0/in0[13]
      : south_data_i_wght_inferred/out[13]
      : south_data_i_wght_inferred/in0[13]
      : HMNoC_cluster_west_1/north_data_o_wght[13]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred__0/out[13]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred__0/in0[13]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred/out[13]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred/in0[13]
      : HMNoC_cluster_west_1/\router_cluster_0/router_wght/data_out_inferred /out0[13]
      : HMNoC_cluster_west_1/\router_cluster_0/router_wght/data_out_inferred /data0[13]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred__0/out[13]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred__0/in0[13]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred/out[13]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred/in0[13]
      : HMNoC_cluster_west_1/north_data_i_wght0[13]
      : north_data_i_wght_inferred__0/out[13]
      : north_data_i_wght_inferred__0/in0[13]
      : north_data_i_wght_inferred/out[13]
      : north_data_i_wght_inferred/in0[13]
      : HMNoC_cluster_west_0/south_data_o_wght[13]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred__0/out[13]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred__0/in0[13]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred/out[13]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred/in0[13]
      : HMNoC_cluster_west_0/\router_cluster_0/router_wght/data_out_inferred /out0[13]
      : HMNoC_cluster_west_0/\router_cluster_0/router_iact/data_out_inferred /data3[13]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred__0 /out[13]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred__0 /in0[13]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred /out[13]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred /in0[13]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred__0/out[13]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred__0/in0[13]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred/out[13]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred/in0[13]
      : HMNoC_cluster_west_0/east_data_i_iact0[13]
      : east_data_i_iact_inferred__0/out[13]
      : east_data_i_iact_inferred__0/in0[13]
      : east_data_i_iact_inferred/out[13]
      : east_data_i_iact_inferred/in0[13]
      : HMNoC_cluster_east_0/west_data_o_iact[13]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred__0/out[13]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred__0/in0[13]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred/out[13]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred/in0[13]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred__0 /out[13]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred__0 /in0[13]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred /out[13]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred /in0[13]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /out0[13]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /data2[13]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred__0 /out[13]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred__0 /in0[13]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred /out[13]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred /in0[13]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred__0/out[13]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred__0/in0[13]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred/out[13]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred/in0[13]
      : HMNoC_cluster_east_0/west_data_i_iact0[13]
      : west_data_i_iact_inferred__0/out[13]
      : west_data_i_iact_inferred__0/in0[13]
      : west_data_i_iact_inferred/out[13]
      : west_data_i_iact_inferred/in0[13]
      : HMNoC_cluster_west_0/east_data_o_iact[13]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred__0/out[13]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred__0/in0[13]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred/out[13]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred/in0[13]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred__0 /out[13]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred__0 /in0[13]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred /out[13]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred /in0[13]
      : HMNoC_cluster_west_0/\router_cluster_0/router_iact/data_out_inferred /out0[13]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /data2[13]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred__0 /out[13]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred__0 /in0[13]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred /out[13]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred /in0[13]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred__0/out[13]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred__0/in0[13]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred/out[13]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred/in0[13]
      : HMNoC_cluster_east_1/west_data_i_iact[13]
      : east_data_o_iact_inferred__2/out[13]
      : east_data_o_iact_inferred__2/in0[13]
      : east_data_o_iact_inferred__1/out[13]
      : east_data_o_iact_inferred__1/in0[13]
      : HMNoC_cluster_west_1/east_data_o_iact0[13]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred__0/out[13]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred__0/in0[13]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred/out[13]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred/in0[13]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred__0 /out[13]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred__0 /in0[13]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred /out[13]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred /in0[13]
      : HMNoC_cluster_west_1/\router_cluster_0/router_iact/data_out_inferred /out0[13]
      : HMNoC_cluster_west_1/\router_cluster_0/router_iact/data_out_inferred /data3[13]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred__0 /out[13]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred__0 /in0[13]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred /out[13]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred /in0[13]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred__0/out[13]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred__0/in0[13]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred/out[13]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred/in0[13]
      : HMNoC_cluster_west_1/east_data_i_iact0[13]
      : east_data_i_iact_inferred__2/out[13]
      : east_data_i_iact_inferred__2/in0[13]
      : east_data_i_iact_inferred__1/out[13]
      : east_data_i_iact_inferred__1/in0[13]
      : HMNoC_cluster_east_1/west_data_o_iact[13]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred__0/out[13]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred__0/in0[13]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred/out[13]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred/in0[13]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred__0 /out[13]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred__0 /in0[13]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred /out[13]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred /in0[13]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /out0[13]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /data1[13]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred__0/out[13]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred__0/in0[13]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred/out[13]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred/in0[13]
      : HMNoC_cluster_east_0/south_data_i_iact0[13]
      : south_data_i_iact_inferred__2/out[13]
      : south_data_i_iact_inferred__2/in0[13]
      : south_data_i_iact_inferred__1/out[13]
      : south_data_i_iact_inferred__1/in0[13]
      : HMNoC_cluster_east_1/north_data_o_iact[13]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred__0/out[13]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred__0/in0[13]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred/out[13]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred/in0[13]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /out0[13]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /data0[13]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred__0/out[13]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred__0/in0[13]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred/out[13]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred/in0[13]
      : HMNoC_cluster_east_1/north_data_i_iact0[13]
      : north_data_i_iact_inferred__2/out[13]
      : north_data_i_iact_inferred__2/in0[13]
      : north_data_i_iact_inferred__1/out[13]
      : north_data_i_iact_inferred__1/in0[13]
      : HMNoC_cluster_east_0/south_data_o_iact[13]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred__0/out[13]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred__0/in0[13]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred/out[13]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred/in0[13]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /out0[13]
      : HMNoC_cluster_west_0/\router_cluster_0/router_wght/data_out_inferred /data1[12]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred__0/out[12]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred__0/in0[12]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred/out[12]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred/in0[12]
      : HMNoC_cluster_west_0/south_data_i_wght0[12]
      : south_data_i_wght_inferred__0/out[12]
      : south_data_i_wght_inferred__0/in0[12]
      : south_data_i_wght_inferred/out[12]
      : south_data_i_wght_inferred/in0[12]
      : HMNoC_cluster_west_1/north_data_o_wght[12]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred__0/out[12]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred__0/in0[12]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred/out[12]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred/in0[12]
      : HMNoC_cluster_west_1/\router_cluster_0/router_wght/data_out_inferred /out0[12]
      : HMNoC_cluster_west_1/\router_cluster_0/router_wght/data_out_inferred /data0[12]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred__0/out[12]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred__0/in0[12]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred/out[12]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred/in0[12]
      : HMNoC_cluster_west_1/north_data_i_wght0[12]
      : north_data_i_wght_inferred__0/out[12]
      : north_data_i_wght_inferred__0/in0[12]
      : north_data_i_wght_inferred/out[12]
      : north_data_i_wght_inferred/in0[12]
      : HMNoC_cluster_west_0/south_data_o_wght[12]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred__0/out[12]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred__0/in0[12]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred/out[12]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred/in0[12]
      : HMNoC_cluster_west_0/\router_cluster_0/router_wght/data_out_inferred /out0[12]
      : HMNoC_cluster_west_0/\router_cluster_0/router_iact/data_out_inferred /data3[12]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred__0 /out[12]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred__0 /in0[12]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred /out[12]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred /in0[12]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred__0/out[12]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred__0/in0[12]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred/out[12]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred/in0[12]
      : HMNoC_cluster_west_0/east_data_i_iact0[12]
      : east_data_i_iact_inferred__0/out[12]
      : east_data_i_iact_inferred__0/in0[12]
      : east_data_i_iact_inferred/out[12]
      : east_data_i_iact_inferred/in0[12]
      : HMNoC_cluster_east_0/west_data_o_iact[12]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred__0/out[12]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred__0/in0[12]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred/out[12]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred/in0[12]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred__0 /out[12]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred__0 /in0[12]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred /out[12]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred /in0[12]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /out0[12]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /data2[12]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred__0 /out[12]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred__0 /in0[12]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred /out[12]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred /in0[12]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred__0/out[12]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred__0/in0[12]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred/out[12]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred/in0[12]
      : HMNoC_cluster_east_0/west_data_i_iact0[12]
      : west_data_i_iact_inferred__0/out[12]
      : west_data_i_iact_inferred__0/in0[12]
      : west_data_i_iact_inferred/out[12]
      : west_data_i_iact_inferred/in0[12]
      : HMNoC_cluster_west_0/east_data_o_iact[12]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred__0/out[12]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred__0/in0[12]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred/out[12]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred/in0[12]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred__0 /out[12]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred__0 /in0[12]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred /out[12]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred /in0[12]
      : HMNoC_cluster_west_0/\router_cluster_0/router_iact/data_out_inferred /out0[12]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /data2[12]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred__0 /out[12]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred__0 /in0[12]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred /out[12]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred /in0[12]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred__0/out[12]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred__0/in0[12]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred/out[12]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred/in0[12]
      : HMNoC_cluster_east_1/west_data_i_iact[12]
      : east_data_o_iact_inferred__2/out[12]
      : east_data_o_iact_inferred__2/in0[12]
      : east_data_o_iact_inferred__1/out[12]
      : east_data_o_iact_inferred__1/in0[12]
      : HMNoC_cluster_west_1/east_data_o_iact0[12]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred__0/out[12]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred__0/in0[12]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred/out[12]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred/in0[12]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred__0 /out[12]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred__0 /in0[12]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred /out[12]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred /in0[12]
      : HMNoC_cluster_west_1/\router_cluster_0/router_iact/data_out_inferred /out0[12]
      : HMNoC_cluster_west_1/\router_cluster_0/router_iact/data_out_inferred /data3[12]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred__0 /out[12]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred__0 /in0[12]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred /out[12]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred /in0[12]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred__0/out[12]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred__0/in0[12]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred/out[12]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred/in0[12]
      : HMNoC_cluster_west_1/east_data_i_iact0[12]
      : east_data_i_iact_inferred__2/out[12]
      : east_data_i_iact_inferred__2/in0[12]
      : east_data_i_iact_inferred__1/out[12]
      : east_data_i_iact_inferred__1/in0[12]
      : HMNoC_cluster_east_1/west_data_o_iact[12]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred__0/out[12]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred__0/in0[12]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred/out[12]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred/in0[12]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred__0 /out[12]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred__0 /in0[12]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred /out[12]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred /in0[12]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /out0[12]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /data1[12]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred__0/out[12]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred__0/in0[12]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred/out[12]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred/in0[12]
      : HMNoC_cluster_east_0/south_data_i_iact0[12]
      : south_data_i_iact_inferred__2/out[12]
      : south_data_i_iact_inferred__2/in0[12]
      : south_data_i_iact_inferred__1/out[12]
      : south_data_i_iact_inferred__1/in0[12]
      : HMNoC_cluster_east_1/north_data_o_iact[12]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred__0/out[12]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred__0/in0[12]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred/out[12]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred/in0[12]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /out0[12]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /data0[12]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred__0/out[12]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred__0/in0[12]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred/out[12]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred/in0[12]
      : HMNoC_cluster_east_1/north_data_i_iact0[12]
      : north_data_i_iact_inferred__2/out[12]
      : north_data_i_iact_inferred__2/in0[12]
      : north_data_i_iact_inferred__1/out[12]
      : north_data_i_iact_inferred__1/in0[12]
      : HMNoC_cluster_east_0/south_data_o_iact[12]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred__0/out[12]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred__0/in0[12]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred/out[12]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred/in0[12]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /out0[12]
      : HMNoC_cluster_west_0/\router_cluster_0/router_wght/data_out_inferred /data1[11]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred__0/out[11]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred__0/in0[11]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred/out[11]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred/in0[11]
      : HMNoC_cluster_west_0/south_data_i_wght0[11]
      : south_data_i_wght_inferred__0/out[11]
      : south_data_i_wght_inferred__0/in0[11]
      : south_data_i_wght_inferred/out[11]
      : south_data_i_wght_inferred/in0[11]
      : HMNoC_cluster_west_1/north_data_o_wght[11]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred__0/out[11]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred__0/in0[11]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred/out[11]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred/in0[11]
      : HMNoC_cluster_west_1/\router_cluster_0/router_wght/data_out_inferred /out0[11]
      : HMNoC_cluster_west_1/\router_cluster_0/router_wght/data_out_inferred /data0[11]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred__0/out[11]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred__0/in0[11]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred/out[11]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred/in0[11]
      : HMNoC_cluster_west_1/north_data_i_wght0[11]
      : north_data_i_wght_inferred__0/out[11]
      : north_data_i_wght_inferred__0/in0[11]
      : north_data_i_wght_inferred/out[11]
      : north_data_i_wght_inferred/in0[11]
      : HMNoC_cluster_west_0/south_data_o_wght[11]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred__0/out[11]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred__0/in0[11]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred/out[11]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred/in0[11]
      : HMNoC_cluster_west_0/\router_cluster_0/router_wght/data_out_inferred /out0[11]
      : HMNoC_cluster_west_0/\router_cluster_0/router_iact/data_out_inferred /data3[11]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred__0 /out[11]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred__0 /in0[11]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred /out[11]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred /in0[11]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred__0/out[11]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred__0/in0[11]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred/out[11]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred/in0[11]
      : HMNoC_cluster_west_0/east_data_i_iact0[11]
      : east_data_i_iact_inferred__0/out[11]
      : east_data_i_iact_inferred__0/in0[11]
      : east_data_i_iact_inferred/out[11]
      : east_data_i_iact_inferred/in0[11]
      : HMNoC_cluster_east_0/west_data_o_iact[11]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred__0/out[11]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred__0/in0[11]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred/out[11]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred/in0[11]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred__0 /out[11]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred__0 /in0[11]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred /out[11]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred /in0[11]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /out0[11]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /data2[11]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred__0 /out[11]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred__0 /in0[11]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred /out[11]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred /in0[11]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred__0/out[11]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred__0/in0[11]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred/out[11]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred/in0[11]
      : HMNoC_cluster_east_0/west_data_i_iact0[11]
      : west_data_i_iact_inferred__0/out[11]
      : west_data_i_iact_inferred__0/in0[11]
      : west_data_i_iact_inferred/out[11]
      : west_data_i_iact_inferred/in0[11]
      : HMNoC_cluster_west_0/east_data_o_iact[11]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred__0/out[11]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred__0/in0[11]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred/out[11]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred/in0[11]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred__0 /out[11]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred__0 /in0[11]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred /out[11]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred /in0[11]
      : HMNoC_cluster_west_0/\router_cluster_0/router_iact/data_out_inferred /out0[11]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /data2[11]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred__0 /out[11]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred__0 /in0[11]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred /out[11]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred /in0[11]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred__0/out[11]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred__0/in0[11]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred/out[11]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred/in0[11]
      : HMNoC_cluster_east_1/west_data_i_iact[11]
      : east_data_o_iact_inferred__2/out[11]
      : east_data_o_iact_inferred__2/in0[11]
      : east_data_o_iact_inferred__1/out[11]
      : east_data_o_iact_inferred__1/in0[11]
      : HMNoC_cluster_west_1/east_data_o_iact0[11]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred__0/out[11]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred__0/in0[11]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred/out[11]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred/in0[11]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred__0 /out[11]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred__0 /in0[11]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred /out[11]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred /in0[11]
      : HMNoC_cluster_west_1/\router_cluster_0/router_iact/data_out_inferred /out0[11]
      : HMNoC_cluster_west_1/\router_cluster_0/router_iact/data_out_inferred /data3[11]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred__0 /out[11]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred__0 /in0[11]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred /out[11]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred /in0[11]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred__0/out[11]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred__0/in0[11]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred/out[11]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred/in0[11]
      : HMNoC_cluster_west_1/east_data_i_iact0[11]
      : east_data_i_iact_inferred__2/out[11]
      : east_data_i_iact_inferred__2/in0[11]
      : east_data_i_iact_inferred__1/out[11]
      : east_data_i_iact_inferred__1/in0[11]
      : HMNoC_cluster_east_1/west_data_o_iact[11]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred__0/out[11]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred__0/in0[11]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred/out[11]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred/in0[11]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred__0 /out[11]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred__0 /in0[11]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred /out[11]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred /in0[11]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /out0[11]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /data1[11]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred__0/out[11]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred__0/in0[11]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred/out[11]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred/in0[11]
      : HMNoC_cluster_east_0/south_data_i_iact0[11]
      : south_data_i_iact_inferred__2/out[11]
      : south_data_i_iact_inferred__2/in0[11]
      : south_data_i_iact_inferred__1/out[11]
      : south_data_i_iact_inferred__1/in0[11]
      : HMNoC_cluster_east_1/north_data_o_iact[11]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred__0/out[11]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred__0/in0[11]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred/out[11]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred/in0[11]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /out0[11]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /data0[11]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred__0/out[11]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred__0/in0[11]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred/out[11]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred/in0[11]
      : HMNoC_cluster_east_1/north_data_i_iact0[11]
      : north_data_i_iact_inferred__2/out[11]
      : north_data_i_iact_inferred__2/in0[11]
      : north_data_i_iact_inferred__1/out[11]
      : north_data_i_iact_inferred__1/in0[11]
      : HMNoC_cluster_east_0/south_data_o_iact[11]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred__0/out[11]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred__0/in0[11]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred/out[11]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred/in0[11]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /out0[11]
      : HMNoC_cluster_west_0/\router_cluster_0/router_wght/data_out_inferred /data1[10]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred__0/out[10]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred__0/in0[10]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred/out[10]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred/in0[10]
      : HMNoC_cluster_west_0/south_data_i_wght0[10]
      : south_data_i_wght_inferred__0/out[10]
      : south_data_i_wght_inferred__0/in0[10]
      : south_data_i_wght_inferred/out[10]
      : south_data_i_wght_inferred/in0[10]
      : HMNoC_cluster_west_1/north_data_o_wght[10]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred__0/out[10]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred__0/in0[10]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred/out[10]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred/in0[10]
      : HMNoC_cluster_west_1/\router_cluster_0/router_wght/data_out_inferred /out0[10]
      : HMNoC_cluster_west_1/\router_cluster_0/router_wght/data_out_inferred /data0[10]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred__0/out[10]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred__0/in0[10]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred/out[10]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred/in0[10]
      : HMNoC_cluster_west_1/north_data_i_wght0[10]
      : north_data_i_wght_inferred__0/out[10]
      : north_data_i_wght_inferred__0/in0[10]
      : north_data_i_wght_inferred/out[10]
      : north_data_i_wght_inferred/in0[10]
      : HMNoC_cluster_west_0/south_data_o_wght[10]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred__0/out[10]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred__0/in0[10]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred/out[10]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred/in0[10]
      : HMNoC_cluster_west_0/\router_cluster_0/router_wght/data_out_inferred /out0[10]
      : HMNoC_cluster_west_0/\router_cluster_0/router_iact/data_out_inferred /data3[10]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred__0 /out[10]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred__0 /in0[10]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred /out[10]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred /in0[10]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred__0/out[10]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred__0/in0[10]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred/out[10]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred/in0[10]
      : HMNoC_cluster_west_0/east_data_i_iact0[10]
      : east_data_i_iact_inferred__0/out[10]
      : east_data_i_iact_inferred__0/in0[10]
      : east_data_i_iact_inferred/out[10]
      : east_data_i_iact_inferred/in0[10]
      : HMNoC_cluster_east_0/west_data_o_iact[10]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred__0/out[10]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred__0/in0[10]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred/out[10]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred/in0[10]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred__0 /out[10]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred__0 /in0[10]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred /out[10]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred /in0[10]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /out0[10]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /data2[10]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred__0 /out[10]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred__0 /in0[10]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred /out[10]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred /in0[10]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred__0/out[10]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred__0/in0[10]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred/out[10]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred/in0[10]
      : HMNoC_cluster_east_0/west_data_i_iact0[10]
      : west_data_i_iact_inferred__0/out[10]
      : west_data_i_iact_inferred__0/in0[10]
      : west_data_i_iact_inferred/out[10]
      : west_data_i_iact_inferred/in0[10]
      : HMNoC_cluster_west_0/east_data_o_iact[10]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred__0/out[10]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred__0/in0[10]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred/out[10]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred/in0[10]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred__0 /out[10]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred__0 /in0[10]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred /out[10]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred /in0[10]
      : HMNoC_cluster_west_0/\router_cluster_0/router_iact/data_out_inferred /out0[10]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /data2[10]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred__0 /out[10]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred__0 /in0[10]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred /out[10]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred /in0[10]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred__0/out[10]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred__0/in0[10]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred/out[10]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred/in0[10]
      : HMNoC_cluster_east_1/west_data_i_iact[10]
      : east_data_o_iact_inferred__2/out[10]
      : east_data_o_iact_inferred__2/in0[10]
      : east_data_o_iact_inferred__1/out[10]
      : east_data_o_iact_inferred__1/in0[10]
      : HMNoC_cluster_west_1/east_data_o_iact0[10]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred__0/out[10]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred__0/in0[10]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred/out[10]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred/in0[10]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred__0 /out[10]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred__0 /in0[10]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred /out[10]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred /in0[10]
      : HMNoC_cluster_west_1/\router_cluster_0/router_iact/data_out_inferred /out0[10]
      : HMNoC_cluster_west_1/\router_cluster_0/router_iact/data_out_inferred /data3[10]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred__0 /out[10]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred__0 /in0[10]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred /out[10]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred /in0[10]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred__0/out[10]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred__0/in0[10]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred/out[10]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred/in0[10]
      : HMNoC_cluster_west_1/east_data_i_iact0[10]
      : east_data_i_iact_inferred__2/out[10]
      : east_data_i_iact_inferred__2/in0[10]
      : east_data_i_iact_inferred__1/out[10]
      : east_data_i_iact_inferred__1/in0[10]
      : HMNoC_cluster_east_1/west_data_o_iact[10]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred__0/out[10]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred__0/in0[10]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred/out[10]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred/in0[10]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred__0 /out[10]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred__0 /in0[10]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred /out[10]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred /in0[10]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /out0[10]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /data1[10]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred__0/out[10]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred__0/in0[10]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred/out[10]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred/in0[10]
      : HMNoC_cluster_east_0/south_data_i_iact0[10]
      : south_data_i_iact_inferred__2/out[10]
      : south_data_i_iact_inferred__2/in0[10]
      : south_data_i_iact_inferred__1/out[10]
      : south_data_i_iact_inferred__1/in0[10]
      : HMNoC_cluster_east_1/north_data_o_iact[10]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred__0/out[10]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred__0/in0[10]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred/out[10]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred/in0[10]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /out0[10]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /data0[10]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred__0/out[10]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred__0/in0[10]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred/out[10]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred/in0[10]
      : HMNoC_cluster_east_1/north_data_i_iact0[10]
      : north_data_i_iact_inferred__2/out[10]
      : north_data_i_iact_inferred__2/in0[10]
      : north_data_i_iact_inferred__1/out[10]
      : north_data_i_iact_inferred__1/in0[10]
      : HMNoC_cluster_east_0/south_data_o_iact[10]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred__0/out[10]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred__0/in0[10]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred/out[10]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred/in0[10]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /out0[10]
      : HMNoC_cluster_west_0/\router_cluster_0/router_wght/data_out_inferred /data1[9]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred__0/out[9]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred__0/in0[9]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred/out[9]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred/in0[9]
      : HMNoC_cluster_west_0/south_data_i_wght0[9]
      : south_data_i_wght_inferred__0/out[9]
      : south_data_i_wght_inferred__0/in0[9]
      : south_data_i_wght_inferred/out[9]
      : south_data_i_wght_inferred/in0[9]
      : HMNoC_cluster_west_1/north_data_o_wght[9]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred__0/out[9]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred__0/in0[9]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred/out[9]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred/in0[9]
      : HMNoC_cluster_west_1/\router_cluster_0/router_wght/data_out_inferred /out0[9]
      : HMNoC_cluster_west_1/\router_cluster_0/router_wght/data_out_inferred /data0[9]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred__0/out[9]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred__0/in0[9]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred/out[9]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred/in0[9]
      : HMNoC_cluster_west_1/north_data_i_wght0[9]
      : north_data_i_wght_inferred__0/out[9]
      : north_data_i_wght_inferred__0/in0[9]
      : north_data_i_wght_inferred/out[9]
      : north_data_i_wght_inferred/in0[9]
      : HMNoC_cluster_west_0/south_data_o_wght[9]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred__0/out[9]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred__0/in0[9]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred/out[9]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred/in0[9]
      : HMNoC_cluster_west_0/\router_cluster_0/router_wght/data_out_inferred /out0[9]
      : HMNoC_cluster_west_0/\router_cluster_0/router_iact/data_out_inferred /data3[9]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred__0 /out[9]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred__0 /in0[9]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred /out[9]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred /in0[9]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred__0/out[9]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred__0/in0[9]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred/out[9]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred/in0[9]
      : HMNoC_cluster_west_0/east_data_i_iact0[9]
      : east_data_i_iact_inferred__0/out[9]
      : east_data_i_iact_inferred__0/in0[9]
      : east_data_i_iact_inferred/out[9]
      : east_data_i_iact_inferred/in0[9]
      : HMNoC_cluster_east_0/west_data_o_iact[9]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred__0/out[9]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred__0/in0[9]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred/out[9]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred/in0[9]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred__0 /out[9]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred__0 /in0[9]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred /out[9]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred /in0[9]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /out0[9]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /data2[9]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred__0 /out[9]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred__0 /in0[9]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred /out[9]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred /in0[9]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred__0/out[9]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred__0/in0[9]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred/out[9]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred/in0[9]
      : HMNoC_cluster_east_0/west_data_i_iact0[9]
      : west_data_i_iact_inferred__0/out[9]
      : west_data_i_iact_inferred__0/in0[9]
      : west_data_i_iact_inferred/out[9]
      : west_data_i_iact_inferred/in0[9]
      : HMNoC_cluster_west_0/east_data_o_iact[9]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred__0/out[9]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred__0/in0[9]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred/out[9]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred/in0[9]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred__0 /out[9]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred__0 /in0[9]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred /out[9]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred /in0[9]
      : HMNoC_cluster_west_0/\router_cluster_0/router_iact/data_out_inferred /out0[9]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /data2[9]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred__0 /out[9]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred__0 /in0[9]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred /out[9]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred /in0[9]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred__0/out[9]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred__0/in0[9]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred/out[9]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred/in0[9]
      : HMNoC_cluster_east_1/west_data_i_iact[9]
      : east_data_o_iact_inferred__2/out[9]
      : east_data_o_iact_inferred__2/in0[9]
      : east_data_o_iact_inferred__1/out[9]
      : east_data_o_iact_inferred__1/in0[9]
      : HMNoC_cluster_west_1/east_data_o_iact0[9]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred__0/out[9]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred__0/in0[9]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred/out[9]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred/in0[9]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred__0 /out[9]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred__0 /in0[9]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred /out[9]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred /in0[9]
      : HMNoC_cluster_west_1/\router_cluster_0/router_iact/data_out_inferred /out0[9]
      : HMNoC_cluster_west_1/\router_cluster_0/router_iact/data_out_inferred /data3[9]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred__0 /out[9]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred__0 /in0[9]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred /out[9]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred /in0[9]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred__0/out[9]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred__0/in0[9]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred/out[9]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred/in0[9]
      : HMNoC_cluster_west_1/east_data_i_iact0[9]
      : east_data_i_iact_inferred__2/out[9]
      : east_data_i_iact_inferred__2/in0[9]
      : east_data_i_iact_inferred__1/out[9]
      : east_data_i_iact_inferred__1/in0[9]
      : HMNoC_cluster_east_1/west_data_o_iact[9]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred__0/out[9]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred__0/in0[9]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred/out[9]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred/in0[9]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred__0 /out[9]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred__0 /in0[9]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred /out[9]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred /in0[9]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /out0[9]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /data1[9]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred__0/out[9]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred__0/in0[9]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred/out[9]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred/in0[9]
      : HMNoC_cluster_east_0/south_data_i_iact0[9]
      : south_data_i_iact_inferred__2/out[9]
      : south_data_i_iact_inferred__2/in0[9]
      : south_data_i_iact_inferred__1/out[9]
      : south_data_i_iact_inferred__1/in0[9]
      : HMNoC_cluster_east_1/north_data_o_iact[9]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred__0/out[9]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred__0/in0[9]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred/out[9]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred/in0[9]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /out0[9]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /data0[9]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred__0/out[9]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred__0/in0[9]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred/out[9]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred/in0[9]
      : HMNoC_cluster_east_1/north_data_i_iact0[9]
      : north_data_i_iact_inferred__2/out[9]
      : north_data_i_iact_inferred__2/in0[9]
      : north_data_i_iact_inferred__1/out[9]
      : north_data_i_iact_inferred__1/in0[9]
      : HMNoC_cluster_east_0/south_data_o_iact[9]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred__0/out[9]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred__0/in0[9]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred/out[9]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred/in0[9]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /out0[9]
      : HMNoC_cluster_west_0/\router_cluster_0/router_wght/data_out_inferred /data1[8]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred__0/out[8]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred__0/in0[8]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred/out[8]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred/in0[8]
      : HMNoC_cluster_west_0/south_data_i_wght0[8]
      : south_data_i_wght_inferred__0/out[8]
      : south_data_i_wght_inferred__0/in0[8]
      : south_data_i_wght_inferred/out[8]
      : south_data_i_wght_inferred/in0[8]
      : HMNoC_cluster_west_1/north_data_o_wght[8]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred__0/out[8]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred__0/in0[8]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred/out[8]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred/in0[8]
      : HMNoC_cluster_west_1/\router_cluster_0/router_wght/data_out_inferred /out0[8]
      : HMNoC_cluster_west_1/\router_cluster_0/router_wght/data_out_inferred /data0[8]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred__0/out[8]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred__0/in0[8]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred/out[8]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred/in0[8]
      : HMNoC_cluster_west_1/north_data_i_wght0[8]
      : north_data_i_wght_inferred__0/out[8]
      : north_data_i_wght_inferred__0/in0[8]
      : north_data_i_wght_inferred/out[8]
      : north_data_i_wght_inferred/in0[8]
      : HMNoC_cluster_west_0/south_data_o_wght[8]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred__0/out[8]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred__0/in0[8]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred/out[8]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred/in0[8]
      : HMNoC_cluster_west_0/\router_cluster_0/router_wght/data_out_inferred /out0[8]
      : HMNoC_cluster_west_0/\router_cluster_0/router_iact/data_out_inferred /data3[8]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred__0 /out[8]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred__0 /in0[8]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred /out[8]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred /in0[8]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred__0/out[8]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred__0/in0[8]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred/out[8]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred/in0[8]
      : HMNoC_cluster_west_0/east_data_i_iact0[8]
      : east_data_i_iact_inferred__0/out[8]
      : east_data_i_iact_inferred__0/in0[8]
      : east_data_i_iact_inferred/out[8]
      : east_data_i_iact_inferred/in0[8]
      : HMNoC_cluster_east_0/west_data_o_iact[8]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred__0/out[8]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred__0/in0[8]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred/out[8]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred/in0[8]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred__0 /out[8]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred__0 /in0[8]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred /out[8]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred /in0[8]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /out0[8]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /data2[8]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred__0 /out[8]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred__0 /in0[8]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred /out[8]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred /in0[8]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred__0/out[8]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred__0/in0[8]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred/out[8]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred/in0[8]
      : HMNoC_cluster_east_0/west_data_i_iact0[8]
      : west_data_i_iact_inferred__0/out[8]
      : west_data_i_iact_inferred__0/in0[8]
      : west_data_i_iact_inferred/out[8]
      : west_data_i_iact_inferred/in0[8]
      : HMNoC_cluster_west_0/east_data_o_iact[8]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred__0/out[8]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred__0/in0[8]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred/out[8]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred/in0[8]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred__0 /out[8]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred__0 /in0[8]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred /out[8]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred /in0[8]
      : HMNoC_cluster_west_0/\router_cluster_0/router_iact/data_out_inferred /out0[8]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /data2[8]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred__0 /out[8]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred__0 /in0[8]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred /out[8]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred /in0[8]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred__0/out[8]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred__0/in0[8]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred/out[8]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred/in0[8]
      : HMNoC_cluster_east_1/west_data_i_iact[8]
      : east_data_o_iact_inferred__2/out[8]
      : east_data_o_iact_inferred__2/in0[8]
      : east_data_o_iact_inferred__1/out[8]
      : east_data_o_iact_inferred__1/in0[8]
      : HMNoC_cluster_west_1/east_data_o_iact0[8]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred__0/out[8]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred__0/in0[8]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred/out[8]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred/in0[8]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred__0 /out[8]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred__0 /in0[8]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred /out[8]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred /in0[8]
      : HMNoC_cluster_west_1/\router_cluster_0/router_iact/data_out_inferred /out0[8]
      : HMNoC_cluster_west_1/\router_cluster_0/router_iact/data_out_inferred /data3[8]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred__0 /out[8]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred__0 /in0[8]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred /out[8]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred /in0[8]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred__0/out[8]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred__0/in0[8]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred/out[8]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred/in0[8]
      : HMNoC_cluster_west_1/east_data_i_iact0[8]
      : east_data_i_iact_inferred__2/out[8]
      : east_data_i_iact_inferred__2/in0[8]
      : east_data_i_iact_inferred__1/out[8]
      : east_data_i_iact_inferred__1/in0[8]
      : HMNoC_cluster_east_1/west_data_o_iact[8]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred__0/out[8]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred__0/in0[8]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred/out[8]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred/in0[8]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred__0 /out[8]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred__0 /in0[8]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred /out[8]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred /in0[8]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /out0[8]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /data1[8]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred__0/out[8]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred__0/in0[8]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred/out[8]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred/in0[8]
      : HMNoC_cluster_east_0/south_data_i_iact0[8]
      : south_data_i_iact_inferred__2/out[8]
      : south_data_i_iact_inferred__2/in0[8]
      : south_data_i_iact_inferred__1/out[8]
      : south_data_i_iact_inferred__1/in0[8]
      : HMNoC_cluster_east_1/north_data_o_iact[8]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred__0/out[8]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred__0/in0[8]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred/out[8]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred/in0[8]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /out0[8]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /data0[8]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred__0/out[8]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred__0/in0[8]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred/out[8]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred/in0[8]
      : HMNoC_cluster_east_1/north_data_i_iact0[8]
      : north_data_i_iact_inferred__2/out[8]
      : north_data_i_iact_inferred__2/in0[8]
      : north_data_i_iact_inferred__1/out[8]
      : north_data_i_iact_inferred__1/in0[8]
      : HMNoC_cluster_east_0/south_data_o_iact[8]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred__0/out[8]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred__0/in0[8]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred/out[8]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred/in0[8]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /out0[8]
      : HMNoC_cluster_west_0/\router_cluster_0/router_wght/data_out_inferred /data1[7]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred__0/out[7]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred__0/in0[7]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred/out[7]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred/in0[7]
      : HMNoC_cluster_west_0/south_data_i_wght0[7]
      : south_data_i_wght_inferred__0/out[7]
      : south_data_i_wght_inferred__0/in0[7]
      : south_data_i_wght_inferred/out[7]
      : south_data_i_wght_inferred/in0[7]
      : HMNoC_cluster_west_1/north_data_o_wght[7]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred__0/out[7]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred__0/in0[7]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred/out[7]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred/in0[7]
      : HMNoC_cluster_west_1/\router_cluster_0/router_wght/data_out_inferred /out0[7]
      : HMNoC_cluster_west_1/\router_cluster_0/router_wght/data_out_inferred /data0[7]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred__0/out[7]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred__0/in0[7]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred/out[7]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred/in0[7]
      : HMNoC_cluster_west_1/north_data_i_wght0[7]
      : north_data_i_wght_inferred__0/out[7]
      : north_data_i_wght_inferred__0/in0[7]
      : north_data_i_wght_inferred/out[7]
      : north_data_i_wght_inferred/in0[7]
      : HMNoC_cluster_west_0/south_data_o_wght[7]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred__0/out[7]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred__0/in0[7]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred/out[7]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred/in0[7]
      : HMNoC_cluster_west_0/\router_cluster_0/router_wght/data_out_inferred /out0[7]
      : HMNoC_cluster_west_0/\router_cluster_0/router_iact/data_out_inferred /data3[7]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred__0 /out[7]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred__0 /in0[7]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred /out[7]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred /in0[7]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred__0/out[7]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred__0/in0[7]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred/out[7]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred/in0[7]
      : HMNoC_cluster_west_0/east_data_i_iact0[7]
      : east_data_i_iact_inferred__0/out[7]
      : east_data_i_iact_inferred__0/in0[7]
      : east_data_i_iact_inferred/out[7]
      : east_data_i_iact_inferred/in0[7]
      : HMNoC_cluster_east_0/west_data_o_iact[7]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred__0/out[7]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred__0/in0[7]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred/out[7]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred/in0[7]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred__0 /out[7]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred__0 /in0[7]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred /out[7]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred /in0[7]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /out0[7]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /data2[7]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred__0 /out[7]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred__0 /in0[7]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred /out[7]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred /in0[7]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred__0/out[7]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred__0/in0[7]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred/out[7]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred/in0[7]
      : HMNoC_cluster_east_0/west_data_i_iact0[7]
      : west_data_i_iact_inferred__0/out[7]
      : west_data_i_iact_inferred__0/in0[7]
      : west_data_i_iact_inferred/out[7]
      : west_data_i_iact_inferred/in0[7]
      : HMNoC_cluster_west_0/east_data_o_iact[7]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred__0/out[7]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred__0/in0[7]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred/out[7]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred/in0[7]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred__0 /out[7]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred__0 /in0[7]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred /out[7]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred /in0[7]
      : HMNoC_cluster_west_0/\router_cluster_0/router_iact/data_out_inferred /out0[7]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /data2[7]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred__0 /out[7]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred__0 /in0[7]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred /out[7]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred /in0[7]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred__0/out[7]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred__0/in0[7]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred/out[7]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred/in0[7]
      : HMNoC_cluster_east_1/west_data_i_iact[7]
      : east_data_o_iact_inferred__2/out[7]
      : east_data_o_iact_inferred__2/in0[7]
      : east_data_o_iact_inferred__1/out[7]
      : east_data_o_iact_inferred__1/in0[7]
      : HMNoC_cluster_west_1/east_data_o_iact0[7]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred__0/out[7]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred__0/in0[7]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred/out[7]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred/in0[7]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred__0 /out[7]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred__0 /in0[7]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred /out[7]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred /in0[7]
      : HMNoC_cluster_west_1/\router_cluster_0/router_iact/data_out_inferred /out0[7]
      : HMNoC_cluster_west_1/\router_cluster_0/router_iact/data_out_inferred /data3[7]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred__0 /out[7]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred__0 /in0[7]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred /out[7]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred /in0[7]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred__0/out[7]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred__0/in0[7]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred/out[7]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred/in0[7]
      : HMNoC_cluster_west_1/east_data_i_iact0[7]
      : east_data_i_iact_inferred__2/out[7]
      : east_data_i_iact_inferred__2/in0[7]
      : east_data_i_iact_inferred__1/out[7]
      : east_data_i_iact_inferred__1/in0[7]
      : HMNoC_cluster_east_1/west_data_o_iact[7]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred__0/out[7]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred__0/in0[7]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred/out[7]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred/in0[7]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred__0 /out[7]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred__0 /in0[7]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred /out[7]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred /in0[7]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /out0[7]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /data1[7]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred__0/out[7]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred__0/in0[7]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred/out[7]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred/in0[7]
      : HMNoC_cluster_east_0/south_data_i_iact0[7]
      : south_data_i_iact_inferred__2/out[7]
      : south_data_i_iact_inferred__2/in0[7]
      : south_data_i_iact_inferred__1/out[7]
      : south_data_i_iact_inferred__1/in0[7]
      : HMNoC_cluster_east_1/north_data_o_iact[7]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred__0/out[7]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred__0/in0[7]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred/out[7]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred/in0[7]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /out0[7]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /data0[7]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred__0/out[7]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred__0/in0[7]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred/out[7]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred/in0[7]
      : HMNoC_cluster_east_1/north_data_i_iact0[7]
      : north_data_i_iact_inferred__2/out[7]
      : north_data_i_iact_inferred__2/in0[7]
      : north_data_i_iact_inferred__1/out[7]
      : north_data_i_iact_inferred__1/in0[7]
      : HMNoC_cluster_east_0/south_data_o_iact[7]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred__0/out[7]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred__0/in0[7]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred/out[7]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred/in0[7]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /out0[7]
      : HMNoC_cluster_west_0/\router_cluster_0/router_wght/data_out_inferred /data1[6]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred__0/out[6]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred__0/in0[6]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred/out[6]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred/in0[6]
      : HMNoC_cluster_west_0/south_data_i_wght0[6]
      : south_data_i_wght_inferred__0/out[6]
      : south_data_i_wght_inferred__0/in0[6]
      : south_data_i_wght_inferred/out[6]
      : south_data_i_wght_inferred/in0[6]
      : HMNoC_cluster_west_1/north_data_o_wght[6]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred__0/out[6]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred__0/in0[6]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred/out[6]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred/in0[6]
      : HMNoC_cluster_west_1/\router_cluster_0/router_wght/data_out_inferred /out0[6]
      : HMNoC_cluster_west_1/\router_cluster_0/router_wght/data_out_inferred /data0[6]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred__0/out[6]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred__0/in0[6]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred/out[6]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred/in0[6]
      : HMNoC_cluster_west_1/north_data_i_wght0[6]
      : north_data_i_wght_inferred__0/out[6]
      : north_data_i_wght_inferred__0/in0[6]
      : north_data_i_wght_inferred/out[6]
      : north_data_i_wght_inferred/in0[6]
      : HMNoC_cluster_west_0/south_data_o_wght[6]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred__0/out[6]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred__0/in0[6]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred/out[6]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred/in0[6]
      : HMNoC_cluster_west_0/\router_cluster_0/router_wght/data_out_inferred /out0[6]
      : HMNoC_cluster_west_0/\router_cluster_0/router_iact/data_out_inferred /data3[6]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred__0 /out[6]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred__0 /in0[6]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred /out[6]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred /in0[6]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred__0/out[6]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred__0/in0[6]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred/out[6]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred/in0[6]
      : HMNoC_cluster_west_0/east_data_i_iact0[6]
      : east_data_i_iact_inferred__0/out[6]
      : east_data_i_iact_inferred__0/in0[6]
      : east_data_i_iact_inferred/out[6]
      : east_data_i_iact_inferred/in0[6]
      : HMNoC_cluster_east_0/west_data_o_iact[6]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred__0/out[6]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred__0/in0[6]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred/out[6]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred/in0[6]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred__0 /out[6]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred__0 /in0[6]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred /out[6]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred /in0[6]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /out0[6]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /data2[6]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred__0 /out[6]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred__0 /in0[6]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred /out[6]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred /in0[6]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred__0/out[6]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred__0/in0[6]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred/out[6]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred/in0[6]
      : HMNoC_cluster_east_0/west_data_i_iact0[6]
      : west_data_i_iact_inferred__0/out[6]
      : west_data_i_iact_inferred__0/in0[6]
      : west_data_i_iact_inferred/out[6]
      : west_data_i_iact_inferred/in0[6]
      : HMNoC_cluster_west_0/east_data_o_iact[6]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred__0/out[6]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred__0/in0[6]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred/out[6]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred/in0[6]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred__0 /out[6]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred__0 /in0[6]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred /out[6]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred /in0[6]
      : HMNoC_cluster_west_0/\router_cluster_0/router_iact/data_out_inferred /out0[6]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /data2[6]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred__0 /out[6]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred__0 /in0[6]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred /out[6]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred /in0[6]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred__0/out[6]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred__0/in0[6]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred/out[6]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred/in0[6]
      : HMNoC_cluster_east_1/west_data_i_iact[6]
      : east_data_o_iact_inferred__2/out[6]
      : east_data_o_iact_inferred__2/in0[6]
      : east_data_o_iact_inferred__1/out[6]
      : east_data_o_iact_inferred__1/in0[6]
      : HMNoC_cluster_west_1/east_data_o_iact0[6]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred__0/out[6]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred__0/in0[6]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred/out[6]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred/in0[6]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred__0 /out[6]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred__0 /in0[6]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred /out[6]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred /in0[6]
      : HMNoC_cluster_west_1/\router_cluster_0/router_iact/data_out_inferred /out0[6]
      : HMNoC_cluster_west_1/\router_cluster_0/router_iact/data_out_inferred /data3[6]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred__0 /out[6]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred__0 /in0[6]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred /out[6]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred /in0[6]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred__0/out[6]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred__0/in0[6]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred/out[6]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred/in0[6]
      : HMNoC_cluster_west_1/east_data_i_iact0[6]
      : east_data_i_iact_inferred__2/out[6]
      : east_data_i_iact_inferred__2/in0[6]
      : east_data_i_iact_inferred__1/out[6]
      : east_data_i_iact_inferred__1/in0[6]
      : HMNoC_cluster_east_1/west_data_o_iact[6]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred__0/out[6]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred__0/in0[6]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred/out[6]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred/in0[6]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred__0 /out[6]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred__0 /in0[6]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred /out[6]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred /in0[6]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /out0[6]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /data1[6]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred__0/out[6]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred__0/in0[6]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred/out[6]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred/in0[6]
      : HMNoC_cluster_east_0/south_data_i_iact0[6]
      : south_data_i_iact_inferred__2/out[6]
      : south_data_i_iact_inferred__2/in0[6]
      : south_data_i_iact_inferred__1/out[6]
      : south_data_i_iact_inferred__1/in0[6]
      : HMNoC_cluster_east_1/north_data_o_iact[6]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred__0/out[6]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred__0/in0[6]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred/out[6]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred/in0[6]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /out0[6]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /data0[6]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred__0/out[6]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred__0/in0[6]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred/out[6]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred/in0[6]
      : HMNoC_cluster_east_1/north_data_i_iact0[6]
      : north_data_i_iact_inferred__2/out[6]
      : north_data_i_iact_inferred__2/in0[6]
      : north_data_i_iact_inferred__1/out[6]
      : north_data_i_iact_inferred__1/in0[6]
      : HMNoC_cluster_east_0/south_data_o_iact[6]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred__0/out[6]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred__0/in0[6]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred/out[6]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred/in0[6]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /out0[6]
      : HMNoC_cluster_west_0/\router_cluster_0/router_wght/data_out_inferred /data1[5]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred__0/out[5]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred__0/in0[5]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred/out[5]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred/in0[5]
      : HMNoC_cluster_west_0/south_data_i_wght0[5]
      : south_data_i_wght_inferred__0/out[5]
      : south_data_i_wght_inferred__0/in0[5]
      : south_data_i_wght_inferred/out[5]
      : south_data_i_wght_inferred/in0[5]
      : HMNoC_cluster_west_1/north_data_o_wght[5]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred__0/out[5]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred__0/in0[5]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred/out[5]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred/in0[5]
      : HMNoC_cluster_west_1/\router_cluster_0/router_wght/data_out_inferred /out0[5]
      : HMNoC_cluster_west_1/\router_cluster_0/router_wght/data_out_inferred /data0[5]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred__0/out[5]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred__0/in0[5]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred/out[5]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred/in0[5]
      : HMNoC_cluster_west_1/north_data_i_wght0[5]
      : north_data_i_wght_inferred__0/out[5]
      : north_data_i_wght_inferred__0/in0[5]
      : north_data_i_wght_inferred/out[5]
      : north_data_i_wght_inferred/in0[5]
      : HMNoC_cluster_west_0/south_data_o_wght[5]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred__0/out[5]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred__0/in0[5]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred/out[5]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred/in0[5]
      : HMNoC_cluster_west_0/\router_cluster_0/router_wght/data_out_inferred /out0[5]
      : HMNoC_cluster_west_0/\router_cluster_0/router_iact/data_out_inferred /data3[5]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred__0 /out[5]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred__0 /in0[5]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred /out[5]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred /in0[5]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred__0/out[5]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred__0/in0[5]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred/out[5]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred/in0[5]
      : HMNoC_cluster_west_0/east_data_i_iact0[5]
      : east_data_i_iact_inferred__0/out[5]
      : east_data_i_iact_inferred__0/in0[5]
      : east_data_i_iact_inferred/out[5]
      : east_data_i_iact_inferred/in0[5]
      : HMNoC_cluster_east_0/west_data_o_iact[5]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred__0/out[5]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred__0/in0[5]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred/out[5]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred/in0[5]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred__0 /out[5]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred__0 /in0[5]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred /out[5]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred /in0[5]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /out0[5]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /data2[5]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred__0 /out[5]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred__0 /in0[5]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred /out[5]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred /in0[5]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred__0/out[5]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred__0/in0[5]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred/out[5]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred/in0[5]
      : HMNoC_cluster_east_0/west_data_i_iact0[5]
      : west_data_i_iact_inferred__0/out[5]
      : west_data_i_iact_inferred__0/in0[5]
      : west_data_i_iact_inferred/out[5]
      : west_data_i_iact_inferred/in0[5]
      : HMNoC_cluster_west_0/east_data_o_iact[5]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred__0/out[5]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred__0/in0[5]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred/out[5]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred/in0[5]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred__0 /out[5]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred__0 /in0[5]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred /out[5]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred /in0[5]
      : HMNoC_cluster_west_0/\router_cluster_0/router_iact/data_out_inferred /out0[5]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /data2[5]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred__0 /out[5]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred__0 /in0[5]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred /out[5]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred /in0[5]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred__0/out[5]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred__0/in0[5]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred/out[5]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred/in0[5]
      : HMNoC_cluster_east_1/west_data_i_iact[5]
      : east_data_o_iact_inferred__2/out[5]
      : east_data_o_iact_inferred__2/in0[5]
      : east_data_o_iact_inferred__1/out[5]
      : east_data_o_iact_inferred__1/in0[5]
      : HMNoC_cluster_west_1/east_data_o_iact0[5]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred__0/out[5]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred__0/in0[5]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred/out[5]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred/in0[5]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred__0 /out[5]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred__0 /in0[5]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred /out[5]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred /in0[5]
      : HMNoC_cluster_west_1/\router_cluster_0/router_iact/data_out_inferred /out0[5]
      : HMNoC_cluster_west_1/\router_cluster_0/router_iact/data_out_inferred /data3[5]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred__0 /out[5]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred__0 /in0[5]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred /out[5]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred /in0[5]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred__0/out[5]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred__0/in0[5]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred/out[5]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred/in0[5]
      : HMNoC_cluster_west_1/east_data_i_iact0[5]
      : east_data_i_iact_inferred__2/out[5]
      : east_data_i_iact_inferred__2/in0[5]
      : east_data_i_iact_inferred__1/out[5]
      : east_data_i_iact_inferred__1/in0[5]
      : HMNoC_cluster_east_1/west_data_o_iact[5]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred__0/out[5]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred__0/in0[5]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred/out[5]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred/in0[5]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred__0 /out[5]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred__0 /in0[5]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred /out[5]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred /in0[5]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /out0[5]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /data1[5]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred__0/out[5]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred__0/in0[5]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred/out[5]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred/in0[5]
      : HMNoC_cluster_east_0/south_data_i_iact0[5]
      : south_data_i_iact_inferred__2/out[5]
      : south_data_i_iact_inferred__2/in0[5]
      : south_data_i_iact_inferred__1/out[5]
      : south_data_i_iact_inferred__1/in0[5]
      : HMNoC_cluster_east_1/north_data_o_iact[5]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred__0/out[5]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred__0/in0[5]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred/out[5]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred/in0[5]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /out0[5]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /data0[5]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred__0/out[5]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred__0/in0[5]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred/out[5]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred/in0[5]
      : HMNoC_cluster_east_1/north_data_i_iact0[5]
      : north_data_i_iact_inferred__2/out[5]
      : north_data_i_iact_inferred__2/in0[5]
      : north_data_i_iact_inferred__1/out[5]
      : north_data_i_iact_inferred__1/in0[5]
      : HMNoC_cluster_east_0/south_data_o_iact[5]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred__0/out[5]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred__0/in0[5]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred/out[5]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred/in0[5]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /out0[5]
      : HMNoC_cluster_west_0/\router_cluster_0/router_wght/data_out_inferred /data1[4]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred__0/out[4]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred__0/in0[4]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred/out[4]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred/in0[4]
      : HMNoC_cluster_west_0/south_data_i_wght0[4]
      : south_data_i_wght_inferred__0/out[4]
      : south_data_i_wght_inferred__0/in0[4]
      : south_data_i_wght_inferred/out[4]
      : south_data_i_wght_inferred/in0[4]
      : HMNoC_cluster_west_1/north_data_o_wght[4]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred__0/out[4]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred__0/in0[4]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred/out[4]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred/in0[4]
      : HMNoC_cluster_west_1/\router_cluster_0/router_wght/data_out_inferred /out0[4]
      : HMNoC_cluster_west_1/\router_cluster_0/router_wght/data_out_inferred /data0[4]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred__0/out[4]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred__0/in0[4]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred/out[4]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred/in0[4]
      : HMNoC_cluster_west_1/north_data_i_wght0[4]
      : north_data_i_wght_inferred__0/out[4]
      : north_data_i_wght_inferred__0/in0[4]
      : north_data_i_wght_inferred/out[4]
      : north_data_i_wght_inferred/in0[4]
      : HMNoC_cluster_west_0/south_data_o_wght[4]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred__0/out[4]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred__0/in0[4]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred/out[4]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred/in0[4]
      : HMNoC_cluster_west_0/\router_cluster_0/router_wght/data_out_inferred /out0[4]
      : HMNoC_cluster_west_0/\router_cluster_0/router_iact/data_out_inferred /data3[4]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred__0 /out[4]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred__0 /in0[4]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred /out[4]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred /in0[4]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred__0/out[4]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred__0/in0[4]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred/out[4]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred/in0[4]
      : HMNoC_cluster_west_0/east_data_i_iact0[4]
      : east_data_i_iact_inferred__0/out[4]
      : east_data_i_iact_inferred__0/in0[4]
      : east_data_i_iact_inferred/out[4]
      : east_data_i_iact_inferred/in0[4]
      : HMNoC_cluster_east_0/west_data_o_iact[4]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred__0/out[4]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred__0/in0[4]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred/out[4]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred/in0[4]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred__0 /out[4]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred__0 /in0[4]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred /out[4]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred /in0[4]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /out0[4]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /data2[4]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred__0 /out[4]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred__0 /in0[4]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred /out[4]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred /in0[4]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred__0/out[4]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred__0/in0[4]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred/out[4]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred/in0[4]
      : HMNoC_cluster_east_0/west_data_i_iact0[4]
      : west_data_i_iact_inferred__0/out[4]
      : west_data_i_iact_inferred__0/in0[4]
      : west_data_i_iact_inferred/out[4]
      : west_data_i_iact_inferred/in0[4]
      : HMNoC_cluster_west_0/east_data_o_iact[4]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred__0/out[4]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred__0/in0[4]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred/out[4]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred/in0[4]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred__0 /out[4]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred__0 /in0[4]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred /out[4]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred /in0[4]
      : HMNoC_cluster_west_0/\router_cluster_0/router_iact/data_out_inferred /out0[4]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /data2[4]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred__0 /out[4]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred__0 /in0[4]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred /out[4]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred /in0[4]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred__0/out[4]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred__0/in0[4]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred/out[4]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred/in0[4]
      : HMNoC_cluster_east_1/west_data_i_iact[4]
      : east_data_o_iact_inferred__2/out[4]
      : east_data_o_iact_inferred__2/in0[4]
      : east_data_o_iact_inferred__1/out[4]
      : east_data_o_iact_inferred__1/in0[4]
      : HMNoC_cluster_west_1/east_data_o_iact0[4]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred__0/out[4]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred__0/in0[4]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred/out[4]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred/in0[4]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred__0 /out[4]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred__0 /in0[4]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred /out[4]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred /in0[4]
      : HMNoC_cluster_west_1/\router_cluster_0/router_iact/data_out_inferred /out0[4]
      : HMNoC_cluster_west_1/\router_cluster_0/router_iact/data_out_inferred /data3[4]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred__0 /out[4]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred__0 /in0[4]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred /out[4]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred /in0[4]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred__0/out[4]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred__0/in0[4]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred/out[4]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred/in0[4]
      : HMNoC_cluster_west_1/east_data_i_iact0[4]
      : east_data_i_iact_inferred__2/out[4]
      : east_data_i_iact_inferred__2/in0[4]
      : east_data_i_iact_inferred__1/out[4]
      : east_data_i_iact_inferred__1/in0[4]
      : HMNoC_cluster_east_1/west_data_o_iact[4]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred__0/out[4]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred__0/in0[4]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred/out[4]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred/in0[4]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred__0 /out[4]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred__0 /in0[4]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred /out[4]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred /in0[4]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /out0[4]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /data1[4]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred__0/out[4]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred__0/in0[4]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred/out[4]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred/in0[4]
      : HMNoC_cluster_east_0/south_data_i_iact0[4]
      : south_data_i_iact_inferred__2/out[4]
      : south_data_i_iact_inferred__2/in0[4]
      : south_data_i_iact_inferred__1/out[4]
      : south_data_i_iact_inferred__1/in0[4]
      : HMNoC_cluster_east_1/north_data_o_iact[4]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred__0/out[4]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred__0/in0[4]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred/out[4]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred/in0[4]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /out0[4]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /data0[4]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred__0/out[4]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred__0/in0[4]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred/out[4]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred/in0[4]
      : HMNoC_cluster_east_1/north_data_i_iact0[4]
      : north_data_i_iact_inferred__2/out[4]
      : north_data_i_iact_inferred__2/in0[4]
      : north_data_i_iact_inferred__1/out[4]
      : north_data_i_iact_inferred__1/in0[4]
      : HMNoC_cluster_east_0/south_data_o_iact[4]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred__0/out[4]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred__0/in0[4]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred/out[4]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred/in0[4]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /out0[4]
      : HMNoC_cluster_west_0/\router_cluster_0/router_wght/data_out_inferred /data1[3]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred__0/out[3]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred__0/in0[3]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred/out[3]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred/in0[3]
      : HMNoC_cluster_west_0/south_data_i_wght0[3]
      : south_data_i_wght_inferred__0/out[3]
      : south_data_i_wght_inferred__0/in0[3]
      : south_data_i_wght_inferred/out[3]
      : south_data_i_wght_inferred/in0[3]
      : HMNoC_cluster_west_1/north_data_o_wght[3]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred__0/out[3]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred__0/in0[3]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred/out[3]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred/in0[3]
      : HMNoC_cluster_west_1/\router_cluster_0/router_wght/data_out_inferred /out0[3]
      : HMNoC_cluster_west_1/\router_cluster_0/router_wght/data_out_inferred /data0[3]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred__0/out[3]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred__0/in0[3]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred/out[3]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred/in0[3]
      : HMNoC_cluster_west_1/north_data_i_wght0[3]
      : north_data_i_wght_inferred__0/out[3]
      : north_data_i_wght_inferred__0/in0[3]
      : north_data_i_wght_inferred/out[3]
      : north_data_i_wght_inferred/in0[3]
      : HMNoC_cluster_west_0/south_data_o_wght[3]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred__0/out[3]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred__0/in0[3]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred/out[3]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred/in0[3]
      : HMNoC_cluster_west_0/\router_cluster_0/router_wght/data_out_inferred /out0[3]
      : HMNoC_cluster_west_0/\router_cluster_0/router_iact/data_out_inferred /data3[3]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred__0 /out[3]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred__0 /in0[3]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred /out[3]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred /in0[3]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred__0/out[3]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred__0/in0[3]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred/out[3]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred/in0[3]
      : HMNoC_cluster_west_0/east_data_i_iact0[3]
      : east_data_i_iact_inferred__0/out[3]
      : east_data_i_iact_inferred__0/in0[3]
      : east_data_i_iact_inferred/out[3]
      : east_data_i_iact_inferred/in0[3]
      : HMNoC_cluster_east_0/west_data_o_iact[3]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred__0/out[3]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred__0/in0[3]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred/out[3]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred/in0[3]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred__0 /out[3]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred__0 /in0[3]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred /out[3]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred /in0[3]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /out0[3]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /data2[3]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred__0 /out[3]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred__0 /in0[3]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred /out[3]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred /in0[3]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred__0/out[3]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred__0/in0[3]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred/out[3]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred/in0[3]
      : HMNoC_cluster_east_0/west_data_i_iact0[3]
      : west_data_i_iact_inferred__0/out[3]
      : west_data_i_iact_inferred__0/in0[3]
      : west_data_i_iact_inferred/out[3]
      : west_data_i_iact_inferred/in0[3]
      : HMNoC_cluster_west_0/east_data_o_iact[3]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred__0/out[3]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred__0/in0[3]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred/out[3]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred/in0[3]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred__0 /out[3]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred__0 /in0[3]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred /out[3]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred /in0[3]
      : HMNoC_cluster_west_0/\router_cluster_0/router_iact/data_out_inferred /out0[3]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /data2[3]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred__0 /out[3]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred__0 /in0[3]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred /out[3]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred /in0[3]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred__0/out[3]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred__0/in0[3]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred/out[3]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred/in0[3]
      : HMNoC_cluster_east_1/west_data_i_iact[3]
      : east_data_o_iact_inferred__2/out[3]
      : east_data_o_iact_inferred__2/in0[3]
      : east_data_o_iact_inferred__1/out[3]
      : east_data_o_iact_inferred__1/in0[3]
      : HMNoC_cluster_west_1/east_data_o_iact0[3]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred__0/out[3]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred__0/in0[3]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred/out[3]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred/in0[3]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred__0 /out[3]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred__0 /in0[3]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred /out[3]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred /in0[3]
      : HMNoC_cluster_west_1/\router_cluster_0/router_iact/data_out_inferred /out0[3]
      : HMNoC_cluster_west_1/\router_cluster_0/router_iact/data_out_inferred /data3[3]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred__0 /out[3]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred__0 /in0[3]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred /out[3]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred /in0[3]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred__0/out[3]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred__0/in0[3]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred/out[3]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred/in0[3]
      : HMNoC_cluster_west_1/east_data_i_iact0[3]
      : east_data_i_iact_inferred__2/out[3]
      : east_data_i_iact_inferred__2/in0[3]
      : east_data_i_iact_inferred__1/out[3]
      : east_data_i_iact_inferred__1/in0[3]
      : HMNoC_cluster_east_1/west_data_o_iact[3]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred__0/out[3]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred__0/in0[3]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred/out[3]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred/in0[3]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred__0 /out[3]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred__0 /in0[3]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred /out[3]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred /in0[3]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /out0[3]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /data1[3]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred__0/out[3]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred__0/in0[3]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred/out[3]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred/in0[3]
      : HMNoC_cluster_east_0/south_data_i_iact0[3]
      : south_data_i_iact_inferred__2/out[3]
      : south_data_i_iact_inferred__2/in0[3]
      : south_data_i_iact_inferred__1/out[3]
      : south_data_i_iact_inferred__1/in0[3]
      : HMNoC_cluster_east_1/north_data_o_iact[3]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred__0/out[3]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred__0/in0[3]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred/out[3]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred/in0[3]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /out0[3]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /data0[3]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred__0/out[3]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred__0/in0[3]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred/out[3]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred/in0[3]
      : HMNoC_cluster_east_1/north_data_i_iact0[3]
      : north_data_i_iact_inferred__2/out[3]
      : north_data_i_iact_inferred__2/in0[3]
      : north_data_i_iact_inferred__1/out[3]
      : north_data_i_iact_inferred__1/in0[3]
      : HMNoC_cluster_east_0/south_data_o_iact[3]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred__0/out[3]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred__0/in0[3]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred/out[3]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred/in0[3]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /out0[3]
      : HMNoC_cluster_west_0/\router_cluster_0/router_wght/data_out_inferred /data1[2]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred__0/out[2]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred__0/in0[2]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred/out[2]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred/in0[2]
      : HMNoC_cluster_west_0/south_data_i_wght0[2]
      : south_data_i_wght_inferred__0/out[2]
      : south_data_i_wght_inferred__0/in0[2]
      : south_data_i_wght_inferred/out[2]
      : south_data_i_wght_inferred/in0[2]
      : HMNoC_cluster_west_1/north_data_o_wght[2]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred__0/out[2]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred__0/in0[2]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred/out[2]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred/in0[2]
      : HMNoC_cluster_west_1/\router_cluster_0/router_wght/data_out_inferred /out0[2]
      : HMNoC_cluster_west_1/\router_cluster_0/router_wght/data_out_inferred /data0[2]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred__0/out[2]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred__0/in0[2]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred/out[2]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred/in0[2]
      : HMNoC_cluster_west_1/north_data_i_wght0[2]
      : north_data_i_wght_inferred__0/out[2]
      : north_data_i_wght_inferred__0/in0[2]
      : north_data_i_wght_inferred/out[2]
      : north_data_i_wght_inferred/in0[2]
      : HMNoC_cluster_west_0/south_data_o_wght[2]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred__0/out[2]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred__0/in0[2]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred/out[2]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred/in0[2]
      : HMNoC_cluster_west_0/\router_cluster_0/router_wght/data_out_inferred /out0[2]
      : HMNoC_cluster_west_0/\router_cluster_0/router_iact/data_out_inferred /data3[2]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred__0 /out[2]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred__0 /in0[2]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred /out[2]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred /in0[2]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred__0/out[2]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred__0/in0[2]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred/out[2]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred/in0[2]
      : HMNoC_cluster_west_0/east_data_i_iact0[2]
      : east_data_i_iact_inferred__0/out[2]
      : east_data_i_iact_inferred__0/in0[2]
      : east_data_i_iact_inferred/out[2]
      : east_data_i_iact_inferred/in0[2]
      : HMNoC_cluster_east_0/west_data_o_iact[2]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred__0/out[2]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred__0/in0[2]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred/out[2]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred/in0[2]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred__0 /out[2]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred__0 /in0[2]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred /out[2]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred /in0[2]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /out0[2]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /data2[2]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred__0 /out[2]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred__0 /in0[2]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred /out[2]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred /in0[2]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred__0/out[2]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred__0/in0[2]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred/out[2]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred/in0[2]
      : HMNoC_cluster_east_0/west_data_i_iact0[2]
      : west_data_i_iact_inferred__0/out[2]
      : west_data_i_iact_inferred__0/in0[2]
      : west_data_i_iact_inferred/out[2]
      : west_data_i_iact_inferred/in0[2]
      : HMNoC_cluster_west_0/east_data_o_iact[2]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred__0/out[2]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred__0/in0[2]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred/out[2]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred/in0[2]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred__0 /out[2]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred__0 /in0[2]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred /out[2]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred /in0[2]
      : HMNoC_cluster_west_0/\router_cluster_0/router_iact/data_out_inferred /out0[2]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /data2[2]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred__0 /out[2]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred__0 /in0[2]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred /out[2]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred /in0[2]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred__0/out[2]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred__0/in0[2]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred/out[2]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred/in0[2]
      : HMNoC_cluster_east_1/west_data_i_iact[2]
      : east_data_o_iact_inferred__2/out[2]
      : east_data_o_iact_inferred__2/in0[2]
      : east_data_o_iact_inferred__1/out[2]
      : east_data_o_iact_inferred__1/in0[2]
      : HMNoC_cluster_west_1/east_data_o_iact0[2]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred__0/out[2]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred__0/in0[2]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred/out[2]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred/in0[2]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred__0 /out[2]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred__0 /in0[2]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred /out[2]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred /in0[2]
      : HMNoC_cluster_west_1/\router_cluster_0/router_iact/data_out_inferred /out0[2]
      : HMNoC_cluster_west_1/\router_cluster_0/router_iact/data_out_inferred /data3[2]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred__0 /out[2]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred__0 /in0[2]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred /out[2]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred /in0[2]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred__0/out[2]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred__0/in0[2]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred/out[2]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred/in0[2]
      : HMNoC_cluster_west_1/east_data_i_iact0[2]
      : east_data_i_iact_inferred__2/out[2]
      : east_data_i_iact_inferred__2/in0[2]
      : east_data_i_iact_inferred__1/out[2]
      : east_data_i_iact_inferred__1/in0[2]
      : HMNoC_cluster_east_1/west_data_o_iact[2]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred__0/out[2]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred__0/in0[2]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred/out[2]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred/in0[2]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred__0 /out[2]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred__0 /in0[2]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred /out[2]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred /in0[2]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /out0[2]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /data1[2]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred__0/out[2]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred__0/in0[2]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred/out[2]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred/in0[2]
      : HMNoC_cluster_east_0/south_data_i_iact0[2]
      : south_data_i_iact_inferred__2/out[2]
      : south_data_i_iact_inferred__2/in0[2]
      : south_data_i_iact_inferred__1/out[2]
      : south_data_i_iact_inferred__1/in0[2]
      : HMNoC_cluster_east_1/north_data_o_iact[2]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred__0/out[2]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred__0/in0[2]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred/out[2]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred/in0[2]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /out0[2]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /data0[2]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred__0/out[2]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred__0/in0[2]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred/out[2]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred/in0[2]
      : HMNoC_cluster_east_1/north_data_i_iact0[2]
      : north_data_i_iact_inferred__2/out[2]
      : north_data_i_iact_inferred__2/in0[2]
      : north_data_i_iact_inferred__1/out[2]
      : north_data_i_iact_inferred__1/in0[2]
      : HMNoC_cluster_east_0/south_data_o_iact[2]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred__0/out[2]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred__0/in0[2]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred/out[2]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred/in0[2]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /out0[2]
      : HMNoC_cluster_west_0/\router_cluster_0/router_wght/data_out_inferred /data1[1]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred__0/out[1]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred__0/in0[1]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred/out[1]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred/in0[1]
      : HMNoC_cluster_west_0/south_data_i_wght0[1]
      : south_data_i_wght_inferred__0/out[1]
      : south_data_i_wght_inferred__0/in0[1]
      : south_data_i_wght_inferred/out[1]
      : south_data_i_wght_inferred/in0[1]
      : HMNoC_cluster_west_1/north_data_o_wght[1]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred__0/out[1]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred__0/in0[1]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred/out[1]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred/in0[1]
      : HMNoC_cluster_west_1/\router_cluster_0/router_wght/data_out_inferred /out0[1]
      : HMNoC_cluster_west_1/\router_cluster_0/router_wght/data_out_inferred /data0[1]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred__0/out[1]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred__0/in0[1]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred/out[1]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred/in0[1]
      : HMNoC_cluster_west_1/north_data_i_wght0[1]
      : north_data_i_wght_inferred__0/out[1]
      : north_data_i_wght_inferred__0/in0[1]
      : north_data_i_wght_inferred/out[1]
      : north_data_i_wght_inferred/in0[1]
      : HMNoC_cluster_west_0/south_data_o_wght[1]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred__0/out[1]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred__0/in0[1]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred/out[1]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred/in0[1]
      : HMNoC_cluster_west_0/\router_cluster_0/router_wght/data_out_inferred /out0[1]
      : HMNoC_cluster_west_0/\router_cluster_0/router_iact/data_out_inferred /data3[1]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred__0 /out[1]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred__0 /in0[1]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred /out[1]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred /in0[1]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred__0/out[1]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred__0/in0[1]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred/out[1]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred/in0[1]
      : HMNoC_cluster_west_0/east_data_i_iact0[1]
      : east_data_i_iact_inferred__0/out[1]
      : east_data_i_iact_inferred__0/in0[1]
      : east_data_i_iact_inferred/out[1]
      : east_data_i_iact_inferred/in0[1]
      : HMNoC_cluster_east_0/west_data_o_iact[1]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred__0/out[1]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred__0/in0[1]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred/out[1]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred/in0[1]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred__0 /out[1]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred__0 /in0[1]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred /out[1]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred /in0[1]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /out0[1]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /data2[1]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred__0 /out[1]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred__0 /in0[1]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred /out[1]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred /in0[1]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred__0/out[1]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred__0/in0[1]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred/out[1]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred/in0[1]
      : HMNoC_cluster_east_0/west_data_i_iact0[1]
      : west_data_i_iact_inferred__0/out[1]
      : west_data_i_iact_inferred__0/in0[1]
      : west_data_i_iact_inferred/out[1]
      : west_data_i_iact_inferred/in0[1]
      : HMNoC_cluster_west_0/east_data_o_iact[1]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred__0/out[1]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred__0/in0[1]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred/out[1]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred/in0[1]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred__0 /out[1]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred__0 /in0[1]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred /out[1]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred /in0[1]
      : HMNoC_cluster_west_0/\router_cluster_0/router_iact/data_out_inferred /out0[1]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /data2[1]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred__0 /out[1]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred__0 /in0[1]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred /out[1]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred /in0[1]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred__0/out[1]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred__0/in0[1]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred/out[1]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred/in0[1]
      : HMNoC_cluster_east_1/west_data_i_iact[1]
      : east_data_o_iact_inferred__2/out[1]
      : east_data_o_iact_inferred__2/in0[1]
      : east_data_o_iact_inferred__1/out[1]
      : east_data_o_iact_inferred__1/in0[1]
      : HMNoC_cluster_west_1/east_data_o_iact0[1]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred__0/out[1]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred__0/in0[1]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred/out[1]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred/in0[1]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred__0 /out[1]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred__0 /in0[1]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred /out[1]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred /in0[1]
      : HMNoC_cluster_west_1/\router_cluster_0/router_iact/data_out_inferred /out0[1]
      : HMNoC_cluster_west_1/\router_cluster_0/router_iact/data_out_inferred /data3[1]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred__0 /out[1]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred__0 /in0[1]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred /out[1]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred /in0[1]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred__0/out[1]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred__0/in0[1]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred/out[1]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred/in0[1]
      : HMNoC_cluster_west_1/east_data_i_iact0[1]
      : east_data_i_iact_inferred__2/out[1]
      : east_data_i_iact_inferred__2/in0[1]
      : east_data_i_iact_inferred__1/out[1]
      : east_data_i_iact_inferred__1/in0[1]
      : HMNoC_cluster_east_1/west_data_o_iact[1]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred__0/out[1]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred__0/in0[1]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred/out[1]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred/in0[1]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred__0 /out[1]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred__0 /in0[1]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred /out[1]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred /in0[1]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /out0[1]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /data1[1]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred__0/out[1]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred__0/in0[1]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred/out[1]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred/in0[1]
      : HMNoC_cluster_east_0/south_data_i_iact0[1]
      : south_data_i_iact_inferred__2/out[1]
      : south_data_i_iact_inferred__2/in0[1]
      : south_data_i_iact_inferred__1/out[1]
      : south_data_i_iact_inferred__1/in0[1]
      : HMNoC_cluster_east_1/north_data_o_iact[1]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred__0/out[1]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred__0/in0[1]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred/out[1]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred/in0[1]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /out0[1]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /data0[1]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred__0/out[1]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred__0/in0[1]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred/out[1]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred/in0[1]
      : HMNoC_cluster_east_1/north_data_i_iact0[1]
      : north_data_i_iact_inferred__2/out[1]
      : north_data_i_iact_inferred__2/in0[1]
      : north_data_i_iact_inferred__1/out[1]
      : north_data_i_iact_inferred__1/in0[1]
      : HMNoC_cluster_east_0/south_data_o_iact[1]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred__0/out[1]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred__0/in0[1]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred/out[1]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred/in0[1]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /out0[1]
      : HMNoC_cluster_west_0/\router_cluster_0/router_wght/data_out_inferred /data1[0]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred__0/out[0]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred__0/in0[0]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred/out[0]
      : HMNoC_cluster_west_0/south_data_i_wght_inferred/in0[0]
      : HMNoC_cluster_west_0/south_data_i_wght0[0]
      : south_data_i_wght_inferred__0/out[0]
      : south_data_i_wght_inferred__0/in0[0]
      : south_data_i_wght_inferred/out[0]
      : south_data_i_wght_inferred/in0[0]
      : HMNoC_cluster_west_1/north_data_o_wght[0]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred__0/out[0]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred__0/in0[0]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred/out[0]
      : HMNoC_cluster_west_1/north_data_o_wght_inferred/in0[0]
      : HMNoC_cluster_west_1/\router_cluster_0/router_wght/data_out_inferred /out0[0]
      : HMNoC_cluster_west_1/\router_cluster_0/router_wght/data_out_inferred /data0[0]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred__0/out[0]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred__0/in0[0]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred/out[0]
      : HMNoC_cluster_west_1/north_data_i_wght_inferred/in0[0]
      : HMNoC_cluster_west_1/north_data_i_wght0[0]
      : north_data_i_wght_inferred__0/out[0]
      : north_data_i_wght_inferred__0/in0[0]
      : north_data_i_wght_inferred/out[0]
      : north_data_i_wght_inferred/in0[0]
      : HMNoC_cluster_west_0/south_data_o_wght[0]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred__0/out[0]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred__0/in0[0]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred/out[0]
      : HMNoC_cluster_west_0/south_data_o_wght_inferred/in0[0]
      : HMNoC_cluster_west_0/\router_cluster_0/router_wght/data_out_inferred /out0[0]
      : HMNoC_cluster_west_0/\router_cluster_0/router_iact/data_out_inferred /data3[0]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred__0 /out[0]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred__0 /in0[0]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred /out[0]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_i_iact_inferred /in0[0]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred__0/out[0]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred__0/in0[0]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred/out[0]
      : HMNoC_cluster_west_0/east_data_i_iact_inferred/in0[0]
      : HMNoC_cluster_west_0/east_data_i_iact0[0]
      : east_data_i_iact_inferred__0/out[0]
      : east_data_i_iact_inferred__0/in0[0]
      : east_data_i_iact_inferred/out[0]
      : east_data_i_iact_inferred/in0[0]
      : HMNoC_cluster_east_0/west_data_o_iact[0]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred__0/out[0]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred__0/in0[0]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred/out[0]
      : HMNoC_cluster_east_0/west_data_o_iact_inferred/in0[0]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred__0 /out[0]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred__0 /in0[0]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred /out[0]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_o_iact_inferred /in0[0]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /out0[0]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /data2[0]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred__0 /out[0]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred__0 /in0[0]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred /out[0]
      : HMNoC_cluster_east_0/\router_cluster_0/west_data_i_iact_inferred /in0[0]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred__0/out[0]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred__0/in0[0]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred/out[0]
      : HMNoC_cluster_east_0/west_data_i_iact_inferred/in0[0]
      : HMNoC_cluster_east_0/west_data_i_iact0[0]
      : west_data_i_iact_inferred__0/out[0]
      : west_data_i_iact_inferred__0/in0[0]
      : west_data_i_iact_inferred/out[0]
      : west_data_i_iact_inferred/in0[0]
      : HMNoC_cluster_west_0/east_data_o_iact[0]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred__0/out[0]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred__0/in0[0]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred/out[0]
      : HMNoC_cluster_west_0/east_data_o_iact_inferred/in0[0]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred__0 /out[0]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred__0 /in0[0]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred /out[0]
      : HMNoC_cluster_west_0/\router_cluster_0/east_data_o_iact_inferred /in0[0]
      : HMNoC_cluster_west_0/\router_cluster_0/router_iact/data_out_inferred /out0[0]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /data2[0]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred__0 /out[0]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred__0 /in0[0]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred /out[0]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_i_iact_inferred /in0[0]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred__0/out[0]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred__0/in0[0]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred/out[0]
      : HMNoC_cluster_east_1/west_data_i_iact_inferred/in0[0]
      : HMNoC_cluster_east_1/west_data_i_iact[0]
      : east_data_o_iact_inferred__2/out[0]
      : east_data_o_iact_inferred__2/in0[0]
      : east_data_o_iact_inferred__1/out[0]
      : east_data_o_iact_inferred__1/in0[0]
      : HMNoC_cluster_west_1/east_data_o_iact0[0]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred__0/out[0]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred__0/in0[0]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred/out[0]
      : HMNoC_cluster_west_1/east_data_o_iact_inferred/in0[0]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred__0 /out[0]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred__0 /in0[0]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred /out[0]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_o_iact_inferred /in0[0]
      : HMNoC_cluster_west_1/\router_cluster_0/router_iact/data_out_inferred /out0[0]
      : HMNoC_cluster_west_1/\router_cluster_0/router_iact/data_out_inferred /data3[0]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred__0 /out[0]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred__0 /in0[0]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred /out[0]
      : HMNoC_cluster_west_1/\router_cluster_0/east_data_i_iact_inferred /in0[0]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred__0/out[0]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred__0/in0[0]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred/out[0]
      : HMNoC_cluster_west_1/east_data_i_iact_inferred/in0[0]
      : HMNoC_cluster_west_1/east_data_i_iact0[0]
      : east_data_i_iact_inferred__2/out[0]
      : east_data_i_iact_inferred__2/in0[0]
      : east_data_i_iact_inferred__1/out[0]
      : east_data_i_iact_inferred__1/in0[0]
      : HMNoC_cluster_east_1/west_data_o_iact[0]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred__0/out[0]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred__0/in0[0]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred/out[0]
      : HMNoC_cluster_east_1/west_data_o_iact_inferred/in0[0]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred__0 /out[0]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred__0 /in0[0]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred /out[0]
      : HMNoC_cluster_east_1/\router_cluster_0/west_data_o_iact_inferred /in0[0]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /out0[0]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /data1[0]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred__0/out[0]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred__0/in0[0]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred/out[0]
      : HMNoC_cluster_east_0/south_data_i_iact_inferred/in0[0]
      : HMNoC_cluster_east_0/south_data_i_iact0[0]
      : south_data_i_iact_inferred__2/out[0]
      : south_data_i_iact_inferred__2/in0[0]
      : south_data_i_iact_inferred__1/out[0]
      : south_data_i_iact_inferred__1/in0[0]
      : HMNoC_cluster_east_1/north_data_o_iact[0]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred__0/out[0]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred__0/in0[0]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred/out[0]
      : HMNoC_cluster_east_1/north_data_o_iact_inferred/in0[0]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /out0[0]
      : HMNoC_cluster_east_1/\router_cluster_0/router_iact/data_out_inferred /data0[0]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred__0/out[0]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred__0/in0[0]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred/out[0]
      : HMNoC_cluster_east_1/north_data_i_iact_inferred/in0[0]
      : HMNoC_cluster_east_1/north_data_i_iact0[0]
      : north_data_i_iact_inferred__2/out[0]
      : north_data_i_iact_inferred__2/in0[0]
      : north_data_i_iact_inferred__1/out[0]
      : north_data_i_iact_inferred__1/in0[0]
      : HMNoC_cluster_east_0/south_data_o_iact[0]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred__0/out[0]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred__0/in0[0]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred/out[0]
      : HMNoC_cluster_east_0/south_data_o_iact_inferred/in0[0]
      : HMNoC_cluster_east_0/\router_cluster_0/router_iact/data_out_inferred /out0[0]
      : HMNoC_cluster_east_1/\router_cluster_0/router_wght/data_out_inferred /data0[1]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred__0/out[1]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred__0/in0[1]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred/out[1]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred/in0[1]
      : HMNoC_cluster_east_1/north_data_i_wght0[1]
      : north_data_i_wght_inferred__2/out[1]
      : north_data_i_wght_inferred__2/in0[1]
      : north_data_i_wght_inferred__1/out[1]
      : north_data_i_wght_inferred__1/in0[1]
      : HMNoC_cluster_east_0/south_data_o_wght[1]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred__0/out[1]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred__0/in0[1]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred/out[1]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred/in0[1]
      : HMNoC_cluster_east_0/\router_cluster_0/router_wght/data_out_inferred /out0[1]
      : HMNoC_cluster_east_0/\router_cluster_0/router_wght/data_out_inferred /data1[1]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred__0/out[1]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred__0/in0[1]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred/out[1]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred/in0[1]
      : HMNoC_cluster_east_0/south_data_i_wght0[1]
      : south_data_i_wght_inferred__2/out[1]
      : south_data_i_wght_inferred__2/in0[1]
      : south_data_i_wght_inferred__1/out[1]
      : south_data_i_wght_inferred__1/in0[1]
      : HMNoC_cluster_east_1/north_data_o_wght[1]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred__0/out[1]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred__0/in0[1]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred/out[1]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred/in0[1]
      : HMNoC_cluster_east_1/\router_cluster_0/router_wght/data_out_inferred /out0[1]
      : HMNoC_cluster_east_1/\router_cluster_0/router_wght/data_out_inferred /data0[3]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred__0/out[3]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred__0/in0[3]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred/out[3]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred/in0[3]
      : HMNoC_cluster_east_1/north_data_i_wght0[3]
      : north_data_i_wght_inferred__2/out[3]
      : north_data_i_wght_inferred__2/in0[3]
      : north_data_i_wght_inferred__1/out[3]
      : north_data_i_wght_inferred__1/in0[3]
      : HMNoC_cluster_east_0/south_data_o_wght[3]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred__0/out[3]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred__0/in0[3]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred/out[3]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred/in0[3]
      : HMNoC_cluster_east_0/\router_cluster_0/router_wght/data_out_inferred /out0[3]
      : HMNoC_cluster_east_0/\router_cluster_0/router_wght/data_out_inferred /data1[3]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred__0/out[3]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred__0/in0[3]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred/out[3]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred/in0[3]
      : HMNoC_cluster_east_0/south_data_i_wght0[3]
      : south_data_i_wght_inferred__2/out[3]
      : south_data_i_wght_inferred__2/in0[3]
      : south_data_i_wght_inferred__1/out[3]
      : south_data_i_wght_inferred__1/in0[3]
      : HMNoC_cluster_east_1/north_data_o_wght[3]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred__0/out[3]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred__0/in0[3]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred/out[3]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred/in0[3]
      : HMNoC_cluster_east_1/\router_cluster_0/router_wght/data_out_inferred /out0[3]
      : HMNoC_cluster_east_1/\router_cluster_0/router_wght/data_out_inferred /data0[7]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred__0/out[7]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred__0/in0[7]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred/out[7]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred/in0[7]
      : HMNoC_cluster_east_1/north_data_i_wght0[7]
      : north_data_i_wght_inferred__2/out[7]
      : north_data_i_wght_inferred__2/in0[7]
      : north_data_i_wght_inferred__1/out[7]
      : north_data_i_wght_inferred__1/in0[7]
      : HMNoC_cluster_east_0/south_data_o_wght[7]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred__0/out[7]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred__0/in0[7]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred/out[7]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred/in0[7]
      : HMNoC_cluster_east_0/\router_cluster_0/router_wght/data_out_inferred /out0[7]
      : HMNoC_cluster_east_0/\router_cluster_0/router_wght/data_out_inferred /data1[7]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred__0/out[7]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred__0/in0[7]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred/out[7]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred/in0[7]
      : HMNoC_cluster_east_0/south_data_i_wght0[7]
      : south_data_i_wght_inferred__2/out[7]
      : south_data_i_wght_inferred__2/in0[7]
      : south_data_i_wght_inferred__1/out[7]
      : south_data_i_wght_inferred__1/in0[7]
      : HMNoC_cluster_east_1/north_data_o_wght[7]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred__0/out[7]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred__0/in0[7]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred/out[7]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred/in0[7]
      : HMNoC_cluster_east_1/\router_cluster_0/router_wght/data_out_inferred /out0[7]
      : HMNoC_cluster_east_1/\router_cluster_0/router_wght/data_out_inferred /data0[11]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred__0/out[11]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred__0/in0[11]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred/out[11]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred/in0[11]
      : HMNoC_cluster_east_1/north_data_i_wght0[11]
      : north_data_i_wght_inferred__2/out[11]
      : north_data_i_wght_inferred__2/in0[11]
      : north_data_i_wght_inferred__1/out[11]
      : north_data_i_wght_inferred__1/in0[11]
      : HMNoC_cluster_east_0/south_data_o_wght[11]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred__0/out[11]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred__0/in0[11]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred/out[11]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred/in0[11]
      : HMNoC_cluster_east_0/\router_cluster_0/router_wght/data_out_inferred /out0[11]
      : HMNoC_cluster_east_0/\router_cluster_0/router_wght/data_out_inferred /data1[11]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred__0/out[11]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred__0/in0[11]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred/out[11]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred/in0[11]
      : HMNoC_cluster_east_0/south_data_i_wght0[11]
      : south_data_i_wght_inferred__2/out[11]
      : south_data_i_wght_inferred__2/in0[11]
      : south_data_i_wght_inferred__1/out[11]
      : south_data_i_wght_inferred__1/in0[11]
      : HMNoC_cluster_east_1/north_data_o_wght[11]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred__0/out[11]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred__0/in0[11]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred/out[11]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred/in0[11]
      : HMNoC_cluster_east_1/\router_cluster_0/router_wght/data_out_inferred /out0[11]
      : HMNoC_cluster_east_1/\router_cluster_0/router_wght/data_out_inferred /data0[12]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred__0/out[12]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred__0/in0[12]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred/out[12]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred/in0[12]
      : HMNoC_cluster_east_1/north_data_i_wght0[12]
      : north_data_i_wght_inferred__2/out[12]
      : north_data_i_wght_inferred__2/in0[12]
      : north_data_i_wght_inferred__1/out[12]
      : north_data_i_wght_inferred__1/in0[12]
      : HMNoC_cluster_east_0/south_data_o_wght[12]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred__0/out[12]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred__0/in0[12]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred/out[12]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred/in0[12]
      : HMNoC_cluster_east_0/\router_cluster_0/router_wght/data_out_inferred /out0[12]
      : HMNoC_cluster_east_0/\router_cluster_0/router_wght/data_out_inferred /data1[12]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred__0/out[12]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred__0/in0[12]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred/out[12]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred/in0[12]
      : HMNoC_cluster_east_0/south_data_i_wght0[12]
      : south_data_i_wght_inferred__2/out[12]
      : south_data_i_wght_inferred__2/in0[12]
      : south_data_i_wght_inferred__1/out[12]
      : south_data_i_wght_inferred__1/in0[12]
      : HMNoC_cluster_east_1/north_data_o_wght[12]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred__0/out[12]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred__0/in0[12]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred/out[12]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred/in0[12]
      : HMNoC_cluster_east_1/\router_cluster_0/router_wght/data_out_inferred /out0[12]
      : HMNoC_cluster_east_1/\router_cluster_0/router_wght/data_out_inferred /data0[14]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred__0/out[14]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred__0/in0[14]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred/out[14]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred/in0[14]
      : HMNoC_cluster_east_1/north_data_i_wght0[14]
      : north_data_i_wght_inferred__2/out[14]
      : north_data_i_wght_inferred__2/in0[14]
      : north_data_i_wght_inferred__1/out[14]
      : north_data_i_wght_inferred__1/in0[14]
      : HMNoC_cluster_east_0/south_data_o_wght[14]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred__0/out[14]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred__0/in0[14]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred/out[14]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred/in0[14]
      : HMNoC_cluster_east_0/\router_cluster_0/router_wght/data_out_inferred /out0[14]
      : HMNoC_cluster_east_0/\router_cluster_0/router_wght/data_out_inferred /data1[14]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred__0/out[14]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred__0/in0[14]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred/out[14]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred/in0[14]
      : HMNoC_cluster_east_0/south_data_i_wght0[14]
      : south_data_i_wght_inferred__2/out[14]
      : south_data_i_wght_inferred__2/in0[14]
      : south_data_i_wght_inferred__1/out[14]
      : south_data_i_wght_inferred__1/in0[14]
      : HMNoC_cluster_east_1/north_data_o_wght[14]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred__0/out[14]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred__0/in0[14]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred/out[14]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred/in0[14]
      : HMNoC_cluster_east_1/\router_cluster_0/router_wght/data_out_inferred /out0[14]
      : HMNoC_cluster_east_1/\router_cluster_0/router_wght/data_out_inferred /data0[15]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred__0/out[15]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred__0/in0[15]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred/out[15]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred/in0[15]
      : HMNoC_cluster_east_1/north_data_i_wght0[15]
      : north_data_i_wght_inferred__2/out[15]
      : north_data_i_wght_inferred__2/in0[15]
      : north_data_i_wght_inferred__1/out[15]
      : north_data_i_wght_inferred__1/in0[15]
      : HMNoC_cluster_east_0/south_data_o_wght[15]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred__0/out[15]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred__0/in0[15]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred/out[15]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred/in0[15]
      : HMNoC_cluster_east_0/\router_cluster_0/router_wght/data_out_inferred /out0[15]
      : HMNoC_cluster_east_0/\router_cluster_0/router_wght/data_out_inferred /data1[15]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred__0/out[15]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred__0/in0[15]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred/out[15]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred/in0[15]
      : HMNoC_cluster_east_0/south_data_i_wght0[15]
      : south_data_i_wght_inferred__2/out[15]
      : south_data_i_wght_inferred__2/in0[15]
      : south_data_i_wght_inferred__1/out[15]
      : south_data_i_wght_inferred__1/in0[15]
      : HMNoC_cluster_east_1/north_data_o_wght[15]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred__0/out[15]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred__0/in0[15]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred/out[15]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred/in0[15]
      : HMNoC_cluster_east_1/\router_cluster_0/router_wght/data_out_inferred /out0[15]
      : HMNoC_cluster_east_1/\router_cluster_0/router_wght/data_out_inferred /data0[0]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred__0/out[0]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred__0/in0[0]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred/out[0]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred/in0[0]
      : HMNoC_cluster_east_1/north_data_i_wght0[0]
      : north_data_i_wght_inferred__2/out[0]
      : north_data_i_wght_inferred__2/in0[0]
      : north_data_i_wght_inferred__1/out[0]
      : north_data_i_wght_inferred__1/in0[0]
      : HMNoC_cluster_east_0/south_data_o_wght[0]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred__0/out[0]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred__0/in0[0]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred/out[0]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred/in0[0]
      : HMNoC_cluster_east_0/\router_cluster_0/router_wght/data_out_inferred /out0[0]
      : HMNoC_cluster_east_0/\router_cluster_0/router_wght/data_out_inferred /data1[0]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred__0/out[0]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred__0/in0[0]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred/out[0]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred/in0[0]
      : HMNoC_cluster_east_0/south_data_i_wght0[0]
      : south_data_i_wght_inferred__2/out[0]
      : south_data_i_wght_inferred__2/in0[0]
      : south_data_i_wght_inferred__1/out[0]
      : south_data_i_wght_inferred__1/in0[0]
      : HMNoC_cluster_east_1/north_data_o_wght[0]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred__0/out[0]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred__0/in0[0]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred/out[0]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred/in0[0]
      : HMNoC_cluster_east_1/\router_cluster_0/router_wght/data_out_inferred /out0[0]
      : HMNoC_cluster_east_1/\router_cluster_0/router_wght/data_out_inferred /data0[2]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred__0/out[2]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred__0/in0[2]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred/out[2]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred/in0[2]
      : HMNoC_cluster_east_1/north_data_i_wght0[2]
      : north_data_i_wght_inferred__2/out[2]
      : north_data_i_wght_inferred__2/in0[2]
      : north_data_i_wght_inferred__1/out[2]
      : north_data_i_wght_inferred__1/in0[2]
      : HMNoC_cluster_east_0/south_data_o_wght[2]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred__0/out[2]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred__0/in0[2]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred/out[2]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred/in0[2]
      : HMNoC_cluster_east_0/\router_cluster_0/router_wght/data_out_inferred /out0[2]
      : HMNoC_cluster_east_0/\router_cluster_0/router_wght/data_out_inferred /data1[2]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred__0/out[2]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred__0/in0[2]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred/out[2]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred/in0[2]
      : HMNoC_cluster_east_0/south_data_i_wght0[2]
      : south_data_i_wght_inferred__2/out[2]
      : south_data_i_wght_inferred__2/in0[2]
      : south_data_i_wght_inferred__1/out[2]
      : south_data_i_wght_inferred__1/in0[2]
      : HMNoC_cluster_east_1/north_data_o_wght[2]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred__0/out[2]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred__0/in0[2]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred/out[2]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred/in0[2]
      : HMNoC_cluster_east_1/\router_cluster_0/router_wght/data_out_inferred /out0[2]
      : HMNoC_cluster_east_1/\router_cluster_0/router_wght/data_out_inferred /data0[4]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred__0/out[4]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred__0/in0[4]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred/out[4]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred/in0[4]
      : HMNoC_cluster_east_1/north_data_i_wght0[4]
      : north_data_i_wght_inferred__2/out[4]
      : north_data_i_wght_inferred__2/in0[4]
      : north_data_i_wght_inferred__1/out[4]
      : north_data_i_wght_inferred__1/in0[4]
      : HMNoC_cluster_east_0/south_data_o_wght[4]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred__0/out[4]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred__0/in0[4]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred/out[4]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred/in0[4]
      : HMNoC_cluster_east_0/\router_cluster_0/router_wght/data_out_inferred /out0[4]
      : HMNoC_cluster_east_0/\router_cluster_0/router_wght/data_out_inferred /data1[4]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred__0/out[4]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred__0/in0[4]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred/out[4]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred/in0[4]
      : HMNoC_cluster_east_0/south_data_i_wght0[4]
      : south_data_i_wght_inferred__2/out[4]
      : south_data_i_wght_inferred__2/in0[4]
      : south_data_i_wght_inferred__1/out[4]
      : south_data_i_wght_inferred__1/in0[4]
      : HMNoC_cluster_east_1/north_data_o_wght[4]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred__0/out[4]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred__0/in0[4]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred/out[4]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred/in0[4]
      : HMNoC_cluster_east_1/\router_cluster_0/router_wght/data_out_inferred /out0[4]
      : HMNoC_cluster_east_1/\router_cluster_0/router_wght/data_out_inferred /data0[5]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred__0/out[5]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred__0/in0[5]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred/out[5]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred/in0[5]
      : HMNoC_cluster_east_1/north_data_i_wght0[5]
      : north_data_i_wght_inferred__2/out[5]
      : north_data_i_wght_inferred__2/in0[5]
      : north_data_i_wght_inferred__1/out[5]
      : north_data_i_wght_inferred__1/in0[5]
      : HMNoC_cluster_east_0/south_data_o_wght[5]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred__0/out[5]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred__0/in0[5]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred/out[5]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred/in0[5]
      : HMNoC_cluster_east_0/\router_cluster_0/router_wght/data_out_inferred /out0[5]
      : HMNoC_cluster_east_0/\router_cluster_0/router_wght/data_out_inferred /data1[5]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred__0/out[5]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred__0/in0[5]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred/out[5]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred/in0[5]
      : HMNoC_cluster_east_0/south_data_i_wght0[5]
      : south_data_i_wght_inferred__2/out[5]
      : south_data_i_wght_inferred__2/in0[5]
      : south_data_i_wght_inferred__1/out[5]
      : south_data_i_wght_inferred__1/in0[5]
      : HMNoC_cluster_east_1/north_data_o_wght[5]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred__0/out[5]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred__0/in0[5]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred/out[5]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred/in0[5]
      : HMNoC_cluster_east_1/\router_cluster_0/router_wght/data_out_inferred /out0[5]
      : HMNoC_cluster_east_1/\router_cluster_0/router_wght/data_out_inferred /data0[6]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred__0/out[6]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred__0/in0[6]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred/out[6]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred/in0[6]
      : HMNoC_cluster_east_1/north_data_i_wght0[6]
      : north_data_i_wght_inferred__2/out[6]
      : north_data_i_wght_inferred__2/in0[6]
      : north_data_i_wght_inferred__1/out[6]
      : north_data_i_wght_inferred__1/in0[6]
      : HMNoC_cluster_east_0/south_data_o_wght[6]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred__0/out[6]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred__0/in0[6]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred/out[6]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred/in0[6]
      : HMNoC_cluster_east_0/\router_cluster_0/router_wght/data_out_inferred /out0[6]
      : HMNoC_cluster_east_0/\router_cluster_0/router_wght/data_out_inferred /data1[6]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred__0/out[6]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred__0/in0[6]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred/out[6]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred/in0[6]
      : HMNoC_cluster_east_0/south_data_i_wght0[6]
      : south_data_i_wght_inferred__2/out[6]
      : south_data_i_wght_inferred__2/in0[6]
      : south_data_i_wght_inferred__1/out[6]
      : south_data_i_wght_inferred__1/in0[6]
      : HMNoC_cluster_east_1/north_data_o_wght[6]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred__0/out[6]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred__0/in0[6]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred/out[6]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred/in0[6]
      : HMNoC_cluster_east_1/\router_cluster_0/router_wght/data_out_inferred /out0[6]
      : HMNoC_cluster_east_1/\router_cluster_0/router_wght/data_out_inferred /data0[8]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred__0/out[8]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred__0/in0[8]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred/out[8]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred/in0[8]
      : HMNoC_cluster_east_1/north_data_i_wght0[8]
      : north_data_i_wght_inferred__2/out[8]
      : north_data_i_wght_inferred__2/in0[8]
      : north_data_i_wght_inferred__1/out[8]
      : north_data_i_wght_inferred__1/in0[8]
      : HMNoC_cluster_east_0/south_data_o_wght[8]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred__0/out[8]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred__0/in0[8]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred/out[8]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred/in0[8]
      : HMNoC_cluster_east_0/\router_cluster_0/router_wght/data_out_inferred /out0[8]
      : HMNoC_cluster_east_0/\router_cluster_0/router_wght/data_out_inferred /data1[8]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred__0/out[8]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred__0/in0[8]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred/out[8]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred/in0[8]
      : HMNoC_cluster_east_0/south_data_i_wght0[8]
      : south_data_i_wght_inferred__2/out[8]
      : south_data_i_wght_inferred__2/in0[8]
      : south_data_i_wght_inferred__1/out[8]
      : south_data_i_wght_inferred__1/in0[8]
      : HMNoC_cluster_east_1/north_data_o_wght[8]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred__0/out[8]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred__0/in0[8]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred/out[8]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred/in0[8]
      : HMNoC_cluster_east_1/\router_cluster_0/router_wght/data_out_inferred /out0[8]
      : HMNoC_cluster_east_1/\router_cluster_0/router_wght/data_out_inferred /data0[9]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred__0/out[9]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred__0/in0[9]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred/out[9]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred/in0[9]
      : HMNoC_cluster_east_1/north_data_i_wght0[9]
      : north_data_i_wght_inferred__2/out[9]
      : north_data_i_wght_inferred__2/in0[9]
      : north_data_i_wght_inferred__1/out[9]
      : north_data_i_wght_inferred__1/in0[9]
      : HMNoC_cluster_east_0/south_data_o_wght[9]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred__0/out[9]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred__0/in0[9]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred/out[9]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred/in0[9]
      : HMNoC_cluster_east_0/\router_cluster_0/router_wght/data_out_inferred /out0[9]
      : HMNoC_cluster_east_0/\router_cluster_0/router_wght/data_out_inferred /data1[9]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred__0/out[9]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred__0/in0[9]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred/out[9]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred/in0[9]
      : HMNoC_cluster_east_0/south_data_i_wght0[9]
      : south_data_i_wght_inferred__2/out[9]
      : south_data_i_wght_inferred__2/in0[9]
      : south_data_i_wght_inferred__1/out[9]
      : south_data_i_wght_inferred__1/in0[9]
      : HMNoC_cluster_east_1/north_data_o_wght[9]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred__0/out[9]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred__0/in0[9]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred/out[9]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred/in0[9]
      : HMNoC_cluster_east_1/\router_cluster_0/router_wght/data_out_inferred /out0[9]
      : HMNoC_cluster_east_1/\router_cluster_0/router_wght/data_out_inferred /data0[10]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred__0/out[10]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred__0/in0[10]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred/out[10]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred/in0[10]
      : HMNoC_cluster_east_1/north_data_i_wght0[10]
      : north_data_i_wght_inferred__2/out[10]
      : north_data_i_wght_inferred__2/in0[10]
      : north_data_i_wght_inferred__1/out[10]
      : north_data_i_wght_inferred__1/in0[10]
      : HMNoC_cluster_east_0/south_data_o_wght[10]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred__0/out[10]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred__0/in0[10]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred/out[10]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred/in0[10]
      : HMNoC_cluster_east_0/\router_cluster_0/router_wght/data_out_inferred /out0[10]
      : HMNoC_cluster_east_0/\router_cluster_0/router_wght/data_out_inferred /data1[10]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred__0/out[10]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred__0/in0[10]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred/out[10]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred/in0[10]
      : HMNoC_cluster_east_0/south_data_i_wght0[10]
      : south_data_i_wght_inferred__2/out[10]
      : south_data_i_wght_inferred__2/in0[10]
      : south_data_i_wght_inferred__1/out[10]
      : south_data_i_wght_inferred__1/in0[10]
      : HMNoC_cluster_east_1/north_data_o_wght[10]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred__0/out[10]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred__0/in0[10]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred/out[10]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred/in0[10]
      : HMNoC_cluster_east_1/\router_cluster_0/router_wght/data_out_inferred /out0[10]
      : HMNoC_cluster_east_1/\router_cluster_0/router_wght/data_out_inferred /data0[13]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred__0/out[13]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred__0/in0[13]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred/out[13]
      : HMNoC_cluster_east_1/north_data_i_wght_inferred/in0[13]
      : HMNoC_cluster_east_1/north_data_i_wght0[13]
      : north_data_i_wght_inferred__2/out[13]
      : north_data_i_wght_inferred__2/in0[13]
      : north_data_i_wght_inferred__1/out[13]
      : north_data_i_wght_inferred__1/in0[13]
      : HMNoC_cluster_east_0/south_data_o_wght[13]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred__0/out[13]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred__0/in0[13]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred/out[13]
      : HMNoC_cluster_east_0/south_data_o_wght_inferred/in0[13]
      : HMNoC_cluster_east_0/\router_cluster_0/router_wght/data_out_inferred /out0[13]
      : HMNoC_cluster_east_0/\router_cluster_0/router_wght/data_out_inferred /data1[13]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred__0/out[13]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred__0/in0[13]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred/out[13]
      : HMNoC_cluster_east_0/south_data_i_wght_inferred/in0[13]
      : HMNoC_cluster_east_0/south_data_i_wght0[13]
      : south_data_i_wght_inferred__2/out[13]
      : south_data_i_wght_inferred__2/in0[13]
      : south_data_i_wght_inferred__1/out[13]
      : south_data_i_wght_inferred__1/in0[13]
      : HMNoC_cluster_east_1/north_data_o_wght[13]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred__0/out[13]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred__0/in0[13]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred/out[13]
      : HMNoC_cluster_east_1/north_data_o_wght_inferred/in0[13]
      : HMNoC_cluster_east_1/\router_cluster_0/router_wght/data_out_inferred /out0[13]
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:54 ; elapsed = 00:01:02 . Memory (MB): peak = 2125.828 ; gain = 1864.645
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------

Distributed RAM: Final Mapping  Report
+----------------------------------+-------------------------------------------------------+-----------+----------------------+-------------------------------+
|Module Name                       | RTL Object                                            | Inference | Size (Depth x Width) | Primitives                    | 
+----------------------------------+-------------------------------------------------------+-----------+----------------------+-------------------------------+
|HMNoC_cluster_west_0/pe_cluster_0 | gen_X[0].gen_Y[0].pe/spad_pe0/mem_reg                 | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster_west_0/pe_cluster_0 | gen_X[0].gen_Y[1].pe/spad_pe0/mem_reg                 | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster_west_0/pe_cluster_0 | gen_X[0].gen_Y[2].pe/spad_pe0/mem_reg                 | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster_west_0/pe_cluster_0 | gen_X[1].gen_Y[0].pe/spad_pe0/mem_reg                 | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster_west_0/pe_cluster_0 | gen_X[1].gen_Y[1].pe/spad_pe0/mem_reg                 | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster_west_0/pe_cluster_0 | gen_X[1].gen_Y[2].pe/spad_pe0/mem_reg                 | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster_west_0/pe_cluster_0 | gen_X[2].gen_Y[0].pe/spad_pe0/mem_reg                 | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster_west_0/pe_cluster_0 | gen_X[2].gen_Y[1].pe/spad_pe0/mem_reg                 | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster_west_0/pe_cluster_0 | gen_X[2].gen_Y[2].pe/spad_pe0/mem_reg                 | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster_west_0              | GLB_cluster_0/glb_iact_gen[0].glb_iact_inst/mem_reg   | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster_west_0              | GLB_cluster_0/glb_psum_gen[0].glb_psum_inst/mem_reg   | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster_west_0              | GLB_cluster_0/glb_wght_gen[0].glb_weight_inst/mem_reg | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster_east_0              | GLB_cluster_0/glb_wght_gen[0].glb_weight_inst/mem_reg | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
|HMNoC_cluster_east_1              | GLB_cluster_0/glb_wght_gen[0].glb_weight_inst/mem_reg | Implied   | 512 x 16             | RAM64X1D x 16  RAM64M8 x 16   | 
+----------------------------------+-------------------------------------------------------+-----------+----------------------+-------------------------------+

---------------------------------------------------------------------------------
Finished ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /out[13]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /in0[13]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /out[13]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /in0[13]
      : east_data_i_psum_inferred__0/out[13]
      : east_data_i_psum_inferred__0/in0[13]
      : east_data_i_psum_inferred/out[13]
      : east_data_i_psum_inferred/in0[13]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /out[13]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /in0[13]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /out[13]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /in0[13]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /out[13]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /in0[13]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /out[13]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /in0[13]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[13]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[13]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[13]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[13]
      : west_data_i_psum_inferred__0/out[13]
      : west_data_i_psum_inferred__0/in0[13]
      : west_data_i_psum_inferred/out[13]
      : west_data_i_psum_inferred/in0[13]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[13]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[13]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[13]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[13]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[13]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[13]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[13]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[13]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[13]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[13]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[13]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[13]
      : south_data_i_psum_inferred__2/out[13]
      : south_data_i_psum_inferred__2/in0[13]
      : south_data_i_psum_inferred__1/out[13]
      : south_data_i_psum_inferred__1/in0[13]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[13]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[13]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[13]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[13]
      : north_data_o_psum_inferred__2/out[13]
      : north_data_o_psum_inferred__2/in0[13]
      : north_data_o_psum_inferred__1/out[13]
      : north_data_o_psum_inferred__1/in0[13]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[13]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[13]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[13]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[13]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /out[12]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /out[12]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /in0[12]
      : east_data_i_psum_inferred__0/out[12]
      : east_data_i_psum_inferred__0/in0[12]
      : east_data_i_psum_inferred/out[12]
      : east_data_i_psum_inferred/in0[12]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /out[12]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /out[12]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /in0[12]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /out[12]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /out[12]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /in0[12]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[12]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[12]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[12]
      : west_data_i_psum_inferred__0/out[12]
      : west_data_i_psum_inferred__0/in0[12]
      : west_data_i_psum_inferred/out[12]
      : west_data_i_psum_inferred/in0[12]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[12]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[12]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[12]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[12]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[12]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[12]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[12]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[12]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[12]
      : south_data_i_psum_inferred__2/out[12]
      : south_data_i_psum_inferred__2/in0[12]
      : south_data_i_psum_inferred__1/out[12]
      : south_data_i_psum_inferred__1/in0[12]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[12]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[12]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[12]
      : north_data_o_psum_inferred__2/out[12]
      : north_data_o_psum_inferred__2/in0[12]
      : north_data_o_psum_inferred__1/out[12]
      : north_data_o_psum_inferred__1/in0[12]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[12]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[12]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[12]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /out[11]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /out[11]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /in0[11]
      : east_data_i_psum_inferred__0/out[11]
      : east_data_i_psum_inferred__0/in0[11]
      : east_data_i_psum_inferred/out[11]
      : east_data_i_psum_inferred/in0[11]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /out[11]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /out[11]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /in0[11]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /out[11]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /out[11]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /in0[11]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[11]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[11]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[11]
      : west_data_i_psum_inferred__0/out[11]
      : west_data_i_psum_inferred__0/in0[11]
      : west_data_i_psum_inferred/out[11]
      : west_data_i_psum_inferred/in0[11]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[11]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[11]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[11]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[11]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[11]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[11]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[11]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[11]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[11]
      : south_data_i_psum_inferred__2/out[11]
      : south_data_i_psum_inferred__2/in0[11]
      : south_data_i_psum_inferred__1/out[11]
      : south_data_i_psum_inferred__1/in0[11]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[11]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[11]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[11]
      : north_data_o_psum_inferred__2/out[11]
      : north_data_o_psum_inferred__2/in0[11]
      : north_data_o_psum_inferred__1/out[11]
      : north_data_o_psum_inferred__1/in0[11]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[11]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[11]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[11]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /out[10]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /in0[10]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /out[10]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /in0[10]
      : east_data_i_psum_inferred__0/out[10]
      : east_data_i_psum_inferred__0/in0[10]
      : east_data_i_psum_inferred/out[10]
      : east_data_i_psum_inferred/in0[10]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /out[10]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /in0[10]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /out[10]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /in0[10]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /out[10]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /in0[10]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /out[10]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /in0[10]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[10]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[10]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[10]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[10]
      : west_data_i_psum_inferred__0/out[10]
      : west_data_i_psum_inferred__0/in0[10]
      : west_data_i_psum_inferred/out[10]
      : west_data_i_psum_inferred/in0[10]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[10]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[10]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[10]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[10]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[10]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[10]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[10]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[10]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[10]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[10]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[10]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[10]
      : south_data_i_psum_inferred__2/out[10]
      : south_data_i_psum_inferred__2/in0[10]
      : south_data_i_psum_inferred__1/out[10]
      : south_data_i_psum_inferred__1/in0[10]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[10]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[10]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[10]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[10]
      : north_data_o_psum_inferred__2/out[10]
      : north_data_o_psum_inferred__2/in0[10]
      : north_data_o_psum_inferred__1/out[10]
      : north_data_o_psum_inferred__1/in0[10]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[10]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[10]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[10]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[10]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /out[9]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /in0[9]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /out[9]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /in0[9]
      : east_data_i_psum_inferred__0/out[9]
      : east_data_i_psum_inferred__0/in0[9]
      : east_data_i_psum_inferred/out[9]
      : east_data_i_psum_inferred/in0[9]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /out[9]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /in0[9]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /out[9]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /in0[9]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /out[9]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /in0[9]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /out[9]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /in0[9]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[9]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[9]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[9]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[9]
      : west_data_i_psum_inferred__0/out[9]
      : west_data_i_psum_inferred__0/in0[9]
      : west_data_i_psum_inferred/out[9]
      : west_data_i_psum_inferred/in0[9]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[9]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[9]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[9]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[9]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[9]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[9]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[9]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[9]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[9]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[9]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[9]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[9]
      : south_data_i_psum_inferred__2/out[9]
      : south_data_i_psum_inferred__2/in0[9]
      : south_data_i_psum_inferred__1/out[9]
      : south_data_i_psum_inferred__1/in0[9]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[9]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[9]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[9]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[9]
      : north_data_o_psum_inferred__2/out[9]
      : north_data_o_psum_inferred__2/in0[9]
      : north_data_o_psum_inferred__1/out[9]
      : north_data_o_psum_inferred__1/in0[9]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[9]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[9]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[9]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[9]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /out[8]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /in0[8]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /out[8]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /in0[8]
      : east_data_i_psum_inferred__0/out[8]
      : east_data_i_psum_inferred__0/in0[8]
      : east_data_i_psum_inferred/out[8]
      : east_data_i_psum_inferred/in0[8]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /out[8]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /in0[8]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /out[8]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /in0[8]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /out[8]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /in0[8]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /out[8]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /in0[8]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[8]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[8]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[8]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[8]
      : west_data_i_psum_inferred__0/out[8]
      : west_data_i_psum_inferred__0/in0[8]
      : west_data_i_psum_inferred/out[8]
      : west_data_i_psum_inferred/in0[8]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[8]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[8]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[8]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[8]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[8]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[8]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[8]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[8]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[8]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[8]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[8]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[8]
      : south_data_i_psum_inferred__2/out[8]
      : south_data_i_psum_inferred__2/in0[8]
      : south_data_i_psum_inferred__1/out[8]
      : south_data_i_psum_inferred__1/in0[8]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[8]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[8]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[8]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[8]
      : north_data_o_psum_inferred__2/out[8]
      : north_data_o_psum_inferred__2/in0[8]
      : north_data_o_psum_inferred__1/out[8]
      : north_data_o_psum_inferred__1/in0[8]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[8]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[8]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[8]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[8]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /out[7]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /out[7]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /in0[7]
      : east_data_i_psum_inferred__0/out[7]
      : east_data_i_psum_inferred__0/in0[7]
      : east_data_i_psum_inferred/out[7]
      : east_data_i_psum_inferred/in0[7]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /out[7]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /out[7]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /in0[7]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /out[7]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /out[7]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /in0[7]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[7]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[7]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[7]
      : west_data_i_psum_inferred__0/out[7]
      : west_data_i_psum_inferred__0/in0[7]
      : west_data_i_psum_inferred/out[7]
      : west_data_i_psum_inferred/in0[7]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[7]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[7]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[7]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[7]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[7]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[7]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[7]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[7]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[7]
      : south_data_i_psum_inferred__2/out[7]
      : south_data_i_psum_inferred__2/in0[7]
      : south_data_i_psum_inferred__1/out[7]
      : south_data_i_psum_inferred__1/in0[7]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[7]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[7]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[7]
      : north_data_o_psum_inferred__2/out[7]
      : north_data_o_psum_inferred__2/in0[7]
      : north_data_o_psum_inferred__1/out[7]
      : north_data_o_psum_inferred__1/in0[7]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[7]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[7]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[7]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /out[6]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /in0[6]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /out[6]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /in0[6]
      : east_data_i_psum_inferred__0/out[6]
      : east_data_i_psum_inferred__0/in0[6]
      : east_data_i_psum_inferred/out[6]
      : east_data_i_psum_inferred/in0[6]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /out[6]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /in0[6]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /out[6]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /in0[6]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /out[6]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /in0[6]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /out[6]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /in0[6]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[6]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[6]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[6]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[6]
      : west_data_i_psum_inferred__0/out[6]
      : west_data_i_psum_inferred__0/in0[6]
      : west_data_i_psum_inferred/out[6]
      : west_data_i_psum_inferred/in0[6]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[6]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[6]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[6]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[6]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[6]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[6]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[6]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[6]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[6]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[6]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[6]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[6]
      : south_data_i_psum_inferred__2/out[6]
      : south_data_i_psum_inferred__2/in0[6]
      : south_data_i_psum_inferred__1/out[6]
      : south_data_i_psum_inferred__1/in0[6]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[6]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[6]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[6]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[6]
      : north_data_o_psum_inferred__2/out[6]
      : north_data_o_psum_inferred__2/in0[6]
      : north_data_o_psum_inferred__1/out[6]
      : north_data_o_psum_inferred__1/in0[6]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[6]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[6]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[6]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[6]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /out[5]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /in0[5]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /out[5]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /in0[5]
      : east_data_i_psum_inferred__0/out[5]
      : east_data_i_psum_inferred__0/in0[5]
      : east_data_i_psum_inferred/out[5]
      : east_data_i_psum_inferred/in0[5]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /out[5]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /in0[5]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /out[5]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /in0[5]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /out[5]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /in0[5]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /out[5]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /in0[5]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[5]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[5]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[5]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[5]
      : west_data_i_psum_inferred__0/out[5]
      : west_data_i_psum_inferred__0/in0[5]
      : west_data_i_psum_inferred/out[5]
      : west_data_i_psum_inferred/in0[5]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[5]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[5]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[5]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[5]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[5]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[5]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[5]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[5]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[5]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[5]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[5]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[5]
      : south_data_i_psum_inferred__2/out[5]
      : south_data_i_psum_inferred__2/in0[5]
      : south_data_i_psum_inferred__1/out[5]
      : south_data_i_psum_inferred__1/in0[5]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[5]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[5]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[5]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[5]
      : north_data_o_psum_inferred__2/out[5]
      : north_data_o_psum_inferred__2/in0[5]
      : north_data_o_psum_inferred__1/out[5]
      : north_data_o_psum_inferred__1/in0[5]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[5]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[5]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[5]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[5]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /out[4]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /in0[4]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /out[4]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /in0[4]
      : east_data_i_psum_inferred__0/out[4]
      : east_data_i_psum_inferred__0/in0[4]
      : east_data_i_psum_inferred/out[4]
      : east_data_i_psum_inferred/in0[4]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /out[4]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /in0[4]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /out[4]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /in0[4]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /out[4]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /in0[4]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /out[4]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /in0[4]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[4]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[4]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[4]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[4]
      : west_data_i_psum_inferred__0/out[4]
      : west_data_i_psum_inferred__0/in0[4]
      : west_data_i_psum_inferred/out[4]
      : west_data_i_psum_inferred/in0[4]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[4]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[4]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[4]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[4]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[4]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[4]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[4]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[4]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[4]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[4]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[4]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[4]
      : south_data_i_psum_inferred__2/out[4]
      : south_data_i_psum_inferred__2/in0[4]
      : south_data_i_psum_inferred__1/out[4]
      : south_data_i_psum_inferred__1/in0[4]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[4]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[4]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[4]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[4]
      : north_data_o_psum_inferred__2/out[4]
      : north_data_o_psum_inferred__2/in0[4]
      : north_data_o_psum_inferred__1/out[4]
      : north_data_o_psum_inferred__1/in0[4]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[4]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[4]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[4]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[4]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /out[3]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /out[3]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /in0[3]
      : east_data_i_psum_inferred__0/out[3]
      : east_data_i_psum_inferred__0/in0[3]
      : east_data_i_psum_inferred/out[3]
      : east_data_i_psum_inferred/in0[3]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /out[3]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /out[3]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /in0[3]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /out[3]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /out[3]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /in0[3]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[3]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[3]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[3]
      : west_data_i_psum_inferred__0/out[3]
      : west_data_i_psum_inferred__0/in0[3]
      : west_data_i_psum_inferred/out[3]
      : west_data_i_psum_inferred/in0[3]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[3]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[3]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[3]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[3]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[3]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[3]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[3]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[3]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[3]
      : south_data_i_psum_inferred__2/out[3]
      : south_data_i_psum_inferred__2/in0[3]
      : south_data_i_psum_inferred__1/out[3]
      : south_data_i_psum_inferred__1/in0[3]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[3]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[3]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[3]
      : north_data_o_psum_inferred__2/out[3]
      : north_data_o_psum_inferred__2/in0[3]
      : north_data_o_psum_inferred__1/out[3]
      : north_data_o_psum_inferred__1/in0[3]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[3]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[3]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[3]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /out[2]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /in0[2]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /out[2]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /in0[2]
      : east_data_i_psum_inferred__0/out[2]
      : east_data_i_psum_inferred__0/in0[2]
      : east_data_i_psum_inferred/out[2]
      : east_data_i_psum_inferred/in0[2]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /out[2]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /in0[2]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /out[2]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /in0[2]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /out[2]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /in0[2]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /out[2]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /in0[2]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[2]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[2]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[2]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[2]
      : west_data_i_psum_inferred__0/out[2]
      : west_data_i_psum_inferred__0/in0[2]
      : west_data_i_psum_inferred/out[2]
      : west_data_i_psum_inferred/in0[2]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[2]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[2]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[2]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[2]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[2]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[2]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[2]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[2]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[2]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[2]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[2]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[2]
      : south_data_i_psum_inferred__2/out[2]
      : south_data_i_psum_inferred__2/in0[2]
      : south_data_i_psum_inferred__1/out[2]
      : south_data_i_psum_inferred__1/in0[2]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[2]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[2]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[2]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[2]
      : north_data_o_psum_inferred__2/out[2]
      : north_data_o_psum_inferred__2/in0[2]
      : north_data_o_psum_inferred__1/out[2]
      : north_data_o_psum_inferred__1/in0[2]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[2]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[2]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[2]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[2]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /out[1]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /out[1]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /in0[1]
      : east_data_i_psum_inferred__0/out[1]
      : east_data_i_psum_inferred__0/in0[1]
      : east_data_i_psum_inferred/out[1]
      : east_data_i_psum_inferred/in0[1]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /out[1]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /out[1]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /in0[1]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /out[1]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /out[1]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /in0[1]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[1]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[1]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[1]
      : west_data_i_psum_inferred__0/out[1]
      : west_data_i_psum_inferred__0/in0[1]
      : west_data_i_psum_inferred/out[1]
      : west_data_i_psum_inferred/in0[1]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[1]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[1]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[1]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[1]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[1]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[1]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[1]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[1]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[1]
      : south_data_i_psum_inferred__2/out[1]
      : south_data_i_psum_inferred__2/in0[1]
      : south_data_i_psum_inferred__1/out[1]
      : south_data_i_psum_inferred__1/in0[1]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[1]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[1]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[1]
      : north_data_o_psum_inferred__2/out[1]
      : north_data_o_psum_inferred__2/in0[1]
      : north_data_o_psum_inferred__1/out[1]
      : north_data_o_psum_inferred__1/in0[1]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[1]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[1]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[1]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /out[0]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /in0[0]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /out[0]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /in0[0]
      : east_data_i_psum_inferred__0/out[0]
      : east_data_i_psum_inferred__0/in0[0]
      : east_data_i_psum_inferred/out[0]
      : east_data_i_psum_inferred/in0[0]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /out[0]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /in0[0]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /out[0]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /in0[0]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /out[0]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /in0[0]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /out[0]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /in0[0]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[0]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[0]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[0]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[0]
      : west_data_i_psum_inferred__0/out[0]
      : west_data_i_psum_inferred__0/in0[0]
      : west_data_i_psum_inferred/out[0]
      : west_data_i_psum_inferred/in0[0]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[0]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[0]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[0]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[0]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[0]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[0]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[0]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[0]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[0]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[0]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[0]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[0]
      : south_data_i_psum_inferred__2/out[0]
      : south_data_i_psum_inferred__2/in0[0]
      : south_data_i_psum_inferred__1/out[0]
      : south_data_i_psum_inferred__1/in0[0]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[0]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[0]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[0]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[0]
      : north_data_o_psum_inferred__2/out[0]
      : north_data_o_psum_inferred__2/in0[0]
      : north_data_o_psum_inferred__1/out[0]
      : north_data_o_psum_inferred__1/in0[0]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[0]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[0]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[0]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[0]
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1624 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1624 /I0 (LUT2)
     2: i_2236/O (LUT5)
     3: i_2236/I2 (LUT5)
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /out[0]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /in0[0]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /out[0]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /in0[0]
      : south_data_i_wght_inferred__0/out[0]
      : south_data_i_wght_inferred__0/in0[0]
      : south_data_i_wght_inferred/out[0]
      : south_data_i_wght_inferred/in0[0]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /out[0]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /in0[0]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /out[0]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /in0[0]
     4: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1855 /O (LUT2)
     5: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1855 /I1 (LUT2)
     6: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1839 /O (LUT2)
     7: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1839 /I0 (LUT2)
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /out[0]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /in0[0]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /out[0]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /in0[0]
      : north_data_i_wght_inferred__0/out[0]
      : north_data_i_wght_inferred__0/in0[0]
      : north_data_i_wght_inferred/out[0]
      : north_data_i_wght_inferred/in0[0]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /out[0]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /in0[0]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /out[0]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /in0[0]
     8: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1624 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1624 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1656 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1656 /I0 (LUT2)
     2: i_2252/O (LUT5)
     3: i_2252/I3 (LUT5)
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /out[0]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /in0[0]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /out[0]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /in0[0]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /out[0]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /in0[0]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /out[0]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /in0[0]
      : east_data_i_iact_inferred__0/out[0]
      : east_data_i_iact_inferred__0/in0[0]
      : east_data_i_iact_inferred/out[0]
      : east_data_i_iact_inferred/in0[0]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /out[0]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /in0[0]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /out[0]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /in0[0]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /out[0]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /in0[0]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /out[0]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /in0[0]
     4: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_1992 /O (LUT2)
     5: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_1992 /I0 (LUT2)
     6: i_2363/O (LUT5)
     7: i_2363/I3 (LUT5)
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /out[0]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /in0[0]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /out[0]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /in0[0]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /out[0]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /in0[0]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /out[0]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /in0[0]
      : west_data_i_iact_inferred__0/out[0]
      : west_data_i_iact_inferred__0/in0[0]
      : west_data_i_iact_inferred/out[0]
      : west_data_i_iact_inferred/in0[0]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /out[0]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /in0[0]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /out[0]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /in0[0]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /out[0]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /in0[0]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /out[0]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /in0[0]
     8: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1656 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1656 "
Found timing loop:
     0: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_1992 /O (LUT2)
     1: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_1992 /I0 (LUT2)
     2: i_2363/O (LUT5)
     3: i_2363/I3 (LUT5)
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /out[0]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /in0[0]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /out[0]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /in0[0]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /out[0]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /in0[0]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /out[0]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /in0[0]
      : west_data_i_iact_inferred__0/out[0]
      : west_data_i_iact_inferred__0/in0[0]
      : west_data_i_iact_inferred/out[0]
      : west_data_i_iact_inferred/in0[0]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /out[0]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /in0[0]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /out[0]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /in0[0]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /out[0]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /in0[0]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /out[0]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /in0[0]
     4: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1656 /O (LUT2)
     5: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1656 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_1992 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1656 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1656 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Found timing loop:
     0: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2136 /O (LUT2)
     1: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2136 /I0 (LUT2)
     2: i_2429/O (LUT5)
     3: i_2429/I3 (LUT5)
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred__0 /out[0]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred__0 /in0[0]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred /out[0]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred /in0[0]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred__0 /out[0]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred__0 /in0[0]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred /out[0]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred /in0[0]
      : east_data_o_iact_inferred__2/out[0]
      : east_data_o_iact_inferred__2/in0[0]
      : east_data_o_iact_inferred__1/out[0]
      : east_data_o_iact_inferred__1/in0[0]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred__0 /out[0]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred__0 /in0[0]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred /out[0]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred /in0[0]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred__0 /out[0]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred__0 /in0[0]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred /out[0]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred /in0[0]
     4: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1887 /O (LUT2)
     5: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1887 /I0 (LUT2)
     6: i_2322/O (LUT5)
     7: i_2322/I3 (LUT5)
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /out[0]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /in0[0]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /out[0]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /in0[0]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /out[0]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /in0[0]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /out[0]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /in0[0]
      : east_data_i_iact_inferred__2/out[0]
      : east_data_i_iact_inferred__2/in0[0]
      : east_data_i_iact_inferred__1/out[0]
      : east_data_i_iact_inferred__1/in0[0]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /out[0]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /in0[0]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /out[0]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /in0[0]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /out[0]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /in0[0]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /out[0]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /in0[0]
     8: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2136 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2136 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1625 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1625 /I0 (LUT2)
     2: i_2237/O (LUT5)
     3: i_2237/I3 (LUT5)
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /out[1]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /in0[1]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /out[1]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /in0[1]
      : south_data_i_wght_inferred__0/out[1]
      : south_data_i_wght_inferred__0/in0[1]
      : south_data_i_wght_inferred/out[1]
      : south_data_i_wght_inferred/in0[1]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /out[1]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /in0[1]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /out[1]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /in0[1]
     4: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1856 /O (LUT2)
     5: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1856 /I1 (LUT2)
     6: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1840 /O (LUT2)
     7: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1840 /I0 (LUT2)
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /out[1]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /in0[1]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /out[1]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /in0[1]
      : north_data_i_wght_inferred__0/out[1]
      : north_data_i_wght_inferred__0/in0[1]
      : north_data_i_wght_inferred/out[1]
      : north_data_i_wght_inferred/in0[1]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /out[1]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /in0[1]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /out[1]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /in0[1]
     8: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1625 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1625 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1657 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1657 /I0 (LUT2)
     2: i_2253/O (LUT5)
     3: i_2253/I3 (LUT5)
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /out[1]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /in0[1]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /out[1]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /in0[1]
      : south_data_i_iact_inferred__0/out[1]
      : south_data_i_iact_inferred__0/in0[1]
      : south_data_i_iact_inferred/out[1]
      : south_data_i_iact_inferred/in0[1]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /out[1]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /in0[1]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /out[1]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /in0[1]
     4: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1888 /O (LUT2)
     5: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1888 /I1 (LUT2)
     6: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1872 /O (LUT2)
     7: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1872 /I0 (LUT2)
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /out[1]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /in0[1]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /out[1]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /in0[1]
      : north_data_i_iact_inferred__0/out[1]
      : north_data_i_iact_inferred__0/in0[1]
      : north_data_i_iact_inferred/out[1]
      : north_data_i_iact_inferred/in0[1]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /out[1]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /in0[1]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /out[1]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /in0[1]
     8: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1657 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1657 "
Found timing loop:
     0: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2137 /O (LUT2)
     1: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2137 /I1 (LUT2)
     2: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2121 /O (LUT2)
     3: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2121 /I0 (LUT2)
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /out[1]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /in0[1]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /out[1]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /in0[1]
      : north_data_i_iact_inferred__2/out[1]
      : north_data_i_iact_inferred__2/in0[1]
      : north_data_i_iact_inferred__1/out[1]
      : north_data_i_iact_inferred__1/in0[1]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /out[1]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /in0[1]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /out[1]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /in0[1]
     4: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_1993 /O (LUT2)
     5: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_1993 /I0 (LUT2)
     6: i_2364/O (LUT5)
     7: i_2364/I3 (LUT5)
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /out[1]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /in0[1]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /out[1]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /in0[1]
      : south_data_i_iact_inferred__2/out[1]
      : south_data_i_iact_inferred__2/in0[1]
      : south_data_i_iact_inferred__1/out[1]
      : south_data_i_iact_inferred__1/in0[1]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /out[1]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /in0[1]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /out[1]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /in0[1]
     8: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2137 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I1 -to O \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2137 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1657 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1657 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Found timing loop:
     0: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1888 /O (LUT2)
     1: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1888 /I0 (LUT2)
     2: i_2323/O (LUT5)
     3: i_2323/I2 (LUT5)
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /out[1]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /in0[1]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /out[1]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /in0[1]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /out[1]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /in0[1]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /out[1]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /in0[1]
      : east_data_i_iact_inferred__2/out[1]
      : east_data_i_iact_inferred__2/in0[1]
      : east_data_i_iact_inferred__1/out[1]
      : east_data_i_iact_inferred__1/in0[1]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /out[1]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /in0[1]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /out[1]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /in0[1]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /out[1]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /in0[1]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /out[1]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /in0[1]
     4: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2137 /O (LUT2)
     5: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2137 /I0 (LUT2)
     6: i_2430/O (LUT5)
     7: i_2430/I2 (LUT5)
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred__0 /out[1]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred__0 /in0[1]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred /out[1]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred /in0[1]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred__0 /out[1]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred__0 /in0[1]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred /out[1]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred /in0[1]
      : east_data_o_iact_inferred__2/out[1]
      : east_data_o_iact_inferred__2/in0[1]
      : east_data_o_iact_inferred__1/out[1]
      : east_data_o_iact_inferred__1/in0[1]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred__0 /out[1]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred__0 /in0[1]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred /out[1]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred /in0[1]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred__0 /out[1]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred__0 /in0[1]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred /out[1]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred /in0[1]
     8: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1888 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1888 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1626 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1626 /I0 (LUT2)
     2: i_2238/O (LUT5)
     3: i_2238/I2 (LUT5)
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /out[2]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /in0[2]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /out[2]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /in0[2]
      : south_data_i_wght_inferred__0/out[2]
      : south_data_i_wght_inferred__0/in0[2]
      : south_data_i_wght_inferred/out[2]
      : south_data_i_wght_inferred/in0[2]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /out[2]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /in0[2]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /out[2]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /in0[2]
     4: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1857 /O (LUT2)
     5: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1857 /I1 (LUT2)
     6: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1841 /O (LUT2)
     7: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1841 /I0 (LUT2)
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /out[2]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /in0[2]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /out[2]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /in0[2]
      : north_data_i_wght_inferred__0/out[2]
      : north_data_i_wght_inferred__0/in0[2]
      : north_data_i_wght_inferred/out[2]
      : north_data_i_wght_inferred/in0[2]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /out[2]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /in0[2]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /out[2]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /in0[2]
     8: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1626 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1626 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1658 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1658 /I0 (LUT2)
     2: i_2254/O (LUT5)
     3: i_2254/I3 (LUT5)
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /out[2]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /in0[2]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /out[2]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /in0[2]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /out[2]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /in0[2]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /out[2]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /in0[2]
      : east_data_i_iact_inferred__0/out[2]
      : east_data_i_iact_inferred__0/in0[2]
      : east_data_i_iact_inferred/out[2]
      : east_data_i_iact_inferred/in0[2]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /out[2]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /in0[2]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /out[2]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /in0[2]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /out[2]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /in0[2]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /out[2]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /in0[2]
     4: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_1994 /O (LUT2)
     5: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_1994 /I0 (LUT2)
     6: i_2365/O (LUT5)
     7: i_2365/I3 (LUT5)
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /out[2]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /in0[2]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /out[2]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /in0[2]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /out[2]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /in0[2]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /out[2]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /in0[2]
      : west_data_i_iact_inferred__0/out[2]
      : west_data_i_iact_inferred__0/in0[2]
      : west_data_i_iact_inferred/out[2]
      : west_data_i_iact_inferred/in0[2]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /out[2]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /in0[2]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /out[2]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /in0[2]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /out[2]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /in0[2]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /out[2]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /in0[2]
     8: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1658 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1658 "
Found timing loop:
     0: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_1994 /O (LUT2)
     1: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_1994 /I0 (LUT2)
     2: i_2365/O (LUT5)
     3: i_2365/I3 (LUT5)
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /out[2]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /in0[2]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /out[2]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /in0[2]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /out[2]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /in0[2]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /out[2]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /in0[2]
      : west_data_i_iact_inferred__0/out[2]
      : west_data_i_iact_inferred__0/in0[2]
      : west_data_i_iact_inferred/out[2]
      : west_data_i_iact_inferred/in0[2]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /out[2]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /in0[2]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /out[2]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /in0[2]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /out[2]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /in0[2]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /out[2]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /in0[2]
     4: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1658 /O (LUT2)
     5: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1658 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_1994 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1658 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1658 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Found timing loop:
     0: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2138 /O (LUT2)
     1: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2138 /I0 (LUT2)
     2: i_2431/O (LUT5)
     3: i_2431/I3 (LUT5)
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred__0 /out[2]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred__0 /in0[2]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred /out[2]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred /in0[2]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred__0 /out[2]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred__0 /in0[2]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred /out[2]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred /in0[2]
      : east_data_o_iact_inferred__2/out[2]
      : east_data_o_iact_inferred__2/in0[2]
      : east_data_o_iact_inferred__1/out[2]
      : east_data_o_iact_inferred__1/in0[2]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred__0 /out[2]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred__0 /in0[2]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred /out[2]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred /in0[2]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred__0 /out[2]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred__0 /in0[2]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred /out[2]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred /in0[2]
     4: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1889 /O (LUT2)
     5: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1889 /I0 (LUT2)
     6: i_2324/O (LUT5)
     7: i_2324/I3 (LUT5)
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /out[2]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /in0[2]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /out[2]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /in0[2]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /out[2]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /in0[2]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /out[2]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /in0[2]
      : east_data_i_iact_inferred__2/out[2]
      : east_data_i_iact_inferred__2/in0[2]
      : east_data_i_iact_inferred__1/out[2]
      : east_data_i_iact_inferred__1/in0[2]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /out[2]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /in0[2]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /out[2]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /in0[2]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /out[2]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /in0[2]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /out[2]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /in0[2]
     8: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2138 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2138 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1627 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1627 /I0 (LUT2)
     2: i_2239/O (LUT5)
     3: i_2239/I3 (LUT5)
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /out[3]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /in0[3]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /out[3]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /in0[3]
      : south_data_i_wght_inferred__0/out[3]
      : south_data_i_wght_inferred__0/in0[3]
      : south_data_i_wght_inferred/out[3]
      : south_data_i_wght_inferred/in0[3]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /out[3]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /in0[3]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /out[3]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /in0[3]
     4: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1858 /O (LUT2)
     5: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1858 /I1 (LUT2)
     6: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1842 /O (LUT2)
     7: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1842 /I0 (LUT2)
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /out[3]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /in0[3]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /out[3]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /in0[3]
      : north_data_i_wght_inferred__0/out[3]
      : north_data_i_wght_inferred__0/in0[3]
      : north_data_i_wght_inferred/out[3]
      : north_data_i_wght_inferred/in0[3]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /out[3]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /in0[3]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /out[3]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /in0[3]
     8: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1627 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1627 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1659 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1659 /I0 (LUT2)
     2: i_2255/O (LUT5)
     3: i_2255/I3 (LUT5)
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /out[3]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /in0[3]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /out[3]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /in0[3]
      : south_data_i_iact_inferred__0/out[3]
      : south_data_i_iact_inferred__0/in0[3]
      : south_data_i_iact_inferred/out[3]
      : south_data_i_iact_inferred/in0[3]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /out[3]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /in0[3]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /out[3]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /in0[3]
     4: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1890 /O (LUT2)
     5: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1890 /I1 (LUT2)
     6: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1874 /O (LUT2)
     7: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1874 /I0 (LUT2)
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /out[3]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /in0[3]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /out[3]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /in0[3]
      : north_data_i_iact_inferred__0/out[3]
      : north_data_i_iact_inferred__0/in0[3]
      : north_data_i_iact_inferred/out[3]
      : north_data_i_iact_inferred/in0[3]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /out[3]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /in0[3]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /out[3]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /in0[3]
     8: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1659 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1659 "
Found timing loop:
     0: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2139 /O (LUT2)
     1: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2139 /I1 (LUT2)
     2: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2123 /O (LUT2)
     3: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2123 /I0 (LUT2)
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /out[3]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /in0[3]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /out[3]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /in0[3]
      : north_data_i_iact_inferred__2/out[3]
      : north_data_i_iact_inferred__2/in0[3]
      : north_data_i_iact_inferred__1/out[3]
      : north_data_i_iact_inferred__1/in0[3]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /out[3]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /in0[3]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /out[3]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /in0[3]
     4: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_1995 /O (LUT2)
     5: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_1995 /I0 (LUT2)
     6: i_2366/O (LUT5)
     7: i_2366/I3 (LUT5)
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /out[3]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /in0[3]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /out[3]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /in0[3]
      : south_data_i_iact_inferred__2/out[3]
      : south_data_i_iact_inferred__2/in0[3]
      : south_data_i_iact_inferred__1/out[3]
      : south_data_i_iact_inferred__1/in0[3]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /out[3]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /in0[3]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /out[3]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /in0[3]
     8: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2139 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I1 -to O \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2139 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1659 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1659 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Found timing loop:
     0: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1890 /O (LUT2)
     1: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1890 /I0 (LUT2)
     2: i_2325/O (LUT5)
     3: i_2325/I2 (LUT5)
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /out[3]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /in0[3]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /out[3]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /in0[3]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /out[3]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /in0[3]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /out[3]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /in0[3]
      : east_data_i_iact_inferred__2/out[3]
      : east_data_i_iact_inferred__2/in0[3]
      : east_data_i_iact_inferred__1/out[3]
      : east_data_i_iact_inferred__1/in0[3]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /out[3]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /in0[3]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /out[3]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /in0[3]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /out[3]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /in0[3]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /out[3]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /in0[3]
     4: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2139 /O (LUT2)
     5: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2139 /I0 (LUT2)
     6: i_2432/O (LUT5)
     7: i_2432/I2 (LUT5)
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred__0 /out[3]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred__0 /in0[3]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred /out[3]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred /in0[3]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred__0 /out[3]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred__0 /in0[3]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred /out[3]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred /in0[3]
      : east_data_o_iact_inferred__2/out[3]
      : east_data_o_iact_inferred__2/in0[3]
      : east_data_o_iact_inferred__1/out[3]
      : east_data_o_iact_inferred__1/in0[3]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred__0 /out[3]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred__0 /in0[3]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred /out[3]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred /in0[3]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred__0 /out[3]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred__0 /in0[3]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred /out[3]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred /in0[3]
     8: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1890 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1890 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1628 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1628 /I0 (LUT2)
     2: i_2240/O (LUT5)
     3: i_2240/I2 (LUT5)
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /out[4]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /in0[4]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /out[4]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /in0[4]
      : south_data_i_wght_inferred__0/out[4]
      : south_data_i_wght_inferred__0/in0[4]
      : south_data_i_wght_inferred/out[4]
      : south_data_i_wght_inferred/in0[4]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /out[4]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /in0[4]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /out[4]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /in0[4]
     4: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1859 /O (LUT2)
     5: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1859 /I1 (LUT2)
     6: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1843 /O (LUT2)
     7: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1843 /I0 (LUT2)
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /out[4]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /in0[4]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /out[4]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /in0[4]
      : north_data_i_wght_inferred__0/out[4]
      : north_data_i_wght_inferred__0/in0[4]
      : north_data_i_wght_inferred/out[4]
      : north_data_i_wght_inferred/in0[4]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /out[4]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /in0[4]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /out[4]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /in0[4]
     8: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1628 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1628 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1660 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1660 /I0 (LUT2)
     2: i_2256/O (LUT5)
     3: i_2256/I3 (LUT5)
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /out[4]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /in0[4]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /out[4]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /in0[4]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /out[4]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /in0[4]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /out[4]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /in0[4]
      : east_data_i_iact_inferred__0/out[4]
      : east_data_i_iact_inferred__0/in0[4]
      : east_data_i_iact_inferred/out[4]
      : east_data_i_iact_inferred/in0[4]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /out[4]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /in0[4]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /out[4]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /in0[4]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /out[4]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /in0[4]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /out[4]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /in0[4]
     4: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_1996 /O (LUT2)
     5: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_1996 /I0 (LUT2)
     6: i_2367/O (LUT5)
     7: i_2367/I3 (LUT5)
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /out[4]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /in0[4]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /out[4]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /in0[4]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /out[4]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /in0[4]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /out[4]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /in0[4]
      : west_data_i_iact_inferred__0/out[4]
      : west_data_i_iact_inferred__0/in0[4]
      : west_data_i_iact_inferred/out[4]
      : west_data_i_iact_inferred/in0[4]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /out[4]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /in0[4]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /out[4]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /in0[4]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /out[4]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /in0[4]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /out[4]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /in0[4]
     8: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1660 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1660 "
Found timing loop:
     0: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_1996 /O (LUT2)
     1: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_1996 /I0 (LUT2)
     2: i_2367/O (LUT5)
     3: i_2367/I3 (LUT5)
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /out[4]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /in0[4]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /out[4]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /in0[4]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /out[4]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /in0[4]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /out[4]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /in0[4]
      : west_data_i_iact_inferred__0/out[4]
      : west_data_i_iact_inferred__0/in0[4]
      : west_data_i_iact_inferred/out[4]
      : west_data_i_iact_inferred/in0[4]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /out[4]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /in0[4]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /out[4]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /in0[4]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /out[4]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /in0[4]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /out[4]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /in0[4]
     4: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1660 /O (LUT2)
     5: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1660 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_1996 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1660 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1660 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Found timing loop:
     0: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2140 /O (LUT2)
     1: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2140 /I0 (LUT2)
     2: i_2433/O (LUT5)
     3: i_2433/I3 (LUT5)
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred__0 /out[4]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred__0 /in0[4]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred /out[4]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred /in0[4]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred__0 /out[4]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred__0 /in0[4]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred /out[4]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred /in0[4]
      : east_data_o_iact_inferred__2/out[4]
      : east_data_o_iact_inferred__2/in0[4]
      : east_data_o_iact_inferred__1/out[4]
      : east_data_o_iact_inferred__1/in0[4]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred__0 /out[4]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred__0 /in0[4]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred /out[4]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred /in0[4]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred__0 /out[4]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred__0 /in0[4]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred /out[4]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred /in0[4]
     4: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1891 /O (LUT2)
     5: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1891 /I0 (LUT2)
     6: i_2326/O (LUT5)
     7: i_2326/I3 (LUT5)
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /out[4]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /in0[4]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /out[4]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /in0[4]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /out[4]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /in0[4]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /out[4]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /in0[4]
      : east_data_i_iact_inferred__2/out[4]
      : east_data_i_iact_inferred__2/in0[4]
      : east_data_i_iact_inferred__1/out[4]
      : east_data_i_iact_inferred__1/in0[4]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /out[4]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /in0[4]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /out[4]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /in0[4]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /out[4]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /in0[4]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /out[4]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /in0[4]
     8: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2140 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2140 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1629 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1629 /I0 (LUT2)
     2: i_2241/O (LUT5)
     3: i_2241/I2 (LUT5)
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /out[5]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /in0[5]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /out[5]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /in0[5]
      : south_data_i_wght_inferred__0/out[5]
      : south_data_i_wght_inferred__0/in0[5]
      : south_data_i_wght_inferred/out[5]
      : south_data_i_wght_inferred/in0[5]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /out[5]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /in0[5]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /out[5]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /in0[5]
     4: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1860 /O (LUT2)
     5: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1860 /I1 (LUT2)
     6: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1844 /O (LUT2)
     7: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1844 /I0 (LUT2)
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /out[5]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /in0[5]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /out[5]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /in0[5]
      : north_data_i_wght_inferred__0/out[5]
      : north_data_i_wght_inferred__0/in0[5]
      : north_data_i_wght_inferred/out[5]
      : north_data_i_wght_inferred/in0[5]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /out[5]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /in0[5]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /out[5]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /in0[5]
     8: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1629 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1629 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1661 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1661 /I0 (LUT2)
     2: i_2257/O (LUT5)
     3: i_2257/I3 (LUT5)
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /out[5]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /in0[5]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /out[5]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /in0[5]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /out[5]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /in0[5]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /out[5]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /in0[5]
      : east_data_i_iact_inferred__0/out[5]
      : east_data_i_iact_inferred__0/in0[5]
      : east_data_i_iact_inferred/out[5]
      : east_data_i_iact_inferred/in0[5]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /out[5]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /in0[5]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /out[5]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /in0[5]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /out[5]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /in0[5]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /out[5]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /in0[5]
     4: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_1997 /O (LUT2)
     5: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_1997 /I0 (LUT2)
     6: i_2368/O (LUT5)
     7: i_2368/I3 (LUT5)
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /out[5]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /in0[5]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /out[5]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /in0[5]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /out[5]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /in0[5]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /out[5]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /in0[5]
      : west_data_i_iact_inferred__0/out[5]
      : west_data_i_iact_inferred__0/in0[5]
      : west_data_i_iact_inferred/out[5]
      : west_data_i_iact_inferred/in0[5]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /out[5]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /in0[5]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /out[5]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /in0[5]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /out[5]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /in0[5]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /out[5]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /in0[5]
     8: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1661 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1661 "
Found timing loop:
     0: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_1997 /O (LUT2)
     1: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_1997 /I0 (LUT2)
     2: i_2368/O (LUT5)
     3: i_2368/I3 (LUT5)
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /out[5]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /in0[5]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /out[5]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /in0[5]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /out[5]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /in0[5]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /out[5]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /in0[5]
      : west_data_i_iact_inferred__0/out[5]
      : west_data_i_iact_inferred__0/in0[5]
      : west_data_i_iact_inferred/out[5]
      : west_data_i_iact_inferred/in0[5]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /out[5]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /in0[5]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /out[5]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /in0[5]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /out[5]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /in0[5]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /out[5]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /in0[5]
     4: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1661 /O (LUT2)
     5: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1661 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_1997 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1661 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1661 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Found timing loop:
     0: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2141 /O (LUT2)
     1: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2141 /I0 (LUT2)
     2: i_2434/O (LUT5)
     3: i_2434/I3 (LUT5)
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred__0 /out[5]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred__0 /in0[5]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred /out[5]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred /in0[5]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred__0 /out[5]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred__0 /in0[5]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred /out[5]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred /in0[5]
      : east_data_o_iact_inferred__2/out[5]
      : east_data_o_iact_inferred__2/in0[5]
      : east_data_o_iact_inferred__1/out[5]
      : east_data_o_iact_inferred__1/in0[5]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred__0 /out[5]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred__0 /in0[5]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred /out[5]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred /in0[5]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred__0 /out[5]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred__0 /in0[5]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred /out[5]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred /in0[5]
     4: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1892 /O (LUT2)
     5: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1892 /I0 (LUT2)
     6: i_2327/O (LUT5)
     7: i_2327/I3 (LUT5)
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /out[5]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /in0[5]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /out[5]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /in0[5]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /out[5]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /in0[5]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /out[5]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /in0[5]
      : east_data_i_iact_inferred__2/out[5]
      : east_data_i_iact_inferred__2/in0[5]
      : east_data_i_iact_inferred__1/out[5]
      : east_data_i_iact_inferred__1/in0[5]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /out[5]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /in0[5]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /out[5]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /in0[5]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /out[5]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /in0[5]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /out[5]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /in0[5]
     8: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2141 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2141 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1630 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1630 /I0 (LUT2)
     2: i_2242/O (LUT5)
     3: i_2242/I2 (LUT5)
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /out[6]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /in0[6]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /out[6]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /in0[6]
      : south_data_i_wght_inferred__0/out[6]
      : south_data_i_wght_inferred__0/in0[6]
      : south_data_i_wght_inferred/out[6]
      : south_data_i_wght_inferred/in0[6]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /out[6]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /in0[6]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /out[6]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /in0[6]
     4: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1861 /O (LUT2)
     5: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1861 /I1 (LUT2)
     6: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1845 /O (LUT2)
     7: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1845 /I0 (LUT2)
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /out[6]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /in0[6]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /out[6]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /in0[6]
      : north_data_i_wght_inferred__0/out[6]
      : north_data_i_wght_inferred__0/in0[6]
      : north_data_i_wght_inferred/out[6]
      : north_data_i_wght_inferred/in0[6]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /out[6]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /in0[6]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /out[6]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /in0[6]
     8: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1630 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1630 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1662 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1662 /I0 (LUT2)
     2: i_2258/O (LUT5)
     3: i_2258/I3 (LUT5)
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /out[6]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /in0[6]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /out[6]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /in0[6]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /out[6]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /in0[6]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /out[6]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /in0[6]
      : east_data_i_iact_inferred__0/out[6]
      : east_data_i_iact_inferred__0/in0[6]
      : east_data_i_iact_inferred/out[6]
      : east_data_i_iact_inferred/in0[6]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /out[6]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /in0[6]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /out[6]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /in0[6]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /out[6]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /in0[6]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /out[6]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /in0[6]
     4: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_1998 /O (LUT2)
     5: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_1998 /I0 (LUT2)
     6: i_2369/O (LUT5)
     7: i_2369/I3 (LUT5)
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /out[6]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /in0[6]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /out[6]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /in0[6]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /out[6]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /in0[6]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /out[6]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /in0[6]
      : west_data_i_iact_inferred__0/out[6]
      : west_data_i_iact_inferred__0/in0[6]
      : west_data_i_iact_inferred/out[6]
      : west_data_i_iact_inferred/in0[6]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /out[6]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /in0[6]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /out[6]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /in0[6]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /out[6]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /in0[6]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /out[6]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /in0[6]
     8: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1662 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1662 "
Found timing loop:
     0: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_1998 /O (LUT2)
     1: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_1998 /I0 (LUT2)
     2: i_2369/O (LUT5)
     3: i_2369/I3 (LUT5)
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /out[6]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /in0[6]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /out[6]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /in0[6]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /out[6]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /in0[6]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /out[6]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /in0[6]
      : west_data_i_iact_inferred__0/out[6]
      : west_data_i_iact_inferred__0/in0[6]
      : west_data_i_iact_inferred/out[6]
      : west_data_i_iact_inferred/in0[6]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /out[6]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /in0[6]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /out[6]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /in0[6]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /out[6]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /in0[6]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /out[6]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /in0[6]
     4: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1662 /O (LUT2)
     5: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1662 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_1998 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1662 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1662 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Found timing loop:
     0: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2142 /O (LUT2)
     1: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2142 /I0 (LUT2)
     2: i_2435/O (LUT5)
     3: i_2435/I3 (LUT5)
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred__0 /out[6]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred__0 /in0[6]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred /out[6]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred /in0[6]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred__0 /out[6]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred__0 /in0[6]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred /out[6]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred /in0[6]
      : east_data_o_iact_inferred__2/out[6]
      : east_data_o_iact_inferred__2/in0[6]
      : east_data_o_iact_inferred__1/out[6]
      : east_data_o_iact_inferred__1/in0[6]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred__0 /out[6]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred__0 /in0[6]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred /out[6]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred /in0[6]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred__0 /out[6]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred__0 /in0[6]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred /out[6]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred /in0[6]
     4: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1893 /O (LUT2)
     5: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1893 /I0 (LUT2)
     6: i_2328/O (LUT5)
     7: i_2328/I3 (LUT5)
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /out[6]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /in0[6]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /out[6]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /in0[6]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /out[6]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /in0[6]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /out[6]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /in0[6]
      : east_data_i_iact_inferred__2/out[6]
      : east_data_i_iact_inferred__2/in0[6]
      : east_data_i_iact_inferred__1/out[6]
      : east_data_i_iact_inferred__1/in0[6]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /out[6]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /in0[6]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /out[6]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /in0[6]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /out[6]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /in0[6]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /out[6]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /in0[6]
     8: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2142 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2142 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1631 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1631 /I0 (LUT2)
     2: i_2243/O (LUT5)
     3: i_2243/I3 (LUT5)
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /out[7]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /in0[7]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /out[7]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /in0[7]
      : south_data_i_wght_inferred__0/out[7]
      : south_data_i_wght_inferred__0/in0[7]
      : south_data_i_wght_inferred/out[7]
      : south_data_i_wght_inferred/in0[7]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /out[7]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /in0[7]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /out[7]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /in0[7]
     4: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1862 /O (LUT2)
     5: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1862 /I1 (LUT2)
     6: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1846 /O (LUT2)
     7: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1846 /I0 (LUT2)
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /out[7]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /in0[7]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /out[7]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /in0[7]
      : north_data_i_wght_inferred__0/out[7]
      : north_data_i_wght_inferred__0/in0[7]
      : north_data_i_wght_inferred/out[7]
      : north_data_i_wght_inferred/in0[7]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /out[7]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /in0[7]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /out[7]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /in0[7]
     8: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1631 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1631 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1663 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1663 /I0 (LUT2)
     2: i_2259/O (LUT5)
     3: i_2259/I3 (LUT5)
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /out[7]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /in0[7]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /out[7]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /in0[7]
      : south_data_i_iact_inferred__0/out[7]
      : south_data_i_iact_inferred__0/in0[7]
      : south_data_i_iact_inferred/out[7]
      : south_data_i_iact_inferred/in0[7]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /out[7]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /in0[7]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /out[7]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /in0[7]
     4: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1894 /O (LUT2)
     5: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1894 /I1 (LUT2)
     6: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1878 /O (LUT2)
     7: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1878 /I0 (LUT2)
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /out[7]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /in0[7]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /out[7]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /in0[7]
      : north_data_i_iact_inferred__0/out[7]
      : north_data_i_iact_inferred__0/in0[7]
      : north_data_i_iact_inferred/out[7]
      : north_data_i_iact_inferred/in0[7]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /out[7]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /in0[7]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /out[7]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /in0[7]
     8: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1663 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1663 "
Found timing loop:
     0: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2143 /O (LUT2)
     1: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2143 /I1 (LUT2)
     2: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2127 /O (LUT2)
     3: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2127 /I0 (LUT2)
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /out[7]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /in0[7]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /out[7]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /in0[7]
      : north_data_i_iact_inferred__2/out[7]
      : north_data_i_iact_inferred__2/in0[7]
      : north_data_i_iact_inferred__1/out[7]
      : north_data_i_iact_inferred__1/in0[7]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /out[7]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /in0[7]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /out[7]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /in0[7]
     4: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_1999 /O (LUT2)
     5: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_1999 /I0 (LUT2)
     6: i_2370/O (LUT5)
     7: i_2370/I3 (LUT5)
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /out[7]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /in0[7]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /out[7]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /in0[7]
      : south_data_i_iact_inferred__2/out[7]
      : south_data_i_iact_inferred__2/in0[7]
      : south_data_i_iact_inferred__1/out[7]
      : south_data_i_iact_inferred__1/in0[7]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /out[7]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /in0[7]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /out[7]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /in0[7]
     8: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2143 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I1 -to O \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2143 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1663 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1663 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Found timing loop:
     0: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1894 /O (LUT2)
     1: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1894 /I0 (LUT2)
     2: i_2329/O (LUT5)
     3: i_2329/I2 (LUT5)
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /out[7]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /in0[7]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /out[7]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /in0[7]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /out[7]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /in0[7]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /out[7]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /in0[7]
      : east_data_i_iact_inferred__2/out[7]
      : east_data_i_iact_inferred__2/in0[7]
      : east_data_i_iact_inferred__1/out[7]
      : east_data_i_iact_inferred__1/in0[7]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /out[7]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /in0[7]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /out[7]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /in0[7]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /out[7]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /in0[7]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /out[7]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /in0[7]
     4: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2143 /O (LUT2)
     5: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2143 /I0 (LUT2)
     6: i_2436/O (LUT5)
     7: i_2436/I2 (LUT5)
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred__0 /out[7]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred__0 /in0[7]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred /out[7]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred /in0[7]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred__0 /out[7]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred__0 /in0[7]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred /out[7]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred /in0[7]
      : east_data_o_iact_inferred__2/out[7]
      : east_data_o_iact_inferred__2/in0[7]
      : east_data_o_iact_inferred__1/out[7]
      : east_data_o_iact_inferred__1/in0[7]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred__0 /out[7]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred__0 /in0[7]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred /out[7]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred /in0[7]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred__0 /out[7]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred__0 /in0[7]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred /out[7]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred /in0[7]
     8: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1894 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1894 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1632 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1632 /I0 (LUT2)
     2: i_2244/O (LUT5)
     3: i_2244/I2 (LUT5)
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /out[8]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /in0[8]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /out[8]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /in0[8]
      : south_data_i_wght_inferred__0/out[8]
      : south_data_i_wght_inferred__0/in0[8]
      : south_data_i_wght_inferred/out[8]
      : south_data_i_wght_inferred/in0[8]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /out[8]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /in0[8]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /out[8]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /in0[8]
     4: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1863 /O (LUT2)
     5: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1863 /I1 (LUT2)
     6: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1847 /O (LUT2)
     7: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1847 /I0 (LUT2)
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /out[8]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /in0[8]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /out[8]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /in0[8]
      : north_data_i_wght_inferred__0/out[8]
      : north_data_i_wght_inferred__0/in0[8]
      : north_data_i_wght_inferred/out[8]
      : north_data_i_wght_inferred/in0[8]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /out[8]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /in0[8]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /out[8]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /in0[8]
     8: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1632 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1632 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1664 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1664 /I0 (LUT2)
     2: i_2260/O (LUT5)
     3: i_2260/I3 (LUT5)
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /out[8]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /in0[8]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /out[8]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /in0[8]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /out[8]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /in0[8]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /out[8]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /in0[8]
      : east_data_i_iact_inferred__0/out[8]
      : east_data_i_iact_inferred__0/in0[8]
      : east_data_i_iact_inferred/out[8]
      : east_data_i_iact_inferred/in0[8]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /out[8]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /in0[8]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /out[8]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /in0[8]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /out[8]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /in0[8]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /out[8]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /in0[8]
     4: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_2000 /O (LUT2)
     5: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_2000 /I0 (LUT2)
     6: i_2371/O (LUT5)
     7: i_2371/I3 (LUT5)
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /out[8]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /in0[8]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /out[8]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /in0[8]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /out[8]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /in0[8]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /out[8]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /in0[8]
      : west_data_i_iact_inferred__0/out[8]
      : west_data_i_iact_inferred__0/in0[8]
      : west_data_i_iact_inferred/out[8]
      : west_data_i_iact_inferred/in0[8]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /out[8]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /in0[8]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /out[8]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /in0[8]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /out[8]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /in0[8]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /out[8]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /in0[8]
     8: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1664 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1664 "
Found timing loop:
     0: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_2000 /O (LUT2)
     1: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_2000 /I0 (LUT2)
     2: i_2371/O (LUT5)
     3: i_2371/I3 (LUT5)
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /out[8]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /in0[8]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /out[8]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /in0[8]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /out[8]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /in0[8]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /out[8]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /in0[8]
      : west_data_i_iact_inferred__0/out[8]
      : west_data_i_iact_inferred__0/in0[8]
      : west_data_i_iact_inferred/out[8]
      : west_data_i_iact_inferred/in0[8]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /out[8]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /in0[8]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /out[8]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /in0[8]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /out[8]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /in0[8]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /out[8]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /in0[8]
     4: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1664 /O (LUT2)
     5: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1664 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_2000 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1664 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1664 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Found timing loop:
     0: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2144 /O (LUT2)
     1: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2144 /I0 (LUT2)
     2: i_2437/O (LUT5)
     3: i_2437/I3 (LUT5)
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred__0 /out[8]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred__0 /in0[8]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred /out[8]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred /in0[8]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred__0 /out[8]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred__0 /in0[8]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred /out[8]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred /in0[8]
      : east_data_o_iact_inferred__2/out[8]
      : east_data_o_iact_inferred__2/in0[8]
      : east_data_o_iact_inferred__1/out[8]
      : east_data_o_iact_inferred__1/in0[8]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred__0 /out[8]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred__0 /in0[8]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred /out[8]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred /in0[8]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred__0 /out[8]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred__0 /in0[8]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred /out[8]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred /in0[8]
     4: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1895 /O (LUT2)
     5: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1895 /I0 (LUT2)
     6: i_2330/O (LUT5)
     7: i_2330/I3 (LUT5)
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /out[8]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /in0[8]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /out[8]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /in0[8]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /out[8]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /in0[8]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /out[8]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /in0[8]
      : east_data_i_iact_inferred__2/out[8]
      : east_data_i_iact_inferred__2/in0[8]
      : east_data_i_iact_inferred__1/out[8]
      : east_data_i_iact_inferred__1/in0[8]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /out[8]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /in0[8]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /out[8]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /in0[8]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /out[8]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /in0[8]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /out[8]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /in0[8]
     8: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2144 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2144 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1633 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1633 /I0 (LUT2)
     2: i_2245/O (LUT5)
     3: i_2245/I2 (LUT5)
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /out[9]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /in0[9]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /out[9]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /in0[9]
      : south_data_i_wght_inferred__0/out[9]
      : south_data_i_wght_inferred__0/in0[9]
      : south_data_i_wght_inferred/out[9]
      : south_data_i_wght_inferred/in0[9]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /out[9]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /in0[9]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /out[9]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /in0[9]
     4: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1864 /O (LUT2)
     5: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1864 /I1 (LUT2)
     6: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1848 /O (LUT2)
     7: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1848 /I0 (LUT2)
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /out[9]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /in0[9]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /out[9]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /in0[9]
      : north_data_i_wght_inferred__0/out[9]
      : north_data_i_wght_inferred__0/in0[9]
      : north_data_i_wght_inferred/out[9]
      : north_data_i_wght_inferred/in0[9]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /out[9]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /in0[9]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /out[9]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /in0[9]
     8: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1633 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1633 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1665 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1665 /I0 (LUT2)
     2: i_2261/O (LUT5)
     3: i_2261/I3 (LUT5)
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /out[9]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /in0[9]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /out[9]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /in0[9]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /out[9]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /in0[9]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /out[9]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /in0[9]
      : east_data_i_iact_inferred__0/out[9]
      : east_data_i_iact_inferred__0/in0[9]
      : east_data_i_iact_inferred/out[9]
      : east_data_i_iact_inferred/in0[9]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /out[9]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /in0[9]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /out[9]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /in0[9]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /out[9]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /in0[9]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /out[9]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /in0[9]
     4: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_2001 /O (LUT2)
     5: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_2001 /I0 (LUT2)
     6: i_2372/O (LUT5)
     7: i_2372/I3 (LUT5)
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /out[9]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /in0[9]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /out[9]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /in0[9]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /out[9]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /in0[9]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /out[9]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /in0[9]
      : west_data_i_iact_inferred__0/out[9]
      : west_data_i_iact_inferred__0/in0[9]
      : west_data_i_iact_inferred/out[9]
      : west_data_i_iact_inferred/in0[9]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /out[9]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /in0[9]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /out[9]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /in0[9]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /out[9]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /in0[9]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /out[9]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /in0[9]
     8: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1665 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1665 "
Found timing loop:
     0: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_2001 /O (LUT2)
     1: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_2001 /I0 (LUT2)
     2: i_2372/O (LUT5)
     3: i_2372/I3 (LUT5)
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /out[9]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /in0[9]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /out[9]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /in0[9]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /out[9]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /in0[9]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /out[9]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /in0[9]
      : west_data_i_iact_inferred__0/out[9]
      : west_data_i_iact_inferred__0/in0[9]
      : west_data_i_iact_inferred/out[9]
      : west_data_i_iact_inferred/in0[9]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /out[9]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /in0[9]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /out[9]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /in0[9]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /out[9]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /in0[9]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /out[9]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /in0[9]
     4: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1665 /O (LUT2)
     5: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1665 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_2001 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1665 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1665 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Found timing loop:
     0: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2145 /O (LUT2)
     1: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2145 /I0 (LUT2)
     2: i_2438/O (LUT5)
     3: i_2438/I3 (LUT5)
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred__0 /out[9]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred__0 /in0[9]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred /out[9]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred /in0[9]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred__0 /out[9]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred__0 /in0[9]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred /out[9]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred /in0[9]
      : east_data_o_iact_inferred__2/out[9]
      : east_data_o_iact_inferred__2/in0[9]
      : east_data_o_iact_inferred__1/out[9]
      : east_data_o_iact_inferred__1/in0[9]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred__0 /out[9]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred__0 /in0[9]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred /out[9]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred /in0[9]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred__0 /out[9]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred__0 /in0[9]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred /out[9]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred /in0[9]
     4: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1896 /O (LUT2)
     5: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1896 /I0 (LUT2)
     6: i_2331/O (LUT5)
     7: i_2331/I3 (LUT5)
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /out[9]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /in0[9]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /out[9]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /in0[9]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /out[9]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /in0[9]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /out[9]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /in0[9]
      : east_data_i_iact_inferred__2/out[9]
      : east_data_i_iact_inferred__2/in0[9]
      : east_data_i_iact_inferred__1/out[9]
      : east_data_i_iact_inferred__1/in0[9]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /out[9]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /in0[9]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /out[9]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /in0[9]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /out[9]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /in0[9]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /out[9]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /in0[9]
     8: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2145 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2145 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1634 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1634 /I0 (LUT2)
     2: i_2246/O (LUT5)
     3: i_2246/I2 (LUT5)
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /out[10]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /in0[10]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /out[10]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /in0[10]
      : south_data_i_wght_inferred__0/out[10]
      : south_data_i_wght_inferred__0/in0[10]
      : south_data_i_wght_inferred/out[10]
      : south_data_i_wght_inferred/in0[10]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /out[10]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /in0[10]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /out[10]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /in0[10]
     4: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1865 /O (LUT2)
     5: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1865 /I1 (LUT2)
     6: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1849 /O (LUT2)
     7: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1849 /I0 (LUT2)
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /out[10]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /in0[10]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /out[10]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /in0[10]
      : north_data_i_wght_inferred__0/out[10]
      : north_data_i_wght_inferred__0/in0[10]
      : north_data_i_wght_inferred/out[10]
      : north_data_i_wght_inferred/in0[10]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /out[10]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /in0[10]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /out[10]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /in0[10]
     8: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1634 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1634 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1666 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1666 /I0 (LUT2)
     2: i_2262/O (LUT5)
     3: i_2262/I3 (LUT5)
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /out[10]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /in0[10]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /out[10]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /in0[10]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /out[10]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /in0[10]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /out[10]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /in0[10]
      : east_data_i_iact_inferred__0/out[10]
      : east_data_i_iact_inferred__0/in0[10]
      : east_data_i_iact_inferred/out[10]
      : east_data_i_iact_inferred/in0[10]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /out[10]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /in0[10]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /out[10]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /in0[10]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /out[10]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /in0[10]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /out[10]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /in0[10]
     4: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_2002 /O (LUT2)
     5: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_2002 /I0 (LUT2)
     6: i_2373/O (LUT5)
     7: i_2373/I3 (LUT5)
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /out[10]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /in0[10]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /out[10]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /in0[10]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /out[10]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /in0[10]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /out[10]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /in0[10]
      : west_data_i_iact_inferred__0/out[10]
      : west_data_i_iact_inferred__0/in0[10]
      : west_data_i_iact_inferred/out[10]
      : west_data_i_iact_inferred/in0[10]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /out[10]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /in0[10]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /out[10]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /in0[10]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /out[10]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /in0[10]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /out[10]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /in0[10]
     8: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1666 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1666 "
Found timing loop:
     0: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_2002 /O (LUT2)
     1: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_2002 /I0 (LUT2)
     2: i_2373/O (LUT5)
     3: i_2373/I3 (LUT5)
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /out[10]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /in0[10]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /out[10]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /in0[10]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /out[10]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /in0[10]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /out[10]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /in0[10]
      : west_data_i_iact_inferred__0/out[10]
      : west_data_i_iact_inferred__0/in0[10]
      : west_data_i_iact_inferred/out[10]
      : west_data_i_iact_inferred/in0[10]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /out[10]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /in0[10]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /out[10]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /in0[10]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /out[10]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /in0[10]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /out[10]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /in0[10]
     4: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1666 /O (LUT2)
     5: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1666 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_2002 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1666 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1666 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Found timing loop:
     0: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2146 /O (LUT2)
     1: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2146 /I0 (LUT2)
     2: i_2439/O (LUT5)
     3: i_2439/I3 (LUT5)
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred__0 /out[10]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred__0 /in0[10]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred /out[10]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred /in0[10]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred__0 /out[10]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred__0 /in0[10]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred /out[10]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred /in0[10]
      : east_data_o_iact_inferred__2/out[10]
      : east_data_o_iact_inferred__2/in0[10]
      : east_data_o_iact_inferred__1/out[10]
      : east_data_o_iact_inferred__1/in0[10]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred__0 /out[10]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred__0 /in0[10]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred /out[10]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred /in0[10]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred__0 /out[10]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred__0 /in0[10]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred /out[10]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred /in0[10]
     4: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1897 /O (LUT2)
     5: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1897 /I0 (LUT2)
     6: i_2332/O (LUT5)
     7: i_2332/I3 (LUT5)
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /out[10]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /in0[10]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /out[10]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /in0[10]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /out[10]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /in0[10]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /out[10]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /in0[10]
      : east_data_i_iact_inferred__2/out[10]
      : east_data_i_iact_inferred__2/in0[10]
      : east_data_i_iact_inferred__1/out[10]
      : east_data_i_iact_inferred__1/in0[10]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /out[10]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /in0[10]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /out[10]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /in0[10]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /out[10]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /in0[10]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /out[10]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /in0[10]
     8: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2146 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2146 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1635 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1635 /I0 (LUT2)
     2: i_2247/O (LUT5)
     3: i_2247/I3 (LUT5)
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /out[11]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /in0[11]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /out[11]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /in0[11]
      : south_data_i_wght_inferred__0/out[11]
      : south_data_i_wght_inferred__0/in0[11]
      : south_data_i_wght_inferred/out[11]
      : south_data_i_wght_inferred/in0[11]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /out[11]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /in0[11]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /out[11]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /in0[11]
     4: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1866 /O (LUT2)
     5: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1866 /I1 (LUT2)
     6: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1850 /O (LUT2)
     7: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1850 /I0 (LUT2)
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /out[11]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /in0[11]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /out[11]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /in0[11]
      : north_data_i_wght_inferred__0/out[11]
      : north_data_i_wght_inferred__0/in0[11]
      : north_data_i_wght_inferred/out[11]
      : north_data_i_wght_inferred/in0[11]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /out[11]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /in0[11]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /out[11]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /in0[11]
     8: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1635 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1635 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1667 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1667 /I0 (LUT2)
     2: i_2263/O (LUT5)
     3: i_2263/I3 (LUT5)
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /out[11]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /in0[11]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /out[11]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /in0[11]
      : south_data_i_iact_inferred__0/out[11]
      : south_data_i_iact_inferred__0/in0[11]
      : south_data_i_iact_inferred/out[11]
      : south_data_i_iact_inferred/in0[11]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /out[11]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /in0[11]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /out[11]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /in0[11]
     4: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1898 /O (LUT2)
     5: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1898 /I1 (LUT2)
     6: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1882 /O (LUT2)
     7: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1882 /I0 (LUT2)
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /out[11]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /in0[11]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /out[11]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /in0[11]
      : north_data_i_iact_inferred__0/out[11]
      : north_data_i_iact_inferred__0/in0[11]
      : north_data_i_iact_inferred/out[11]
      : north_data_i_iact_inferred/in0[11]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /out[11]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /in0[11]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /out[11]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /in0[11]
     8: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1667 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1667 "
Found timing loop:
     0: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2147 /O (LUT2)
     1: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2147 /I1 (LUT2)
     2: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2131 /O (LUT2)
     3: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2131 /I0 (LUT2)
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /out[11]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /in0[11]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /out[11]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /in0[11]
      : north_data_i_iact_inferred__2/out[11]
      : north_data_i_iact_inferred__2/in0[11]
      : north_data_i_iact_inferred__1/out[11]
      : north_data_i_iact_inferred__1/in0[11]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /out[11]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /in0[11]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /out[11]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /in0[11]
     4: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_2003 /O (LUT2)
     5: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_2003 /I0 (LUT2)
     6: i_2374/O (LUT5)
     7: i_2374/I3 (LUT5)
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /out[11]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /in0[11]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /out[11]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /in0[11]
      : south_data_i_iact_inferred__2/out[11]
      : south_data_i_iact_inferred__2/in0[11]
      : south_data_i_iact_inferred__1/out[11]
      : south_data_i_iact_inferred__1/in0[11]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /out[11]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /in0[11]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /out[11]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /in0[11]
     8: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2147 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I1 -to O \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2147 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1667 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1667 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Found timing loop:
     0: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1898 /O (LUT2)
     1: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1898 /I0 (LUT2)
     2: i_2333/O (LUT5)
     3: i_2333/I2 (LUT5)
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /out[11]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /in0[11]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /out[11]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /in0[11]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /out[11]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /in0[11]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /out[11]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /in0[11]
      : east_data_i_iact_inferred__2/out[11]
      : east_data_i_iact_inferred__2/in0[11]
      : east_data_i_iact_inferred__1/out[11]
      : east_data_i_iact_inferred__1/in0[11]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /out[11]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /in0[11]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /out[11]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /in0[11]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /out[11]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /in0[11]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /out[11]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /in0[11]
     4: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2147 /O (LUT2)
     5: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2147 /I0 (LUT2)
     6: i_2440/O (LUT5)
     7: i_2440/I2 (LUT5)
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred__0 /out[11]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred__0 /in0[11]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred /out[11]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred /in0[11]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred__0 /out[11]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred__0 /in0[11]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred /out[11]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred /in0[11]
      : east_data_o_iact_inferred__2/out[11]
      : east_data_o_iact_inferred__2/in0[11]
      : east_data_o_iact_inferred__1/out[11]
      : east_data_o_iact_inferred__1/in0[11]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred__0 /out[11]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred__0 /in0[11]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred /out[11]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred /in0[11]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred__0 /out[11]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred__0 /in0[11]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred /out[11]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred /in0[11]
     8: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1898 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1898 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1636 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1636 /I0 (LUT2)
     2: i_2248/O (LUT5)
     3: i_2248/I3 (LUT5)
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /out[12]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /in0[12]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /out[12]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /in0[12]
      : south_data_i_wght_inferred__0/out[12]
      : south_data_i_wght_inferred__0/in0[12]
      : south_data_i_wght_inferred/out[12]
      : south_data_i_wght_inferred/in0[12]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /out[12]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /in0[12]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /out[12]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /in0[12]
     4: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1867 /O (LUT2)
     5: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1867 /I1 (LUT2)
     6: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1851 /O (LUT2)
     7: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1851 /I0 (LUT2)
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /out[12]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /in0[12]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /out[12]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /in0[12]
      : north_data_i_wght_inferred__0/out[12]
      : north_data_i_wght_inferred__0/in0[12]
      : north_data_i_wght_inferred/out[12]
      : north_data_i_wght_inferred/in0[12]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /out[12]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /in0[12]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /out[12]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /in0[12]
     8: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1636 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1636 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1668 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1668 /I0 (LUT2)
     2: i_2264/O (LUT5)
     3: i_2264/I3 (LUT5)
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /out[12]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /in0[12]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /out[12]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /in0[12]
      : south_data_i_iact_inferred__0/out[12]
      : south_data_i_iact_inferred__0/in0[12]
      : south_data_i_iact_inferred/out[12]
      : south_data_i_iact_inferred/in0[12]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /out[12]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /in0[12]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /out[12]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /in0[12]
     4: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1899 /O (LUT2)
     5: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1899 /I1 (LUT2)
     6: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1883 /O (LUT2)
     7: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1883 /I0 (LUT2)
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /out[12]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /in0[12]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /out[12]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /in0[12]
      : north_data_i_iact_inferred__0/out[12]
      : north_data_i_iact_inferred__0/in0[12]
      : north_data_i_iact_inferred/out[12]
      : north_data_i_iact_inferred/in0[12]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /out[12]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /in0[12]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /out[12]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /in0[12]
     8: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1668 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1668 "
Found timing loop:
     0: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2148 /O (LUT2)
     1: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2148 /I1 (LUT2)
     2: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2132 /O (LUT2)
     3: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2132 /I0 (LUT2)
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /out[12]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /in0[12]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /out[12]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /in0[12]
      : north_data_i_iact_inferred__2/out[12]
      : north_data_i_iact_inferred__2/in0[12]
      : north_data_i_iact_inferred__1/out[12]
      : north_data_i_iact_inferred__1/in0[12]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /out[12]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /in0[12]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /out[12]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /in0[12]
     4: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_2004 /O (LUT2)
     5: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_2004 /I0 (LUT2)
     6: i_2375/O (LUT5)
     7: i_2375/I3 (LUT5)
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /out[12]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /in0[12]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /out[12]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /in0[12]
      : south_data_i_iact_inferred__2/out[12]
      : south_data_i_iact_inferred__2/in0[12]
      : south_data_i_iact_inferred__1/out[12]
      : south_data_i_iact_inferred__1/in0[12]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /out[12]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /in0[12]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /out[12]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /in0[12]
     8: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2148 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I1 -to O \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2148 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1668 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1668 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Found timing loop:
     0: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1899 /O (LUT2)
     1: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1899 /I0 (LUT2)
     2: i_2334/O (LUT5)
     3: i_2334/I2 (LUT5)
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /out[12]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /in0[12]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /out[12]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /in0[12]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /out[12]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /in0[12]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /out[12]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /in0[12]
      : east_data_i_iact_inferred__2/out[12]
      : east_data_i_iact_inferred__2/in0[12]
      : east_data_i_iact_inferred__1/out[12]
      : east_data_i_iact_inferred__1/in0[12]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /out[12]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /in0[12]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /out[12]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /in0[12]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /out[12]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /in0[12]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /out[12]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /in0[12]
     4: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2148 /O (LUT2)
     5: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2148 /I0 (LUT2)
     6: i_2441/O (LUT5)
     7: i_2441/I2 (LUT5)
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred__0 /out[12]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred__0 /in0[12]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred /out[12]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred /in0[12]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred__0 /out[12]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred__0 /in0[12]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred /out[12]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred /in0[12]
      : east_data_o_iact_inferred__2/out[12]
      : east_data_o_iact_inferred__2/in0[12]
      : east_data_o_iact_inferred__1/out[12]
      : east_data_o_iact_inferred__1/in0[12]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred__0 /out[12]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred__0 /in0[12]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred /out[12]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred /in0[12]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred__0 /out[12]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred__0 /in0[12]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred /out[12]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred /in0[12]
     8: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1899 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1899 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1637 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1637 /I0 (LUT2)
     2: i_2249/O (LUT5)
     3: i_2249/I2 (LUT5)
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /out[13]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /in0[13]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /out[13]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /in0[13]
      : south_data_i_wght_inferred__0/out[13]
      : south_data_i_wght_inferred__0/in0[13]
      : south_data_i_wght_inferred/out[13]
      : south_data_i_wght_inferred/in0[13]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /out[13]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /in0[13]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /out[13]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /in0[13]
     4: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1868 /O (LUT2)
     5: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1868 /I1 (LUT2)
     6: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1852 /O (LUT2)
     7: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1852 /I0 (LUT2)
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /out[13]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /in0[13]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /out[13]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /in0[13]
      : north_data_i_wght_inferred__0/out[13]
      : north_data_i_wght_inferred__0/in0[13]
      : north_data_i_wght_inferred/out[13]
      : north_data_i_wght_inferred/in0[13]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /out[13]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /in0[13]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /out[13]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /in0[13]
     8: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1637 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1637 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1669 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1669 /I0 (LUT2)
     2: i_2265/O (LUT5)
     3: i_2265/I3 (LUT5)
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /out[13]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /in0[13]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /out[13]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /in0[13]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /out[13]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /in0[13]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /out[13]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /in0[13]
      : east_data_i_iact_inferred__0/out[13]
      : east_data_i_iact_inferred__0/in0[13]
      : east_data_i_iact_inferred/out[13]
      : east_data_i_iact_inferred/in0[13]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /out[13]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /in0[13]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /out[13]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /in0[13]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /out[13]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /in0[13]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /out[13]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /in0[13]
     4: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_2005 /O (LUT2)
     5: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_2005 /I0 (LUT2)
     6: i_2376/O (LUT5)
     7: i_2376/I3 (LUT5)
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /out[13]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /in0[13]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /out[13]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /in0[13]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /out[13]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /in0[13]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /out[13]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /in0[13]
      : west_data_i_iact_inferred__0/out[13]
      : west_data_i_iact_inferred__0/in0[13]
      : west_data_i_iact_inferred/out[13]
      : west_data_i_iact_inferred/in0[13]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /out[13]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /in0[13]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /out[13]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /in0[13]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /out[13]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /in0[13]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /out[13]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /in0[13]
     8: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1669 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1669 "
Found timing loop:
     0: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_2005 /O (LUT2)
     1: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_2005 /I0 (LUT2)
     2: i_2376/O (LUT5)
     3: i_2376/I3 (LUT5)
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /out[13]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /in0[13]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /out[13]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /in0[13]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /out[13]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /in0[13]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /out[13]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /in0[13]
      : west_data_i_iact_inferred__0/out[13]
      : west_data_i_iact_inferred__0/in0[13]
      : west_data_i_iact_inferred/out[13]
      : west_data_i_iact_inferred/in0[13]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /out[13]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /in0[13]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /out[13]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /in0[13]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /out[13]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /in0[13]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /out[13]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /in0[13]
     4: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1669 /O (LUT2)
     5: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1669 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_2005 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1669 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1669 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Found timing loop:
     0: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2149 /O (LUT2)
     1: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2149 /I0 (LUT2)
     2: i_2442/O (LUT5)
     3: i_2442/I3 (LUT5)
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred__0 /out[13]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred__0 /in0[13]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred /out[13]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred /in0[13]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred__0 /out[13]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred__0 /in0[13]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred /out[13]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred /in0[13]
      : east_data_o_iact_inferred__2/out[13]
      : east_data_o_iact_inferred__2/in0[13]
      : east_data_o_iact_inferred__1/out[13]
      : east_data_o_iact_inferred__1/in0[13]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred__0 /out[13]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred__0 /in0[13]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred /out[13]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred /in0[13]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred__0 /out[13]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred__0 /in0[13]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred /out[13]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred /in0[13]
     4: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1900 /O (LUT2)
     5: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1900 /I0 (LUT2)
     6: i_2335/O (LUT5)
     7: i_2335/I3 (LUT5)
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /out[13]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /in0[13]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /out[13]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /in0[13]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /out[13]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /in0[13]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /out[13]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /in0[13]
      : east_data_i_iact_inferred__2/out[13]
      : east_data_i_iact_inferred__2/in0[13]
      : east_data_i_iact_inferred__1/out[13]
      : east_data_i_iact_inferred__1/in0[13]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /out[13]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /in0[13]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /out[13]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /in0[13]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /out[13]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /in0[13]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /out[13]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /in0[13]
     8: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2149 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2149 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1638 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1638 /I0 (LUT2)
     2: i_2250/O (LUT5)
     3: i_2250/I3 (LUT5)
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /out[14]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /in0[14]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /out[14]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /in0[14]
      : south_data_i_wght_inferred__0/out[14]
      : south_data_i_wght_inferred__0/in0[14]
      : south_data_i_wght_inferred/out[14]
      : south_data_i_wght_inferred/in0[14]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /out[14]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /in0[14]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /out[14]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /in0[14]
     4: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1869 /O (LUT2)
     5: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1869 /I1 (LUT2)
     6: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1853 /O (LUT2)
     7: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1853 /I0 (LUT2)
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /out[14]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /in0[14]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /out[14]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /in0[14]
      : north_data_i_wght_inferred__0/out[14]
      : north_data_i_wght_inferred__0/in0[14]
      : north_data_i_wght_inferred/out[14]
      : north_data_i_wght_inferred/in0[14]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /out[14]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /in0[14]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /out[14]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /in0[14]
     8: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1638 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1638 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1670 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1670 /I0 (LUT2)
     2: i_2266/O (LUT5)
     3: i_2266/I3 (LUT5)
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /out[14]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /in0[14]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /out[14]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /in0[14]
      : south_data_i_iact_inferred__0/out[14]
      : south_data_i_iact_inferred__0/in0[14]
      : south_data_i_iact_inferred/out[14]
      : south_data_i_iact_inferred/in0[14]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /out[14]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /in0[14]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /out[14]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /in0[14]
     4: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1901 /O (LUT2)
     5: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1901 /I1 (LUT2)
     6: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1885 /O (LUT2)
     7: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1885 /I0 (LUT2)
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /out[14]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /in0[14]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /out[14]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /in0[14]
      : north_data_i_iact_inferred__0/out[14]
      : north_data_i_iact_inferred__0/in0[14]
      : north_data_i_iact_inferred/out[14]
      : north_data_i_iact_inferred/in0[14]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /out[14]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /in0[14]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /out[14]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /in0[14]
     8: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1670 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1670 "
Found timing loop:
     0: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2150 /O (LUT2)
     1: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2150 /I1 (LUT2)
     2: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2134 /O (LUT2)
     3: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2134 /I0 (LUT2)
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /out[14]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /in0[14]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /out[14]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /in0[14]
      : north_data_i_iact_inferred__2/out[14]
      : north_data_i_iact_inferred__2/in0[14]
      : north_data_i_iact_inferred__1/out[14]
      : north_data_i_iact_inferred__1/in0[14]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /out[14]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /in0[14]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /out[14]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /in0[14]
     4: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_2006 /O (LUT2)
     5: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_2006 /I0 (LUT2)
     6: i_2377/O (LUT5)
     7: i_2377/I3 (LUT5)
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /out[14]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /in0[14]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /out[14]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /in0[14]
      : south_data_i_iact_inferred__2/out[14]
      : south_data_i_iact_inferred__2/in0[14]
      : south_data_i_iact_inferred__1/out[14]
      : south_data_i_iact_inferred__1/in0[14]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /out[14]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /in0[14]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /out[14]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /in0[14]
     8: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2150 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I1 -to O \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2150 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1670 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1670 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Found timing loop:
     0: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1901 /O (LUT2)
     1: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1901 /I0 (LUT2)
     2: i_2336/O (LUT5)
     3: i_2336/I2 (LUT5)
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /out[14]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /in0[14]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /out[14]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /in0[14]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /out[14]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /in0[14]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /out[14]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /in0[14]
      : east_data_i_iact_inferred__2/out[14]
      : east_data_i_iact_inferred__2/in0[14]
      : east_data_i_iact_inferred__1/out[14]
      : east_data_i_iact_inferred__1/in0[14]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /out[14]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /in0[14]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /out[14]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /in0[14]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /out[14]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /in0[14]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /out[14]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /in0[14]
     4: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2150 /O (LUT2)
     5: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2150 /I0 (LUT2)
     6: i_2443/O (LUT5)
     7: i_2443/I2 (LUT5)
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred__0 /out[14]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred__0 /in0[14]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred /out[14]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred /in0[14]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred__0 /out[14]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred__0 /in0[14]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred /out[14]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred /in0[14]
      : east_data_o_iact_inferred__2/out[14]
      : east_data_o_iact_inferred__2/in0[14]
      : east_data_o_iact_inferred__1/out[14]
      : east_data_o_iact_inferred__1/in0[14]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred__0 /out[14]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred__0 /in0[14]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred /out[14]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred /in0[14]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred__0 /out[14]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred__0 /in0[14]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred /out[14]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred /in0[14]
     8: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1901 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1901 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1639 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1639 /I0 (LUT2)
     2: i_2251/O (LUT5)
     3: i_2251/I3 (LUT5)
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /out[15]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /in0[15]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /out[15]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /in0[15]
      : south_data_i_wght_inferred__0/out[15]
      : south_data_i_wght_inferred__0/in0[15]
      : south_data_i_wght_inferred/out[15]
      : south_data_i_wght_inferred/in0[15]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /out[15]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /in0[15]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /out[15]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /in0[15]
     4: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1870 /O (LUT2)
     5: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1870 /I1 (LUT2)
     6: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1854 /O (LUT2)
     7: \HMNoC_cluster_west_1/router_cluster_0/router_wght/i_1854 /I0 (LUT2)
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /out[15]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /in0[15]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /out[15]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /in0[15]
      : north_data_i_wght_inferred__0/out[15]
      : north_data_i_wght_inferred__0/in0[15]
      : north_data_i_wght_inferred/out[15]
      : north_data_i_wght_inferred/in0[15]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /out[15]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /in0[15]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /out[15]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /in0[15]
     8: \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1639 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_wght/i_1639 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1671 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1671 /I0 (LUT2)
     2: i_2267/O (LUT5)
     3: i_2267/I3 (LUT5)
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /out[15]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /in0[15]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /out[15]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /in0[15]
      : south_data_i_iact_inferred__0/out[15]
      : south_data_i_iact_inferred__0/in0[15]
      : south_data_i_iact_inferred/out[15]
      : south_data_i_iact_inferred/in0[15]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /out[15]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /in0[15]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /out[15]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /in0[15]
     4: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1902 /O (LUT2)
     5: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1902 /I1 (LUT2)
     6: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1886 /O (LUT2)
     7: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1886 /I0 (LUT2)
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /out[15]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /in0[15]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /out[15]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /in0[15]
      : north_data_i_iact_inferred__0/out[15]
      : north_data_i_iact_inferred__0/in0[15]
      : north_data_i_iact_inferred/out[15]
      : north_data_i_iact_inferred/in0[15]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /out[15]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /in0[15]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /out[15]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /in0[15]
     8: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1671 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1671 "
Found timing loop:
     0: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2151 /O (LUT2)
     1: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2151 /I1 (LUT2)
     2: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2135 /O (LUT2)
     3: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2135 /I0 (LUT2)
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /out[15]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /in0[15]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /out[15]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /in0[15]
      : north_data_i_iact_inferred__2/out[15]
      : north_data_i_iact_inferred__2/in0[15]
      : north_data_i_iact_inferred__1/out[15]
      : north_data_i_iact_inferred__1/in0[15]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /out[15]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /in0[15]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /out[15]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /in0[15]
     4: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_2007 /O (LUT2)
     5: \HMNoC_cluster_east_0/router_cluster_0/router_iact/i_2007 /I0 (LUT2)
     6: i_2378/O (LUT5)
     7: i_2378/I3 (LUT5)
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /out[15]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /in0[15]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /out[15]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /in0[15]
      : south_data_i_iact_inferred__2/out[15]
      : south_data_i_iact_inferred__2/in0[15]
      : south_data_i_iact_inferred__1/out[15]
      : south_data_i_iact_inferred__1/in0[15]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /out[15]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /in0[15]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /out[15]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /in0[15]
     8: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2151 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I1 -to O \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2151 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1671 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_iact/i_1671 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Found timing loop:
     0: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1902 /O (LUT2)
     1: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1902 /I0 (LUT2)
     2: i_2337/O (LUT5)
     3: i_2337/I2 (LUT5)
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /out[15]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /in0[15]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /out[15]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /in0[15]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /out[15]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /in0[15]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /out[15]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /in0[15]
      : east_data_i_iact_inferred__2/out[15]
      : east_data_i_iact_inferred__2/in0[15]
      : east_data_i_iact_inferred__1/out[15]
      : east_data_i_iact_inferred__1/in0[15]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /out[15]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /in0[15]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /out[15]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /in0[15]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /out[15]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /in0[15]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /out[15]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /in0[15]
     4: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2151 /O (LUT2)
     5: \HMNoC_cluster_east_1/router_cluster_0/router_iact/i_2151 /I0 (LUT2)
     6: i_2444/O (LUT5)
     7: i_2444/I2 (LUT5)
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred__0 /out[15]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred__0 /in0[15]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred /out[15]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_i_iact_inferred /in0[15]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred__0 /out[15]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred__0 /in0[15]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred /out[15]
      : \HMNoC_cluster_east_1/west_data_i_iact_inferred /in0[15]
      : east_data_o_iact_inferred__2/out[15]
      : east_data_o_iact_inferred__2/in0[15]
      : east_data_o_iact_inferred__1/out[15]
      : east_data_o_iact_inferred__1/in0[15]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred__0 /out[15]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred__0 /in0[15]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred /out[15]
      : \HMNoC_cluster_west_1/east_data_o_iact_inferred /in0[15]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred__0 /out[15]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred__0 /in0[15]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred /out[15]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_iact_inferred /in0[15]
     8: \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1902 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_1/router_cluster_0/router_iact/i_1902 "
Found timing loop:
     0: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1919 /O (LUT2)
     1: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1919 /I1 (LUT2)
     2: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1903 /O (LUT2)
     3: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1903 /I0 (LUT2)
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /out[0]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /in0[0]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /out[0]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /in0[0]
      : north_data_i_psum_inferred__0/out[0]
      : north_data_i_psum_inferred__0/in0[0]
      : north_data_i_psum_inferred/out[0]
      : north_data_i_psum_inferred/in0[0]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /out[0]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /in0[0]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /out[0]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /in0[0]
     4: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1677 /O (LUT3)
     5: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1677 /I0 (LUT3)
     6: i_2447/O (LUT2)
     7: i_2447/I0 (LUT2)
     8: i_2268/O (LUT4)
     9: i_2268/I1 (LUT4)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[0]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[0]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[0]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[0]
      : south_data_i_psum_inferred__0/out[0]
      : south_data_i_psum_inferred__0/in0[0]
      : south_data_i_psum_inferred/out[0]
      : south_data_i_psum_inferred/in0[0]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[0]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[0]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[0]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[0]
    10: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1919 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I1 -to O \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1919 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1677 /O (LUT3)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1677 /I0 (LUT3)
     2: i_2447/O (LUT2)
     3: i_2447/I0 (LUT2)
     4: i_2268/O (LUT4)
     5: i_2268/I1 (LUT4)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[0]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[0]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[0]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[0]
      : south_data_i_psum_inferred__0/out[0]
      : south_data_i_psum_inferred__0/in0[0]
      : south_data_i_psum_inferred/out[0]
      : south_data_i_psum_inferred/in0[0]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[0]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[0]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[0]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[0]
     6: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1919 /O (LUT2)
     7: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1919 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1677 "
Found timing loop:
     0: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2024 /O (LUT2)
     1: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2024 /I0 (LUT2)
     2: i_2379/O (LUT5)
     3: i_2379/I3 (LUT5)
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[0]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[0]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[0]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[0]
      : west_data_i_psum_inferred__0/out[0]
      : west_data_i_psum_inferred__0/in0[0]
      : west_data_i_psum_inferred/out[0]
      : west_data_i_psum_inferred/in0[0]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[0]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[0]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[0]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[0]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[0]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[0]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[0]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[0]
     4: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1677 /O (LUT3)
     5: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1677 /O (LUT3)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2024 "
Found timing loop:
     0: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1919 /O (LUT2)
     1: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1919 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Found timing loop:
     0: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2025 /O (LUT2)
     1: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2025 /I0 (LUT2)
     2: i_2380/O (LUT5)
     3: i_2380/I3 (LUT5)
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[1]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[1]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[1]
      : south_data_i_psum_inferred__2/out[1]
      : south_data_i_psum_inferred__2/in0[1]
      : south_data_i_psum_inferred__1/out[1]
      : south_data_i_psum_inferred__1/in0[1]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[1]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[1]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[1]
     4: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2057 /O (LUT2)
     5: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2057 /I1 (LUT2)
     6: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2041 /O (LUT2)
     7: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2041 /I0 (LUT2)
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /out[1]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /out[1]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /in0[1]
      : south_data_o_psum_inferred__2/out[1]
      : south_data_o_psum_inferred__2/in0[1]
      : south_data_o_psum_inferred__1/out[1]
      : south_data_o_psum_inferred__1/in0[1]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[1]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[1]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[1]
     8: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2025 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2025 "
Found timing loop:
     0: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2025 /O (LUT2)
     1: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2025 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Found timing loop:
     0: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1920 /O (LUT2)
     1: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1920 /I1 (LUT2)
     2: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1904 /O (LUT2)
     3: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1904 /I0 (LUT2)
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /out[1]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /out[1]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /in0[1]
      : north_data_i_psum_inferred__0/out[1]
      : north_data_i_psum_inferred__0/in0[1]
      : north_data_i_psum_inferred/out[1]
      : north_data_i_psum_inferred/in0[1]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /out[1]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /out[1]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /in0[1]
     4: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1678 /O (LUT3)
     5: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1678 /I0 (LUT3)
     6: i_2448/O (LUT2)
     7: i_2448/I0 (LUT2)
     8: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1672 /O (LUT4)
     9: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1672 /I1 (LUT4)
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /out[1]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /out[1]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /in0[1]
      : east_data_i_psum_inferred__0/out[1]
      : east_data_i_psum_inferred__0/in0[1]
      : east_data_i_psum_inferred/out[1]
      : east_data_i_psum_inferred/in0[1]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /out[1]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /out[1]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /in0[1]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /out[1]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /out[1]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /in0[1]
    10: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2025 /O (LUT2)
    11: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2025 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I1 -to O \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1920 "
Found timing loop:
     0: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2057 /O (LUT2)
     1: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2057 /I0 (LUT2)
     2: i_2396/O (LUT5)
     3: i_2396/I2 (LUT5)
      : \HMNoC_cluster_east_1/west_data_i_psum_inferred__0 /out[1]
      : \HMNoC_cluster_east_1/west_data_i_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_east_1/west_data_i_psum_inferred /out[1]
      : \HMNoC_cluster_east_1/west_data_i_psum_inferred /in0[1]
      : west_data_i_psum_inferred__2/out[1]
      : west_data_i_psum_inferred__2/in0[1]
      : west_data_i_psum_inferred__1/out[1]
      : west_data_i_psum_inferred__1/in0[1]
      : \HMNoC_cluster_west_1/east_data_o_psum_inferred__0 /out[1]
      : \HMNoC_cluster_west_1/east_data_o_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_west_1/east_data_o_psum_inferred /out[1]
      : \HMNoC_cluster_west_1/east_data_o_psum_inferred /in0[1]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_psum_inferred__0 /out[1]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_psum_inferred /out[1]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_psum_inferred /in0[1]
     4: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1920 /O (LUT2)
     5: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1920 /I0 (LUT2)
     6: i_2339/O (LUT5)
     7: i_2339/I2 (LUT5)
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred__0 /out[1]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred /out[1]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred /in0[1]
      : east_data_i_psum_inferred__2/out[1]
      : east_data_i_psum_inferred__2/in0[1]
      : east_data_i_psum_inferred__1/out[1]
      : east_data_i_psum_inferred__1/in0[1]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred__0 /out[1]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred /out[1]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred /in0[1]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred__0 /out[1]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred /out[1]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred /in0[1]
     8: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2057 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2057 "
Found timing loop:
     0: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1921 /O (LUT2)
     1: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1921 /I1 (LUT2)
     2: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1905 /O (LUT2)
     3: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1905 /I0 (LUT2)
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /out[2]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /in0[2]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /out[2]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /in0[2]
      : north_data_i_psum_inferred__0/out[2]
      : north_data_i_psum_inferred__0/in0[2]
      : north_data_i_psum_inferred/out[2]
      : north_data_i_psum_inferred/in0[2]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /out[2]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /in0[2]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /out[2]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /in0[2]
     4: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1679 /O (LUT3)
     5: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1679 /I0 (LUT3)
     6: i_2449/O (LUT2)
     7: i_2449/I0 (LUT2)
     8: i_2269/O (LUT4)
     9: i_2269/I1 (LUT4)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[2]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[2]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[2]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[2]
      : south_data_i_psum_inferred__0/out[2]
      : south_data_i_psum_inferred__0/in0[2]
      : south_data_i_psum_inferred/out[2]
      : south_data_i_psum_inferred/in0[2]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[2]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[2]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[2]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[2]
    10: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1921 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I1 -to O \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1921 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1679 /O (LUT3)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1679 /I0 (LUT3)
     2: i_2449/O (LUT2)
     3: i_2449/I0 (LUT2)
     4: i_2269/O (LUT4)
     5: i_2269/I1 (LUT4)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[2]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[2]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[2]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[2]
      : south_data_i_psum_inferred__0/out[2]
      : south_data_i_psum_inferred__0/in0[2]
      : south_data_i_psum_inferred/out[2]
      : south_data_i_psum_inferred/in0[2]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[2]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[2]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[2]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[2]
     6: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1921 /O (LUT2)
     7: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1921 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1679 "
Found timing loop:
     0: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2026 /O (LUT2)
     1: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2026 /I0 (LUT2)
     2: i_2381/O (LUT5)
     3: i_2381/I3 (LUT5)
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[2]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[2]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[2]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[2]
      : west_data_i_psum_inferred__0/out[2]
      : west_data_i_psum_inferred__0/in0[2]
      : west_data_i_psum_inferred/out[2]
      : west_data_i_psum_inferred/in0[2]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[2]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[2]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[2]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[2]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[2]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[2]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[2]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[2]
     4: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1679 /O (LUT3)
     5: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1679 /O (LUT3)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2026 "
Found timing loop:
     0: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1921 /O (LUT2)
     1: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1921 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Found timing loop:
     0: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2027 /O (LUT2)
     1: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2027 /I0 (LUT2)
     2: i_2382/O (LUT5)
     3: i_2382/I3 (LUT5)
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[3]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[3]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[3]
      : south_data_i_psum_inferred__2/out[3]
      : south_data_i_psum_inferred__2/in0[3]
      : south_data_i_psum_inferred__1/out[3]
      : south_data_i_psum_inferred__1/in0[3]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[3]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[3]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[3]
     4: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2059 /O (LUT2)
     5: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2059 /I1 (LUT2)
     6: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2043 /O (LUT2)
     7: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2043 /I0 (LUT2)
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /out[3]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /out[3]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /in0[3]
      : south_data_o_psum_inferred__2/out[3]
      : south_data_o_psum_inferred__2/in0[3]
      : south_data_o_psum_inferred__1/out[3]
      : south_data_o_psum_inferred__1/in0[3]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[3]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[3]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[3]
     8: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2027 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2027 "
Found timing loop:
     0: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2027 /O (LUT2)
     1: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2027 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Found timing loop:
     0: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1922 /O (LUT2)
     1: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1922 /I1 (LUT2)
     2: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1906 /O (LUT2)
     3: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1906 /I0 (LUT2)
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /out[3]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /out[3]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /in0[3]
      : north_data_i_psum_inferred__0/out[3]
      : north_data_i_psum_inferred__0/in0[3]
      : north_data_i_psum_inferred/out[3]
      : north_data_i_psum_inferred/in0[3]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /out[3]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /out[3]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /in0[3]
     4: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1680 /O (LUT3)
     5: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1680 /I0 (LUT3)
     6: i_2450/O (LUT2)
     7: i_2450/I0 (LUT2)
     8: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1673 /O (LUT4)
     9: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1673 /I1 (LUT4)
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /out[3]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /out[3]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /in0[3]
      : east_data_i_psum_inferred__0/out[3]
      : east_data_i_psum_inferred__0/in0[3]
      : east_data_i_psum_inferred/out[3]
      : east_data_i_psum_inferred/in0[3]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /out[3]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /out[3]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /in0[3]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /out[3]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /out[3]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /in0[3]
    10: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2027 /O (LUT2)
    11: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2027 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I1 -to O \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1922 "
Found timing loop:
     0: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2059 /O (LUT2)
     1: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2059 /I0 (LUT2)
     2: i_2398/O (LUT5)
     3: i_2398/I2 (LUT5)
      : \HMNoC_cluster_east_1/west_data_i_psum_inferred__0 /out[3]
      : \HMNoC_cluster_east_1/west_data_i_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_east_1/west_data_i_psum_inferred /out[3]
      : \HMNoC_cluster_east_1/west_data_i_psum_inferred /in0[3]
      : west_data_i_psum_inferred__2/out[3]
      : west_data_i_psum_inferred__2/in0[3]
      : west_data_i_psum_inferred__1/out[3]
      : west_data_i_psum_inferred__1/in0[3]
      : \HMNoC_cluster_west_1/east_data_o_psum_inferred__0 /out[3]
      : \HMNoC_cluster_west_1/east_data_o_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_west_1/east_data_o_psum_inferred /out[3]
      : \HMNoC_cluster_west_1/east_data_o_psum_inferred /in0[3]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_psum_inferred__0 /out[3]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_psum_inferred /out[3]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_psum_inferred /in0[3]
     4: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1922 /O (LUT2)
     5: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1922 /I0 (LUT2)
     6: i_2341/O (LUT5)
     7: i_2341/I2 (LUT5)
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred__0 /out[3]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred /out[3]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred /in0[3]
      : east_data_i_psum_inferred__2/out[3]
      : east_data_i_psum_inferred__2/in0[3]
      : east_data_i_psum_inferred__1/out[3]
      : east_data_i_psum_inferred__1/in0[3]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred__0 /out[3]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred /out[3]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred /in0[3]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred__0 /out[3]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred /out[3]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred /in0[3]
     8: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2059 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2059 "
Found timing loop:
     0: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1923 /O (LUT2)
     1: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1923 /I1 (LUT2)
     2: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1907 /O (LUT2)
     3: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1907 /I0 (LUT2)
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /out[4]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /in0[4]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /out[4]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /in0[4]
      : north_data_i_psum_inferred__0/out[4]
      : north_data_i_psum_inferred__0/in0[4]
      : north_data_i_psum_inferred/out[4]
      : north_data_i_psum_inferred/in0[4]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /out[4]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /in0[4]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /out[4]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /in0[4]
     4: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1681 /O (LUT3)
     5: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1681 /I0 (LUT3)
     6: i_2451/O (LUT2)
     7: i_2451/I0 (LUT2)
     8: i_2270/O (LUT4)
     9: i_2270/I1 (LUT4)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[4]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[4]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[4]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[4]
      : south_data_i_psum_inferred__0/out[4]
      : south_data_i_psum_inferred__0/in0[4]
      : south_data_i_psum_inferred/out[4]
      : south_data_i_psum_inferred/in0[4]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[4]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[4]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[4]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[4]
    10: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1923 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I1 -to O \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1923 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1681 /O (LUT3)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1681 /I0 (LUT3)
     2: i_2451/O (LUT2)
     3: i_2451/I0 (LUT2)
     4: i_2270/O (LUT4)
     5: i_2270/I1 (LUT4)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[4]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[4]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[4]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[4]
      : south_data_i_psum_inferred__0/out[4]
      : south_data_i_psum_inferred__0/in0[4]
      : south_data_i_psum_inferred/out[4]
      : south_data_i_psum_inferred/in0[4]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[4]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[4]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[4]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[4]
     6: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1923 /O (LUT2)
     7: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1923 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1681 "
Found timing loop:
     0: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2028 /O (LUT2)
     1: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2028 /I0 (LUT2)
     2: i_2383/O (LUT5)
     3: i_2383/I3 (LUT5)
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[4]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[4]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[4]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[4]
      : west_data_i_psum_inferred__0/out[4]
      : west_data_i_psum_inferred__0/in0[4]
      : west_data_i_psum_inferred/out[4]
      : west_data_i_psum_inferred/in0[4]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[4]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[4]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[4]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[4]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[4]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[4]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[4]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[4]
     4: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1681 /O (LUT3)
     5: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1681 /O (LUT3)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2028 "
Found timing loop:
     0: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1923 /O (LUT2)
     1: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1923 /O (LUT2)
CRITICAL WARNING: [Synth 8-295] found timing loop. [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/HMNoC_top.sv:23]
INFO: [Common 17-14] Message 'Synth 8-295' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Found timing loop:
     0: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1924 /O (LUT2)
     1: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1924 /I1 (LUT2)
     2: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1908 /O (LUT2)
     3: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1908 /I0 (LUT2)
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /out[5]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /in0[5]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /out[5]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /in0[5]
      : north_data_i_psum_inferred__0/out[5]
      : north_data_i_psum_inferred__0/in0[5]
      : north_data_i_psum_inferred/out[5]
      : north_data_i_psum_inferred/in0[5]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /out[5]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /in0[5]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /out[5]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /in0[5]
     4: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1682 /O (LUT3)
     5: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1682 /I0 (LUT3)
     6: i_2452/O (LUT2)
     7: i_2452/I0 (LUT2)
     8: i_2271/O (LUT4)
     9: i_2271/I1 (LUT4)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[5]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[5]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[5]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[5]
      : south_data_i_psum_inferred__0/out[5]
      : south_data_i_psum_inferred__0/in0[5]
      : south_data_i_psum_inferred/out[5]
      : south_data_i_psum_inferred/in0[5]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[5]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[5]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[5]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[5]
    10: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1924 /O (LUT2)
Inferred a: "set_disable_timing -from I1 -to O \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1924 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1682 /O (LUT3)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1682 /I0 (LUT3)
     2: i_2452/O (LUT2)
     3: i_2452/I0 (LUT2)
     4: i_2271/O (LUT4)
     5: i_2271/I1 (LUT4)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[5]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[5]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[5]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[5]
      : south_data_i_psum_inferred__0/out[5]
      : south_data_i_psum_inferred__0/in0[5]
      : south_data_i_psum_inferred/out[5]
      : south_data_i_psum_inferred/in0[5]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[5]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[5]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[5]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[5]
     6: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1924 /O (LUT2)
     7: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1924 /O (LUT2)
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1682 "
Found timing loop:
     0: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2029 /O (LUT2)
     1: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2029 /I0 (LUT2)
     2: i_2384/O (LUT5)
     3: i_2384/I3 (LUT5)
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[5]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[5]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[5]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[5]
      : west_data_i_psum_inferred__0/out[5]
      : west_data_i_psum_inferred__0/in0[5]
      : west_data_i_psum_inferred/out[5]
      : west_data_i_psum_inferred/in0[5]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[5]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[5]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[5]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[5]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[5]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[5]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[5]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[5]
     4: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1682 /O (LUT3)
     5: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1682 /O (LUT3)
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2029 "
Found timing loop:
     0: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1924 /O (LUT2)
     1: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1924 /O (LUT2)
Found timing loop:
     0: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1925 /O (LUT2)
     1: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1925 /I1 (LUT2)
     2: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1909 /O (LUT2)
     3: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1909 /I0 (LUT2)
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /out[6]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /in0[6]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /out[6]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /in0[6]
      : north_data_i_psum_inferred__0/out[6]
      : north_data_i_psum_inferred__0/in0[6]
      : north_data_i_psum_inferred/out[6]
      : north_data_i_psum_inferred/in0[6]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /out[6]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /in0[6]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /out[6]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /in0[6]
     4: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1683 /O (LUT3)
     5: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1683 /I0 (LUT3)
     6: i_2453/O (LUT2)
     7: i_2453/I0 (LUT2)
     8: i_2272/O (LUT4)
     9: i_2272/I1 (LUT4)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[6]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[6]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[6]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[6]
      : south_data_i_psum_inferred__0/out[6]
      : south_data_i_psum_inferred__0/in0[6]
      : south_data_i_psum_inferred/out[6]
      : south_data_i_psum_inferred/in0[6]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[6]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[6]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[6]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[6]
    10: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1925 /O (LUT2)
Inferred a: "set_disable_timing -from I1 -to O \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1925 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1683 /O (LUT3)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1683 /I0 (LUT3)
     2: i_2453/O (LUT2)
     3: i_2453/I0 (LUT2)
     4: i_2272/O (LUT4)
     5: i_2272/I1 (LUT4)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[6]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[6]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[6]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[6]
      : south_data_i_psum_inferred__0/out[6]
      : south_data_i_psum_inferred__0/in0[6]
      : south_data_i_psum_inferred/out[6]
      : south_data_i_psum_inferred/in0[6]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[6]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[6]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[6]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[6]
     6: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1925 /O (LUT2)
     7: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1925 /O (LUT2)
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1683 "
Found timing loop:
     0: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2030 /O (LUT2)
     1: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2030 /I0 (LUT2)
     2: i_2385/O (LUT5)
     3: i_2385/I3 (LUT5)
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[6]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[6]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[6]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[6]
      : west_data_i_psum_inferred__0/out[6]
      : west_data_i_psum_inferred__0/in0[6]
      : west_data_i_psum_inferred/out[6]
      : west_data_i_psum_inferred/in0[6]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[6]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[6]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[6]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[6]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[6]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[6]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[6]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[6]
     4: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1683 /O (LUT3)
     5: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1683 /O (LUT3)
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2030 "
Found timing loop:
     0: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1925 /O (LUT2)
     1: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1925 /O (LUT2)
Found timing loop:
     0: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2031 /O (LUT2)
     1: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2031 /I0 (LUT2)
     2: i_2386/O (LUT5)
     3: i_2386/I3 (LUT5)
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[7]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[7]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[7]
      : south_data_i_psum_inferred__2/out[7]
      : south_data_i_psum_inferred__2/in0[7]
      : south_data_i_psum_inferred__1/out[7]
      : south_data_i_psum_inferred__1/in0[7]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[7]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[7]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[7]
     4: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2063 /O (LUT2)
     5: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2063 /I1 (LUT2)
     6: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2047 /O (LUT2)
     7: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2047 /I0 (LUT2)
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /out[7]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /out[7]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /in0[7]
      : south_data_o_psum_inferred__2/out[7]
      : south_data_o_psum_inferred__2/in0[7]
      : south_data_o_psum_inferred__1/out[7]
      : south_data_o_psum_inferred__1/in0[7]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[7]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[7]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[7]
     8: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2031 /O (LUT2)
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2031 "
Found timing loop:
     0: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2031 /O (LUT2)
     1: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2031 /O (LUT2)
Found timing loop:
     0: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1926 /O (LUT2)
     1: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1926 /I1 (LUT2)
     2: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1910 /O (LUT2)
     3: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1910 /I0 (LUT2)
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /out[7]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /out[7]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /in0[7]
      : north_data_i_psum_inferred__0/out[7]
      : north_data_i_psum_inferred__0/in0[7]
      : north_data_i_psum_inferred/out[7]
      : north_data_i_psum_inferred/in0[7]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /out[7]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /out[7]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /in0[7]
     4: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1684 /O (LUT3)
     5: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1684 /I0 (LUT3)
     6: i_2454/O (LUT2)
     7: i_2454/I0 (LUT2)
     8: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1674 /O (LUT4)
     9: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1674 /I1 (LUT4)
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /out[7]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /out[7]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /in0[7]
      : east_data_i_psum_inferred__0/out[7]
      : east_data_i_psum_inferred__0/in0[7]
      : east_data_i_psum_inferred/out[7]
      : east_data_i_psum_inferred/in0[7]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /out[7]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /out[7]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /in0[7]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /out[7]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /out[7]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /in0[7]
    10: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2031 /O (LUT2)
    11: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2031 /O (LUT2)
Inferred a: "set_disable_timing -from I1 -to O \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1926 "
Found timing loop:
     0: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2063 /O (LUT2)
     1: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2063 /I0 (LUT2)
     2: i_2402/O (LUT5)
     3: i_2402/I2 (LUT5)
      : \HMNoC_cluster_east_1/west_data_i_psum_inferred__0 /out[7]
      : \HMNoC_cluster_east_1/west_data_i_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_east_1/west_data_i_psum_inferred /out[7]
      : \HMNoC_cluster_east_1/west_data_i_psum_inferred /in0[7]
      : west_data_i_psum_inferred__2/out[7]
      : west_data_i_psum_inferred__2/in0[7]
      : west_data_i_psum_inferred__1/out[7]
      : west_data_i_psum_inferred__1/in0[7]
      : \HMNoC_cluster_west_1/east_data_o_psum_inferred__0 /out[7]
      : \HMNoC_cluster_west_1/east_data_o_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_west_1/east_data_o_psum_inferred /out[7]
      : \HMNoC_cluster_west_1/east_data_o_psum_inferred /in0[7]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_psum_inferred__0 /out[7]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_psum_inferred /out[7]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_psum_inferred /in0[7]
     4: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1926 /O (LUT2)
     5: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1926 /I0 (LUT2)
     6: i_2345/O (LUT5)
     7: i_2345/I2 (LUT5)
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred__0 /out[7]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred /out[7]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred /in0[7]
      : east_data_i_psum_inferred__2/out[7]
      : east_data_i_psum_inferred__2/in0[7]
      : east_data_i_psum_inferred__1/out[7]
      : east_data_i_psum_inferred__1/in0[7]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred__0 /out[7]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred /out[7]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred /in0[7]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred__0 /out[7]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred /out[7]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred /in0[7]
     8: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2063 /O (LUT2)
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2063 "
Found timing loop:
     0: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1927 /O (LUT2)
     1: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1927 /I1 (LUT2)
     2: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1911 /O (LUT2)
     3: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1911 /I0 (LUT2)
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /out[8]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /in0[8]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /out[8]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /in0[8]
      : north_data_i_psum_inferred__0/out[8]
      : north_data_i_psum_inferred__0/in0[8]
      : north_data_i_psum_inferred/out[8]
      : north_data_i_psum_inferred/in0[8]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /out[8]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /in0[8]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /out[8]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /in0[8]
     4: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1685 /O (LUT3)
     5: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1685 /I0 (LUT3)
     6: i_2455/O (LUT2)
     7: i_2455/I0 (LUT2)
     8: i_2273/O (LUT4)
     9: i_2273/I1 (LUT4)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[8]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[8]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[8]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[8]
      : south_data_i_psum_inferred__0/out[8]
      : south_data_i_psum_inferred__0/in0[8]
      : south_data_i_psum_inferred/out[8]
      : south_data_i_psum_inferred/in0[8]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[8]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[8]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[8]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[8]
    10: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1927 /O (LUT2)
Inferred a: "set_disable_timing -from I1 -to O \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1927 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1685 /O (LUT3)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1685 /I0 (LUT3)
     2: i_2455/O (LUT2)
     3: i_2455/I0 (LUT2)
     4: i_2273/O (LUT4)
     5: i_2273/I1 (LUT4)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[8]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[8]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[8]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[8]
      : south_data_i_psum_inferred__0/out[8]
      : south_data_i_psum_inferred__0/in0[8]
      : south_data_i_psum_inferred/out[8]
      : south_data_i_psum_inferred/in0[8]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[8]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[8]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[8]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[8]
     6: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1927 /O (LUT2)
     7: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1927 /O (LUT2)
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1685 "
Found timing loop:
     0: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2032 /O (LUT2)
     1: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2032 /I0 (LUT2)
     2: i_2387/O (LUT5)
     3: i_2387/I3 (LUT5)
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[8]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[8]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[8]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[8]
      : west_data_i_psum_inferred__0/out[8]
      : west_data_i_psum_inferred__0/in0[8]
      : west_data_i_psum_inferred/out[8]
      : west_data_i_psum_inferred/in0[8]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[8]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[8]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[8]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[8]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[8]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[8]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[8]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[8]
     4: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1685 /O (LUT3)
     5: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1685 /O (LUT3)
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2032 "
Found timing loop:
     0: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1927 /O (LUT2)
     1: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1927 /O (LUT2)
Found timing loop:
     0: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1928 /O (LUT2)
     1: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1928 /I1 (LUT2)
     2: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1912 /O (LUT2)
     3: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1912 /I0 (LUT2)
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /out[9]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /in0[9]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /out[9]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /in0[9]
      : north_data_i_psum_inferred__0/out[9]
      : north_data_i_psum_inferred__0/in0[9]
      : north_data_i_psum_inferred/out[9]
      : north_data_i_psum_inferred/in0[9]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /out[9]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /in0[9]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /out[9]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /in0[9]
     4: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1686 /O (LUT3)
     5: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1686 /I0 (LUT3)
     6: i_2456/O (LUT2)
     7: i_2456/I0 (LUT2)
     8: i_2274/O (LUT4)
     9: i_2274/I1 (LUT4)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[9]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[9]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[9]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[9]
      : south_data_i_psum_inferred__0/out[9]
      : south_data_i_psum_inferred__0/in0[9]
      : south_data_i_psum_inferred/out[9]
      : south_data_i_psum_inferred/in0[9]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[9]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[9]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[9]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[9]
    10: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1928 /O (LUT2)
Inferred a: "set_disable_timing -from I1 -to O \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1928 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1686 /O (LUT3)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1686 /I0 (LUT3)
     2: i_2456/O (LUT2)
     3: i_2456/I0 (LUT2)
     4: i_2274/O (LUT4)
     5: i_2274/I1 (LUT4)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[9]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[9]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[9]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[9]
      : south_data_i_psum_inferred__0/out[9]
      : south_data_i_psum_inferred__0/in0[9]
      : south_data_i_psum_inferred/out[9]
      : south_data_i_psum_inferred/in0[9]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[9]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[9]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[9]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[9]
     6: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1928 /O (LUT2)
     7: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1928 /O (LUT2)
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1686 "
Found timing loop:
     0: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2033 /O (LUT2)
     1: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2033 /I0 (LUT2)
     2: i_2388/O (LUT5)
     3: i_2388/I3 (LUT5)
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[9]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[9]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[9]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[9]
      : west_data_i_psum_inferred__0/out[9]
      : west_data_i_psum_inferred__0/in0[9]
      : west_data_i_psum_inferred/out[9]
      : west_data_i_psum_inferred/in0[9]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[9]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[9]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[9]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[9]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[9]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[9]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[9]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[9]
     4: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1686 /O (LUT3)
     5: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1686 /O (LUT3)
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2033 "
Found timing loop:
     0: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1928 /O (LUT2)
     1: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1928 /O (LUT2)
Found timing loop:
     0: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1929 /O (LUT2)
     1: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1929 /I1 (LUT2)
     2: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1913 /O (LUT2)
     3: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1913 /I0 (LUT2)
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /out[10]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /in0[10]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /out[10]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /in0[10]
      : north_data_i_psum_inferred__0/out[10]
      : north_data_i_psum_inferred__0/in0[10]
      : north_data_i_psum_inferred/out[10]
      : north_data_i_psum_inferred/in0[10]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /out[10]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /in0[10]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /out[10]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /in0[10]
     4: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1687 /O (LUT3)
     5: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1687 /I0 (LUT3)
     6: i_2457/O (LUT2)
     7: i_2457/I0 (LUT2)
     8: i_2275/O (LUT4)
     9: i_2275/I1 (LUT4)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[10]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[10]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[10]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[10]
      : south_data_i_psum_inferred__0/out[10]
      : south_data_i_psum_inferred__0/in0[10]
      : south_data_i_psum_inferred/out[10]
      : south_data_i_psum_inferred/in0[10]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[10]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[10]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[10]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[10]
    10: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1929 /O (LUT2)
Inferred a: "set_disable_timing -from I1 -to O \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1929 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1687 /O (LUT3)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1687 /I0 (LUT3)
     2: i_2457/O (LUT2)
     3: i_2457/I0 (LUT2)
     4: i_2275/O (LUT4)
     5: i_2275/I1 (LUT4)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[10]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[10]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[10]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[10]
      : south_data_i_psum_inferred__0/out[10]
      : south_data_i_psum_inferred__0/in0[10]
      : south_data_i_psum_inferred/out[10]
      : south_data_i_psum_inferred/in0[10]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[10]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[10]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[10]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[10]
     6: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1929 /O (LUT2)
     7: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1929 /O (LUT2)
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1687 "
Found timing loop:
     0: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2034 /O (LUT2)
     1: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2034 /I0 (LUT2)
     2: i_2389/O (LUT5)
     3: i_2389/I3 (LUT5)
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[10]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[10]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[10]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[10]
      : west_data_i_psum_inferred__0/out[10]
      : west_data_i_psum_inferred__0/in0[10]
      : west_data_i_psum_inferred/out[10]
      : west_data_i_psum_inferred/in0[10]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[10]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[10]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[10]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[10]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[10]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[10]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[10]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[10]
     4: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1687 /O (LUT3)
     5: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1687 /O (LUT3)
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2034 "
Found timing loop:
     0: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1929 /O (LUT2)
     1: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1929 /O (LUT2)
Found timing loop:
     0: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2035 /O (LUT2)
     1: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2035 /I0 (LUT2)
     2: i_2390/O (LUT5)
     3: i_2390/I3 (LUT5)
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[11]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[11]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[11]
      : south_data_i_psum_inferred__2/out[11]
      : south_data_i_psum_inferred__2/in0[11]
      : south_data_i_psum_inferred__1/out[11]
      : south_data_i_psum_inferred__1/in0[11]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[11]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[11]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[11]
     4: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2067 /O (LUT2)
     5: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2067 /I1 (LUT2)
     6: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2051 /O (LUT2)
     7: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2051 /I0 (LUT2)
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /out[11]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /out[11]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /in0[11]
      : south_data_o_psum_inferred__2/out[11]
      : south_data_o_psum_inferred__2/in0[11]
      : south_data_o_psum_inferred__1/out[11]
      : south_data_o_psum_inferred__1/in0[11]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[11]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[11]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[11]
     8: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2035 /O (LUT2)
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2035 "
Found timing loop:
     0: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2035 /O (LUT2)
     1: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2035 /O (LUT2)
Found timing loop:
     0: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1930 /O (LUT2)
     1: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1930 /I1 (LUT2)
     2: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1914 /O (LUT2)
     3: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1914 /I0 (LUT2)
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /out[11]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /out[11]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /in0[11]
      : north_data_i_psum_inferred__0/out[11]
      : north_data_i_psum_inferred__0/in0[11]
      : north_data_i_psum_inferred/out[11]
      : north_data_i_psum_inferred/in0[11]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /out[11]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /out[11]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /in0[11]
     4: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1688 /O (LUT3)
     5: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1688 /I0 (LUT3)
     6: i_2458/O (LUT2)
     7: i_2458/I0 (LUT2)
     8: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1675 /O (LUT4)
     9: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1675 /I1 (LUT4)
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /out[11]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /out[11]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /in0[11]
      : east_data_i_psum_inferred__0/out[11]
      : east_data_i_psum_inferred__0/in0[11]
      : east_data_i_psum_inferred/out[11]
      : east_data_i_psum_inferred/in0[11]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /out[11]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /out[11]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /in0[11]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /out[11]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /out[11]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /in0[11]
    10: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2035 /O (LUT2)
    11: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2035 /O (LUT2)
Inferred a: "set_disable_timing -from I1 -to O \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1930 "
Found timing loop:
     0: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2067 /O (LUT2)
     1: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2067 /I0 (LUT2)
     2: i_2406/O (LUT5)
     3: i_2406/I2 (LUT5)
      : \HMNoC_cluster_east_1/west_data_i_psum_inferred__0 /out[11]
      : \HMNoC_cluster_east_1/west_data_i_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_east_1/west_data_i_psum_inferred /out[11]
      : \HMNoC_cluster_east_1/west_data_i_psum_inferred /in0[11]
      : west_data_i_psum_inferred__2/out[11]
      : west_data_i_psum_inferred__2/in0[11]
      : west_data_i_psum_inferred__1/out[11]
      : west_data_i_psum_inferred__1/in0[11]
      : \HMNoC_cluster_west_1/east_data_o_psum_inferred__0 /out[11]
      : \HMNoC_cluster_west_1/east_data_o_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_west_1/east_data_o_psum_inferred /out[11]
      : \HMNoC_cluster_west_1/east_data_o_psum_inferred /in0[11]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_psum_inferred__0 /out[11]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_psum_inferred /out[11]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_psum_inferred /in0[11]
     4: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1930 /O (LUT2)
     5: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1930 /I0 (LUT2)
     6: i_2349/O (LUT5)
     7: i_2349/I2 (LUT5)
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred__0 /out[11]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred /out[11]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred /in0[11]
      : east_data_i_psum_inferred__2/out[11]
      : east_data_i_psum_inferred__2/in0[11]
      : east_data_i_psum_inferred__1/out[11]
      : east_data_i_psum_inferred__1/in0[11]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred__0 /out[11]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred /out[11]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred /in0[11]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred__0 /out[11]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred /out[11]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred /in0[11]
     8: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2067 /O (LUT2)
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2067 "
Found timing loop:
     0: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2036 /O (LUT2)
     1: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2036 /I0 (LUT2)
     2: i_2391/O (LUT5)
     3: i_2391/I3 (LUT5)
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[12]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[12]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[12]
      : south_data_i_psum_inferred__2/out[12]
      : south_data_i_psum_inferred__2/in0[12]
      : south_data_i_psum_inferred__1/out[12]
      : south_data_i_psum_inferred__1/in0[12]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[12]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[12]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[12]
     4: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2068 /O (LUT2)
     5: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2068 /I1 (LUT2)
     6: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2052 /O (LUT2)
     7: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2052 /I0 (LUT2)
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /out[12]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /out[12]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /in0[12]
      : south_data_o_psum_inferred__2/out[12]
      : south_data_o_psum_inferred__2/in0[12]
      : south_data_o_psum_inferred__1/out[12]
      : south_data_o_psum_inferred__1/in0[12]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[12]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[12]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[12]
     8: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2036 /O (LUT2)
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2036 "
Found timing loop:
     0: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2036 /O (LUT2)
     1: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2036 /O (LUT2)
Found timing loop:
     0: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1931 /O (LUT2)
     1: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1931 /I1 (LUT2)
     2: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1915 /O (LUT2)
     3: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1915 /I0 (LUT2)
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /out[12]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /out[12]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /in0[12]
      : north_data_i_psum_inferred__0/out[12]
      : north_data_i_psum_inferred__0/in0[12]
      : north_data_i_psum_inferred/out[12]
      : north_data_i_psum_inferred/in0[12]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /out[12]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /out[12]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /in0[12]
     4: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1689 /O (LUT3)
     5: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1689 /I0 (LUT3)
     6: i_2459/O (LUT2)
     7: i_2459/I0 (LUT2)
     8: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1676 /O (LUT4)
     9: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1676 /I1 (LUT4)
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /out[12]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /out[12]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /in0[12]
      : east_data_i_psum_inferred__0/out[12]
      : east_data_i_psum_inferred__0/in0[12]
      : east_data_i_psum_inferred/out[12]
      : east_data_i_psum_inferred/in0[12]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /out[12]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /out[12]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /in0[12]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /out[12]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /out[12]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /in0[12]
    10: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2036 /O (LUT2)
    11: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2036 /O (LUT2)
Inferred a: "set_disable_timing -from I1 -to O \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1931 "
Found timing loop:
     0: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2068 /O (LUT2)
     1: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2068 /I0 (LUT2)
     2: i_2407/O (LUT5)
     3: i_2407/I2 (LUT5)
      : \HMNoC_cluster_east_1/west_data_i_psum_inferred__0 /out[12]
      : \HMNoC_cluster_east_1/west_data_i_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_east_1/west_data_i_psum_inferred /out[12]
      : \HMNoC_cluster_east_1/west_data_i_psum_inferred /in0[12]
      : west_data_i_psum_inferred__2/out[12]
      : west_data_i_psum_inferred__2/in0[12]
      : west_data_i_psum_inferred__1/out[12]
      : west_data_i_psum_inferred__1/in0[12]
      : \HMNoC_cluster_west_1/east_data_o_psum_inferred__0 /out[12]
      : \HMNoC_cluster_west_1/east_data_o_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_west_1/east_data_o_psum_inferred /out[12]
      : \HMNoC_cluster_west_1/east_data_o_psum_inferred /in0[12]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_psum_inferred__0 /out[12]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_psum_inferred /out[12]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_o_psum_inferred /in0[12]
     4: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1931 /O (LUT2)
     5: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1931 /I0 (LUT2)
     6: i_2350/O (LUT5)
     7: i_2350/I2 (LUT5)
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred__0 /out[12]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred /out[12]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred /in0[12]
      : east_data_i_psum_inferred__2/out[12]
      : east_data_i_psum_inferred__2/in0[12]
      : east_data_i_psum_inferred__1/out[12]
      : east_data_i_psum_inferred__1/in0[12]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred__0 /out[12]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred /out[12]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred /in0[12]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred__0 /out[12]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred /out[12]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred /in0[12]
     8: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2068 /O (LUT2)
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2068 "
Found timing loop:
     0: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1932 /O (LUT2)
     1: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1932 /I1 (LUT2)
     2: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1916 /O (LUT2)
     3: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1916 /I0 (LUT2)
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /out[13]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /in0[13]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /out[13]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /in0[13]
      : north_data_i_psum_inferred__0/out[13]
      : north_data_i_psum_inferred__0/in0[13]
      : north_data_i_psum_inferred/out[13]
      : north_data_i_psum_inferred/in0[13]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /out[13]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /in0[13]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /out[13]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /in0[13]
     4: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1690 /O (LUT3)
     5: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1690 /I0 (LUT3)
     6: i_2460/O (LUT2)
     7: i_2460/I0 (LUT2)
     8: i_2276/O (LUT4)
     9: i_2276/I1 (LUT4)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[13]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[13]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[13]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[13]
      : south_data_i_psum_inferred__0/out[13]
      : south_data_i_psum_inferred__0/in0[13]
      : south_data_i_psum_inferred/out[13]
      : south_data_i_psum_inferred/in0[13]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[13]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[13]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[13]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[13]
    10: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1932 /O (LUT2)
Inferred a: "set_disable_timing -from I1 -to O \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1932 "
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1690 /O (LUT3)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1690 /I0 (LUT3)
     2: i_2460/O (LUT2)
     3: i_2460/I0 (LUT2)
     4: i_2276/O (LUT4)
     5: i_2276/I1 (LUT4)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[13]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[13]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[13]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[13]
      : south_data_i_psum_inferred__0/out[13]
      : south_data_i_psum_inferred__0/in0[13]
      : south_data_i_psum_inferred/out[13]
      : south_data_i_psum_inferred/in0[13]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[13]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[13]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[13]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[13]
     6: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1932 /O (LUT2)
     7: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1932 /O (LUT2)
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1690 "
Found timing loop:
     0: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2037 /O (LUT2)
     1: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2037 /I0 (LUT2)
     2: i_2392/O (LUT5)
     3: i_2392/I3 (LUT5)
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[13]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[13]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[13]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[13]
      : west_data_i_psum_inferred__0/out[13]
      : west_data_i_psum_inferred__0/in0[13]
      : west_data_i_psum_inferred/out[13]
      : west_data_i_psum_inferred/in0[13]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[13]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[13]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[13]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[13]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[13]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[13]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[13]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[13]
     4: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1690 /O (LUT3)
     5: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1690 /O (LUT3)
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2037 "
Found timing loop:
     0: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1932 /O (LUT2)
     1: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1932 /O (LUT2)
Found timing loop:
     0: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1933 /O (LUT2)
     1: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1933 /I1 (LUT2)
     2: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1917 /O (LUT2)
     3: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1917 /I0 (LUT2)
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /out[14]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /in0[14]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /out[14]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /in0[14]
      : north_data_i_psum_inferred__0/out[14]
      : north_data_i_psum_inferred__0/in0[14]
      : north_data_i_psum_inferred/out[14]
      : north_data_i_psum_inferred/in0[14]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /out[14]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /in0[14]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /out[14]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /in0[14]
     4: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1693 /O (LUT2)
     5: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1693 /I0 (LUT2)
     6: i_2277/O (LUT5)
     7: i_2277/I3 (LUT5)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[14]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[14]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[14]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[14]
      : south_data_i_psum_inferred__0/out[14]
      : south_data_i_psum_inferred__0/in0[14]
      : south_data_i_psum_inferred/out[14]
      : south_data_i_psum_inferred/in0[14]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[14]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[14]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[14]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[14]
     8: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1933 /O (LUT2)
Inferred a: "set_disable_timing -from I1 -to O \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1933 "
Found timing loop:
     0: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2038 /O (LUT2)
     1: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2038 /I0 (LUT2)
     2: i_2393/O (LUT5)
     3: i_2393/I3 (LUT5)
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[14]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[14]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[14]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[14]
      : south_data_i_psum_inferred__2/out[14]
      : south_data_i_psum_inferred__2/in0[14]
      : south_data_i_psum_inferred__1/out[14]
      : south_data_i_psum_inferred__1/in0[14]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[14]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[14]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[14]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[14]
     4: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2070 /O (LUT2)
     5: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2070 /I1 (LUT2)
     6: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2054 /O (LUT2)
     7: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2054 /I0 (LUT2)
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /out[14]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /in0[14]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /out[14]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /in0[14]
      : south_data_o_psum_inferred__2/out[14]
      : south_data_o_psum_inferred__2/in0[14]
      : south_data_o_psum_inferred__1/out[14]
      : south_data_o_psum_inferred__1/in0[14]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[14]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[14]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[14]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[14]
     8: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2038 /O (LUT2)
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2038 "
Found timing loop:
     0: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1933 /O (LUT2)
     1: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1933 /O (LUT2)
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1693 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1693 /I0 (LUT2)
     2: i_2277/O (LUT5)
     3: i_2277/I3 (LUT5)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[14]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[14]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[14]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[14]
      : south_data_i_psum_inferred__0/out[14]
      : south_data_i_psum_inferred__0/in0[14]
      : south_data_i_psum_inferred/out[14]
      : south_data_i_psum_inferred/in0[14]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[14]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[14]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[14]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[14]
     4: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1933 /O (LUT2)
     5: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1933 /O (LUT2)
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1693 "
Found timing loop:
     0: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1934 /O (LUT2)
     1: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1934 /I1 (LUT2)
     2: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1918 /O (LUT2)
     3: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1918 /I0 (LUT2)
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /out[15]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /in0[15]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /out[15]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /in0[15]
      : north_data_i_psum_inferred__0/out[15]
      : north_data_i_psum_inferred__0/in0[15]
      : north_data_i_psum_inferred/out[15]
      : north_data_i_psum_inferred/in0[15]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /out[15]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /in0[15]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /out[15]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /in0[15]
     4: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1694 /O (LUT2)
     5: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1694 /I0 (LUT2)
     6: i_2278/O (LUT5)
     7: i_2278/I3 (LUT5)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[15]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[15]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[15]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[15]
      : south_data_i_psum_inferred__0/out[15]
      : south_data_i_psum_inferred__0/in0[15]
      : south_data_i_psum_inferred/out[15]
      : south_data_i_psum_inferred/in0[15]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[15]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[15]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[15]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[15]
     8: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1934 /O (LUT2)
Inferred a: "set_disable_timing -from I1 -to O \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1934 "
Found timing loop:
     0: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2039 /O (LUT2)
     1: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2039 /I0 (LUT2)
     2: i_2394/O (LUT5)
     3: i_2394/I3 (LUT5)
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[15]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[15]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[15]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[15]
      : south_data_i_psum_inferred__2/out[15]
      : south_data_i_psum_inferred__2/in0[15]
      : south_data_i_psum_inferred__1/out[15]
      : south_data_i_psum_inferred__1/in0[15]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[15]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[15]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[15]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[15]
     4: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2071 /O (LUT2)
     5: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2071 /I1 (LUT2)
     6: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2055 /O (LUT2)
     7: \HMNoC_cluster_east_1/router_cluster_0/router_psum/i_2055 /I0 (LUT2)
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /out[15]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /in0[15]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /out[15]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /in0[15]
      : south_data_o_psum_inferred__2/out[15]
      : south_data_o_psum_inferred__2/in0[15]
      : south_data_o_psum_inferred__1/out[15]
      : south_data_o_psum_inferred__1/in0[15]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[15]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[15]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[15]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[15]
     8: \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2039 /O (LUT2)
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_0/router_cluster_0/router_psum/i_2039 "
Found timing loop:
     0: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1934 /O (LUT2)
     1: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1934 /O (LUT2)
Found timing loop:
     0: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1694 /O (LUT2)
     1: \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1694 /I0 (LUT2)
     2: i_2278/O (LUT5)
     3: i_2278/I3 (LUT5)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[15]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[15]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[15]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[15]
      : south_data_i_psum_inferred__0/out[15]
      : south_data_i_psum_inferred__0/in0[15]
      : south_data_i_psum_inferred/out[15]
      : south_data_i_psum_inferred/in0[15]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[15]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[15]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[15]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[15]
     4: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1934 /O (LUT2)
     5: \HMNoC_cluster_west_1/router_cluster_0/router_psum/i_1934 /O (LUT2)
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_west_0/router_cluster_0/router_psum/i_1694 "
Found timing loop:
     0: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2072 /O (LUT2)
     1: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2072 /I1 (LUT2)
     2: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2095 /O (LUT2)
     3: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2095 /I0 (LUT2)
     4: i_2420/O (LUT2)
     5: i_2420/I0 (LUT2)
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /out[0]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /in0[0]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /out[0]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /in0[0]
      : north_data_i_wght_inferred__2/out[0]
      : north_data_i_wght_inferred__2/in0[0]
      : north_data_i_wght_inferred__1/out[0]
      : north_data_i_wght_inferred__1/in0[0]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /out[0]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /in0[0]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /out[0]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /in0[0]
     6: \HMNoC_cluster_east_0/router_cluster_0/router_wght/i_1951 /O (LUT2)
     7: \HMNoC_cluster_east_0/router_cluster_0/router_wght/i_1951 /I0 (LUT2)
     8: i_2354/O (LUT6)
     9: i_2354/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /out[0]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /in0[0]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /out[0]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /in0[0]
      : south_data_i_wght_inferred__2/out[0]
      : south_data_i_wght_inferred__2/in0[0]
      : south_data_i_wght_inferred__1/out[0]
      : south_data_i_wght_inferred__1/in0[0]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /out[0]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /in0[0]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /out[0]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /in0[0]
    10: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2072 /O (LUT2)
Inferred a: "set_disable_timing -from I1 -to O \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2072 "
Found timing loop:
     0: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2074 /O (LUT2)
     1: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2074 /I1 (LUT2)
     2: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2097 /O (LUT2)
     3: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2097 /I0 (LUT2)
     4: i_2421/O (LUT2)
     5: i_2421/I0 (LUT2)
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /out[2]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /in0[2]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /out[2]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /in0[2]
      : north_data_i_wght_inferred__2/out[2]
      : north_data_i_wght_inferred__2/in0[2]
      : north_data_i_wght_inferred__1/out[2]
      : north_data_i_wght_inferred__1/in0[2]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /out[2]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /in0[2]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /out[2]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /in0[2]
     6: \HMNoC_cluster_east_0/router_cluster_0/router_wght/i_1953 /O (LUT2)
     7: \HMNoC_cluster_east_0/router_cluster_0/router_wght/i_1953 /I0 (LUT2)
     8: i_2355/O (LUT6)
     9: i_2355/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /out[2]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /in0[2]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /out[2]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /in0[2]
      : south_data_i_wght_inferred__2/out[2]
      : south_data_i_wght_inferred__2/in0[2]
      : south_data_i_wght_inferred__1/out[2]
      : south_data_i_wght_inferred__1/in0[2]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /out[2]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /in0[2]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /out[2]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /in0[2]
    10: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2074 /O (LUT2)
Inferred a: "set_disable_timing -from I1 -to O \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2074 "
Found timing loop:
     0: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2076 /O (LUT2)
     1: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2076 /I1 (LUT2)
     2: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2099 /O (LUT2)
     3: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2099 /I0 (LUT2)
     4: i_2422/O (LUT2)
     5: i_2422/I0 (LUT2)
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /out[4]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /in0[4]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /out[4]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /in0[4]
      : north_data_i_wght_inferred__2/out[4]
      : north_data_i_wght_inferred__2/in0[4]
      : north_data_i_wght_inferred__1/out[4]
      : north_data_i_wght_inferred__1/in0[4]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /out[4]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /in0[4]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /out[4]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /in0[4]
     6: \HMNoC_cluster_east_0/router_cluster_0/router_wght/i_1955 /O (LUT2)
     7: \HMNoC_cluster_east_0/router_cluster_0/router_wght/i_1955 /I0 (LUT2)
     8: i_2356/O (LUT6)
     9: i_2356/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /out[4]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /in0[4]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /out[4]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /in0[4]
      : south_data_i_wght_inferred__2/out[4]
      : south_data_i_wght_inferred__2/in0[4]
      : south_data_i_wght_inferred__1/out[4]
      : south_data_i_wght_inferred__1/in0[4]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /out[4]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /in0[4]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /out[4]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /in0[4]
    10: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2076 /O (LUT2)
Inferred a: "set_disable_timing -from I1 -to O \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2076 "
Found timing loop:
     0: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2077 /O (LUT2)
     1: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2077 /I1 (LUT2)
     2: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2100 /O (LUT2)
     3: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2100 /I0 (LUT2)
     4: i_2423/O (LUT2)
     5: i_2423/I0 (LUT2)
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /out[5]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /in0[5]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /out[5]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /in0[5]
      : north_data_i_wght_inferred__2/out[5]
      : north_data_i_wght_inferred__2/in0[5]
      : north_data_i_wght_inferred__1/out[5]
      : north_data_i_wght_inferred__1/in0[5]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /out[5]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /in0[5]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /out[5]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /in0[5]
     6: \HMNoC_cluster_east_0/router_cluster_0/router_wght/i_1956 /O (LUT2)
     7: \HMNoC_cluster_east_0/router_cluster_0/router_wght/i_1956 /I0 (LUT2)
     8: i_2357/O (LUT6)
     9: i_2357/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /out[5]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /in0[5]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /out[5]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /in0[5]
      : south_data_i_wght_inferred__2/out[5]
      : south_data_i_wght_inferred__2/in0[5]
      : south_data_i_wght_inferred__1/out[5]
      : south_data_i_wght_inferred__1/in0[5]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /out[5]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /in0[5]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /out[5]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /in0[5]
    10: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2077 /O (LUT2)
Inferred a: "set_disable_timing -from I1 -to O \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2077 "
Found timing loop:
     0: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2078 /O (LUT2)
     1: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2078 /I1 (LUT2)
     2: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2101 /O (LUT2)
     3: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2101 /I0 (LUT2)
     4: i_2424/O (LUT2)
     5: i_2424/I0 (LUT2)
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /out[6]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /in0[6]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /out[6]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /in0[6]
      : north_data_i_wght_inferred__2/out[6]
      : north_data_i_wght_inferred__2/in0[6]
      : north_data_i_wght_inferred__1/out[6]
      : north_data_i_wght_inferred__1/in0[6]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /out[6]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /in0[6]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /out[6]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /in0[6]
     6: \HMNoC_cluster_east_0/router_cluster_0/router_wght/i_1957 /O (LUT2)
     7: \HMNoC_cluster_east_0/router_cluster_0/router_wght/i_1957 /I0 (LUT2)
     8: i_2358/O (LUT6)
     9: i_2358/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /out[6]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /in0[6]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /out[6]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /in0[6]
      : south_data_i_wght_inferred__2/out[6]
      : south_data_i_wght_inferred__2/in0[6]
      : south_data_i_wght_inferred__1/out[6]
      : south_data_i_wght_inferred__1/in0[6]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /out[6]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /in0[6]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /out[6]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /in0[6]
    10: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2078 /O (LUT2)
Inferred a: "set_disable_timing -from I1 -to O \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2078 "
Found timing loop:
     0: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2080 /O (LUT2)
     1: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2080 /I1 (LUT2)
     2: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2103 /O (LUT2)
     3: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2103 /I0 (LUT2)
     4: i_2425/O (LUT2)
     5: i_2425/I0 (LUT2)
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /out[8]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /in0[8]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /out[8]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /in0[8]
      : north_data_i_wght_inferred__2/out[8]
      : north_data_i_wght_inferred__2/in0[8]
      : north_data_i_wght_inferred__1/out[8]
      : north_data_i_wght_inferred__1/in0[8]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /out[8]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /in0[8]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /out[8]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /in0[8]
     6: \HMNoC_cluster_east_0/router_cluster_0/router_wght/i_1959 /O (LUT2)
     7: \HMNoC_cluster_east_0/router_cluster_0/router_wght/i_1959 /I0 (LUT2)
     8: i_2359/O (LUT6)
     9: i_2359/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /out[8]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /in0[8]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /out[8]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /in0[8]
      : south_data_i_wght_inferred__2/out[8]
      : south_data_i_wght_inferred__2/in0[8]
      : south_data_i_wght_inferred__1/out[8]
      : south_data_i_wght_inferred__1/in0[8]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /out[8]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /in0[8]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /out[8]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /in0[8]
    10: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2080 /O (LUT2)
Inferred a: "set_disable_timing -from I1 -to O \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2080 "
Found timing loop:
     0: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2081 /O (LUT2)
     1: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2081 /I1 (LUT2)
     2: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2104 /O (LUT2)
     3: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2104 /I0 (LUT2)
     4: i_2426/O (LUT2)
     5: i_2426/I0 (LUT2)
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /out[9]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /in0[9]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /out[9]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /in0[9]
      : north_data_i_wght_inferred__2/out[9]
      : north_data_i_wght_inferred__2/in0[9]
      : north_data_i_wght_inferred__1/out[9]
      : north_data_i_wght_inferred__1/in0[9]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /out[9]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /in0[9]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /out[9]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /in0[9]
     6: \HMNoC_cluster_east_0/router_cluster_0/router_wght/i_1960 /O (LUT2)
     7: \HMNoC_cluster_east_0/router_cluster_0/router_wght/i_1960 /I0 (LUT2)
     8: i_2360/O (LUT6)
     9: i_2360/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /out[9]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /in0[9]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /out[9]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /in0[9]
      : south_data_i_wght_inferred__2/out[9]
      : south_data_i_wght_inferred__2/in0[9]
      : south_data_i_wght_inferred__1/out[9]
      : south_data_i_wght_inferred__1/in0[9]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /out[9]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /in0[9]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /out[9]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /in0[9]
    10: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2081 /O (LUT2)
Inferred a: "set_disable_timing -from I1 -to O \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2081 "
Found timing loop:
     0: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2082 /O (LUT2)
     1: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2082 /I1 (LUT2)
     2: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2105 /O (LUT2)
     3: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2105 /I0 (LUT2)
     4: i_2427/O (LUT2)
     5: i_2427/I0 (LUT2)
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /out[10]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /in0[10]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /out[10]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /in0[10]
      : north_data_i_wght_inferred__2/out[10]
      : north_data_i_wght_inferred__2/in0[10]
      : north_data_i_wght_inferred__1/out[10]
      : north_data_i_wght_inferred__1/in0[10]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /out[10]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /in0[10]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /out[10]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /in0[10]
     6: \HMNoC_cluster_east_0/router_cluster_0/router_wght/i_1961 /O (LUT2)
     7: \HMNoC_cluster_east_0/router_cluster_0/router_wght/i_1961 /I0 (LUT2)
     8: i_2361/O (LUT6)
     9: i_2361/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /out[10]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /in0[10]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /out[10]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /in0[10]
      : south_data_i_wght_inferred__2/out[10]
      : south_data_i_wght_inferred__2/in0[10]
      : south_data_i_wght_inferred__1/out[10]
      : south_data_i_wght_inferred__1/in0[10]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /out[10]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /in0[10]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /out[10]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /in0[10]
    10: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2082 /O (LUT2)
Inferred a: "set_disable_timing -from I1 -to O \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2082 "
Found timing loop:
     0: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2085 /O (LUT2)
     1: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2085 /I1 (LUT2)
     2: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2108 /O (LUT2)
     3: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2108 /I0 (LUT2)
     4: i_2428/O (LUT2)
     5: i_2428/I0 (LUT2)
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /out[13]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /in0[13]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /out[13]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /in0[13]
      : north_data_i_wght_inferred__2/out[13]
      : north_data_i_wght_inferred__2/in0[13]
      : north_data_i_wght_inferred__1/out[13]
      : north_data_i_wght_inferred__1/in0[13]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /out[13]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /in0[13]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /out[13]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /in0[13]
     6: \HMNoC_cluster_east_0/router_cluster_0/router_wght/i_1964 /O (LUT2)
     7: \HMNoC_cluster_east_0/router_cluster_0/router_wght/i_1964 /I0 (LUT2)
     8: i_2362/O (LUT6)
     9: i_2362/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /out[13]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /in0[13]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /out[13]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /in0[13]
      : south_data_i_wght_inferred__2/out[13]
      : south_data_i_wght_inferred__2/in0[13]
      : south_data_i_wght_inferred__1/out[13]
      : south_data_i_wght_inferred__1/in0[13]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /out[13]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /in0[13]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /out[13]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /in0[13]
    10: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2085 /O (LUT2)
Inferred a: "set_disable_timing -from I1 -to O \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2085 "
Found timing loop:
     0: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2096 /O (LUT2)
     1: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2096 /I0 (LUT2)
     2: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2088 /O (LUT2)
     3: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2088 /I0 (LUT2)
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /out[1]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /in0[1]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /out[1]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /in0[1]
      : north_data_i_wght_inferred__2/out[1]
      : north_data_i_wght_inferred__2/in0[1]
      : north_data_i_wght_inferred__1/out[1]
      : north_data_i_wght_inferred__1/in0[1]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /out[1]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /in0[1]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /out[1]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /in0[1]
     4: \HMNoC_cluster_east_0/router_cluster_0/router_wght/i_1952 /O (LUT2)
     5: \HMNoC_cluster_east_0/router_cluster_0/router_wght/i_1952 /I0 (LUT2)
     6: i_2466/O (LUT5)
     7: i_2466/I3 (LUT5)
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /out[1]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /in0[1]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /out[1]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /in0[1]
      : south_data_i_wght_inferred__2/out[1]
      : south_data_i_wght_inferred__2/in0[1]
      : south_data_i_wght_inferred__1/out[1]
      : south_data_i_wght_inferred__1/in0[1]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /out[1]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /in0[1]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /out[1]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /in0[1]
     8: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2073 /O (LUT2)
     9: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2073 /I1 (LUT2)
    10: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2096 /O (LUT2)
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2096 "
Found timing loop:
     0: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2098 /O (LUT2)
     1: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2098 /I0 (LUT2)
     2: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2089 /O (LUT2)
     3: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2089 /I0 (LUT2)
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /out[3]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /in0[3]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /out[3]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /in0[3]
      : north_data_i_wght_inferred__2/out[3]
      : north_data_i_wght_inferred__2/in0[3]
      : north_data_i_wght_inferred__1/out[3]
      : north_data_i_wght_inferred__1/in0[3]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /out[3]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /in0[3]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /out[3]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /in0[3]
     4: \HMNoC_cluster_east_0/router_cluster_0/router_wght/i_1954 /O (LUT2)
     5: \HMNoC_cluster_east_0/router_cluster_0/router_wght/i_1954 /I0 (LUT2)
     6: i_2467/O (LUT5)
     7: i_2467/I3 (LUT5)
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /out[3]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /in0[3]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /out[3]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /in0[3]
      : south_data_i_wght_inferred__2/out[3]
      : south_data_i_wght_inferred__2/in0[3]
      : south_data_i_wght_inferred__1/out[3]
      : south_data_i_wght_inferred__1/in0[3]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /out[3]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /in0[3]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /out[3]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /in0[3]
     8: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2075 /O (LUT2)
     9: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2075 /I1 (LUT2)
    10: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2098 /O (LUT2)
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2098 "
Found timing loop:
     0: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2102 /O (LUT2)
     1: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2102 /I0 (LUT2)
     2: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2090 /O (LUT2)
     3: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2090 /I0 (LUT2)
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /out[7]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /in0[7]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /out[7]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /in0[7]
      : north_data_i_wght_inferred__2/out[7]
      : north_data_i_wght_inferred__2/in0[7]
      : north_data_i_wght_inferred__1/out[7]
      : north_data_i_wght_inferred__1/in0[7]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /out[7]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /in0[7]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /out[7]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /in0[7]
     4: \HMNoC_cluster_east_0/router_cluster_0/router_wght/i_1958 /O (LUT2)
     5: \HMNoC_cluster_east_0/router_cluster_0/router_wght/i_1958 /I0 (LUT2)
     6: i_2468/O (LUT5)
     7: i_2468/I3 (LUT5)
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /out[7]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /in0[7]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /out[7]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /in0[7]
      : south_data_i_wght_inferred__2/out[7]
      : south_data_i_wght_inferred__2/in0[7]
      : south_data_i_wght_inferred__1/out[7]
      : south_data_i_wght_inferred__1/in0[7]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /out[7]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /in0[7]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /out[7]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /in0[7]
     8: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2079 /O (LUT2)
     9: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2079 /I1 (LUT2)
    10: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2102 /O (LUT2)
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2102 "
Found timing loop:
     0: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2106 /O (LUT2)
     1: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2106 /I0 (LUT2)
     2: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2091 /O (LUT2)
     3: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2091 /I0 (LUT2)
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /out[11]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /in0[11]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /out[11]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /in0[11]
      : north_data_i_wght_inferred__2/out[11]
      : north_data_i_wght_inferred__2/in0[11]
      : north_data_i_wght_inferred__1/out[11]
      : north_data_i_wght_inferred__1/in0[11]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /out[11]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /in0[11]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /out[11]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /in0[11]
     4: \HMNoC_cluster_east_0/router_cluster_0/router_wght/i_1962 /O (LUT2)
     5: \HMNoC_cluster_east_0/router_cluster_0/router_wght/i_1962 /I0 (LUT2)
     6: i_2469/O (LUT5)
     7: i_2469/I3 (LUT5)
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /out[11]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /in0[11]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /out[11]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /in0[11]
      : south_data_i_wght_inferred__2/out[11]
      : south_data_i_wght_inferred__2/in0[11]
      : south_data_i_wght_inferred__1/out[11]
      : south_data_i_wght_inferred__1/in0[11]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /out[11]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /in0[11]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /out[11]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /in0[11]
     8: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2083 /O (LUT2)
     9: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2083 /I1 (LUT2)
    10: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2106 /O (LUT2)
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2106 "
Found timing loop:
     0: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2107 /O (LUT2)
     1: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2107 /I0 (LUT2)
     2: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2092 /O (LUT2)
     3: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2092 /I0 (LUT2)
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /out[12]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /in0[12]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /out[12]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /in0[12]
      : north_data_i_wght_inferred__2/out[12]
      : north_data_i_wght_inferred__2/in0[12]
      : north_data_i_wght_inferred__1/out[12]
      : north_data_i_wght_inferred__1/in0[12]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /out[12]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /in0[12]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /out[12]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /in0[12]
     4: \HMNoC_cluster_east_0/router_cluster_0/router_wght/i_1963 /O (LUT2)
     5: \HMNoC_cluster_east_0/router_cluster_0/router_wght/i_1963 /I0 (LUT2)
     6: i_2470/O (LUT5)
     7: i_2470/I3 (LUT5)
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /out[12]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /in0[12]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /out[12]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /in0[12]
      : south_data_i_wght_inferred__2/out[12]
      : south_data_i_wght_inferred__2/in0[12]
      : south_data_i_wght_inferred__1/out[12]
      : south_data_i_wght_inferred__1/in0[12]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /out[12]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /in0[12]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /out[12]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /in0[12]
     8: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2084 /O (LUT2)
     9: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2084 /I1 (LUT2)
    10: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2107 /O (LUT2)
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2107 "
Found timing loop:
     0: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2109 /O (LUT2)
     1: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2109 /I0 (LUT2)
     2: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2093 /O (LUT2)
     3: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2093 /I0 (LUT2)
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /out[14]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /in0[14]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /out[14]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /in0[14]
      : north_data_i_wght_inferred__2/out[14]
      : north_data_i_wght_inferred__2/in0[14]
      : north_data_i_wght_inferred__1/out[14]
      : north_data_i_wght_inferred__1/in0[14]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /out[14]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /in0[14]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /out[14]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /in0[14]
     4: \HMNoC_cluster_east_0/router_cluster_0/router_wght/i_1965 /O (LUT2)
     5: \HMNoC_cluster_east_0/router_cluster_0/router_wght/i_1965 /I0 (LUT2)
     6: i_2471/O (LUT5)
     7: i_2471/I3 (LUT5)
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /out[14]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /in0[14]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /out[14]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /in0[14]
      : south_data_i_wght_inferred__2/out[14]
      : south_data_i_wght_inferred__2/in0[14]
      : south_data_i_wght_inferred__1/out[14]
      : south_data_i_wght_inferred__1/in0[14]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /out[14]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /in0[14]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /out[14]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /in0[14]
     8: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2086 /O (LUT2)
     9: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2086 /I1 (LUT2)
    10: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2109 /O (LUT2)
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2109 "
Found timing loop:
     0: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2110 /O (LUT2)
     1: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2110 /I0 (LUT2)
     2: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2094 /O (LUT2)
     3: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2094 /I0 (LUT2)
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /out[15]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /in0[15]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /out[15]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /in0[15]
      : north_data_i_wght_inferred__2/out[15]
      : north_data_i_wght_inferred__2/in0[15]
      : north_data_i_wght_inferred__1/out[15]
      : north_data_i_wght_inferred__1/in0[15]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /out[15]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /in0[15]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /out[15]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /in0[15]
     4: \HMNoC_cluster_east_0/router_cluster_0/router_wght/i_1966 /O (LUT2)
     5: \HMNoC_cluster_east_0/router_cluster_0/router_wght/i_1966 /I0 (LUT2)
     6: i_2472/O (LUT5)
     7: i_2472/I3 (LUT5)
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /out[15]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /in0[15]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /out[15]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /in0[15]
      : south_data_i_wght_inferred__2/out[15]
      : south_data_i_wght_inferred__2/in0[15]
      : south_data_i_wght_inferred__1/out[15]
      : south_data_i_wght_inferred__1/in0[15]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /out[15]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /in0[15]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /out[15]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /in0[15]
     8: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2087 /O (LUT2)
     9: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2087 /I1 (LUT2)
    10: \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2110 /O (LUT2)
Inferred a: "set_disable_timing -from I0 -to O \HMNoC_cluster_east_1/router_cluster_0/router_wght/i_2110 "
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:57 ; elapsed = 00:01:05 . Memory (MB): peak = 2126.836 ; gain = 1865.652
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:58 ; elapsed = 00:01:06 . Memory (MB): peak = 2126.836 ; gain = 1865.652
---------------------------------------------------------------------------------
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin HMNoC_cluster_west_0/east_data_i_psum_inferred__0_n_1 with 1st driver pin 'i_1694/O' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router.sv:85]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin HMNoC_cluster_west_0/east_data_i_psum_inferred__0_n_1 with 2nd driver pin 'i_1678/O' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router.sv:85]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin HMNoC_cluster_west_0/east_data_i_psum_inferred__0_n_0 with 1st driver pin 'i_1839/O' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router.sv:85]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin HMNoC_cluster_west_0/east_data_i_psum_inferred__0_n_0 with 2nd driver pin 'i_1679/O' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router.sv:85]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin HMNoC_cluster_west_1/east_data_i_psum_inferred__0_n_15 with 1st driver pin 'i_1664/O' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router.sv:85]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin HMNoC_cluster_west_1/east_data_i_psum_inferred__0_n_15 with 2nd driver pin 'i_1680/O' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router.sv:85]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin HMNoC_cluster_west_1/east_data_i_psum_inferred__0_n_14 with 1st driver pin 'i_1665/O' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router.sv:85]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin HMNoC_cluster_west_1/east_data_i_psum_inferred__0_n_14 with 2nd driver pin 'i_1681/O' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router.sv:85]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin HMNoC_cluster_west_1/east_data_i_psum_inferred__0_n_13 with 1st driver pin 'i_1666/O' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router.sv:85]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin HMNoC_cluster_west_1/east_data_i_psum_inferred__0_n_13 with 2nd driver pin 'i_1682/O' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router.sv:85]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin HMNoC_cluster_west_1/east_data_i_psum_inferred__0_n_12 with 1st driver pin 'i_1667/O' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router.sv:85]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin HMNoC_cluster_west_1/east_data_i_psum_inferred__0_n_12 with 2nd driver pin 'i_1683/O' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router.sv:85]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin HMNoC_cluster_west_1/east_data_i_psum_inferred__0_n_11 with 1st driver pin 'i_1668/O' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router.sv:85]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin HMNoC_cluster_west_1/east_data_i_psum_inferred__0_n_11 with 2nd driver pin 'i_1684/O' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router.sv:85]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin HMNoC_cluster_west_1/east_data_i_psum_inferred__0_n_10 with 1st driver pin 'i_1669/O' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router.sv:85]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin HMNoC_cluster_west_1/east_data_i_psum_inferred__0_n_10 with 2nd driver pin 'i_1685/O' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router.sv:85]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin HMNoC_cluster_west_1/east_data_i_psum_inferred__0_n_9 with 1st driver pin 'i_1670/O' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router.sv:85]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin HMNoC_cluster_west_1/east_data_i_psum_inferred__0_n_9 with 2nd driver pin 'i_1686/O' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router.sv:85]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin HMNoC_cluster_west_1/east_data_i_psum_inferred__0_n_8 with 1st driver pin 'i_1671/O' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router.sv:85]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin HMNoC_cluster_west_1/east_data_i_psum_inferred__0_n_8 with 2nd driver pin 'i_1687/O' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router.sv:85]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin HMNoC_cluster_west_1/east_data_i_psum_inferred__0_n_7 with 1st driver pin 'i_1672/O' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router.sv:85]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin HMNoC_cluster_west_1/east_data_i_psum_inferred__0_n_7 with 2nd driver pin 'i_1688/O' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router.sv:85]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin HMNoC_cluster_west_1/east_data_i_psum_inferred__0_n_6 with 1st driver pin 'i_1673/O' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router.sv:85]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin HMNoC_cluster_west_1/east_data_i_psum_inferred__0_n_6 with 2nd driver pin 'i_1689/O' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router.sv:85]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin HMNoC_cluster_west_1/east_data_i_psum_inferred__0_n_5 with 1st driver pin 'i_1674/O' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router.sv:85]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin HMNoC_cluster_west_1/east_data_i_psum_inferred__0_n_5 with 2nd driver pin 'i_1690/O' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router.sv:85]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin HMNoC_cluster_west_1/east_data_i_psum_inferred__0_n_4 with 1st driver pin 'i_1675/O' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router.sv:85]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin HMNoC_cluster_west_1/east_data_i_psum_inferred__0_n_4 with 2nd driver pin 'i_1691/O' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router.sv:85]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin HMNoC_cluster_west_1/east_data_i_psum_inferred__0_n_3 with 1st driver pin 'i_1676/O' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router.sv:85]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin HMNoC_cluster_west_1/east_data_i_psum_inferred__0_n_3 with 2nd driver pin 'i_1692/O' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router.sv:85]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin HMNoC_cluster_west_1/east_data_i_psum_inferred__0_n_2 with 1st driver pin 'i_1677/O' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router.sv:85]
CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin HMNoC_cluster_west_1/east_data_i_psum_inferred__0_n_2 with 2nd driver pin 'i_1693/O' [D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.srcs/sources_1/new/router.sv:85]

Report Check Netlist: 
+------+------------------+-------+---------+-------+------------------+
|      |Item              |Errors |Warnings |Status |Description       |
+------+------------------+-------+---------+-------+------------------+
|1     |multi_driven_nets |      0|       16|Failed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:58 ; elapsed = 00:01:07 . Memory (MB): peak = 2126.836 ; gain = 1865.652
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
Found timing loop:
     0: west_data_o_psum_inferred_i_15__0/O (LUT6)
     1: west_data_o_psum_inferred_i_15__0/I3 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[1]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[1]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[1]
      : south_data_i_psum_inferred__2/out[1]
      : south_data_i_psum_inferred__2/in0[1]
      : south_data_i_psum_inferred__1/out[1]
      : south_data_i_psum_inferred__1/in0[1]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[1]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[1]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[1]
     2: west_data_o_psum_inferred_i_15__1/O (LUT6)
     3: west_data_o_psum_inferred_i_15__1/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /out[1]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /out[1]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /in0[1]
      : south_data_o_psum_inferred__2/out[1]
      : south_data_o_psum_inferred__2/in0[1]
      : south_data_o_psum_inferred__1/out[1]
      : south_data_o_psum_inferred__1/in0[1]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[1]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[1]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[1]
     4: west_data_o_psum_inferred_i_15__0/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_psum_inferred_i_15__0"
Found timing loop:
     0: west_data_o_psum_inferred_i_15__2/O (LUT6)
     1: west_data_o_psum_inferred_i_15__2/I1 (LUT6)
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /out[1]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /out[1]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /in0[1]
      : east_data_i_psum_inferred__0/out[1]
      : east_data_i_psum_inferred__0/in0[1]
      : east_data_i_psum_inferred/out[1]
      : east_data_i_psum_inferred/in0[1]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /out[1]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /out[1]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /in0[1]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /out[1]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /out[1]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /in0[1]
     2: west_data_o_psum_inferred_i_15__0/O (LUT6)
     3: west_data_o_psum_inferred_i_15__0/I2 (LUT6)
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[1]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[1]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[1]
      : west_data_i_psum_inferred__0/out[1]
      : west_data_i_psum_inferred__0/in0[1]
      : west_data_i_psum_inferred/out[1]
      : west_data_i_psum_inferred/in0[1]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[1]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[1]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[1]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[1]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[1]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[1]
     4: west_data_o_psum_inferred_i_15__2/O (LUT6)
Inferred a: "set_disable_timing -from I1 -to O west_data_o_psum_inferred_i_15__2"
Found timing loop:
     0: west_data_o_psum_inferred_i_15__1/O (LUT6)
     1: west_data_o_psum_inferred_i_15__1/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /out[1]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /out[1]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /in0[1]
      : south_data_o_psum_inferred__2/out[1]
      : south_data_o_psum_inferred__2/in0[1]
      : south_data_o_psum_inferred__1/out[1]
      : south_data_o_psum_inferred__1/in0[1]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[1]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[1]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[1]
     2: west_data_o_psum_inferred_i_15__0/O (LUT6)
     3: west_data_o_psum_inferred_i_15__0/I2 (LUT6)
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[1]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[1]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[1]
      : west_data_i_psum_inferred__0/out[1]
      : west_data_i_psum_inferred__0/in0[1]
      : west_data_i_psum_inferred/out[1]
      : west_data_i_psum_inferred/in0[1]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[1]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[1]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[1]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[1]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[1]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[1]
     4: west_data_o_psum_inferred_i_15__2/O (LUT6)
     5: west_data_o_psum_inferred_i_15__2/I0 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[1]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[1]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[1]
      : south_data_i_psum_inferred__0/out[1]
      : south_data_i_psum_inferred__0/in0[1]
      : south_data_i_psum_inferred/out[1]
      : south_data_i_psum_inferred/in0[1]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[1]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[1]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[1]
     6: west_data_o_psum_inferred_i_15/O (LUT6)
     7: west_data_o_psum_inferred_i_15/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /out[1]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /out[1]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /in0[1]
      : north_data_i_psum_inferred__0/out[1]
      : north_data_i_psum_inferred__0/in0[1]
      : north_data_i_psum_inferred/out[1]
      : north_data_i_psum_inferred/in0[1]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /out[1]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /in0[1]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /out[1]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /in0[1]
     8: west_data_o_psum_inferred_i_15__2/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_psum_inferred_i_15__1"
Found timing loop:
     0: west_data_o_psum_inferred_i_15__2/O (LUT6)
     1: west_data_o_psum_inferred_i_15__2/O (LUT6)
Found timing loop:
     0: west_data_o_psum_inferred_i_15__2/O (LUT6)
     1: west_data_o_psum_inferred_i_15__2/O (LUT6)
Found timing loop:
     0: west_data_o_psum_inferred_i_13__0/O (LUT6)
     1: west_data_o_psum_inferred_i_13__0/I3 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[3]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[3]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[3]
      : south_data_i_psum_inferred__2/out[3]
      : south_data_i_psum_inferred__2/in0[3]
      : south_data_i_psum_inferred__1/out[3]
      : south_data_i_psum_inferred__1/in0[3]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[3]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[3]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[3]
     2: west_data_o_psum_inferred_i_13__1/O (LUT6)
     3: west_data_o_psum_inferred_i_13__1/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /out[3]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /out[3]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /in0[3]
      : south_data_o_psum_inferred__2/out[3]
      : south_data_o_psum_inferred__2/in0[3]
      : south_data_o_psum_inferred__1/out[3]
      : south_data_o_psum_inferred__1/in0[3]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[3]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[3]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[3]
     4: west_data_o_psum_inferred_i_13__0/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_psum_inferred_i_13__0"
Found timing loop:
     0: west_data_o_psum_inferred_i_13__2/O (LUT6)
     1: west_data_o_psum_inferred_i_13__2/I1 (LUT6)
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /out[3]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /out[3]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /in0[3]
      : east_data_i_psum_inferred__0/out[3]
      : east_data_i_psum_inferred__0/in0[3]
      : east_data_i_psum_inferred/out[3]
      : east_data_i_psum_inferred/in0[3]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /out[3]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /out[3]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /in0[3]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /out[3]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /out[3]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /in0[3]
     2: west_data_o_psum_inferred_i_13__0/O (LUT6)
     3: west_data_o_psum_inferred_i_13__0/I2 (LUT6)
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[3]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[3]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[3]
      : west_data_i_psum_inferred__0/out[3]
      : west_data_i_psum_inferred__0/in0[3]
      : west_data_i_psum_inferred/out[3]
      : west_data_i_psum_inferred/in0[3]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[3]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[3]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[3]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[3]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[3]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[3]
     4: west_data_o_psum_inferred_i_13__2/O (LUT6)
Inferred a: "set_disable_timing -from I1 -to O west_data_o_psum_inferred_i_13__2"
Found timing loop:
     0: west_data_o_psum_inferred_i_13__1/O (LUT6)
     1: west_data_o_psum_inferred_i_13__1/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /out[3]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /out[3]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /in0[3]
      : south_data_o_psum_inferred__2/out[3]
      : south_data_o_psum_inferred__2/in0[3]
      : south_data_o_psum_inferred__1/out[3]
      : south_data_o_psum_inferred__1/in0[3]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[3]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[3]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[3]
     2: west_data_o_psum_inferred_i_13__0/O (LUT6)
     3: west_data_o_psum_inferred_i_13__0/I2 (LUT6)
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[3]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[3]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[3]
      : west_data_i_psum_inferred__0/out[3]
      : west_data_i_psum_inferred__0/in0[3]
      : west_data_i_psum_inferred/out[3]
      : west_data_i_psum_inferred/in0[3]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[3]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[3]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[3]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[3]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[3]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[3]
     4: west_data_o_psum_inferred_i_13__2/O (LUT6)
     5: west_data_o_psum_inferred_i_13__2/I0 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[3]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[3]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[3]
      : south_data_i_psum_inferred__0/out[3]
      : south_data_i_psum_inferred__0/in0[3]
      : south_data_i_psum_inferred/out[3]
      : south_data_i_psum_inferred/in0[3]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[3]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[3]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[3]
     6: west_data_o_psum_inferred_i_13/O (LUT6)
     7: west_data_o_psum_inferred_i_13/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /out[3]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /out[3]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /in0[3]
      : north_data_i_psum_inferred__0/out[3]
      : north_data_i_psum_inferred__0/in0[3]
      : north_data_i_psum_inferred/out[3]
      : north_data_i_psum_inferred/in0[3]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /out[3]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /in0[3]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /out[3]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /in0[3]
     8: west_data_o_psum_inferred_i_13__2/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_psum_inferred_i_13__1"
Found timing loop:
     0: west_data_o_psum_inferred_i_13__2/O (LUT6)
     1: west_data_o_psum_inferred_i_13__2/O (LUT6)
Found timing loop:
     0: west_data_o_psum_inferred_i_13__2/O (LUT6)
     1: west_data_o_psum_inferred_i_13__2/O (LUT6)
Found timing loop:
     0: west_data_o_psum_inferred_i_9__0/O (LUT6)
     1: west_data_o_psum_inferred_i_9__0/I3 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[7]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[7]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[7]
      : south_data_i_psum_inferred__2/out[7]
      : south_data_i_psum_inferred__2/in0[7]
      : south_data_i_psum_inferred__1/out[7]
      : south_data_i_psum_inferred__1/in0[7]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[7]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[7]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[7]
     2: west_data_o_psum_inferred_i_9__1/O (LUT6)
     3: west_data_o_psum_inferred_i_9__1/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /out[7]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /out[7]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /in0[7]
      : south_data_o_psum_inferred__2/out[7]
      : south_data_o_psum_inferred__2/in0[7]
      : south_data_o_psum_inferred__1/out[7]
      : south_data_o_psum_inferred__1/in0[7]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[7]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[7]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[7]
     4: west_data_o_psum_inferred_i_9__0/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_psum_inferred_i_9__0"
Found timing loop:
     0: west_data_o_psum_inferred_i_9__2/O (LUT6)
     1: west_data_o_psum_inferred_i_9__2/I1 (LUT6)
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /out[7]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /out[7]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /in0[7]
      : east_data_i_psum_inferred__0/out[7]
      : east_data_i_psum_inferred__0/in0[7]
      : east_data_i_psum_inferred/out[7]
      : east_data_i_psum_inferred/in0[7]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /out[7]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /out[7]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /in0[7]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /out[7]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /out[7]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /in0[7]
     2: west_data_o_psum_inferred_i_9__0/O (LUT6)
     3: west_data_o_psum_inferred_i_9__0/I2 (LUT6)
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[7]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[7]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[7]
      : west_data_i_psum_inferred__0/out[7]
      : west_data_i_psum_inferred__0/in0[7]
      : west_data_i_psum_inferred/out[7]
      : west_data_i_psum_inferred/in0[7]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[7]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[7]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[7]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[7]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[7]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[7]
     4: west_data_o_psum_inferred_i_9__2/O (LUT6)
Inferred a: "set_disable_timing -from I1 -to O west_data_o_psum_inferred_i_9__2"
Found timing loop:
     0: west_data_o_psum_inferred_i_9__1/O (LUT6)
     1: west_data_o_psum_inferred_i_9__1/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /out[7]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /out[7]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /in0[7]
      : south_data_o_psum_inferred__2/out[7]
      : south_data_o_psum_inferred__2/in0[7]
      : south_data_o_psum_inferred__1/out[7]
      : south_data_o_psum_inferred__1/in0[7]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[7]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[7]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[7]
     2: west_data_o_psum_inferred_i_9__0/O (LUT6)
     3: west_data_o_psum_inferred_i_9__0/I2 (LUT6)
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[7]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[7]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[7]
      : west_data_i_psum_inferred__0/out[7]
      : west_data_i_psum_inferred__0/in0[7]
      : west_data_i_psum_inferred/out[7]
      : west_data_i_psum_inferred/in0[7]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[7]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[7]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[7]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[7]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[7]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[7]
     4: west_data_o_psum_inferred_i_9__2/O (LUT6)
     5: west_data_o_psum_inferred_i_9__2/I0 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[7]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[7]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[7]
      : south_data_i_psum_inferred__0/out[7]
      : south_data_i_psum_inferred__0/in0[7]
      : south_data_i_psum_inferred/out[7]
      : south_data_i_psum_inferred/in0[7]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[7]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[7]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[7]
     6: west_data_o_psum_inferred_i_9/O (LUT6)
     7: west_data_o_psum_inferred_i_9/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /out[7]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /out[7]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /in0[7]
      : north_data_i_psum_inferred__0/out[7]
      : north_data_i_psum_inferred__0/in0[7]
      : north_data_i_psum_inferred/out[7]
      : north_data_i_psum_inferred/in0[7]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /out[7]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /in0[7]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /out[7]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /in0[7]
     8: west_data_o_psum_inferred_i_9__2/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_psum_inferred_i_9__1"
Found timing loop:
     0: west_data_o_psum_inferred_i_9__2/O (LUT6)
     1: west_data_o_psum_inferred_i_9__2/O (LUT6)
Found timing loop:
     0: west_data_o_psum_inferred_i_9__2/O (LUT6)
     1: west_data_o_psum_inferred_i_9__2/O (LUT6)
Found timing loop:
     0: west_data_o_psum_inferred_i_5__0/O (LUT6)
     1: west_data_o_psum_inferred_i_5__0/I3 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[11]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[11]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[11]
      : south_data_i_psum_inferred__2/out[11]
      : south_data_i_psum_inferred__2/in0[11]
      : south_data_i_psum_inferred__1/out[11]
      : south_data_i_psum_inferred__1/in0[11]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[11]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[11]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[11]
     2: west_data_o_psum_inferred_i_5__1/O (LUT6)
     3: west_data_o_psum_inferred_i_5__1/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /out[11]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /out[11]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /in0[11]
      : south_data_o_psum_inferred__2/out[11]
      : south_data_o_psum_inferred__2/in0[11]
      : south_data_o_psum_inferred__1/out[11]
      : south_data_o_psum_inferred__1/in0[11]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[11]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[11]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[11]
     4: west_data_o_psum_inferred_i_5__0/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_psum_inferred_i_5__0"
Found timing loop:
     0: west_data_o_psum_inferred_i_5__2/O (LUT6)
     1: west_data_o_psum_inferred_i_5__2/I1 (LUT6)
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /out[11]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /out[11]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /in0[11]
      : east_data_i_psum_inferred__0/out[11]
      : east_data_i_psum_inferred__0/in0[11]
      : east_data_i_psum_inferred/out[11]
      : east_data_i_psum_inferred/in0[11]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /out[11]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /out[11]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /in0[11]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /out[11]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /out[11]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /in0[11]
     2: west_data_o_psum_inferred_i_5__0/O (LUT6)
     3: west_data_o_psum_inferred_i_5__0/I2 (LUT6)
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[11]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[11]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[11]
      : west_data_i_psum_inferred__0/out[11]
      : west_data_i_psum_inferred__0/in0[11]
      : west_data_i_psum_inferred/out[11]
      : west_data_i_psum_inferred/in0[11]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[11]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[11]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[11]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[11]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[11]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[11]
     4: west_data_o_psum_inferred_i_5__2/O (LUT6)
Inferred a: "set_disable_timing -from I1 -to O west_data_o_psum_inferred_i_5__2"
Found timing loop:
     0: west_data_o_psum_inferred_i_5__1/O (LUT6)
     1: west_data_o_psum_inferred_i_5__1/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /out[11]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /out[11]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /in0[11]
      : south_data_o_psum_inferred__2/out[11]
      : south_data_o_psum_inferred__2/in0[11]
      : south_data_o_psum_inferred__1/out[11]
      : south_data_o_psum_inferred__1/in0[11]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[11]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[11]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[11]
     2: west_data_o_psum_inferred_i_5__0/O (LUT6)
     3: west_data_o_psum_inferred_i_5__0/I2 (LUT6)
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[11]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[11]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[11]
      : west_data_i_psum_inferred__0/out[11]
      : west_data_i_psum_inferred__0/in0[11]
      : west_data_i_psum_inferred/out[11]
      : west_data_i_psum_inferred/in0[11]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[11]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[11]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[11]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[11]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[11]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[11]
     4: west_data_o_psum_inferred_i_5__2/O (LUT6)
     5: west_data_o_psum_inferred_i_5__2/I0 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[11]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[11]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[11]
      : south_data_i_psum_inferred__0/out[11]
      : south_data_i_psum_inferred__0/in0[11]
      : south_data_i_psum_inferred/out[11]
      : south_data_i_psum_inferred/in0[11]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[11]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[11]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[11]
     6: west_data_o_psum_inferred_i_5/O (LUT6)
     7: west_data_o_psum_inferred_i_5/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /out[11]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /out[11]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /in0[11]
      : north_data_i_psum_inferred__0/out[11]
      : north_data_i_psum_inferred__0/in0[11]
      : north_data_i_psum_inferred/out[11]
      : north_data_i_psum_inferred/in0[11]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /out[11]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /in0[11]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /out[11]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /in0[11]
     8: west_data_o_psum_inferred_i_5__2/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_psum_inferred_i_5__1"
Found timing loop:
     0: west_data_o_psum_inferred_i_5__2/O (LUT6)
     1: west_data_o_psum_inferred_i_5__2/O (LUT6)
Found timing loop:
     0: west_data_o_psum_inferred_i_5__2/O (LUT6)
     1: west_data_o_psum_inferred_i_5__2/O (LUT6)
Found timing loop:
     0: west_data_o_psum_inferred_i_4__0/O (LUT6)
     1: west_data_o_psum_inferred_i_4__0/I3 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[12]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[12]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[12]
      : south_data_i_psum_inferred__2/out[12]
      : south_data_i_psum_inferred__2/in0[12]
      : south_data_i_psum_inferred__1/out[12]
      : south_data_i_psum_inferred__1/in0[12]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[12]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[12]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[12]
     2: west_data_o_psum_inferred_i_4__1/O (LUT6)
     3: west_data_o_psum_inferred_i_4__1/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /out[12]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /out[12]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /in0[12]
      : south_data_o_psum_inferred__2/out[12]
      : south_data_o_psum_inferred__2/in0[12]
      : south_data_o_psum_inferred__1/out[12]
      : south_data_o_psum_inferred__1/in0[12]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[12]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[12]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[12]
     4: west_data_o_psum_inferred_i_4__0/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_psum_inferred_i_4__0"
Found timing loop:
     0: west_data_o_psum_inferred_i_4__2/O (LUT6)
     1: west_data_o_psum_inferred_i_4__2/I1 (LUT6)
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /out[12]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /out[12]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /in0[12]
      : east_data_i_psum_inferred__0/out[12]
      : east_data_i_psum_inferred__0/in0[12]
      : east_data_i_psum_inferred/out[12]
      : east_data_i_psum_inferred/in0[12]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /out[12]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /out[12]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /in0[12]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /out[12]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /out[12]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /in0[12]
     2: west_data_o_psum_inferred_i_4__0/O (LUT6)
     3: west_data_o_psum_inferred_i_4__0/I2 (LUT6)
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[12]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[12]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[12]
      : west_data_i_psum_inferred__0/out[12]
      : west_data_i_psum_inferred__0/in0[12]
      : west_data_i_psum_inferred/out[12]
      : west_data_i_psum_inferred/in0[12]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[12]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[12]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[12]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[12]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[12]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[12]
     4: west_data_o_psum_inferred_i_4__2/O (LUT6)
Inferred a: "set_disable_timing -from I1 -to O west_data_o_psum_inferred_i_4__2"
Found timing loop:
     0: west_data_o_psum_inferred_i_4__1/O (LUT6)
     1: west_data_o_psum_inferred_i_4__1/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /out[12]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /out[12]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /in0[12]
      : south_data_o_psum_inferred__2/out[12]
      : south_data_o_psum_inferred__2/in0[12]
      : south_data_o_psum_inferred__1/out[12]
      : south_data_o_psum_inferred__1/in0[12]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[12]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[12]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[12]
     2: west_data_o_psum_inferred_i_4__0/O (LUT6)
     3: west_data_o_psum_inferred_i_4__0/I2 (LUT6)
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[12]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[12]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[12]
      : west_data_i_psum_inferred__0/out[12]
      : west_data_i_psum_inferred__0/in0[12]
      : west_data_i_psum_inferred/out[12]
      : west_data_i_psum_inferred/in0[12]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[12]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[12]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[12]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[12]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[12]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[12]
     4: west_data_o_psum_inferred_i_4__2/O (LUT6)
     5: west_data_o_psum_inferred_i_4__2/I0 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[12]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[12]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[12]
      : south_data_i_psum_inferred__0/out[12]
      : south_data_i_psum_inferred__0/in0[12]
      : south_data_i_psum_inferred/out[12]
      : south_data_i_psum_inferred/in0[12]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[12]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[12]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[12]
     6: west_data_o_psum_inferred_i_4/O (LUT6)
     7: west_data_o_psum_inferred_i_4/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /out[12]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /out[12]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /in0[12]
      : north_data_i_psum_inferred__0/out[12]
      : north_data_i_psum_inferred__0/in0[12]
      : north_data_i_psum_inferred/out[12]
      : north_data_i_psum_inferred/in0[12]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /out[12]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /in0[12]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /out[12]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /in0[12]
     8: west_data_o_psum_inferred_i_4__2/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_psum_inferred_i_4__1"
Found timing loop:
     0: west_data_o_psum_inferred_i_4__2/O (LUT6)
     1: west_data_o_psum_inferred_i_4__2/O (LUT6)
Found timing loop:
     0: west_data_o_psum_inferred_i_4__2/O (LUT6)
     1: west_data_o_psum_inferred_i_4__2/O (LUT6)
Found timing loop:
     0: west_data_o_wght_inferred_i_16__0/O (LUT6)
     1: west_data_o_wght_inferred_i_16__0/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /out[0]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /in0[0]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /out[0]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /in0[0]
      : north_data_i_wght_inferred__0/out[0]
      : north_data_i_wght_inferred__0/in0[0]
      : north_data_i_wght_inferred/out[0]
      : north_data_i_wght_inferred/in0[0]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /out[0]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /in0[0]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /out[0]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /in0[0]
     2: west_data_o_wght_inferred_i_16/O (LUT6)
     3: west_data_o_wght_inferred_i_16/I2 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /out[0]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /in0[0]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /out[0]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /in0[0]
      : south_data_i_wght_inferred__0/out[0]
      : south_data_i_wght_inferred__0/in0[0]
      : south_data_i_wght_inferred/out[0]
      : south_data_i_wght_inferred/in0[0]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /out[0]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /in0[0]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /out[0]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /in0[0]
     4: west_data_o_wght_inferred_i_16__0/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_wght_inferred_i_16__0"
Found timing loop:
     0: west_data_o_wght_inferred_i_15__0/O (LUT6)
     1: west_data_o_wght_inferred_i_15__0/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /out[1]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /in0[1]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /out[1]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /in0[1]
      : north_data_i_wght_inferred__0/out[1]
      : north_data_i_wght_inferred__0/in0[1]
      : north_data_i_wght_inferred/out[1]
      : north_data_i_wght_inferred/in0[1]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /out[1]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /in0[1]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /out[1]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /in0[1]
     2: west_data_o_wght_inferred_i_15/O (LUT6)
     3: west_data_o_wght_inferred_i_15/I3 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /out[1]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /in0[1]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /out[1]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /in0[1]
      : south_data_i_wght_inferred__0/out[1]
      : south_data_i_wght_inferred__0/in0[1]
      : south_data_i_wght_inferred/out[1]
      : south_data_i_wght_inferred/in0[1]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /out[1]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /in0[1]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /out[1]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /in0[1]
     4: west_data_o_wght_inferred_i_15__0/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_wght_inferred_i_15__0"
Found timing loop:
     0: west_data_o_wght_inferred_i_14__0/O (LUT6)
     1: west_data_o_wght_inferred_i_14__0/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /out[2]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /in0[2]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /out[2]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /in0[2]
      : north_data_i_wght_inferred__0/out[2]
      : north_data_i_wght_inferred__0/in0[2]
      : north_data_i_wght_inferred/out[2]
      : north_data_i_wght_inferred/in0[2]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /out[2]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /in0[2]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /out[2]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /in0[2]
     2: west_data_o_wght_inferred_i_14/O (LUT6)
     3: west_data_o_wght_inferred_i_14/I2 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /out[2]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /in0[2]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /out[2]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /in0[2]
      : south_data_i_wght_inferred__0/out[2]
      : south_data_i_wght_inferred__0/in0[2]
      : south_data_i_wght_inferred/out[2]
      : south_data_i_wght_inferred/in0[2]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /out[2]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /in0[2]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /out[2]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /in0[2]
     4: west_data_o_wght_inferred_i_14__0/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_wght_inferred_i_14__0"
Found timing loop:
     0: west_data_o_wght_inferred_i_13__0/O (LUT6)
     1: west_data_o_wght_inferred_i_13__0/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /out[3]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /in0[3]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /out[3]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /in0[3]
      : north_data_i_wght_inferred__0/out[3]
      : north_data_i_wght_inferred__0/in0[3]
      : north_data_i_wght_inferred/out[3]
      : north_data_i_wght_inferred/in0[3]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /out[3]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /in0[3]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /out[3]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /in0[3]
     2: west_data_o_wght_inferred_i_13/O (LUT6)
     3: west_data_o_wght_inferred_i_13/I3 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /out[3]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /in0[3]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /out[3]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /in0[3]
      : south_data_i_wght_inferred__0/out[3]
      : south_data_i_wght_inferred__0/in0[3]
      : south_data_i_wght_inferred/out[3]
      : south_data_i_wght_inferred/in0[3]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /out[3]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /in0[3]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /out[3]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /in0[3]
     4: west_data_o_wght_inferred_i_13__0/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_wght_inferred_i_13__0"
Found timing loop:
     0: west_data_o_wght_inferred_i_12__0/O (LUT6)
     1: west_data_o_wght_inferred_i_12__0/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /out[4]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /in0[4]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /out[4]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /in0[4]
      : north_data_i_wght_inferred__0/out[4]
      : north_data_i_wght_inferred__0/in0[4]
      : north_data_i_wght_inferred/out[4]
      : north_data_i_wght_inferred/in0[4]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /out[4]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /in0[4]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /out[4]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /in0[4]
     2: west_data_o_wght_inferred_i_12/O (LUT6)
     3: west_data_o_wght_inferred_i_12/I2 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /out[4]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /in0[4]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /out[4]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /in0[4]
      : south_data_i_wght_inferred__0/out[4]
      : south_data_i_wght_inferred__0/in0[4]
      : south_data_i_wght_inferred/out[4]
      : south_data_i_wght_inferred/in0[4]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /out[4]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /in0[4]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /out[4]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /in0[4]
     4: west_data_o_wght_inferred_i_12__0/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_wght_inferred_i_12__0"
Found timing loop:
     0: west_data_o_wght_inferred_i_11__0/O (LUT6)
     1: west_data_o_wght_inferred_i_11__0/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /out[5]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /in0[5]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /out[5]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /in0[5]
      : north_data_i_wght_inferred__0/out[5]
      : north_data_i_wght_inferred__0/in0[5]
      : north_data_i_wght_inferred/out[5]
      : north_data_i_wght_inferred/in0[5]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /out[5]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /in0[5]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /out[5]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /in0[5]
     2: west_data_o_wght_inferred_i_11/O (LUT6)
     3: west_data_o_wght_inferred_i_11/I2 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /out[5]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /in0[5]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /out[5]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /in0[5]
      : south_data_i_wght_inferred__0/out[5]
      : south_data_i_wght_inferred__0/in0[5]
      : south_data_i_wght_inferred/out[5]
      : south_data_i_wght_inferred/in0[5]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /out[5]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /in0[5]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /out[5]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /in0[5]
     4: west_data_o_wght_inferred_i_11__0/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_wght_inferred_i_11__0"
Found timing loop:
     0: west_data_o_wght_inferred_i_10__0/O (LUT6)
     1: west_data_o_wght_inferred_i_10__0/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /out[6]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /in0[6]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /out[6]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /in0[6]
      : north_data_i_wght_inferred__0/out[6]
      : north_data_i_wght_inferred__0/in0[6]
      : north_data_i_wght_inferred/out[6]
      : north_data_i_wght_inferred/in0[6]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /out[6]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /in0[6]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /out[6]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /in0[6]
     2: west_data_o_wght_inferred_i_10/O (LUT6)
     3: west_data_o_wght_inferred_i_10/I2 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /out[6]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /in0[6]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /out[6]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /in0[6]
      : south_data_i_wght_inferred__0/out[6]
      : south_data_i_wght_inferred__0/in0[6]
      : south_data_i_wght_inferred/out[6]
      : south_data_i_wght_inferred/in0[6]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /out[6]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /in0[6]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /out[6]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /in0[6]
     4: west_data_o_wght_inferred_i_10__0/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_wght_inferred_i_10__0"
Found timing loop:
     0: west_data_o_wght_inferred_i_9__0/O (LUT6)
     1: west_data_o_wght_inferred_i_9__0/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /out[7]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /in0[7]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /out[7]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /in0[7]
      : north_data_i_wght_inferred__0/out[7]
      : north_data_i_wght_inferred__0/in0[7]
      : north_data_i_wght_inferred/out[7]
      : north_data_i_wght_inferred/in0[7]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /out[7]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /in0[7]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /out[7]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /in0[7]
     2: west_data_o_wght_inferred_i_9/O (LUT6)
     3: west_data_o_wght_inferred_i_9/I3 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /out[7]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /in0[7]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /out[7]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /in0[7]
      : south_data_i_wght_inferred__0/out[7]
      : south_data_i_wght_inferred__0/in0[7]
      : south_data_i_wght_inferred/out[7]
      : south_data_i_wght_inferred/in0[7]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /out[7]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /in0[7]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /out[7]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /in0[7]
     4: west_data_o_wght_inferred_i_9__0/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_wght_inferred_i_9__0"
Found timing loop:
     0: west_data_o_wght_inferred_i_8__0/O (LUT6)
     1: west_data_o_wght_inferred_i_8__0/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /out[8]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /in0[8]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /out[8]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /in0[8]
      : north_data_i_wght_inferred__0/out[8]
      : north_data_i_wght_inferred__0/in0[8]
      : north_data_i_wght_inferred/out[8]
      : north_data_i_wght_inferred/in0[8]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /out[8]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /in0[8]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /out[8]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /in0[8]
     2: west_data_o_wght_inferred_i_8/O (LUT6)
     3: west_data_o_wght_inferred_i_8/I2 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /out[8]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /in0[8]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /out[8]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /in0[8]
      : south_data_i_wght_inferred__0/out[8]
      : south_data_i_wght_inferred__0/in0[8]
      : south_data_i_wght_inferred/out[8]
      : south_data_i_wght_inferred/in0[8]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /out[8]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /in0[8]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /out[8]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /in0[8]
     4: west_data_o_wght_inferred_i_8__0/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_wght_inferred_i_8__0"
Found timing loop:
     0: west_data_o_wght_inferred_i_7__0/O (LUT6)
     1: west_data_o_wght_inferred_i_7__0/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /out[9]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /in0[9]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /out[9]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /in0[9]
      : north_data_i_wght_inferred__0/out[9]
      : north_data_i_wght_inferred__0/in0[9]
      : north_data_i_wght_inferred/out[9]
      : north_data_i_wght_inferred/in0[9]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /out[9]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /in0[9]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /out[9]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /in0[9]
     2: west_data_o_wght_inferred_i_7/O (LUT6)
     3: west_data_o_wght_inferred_i_7/I2 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /out[9]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /in0[9]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /out[9]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /in0[9]
      : south_data_i_wght_inferred__0/out[9]
      : south_data_i_wght_inferred__0/in0[9]
      : south_data_i_wght_inferred/out[9]
      : south_data_i_wght_inferred/in0[9]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /out[9]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /in0[9]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /out[9]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /in0[9]
     4: west_data_o_wght_inferred_i_7__0/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_wght_inferred_i_7__0"
Found timing loop:
     0: west_data_o_wght_inferred_i_6__0/O (LUT6)
     1: west_data_o_wght_inferred_i_6__0/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /out[10]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /in0[10]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /out[10]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /in0[10]
      : north_data_i_wght_inferred__0/out[10]
      : north_data_i_wght_inferred__0/in0[10]
      : north_data_i_wght_inferred/out[10]
      : north_data_i_wght_inferred/in0[10]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /out[10]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /in0[10]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /out[10]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /in0[10]
     2: west_data_o_wght_inferred_i_6/O (LUT6)
     3: west_data_o_wght_inferred_i_6/I2 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /out[10]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /in0[10]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /out[10]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /in0[10]
      : south_data_i_wght_inferred__0/out[10]
      : south_data_i_wght_inferred__0/in0[10]
      : south_data_i_wght_inferred/out[10]
      : south_data_i_wght_inferred/in0[10]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /out[10]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /in0[10]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /out[10]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /in0[10]
     4: west_data_o_wght_inferred_i_6__0/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_wght_inferred_i_6__0"
Found timing loop:
     0: west_data_o_wght_inferred_i_5__0/O (LUT6)
     1: west_data_o_wght_inferred_i_5__0/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /out[11]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /in0[11]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /out[11]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /in0[11]
      : north_data_i_wght_inferred__0/out[11]
      : north_data_i_wght_inferred__0/in0[11]
      : north_data_i_wght_inferred/out[11]
      : north_data_i_wght_inferred/in0[11]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /out[11]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /in0[11]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /out[11]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /in0[11]
     2: west_data_o_wght_inferred_i_5/O (LUT6)
     3: west_data_o_wght_inferred_i_5/I3 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /out[11]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /in0[11]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /out[11]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /in0[11]
      : south_data_i_wght_inferred__0/out[11]
      : south_data_i_wght_inferred__0/in0[11]
      : south_data_i_wght_inferred/out[11]
      : south_data_i_wght_inferred/in0[11]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /out[11]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /in0[11]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /out[11]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /in0[11]
     4: west_data_o_wght_inferred_i_5__0/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_wght_inferred_i_5__0"
Found timing loop:
     0: west_data_o_wght_inferred_i_4__0/O (LUT6)
     1: west_data_o_wght_inferred_i_4__0/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /out[12]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /in0[12]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /out[12]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /in0[12]
      : north_data_i_wght_inferred__0/out[12]
      : north_data_i_wght_inferred__0/in0[12]
      : north_data_i_wght_inferred/out[12]
      : north_data_i_wght_inferred/in0[12]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /out[12]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /in0[12]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /out[12]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /in0[12]
     2: west_data_o_wght_inferred_i_4/O (LUT6)
     3: west_data_o_wght_inferred_i_4/I3 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /out[12]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /in0[12]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /out[12]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /in0[12]
      : south_data_i_wght_inferred__0/out[12]
      : south_data_i_wght_inferred__0/in0[12]
      : south_data_i_wght_inferred/out[12]
      : south_data_i_wght_inferred/in0[12]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /out[12]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /in0[12]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /out[12]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /in0[12]
     4: west_data_o_wght_inferred_i_4__0/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_wght_inferred_i_4__0"
Found timing loop:
     0: west_data_o_wght_inferred_i_3__0/O (LUT6)
     1: west_data_o_wght_inferred_i_3__0/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /out[13]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /in0[13]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /out[13]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /in0[13]
      : north_data_i_wght_inferred__0/out[13]
      : north_data_i_wght_inferred__0/in0[13]
      : north_data_i_wght_inferred/out[13]
      : north_data_i_wght_inferred/in0[13]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /out[13]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /in0[13]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /out[13]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /in0[13]
     2: west_data_o_wght_inferred_i_3/O (LUT6)
     3: west_data_o_wght_inferred_i_3/I2 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /out[13]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /in0[13]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /out[13]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /in0[13]
      : south_data_i_wght_inferred__0/out[13]
      : south_data_i_wght_inferred__0/in0[13]
      : south_data_i_wght_inferred/out[13]
      : south_data_i_wght_inferred/in0[13]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /out[13]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /in0[13]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /out[13]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /in0[13]
     4: west_data_o_wght_inferred_i_3__0/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_wght_inferred_i_3__0"
Found timing loop:
     0: west_data_o_wght_inferred_i_2__0/O (LUT6)
     1: west_data_o_wght_inferred_i_2__0/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /out[14]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /in0[14]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /out[14]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /in0[14]
      : north_data_i_wght_inferred__0/out[14]
      : north_data_i_wght_inferred__0/in0[14]
      : north_data_i_wght_inferred/out[14]
      : north_data_i_wght_inferred/in0[14]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /out[14]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /in0[14]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /out[14]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /in0[14]
     2: west_data_o_wght_inferred_i_2/O (LUT6)
     3: west_data_o_wght_inferred_i_2/I3 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /out[14]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /in0[14]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /out[14]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /in0[14]
      : south_data_i_wght_inferred__0/out[14]
      : south_data_i_wght_inferred__0/in0[14]
      : south_data_i_wght_inferred/out[14]
      : south_data_i_wght_inferred/in0[14]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /out[14]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /in0[14]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /out[14]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /in0[14]
     4: west_data_o_wght_inferred_i_2__0/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_wght_inferred_i_2__0"
Found timing loop:
     0: west_data_o_wght_inferred_i_1__0/O (LUT6)
     1: west_data_o_wght_inferred_i_1__0/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /out[15]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred__0 /in0[15]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /out[15]
      : \HMNoC_cluster_west_1/north_data_i_wght_inferred /in0[15]
      : north_data_i_wght_inferred__0/out[15]
      : north_data_i_wght_inferred__0/in0[15]
      : north_data_i_wght_inferred/out[15]
      : north_data_i_wght_inferred/in0[15]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /out[15]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred__0 /in0[15]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /out[15]
      : \HMNoC_cluster_west_0/south_data_o_wght_inferred /in0[15]
     2: west_data_o_wght_inferred_i_1/O (LUT6)
     3: west_data_o_wght_inferred_i_1/I3 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /out[15]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred__0 /in0[15]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /out[15]
      : \HMNoC_cluster_west_0/south_data_i_wght_inferred /in0[15]
      : south_data_i_wght_inferred__0/out[15]
      : south_data_i_wght_inferred__0/in0[15]
      : south_data_i_wght_inferred/out[15]
      : south_data_i_wght_inferred/in0[15]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /out[15]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred__0 /in0[15]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /out[15]
      : \HMNoC_cluster_west_1/north_data_o_wght_inferred /in0[15]
     4: west_data_o_wght_inferred_i_1__0/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_wght_inferred_i_1__0"
Found timing loop:
     0: west_data_o_iact_inferred_i_16__1/O (LUT6)
     1: west_data_o_iact_inferred_i_16__1/I3 (LUT6)
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /out[0]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /in0[0]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /out[0]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /in0[0]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /out[0]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /in0[0]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /out[0]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /in0[0]
      : west_data_i_iact_inferred__0/out[0]
      : west_data_i_iact_inferred__0/in0[0]
      : west_data_i_iact_inferred/out[0]
      : west_data_i_iact_inferred/in0[0]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /out[0]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /in0[0]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /out[0]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /in0[0]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /out[0]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /in0[0]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /out[0]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /in0[0]
     2: west_data_o_iact_inferred_i_16/O (LUT6)
     3: west_data_o_iact_inferred_i_16/I3 (LUT6)
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /out[0]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /in0[0]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /out[0]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /in0[0]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /out[0]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /in0[0]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /out[0]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /in0[0]
      : east_data_i_iact_inferred__0/out[0]
      : east_data_i_iact_inferred__0/in0[0]
      : east_data_i_iact_inferred/out[0]
      : east_data_i_iact_inferred/in0[0]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /out[0]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /in0[0]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /out[0]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /in0[0]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /out[0]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /in0[0]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /out[0]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /in0[0]
     4: west_data_o_iact_inferred_i_16__1/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_iact_inferred_i_16__1"
Found timing loop:
     0: west_data_o_iact_inferred_i_16/O (LUT6)
     1: west_data_o_iact_inferred_i_16/I3 (LUT6)
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /out[0]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /in0[0]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /out[0]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /in0[0]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /out[0]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /in0[0]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /out[0]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /in0[0]
      : east_data_i_iact_inferred__0/out[0]
      : east_data_i_iact_inferred__0/in0[0]
      : east_data_i_iact_inferred/out[0]
      : east_data_i_iact_inferred/in0[0]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /out[0]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /in0[0]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /out[0]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /in0[0]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /out[0]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /in0[0]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /out[0]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /in0[0]
     2: west_data_o_iact_inferred_i_16__1/O (LUT6)
     3: west_data_o_iact_inferred_i_16__1/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_iact_inferred_i_16"
Found timing loop:
     0: west_data_o_iact_inferred_i_16__1/O (LUT6)
     1: west_data_o_iact_inferred_i_16__1/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /out[0]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /in0[0]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /out[0]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /in0[0]
      : south_data_i_iact_inferred__2/out[0]
      : south_data_i_iact_inferred__2/in0[0]
      : south_data_i_iact_inferred__1/out[0]
      : south_data_i_iact_inferred__1/in0[0]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /out[0]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /in0[0]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /out[0]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /in0[0]
     2: west_data_o_iact_inferred_i_16__2/O (LUT6)
     3: west_data_o_iact_inferred_i_16__2/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /out[0]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /in0[0]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /out[0]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /in0[0]
      : north_data_i_iact_inferred__2/out[0]
      : north_data_i_iact_inferred__2/in0[0]
      : north_data_i_iact_inferred__1/out[0]
      : north_data_i_iact_inferred__1/in0[0]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /out[0]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /in0[0]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /out[0]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /in0[0]
     4: west_data_o_iact_inferred_i_16__1/O (LUT6)
Inferred a: "set_disable_timing -from I2 -to O west_data_o_iact_inferred_i_16__1"
Found timing loop:
     0: west_data_o_iact_inferred_i_16__0/O (LUT6)
     1: west_data_o_iact_inferred_i_16__0/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /out[0]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /in0[0]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /out[0]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /in0[0]
      : north_data_i_iact_inferred__0/out[0]
      : north_data_i_iact_inferred__0/in0[0]
      : north_data_i_iact_inferred/out[0]
      : north_data_i_iact_inferred/in0[0]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /out[0]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /in0[0]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /out[0]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /in0[0]
     2: west_data_o_iact_inferred_i_16/O (LUT6)
     3: west_data_o_iact_inferred_i_16/I2 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /out[0]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /in0[0]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /out[0]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /in0[0]
      : south_data_i_iact_inferred__0/out[0]
      : south_data_i_iact_inferred__0/in0[0]
      : south_data_i_iact_inferred/out[0]
      : south_data_i_iact_inferred/in0[0]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /out[0]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /in0[0]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /out[0]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /in0[0]
     4: west_data_o_iact_inferred_i_16__0/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_iact_inferred_i_16__0"
Found timing loop:
     0: west_data_o_iact_inferred_i_15__0/O (LUT6)
     1: west_data_o_iact_inferred_i_15__0/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /out[1]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /in0[1]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /out[1]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /in0[1]
      : north_data_i_iact_inferred__0/out[1]
      : north_data_i_iact_inferred__0/in0[1]
      : north_data_i_iact_inferred/out[1]
      : north_data_i_iact_inferred/in0[1]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /out[1]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /in0[1]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /out[1]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /in0[1]
     2: west_data_o_iact_inferred_i_15/O (LUT6)
     3: west_data_o_iact_inferred_i_15/I3 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /out[1]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /in0[1]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /out[1]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /in0[1]
      : south_data_i_iact_inferred__0/out[1]
      : south_data_i_iact_inferred__0/in0[1]
      : south_data_i_iact_inferred/out[1]
      : south_data_i_iact_inferred/in0[1]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /out[1]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /in0[1]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /out[1]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /in0[1]
     4: west_data_o_iact_inferred_i_15__0/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_iact_inferred_i_15__0"
Found timing loop:
     0: west_data_o_iact_inferred_i_15__1/O (LUT6)
     1: west_data_o_iact_inferred_i_15__1/I3 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /out[1]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /in0[1]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /out[1]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /in0[1]
      : south_data_i_iact_inferred__2/out[1]
      : south_data_i_iact_inferred__2/in0[1]
      : south_data_i_iact_inferred__1/out[1]
      : south_data_i_iact_inferred__1/in0[1]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /out[1]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /in0[1]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /out[1]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /in0[1]
     2: west_data_o_iact_inferred_i_15__2/O (LUT6)
     3: west_data_o_iact_inferred_i_15__2/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /out[1]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /in0[1]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /out[1]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /in0[1]
      : north_data_i_iact_inferred__2/out[1]
      : north_data_i_iact_inferred__2/in0[1]
      : north_data_i_iact_inferred__1/out[1]
      : north_data_i_iact_inferred__1/in0[1]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /out[1]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /in0[1]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /out[1]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /in0[1]
     4: west_data_o_iact_inferred_i_15__1/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_iact_inferred_i_15__1"
Found timing loop:
     0: west_data_o_iact_inferred_i_15__0/O (LUT6)
     1: west_data_o_iact_inferred_i_15__0/I2 (LUT6)
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /out[1]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /in0[1]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /out[1]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /in0[1]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /out[1]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /in0[1]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /out[1]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /in0[1]
      : east_data_i_iact_inferred__2/out[1]
      : east_data_i_iact_inferred__2/in0[1]
      : east_data_i_iact_inferred__1/out[1]
      : east_data_i_iact_inferred__1/in0[1]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /out[1]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /in0[1]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /out[1]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /in0[1]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /out[1]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /in0[1]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /out[1]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /in0[1]
     2: west_data_o_iact_inferred_i_15__2/O (LUT6)
     3: west_data_o_iact_inferred_i_15__2/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /out[1]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /in0[1]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /out[1]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /in0[1]
      : north_data_i_iact_inferred__2/out[1]
      : north_data_i_iact_inferred__2/in0[1]
      : north_data_i_iact_inferred__1/out[1]
      : north_data_i_iact_inferred__1/in0[1]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /out[1]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /in0[1]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /out[1]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /in0[1]
     4: west_data_o_iact_inferred_i_15__1/O (LUT6)
     5: west_data_o_iact_inferred_i_15__1/I2 (LUT6)
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /out[1]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /in0[1]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /out[1]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /in0[1]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /out[1]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /in0[1]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /out[1]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /in0[1]
      : west_data_i_iact_inferred__0/out[1]
      : west_data_i_iact_inferred__0/in0[1]
      : west_data_i_iact_inferred/out[1]
      : west_data_i_iact_inferred/in0[1]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /out[1]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /in0[1]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /out[1]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /in0[1]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /out[1]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /in0[1]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /out[1]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /in0[1]
     6: west_data_o_iact_inferred_i_15/O (LUT6)
     7: west_data_o_iact_inferred_i_15/I3 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /out[1]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /in0[1]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /out[1]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /in0[1]
      : south_data_i_iact_inferred__0/out[1]
      : south_data_i_iact_inferred__0/in0[1]
      : south_data_i_iact_inferred/out[1]
      : south_data_i_iact_inferred/in0[1]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /out[1]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /in0[1]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /out[1]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /in0[1]
     8: west_data_o_iact_inferred_i_15__0/O (LUT6)
Inferred a: "set_disable_timing -from I2 -to O west_data_o_iact_inferred_i_15__0"
Found timing loop:
     0: west_data_o_iact_inferred_i_15/O (LUT6)
     1: west_data_o_iact_inferred_i_15/I3 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /out[1]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /in0[1]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /out[1]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /in0[1]
      : south_data_i_iact_inferred__0/out[1]
      : south_data_i_iact_inferred__0/in0[1]
      : south_data_i_iact_inferred/out[1]
      : south_data_i_iact_inferred/in0[1]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /out[1]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /in0[1]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /out[1]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /in0[1]
     2: west_data_o_iact_inferred_i_15__0/O (LUT6)
     3: west_data_o_iact_inferred_i_15__0/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_iact_inferred_i_15"
Found timing loop:
     0: west_data_o_iact_inferred_i_14__1/O (LUT6)
     1: west_data_o_iact_inferred_i_14__1/I3 (LUT6)
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /out[2]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /in0[2]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /out[2]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /in0[2]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /out[2]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /in0[2]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /out[2]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /in0[2]
      : west_data_i_iact_inferred__0/out[2]
      : west_data_i_iact_inferred__0/in0[2]
      : west_data_i_iact_inferred/out[2]
      : west_data_i_iact_inferred/in0[2]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /out[2]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /in0[2]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /out[2]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /in0[2]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /out[2]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /in0[2]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /out[2]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /in0[2]
     2: west_data_o_iact_inferred_i_14/O (LUT6)
     3: west_data_o_iact_inferred_i_14/I3 (LUT6)
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /out[2]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /in0[2]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /out[2]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /in0[2]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /out[2]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /in0[2]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /out[2]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /in0[2]
      : east_data_i_iact_inferred__0/out[2]
      : east_data_i_iact_inferred__0/in0[2]
      : east_data_i_iact_inferred/out[2]
      : east_data_i_iact_inferred/in0[2]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /out[2]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /in0[2]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /out[2]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /in0[2]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /out[2]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /in0[2]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /out[2]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /in0[2]
     4: west_data_o_iact_inferred_i_14__1/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_iact_inferred_i_14__1"
Found timing loop:
     0: west_data_o_iact_inferred_i_14/O (LUT6)
     1: west_data_o_iact_inferred_i_14/I3 (LUT6)
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /out[2]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /in0[2]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /out[2]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /in0[2]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /out[2]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /in0[2]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /out[2]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /in0[2]
      : east_data_i_iact_inferred__0/out[2]
      : east_data_i_iact_inferred__0/in0[2]
      : east_data_i_iact_inferred/out[2]
      : east_data_i_iact_inferred/in0[2]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /out[2]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /in0[2]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /out[2]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /in0[2]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /out[2]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /in0[2]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /out[2]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /in0[2]
     2: west_data_o_iact_inferred_i_14__1/O (LUT6)
     3: west_data_o_iact_inferred_i_14__1/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_iact_inferred_i_14"
Found timing loop:
     0: west_data_o_iact_inferred_i_14__1/O (LUT6)
     1: west_data_o_iact_inferred_i_14__1/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /out[2]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /in0[2]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /out[2]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /in0[2]
      : south_data_i_iact_inferred__2/out[2]
      : south_data_i_iact_inferred__2/in0[2]
      : south_data_i_iact_inferred__1/out[2]
      : south_data_i_iact_inferred__1/in0[2]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /out[2]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /in0[2]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /out[2]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /in0[2]
     2: west_data_o_iact_inferred_i_14__2/O (LUT6)
     3: west_data_o_iact_inferred_i_14__2/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /out[2]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /in0[2]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /out[2]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /in0[2]
      : north_data_i_iact_inferred__2/out[2]
      : north_data_i_iact_inferred__2/in0[2]
      : north_data_i_iact_inferred__1/out[2]
      : north_data_i_iact_inferred__1/in0[2]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /out[2]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /in0[2]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /out[2]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /in0[2]
     4: west_data_o_iact_inferred_i_14__1/O (LUT6)
Inferred a: "set_disable_timing -from I2 -to O west_data_o_iact_inferred_i_14__1"
Found timing loop:
     0: west_data_o_iact_inferred_i_14__0/O (LUT6)
     1: west_data_o_iact_inferred_i_14__0/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /out[2]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /in0[2]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /out[2]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /in0[2]
      : north_data_i_iact_inferred__0/out[2]
      : north_data_i_iact_inferred__0/in0[2]
      : north_data_i_iact_inferred/out[2]
      : north_data_i_iact_inferred/in0[2]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /out[2]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /in0[2]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /out[2]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /in0[2]
     2: west_data_o_iact_inferred_i_14/O (LUT6)
     3: west_data_o_iact_inferred_i_14/I2 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /out[2]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /in0[2]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /out[2]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /in0[2]
      : south_data_i_iact_inferred__0/out[2]
      : south_data_i_iact_inferred__0/in0[2]
      : south_data_i_iact_inferred/out[2]
      : south_data_i_iact_inferred/in0[2]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /out[2]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /in0[2]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /out[2]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /in0[2]
     4: west_data_o_iact_inferred_i_14__0/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_iact_inferred_i_14__0"
Found timing loop:
     0: west_data_o_iact_inferred_i_13__0/O (LUT6)
     1: west_data_o_iact_inferred_i_13__0/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /out[3]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /in0[3]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /out[3]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /in0[3]
      : north_data_i_iact_inferred__0/out[3]
      : north_data_i_iact_inferred__0/in0[3]
      : north_data_i_iact_inferred/out[3]
      : north_data_i_iact_inferred/in0[3]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /out[3]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /in0[3]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /out[3]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /in0[3]
     2: west_data_o_iact_inferred_i_13/O (LUT6)
     3: west_data_o_iact_inferred_i_13/I3 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /out[3]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /in0[3]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /out[3]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /in0[3]
      : south_data_i_iact_inferred__0/out[3]
      : south_data_i_iact_inferred__0/in0[3]
      : south_data_i_iact_inferred/out[3]
      : south_data_i_iact_inferred/in0[3]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /out[3]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /in0[3]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /out[3]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /in0[3]
     4: west_data_o_iact_inferred_i_13__0/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_iact_inferred_i_13__0"
Found timing loop:
     0: west_data_o_iact_inferred_i_13__1/O (LUT6)
     1: west_data_o_iact_inferred_i_13__1/I3 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /out[3]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /in0[3]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /out[3]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /in0[3]
      : south_data_i_iact_inferred__2/out[3]
      : south_data_i_iact_inferred__2/in0[3]
      : south_data_i_iact_inferred__1/out[3]
      : south_data_i_iact_inferred__1/in0[3]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /out[3]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /in0[3]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /out[3]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /in0[3]
     2: west_data_o_iact_inferred_i_13__2/O (LUT6)
     3: west_data_o_iact_inferred_i_13__2/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /out[3]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /in0[3]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /out[3]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /in0[3]
      : north_data_i_iact_inferred__2/out[3]
      : north_data_i_iact_inferred__2/in0[3]
      : north_data_i_iact_inferred__1/out[3]
      : north_data_i_iact_inferred__1/in0[3]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /out[3]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /in0[3]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /out[3]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /in0[3]
     4: west_data_o_iact_inferred_i_13__1/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_iact_inferred_i_13__1"
Found timing loop:
     0: west_data_o_iact_inferred_i_13__0/O (LUT6)
     1: west_data_o_iact_inferred_i_13__0/I2 (LUT6)
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /out[3]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /in0[3]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /out[3]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /in0[3]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /out[3]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /in0[3]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /out[3]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /in0[3]
      : east_data_i_iact_inferred__2/out[3]
      : east_data_i_iact_inferred__2/in0[3]
      : east_data_i_iact_inferred__1/out[3]
      : east_data_i_iact_inferred__1/in0[3]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /out[3]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /in0[3]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /out[3]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /in0[3]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /out[3]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /in0[3]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /out[3]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /in0[3]
     2: west_data_o_iact_inferred_i_13__2/O (LUT6)
     3: west_data_o_iact_inferred_i_13__2/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /out[3]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /in0[3]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /out[3]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /in0[3]
      : north_data_i_iact_inferred__2/out[3]
      : north_data_i_iact_inferred__2/in0[3]
      : north_data_i_iact_inferred__1/out[3]
      : north_data_i_iact_inferred__1/in0[3]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /out[3]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /in0[3]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /out[3]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /in0[3]
     4: west_data_o_iact_inferred_i_13__1/O (LUT6)
     5: west_data_o_iact_inferred_i_13__1/I2 (LUT6)
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /out[3]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /in0[3]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /out[3]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /in0[3]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /out[3]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /in0[3]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /out[3]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /in0[3]
      : west_data_i_iact_inferred__0/out[3]
      : west_data_i_iact_inferred__0/in0[3]
      : west_data_i_iact_inferred/out[3]
      : west_data_i_iact_inferred/in0[3]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /out[3]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /in0[3]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /out[3]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /in0[3]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /out[3]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /in0[3]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /out[3]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /in0[3]
     6: west_data_o_iact_inferred_i_13/O (LUT6)
     7: west_data_o_iact_inferred_i_13/I3 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /out[3]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /in0[3]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /out[3]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /in0[3]
      : south_data_i_iact_inferred__0/out[3]
      : south_data_i_iact_inferred__0/in0[3]
      : south_data_i_iact_inferred/out[3]
      : south_data_i_iact_inferred/in0[3]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /out[3]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /in0[3]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /out[3]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /in0[3]
     8: west_data_o_iact_inferred_i_13__0/O (LUT6)
Inferred a: "set_disable_timing -from I2 -to O west_data_o_iact_inferred_i_13__0"
Found timing loop:
     0: west_data_o_iact_inferred_i_13/O (LUT6)
     1: west_data_o_iact_inferred_i_13/I3 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /out[3]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /in0[3]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /out[3]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /in0[3]
      : south_data_i_iact_inferred__0/out[3]
      : south_data_i_iact_inferred__0/in0[3]
      : south_data_i_iact_inferred/out[3]
      : south_data_i_iact_inferred/in0[3]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /out[3]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /in0[3]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /out[3]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /in0[3]
     2: west_data_o_iact_inferred_i_13__0/O (LUT6)
     3: west_data_o_iact_inferred_i_13__0/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_iact_inferred_i_13"
Found timing loop:
     0: west_data_o_iact_inferred_i_12__1/O (LUT6)
     1: west_data_o_iact_inferred_i_12__1/I3 (LUT6)
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /out[4]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /in0[4]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /out[4]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /in0[4]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /out[4]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /in0[4]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /out[4]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /in0[4]
      : west_data_i_iact_inferred__0/out[4]
      : west_data_i_iact_inferred__0/in0[4]
      : west_data_i_iact_inferred/out[4]
      : west_data_i_iact_inferred/in0[4]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /out[4]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /in0[4]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /out[4]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /in0[4]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /out[4]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /in0[4]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /out[4]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /in0[4]
     2: west_data_o_iact_inferred_i_12/O (LUT6)
     3: west_data_o_iact_inferred_i_12/I3 (LUT6)
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /out[4]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /in0[4]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /out[4]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /in0[4]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /out[4]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /in0[4]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /out[4]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /in0[4]
      : east_data_i_iact_inferred__0/out[4]
      : east_data_i_iact_inferred__0/in0[4]
      : east_data_i_iact_inferred/out[4]
      : east_data_i_iact_inferred/in0[4]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /out[4]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /in0[4]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /out[4]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /in0[4]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /out[4]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /in0[4]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /out[4]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /in0[4]
     4: west_data_o_iact_inferred_i_12__1/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_iact_inferred_i_12__1"
Found timing loop:
     0: west_data_o_iact_inferred_i_12/O (LUT6)
     1: west_data_o_iact_inferred_i_12/I3 (LUT6)
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /out[4]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /in0[4]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /out[4]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /in0[4]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /out[4]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /in0[4]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /out[4]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /in0[4]
      : east_data_i_iact_inferred__0/out[4]
      : east_data_i_iact_inferred__0/in0[4]
      : east_data_i_iact_inferred/out[4]
      : east_data_i_iact_inferred/in0[4]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /out[4]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /in0[4]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /out[4]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /in0[4]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /out[4]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /in0[4]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /out[4]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /in0[4]
     2: west_data_o_iact_inferred_i_12__1/O (LUT6)
     3: west_data_o_iact_inferred_i_12__1/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_iact_inferred_i_12"
Found timing loop:
     0: west_data_o_iact_inferred_i_12__1/O (LUT6)
     1: west_data_o_iact_inferred_i_12__1/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /out[4]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /in0[4]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /out[4]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /in0[4]
      : south_data_i_iact_inferred__2/out[4]
      : south_data_i_iact_inferred__2/in0[4]
      : south_data_i_iact_inferred__1/out[4]
      : south_data_i_iact_inferred__1/in0[4]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /out[4]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /in0[4]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /out[4]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /in0[4]
     2: west_data_o_iact_inferred_i_12__2/O (LUT6)
     3: west_data_o_iact_inferred_i_12__2/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /out[4]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /in0[4]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /out[4]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /in0[4]
      : north_data_i_iact_inferred__2/out[4]
      : north_data_i_iact_inferred__2/in0[4]
      : north_data_i_iact_inferred__1/out[4]
      : north_data_i_iact_inferred__1/in0[4]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /out[4]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /in0[4]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /out[4]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /in0[4]
     4: west_data_o_iact_inferred_i_12__1/O (LUT6)
Inferred a: "set_disable_timing -from I2 -to O west_data_o_iact_inferred_i_12__1"
Found timing loop:
     0: west_data_o_iact_inferred_i_12__0/O (LUT6)
     1: west_data_o_iact_inferred_i_12__0/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /out[4]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /in0[4]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /out[4]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /in0[4]
      : north_data_i_iact_inferred__0/out[4]
      : north_data_i_iact_inferred__0/in0[4]
      : north_data_i_iact_inferred/out[4]
      : north_data_i_iact_inferred/in0[4]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /out[4]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /in0[4]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /out[4]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /in0[4]
     2: west_data_o_iact_inferred_i_12/O (LUT6)
     3: west_data_o_iact_inferred_i_12/I2 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /out[4]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /in0[4]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /out[4]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /in0[4]
      : south_data_i_iact_inferred__0/out[4]
      : south_data_i_iact_inferred__0/in0[4]
      : south_data_i_iact_inferred/out[4]
      : south_data_i_iact_inferred/in0[4]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /out[4]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /in0[4]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /out[4]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /in0[4]
     4: west_data_o_iact_inferred_i_12__0/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_iact_inferred_i_12__0"
Found timing loop:
     0: west_data_o_iact_inferred_i_11__1/O (LUT6)
     1: west_data_o_iact_inferred_i_11__1/I3 (LUT6)
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /out[5]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /in0[5]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /out[5]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /in0[5]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /out[5]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /in0[5]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /out[5]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /in0[5]
      : west_data_i_iact_inferred__0/out[5]
      : west_data_i_iact_inferred__0/in0[5]
      : west_data_i_iact_inferred/out[5]
      : west_data_i_iact_inferred/in0[5]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /out[5]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /in0[5]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /out[5]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /in0[5]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /out[5]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /in0[5]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /out[5]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /in0[5]
     2: west_data_o_iact_inferred_i_11/O (LUT6)
     3: west_data_o_iact_inferred_i_11/I3 (LUT6)
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /out[5]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /in0[5]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /out[5]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /in0[5]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /out[5]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /in0[5]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /out[5]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /in0[5]
      : east_data_i_iact_inferred__0/out[5]
      : east_data_i_iact_inferred__0/in0[5]
      : east_data_i_iact_inferred/out[5]
      : east_data_i_iact_inferred/in0[5]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /out[5]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /in0[5]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /out[5]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /in0[5]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /out[5]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /in0[5]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /out[5]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /in0[5]
     4: west_data_o_iact_inferred_i_11__1/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_iact_inferred_i_11__1"
Found timing loop:
     0: west_data_o_iact_inferred_i_11/O (LUT6)
     1: west_data_o_iact_inferred_i_11/I3 (LUT6)
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /out[5]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /in0[5]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /out[5]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /in0[5]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /out[5]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /in0[5]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /out[5]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /in0[5]
      : east_data_i_iact_inferred__0/out[5]
      : east_data_i_iact_inferred__0/in0[5]
      : east_data_i_iact_inferred/out[5]
      : east_data_i_iact_inferred/in0[5]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /out[5]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /in0[5]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /out[5]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /in0[5]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /out[5]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /in0[5]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /out[5]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /in0[5]
     2: west_data_o_iact_inferred_i_11__1/O (LUT6)
     3: west_data_o_iact_inferred_i_11__1/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_iact_inferred_i_11"
Found timing loop:
     0: west_data_o_iact_inferred_i_11__1/O (LUT6)
     1: west_data_o_iact_inferred_i_11__1/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /out[5]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /in0[5]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /out[5]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /in0[5]
      : south_data_i_iact_inferred__2/out[5]
      : south_data_i_iact_inferred__2/in0[5]
      : south_data_i_iact_inferred__1/out[5]
      : south_data_i_iact_inferred__1/in0[5]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /out[5]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /in0[5]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /out[5]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /in0[5]
     2: west_data_o_iact_inferred_i_11__2/O (LUT6)
     3: west_data_o_iact_inferred_i_11__2/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /out[5]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /in0[5]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /out[5]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /in0[5]
      : north_data_i_iact_inferred__2/out[5]
      : north_data_i_iact_inferred__2/in0[5]
      : north_data_i_iact_inferred__1/out[5]
      : north_data_i_iact_inferred__1/in0[5]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /out[5]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /in0[5]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /out[5]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /in0[5]
     4: west_data_o_iact_inferred_i_11__1/O (LUT6)
Inferred a: "set_disable_timing -from I2 -to O west_data_o_iact_inferred_i_11__1"
Found timing loop:
     0: west_data_o_iact_inferred_i_11__0/O (LUT6)
     1: west_data_o_iact_inferred_i_11__0/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /out[5]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /in0[5]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /out[5]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /in0[5]
      : north_data_i_iact_inferred__0/out[5]
      : north_data_i_iact_inferred__0/in0[5]
      : north_data_i_iact_inferred/out[5]
      : north_data_i_iact_inferred/in0[5]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /out[5]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /in0[5]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /out[5]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /in0[5]
     2: west_data_o_iact_inferred_i_11/O (LUT6)
     3: west_data_o_iact_inferred_i_11/I2 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /out[5]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /in0[5]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /out[5]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /in0[5]
      : south_data_i_iact_inferred__0/out[5]
      : south_data_i_iact_inferred__0/in0[5]
      : south_data_i_iact_inferred/out[5]
      : south_data_i_iact_inferred/in0[5]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /out[5]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /in0[5]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /out[5]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /in0[5]
     4: west_data_o_iact_inferred_i_11__0/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_iact_inferred_i_11__0"
Found timing loop:
     0: west_data_o_iact_inferred_i_10__1/O (LUT6)
     1: west_data_o_iact_inferred_i_10__1/I3 (LUT6)
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /out[6]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /in0[6]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /out[6]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /in0[6]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /out[6]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /in0[6]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /out[6]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /in0[6]
      : west_data_i_iact_inferred__0/out[6]
      : west_data_i_iact_inferred__0/in0[6]
      : west_data_i_iact_inferred/out[6]
      : west_data_i_iact_inferred/in0[6]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /out[6]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /in0[6]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /out[6]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /in0[6]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /out[6]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /in0[6]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /out[6]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /in0[6]
     2: west_data_o_iact_inferred_i_10/O (LUT6)
     3: west_data_o_iact_inferred_i_10/I3 (LUT6)
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /out[6]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /in0[6]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /out[6]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /in0[6]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /out[6]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /in0[6]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /out[6]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /in0[6]
      : east_data_i_iact_inferred__0/out[6]
      : east_data_i_iact_inferred__0/in0[6]
      : east_data_i_iact_inferred/out[6]
      : east_data_i_iact_inferred/in0[6]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /out[6]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /in0[6]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /out[6]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /in0[6]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /out[6]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /in0[6]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /out[6]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /in0[6]
     4: west_data_o_iact_inferred_i_10__1/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_iact_inferred_i_10__1"
Found timing loop:
     0: west_data_o_iact_inferred_i_10/O (LUT6)
     1: west_data_o_iact_inferred_i_10/I3 (LUT6)
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /out[6]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /in0[6]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /out[6]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /in0[6]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /out[6]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /in0[6]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /out[6]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /in0[6]
      : east_data_i_iact_inferred__0/out[6]
      : east_data_i_iact_inferred__0/in0[6]
      : east_data_i_iact_inferred/out[6]
      : east_data_i_iact_inferred/in0[6]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /out[6]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /in0[6]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /out[6]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /in0[6]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /out[6]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /in0[6]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /out[6]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /in0[6]
     2: west_data_o_iact_inferred_i_10__1/O (LUT6)
     3: west_data_o_iact_inferred_i_10__1/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_iact_inferred_i_10"
Found timing loop:
     0: west_data_o_iact_inferred_i_10__1/O (LUT6)
     1: west_data_o_iact_inferred_i_10__1/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /out[6]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /in0[6]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /out[6]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /in0[6]
      : south_data_i_iact_inferred__2/out[6]
      : south_data_i_iact_inferred__2/in0[6]
      : south_data_i_iact_inferred__1/out[6]
      : south_data_i_iact_inferred__1/in0[6]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /out[6]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /in0[6]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /out[6]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /in0[6]
     2: west_data_o_iact_inferred_i_10__2/O (LUT6)
     3: west_data_o_iact_inferred_i_10__2/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /out[6]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /in0[6]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /out[6]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /in0[6]
      : north_data_i_iact_inferred__2/out[6]
      : north_data_i_iact_inferred__2/in0[6]
      : north_data_i_iact_inferred__1/out[6]
      : north_data_i_iact_inferred__1/in0[6]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /out[6]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /in0[6]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /out[6]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /in0[6]
     4: west_data_o_iact_inferred_i_10__1/O (LUT6)
Inferred a: "set_disable_timing -from I2 -to O west_data_o_iact_inferred_i_10__1"
Found timing loop:
     0: west_data_o_iact_inferred_i_10__0/O (LUT6)
     1: west_data_o_iact_inferred_i_10__0/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /out[6]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /in0[6]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /out[6]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /in0[6]
      : north_data_i_iact_inferred__0/out[6]
      : north_data_i_iact_inferred__0/in0[6]
      : north_data_i_iact_inferred/out[6]
      : north_data_i_iact_inferred/in0[6]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /out[6]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /in0[6]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /out[6]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /in0[6]
     2: west_data_o_iact_inferred_i_10/O (LUT6)
     3: west_data_o_iact_inferred_i_10/I2 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /out[6]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /in0[6]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /out[6]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /in0[6]
      : south_data_i_iact_inferred__0/out[6]
      : south_data_i_iact_inferred__0/in0[6]
      : south_data_i_iact_inferred/out[6]
      : south_data_i_iact_inferred/in0[6]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /out[6]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /in0[6]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /out[6]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /in0[6]
     4: west_data_o_iact_inferred_i_10__0/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_iact_inferred_i_10__0"
Found timing loop:
     0: west_data_o_iact_inferred_i_9__0/O (LUT6)
     1: west_data_o_iact_inferred_i_9__0/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /out[7]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /in0[7]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /out[7]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /in0[7]
      : north_data_i_iact_inferred__0/out[7]
      : north_data_i_iact_inferred__0/in0[7]
      : north_data_i_iact_inferred/out[7]
      : north_data_i_iact_inferred/in0[7]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /out[7]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /in0[7]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /out[7]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /in0[7]
     2: west_data_o_iact_inferred_i_9/O (LUT6)
     3: west_data_o_iact_inferred_i_9/I3 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /out[7]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /in0[7]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /out[7]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /in0[7]
      : south_data_i_iact_inferred__0/out[7]
      : south_data_i_iact_inferred__0/in0[7]
      : south_data_i_iact_inferred/out[7]
      : south_data_i_iact_inferred/in0[7]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /out[7]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /in0[7]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /out[7]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /in0[7]
     4: west_data_o_iact_inferred_i_9__0/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_iact_inferred_i_9__0"
Found timing loop:
     0: west_data_o_iact_inferred_i_9__1/O (LUT6)
     1: west_data_o_iact_inferred_i_9__1/I3 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /out[7]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /in0[7]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /out[7]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /in0[7]
      : south_data_i_iact_inferred__2/out[7]
      : south_data_i_iact_inferred__2/in0[7]
      : south_data_i_iact_inferred__1/out[7]
      : south_data_i_iact_inferred__1/in0[7]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /out[7]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /in0[7]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /out[7]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /in0[7]
     2: west_data_o_iact_inferred_i_9__2/O (LUT6)
     3: west_data_o_iact_inferred_i_9__2/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /out[7]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /in0[7]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /out[7]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /in0[7]
      : north_data_i_iact_inferred__2/out[7]
      : north_data_i_iact_inferred__2/in0[7]
      : north_data_i_iact_inferred__1/out[7]
      : north_data_i_iact_inferred__1/in0[7]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /out[7]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /in0[7]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /out[7]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /in0[7]
     4: west_data_o_iact_inferred_i_9__1/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_iact_inferred_i_9__1"
Found timing loop:
     0: west_data_o_iact_inferred_i_9__0/O (LUT6)
     1: west_data_o_iact_inferred_i_9__0/I2 (LUT6)
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /out[7]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /in0[7]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /out[7]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /in0[7]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /out[7]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /in0[7]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /out[7]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /in0[7]
      : east_data_i_iact_inferred__2/out[7]
      : east_data_i_iact_inferred__2/in0[7]
      : east_data_i_iact_inferred__1/out[7]
      : east_data_i_iact_inferred__1/in0[7]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /out[7]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /in0[7]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /out[7]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /in0[7]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /out[7]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /in0[7]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /out[7]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /in0[7]
     2: west_data_o_iact_inferred_i_9__2/O (LUT6)
     3: west_data_o_iact_inferred_i_9__2/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /out[7]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /in0[7]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /out[7]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /in0[7]
      : north_data_i_iact_inferred__2/out[7]
      : north_data_i_iact_inferred__2/in0[7]
      : north_data_i_iact_inferred__1/out[7]
      : north_data_i_iact_inferred__1/in0[7]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /out[7]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /in0[7]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /out[7]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /in0[7]
     4: west_data_o_iact_inferred_i_9__1/O (LUT6)
     5: west_data_o_iact_inferred_i_9__1/I2 (LUT6)
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /out[7]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /in0[7]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /out[7]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /in0[7]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /out[7]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /in0[7]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /out[7]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /in0[7]
      : west_data_i_iact_inferred__0/out[7]
      : west_data_i_iact_inferred__0/in0[7]
      : west_data_i_iact_inferred/out[7]
      : west_data_i_iact_inferred/in0[7]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /out[7]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /in0[7]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /out[7]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /in0[7]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /out[7]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /in0[7]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /out[7]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /in0[7]
     6: west_data_o_iact_inferred_i_9/O (LUT6)
     7: west_data_o_iact_inferred_i_9/I3 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /out[7]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /in0[7]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /out[7]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /in0[7]
      : south_data_i_iact_inferred__0/out[7]
      : south_data_i_iact_inferred__0/in0[7]
      : south_data_i_iact_inferred/out[7]
      : south_data_i_iact_inferred/in0[7]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /out[7]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /in0[7]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /out[7]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /in0[7]
     8: west_data_o_iact_inferred_i_9__0/O (LUT6)
Inferred a: "set_disable_timing -from I2 -to O west_data_o_iact_inferred_i_9__0"
Found timing loop:
     0: west_data_o_iact_inferred_i_9/O (LUT6)
     1: west_data_o_iact_inferred_i_9/I3 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /out[7]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /in0[7]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /out[7]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /in0[7]
      : south_data_i_iact_inferred__0/out[7]
      : south_data_i_iact_inferred__0/in0[7]
      : south_data_i_iact_inferred/out[7]
      : south_data_i_iact_inferred/in0[7]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /out[7]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /in0[7]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /out[7]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /in0[7]
     2: west_data_o_iact_inferred_i_9__0/O (LUT6)
     3: west_data_o_iact_inferred_i_9__0/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_iact_inferred_i_9"
Found timing loop:
     0: west_data_o_iact_inferred_i_8__1/O (LUT6)
     1: west_data_o_iact_inferred_i_8__1/I3 (LUT6)
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /out[8]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /in0[8]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /out[8]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /in0[8]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /out[8]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /in0[8]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /out[8]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /in0[8]
      : west_data_i_iact_inferred__0/out[8]
      : west_data_i_iact_inferred__0/in0[8]
      : west_data_i_iact_inferred/out[8]
      : west_data_i_iact_inferred/in0[8]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /out[8]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /in0[8]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /out[8]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /in0[8]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /out[8]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /in0[8]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /out[8]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /in0[8]
     2: west_data_o_iact_inferred_i_8/O (LUT6)
     3: west_data_o_iact_inferred_i_8/I3 (LUT6)
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /out[8]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /in0[8]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /out[8]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /in0[8]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /out[8]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /in0[8]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /out[8]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /in0[8]
      : east_data_i_iact_inferred__0/out[8]
      : east_data_i_iact_inferred__0/in0[8]
      : east_data_i_iact_inferred/out[8]
      : east_data_i_iact_inferred/in0[8]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /out[8]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /in0[8]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /out[8]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /in0[8]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /out[8]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /in0[8]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /out[8]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /in0[8]
     4: west_data_o_iact_inferred_i_8__1/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_iact_inferred_i_8__1"
Found timing loop:
     0: west_data_o_iact_inferred_i_8/O (LUT6)
     1: west_data_o_iact_inferred_i_8/I3 (LUT6)
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /out[8]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /in0[8]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /out[8]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /in0[8]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /out[8]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /in0[8]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /out[8]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /in0[8]
      : east_data_i_iact_inferred__0/out[8]
      : east_data_i_iact_inferred__0/in0[8]
      : east_data_i_iact_inferred/out[8]
      : east_data_i_iact_inferred/in0[8]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /out[8]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /in0[8]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /out[8]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /in0[8]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /out[8]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /in0[8]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /out[8]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /in0[8]
     2: west_data_o_iact_inferred_i_8__1/O (LUT6)
     3: west_data_o_iact_inferred_i_8__1/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_iact_inferred_i_8"
Found timing loop:
     0: west_data_o_iact_inferred_i_8__1/O (LUT6)
     1: west_data_o_iact_inferred_i_8__1/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /out[8]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /in0[8]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /out[8]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /in0[8]
      : south_data_i_iact_inferred__2/out[8]
      : south_data_i_iact_inferred__2/in0[8]
      : south_data_i_iact_inferred__1/out[8]
      : south_data_i_iact_inferred__1/in0[8]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /out[8]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /in0[8]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /out[8]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /in0[8]
     2: west_data_o_iact_inferred_i_8__2/O (LUT6)
     3: west_data_o_iact_inferred_i_8__2/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /out[8]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /in0[8]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /out[8]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /in0[8]
      : north_data_i_iact_inferred__2/out[8]
      : north_data_i_iact_inferred__2/in0[8]
      : north_data_i_iact_inferred__1/out[8]
      : north_data_i_iact_inferred__1/in0[8]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /out[8]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /in0[8]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /out[8]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /in0[8]
     4: west_data_o_iact_inferred_i_8__1/O (LUT6)
Inferred a: "set_disable_timing -from I2 -to O west_data_o_iact_inferred_i_8__1"
Found timing loop:
     0: west_data_o_iact_inferred_i_8__0/O (LUT6)
     1: west_data_o_iact_inferred_i_8__0/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /out[8]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /in0[8]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /out[8]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /in0[8]
      : north_data_i_iact_inferred__0/out[8]
      : north_data_i_iact_inferred__0/in0[8]
      : north_data_i_iact_inferred/out[8]
      : north_data_i_iact_inferred/in0[8]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /out[8]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /in0[8]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /out[8]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /in0[8]
     2: west_data_o_iact_inferred_i_8/O (LUT6)
     3: west_data_o_iact_inferred_i_8/I2 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /out[8]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /in0[8]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /out[8]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /in0[8]
      : south_data_i_iact_inferred__0/out[8]
      : south_data_i_iact_inferred__0/in0[8]
      : south_data_i_iact_inferred/out[8]
      : south_data_i_iact_inferred/in0[8]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /out[8]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /in0[8]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /out[8]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /in0[8]
     4: west_data_o_iact_inferred_i_8__0/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_iact_inferred_i_8__0"
Found timing loop:
     0: west_data_o_iact_inferred_i_7__1/O (LUT6)
     1: west_data_o_iact_inferred_i_7__1/I3 (LUT6)
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /out[9]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /in0[9]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /out[9]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /in0[9]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /out[9]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /in0[9]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /out[9]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /in0[9]
      : west_data_i_iact_inferred__0/out[9]
      : west_data_i_iact_inferred__0/in0[9]
      : west_data_i_iact_inferred/out[9]
      : west_data_i_iact_inferred/in0[9]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /out[9]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /in0[9]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /out[9]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /in0[9]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /out[9]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /in0[9]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /out[9]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /in0[9]
     2: west_data_o_iact_inferred_i_7/O (LUT6)
     3: west_data_o_iact_inferred_i_7/I3 (LUT6)
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /out[9]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /in0[9]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /out[9]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /in0[9]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /out[9]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /in0[9]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /out[9]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /in0[9]
      : east_data_i_iact_inferred__0/out[9]
      : east_data_i_iact_inferred__0/in0[9]
      : east_data_i_iact_inferred/out[9]
      : east_data_i_iact_inferred/in0[9]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /out[9]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /in0[9]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /out[9]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /in0[9]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /out[9]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /in0[9]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /out[9]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /in0[9]
     4: west_data_o_iact_inferred_i_7__1/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_iact_inferred_i_7__1"
Found timing loop:
     0: west_data_o_iact_inferred_i_7/O (LUT6)
     1: west_data_o_iact_inferred_i_7/I3 (LUT6)
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /out[9]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /in0[9]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /out[9]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /in0[9]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /out[9]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /in0[9]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /out[9]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /in0[9]
      : east_data_i_iact_inferred__0/out[9]
      : east_data_i_iact_inferred__0/in0[9]
      : east_data_i_iact_inferred/out[9]
      : east_data_i_iact_inferred/in0[9]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /out[9]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /in0[9]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /out[9]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /in0[9]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /out[9]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /in0[9]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /out[9]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /in0[9]
     2: west_data_o_iact_inferred_i_7__1/O (LUT6)
     3: west_data_o_iact_inferred_i_7__1/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_iact_inferred_i_7"
Found timing loop:
     0: west_data_o_iact_inferred_i_7__1/O (LUT6)
     1: west_data_o_iact_inferred_i_7__1/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /out[9]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /in0[9]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /out[9]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /in0[9]
      : south_data_i_iact_inferred__2/out[9]
      : south_data_i_iact_inferred__2/in0[9]
      : south_data_i_iact_inferred__1/out[9]
      : south_data_i_iact_inferred__1/in0[9]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /out[9]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /in0[9]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /out[9]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /in0[9]
     2: west_data_o_iact_inferred_i_7__2/O (LUT6)
     3: west_data_o_iact_inferred_i_7__2/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /out[9]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /in0[9]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /out[9]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /in0[9]
      : north_data_i_iact_inferred__2/out[9]
      : north_data_i_iact_inferred__2/in0[9]
      : north_data_i_iact_inferred__1/out[9]
      : north_data_i_iact_inferred__1/in0[9]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /out[9]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /in0[9]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /out[9]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /in0[9]
     4: west_data_o_iact_inferred_i_7__1/O (LUT6)
Inferred a: "set_disable_timing -from I2 -to O west_data_o_iact_inferred_i_7__1"
Found timing loop:
     0: west_data_o_iact_inferred_i_7__0/O (LUT6)
     1: west_data_o_iact_inferred_i_7__0/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /out[9]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /in0[9]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /out[9]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /in0[9]
      : north_data_i_iact_inferred__0/out[9]
      : north_data_i_iact_inferred__0/in0[9]
      : north_data_i_iact_inferred/out[9]
      : north_data_i_iact_inferred/in0[9]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /out[9]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /in0[9]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /out[9]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /in0[9]
     2: west_data_o_iact_inferred_i_7/O (LUT6)
     3: west_data_o_iact_inferred_i_7/I2 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /out[9]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /in0[9]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /out[9]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /in0[9]
      : south_data_i_iact_inferred__0/out[9]
      : south_data_i_iact_inferred__0/in0[9]
      : south_data_i_iact_inferred/out[9]
      : south_data_i_iact_inferred/in0[9]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /out[9]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /in0[9]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /out[9]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /in0[9]
     4: west_data_o_iact_inferred_i_7__0/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_iact_inferred_i_7__0"
Found timing loop:
     0: west_data_o_iact_inferred_i_6__1/O (LUT6)
     1: west_data_o_iact_inferred_i_6__1/I3 (LUT6)
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /out[10]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /in0[10]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /out[10]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /in0[10]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /out[10]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /in0[10]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /out[10]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /in0[10]
      : west_data_i_iact_inferred__0/out[10]
      : west_data_i_iact_inferred__0/in0[10]
      : west_data_i_iact_inferred/out[10]
      : west_data_i_iact_inferred/in0[10]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /out[10]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /in0[10]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /out[10]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /in0[10]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /out[10]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /in0[10]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /out[10]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /in0[10]
     2: west_data_o_iact_inferred_i_6/O (LUT6)
     3: west_data_o_iact_inferred_i_6/I3 (LUT6)
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /out[10]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /in0[10]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /out[10]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /in0[10]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /out[10]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /in0[10]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /out[10]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /in0[10]
      : east_data_i_iact_inferred__0/out[10]
      : east_data_i_iact_inferred__0/in0[10]
      : east_data_i_iact_inferred/out[10]
      : east_data_i_iact_inferred/in0[10]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /out[10]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /in0[10]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /out[10]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /in0[10]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /out[10]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /in0[10]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /out[10]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /in0[10]
     4: west_data_o_iact_inferred_i_6__1/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_iact_inferred_i_6__1"
Found timing loop:
     0: west_data_o_iact_inferred_i_6/O (LUT6)
     1: west_data_o_iact_inferred_i_6/I3 (LUT6)
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /out[10]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /in0[10]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /out[10]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /in0[10]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /out[10]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /in0[10]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /out[10]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /in0[10]
      : east_data_i_iact_inferred__0/out[10]
      : east_data_i_iact_inferred__0/in0[10]
      : east_data_i_iact_inferred/out[10]
      : east_data_i_iact_inferred/in0[10]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /out[10]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /in0[10]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /out[10]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /in0[10]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /out[10]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /in0[10]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /out[10]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /in0[10]
     2: west_data_o_iact_inferred_i_6__1/O (LUT6)
     3: west_data_o_iact_inferred_i_6__1/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_iact_inferred_i_6"
Found timing loop:
     0: west_data_o_iact_inferred_i_6__1/O (LUT6)
     1: west_data_o_iact_inferred_i_6__1/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /out[10]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /in0[10]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /out[10]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /in0[10]
      : south_data_i_iact_inferred__2/out[10]
      : south_data_i_iact_inferred__2/in0[10]
      : south_data_i_iact_inferred__1/out[10]
      : south_data_i_iact_inferred__1/in0[10]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /out[10]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /in0[10]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /out[10]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /in0[10]
     2: west_data_o_iact_inferred_i_6__2/O (LUT6)
     3: west_data_o_iact_inferred_i_6__2/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /out[10]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /in0[10]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /out[10]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /in0[10]
      : north_data_i_iact_inferred__2/out[10]
      : north_data_i_iact_inferred__2/in0[10]
      : north_data_i_iact_inferred__1/out[10]
      : north_data_i_iact_inferred__1/in0[10]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /out[10]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /in0[10]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /out[10]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /in0[10]
     4: west_data_o_iact_inferred_i_6__1/O (LUT6)
Inferred a: "set_disable_timing -from I2 -to O west_data_o_iact_inferred_i_6__1"
Found timing loop:
     0: west_data_o_iact_inferred_i_6__0/O (LUT6)
     1: west_data_o_iact_inferred_i_6__0/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /out[10]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /in0[10]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /out[10]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /in0[10]
      : north_data_i_iact_inferred__0/out[10]
      : north_data_i_iact_inferred__0/in0[10]
      : north_data_i_iact_inferred/out[10]
      : north_data_i_iact_inferred/in0[10]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /out[10]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /in0[10]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /out[10]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /in0[10]
     2: west_data_o_iact_inferred_i_6/O (LUT6)
     3: west_data_o_iact_inferred_i_6/I2 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /out[10]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /in0[10]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /out[10]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /in0[10]
      : south_data_i_iact_inferred__0/out[10]
      : south_data_i_iact_inferred__0/in0[10]
      : south_data_i_iact_inferred/out[10]
      : south_data_i_iact_inferred/in0[10]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /out[10]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /in0[10]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /out[10]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /in0[10]
     4: west_data_o_iact_inferred_i_6__0/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_iact_inferred_i_6__0"
Found timing loop:
     0: west_data_o_iact_inferred_i_5__0/O (LUT6)
     1: west_data_o_iact_inferred_i_5__0/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /out[11]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /in0[11]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /out[11]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /in0[11]
      : north_data_i_iact_inferred__0/out[11]
      : north_data_i_iact_inferred__0/in0[11]
      : north_data_i_iact_inferred/out[11]
      : north_data_i_iact_inferred/in0[11]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /out[11]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /in0[11]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /out[11]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /in0[11]
     2: west_data_o_iact_inferred_i_5/O (LUT6)
     3: west_data_o_iact_inferred_i_5/I3 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /out[11]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /in0[11]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /out[11]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /in0[11]
      : south_data_i_iact_inferred__0/out[11]
      : south_data_i_iact_inferred__0/in0[11]
      : south_data_i_iact_inferred/out[11]
      : south_data_i_iact_inferred/in0[11]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /out[11]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /in0[11]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /out[11]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /in0[11]
     4: west_data_o_iact_inferred_i_5__0/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_iact_inferred_i_5__0"
Found timing loop:
     0: west_data_o_iact_inferred_i_5__1/O (LUT6)
     1: west_data_o_iact_inferred_i_5__1/I3 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /out[11]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /in0[11]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /out[11]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /in0[11]
      : south_data_i_iact_inferred__2/out[11]
      : south_data_i_iact_inferred__2/in0[11]
      : south_data_i_iact_inferred__1/out[11]
      : south_data_i_iact_inferred__1/in0[11]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /out[11]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /in0[11]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /out[11]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /in0[11]
     2: west_data_o_iact_inferred_i_5__2/O (LUT6)
     3: west_data_o_iact_inferred_i_5__2/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /out[11]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /in0[11]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /out[11]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /in0[11]
      : north_data_i_iact_inferred__2/out[11]
      : north_data_i_iact_inferred__2/in0[11]
      : north_data_i_iact_inferred__1/out[11]
      : north_data_i_iact_inferred__1/in0[11]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /out[11]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /in0[11]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /out[11]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /in0[11]
     4: west_data_o_iact_inferred_i_5__1/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_iact_inferred_i_5__1"
Found timing loop:
     0: west_data_o_iact_inferred_i_5__0/O (LUT6)
     1: west_data_o_iact_inferred_i_5__0/I2 (LUT6)
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /out[11]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /in0[11]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /out[11]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /in0[11]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /out[11]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /in0[11]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /out[11]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /in0[11]
      : east_data_i_iact_inferred__2/out[11]
      : east_data_i_iact_inferred__2/in0[11]
      : east_data_i_iact_inferred__1/out[11]
      : east_data_i_iact_inferred__1/in0[11]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /out[11]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /in0[11]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /out[11]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /in0[11]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /out[11]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /in0[11]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /out[11]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /in0[11]
     2: west_data_o_iact_inferred_i_5__2/O (LUT6)
     3: west_data_o_iact_inferred_i_5__2/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /out[11]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /in0[11]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /out[11]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /in0[11]
      : north_data_i_iact_inferred__2/out[11]
      : north_data_i_iact_inferred__2/in0[11]
      : north_data_i_iact_inferred__1/out[11]
      : north_data_i_iact_inferred__1/in0[11]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /out[11]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /in0[11]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /out[11]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /in0[11]
     4: west_data_o_iact_inferred_i_5__1/O (LUT6)
     5: west_data_o_iact_inferred_i_5__1/I2 (LUT6)
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /out[11]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /in0[11]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /out[11]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /in0[11]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /out[11]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /in0[11]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /out[11]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /in0[11]
      : west_data_i_iact_inferred__0/out[11]
      : west_data_i_iact_inferred__0/in0[11]
      : west_data_i_iact_inferred/out[11]
      : west_data_i_iact_inferred/in0[11]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /out[11]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /in0[11]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /out[11]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /in0[11]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /out[11]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /in0[11]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /out[11]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /in0[11]
     6: west_data_o_iact_inferred_i_5/O (LUT6)
     7: west_data_o_iact_inferred_i_5/I3 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /out[11]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /in0[11]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /out[11]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /in0[11]
      : south_data_i_iact_inferred__0/out[11]
      : south_data_i_iact_inferred__0/in0[11]
      : south_data_i_iact_inferred/out[11]
      : south_data_i_iact_inferred/in0[11]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /out[11]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /in0[11]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /out[11]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /in0[11]
     8: west_data_o_iact_inferred_i_5__0/O (LUT6)
Inferred a: "set_disable_timing -from I2 -to O west_data_o_iact_inferred_i_5__0"
Found timing loop:
     0: west_data_o_iact_inferred_i_5/O (LUT6)
     1: west_data_o_iact_inferred_i_5/I3 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /out[11]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /in0[11]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /out[11]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /in0[11]
      : south_data_i_iact_inferred__0/out[11]
      : south_data_i_iact_inferred__0/in0[11]
      : south_data_i_iact_inferred/out[11]
      : south_data_i_iact_inferred/in0[11]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /out[11]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /in0[11]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /out[11]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /in0[11]
     2: west_data_o_iact_inferred_i_5__0/O (LUT6)
     3: west_data_o_iact_inferred_i_5__0/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_iact_inferred_i_5"
Found timing loop:
     0: west_data_o_iact_inferred_i_4__0/O (LUT6)
     1: west_data_o_iact_inferred_i_4__0/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /out[12]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /in0[12]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /out[12]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /in0[12]
      : north_data_i_iact_inferred__0/out[12]
      : north_data_i_iact_inferred__0/in0[12]
      : north_data_i_iact_inferred/out[12]
      : north_data_i_iact_inferred/in0[12]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /out[12]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /in0[12]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /out[12]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /in0[12]
     2: west_data_o_iact_inferred_i_4/O (LUT6)
     3: west_data_o_iact_inferred_i_4/I3 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /out[12]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /in0[12]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /out[12]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /in0[12]
      : south_data_i_iact_inferred__0/out[12]
      : south_data_i_iact_inferred__0/in0[12]
      : south_data_i_iact_inferred/out[12]
      : south_data_i_iact_inferred/in0[12]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /out[12]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /in0[12]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /out[12]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /in0[12]
     4: west_data_o_iact_inferred_i_4__0/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_iact_inferred_i_4__0"
Found timing loop:
     0: west_data_o_iact_inferred_i_4__1/O (LUT6)
     1: west_data_o_iact_inferred_i_4__1/I3 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /out[12]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /in0[12]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /out[12]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /in0[12]
      : south_data_i_iact_inferred__2/out[12]
      : south_data_i_iact_inferred__2/in0[12]
      : south_data_i_iact_inferred__1/out[12]
      : south_data_i_iact_inferred__1/in0[12]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /out[12]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /in0[12]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /out[12]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /in0[12]
     2: west_data_o_iact_inferred_i_4__2/O (LUT6)
     3: west_data_o_iact_inferred_i_4__2/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /out[12]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /in0[12]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /out[12]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /in0[12]
      : north_data_i_iact_inferred__2/out[12]
      : north_data_i_iact_inferred__2/in0[12]
      : north_data_i_iact_inferred__1/out[12]
      : north_data_i_iact_inferred__1/in0[12]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /out[12]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /in0[12]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /out[12]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /in0[12]
     4: west_data_o_iact_inferred_i_4__1/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_iact_inferred_i_4__1"
Found timing loop:
     0: west_data_o_iact_inferred_i_4__0/O (LUT6)
     1: west_data_o_iact_inferred_i_4__0/I2 (LUT6)
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /out[12]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /in0[12]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /out[12]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /in0[12]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /out[12]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /in0[12]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /out[12]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /in0[12]
      : east_data_i_iact_inferred__2/out[12]
      : east_data_i_iact_inferred__2/in0[12]
      : east_data_i_iact_inferred__1/out[12]
      : east_data_i_iact_inferred__1/in0[12]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /out[12]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /in0[12]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /out[12]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /in0[12]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /out[12]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /in0[12]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /out[12]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /in0[12]
     2: west_data_o_iact_inferred_i_4__2/O (LUT6)
     3: west_data_o_iact_inferred_i_4__2/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /out[12]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /in0[12]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /out[12]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /in0[12]
      : north_data_i_iact_inferred__2/out[12]
      : north_data_i_iact_inferred__2/in0[12]
      : north_data_i_iact_inferred__1/out[12]
      : north_data_i_iact_inferred__1/in0[12]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /out[12]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /in0[12]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /out[12]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /in0[12]
     4: west_data_o_iact_inferred_i_4__1/O (LUT6)
     5: west_data_o_iact_inferred_i_4__1/I2 (LUT6)
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /out[12]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /in0[12]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /out[12]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /in0[12]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /out[12]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /in0[12]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /out[12]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /in0[12]
      : west_data_i_iact_inferred__0/out[12]
      : west_data_i_iact_inferred__0/in0[12]
      : west_data_i_iact_inferred/out[12]
      : west_data_i_iact_inferred/in0[12]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /out[12]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /in0[12]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /out[12]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /in0[12]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /out[12]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /in0[12]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /out[12]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /in0[12]
     6: west_data_o_iact_inferred_i_4/O (LUT6)
     7: west_data_o_iact_inferred_i_4/I3 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /out[12]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /in0[12]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /out[12]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /in0[12]
      : south_data_i_iact_inferred__0/out[12]
      : south_data_i_iact_inferred__0/in0[12]
      : south_data_i_iact_inferred/out[12]
      : south_data_i_iact_inferred/in0[12]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /out[12]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /in0[12]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /out[12]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /in0[12]
     8: west_data_o_iact_inferred_i_4__0/O (LUT6)
Inferred a: "set_disable_timing -from I2 -to O west_data_o_iact_inferred_i_4__0"
Found timing loop:
     0: west_data_o_iact_inferred_i_4/O (LUT6)
     1: west_data_o_iact_inferred_i_4/I3 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /out[12]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /in0[12]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /out[12]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /in0[12]
      : south_data_i_iact_inferred__0/out[12]
      : south_data_i_iact_inferred__0/in0[12]
      : south_data_i_iact_inferred/out[12]
      : south_data_i_iact_inferred/in0[12]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /out[12]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /in0[12]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /out[12]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /in0[12]
     2: west_data_o_iact_inferred_i_4__0/O (LUT6)
     3: west_data_o_iact_inferred_i_4__0/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_iact_inferred_i_4"
Found timing loop:
     0: west_data_o_iact_inferred_i_3__1/O (LUT6)
     1: west_data_o_iact_inferred_i_3__1/I3 (LUT6)
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /out[13]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /in0[13]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /out[13]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /in0[13]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /out[13]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /in0[13]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /out[13]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /in0[13]
      : west_data_i_iact_inferred__0/out[13]
      : west_data_i_iact_inferred__0/in0[13]
      : west_data_i_iact_inferred/out[13]
      : west_data_i_iact_inferred/in0[13]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /out[13]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /in0[13]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /out[13]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /in0[13]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /out[13]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /in0[13]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /out[13]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /in0[13]
     2: west_data_o_iact_inferred_i_3/O (LUT6)
     3: west_data_o_iact_inferred_i_3/I3 (LUT6)
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /out[13]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /in0[13]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /out[13]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /in0[13]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /out[13]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /in0[13]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /out[13]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /in0[13]
      : east_data_i_iact_inferred__0/out[13]
      : east_data_i_iact_inferred__0/in0[13]
      : east_data_i_iact_inferred/out[13]
      : east_data_i_iact_inferred/in0[13]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /out[13]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /in0[13]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /out[13]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /in0[13]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /out[13]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /in0[13]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /out[13]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /in0[13]
     4: west_data_o_iact_inferred_i_3__1/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_iact_inferred_i_3__1"
Found timing loop:
     0: west_data_o_iact_inferred_i_3/O (LUT6)
     1: west_data_o_iact_inferred_i_3/I3 (LUT6)
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /out[13]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred__0 /in0[13]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /out[13]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_i_iact_inferred /in0[13]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /out[13]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred__0 /in0[13]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /out[13]
      : \HMNoC_cluster_west_0/east_data_i_iact_inferred /in0[13]
      : east_data_i_iact_inferred__0/out[13]
      : east_data_i_iact_inferred__0/in0[13]
      : east_data_i_iact_inferred/out[13]
      : east_data_i_iact_inferred/in0[13]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /out[13]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred__0 /in0[13]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /out[13]
      : \HMNoC_cluster_east_0/west_data_o_iact_inferred /in0[13]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /out[13]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred__0 /in0[13]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /out[13]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_iact_inferred /in0[13]
     2: west_data_o_iact_inferred_i_3__1/O (LUT6)
     3: west_data_o_iact_inferred_i_3__1/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_iact_inferred_i_3"
Found timing loop:
     0: west_data_o_iact_inferred_i_3__1/O (LUT6)
     1: west_data_o_iact_inferred_i_3__1/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /out[13]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /in0[13]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /out[13]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /in0[13]
      : south_data_i_iact_inferred__2/out[13]
      : south_data_i_iact_inferred__2/in0[13]
      : south_data_i_iact_inferred__1/out[13]
      : south_data_i_iact_inferred__1/in0[13]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /out[13]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /in0[13]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /out[13]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /in0[13]
     2: west_data_o_iact_inferred_i_3__2/O (LUT6)
     3: west_data_o_iact_inferred_i_3__2/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /out[13]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /in0[13]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /out[13]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /in0[13]
      : north_data_i_iact_inferred__2/out[13]
      : north_data_i_iact_inferred__2/in0[13]
      : north_data_i_iact_inferred__1/out[13]
      : north_data_i_iact_inferred__1/in0[13]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /out[13]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /in0[13]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /out[13]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /in0[13]
     4: west_data_o_iact_inferred_i_3__1/O (LUT6)
Inferred a: "set_disable_timing -from I2 -to O west_data_o_iact_inferred_i_3__1"
Found timing loop:
     0: west_data_o_iact_inferred_i_3__0/O (LUT6)
     1: west_data_o_iact_inferred_i_3__0/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /out[13]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /in0[13]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /out[13]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /in0[13]
      : north_data_i_iact_inferred__0/out[13]
      : north_data_i_iact_inferred__0/in0[13]
      : north_data_i_iact_inferred/out[13]
      : north_data_i_iact_inferred/in0[13]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /out[13]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /in0[13]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /out[13]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /in0[13]
     2: west_data_o_iact_inferred_i_3/O (LUT6)
     3: west_data_o_iact_inferred_i_3/I2 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /out[13]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /in0[13]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /out[13]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /in0[13]
      : south_data_i_iact_inferred__0/out[13]
      : south_data_i_iact_inferred__0/in0[13]
      : south_data_i_iact_inferred/out[13]
      : south_data_i_iact_inferred/in0[13]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /out[13]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /in0[13]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /out[13]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /in0[13]
     4: west_data_o_iact_inferred_i_3__0/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_iact_inferred_i_3__0"
Found timing loop:
     0: west_data_o_iact_inferred_i_2__0/O (LUT6)
     1: west_data_o_iact_inferred_i_2__0/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /out[14]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /in0[14]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /out[14]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /in0[14]
      : north_data_i_iact_inferred__0/out[14]
      : north_data_i_iact_inferred__0/in0[14]
      : north_data_i_iact_inferred/out[14]
      : north_data_i_iact_inferred/in0[14]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /out[14]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /in0[14]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /out[14]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /in0[14]
     2: west_data_o_iact_inferred_i_2/O (LUT6)
     3: west_data_o_iact_inferred_i_2/I3 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /out[14]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /in0[14]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /out[14]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /in0[14]
      : south_data_i_iact_inferred__0/out[14]
      : south_data_i_iact_inferred__0/in0[14]
      : south_data_i_iact_inferred/out[14]
      : south_data_i_iact_inferred/in0[14]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /out[14]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /in0[14]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /out[14]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /in0[14]
     4: west_data_o_iact_inferred_i_2__0/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_iact_inferred_i_2__0"
Found timing loop:
     0: west_data_o_iact_inferred_i_2__1/O (LUT6)
     1: west_data_o_iact_inferred_i_2__1/I3 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /out[14]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /in0[14]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /out[14]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /in0[14]
      : south_data_i_iact_inferred__2/out[14]
      : south_data_i_iact_inferred__2/in0[14]
      : south_data_i_iact_inferred__1/out[14]
      : south_data_i_iact_inferred__1/in0[14]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /out[14]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /in0[14]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /out[14]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /in0[14]
     2: west_data_o_iact_inferred_i_2__2/O (LUT6)
     3: west_data_o_iact_inferred_i_2__2/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /out[14]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /in0[14]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /out[14]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /in0[14]
      : north_data_i_iact_inferred__2/out[14]
      : north_data_i_iact_inferred__2/in0[14]
      : north_data_i_iact_inferred__1/out[14]
      : north_data_i_iact_inferred__1/in0[14]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /out[14]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /in0[14]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /out[14]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /in0[14]
     4: west_data_o_iact_inferred_i_2__1/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_iact_inferred_i_2__1"
Found timing loop:
     0: west_data_o_iact_inferred_i_2__0/O (LUT6)
     1: west_data_o_iact_inferred_i_2__0/I2 (LUT6)
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /out[14]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /in0[14]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /out[14]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /in0[14]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /out[14]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /in0[14]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /out[14]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /in0[14]
      : east_data_i_iact_inferred__2/out[14]
      : east_data_i_iact_inferred__2/in0[14]
      : east_data_i_iact_inferred__1/out[14]
      : east_data_i_iact_inferred__1/in0[14]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /out[14]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /in0[14]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /out[14]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /in0[14]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /out[14]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /in0[14]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /out[14]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /in0[14]
     2: west_data_o_iact_inferred_i_2__2/O (LUT6)
     3: west_data_o_iact_inferred_i_2__2/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /out[14]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /in0[14]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /out[14]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /in0[14]
      : north_data_i_iact_inferred__2/out[14]
      : north_data_i_iact_inferred__2/in0[14]
      : north_data_i_iact_inferred__1/out[14]
      : north_data_i_iact_inferred__1/in0[14]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /out[14]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /in0[14]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /out[14]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /in0[14]
     4: west_data_o_iact_inferred_i_2__1/O (LUT6)
     5: west_data_o_iact_inferred_i_2__1/I2 (LUT6)
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /out[14]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /in0[14]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /out[14]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /in0[14]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /out[14]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /in0[14]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /out[14]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /in0[14]
      : west_data_i_iact_inferred__0/out[14]
      : west_data_i_iact_inferred__0/in0[14]
      : west_data_i_iact_inferred/out[14]
      : west_data_i_iact_inferred/in0[14]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /out[14]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /in0[14]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /out[14]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /in0[14]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /out[14]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /in0[14]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /out[14]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /in0[14]
     6: west_data_o_iact_inferred_i_2/O (LUT6)
     7: west_data_o_iact_inferred_i_2/I3 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /out[14]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /in0[14]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /out[14]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /in0[14]
      : south_data_i_iact_inferred__0/out[14]
      : south_data_i_iact_inferred__0/in0[14]
      : south_data_i_iact_inferred/out[14]
      : south_data_i_iact_inferred/in0[14]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /out[14]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /in0[14]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /out[14]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /in0[14]
     8: west_data_o_iact_inferred_i_2__0/O (LUT6)
Inferred a: "set_disable_timing -from I2 -to O west_data_o_iact_inferred_i_2__0"
Found timing loop:
     0: west_data_o_iact_inferred_i_2/O (LUT6)
     1: west_data_o_iact_inferred_i_2/I3 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /out[14]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /in0[14]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /out[14]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /in0[14]
      : south_data_i_iact_inferred__0/out[14]
      : south_data_i_iact_inferred__0/in0[14]
      : south_data_i_iact_inferred/out[14]
      : south_data_i_iact_inferred/in0[14]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /out[14]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /in0[14]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /out[14]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /in0[14]
     2: west_data_o_iact_inferred_i_2__0/O (LUT6)
     3: west_data_o_iact_inferred_i_2__0/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_iact_inferred_i_2"
Found timing loop:
     0: west_data_o_iact_inferred_i_1__0/O (LUT6)
     1: west_data_o_iact_inferred_i_1__0/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /out[15]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred__0 /in0[15]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /out[15]
      : \HMNoC_cluster_west_1/north_data_i_iact_inferred /in0[15]
      : north_data_i_iact_inferred__0/out[15]
      : north_data_i_iact_inferred__0/in0[15]
      : north_data_i_iact_inferred/out[15]
      : north_data_i_iact_inferred/in0[15]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /out[15]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred__0 /in0[15]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /out[15]
      : \HMNoC_cluster_west_0/south_data_o_iact_inferred /in0[15]
     2: west_data_o_iact_inferred_i_1/O (LUT6)
     3: west_data_o_iact_inferred_i_1/I3 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /out[15]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /in0[15]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /out[15]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /in0[15]
      : south_data_i_iact_inferred__0/out[15]
      : south_data_i_iact_inferred__0/in0[15]
      : south_data_i_iact_inferred/out[15]
      : south_data_i_iact_inferred/in0[15]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /out[15]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /in0[15]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /out[15]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /in0[15]
     4: west_data_o_iact_inferred_i_1__0/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_iact_inferred_i_1__0"
Found timing loop:
     0: west_data_o_iact_inferred_i_1__1/O (LUT6)
     1: west_data_o_iact_inferred_i_1__1/I3 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /out[15]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred__0 /in0[15]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /out[15]
      : \HMNoC_cluster_east_0/south_data_i_iact_inferred /in0[15]
      : south_data_i_iact_inferred__2/out[15]
      : south_data_i_iact_inferred__2/in0[15]
      : south_data_i_iact_inferred__1/out[15]
      : south_data_i_iact_inferred__1/in0[15]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /out[15]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred__0 /in0[15]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /out[15]
      : \HMNoC_cluster_east_1/north_data_o_iact_inferred /in0[15]
     2: west_data_o_iact_inferred_i_1__2/O (LUT6)
     3: west_data_o_iact_inferred_i_1__2/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /out[15]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /in0[15]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /out[15]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /in0[15]
      : north_data_i_iact_inferred__2/out[15]
      : north_data_i_iact_inferred__2/in0[15]
      : north_data_i_iact_inferred__1/out[15]
      : north_data_i_iact_inferred__1/in0[15]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /out[15]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /in0[15]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /out[15]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /in0[15]
     4: west_data_o_iact_inferred_i_1__1/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_iact_inferred_i_1__1"
Found timing loop:
     0: west_data_o_iact_inferred_i_1__0/O (LUT6)
     1: west_data_o_iact_inferred_i_1__0/I2 (LUT6)
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /out[15]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred__0 /in0[15]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /out[15]
      : \HMNoC_cluster_west_1/router_cluster_0/east_data_i_iact_inferred /in0[15]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /out[15]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred__0 /in0[15]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /out[15]
      : \HMNoC_cluster_west_1/east_data_i_iact_inferred /in0[15]
      : east_data_i_iact_inferred__2/out[15]
      : east_data_i_iact_inferred__2/in0[15]
      : east_data_i_iact_inferred__1/out[15]
      : east_data_i_iact_inferred__1/in0[15]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /out[15]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred__0 /in0[15]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /out[15]
      : \HMNoC_cluster_east_1/west_data_o_iact_inferred /in0[15]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /out[15]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred__0 /in0[15]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /out[15]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_iact_inferred /in0[15]
     2: west_data_o_iact_inferred_i_1__2/O (LUT6)
     3: west_data_o_iact_inferred_i_1__2/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /out[15]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred__0 /in0[15]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /out[15]
      : \HMNoC_cluster_east_1/north_data_i_iact_inferred /in0[15]
      : north_data_i_iact_inferred__2/out[15]
      : north_data_i_iact_inferred__2/in0[15]
      : north_data_i_iact_inferred__1/out[15]
      : north_data_i_iact_inferred__1/in0[15]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /out[15]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred__0 /in0[15]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /out[15]
      : \HMNoC_cluster_east_0/south_data_o_iact_inferred /in0[15]
     4: west_data_o_iact_inferred_i_1__1/O (LUT6)
     5: west_data_o_iact_inferred_i_1__1/I2 (LUT6)
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /out[15]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred__0 /in0[15]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /out[15]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_i_iact_inferred /in0[15]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /out[15]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred__0 /in0[15]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /out[15]
      : \HMNoC_cluster_east_0/west_data_i_iact_inferred /in0[15]
      : west_data_i_iact_inferred__0/out[15]
      : west_data_i_iact_inferred__0/in0[15]
      : west_data_i_iact_inferred/out[15]
      : west_data_i_iact_inferred/in0[15]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /out[15]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred__0 /in0[15]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /out[15]
      : \HMNoC_cluster_west_0/east_data_o_iact_inferred /in0[15]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /out[15]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred__0 /in0[15]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /out[15]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_iact_inferred /in0[15]
     6: west_data_o_iact_inferred_i_1/O (LUT6)
     7: west_data_o_iact_inferred_i_1/I3 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /out[15]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /in0[15]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /out[15]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /in0[15]
      : south_data_i_iact_inferred__0/out[15]
      : south_data_i_iact_inferred__0/in0[15]
      : south_data_i_iact_inferred/out[15]
      : south_data_i_iact_inferred/in0[15]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /out[15]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /in0[15]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /out[15]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /in0[15]
     8: west_data_o_iact_inferred_i_1__0/O (LUT6)
Inferred a: "set_disable_timing -from I2 -to O west_data_o_iact_inferred_i_1__0"
Found timing loop:
     0: west_data_o_iact_inferred_i_1/O (LUT6)
     1: west_data_o_iact_inferred_i_1/I3 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /out[15]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred__0 /in0[15]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /out[15]
      : \HMNoC_cluster_west_0/south_data_i_iact_inferred /in0[15]
      : south_data_i_iact_inferred__0/out[15]
      : south_data_i_iact_inferred__0/in0[15]
      : south_data_i_iact_inferred/out[15]
      : south_data_i_iact_inferred/in0[15]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /out[15]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred__0 /in0[15]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /out[15]
      : \HMNoC_cluster_west_1/north_data_o_iact_inferred /in0[15]
     2: west_data_o_iact_inferred_i_1__0/O (LUT6)
     3: west_data_o_iact_inferred_i_1__0/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_iact_inferred_i_1"
Found timing loop:
     0: west_data_o_psum_inferred_i_16/O (LUT6)
     1: west_data_o_psum_inferred_i_16/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /out[0]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /in0[0]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /out[0]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /in0[0]
      : north_data_i_psum_inferred__0/out[0]
      : north_data_i_psum_inferred__0/in0[0]
      : north_data_i_psum_inferred/out[0]
      : north_data_i_psum_inferred/in0[0]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /out[0]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /in0[0]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /out[0]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /in0[0]
     2: west_data_o_psum_inferred_i_16__2/O (LUT6)
     3: west_data_o_psum_inferred_i_16__2/I1 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[0]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[0]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[0]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[0]
      : south_data_i_psum_inferred__0/out[0]
      : south_data_i_psum_inferred__0/in0[0]
      : south_data_i_psum_inferred/out[0]
      : south_data_i_psum_inferred/in0[0]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[0]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[0]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[0]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[0]
     4: west_data_o_psum_inferred_i_16/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_psum_inferred_i_16"
Found timing loop:
     0: west_data_o_psum_inferred_i_16__2/O (LUT6)
     1: west_data_o_psum_inferred_i_16__2/I1 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[0]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[0]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[0]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[0]
      : south_data_i_psum_inferred__0/out[0]
      : south_data_i_psum_inferred__0/in0[0]
      : south_data_i_psum_inferred/out[0]
      : south_data_i_psum_inferred/in0[0]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[0]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[0]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[0]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[0]
     2: west_data_o_psum_inferred_i_16/O (LUT6)
     3: west_data_o_psum_inferred_i_16/O (LUT6)
Inferred a: "set_disable_timing -from I1 -to O west_data_o_psum_inferred_i_16__2"
Found timing loop:
     0: west_data_o_psum_inferred_i_16__0/O (LUT6)
     1: west_data_o_psum_inferred_i_16__0/I3 (LUT6)
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[0]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[0]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[0]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[0]
      : west_data_i_psum_inferred__0/out[0]
      : west_data_i_psum_inferred__0/in0[0]
      : west_data_i_psum_inferred/out[0]
      : west_data_i_psum_inferred/in0[0]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[0]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[0]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[0]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[0]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[0]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[0]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[0]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[0]
     2: west_data_o_psum_inferred_i_16__2/O (LUT6)
     3: west_data_o_psum_inferred_i_16__2/I0 (LUT6)
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /out[0]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /in0[0]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /out[0]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /in0[0]
      : east_data_i_psum_inferred__0/out[0]
      : east_data_i_psum_inferred__0/in0[0]
      : east_data_i_psum_inferred/out[0]
      : east_data_i_psum_inferred/in0[0]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /out[0]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /in0[0]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /out[0]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /in0[0]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /out[0]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /in0[0]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /out[0]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /in0[0]
     4: west_data_o_psum_inferred_i_16__0/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_psum_inferred_i_16__0"
Found timing loop:
     0: west_data_o_psum_inferred_i_16/O (LUT6)
     1: west_data_o_psum_inferred_i_16/I3 (LUT6)
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred__0 /out[0]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred__0 /in0[0]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred /out[0]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred /in0[0]
      : east_data_i_psum_inferred__2/out[0]
      : east_data_i_psum_inferred__2/in0[0]
      : east_data_i_psum_inferred__1/out[0]
      : east_data_i_psum_inferred__1/in0[0]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred__0 /out[0]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred__0 /in0[0]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred /out[0]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred /in0[0]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred__0 /out[0]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred__0 /in0[0]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred /out[0]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred /in0[0]
     2: west_data_o_psum_inferred_i_16__1/O (LUT6)
     3: west_data_o_psum_inferred_i_16__1/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /out[0]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /in0[0]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /out[0]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /in0[0]
      : south_data_o_psum_inferred__2/out[0]
      : south_data_o_psum_inferred__2/in0[0]
      : south_data_o_psum_inferred__1/out[0]
      : south_data_o_psum_inferred__1/in0[0]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[0]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[0]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[0]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[0]
     4: west_data_o_psum_inferred_i_16__0/O (LUT6)
     5: west_data_o_psum_inferred_i_16__0/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[0]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[0]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[0]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[0]
      : south_data_i_psum_inferred__2/out[0]
      : south_data_i_psum_inferred__2/in0[0]
      : south_data_i_psum_inferred__1/out[0]
      : south_data_i_psum_inferred__1/in0[0]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[0]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[0]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[0]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[0]
     6: west_data_o_psum_inferred_i_16__1/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_psum_inferred_i_16"
Found timing loop:
     0: west_data_o_psum_inferred_i_16__1/O (LUT6)
     1: west_data_o_psum_inferred_i_16__1/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /out[0]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /in0[0]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /out[0]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /in0[0]
      : south_data_o_psum_inferred__2/out[0]
      : south_data_o_psum_inferred__2/in0[0]
      : south_data_o_psum_inferred__1/out[0]
      : south_data_o_psum_inferred__1/in0[0]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[0]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[0]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[0]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[0]
     2: west_data_o_psum_inferred_i_16__0/O (LUT6)
     3: west_data_o_psum_inferred_i_16__0/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[0]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[0]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[0]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[0]
      : south_data_i_psum_inferred__2/out[0]
      : south_data_i_psum_inferred__2/in0[0]
      : south_data_i_psum_inferred__1/out[0]
      : south_data_i_psum_inferred__1/in0[0]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[0]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[0]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[0]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[0]
     4: west_data_o_psum_inferred_i_16__1/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_psum_inferred_i_16__1"
Found timing loop:
     0: west_data_o_psum_inferred_i_14/O (LUT6)
     1: west_data_o_psum_inferred_i_14/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /out[2]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /in0[2]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /out[2]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /in0[2]
      : north_data_i_psum_inferred__0/out[2]
      : north_data_i_psum_inferred__0/in0[2]
      : north_data_i_psum_inferred/out[2]
      : north_data_i_psum_inferred/in0[2]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /out[2]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /in0[2]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /out[2]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /in0[2]
     2: west_data_o_psum_inferred_i_14__2/O (LUT6)
     3: west_data_o_psum_inferred_i_14__2/I1 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[2]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[2]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[2]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[2]
      : south_data_i_psum_inferred__0/out[2]
      : south_data_i_psum_inferred__0/in0[2]
      : south_data_i_psum_inferred/out[2]
      : south_data_i_psum_inferred/in0[2]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[2]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[2]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[2]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[2]
     4: west_data_o_psum_inferred_i_14/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_psum_inferred_i_14"
Found timing loop:
     0: west_data_o_psum_inferred_i_14__2/O (LUT6)
     1: west_data_o_psum_inferred_i_14__2/I1 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[2]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[2]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[2]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[2]
      : south_data_i_psum_inferred__0/out[2]
      : south_data_i_psum_inferred__0/in0[2]
      : south_data_i_psum_inferred/out[2]
      : south_data_i_psum_inferred/in0[2]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[2]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[2]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[2]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[2]
     2: west_data_o_psum_inferred_i_14/O (LUT6)
     3: west_data_o_psum_inferred_i_14/O (LUT6)
Inferred a: "set_disable_timing -from I1 -to O west_data_o_psum_inferred_i_14__2"
Found timing loop:
     0: west_data_o_psum_inferred_i_14__0/O (LUT6)
     1: west_data_o_psum_inferred_i_14__0/I3 (LUT6)
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[2]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[2]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[2]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[2]
      : west_data_i_psum_inferred__0/out[2]
      : west_data_i_psum_inferred__0/in0[2]
      : west_data_i_psum_inferred/out[2]
      : west_data_i_psum_inferred/in0[2]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[2]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[2]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[2]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[2]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[2]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[2]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[2]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[2]
     2: west_data_o_psum_inferred_i_14__2/O (LUT6)
     3: west_data_o_psum_inferred_i_14__2/I0 (LUT6)
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /out[2]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /in0[2]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /out[2]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /in0[2]
      : east_data_i_psum_inferred__0/out[2]
      : east_data_i_psum_inferred__0/in0[2]
      : east_data_i_psum_inferred/out[2]
      : east_data_i_psum_inferred/in0[2]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /out[2]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /in0[2]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /out[2]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /in0[2]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /out[2]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /in0[2]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /out[2]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /in0[2]
     4: west_data_o_psum_inferred_i_14__0/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_psum_inferred_i_14__0"
Found timing loop:
     0: west_data_o_psum_inferred_i_14/O (LUT6)
     1: west_data_o_psum_inferred_i_14/I3 (LUT6)
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred__0 /out[2]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred__0 /in0[2]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred /out[2]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred /in0[2]
      : east_data_i_psum_inferred__2/out[2]
      : east_data_i_psum_inferred__2/in0[2]
      : east_data_i_psum_inferred__1/out[2]
      : east_data_i_psum_inferred__1/in0[2]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred__0 /out[2]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred__0 /in0[2]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred /out[2]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred /in0[2]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred__0 /out[2]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred__0 /in0[2]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred /out[2]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred /in0[2]
     2: west_data_o_psum_inferred_i_14__1/O (LUT6)
     3: west_data_o_psum_inferred_i_14__1/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /out[2]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /in0[2]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /out[2]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /in0[2]
      : south_data_o_psum_inferred__2/out[2]
      : south_data_o_psum_inferred__2/in0[2]
      : south_data_o_psum_inferred__1/out[2]
      : south_data_o_psum_inferred__1/in0[2]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[2]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[2]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[2]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[2]
     4: west_data_o_psum_inferred_i_14__0/O (LUT6)
     5: west_data_o_psum_inferred_i_14__0/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[2]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[2]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[2]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[2]
      : south_data_i_psum_inferred__2/out[2]
      : south_data_i_psum_inferred__2/in0[2]
      : south_data_i_psum_inferred__1/out[2]
      : south_data_i_psum_inferred__1/in0[2]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[2]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[2]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[2]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[2]
     6: west_data_o_psum_inferred_i_14__1/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_psum_inferred_i_14"
Found timing loop:
     0: west_data_o_psum_inferred_i_14__1/O (LUT6)
     1: west_data_o_psum_inferred_i_14__1/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /out[2]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /in0[2]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /out[2]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /in0[2]
      : south_data_o_psum_inferred__2/out[2]
      : south_data_o_psum_inferred__2/in0[2]
      : south_data_o_psum_inferred__1/out[2]
      : south_data_o_psum_inferred__1/in0[2]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[2]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[2]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[2]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[2]
     2: west_data_o_psum_inferred_i_14__0/O (LUT6)
     3: west_data_o_psum_inferred_i_14__0/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[2]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[2]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[2]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[2]
      : south_data_i_psum_inferred__2/out[2]
      : south_data_i_psum_inferred__2/in0[2]
      : south_data_i_psum_inferred__1/out[2]
      : south_data_i_psum_inferred__1/in0[2]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[2]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[2]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[2]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[2]
     4: west_data_o_psum_inferred_i_14__1/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_psum_inferred_i_14__1"
Found timing loop:
     0: west_data_o_psum_inferred_i_12/O (LUT6)
     1: west_data_o_psum_inferred_i_12/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /out[4]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /in0[4]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /out[4]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /in0[4]
      : north_data_i_psum_inferred__0/out[4]
      : north_data_i_psum_inferred__0/in0[4]
      : north_data_i_psum_inferred/out[4]
      : north_data_i_psum_inferred/in0[4]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /out[4]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /in0[4]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /out[4]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /in0[4]
     2: west_data_o_psum_inferred_i_12__2/O (LUT6)
     3: west_data_o_psum_inferred_i_12__2/I1 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[4]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[4]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[4]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[4]
      : south_data_i_psum_inferred__0/out[4]
      : south_data_i_psum_inferred__0/in0[4]
      : south_data_i_psum_inferred/out[4]
      : south_data_i_psum_inferred/in0[4]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[4]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[4]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[4]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[4]
     4: west_data_o_psum_inferred_i_12/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_psum_inferred_i_12"
Found timing loop:
     0: west_data_o_psum_inferred_i_12__2/O (LUT6)
     1: west_data_o_psum_inferred_i_12__2/I1 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[4]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[4]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[4]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[4]
      : south_data_i_psum_inferred__0/out[4]
      : south_data_i_psum_inferred__0/in0[4]
      : south_data_i_psum_inferred/out[4]
      : south_data_i_psum_inferred/in0[4]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[4]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[4]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[4]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[4]
     2: west_data_o_psum_inferred_i_12/O (LUT6)
     3: west_data_o_psum_inferred_i_12/O (LUT6)
Inferred a: "set_disable_timing -from I1 -to O west_data_o_psum_inferred_i_12__2"
Found timing loop:
     0: west_data_o_psum_inferred_i_12__0/O (LUT6)
     1: west_data_o_psum_inferred_i_12__0/I3 (LUT6)
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[4]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[4]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[4]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[4]
      : west_data_i_psum_inferred__0/out[4]
      : west_data_i_psum_inferred__0/in0[4]
      : west_data_i_psum_inferred/out[4]
      : west_data_i_psum_inferred/in0[4]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[4]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[4]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[4]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[4]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[4]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[4]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[4]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[4]
     2: west_data_o_psum_inferred_i_12__2/O (LUT6)
     3: west_data_o_psum_inferred_i_12__2/I0 (LUT6)
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /out[4]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /in0[4]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /out[4]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /in0[4]
      : east_data_i_psum_inferred__0/out[4]
      : east_data_i_psum_inferred__0/in0[4]
      : east_data_i_psum_inferred/out[4]
      : east_data_i_psum_inferred/in0[4]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /out[4]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /in0[4]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /out[4]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /in0[4]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /out[4]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /in0[4]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /out[4]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /in0[4]
     4: west_data_o_psum_inferred_i_12__0/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_psum_inferred_i_12__0"
Found timing loop:
     0: west_data_o_psum_inferred_i_12/O (LUT6)
     1: west_data_o_psum_inferred_i_12/I3 (LUT6)
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred__0 /out[4]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred__0 /in0[4]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred /out[4]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred /in0[4]
      : east_data_i_psum_inferred__2/out[4]
      : east_data_i_psum_inferred__2/in0[4]
      : east_data_i_psum_inferred__1/out[4]
      : east_data_i_psum_inferred__1/in0[4]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred__0 /out[4]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred__0 /in0[4]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred /out[4]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred /in0[4]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred__0 /out[4]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred__0 /in0[4]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred /out[4]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred /in0[4]
     2: west_data_o_psum_inferred_i_12__1/O (LUT6)
     3: west_data_o_psum_inferred_i_12__1/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /out[4]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /in0[4]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /out[4]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /in0[4]
      : south_data_o_psum_inferred__2/out[4]
      : south_data_o_psum_inferred__2/in0[4]
      : south_data_o_psum_inferred__1/out[4]
      : south_data_o_psum_inferred__1/in0[4]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[4]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[4]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[4]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[4]
     4: west_data_o_psum_inferred_i_12__0/O (LUT6)
     5: west_data_o_psum_inferred_i_12__0/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[4]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[4]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[4]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[4]
      : south_data_i_psum_inferred__2/out[4]
      : south_data_i_psum_inferred__2/in0[4]
      : south_data_i_psum_inferred__1/out[4]
      : south_data_i_psum_inferred__1/in0[4]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[4]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[4]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[4]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[4]
     6: west_data_o_psum_inferred_i_12__1/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_psum_inferred_i_12"
Found timing loop:
     0: west_data_o_psum_inferred_i_12__1/O (LUT6)
     1: west_data_o_psum_inferred_i_12__1/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /out[4]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /in0[4]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /out[4]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /in0[4]
      : south_data_o_psum_inferred__2/out[4]
      : south_data_o_psum_inferred__2/in0[4]
      : south_data_o_psum_inferred__1/out[4]
      : south_data_o_psum_inferred__1/in0[4]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[4]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[4]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[4]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[4]
     2: west_data_o_psum_inferred_i_12__0/O (LUT6)
     3: west_data_o_psum_inferred_i_12__0/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[4]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[4]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[4]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[4]
      : south_data_i_psum_inferred__2/out[4]
      : south_data_i_psum_inferred__2/in0[4]
      : south_data_i_psum_inferred__1/out[4]
      : south_data_i_psum_inferred__1/in0[4]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[4]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[4]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[4]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[4]
     4: west_data_o_psum_inferred_i_12__1/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_psum_inferred_i_12__1"
Found timing loop:
     0: west_data_o_psum_inferred_i_11/O (LUT6)
     1: west_data_o_psum_inferred_i_11/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /out[5]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /in0[5]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /out[5]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /in0[5]
      : north_data_i_psum_inferred__0/out[5]
      : north_data_i_psum_inferred__0/in0[5]
      : north_data_i_psum_inferred/out[5]
      : north_data_i_psum_inferred/in0[5]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /out[5]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /in0[5]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /out[5]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /in0[5]
     2: west_data_o_psum_inferred_i_11__2/O (LUT6)
     3: west_data_o_psum_inferred_i_11__2/I1 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[5]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[5]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[5]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[5]
      : south_data_i_psum_inferred__0/out[5]
      : south_data_i_psum_inferred__0/in0[5]
      : south_data_i_psum_inferred/out[5]
      : south_data_i_psum_inferred/in0[5]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[5]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[5]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[5]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[5]
     4: west_data_o_psum_inferred_i_11/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_psum_inferred_i_11"
Found timing loop:
     0: west_data_o_psum_inferred_i_11__2/O (LUT6)
     1: west_data_o_psum_inferred_i_11__2/I1 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[5]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[5]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[5]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[5]
      : south_data_i_psum_inferred__0/out[5]
      : south_data_i_psum_inferred__0/in0[5]
      : south_data_i_psum_inferred/out[5]
      : south_data_i_psum_inferred/in0[5]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[5]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[5]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[5]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[5]
     2: west_data_o_psum_inferred_i_11/O (LUT6)
     3: west_data_o_psum_inferred_i_11/O (LUT6)
Inferred a: "set_disable_timing -from I1 -to O west_data_o_psum_inferred_i_11__2"
Found timing loop:
     0: west_data_o_psum_inferred_i_11__0/O (LUT6)
     1: west_data_o_psum_inferred_i_11__0/I3 (LUT6)
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[5]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[5]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[5]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[5]
      : west_data_i_psum_inferred__0/out[5]
      : west_data_i_psum_inferred__0/in0[5]
      : west_data_i_psum_inferred/out[5]
      : west_data_i_psum_inferred/in0[5]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[5]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[5]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[5]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[5]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[5]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[5]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[5]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[5]
     2: west_data_o_psum_inferred_i_11__2/O (LUT6)
     3: west_data_o_psum_inferred_i_11__2/I0 (LUT6)
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /out[5]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /in0[5]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /out[5]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /in0[5]
      : east_data_i_psum_inferred__0/out[5]
      : east_data_i_psum_inferred__0/in0[5]
      : east_data_i_psum_inferred/out[5]
      : east_data_i_psum_inferred/in0[5]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /out[5]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /in0[5]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /out[5]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /in0[5]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /out[5]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /in0[5]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /out[5]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /in0[5]
     4: west_data_o_psum_inferred_i_11__0/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_psum_inferred_i_11__0"
Found timing loop:
     0: west_data_o_psum_inferred_i_11/O (LUT6)
     1: west_data_o_psum_inferred_i_11/I3 (LUT6)
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred__0 /out[5]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred__0 /in0[5]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred /out[5]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred /in0[5]
      : east_data_i_psum_inferred__2/out[5]
      : east_data_i_psum_inferred__2/in0[5]
      : east_data_i_psum_inferred__1/out[5]
      : east_data_i_psum_inferred__1/in0[5]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred__0 /out[5]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred__0 /in0[5]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred /out[5]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred /in0[5]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred__0 /out[5]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred__0 /in0[5]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred /out[5]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred /in0[5]
     2: west_data_o_psum_inferred_i_11__1/O (LUT6)
     3: west_data_o_psum_inferred_i_11__1/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /out[5]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /in0[5]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /out[5]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /in0[5]
      : south_data_o_psum_inferred__2/out[5]
      : south_data_o_psum_inferred__2/in0[5]
      : south_data_o_psum_inferred__1/out[5]
      : south_data_o_psum_inferred__1/in0[5]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[5]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[5]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[5]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[5]
     4: west_data_o_psum_inferred_i_11__0/O (LUT6)
     5: west_data_o_psum_inferred_i_11__0/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[5]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[5]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[5]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[5]
      : south_data_i_psum_inferred__2/out[5]
      : south_data_i_psum_inferred__2/in0[5]
      : south_data_i_psum_inferred__1/out[5]
      : south_data_i_psum_inferred__1/in0[5]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[5]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[5]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[5]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[5]
     6: west_data_o_psum_inferred_i_11__1/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_psum_inferred_i_11"
Found timing loop:
     0: west_data_o_psum_inferred_i_11__1/O (LUT6)
     1: west_data_o_psum_inferred_i_11__1/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /out[5]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /in0[5]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /out[5]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /in0[5]
      : south_data_o_psum_inferred__2/out[5]
      : south_data_o_psum_inferred__2/in0[5]
      : south_data_o_psum_inferred__1/out[5]
      : south_data_o_psum_inferred__1/in0[5]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[5]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[5]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[5]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[5]
     2: west_data_o_psum_inferred_i_11__0/O (LUT6)
     3: west_data_o_psum_inferred_i_11__0/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[5]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[5]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[5]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[5]
      : south_data_i_psum_inferred__2/out[5]
      : south_data_i_psum_inferred__2/in0[5]
      : south_data_i_psum_inferred__1/out[5]
      : south_data_i_psum_inferred__1/in0[5]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[5]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[5]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[5]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[5]
     4: west_data_o_psum_inferred_i_11__1/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_psum_inferred_i_11__1"
Found timing loop:
     0: west_data_o_psum_inferred_i_10/O (LUT6)
     1: west_data_o_psum_inferred_i_10/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /out[6]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /in0[6]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /out[6]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /in0[6]
      : north_data_i_psum_inferred__0/out[6]
      : north_data_i_psum_inferred__0/in0[6]
      : north_data_i_psum_inferred/out[6]
      : north_data_i_psum_inferred/in0[6]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /out[6]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /in0[6]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /out[6]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /in0[6]
     2: west_data_o_psum_inferred_i_10__2/O (LUT6)
     3: west_data_o_psum_inferred_i_10__2/I1 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[6]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[6]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[6]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[6]
      : south_data_i_psum_inferred__0/out[6]
      : south_data_i_psum_inferred__0/in0[6]
      : south_data_i_psum_inferred/out[6]
      : south_data_i_psum_inferred/in0[6]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[6]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[6]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[6]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[6]
     4: west_data_o_psum_inferred_i_10/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_psum_inferred_i_10"
Found timing loop:
     0: west_data_o_psum_inferred_i_10__2/O (LUT6)
     1: west_data_o_psum_inferred_i_10__2/I1 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[6]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[6]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[6]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[6]
      : south_data_i_psum_inferred__0/out[6]
      : south_data_i_psum_inferred__0/in0[6]
      : south_data_i_psum_inferred/out[6]
      : south_data_i_psum_inferred/in0[6]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[6]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[6]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[6]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[6]
     2: west_data_o_psum_inferred_i_10/O (LUT6)
     3: west_data_o_psum_inferred_i_10/O (LUT6)
Inferred a: "set_disable_timing -from I1 -to O west_data_o_psum_inferred_i_10__2"
Found timing loop:
     0: west_data_o_psum_inferred_i_10__0/O (LUT6)
     1: west_data_o_psum_inferred_i_10__0/I3 (LUT6)
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[6]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[6]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[6]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[6]
      : west_data_i_psum_inferred__0/out[6]
      : west_data_i_psum_inferred__0/in0[6]
      : west_data_i_psum_inferred/out[6]
      : west_data_i_psum_inferred/in0[6]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[6]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[6]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[6]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[6]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[6]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[6]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[6]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[6]
     2: west_data_o_psum_inferred_i_10__2/O (LUT6)
     3: west_data_o_psum_inferred_i_10__2/I0 (LUT6)
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /out[6]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /in0[6]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /out[6]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /in0[6]
      : east_data_i_psum_inferred__0/out[6]
      : east_data_i_psum_inferred__0/in0[6]
      : east_data_i_psum_inferred/out[6]
      : east_data_i_psum_inferred/in0[6]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /out[6]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /in0[6]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /out[6]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /in0[6]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /out[6]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /in0[6]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /out[6]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /in0[6]
     4: west_data_o_psum_inferred_i_10__0/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_psum_inferred_i_10__0"
Found timing loop:
     0: west_data_o_psum_inferred_i_10/O (LUT6)
     1: west_data_o_psum_inferred_i_10/I3 (LUT6)
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred__0 /out[6]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred__0 /in0[6]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred /out[6]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred /in0[6]
      : east_data_i_psum_inferred__2/out[6]
      : east_data_i_psum_inferred__2/in0[6]
      : east_data_i_psum_inferred__1/out[6]
      : east_data_i_psum_inferred__1/in0[6]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred__0 /out[6]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred__0 /in0[6]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred /out[6]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred /in0[6]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred__0 /out[6]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred__0 /in0[6]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred /out[6]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred /in0[6]
     2: west_data_o_psum_inferred_i_10__1/O (LUT6)
     3: west_data_o_psum_inferred_i_10__1/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /out[6]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /in0[6]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /out[6]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /in0[6]
      : south_data_o_psum_inferred__2/out[6]
      : south_data_o_psum_inferred__2/in0[6]
      : south_data_o_psum_inferred__1/out[6]
      : south_data_o_psum_inferred__1/in0[6]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[6]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[6]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[6]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[6]
     4: west_data_o_psum_inferred_i_10__0/O (LUT6)
     5: west_data_o_psum_inferred_i_10__0/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[6]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[6]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[6]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[6]
      : south_data_i_psum_inferred__2/out[6]
      : south_data_i_psum_inferred__2/in0[6]
      : south_data_i_psum_inferred__1/out[6]
      : south_data_i_psum_inferred__1/in0[6]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[6]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[6]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[6]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[6]
     6: west_data_o_psum_inferred_i_10__1/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_psum_inferred_i_10"
Found timing loop:
     0: west_data_o_psum_inferred_i_10__1/O (LUT6)
     1: west_data_o_psum_inferred_i_10__1/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /out[6]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /in0[6]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /out[6]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /in0[6]
      : south_data_o_psum_inferred__2/out[6]
      : south_data_o_psum_inferred__2/in0[6]
      : south_data_o_psum_inferred__1/out[6]
      : south_data_o_psum_inferred__1/in0[6]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[6]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[6]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[6]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[6]
     2: west_data_o_psum_inferred_i_10__0/O (LUT6)
     3: west_data_o_psum_inferred_i_10__0/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[6]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[6]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[6]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[6]
      : south_data_i_psum_inferred__2/out[6]
      : south_data_i_psum_inferred__2/in0[6]
      : south_data_i_psum_inferred__1/out[6]
      : south_data_i_psum_inferred__1/in0[6]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[6]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[6]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[6]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[6]
     4: west_data_o_psum_inferred_i_10__1/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_psum_inferred_i_10__1"
Found timing loop:
     0: west_data_o_psum_inferred_i_8/O (LUT6)
     1: west_data_o_psum_inferred_i_8/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /out[8]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /in0[8]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /out[8]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /in0[8]
      : north_data_i_psum_inferred__0/out[8]
      : north_data_i_psum_inferred__0/in0[8]
      : north_data_i_psum_inferred/out[8]
      : north_data_i_psum_inferred/in0[8]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /out[8]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /in0[8]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /out[8]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /in0[8]
     2: west_data_o_psum_inferred_i_8__2/O (LUT6)
     3: west_data_o_psum_inferred_i_8__2/I1 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[8]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[8]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[8]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[8]
      : south_data_i_psum_inferred__0/out[8]
      : south_data_i_psum_inferred__0/in0[8]
      : south_data_i_psum_inferred/out[8]
      : south_data_i_psum_inferred/in0[8]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[8]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[8]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[8]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[8]
     4: west_data_o_psum_inferred_i_8/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_psum_inferred_i_8"
Found timing loop:
     0: west_data_o_psum_inferred_i_8__2/O (LUT6)
     1: west_data_o_psum_inferred_i_8__2/I1 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[8]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[8]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[8]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[8]
      : south_data_i_psum_inferred__0/out[8]
      : south_data_i_psum_inferred__0/in0[8]
      : south_data_i_psum_inferred/out[8]
      : south_data_i_psum_inferred/in0[8]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[8]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[8]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[8]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[8]
     2: west_data_o_psum_inferred_i_8/O (LUT6)
     3: west_data_o_psum_inferred_i_8/O (LUT6)
Inferred a: "set_disable_timing -from I1 -to O west_data_o_psum_inferred_i_8__2"
Found timing loop:
     0: west_data_o_psum_inferred_i_8__0/O (LUT6)
     1: west_data_o_psum_inferred_i_8__0/I3 (LUT6)
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[8]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[8]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[8]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[8]
      : west_data_i_psum_inferred__0/out[8]
      : west_data_i_psum_inferred__0/in0[8]
      : west_data_i_psum_inferred/out[8]
      : west_data_i_psum_inferred/in0[8]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[8]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[8]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[8]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[8]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[8]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[8]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[8]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[8]
     2: west_data_o_psum_inferred_i_8__2/O (LUT6)
     3: west_data_o_psum_inferred_i_8__2/I0 (LUT6)
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /out[8]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /in0[8]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /out[8]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /in0[8]
      : east_data_i_psum_inferred__0/out[8]
      : east_data_i_psum_inferred__0/in0[8]
      : east_data_i_psum_inferred/out[8]
      : east_data_i_psum_inferred/in0[8]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /out[8]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /in0[8]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /out[8]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /in0[8]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /out[8]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /in0[8]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /out[8]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /in0[8]
     4: west_data_o_psum_inferred_i_8__0/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_psum_inferred_i_8__0"
Found timing loop:
     0: west_data_o_psum_inferred_i_8/O (LUT6)
     1: west_data_o_psum_inferred_i_8/I3 (LUT6)
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred__0 /out[8]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred__0 /in0[8]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred /out[8]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred /in0[8]
      : east_data_i_psum_inferred__2/out[8]
      : east_data_i_psum_inferred__2/in0[8]
      : east_data_i_psum_inferred__1/out[8]
      : east_data_i_psum_inferred__1/in0[8]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred__0 /out[8]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred__0 /in0[8]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred /out[8]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred /in0[8]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred__0 /out[8]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred__0 /in0[8]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred /out[8]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred /in0[8]
     2: west_data_o_psum_inferred_i_8__1/O (LUT6)
     3: west_data_o_psum_inferred_i_8__1/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /out[8]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /in0[8]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /out[8]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /in0[8]
      : south_data_o_psum_inferred__2/out[8]
      : south_data_o_psum_inferred__2/in0[8]
      : south_data_o_psum_inferred__1/out[8]
      : south_data_o_psum_inferred__1/in0[8]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[8]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[8]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[8]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[8]
     4: west_data_o_psum_inferred_i_8__0/O (LUT6)
     5: west_data_o_psum_inferred_i_8__0/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[8]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[8]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[8]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[8]
      : south_data_i_psum_inferred__2/out[8]
      : south_data_i_psum_inferred__2/in0[8]
      : south_data_i_psum_inferred__1/out[8]
      : south_data_i_psum_inferred__1/in0[8]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[8]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[8]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[8]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[8]
     6: west_data_o_psum_inferred_i_8__1/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_psum_inferred_i_8"
Found timing loop:
     0: west_data_o_psum_inferred_i_8__1/O (LUT6)
     1: west_data_o_psum_inferred_i_8__1/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /out[8]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /in0[8]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /out[8]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /in0[8]
      : south_data_o_psum_inferred__2/out[8]
      : south_data_o_psum_inferred__2/in0[8]
      : south_data_o_psum_inferred__1/out[8]
      : south_data_o_psum_inferred__1/in0[8]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[8]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[8]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[8]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[8]
     2: west_data_o_psum_inferred_i_8__0/O (LUT6)
     3: west_data_o_psum_inferred_i_8__0/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[8]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[8]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[8]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[8]
      : south_data_i_psum_inferred__2/out[8]
      : south_data_i_psum_inferred__2/in0[8]
      : south_data_i_psum_inferred__1/out[8]
      : south_data_i_psum_inferred__1/in0[8]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[8]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[8]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[8]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[8]
     4: west_data_o_psum_inferred_i_8__1/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_psum_inferred_i_8__1"
Found timing loop:
     0: west_data_o_psum_inferred_i_7/O (LUT6)
     1: west_data_o_psum_inferred_i_7/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /out[9]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /in0[9]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /out[9]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /in0[9]
      : north_data_i_psum_inferred__0/out[9]
      : north_data_i_psum_inferred__0/in0[9]
      : north_data_i_psum_inferred/out[9]
      : north_data_i_psum_inferred/in0[9]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /out[9]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /in0[9]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /out[9]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /in0[9]
     2: west_data_o_psum_inferred_i_7__2/O (LUT6)
     3: west_data_o_psum_inferred_i_7__2/I1 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[9]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[9]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[9]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[9]
      : south_data_i_psum_inferred__0/out[9]
      : south_data_i_psum_inferred__0/in0[9]
      : south_data_i_psum_inferred/out[9]
      : south_data_i_psum_inferred/in0[9]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[9]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[9]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[9]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[9]
     4: west_data_o_psum_inferred_i_7/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_psum_inferred_i_7"
Found timing loop:
     0: west_data_o_psum_inferred_i_7__2/O (LUT6)
     1: west_data_o_psum_inferred_i_7__2/I1 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[9]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[9]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[9]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[9]
      : south_data_i_psum_inferred__0/out[9]
      : south_data_i_psum_inferred__0/in0[9]
      : south_data_i_psum_inferred/out[9]
      : south_data_i_psum_inferred/in0[9]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[9]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[9]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[9]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[9]
     2: west_data_o_psum_inferred_i_7/O (LUT6)
     3: west_data_o_psum_inferred_i_7/O (LUT6)
Inferred a: "set_disable_timing -from I1 -to O west_data_o_psum_inferred_i_7__2"
Found timing loop:
     0: west_data_o_psum_inferred_i_7__0/O (LUT6)
     1: west_data_o_psum_inferred_i_7__0/I3 (LUT6)
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[9]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[9]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[9]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[9]
      : west_data_i_psum_inferred__0/out[9]
      : west_data_i_psum_inferred__0/in0[9]
      : west_data_i_psum_inferred/out[9]
      : west_data_i_psum_inferred/in0[9]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[9]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[9]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[9]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[9]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[9]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[9]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[9]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[9]
     2: west_data_o_psum_inferred_i_7__2/O (LUT6)
     3: west_data_o_psum_inferred_i_7__2/I0 (LUT6)
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /out[9]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /in0[9]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /out[9]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /in0[9]
      : east_data_i_psum_inferred__0/out[9]
      : east_data_i_psum_inferred__0/in0[9]
      : east_data_i_psum_inferred/out[9]
      : east_data_i_psum_inferred/in0[9]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /out[9]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /in0[9]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /out[9]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /in0[9]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /out[9]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /in0[9]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /out[9]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /in0[9]
     4: west_data_o_psum_inferred_i_7__0/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_psum_inferred_i_7__0"
Found timing loop:
     0: west_data_o_psum_inferred_i_7/O (LUT6)
     1: west_data_o_psum_inferred_i_7/I3 (LUT6)
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred__0 /out[9]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred__0 /in0[9]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred /out[9]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred /in0[9]
      : east_data_i_psum_inferred__2/out[9]
      : east_data_i_psum_inferred__2/in0[9]
      : east_data_i_psum_inferred__1/out[9]
      : east_data_i_psum_inferred__1/in0[9]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred__0 /out[9]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred__0 /in0[9]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred /out[9]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred /in0[9]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred__0 /out[9]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred__0 /in0[9]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred /out[9]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred /in0[9]
     2: west_data_o_psum_inferred_i_7__1/O (LUT6)
     3: west_data_o_psum_inferred_i_7__1/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /out[9]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /in0[9]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /out[9]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /in0[9]
      : south_data_o_psum_inferred__2/out[9]
      : south_data_o_psum_inferred__2/in0[9]
      : south_data_o_psum_inferred__1/out[9]
      : south_data_o_psum_inferred__1/in0[9]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[9]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[9]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[9]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[9]
     4: west_data_o_psum_inferred_i_7__0/O (LUT6)
     5: west_data_o_psum_inferred_i_7__0/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[9]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[9]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[9]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[9]
      : south_data_i_psum_inferred__2/out[9]
      : south_data_i_psum_inferred__2/in0[9]
      : south_data_i_psum_inferred__1/out[9]
      : south_data_i_psum_inferred__1/in0[9]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[9]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[9]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[9]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[9]
     6: west_data_o_psum_inferred_i_7__1/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_psum_inferred_i_7"
Found timing loop:
     0: west_data_o_psum_inferred_i_7__1/O (LUT6)
     1: west_data_o_psum_inferred_i_7__1/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /out[9]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /in0[9]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /out[9]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /in0[9]
      : south_data_o_psum_inferred__2/out[9]
      : south_data_o_psum_inferred__2/in0[9]
      : south_data_o_psum_inferred__1/out[9]
      : south_data_o_psum_inferred__1/in0[9]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[9]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[9]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[9]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[9]
     2: west_data_o_psum_inferred_i_7__0/O (LUT6)
     3: west_data_o_psum_inferred_i_7__0/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[9]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[9]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[9]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[9]
      : south_data_i_psum_inferred__2/out[9]
      : south_data_i_psum_inferred__2/in0[9]
      : south_data_i_psum_inferred__1/out[9]
      : south_data_i_psum_inferred__1/in0[9]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[9]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[9]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[9]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[9]
     4: west_data_o_psum_inferred_i_7__1/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_psum_inferred_i_7__1"
Found timing loop:
     0: west_data_o_psum_inferred_i_6/O (LUT6)
     1: west_data_o_psum_inferred_i_6/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /out[10]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /in0[10]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /out[10]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /in0[10]
      : north_data_i_psum_inferred__0/out[10]
      : north_data_i_psum_inferred__0/in0[10]
      : north_data_i_psum_inferred/out[10]
      : north_data_i_psum_inferred/in0[10]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /out[10]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /in0[10]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /out[10]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /in0[10]
     2: west_data_o_psum_inferred_i_6__2/O (LUT6)
     3: west_data_o_psum_inferred_i_6__2/I1 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[10]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[10]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[10]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[10]
      : south_data_i_psum_inferred__0/out[10]
      : south_data_i_psum_inferred__0/in0[10]
      : south_data_i_psum_inferred/out[10]
      : south_data_i_psum_inferred/in0[10]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[10]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[10]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[10]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[10]
     4: west_data_o_psum_inferred_i_6/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_psum_inferred_i_6"
Found timing loop:
     0: west_data_o_psum_inferred_i_6__2/O (LUT6)
     1: west_data_o_psum_inferred_i_6__2/I1 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[10]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[10]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[10]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[10]
      : south_data_i_psum_inferred__0/out[10]
      : south_data_i_psum_inferred__0/in0[10]
      : south_data_i_psum_inferred/out[10]
      : south_data_i_psum_inferred/in0[10]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[10]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[10]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[10]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[10]
     2: west_data_o_psum_inferred_i_6/O (LUT6)
     3: west_data_o_psum_inferred_i_6/O (LUT6)
Inferred a: "set_disable_timing -from I1 -to O west_data_o_psum_inferred_i_6__2"
Found timing loop:
     0: west_data_o_psum_inferred_i_6__0/O (LUT6)
     1: west_data_o_psum_inferred_i_6__0/I3 (LUT6)
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[10]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[10]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[10]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[10]
      : west_data_i_psum_inferred__0/out[10]
      : west_data_i_psum_inferred__0/in0[10]
      : west_data_i_psum_inferred/out[10]
      : west_data_i_psum_inferred/in0[10]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[10]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[10]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[10]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[10]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[10]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[10]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[10]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[10]
     2: west_data_o_psum_inferred_i_6__2/O (LUT6)
     3: west_data_o_psum_inferred_i_6__2/I0 (LUT6)
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /out[10]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /in0[10]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /out[10]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /in0[10]
      : east_data_i_psum_inferred__0/out[10]
      : east_data_i_psum_inferred__0/in0[10]
      : east_data_i_psum_inferred/out[10]
      : east_data_i_psum_inferred/in0[10]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /out[10]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /in0[10]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /out[10]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /in0[10]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /out[10]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /in0[10]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /out[10]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /in0[10]
     4: west_data_o_psum_inferred_i_6__0/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_psum_inferred_i_6__0"
Found timing loop:
     0: west_data_o_psum_inferred_i_6/O (LUT6)
     1: west_data_o_psum_inferred_i_6/I3 (LUT6)
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred__0 /out[10]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred__0 /in0[10]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred /out[10]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred /in0[10]
      : east_data_i_psum_inferred__2/out[10]
      : east_data_i_psum_inferred__2/in0[10]
      : east_data_i_psum_inferred__1/out[10]
      : east_data_i_psum_inferred__1/in0[10]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred__0 /out[10]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred__0 /in0[10]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred /out[10]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred /in0[10]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred__0 /out[10]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred__0 /in0[10]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred /out[10]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred /in0[10]
     2: west_data_o_psum_inferred_i_6__1/O (LUT6)
     3: west_data_o_psum_inferred_i_6__1/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /out[10]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /in0[10]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /out[10]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /in0[10]
      : south_data_o_psum_inferred__2/out[10]
      : south_data_o_psum_inferred__2/in0[10]
      : south_data_o_psum_inferred__1/out[10]
      : south_data_o_psum_inferred__1/in0[10]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[10]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[10]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[10]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[10]
     4: west_data_o_psum_inferred_i_6__0/O (LUT6)
     5: west_data_o_psum_inferred_i_6__0/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[10]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[10]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[10]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[10]
      : south_data_i_psum_inferred__2/out[10]
      : south_data_i_psum_inferred__2/in0[10]
      : south_data_i_psum_inferred__1/out[10]
      : south_data_i_psum_inferred__1/in0[10]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[10]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[10]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[10]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[10]
     6: west_data_o_psum_inferred_i_6__1/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_psum_inferred_i_6"
Found timing loop:
     0: west_data_o_psum_inferred_i_6__1/O (LUT6)
     1: west_data_o_psum_inferred_i_6__1/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /out[10]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /in0[10]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /out[10]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /in0[10]
      : south_data_o_psum_inferred__2/out[10]
      : south_data_o_psum_inferred__2/in0[10]
      : south_data_o_psum_inferred__1/out[10]
      : south_data_o_psum_inferred__1/in0[10]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[10]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[10]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[10]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[10]
     2: west_data_o_psum_inferred_i_6__0/O (LUT6)
     3: west_data_o_psum_inferred_i_6__0/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[10]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[10]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[10]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[10]
      : south_data_i_psum_inferred__2/out[10]
      : south_data_i_psum_inferred__2/in0[10]
      : south_data_i_psum_inferred__1/out[10]
      : south_data_i_psum_inferred__1/in0[10]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[10]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[10]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[10]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[10]
     4: west_data_o_psum_inferred_i_6__1/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_psum_inferred_i_6__1"
Found timing loop:
     0: west_data_o_psum_inferred_i_3/O (LUT6)
     1: west_data_o_psum_inferred_i_3/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /out[13]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /in0[13]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /out[13]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /in0[13]
      : north_data_i_psum_inferred__0/out[13]
      : north_data_i_psum_inferred__0/in0[13]
      : north_data_i_psum_inferred/out[13]
      : north_data_i_psum_inferred/in0[13]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /out[13]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /in0[13]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /out[13]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /in0[13]
     2: west_data_o_psum_inferred_i_3__2/O (LUT6)
     3: west_data_o_psum_inferred_i_3__2/I1 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[13]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[13]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[13]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[13]
      : south_data_i_psum_inferred__0/out[13]
      : south_data_i_psum_inferred__0/in0[13]
      : south_data_i_psum_inferred/out[13]
      : south_data_i_psum_inferred/in0[13]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[13]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[13]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[13]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[13]
     4: west_data_o_psum_inferred_i_3/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_psum_inferred_i_3"
Found timing loop:
     0: west_data_o_psum_inferred_i_3__2/O (LUT6)
     1: west_data_o_psum_inferred_i_3__2/I1 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[13]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[13]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[13]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[13]
      : south_data_i_psum_inferred__0/out[13]
      : south_data_i_psum_inferred__0/in0[13]
      : south_data_i_psum_inferred/out[13]
      : south_data_i_psum_inferred/in0[13]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[13]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[13]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[13]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[13]
     2: west_data_o_psum_inferred_i_3/O (LUT6)
     3: west_data_o_psum_inferred_i_3/O (LUT6)
Inferred a: "set_disable_timing -from I1 -to O west_data_o_psum_inferred_i_3__2"
Found timing loop:
     0: west_data_o_psum_inferred_i_3__0/O (LUT6)
     1: west_data_o_psum_inferred_i_3__0/I3 (LUT6)
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[13]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[13]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[13]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[13]
      : west_data_i_psum_inferred__0/out[13]
      : west_data_i_psum_inferred__0/in0[13]
      : west_data_i_psum_inferred/out[13]
      : west_data_i_psum_inferred/in0[13]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[13]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[13]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[13]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[13]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[13]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[13]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[13]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[13]
     2: west_data_o_psum_inferred_i_3__2/O (LUT6)
     3: west_data_o_psum_inferred_i_3__2/I0 (LUT6)
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /out[13]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred__0 /in0[13]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /out[13]
      : \HMNoC_cluster_west_0/east_data_i_psum_inferred /in0[13]
      : east_data_i_psum_inferred__0/out[13]
      : east_data_i_psum_inferred__0/in0[13]
      : east_data_i_psum_inferred/out[13]
      : east_data_i_psum_inferred/in0[13]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /out[13]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred__0 /in0[13]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /out[13]
      : \HMNoC_cluster_east_0/west_data_o_psum_inferred /in0[13]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /out[13]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred__0 /in0[13]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /out[13]
      : \HMNoC_cluster_east_0/router_cluster_0/west_data_o_psum_inferred /in0[13]
     4: west_data_o_psum_inferred_i_3__0/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_psum_inferred_i_3__0"
Found timing loop:
     0: west_data_o_psum_inferred_i_3/O (LUT6)
     1: west_data_o_psum_inferred_i_3/I3 (LUT6)
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred__0 /out[13]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred__0 /in0[13]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred /out[13]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred /in0[13]
      : east_data_i_psum_inferred__2/out[13]
      : east_data_i_psum_inferred__2/in0[13]
      : east_data_i_psum_inferred__1/out[13]
      : east_data_i_psum_inferred__1/in0[13]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred__0 /out[13]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred__0 /in0[13]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred /out[13]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred /in0[13]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred__0 /out[13]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred__0 /in0[13]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred /out[13]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred /in0[13]
     2: west_data_o_psum_inferred_i_3__1/O (LUT6)
     3: west_data_o_psum_inferred_i_3__1/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /out[13]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /in0[13]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /out[13]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /in0[13]
      : south_data_o_psum_inferred__2/out[13]
      : south_data_o_psum_inferred__2/in0[13]
      : south_data_o_psum_inferred__1/out[13]
      : south_data_o_psum_inferred__1/in0[13]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[13]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[13]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[13]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[13]
     4: west_data_o_psum_inferred_i_3__0/O (LUT6)
     5: west_data_o_psum_inferred_i_3__0/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[13]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[13]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[13]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[13]
      : south_data_i_psum_inferred__2/out[13]
      : south_data_i_psum_inferred__2/in0[13]
      : south_data_i_psum_inferred__1/out[13]
      : south_data_i_psum_inferred__1/in0[13]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[13]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[13]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[13]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[13]
     6: west_data_o_psum_inferred_i_3__1/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_psum_inferred_i_3"
Found timing loop:
     0: west_data_o_psum_inferred_i_3__1/O (LUT6)
     1: west_data_o_psum_inferred_i_3__1/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /out[13]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /in0[13]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /out[13]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /in0[13]
      : south_data_o_psum_inferred__2/out[13]
      : south_data_o_psum_inferred__2/in0[13]
      : south_data_o_psum_inferred__1/out[13]
      : south_data_o_psum_inferred__1/in0[13]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[13]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[13]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[13]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[13]
     2: west_data_o_psum_inferred_i_3__0/O (LUT6)
     3: west_data_o_psum_inferred_i_3__0/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[13]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[13]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[13]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[13]
      : south_data_i_psum_inferred__2/out[13]
      : south_data_i_psum_inferred__2/in0[13]
      : south_data_i_psum_inferred__1/out[13]
      : south_data_i_psum_inferred__1/in0[13]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[13]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[13]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[13]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[13]
     4: west_data_o_psum_inferred_i_3__1/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_psum_inferred_i_3__1"
Found timing loop:
     0: west_data_o_psum_inferred_i_2__0/O (LUT6)
     1: west_data_o_psum_inferred_i_2__0/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /out[14]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /in0[14]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /out[14]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /in0[14]
      : north_data_i_psum_inferred__0/out[14]
      : north_data_i_psum_inferred__0/in0[14]
      : north_data_i_psum_inferred/out[14]
      : north_data_i_psum_inferred/in0[14]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /out[14]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /in0[14]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /out[14]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /in0[14]
     2: west_data_o_psum_inferred_i_2/O (LUT6)
     3: west_data_o_psum_inferred_i_2/I3 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[14]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[14]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[14]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[14]
      : south_data_i_psum_inferred__0/out[14]
      : south_data_i_psum_inferred__0/in0[14]
      : south_data_i_psum_inferred/out[14]
      : south_data_i_psum_inferred/in0[14]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[14]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[14]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[14]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[14]
     4: west_data_o_psum_inferred_i_2__0/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_psum_inferred_i_2__0"
Found timing loop:
     0: west_data_o_psum_inferred_i_2__1/O (LUT6)
     1: west_data_o_psum_inferred_i_2__1/I3 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[14]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[14]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[14]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[14]
      : south_data_i_psum_inferred__2/out[14]
      : south_data_i_psum_inferred__2/in0[14]
      : south_data_i_psum_inferred__1/out[14]
      : south_data_i_psum_inferred__1/in0[14]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[14]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[14]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[14]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[14]
     2: west_data_o_psum_inferred_i_2__2/O (LUT6)
     3: west_data_o_psum_inferred_i_2__2/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /out[14]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /in0[14]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /out[14]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /in0[14]
      : south_data_o_psum_inferred__2/out[14]
      : south_data_o_psum_inferred__2/in0[14]
      : south_data_o_psum_inferred__1/out[14]
      : south_data_o_psum_inferred__1/in0[14]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[14]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[14]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[14]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[14]
     4: west_data_o_psum_inferred_i_2__1/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_psum_inferred_i_2__1"
Found timing loop:
     0: west_data_o_psum_inferred_i_2__0/O (LUT6)
     1: west_data_o_psum_inferred_i_2__0/I2 (LUT6)
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred__0 /out[14]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred__0 /in0[14]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred /out[14]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred /in0[14]
      : east_data_i_psum_inferred__2/out[14]
      : east_data_i_psum_inferred__2/in0[14]
      : east_data_i_psum_inferred__1/out[14]
      : east_data_i_psum_inferred__1/in0[14]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred__0 /out[14]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred__0 /in0[14]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred /out[14]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred /in0[14]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred__0 /out[14]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred__0 /in0[14]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred /out[14]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred /in0[14]
     2: west_data_o_psum_inferred_i_2__2/O (LUT6)
     3: west_data_o_psum_inferred_i_2__2/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /out[14]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /in0[14]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /out[14]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /in0[14]
      : south_data_o_psum_inferred__2/out[14]
      : south_data_o_psum_inferred__2/in0[14]
      : south_data_o_psum_inferred__1/out[14]
      : south_data_o_psum_inferred__1/in0[14]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[14]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[14]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[14]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[14]
     4: west_data_o_psum_inferred_i_2__1/O (LUT6)
     5: west_data_o_psum_inferred_i_2__1/I2 (LUT6)
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[14]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[14]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[14]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[14]
      : west_data_i_psum_inferred__0/out[14]
      : west_data_i_psum_inferred__0/in0[14]
      : west_data_i_psum_inferred/out[14]
      : west_data_i_psum_inferred/in0[14]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[14]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[14]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[14]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[14]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[14]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[14]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[14]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[14]
     6: west_data_o_psum_inferred_i_2/O (LUT6)
     7: west_data_o_psum_inferred_i_2/I3 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[14]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[14]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[14]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[14]
      : south_data_i_psum_inferred__0/out[14]
      : south_data_i_psum_inferred__0/in0[14]
      : south_data_i_psum_inferred/out[14]
      : south_data_i_psum_inferred/in0[14]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[14]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[14]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[14]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[14]
     8: west_data_o_psum_inferred_i_2__0/O (LUT6)
Inferred a: "set_disable_timing -from I2 -to O west_data_o_psum_inferred_i_2__0"
Found timing loop:
     0: west_data_o_psum_inferred_i_2/O (LUT6)
     1: west_data_o_psum_inferred_i_2/I3 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[14]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[14]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[14]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[14]
      : south_data_i_psum_inferred__0/out[14]
      : south_data_i_psum_inferred__0/in0[14]
      : south_data_i_psum_inferred/out[14]
      : south_data_i_psum_inferred/in0[14]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[14]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[14]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[14]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[14]
     2: west_data_o_psum_inferred_i_2__0/O (LUT6)
     3: west_data_o_psum_inferred_i_2__0/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_psum_inferred_i_2"
Found timing loop:
     0: west_data_o_psum_inferred_i_2/O (LUT6)
     1: west_data_o_psum_inferred_i_2/O (LUT6)
Found timing loop:
     0: west_data_o_psum_inferred_i_1__0/O (LUT6)
     1: west_data_o_psum_inferred_i_1__0/I5 (LUT6)
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /out[15]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred__0 /in0[15]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /out[15]
      : \HMNoC_cluster_west_1/north_data_i_psum_inferred /in0[15]
      : north_data_i_psum_inferred__0/out[15]
      : north_data_i_psum_inferred__0/in0[15]
      : north_data_i_psum_inferred/out[15]
      : north_data_i_psum_inferred/in0[15]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /out[15]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred__0 /in0[15]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /out[15]
      : \HMNoC_cluster_west_0/south_data_o_psum_inferred /in0[15]
     2: west_data_o_psum_inferred_i_1/O (LUT6)
     3: west_data_o_psum_inferred_i_1/I3 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[15]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[15]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[15]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[15]
      : south_data_i_psum_inferred__0/out[15]
      : south_data_i_psum_inferred__0/in0[15]
      : south_data_i_psum_inferred/out[15]
      : south_data_i_psum_inferred/in0[15]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[15]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[15]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[15]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[15]
     4: west_data_o_psum_inferred_i_1__0/O (LUT6)
Inferred a: "set_disable_timing -from I5 -to O west_data_o_psum_inferred_i_1__0"
Found timing loop:
     0: west_data_o_psum_inferred_i_1__1/O (LUT6)
     1: west_data_o_psum_inferred_i_1__1/I3 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /out[15]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred__0 /in0[15]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /out[15]
      : \HMNoC_cluster_east_0/south_data_i_psum_inferred /in0[15]
      : south_data_i_psum_inferred__2/out[15]
      : south_data_i_psum_inferred__2/in0[15]
      : south_data_i_psum_inferred__1/out[15]
      : south_data_i_psum_inferred__1/in0[15]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /out[15]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred__0 /in0[15]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /out[15]
      : \HMNoC_cluster_east_1/north_data_o_psum_inferred /in0[15]
     2: west_data_o_psum_inferred_i_1__2/O (LUT6)
     3: west_data_o_psum_inferred_i_1__2/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /out[15]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /in0[15]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /out[15]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /in0[15]
      : south_data_o_psum_inferred__2/out[15]
      : south_data_o_psum_inferred__2/in0[15]
      : south_data_o_psum_inferred__1/out[15]
      : south_data_o_psum_inferred__1/in0[15]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[15]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[15]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[15]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[15]
     4: west_data_o_psum_inferred_i_1__1/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_psum_inferred_i_1__1"
Found timing loop:
     0: west_data_o_psum_inferred_i_1__0/O (LUT6)
     1: west_data_o_psum_inferred_i_1__0/I2 (LUT6)
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred__0 /out[15]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred__0 /in0[15]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred /out[15]
      : \HMNoC_cluster_west_1/east_data_i_psum_inferred /in0[15]
      : east_data_i_psum_inferred__2/out[15]
      : east_data_i_psum_inferred__2/in0[15]
      : east_data_i_psum_inferred__1/out[15]
      : east_data_i_psum_inferred__1/in0[15]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred__0 /out[15]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred__0 /in0[15]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred /out[15]
      : \HMNoC_cluster_east_1/west_data_o_psum_inferred /in0[15]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred__0 /out[15]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred__0 /in0[15]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred /out[15]
      : \HMNoC_cluster_east_1/router_cluster_0/west_data_o_psum_inferred /in0[15]
     2: west_data_o_psum_inferred_i_1__2/O (LUT6)
     3: west_data_o_psum_inferred_i_1__2/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /out[15]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred__0 /in0[15]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /out[15]
      : \HMNoC_cluster_east_1/north_data_i_psum_inferred /in0[15]
      : south_data_o_psum_inferred__2/out[15]
      : south_data_o_psum_inferred__2/in0[15]
      : south_data_o_psum_inferred__1/out[15]
      : south_data_o_psum_inferred__1/in0[15]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /out[15]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred__0 /in0[15]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /out[15]
      : \HMNoC_cluster_east_0/south_data_o_psum_inferred /in0[15]
     4: west_data_o_psum_inferred_i_1__1/O (LUT6)
     5: west_data_o_psum_inferred_i_1__1/I2 (LUT6)
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /out[15]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred__0 /in0[15]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /out[15]
      : \HMNoC_cluster_east_0/west_data_i_psum_inferred /in0[15]
      : west_data_i_psum_inferred__0/out[15]
      : west_data_i_psum_inferred__0/in0[15]
      : west_data_i_psum_inferred/out[15]
      : west_data_i_psum_inferred/in0[15]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /out[15]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred__0 /in0[15]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /out[15]
      : \HMNoC_cluster_west_0/east_data_o_psum_inferred /in0[15]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /out[15]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred__0 /in0[15]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /out[15]
      : \HMNoC_cluster_west_0/router_cluster_0/east_data_o_psum_inferred /in0[15]
     6: west_data_o_psum_inferred_i_1/O (LUT6)
     7: west_data_o_psum_inferred_i_1/I3 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[15]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[15]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[15]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[15]
      : south_data_i_psum_inferred__0/out[15]
      : south_data_i_psum_inferred__0/in0[15]
      : south_data_i_psum_inferred/out[15]
      : south_data_i_psum_inferred/in0[15]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[15]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[15]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[15]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[15]
     8: west_data_o_psum_inferred_i_1__0/O (LUT6)
Inferred a: "set_disable_timing -from I2 -to O west_data_o_psum_inferred_i_1__0"
Found timing loop:
     0: west_data_o_psum_inferred_i_1/O (LUT6)
     1: west_data_o_psum_inferred_i_1/I3 (LUT6)
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /out[15]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred__0 /in0[15]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /out[15]
      : \HMNoC_cluster_west_0/south_data_i_psum_inferred /in0[15]
      : south_data_i_psum_inferred__0/out[15]
      : south_data_i_psum_inferred__0/in0[15]
      : south_data_i_psum_inferred/out[15]
      : south_data_i_psum_inferred/in0[15]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /out[15]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred__0 /in0[15]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /out[15]
      : \HMNoC_cluster_west_1/north_data_o_psum_inferred /in0[15]
     2: west_data_o_psum_inferred_i_1__0/O (LUT6)
     3: west_data_o_psum_inferred_i_1__0/O (LUT6)
Inferred a: "set_disable_timing -from I3 -to O west_data_o_psum_inferred_i_1"
Found timing loop:
     0: west_data_o_psum_inferred_i_1/O (LUT6)
     1: west_data_o_psum_inferred_i_1/O (LUT6)
Found timing loop:
     0: west_data_o_wght_inferred_i_16__1/O (LUT6)
     1: west_data_o_wght_inferred_i_16__1/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /out[0]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /in0[0]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /out[0]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /in0[0]
      : south_data_i_wght_inferred__2/out[0]
      : south_data_i_wght_inferred__2/in0[0]
      : south_data_i_wght_inferred__1/out[0]
      : south_data_i_wght_inferred__1/in0[0]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /out[0]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /in0[0]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /out[0]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /in0[0]
     2: west_data_o_wght_inferred_i_16__2/O (LUT6)
     3: west_data_o_wght_inferred_i_16__2/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /out[0]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /in0[0]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /out[0]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /in0[0]
      : north_data_i_wght_inferred__2/out[0]
      : north_data_i_wght_inferred__2/in0[0]
      : north_data_i_wght_inferred__1/out[0]
      : north_data_i_wght_inferred__1/in0[0]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /out[0]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /in0[0]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /out[0]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /in0[0]
     4: west_data_o_wght_inferred_i_16__1/O (LUT6)
Inferred a: "set_disable_timing -from I2 -to O west_data_o_wght_inferred_i_16__1"
Found timing loop:
     0: west_data_o_wght_inferred_i_14__1/O (LUT6)
     1: west_data_o_wght_inferred_i_14__1/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /out[2]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /in0[2]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /out[2]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /in0[2]
      : south_data_i_wght_inferred__2/out[2]
      : south_data_i_wght_inferred__2/in0[2]
      : south_data_i_wght_inferred__1/out[2]
      : south_data_i_wght_inferred__1/in0[2]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /out[2]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /in0[2]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /out[2]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /in0[2]
     2: west_data_o_wght_inferred_i_14__2/O (LUT6)
     3: west_data_o_wght_inferred_i_14__2/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /out[2]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /in0[2]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /out[2]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /in0[2]
      : north_data_i_wght_inferred__2/out[2]
      : north_data_i_wght_inferred__2/in0[2]
      : north_data_i_wght_inferred__1/out[2]
      : north_data_i_wght_inferred__1/in0[2]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /out[2]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /in0[2]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /out[2]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /in0[2]
     4: west_data_o_wght_inferred_i_14__1/O (LUT6)
Inferred a: "set_disable_timing -from I2 -to O west_data_o_wght_inferred_i_14__1"
Found timing loop:
     0: west_data_o_wght_inferred_i_12__1/O (LUT6)
     1: west_data_o_wght_inferred_i_12__1/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /out[4]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /in0[4]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /out[4]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /in0[4]
      : south_data_i_wght_inferred__2/out[4]
      : south_data_i_wght_inferred__2/in0[4]
      : south_data_i_wght_inferred__1/out[4]
      : south_data_i_wght_inferred__1/in0[4]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /out[4]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /in0[4]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /out[4]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /in0[4]
     2: west_data_o_wght_inferred_i_12__2/O (LUT6)
     3: west_data_o_wght_inferred_i_12__2/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /out[4]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /in0[4]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /out[4]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /in0[4]
      : north_data_i_wght_inferred__2/out[4]
      : north_data_i_wght_inferred__2/in0[4]
      : north_data_i_wght_inferred__1/out[4]
      : north_data_i_wght_inferred__1/in0[4]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /out[4]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /in0[4]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /out[4]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /in0[4]
     4: west_data_o_wght_inferred_i_12__1/O (LUT6)
Inferred a: "set_disable_timing -from I2 -to O west_data_o_wght_inferred_i_12__1"
Found timing loop:
     0: west_data_o_wght_inferred_i_11__1/O (LUT6)
     1: west_data_o_wght_inferred_i_11__1/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /out[5]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /in0[5]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /out[5]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /in0[5]
      : south_data_i_wght_inferred__2/out[5]
      : south_data_i_wght_inferred__2/in0[5]
      : south_data_i_wght_inferred__1/out[5]
      : south_data_i_wght_inferred__1/in0[5]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /out[5]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /in0[5]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /out[5]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /in0[5]
     2: west_data_o_wght_inferred_i_11__2/O (LUT6)
     3: west_data_o_wght_inferred_i_11__2/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /out[5]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /in0[5]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /out[5]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /in0[5]
      : north_data_i_wght_inferred__2/out[5]
      : north_data_i_wght_inferred__2/in0[5]
      : north_data_i_wght_inferred__1/out[5]
      : north_data_i_wght_inferred__1/in0[5]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /out[5]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /in0[5]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /out[5]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /in0[5]
     4: west_data_o_wght_inferred_i_11__1/O (LUT6)
Inferred a: "set_disable_timing -from I2 -to O west_data_o_wght_inferred_i_11__1"
Found timing loop:
     0: west_data_o_wght_inferred_i_10__1/O (LUT6)
     1: west_data_o_wght_inferred_i_10__1/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /out[6]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /in0[6]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /out[6]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /in0[6]
      : south_data_i_wght_inferred__2/out[6]
      : south_data_i_wght_inferred__2/in0[6]
      : south_data_i_wght_inferred__1/out[6]
      : south_data_i_wght_inferred__1/in0[6]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /out[6]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /in0[6]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /out[6]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /in0[6]
     2: west_data_o_wght_inferred_i_10__2/O (LUT6)
     3: west_data_o_wght_inferred_i_10__2/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /out[6]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /in0[6]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /out[6]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /in0[6]
      : north_data_i_wght_inferred__2/out[6]
      : north_data_i_wght_inferred__2/in0[6]
      : north_data_i_wght_inferred__1/out[6]
      : north_data_i_wght_inferred__1/in0[6]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /out[6]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /in0[6]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /out[6]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /in0[6]
     4: west_data_o_wght_inferred_i_10__1/O (LUT6)
Inferred a: "set_disable_timing -from I2 -to O west_data_o_wght_inferred_i_10__1"
Found timing loop:
     0: west_data_o_wght_inferred_i_8__1/O (LUT6)
     1: west_data_o_wght_inferred_i_8__1/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /out[8]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /in0[8]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /out[8]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /in0[8]
      : south_data_i_wght_inferred__2/out[8]
      : south_data_i_wght_inferred__2/in0[8]
      : south_data_i_wght_inferred__1/out[8]
      : south_data_i_wght_inferred__1/in0[8]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /out[8]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /in0[8]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /out[8]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /in0[8]
     2: west_data_o_wght_inferred_i_8__2/O (LUT6)
     3: west_data_o_wght_inferred_i_8__2/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /out[8]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /in0[8]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /out[8]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /in0[8]
      : north_data_i_wght_inferred__2/out[8]
      : north_data_i_wght_inferred__2/in0[8]
      : north_data_i_wght_inferred__1/out[8]
      : north_data_i_wght_inferred__1/in0[8]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /out[8]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /in0[8]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /out[8]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /in0[8]
     4: west_data_o_wght_inferred_i_8__1/O (LUT6)
Inferred a: "set_disable_timing -from I2 -to O west_data_o_wght_inferred_i_8__1"
Found timing loop:
     0: west_data_o_wght_inferred_i_7__1/O (LUT6)
     1: west_data_o_wght_inferred_i_7__1/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /out[9]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /in0[9]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /out[9]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /in0[9]
      : south_data_i_wght_inferred__2/out[9]
      : south_data_i_wght_inferred__2/in0[9]
      : south_data_i_wght_inferred__1/out[9]
      : south_data_i_wght_inferred__1/in0[9]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /out[9]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /in0[9]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /out[9]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /in0[9]
     2: west_data_o_wght_inferred_i_7__2/O (LUT6)
     3: west_data_o_wght_inferred_i_7__2/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /out[9]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /in0[9]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /out[9]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /in0[9]
      : north_data_i_wght_inferred__2/out[9]
      : north_data_i_wght_inferred__2/in0[9]
      : north_data_i_wght_inferred__1/out[9]
      : north_data_i_wght_inferred__1/in0[9]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /out[9]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /in0[9]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /out[9]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /in0[9]
     4: west_data_o_wght_inferred_i_7__1/O (LUT6)
Inferred a: "set_disable_timing -from I2 -to O west_data_o_wght_inferred_i_7__1"
Found timing loop:
     0: west_data_o_wght_inferred_i_6__1/O (LUT6)
     1: west_data_o_wght_inferred_i_6__1/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /out[10]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /in0[10]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /out[10]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /in0[10]
      : south_data_i_wght_inferred__2/out[10]
      : south_data_i_wght_inferred__2/in0[10]
      : south_data_i_wght_inferred__1/out[10]
      : south_data_i_wght_inferred__1/in0[10]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /out[10]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /in0[10]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /out[10]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /in0[10]
     2: west_data_o_wght_inferred_i_6__2/O (LUT6)
     3: west_data_o_wght_inferred_i_6__2/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /out[10]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /in0[10]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /out[10]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /in0[10]
      : north_data_i_wght_inferred__2/out[10]
      : north_data_i_wght_inferred__2/in0[10]
      : north_data_i_wght_inferred__1/out[10]
      : north_data_i_wght_inferred__1/in0[10]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /out[10]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /in0[10]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /out[10]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /in0[10]
     4: west_data_o_wght_inferred_i_6__1/O (LUT6)
Inferred a: "set_disable_timing -from I2 -to O west_data_o_wght_inferred_i_6__1"
Found timing loop:
     0: west_data_o_wght_inferred_i_3__1/O (LUT6)
     1: west_data_o_wght_inferred_i_3__1/I2 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /out[13]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /in0[13]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /out[13]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /in0[13]
      : south_data_i_wght_inferred__2/out[13]
      : south_data_i_wght_inferred__2/in0[13]
      : south_data_i_wght_inferred__1/out[13]
      : south_data_i_wght_inferred__1/in0[13]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /out[13]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /in0[13]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /out[13]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /in0[13]
     2: west_data_o_wght_inferred_i_3__2/O (LUT6)
     3: west_data_o_wght_inferred_i_3__2/I5 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /out[13]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /in0[13]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /out[13]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /in0[13]
      : north_data_i_wght_inferred__2/out[13]
      : north_data_i_wght_inferred__2/in0[13]
      : north_data_i_wght_inferred__1/out[13]
      : north_data_i_wght_inferred__1/in0[13]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /out[13]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /in0[13]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /out[13]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /in0[13]
     4: west_data_o_wght_inferred_i_3__1/O (LUT6)
Inferred a: "set_disable_timing -from I2 -to O west_data_o_wght_inferred_i_3__1"
Found timing loop:
     0: west_data_o_wght_inferred_i_15__2/O (LUT6)
     1: west_data_o_wght_inferred_i_15__2/I0 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /out[1]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /in0[1]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /out[1]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /in0[1]
      : north_data_i_wght_inferred__2/out[1]
      : north_data_i_wght_inferred__2/in0[1]
      : north_data_i_wght_inferred__1/out[1]
      : north_data_i_wght_inferred__1/in0[1]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /out[1]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /in0[1]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /out[1]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /in0[1]
     2: west_data_o_wght_inferred_i_15__1/O (LUT6)
     3: west_data_o_wght_inferred_i_15__1/I3 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /out[1]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /in0[1]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /out[1]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /in0[1]
      : south_data_i_wght_inferred__2/out[1]
      : south_data_i_wght_inferred__2/in0[1]
      : south_data_i_wght_inferred__1/out[1]
      : south_data_i_wght_inferred__1/in0[1]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /out[1]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /in0[1]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /out[1]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /in0[1]
     4: west_data_o_wght_inferred_i_15__2/O (LUT6)
Inferred a: "set_disable_timing -from I0 -to O west_data_o_wght_inferred_i_15__2"
Found timing loop:
     0: west_data_o_wght_inferred_i_13__2/O (LUT6)
     1: west_data_o_wght_inferred_i_13__2/I0 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /out[3]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /in0[3]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /out[3]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /in0[3]
      : north_data_i_wght_inferred__2/out[3]
      : north_data_i_wght_inferred__2/in0[3]
      : north_data_i_wght_inferred__1/out[3]
      : north_data_i_wght_inferred__1/in0[3]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /out[3]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /in0[3]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /out[3]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /in0[3]
     2: west_data_o_wght_inferred_i_13__1/O (LUT6)
     3: west_data_o_wght_inferred_i_13__1/I3 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /out[3]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /in0[3]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /out[3]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /in0[3]
      : south_data_i_wght_inferred__2/out[3]
      : south_data_i_wght_inferred__2/in0[3]
      : south_data_i_wght_inferred__1/out[3]
      : south_data_i_wght_inferred__1/in0[3]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /out[3]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /in0[3]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /out[3]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /in0[3]
     4: west_data_o_wght_inferred_i_13__2/O (LUT6)
Inferred a: "set_disable_timing -from I0 -to O west_data_o_wght_inferred_i_13__2"
Found timing loop:
     0: west_data_o_wght_inferred_i_9__2/O (LUT6)
     1: west_data_o_wght_inferred_i_9__2/I0 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /out[7]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /in0[7]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /out[7]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /in0[7]
      : north_data_i_wght_inferred__2/out[7]
      : north_data_i_wght_inferred__2/in0[7]
      : north_data_i_wght_inferred__1/out[7]
      : north_data_i_wght_inferred__1/in0[7]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /out[7]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /in0[7]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /out[7]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /in0[7]
     2: west_data_o_wght_inferred_i_9__1/O (LUT6)
     3: west_data_o_wght_inferred_i_9__1/I3 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /out[7]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /in0[7]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /out[7]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /in0[7]
      : south_data_i_wght_inferred__2/out[7]
      : south_data_i_wght_inferred__2/in0[7]
      : south_data_i_wght_inferred__1/out[7]
      : south_data_i_wght_inferred__1/in0[7]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /out[7]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /in0[7]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /out[7]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /in0[7]
     4: west_data_o_wght_inferred_i_9__2/O (LUT6)
Inferred a: "set_disable_timing -from I0 -to O west_data_o_wght_inferred_i_9__2"
Found timing loop:
     0: west_data_o_wght_inferred_i_5__2/O (LUT6)
     1: west_data_o_wght_inferred_i_5__2/I0 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /out[11]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /in0[11]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /out[11]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /in0[11]
      : north_data_i_wght_inferred__2/out[11]
      : north_data_i_wght_inferred__2/in0[11]
      : north_data_i_wght_inferred__1/out[11]
      : north_data_i_wght_inferred__1/in0[11]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /out[11]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /in0[11]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /out[11]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /in0[11]
     2: west_data_o_wght_inferred_i_5__1/O (LUT6)
     3: west_data_o_wght_inferred_i_5__1/I3 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /out[11]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /in0[11]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /out[11]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /in0[11]
      : south_data_i_wght_inferred__2/out[11]
      : south_data_i_wght_inferred__2/in0[11]
      : south_data_i_wght_inferred__1/out[11]
      : south_data_i_wght_inferred__1/in0[11]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /out[11]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /in0[11]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /out[11]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /in0[11]
     4: west_data_o_wght_inferred_i_5__2/O (LUT6)
Inferred a: "set_disable_timing -from I0 -to O west_data_o_wght_inferred_i_5__2"
Found timing loop:
     0: west_data_o_wght_inferred_i_4__2/O (LUT6)
     1: west_data_o_wght_inferred_i_4__2/I0 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /out[12]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /in0[12]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /out[12]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /in0[12]
      : north_data_i_wght_inferred__2/out[12]
      : north_data_i_wght_inferred__2/in0[12]
      : north_data_i_wght_inferred__1/out[12]
      : north_data_i_wght_inferred__1/in0[12]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /out[12]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /in0[12]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /out[12]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /in0[12]
     2: west_data_o_wght_inferred_i_4__1/O (LUT6)
     3: west_data_o_wght_inferred_i_4__1/I3 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /out[12]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /in0[12]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /out[12]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /in0[12]
      : south_data_i_wght_inferred__2/out[12]
      : south_data_i_wght_inferred__2/in0[12]
      : south_data_i_wght_inferred__1/out[12]
      : south_data_i_wght_inferred__1/in0[12]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /out[12]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /in0[12]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /out[12]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /in0[12]
     4: west_data_o_wght_inferred_i_4__2/O (LUT6)
Inferred a: "set_disable_timing -from I0 -to O west_data_o_wght_inferred_i_4__2"
Found timing loop:
     0: west_data_o_wght_inferred_i_2__2/O (LUT6)
     1: west_data_o_wght_inferred_i_2__2/I0 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /out[14]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /in0[14]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /out[14]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /in0[14]
      : north_data_i_wght_inferred__2/out[14]
      : north_data_i_wght_inferred__2/in0[14]
      : north_data_i_wght_inferred__1/out[14]
      : north_data_i_wght_inferred__1/in0[14]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /out[14]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /in0[14]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /out[14]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /in0[14]
     2: west_data_o_wght_inferred_i_2__1/O (LUT6)
     3: west_data_o_wght_inferred_i_2__1/I3 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /out[14]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /in0[14]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /out[14]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /in0[14]
      : south_data_i_wght_inferred__2/out[14]
      : south_data_i_wght_inferred__2/in0[14]
      : south_data_i_wght_inferred__1/out[14]
      : south_data_i_wght_inferred__1/in0[14]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /out[14]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /in0[14]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /out[14]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /in0[14]
     4: west_data_o_wght_inferred_i_2__2/O (LUT6)
Inferred a: "set_disable_timing -from I0 -to O west_data_o_wght_inferred_i_2__2"
Found timing loop:
     0: west_data_o_wght_inferred_i_1__2/O (LUT6)
     1: west_data_o_wght_inferred_i_1__2/I0 (LUT6)
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /out[15]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred__0 /in0[15]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /out[15]
      : \HMNoC_cluster_east_1/north_data_i_wght_inferred /in0[15]
      : north_data_i_wght_inferred__2/out[15]
      : north_data_i_wght_inferred__2/in0[15]
      : north_data_i_wght_inferred__1/out[15]
      : north_data_i_wght_inferred__1/in0[15]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /out[15]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred__0 /in0[15]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /out[15]
      : \HMNoC_cluster_east_0/south_data_o_wght_inferred /in0[15]
     2: west_data_o_wght_inferred_i_1__1/O (LUT6)
     3: west_data_o_wght_inferred_i_1__1/I3 (LUT6)
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /out[15]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred__0 /in0[15]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /out[15]
      : \HMNoC_cluster_east_0/south_data_i_wght_inferred /in0[15]
      : south_data_i_wght_inferred__2/out[15]
      : south_data_i_wght_inferred__2/in0[15]
      : south_data_i_wght_inferred__1/out[15]
      : south_data_i_wght_inferred__1/in0[15]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /out[15]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred__0 /in0[15]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /out[15]
      : \HMNoC_cluster_east_1/north_data_o_wght_inferred /in0[15]
     4: west_data_o_wght_inferred_i_1__2/O (LUT6)
Inferred a: "set_disable_timing -from I0 -to O west_data_o_wght_inferred_i_1__2"
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:59 ; elapsed = 00:01:08 . Memory (MB): peak = 2126.836 ; gain = 1865.652
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:59 ; elapsed = 00:01:08 . Memory (MB): peak = 2126.836 ; gain = 1865.652
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:59 ; elapsed = 00:01:08 . Memory (MB): peak = 2126.836 ; gain = 1865.652
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:59 ; elapsed = 00:01:08 . Memory (MB): peak = 2126.836 ; gain = 1865.652
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------

Report BlackBoxes: 
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+

Report Cell Usage: 
+------+----------------+------+
|      |Cell            |Count |
+------+----------------+------+
|1     |BUFG            |     1|
|2     |CARRY8          |     6|
|3     |DSP_ALU         |     9|
|4     |DSP_A_B_DATA    |     9|
|5     |DSP_C_DATA      |     9|
|6     |DSP_MULTIPLIER  |     9|
|7     |DSP_M_DATA      |     9|
|8     |DSP_OUTPUT      |     9|
|9     |DSP_PREADD      |     9|
|10    |DSP_PREADD_DATA |     9|
|11    |LUT1            |  1042|
|12    |LUT2            |   111|
|13    |LUT3            |   169|
|14    |LUT4            |   315|
|15    |LUT5            |   280|
|16    |LUT6            |  1055|
|17    |MUXF7           |    84|
|18    |RAM64M8         |   196|
|19    |RAM64X1D        |   196|
|20    |FDRE            |   746|
|21    |FDSE            |    24|
|22    |IBUF            |   108|
|23    |OBUF            |    66|
+------+----------------+------+

Report Instance Areas: 
+------+----------------------------------------+-----------------------------------------------+------+
|      |Instance                                |Module                                         |Cells |
+------+----------------------------------------+-----------------------------------------------+------+
|1     |top                                     |                                               |  4471|
|2     |  HMNoC_cluster_east_0                  |HMNoC_cluster_east__hierPathDup__1             |   266|
|3     |    GLB_cluster_0                       |GLB_cluster                                    |    36|
|4     |      \glb_iact_gen[0].glb_iact_inst    |glb_iact_23                                    |     9|
|5     |      \glb_wght_gen[0].glb_weight_inst  |glb_weight_24                                  |    20|
|6     |    pe_cluster_0                        |PE_cluster                                     |     0|
|7     |    router_cluster_0                    |router_cluster                                 |    50|
|8     |  HMNoC_cluster_east_1                  |HMNoC_cluster_east                             |   240|
|9     |    GLB_cluster_0                       |GLB_cluster__hierPathDup__2                    |    36|
|10    |      \glb_iact_gen[0].glb_iact_inst    |glb_iact_21                                    |     1|
|11    |      \glb_wght_gen[0].glb_weight_inst  |glb_weight_22                                  |    20|
|12    |    pe_cluster_0                        |PE_cluster__hierPathDup__2                     |     0|
|13    |    router_cluster_0                    |router_cluster__hierPathDup__2                 |    51|
|14    |      router_iact                       |router_20                                      |     1|
|15    |  HMNoC_cluster_west_0                  |HMNoC_cluster_west                             |  3164|
|16    |    GLB_cluster_0                       |GLB_cluster__hierPathDup__1                    |   315|
|17    |      \glb_iact_gen[0].glb_iact_inst    |glb_iact_18                                    |   105|
|18    |      \glb_psum_gen[0].glb_psum_inst    |glb_psum                                       |   105|
|19    |      \glb_wght_gen[0].glb_weight_inst  |glb_weight_19                                  |   105|
|20    |    pe_cluster_0                        |PE_cluster__hierPathDup__1                     |  2677|
|21    |      \gen_X[0].gen_Y[0].pe             |PE                                             |   320|
|22    |        mac_0                           |MAC_16                                         |    60|
|23    |          out_reg                       |\gen_X[0].gen_Y[0].pe/mac_0/out_reg_funnel     |     8|
|24    |        spad_pe0                        |SPad_17                                        |   105|
|25    |      \gen_X[0].gen_Y[1].pe             |PE__parameterized0                             |   280|
|26    |        mac_0                           |MAC_14                                         |    30|
|27    |          out_reg                       |\gen_X[0].gen_Y[0].pe/mac_0/out_reg_funnel__1  |     8|
|28    |        spad_pe0                        |SPad_15                                        |   105|
|29    |      \gen_X[0].gen_Y[2].pe             |PE__parameterized1                             |   283|
|30    |        mac_0                           |MAC_12                                         |    29|
|31    |          out_reg                       |\gen_X[0].gen_Y[0].pe/mac_0/out_reg_funnel__2  |     8|
|32    |        spad_pe0                        |SPad_13                                        |   105|
|33    |      \gen_X[1].gen_Y[0].pe             |PE__parameterized2                             |   305|
|34    |        mac_0                           |MAC_10                                         |    60|
|35    |          out_reg                       |\gen_X[0].gen_Y[0].pe/mac_0/out_reg_funnel__3  |     8|
|36    |        spad_pe0                        |SPad_11                                        |   105|
|37    |      \gen_X[1].gen_Y[1].pe             |PE__parameterized3                             |   284|
|38    |        mac_0                           |MAC_8                                          |    30|
|39    |          out_reg                       |\gen_X[0].gen_Y[0].pe/mac_0/out_reg_funnel__4  |     8|
|40    |        spad_pe0                        |SPad_9                                         |   105|
|41    |      \gen_X[1].gen_Y[2].pe             |PE__parameterized4                             |   284|
|42    |        mac_0                           |MAC_6                                          |    29|
|43    |          out_reg                       |\gen_X[0].gen_Y[0].pe/mac_0/out_reg_funnel__5  |     8|
|44    |        spad_pe0                        |SPad_7                                         |   105|
|45    |      \gen_X[2].gen_Y[0].pe             |PE__parameterized5                             |   308|
|46    |        mac_0                           |MAC_4                                          |    60|
|47    |          out_reg                       |\gen_X[0].gen_Y[0].pe/mac_0/out_reg_funnel__6  |     8|
|48    |        spad_pe0                        |SPad_5                                         |   105|
|49    |      \gen_X[2].gen_Y[1].pe             |PE__parameterized6                             |   284|
|50    |        mac_0                           |MAC_2                                          |    30|
|51    |          out_reg                       |\gen_X[0].gen_Y[0].pe/mac_0/out_reg_funnel__7  |     8|
|52    |        spad_pe0                        |SPad_3                                         |   105|
|53    |      \gen_X[2].gen_Y[2].pe             |PE__parameterized7                             |   281|
|54    |        mac_0                           |MAC                                            |    29|
|55    |          out_reg                       |\gen_X[0].gen_Y[0].pe/mac_0/out_reg_funnel__8  |     8|
|56    |        spad_pe0                        |SPad                                           |   105|
|57    |    router_cluster_0                    |router_cluster__hierPathDup__1                 |    56|
|58    |      router_iact                       |router                                         |     1|
|59    |      router_psum                       |router_0                                       |     4|
|60    |      router_wght                       |router_1                                       |     3|
|61    |  HMNoC_cluster_west_1                  |HMNoC_cluster_west__hierPathDup__1             |   269|
|62    |    GLB_cluster_0                       |GLB_cluster__hierPathDup__1__hierPathDup__1    |    32|
|63    |      \glb_iact_gen[0].glb_iact_inst    |glb_iact                                       |     9|
|64    |      \glb_wght_gen[0].glb_weight_inst  |glb_weight                                     |     9|
|65    |    pe_cluster_0                        |PE_cluster__hierPathDup__3                     |     0|
|66    |    router_cluster_0                    |router_cluster__hierPathDup__1__hierPathDup__1 |    50|
+------+----------------------------------------+-----------------------------------------------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:59 ; elapsed = 00:01:08 . Memory (MB): peak = 2126.836 ; gain = 1865.652
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 431 critical warnings and 134 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:45 ; elapsed = 00:00:55 . Memory (MB): peak = 2126.836 ; gain = 754.430
Synthesis Optimization Complete : Time (s): cpu = 00:00:59 ; elapsed = 00:01:08 . Memory (MB): peak = 2126.836 ; gain = 1865.652
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Netlist 29-17] Analyzing 600 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2133.340 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 510 instances were transformed.
  BUFG => BUFGCE: 1 instances
  DSP48E2 => DSP48E2 (DSP_ALU, DSP_A_B_DATA, DSP_C_DATA, DSP_MULTIPLIER, DSP_M_DATA, DSP_OUTPUT, DSP_PREADD_DATA, DSP_PREADD): 9 instances
  IBUF => IBUF (IBUFCTRL, INBUF): 108 instances
  RAM64M8 => RAM64M8 (RAMD64E, RAMD64E, RAMD64E, RAMD64E, RAMD64E, RAMD64E, RAMD64E, RAMD64E): 196 instances
  RAM64X1D => RAM64X1D (RAMD64E, RAMD64E): 196 instances

INFO: [Common 17-83] Releasing license: Synthesis
302 Infos, 266 Warnings, 195 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:01:03 ; elapsed = 00:01:14 . Memory (MB): peak = 2133.340 ; gain = 1879.988
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 2133.340 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint 'D:/Fall 19/CSE 240D/Project/Vivado/src/HMNoC/HMNoC.runs/synth_1/HMNoC_top.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file HMNoC_top_utilization_synth.rpt -pb HMNoC_top_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Fri Dec 13 11:08:05 2019...


================================================
FILE: synth/HMNoC_top_utilization_synth.rpt
================================================
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec  6 23:38:27 MST 2018
| Date         : Fri Dec 13 11:08:05 2019
| Host         : Karthi running 64-bit major release  (build 9200)
| Command      : report_utilization -file HMNoC_top_utilization_synth.rpt -pb HMNoC_top_utilization_synth.pb
| Design       : HMNoC_top
| Device       : xczu7evffvf1517-1LV
| Design State : Synthesized
-------------------------------------------------------------------------------------------------------------

Utilization Design Information

Table of Contents
-----------------
1. CLB Logic
1.1 Summary of Registers by Type
2. BLOCKRAM
3. ARITHMETIC
4. I/O
5. CLOCK
6. ADVANCED
7. CONFIGURATION
8. Primitives
9. Black Boxes
10. Instantiated Netlists

1. CLB Logic
------------

+----------------------------+------+-------+-----------+-------+
|          Site Type         | Used | Fixed | Available | Util% |
+----------------------------+------+-------+-----------+-------+
| CLB LUTs*                  | 4679 |     0 |    230400 |  2.03 |
|   LUT as Logic             | 2719 |     0 |    230400 |  1.18 |
|   LUT as Memory            | 1960 |     0 |    101760 |  1.93 |
|     LUT as Distributed RAM | 1960 |     0 |           |       |
|     LUT as Shift Register  |    0 |     0 |           |       |
| CLB Registers              |  770 |     0 |    460800 |  0.17 |
|   Register as Flip Flop    |  770 |     0 |    460800 |  0.17 |
|   Register as Latch        |    0 |     0 |    460800 |  0.00 |
| CARRY8                     |    6 |     0 |     28800 |  0.02 |
| F7 Muxes                   |   84 |     0 |    115200 |  0.07 |
| F8 Muxes                   |    0 |     0 |     57600 |  0.00 |
| F9 Muxes                   |    0 |     0 |     28800 |  0.00 |
+----------------------------+------+-------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.


1.1 Summary of Registers by Type
--------------------------------

+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0     |            _ |           - |            - |
| 0     |            _ |           - |          Set |
| 0     |            _ |           - |        Reset |
| 0     |            _ |         Set |            - |
| 0     |            _ |       Reset |            - |
| 0     |          Yes |           - |            - |
| 0     |          Yes |           - |          Set |
| 0     |          Yes |           - |        Reset |
| 24    |          Yes |         Set |            - |
| 746   |          Yes |       Reset |            - |
+-------+--------------+-------------+--------------+


2. BLOCKRAM
-----------

+----------------+------+-------+-----------+-------+
|    Site Type   | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| Block RAM Tile |    0 |     0 |       312 |  0.00 |
|   RAMB36/FIFO* |    0 |     0 |       312 |  0.00 |
|   RAMB18       |    0 |     0 |       624 |  0.00 |
| URAM           |    0 |     0 |        96 |  0.00 |
+----------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E2 or one FIFO18E2. However, if a FIFO18E2 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E2


3. ARITHMETIC
-------------

+----------------+------+-------+-----------+-------+
|    Site Type   | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| DSPs           |    9 |     0 |      1728 |  0.52 |
|   DSP48E2 only |    9 |       |           |       |
+----------------+------+-------+-----------+-------+


4. I/O
------

+------------+------+-------+-----------+-------+
|  Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
| Bonded IOB |  174 |     0 |       464 | 37.50 |
+------------+------+-------+-----------+-------+


5. CLOCK
--------

+----------------------+------+-------+-----------+-------+
|       Site Type      | Used | Fixed | Available | Util% |
+----------------------+------+-------+-----------+-------+
| GLOBAL CLOCK BUFFERs |    1 |     0 |       544 |  0.18 |
|   BUFGCE             |    1 |     0 |       208 |  0.48 |
|   BUFGCE_DIV         |    0 |     0 |        32 |  0.00 |
|   BUFG_GT            |    0 |     0 |       144 |  0.00 |
|   BUFG_PS            |    0 |     0 |        96 |  0.00 |
|   BUFGCTRL*          |    0 |     0 |        64 |  0.00 |
| PLL                  |    0 |     0 |        16 |  0.00 |
| MMCM                 |    0 |     0 |         8 |  0.00 |
+----------------------+------+-------+-----------+-------+
* Note: Each used BUFGCTRL counts as two global buffer resources. This table does not include global clocking resources, only buffer cell usage. See the Clock Utilization Report (report_clock_utilization) for detailed accounting of global clocking resource availability.


6. ADVANCED
-----------

+-----------------+------+-------+-----------+-------+
|    Site Type    | Used | Fixed | Available | Util% |
+-----------------+------+-------+-----------+-------+
| GTHE4_CHANNEL   |    0 |     0 |        24 |  0.00 |
| GTHE4_COMMON    |    0 |     0 |         6 |  0.00 |
| OBUFDS_GTE4     |    0 |     0 |        12 |  0.00 |
| OBUFDS_GTE4_ADV |    0 |     0 |        12 |  0.00 |
| PCIE40E4        |    0 |     0 |         2 |  0.00 |
| PS8             |    0 |     0 |         1 |  0.00 |
| SYSMONE4        |    0 |     0 |         1 |  0.00 |
| VCU             |    0 |     0 |         1 |  0.00 |
+-----------------+------+-------+-----------+-------+


7. CONFIGURATION
----------------

+-------------+------+-------+-----------+-------+
|  Site Type  | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2     |    0 |     0 |         4 |  0.00 |
| DNA_PORTE2  |    0 |     0 |         1 |  0.00 |
| EFUSE_USR   |    0 |     0 |         1 |  0.00 |
| FRAME_ECCE4 |    0 |     0 |         1 |  0.00 |
| ICAPE3      |    0 |     0 |         2 |  0.00 |
| MASTER_JTAG |    0 |     0 |         1 |  0.00 |
| STARTUPE3   |    0 |     0 |         1 |  0.00 |
+-------------+------+-------+-----------+-------+


8. Primitives
-------------

+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| RAMD64E  | 1960 |                 CLB |
| LUT6     | 1055 |                 CLB |
| LUT1     | 1042 |                 CLB |
| FDRE     |  746 |            Register |
| LUT4     |  315 |                 CLB |
| LUT5     |  280 |                 CLB |
| LUT3     |  169 |                 CLB |
| LUT2     |  111 |                 CLB |
| INBUF    |  108 |                 I/O |
| IBUFCTRL |  108 |              Others |
| MUXF7    |   84 |                 CLB |
| OBUF     |   66 |                 I/O |
| FDSE     |   24 |            Register |
| DSP48E2  |    9 |          Arithmetic |
| CARRY8   |    6 |                 CLB |
| BUFGCE   |    1 |               Clock |
+----------+------+---------------------+


9. Black Boxes
--------------

+----------+------+
| Ref Name | Used |
+----------+------+


10. Instantiated Netlists
-------------------------

+----------+------+
| Ref Name | Used |
+----------+------+




================================================
FILE: synth/constraints_1.xdc
================================================
create_clock -period 3.500 -name clk -waveform {0.000 1.750} -add clk







================================================
FILE: testbench/GLB_cluster_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/01/2019 01:54:30 PM
// Design Name: 
// Module Name: GLB_cluster_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module GLB_cluster_tb();

    parameter DATA_BITWIDTH = 16;
	parameter ADDR_BITWIDTH = 10;
    parameter NUM_GLB_IACT = 1;
    parameter NUM_GLB_PSUM = 1;
	parameter NUM_GLB_WGHT = 1;
	
    logic clk;
    logic reset;

    logic read_req_iact[NUM_GLB_IACT-1:0];
	logic read_req_psum[NUM_GLB_PSUM-1:0];
	logic read_req_wght[NUM_GLB_WGHT-1:0];
	
    logic write_en_iact[NUM_GLB_IACT-1:0];
	logic write_en_psum[NUM_GLB_PSUM-1:0];
	logic write_en_wght[NUM_GLB_WGHT-1:0];
	
    logic [ADDR_BITWIDTH-1 : 0] r_addr_iact[NUM_GLB_IACT-1:0];
    logic [ADDR_BITWIDTH-1 : 0] r_addr_psum[NUM_GLB_PSUM-1:0];
	logic [ADDR_BITWIDTH-1 : 0] r_addr_wght[NUM_GLB_WGHT-1:0];
	
    logic [ADDR_BITWIDTH-1 : 0] w_addr_iact[NUM_GLB_IACT-1:0];
    logic [ADDR_BITWIDTH-1 : 0] w_addr_psum[NUM_GLB_PSUM-1:0];
	logic [ADDR_BITWIDTH-1 : 0] w_addr_wght[NUM_GLB_WGHT-1:0];
	
    logic [DATA_BITWIDTH-1 : 0] w_data_iact[NUM_GLB_IACT-1:0];
    logic [DATA_BITWIDTH-1 : 0] w_data_psum[NUM_GLB_PSUM-1:0];
	logic [DATA_BITWIDTH-1 : 0] w_data_wght[NUM_GLB_WGHT-1:0];
	
    logic [DATA_BITWIDTH-1 : 0] r_data_iact[NUM_GLB_IACT-1:0];
    logic [DATA_BITWIDTH-1 : 0] r_data_psum[NUM_GLB_PSUM-1:0];
    logic [DATA_BITWIDTH-1 : 0] r_data_wght[NUM_GLB_WGHT-1:0];

	GLB_cluster 
			#(	.DATA_BITWIDTH(DATA_BITWIDTH),
				.ADDR_BITWIDTH(ADDR_BITWIDTH),
				.NUM_GLB_IACT(NUM_GLB_IACT),
				.NUM_GLB_PSUM(NUM_GLB_PSUM),
				.NUM_GLB_WGHT(NUM_GLB_WGHT)
			)
	GLB_cluster_0
			(
				.clk(clk), 
				.reset(reset),
				
				.read_req_iact(read_req_iact),
				.read_req_psum(read_req_psum),
				.read_req_wght(read_req_wght),
				
				.write_en_iact(write_en_iact),
				.write_en_psum(write_en_psum),
				.write_en_wght(write_en_wght),
				
				.r_addr_iact(r_addr_iact),
			    .r_addr_psum(r_addr_psum),
				.r_addr_wght(r_addr_wght),

			    .w_addr_iact(w_addr_iact),
			    .w_addr_psum(w_addr_psum),
				.w_addr_wght(w_addr_wght),

			    .w_data_iact(w_data_iact),
			    .w_data_psum(w_data_psum),
				.w_data_wght(w_data_wght),

			    .r_data_iact(r_data_iact),
			    .r_data_psum(r_data_psum),
				.r_data_wght(r_data_wght)
			);
			
			
	always begin
		clk = 0; #10;
		clk = 1; #10;
	end

	
	initial begin
		reset = 1; #30;
		reset = 0;
	
		write_en_iact[0] = 1;
		write_en_psum[0] = 1;
		write_en_wght[0] = 1;
		
		for(int i=0; i<16; i++) begin
			w_addr_iact[0] = i;
			w_data_iact[0] = i*2;

			w_addr_psum[0] = i;
			w_data_psum[0] = i;
			
			w_addr_wght[0] = i;
			w_data_wght[0] = i*3;
			
			#20;
		end
		
		write_en_iact[0] = 0;
		write_en_psum[0] = 0;
		write_en_wght[0] = 0;
		
		for(int i=0; i<2; i++) begin
			w_addr_iact[0] = i;
			w_data_iact[0] = i*200;

			w_addr_psum[0] = i;
			w_data_psum[0] = i*200;
			
			w_addr_wght[0] = i;
			w_data_wght[0] = i*200;			
			
			#20;
		end
	
	#100;
	
		read_req_iact[0] = 1;
		read_req_psum[0] = 1;
		read_req_wght[0] = 1;
		
		for(int i=0; i<16; i++  ) begin
			r_addr_iact[0] = i;

			r_addr_psum[0] = i;
			
			r_addr_wght[0] = i;
			#20;
		end
	
		read_req_iact[0] = 0;
		read_req_psum[0] = 0;
		read_req_wght[0] = 0;
		
		for(int i=0; i<2; i++) begin
			r_addr_iact[0] = i;

			r_addr_psum[0] = i;
			
			r_addr_wght[0] = i;
			
			#20;
		end
		
	end
	 
endmodule

================================================
FILE: testbench/HMNoC_1_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/01/2019 04:37:46 PM
// Design Name: 
// Module Name: HMNoC_1_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module HMNoC_1_tb();

	parameter DATA_BITWIDTH = 16;
	parameter ADDR_BITWIDTH = 10;
	
	// GLB Cluster parameters. This TestBench uses only 1 of each
    parameter NUM_GLB_IACT = 1;
    parameter NUM_GLB_PSUM = 1;
	parameter NUM_GLB_WGHT = 1;
	
	
    logic clk;
    logic reset;

	//logic for GLB cluster
    logic read_req_iact[NUM_GLB_IACT-1:0];
	logic read_req_psum[NUM_GLB_PSUM-1:0];
	logic read_req_wght[NUM_GLB_WGHT-1:0];
	
    logic write_en_iact[NUM_GLB_IACT-1:0];
	logic write_en_psum[NUM_GLB_PSUM-1:0];
	logic write_en_wght[NUM_GLB_WGHT-1:0];
	
    logic [ADDR_BITWIDTH-1 : 0] r_addr_iact[NUM_GLB_IACT-1:0];
    logic [ADDR_BITWIDTH-1 : 0] r_addr_psum[NUM_GLB_PSUM-1:0];
	logic [ADDR_BITWIDTH-1 : 0] r_addr_wght[NUM_GLB_WGHT-1:0];
	
    logic [ADDR_BITWIDTH-1 : 0] w_addr_iact[NUM_GLB_IACT-1:0];
    logic [ADDR_BITWIDTH-1 : 0] w_addr_psum[NUM_GLB_PSUM-1:0];
	logic [ADDR_BITWIDTH-1 : 0] w_addr_wght[NUM_GLB_WGHT-1:0];
	
    logic [DATA_BITWIDTH-1 : 0] w_data_iact[NUM_GLB_IACT-1:0];
    logic [DATA_BITWIDTH-1 : 0] w_data_psum[NUM_GLB_PSUM-1:0];
	logic [DATA_BITWIDTH-1 : 0] w_data_wght[NUM_GLB_WGHT-1:0];
	
    logic [DATA_BITWIDTH-1 : 0] r_data_iact[NUM_GLB_IACT-1:0];
    logic [DATA_BITWIDTH-1 : 0] r_data_psum[NUM_GLB_PSUM-1:0];
    logic [DATA_BITWIDTH-1 : 0] r_data_wght[NUM_GLB_WGHT-1:0];

	
	//GLB cluster initialization
	GLB_cluster 
			#(	.DATA_BITWIDTH(DATA_BITWIDTH),
				.ADDR_BITWIDTH(ADDR_BITWIDTH),
				.NUM_GLB_IACT(NUM_GLB_IACT),
				.NUM_GLB_PSUM(NUM_GLB_PSUM),
				.NUM_GLB_WGHT(NUM_GLB_WGHT)
			)
	GLB_cluster_0
			(
				.clk(clk), 
				.reset(reset),
				
				.read_req_iact(read_req_iact),
				.read_req_psum(read_req_psum),
				.read_req_wght(read_req_wght),
				
				.write_en_iact(write_en_iact),
				.write_en_psum(write_en_psum),
				.write_en_wght(write_en_wght),
				
				.r_addr_iact(r_addr_iact),
			    .r_addr_psum(r_addr_psum),
				.r_addr_wght(r_addr_wght),

			    .w_addr_iact(w_addr_iact),
			    .w_addr_psum(w_addr_psum),
				.w_addr_wght(w_addr_wght),

			    .w_data_iact(w_data_iact),
			    .w_data_psum(w_data_psum),
				.w_data_wght(w_data_wght),

			    .r_data_iact(r_data_iact),
			    .r_data_psum(r_data_psum),
				.r_data_wght(r_data_wght)
			);

			
	// Router Instantiation
			
	integer clk_prd = 10;
	
	always begin
		clk = 0; #(clk_prd/2);
		clk = 1; #(clk_prd/2);
		//0.1GHz
	end
	
	integer kernel_1,act_1;
	integer w_addr = 0;
	int args;
	
	initial begin
		reset = 1; #30;
		reset = 0;
		

		//Write weights to weight glb
		write_en_wght[0] = 1;
		kernel_1 = $fopen("kernel_3x3.txt","r");		
		while(!$feof(kernel_1))begin
			w_addr_wght[0] = w_addr;
			args = $fscanf(kernel_1,"%d\n",w_data_wght[0]);
			$display("Writing value %0d to address %0d in weight glb",w_data_wght[0],w_addr);
			w_addr++;
			#(clk_prd);
		end
		write_en_wght[0] = 0;
		$fclose(kernel_1); 
		
		
		//Write activations to weight glb
		write_en_iact[0] = 1;
		w_addr = 0;
		act_1 = $fopen("act_5x5.txt","r");
		while(!$feof(act_1))begin
			w_addr_iact[0] = w_addr;
			args = $fscanf(act_1,"%d\n",w_data_iact[0]);
			$display("Writing value %0d to address %0d in iact glb",w_data_iact[0],w_addr);
			w_addr++;
			#(clk_prd);
		end
		write_en_iact[0] = 0;
		$fclose(act_1); 
		
		
//		write_en_wght[0] = 0;
	
	end
	
endmodule


================================================
FILE: testbench/HMNoC_cluster_west_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/10/2019 01:41:06 PM
// Design Name: 
// Module Name: HMNoC_cluster_west_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module HMNoC_cluster_west_tb();

		parameter DATA_BITWIDTH = 16;
		parameter ADDR_BITWIDTH = 10;
		
		parameter DATA_WIDTH = 16;
		parameter ADDR_WIDTH = 9;
		
		// GLB Cluster parameters. This TestBench uses only 1 of each
		parameter NUM_GLB_IACT = 1;
		parameter NUM_GLB_PSUM = 1;
		parameter NUM_GLB_WGHT = 1;
		
		parameter ADDR_BITWIDTH_GLB = 10;
		parameter ADDR_BITWIDTH_SPAD = 9;
		
		parameter NUM_ROUTER_PSUM = 1;
		parameter NUM_ROUTER_IACT = 1;
		parameter NUM_ROUTER_WGHT = 1;
				
		parameter int kernel_size = 3;
		parameter int act_size = 5;
		
		parameter int X_dim = 3;
		parameter int Y_dim = 3;
		
		parameter W_READ_ADDR = 0; 
		parameter A_READ_ADDR = 0;
		
		parameter W_LOAD_ADDR = 0;  
		parameter A_LOAD_ADDR = 0;
		
		parameter PSUM_READ_ADDR = 0;
		parameter PSUM_LOAD_ADDR = 0;

		
		// Logic
		logic clk;
		logic reset;
		
		//PE Cluster Interface
		logic start;
		logic load_done;
		
		logic load_en_wght;
		logic load_en_act;
		
        logic [DATA_WIDTH-1:0] pe_out[X_dim-1:0];
		logic compute_done;
		
		
		
		//GLB Cluster Interface

		logic write_en_iact;
		logic write_en_wght;
		
		logic [DATA_WIDTH-1:0] w_data_iact;
		logic [ADDR_WIDTH-1:0] w_addr_iact;
		
		logic [DATA_WIDTH-1:0] w_data_wght;
		logic [ADDR_WIDTH-1:0] w_addr_wght;
		
		logic [DATA_WIDTH-1:0] r_data_psum;
		logic [ADDR_WIDTH-1:0] r_addr_psum;
		
		logic [ADDR_WIDTH-1:0] w_addr_psum;
		
		logic read_req_iact;
		logic read_req_psum;
		logic read_req_wght;
		
		logic [ADDR_WIDTH-1:0] r_addr_iact;
		logic [ADDR_WIDTH-1:0] r_addr_wght;
		
		
		
		//WGHT Router Ports
		logic [3:0] router_mode_wght;
		
		//Interface with North
		//Source ports
		logic [DATA_WIDTH-1:0] north_data_i_wght;
		logic north_enable_i_wght;
		
		//Destination ports
		logic [DATA_WIDTH-1:0] north_data_o_wght;
		logic north_enable_o_wght;
		
		
		//Interface with South
		//Source ports
		logic [DATA_WIDTH-1:0] south_data_i_wght;
		logic south_enable_i_wght;
		
		//Destination ports
		logic [DATA_WIDTH-1:0] south_data_o_wght;
		logic south_enable_o_wght;
		
		
		//Interface with West
		//Source ports
//		logic [DATA_WIDTH-1:0] west_data_i_wght;
		logic west_enable_i_wght;
		
		//Destination ports
//		logic logic [DATA_WIDTH-1:0] west_data_o_wght;
		logic west_enable_o_wght;
		
		
		//Interface with East - Devices
		//Source ports
		logic [DATA_WIDTH-1:0] east_data_i_wght;
		logic east_enable_i_wght;
		
		//Destination ports
		logic [DATA_WIDTH-1:0] east_data_o_wght;
		logic east_enable_o_wght;
		
	//IACT Router Ports
		logic [3:0] router_mode_iact;
		
		//Interface with North
		//Source ports
		logic [DATA_WIDTH-1:0] north_data_i_iact;
		logic north_enable_i_iact;
		
		//Destination ports
		logic [DATA_WIDTH-1:0] north_data_o_iact;
		logic north_enable_o_iact;
		
		
		//Interface with South
		//Source ports
		logic [DATA_WIDTH-1:0] south_data_i_iact;
		logic south_enable_i_iact;
		
		//Destination ports
		logic [DATA_WIDTH-1:0] south_data_o_iact;
		logic south_enable_o_iact;
		
		
		//Interface with West
		//Source ports
//		logic [DATA_WIDTH-1:0] west_data_i_iact;
		logic west_enable_i_iact;
		
		//Destination ports
//		logic logic [DATA_WIDTH-1:0] west_data_o_iact;
		logic west_enable_o_iact;
		
		
		//Interface with East - Devices
		//Source ports
		logic [DATA_WIDTH-1:0] east_data_i_iact;
		logic east_enable_i_iact;
		
		//Destination ports
		logic [DATA_WIDTH-1:0] east_data_o_iact;
		logic east_enable_o_iact;
		
	
	//PSUM Router Ports
		logic [3:0] router_mode_psum;
		
		//Interface with North
		//Source ports
		logic [DATA_WIDTH-1:0] north_data_i_psum;
		logic north_enable_i_psum;
		
		//Destination ports
		logic [DATA_WIDTH-1:0] north_data_o_psum;
		logic north_enable_o_psum;
		
		
		//Interface with South
		//Source ports
		logic [DATA_WIDTH-1:0] south_data_i_psum;
		logic south_enable_i_psum;
		
		//Destination ports
		logic [DATA_WIDTH-1:0] south_data_o_psum;
		logic south_enable_o_psum;
		
		
		//Interface with West
		//Source ports
		logic [DATA_WIDTH-1:0] west_data_i_psum;
		logic west_enable_i_psum;
		
		//Destination ports
		logic [DATA_WIDTH-1:0] west_data_o_psum;
		logic west_enable_o_psum;
		
		//Interface with East - Devices
		//Source ports
		logic [DATA_WIDTH-1:0] east_data_i_psum;
		logic east_enable_i_psum;
		
		//Destination ports
		logic [DATA_WIDTH-1:0] east_data_o_psum;
		logic east_enable_o_psum;
		
		
		
	//Instantiation
	HMNoC_cluster_west 
		#(
			.DATA_BITWIDTH(DATA_BITWIDTH),
			.ADDR_BITWIDTH(ADDR_BITWIDTH),
			
			.DATA_WIDTH(DATA_WIDTH),
			.ADDR_WIDTH(ADDR_WIDTH),
			
			.NUM_GLB_IACT(NUM_GLB_IACT),
			.NUM_GLB_PSUM(NUM_GLB_PSUM),
			.NUM_GLB_WGHT(NUM_GLB_WGHT),

			.kernel_size(kernel_size),
			.act_size(act_size),
			
			.X_dim(X_dim),
			.Y_dim(Y_dim)
		)
	HMNoC_cluster_west_0 
		(
			.clk(clk),   //TestBench/Controller
			.reset(reset),  //TestBench/Controller
			
			//Signals for reading from GLB
			.read_req_iact(read_req_iact),
			.read_req_psum(read_req_psum), //Read by testbench/controller
			.read_req_wght(read_req_wght),
			
//			.r_data_iact(router_cluster_0.r_data_glb_iact),
			.r_data_psum(r_data_psum), //Read by testbench/controller
//			.r_data_wght(router_cluster_0.r_data_glb_wght),
			
			.r_addr_iact(r_addr_iact),
			.r_addr_psum(r_addr_psum), //testbench for reading final psums
			.r_addr_wght(r_addr_wght),

			//Signals for writing to GLB
			.w_addr_iact(w_addr_iact), //testbench for writing
			.w_addr_psum(w_addr_psum),
			.w_addr_wght(w_addr_wght), //testbench for writing

			.w_data_iact(w_data_iact), //testbench for writing
//			.w_data_psum(router_cluster_0.w_data_glb_psum),
			.w_data_wght(w_data_wght), //testbench for writing

			.write_en_iact(write_en_iact), //testbench for writing
//			.write_en_psum(router_cluster_0.write_en_glb_psum),
			.write_en_wght(write_en_wght), //testbench for writing
				
				
	
			//Ports for WGHT router
			.router_mode_wght(router_mode_wght), //TB*
			
			//Interface with North
			//Source ports
			.north_data_i_wght(north_data_i_wght),
			.north_enable_i_wght(north_enable_i_wght),
			
			//Destination ports
			.north_data_o_wght(north_data_o_wght),
			.north_enable_o_wght(north_enable_o_wght),
			
			
			//Interface with South
			//Source ports
			.south_data_i_wght(south_data_i_wght),
			.south_enable_i_wght(south_enable_i_wght),
			
			//Destination ports
			.south_data_o_wght(south_data_o_wght),
			.south_enable_o_wght(south_enable_o_wght),
			
			
			//Interface with West
			//Source ports
//			.west_data_i_wght(GLB_cluster_0.r_data_wght), //GLB_cluster
			.west_enable_i_wght(west_enable_i_wght),
			
			//Destination ports
//			.west_data_o_wght(pe_cluster_0.filt_in),  //PE_cluster
			.west_enable_o_wght(west_enable_o_wght),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_wght(east_data_i_wght),
			.east_enable_i_wght(east_enable_i_wght),
	        
			//Destination ports
	        .east_data_o_wght(east_data_o_wght),
            .east_enable_o_wght(east_enable_o_wght),
			
		////////////////////////////////////////////
			
		//Ports for IACT router
			.router_mode_iact(router_mode_iact),  //TB*
			
			//Interface with North
			//Source ports
			.north_data_i_iact(north_data_i_iact),
			.north_enable_i_iact(north_enable_i_iact),
			
			//Destination ports
			.north_data_o_iact(north_data_o_iact),
			.north_enable_o_iact(north_enable_o_iact),
			
			
			//Interface with South
			//Source ports
			.south_data_i_iact(south_data_i_iact),
			.south_enable_i_iact(south_enable_i_iact),
			
			//Destination ports
			.south_data_o_iact(south_data_o_iact),
			.south_enable_o_iact(south_enable_o_iact),
			
			
			//Interface with West
			//Source ports
//			.west_data_i_iact(GLB_cluster_0.r_data_iact),   //GLB_cluster
			.west_enable_i_iact(west_enable_i_iact),
			
			//Destination ports
//			.west_data_o_iact(pe_cluster_0.act_in),  //PE_cluster
			.west_enable_o_iact(west_enable_o_iact),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_iact(east_data_i_iact),
			.east_enable_i_iact(east_enable_i_iact),
	        
			//Destination ports
	        .east_data_o_iact(east_data_o_iact),
            .east_enable_o_iact(east_enable_o_iact),
			
			
		////////////////////////////////////////////
			
		//Ports for PSUM router
			.router_mode_psum(router_mode_psum),
			
			//Interface with North
			//Source ports
			.north_data_i_psum(north_data_i_psum),
			.north_enable_i_psum(north_enable_i_psum),
			
			//Destination ports
			.north_data_o_psum(north_data_o_psum),
			.north_enable_o_psum(north_enable_o_psum),
			
			
			//Interface with South
			//Source ports
			.south_data_i_psum(south_data_i_psum),
			.south_enable_i_psum(south_enable_i_psum),
			
			//Destination ports
			.south_data_o_psum(south_data_o_psum),
			.south_enable_o_psum(south_enable_o_psum),
			
			
			//Interface with West
			//Source ports
			.west_data_i_psum(west_data_i_psum), //PE_cluster
			.west_enable_i_psum(west_enable_i_psum),
			
			//Destination ports
//			.west_data_o_psum(GLB_cluster_0.w_data_psum), //GLB_cluster
//			.west_enable_o_psum(GLB_cluster_0.write_en_psum), //GLB_cluster
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_psum(east_data_i_psum),
			.east_enable_i_psum(east_enable_i_psum),
	        
			//Destination ports
	        .east_data_o_psum(east_data_o_psum),
            .east_enable_o_psum(east_enable_o_psum),
			
			
			
			//PE Cluster
			.load_en_wght(load_en_wght),
			.load_en_act(load_en_act),
			.start(start),
			.pe_out(pe_out),
			.compute_done(compute_done),
			.load_done(load_done)
		);
		
	
		//Logic for Direction
	enum logic [3:0] {ALL=0, NORTH=1, SOUTH=2, WEST=3, EAST=4,
						EASTNORTH=5, EASTSOUTH=6, EASTWEST=7,
						WESTNORTH=8, WESTSOUTH=9, WESTEAST=10} direction;
						
	integer clk_prd = 10;
	
	always begin
		clk = 0; #(clk_prd/2);
		clk = 1; #(clk_prd/2);
		//0.1GHz
	end
	
	integer kernel_1,act_1,psum_1;
	integer w_addr = 0;
	int args;
	
	logic [DATA_WIDTH-1:0] cluster_out_1[0:8];
	
	initial begin
		reset = 1; #30;
		reset = 0;
		start = 0;
		
		//Write weights to weight glb
/* 		write_en_wght = 1;
		kernel_1 = $fopen("kernel_3x3.txt","r");		
		while(!$feof(kernel_1))begin
			w_addr_wght = w_addr;
			args = $fscanf(kernel_1,"%d\n",w_data_wght);
			$display("Writing value %0d to address %0d in weight glb",w_data_wght,w_addr);
			w_addr++;
			#(clk_prd);
		end
		write_en_wght = 0;
		$fclose(kernel_1); 
		
		
		//Write activations to weight glb
		write_en_iact = 1;
		w_addr = 0;
		act_1 = $fopen("act_5x5.txt","r");
		while(!$feof(act_1))begin
			w_addr_iact = w_addr;
			args = $fscanf(act_1,"%d\n",w_data_iact);
			$display("Writing value %0d to address %0d in iact glb",w_data_iact,w_addr);
			w_addr++;
			#(clk_prd);
		end
		write_en_iact = 0;
		$fclose(act_1);  */
		
		//Write weights to weight glb
 		write_en_wght = 1;		
		for(int i=0; i<kernel_size**2;i++) begin
			w_data_wght = 1;
			w_addr_wght = i;
			#(clk_prd);
		end
		write_en_wght = 0;
	
		//Write activations to weight glb
		write_en_iact = 1;
		for(int i=0; i<act_size**2;i++) begin
			w_data_iact = i+1;
			w_addr_iact = i;
			#(clk_prd);
		end
		write_en_iact = 0;

		
		
		#(clk_prd);
	
//		assign west_data_o_wght = router_cluster_0.west_data_o_wght;
		
		$display("\n\nLoading Begins: Weights.....\n\n");
			read_req_wght = 1;
			r_addr_wght	= 0;
			#(clk_prd);
			
			west_enable_i_wght = 1;
			router_mode_wght = WEST;
			
			
		//Filter
			load_en_wght = 1;
			for(int i=1; i<=kernel_size**2; i++) begin
				r_addr_wght = i; #(clk_prd);
//				$display("Weight Read: %d",west_data_o_wght);
				load_en_wght = 0;
			end
		
		read_req_wght = 0;
		west_enable_i_wght = 0;
		
		#(clk_prd);
		
		
		$display("\n\nLoading Begins: Activations.....\n\n");
			
			read_req_iact = 1;
			r_addr_iact	= 0;
			#(clk_prd);
			
			west_enable_i_iact = 1;
			router_mode_iact = WEST;
			load_en_act = 1;
			
		//Filter
			for(int i=1; i<=act_size**2; i++) begin
				r_addr_iact = i; #(clk_prd);
				load_en_act = 0;
			end
		
		read_req_iact = 0;	
		west_enable_i_iact = 0;
		
		#(clk_prd);
	
	
	end	

endmodule


================================================
FILE: testbench/MAC_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 11/27/2019 10:01:40 AM
// Design Name: 
// Module Name: MAC_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

module MAC_tb(

    );
	
	parameter IN_BITWIDTH = 16;
	parameter OUT_BITWIDTH = 2*IN_BITWIDTH;
	
	logic [IN_BITWIDTH-1 : 0] a_in; 
	logic [IN_BITWIDTH-1 : 0] w_in;
	logic [IN_BITWIDTH-1 : 0] sum_in;
	logic [OUT_BITWIDTH-1 : 0] out;
	
	MAC mac_0 ( .a_in(a_in), .w_in(w_in), .sum_in(sum_in), .out(out) );
	
	
	initial begin
	
		a_in = 0;
		w_in = 0;
		sum_in = 0;
		
		#50
		
		a_in = 15;
		w_in = 0;
		sum_in = 0;
		
		#50
		
		a_in = 1;
		w_in = 61000;
		sum_in = 0;
		
		#50
	
		a_in = 1;
		w_in = 61000;
		sum_in = 4000;
		
				#50
	
		a_in = 1;
		w_in = 61000;
		sum_in = 4000;
		
				#50
	
		a_in = 500;
		w_in = 50;
		sum_in = 17000;
		
				#50
	
		a_in = 2;
		w_in = 12000;
		sum_in = 4000;
		
						#50
	
		a_in = 60000;
		w_in = 12000;
		sum_in = 15000;
	
		
	end
	
endmodule


================================================
FILE: testbench/PE_cluster_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 11/29/2019 09:56:14 PM
// Design Name: 
// Module Name: PE_cluster_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module PE_cluster_tb();

	parameter DATA_WIDTH = 16;
    parameter ADDR_WIDTH = 9;
    
    parameter int X_dim = 3;
    parameter int Y_dim = 3;
    
    parameter int kernel_size = 3;
    parameter int act_size = 5;
    
    parameter W_READ_ADDR = 0;  
    parameter A_READ_ADDR = 100;
    
    parameter W_LOAD_ADDR = 0;  
    parameter A_LOAD_ADDR = 100;
    
    parameter PSUM_ADDR = 500;
	
    logic clk, reset;
    logic [DATA_WIDTH-1:0] act_in;
    logic [DATA_WIDTH-1:0] filt_in;
//    logic load_en;
	logic start;
	logic load_en_wght, load_en_act;

    logic [DATA_WIDTH-1:0] pe_out[X_dim-1:0];
  
	logic compute_done;
	
//	logic [DATA_WIDTH-1:0] psum_out[0 : X_dim*Y_dim-1];
	
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_0
    			(
					.clk(clk),
				    .reset(reset),
				    .act_in(act_in),
				    .filt_in(filt_in),
//				    .load_en(load_en),
					.load_en_wght(load_en_wght),
					.load_en_act(load_en_act),
					.start(start),
                    .pe_out(pe_out),
					.compute_done(compute_done),
					.load_done(load_done)
					
		//extra
//					.psum_out(psum_out)
    			);
				
				
	always begin
		clk = 0; #10;
		clk = 1; #10;
	end

	
		initial begin
		reset = 1; #30;
		reset = 0;
		start = 0;
		
	$display("\n\nLoading Begins: Weights.....\n\n");
		load_en_wght = 1;
		
	//Filter
		for(int i=1; i<=kernel_size**2; i++) begin
			filt_in = i; #20;
			load_en_wght = 0;
		end
		
	#50
	
	$display("\n\nLoading Begins: Activations.....\n\n");
		load_en_act = 1;
		
	//Activations
		for(int i=1; i<=act_size**2; i++) begin
			act_in = i; #20;
			load_en_act = 0;
		end
		
//		load_en = 0;
		#20
		
		start = 1; #25; 
		$display("\n\nReading & Computing Begins.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		#40
		$display("\n\nFinal PSUM of Iteration 1");
 		for(int i=0; i<X_dim; i++) begin
			$display("\npsum from column %d is:%d",i+1,pe_out[i]);
		end
		
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 2.....\n\n");
		start = 0;
		
				wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 2:");
 		for(int i=0; i<X_dim; i++) begin
			$display("\npsum from column %d is:%d",i+1,pe_out[i]);
		end
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 3.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 3:");
 		for(int i=0; i<X_dim; i++) begin
			$display("\npsum from column %d is:%d",i+1,pe_out[i]);
		end
		
		
/* 		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 4.....\n\n");
		start = 0;
		
				wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 4:");
 		for(int i=0; i<X_dim; i++) begin
			$display("\npsum from column %d is:%d",i+1,pe_out[i]);
		end
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 5.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 5:");
 		for(int i=0; i<X_dim; i++) begin
			$display("\npsum from column %d is:%d",i+1,pe_out[i]);
		end */

		
		reset = 1; #30;
		reset = 0;
		start = 0;
		
	$display("\n\nLoading Begins.....\n\n");
		load_en_wght = 1;
		
	//Filter
		for(int i=1; i<=kernel_size**2; i++) begin
			filt_in = i; #20;
			load_en_wght = 0;
		end

	$display("\n\nLoading Begins.....\n\n");
		load_en_act = 1;
		
	//Activations
		for(int i=1; i<=act_size**2; i++) begin
			act_in = i; #20;
			load_en_act = 0;
		end
		
//		load_en = 0;
//		#20
		
		start = 1; #40; 
		$display("\n\nReading & Computing Begins.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		#40
		$display("\n\nFinal PSUM of Iteration 1");
 		for(int i=0; i<X_dim; i++) begin
			$display("\npsum from column %d is:%d",i+1,pe_out[i]);
		end
		
		
		
	end
				
				
endmodule

================================================
FILE: testbench/PE_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 11/28/2019 02:02:47 AM
// Design Name: 
// Module Name: PE_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module PE_tb();

	parameter DATA_WIDTH = 16;
	parameter ADDR_WIDTH = 9;
	
	parameter int kernel_size = 3;
	parameter int act_size = 5;
	
	//KEEP READ AND WRITE ADDRESSES SAME for proper working of RS-PE 
	//Addresses to READ weights and activations from SPad
	parameter W_READ_ADDR = 0; 
	parameter A_READ_ADDR = 100;
	
	//Addresses to WRITE weights and activations in SPad
	parameter W_LOAD_ADDR = 0;
	parameter A_LOAD_ADDR = 100;
	
	parameter PSUM_ADDR = 500;
	

			 
	logic clk, reset;
	logic [DATA_WIDTH-1:0] act_in, filt_in, pe_out;
	
//	logic load_en, start;
	logic load_en_wght, load_en_act, start;
	
	PE  #( 	.kernel_size(kernel_size),
			.act_size(act_size),
			.W_READ_ADDR(W_READ_ADDR),
			.A_READ_ADDR(A_READ_ADDR),
			.W_LOAD_ADDR(W_LOAD_ADDR),
			.A_LOAD_ADDR(A_LOAD_ADDR)
		   )
	pe_0		   
		( .clk(clk), .reset(reset), 
		  .act_in(act_in), .filt_in(filt_in),
		  .pe_out(pe_out),  //out
		  .compute_done(compute_done), //out
//		  .load_en(load_en),
		  .load_en_wght(load_en_wght),
		  .load_en_act(load_en_act),
		  .start(start)
		);
			  
	always begin
		clk = 0; #10;
		clk = 1; #10;
	end
	
	initial begin
		reset = 1; #30;
		reset = 0;
		start = 0;
		
	$display("\n\nLoading Begins: Weights.....\n\n");
		load_en_wght = 1;
/*	
	//Filter
	//1st row
		filt_in = 1; 
		#20; load_en = 0;
		filt_in = 1; 
		#20;
		filt_in = 1; 
		#20;
	
	//2nd row	
		filt_in = 1; 
		#20;
		filt_in = 1; 
		#20;
		filt_in = 1; 
		#20;
		
	//3rd row
		filt_in = 1; 
		#20;
		filt_in = 1; 
		#20;
		filt_in = 1; 
		#20;
*/
		
	//Filter
		for(int i=1; i<=kernel_size**2; i++) begin
			filt_in = i; #20;
			load_en_wght = 0;
		end
		
		#50;
		
		
		$display("\n\nLoading Begins: Activations.....\n\n");
		load_en_act = 1;
	//Activations
		for(int i=1; i<=act_size**2; i++) begin
			act_in = i; #20;
			load_en_act = 0;
		end
		
//		load_en = 0;
		#20
		
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 1.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 1:%d\n\n",pe_out);
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 2.....\n\n");
		start = 0;
		
				wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 2:%d\n\n",pe_out);
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 3.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 3:%d\n\n",pe_out);
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 4.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 4:%d\n\n",pe_out);
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 5.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 5:%d\n\n",pe_out);
	end
	
endmodule


================================================
FILE: testbench/SPad_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 11/27/2019 08:46:43 PM
// Design Name: 
// Module Name: SPad_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module SPad_tb();
	
	parameter ADDR_BITWIDTH = 9;
	parameter DATA_BITWIDTH = 16;
	
	logic clk, reset, read_req, write_en;
	logic [ADDR_BITWIDTH-1 : 0] r_addr, w_addr;
	logic [DATA_BITWIDTH-1 : 0] w_data;
	logic [DATA_BITWIDTH-1 : 0] r_data;
	
	//
	SPad SPad_0 ( .clk(clk), .reset(reset), .read_req(read_req),
				  .write_en(write_en), .r_addr(r_addr), .w_data(w_data),
				  .r_data(r_data), .w_addr(w_addr)
				);
	
	always begin
		clk = 0; #10;
		clk = 1; #10;
	end
	
	initial begin
		reset = 1; #20
		reset = 0;
		//$display("Data at location 0 is %d", mem[0]);
		
		write_en = 1;
		w_addr = 0;
		w_data = 25;
		#40
		
		write_en = 0;
		read_req = 1;
		r_addr = 0;
		#40
		$display("Data at location 0 is %d", r_data);
		
		write_en = 1;
		for (int i = 1; i<8; i+=2) begin
			w_addr = i;
			w_data = i*2 + 10;
			#40;
		end
		write_en = 0;
		
		for (int i = 1; i<8; i+=2) begin
			r_addr = i;
			#40
			$display("Data at location %d is %d", i, r_data);
		end
		
	end
	
	
endmodule


================================================
FILE: testbench/act_5x5.txt
================================================
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

================================================
FILE: testbench/act_7x7.txt
================================================
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
0
0
0
0
0


================================================
FILE: testbench/adder_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 11/27/2019 07:39:19 AM
// Design Name: 
// Module Name: adder_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

module adder_tb();

	logic A_in, B_in, C_in;
	logic HA_S_out,HA_C_out;
	logic FA_S_out,FA_C_out;
	
	HA HA_0 ( .A_in(A_in), .B_in(B_in), .C_out(HA_C_out), .S_out(HA_S_out) );
	
	FA FA_0 ( .A_in(A_in), .B_in(B_in), .C_in(C_in), .C_out(FA_C_out), .S_out(FA_S_out) );
	
	
	initial begin
		A_in = 0;
		B_in = 0;
		C_in = 0;
		
		#50
		
		A_in = 0;
		B_in = 1;
		C_in = 0;
		
		#50
		
		A_in = 1;
		B_in = 0;
		C_in = 0;
		
		#50
		
		A_in = 1;
		B_in = 1;
		C_in = 0;
		
		#50
		
		A_in = 0;
		B_in = 0;
		C_in = 1;
		
		#50
		
		A_in = 0;
		B_in = 1;
		C_in = 1;
		
		#50
		
		A_in = 1;
		B_in = 0;
		C_in = 1;
		
		#50
		
		A_in = 1;
		B_in = 1;
		C_in = 1;
	end
	
endmodule


================================================
FILE: testbench/glb_iact_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/01/2019 01:05:33 PM
// Design Name: 
// Module Name: glb_iact_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module glb_iact_tb();
	
	parameter ADDR_BITWIDTH = 10;
	parameter DATA_BITWIDTH = 16;
	
	logic clk, reset, read_req, write_en;
	logic [ADDR_BITWIDTH-1 : 0] r_addr, w_addr;
	logic [DATA_BITWIDTH-1 : 0] w_data;
	logic [DATA_BITWIDTH-1 : 0] r_data;
	
	//
	glb_iact glb_iact_0 ( .clk(clk), .reset(reset), .read_req(read_req),
				  .write_en(write_en), .r_addr(r_addr), .w_data(w_data),
				  .r_data(r_data), .w_addr(w_addr)
				);
	
	always begin
		clk = 0; #10;
		clk = 1; #10;
	end
	
	initial begin
		reset = 1; #20
		reset = 0;
		//$display("Data at location 0 is %d", mem[0]);
		
		write_en = 1;
		w_addr = 0;
		w_data = 25;
		#40
		
		write_en = 0;
		read_req = 1;
		r_addr = 0;
		#40
		$display("Data at location 0 is %d", r_data);
		
		write_en = 1;
		for (int i = 1; i<8; i+=2) begin
			w_addr = i;
			w_data = i*2 + 10;
			#40;
		end
		write_en = 0;
		
		for (int i = 1; i<8; i+=2) begin
			r_addr = i;
			#40
			$display("Data at location %d is %d", i, r_data);
		end
		
	end
	
endmodule


================================================
FILE: testbench/kernel_3x3.txt
================================================
1
2
3
4
5
6
7
8
9

================================================
FILE: testbench/kernel_5x5.txt
================================================
1
2
3
4
5
6
7
8
9
1
1
1
1
1
2
2
2
2
2
3
3
3
3
3
0


================================================
FILE: testbench/phase_1/GLB_cluster_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/01/2019 01:54:30 PM
// Design Name: 
// Module Name: GLB_cluster_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module GLB_cluster_tb();

    parameter DATA_BITWIDTH = 16;
	parameter ADDR_BITWIDTH = 10;
    parameter NUM_GLB_IACT = 1;
    parameter NUM_GLB_PSUM = 1;
	parameter NUM_GLB_WGHT = 1;
	
    logic clk;
    logic reset;

    logic read_req_iact[NUM_GLB_IACT-1:0];
	logic read_req_psum[NUM_GLB_PSUM-1:0];
	logic read_req_wght[NUM_GLB_WGHT-1:0];
	
    logic write_en_iact[NUM_GLB_IACT-1:0];
	logic write_en_psum[NUM_GLB_PSUM-1:0];
	logic write_en_wght[NUM_GLB_WGHT-1:0];
	
    logic [ADDR_BITWIDTH-1 : 0] r_addr_iact[NUM_GLB_IACT-1:0];
    logic [ADDR_BITWIDTH-1 : 0] r_addr_psum[NUM_GLB_PSUM-1:0];
	logic [ADDR_BITWIDTH-1 : 0] r_addr_wght[NUM_GLB_WGHT-1:0];
	
    logic [ADDR_BITWIDTH-1 : 0] w_addr_iact[NUM_GLB_IACT-1:0];
    logic [ADDR_BITWIDTH-1 : 0] w_addr_psum[NUM_GLB_PSUM-1:0];
	logic [ADDR_BITWIDTH-1 : 0] w_addr_wght[NUM_GLB_WGHT-1:0];
	
    logic [DATA_BITWIDTH-1 : 0] w_data_iact[NUM_GLB_IACT-1:0];
    logic [DATA_BITWIDTH-1 : 0] w_data_psum[NUM_GLB_PSUM-1:0];
	logic [DATA_BITWIDTH-1 : 0] w_data_wght[NUM_GLB_WGHT-1:0];
	
    logic [DATA_BITWIDTH-1 : 0] r_data_iact[NUM_GLB_IACT-1:0];
    logic [DATA_BITWIDTH-1 : 0] r_data_psum[NUM_GLB_PSUM-1:0];
    logic [DATA_BITWIDTH-1 : 0] r_data_wght[NUM_GLB_WGHT-1:0];

	GLB_cluster 
			#(	.DATA_BITWIDTH(DATA_BITWIDTH),
				.ADDR_BITWIDTH(ADDR_BITWIDTH),
				.NUM_GLB_IACT(NUM_GLB_IACT),
				.NUM_GLB_PSUM(NUM_GLB_PSUM),
				.NUM_GLB_WGHT(NUM_GLB_WGHT)
			)
	GLB_cluster_0
			(
				.clk(clk), 
				.reset(reset),
				
				.read_req_iact(read_req_iact),
				.read_req_psum(read_req_psum),
				.read_req_wght(read_req_wght),
				
				.write_en_iact(write_en_iact),
				.write_en_psum(write_en_psum),
				.write_en_wght(write_en_wght),
				
				.r_addr_iact(r_addr_iact),
			    .r_addr_psum(r_addr_psum),
				.r_addr_wght(r_addr_wght),

			    .w_addr_iact(w_addr_iact),
			    .w_addr_psum(w_addr_psum),
				.w_addr_wght(w_addr_wght),

			    .w_data_iact(w_data_iact),
			    .w_data_psum(w_data_psum),
				.w_data_wght(w_data_wght),

			    .r_data_iact(r_data_iact),
			    .r_data_psum(r_data_psum),
				.r_data_wght(r_data_wght)
			);
			
			
	always begin
		clk = 0; #10;
		clk = 1; #10;
	end

	
	initial begin
		reset = 1; #30;
		reset = 0;
	
		write_en_iact[0] = 1;
		write_en_psum[0] = 1;
		write_en_wght[0] = 1;
		
		for(int i=0; i<16; i++) begin
			w_addr_iact[0] = i;
			w_data_iact[0] = i*2;

			w_addr_psum[0] = i;
			w_data_psum[0] = i;
			
			w_addr_wght[0] = i;
			w_data_wght[0] = i*3;
			
			#20;
		end
		
		write_en_iact[0] = 0;
		write_en_psum[0] = 0;
		write_en_wght[0] = 0;
		
		for(int i=0; i<2; i++) begin
			w_addr_iact[0] = i;
			w_data_iact[0] = i*200;

			w_addr_psum[0] = i;
			w_data_psum[0] = i*200;
			
			w_addr_wght[0] = i;
			w_data_wght[0] = i*200;			
			
			#20;
		end
	
	#100;
	
		read_req_iact[0] = 1;
		read_req_psum[0] = 1;
		read_req_wght[0] = 1;
		
		for(int i=0; i<16; i++  ) begin
			r_addr_iact[0] = i;

			r_addr_psum[0] = i;
			
			r_addr_wght[0] = i;
			#20;
		end
	
		read_req_iact[0] = 0;
		read_req_psum[0] = 0;
		read_req_wght[0] = 0;
		
		for(int i=0; i<2; i++) begin
			r_addr_iact[0] = i;

			r_addr_psum[0] = i;
			
			r_addr_wght[0] = i;
			
			#20;
		end
		
	end
	 
endmodule

================================================
FILE: testbench/phase_1/HMNoC_1_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/01/2019 04:37:46 PM
// Design Name: 
// Module Name: HMNoC_1_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module HMNoC_1_tb();

	parameter DATA_BITWIDTH = 16;
	parameter ADDR_BITWIDTH = 10;
	
	// GLB Cluster parameters. This TestBench uses only 1 of each
    parameter NUM_GLB_IACT = 1;
    parameter NUM_GLB_PSUM = 1;
	parameter NUM_GLB_WGHT = 1;
	
	
    logic clk;
    logic reset;

	//logic for GLB cluster
    logic read_req_iact[NUM_GLB_IACT-1:0];
	logic read_req_psum[NUM_GLB_PSUM-1:0];
	logic read_req_wght[NUM_GLB_WGHT-1:0];
	
    logic write_en_iact[NUM_GLB_IACT-1:0];
	logic write_en_psum[NUM_GLB_PSUM-1:0];
	logic write_en_wght[NUM_GLB_WGHT-1:0];
	
    logic [ADDR_BITWIDTH-1 : 0] r_addr_iact[NUM_GLB_IACT-1:0];
    logic [ADDR_BITWIDTH-1 : 0] r_addr_psum[NUM_GLB_PSUM-1:0];
	logic [ADDR_BITWIDTH-1 : 0] r_addr_wght[NUM_GLB_WGHT-1:0];
	
    logic [ADDR_BITWIDTH-1 : 0] w_addr_iact[NUM_GLB_IACT-1:0];
    logic [ADDR_BITWIDTH-1 : 0] w_addr_psum[NUM_GLB_PSUM-1:0];
	logic [ADDR_BITWIDTH-1 : 0] w_addr_wght[NUM_GLB_WGHT-1:0];
	
    logic [DATA_BITWIDTH-1 : 0] w_data_iact[NUM_GLB_IACT-1:0];
    logic [DATA_BITWIDTH-1 : 0] w_data_psum[NUM_GLB_PSUM-1:0];
	logic [DATA_BITWIDTH-1 : 0] w_data_wght[NUM_GLB_WGHT-1:0];
	
    logic [DATA_BITWIDTH-1 : 0] r_data_iact[NUM_GLB_IACT-1:0];
    logic [DATA_BITWIDTH-1 : 0] r_data_psum[NUM_GLB_PSUM-1:0];
    logic [DATA_BITWIDTH-1 : 0] r_data_wght[NUM_GLB_WGHT-1:0];

	
	//GLB cluster initialization
	GLB_cluster 
			#(	.DATA_BITWIDTH(DATA_BITWIDTH),
				.ADDR_BITWIDTH(ADDR_BITWIDTH),
				.NUM_GLB_IACT(NUM_GLB_IACT),
				.NUM_GLB_PSUM(NUM_GLB_PSUM),
				.NUM_GLB_WGHT(NUM_GLB_WGHT)
			)
	GLB_cluster_0
			(
				.clk(clk), 
				.reset(reset),
				
				.read_req_iact(read_req_iact),
				.read_req_psum(read_req_psum),
				.read_req_wght(read_req_wght),
				
				.write_en_iact(write_en_iact),
				.write_en_psum(write_en_psum),
				.write_en_wght(write_en_wght),
				
				.r_addr_iact(r_addr_iact),
			    .r_addr_psum(r_addr_psum),
				.r_addr_wght(r_addr_wght),

			    .w_addr_iact(w_addr_iact),
			    .w_addr_psum(w_addr_psum),
				.w_addr_wght(w_addr_wght),

			    .w_data_iact(w_data_iact),
			    .w_data_psum(w_data_psum),
				.w_data_wght(w_data_wght),

			    .r_data_iact(r_data_iact),
			    .r_data_psum(r_data_psum),
				.r_data_wght(r_data_wght)
			);

			
	// Router Instantiation
			
	integer clk_prd = 10;
	
	always begin
		clk = 0; #(clk_prd/2);
		clk = 1; #(clk_prd/2);
		//0.1GHz
	end
	
	integer kernel_1,act_1;
	integer w_addr = 0;
	int args;
	
	initial begin
		reset = 1; #30;
		reset = 0;
		

		//Write weights to weight glb
		write_en_wght[0] = 1;
		kernel_1 = $fopen("kernel_3x3.txt","r");		
		while(!$feof(kernel_1))begin
			w_addr_wght[0] = w_addr;
			args = $fscanf(kernel_1,"%d\n",w_data_wght[0]);
			$display("Writing value %0d to address %0d in weight glb",w_data_wght[0],w_addr);
			w_addr++;
			#(clk_prd);
		end
		write_en_wght[0] = 0;
		$fclose(kernel_1); 
		
		
		//Write activations to weight glb
		write_en_iact[0] = 1;
		w_addr = 0;
		act_1 = $fopen("act_5x5.txt","r");
		while(!$feof(act_1))begin
			w_addr_iact[0] = w_addr;
			args = $fscanf(act_1,"%d\n",w_data_iact[0]);
			$display("Writing value %0d to address %0d in iact glb",w_data_iact[0],w_addr);
			w_addr++;
			#(clk_prd);
		end
		write_en_iact[0] = 0;
		$fclose(act_1); 
		
		
//		write_en_wght[0] = 0;
	
	end
	
endmodule


================================================
FILE: testbench/phase_1/PE_cluster_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 11/29/2019 09:56:14 PM
// Design Name: 
// Module Name: PE_cluster_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module PE_cluster_tb();

	parameter DATA_WIDTH = 16;
    parameter ADDR_WIDTH = 9;
    
    parameter int X_dim = 3;
    parameter int Y_dim = 3;
    
    parameter int kernel_size = 3;
    parameter int act_size = 5;
    
    parameter W_READ_ADDR = 0;  
    parameter A_READ_ADDR = 100;
    
    parameter W_LOAD_ADDR = 0;  
    parameter A_LOAD_ADDR = 100;
    
    parameter PSUM_ADDR = 500;
	
    logic clk, reset;
    logic [DATA_WIDTH-1:0] act_in;
    logic [DATA_WIDTH-1:0] filt_in;
//    logic load_en;
	logic start;
	logic load_en_wght, load_en_act;

    logic [DATA_WIDTH-1:0] pe_out[X_dim-1:0];
  
	logic compute_done;
	
//	logic [DATA_WIDTH-1:0] psum_out[0 : X_dim*Y_dim-1];
	
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_0
    			(
					.clk(clk),
				    .reset(reset),
				    .act_in(act_in),
				    .filt_in(filt_in),
//				    .load_en(load_en),
					.load_en_wght(load_en_wght),
					.load_en_act(load_en_act),
					.start(start),
                    .pe_out(pe_out),
					.compute_done(compute_done),
					.load_done(load_done)
					
		//extra
//					.psum_out(psum_out)
    			);
				
				
	always begin
		clk = 0; #10;
		clk = 1; #10;
	end

	
		initial begin
		reset = 1; #30;
		reset = 0;
		start = 0;
		
	$display("\n\nLoading Begins: Weights.....\n\n");
		load_en_wght = 1;
		
	//Filter
		for(int i=1; i<=kernel_size**2; i++) begin
			filt_in = i; #20;
			load_en_wght = 0;
		end
		
	#50
	
	$display("\n\nLoading Begins: Activations.....\n\n");
		load_en_act = 1;
		
	//Activations
		for(int i=1; i<=act_size**2; i++) begin
			act_in = i; #20;
			load_en_act = 0;
		end
		
//		load_en = 0;
		#20
		
		start = 1; #25; 
		$display("\n\nReading & Computing Begins.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		#40
		$display("\n\nFinal PSUM of Iteration 1");
 		for(int i=0; i<X_dim; i++) begin
			$display("\npsum from column %d is:%d",i+1,pe_out[i]);
		end
		
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 2.....\n\n");
		start = 0;
		
				wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 2:");
 		for(int i=0; i<X_dim; i++) begin
			$display("\npsum from column %d is:%d",i+1,pe_out[i]);
		end
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 3.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 3:");
 		for(int i=0; i<X_dim; i++) begin
			$display("\npsum from column %d is:%d",i+1,pe_out[i]);
		end
		
		
/* 		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 4.....\n\n");
		start = 0;
		
				wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 4:");
 		for(int i=0; i<X_dim; i++) begin
			$display("\npsum from column %d is:%d",i+1,pe_out[i]);
		end
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 5.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 5:");
 		for(int i=0; i<X_dim; i++) begin
			$display("\npsum from column %d is:%d",i+1,pe_out[i]);
		end */

		
		reset = 1; #30;
		reset = 0;
		start = 0;
		
	$display("\n\nLoading Begins.....\n\n");
		load_en_wght = 1;
		
	//Filter
		for(int i=1; i<=kernel_size**2; i++) begin
			filt_in = i; #20;
			load_en_wght = 0;
		end

	$display("\n\nLoading Begins.....\n\n");
		load_en_act = 1;
		
	//Activations
		for(int i=1; i<=act_size**2; i++) begin
			act_in = i; #20;
			load_en_act = 0;
		end
		
//		load_en = 0;
//		#20
		
		start = 1; #40; 
		$display("\n\nReading & Computing Begins.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		#40
		$display("\n\nFinal PSUM of Iteration 1");
 		for(int i=0; i<X_dim; i++) begin
			$display("\npsum from column %d is:%d",i+1,pe_out[i]);
		end
		
		
		
	end
				
				
endmodule

================================================
FILE: testbench/phase_1/PE_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 11/28/2019 02:02:47 AM
// Design Name: 
// Module Name: PE_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module PE_tb();

	parameter DATA_WIDTH = 16;
	parameter ADDR_WIDTH = 9;
	
	parameter int kernel_size = 3;
	parameter int act_size = 5;
	
	//KEEP READ AND WRITE ADDRESSES SAME for proper working of RS-PE 
	//Addresses to READ weights and activations from SPad
	parameter W_READ_ADDR = 0; 
	parameter A_READ_ADDR = 100;
	
	//Addresses to WRITE weights and activations in SPad
	parameter W_LOAD_ADDR = 0;
	parameter A_LOAD_ADDR = 100;
	
	parameter PSUM_ADDR = 500;
	

			 
	logic clk, reset;
	logic [DATA_WIDTH-1:0] act_in, filt_in, pe_out;
	
//	logic load_en, start;
	logic load_en_wght, load_en_act, start;
	
	PE  #( 	.kernel_size(kernel_size),
			.act_size(act_size),
			.W_READ_ADDR(W_READ_ADDR),
			.A_READ_ADDR(A_READ_ADDR),
			.W_LOAD_ADDR(W_LOAD_ADDR),
			.A_LOAD_ADDR(A_LOAD_ADDR)
		   )
	pe_0		   
		( .clk(clk), .reset(reset), 
		  .act_in(act_in), .filt_in(filt_in),
		  .pe_out(pe_out),  //out
		  .compute_done(compute_done), //out
//		  .load_en(load_en),
		  .load_en_wght(load_en_wght),
		  .load_en_act(load_en_act),
		  .start(start)
		);
			  
	always begin
		clk = 0; #10;
		clk = 1; #10;
	end
	
	initial begin
		reset = 1; #30;
		reset = 0;
		start = 0;
		
	$display("\n\nLoading Begins: Weights.....\n\n");
		load_en_wght = 1;
/*	
	//Filter
	//1st row
		filt_in = 1; 
		#20; load_en = 0;
		filt_in = 1; 
		#20;
		filt_in = 1; 
		#20;
	
	//2nd row	
		filt_in = 1; 
		#20;
		filt_in = 1; 
		#20;
		filt_in = 1; 
		#20;
		
	//3rd row
		filt_in = 1; 
		#20;
		filt_in = 1; 
		#20;
		filt_in = 1; 
		#20;
*/
		
	//Filter
		for(int i=1; i<=kernel_size**2; i++) begin
			filt_in = i; #20;
			load_en_wght = 0;
		end
		
		#50;
		
		
		$display("\n\nLoading Begins: Activations.....\n\n");
		load_en_act = 1;
	//Activations
		for(int i=1; i<=act_size**2; i++) begin
			act_in = i; #20;
			load_en_act = 0;
		end
		
//		load_en = 0;
		#20
		
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 1.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 1:%d\n\n",pe_out);
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 2.....\n\n");
		start = 0;
		
				wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 2:%d\n\n",pe_out);
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 3.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 3:%d\n\n",pe_out);
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 4.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 4:%d\n\n",pe_out);
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 5.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 5:%d\n\n",pe_out);
	end
	
endmodule


================================================
FILE: testbench/phase_1/router_cluster_5x5_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/13/2019 10:16:00 AM
// Design Name: 
// Module Name: router_cluster_5x5_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_cluster_5x5_tb();
	
	parameter DATA_BITWIDTH = 16;
	parameter ADDR_BITWIDTH = 10;
	
	parameter DATA_WIDTH = 16;
    parameter ADDR_WIDTH = 9;
	
	// GLB Cluster parameters. This TestBench uses only 1 of each
    parameter NUM_GLB_IACT = 1;
    parameter NUM_GLB_PSUM = 1;
	parameter NUM_GLB_WGHT = 1;
	
	parameter ADDR_BITWIDTH_GLB = 10;
	parameter ADDR_BITWIDTH_SPAD = 9;
	
	parameter NUM_ROUTER_PSUM = 1;
	parameter NUM_ROUTER_IACT = 1;
	parameter NUM_ROUTER_WGHT = 1;
			
	parameter int kernel_size = 5;
    parameter int act_size = 7;
	
	parameter int X_dim = 5;
    parameter int Y_dim = 5;
	
	//Used inside PEs
/* 	parameter W_READ_ADDR = 0;  
    parameter A_READ_ADDR_PE = 100;
    
    parameter W_LOAD_ADDR = 0;  
    parameter A_LOAD_ADDR_PE = 100;
    
    parameter PSUM_ADDR = 500; */
	
	parameter W_READ_ADDR = 0;  
    parameter A_READ_ADDR = 0;
    
    parameter W_LOAD_ADDR = 0;  
    parameter A_LOAD_ADDR = 0;
	
	parameter PSUM_READ_ADDR = 0;
	parameter PSUM_LOAD_ADDR = 0;
	
	int cycles, pe_cycles;
	
    logic clk;
    logic reset;

	//logic for GLB cluster
//    logic read_req_iact;
	logic read_req_psum;
//	logic read_req_wght;
	
    logic write_en_iact;
//	logic write_en_psum;
	logic write_en_wght;
	
			
	logic load_spad_ctrl_wght;
	logic load_spad_ctrl_iact;
		
//    logic [ADDR_BITWIDTH-1 : 0] r_addr_iact;
    logic [ADDR_BITWIDTH-1 : 0] r_addr_psum;
//	logic [ADDR_BITWIDTH-1 : 0] r_addr_wght;
	
    logic [ADDR_BITWIDTH-1 : 0] w_addr_iact;
    logic [ADDR_BITWIDTH-1 : 0] w_addr_psum;
	logic [ADDR_BITWIDTH-1 : 0] w_addr_wght;
	
    logic [DATA_BITWIDTH-1 : 0] w_data_iact;
    logic [DATA_BITWIDTH-1 : 0] w_data_psum;
	logic [DATA_BITWIDTH-1 : 0] w_data_wght;
	
//    logic [DATA_BITWIDTH-1 : 0] r_data_iact;
    logic [DATA_BITWIDTH-1 : 0] r_data_psum;
//   logic [DATA_BITWIDTH-1 : 0] r_data_wght;
	
	logic compute_done;
	
	
	//GLB cluster initialization
	GLB_cluster 
			#(	.DATA_BITWIDTH(DATA_BITWIDTH),
				.ADDR_BITWIDTH(ADDR_BITWIDTH),
				.NUM_GLB_IACT(NUM_GLB_IACT),
				.NUM_GLB_PSUM(NUM_GLB_PSUM),
				.NUM_GLB_WGHT(NUM_GLB_WGHT)
			)
	GLB_cluster_0
			(
				.clk(clk),   //TestBench/Controller
				.reset(reset),  //TestBench/Controller
				
				//Signals for reading from GLB
				.read_req_iact(router_cluster.read_req_glb_iact),
				.read_req_psum(read_req_psum), //Read by testbench/controller
				.read_req_wght(router_cluster_0.read_req_glb_wght),
				
			    .r_data_iact(router_cluster_0.r_data_glb_iact),
			    .r_data_psum(r_data_psum), //Read by testbench/controller
				.r_data_wght(router_cluster_0.r_data_glb_wght),
				
				.r_addr_iact(router_cluster_0.r_addr_glb_iact),
			    .r_addr_psum(r_addr_psum), //testbench for reading final psums
				.r_addr_wght(router_cluster_0.r_addr_glb_wght),

				
				//Signals for writing to GLB
			    .w_addr_iact(w_addr_iact), //testbench for writing
			    .w_addr_psum(router_cluster_0.w_addr_glb_psum),
				.w_addr_wght(w_addr_wght), //testbench for writing
 
			    .w_data_iact(w_data_iact), //testbench for writing
			    .w_data_psum(router_cluster_0.w_data_glb_psum),
				.w_data_wght(w_data_wght), //testbench for writing

				.write_en_iact(write_en_iact), //testbench for writing
				.write_en_psum(router_cluster_0.write_en_glb_psum),
				.write_en_wght(write_en_wght) //testbench for writing
			
			);

			
	logic [DATA_BITWIDTH-1 : 0] r_data_spad_psum[0:kernel_size-1];		
	
	//Router Cluster Instantiation
	router_cluster#(.DATA_BITWIDTH(DATA_BITWIDTH),
	                .ADDR_BITWIDTH_GLB(ADDR_BITWIDTH_GLB),
	                .ADDR_BITWIDTH_SPAD(ADDR_BITWIDTH_SPAD),

	                .kernel_size(kernel_size),
	                .act_size(act_size),

	                .NUM_ROUTER_PSUM(NUM_ROUTER_PSUM),
	                .NUM_ROUTER_IACT(NUM_ROUTER_IACT),
	                .NUM_ROUTER_WGHT(NUM_ROUTER_WGHT),

	                .A_READ_ADDR(A_READ_ADDR), 
	                .A_LOAD_ADDR(A_LOAD_ADDR),

	                .W_READ_ADDR(W_READ_ADDR), 
	                .W_LOAD_ADDR(W_LOAD_ADDR),

	                .PSUM_READ_ADDR(PSUM_READ_ADDR),
	                .PSUM_LOAD_ADDR(PSUM_LOAD_ADDR)
					)
	router_cluster_0
					(
					.clk(clk),  //TestBench/Controller
					.reset(reset),  //TestBench/Controller
					
					//Signals for activation router
					.r_data_glb_iact(GLB_cluster_0.r_data_iact),
					.r_addr_glb_iact(GLB_cluster_0.r_addr_iact),
					.read_req_glb_iact(GLB_cluster_0.read_req_iact),

					.w_data_spad_iact(pe_cluster_0.act_in),
					.load_en_spad_iact(pe_cluster_0.load_en_act),
					
					.load_spad_ctrl_iact(load_spad_ctrl_iact), //TestBench/Controller
					
					
					//Signals for weight router
					.r_data_glb_wght(GLB_cluster_0.r_data_wght),
					.r_addr_glb_wght(GLB_cluster_0.r_addr_wght),
					.read_req_glb_wght(GLB_cluster_0.read_req_wght),
					
					.w_data_spad_wght(pe_cluster_0.filt_in),
					.load_en_spad_wght(pe_cluster_0.load_en_wght),

					.load_spad_ctrl_wght(load_spad_ctrl_wght), //TestBench/Controller

					
					//Signals for psum router
					.r_data_spad_psum(pe_cluster_0.pe_out),
					
					.w_addr_glb_psum(GLB_cluster_0.w_addr_psum),
					.write_en_glb_psum(GLB_cluster_0.write_en_psum),
					.w_data_glb_psum(GLB_cluster_0.w_data_psum),
					
					.write_psum_ctrl(pe_cluster_0.compute_done) //Connected to compute done of PE
					);
	

//Declarations for PE_cluster
				

	
	logic [DATA_WIDTH-1:0] act_in;
    logic [DATA_WIDTH-1:0] filt_in;

	logic start;
	logic load_en_wght, load_en_act;

    logic [DATA_WIDTH-1:0] pe_out[X_dim-1:0];
  
	logic load_done; //TestBench/Controller
	
//PE_cluster Instantiation
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_0
    			(
					.clk(clk), 	   //TestBench/Controller
				    .reset(reset), //TestBench/Controller
					.start(start), //TestBench/Controller
					
				    .act_in(router_cluster_0.w_data_spad_iact),
					.filt_in(router_cluster_0.w_data_spad_wght),
					
					.load_en_wght(router_cluster_0.load_en_spad_wght),
					.load_en_act(router_cluster_0.load_en_spad_iact),
					
                    .pe_out(router_cluster_0.r_data_spad_psum),
					.compute_done(router_cluster_0.write_psum_ctrl),
					.load_done(load_done) //TestBench/Controller
    			);
				

	
	integer clk_prd = 10;
	
	always begin
		clk = 0; #(clk_prd/2);
		clk = 1; #(clk_prd/2);
		//0.1GHz
	end
	
	integer kernel_1,act_1,psum_1;
	integer w_addr = 0;
	int args;
	
	initial begin
		reset = 1; #30;
		reset = 0;
		

		//Write weights to weight glb
		write_en_wght = 1;
		kernel_1 = $fopen("kernel_5x5.txt","r");		
		while(!$feof(kernel_1))begin
			w_addr_wght = w_addr;
			args = $fscanf(kernel_1,"%d\n",w_data_wght);
			$display("Writing value %0d to address %0d in weight glb",w_data_wght,w_addr);
			w_addr++;
			#(clk_prd);
		end
		write_en_wght = 0;
		$fclose(kernel_1); 
		
		
		//Write activations to weight glb
		write_en_iact = 1;
		w_addr = 0;
		act_1 = $fopen("act_7x7.txt","r");
		while(!$feof(act_1))begin
			w_addr_iact = w_addr;
			args = $fscanf(act_1,"%d\n",w_data_iact);
			$display("Writing value %0d to address %0d in iact glb",w_data_iact,w_addr);
			w_addr++;
			#(clk_prd);
		end
		write_en_iact = 0;
		$fclose(act_1); 
		
		
		assign pe_out = pe_cluster_0.pe_out;
		assign compute_done = pe_cluster_0.compute_done;
		
		#(clk_prd);
		load_spad_ctrl_wght = 1; #15;
		load_spad_ctrl_wght = 0;
		
		wait (load_done == 1);
		
		#(clk_prd);
		load_spad_ctrl_iact = 1; #15;
		load_spad_ctrl_iact = 0;
	
		wait (load_done == 1);
	
		#(clk_prd);
		
		start = 1; 
		pe_cycles = cycles;
		#25; 
		$display("\n\nReading & Computing Begins.....\n\n");
		start = 0;
		
		wait (compute_done == 1);
		pe_cycles = cycles - pe_cycles;
		
		$display("\n\nPE_OUT from cluster is:%d\n,%d\n,%d\n",pe_cluster_0.pe_out[0],pe_cluster_0.pe_out[1],pe_cluster_0.pe_out[2]);
		#40
		$display("\n\nFinal PSUM of Iteration 1");
 		for(int i=0; i<X_dim; i++) begin
			$display("\npsum from column %d is:%d",i+1,pe_out[i]);
		end
		
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 2.....\n\n");
		start = 0;
		
				wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 2:");
 		for(int i=0; i<X_dim; i++) begin
			$display("\npsum from column %d is:%d",i+1,pe_out[i]);
		end
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 3.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 3:");
 		for(int i=0; i<X_dim; i++) begin
			$display("\npsum from column %d is:%d",i+1,pe_out[i]);
		end

				
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 5.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 4:");
 		for(int i=0; i<X_dim; i++) begin
			$display("\npsum from column %d is:%d",i+1,pe_out[i]);
		end

		
				
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 5.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 5:");
 		for(int i=0; i<X_dim; i++) begin
			$display("\npsum from column %d is:%d",i+1,pe_out[i]);
		end

		
		//Write Outputs to file
		
		$display("Total Cycles taken(including data transfer): %0d", cycles);
		$display("Total Cycle taken for computation: %0d", pe_cycles*3);
		$finish;
		
		#100;
		read_req_psum = 1;
		psum_1 = $fopen("./psum_3x3.txt","w");
		if (psum_1)  $display("File was opened successfully : %0d", psum_1);
		else     $display("File was NOT opened successfully : %0d", psum_1);
		for(int p=0; p<kernel_size**2; p++) begin
			r_addr_psum = p;
//			$fwrite(psum_1,"%d\n",r_data_psum);
			$fwrite(psum_1,"Hello\n");
			$display("Writing value %0d from address %0d GLB_psum to output text file",r_data_psum,p);
			#(clk_prd);
		end
		read_req_psum = 0;
		$fclose(psum_1);
		
		
	end

		// track # of cycles
		always @(posedge clk)
		begin
			if (reset)
				cycles = 0;
			else
				cycles = cycles + 1;
		end
	
endmodule


================================================
FILE: testbench/phase_1/router_cluster_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/03/2019 03:07:28 PM
// Design Name: 
// Module Name: router_cluster_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_cluster_tb();
	
	parameter DATA_BITWIDTH = 16;
	parameter ADDR_BITWIDTH = 10;
	
	parameter DATA_WIDTH = 16;
    parameter ADDR_WIDTH = 9;
	
	// GLB Cluster parameters. This TestBench uses only 1 of each
    parameter NUM_GLB_IACT = 1;
    parameter NUM_GLB_PSUM = 1;
	parameter NUM_GLB_WGHT = 1;
	
	parameter ADDR_BITWIDTH_GLB = 10;
	parameter ADDR_BITWIDTH_SPAD = 9;
	
	parameter NUM_ROUTER_PSUM = 1;
	parameter NUM_ROUTER_IACT = 1;
	parameter NUM_ROUTER_WGHT = 1;
			
	parameter int kernel_size = 3;
    parameter int act_size = 5;
	
	parameter int X_dim = 3;
    parameter int Y_dim = 3;
	
	//Used inside PEs
/* 	parameter W_READ_ADDR = 0;  
    parameter A_READ_ADDR_PE = 100;
    
    parameter W_LOAD_ADDR = 0;  
    parameter A_LOAD_ADDR_PE = 100;
    
    parameter PSUM_ADDR = 500; */
	
	parameter W_READ_ADDR = 0;  
    parameter A_READ_ADDR = 0;
    
    parameter W_LOAD_ADDR = 0;  
    parameter A_LOAD_ADDR = 0;
	
	parameter PSUM_READ_ADDR = 0;
	parameter PSUM_LOAD_ADDR = 0;
	
	int cycles, pe_cycles;
	
    logic clk;
    logic reset;

	//logic for GLB cluster
//    logic read_req_iact;
	logic read_req_psum;
//	logic read_req_wght;
	
    logic write_en_iact;
//	logic write_en_psum;
	logic write_en_wght;
	
			
	logic load_spad_ctrl_wght;
	logic load_spad_ctrl_iact;
		
//    logic [ADDR_BITWIDTH-1 : 0] r_addr_iact;
    logic [ADDR_BITWIDTH-1 : 0] r_addr_psum;
//	logic [ADDR_BITWIDTH-1 : 0] r_addr_wght;
	
    logic [ADDR_BITWIDTH-1 : 0] w_addr_iact;
    logic [ADDR_BITWIDTH-1 : 0] w_addr_psum;
	logic [ADDR_BITWIDTH-1 : 0] w_addr_wght;
	
    logic [DATA_BITWIDTH-1 : 0] w_data_iact;
    logic [DATA_BITWIDTH-1 : 0] w_data_psum;
	logic [DATA_BITWIDTH-1 : 0] w_data_wght;
	
//    logic [DATA_BITWIDTH-1 : 0] r_data_iact;
    logic [DATA_BITWIDTH-1 : 0] r_data_psum;
//   logic [DATA_BITWIDTH-1 : 0] r_data_wght;
	
	logic compute_done;
	
	
	//GLB cluster initialization
	GLB_cluster 
			#(	.DATA_BITWIDTH(DATA_BITWIDTH),
				.ADDR_BITWIDTH(ADDR_BITWIDTH),
				.NUM_GLB_IACT(NUM_GLB_IACT),
				.NUM_GLB_PSUM(NUM_GLB_PSUM),
				.NUM_GLB_WGHT(NUM_GLB_WGHT)
			)
	GLB_cluster_0
			(
				.clk(clk),   //TestBench/Controller
				.reset(reset),  //TestBench/Controller
				
				//Signals for reading from GLB
				.read_req_iact(router_cluster.read_req_glb_iact),
				.read_req_psum(read_req_psum), //Read by testbench/controller
				.read_req_wght(router_cluster_0.read_req_glb_wght),
				
			    .r_data_iact(router_cluster_0.r_data_glb_iact),
			    .r_data_psum(r_data_psum), //Read by testbench/controller
				.r_data_wght(router_cluster_0.r_data_glb_wght),
				
				.r_addr_iact(router_cluster_0.r_addr_glb_iact),
			    .r_addr_psum(r_addr_psum), //testbench for reading final psums
				.r_addr_wght(router_cluster_0.r_addr_glb_wght),

				
				//Signals for writing to GLB
			    .w_addr_iact(w_addr_iact), //testbench for writing
			    .w_addr_psum(router_cluster_0.w_addr_glb_psum),
				.w_addr_wght(w_addr_wght), //testbench for writing
 
			    .w_data_iact(w_data_iact), //testbench for writing
			    .w_data_psum(router_cluster_0.w_data_glb_psum),
				.w_data_wght(w_data_wght), //testbench for writing

				.write_en_iact(write_en_iact), //testbench for writing
				.write_en_psum(router_cluster_0.write_en_glb_psum),
				.write_en_wght(write_en_wght) //testbench for writing
			
			);

			
	logic [DATA_BITWIDTH-1 : 0] r_data_spad_psum[0:kernel_size-1];		
	
	//Router Cluster Instantiation
	router_cluster#(.DATA_BITWIDTH(DATA_BITWIDTH),
	                .ADDR_BITWIDTH_GLB(ADDR_BITWIDTH_GLB),
	                .ADDR_BITWIDTH_SPAD(ADDR_BITWIDTH_SPAD),

	                .kernel_size(kernel_size),
	                .act_size(act_size),

	                .NUM_ROUTER_PSUM(NUM_ROUTER_PSUM),
	                .NUM_ROUTER_IACT(NUM_ROUTER_IACT),
	                .NUM_ROUTER_WGHT(NUM_ROUTER_WGHT),

	                .A_READ_ADDR(A_READ_ADDR), 
	                .A_LOAD_ADDR(A_LOAD_ADDR),

	                .W_READ_ADDR(W_READ_ADDR), 
	                .W_LOAD_ADDR(W_LOAD_ADDR),

	                .PSUM_READ_ADDR(PSUM_READ_ADDR),
	                .PSUM_LOAD_ADDR(PSUM_LOAD_ADDR)
					)
	router_cluster_0
					(
					.clk(clk),  //TestBench/Controller
					.reset(reset),  //TestBench/Controller
					
					//Signals for activation router
					.r_data_glb_iact(GLB_cluster_0.r_data_iact),
					.r_addr_glb_iact(GLB_cluster_0.r_addr_iact),
					.read_req_glb_iact(GLB_cluster_0.read_req_iact),

					.w_data_spad_iact(pe_cluster_0.act_in),
					.load_en_spad_iact(pe_cluster_0.load_en_act),
					
					.load_spad_ctrl_iact(load_spad_ctrl_iact), //TestBench/Controller
					
					
					//Signals for weight router
					.r_data_glb_wght(GLB_cluster_0.r_data_wght),
					.r_addr_glb_wght(GLB_cluster_0.r_addr_wght),
					.read_req_glb_wght(GLB_cluster_0.read_req_wght),
					
					.w_data_spad_wght(pe_cluster_0.filt_in),
					.load_en_spad_wght(pe_cluster_0.load_en_wght),

					.load_spad_ctrl_wght(load_spad_ctrl_wght), //TestBench/Controller

					
					//Signals for psum router
					.r_data_spad_psum(pe_cluster_0.pe_out),
					
					.w_addr_glb_psum(GLB_cluster_0.w_addr_psum),
					.write_en_glb_psum(GLB_cluster_0.write_en_psum),
					.w_data_glb_psum(GLB_cluster_0.w_data_psum),
					
					.write_psum_ctrl(pe_cluster_0.compute_done) //Connected to compute done of PE
					);
	

//Declarations for PE_cluster
				

	
	logic [DATA_WIDTH-1:0] act_in;
    logic [DATA_WIDTH-1:0] filt_in;

	logic start;
	logic load_en_wght, load_en_act;

    logic [DATA_WIDTH-1:0] pe_out[X_dim-1:0];
  
	logic load_done; //TestBench/Controller
	
//PE_cluster Instantiation
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_0
    			(
					.clk(clk), 	   //TestBench/Controller
				    .reset(reset), //TestBench/Controller
					.start(start), //TestBench/Controller
					
				    .act_in(router_cluster_0.w_data_spad_iact),
					.filt_in(router_cluster_0.w_data_spad_wght),
					
					.load_en_wght(router_cluster_0.load_en_spad_wght),
					.load_en_act(router_cluster_0.load_en_spad_iact),
					
                    .pe_out(router_cluster_0.r_data_spad_psum),
					.compute_done(router_cluster_0.write_psum_ctrl),
					.load_done(load_done) //TestBench/Controller
    			);
				

	
	integer clk_prd = 10;
	
	always begin
		clk = 0; #(clk_prd/2);
		clk = 1; #(clk_prd/2);
		//0.1GHz
	end
	
	integer kernel_1,act_1,psum_1;
	integer w_addr = 0;
	int args;
	
	initial begin
		reset = 1; #30;
		reset = 0;
		

		//Write weights to weight glb
		write_en_wght = 1;
		kernel_1 = $fopen("kernel_3x3.txt","r");		
		while(!$feof(kernel_1))begin
			w_addr_wght = w_addr;
			args = $fscanf(kernel_1,"%d\n",w_data_wght);
			$display("Writing value %0d to address %0d in weight glb",w_data_wght,w_addr);
			w_addr++;
			#(clk_prd);
		end
		write_en_wght = 0;
		$fclose(kernel_1); 
		
		
		//Write activations to weight glb
		write_en_iact = 1;
		w_addr = 0;
		act_1 = $fopen("act_5x5.txt","r");
		while(!$feof(act_1))begin
			w_addr_iact = w_addr;
			args = $fscanf(act_1,"%d\n",w_data_iact);
			$display("Writing value %0d to address %0d in iact glb",w_data_iact,w_addr);
			w_addr++;
			#(clk_prd);
		end
		write_en_iact = 0;
		$fclose(act_1); 
		
		
		assign pe_out = pe_cluster_0.pe_out;
		assign compute_done = pe_cluster_0.compute_done;
		
		#(clk_prd);
		load_spad_ctrl_wght = 1; #15;
		load_spad_ctrl_wght = 0;
		
		wait (load_done == 1);
		
		#(clk_prd);
		load_spad_ctrl_iact = 1; #15;
		load_spad_ctrl_iact = 0;
	
		wait (load_done == 1);
	
		#(clk_prd);
		
		start = 1; 
		pe_cycles = cycles;
		#25; 
		$display("\n\nReading & Computing Begins.....\n\n");
		start = 0;
		
		wait (compute_done == 1);
		pe_cycles = cycles - pe_cycles;
		
		$display("\n\nPE_OUT from cluster is:%d\n,%d\n,%d\n",pe_cluster_0.pe_out[0],pe_cluster_0.pe_out[1],pe_cluster_0.pe_out[2]);
		#40
		$display("\n\nFinal PSUM of Iteration 1");
 		for(int i=0; i<X_dim; i++) begin
			$display("\npsum from column %d is:%d",i+1,pe_out[i]);
		end
		
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 2.....\n\n");
		start = 0;
		
				wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 2:");
 		for(int i=0; i<X_dim; i++) begin
			$display("\npsum from column %d is:%d",i+1,pe_out[i]);
		end
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 3.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 3:");
 		for(int i=0; i<X_dim; i++) begin
			$display("\npsum from column %d is:%d",i+1,pe_out[i]);
		end

		
		//Write Outputs to file
		
		$display("Total Cycles taken(including data transfer): %0d", cycles);
		$display("Total Cycle taken for computation: %0d", pe_cycles*3);
		$finish;
		
		#100;
		read_req_psum = 1;
		psum_1 = $fopen("./psum_3x3.txt","w");
		if (psum_1)  $display("File was opened successfully : %0d", psum_1);
		else     $display("File was NOT opened successfully : %0d", psum_1);
		for(int p=0; p<kernel_size**2; p++) begin
			r_addr_psum = p;
//			$fwrite(psum_1,"%d\n",r_data_psum);
			$fwrite(psum_1,"Hello\n");
			$display("Writing value %0d from address %0d GLB_psum to output text file",r_data_psum,p);
			#(clk_prd);
		end
		read_req_psum = 0;
		$fclose(psum_1);
		
		
	end

		
		// track # of cycles
		always @(posedge clk)
		begin
			if (reset)
				cycles = 0;
			else
				cycles = cycles + 1;
		end
		
endmodule


================================================
FILE: testbench/phase_1/router_iact.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/02/2019 03:12:11 PM
// Design Name: 
// Module Name: router_act
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_iact #( parameter DATA_BITWIDTH = 16,
						parameter ADDR_BITWIDTH_GLB = 10,
						parameter ADDR_BITWIDTH_SPAD = 9,
						
						parameter int X_dim = 5,
                        parameter int Y_dim = 3,
                        parameter int kernel_size = 3,
                        parameter int act_size = 5,
						
						parameter W_READ_ADDR = 0, 
                        
                        parameter W_LOAD_ADDR = 0,
						
						parameter PSUM_READ_ADDR = 500,
						parameter PSUM_LOAD_ADDR = 0
					)
					
					(	input clk,
						input reset,
						
						//for reading glb
						input [DATA_BITWIDTH-1 : 0] r_data_glb_wght,
						output logic [ADDR_BITWIDTH_GLB-1 : 0] r_addr_glb_wght,
						output logic read_req_glb_wght,
						
						//for writing to spad
						output logic [DATA_BITWIDTH-1 : 0] w_data_spad,
						output logic load_en_spad,
						
						//Input from control unit to load weights to spad
						input load_spad_ctrl
			
					);
				
					
		enum logic [2:0] {IDLE=3'b000, READ_GLB=3'b001, WRITE_SPAD=3'b010, READ_GLB_0=3'b011} state;
		
		logic [4:0] filt_count;
		
		always@(posedge clk) begin
			$display("State: %s", state.name());
			if(reset) begin
				read_req_glb_wght <= 0;
				r_addr_glb_wght <= 0;
				load_en_spad <= 0;
				filt_count <= 0;
				state <= IDLE;
			end else begin
				case(state)
					IDLE:begin
						if(load_spad_ctrl) begin
							read_req_glb_wght <= 1;
							r_addr_glb_wght <= W_READ_ADDR;
							state <= READ_GLB;
						end else begin
							read_req_glb_wght = 0;
							load_en_spad = 0;
							state <= IDLE;
						end
					end
					
					READ_GLB:begin
						load_en_spad <= 1;
						filt_count <= filt_count + 1;
						r_addr_glb_wght <= r_addr_glb_wght + 1;
						w_data_spad <= r_data_glb_wght;
						state <= WRITE_SPAD;
					end
					
					WRITE_SPAD:begin
						if(filt_count == (kernel_size**2)) begin
							w_data_spad <= r_data_glb_wght;
							filt_count <= 0;
							r_addr_glb_wght <= W_READ_ADDR;
							
							state <= IDLE;
						end else begin
							w_data_spad <= r_data_glb_wght;
							filt_count <= filt_count + 1;
							r_addr_glb_wght <= r_addr_glb_wght + 1;
							state <= WRITE_SPAD;
						end
					end
				endcase
			end
		end
 
endmodule



================================================
FILE: testbench/phase_1/router_iact_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/03/2019 07:08:42 AM
// Design Name: 
// Module Name: router_iact_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////



module router_iact_tb();

	parameter DATA_BITWIDTH = 16;
	parameter ADDR_BITWIDTH = 10;
	
	// GLB Cluster parameters. This TestBench uses only 1 of each
    parameter NUM_GLB_IACT = 1;
    parameter NUM_GLB_PSUM = 1;
	parameter NUM_GLB_WGHT = 1;
	
	
    logic clk;
    logic reset;

	//logic for GLB cluster
//    logic read_req_iact;
	logic read_req_psum;
//	logic read_req_wght;
	
    logic write_en_iact;
	logic write_en_psum;
	logic write_en_wght;
	
//    logic [ADDR_BITWIDTH-1 : 0] r_addr_iact;
    logic [ADDR_BITWIDTH-1 : 0] r_addr_psum;
//	logic [ADDR_BITWIDTH-1 : 0] r_addr_wght;
	
    logic [ADDR_BITWIDTH-1 : 0] w_addr_iact;
    logic [ADDR_BITWIDTH-1 : 0] w_addr_psum;
	logic [ADDR_BITWIDTH-1 : 0] w_addr_wght;
	
    logic [DATA_BITWIDTH-1 : 0] w_data_iact;
    logic [DATA_BITWIDTH-1 : 0] w_data_psum;
	logic [DATA_BITWIDTH-1 : 0] w_data_wght;
	
//    logic [DATA_BITWIDTH-1 : 0] r_data_iact;
    logic [DATA_BITWIDTH-1 : 0] r_data_psum;
//   logic [DATA_BITWIDTH-1 : 0] r_data_wght;

	
	//GLB cluster initialization
	GLB_cluster 
			#(	.DATA_BITWIDTH(DATA_BITWIDTH),
				.ADDR_BITWIDTH(ADDR_BITWIDTH),
				.NUM_GLB_IACT(NUM_GLB_IACT),
				.NUM_GLB_PSUM(NUM_GLB_PSUM),
				.NUM_GLB_WGHT(NUM_GLB_WGHT)
			)
	GLB_cluster_0
			(
				.clk(clk), 
				.reset(reset),
				
				.read_req_iact(router_iact_0.read_req_glb_iact),
				.read_req_psum(read_req_psum),
//				.read_req_wght(read_req_wght),
				.read_req_wght(router_weight_0.read_req_glb_wght),
				
				.write_en_iact(write_en_iact),
				.write_en_psum(write_en_psum),
				.write_en_wght(write_en_wght),
				
				.r_addr_iact(router_iact_0.r_addr_glb_iact),
			    .r_addr_psum(r_addr_psum),
//				.r_addr_wght(r_addr_wght),
				.r_addr_wght(router_weight_0.r_addr_glb_wght),

			    .w_addr_iact(w_addr_iact),
			    .w_addr_psum(w_addr_psum),
				.w_addr_wght(w_addr_wght),

			    .w_data_iact(w_data_iact),
			    .w_data_psum(w_data_psum),
				.w_data_wght(w_data_wght),

			    .r_data_iact(router_iact_0.r_data_glb_iact),
			    .r_data_psum(r_data_psum),
//				.r_data_wght(r_data_wght)
				.r_data_wght(router_weight_0.r_data_glb_wght)
			);

			
	//Declarations for weight router
	parameter ADDR_BITWIDTH_GLB = 10;
	parameter ADDR_BITWIDTH_SPAD = 9;
	
	parameter int kernel_size = 3;
	parameter int act_size = 5;
	
	parameter W_READ_ADDR = 0;
	
	parameter W_LOAD_ADDR = 0;
	
	parameter PSUM_READ_ADDR = 500;
	parameter PSUM_LOAD_ADDR = 0;
	
//	logic [ADDR_BITWIDTH_SPAD-1 : 0] w_addr_spad;
	logic [DATA_BITWIDTH-1 : 0] w_data_spad_wght;
	
	logic [DATA_BITWIDTH-1 : 0] r_data_glb_wght;
	
	logic load_en_spad_wght;
	
	logic load_spad_ctrl;
	
			
	//Weight Router Instantiation
	router_weight #(.DATA_BITWIDTH(DATA_BITWIDTH),
					.ADDR_BITWIDTH_GLB(ADDR_BITWIDTH_GLB),
					.ADDR_BITWIDTH_SPAD(ADDR_BITWIDTH_SPAD),
//					X_dim = 5,
//	                Y_dim = 3,
	                .kernel_size(kernel_size),
	                .act_size(act_size),
					
					.W_READ_ADDR(W_READ_ADDR), 
	                .W_LOAD_ADDR(W_LOAD_ADDR),
					
					.PSUM_READ_ADDR(PSUM_READ_ADDR),
					.PSUM_LOAD_ADDR(PSUM_LOAD_ADDR)
				)
	router_weight_0
				(	.clk(clk),
					.reset(reset),
					
					.r_data_glb_wght(GLB_cluster_0.r_data_wght),
//					read_wght_ctrl,
					 .r_addr_glb_wght(GLB_cluster_0.r_addr_wght),
					 .read_req_glb_wght(GLB_cluster_0.read_req_wght),
					
					//for writing to spad
//					write_wght_ctrl,
//					.w_addr_spad(w_addr_spad),
					.w_data_spad(w_data_spad_wght),
					.load_en_spad(load_en_spad_wght),
					
					//Input from control unit to load weights to spad
					.load_spad_ctrl(load_spad_ctrl)
				);
	
	
	parameter A_READ_ADDR = 0;
	parameter A_LOAD_ADDR = 100;
	
//	logic [ADDR_BITWIDTH_SPAD-1 : 0] w_addr_spad_iact;
	logic [DATA_BITWIDTH-1 : 0] w_data_spad_iact;
	
	logic [DATA_BITWIDTH-1 : 0] r_data_glb_iact;
	
	logic load_en_spad_iact;
	
	logic load_spad_ctrl_iact;
			
	//Activation Router Instantiation
	router_iact #(.DATA_BITWIDTH(DATA_BITWIDTH),
					.ADDR_BITWIDTH_GLB(ADDR_BITWIDTH_GLB),
					.ADDR_BITWIDTH_SPAD(ADDR_BITWIDTH_SPAD),
//					X_dim = 5,
//	                Y_dim = 3,
	                .kernel_size(kernel_size),
	                .act_size(act_size),
					
					.A_READ_ADDR(A_READ_ADDR), 
	                .A_LOAD_ADDR(A_LOAD_ADDR)
				)
	router_iact_0
				(	.clk(clk),
					.reset(reset),
					
					.r_data_glb_iact(GLB_cluster_0.r_data_iact),
//					read_wght_ctrl,
					 .r_addr_glb_iact(GLB_cluster_0.r_addr_iact),
					 .read_req_glb_iact(GLB_cluster_0.read_req_iact),
					
					//for writing to spad
//					write_wght_ctrl,
//					.w_addr_spad(w_addr_spad),
					.w_data_spad(w_data_spad_iact),
					.load_en_spad(load_en_spad_iact),
					
					//Input from control unit to load weights to spad
					.load_spad_ctrl(load_spad_ctrl_iact)
				);	
	
	parameter DATA_WIDTH = 16;
    parameter ADDR_WIDTH = 9;
	parameter int X_dim = 3;
    parameter int Y_dim = 3;
	
	logic [DATA_WIDTH-1:0] act_in;
    logic [DATA_WIDTH-1:0] filt_in;
//    logic load_en;
	logic start;
	logic load_en_wght, load_en_act;

    logic [DATA_WIDTH-1:0] pe_out[X_dim-1:0];
  
	logic compute_done;
	logic load_done;
	
//	logic [DATA_WIDTH-1:0] psum_out[0 : X_dim*Y_dim-1];
	
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_0
    			(
					.clk(clk),
				    .reset(reset),
				    .act_in(w_data_spad_iact),
//				    .filt_in(filt_in),
					.filt_in(w_data_spad_wght),
//				    .load_en(load_en),
					.load_en_wght(load_en_spad_wght),
					.load_en_act(load_en_spad_iact),
					.start(start),
                    .pe_out(pe_out),
					.compute_done(compute_done),
					.load_done(load_done)
					
		//extra
//					.psum_out(psum_out)
    			);
				
	
	
	
	integer clk_prd = 10;
	
	always begin
		clk = 0; #(clk_prd/2);
		clk = 1; #(clk_prd/2);
		//0.1GHz
	end
	
	integer kernel_1,act_1;
	integer w_addr = 0;
	int args;
	
	initial begin
		reset = 1; #30;
		reset = 0;
		

		//Write weights to weight glb
		write_en_wght = 1;
		kernel_1 = $fopen("kernel_3x3.txt","r");		
		while(!$feof(kernel_1))begin
			w_addr_wght = w_addr;
			args = $fscanf(kernel_1,"%d\n",w_data_wght);
			$display("Writing value %0d to address %0d in weight glb",w_data_wght,w_addr);
			w_addr++;
			#(clk_prd);
		end
		write_en_wght = 0;
		$fclose(kernel_1); 
		
		
		//Write activations to weight glb
		write_en_iact = 1;
		w_addr = 0;
		act_1 = $fopen("act_5x5.txt","r");
		while(!$feof(act_1))begin
			w_addr_iact = w_addr;
			args = $fscanf(act_1,"%d\n",w_data_iact);
			$display("Writing value %0d to address %0d in iact glb",w_data_iact,w_addr);
			w_addr++;
			#(clk_prd);
		end
		write_en_iact = 0;
		$fclose(act_1); 
		
		
		
		#300;
		load_spad_ctrl = 1; #15;
		load_spad_ctrl = 0;
		
		wait (load_done == 1);
		
		#50;
		load_spad_ctrl_iact = 1; #15;
		load_spad_ctrl_iact = 0;
	
		wait (load_done == 1);
	
		#100;
		
		start = 1; #25; 
		$display("\n\nReading & Computing Begins.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		#40
		$display("\n\nFinal PSUM of Iteration 1");
 		for(int i=0; i<X_dim; i++) begin
			$display("\npsum from column %d is:%d",i+1,pe_out[i]);
		end
		
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 2.....\n\n");
		start = 0;
		
				wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 2:");
 		for(int i=0; i<X_dim; i++) begin
			$display("\npsum from column %d is:%d",i+1,pe_out[i]);
		end
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 3.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 3:");
 		for(int i=0; i<X_dim; i++) begin
			$display("\npsum from column %d is:%d",i+1,pe_out[i]);
		end

	end
	
endmodule




================================================
FILE: testbench/phase_1/router_psum_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/03/2019 01:09:58 PM
// Design Name: 
// Module Name: router_psum_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_psum_tb();

	parameter DATA_BITWIDTH = 16;
	parameter ADDR_BITWIDTH = 10;
	
	// GLB Cluster parameters. This TestBench uses only 1 of each
    parameter NUM_GLB_IACT = 1;
    parameter NUM_GLB_PSUM = 1;
	parameter NUM_GLB_WGHT = 1;
	
	
    logic clk;
    logic reset;

	//logic for GLB cluster
//    logic read_req_iact;
	logic read_req_psum;
//	logic read_req_wght;
	
    logic write_en_iact;
	logic write_en_psum;
	logic write_en_wght;
	
//    logic [ADDR_BITWIDTH-1 : 0] r_addr_iact;
    logic [ADDR_BITWIDTH-1 : 0] r_addr_psum;
//	logic [ADDR_BITWIDTH-1 : 0] r_addr_wght;
	
    logic [ADDR_BITWIDTH-1 : 0] w_addr_iact;
    logic [ADDR_BITWIDTH-1 : 0] w_addr_psum;
	logic [ADDR_BITWIDTH-1 : 0] w_addr_wght;
	
    logic [DATA_BITWIDTH-1 : 0] w_data_iact;
    logic [DATA_BITWIDTH-1 : 0] w_data_psum;
	logic [DATA_BITWIDTH-1 : 0] w_data_wght;
	
//    logic [DATA_BITWIDTH-1 : 0] r_data_iact;
    logic [DATA_BITWIDTH-1 : 0] r_data_psum;
//   logic [DATA_BITWIDTH-1 : 0] r_data_wght;
	
	logic compute_done;
	
	//GLB cluster initialization
	GLB_cluster 
			#(	.DATA_BITWIDTH(DATA_BITWIDTH),
				.ADDR_BITWIDTH(ADDR_BITWIDTH),
				.NUM_GLB_IACT(NUM_GLB_IACT),
				.NUM_GLB_PSUM(NUM_GLB_PSUM),
				.NUM_GLB_WGHT(NUM_GLB_WGHT)
			)
	GLB_cluster_0
			(
				.clk(clk), 
				.reset(reset),
				
				.read_req_iact(router_iact_0.read_req_glb_iact),
				.read_req_psum(read_req_psum),
//				.read_req_wght(read_req_wght),
				.read_req_wght(router_weight_0.read_req_glb_wght),
				
				.write_en_iact(write_en_iact),
				.write_en_psum(write_en_psum),
				.write_en_wght(write_en_wght),
				
				.r_addr_iact(router_iact_0.r_addr_glb_iact),
			    .r_addr_psum(r_addr_psum),
//				.r_addr_wght(r_addr_wght),
				.r_addr_wght(router_weight_0.r_addr_glb_wght),

			    .w_addr_iact(w_addr_iact),
			    .w_addr_psum(w_addr_psum),
				.w_addr_wght(w_addr_wght),

			    .w_data_iact(w_data_iact),
			    .w_data_psum(w_data_psum),
				.w_data_wght(w_data_wght),

			    .r_data_iact(router_iact_0.r_data_glb_iact),
			    .r_data_psum(r_data_psum),
//				.r_data_wght(r_data_wght)
				.r_data_wght(router_weight_0.r_data_glb_wght)
			);

			
	//Declarations for weight router
	parameter ADDR_BITWIDTH_GLB = 10;
	parameter ADDR_BITWIDTH_SPAD = 9;
	
	parameter int kernel_size = 3;
	parameter int act_size = 5;
	
	parameter W_READ_ADDR = 0;
	
	parameter W_LOAD_ADDR = 0;
	
	parameter PSUM_READ_ADDR = 500;
	parameter PSUM_LOAD_ADDR = 0;
	
//	logic [ADDR_BITWIDTH_SPAD-1 : 0] w_addr_spad;
	logic [DATA_BITWIDTH-1 : 0] w_data_spad_wght;
	
	logic [DATA_BITWIDTH-1 : 0] r_data_glb_wght;
	
	logic load_en_spad_wght;
	
	logic load_spad_ctrl;
	
			
	//Weight Router Instantiation
	router_weight #(.DATA_BITWIDTH(DATA_BITWIDTH),
					.ADDR_BITWIDTH_GLB(ADDR_BITWIDTH_GLB),
					.ADDR_BITWIDTH_SPAD(ADDR_BITWIDTH_SPAD),
//					X_dim = 5,
//	                Y_dim = 3,
	                .kernel_size(kernel_size),
	                .act_size(act_size),
					
					.W_READ_ADDR(W_READ_ADDR), 
	                .W_LOAD_ADDR(W_LOAD_ADDR),
					
					.PSUM_READ_ADDR(PSUM_READ_ADDR),
					.PSUM_LOAD_ADDR(PSUM_LOAD_ADDR)
				)
	router_weight_0
				(	.clk(clk),
					.reset(reset),
					
					.r_data_glb_wght(GLB_cluster_0.r_data_wght),
//					read_wght_ctrl,
					 .r_addr_glb_wght(GLB_cluster_0.r_addr_wght),
					 .read_req_glb_wght(GLB_cluster_0.read_req_wght),
					
					//for writing to spad
//					write_wght_ctrl,
//					.w_addr_spad(w_addr_spad),
					.w_data_spad(w_data_spad_wght),
					.load_en_spad(load_en_spad_wght),
					
					//Input from control unit to load weights to spad
					.load_spad_ctrl(load_spad_ctrl)
				);
	
	
	parameter A_READ_ADDR = 0;
	parameter A_LOAD_ADDR = 100;
	
//	logic [ADDR_BITWIDTH_SPAD-1 : 0] w_addr_spad_iact;
	logic [DATA_BITWIDTH-1 : 0] w_data_spad_iact;
	
	logic [DATA_BITWIDTH-1 : 0] r_data_glb_iact;
	
	logic load_en_spad_iact;
	
	logic load_spad_ctrl_iact;
			
	//Activation Router Instantiation
	router_iact #(.DATA_BITWIDTH(DATA_BITWIDTH),
					.ADDR_BITWIDTH_GLB(ADDR_BITWIDTH_GLB),
					.ADDR_BITWIDTH_SPAD(ADDR_BITWIDTH_SPAD),
//					X_dim = 5,
//	                Y_dim = 3,
	                .kernel_size(kernel_size),
	                .act_size(act_size),
					
					.A_READ_ADDR(A_READ_ADDR), 
	                .A_LOAD_ADDR(A_LOAD_ADDR),
					
					.PSUM_READ_ADDR(PSUM_READ_ADDR),
					.PSUM_LOAD_ADDR(PSUM_LOAD_ADDR)
				)
	router_iact_0
				(	.clk(clk),
					.reset(reset),
					
					.r_data_glb_iact(GLB_cluster_0.r_data_iact),
//					read_wght_ctrl,
					 .r_addr_glb_iact(GLB_cluster_0.r_addr_iact),
					 .read_req_glb_iact(GLB_cluster_0.read_req_iact),
					
					//for writing to spad
//					write_wght_ctrl,
//					.w_addr_spad(w_addr_spad),
					.w_data_spad(w_data_spad_iact),
					.load_en_spad(load_en_spad_iact),
					
					//Input from control unit to load weights to spad
					.load_spad_ctrl(load_spad_ctrl_iact)
				);	
	
		//psum Router Instantiation
	router_psum #(.DATA_BITWIDTH(DATA_BITWIDTH),
					.ADDR_BITWIDTH_GLB(ADDR_BITWIDTH_GLB),
					.ADDR_BITWIDTH_SPAD(ADDR_BITWIDTH_SPAD),
//					X_dim = 5,
//	                Y_dim = 3,
	                .kernel_size(kernel_size),
	                .act_size(act_size),
					
					.PSUM_LOAD_ADDR(PSUM_LOAD_ADDR)
				)
	router_psum_0
				(	.clk(clk),
					.reset(reset),
					
					.r_data_spad_psum(pe_cluster_0.pe_out),
//					read_wght_ctrl,
//					.r_addr_glb_iact(GLB_cluster_0.r_addr_iact),
//					 .read_req_glb_iact(GLB_cluster_0.read_req_iact),
					
					//for writing to spad
//					write_wght_ctrl,
					.w_addr_glb_psum(w_addr_psum),
					.w_data_glb_psum(w_data_psum),
					.write_en_glb_psum(write_en_psum),
					
					//Input from control unit to load weights to spad
					.write_psum_ctrl(compute_done)
				);	
				
	parameter DATA_WIDTH = 16;
    parameter ADDR_WIDTH = 9;
	parameter int X_dim = 3;
    parameter int Y_dim = 3;
	
	logic [DATA_WIDTH-1:0] act_in;
    logic [DATA_WIDTH-1:0] filt_in;
//    logic load_en;
	logic start;
	logic load_en_wght, load_en_act;

    logic [DATA_WIDTH-1:0] pe_out[X_dim-1:0];
  

	logic load_done;
	
//	logic [DATA_WIDTH-1:0] psum_out[0 : X_dim*Y_dim-1];
	
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_0
    			(
					.clk(clk),
				    .reset(reset),
				    .act_in(w_data_spad_iact),
//				    .filt_in(filt_in),
					.filt_in(w_data_spad_wght),
//				    .load_en(load_en),
					.load_en_wght(load_en_spad_wght),
					.load_en_act(load_en_spad_iact),
					.start(start),
                    .pe_out(router_psum_0.r_data_spad_psum),
					.compute_done(compute_done),
					.load_done(load_done)
					
		//extra
//					.psum_out(psum_out)
    			);
				

	
	integer clk_prd = 10;
	
	always begin
		clk = 0; #(clk_prd/2);
		clk = 1; #(clk_prd/2);
		//0.1GHz
	end
	
	integer kernel_1,act_1;
	integer w_addr = 0;
	int args;
	
	initial begin
		reset = 1; #30;
		reset = 0;
		

		//Write weights to weight glb
		write_en_wght = 1;
		kernel_1 = $fopen("kernel_3x3.txt","r");		
		while(!$feof(kernel_1))begin
			w_addr_wght = w_addr;
			args = $fscanf(kernel_1,"%d\n",w_data_wght);
			$display("Writing value %0d to address %0d in weight glb",w_data_wght,w_addr);
			w_addr++;
			#(clk_prd);
		end
		write_en_wght = 0;
		$fclose(kernel_1); 
		
		
		//Write activations to weight glb
		write_en_iact = 1;
		w_addr = 0;
		act_1 = $fopen("act_5x5.txt","r");
		while(!$feof(act_1))begin
			w_addr_iact = w_addr;
			args = $fscanf(act_1,"%d\n",w_data_iact);
			$display("Writing value %0d to address %0d in iact glb",w_data_iact,w_addr);
			w_addr++;
			#(clk_prd);
		end
		write_en_iact = 0;
		$fclose(act_1); 
		
		
		
		#300;
		load_spad_ctrl = 1; #15;
		load_spad_ctrl = 0;
		
		wait (load_done == 1);
		
		#50;
		load_spad_ctrl_iact = 1; #15;
		load_spad_ctrl_iact = 0;
	
		wait (load_done == 1);
	
		#100;
		
		start = 1; #25; 
		$display("\n\nReading & Computing Begins.....\n\n");
		start = 0;
		
		wait (compute_done == 1);
		$display("\n\nPE_OUT from cluster is:%d\n,%d\n,%d\n",pe_cluster_0.pe_out[0],pe_cluster_0.pe_out[1],pe_cluster_0.pe_out[2]);
		#40
		$display("\n\nFinal PSUM of Iteration 1");
 		for(int i=0; i<X_dim; i++) begin
			$display("\npsum from column %d is:%d",i+1,pe_out[i]);
		end
		
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 2.....\n\n");
		start = 0;
		
				wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 2:");
 		for(int i=0; i<X_dim; i++) begin
			$display("\npsum from column %d is:%d",i+1,pe_out[i]);
		end
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 3.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 3:");
 		for(int i=0; i<X_dim; i++) begin
			$display("\npsum from column %d is:%d",i+1,pe_out[i]);
		end

	end
	
endmodule







================================================
FILE: testbench/phase_1/router_weight.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/01/2019 03:50:08 PM
// Design Name: 
// Module Name: router_weight
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_weight #( parameter DATA_BITWIDTH = 16,
						parameter ADDR_BITWIDTH_GLB = 10,
						parameter ADDR_BITWIDTH_SPAD = 9,
						
						parameter int X_dim = 5,
                        parameter int Y_dim = 3,
                        parameter int kernel_size = 3,
                        parameter int act_size = 5,
						
						parameter W_READ_ADDR = 0, 
                        
                        parameter W_LOAD_ADDR = 0,
						
						parameter PSUM_READ_ADDR = 500,
						parameter PSUM_LOAD_ADDR = 0
					)
					
					(	input clk,
						input reset,
						
						//for reading glb
						input [DATA_BITWIDTH-1 : 0] r_data_glb_wght,
						output logic [ADDR_BITWIDTH_GLB-1 : 0] r_addr_glb_wght,
						output logic read_req_glb_wght,
						
						//for writing to spad
						output logic [DATA_BITWIDTH-1 : 0] w_data_spad,
						output logic load_en_spad,
						
						//Input from control unit to load weights to spad
						input load_spad_ctrl
			
					);
				
					
		enum logic [2:0] {IDLE=3'b000, READ_GLB=3'b001, WRITE_SPAD=3'b010, READ_GLB_0=3'b011} state;
		
		logic [4:0] filt_count;
		
		always@(posedge clk) begin
//			$display("State: %s", state.name());
			if(reset) begin
				read_req_glb_wght <= 0;
				r_addr_glb_wght <= 0;
				load_en_spad <= 0;
				filt_count <= 0;
				state <= IDLE;
			end else begin
				case(state)
					IDLE:begin
						if(load_spad_ctrl) begin
							read_req_glb_wght <= 1;
							r_addr_glb_wght <= W_READ_ADDR;
							state <= READ_GLB;
						end else begin
							read_req_glb_wght = 0;
							load_en_spad = 0;
							state <= IDLE;
						end
					end
					
					READ_GLB:begin
						load_en_spad <= 1;
						filt_count <= filt_count + 1;
						r_addr_glb_wght <= r_addr_glb_wght + 1;
						w_data_spad <= r_data_glb_wght;
						state <= WRITE_SPAD;
					end
					
					WRITE_SPAD:begin
						if(filt_count == (kernel_size**2)) begin
							w_data_spad <= r_data_glb_wght;
							filt_count <= 0;
							r_addr_glb_wght <= W_READ_ADDR;
							
							state <= IDLE;
						end else begin
							w_data_spad <= r_data_glb_wght;
							filt_count <= filt_count + 1;
							r_addr_glb_wght <= r_addr_glb_wght + 1;
							state <= WRITE_SPAD;
						end
					end
				endcase
			end
		end
 
endmodule


================================================
FILE: testbench/phase_1/router_weight_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/01/2019 07:02:07 PM
// Design Name: 
// Module Name: router_weight_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_weight_tb();

	parameter DATA_BITWIDTH = 16;
	parameter ADDR_BITWIDTH = 10;
	
	// GLB Cluster parameters. This TestBench uses only 1 of each
    parameter NUM_GLB_IACT = 1;
    parameter NUM_GLB_PSUM = 1;
	parameter NUM_GLB_WGHT = 1;
	
	
    logic clk;
    logic reset;

	//logic for GLB cluster
    logic read_req_iact;
	logic read_req_psum;
	logic read_req_wght;
	
    logic write_en_iact;
	logic write_en_psum;
	logic write_en_wght;
	
    logic [ADDR_BITWIDTH-1 : 0] r_addr_iact;
    logic [ADDR_BITWIDTH-1 : 0] r_addr_psum;
	logic [ADDR_BITWIDTH-1 : 0] r_addr_wght;
	
    logic [ADDR_BITWIDTH-1 : 0] w_addr_iact;
    logic [ADDR_BITWIDTH-1 : 0] w_addr_psum;
	logic [ADDR_BITWIDTH-1 : 0] w_addr_wght;
	
    logic [DATA_BITWIDTH-1 : 0] w_data_iact;
    logic [DATA_BITWIDTH-1 : 0] w_data_psum;
	logic [DATA_BITWIDTH-1 : 0] w_data_wght;
	
    logic [DATA_BITWIDTH-1 : 0] r_data_iact;
    logic [DATA_BITWIDTH-1 : 0] r_data_psum;
    logic [DATA_BITWIDTH-1 : 0] r_data_wght;

	
	//GLB cluster initialization
	GLB_cluster 
			#(	.DATA_BITWIDTH(DATA_BITWIDTH),
				.ADDR_BITWIDTH(ADDR_BITWIDTH),
				.NUM_GLB_IACT(NUM_GLB_IACT),
				.NUM_GLB_PSUM(NUM_GLB_PSUM),
				.NUM_GLB_WGHT(NUM_GLB_WGHT)
			)
	GLB_cluster_0
			(
				.clk(clk), 
				.reset(reset),
				
				.read_req_iact(read_req_iact),
				.read_req_psum(read_req_psum),
//				.read_req_wght(read_req_wght),
				.read_req_wght(router_weight_0.read_req_glb_wght),
				
				.write_en_iact(write_en_iact),
				.write_en_psum(write_en_psum),
				.write_en_wght(write_en_wght),
				
				.r_addr_iact(r_addr_iact),
			    .r_addr_psum(r_addr_psum),
//				.r_addr_wght(r_addr_wght),
				.r_addr_wght(router_weight_0.r_addr_glb_wght),

			    .w_addr_iact(w_addr_iact),
			    .w_addr_psum(w_addr_psum),
				.w_addr_wght(w_addr_wght),

			    .w_data_iact(w_data_iact),
			    .w_data_psum(w_data_psum),
				.w_data_wght(w_data_wght),

			    .r_data_iact(r_data_iact),
			    .r_data_psum(r_data_psum),
//				.r_data_wght(r_data_wght)
				.r_data_wght(router_weight_0.r_data_glb_wght)
			);

			
	//Declarations for weight router
	parameter ADDR_BITWIDTH_GLB = 10;
	parameter ADDR_BITWIDTH_SPAD = 9;
	
	parameter int kernel_size = 3;
	parameter int act_size = 5;
	
	parameter W_READ_ADDR = 0;
	
	parameter W_LOAD_ADDR = 0;
	
	parameter PSUM_READ_ADDR = 500;
	parameter PSUM_LOAD_ADDR = 0;
	
	logic [ADDR_BITWIDTH_SPAD-1 : 0] w_addr_spad;
	logic [DATA_BITWIDTH-1 : 0] w_data_spad;
	
	logic [DATA_BITWIDTH-1 : 0] r_data_glb_wght;
	
	logic load_en_spad;
	
	logic load_spad_ctrl;
	
			
	//Weight Router Instantiation
	router_weight #(.DATA_BITWIDTH(DATA_BITWIDTH),
					.ADDR_BITWIDTH_GLB(ADDR_BITWIDTH_GLB),
					.ADDR_BITWIDTH_SPAD(ADDR_BITWIDTH_SPAD),
//					X_dim = 5,
//	                Y_dim = 3,
	                .kernel_size(kernel_size),
	                .act_size(act_size),
					
					.W_READ_ADDR(W_READ_ADDR), 
	                .W_LOAD_ADDR(W_LOAD_ADDR),
					
					.PSUM_READ_ADDR(PSUM_READ_ADDR),
					.PSUM_LOAD_ADDR(PSUM_LOAD_ADDR)
				)
	router_weight_0
				(	.clk(clk),
					.reset(reset),
					
					.r_data_glb_wght(GLB_cluster_0.r_data_wght),
//					read_wght_ctrl,
					 .r_addr_glb_wght(GLB_cluster_0.r_addr_wght),
					 .read_req_glb_wght(GLB_cluster_0.read_req_wght),
					
					//for writing to spad
//					write_wght_ctrl,
//					.w_addr_spad(w_addr_spad),
					.w_data_spad(w_data_spad),
					.load_en_spad(load_en_spad),
					
					//Input from control unit to load weights to spad
					.load_spad_ctrl(load_spad_ctrl)
				);
	
	
	
	integer clk_prd = 10;
	
	always begin
		clk = 0; #(clk_prd/2);
		clk = 1; #(clk_prd/2);
		//0.1GHz
	end
	
	integer kernel_1,act_1;
	integer w_addr = 0;
	int args;
	
	initial begin
		reset = 1; #30;
		reset = 0;
		

		//Write weights to weight glb
		write_en_wght = 1;
		kernel_1 = $fopen("kernel_3x3.txt","r");		
		while(!$feof(kernel_1))begin
			w_addr_wght = w_addr;
			args = $fscanf(kernel_1,"%d\n",w_data_wght);
			$display("Writing value %0d to address %0d in weight glb",w_data_wght,w_addr);
			w_addr++;
			#(clk_prd);
		end
		write_en_wght = 0;
		$fclose(kernel_1); 
		
		
		//Write activations to weight glb
		write_en_iact = 1;
		w_addr = 0;
		act_1 = $fopen("act_5x5.txt","r");
		while(!$feof(act_1))begin
			w_addr_iact = w_addr;
			args = $fscanf(act_1,"%d\n",w_data_iact);
			$display("Writing value %0d to address %0d in iact glb",w_data_iact,w_addr);
			w_addr++;
			#(clk_prd);
		end
		write_en_iact = 0;
		$fclose(act_1); 
		
		#30;
		load_spad_ctrl = 1; #15;
		load_spad_ctrl = 0;
	
	end
	
endmodule



================================================
FILE: testbench/phase_2/HMNoC_cluster_west_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/10/2019 01:41:06 PM
// Design Name: 
// Module Name: HMNoC_cluster_west_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module HMNoC_cluster_west_tb();

		parameter DATA_BITWIDTH = 16;
		parameter ADDR_BITWIDTH = 10;
		
		parameter DATA_WIDTH = 16;
		parameter ADDR_WIDTH = 9;
		
		// GLB Cluster parameters. This TestBench uses only 1 of each
		parameter NUM_GLB_IACT = 1;
		parameter NUM_GLB_PSUM = 1;
		parameter NUM_GLB_WGHT = 1;
		
		parameter ADDR_BITWIDTH_GLB = 10;
		parameter ADDR_BITWIDTH_SPAD = 9;
		
		parameter NUM_ROUTER_PSUM = 1;
		parameter NUM_ROUTER_IACT = 1;
		parameter NUM_ROUTER_WGHT = 1;
				
		parameter int kernel_size = 3;
		parameter int act_size = 5;
		
		parameter int X_dim = 3;
		parameter int Y_dim = 3;
		
		parameter W_READ_ADDR = 0; 
		parameter A_READ_ADDR = 0;
		
		parameter W_LOAD_ADDR = 0;  
		parameter A_LOAD_ADDR = 0;
		
		parameter PSUM_READ_ADDR = 0;
		parameter PSUM_LOAD_ADDR = 0;

		
		// Logic
		logic clk;
		logic reset;
		
		//PE Cluster Interface
		logic start;
		logic load_done;
		
		logic load_en_wght;
		logic load_en_act;
		
        logic [DATA_WIDTH-1:0] pe_out[X_dim-1:0];
		logic compute_done;
		
		
		
		//GLB Cluster Interface

		logic write_en_iact;
		logic write_en_wght;
		
		logic [DATA_WIDTH-1:0] w_data_iact;
		logic [ADDR_WIDTH-1:0] w_addr_iact;
		
		logic [DATA_WIDTH-1:0] w_data_wght;
		logic [ADDR_WIDTH-1:0] w_addr_wght;
		
		logic [DATA_WIDTH-1:0] r_data_psum;
		logic [ADDR_WIDTH-1:0] r_addr_psum;
		
		logic [ADDR_WIDTH-1:0] w_addr_psum;
		
		logic read_req_iact;
		logic read_req_psum;
		logic read_req_wght;
		
		logic [ADDR_WIDTH-1:0] r_addr_iact;
		logic [ADDR_WIDTH-1:0] r_addr_wght;
		
		
		
		//WGHT Router Ports
		logic [3:0] router_mode_wght;
		
		//Interface with North
		//Source ports
		logic [DATA_WIDTH-1:0] north_data_i_wght;
		logic north_enable_i_wght;
		
		//Destination ports
		logic [DATA_WIDTH-1:0] north_data_o_wght;
		logic north_enable_o_wght;
		
		
		//Interface with South
		//Source ports
		logic [DATA_WIDTH-1:0] south_data_i_wght;
		logic south_enable_i_wght;
		
		//Destination ports
		logic [DATA_WIDTH-1:0] south_data_o_wght;
		logic south_enable_o_wght;
		
		
		//Interface with West
		//Source ports
//		logic [DATA_WIDTH-1:0] west_data_i_wght;
		logic west_enable_i_wght;
		
		//Destination ports
//		logic logic [DATA_WIDTH-1:0] west_data_o_wght;
		logic west_enable_o_wght;
		
		
		//Interface with East - Devices
		//Source ports
		logic [DATA_WIDTH-1:0] east_data_i_wght;
		logic east_enable_i_wght;
		
		//Destination ports
		logic [DATA_WIDTH-1:0] east_data_o_wght;
		logic east_enable_o_wght;
		
	//IACT Router Ports
		logic [3:0] router_mode_iact;
		
		//Interface with North
		//Source ports
		logic [DATA_WIDTH-1:0] north_data_i_iact;
		logic north_enable_i_iact;
		
		//Destination ports
		logic [DATA_WIDTH-1:0] north_data_o_iact;
		logic north_enable_o_iact;
		
		
		//Interface with South
		//Source ports
		logic [DATA_WIDTH-1:0] south_data_i_iact;
		logic south_enable_i_iact;
		
		//Destination ports
		logic [DATA_WIDTH-1:0] south_data_o_iact;
		logic south_enable_o_iact;
		
		
		//Interface with West
		//Source ports
//		logic [DATA_WIDTH-1:0] west_data_i_iact;
		logic west_enable_i_iact;
		
		//Destination ports
//		logic logic [DATA_WIDTH-1:0] west_data_o_iact;
		logic west_enable_o_iact;
		
		
		//Interface with East - Devices
		//Source ports
		logic [DATA_WIDTH-1:0] east_data_i_iact;
		logic east_enable_i_iact;
		
		//Destination ports
		logic [DATA_WIDTH-1:0] east_data_o_iact;
		logic east_enable_o_iact;
		
	
	//PSUM Router Ports
		logic [3:0] router_mode_psum;
		
		//Interface with North
		//Source ports
		logic [DATA_WIDTH-1:0] north_data_i_psum;
		logic north_enable_i_psum;
		
		//Destination ports
		logic [DATA_WIDTH-1:0] north_data_o_psum;
		logic north_enable_o_psum;
		
		
		//Interface with South
		//Source ports
		logic [DATA_WIDTH-1:0] south_data_i_psum;
		logic south_enable_i_psum;
		
		//Destination ports
		logic [DATA_WIDTH-1:0] south_data_o_psum;
		logic south_enable_o_psum;
		
		
		//Interface with West
		//Source ports
		logic [DATA_WIDTH-1:0] west_data_i_psum;
		logic west_enable_i_psum;
		
		//Destination ports
		logic [DATA_WIDTH-1:0] west_data_o_psum;
		logic west_enable_o_psum;
		
		//Interface with East - Devices
		//Source ports
		logic [DATA_WIDTH-1:0] east_data_i_psum;
		logic east_enable_i_psum;
		
		//Destination ports
		logic [DATA_WIDTH-1:0] east_data_o_psum;
		logic east_enable_o_psum;
		
		
		
	//Instantiation
	HMNoC_cluster_west 
		#(
			.DATA_BITWIDTH(DATA_BITWIDTH),
			.ADDR_BITWIDTH(ADDR_BITWIDTH),
			
			.DATA_WIDTH(DATA_WIDTH),
			.ADDR_WIDTH(ADDR_WIDTH),
			
			.NUM_GLB_IACT(NUM_GLB_IACT),
			.NUM_GLB_PSUM(NUM_GLB_PSUM),
			.NUM_GLB_WGHT(NUM_GLB_WGHT),

			.kernel_size(kernel_size),
			.act_size(act_size),
			
			.X_dim(X_dim),
			.Y_dim(Y_dim)
		)
	HMNoC_cluster_west_0 
		(
			.clk(clk),   //TestBench/Controller
			.reset(reset),  //TestBench/Controller
			
			//Signals for reading from GLB
			.read_req_iact(read_req_iact),
			.read_req_psum(read_req_psum), //Read by testbench/controller
			.read_req_wght(read_req_wght),
			
//			.r_data_iact(router_cluster_0.r_data_glb_iact),
			.r_data_psum(r_data_psum), //Read by testbench/controller
//			.r_data_wght(router_cluster_0.r_data_glb_wght),
			
			.r_addr_iact(r_addr_iact),
			.r_addr_psum(r_addr_psum), //testbench for reading final psums
			.r_addr_wght(r_addr_wght),

			//Signals for writing to GLB
			.w_addr_iact(w_addr_iact), //testbench for writing
			.w_addr_psum(w_addr_psum),
			.w_addr_wght(w_addr_wght), //testbench for writing

			.w_data_iact(w_data_iact), //testbench for writing
//			.w_data_psum(router_cluster_0.w_data_glb_psum),
			.w_data_wght(w_data_wght), //testbench for writing

			.write_en_iact(write_en_iact), //testbench for writing
//			.write_en_psum(router_cluster_0.write_en_glb_psum),
			.write_en_wght(write_en_wght), //testbench for writing
				
				
	
			//Ports for WGHT router
			.router_mode_wght(router_mode_wght), //TB*
			
			//Interface with North
			//Source ports
			.north_data_i_wght(north_data_i_wght),
			.north_enable_i_wght(north_enable_i_wght),
			
			//Destination ports
			.north_data_o_wght(north_data_o_wght),
			.north_enable_o_wght(north_enable_o_wght),
			
			
			//Interface with South
			//Source ports
			.south_data_i_wght(south_data_i_wght),
			.south_enable_i_wght(south_enable_i_wght),
			
			//Destination ports
			.south_data_o_wght(south_data_o_wght),
			.south_enable_o_wght(south_enable_o_wght),
			
			
			//Interface with West
			//Source ports
//			.west_data_i_wght(GLB_cluster_0.r_data_wght), //GLB_cluster
			.west_enable_i_wght(west_enable_i_wght),
			
			//Destination ports
//			.west_data_o_wght(pe_cluster_0.filt_in),  //PE_cluster
			.west_enable_o_wght(west_enable_o_wght),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_wght(east_data_i_wght),
			.east_enable_i_wght(east_enable_i_wght),
	        
			//Destination ports
	        .east_data_o_wght(east_data_o_wght),
            .east_enable_o_wght(east_enable_o_wght),
			
		////////////////////////////////////////////
			
		//Ports for IACT router
			.router_mode_iact(router_mode_iact),  //TB*
			
			//Interface with North
			//Source ports
			.north_data_i_iact(north_data_i_iact),
			.north_enable_i_iact(north_enable_i_iact),
			
			//Destination ports
			.north_data_o_iact(north_data_o_iact),
			.north_enable_o_iact(north_enable_o_iact),
			
			
			//Interface with South
			//Source ports
			.south_data_i_iact(south_data_i_iact),
			.south_enable_i_iact(south_enable_i_iact),
			
			//Destination ports
			.south_data_o_iact(south_data_o_iact),
			.south_enable_o_iact(south_enable_o_iact),
			
			
			//Interface with West
			//Source ports
//			.west_data_i_iact(GLB_cluster_0.r_data_iact),   //GLB_cluster
			.west_enable_i_iact(west_enable_i_iact),
			
			//Destination ports
//			.west_data_o_iact(pe_cluster_0.act_in),  //PE_cluster
			.west_enable_o_iact(west_enable_o_iact),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_iact(east_data_i_iact),
			.east_enable_i_iact(east_enable_i_iact),
	        
			//Destination ports
	        .east_data_o_iact(east_data_o_iact),
            .east_enable_o_iact(east_enable_o_iact),
			
			
		////////////////////////////////////////////
			
		//Ports for PSUM router
			.router_mode_psum(router_mode_psum),
			
			//Interface with North
			//Source ports
			.north_data_i_psum(north_data_i_psum),
			.north_enable_i_psum(north_enable_i_psum),
			
			//Destination ports
			.north_data_o_psum(north_data_o_psum),
			.north_enable_o_psum(north_enable_o_psum),
			
			
			//Interface with South
			//Source ports
			.south_data_i_psum(south_data_i_psum),
			.south_enable_i_psum(south_enable_i_psum),
			
			//Destination ports
			.south_data_o_psum(south_data_o_psum),
			.south_enable_o_psum(south_enable_o_psum),
			
			
			//Interface with West
			//Source ports
			.west_data_i_psum(west_data_i_psum), //PE_cluster
			.west_enable_i_psum(west_enable_i_psum),
			
			//Destination ports
//			.west_data_o_psum(GLB_cluster_0.w_data_psum), //GLB_cluster
//			.west_enable_o_psum(GLB_cluster_0.write_en_psum), //GLB_cluster
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_psum(east_data_i_psum),
			.east_enable_i_psum(east_enable_i_psum),
	        
			//Destination ports
	        .east_data_o_psum(east_data_o_psum),
            .east_enable_o_psum(east_enable_o_psum),
			
			
			
			//PE Cluster
			.load_en_wght(load_en_wght),
			.load_en_act(load_en_act),
			.start(start),
			.pe_out(pe_out),
			.compute_done(compute_done),
			.load_done(load_done)
		);
		
	
		//Logic for Direction
	enum logic [3:0] {ALL=0, NORTH=1, SOUTH=2, WEST=3, EAST=4,
						EASTNORTH=5, EASTSOUTH=6, EASTWEST=7,
						WESTNORTH=8, WESTSOUTH=9, WESTEAST=10} direction;
						
	integer clk_prd = 10;
	
	always begin
		clk = 0; #(clk_prd/2);
		clk = 1; #(clk_prd/2);
		//0.1GHz
	end
	
	integer kernel_1,act_1,psum_1;
	integer w_addr = 0;
	int args;
	
	logic [DATA_WIDTH-1:0] cluster_out_1[0:8];
	
	initial begin
		reset = 1; #30;
		reset = 0;
		start = 0;
		
		//Write weights to weight glb
/* 		write_en_wght = 1;
		kernel_1 = $fopen("kernel_3x3.txt","r");		
		while(!$feof(kernel_1))begin
			w_addr_wght = w_addr;
			args = $fscanf(kernel_1,"%d\n",w_data_wght);
			$display("Writing value %0d to address %0d in weight glb",w_data_wght,w_addr);
			w_addr++;
			#(clk_prd);
		end
		write_en_wght = 0;
		$fclose(kernel_1); 
		
		
		//Write activations to weight glb
		write_en_iact = 1;
		w_addr = 0;
		act_1 = $fopen("act_5x5.txt","r");
		while(!$feof(act_1))begin
			w_addr_iact = w_addr;
			args = $fscanf(act_1,"%d\n",w_data_iact);
			$display("Writing value %0d to address %0d in iact glb",w_data_iact,w_addr);
			w_addr++;
			#(clk_prd);
		end
		write_en_iact = 0;
		$fclose(act_1);  */
		
		//Write weights to weight glb
 		write_en_wght = 1;		
		for(int i=0; i<kernel_size**2;i++) begin
			w_data_wght = 1;
			w_addr_wght = i;
			#(clk_prd);
		end
		write_en_wght = 0;
	
		//Write activations to weight glb
		write_en_iact = 1;
		for(int i=0; i<act_size**2;i++) begin
			w_data_iact = i+1;
			w_addr_iact = i;
			#(clk_prd);
		end
		write_en_iact = 0;

		
		
		#(clk_prd);
	
//		assign west_data_o_wght = router_cluster_0.west_data_o_wght;
		
		$display("\n\nLoading Begins: Weights.....\n\n");
			read_req_wght = 1;
			r_addr_wght	= 0;
			#(clk_prd);
			
			west_enable_i_wght = 1;
			router_mode_wght = WEST;
			
			
		//Filter
			load_en_wght = 1;
			for(int i=1; i<=kernel_size**2; i++) begin
				r_addr_wght = i; #(clk_prd);
//				$display("Weight Read: %d",west_data_o_wght);
				load_en_wght = 0;
			end
		
		read_req_wght = 0;
		west_enable_i_wght = 0;
		
		#(clk_prd);
		
		
		$display("\n\nLoading Begins: Activations.....\n\n");
			
			read_req_iact = 1;
			r_addr_iact	= 0;
			#(clk_prd);
			
			west_enable_i_iact = 1;
			router_mode_iact = WEST;
			load_en_act = 1;
			
		//Filter
			for(int i=1; i<=act_size**2; i++) begin
				r_addr_iact = i; #(clk_prd);
				load_en_act = 0;
			end
		
		read_req_iact = 0;	
		west_enable_i_iact = 0;
		
		#(clk_prd);
	
	
	end	

endmodule


================================================
FILE: testbench/phase_2/router_cluster_new_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/10/2019 03:55:23 AM
// Design Name: 
// Module Name: router_cluster_new_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_cluster_new_tb();

	parameter DATA_WIDTH = 16;
	
	
//Logic for WGHTs
	
	logic [3:0] router_mode_wght;
	
	//Interface with North
	//Source ports
	logic [DATA_WIDTH-1:0] north_data_i_wght;
	logic north_enable_i_wght;

	//Destination ports
	logic  [DATA_WIDTH-1:0] north_data_o_wght;
	logic  north_enable_o_wght;
	
	
	//Interface with South
	//Source ports
	logic [DATA_WIDTH-1:0] south_data_i_wght;
	logic south_enable_i_wght;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] south_data_o_wght;
	logic south_enable_o_wght;
	
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i_wght;
	logic west_enable_i_wght;
	
	//Destination ports
	logic  [DATA_WIDTH-1:0] west_data_o_wght;
	logic  west_enable_o_wght;
	

    //Interface with East - Devices
    //Source ports
    logic [DATA_WIDTH-1:0] east_data_i_wght;
    logic east_enable_i_wght;

    //Destination ports
    logic  [DATA_WIDTH-1:0] east_data_o_wght;
    logic  east_enable_o_wght;
	
	
//Logic for IACTs
	logic [3:0] router_mode_iact;
	
	//Interface with North
	//Source ports
	logic [DATA_WIDTH-1:0] north_data_i_iact;
	logic north_enable_i_iact;

	//Destination ports
	logic  [DATA_WIDTH-1:0] north_data_o_iact;
	logic  north_enable_o_iact;
	
	
	//Interface with South
	//Source ports
	logic [DATA_WIDTH-1:0] south_data_i_iact;
	logic south_enable_i_iact;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] south_data_o_iact;
	logic south_enable_o_iact;
	
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i_iact;
	logic west_enable_i_iact;
	
	//Destination ports
	logic  [DATA_WIDTH-1:0] west_data_o_iact;
	logic  west_enable_o_iact;
	

    //Interface with East - Devices
    //Source ports
    logic [DATA_WIDTH-1:0] east_data_i_iact;
    logic east_enable_i_iact;

    //Destination ports
    logic  [DATA_WIDTH-1:0] east_data_o_iact;
    logic  east_enable_o_iact;
	
	
//Logic for PSUM
	
	logic [3:0] router_mode_psum;
	
	//Interface with North
	//Source ports
	logic [DATA_WIDTH-1:0] north_data_i_psum;
	logic north_enable_i_psum;

	//Destination ports
	logic  [DATA_WIDTH-1:0] north_data_o_psum;
	logic  north_enable_o_psum;
	
	
	//Interface with South
	//Source ports
	logic [DATA_WIDTH-1:0] south_data_i_psum;
	logic south_enable_i_psum;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] south_data_o_psum;
	logic south_enable_o_psum;
	
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i_psum;
	logic west_enable_i_psum;
	
	//Destination ports
	logic  [DATA_WIDTH-1:0] west_data_o_psum;
	logic  west_enable_o_psum;
	

    //Interface with East - Devices
    //Source ports
    logic [DATA_WIDTH-1:0] east_data_i_psum;
    logic east_enable_i_psum;

    //Destination ports
    logic  [DATA_WIDTH-1:0] east_data_o_psum;
    logic  east_enable_o_psum;
	
	
	//Other logic
	//Instantiation
	enum logic [3:0] {ALL=0, NORTH=1, SOUTH=2, WEST=3, EAST=4,
						EASTNORTH=5, EASTSOUTH=6, EASTWEST=7,
						WESTNORTH=8, WESTSOUTH=9, WESTEAST=10} direction;
	
	router_cluster
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_cluster_0
		(
		
		//Ports for WGHT router
			.router_mode_wght(router_mode_wght),
			
			//Interface with North
			//Source ports
			.north_data_i_wght(north_data_i_wght),
			.north_enable_i_wght(north_enable_i_wght),
			
			//Destination ports
			.north_data_o_wght(north_data_o_wght),
			.north_enable_o_wght(north_enable_o_wght),
			
			
			//Interface with South
			//Source ports
			.south_data_i_wght(south_data_i_wght),
			.south_enable_i_wght(south_enable_i_wght),
			
			//Destination ports
			.south_data_o_wght(south_data_o_wght),
			.south_enable_o_wght(south_enable_o_wght),
			
			
			//Interface with West
			//Source ports
			.west_data_i_wght(GLB_cluster_0.r_data_wght),
			.west_enable_i_wght(west_enable_i_wght),
			
			//Destination ports
			.west_data_o_wght(west_data_o_wght),
			.west_enable_o_wght(west_enable_o_wght),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_wght(east_data_i_wght),
			.east_enable_i_wght(east_enable_i_wght),
	        
			//Destination ports
	        .east_data_o_wght(east_data_o_wght),
            .east_enable_o_wght(east_enable_o_wght),
			
		////////////////////////////////////////////
			
		//Ports for IACT router
			.router_mode_iact(router_mode_iact),
			
			//Interface with North
			//Source ports
			.north_data_i_iact(north_data_i_iact),
			.north_enable_i_iact(north_enable_i_iact),
			
			//Destination ports
			.north_data_o_iact(north_data_o_iact),
			.north_enable_o_iact(north_enable_o_iact),
			
			
			//Interface with South
			//Source ports
			.south_data_i_iact(south_data_i_iact),
			.south_enable_i_iact(south_enable_i_iact),
			
			//Destination ports
			.south_data_o_iact(south_data_o_iact),
			.south_enable_o_iact(south_enable_o_iact),
			
			
			//Interface with West
			//Source ports
			.west_data_i_iact(GLB_cluster_0.r_data_iact),
			.west_enable_i_iact(west_enable_i_iact),
			
			//Destination ports
			.west_data_o_iact(west_data_o_iact),
			.west_enable_o_iact(west_enable_o_iact),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_iact(east_data_i_iact),
			.east_enable_i_iact(east_enable_i_iact),
	        
			//Destination ports
	        .east_data_o_iact(east_data_o_iact),
            .east_enable_o_iact(east_enable_o_iact),
			
			
		////////////////////////////////////////////
			
		//Ports for PSUM router
			.router_mode_psum(router_mode_psum),
			
			//Interface with North
			//Source ports
			.north_data_i_psum(north_data_i_psum),
			.north_enable_i_psum(north_enable_i_psum),
			
			//Destination ports
			.north_data_o_psum(north_data_o_psum),
			.north_enable_o_psum(north_enable_o_psum),
			
			
			//Interface with South
			//Source ports
			.south_data_i_psum(south_data_i_psum),
			.south_enable_i_psum(south_enable_i_psum),
			
			//Destination ports
			.south_data_o_psum(south_data_o_psum),
			.south_enable_o_psum(south_enable_o_psum),
			
			
			//Interface with West
			//Source ports
			.west_data_i_psum(west_data_i_psum),
			.west_enable_i_psum(west_enable_i_psum),
			
			//Destination ports
			.west_data_o_psum(GLB_cluster_0.w_data_psum),
			.west_enable_o_psum(GLB_cluster_0.write_en_psum),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_psum(east_data_i_psum),
			.east_enable_i_psum(east_enable_i_psum),
	        
			//Destination ports
	        .east_data_o_psum(east_data_o_psum),
            .east_enable_o_psum(east_enable_o_psum)	
	);
	
	
    parameter DATA_BITWIDTH = 16;
	parameter ADDR_BITWIDTH = 10;
    parameter NUM_GLB_IACT = 1;
    parameter NUM_GLB_PSUM = 1;
	parameter NUM_GLB_WGHT = 1;
	
    logic clk;
    logic reset;

    logic read_req_iact; //[NUM_GLB_IACT-1:0];
	logic read_req_psum; //[NUM_GLB_PSUM-1:0];
	logic read_req_wght; //[NUM_GLB_WGHT-1:0];
	                    //
    logic write_en_iact; //[NUM_GLB_IACT-1:0];
	logic write_en_psum; //[NUM_GLB_PSUM-1:0];
	logic write_en_wght; //[NUM_GLB_WGHT-1:0];
	
    logic [ADDR_BITWIDTH-1 : 0] r_addr_iact; //[NUM_GLB_IACT-1:0];
    logic [ADDR_BITWIDTH-1 : 0] r_addr_psum; //[NUM_GLB_PSUM-1:0];
	logic [ADDR_BITWIDTH-1 : 0] r_addr_wght; //[NUM_GLB_WGHT-1:0];
	                                        //
    logic [ADDR_BITWIDTH-1 : 0] w_addr_iact; //[NUM_GLB_IACT-1:0];
    logic [ADDR_BITWIDTH-1 : 0] w_addr_psum; //[NUM_GLB_PSUM-1:0];
	logic [ADDR_BITWIDTH-1 : 0] w_addr_wght; //[NUM_GLB_WGHT-1:0];
	                                        //
    logic [DATA_BITWIDTH-1 : 0] w_data_iact; //[NUM_GLB_IACT-1:0];
    logic [DATA_BITWIDTH-1 : 0] w_data_psum; //[NUM_GLB_PSUM-1:0];
	logic [DATA_BITWIDTH-1 : 0] w_data_wght; //[NUM_GLB_WGHT-1:0];
	                                        //
    logic [DATA_BITWIDTH-1 : 0] r_data_iact; //[NUM_GLB_IACT-1:0];
    logic [DATA_BITWIDTH-1 : 0] r_data_psum; //[NUM_GLB_PSUM-1:0];
//    logic [DATA_BITWIDTH-1 : 0] r_data_wght[NUM_GLB_WGHT-1:0];

	GLB_cluster 
			#(	.DATA_BITWIDTH(DATA_BITWIDTH),
				.ADDR_BITWIDTH(ADDR_BITWIDTH),
				.NUM_GLB_IACT(NUM_GLB_IACT),
				.NUM_GLB_PSUM(NUM_GLB_PSUM),
				.NUM_GLB_WGHT(NUM_GLB_WGHT)
			)
	GLB_cluster_0
			(
				.clk(clk), 
				.reset(reset),
				
				.read_req_iact(read_req_iact),
				.read_req_psum(read_req_psum),
				.read_req_wght(read_req_wght),
				
				.write_en_iact(write_en_iact),
				.write_en_psum(router_cluster_0.west_enable_o_psum),
				.write_en_wght(write_en_wght),
				
				.r_addr_iact(r_addr_iact),
			    .r_addr_psum(r_addr_psum),
				.r_addr_wght(r_addr_wght),

			    .w_addr_iact(w_addr_iact),
			    .w_addr_psum(w_addr_psum),
				.w_addr_wght(w_addr_wght),

			    .w_data_iact(w_data_iact),
			    .w_data_psum(router_cluster_0.west_data_o_psum),
				.w_data_wght(w_data_wght),

			    .r_data_iact(router_cluster_0.west_data_i_iact),
			    .r_data_psum(r_data_psum),
				.r_data_wght(router_cluster_0.west_data_i_wght)
			);

	
	always begin
		clk = 0; #10;
		clk = 1; #10;
	end

	
	initial begin
		reset = 1; #30;
		reset = 0;
	
		write_en_iact = 1;
		write_en_psum = 1;
		write_en_wght = 1;
		
		for(int i=0; i<25; i++) begin
			w_addr_iact = i;
			w_data_iact = i*2;

/* 			w_addr_psum = i;
			w_data_psum = i; */
			
			w_addr_wght = i;
			w_data_wght = i*3;
			
			#20;
		end
		
		write_en_iact = 0;
		write_en_psum = 0;
		write_en_wght = 0;
		
		for(int i=0; i<2; i++) begin
			w_addr_iact = i;
			w_data_iact = i*200;

/* 			w_addr_psum = i;
			w_data_psum = i*200; */
			
			w_addr_wght = i;
			w_data_wght = i*200;			
			
			#20;
		end
		
		
/* 		read_req_iact = 1;
		read_req_psum = 1;
		read_req_wght = 1;
		
		west_enable_i_iact = 1;
		router_mode_iact = EAST;
		
		for(int i=0; i<4; i++  ) begin
			r_addr_iact = i;

			r_addr_psum = i;
			
			r_addr_wght = i;
			#20;
		end
		
		west_enable_i_iact = 0;
		west_enable_i_wght = 1;
		router_mode_wght = WESTNORTH;
		
		for(int i=4; i<8; i++  ) begin
			r_addr_iact = i;

			r_addr_psum = i;
			
			r_addr_wght = i;
			#20;
		end
		
		
		west_enable_i_wght = 0;
		west_enable_i_iact = 1;
		router_mode_iact = SOUTH;
		
		for(int i=8; i<12; i++  ) begin
			r_addr_iact = i;

			r_addr_psum = i;
			
			r_addr_wght = i;
			#20;
		end */
		
		
	//	write_en_psum = 1;
		//write_en_wght = 1;
		
		west_enable_i_psum = 1;
		router_mode_psum = WEST;
		#5;
		
		for(int i=0; i<8; i++) begin
			w_addr_psum = i;
			west_data_i_psum = i;
			#20;
		end
		#20;
		
		read_req_iact = 0;
		read_req_psum = 0;
		read_req_wght = 0;
		
		for(int i=0; i<2; i++) begin
			r_addr_iact = i;

			r_addr_psum = i;
			
			r_addr_wght = i;
			
			#20;
		end
		
	end

endmodule


================================================
FILE: testbench/phase_2/router_cluster_pe_cluster_5x5_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/13/2019 09:56:29 AM
// Design Name: 
// Module Name: router_cluster_pe_cluster_5x5_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_cluster_pe_cluster_5x5_tb();

	parameter DATA_WIDTH = 16;
	
	
//Logic for WGHTs
	
	logic [3:0] router_mode_wght;
	
	//Interface with North
	//Source ports
	logic [DATA_WIDTH-1:0] north_data_i_wght;
	logic north_enable_i_wght;

	//Destination ports
	logic  [DATA_WIDTH-1:0] north_data_o_wght;
	logic  north_enable_o_wght;
	
	
	//Interface with South
	//Source ports
	logic [DATA_WIDTH-1:0] south_data_i_wght;
	logic south_enable_i_wght;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] south_data_o_wght;
	logic south_enable_o_wght;
	
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i_wght;
	logic west_enable_i_wght;
	
	//Destination ports
	logic  [DATA_WIDTH-1:0] west_data_o_wght;
	logic  west_enable_o_wght;
	

    //Interface with East - Devices
    //Source ports
    logic [DATA_WIDTH-1:0] east_data_i_wght;
    logic east_enable_i_wght;

    //Destination ports
    logic  [DATA_WIDTH-1:0] east_data_o_wght;
    logic  east_enable_o_wght;
	
	
//Logic for IACTs
	logic [3:0] router_mode_iact;
	
	//Interface with North
	//Source ports
	logic [DATA_WIDTH-1:0] north_data_i_iact;
	logic north_enable_i_iact;

	//Destination ports
	logic  [DATA_WIDTH-1:0] north_data_o_iact;
	logic  north_enable_o_iact;
	
	
	//Interface with South
	//Source ports
	logic [DATA_WIDTH-1:0] south_data_i_iact;
	logic south_enable_i_iact;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] south_data_o_iact;
	logic south_enable_o_iact;
	
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i_iact;
	logic west_enable_i_iact;
	
	//Destination ports
	logic  [DATA_WIDTH-1:0] west_data_o_iact;
	logic  west_enable_o_iact;
	

    //Interface with East - Devices
    //Source ports
    logic [DATA_WIDTH-1:0] east_data_i_iact;
    logic east_enable_i_iact;

    //Destination ports
    logic  [DATA_WIDTH-1:0] east_data_o_iact;
    logic  east_enable_o_iact;
	
	
//Logic for PSUM
	
	logic [3:0] router_mode_psum;
	
	//Interface with North
	//Source ports
	logic [DATA_WIDTH-1:0] north_data_i_psum;
	logic north_enable_i_psum;

	//Destination ports
	logic  [DATA_WIDTH-1:0] north_data_o_psum;
	logic  north_enable_o_psum;
	
	
	//Interface with South
	//Source ports
	logic [DATA_WIDTH-1:0] south_data_i_psum;
	logic south_enable_i_psum;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] south_data_o_psum;
	logic south_enable_o_psum;
	
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i_psum;
	logic west_enable_i_psum;
	
	//Destination ports
	logic  [DATA_WIDTH-1:0] west_data_o_psum;
	logic  west_enable_o_psum;
	

    //Interface with East - Devices
    //Source ports
    logic [DATA_WIDTH-1:0] east_data_i_psum;
    logic east_enable_i_psum;

    //Destination ports
    logic  [DATA_WIDTH-1:0] east_data_o_psum;
    logic  east_enable_o_psum;
	
	
	//Other logic
	//Instantiation
	enum logic [3:0] {ALL=0, NORTH=1, SOUTH=2, WEST=3, EAST=4,
						EASTNORTH=5, EASTSOUTH=6, EASTWEST=7,
						WESTNORTH=8, WESTSOUTH=9, WESTEAST=10} direction;
	
	router_cluster
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_cluster_0
		(
		
		//Ports for WGHT router
			.router_mode_wght(router_mode_wght),
			
			//Interface with North
			//Source ports
			.north_data_i_wght(north_data_i_wght),
			.north_enable_i_wght(north_enable_i_wght),
			
			//Destination ports
			.north_data_o_wght(north_data_o_wght),
			.north_enable_o_wght(north_enable_o_wght),
			
			
			//Interface with South
			//Source ports
			.south_data_i_wght(south_data_i_wght),
			.south_enable_i_wght(south_enable_i_wght),
			
			//Destination ports
			.south_data_o_wght(south_data_o_wght),
			.south_enable_o_wght(south_enable_o_wght),
			
			
			//Interface with West
			//Source ports
			.west_data_i_wght(GLB_cluster_0.r_data_wght),
			.west_enable_i_wght(west_enable_i_wght),
			
			//Destination ports
			.west_data_o_wght(pe_cluster_0.filt_in),
			.west_enable_o_wght(west_enable_o_wght),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_wght(east_data_i_wght),
			.east_enable_i_wght(east_enable_i_wght),
	        
			//Destination ports
	        .east_data_o_wght(east_data_o_wght),
            .east_enable_o_wght(east_enable_o_wght),
			
		////////////////////////////////////////////
			
		//Ports for IACT router
			.router_mode_iact(router_mode_iact),
			
			//Interface with North
			//Source ports
			.north_data_i_iact(north_data_i_iact),
			.north_enable_i_iact(north_enable_i_iact),
			
			//Destination ports
			.north_data_o_iact(north_data_o_iact),
			.north_enable_o_iact(north_enable_o_iact),
			
			
			//Interface with South
			//Source ports
			.south_data_i_iact(south_data_i_iact),
			.south_enable_i_iact(south_enable_i_iact),
			
			//Destination ports
			.south_data_o_iact(south_data_o_iact),
			.south_enable_o_iact(south_enable_o_iact),
			
			
			//Interface with West
			//Source ports
			.west_data_i_iact(GLB_cluster_0.r_data_iact),
			.west_enable_i_iact(west_enable_i_iact),
			
			//Destination ports
			.west_data_o_iact(pe_cluster_0.act_in),
			.west_enable_o_iact(west_enable_o_iact),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_iact(east_data_i_iact),
			.east_enable_i_iact(east_enable_i_iact),
	        
			//Destination ports
	        .east_data_o_iact(east_data_o_iact),
            .east_enable_o_iact(east_enable_o_iact),
			
			
		////////////////////////////////////////////
			
		//Ports for PSUM router
			.router_mode_psum(router_mode_psum),
			
			//Interface with North
			//Source ports
			.north_data_i_psum(north_data_i_psum),
			.north_enable_i_psum(north_enable_i_psum),
			
			//Destination ports
			.north_data_o_psum(north_data_o_psum),
			.north_enable_o_psum(north_enable_o_psum),
			
			
			//Interface with South
			//Source ports
			.south_data_i_psum(south_data_i_psum),
			.south_enable_i_psum(south_enable_i_psum),
			
			//Destination ports
			.south_data_o_psum(south_data_o_psum),
			.south_enable_o_psum(south_enable_o_psum),
			
			
			//Interface with West
			//Source ports
			.west_data_i_psum(west_data_i_psum),
			.west_enable_i_psum(west_enable_i_psum),
			
			//Destination ports
			.west_data_o_psum(GLB_cluster_0.w_data_psum),
			.west_enable_o_psum(GLB_cluster_0.write_en_psum),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_psum(east_data_i_psum),
			.east_enable_i_psum(east_enable_i_psum),
	        
			//Destination ports
	        .east_data_o_psum(east_data_o_psum),
            .east_enable_o_psum(east_enable_o_psum)	
	);
	
	
    parameter DATA_BITWIDTH = 16;
	parameter ADDR_BITWIDTH = 10;
    parameter NUM_GLB_IACT = 1;
    parameter NUM_GLB_PSUM = 1;
	parameter NUM_GLB_WGHT = 1;
	
    logic clk;
    logic reset;

    logic read_req_iact; //[NUM_GLB_IACT-1:0];
	logic read_req_psum; //[NUM_GLB_PSUM-1:0];
	logic read_req_wght; //[NUM_GLB_WGHT-1:0];
	                    //
    logic write_en_iact; //[NUM_GLB_IACT-1:0];
	logic write_en_psum; //[NUM_GLB_PSUM-1:0];
	logic write_en_wght; //[NUM_GLB_WGHT-1:0];
	
    logic [ADDR_BITWIDTH-1 : 0] r_addr_iact; //[NUM_GLB_IACT-1:0];
    logic [ADDR_BITWIDTH-1 : 0] r_addr_psum; //[NUM_GLB_PSUM-1:0];
	logic [ADDR_BITWIDTH-1 : 0] r_addr_wght; //[NUM_GLB_WGHT-1:0];
	                                        //
    logic [ADDR_BITWIDTH-1 : 0] w_addr_iact; //[NUM_GLB_IACT-1:0];
    logic [ADDR_BITWIDTH-1 : 0] w_addr_psum; //[NUM_GLB_PSUM-1:0];
	logic [ADDR_BITWIDTH-1 : 0] w_addr_wght; //[NUM_GLB_WGHT-1:0];
	                                        //
    logic [DATA_BITWIDTH-1 : 0] w_data_iact; //[NUM_GLB_IACT-1:0];
    logic [DATA_BITWIDTH-1 : 0] w_data_psum; //[NUM_GLB_PSUM-1:0];
	logic [DATA_BITWIDTH-1 : 0] w_data_wght; //[NUM_GLB_WGHT-1:0];
	                                        //
    logic [DATA_BITWIDTH-1 : 0] r_data_iact; //[NUM_GLB_IACT-1:0];
    logic [DATA_BITWIDTH-1 : 0] r_data_psum; //[NUM_GLB_PSUM-1:0];
//    logic [DATA_BITWIDTH-1 : 0] r_data_wght[NUM_GLB_WGHT-1:0];

	GLB_cluster 
			#(	.DATA_BITWIDTH(DATA_BITWIDTH),
				.ADDR_BITWIDTH(ADDR_BITWIDTH),
				.NUM_GLB_IACT(NUM_GLB_IACT),
				.NUM_GLB_PSUM(NUM_GLB_PSUM),
				.NUM_GLB_WGHT(NUM_GLB_WGHT)
			)
	GLB_cluster_0
			(
				.clk(clk), 
				.reset(reset),
				
				.read_req_iact(read_req_iact),
				.read_req_psum(read_req_psum),
				.read_req_wght(read_req_wght),
				
				.write_en_iact(write_en_iact),
				.write_en_psum(router_cluster_0.west_enable_o_psum),
				.write_en_wght(write_en_wght),
				
				.r_addr_iact(r_addr_iact),
			    .r_addr_psum(r_addr_psum),
				.r_addr_wght(r_addr_wght),

			    .w_addr_iact(w_addr_iact),
			    .w_addr_psum(w_addr_psum),
				.w_addr_wght(w_addr_wght),

			    .w_data_iact(w_data_iact),
			    .w_data_psum(router_cluster_0.west_data_o_psum),
				.w_data_wght(w_data_wght),

			    .r_data_iact(router_cluster_0.west_data_i_iact),
			    .r_data_psum(r_data_psum),
				.r_data_wght(router_cluster_0.west_data_i_wght)
			);
			
	//	parameter DATA_WIDTH = 16;
    parameter ADDR_WIDTH = 9;
    
    parameter int X_dim = 5;
    parameter int Y_dim = 5;
    
    parameter int kernel_size = 5;
    parameter int act_size = 7;
    
    parameter W_READ_ADDR = 0;  
    parameter A_READ_ADDR = 100;
    
    parameter W_LOAD_ADDR = 0;  
    parameter A_LOAD_ADDR = 100;
    
    parameter PSUM_ADDR = 500;
	
    logic [DATA_WIDTH-1:0] act_in;
    logic [DATA_WIDTH-1:0] filt_in;

	logic start;
	logic load_en_wght, load_en_act;

    logic [DATA_WIDTH-1:0] pe_out[X_dim-1:0];
  
	logic compute_done;
	
	
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_0
    			(
					.clk(clk),
				    .reset(reset),
				    .act_in(router_cluster_0.west_data_o_iact),
				    .filt_in(router_cluster_0.west_data_o_wght),
					.load_en_wght(load_en_wght),
					.load_en_act(load_en_act),
					.start(start),
                    .pe_out(pe_out),
					.compute_done(compute_done),
					.load_done(load_done)
    			);

				
	integer clk_prd = 10;
	
	always begin
		clk = 0; #(clk_prd/2);
		clk = 1; #(clk_prd/2);
		//0.1GHz
	end
	
	integer kernel_1,act_1,psum_1;
	integer w_addr = 0;
	int args;
	
	logic [DATA_WIDTH-1:0] cluster_out_1[0:8];
	
	initial begin
		reset = 1; #30;
		reset = 0;
		start = 0;
		
		//Write weights to weight glb
/* 		write_en_wght = 1;
		kernel_1 = $fopen("kernel_3x3.txt","r");		
		while(!$feof(kernel_1))begin
			w_addr_wght = w_addr;
			args = $fscanf(kernel_1,"%d\n",w_data_wght);
			$display("Writing value %0d to address %0d in weight glb",w_data_wght,w_addr);
			w_addr++;
			#(clk_prd);
		end
		write_en_wght = 0;
		$fclose(kernel_1); 
		
		
		//Write activations to weight glb
		write_en_iact = 1;
		w_addr = 0;
		act_1 = $fopen("act_5x5.txt","r");
		while(!$feof(act_1))begin
			w_addr_iact = w_addr;
			args = $fscanf(act_1,"%d\n",w_data_iact);
			$display("Writing value %0d to address %0d in iact glb",w_data_iact,w_addr);
			w_addr++;
			#(clk_prd);
		end
		write_en_iact = 0;
		$fclose(act_1);  */
		
			//Write weights to weight glb
 		write_en_wght = 1;		
		for(int i=0; i<kernel_size**2;i++) begin
			w_data_wght = 1;
			w_addr_wght = i;
			#(clk_prd);
		end
		write_en_wght = 0;
	
		//Write activations to weight glb
		write_en_iact = 1;
		for(int i=0; i<act_size**2;i++) begin
			w_data_iact = i+1;
			w_addr_iact = i;
			#(clk_prd);
		end
		write_en_iact = 0;

		
	#(clk_prd);
	
	assign west_data_o_wght = router_cluster_0.west_data_o_wght;
	
	$display("\n\nLoading Begins: Weights.....\n\n");
		read_req_wght = 1;
		r_addr_wght	= 0;
		#(clk_prd);
		
		west_enable_i_wght = 1;
		router_mode_wght = WEST;
		
		
	//Filter
		load_en_wght = 1;
		for(int i=1; i<=kernel_size**2; i++) begin
			r_addr_wght = i; #(clk_prd);
			$display("Weight Read: %d",west_data_o_wght);
			load_en_wght = 0;
		end
	
	read_req_wght = 0;
	west_enable_i_wght = 0;
	
	#(clk_prd);
	
	
	$display("\n\nLoading Begins: Activations.....\n\n");
		
		read_req_iact = 1;
		r_addr_iact	= 0;
		#(clk_prd);
		
		west_enable_i_iact = 1;
		router_mode_iact = WEST;
		load_en_act = 1;
		
	//Filter
		for(int i=1; i<=act_size**2; i++) begin
			r_addr_iact = i; #(clk_prd);
			load_en_act = 0;
		end
	
	read_req_iact = 0;	
	west_enable_i_iact = 0;
	
	#(clk_prd);
		
		
	
// Control for PE cluster Computations
	
	
	//logic   [31:0] dpsram[0:16383]
		
		start = 1; #25; 
		$display("\n\nReading & Computing Begins.....\n\n");
		start = 0;
		
		wait (compute_done == 1);
		
		$display("\n\nFinal PSUM of Iteration 1");
 		for(int i=0; i<X_dim; i++) begin
			cluster_out_1[i] = pe_out[X_dim-i-1];
			$display("\npsum from column %d is:%d",i+1,pe_out[X_dim-i-1]);
		end
		
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 2.....\n\n");
		start = 0;
		
				wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 2:");
 		for(int i=0; i<X_dim; i++) begin
			cluster_out_1[i+5] = pe_out[X_dim-i-1];
			$display("\npsum from column %d is:%d",i+1,pe_out[X_dim-i-1]);
		end
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 3.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 3:");
 		for(int i=0; i<X_dim; i++) begin
		cluster_out_1[i+10] = pe_out[X_dim-i-1];
			$display("\npsum from column %d is:%d",i+1,pe_out[X_dim-i-1]);
		end
		
			#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 4.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 4:");
 		for(int i=0; i<X_dim; i++) begin
		cluster_out_1[i+15] = pe_out[X_dim-i-1];
			$display("\npsum from column %d is:%d",i+1,pe_out[X_dim-i-1]);
		end
		
			#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 5.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 5:");
 		for(int i=0; i<X_dim; i++) begin
		cluster_out_1[i+20] = pe_out[X_dim-i-1];
			$display("\npsum from column %d is:%d",i+1,pe_out[X_dim-i-1]);
		end
		
		
		$display("\tFinal psums of Cluster 1:\n");
		for(int a=0; a<kernel_size**2; a++) begin
			$display("\t\t %d \n",cluster_out_1[a]);
		end
		
		$display("\tTotal #cycles taken: %d",cycles);
		$stop;
	end

		int cycles;
		// track # of cycles
	always @(posedge clk)
	begin
		if (reset)
			cycles = 0;
		else
			cycles = cycles + 1;
end

endmodule


================================================
FILE: testbench/phase_2/router_cluster_pe_cluster_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/10/2019 08:31:24 AM
// Design Name: 
// Module Name: router_cluster_pe_cluster_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_cluster_pe_cluster_tb();

	parameter DATA_WIDTH = 16;
	
	
//Logic for WGHTs
	
	logic [3:0] router_mode_wght;
	
	//Interface with North
	//Source ports
	logic [DATA_WIDTH-1:0] north_data_i_wght;
	logic north_enable_i_wght;

	//Destination ports
	logic  [DATA_WIDTH-1:0] north_data_o_wght;
	logic  north_enable_o_wght;
	
	
	//Interface with South
	//Source ports
	logic [DATA_WIDTH-1:0] south_data_i_wght;
	logic south_enable_i_wght;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] south_data_o_wght;
	logic south_enable_o_wght;
	
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i_wght;
	logic west_enable_i_wght;
	
	//Destination ports
	logic  [DATA_WIDTH-1:0] west_data_o_wght;
	logic  west_enable_o_wght;
	

    //Interface with East - Devices
    //Source ports
    logic [DATA_WIDTH-1:0] east_data_i_wght;
    logic east_enable_i_wght;

    //Destination ports
    logic  [DATA_WIDTH-1:0] east_data_o_wght;
    logic  east_enable_o_wght;
	
	
//Logic for IACTs
	logic [3:0] router_mode_iact;
	
	//Interface with North
	//Source ports
	logic [DATA_WIDTH-1:0] north_data_i_iact;
	logic north_enable_i_iact;

	//Destination ports
	logic  [DATA_WIDTH-1:0] north_data_o_iact;
	logic  north_enable_o_iact;
	
	
	//Interface with South
	//Source ports
	logic [DATA_WIDTH-1:0] south_data_i_iact;
	logic south_enable_i_iact;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] south_data_o_iact;
	logic south_enable_o_iact;
	
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i_iact;
	logic west_enable_i_iact;
	
	//Destination ports
	logic  [DATA_WIDTH-1:0] west_data_o_iact;
	logic  west_enable_o_iact;
	

    //Interface with East - Devices
    //Source ports
    logic [DATA_WIDTH-1:0] east_data_i_iact;
    logic east_enable_i_iact;

    //Destination ports
    logic  [DATA_WIDTH-1:0] east_data_o_iact;
    logic  east_enable_o_iact;
	
	
//Logic for PSUM
	
	logic [3:0] router_mode_psum;
	
	//Interface with North
	//Source ports
	logic [DATA_WIDTH-1:0] north_data_i_psum;
	logic north_enable_i_psum;

	//Destination ports
	logic  [DATA_WIDTH-1:0] north_data_o_psum;
	logic  north_enable_o_psum;
	
	
	//Interface with South
	//Source ports
	logic [DATA_WIDTH-1:0] south_data_i_psum;
	logic south_enable_i_psum;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] south_data_o_psum;
	logic south_enable_o_psum;
	
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i_psum;
	logic west_enable_i_psum;
	
	//Destination ports
	logic  [DATA_WIDTH-1:0] west_data_o_psum;
	logic  west_enable_o_psum;
	

    //Interface with East - Devices
    //Source ports
    logic [DATA_WIDTH-1:0] east_data_i_psum;
    logic east_enable_i_psum;

    //Destination ports
    logic  [DATA_WIDTH-1:0] east_data_o_psum;
    logic  east_enable_o_psum;
	
	
	//Other logic
	//Instantiation
	enum logic [3:0] {ALL=0, NORTH=1, SOUTH=2, WEST=3, EAST=4,
						EASTNORTH=5, EASTSOUTH=6, EASTWEST=7,
						WESTNORTH=8, WESTSOUTH=9, WESTEAST=10} direction;
	
	router_cluster
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_cluster_0
		(
		
		//Ports for WGHT router
			.router_mode_wght(router_mode_wght),
			
			//Interface with North
			//Source ports
			.north_data_i_wght(north_data_i_wght),
			.north_enable_i_wght(north_enable_i_wght),
			
			//Destination ports
			.north_data_o_wght(north_data_o_wght),
			.north_enable_o_wght(north_enable_o_wght),
			
			
			//Interface with South
			//Source ports
			.south_data_i_wght(south_data_i_wght),
			.south_enable_i_wght(south_enable_i_wght),
			
			//Destination ports
			.south_data_o_wght(south_data_o_wght),
			.south_enable_o_wght(south_enable_o_wght),
			
			
			//Interface with West
			//Source ports
			.west_data_i_wght(GLB_cluster_0.r_data_wght),
			.west_enable_i_wght(west_enable_i_wght),
			
			//Destination ports
			.west_data_o_wght(pe_cluster_0.filt_in),
			.west_enable_o_wght(west_enable_o_wght),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_wght(east_data_i_wght),
			.east_enable_i_wght(east_enable_i_wght),
	        
			//Destination ports
	        .east_data_o_wght(east_data_o_wght),
            .east_enable_o_wght(east_enable_o_wght),
			
		////////////////////////////////////////////
			
		//Ports for IACT router
			.router_mode_iact(router_mode_iact),
			
			//Interface with North
			//Source ports
			.north_data_i_iact(north_data_i_iact),
			.north_enable_i_iact(north_enable_i_iact),
			
			//Destination ports
			.north_data_o_iact(north_data_o_iact),
			.north_enable_o_iact(north_enable_o_iact),
			
			
			//Interface with South
			//Source ports
			.south_data_i_iact(south_data_i_iact),
			.south_enable_i_iact(south_enable_i_iact),
			
			//Destination ports
			.south_data_o_iact(south_data_o_iact),
			.south_enable_o_iact(south_enable_o_iact),
			
			
			//Interface with West
			//Source ports
			.west_data_i_iact(GLB_cluster_0.r_data_iact),
			.west_enable_i_iact(west_enable_i_iact),
			
			//Destination ports
			.west_data_o_iact(pe_cluster_0.act_in),
			.west_enable_o_iact(west_enable_o_iact),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_iact(east_data_i_iact),
			.east_enable_i_iact(east_enable_i_iact),
	        
			//Destination ports
	        .east_data_o_iact(east_data_o_iact),
            .east_enable_o_iact(east_enable_o_iact),
			
			
		////////////////////////////////////////////
			
		//Ports for PSUM router
			.router_mode_psum(router_mode_psum),
			
			//Interface with North
			//Source ports
			.north_data_i_psum(north_data_i_psum),
			.north_enable_i_psum(north_enable_i_psum),
			
			//Destination ports
			.north_data_o_psum(north_data_o_psum),
			.north_enable_o_psum(north_enable_o_psum),
			
			
			//Interface with South
			//Source ports
			.south_data_i_psum(south_data_i_psum),
			.south_enable_i_psum(south_enable_i_psum),
			
			//Destination ports
			.south_data_o_psum(south_data_o_psum),
			.south_enable_o_psum(south_enable_o_psum),
			
			
			//Interface with West
			//Source ports
			.west_data_i_psum(west_data_i_psum),
			.west_enable_i_psum(west_enable_i_psum),
			
			//Destination ports
			.west_data_o_psum(GLB_cluster_0.w_data_psum),
			.west_enable_o_psum(GLB_cluster_0.write_en_psum),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_psum(east_data_i_psum),
			.east_enable_i_psum(east_enable_i_psum),
	        
			//Destination ports
	        .east_data_o_psum(east_data_o_psum),
            .east_enable_o_psum(east_enable_o_psum)	
	);
	
	
    parameter DATA_BITWIDTH = 16;
	parameter ADDR_BITWIDTH = 10;
    parameter NUM_GLB_IACT = 1;
    parameter NUM_GLB_PSUM = 1;
	parameter NUM_GLB_WGHT = 1;
	
    logic clk;
    logic reset;

    logic read_req_iact; //[NUM_GLB_IACT-1:0];
	logic read_req_psum; //[NUM_GLB_PSUM-1:0];
	logic read_req_wght; //[NUM_GLB_WGHT-1:0];
	                    //
    logic write_en_iact; //[NUM_GLB_IACT-1:0];
	logic write_en_psum; //[NUM_GLB_PSUM-1:0];
	logic write_en_wght; //[NUM_GLB_WGHT-1:0];
	
    logic [ADDR_BITWIDTH-1 : 0] r_addr_iact; //[NUM_GLB_IACT-1:0];
    logic [ADDR_BITWIDTH-1 : 0] r_addr_psum; //[NUM_GLB_PSUM-1:0];
	logic [ADDR_BITWIDTH-1 : 0] r_addr_wght; //[NUM_GLB_WGHT-1:0];
	                                        //
    logic [ADDR_BITWIDTH-1 : 0] w_addr_iact; //[NUM_GLB_IACT-1:0];
    logic [ADDR_BITWIDTH-1 : 0] w_addr_psum; //[NUM_GLB_PSUM-1:0];
	logic [ADDR_BITWIDTH-1 : 0] w_addr_wght; //[NUM_GLB_WGHT-1:0];
	                                        //
    logic [DATA_BITWIDTH-1 : 0] w_data_iact; //[NUM_GLB_IACT-1:0];
    logic [DATA_BITWIDTH-1 : 0] w_data_psum; //[NUM_GLB_PSUM-1:0];
	logic [DATA_BITWIDTH-1 : 0] w_data_wght; //[NUM_GLB_WGHT-1:0];
	                                        //
    logic [DATA_BITWIDTH-1 : 0] r_data_iact; //[NUM_GLB_IACT-1:0];
    logic [DATA_BITWIDTH-1 : 0] r_data_psum; //[NUM_GLB_PSUM-1:0];
//    logic [DATA_BITWIDTH-1 : 0] r_data_wght[NUM_GLB_WGHT-1:0];

	GLB_cluster 
			#(	.DATA_BITWIDTH(DATA_BITWIDTH),
				.ADDR_BITWIDTH(ADDR_BITWIDTH),
				.NUM_GLB_IACT(NUM_GLB_IACT),
				.NUM_GLB_PSUM(NUM_GLB_PSUM),
				.NUM_GLB_WGHT(NUM_GLB_WGHT)
			)
	GLB_cluster_0
			(
				.clk(clk), 
				.reset(reset),
				
				.read_req_iact(read_req_iact),
				.read_req_psum(read_req_psum),
				.read_req_wght(read_req_wght),
				
				.write_en_iact(write_en_iact),
				.write_en_psum(router_cluster_0.west_enable_o_psum),
				.write_en_wght(write_en_wght),
				
				.r_addr_iact(r_addr_iact),
			    .r_addr_psum(r_addr_psum),
				.r_addr_wght(r_addr_wght),

			    .w_addr_iact(w_addr_iact),
			    .w_addr_psum(w_addr_psum),
				.w_addr_wght(w_addr_wght),

			    .w_data_iact(w_data_iact),
			    .w_data_psum(router_cluster_0.west_data_o_psum),
				.w_data_wght(w_data_wght),

			    .r_data_iact(router_cluster_0.west_data_i_iact),
			    .r_data_psum(r_data_psum),
				.r_data_wght(router_cluster_0.west_data_i_wght)
			);
			
	//	parameter DATA_WIDTH = 16;
    parameter ADDR_WIDTH = 9;
    
    parameter int X_dim = 3;
    parameter int Y_dim = 3;
    
    parameter int kernel_size = 3;
    parameter int act_size = 5;
    
    parameter W_READ_ADDR = 0;  
    parameter A_READ_ADDR = 100;
    
    parameter W_LOAD_ADDR = 0;  
    parameter A_LOAD_ADDR = 100;
    
    parameter PSUM_ADDR = 500;
	
    logic [DATA_WIDTH-1:0] act_in;
    logic [DATA_WIDTH-1:0] filt_in;

	logic start;
	logic load_en_wght, load_en_act;

    logic [DATA_WIDTH-1:0] pe_out[X_dim-1:0];
  
	logic compute_done;
	
	
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_0
    			(
					.clk(clk),
				    .reset(reset),
				    .act_in(router_cluster_0.west_data_o_iact),
				    .filt_in(router_cluster_0.west_data_o_wght),
					.load_en_wght(load_en_wght),
					.load_en_act(load_en_act),
					.start(start),
                    .pe_out(pe_out),
					.compute_done(compute_done),
					.load_done(load_done)
    			);

				
	integer clk_prd = 10;
	
	always begin
		clk = 0; #(clk_prd/2);
		clk = 1; #(clk_prd/2);
		//0.1GHz
	end
	
	integer kernel_1,act_1,psum_1;
	integer w_addr = 0;
	int args;
	
	logic [DATA_WIDTH-1:0] cluster_out_1[0:8];
	
	initial begin
		reset = 1; #30;
		reset = 0;
		start = 0;
		
		//Write weights to weight glb
/* 		write_en_wght = 1;
		kernel_1 = $fopen("kernel_3x3.txt","r");		
		while(!$feof(kernel_1))begin
			w_addr_wght = w_addr;
			args = $fscanf(kernel_1,"%d\n",w_data_wght);
			$display("Writing value %0d to address %0d in weight glb",w_data_wght,w_addr);
			w_addr++;
			#(clk_prd);
		end
		write_en_wght = 0;
		$fclose(kernel_1); 
		
		
		//Write activations to weight glb
		write_en_iact = 1;
		w_addr = 0;
		act_1 = $fopen("act_5x5.txt","r");
		while(!$feof(act_1))begin
			w_addr_iact = w_addr;
			args = $fscanf(act_1,"%d\n",w_data_iact);
			$display("Writing value %0d to address %0d in iact glb",w_data_iact,w_addr);
			w_addr++;
			#(clk_prd);
		end
		write_en_iact = 0;
		$fclose(act_1);  */
		
			//Write weights to weight glb
 		write_en_wght = 1;		
		for(int i=0; i<kernel_size**2;i++) begin
			w_data_wght = 1;
			w_addr_wght = i;
			#(clk_prd);
		end
		write_en_wght = 0;
	
		//Write activations to weight glb
		write_en_iact = 1;
		for(int i=0; i<act_size**2;i++) begin
			w_data_iact = i+1;
			w_addr_iact = i;
			#(clk_prd);
		end
		write_en_iact = 0;

		
	#(clk_prd);
	
	assign west_data_o_wght = router_cluster_0.west_data_o_wght;
	
	$display("\n\nLoading Begins: Weights.....\n\n");
		read_req_wght = 1;
		r_addr_wght	= 0;
		#(clk_prd);
		
		west_enable_i_wght = 1;
		router_mode_wght = WEST;
		
		
	//Filter
		load_en_wght = 1;
		for(int i=1; i<=kernel_size**2; i++) begin
			r_addr_wght = i; #(clk_prd);
			$display("Weight Read: %d",west_data_o_wght);
			load_en_wght = 0;
		end
	
	read_req_wght = 0;
	west_enable_i_wght = 0;
	
	#(clk_prd);
	
	
	$display("\n\nLoading Begins: Activations.....\n\n");
		
		read_req_iact = 1;
		r_addr_iact	= 0;
		#(clk_prd);
		
		west_enable_i_iact = 1;
		router_mode_iact = WEST;
		load_en_act = 1;
		
	//Filter
		for(int i=1; i<=act_size**2; i++) begin
			r_addr_iact = i; #(clk_prd);
			load_en_act = 0;
		end
	
	read_req_iact = 0;	
	west_enable_i_iact = 0;
	
	#(clk_prd);
		
		
	
// Control for PE cluster Computations
	
	
	//logic   [31:0] dpsram[0:16383]
		
		start = 1; #25; 
		$display("\n\nReading & Computing Begins.....\n\n");
		start = 0;
		
		wait (compute_done == 1);
		
		$display("\n\nFinal PSUM of Iteration 1");
 		for(int i=0; i<X_dim; i++) begin
			cluster_out_1[i] = pe_out[X_dim-i-1];
			$display("\npsum from column %d is:%d",i+1,pe_out[X_dim-i-1]);
		end
		
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 2.....\n\n");
		start = 0;
		
				wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 2:");
 		for(int i=0; i<X_dim; i++) begin
			cluster_out_1[i+3] = pe_out[X_dim-i-1];
			$display("\npsum from column %d is:%d",i+1,pe_out[X_dim-i-1]);
		end
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 3.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 3:");
 		for(int i=0; i<X_dim; i++) begin
		cluster_out_1[i+6] = pe_out[X_dim-i-1];
			$display("\npsum from column %d is:%d",i+1,pe_out[X_dim-i-1]);
		end
		 
		
		$display("\tFinal psums of Cluster 1:\n");
		for(int a=0; a<kernel_size**2; a++) begin
			$display("\t\t %d \n",cluster_out_1[a]);
		end
		
		$display("\tTotal #cycles taken: %d",cycles);
		$stop;
	end

	int cycles;
	// track # of cycles
always @(posedge clk)
begin
    if (reset)
        cycles = 0;
    else
        cycles = cycles + 1;
end

endmodule


================================================
FILE: testbench/phase_2/router_east_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/09/2019 11:53:15 PM
// Design Name: 
// Module Name: router_east_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_east_tb();

	parameter DATA_WIDTH = 16;
	
	logic [2:0] router_mode;
	
	//Interface with North
	//Source ports
	logic [DATA_WIDTH-1:0] north_data_i;
	logic north_enable_i;
	logic  north_ready_o;
	
	//Destination ports
	logic  [DATA_WIDTH-1:0] north_data_o;
	logic  north_enable_o;
	logic north_ready_i;
	
	
	//Interface with South
	//Source ports
	logic [DATA_WIDTH-1:0] south_data_i;
	logic south_enable_i;
	logic  south_ready_o;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] south_data_o;
	logic south_enable_o;
	logic south_ready_i;
	
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i;
	logic west_enable_i;
	logic  west_ready_o;
	
	//Destination ports
	logic  [DATA_WIDTH-1:0] west_data_o;
	logic  west_enable_o;
    logic west_ready_i;

    //Interface with East - Devices
    //Source ports
    logic [DATA_WIDTH-1:0] east_data_i;
    logic east_enable_i;
    logic  east_ready_o;
    
    //Destination ports
    logic  [DATA_WIDTH-1:0] east_data_o;
    logic  east_enable_o;
    logic east_ready_i;
	
	
	//Other logic

	//Instantiation
	
	router_east 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_east_0
		(
			.router_mode(router_mode),
			
			//Interface with North
			//Source ports
			.north_data_i(north_data_i),
			.north_enable_i(north_enable_i),
			.north_ready_o(north_ready_o),
			
			//Destination ports
			.north_data_o(north_data_o),
			.north_enable_o(north_enable_o),
			.north_ready_i(north_ready_i),
			
			
			//Interface with South
			//Source ports
			.south_data_i(south_data_i),
			.south_enable_i(south_enable_i),
			.south_ready_o(south_ready_o),
			
			//Destination ports
			.south_data_o(south_data_o),
			.south_enable_o(south_enable_o),
			.south_ready_i(south_ready_i),
			
			//Interface with West
			//Source ports
			.west_data_i(west_data_i),
			.west_enable_i(west_enable_i),
			.west_ready_o(west_ready_o),
			
			//Destination ports
			.west_data_o(west_data_o),
			.west_enable_o(west_enable_o),
			.west_ready_i(west_ready_i),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i(east_data_i),
			.east_enable_i(east_enable_i),
			.east_ready_o(east_ready_o),
	        
			//Destination ports
	        .east_data_o(east_data_o),
            .east_enable_o(east_enable_o),
            .east_ready_i(east_ready_i)
	);
	
	initial begin
		for(int i=0; i<20; i++) begin
			north_data_i = i;
			south_data_i = i*2;
			west_data_i = i*5;
			east_data_i = i*100;
			#50;
		end
	end
	
	enum logic [2:0] {ALL=0, NORTH=1, SOUTH=2, WEST=3, EAST=4} direction;
	
	initial begin
		router_mode = ALL;
		north_enable_i = 1;
		#100;
		
		router_mode = SOUTH;
		east_enable_i = 1;
		north_enable_i = 0;
		#100;
		
		router_mode = EAST;
		east_enable_i = 1;
		north_enable_i = 0;
		#100;
		
		router_mode = WEST;
		east_enable_i = 1;
		north_enable_i = 0;
		#100;
	end
	
endmodule

================================================
FILE: testbench/phase_2/router_pe_4_clusters_5x5_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/13/2019 04:47:06 AM
// Design Name: 
// Module Name: router_pe_4_clusters
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_pe_4_clusters_5x5_tb();

	parameter DATA_WIDTH = 16;
	
	
	///////////////      WGHT ROUTER WEST 0      ///////////////////////////////////
	
	logic [3:0] router_mode_west_0_whgt;
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i_west_0_whgt;
	logic west_enable_i_west_0_whgt;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] west_data_o_west_0_whgt;
	logic west_enable_o_west_0_whgt;

	
	
		///////////////      WGHT ROUTER WEST 1     ///////////////////////////////////
	
	logic [3:0] router_mode_west_1_whgt;
	
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i_west_1_whgt;
	logic west_enable_i_west_1_whgt;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] west_data_o_west_1_whgt;
	logic west_enable_o_west_1_whgt;

		
			///////////////      WGHT ROUTER EAST 0    ///////////////////////////////////
	
	logic [3:0] router_mode_east_0_whgt;
	
	
	//Interface with East
	//Source ports
	logic [DATA_WIDTH-1:0] east_data_i_east_0_whgt;
	logic east_enable_i_east_0_whgt;

	//Destination ports
	logic [DATA_WIDTH-1:0] east_data_o_east_0_whgt;
	logic east_enable_o_east_0_whgt;

		
		
			///////////////      WGHT ROUTER EAST 1     ///////////////////////////////////
	
	logic [3:0] router_mode_east_1_whgt;
	
	
	//Interface with East
	//Source ports
	logic [DATA_WIDTH-1:0] east_data_i_east_1_whgt;
	logic east_enable_i_east_1_whgt;

	//Destination ports
	logic [DATA_WIDTH-1:0] east_data_o_east_1_whgt;
	logic east_enable_o_east_1_whgt;

	
	
	router_network4 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	network_wght
		(
			.router_mode_west_0(router_mode_west_0_whgt),
			.router_mode_west_1(router_mode_west_1_whgt),
			.router_mode_east_0(router_mode_east_0_whgt),
			.router_mode_east_1(router_mode_east_1_whgt),
			
			
			//WEST 0
			//Source Ports
			.west_data_i_west_0(west_data_i_west_0_whgt),
			.west_enable_i_west_0(west_enable_i_west_0_whgt),
			
			//Destination ports
			.west_data_o_west_0(west_data_o_west_0_whgt),
			.west_enable_o_west_0(west_enable_o_west_0_whgt),
			
			
			
			//WEST 1
			//Source Ports
			.west_data_i_west_1(west_data_i_west_1_whgt),
			.west_enable_i_west_1(west_enable_i_west_1_whgt),
			
			//Destination ports
			.west_data_o_west_1(west_data_o_west_1_whgt),
			.west_enable_o_west_1(west_enable_o_west_1_whgt),
			
			
			
			//EAST 0
			//Source Ports
			.east_data_i_east_0(east_data_i_east_0_whgt),
			.east_enable_i_east_0(east_enable_i_east_0_whgt),
			
			//Destination ports
			.east_data_o_east_0(east_data_o_east_0_whgt),
			.east_enable_o_east_0(east_enable_o_east_0_whgt),
			
			
			//east 1
			//Source Ports
			.east_data_i_east_1(east_data_i_east_1_whgt),
			.east_enable_i_east_1(east_enable_i_east_1_whgt),
			
			//Destination ports
			.east_data_o_east_1(east_data_o_east_1_whgt),
			.east_enable_o_east_1(east_enable_o_east_1_whgt)
			
		);

	
	
	
		///////////////      IACT ROUTER WEST 0      ///////////////////////////////////
	
	logic [3:0] router_mode_west_0_iact;
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i_west_0_iact;
	logic west_enable_i_west_0_iact;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] west_data_o_west_0_iact;
	logic west_enable_o_west_0_iact;

	
	
		///////////////      IACT ROUTER WEST 1     ///////////////////////////////////
	
	logic [3:0] router_mode_west_1_iact;
	
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i_west_1_iact;
	logic west_enable_i_west_1_iact;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] west_data_o_west_1_iact;
	logic west_enable_o_west_1_iact;

		
			///////////////      IACT ROUTER EAST 0    ///////////////////////////////////
	
	logic [3:0] router_mode_east_0_iact;
	
	
	//Interface with East
	//Source ports
	logic [DATA_WIDTH-1:0] east_data_i_east_0_iact;
	logic east_enable_i_east_0_iact;

	//Destination ports
	logic [DATA_WIDTH-1:0] east_data_o_east_0_iact;
	logic east_enable_o_east_0_iact;

		
		
			///////////////      IACT ROUTER EAST 1     ///////////////////////////////////
	
	logic [3:0] router_mode_east_1_iact;
	
	
	//Interface with East
	//Source ports
	logic [DATA_WIDTH-1:0] east_data_i_east_1_iact;
	logic east_enable_i_east_1_iact;

	//Destination ports
	logic [DATA_WIDTH-1:0] east_data_o_east_1_iact;
	logic east_enable_o_east_1_iact;

	
	
	router_network4 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	network_iact
		(
			.router_mode_west_0(router_mode_west_0_iact),
			.router_mode_west_1(router_mode_west_1_iact),
			.router_mode_east_0(router_mode_east_0_iact),
			.router_mode_east_1(router_mode_east_1_iact),
			
			
			//WEST 0
			//Source Ports
			.west_data_i_west_0(west_data_i_west_0_iact),
			.west_enable_i_west_0(west_enable_i_west_0_iact),
			
			//Destination ports
			.west_data_o_west_0(west_data_o_west_0_iact),
			.west_enable_o_west_0(west_enable_o_west_0_iact),
			
			
			
			//WEST 1
			//Source Ports
			.west_data_i_west_1(west_data_i_west_1_iact),
			.west_enable_i_west_1(west_enable_i_west_1_iact),
			
			//Destination ports
			.west_data_o_west_1(west_data_o_west_1_iact),
			.west_enable_o_west_1(west_enable_o_west_1_iact),
			
			
			
			//EAST 0
			//Source Ports
			.east_data_i_east_0(east_data_i_east_0_iact),
			.east_enable_i_east_0(east_enable_i_east_0_iact),
			
			//Destination ports
			.east_data_o_east_0(east_data_o_east_0_iact),
			.east_enable_o_east_0(east_enable_o_east_0_iact),
			
			
			//east 1
			//Source Ports
			.east_data_i_east_1(east_data_i_east_1_iact),
			.east_enable_i_east_1(east_enable_i_east_1_iact),
			
			//Destination ports
			.east_data_o_east_1(east_data_o_east_1_iact),
			.east_enable_o_east_1(east_enable_o_east_1_iact)
			
		);
		
		
	
	logic clk, reset;
	
	
	/////// INST PE CLUSTER
	parameter ADDR_WIDTH = 9;
    
    parameter int X_dim = 5;
    parameter int Y_dim = 5;
    
    parameter int kernel_size = 5;
    parameter int act_size = 7;
		
//    logic [DATA_WIDTH-1:0] act_in;
//    logic [DATA_WIDTH-1:0] filt_in;

	logic start;
	logic load_en_wght, load_en_iact;
  
	logic compute_done;
	logic load_done;
	
	
	logic [DATA_WIDTH-1:0] pe_out[X_dim-1:0];
	logic [DATA_WIDTH-1:0] pe_out_west_0[X_dim-1:0];
	logic [DATA_WIDTH-1:0] pe_out_west_1[X_dim-1:0];
	logic [DATA_WIDTH-1:0] pe_out_east_0[X_dim-1:0];
	logic [DATA_WIDTH-1:0] pe_out_east_1[X_dim-1:0];
	
	// PE CLUSTER WEST 0	
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_west_0
    			(
					.clk(clk),
				    .reset(reset),
					
				    .act_in(network_iact.west_data_o_west_0),
				    .filt_in(network_wght.west_data_o_west_0),
					
					.load_en_wght(load_en_wght),
					.load_en_act(load_en_iact),
					
					.start(start),
                    .pe_out(pe_out_west_0),
					.compute_done(compute_done),
					.load_done(load_done)
    			);
		
	
	// PE CLUSTER WEST 1
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_west_1
    			(
					.clk(clk),
				    .reset(reset),
					
				    .act_in(network_iact.west_data_o_west_1),
				    .filt_in(network_wght.west_data_o_west_1),
					
					.load_en_wght(load_en_wght),
					.load_en_act(load_en_iact),
					
					.start(start),
                    .pe_out(pe_out_west_1),
					.compute_done(),
					.load_done()
    			);
				
	
	// PE CLUSTER EAST 0
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_east_0
    			(
					.clk(clk),
				    .reset(reset),
					
				    .act_in(network_iact.east_data_o_east_0),
				    .filt_in(network_wght.east_data_o_east_0),
					
					.load_en_wght(load_en_wght),
					.load_en_act(load_en_iact),
					
					.start(start),
                    .pe_out(pe_out_east_0),
					.compute_done(),
					.load_done()
    			);
				
			
	// PE CLUSTER EAST 1	
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_east_1
    			(
					.clk(clk),
				    .reset(reset),
					
				    .act_in(network_iact.east_data_o_east_1),
				    .filt_in(network_wght.east_data_o_east_1),
					
					.load_en_wght(load_en_wght),
					.load_en_act(load_en_iact),
					
					.start(start),
                    .pe_out(pe_out_east_1),
					.compute_done(),
					.load_done()
    			);
		
/* 	logic [DATA_WIDTH-1:0] temp;
	assign temp = wght_router_east_0.south_data_o;
	
	logic temp_en;
	assign temp_en = wght_router_east_0.south_enable_o; */
	
		
/* 	initial begin
		for(int i=0; i<20; i++) begin
			west_data_i_west_0 = i;
//			south_data_i = i*2;
//			west_data_i = i*5;
//			east_data_i = i*100;
			#50;
		end
	end */
	
	
	integer clk_prd = 10;
	logic [DATA_WIDTH-1:0] cluster_out_1[0:8];
	
	always begin
		clk = 0; #(clk_prd/2);
		clk = 1; #(clk_prd/2);
		//0.1GHz
	end
	
	
	enum logic [3:0] {ALL=0, NORTH=1, SOUTH=2, WEST=3, EAST=4,
						EASTNORTH=5, EASTSOUTH=6, EASTWEST=7,
						WESTNORTH=8, WESTSOUTH=9, WESTEAST=10} direction;
	
	initial begin
	
		reset = 1; #30;
		reset = 0;
		start = 0;
		
		
		router_mode_west_0_whgt = ALL;

		router_mode_east_0_whgt = EASTSOUTH;
		
		router_mode_west_1_whgt = WEST;
		
		router_mode_east_1_whgt = EAST;
		
		

		#100;
		
		$display("\n\nLoading Begins: Weights.....\n\n");
		
		load_en_wght = 1;
		west_enable_i_west_0_whgt = 1;
		
		for(int i=0; i<kernel_size**2; i++) begin
			west_data_i_west_0_whgt = 1;
			#(clk_prd);
			load_en_wght = 0;
		end
		
		
		
		
		
		router_mode_east_0_iact = EAST;
		router_mode_east_1_iact = EAST;
		
		router_mode_west_0_iact = WEST;
		router_mode_west_1_iact = WEST;
		
		#100;
		
		$display("\n\nLoading Begins: Iacts.....\n\n");
		
		load_en_iact = 1;
		
		east_enable_i_east_0_iact = 1;
		east_enable_i_east_1_iact = 1;
		
		west_enable_i_west_0_iact = 1;
		west_enable_i_west_1_iact = 1;
		
		for(int i=1; i<act_size**2+1; i++) begin
			east_data_i_east_0_iact = i;
			east_data_i_east_1_iact = i+1;
			west_data_i_west_0_iact = i+2;
			west_data_i_west_1_iact = i+3;
			#(clk_prd);	
			load_en_iact = 0;
		end
		
		
		
		
		#50;
		
		assign pe_out = pe_out_east_0;
		
		start = 1; #25; 
		$display("\n\nReading & Computing Begins.....\n\n");
		start = 0;
		
		wait (compute_done == 1);
		
		$display("\n\nFinal PSUM of Iteration 1");
 		for(int i=0; i<X_dim; i++) begin
			cluster_out_1[i] = pe_out[X_dim-i-1];
			$display("\npsum from column %d is:%d",i+1,pe_out[X_dim-i-1]);
		end
		
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 2.....\n\n");
		start = 0;
		
				wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 2:");
 		for(int i=0; i<X_dim; i++) begin
			cluster_out_1[i+5] = pe_out[X_dim-i-1];
			$display("\npsum from column %d is:%d",i+1,pe_out[X_dim-i-1]);
		end
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 3.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 3:");
 		for(int i=0; i<X_dim; i++) begin
		cluster_out_1[i+10] = pe_out[X_dim-i-1];
			$display("\npsum from column %d is:%d",i+1,pe_out[X_dim-i-1]);
		end
		 
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 4.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 4:");
 		for(int i=0; i<X_dim; i++) begin
		cluster_out_1[i+15] = pe_out[X_dim-i-1];
			$display("\npsum from column %d is:%d",i+1,pe_out[X_dim-i-1]);
		end
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 5.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 5:");
 		for(int i=0; i<X_dim; i++) begin
		cluster_out_1[i+20] = pe_out[X_dim-i-1];
			$display("\npsum from column %d is:%d",i+1,pe_out[X_dim-i-1]);
		end
		
		
		$display("\tFinal psums of Cluster 1:\n");
		for(int a=0; a<kernel_size**2; a++) begin
			$display("\t\t %d \n",cluster_out_1[a]);
		end
		
		$display("\tTotal #cycles taken: %d",cycles);
		$stop;
		
		
	end 
	
		int cycles;
		// track # of cycles
	always @(posedge clk)
	begin
		if (reset)
			cycles = 0;
		else
			cycles = cycles + 1;
	end


endmodule


================================================
FILE: testbench/phase_2/router_pe_4_clusters_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/13/2019 04:47:06 AM
// Design Name: 
// Module Name: router_pe_4_clusters
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_pe_4_clusters_tb();

	parameter DATA_WIDTH = 16;
	
	
	///////////////      WGHT ROUTER WEST 0      ///////////////////////////////////
	
	logic [3:0] router_mode_west_0_whgt;
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i_west_0_whgt;
	logic west_enable_i_west_0_whgt;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] west_data_o_west_0_whgt;
	logic west_enable_o_west_0_whgt;

	
	
		///////////////      WGHT ROUTER WEST 1     ///////////////////////////////////
	
	logic [3:0] router_mode_west_1_whgt;
	
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i_west_1_whgt;
	logic west_enable_i_west_1_whgt;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] west_data_o_west_1_whgt;
	logic west_enable_o_west_1_whgt;

		
			///////////////      WGHT ROUTER EAST 0    ///////////////////////////////////
	
	logic [3:0] router_mode_east_0_whgt;
	
	
	//Interface with East
	//Source ports
	logic [DATA_WIDTH-1:0] east_data_i_east_0_whgt;
	logic east_enable_i_east_0_whgt;

	//Destination ports
	logic [DATA_WIDTH-1:0] east_data_o_east_0_whgt;
	logic east_enable_o_east_0_whgt;

		
		
			///////////////      WGHT ROUTER EAST 1     ///////////////////////////////////
	
	logic [3:0] router_mode_east_1_whgt;
	
	
	//Interface with East
	//Source ports
	logic [DATA_WIDTH-1:0] east_data_i_east_1_whgt;
	logic east_enable_i_east_1_whgt;

	//Destination ports
	logic [DATA_WIDTH-1:0] east_data_o_east_1_whgt;
	logic east_enable_o_east_1_whgt;

	
	
	router_network4 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	network_wght
		(
			.router_mode_west_0(router_mode_west_0_whgt),
			.router_mode_west_1(router_mode_west_1_whgt),
			.router_mode_east_0(router_mode_east_0_whgt),
			.router_mode_east_1(router_mode_east_1_whgt),
			
			
			//WEST 0
			//Source Ports
			.west_data_i_west_0(west_data_i_west_0_whgt),
			.west_enable_i_west_0(west_enable_i_west_0_whgt),
			
			//Destination ports
			.west_data_o_west_0(west_data_o_west_0_whgt),
			.west_enable_o_west_0(west_enable_o_west_0_whgt),
			
			
			
			//WEST 1
			//Source Ports
			.west_data_i_west_1(west_data_i_west_1_whgt),
			.west_enable_i_west_1(west_enable_i_west_1_whgt),
			
			//Destination ports
			.west_data_o_west_1(west_data_o_west_1_whgt),
			.west_enable_o_west_1(west_enable_o_west_1_whgt),
			
			
			
			//EAST 0
			//Source Ports
			.east_data_i_east_0(east_data_i_east_0_whgt),
			.east_enable_i_east_0(east_enable_i_east_0_whgt),
			
			//Destination ports
			.east_data_o_east_0(east_data_o_east_0_whgt),
			.east_enable_o_east_0(east_enable_o_east_0_whgt),
			
			
			//east 1
			//Source Ports
			.east_data_i_east_1(east_data_i_east_1_whgt),
			.east_enable_i_east_1(east_enable_i_east_1_whgt),
			
			//Destination ports
			.east_data_o_east_1(east_data_o_east_1_whgt),
			.east_enable_o_east_1(east_enable_o_east_1_whgt)
			
		);

	
	
	
		///////////////      IACT ROUTER WEST 0      ///////////////////////////////////
	
	logic [3:0] router_mode_west_0_iact;
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i_west_0_iact;
	logic west_enable_i_west_0_iact;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] west_data_o_west_0_iact;
	logic west_enable_o_west_0_iact;

	
	
		///////////////      IACT ROUTER WEST 1     ///////////////////////////////////
	
	logic [3:0] router_mode_west_1_iact;
	
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i_west_1_iact;
	logic west_enable_i_west_1_iact;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] west_data_o_west_1_iact;
	logic west_enable_o_west_1_iact;

		
			///////////////      IACT ROUTER EAST 0    ///////////////////////////////////
	
	logic [3:0] router_mode_east_0_iact;
	
	
	//Interface with East
	//Source ports
	logic [DATA_WIDTH-1:0] east_data_i_east_0_iact;
	logic east_enable_i_east_0_iact;

	//Destination ports
	logic [DATA_WIDTH-1:0] east_data_o_east_0_iact;
	logic east_enable_o_east_0_iact;

		
		
			///////////////      IACT ROUTER EAST 1     ///////////////////////////////////
	
	logic [3:0] router_mode_east_1_iact;
	
	
	//Interface with East
	//Source ports
	logic [DATA_WIDTH-1:0] east_data_i_east_1_iact;
	logic east_enable_i_east_1_iact;

	//Destination ports
	logic [DATA_WIDTH-1:0] east_data_o_east_1_iact;
	logic east_enable_o_east_1_iact;

	
	
	router_network4 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	network_iact
		(
			.router_mode_west_0(router_mode_west_0_iact),
			.router_mode_west_1(router_mode_west_1_iact),
			.router_mode_east_0(router_mode_east_0_iact),
			.router_mode_east_1(router_mode_east_1_iact),
			
			
			//WEST 0
			//Source Ports
			.west_data_i_west_0(west_data_i_west_0_iact),
			.west_enable_i_west_0(west_enable_i_west_0_iact),
			
			//Destination ports
			.west_data_o_west_0(west_data_o_west_0_iact),
			.west_enable_o_west_0(west_enable_o_west_0_iact),
			
			
			
			//WEST 1
			//Source Ports
			.west_data_i_west_1(west_data_i_west_1_iact),
			.west_enable_i_west_1(west_enable_i_west_1_iact),
			
			//Destination ports
			.west_data_o_west_1(west_data_o_west_1_iact),
			.west_enable_o_west_1(west_enable_o_west_1_iact),
			
			
			
			//EAST 0
			//Source Ports
			.east_data_i_east_0(east_data_i_east_0_iact),
			.east_enable_i_east_0(east_enable_i_east_0_iact),
			
			//Destination ports
			.east_data_o_east_0(east_data_o_east_0_iact),
			.east_enable_o_east_0(east_enable_o_east_0_iact),
			
			
			//east 1
			//Source Ports
			.east_data_i_east_1(east_data_i_east_1_iact),
			.east_enable_i_east_1(east_enable_i_east_1_iact),
			
			//Destination ports
			.east_data_o_east_1(east_data_o_east_1_iact),
			.east_enable_o_east_1(east_enable_o_east_1_iact)
			
		);
		
		
	
	logic clk, reset;
	
	
	/////// INST PE CLUSTER
	parameter ADDR_WIDTH = 9;
    
    parameter int X_dim = 3;
    parameter int Y_dim = 3;
    
    parameter int kernel_size = 3;
    parameter int act_size = 5;
		
//    logic [DATA_WIDTH-1:0] act_in;
//    logic [DATA_WIDTH-1:0] filt_in;

	logic start;
	logic load_en_wght, load_en_iact;
  
	logic compute_done;
	logic load_done;
	
	
	logic [DATA_WIDTH-1:0] pe_out[X_dim-1:0];
	logic [DATA_WIDTH-1:0] pe_out_west_0[X_dim-1:0];
	logic [DATA_WIDTH-1:0] pe_out_west_1[X_dim-1:0];
	logic [DATA_WIDTH-1:0] pe_out_east_0[X_dim-1:0];
	logic [DATA_WIDTH-1:0] pe_out_east_1[X_dim-1:0];
	
	// PE CLUSTER WEST 0	
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_west_0
    			(
					.clk(clk),
				    .reset(reset),
					
				    .act_in(network_iact.west_data_o_west_0),
				    .filt_in(network_wght.west_data_o_west_0),
					
					.load_en_wght(load_en_wght),
					.load_en_act(load_en_iact),
					
					.start(start),
                    .pe_out(pe_out_west_0),
					.compute_done(compute_done),
					.load_done(load_done)
    			);
		
	
	// PE CLUSTER WEST 1
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_west_1
    			(
					.clk(clk),
				    .reset(reset),
					
				    .act_in(network_iact.west_data_o_west_1),
				    .filt_in(network_wght.west_data_o_west_1),
					
					.load_en_wght(load_en_wght),
					.load_en_act(load_en_iact),
					
					.start(start),
                    .pe_out(pe_out_west_1),
					.compute_done(),
					.load_done()
    			);
				
	
	// PE CLUSTER EAST 0
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_east_0
    			(
					.clk(clk),
				    .reset(reset),
					
				    .act_in(network_iact.east_data_o_east_0),
				    .filt_in(network_wght.east_data_o_east_0),
					
					.load_en_wght(load_en_wght),
					.load_en_act(load_en_iact),
					
					.start(start),
                    .pe_out(pe_out_east_0),
					.compute_done(),
					.load_done()
    			);
				
			
	// PE CLUSTER EAST 1	
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_east_1
    			(
					.clk(clk),
				    .reset(reset),
					
				    .act_in(network_iact.east_data_o_east_1),
				    .filt_in(network_wght.east_data_o_east_1),
					
					.load_en_wght(load_en_wght),
					.load_en_act(load_en_iact),
					
					.start(start),
                    .pe_out(pe_out_east_1),
					.compute_done(),
					.load_done()
    			);
		
/* 	logic [DATA_WIDTH-1:0] temp;
	assign temp = wght_router_east_0.south_data_o;
	
	logic temp_en;
	assign temp_en = wght_router_east_0.south_enable_o; */
	
		
/* 	initial begin
		for(int i=0; i<20; i++) begin
			west_data_i_west_0 = i;
//			south_data_i = i*2;
//			west_data_i = i*5;
//			east_data_i = i*100;
			#50;
		end
	end */
	
	
	integer clk_prd = 10;
	logic [DATA_WIDTH-1:0] cluster_out_1[0:8];
	
	always begin
		clk = 0; #(clk_prd/2);
		clk = 1; #(clk_prd/2);
		//0.1GHz
	end
	
	
	enum logic [3:0] {ALL=0, NORTH=1, SOUTH=2, WEST=3, EAST=4,
						EASTNORTH=5, EASTSOUTH=6, EASTWEST=7,
						WESTNORTH=8, WESTSOUTH=9, WESTEAST=10} direction;
	
	initial begin
	
		reset = 1; #30;
		reset = 0;
		start = 0;
		
		
		router_mode_west_0_whgt = ALL;

		router_mode_east_0_whgt = EASTSOUTH;
		
		router_mode_west_1_whgt = WEST;
		
		router_mode_east_1_whgt = EAST;
		
		

		#100;
		
		$display("\n\nLoading Begins: Weights.....\n\n");
		
		load_en_wght = 1;
		west_enable_i_west_0_whgt = 1;
		
		for(int i=0; i<kernel_size**2; i++) begin
			west_data_i_west_0_whgt = i+1;
			#(clk_prd);
			load_en_wght = 0;
		end
		
		
		
		
		
		router_mode_east_0_iact = EAST;
		router_mode_east_1_iact = EAST;
		
		router_mode_west_0_iact = WEST;
		router_mode_west_1_iact = WEST;
		
		#100;
		
		$display("\n\nLoading Begins: Iacts.....\n\n");
		
		load_en_iact = 1;
		
		east_enable_i_east_0_iact = 1;
		east_enable_i_east_1_iact = 1;
		
		west_enable_i_west_0_iact = 1;
		west_enable_i_west_1_iact = 1;
		
		for(int i=1; i<act_size**2+1; i++) begin
			east_data_i_east_0_iact = i;
			east_data_i_east_1_iact = i+2;
			west_data_i_west_0_iact = i*5;
			west_data_i_west_1_iact = i+3;
			#(clk_prd);
			load_en_iact = 0;
		end
		
		
		
		
		#50;
		
		assign pe_out = pe_out_east_0;
		
		start = 1; #25; 
		$display("\n\nReading & Computing Begins.....\n\n");
		start = 0;
		
		wait (compute_done == 1);
		
		$display("\n\nFinal PSUM of Iteration 1");
 		for(int i=0; i<X_dim; i++) begin
			cluster_out_1[i] = pe_out[X_dim-i-1];
			$display("\npsum from column %d is:%d",i+1,pe_out[X_dim-i-1]);
		end
		
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 2.....\n\n");
		start = 0;
		
				wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 2:");
 		for(int i=0; i<X_dim; i++) begin
			cluster_out_1[i+3] = pe_out[X_dim-i-1];
			$display("\npsum from column %d is:%d",i+1,pe_out[X_dim-i-1]);
		end
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 3.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 3:");
 		for(int i=0; i<X_dim; i++) begin
		cluster_out_1[i+6] = pe_out[X_dim-i-1];
			$display("\npsum from column %d is:%d",i+1,pe_out[X_dim-i-1]);
		end
		 
		
		$display("\tFinal psums of Cluster 1:\n");
		for(int a=0; a<kernel_size**2; a++) begin
			$display("\t\t %d \n",cluster_out_1[a]);
		end
		
		$display("\tTotal #cycles taken: %d",cycles);
		$stop;
		
		
	end 
	
		int cycles;
		// track # of cycles
	always @(posedge clk)
	begin
		if (reset)
			cycles = 0;
		else
			cycles = cycles + 1;
	end


endmodule


================================================
FILE: testbench/phase_3/router_broadcast_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/11/2019 05:07:36 PM
// Design Name: 
// Module Name: router_broadcast_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_broadcast_tb();

	parameter DATA_WIDTH = 16;
	
	
	///////////////      ROUTER WEST 0      ///////////////////////////////////
	
	logic [3:0] router_mode_west_0;
	
	
	//Interface with North
	//Source ports
	logic [DATA_WIDTH-1:0] north_data_i_west_0;
	logic north_enable_i_west_0;

	//Destination ports
	logic [DATA_WIDTH-1:0] north_data_o_west_0;
	logic north_enable_o_west_0;

	
	
	//Interface with South
	//Source ports
	logic [DATA_WIDTH-1:0] south_data_i_west_0;
	logic south_enable_i_west_0;

	//Destination ports
	logic [DATA_WIDTH-1:0] south_data_o_west_0;
	logic south_enable_o_west_0;

	
	
	//Interface with West
	//Source ports
 logic [DATA_WIDTH-1:0] west_data_i_west_0;
	logic west_enable_i_west_0;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] west_data_o_west_0;
	logic west_enable_o_west_0;

	
	
	//Interface with East
	//Source ports
//	logic [DATA_WIDTH-1:0] east_data_i_west_0;
//	logic east_enable_i_west_0;

	//Destination ports
//	logic [DATA_WIDTH-1:0] east_data_o_west_0;
//	logic east_enable_o_west_0;

	
	
	router 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_west_0
		(
			.router_mode(router_mode_west_0),
			
			
			//Interface with North
			//Source ports
			.north_data_i(north_data_i_west_0),
			.north_enable_i(north_enable_i_west_0),
			
			//Destination ports
			.north_data_o(north_data_o_west_0),
			.north_enable_o(north_enable_o_west_0),
			
			
			//Interface with South
			//Source ports
			.south_data_i(south_data_i_west_0),
			.south_enable_i(south_enable_i_west_0),
			
			//Destination ports
			.south_data_o(south_data_o_west_0),
			.south_enable_o(south_enable_o_west_0),
			
			
			//Interface with West
			//Source ports
			.west_data_i(west_data_i_west_0),
			.west_enable_i(west_enable_i_west_0),
			
			//Destination ports
			.west_data_o(west_data_0_west_0),
			.west_enable_o(west_enable_o_west_0),
			
			
			//Interface with East
			//Source ports
			.east_data_i(router_east_0.west_data_o),
			.east_enable_i(router_east_0.west_enable_o),
	        
			//Destination ports
	        .east_data_o(router_east_0.west_data_i),
            .east_enable_o(router_east_0.west_enable_i)
		);
	
	
	
	///////////////      ROUTER EAST 0      ///////////////////////////////////
		
		
	logic [3:0] router_mode_east_0;
	

	//Interface with North
	//Source ports
	logic [DATA_WIDTH-1:0] north_data_i_east_0;
	logic north_enable_i_east_0;

	//Destination ports
	logic [DATA_WIDTH-1:0] north_data_o_east_0;
	logic north_enable_o_east_0;

	
	
	//Interface with South
	//Source ports
	logic [DATA_WIDTH-1:0] south_data_i_east_0;
	logic south_enable_i_east_0;

	//Destination ports
	logic [DATA_WIDTH-1:0] south_data_o_east_0;
	logic south_enable_o_east_0;

	
	
	//Interface with West
	//Source ports
//	logic [DATA_WIDTH-1:0] west_data_i_east_0;
//	logic west_enable_i_east_0;
	
	//Destination ports
//	logic [DATA_WIDTH-1:0] west_data_o_east_0;
//	logic west_enable_o_east_0;

	
	
	//Interface with East
	//Source ports
	logic [DATA_WIDTH-1:0] east_data_i_east_0;
	logic east_enable_i_east_0;

	//Destination ports
	logic [DATA_WIDTH-1:0] east_data_o_east_0;
	logic east_enable_o_east_0;

	
	
	router 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_east_0
		(
			.router_mode(router_mode_east_0),
			
			
			//Interface with North
			//Source ports
			.north_data_i(north_data_i_east_0),
			.north_enable_i(north_enable_i_east_0),
			
			//Destination ports
			.north_data_o(north_data_o_east_0),
			.north_enable_o(north_enable_o_east_0),
			
			
			//Interface with South
			//Source ports
			.south_data_i(south_data_i_east_0),
			.south_enable_i(south_enable_i_east_0),
			
			//Destination ports
			.south_data_o(south_data_o_east_0),
			.south_enable_o(south_enable_o_east_0),
			
			
			//Interface with West
			//Source ports
			.west_data_i(router_west_0.east_data_o),
			.west_enable_i(router_west_0.east_enable_o),
			
			//Destination ports
			.west_data_o(router_west_0.east_data_i),
			.west_enable_o(router_west_0.east_enable_i),
			
			
			//Interface with East
			//Source ports
			.east_data_i(east_data_i_east_0),
			.east_enable_i(east_enable_i_east_0),
	        
			//Destination ports
	        .east_data_o(east_data_o_east_0),
            .east_enable_o(east_enable_o_east_0)
		);
		
 	initial begin
		for(int i=0; i<20; i++) begin
			north_data_i_west_0 = i;
//			south_data_i = i*2;
//			west_data_i = i*5;
//			east_data_i = i*100;
			#50;
		end
	end
	
	enum logic [3:0] {ALL=0, NORTH=1, SOUTH=2, WEST=3, EAST=4,
						EASTNORTH=5, EASTSOUTH=6, EASTWEST=7,
						WESTNORTH=8, WESTSOUTH=9, WESTEAST=10} direction;
	
	initial begin
		router_mode_west_0 = EASTSOUTH;
		north_enable_i_west_0 = 1;

		#100;
		router_mode_east_0 = SOUTH;
		
		#100;
		router_mode_east_0 = EASTNORTH;
		
		#100;
		router_mode_east_0 = NORTH;
		
		#100;
		router_mode_east_0 = EASTSOUTH;
		
	end 
	
endmodule

================================================
FILE: testbench/phase_3/router_multicast_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/11/2019 07:50:20 PM
// Design Name: 
// Module Name: router_multicast_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_multicast_tb();


	parameter DATA_WIDTH = 16;
	
	
	///////////////      ROUTER WEST 0      ///////////////////////////////////
	
	logic [3:0] router_mode_west_0;
	
	
	//Interface with North
	//Source ports
	logic [DATA_WIDTH-1:0] north_data_i_west_0;
	logic north_enable_i_west_0;

	//Destination ports
	logic [DATA_WIDTH-1:0] north_data_o_west_0;
	logic north_enable_o_west_0;

	
	
	//Interface with South
	//Source ports
	logic [DATA_WIDTH-1:0] south_data_i_west_0;
	logic south_enable_i_west_0;

	//Destination ports
	logic [DATA_WIDTH-1:0] south_data_o_west_0;
	logic south_enable_o_west_0;

	
	
	//Interface with West
	//Source ports
 logic [DATA_WIDTH-1:0] west_data_i_west_0;
	logic west_enable_i_west_0;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] west_data_o_west_0;
	logic west_enable_o_west_0;

	
	
	//Interface with East
	//Source ports
//	logic [DATA_WIDTH-1:0] east_data_i_west_0;
//	logic east_enable_i_west_0;

	//Destination ports
//	logic [DATA_WIDTH-1:0] east_data_o_west_0;
//	logic east_enable_o_west_0;

	
	
	router 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_west_0
		(
			.router_mode(router_mode_west_0),
			
			
			//Interface with North
			//Source ports
			.north_data_i(north_data_i_west_0),
			.north_enable_i(north_enable_i_west_0),
			
			//Destination ports
			.north_data_o(north_data_o_west_0),
			.north_enable_o(north_enable_o_west_0),
			
			
			//Interface with South
			//Source ports
			.south_data_i(south_data_i_west_0),
			.south_enable_i(south_enable_i_west_0),
			
			//Destination ports
			.south_data_o(south_data_o_west_0),
			.south_enable_o(south_enable_o_west_0),
			
			
			//Interface with West
			//Source ports
			.west_data_i(west_data_i_west_0),
			.west_enable_i(west_enable_i_west_0),
			
			//Destination ports
			.west_data_o(west_data_0_west_0),
			.west_enable_o(west_enable_o_west_0),
			
			
			//Interface with East
			//Source ports
			.east_data_i(router_east_0.west_data_o),
			.east_enable_i(router_east_0.west_enable_o),
	        
			//Destination ports
	        .east_data_o(router_east_0.west_data_i),
            .east_enable_o(router_east_0.west_enable_i)
		);
	
	
	
	///////////////      ROUTER EAST 0      ///////////////////////////////////
		
		
	logic [3:0] router_mode_east_0;
	

	//Interface with North
	//Source ports
	logic [DATA_WIDTH-1:0] north_data_i_east_0;
	logic north_enable_i_east_0;

	//Destination ports
	logic [DATA_WIDTH-1:0] north_data_o_east_0;
	logic north_enable_o_east_0;

	
	
	//Interface with South
	//Source ports
	logic [DATA_WIDTH-1:0] south_data_i_east_0;
	logic south_enable_i_east_0;

	//Destination ports
	logic [DATA_WIDTH-1:0] south_data_o_east_0;
	logic south_enable_o_east_0;

	
	
	//Interface with West
	//Source ports
//	logic [DATA_WIDTH-1:0] west_data_i_east_0;
//	logic west_enable_i_east_0;
	
	//Destination ports
//	logic [DATA_WIDTH-1:0] west_data_o_east_0;
//	logic west_enable_o_east_0;

	
	
	//Interface with East
	//Source ports
	logic [DATA_WIDTH-1:0] east_data_i_east_0;
	logic east_enable_i_east_0;

	//Destination ports
	logic [DATA_WIDTH-1:0] east_data_o_east_0;
	logic east_enable_o_east_0;

	
	
	router 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_east_0
		(
			.router_mode(router_mode_east_0),
			
			
			//Interface with North
			//Source ports
			.north_data_i(north_data_i_east_0),
			.north_enable_i(north_enable_i_east_0),
			
			//Destination ports
			.north_data_o(north_data_o_east_0),
			.north_enable_o(north_enable_o_east_0),
			
			
			//Interface with South
			//Source ports
			.south_data_i(south_data_i_east_0),
			.south_enable_i(south_enable_i_east_0),
			
			//Destination ports
			.south_data_o(south_data_o_east_0),
			.south_enable_o(south_enable_o_east_0),
			
			
			//Interface with West
			//Source ports
			.west_data_i(router_west_0.east_data_o),
			.west_enable_i(router_west_0.east_enable_o),
			
			//Destination ports
			.west_data_o(router_west_0.east_data_i),
			.west_enable_o(router_west_0.east_enable_i),
			
			
			//Interface with East
			//Source ports
			.east_data_i(east_data_i_east_0),
			.east_enable_i(east_enable_i_east_0),
	        
			//Destination ports
	        .east_data_o(east_data_o_east_0),
            .east_enable_o(east_enable_o_east_0)
		);


		
		
	////////////// ROUTER WEST 1 /////////////////////////	
		
	logic [3:0] router_mode_west_1;
	
	
	//Interface with North
	//Source ports
	logic [DATA_WIDTH-1:0] north_data_i_west_1;
	logic north_enable_i_west_1;

	//Destination ports
	logic [DATA_WIDTH-1:0] north_data_o_west_1;
	logic north_enable_o_west_1;

	
	
	//Interface with South
	//Source ports
	logic [DATA_WIDTH-1:0] south_data_i_west_1;
	logic south_enable_i_west_1;

	//Destination ports
	logic [DATA_WIDTH-1:0] south_data_o_west_1;
	logic south_enable_o_west_1;

	
	
	//Interface with West
	//Source ports
 logic [DATA_WIDTH-1:0] west_data_i_west_1;
	logic west_enable_i_west_1;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] west_data_o_west_1;
	logic west_enable_o_west_1;

	
	
	//Interface with East
	//Source ports
//	logic [DATA_WIDTH-1:0] east_data_i_west_1;
//	logic east_enable_i_west_1;

	//Destination ports
//	logic [DATA_WIDTH-1:0] east_data_o_west_1;
//	logic east_enable_o_west_1;

	
	
	router 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_west_1
		(
			.router_mode(router_mode_west_1),
			
			
			//Interface with North
			//Source ports
			.north_data_i(north_data_i_west_1),
			.north_enable_i(north_enable_i_west_1),
			
			//Destination ports
			.north_data_o(north_data_o_west_1),
			.north_enable_o(north_enable_o_west_1),
			
			
			//Interface with South
			//Source ports
			.south_data_i(south_data_i_west_1),
			.south_enable_i(south_enable_i_west_1),
			
			//Destination ports
			.south_data_o(south_data_o_west_1),
			.south_enable_o(south_enable_o_west_1),
			
			
			//Interface with West
			//Source ports
			.west_data_i(west_data_i_west_1),
			.west_enable_i(west_enable_i_west_1),
			
			//Destination ports
			.west_data_o(west_data_0_west_1),
			.west_enable_o(west_enable_o_west_1),
			
			
			//Interface with East
			//Source ports
			.east_data_i(router_east_1.west_data_o),
			.east_enable_i(router_east_1.west_enable_o),
	        
			//Destination ports
	        .east_data_o(router_east_1.west_data_i),
            .east_enable_o(router_east_1.west_enable_i)
		);
	
	
	
	///////////////      ROUTER EAST 1      ///////////////////////////////////
		
		
	logic [3:0] router_mode_east_1;
	

	//Interface with North
	//Source ports
	logic [DATA_WIDTH-1:0] north_data_i_east_1;
	logic north_enable_i_east_1;

	//Destination ports
	logic [DATA_WIDTH-1:0] north_data_o_east_1;
	logic north_enable_o_east_1;

	
	
	//Interface with South
	//Source ports
	logic [DATA_WIDTH-1:0] south_data_i_east_1;
	logic south_enable_i_east_1;

	//Destination ports
	logic [DATA_WIDTH-1:0] south_data_o_east_1;
	logic south_enable_o_east_1;

	
	
	//Interface with West
	//Source ports
//	logic [DATA_WIDTH-1:0] west_data_i_east_1;
//	logic west_enable_i_east_1;
	
	//Destination ports
//	logic [DATA_WIDTH-1:0] west_data_o_east_1;
//	logic west_enable_o_east_1;

	
	
	//Interface with East
	//Source ports
	logic [DATA_WIDTH-1:0] east_data_i_east_1;
	logic east_enable_i_east_1;

	//Destination ports
	logic [DATA_WIDTH-1:0] east_data_o_east_1;
	logic east_enable_o_east_1;

	
	
	router 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_east_1
		(
			.router_mode(router_mode_east_1),
			
			
			//Interface with North
			//Source ports
			.north_data_i(north_data_i_east_1),
			.north_enable_i(north_enable_i_east_1),
			
			//Destination ports
			.north_data_o(north_data_o_east_1),
			.north_enable_o(north_enable_o_east_1),
			
			
			//Interface with South
			//Source ports
			.south_data_i(south_data_i_east_1),
			.south_enable_i(south_enable_i_east_1),
			
			//Destination ports
			.south_data_o(south_data_o_east_1),
			.south_enable_o(south_enable_o_east_1),
			
			
			//Interface with West
			//Source ports
			.west_data_i(router_west_1.east_data_o),
			.west_enable_i(router_west_1.east_enable_o),
			
			//Destination ports
			.west_data_o(router_west_1.east_data_i),
			.west_enable_o(router_west_1.east_enable_i),
			
			
			//Interface with East
			//Source ports
			.east_data_i(east_data_i_east_1),
			.east_enable_i(east_enable_i_east_1),
	        
			//Destination ports
	        .east_data_o(east_data_o_east_1),
            .east_enable_o(east_enable_o_east_1)
		);
		
		
		
		 	initial begin
		for(int i=0; i<20; i++) begin
			north_data_i_west_0 = i;
			north_data_i_west_1 = i*10;
			#50;
		end
	end
	
	enum logic [3:0] {ALL=0, NORTH=1, SOUTH=2, WEST=3, EAST=4,
						EASTNORTH=5, EASTSOUTH=6, EASTWEST=7,
						WESTNORTH=8, WESTSOUTH=9, WESTEAST=10} direction;
	
	initial begin
		#100;

		router_mode_west_0 = EASTSOUTH;
		north_enable_i_west_0 = 1;
		#100;
		router_mode_east_0 = NORTH;
		
		
		
		#300;
		
		
		router_mode_west_1 = EASTSOUTH;
		north_enable_i_west_1 = 1;
		#100;
		router_mode_east_1 = SOUTH;
		
	end 

endmodule


================================================
FILE: testbench/phase_3/router_pe_4_clusters_5x5_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/13/2019 04:47:06 AM
// Design Name: 
// Module Name: router_pe_4_clusters
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_pe_4_clusters_5x5_tb();

	parameter DATA_WIDTH = 16;
	
	
	///////////////      WGHT ROUTER WEST 0      ///////////////////////////////////
	
	logic [3:0] router_mode_west_0_whgt;
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i_west_0_whgt;
	logic west_enable_i_west_0_whgt;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] west_data_o_west_0_whgt;
	logic west_enable_o_west_0_whgt;

	
	
		///////////////      WGHT ROUTER WEST 1     ///////////////////////////////////
	
	logic [3:0] router_mode_west_1_whgt;
	
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i_west_1_whgt;
	logic west_enable_i_west_1_whgt;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] west_data_o_west_1_whgt;
	logic west_enable_o_west_1_whgt;

		
			///////////////      WGHT ROUTER EAST 0    ///////////////////////////////////
	
	logic [3:0] router_mode_east_0_whgt;
	
	
	//Interface with East
	//Source ports
	logic [DATA_WIDTH-1:0] east_data_i_east_0_whgt;
	logic east_enable_i_east_0_whgt;

	//Destination ports
	logic [DATA_WIDTH-1:0] east_data_o_east_0_whgt;
	logic east_enable_o_east_0_whgt;

		
		
			///////////////      WGHT ROUTER EAST 1     ///////////////////////////////////
	
	logic [3:0] router_mode_east_1_whgt;
	
	
	//Interface with East
	//Source ports
	logic [DATA_WIDTH-1:0] east_data_i_east_1_whgt;
	logic east_enable_i_east_1_whgt;

	//Destination ports
	logic [DATA_WIDTH-1:0] east_data_o_east_1_whgt;
	logic east_enable_o_east_1_whgt;

	
	
	router_network4 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	network_wght
		(
			.router_mode_west_0(router_mode_west_0_whgt),
			.router_mode_west_1(router_mode_west_1_whgt),
			.router_mode_east_0(router_mode_east_0_whgt),
			.router_mode_east_1(router_mode_east_1_whgt),
			
			
			//WEST 0
			//Source Ports
			.west_data_i_west_0(west_data_i_west_0_whgt),
			.west_enable_i_west_0(west_enable_i_west_0_whgt),
			
			//Destination ports
			.west_data_o_west_0(west_data_o_west_0_whgt),
			.west_enable_o_west_0(west_enable_o_west_0_whgt),
			
			
			
			//WEST 1
			//Source Ports
			.west_data_i_west_1(west_data_i_west_1_whgt),
			.west_enable_i_west_1(west_enable_i_west_1_whgt),
			
			//Destination ports
			.west_data_o_west_1(west_data_o_west_1_whgt),
			.west_enable_o_west_1(west_enable_o_west_1_whgt),
			
			
			
			//EAST 0
			//Source Ports
			.east_data_i_east_0(east_data_i_east_0_whgt),
			.east_enable_i_east_0(east_enable_i_east_0_whgt),
			
			//Destination ports
			.east_data_o_east_0(east_data_o_east_0_whgt),
			.east_enable_o_east_0(east_enable_o_east_0_whgt),
			
			
			//east 1
			//Source Ports
			.east_data_i_east_1(east_data_i_east_1_whgt),
			.east_enable_i_east_1(east_enable_i_east_1_whgt),
			
			//Destination ports
			.east_data_o_east_1(east_data_o_east_1_whgt),
			.east_enable_o_east_1(east_enable_o_east_1_whgt)
			
		);

	
	
	
		///////////////      IACT ROUTER WEST 0      ///////////////////////////////////
	
	logic [3:0] router_mode_west_0_iact;
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i_west_0_iact;
	logic west_enable_i_west_0_iact;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] west_data_o_west_0_iact;
	logic west_enable_o_west_0_iact;

	
	
		///////////////      IACT ROUTER WEST 1     ///////////////////////////////////
	
	logic [3:0] router_mode_west_1_iact;
	
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i_west_1_iact;
	logic west_enable_i_west_1_iact;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] west_data_o_west_1_iact;
	logic west_enable_o_west_1_iact;

		
			///////////////      IACT ROUTER EAST 0    ///////////////////////////////////
	
	logic [3:0] router_mode_east_0_iact;
	
	
	//Interface with East
	//Source ports
	logic [DATA_WIDTH-1:0] east_data_i_east_0_iact;
	logic east_enable_i_east_0_iact;

	//Destination ports
	logic [DATA_WIDTH-1:0] east_data_o_east_0_iact;
	logic east_enable_o_east_0_iact;

		
		
			///////////////      IACT ROUTER EAST 1     ///////////////////////////////////
	
	logic [3:0] router_mode_east_1_iact;
	
	
	//Interface with East
	//Source ports
	logic [DATA_WIDTH-1:0] east_data_i_east_1_iact;
	logic east_enable_i_east_1_iact;

	//Destination ports
	logic [DATA_WIDTH-1:0] east_data_o_east_1_iact;
	logic east_enable_o_east_1_iact;

	
	
	router_network4 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	network_iact
		(
			.router_mode_west_0(router_mode_west_0_iact),
			.router_mode_west_1(router_mode_west_1_iact),
			.router_mode_east_0(router_mode_east_0_iact),
			.router_mode_east_1(router_mode_east_1_iact),
			
			
			//WEST 0
			//Source Ports
			.west_data_i_west_0(west_data_i_west_0_iact),
			.west_enable_i_west_0(west_enable_i_west_0_iact),
			
			//Destination ports
			.west_data_o_west_0(west_data_o_west_0_iact),
			.west_enable_o_west_0(west_enable_o_west_0_iact),
			
			
			
			//WEST 1
			//Source Ports
			.west_data_i_west_1(west_data_i_west_1_iact),
			.west_enable_i_west_1(west_enable_i_west_1_iact),
			
			//Destination ports
			.west_data_o_west_1(west_data_o_west_1_iact),
			.west_enable_o_west_1(west_enable_o_west_1_iact),
			
			
			
			//EAST 0
			//Source Ports
			.east_data_i_east_0(east_data_i_east_0_iact),
			.east_enable_i_east_0(east_enable_i_east_0_iact),
			
			//Destination ports
			.east_data_o_east_0(east_data_o_east_0_iact),
			.east_enable_o_east_0(east_enable_o_east_0_iact),
			
			
			//east 1
			//Source Ports
			.east_data_i_east_1(east_data_i_east_1_iact),
			.east_enable_i_east_1(east_enable_i_east_1_iact),
			
			//Destination ports
			.east_data_o_east_1(east_data_o_east_1_iact),
			.east_enable_o_east_1(east_enable_o_east_1_iact)
			
		);
		
		
	
	logic clk, reset;
	
	
	/////// INST PE CLUSTER
	parameter ADDR_WIDTH = 9;
    
    parameter int X_dim = 5;
    parameter int Y_dim = 5;
    
    parameter int kernel_size = 5;
    parameter int act_size = 7;
		
//    logic [DATA_WIDTH-1:0] act_in;
//    logic [DATA_WIDTH-1:0] filt_in;

	logic start;
	logic load_en_wght, load_en_iact;
  
	logic compute_done;
	logic load_done;
	
	
	logic [DATA_WIDTH-1:0] pe_out[X_dim-1:0];
	logic [DATA_WIDTH-1:0] pe_out_west_0[X_dim-1:0];
	logic [DATA_WIDTH-1:0] pe_out_west_1[X_dim-1:0];
	logic [DATA_WIDTH-1:0] pe_out_east_0[X_dim-1:0];
	logic [DATA_WIDTH-1:0] pe_out_east_1[X_dim-1:0];
	
	// PE CLUSTER WEST 0	
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_west_0
    			(
					.clk(clk),
				    .reset(reset),
					
				    .act_in(network_iact.west_data_o_west_0),
				    .filt_in(network_wght.west_data_o_west_0),
					
					.load_en_wght(load_en_wght),
					.load_en_act(load_en_iact),
					
					.start(start),
                    .pe_out(pe_out_west_0),
					.compute_done(compute_done),
					.load_done(load_done)
    			);
		
	
	// PE CLUSTER WEST 1
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_west_1
    			(
					.clk(clk),
				    .reset(reset),
					
				    .act_in(network_iact.west_data_o_west_1),
				    .filt_in(network_wght.west_data_o_west_1),
					
					.load_en_wght(load_en_wght),
					.load_en_act(load_en_iact),
					
					.start(start),
                    .pe_out(pe_out_west_1),
					.compute_done(),
					.load_done()
    			);
				
	
	// PE CLUSTER EAST 0
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_east_0
    			(
					.clk(clk),
				    .reset(reset),
					
				    .act_in(network_iact.east_data_o_east_0),
				    .filt_in(network_wght.east_data_o_east_0),
					
					.load_en_wght(load_en_wght),
					.load_en_act(load_en_iact),
					
					.start(start),
                    .pe_out(pe_out_east_0),
					.compute_done(),
					.load_done()
    			);
				
			
	// PE CLUSTER EAST 1	
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_east_1
    			(
					.clk(clk),
				    .reset(reset),
					
				    .act_in(network_iact.east_data_o_east_1),
				    .filt_in(network_wght.east_data_o_east_1),
					
					.load_en_wght(load_en_wght),
					.load_en_act(load_en_iact),
					
					.start(start),
                    .pe_out(pe_out_east_1),
					.compute_done(),
					.load_done()
    			);
		
/* 	logic [DATA_WIDTH-1:0] temp;
	assign temp = wght_router_east_0.south_data_o;
	
	logic temp_en;
	assign temp_en = wght_router_east_0.south_enable_o; */
	
		
/* 	initial begin
		for(int i=0; i<20; i++) begin
			west_data_i_west_0 = i;
//			south_data_i = i*2;
//			west_data_i = i*5;
//			east_data_i = i*100;
			#50;
		end
	end */
	
	
	integer clk_prd = 10;
	logic [DATA_WIDTH-1:0] cluster_out_1[0:8];
	
	always begin
		clk = 0; #(clk_prd/2);
		clk = 1; #(clk_prd/2);
		//0.1GHz
	end
	
	
	enum logic [3:0] {ALL=0, NORTH=1, SOUTH=2, WEST=3, EAST=4,
						EASTNORTH=5, EASTSOUTH=6, EASTWEST=7,
						WESTNORTH=8, WESTSOUTH=9, WESTEAST=10} direction;
	
	initial begin
	
		reset = 1; #30;
		reset = 0;
		start = 0;
		
		
		router_mode_west_0_whgt = ALL;

		router_mode_east_0_whgt = EASTSOUTH;
		
		router_mode_west_1_whgt = WEST;
		
		router_mode_east_1_whgt = EAST;
		
		

		#100;
		
		$display("\n\nLoading Begins: Weights.....\n\n");
		
		load_en_wght = 1;
		west_enable_i_west_0_whgt = 1;
		
		for(int i=0; i<kernel_size**2; i++) begin
			west_data_i_west_0_whgt = 1;
			#(clk_prd);
			load_en_wght = 0;
		end
		
		
		
		
		
		router_mode_east_0_iact = EAST;
		router_mode_east_1_iact = EAST;
		
		router_mode_west_0_iact = WEST;
		router_mode_west_1_iact = WEST;
		
		#100;
		
		$display("\n\nLoading Begins: Iacts.....\n\n");
		
		load_en_iact = 1;
		
		east_enable_i_east_0_iact = 1;
		east_enable_i_east_1_iact = 1;
		
		west_enable_i_west_0_iact = 1;
		west_enable_i_west_1_iact = 1;
		
		for(int i=1; i<act_size**2+1; i++) begin
			east_data_i_east_0_iact = i;
			east_data_i_east_1_iact = i+1;
			west_data_i_west_0_iact = i+2;
			west_data_i_west_1_iact = i+3;
			#(clk_prd);	
			load_en_iact = 0;
		end
		
		
		
		
		#50;
		
		assign pe_out = pe_out_east_0;
		
		start = 1; #25; 
		$display("\n\nReading & Computing Begins.....\n\n");
		start = 0;
		
		wait (compute_done == 1);
		
		$display("\n\nFinal PSUM of Iteration 1");
 		for(int i=0; i<X_dim; i++) begin
			cluster_out_1[i] = pe_out[X_dim-i-1];
			$display("\npsum from column %d is:%d",i+1,pe_out[X_dim-i-1]);
		end
		
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 2.....\n\n");
		start = 0;
		
				wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 2:");
 		for(int i=0; i<X_dim; i++) begin
			cluster_out_1[i+5] = pe_out[X_dim-i-1];
			$display("\npsum from column %d is:%d",i+1,pe_out[X_dim-i-1]);
		end
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 3.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 3:");
 		for(int i=0; i<X_dim; i++) begin
		cluster_out_1[i+10] = pe_out[X_dim-i-1];
			$display("\npsum from column %d is:%d",i+1,pe_out[X_dim-i-1]);
		end
		 
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 4.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 4:");
 		for(int i=0; i<X_dim; i++) begin
		cluster_out_1[i+15] = pe_out[X_dim-i-1];
			$display("\npsum from column %d is:%d",i+1,pe_out[X_dim-i-1]);
		end
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 5.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 5:");
 		for(int i=0; i<X_dim; i++) begin
		cluster_out_1[i+20] = pe_out[X_dim-i-1];
			$display("\npsum from column %d is:%d",i+1,pe_out[X_dim-i-1]);
		end
		
		
		$display("\tFinal psums of Cluster 1:\n");
		for(int a=0; a<kernel_size**2; a++) begin
			$display("\t\t %d \n",cluster_out_1[a]);
		end
		
		$display("\tTotal #cycles taken: %d",cycles);
		$stop;
		
		
	end 
	
		int cycles;
		// track # of cycles
	always @(posedge clk)
	begin
		if (reset)
			cycles = 0;
		else
			cycles = cycles + 1;
	end


endmodule


================================================
FILE: testbench/phase_3/router_pe_4_clusters_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/13/2019 04:47:06 AM
// Design Name: 
// Module Name: router_pe_4_clusters
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_pe_4_clusters_tb();

	parameter DATA_WIDTH = 16;
	
	
	///////////////      WGHT ROUTER WEST 0      ///////////////////////////////////
	
	logic [3:0] router_mode_west_0_whgt;
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i_west_0_whgt;
	logic west_enable_i_west_0_whgt;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] west_data_o_west_0_whgt;
	logic west_enable_o_west_0_whgt;

	
	
		///////////////      WGHT ROUTER WEST 1     ///////////////////////////////////
	
	logic [3:0] router_mode_west_1_whgt;
	
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i_west_1_whgt;
	logic west_enable_i_west_1_whgt;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] west_data_o_west_1_whgt;
	logic west_enable_o_west_1_whgt;

		
			///////////////      WGHT ROUTER EAST 0    ///////////////////////////////////
	
	logic [3:0] router_mode_east_0_whgt;
	
	
	//Interface with East
	//Source ports
	logic [DATA_WIDTH-1:0] east_data_i_east_0_whgt;
	logic east_enable_i_east_0_whgt;

	//Destination ports
	logic [DATA_WIDTH-1:0] east_data_o_east_0_whgt;
	logic east_enable_o_east_0_whgt;

		
		
			///////////////      WGHT ROUTER EAST 1     ///////////////////////////////////
	
	logic [3:0] router_mode_east_1_whgt;
	
	
	//Interface with East
	//Source ports
	logic [DATA_WIDTH-1:0] east_data_i_east_1_whgt;
	logic east_enable_i_east_1_whgt;

	//Destination ports
	logic [DATA_WIDTH-1:0] east_data_o_east_1_whgt;
	logic east_enable_o_east_1_whgt;

	
	
	router_network4 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	network_wght
		(
			.router_mode_west_0(router_mode_west_0_whgt),
			.router_mode_west_1(router_mode_west_1_whgt),
			.router_mode_east_0(router_mode_east_0_whgt),
			.router_mode_east_1(router_mode_east_1_whgt),
			
			
			//WEST 0
			//Source Ports
			.west_data_i_west_0(west_data_i_west_0_whgt),
			.west_enable_i_west_0(west_enable_i_west_0_whgt),
			
			//Destination ports
			.west_data_o_west_0(west_data_o_west_0_whgt),
			.west_enable_o_west_0(west_enable_o_west_0_whgt),
			
			
			
			//WEST 1
			//Source Ports
			.west_data_i_west_1(west_data_i_west_1_whgt),
			.west_enable_i_west_1(west_enable_i_west_1_whgt),
			
			//Destination ports
			.west_data_o_west_1(west_data_o_west_1_whgt),
			.west_enable_o_west_1(west_enable_o_west_1_whgt),
			
			
			
			//EAST 0
			//Source Ports
			.east_data_i_east_0(east_data_i_east_0_whgt),
			.east_enable_i_east_0(east_enable_i_east_0_whgt),
			
			//Destination ports
			.east_data_o_east_0(east_data_o_east_0_whgt),
			.east_enable_o_east_0(east_enable_o_east_0_whgt),
			
			
			//east 1
			//Source Ports
			.east_data_i_east_1(east_data_i_east_1_whgt),
			.east_enable_i_east_1(east_enable_i_east_1_whgt),
			
			//Destination ports
			.east_data_o_east_1(east_data_o_east_1_whgt),
			.east_enable_o_east_1(east_enable_o_east_1_whgt)
			
		);

	
	
	
		///////////////      IACT ROUTER WEST 0      ///////////////////////////////////
	
	logic [3:0] router_mode_west_0_iact;
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i_west_0_iact;
	logic west_enable_i_west_0_iact;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] west_data_o_west_0_iact;
	logic west_enable_o_west_0_iact;

	
	
		///////////////      IACT ROUTER WEST 1     ///////////////////////////////////
	
	logic [3:0] router_mode_west_1_iact;
	
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i_west_1_iact;
	logic west_enable_i_west_1_iact;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] west_data_o_west_1_iact;
	logic west_enable_o_west_1_iact;

		
			///////////////      IACT ROUTER EAST 0    ///////////////////////////////////
	
	logic [3:0] router_mode_east_0_iact;
	
	
	//Interface with East
	//Source ports
	logic [DATA_WIDTH-1:0] east_data_i_east_0_iact;
	logic east_enable_i_east_0_iact;

	//Destination ports
	logic [DATA_WIDTH-1:0] east_data_o_east_0_iact;
	logic east_enable_o_east_0_iact;

		
		
			///////////////      IACT ROUTER EAST 1     ///////////////////////////////////
	
	logic [3:0] router_mode_east_1_iact;
	
	
	//Interface with East
	//Source ports
	logic [DATA_WIDTH-1:0] east_data_i_east_1_iact;
	logic east_enable_i_east_1_iact;

	//Destination ports
	logic [DATA_WIDTH-1:0] east_data_o_east_1_iact;
	logic east_enable_o_east_1_iact;

	
	
	router_network4 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	network_iact
		(
			.router_mode_west_0(router_mode_west_0_iact),
			.router_mode_west_1(router_mode_west_1_iact),
			.router_mode_east_0(router_mode_east_0_iact),
			.router_mode_east_1(router_mode_east_1_iact),
			
			
			//WEST 0
			//Source Ports
			.west_data_i_west_0(west_data_i_west_0_iact),
			.west_enable_i_west_0(west_enable_i_west_0_iact),
			
			//Destination ports
			.west_data_o_west_0(west_data_o_west_0_iact),
			.west_enable_o_west_0(west_enable_o_west_0_iact),
			
			
			
			//WEST 1
			//Source Ports
			.west_data_i_west_1(west_data_i_west_1_iact),
			.west_enable_i_west_1(west_enable_i_west_1_iact),
			
			//Destination ports
			.west_data_o_west_1(west_data_o_west_1_iact),
			.west_enable_o_west_1(west_enable_o_west_1_iact),
			
			
			
			//EAST 0
			//Source Ports
			.east_data_i_east_0(east_data_i_east_0_iact),
			.east_enable_i_east_0(east_enable_i_east_0_iact),
			
			//Destination ports
			.east_data_o_east_0(east_data_o_east_0_iact),
			.east_enable_o_east_0(east_enable_o_east_0_iact),
			
			
			//east 1
			//Source Ports
			.east_data_i_east_1(east_data_i_east_1_iact),
			.east_enable_i_east_1(east_enable_i_east_1_iact),
			
			//Destination ports
			.east_data_o_east_1(east_data_o_east_1_iact),
			.east_enable_o_east_1(east_enable_o_east_1_iact)
			
		);
		
		
	
	logic clk, reset;
	
	
	/////// INST PE CLUSTER
	parameter ADDR_WIDTH = 9;
    
    parameter int X_dim = 3;
    parameter int Y_dim = 3;
    
    parameter int kernel_size = 3;
    parameter int act_size = 5;
		
//    logic [DATA_WIDTH-1:0] act_in;
//    logic [DATA_WIDTH-1:0] filt_in;

	logic start;
	logic load_en_wght, load_en_iact;
  
	logic compute_done;
	logic load_done;
	
	
	logic [DATA_WIDTH-1:0] pe_out[X_dim-1:0];
	logic [DATA_WIDTH-1:0] pe_out_west_0[X_dim-1:0];
	logic [DATA_WIDTH-1:0] pe_out_west_1[X_dim-1:0];
	logic [DATA_WIDTH-1:0] pe_out_east_0[X_dim-1:0];
	logic [DATA_WIDTH-1:0] pe_out_east_1[X_dim-1:0];
	
	// PE CLUSTER WEST 0	
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_west_0
    			(
					.clk(clk),
				    .reset(reset),
					
				    .act_in(network_iact.west_data_o_west_0),
				    .filt_in(network_wght.west_data_o_west_0),
					
					.load_en_wght(load_en_wght),
					.load_en_act(load_en_iact),
					
					.start(start),
                    .pe_out(pe_out_west_0),
					.compute_done(compute_done),
					.load_done(load_done)
    			);
		
	
	// PE CLUSTER WEST 1
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_west_1
    			(
					.clk(clk),
				    .reset(reset),
					
				    .act_in(network_iact.west_data_o_west_1),
				    .filt_in(network_wght.west_data_o_west_1),
					
					.load_en_wght(load_en_wght),
					.load_en_act(load_en_iact),
					
					.start(start),
                    .pe_out(pe_out_west_1),
					.compute_done(),
					.load_done()
    			);
				
	
	// PE CLUSTER EAST 0
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_east_0
    			(
					.clk(clk),
				    .reset(reset),
					
				    .act_in(network_iact.east_data_o_east_0),
				    .filt_in(network_wght.east_data_o_east_0),
					
					.load_en_wght(load_en_wght),
					.load_en_act(load_en_iact),
					
					.start(start),
                    .pe_out(pe_out_east_0),
					.compute_done(),
					.load_done()
    			);
				
			
	// PE CLUSTER EAST 1	
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_east_1
    			(
					.clk(clk),
				    .reset(reset),
					
				    .act_in(network_iact.east_data_o_east_1),
				    .filt_in(network_wght.east_data_o_east_1),
					
					.load_en_wght(load_en_wght),
					.load_en_act(load_en_iact),
					
					.start(start),
                    .pe_out(pe_out_east_1),
					.compute_done(),
					.load_done()
    			);
		
/* 	logic [DATA_WIDTH-1:0] temp;
	assign temp = wght_router_east_0.south_data_o;
	
	logic temp_en;
	assign temp_en = wght_router_east_0.south_enable_o; */
	
		
/* 	initial begin
		for(int i=0; i<20; i++) begin
			west_data_i_west_0 = i;
//			south_data_i = i*2;
//			west_data_i = i*5;
//			east_data_i = i*100;
			#50;
		end
	end */
	
	
	integer clk_prd = 10;
	logic [DATA_WIDTH-1:0] cluster_out_1[0:8];
	
	always begin
		clk = 0; #(clk_prd/2);
		clk = 1; #(clk_prd/2);
		//0.1GHz
	end
	
	
	enum logic [3:0] {ALL=0, NORTH=1, SOUTH=2, WEST=3, EAST=4,
						EASTNORTH=5, EASTSOUTH=6, EASTWEST=7,
						WESTNORTH=8, WESTSOUTH=9, WESTEAST=10} direction;
	
	initial begin
	
		reset = 1; #30;
		reset = 0;
		start = 0;
		
		
		router_mode_west_0_whgt = ALL;

		router_mode_east_0_whgt = EASTSOUTH;
		
		router_mode_west_1_whgt = WEST;
		
		router_mode_east_1_whgt = EAST;
		
		

		#100;
		
		$display("\n\nLoading Begins: Weights.....\n\n");
		
		load_en_wght = 1;
		west_enable_i_west_0_whgt = 1;
		
		for(int i=0; i<kernel_size**2; i++) begin
			west_data_i_west_0_whgt = i+1;
			#(clk_prd);
			load_en_wght = 0;
		end
		
		
		
		
		
		router_mode_east_0_iact = EAST;
		router_mode_east_1_iact = EAST;
		
		router_mode_west_0_iact = WEST;
		router_mode_west_1_iact = WEST;
		
		#100;
		
		$display("\n\nLoading Begins: Iacts.....\n\n");
		
		load_en_iact = 1;
		
		east_enable_i_east_0_iact = 1;
		east_enable_i_east_1_iact = 1;
		
		west_enable_i_west_0_iact = 1;
		west_enable_i_west_1_iact = 1;
		
		for(int i=1; i<act_size**2+1; i++) begin
			east_data_i_east_0_iact = i;
			east_data_i_east_1_iact = i+2;
			west_data_i_west_0_iact = i*5;
			west_data_i_west_1_iact = i+3;
			#(clk_prd);
			load_en_iact = 0;
		end
		
		
		
		
		#50;
		
		assign pe_out = pe_out_east_0;
		
		start = 1; #25; 
		$display("\n\nReading & Computing Begins.....\n\n");
		start = 0;
		
		wait (compute_done == 1);
		
		$display("\n\nFinal PSUM of Iteration 1");
 		for(int i=0; i<X_dim; i++) begin
			cluster_out_1[i] = pe_out[X_dim-i-1];
			$display("\npsum from column %d is:%d",i+1,pe_out[X_dim-i-1]);
		end
		
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 2.....\n\n");
		start = 0;
		
				wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 2:");
 		for(int i=0; i<X_dim; i++) begin
			cluster_out_1[i+3] = pe_out[X_dim-i-1];
			$display("\npsum from column %d is:%d",i+1,pe_out[X_dim-i-1]);
		end
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 3.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 3:");
 		for(int i=0; i<X_dim; i++) begin
		cluster_out_1[i+6] = pe_out[X_dim-i-1];
			$display("\npsum from column %d is:%d",i+1,pe_out[X_dim-i-1]);
		end
		 
		
		$display("\tFinal psums of Cluster 1:\n");
		for(int a=0; a<kernel_size**2; a++) begin
			$display("\t\t %d \n",cluster_out_1[a]);
		end
		
		$display("\tTotal #cycles taken: %d",cycles);
		$stop;
		
		
	end 
	
		int cycles;
		// track # of cycles
	always @(posedge clk)
	begin
		if (reset)
			cycles = 0;
		else
			cycles = cycles + 1;
	end


endmodule


================================================
FILE: testbench/phase_3/router_unicast_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/11/2019 07:36:26 PM
// Design Name: 
// Module Name: router_unicast_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_unicast_tb();

	parameter DATA_WIDTH = 16;
	
	
	///////////////      ROUTER WEST 0      ///////////////////////////////////
	
	logic [3:0] router_mode_west_0;
	
	
	//Interface with North
	//Source ports
	logic [DATA_WIDTH-1:0] north_data_i_west_0;
	logic north_enable_i_west_0;

	//Destination ports
	logic [DATA_WIDTH-1:0] north_data_o_west_0;
	logic north_enable_o_west_0;

	
	
	//Interface with South
	//Source ports
	logic [DATA_WIDTH-1:0] south_data_i_west_0;
	logic south_enable_i_west_0;

	//Destination ports
	logic [DATA_WIDTH-1:0] south_data_o_west_0;
	logic south_enable_o_west_0;

	
	
	//Interface with West
	//Source ports
 logic [DATA_WIDTH-1:0] west_data_i_west_0;
	logic west_enable_i_west_0;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] west_data_o_west_0;
	logic west_enable_o_west_0;

	
	
	//Interface with East
	//Source ports
//	logic [DATA_WIDTH-1:0] east_data_i_west_0;
//	logic east_enable_i_west_0;

	//Destination ports
//	logic [DATA_WIDTH-1:0] east_data_o_west_0;
//	logic east_enable_o_west_0;

	
	
	router 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_west_0
		(
			.router_mode(router_mode_west_0),
			
			
			//Interface with North
			//Source ports
			.north_data_i(north_data_i_west_0),
			.north_enable_i(north_enable_i_west_0),
			
			//Destination ports
			.north_data_o(north_data_o_west_0),
			.north_enable_o(north_enable_o_west_0),
			
			
			//Interface with South
			//Source ports
			.south_data_i(south_data_i_west_0),
			.south_enable_i(south_enable_i_west_0),
			
			//Destination ports
			.south_data_o(south_data_o_west_0),
			.south_enable_o(south_enable_o_west_0),
			
			
			//Interface with West
			//Source ports
			.west_data_i(west_data_i_west_0),
			.west_enable_i(west_enable_i_west_0),
			
			//Destination ports
			.west_data_o(west_data_0_west_0),
			.west_enable_o(west_enable_o_west_0),
			
			
			//Interface with East
			//Source ports
			.east_data_i(router_east_0.west_data_o),
			.east_enable_i(router_east_0.west_enable_o),
	        
			//Destination ports
	        .east_data_o(router_east_0.west_data_i),
            .east_enable_o(router_east_0.west_enable_i)
		);
	
	
	
	///////////////      ROUTER EAST 0      ///////////////////////////////////
		
		
	logic [3:0] router_mode_east_0;
	

	//Interface with North
	//Source ports
	logic [DATA_WIDTH-1:0] north_data_i_east_0;
	logic north_enable_i_east_0;

	//Destination ports
	logic [DATA_WIDTH-1:0] north_data_o_east_0;
	logic north_enable_o_east_0;

	
	
	//Interface with South
	//Source ports
	logic [DATA_WIDTH-1:0] south_data_i_east_0;
	logic south_enable_i_east_0;

	//Destination ports
	logic [DATA_WIDTH-1:0] south_data_o_east_0;
	logic south_enable_o_east_0;

	
	
	//Interface with West
	//Source ports
//	logic [DATA_WIDTH-1:0] west_data_i_east_0;
//	logic west_enable_i_east_0;
	
	//Destination ports
//	logic [DATA_WIDTH-1:0] west_data_o_east_0;
//	logic west_enable_o_east_0;

	
	
	//Interface with East
	//Source ports
	logic [DATA_WIDTH-1:0] east_data_i_east_0;
	logic east_enable_i_east_0;

	//Destination ports
	logic [DATA_WIDTH-1:0] east_data_o_east_0;
	logic east_enable_o_east_0;

	
	
	router 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_east_0
		(
			.router_mode(router_mode_east_0),
			
			
			//Interface with North
			//Source ports
			.north_data_i(north_data_i_east_0),
			.north_enable_i(north_enable_i_east_0),
			
			//Destination ports
			.north_data_o(north_data_o_east_0),
			.north_enable_o(north_enable_o_east_0),
			
			
			//Interface with South
			//Source ports
			.south_data_i(south_data_i_east_0),
			.south_enable_i(south_enable_i_east_0),
			
			//Destination ports
			.south_data_o(south_data_o_east_0),
			.south_enable_o(south_enable_o_east_0),
			
			
			//Interface with West
			//Source ports
			.west_data_i(router_west_0.east_data_o),
			.west_enable_i(router_west_0.east_enable_o),
			
			//Destination ports
			.west_data_o(router_west_0.east_data_i),
			.west_enable_o(router_west_0.east_enable_i),
			
			
			//Interface with East
			//Source ports
			.east_data_i(east_data_i_east_0),
			.east_enable_i(east_enable_i_east_0),
	        
			//Destination ports
	        .east_data_o(east_data_o_east_0),
            .east_enable_o(east_enable_o_east_0)
		);


		
		
	////////////// ROUTER WEST 1 /////////////////////////	
		
	logic [3:0] router_mode_west_1;
	
	
	//Interface with North
	//Source ports
	logic [DATA_WIDTH-1:0] north_data_i_west_1;
	logic north_enable_i_west_1;

	//Destination ports
	logic [DATA_WIDTH-1:0] north_data_o_west_1;
	logic north_enable_o_west_1;

	
	
	//Interface with South
	//Source ports
	logic [DATA_WIDTH-1:0] south_data_i_west_1;
	logic south_enable_i_west_1;

	//Destination ports
	logic [DATA_WIDTH-1:0] south_data_o_west_1;
	logic south_enable_o_west_1;

	
	
	//Interface with West
	//Source ports
 logic [DATA_WIDTH-1:0] west_data_i_west_1;
	logic west_enable_i_west_1;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] west_data_o_west_1;
	logic west_enable_o_west_1;

	
	
	//Interface with East
	//Source ports
//	logic [DATA_WIDTH-1:0] east_data_i_west_1;
//	logic east_enable_i_west_1;

	//Destination ports
//	logic [DATA_WIDTH-1:0] east_data_o_west_1;
//	logic east_enable_o_west_1;

	
	
	router 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_west_1
		(
			.router_mode(router_mode_west_1),
			
			
			//Interface with North
			//Source ports
			.north_data_i(north_data_i_west_1),
			.north_enable_i(north_enable_i_west_1),
			
			//Destination ports
			.north_data_o(north_data_o_west_1),
			.north_enable_o(north_enable_o_west_1),
			
			
			//Interface with South
			//Source ports
			.south_data_i(south_data_i_west_1),
			.south_enable_i(south_enable_i_west_1),
			
			//Destination ports
			.south_data_o(south_data_o_west_1),
			.south_enable_o(south_enable_o_west_1),
			
			
			//Interface with West
			//Source ports
			.west_data_i(west_data_i_west_1),
			.west_enable_i(west_enable_i_west_1),
			
			//Destination ports
			.west_data_o(west_data_0_west_1),
			.west_enable_o(west_enable_o_west_1),
			
			
			//Interface with East
			//Source ports
			.east_data_i(router_east_0.west_data_o),
			.east_enable_i(router_east_0.west_enable_o),
	        
			//Destination ports
	        .east_data_o(router_east_0.west_data_i),
            .east_enable_o(router_east_0.west_enable_i)
		);
	
	
	
	///////////////      ROUTER EAST 1      ///////////////////////////////////
		
		
	logic [3:0] router_mode_east_1;
	

	//Interface with North
	//Source ports
	logic [DATA_WIDTH-1:0] north_data_i_east_1;
	logic north_enable_i_east_1;

	//Destination ports
	logic [DATA_WIDTH-1:0] north_data_o_east_1;
	logic north_enable_o_east_1;

	
	
	//Interface with South
	//Source ports
	logic [DATA_WIDTH-1:0] south_data_i_east_1;
	logic south_enable_i_east_1;

	//Destination ports
	logic [DATA_WIDTH-1:0] south_data_o_east_1;
	logic south_enable_o_east_1;

	
	
	//Interface with West
	//Source ports
//	logic [DATA_WIDTH-1:0] west_data_i_east_1;
//	logic west_enable_i_east_1;
	
	//Destination ports
//	logic [DATA_WIDTH-1:0] west_data_o_east_1;
//	logic west_enable_o_east_1;

	
	
	//Interface with East
	//Source ports
	logic [DATA_WIDTH-1:0] east_data_i_east_1;
	logic east_enable_i_east_1;

	//Destination ports
	logic [DATA_WIDTH-1:0] east_data_o_east_1;
	logic east_enable_o_east_1;

	
	
	router 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_east_1
		(
			.router_mode(router_mode_east_1),
			
			
			//Interface with North
			//Source ports
			.north_data_i(north_data_i_east_1),
			.north_enable_i(north_enable_i_east_1),
			
			//Destination ports
			.north_data_o(north_data_o_east_1),
			.north_enable_o(north_enable_o_east_1),
			
			
			//Interface with South
			//Source ports
			.south_data_i(south_data_i_east_1),
			.south_enable_i(south_enable_i_east_1),
			
			//Destination ports
			.south_data_o(south_data_o_east_1),
			.south_enable_o(south_enable_o_east_1),
			
			
			//Interface with West
			//Source ports
			.west_data_i(router_west_1.east_data_o),
			.west_enable_i(router_west_1.east_enable_o),
			
			//Destination ports
			.west_data_o(router_west_1.east_data_i),
			.west_enable_o(router_west_1.east_enable_i),
			
			
			//Interface with East
			//Source ports
			.east_data_i(east_data_i_east_1),
			.east_enable_i(east_enable_i_east_1),
	        
			//Destination ports
	        .east_data_o(east_data_o_east_1),
            .east_enable_o(east_enable_o_east_1)
		);
		
		
		
		 	initial begin
		for(int i=0; i<20; i++) begin
			north_data_i_west_0 = i;
			north_data_i_west_1 = i*2;
			north_data_i_east_0 = i*10;
			north_data_i_east_1 = i*100;
			
			#50;
		end
	end
	
	enum logic [3:0] {ALL=0, NORTH=1, SOUTH=2, WEST=3, EAST=4,
						EASTNORTH=5, EASTSOUTH=6, EASTWEST=7,
						WESTNORTH=8, WESTSOUTH=9, WESTEAST=10} direction;
	
	initial begin
		router_mode_west_0 = SOUTH;
		north_enable_i_west_0 = 1;

		#100;
		router_mode_east_0 = SOUTH;
		north_enable_i_east_0 = 1;
		
		#100;
		router_mode_west_1 = SOUTH;
		north_enable_i_west_1 = 1;
		
		#100;
		router_mode_east_1 = SOUTH;
		north_enable_i_east_1 = 1;
		
	end 
	
		
endmodule


================================================
FILE: testbench/psum_3x3.txt
================================================


================================================
FILE: testbench/router_act.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/02/2019 03:12:11 PM
// Design Name: 
// Module Name: router_act
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_iact #( parameter DATA_BITWIDTH = 16,
						parameter ADDR_BITWIDTH_GLB = 10,
						parameter ADDR_BITWIDTH_SPAD = 9,
						
						parameter int X_dim = 5,
                        parameter int Y_dim = 3,
                        parameter int kernel_size = 3,
                        parameter int act_size = 5,
						
						parameter W_READ_ADDR = 0, 
                        
                        parameter W_LOAD_ADDR = 0,
						
						parameter PSUM_READ_ADDR = 500,
						parameter PSUM_LOAD_ADDR = 0
					)
					
					(	input clk,
						input reset,
						
						//for reading glb
						input [DATA_BITWIDTH-1 : 0] r_data_glb_wght,
						output logic [ADDR_BITWIDTH_GLB-1 : 0] r_addr_glb_wght,
						output logic read_req_glb_wght,
						
						//for writing to spad
						output logic [DATA_BITWIDTH-1 : 0] w_data_spad,
						output logic load_en_spad,
						
						//Input from control unit to load weights to spad
						input load_spad_ctrl
			
					);
				
					
		enum logic [2:0] {IDLE=3'b000, READ_GLB=3'b001, WRITE_SPAD=3'b010, READ_GLB_0=3'b011} state;
		
		logic [4:0] filt_count;
		
		always@(posedge clk) begin
			$display("State: %s", state.name());
			if(reset) begin
				read_req_glb_wght <= 0;
				r_addr_glb_wght <= 0;
				load_en_spad <= 0;
				filt_count <= 0;
				state <= IDLE;
			end else begin
				case(state)
					IDLE:begin
						if(load_spad_ctrl) begin
							read_req_glb_wght <= 1;
							r_addr_glb_wght <= W_READ_ADDR;
							state <= READ_GLB;
						end else begin
							read_req_glb_wght = 0;
							load_en_spad = 0;
							state <= IDLE;
						end
					end
					
					READ_GLB:begin
						load_en_spad <= 1;
						filt_count <= filt_count + 1;
						r_addr_glb_wght <= r_addr_glb_wght + 1;
						w_data_spad <= r_data_glb_wght;
						state <= WRITE_SPAD;
					end
					
					WRITE_SPAD:begin
						if(filt_count == (kernel_size**2)) begin
							w_data_spad <= r_data_glb_wght;
							filt_count <= 0;
							r_addr_glb_wght <= W_READ_ADDR;
							
							state <= IDLE;
						end else begin
							w_data_spad <= r_data_glb_wght;
							filt_count <= filt_count + 1;
							r_addr_glb_wght <= r_addr_glb_wght + 1;
							state <= WRITE_SPAD;
						end
					end
				endcase
			end
		end
 
endmodule



================================================
FILE: testbench/router_broadcast_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/11/2019 05:07:36 PM
// Design Name: 
// Module Name: router_broadcast_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_broadcast_tb();

	parameter DATA_WIDTH = 16;
	
	
	///////////////      ROUTER WEST 0      ///////////////////////////////////
	
	logic [3:0] router_mode_west_0;
	
	
	//Interface with North
	//Source ports
	logic [DATA_WIDTH-1:0] north_data_i_west_0;
	logic north_enable_i_west_0;

	//Destination ports
	logic [DATA_WIDTH-1:0] north_data_o_west_0;
	logic north_enable_o_west_0;

	
	
	//Interface with South
	//Source ports
	logic [DATA_WIDTH-1:0] south_data_i_west_0;
	logic south_enable_i_west_0;

	//Destination ports
	logic [DATA_WIDTH-1:0] south_data_o_west_0;
	logic south_enable_o_west_0;

	
	
	//Interface with West
	//Source ports
 logic [DATA_WIDTH-1:0] west_data_i_west_0;
	logic west_enable_i_west_0;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] west_data_o_west_0;
	logic west_enable_o_west_0;

	
	
	//Interface with East
	//Source ports
//	logic [DATA_WIDTH-1:0] east_data_i_west_0;
//	logic east_enable_i_west_0;

	//Destination ports
//	logic [DATA_WIDTH-1:0] east_data_o_west_0;
//	logic east_enable_o_west_0;

	
	
	router 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_west_0
		(
			.router_mode(router_mode_west_0),
			
			
			//Interface with North
			//Source ports
			.north_data_i(north_data_i_west_0),
			.north_enable_i(north_enable_i_west_0),
			
			//Destination ports
			.north_data_o(north_data_o_west_0),
			.north_enable_o(north_enable_o_west_0),
			
			
			//Interface with South
			//Source ports
			.south_data_i(south_data_i_west_0),
			.south_enable_i(south_enable_i_west_0),
			
			//Destination ports
			.south_data_o(south_data_o_west_0),
			.south_enable_o(south_enable_o_west_0),
			
			
			//Interface with West
			//Source ports
			.west_data_i(west_data_i_west_0),
			.west_enable_i(west_enable_i_west_0),
			
			//Destination ports
			.west_data_o(west_data_0_west_0),
			.west_enable_o(west_enable_o_west_0),
			
			
			//Interface with East
			//Source ports
			.east_data_i(router_east_0.west_data_o),
			.east_enable_i(router_east_0.west_enable_o),
	        
			//Destination ports
	        .east_data_o(router_east_0.west_data_i),
            .east_enable_o(router_east_0.west_enable_i)
		);
	
	
	
	///////////////      ROUTER EAST 0      ///////////////////////////////////
		
		
	logic [3:0] router_mode_east_0;
	

	//Interface with North
	//Source ports
	logic [DATA_WIDTH-1:0] north_data_i_east_0;
	logic north_enable_i_east_0;

	//Destination ports
	logic [DATA_WIDTH-1:0] north_data_o_east_0;
	logic north_enable_o_east_0;

	
	
	//Interface with South
	//Source ports
	logic [DATA_WIDTH-1:0] south_data_i_east_0;
	logic south_enable_i_east_0;

	//Destination ports
	logic [DATA_WIDTH-1:0] south_data_o_east_0;
	logic south_enable_o_east_0;

	
	
	//Interface with West
	//Source ports
//	logic [DATA_WIDTH-1:0] west_data_i_east_0;
//	logic west_enable_i_east_0;
	
	//Destination ports
//	logic [DATA_WIDTH-1:0] west_data_o_east_0;
//	logic west_enable_o_east_0;

	
	
	//Interface with East
	//Source ports
	logic [DATA_WIDTH-1:0] east_data_i_east_0;
	logic east_enable_i_east_0;

	//Destination ports
	logic [DATA_WIDTH-1:0] east_data_o_east_0;
	logic east_enable_o_east_0;

	
	
	router 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_east_0
		(
			.router_mode(router_mode_east_0),
			
			
			//Interface with North
			//Source ports
			.north_data_i(north_data_i_east_0),
			.north_enable_i(north_enable_i_east_0),
			
			//Destination ports
			.north_data_o(north_data_o_east_0),
			.north_enable_o(north_enable_o_east_0),
			
			
			//Interface with South
			//Source ports
			.south_data_i(south_data_i_east_0),
			.south_enable_i(south_enable_i_east_0),
			
			//Destination ports
			.south_data_o(south_data_o_east_0),
			.south_enable_o(south_enable_o_east_0),
			
			
			//Interface with West
			//Source ports
			.west_data_i(router_west_0.east_data_o),
			.west_enable_i(router_west_0.east_enable_o),
			
			//Destination ports
			.west_data_o(router_west_0.east_data_i),
			.west_enable_o(router_west_0.east_enable_i),
			
			
			//Interface with East
			//Source ports
			.east_data_i(east_data_i_east_0),
			.east_enable_i(east_enable_i_east_0),
	        
			//Destination ports
	        .east_data_o(east_data_o_east_0),
            .east_enable_o(east_enable_o_east_0)
		);
		
 	initial begin
		for(int i=0; i<20; i++) begin
			north_data_i_west_0 = i;
//			south_data_i = i*2;
//			west_data_i = i*5;
//			east_data_i = i*100;
			#50;
		end
	end
	
	enum logic [3:0] {ALL=0, NORTH=1, SOUTH=2, WEST=3, EAST=4,
						EASTNORTH=5, EASTSOUTH=6, EASTWEST=7,
						WESTNORTH=8, WESTSOUTH=9, WESTEAST=10} direction;
	
	initial begin
		router_mode_west_0 = EASTSOUTH;
		north_enable_i_west_0 = 1;

		#100;
		router_mode_east_0 = SOUTH;
		
		#100;
		router_mode_east_0 = EASTNORTH;
		
		#100;
		router_mode_east_0 = NORTH;
		
		#100;
		router_mode_east_0 = EASTSOUTH;
		
	end 
	
endmodule

================================================
FILE: testbench/router_cluster_5x5_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/13/2019 10:16:00 AM
// Design Name: 
// Module Name: router_cluster_5x5_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_cluster_5x5_tb();
	
	parameter DATA_BITWIDTH = 16;
	parameter ADDR_BITWIDTH = 10;
	
	parameter DATA_WIDTH = 16;
    parameter ADDR_WIDTH = 9;
	
	// GLB Cluster parameters. This TestBench uses only 1 of each
    parameter NUM_GLB_IACT = 1;
    parameter NUM_GLB_PSUM = 1;
	parameter NUM_GLB_WGHT = 1;
	
	parameter ADDR_BITWIDTH_GLB = 10;
	parameter ADDR_BITWIDTH_SPAD = 9;
	
	parameter NUM_ROUTER_PSUM = 1;
	parameter NUM_ROUTER_IACT = 1;
	parameter NUM_ROUTER_WGHT = 1;
			
	parameter int kernel_size = 5;
    parameter int act_size = 7;
	
	parameter int X_dim = 5;
    parameter int Y_dim = 5;
	
	//Used inside PEs
/* 	parameter W_READ_ADDR = 0;  
    parameter A_READ_ADDR_PE = 100;
    
    parameter W_LOAD_ADDR = 0;  
    parameter A_LOAD_ADDR_PE = 100;
    
    parameter PSUM_ADDR = 500; */
	
	parameter W_READ_ADDR = 0;  
    parameter A_READ_ADDR = 0;
    
    parameter W_LOAD_ADDR = 0;  
    parameter A_LOAD_ADDR = 0;
	
	parameter PSUM_READ_ADDR = 0;
	parameter PSUM_LOAD_ADDR = 0;
	
	int cycles, pe_cycles;
	
    logic clk;
    logic reset;

	//logic for GLB cluster
//    logic read_req_iact;
	logic read_req_psum;
//	logic read_req_wght;
	
    logic write_en_iact;
//	logic write_en_psum;
	logic write_en_wght;
	
			
	logic load_spad_ctrl_wght;
	logic load_spad_ctrl_iact;
		
//    logic [ADDR_BITWIDTH-1 : 0] r_addr_iact;
    logic [ADDR_BITWIDTH-1 : 0] r_addr_psum;
//	logic [ADDR_BITWIDTH-1 : 0] r_addr_wght;
	
    logic [ADDR_BITWIDTH-1 : 0] w_addr_iact;
    logic [ADDR_BITWIDTH-1 : 0] w_addr_psum;
	logic [ADDR_BITWIDTH-1 : 0] w_addr_wght;
	
    logic [DATA_BITWIDTH-1 : 0] w_data_iact;
    logic [DATA_BITWIDTH-1 : 0] w_data_psum;
	logic [DATA_BITWIDTH-1 : 0] w_data_wght;
	
//    logic [DATA_BITWIDTH-1 : 0] r_data_iact;
    logic [DATA_BITWIDTH-1 : 0] r_data_psum;
//   logic [DATA_BITWIDTH-1 : 0] r_data_wght;
	
	logic compute_done;
	
	
	//GLB cluster initialization
	GLB_cluster 
			#(	.DATA_BITWIDTH(DATA_BITWIDTH),
				.ADDR_BITWIDTH(ADDR_BITWIDTH),
				.NUM_GLB_IACT(NUM_GLB_IACT),
				.NUM_GLB_PSUM(NUM_GLB_PSUM),
				.NUM_GLB_WGHT(NUM_GLB_WGHT)
			)
	GLB_cluster_0
			(
				.clk(clk),   //TestBench/Controller
				.reset(reset),  //TestBench/Controller
				
				//Signals for reading from GLB
				.read_req_iact(router_cluster.read_req_glb_iact),
				.read_req_psum(read_req_psum), //Read by testbench/controller
				.read_req_wght(router_cluster_0.read_req_glb_wght),
				
			    .r_data_iact(router_cluster_0.r_data_glb_iact),
			    .r_data_psum(r_data_psum), //Read by testbench/controller
				.r_data_wght(router_cluster_0.r_data_glb_wght),
				
				.r_addr_iact(router_cluster_0.r_addr_glb_iact),
			    .r_addr_psum(r_addr_psum), //testbench for reading final psums
				.r_addr_wght(router_cluster_0.r_addr_glb_wght),

				
				//Signals for writing to GLB
			    .w_addr_iact(w_addr_iact), //testbench for writing
			    .w_addr_psum(router_cluster_0.w_addr_glb_psum),
				.w_addr_wght(w_addr_wght), //testbench for writing
 
			    .w_data_iact(w_data_iact), //testbench for writing
			    .w_data_psum(router_cluster_0.w_data_glb_psum),
				.w_data_wght(w_data_wght), //testbench for writing

				.write_en_iact(write_en_iact), //testbench for writing
				.write_en_psum(router_cluster_0.write_en_glb_psum),
				.write_en_wght(write_en_wght) //testbench for writing
			
			);

			
	logic [DATA_BITWIDTH-1 : 0] r_data_spad_psum[0:kernel_size-1];		
	
	//Router Cluster Instantiation
	router_cluster#(.DATA_BITWIDTH(DATA_BITWIDTH),
	                .ADDR_BITWIDTH_GLB(ADDR_BITWIDTH_GLB),
	                .ADDR_BITWIDTH_SPAD(ADDR_BITWIDTH_SPAD),

	                .kernel_size(kernel_size),
	                .act_size(act_size),

	                .NUM_ROUTER_PSUM(NUM_ROUTER_PSUM),
	                .NUM_ROUTER_IACT(NUM_ROUTER_IACT),
	                .NUM_ROUTER_WGHT(NUM_ROUTER_WGHT),

	                .A_READ_ADDR(A_READ_ADDR), 
	                .A_LOAD_ADDR(A_LOAD_ADDR),

	                .W_READ_ADDR(W_READ_ADDR), 
	                .W_LOAD_ADDR(W_LOAD_ADDR),

	                .PSUM_READ_ADDR(PSUM_READ_ADDR),
	                .PSUM_LOAD_ADDR(PSUM_LOAD_ADDR)
					)
	router_cluster_0
					(
					.clk(clk),  //TestBench/Controller
					.reset(reset),  //TestBench/Controller
					
					//Signals for activation router
					.r_data_glb_iact(GLB_cluster_0.r_data_iact),
					.r_addr_glb_iact(GLB_cluster_0.r_addr_iact),
					.read_req_glb_iact(GLB_cluster_0.read_req_iact),

					.w_data_spad_iact(pe_cluster_0.act_in),
					.load_en_spad_iact(pe_cluster_0.load_en_act),
					
					.load_spad_ctrl_iact(load_spad_ctrl_iact), //TestBench/Controller
					
					
					//Signals for weight router
					.r_data_glb_wght(GLB_cluster_0.r_data_wght),
					.r_addr_glb_wght(GLB_cluster_0.r_addr_wght),
					.read_req_glb_wght(GLB_cluster_0.read_req_wght),
					
					.w_data_spad_wght(pe_cluster_0.filt_in),
					.load_en_spad_wght(pe_cluster_0.load_en_wght),

					.load_spad_ctrl_wght(load_spad_ctrl_wght), //TestBench/Controller

					
					//Signals for psum router
					.r_data_spad_psum(pe_cluster_0.pe_out),
					
					.w_addr_glb_psum(GLB_cluster_0.w_addr_psum),
					.write_en_glb_psum(GLB_cluster_0.write_en_psum),
					.w_data_glb_psum(GLB_cluster_0.w_data_psum),
					
					.write_psum_ctrl(pe_cluster_0.compute_done) //Connected to compute done of PE
					);
	

//Declarations for PE_cluster
				

	
	logic [DATA_WIDTH-1:0] act_in;
    logic [DATA_WIDTH-1:0] filt_in;

	logic start;
	logic load_en_wght, load_en_act;

    logic [DATA_WIDTH-1:0] pe_out[X_dim-1:0];
  
	logic load_done; //TestBench/Controller
	
//PE_cluster Instantiation
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_0
    			(
					.clk(clk), 	   //TestBench/Controller
				    .reset(reset), //TestBench/Controller
					.start(start), //TestBench/Controller
					
				    .act_in(router_cluster_0.w_data_spad_iact),
					.filt_in(router_cluster_0.w_data_spad_wght),
					
					.load_en_wght(router_cluster_0.load_en_spad_wght),
					.load_en_act(router_cluster_0.load_en_spad_iact),
					
                    .pe_out(router_cluster_0.r_data_spad_psum),
					.compute_done(router_cluster_0.write_psum_ctrl),
					.load_done(load_done) //TestBench/Controller
    			);
				

	
	integer clk_prd = 10;
	
	always begin
		clk = 0; #(clk_prd/2);
		clk = 1; #(clk_prd/2);
		//0.1GHz
	end
	
	integer kernel_1,act_1,psum_1;
	integer w_addr = 0;
	int args;
	
	initial begin
		reset = 1; #30;
		reset = 0;
		

		//Write weights to weight glb
		write_en_wght = 1;
		kernel_1 = $fopen("kernel_5x5.txt","r");		
		while(!$feof(kernel_1))begin
			w_addr_wght = w_addr;
			args = $fscanf(kernel_1,"%d\n",w_data_wght);
			$display("Writing value %0d to address %0d in weight glb",w_data_wght,w_addr);
			w_addr++;
			#(clk_prd);
		end
		write_en_wght = 0;
		$fclose(kernel_1); 
		
		
		//Write activations to weight glb
		write_en_iact = 1;
		w_addr = 0;
		act_1 = $fopen("act_7x7.txt","r");
		while(!$feof(act_1))begin
			w_addr_iact = w_addr;
			args = $fscanf(act_1,"%d\n",w_data_iact);
			$display("Writing value %0d to address %0d in iact glb",w_data_iact,w_addr);
			w_addr++;
			#(clk_prd);
		end
		write_en_iact = 0;
		$fclose(act_1); 
		
		
		assign pe_out = pe_cluster_0.pe_out;
		assign compute_done = pe_cluster_0.compute_done;
		
		#(clk_prd);
		load_spad_ctrl_wght = 1; #15;
		load_spad_ctrl_wght = 0;
		
		wait (load_done == 1);
		
		#(clk_prd);
		load_spad_ctrl_iact = 1; #15;
		load_spad_ctrl_iact = 0;
	
		wait (load_done == 1);
	
		#(clk_prd);
		
		start = 1; 
		pe_cycles = cycles;
		#25; 
		$display("\n\nReading & Computing Begins.....\n\n");
		start = 0;
		
		wait (compute_done == 1);
		pe_cycles = cycles - pe_cycles;
		
		$display("\n\nPE_OUT from cluster is:%d\n,%d\n,%d\n",pe_cluster_0.pe_out[0],pe_cluster_0.pe_out[1],pe_cluster_0.pe_out[2]);
		#40
		$display("\n\nFinal PSUM of Iteration 1");
 		for(int i=0; i<X_dim; i++) begin
			$display("\npsum from column %d is:%d",i+1,pe_out[i]);
		end
		
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 2.....\n\n");
		start = 0;
		
				wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 2:");
 		for(int i=0; i<X_dim; i++) begin
			$display("\npsum from column %d is:%d",i+1,pe_out[i]);
		end
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 3.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 3:");
 		for(int i=0; i<X_dim; i++) begin
			$display("\npsum from column %d is:%d",i+1,pe_out[i]);
		end

				
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 5.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 4:");
 		for(int i=0; i<X_dim; i++) begin
			$display("\npsum from column %d is:%d",i+1,pe_out[i]);
		end

		
				
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 5.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 5:");
 		for(int i=0; i<X_dim; i++) begin
			$display("\npsum from column %d is:%d",i+1,pe_out[i]);
		end

		
		//Write Outputs to file
		
		$display("Total Cycles taken(including data transfer): %0d", cycles);
		$display("Total Cycle taken for computation: %0d", pe_cycles*3);
		$finish;
		
		#100;
		read_req_psum = 1;
		psum_1 = $fopen("./psum_3x3.txt","w");
		if (psum_1)  $display("File was opened successfully : %0d", psum_1);
		else     $display("File was NOT opened successfully : %0d", psum_1);
		for(int p=0; p<kernel_size**2; p++) begin
			r_addr_psum = p;
//			$fwrite(psum_1,"%d\n",r_data_psum);
			$fwrite(psum_1,"Hello\n");
			$display("Writing value %0d from address %0d GLB_psum to output text file",r_data_psum,p);
			#(clk_prd);
		end
		read_req_psum = 0;
		$fclose(psum_1);
		
		
	end

		// track # of cycles
		always @(posedge clk)
		begin
			if (reset)
				cycles = 0;
			else
				cycles = cycles + 1;
		end
	
endmodule


================================================
FILE: testbench/router_cluster_new_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/10/2019 03:55:23 AM
// Design Name: 
// Module Name: router_cluster_new_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_cluster_new_tb();

	parameter DATA_WIDTH = 16;
	
	
//Logic for WGHTs
	
	logic [3:0] router_mode_wght;
	
	//Interface with North
	//Source ports
	logic [DATA_WIDTH-1:0] north_data_i_wght;
	logic north_enable_i_wght;

	//Destination ports
	logic  [DATA_WIDTH-1:0] north_data_o_wght;
	logic  north_enable_o_wght;
	
	
	//Interface with South
	//Source ports
	logic [DATA_WIDTH-1:0] south_data_i_wght;
	logic south_enable_i_wght;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] south_data_o_wght;
	logic south_enable_o_wght;
	
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i_wght;
	logic west_enable_i_wght;
	
	//Destination ports
	logic  [DATA_WIDTH-1:0] west_data_o_wght;
	logic  west_enable_o_wght;
	

    //Interface with East - Devices
    //Source ports
    logic [DATA_WIDTH-1:0] east_data_i_wght;
    logic east_enable_i_wght;

    //Destination ports
    logic  [DATA_WIDTH-1:0] east_data_o_wght;
    logic  east_enable_o_wght;
	
	
//Logic for IACTs
	logic [3:0] router_mode_iact;
	
	//Interface with North
	//Source ports
	logic [DATA_WIDTH-1:0] north_data_i_iact;
	logic north_enable_i_iact;

	//Destination ports
	logic  [DATA_WIDTH-1:0] north_data_o_iact;
	logic  north_enable_o_iact;
	
	
	//Interface with South
	//Source ports
	logic [DATA_WIDTH-1:0] south_data_i_iact;
	logic south_enable_i_iact;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] south_data_o_iact;
	logic south_enable_o_iact;
	
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i_iact;
	logic west_enable_i_iact;
	
	//Destination ports
	logic  [DATA_WIDTH-1:0] west_data_o_iact;
	logic  west_enable_o_iact;
	

    //Interface with East - Devices
    //Source ports
    logic [DATA_WIDTH-1:0] east_data_i_iact;
    logic east_enable_i_iact;

    //Destination ports
    logic  [DATA_WIDTH-1:0] east_data_o_iact;
    logic  east_enable_o_iact;
	
	
//Logic for PSUM
	
	logic [3:0] router_mode_psum;
	
	//Interface with North
	//Source ports
	logic [DATA_WIDTH-1:0] north_data_i_psum;
	logic north_enable_i_psum;

	//Destination ports
	logic  [DATA_WIDTH-1:0] north_data_o_psum;
	logic  north_enable_o_psum;
	
	
	//Interface with South
	//Source ports
	logic [DATA_WIDTH-1:0] south_data_i_psum;
	logic south_enable_i_psum;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] south_data_o_psum;
	logic south_enable_o_psum;
	
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i_psum;
	logic west_enable_i_psum;
	
	//Destination ports
	logic  [DATA_WIDTH-1:0] west_data_o_psum;
	logic  west_enable_o_psum;
	

    //Interface with East - Devices
    //Source ports
    logic [DATA_WIDTH-1:0] east_data_i_psum;
    logic east_enable_i_psum;

    //Destination ports
    logic  [DATA_WIDTH-1:0] east_data_o_psum;
    logic  east_enable_o_psum;
	
	
	//Other logic
	//Instantiation
	enum logic [3:0] {ALL=0, NORTH=1, SOUTH=2, WEST=3, EAST=4,
						EASTNORTH=5, EASTSOUTH=6, EASTWEST=7,
						WESTNORTH=8, WESTSOUTH=9, WESTEAST=10} direction;
	
	router_cluster
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_cluster_0
		(
		
		//Ports for WGHT router
			.router_mode_wght(router_mode_wght),
			
			//Interface with North
			//Source ports
			.north_data_i_wght(north_data_i_wght),
			.north_enable_i_wght(north_enable_i_wght),
			
			//Destination ports
			.north_data_o_wght(north_data_o_wght),
			.north_enable_o_wght(north_enable_o_wght),
			
			
			//Interface with South
			//Source ports
			.south_data_i_wght(south_data_i_wght),
			.south_enable_i_wght(south_enable_i_wght),
			
			//Destination ports
			.south_data_o_wght(south_data_o_wght),
			.south_enable_o_wght(south_enable_o_wght),
			
			
			//Interface with West
			//Source ports
			.west_data_i_wght(GLB_cluster_0.r_data_wght),
			.west_enable_i_wght(west_enable_i_wght),
			
			//Destination ports
			.west_data_o_wght(west_data_o_wght),
			.west_enable_o_wght(west_enable_o_wght),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_wght(east_data_i_wght),
			.east_enable_i_wght(east_enable_i_wght),
	        
			//Destination ports
	        .east_data_o_wght(east_data_o_wght),
            .east_enable_o_wght(east_enable_o_wght),
			
		////////////////////////////////////////////
			
		//Ports for IACT router
			.router_mode_iact(router_mode_iact),
			
			//Interface with North
			//Source ports
			.north_data_i_iact(north_data_i_iact),
			.north_enable_i_iact(north_enable_i_iact),
			
			//Destination ports
			.north_data_o_iact(north_data_o_iact),
			.north_enable_o_iact(north_enable_o_iact),
			
			
			//Interface with South
			//Source ports
			.south_data_i_iact(south_data_i_iact),
			.south_enable_i_iact(south_enable_i_iact),
			
			//Destination ports
			.south_data_o_iact(south_data_o_iact),
			.south_enable_o_iact(south_enable_o_iact),
			
			
			//Interface with West
			//Source ports
			.west_data_i_iact(GLB_cluster_0.r_data_iact),
			.west_enable_i_iact(west_enable_i_iact),
			
			//Destination ports
			.west_data_o_iact(west_data_o_iact),
			.west_enable_o_iact(west_enable_o_iact),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_iact(east_data_i_iact),
			.east_enable_i_iact(east_enable_i_iact),
	        
			//Destination ports
	        .east_data_o_iact(east_data_o_iact),
            .east_enable_o_iact(east_enable_o_iact),
			
			
		////////////////////////////////////////////
			
		//Ports for PSUM router
			.router_mode_psum(router_mode_psum),
			
			//Interface with North
			//Source ports
			.north_data_i_psum(north_data_i_psum),
			.north_enable_i_psum(north_enable_i_psum),
			
			//Destination ports
			.north_data_o_psum(north_data_o_psum),
			.north_enable_o_psum(north_enable_o_psum),
			
			
			//Interface with South
			//Source ports
			.south_data_i_psum(south_data_i_psum),
			.south_enable_i_psum(south_enable_i_psum),
			
			//Destination ports
			.south_data_o_psum(south_data_o_psum),
			.south_enable_o_psum(south_enable_o_psum),
			
			
			//Interface with West
			//Source ports
			.west_data_i_psum(west_data_i_psum),
			.west_enable_i_psum(west_enable_i_psum),
			
			//Destination ports
			.west_data_o_psum(GLB_cluster_0.w_data_psum),
			.west_enable_o_psum(GLB_cluster_0.write_en_psum),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_psum(east_data_i_psum),
			.east_enable_i_psum(east_enable_i_psum),
	        
			//Destination ports
	        .east_data_o_psum(east_data_o_psum),
            .east_enable_o_psum(east_enable_o_psum)	
	);
	
	
    parameter DATA_BITWIDTH = 16;
	parameter ADDR_BITWIDTH = 10;
    parameter NUM_GLB_IACT = 1;
    parameter NUM_GLB_PSUM = 1;
	parameter NUM_GLB_WGHT = 1;
	
    logic clk;
    logic reset;

    logic read_req_iact; //[NUM_GLB_IACT-1:0];
	logic read_req_psum; //[NUM_GLB_PSUM-1:0];
	logic read_req_wght; //[NUM_GLB_WGHT-1:0];
	                    //
    logic write_en_iact; //[NUM_GLB_IACT-1:0];
	logic write_en_psum; //[NUM_GLB_PSUM-1:0];
	logic write_en_wght; //[NUM_GLB_WGHT-1:0];
	
    logic [ADDR_BITWIDTH-1 : 0] r_addr_iact; //[NUM_GLB_IACT-1:0];
    logic [ADDR_BITWIDTH-1 : 0] r_addr_psum; //[NUM_GLB_PSUM-1:0];
	logic [ADDR_BITWIDTH-1 : 0] r_addr_wght; //[NUM_GLB_WGHT-1:0];
	                                        //
    logic [ADDR_BITWIDTH-1 : 0] w_addr_iact; //[NUM_GLB_IACT-1:0];
    logic [ADDR_BITWIDTH-1 : 0] w_addr_psum; //[NUM_GLB_PSUM-1:0];
	logic [ADDR_BITWIDTH-1 : 0] w_addr_wght; //[NUM_GLB_WGHT-1:0];
	                                        //
    logic [DATA_BITWIDTH-1 : 0] w_data_iact; //[NUM_GLB_IACT-1:0];
    logic [DATA_BITWIDTH-1 : 0] w_data_psum; //[NUM_GLB_PSUM-1:0];
	logic [DATA_BITWIDTH-1 : 0] w_data_wght; //[NUM_GLB_WGHT-1:0];
	                                        //
    logic [DATA_BITWIDTH-1 : 0] r_data_iact; //[NUM_GLB_IACT-1:0];
    logic [DATA_BITWIDTH-1 : 0] r_data_psum; //[NUM_GLB_PSUM-1:0];
//    logic [DATA_BITWIDTH-1 : 0] r_data_wght[NUM_GLB_WGHT-1:0];

	GLB_cluster 
			#(	.DATA_BITWIDTH(DATA_BITWIDTH),
				.ADDR_BITWIDTH(ADDR_BITWIDTH),
				.NUM_GLB_IACT(NUM_GLB_IACT),
				.NUM_GLB_PSUM(NUM_GLB_PSUM),
				.NUM_GLB_WGHT(NUM_GLB_WGHT)
			)
	GLB_cluster_0
			(
				.clk(clk), 
				.reset(reset),
				
				.read_req_iact(read_req_iact),
				.read_req_psum(read_req_psum),
				.read_req_wght(read_req_wght),
				
				.write_en_iact(write_en_iact),
				.write_en_psum(router_cluster_0.west_enable_o_psum),
				.write_en_wght(write_en_wght),
				
				.r_addr_iact(r_addr_iact),
			    .r_addr_psum(r_addr_psum),
				.r_addr_wght(r_addr_wght),

			    .w_addr_iact(w_addr_iact),
			    .w_addr_psum(w_addr_psum),
				.w_addr_wght(w_addr_wght),

			    .w_data_iact(w_data_iact),
			    .w_data_psum(router_cluster_0.west_data_o_psum),
				.w_data_wght(w_data_wght),

			    .r_data_iact(router_cluster_0.west_data_i_iact),
			    .r_data_psum(r_data_psum),
				.r_data_wght(router_cluster_0.west_data_i_wght)
			);

	
	always begin
		clk = 0; #10;
		clk = 1; #10;
	end

	
	initial begin
		reset = 1; #30;
		reset = 0;
	
		write_en_iact = 1;
		write_en_psum = 1;
		write_en_wght = 1;
		
		for(int i=0; i<25; i++) begin
			w_addr_iact = i;
			w_data_iact = i*2;

/* 			w_addr_psum = i;
			w_data_psum = i; */
			
			w_addr_wght = i;
			w_data_wght = i*3;
			
			#20;
		end
		
		write_en_iact = 0;
		write_en_psum = 0;
		write_en_wght = 0;
		
		for(int i=0; i<2; i++) begin
			w_addr_iact = i;
			w_data_iact = i*200;

/* 			w_addr_psum = i;
			w_data_psum = i*200; */
			
			w_addr_wght = i;
			w_data_wght = i*200;			
			
			#20;
		end
		
		
/* 		read_req_iact = 1;
		read_req_psum = 1;
		read_req_wght = 1;
		
		west_enable_i_iact = 1;
		router_mode_iact = EAST;
		
		for(int i=0; i<4; i++  ) begin
			r_addr_iact = i;

			r_addr_psum = i;
			
			r_addr_wght = i;
			#20;
		end
		
		west_enable_i_iact = 0;
		west_enable_i_wght = 1;
		router_mode_wght = WESTNORTH;
		
		for(int i=4; i<8; i++  ) begin
			r_addr_iact = i;

			r_addr_psum = i;
			
			r_addr_wght = i;
			#20;
		end
		
		
		west_enable_i_wght = 0;
		west_enable_i_iact = 1;
		router_mode_iact = SOUTH;
		
		for(int i=8; i<12; i++  ) begin
			r_addr_iact = i;

			r_addr_psum = i;
			
			r_addr_wght = i;
			#20;
		end */
		
		
	//	write_en_psum = 1;
		//write_en_wght = 1;
		
		west_enable_i_psum = 1;
		router_mode_psum = WEST;
		#5;
		
		for(int i=0; i<8; i++) begin
			w_addr_psum = i;
			west_data_i_psum = i;
			#20;
		end
		#20;
		
		read_req_iact = 0;
		read_req_psum = 0;
		read_req_wght = 0;
		
		for(int i=0; i<2; i++) begin
			r_addr_iact = i;

			r_addr_psum = i;
			
			r_addr_wght = i;
			
			#20;
		end
		
	end

endmodule


================================================
FILE: testbench/router_cluster_pe_cluster_5x5_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/13/2019 09:56:29 AM
// Design Name: 
// Module Name: router_cluster_pe_cluster_5x5_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_cluster_pe_cluster_5x5_tb();

	parameter DATA_WIDTH = 16;
	
	
//Logic for WGHTs
	
	logic [3:0] router_mode_wght;
	
	//Interface with North
	//Source ports
	logic [DATA_WIDTH-1:0] north_data_i_wght;
	logic north_enable_i_wght;

	//Destination ports
	logic  [DATA_WIDTH-1:0] north_data_o_wght;
	logic  north_enable_o_wght;
	
	
	//Interface with South
	//Source ports
	logic [DATA_WIDTH-1:0] south_data_i_wght;
	logic south_enable_i_wght;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] south_data_o_wght;
	logic south_enable_o_wght;
	
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i_wght;
	logic west_enable_i_wght;
	
	//Destination ports
	logic  [DATA_WIDTH-1:0] west_data_o_wght;
	logic  west_enable_o_wght;
	

    //Interface with East - Devices
    //Source ports
    logic [DATA_WIDTH-1:0] east_data_i_wght;
    logic east_enable_i_wght;

    //Destination ports
    logic  [DATA_WIDTH-1:0] east_data_o_wght;
    logic  east_enable_o_wght;
	
	
//Logic for IACTs
	logic [3:0] router_mode_iact;
	
	//Interface with North
	//Source ports
	logic [DATA_WIDTH-1:0] north_data_i_iact;
	logic north_enable_i_iact;

	//Destination ports
	logic  [DATA_WIDTH-1:0] north_data_o_iact;
	logic  north_enable_o_iact;
	
	
	//Interface with South
	//Source ports
	logic [DATA_WIDTH-1:0] south_data_i_iact;
	logic south_enable_i_iact;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] south_data_o_iact;
	logic south_enable_o_iact;
	
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i_iact;
	logic west_enable_i_iact;
	
	//Destination ports
	logic  [DATA_WIDTH-1:0] west_data_o_iact;
	logic  west_enable_o_iact;
	

    //Interface with East - Devices
    //Source ports
    logic [DATA_WIDTH-1:0] east_data_i_iact;
    logic east_enable_i_iact;

    //Destination ports
    logic  [DATA_WIDTH-1:0] east_data_o_iact;
    logic  east_enable_o_iact;
	
	
//Logic for PSUM
	
	logic [3:0] router_mode_psum;
	
	//Interface with North
	//Source ports
	logic [DATA_WIDTH-1:0] north_data_i_psum;
	logic north_enable_i_psum;

	//Destination ports
	logic  [DATA_WIDTH-1:0] north_data_o_psum;
	logic  north_enable_o_psum;
	
	
	//Interface with South
	//Source ports
	logic [DATA_WIDTH-1:0] south_data_i_psum;
	logic south_enable_i_psum;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] south_data_o_psum;
	logic south_enable_o_psum;
	
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i_psum;
	logic west_enable_i_psum;
	
	//Destination ports
	logic  [DATA_WIDTH-1:0] west_data_o_psum;
	logic  west_enable_o_psum;
	

    //Interface with East - Devices
    //Source ports
    logic [DATA_WIDTH-1:0] east_data_i_psum;
    logic east_enable_i_psum;

    //Destination ports
    logic  [DATA_WIDTH-1:0] east_data_o_psum;
    logic  east_enable_o_psum;
	
	
	//Other logic
	//Instantiation
	enum logic [3:0] {ALL=0, NORTH=1, SOUTH=2, WEST=3, EAST=4,
						EASTNORTH=5, EASTSOUTH=6, EASTWEST=7,
						WESTNORTH=8, WESTSOUTH=9, WESTEAST=10} direction;
	
	router_cluster
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_cluster_0
		(
		
		//Ports for WGHT router
			.router_mode_wght(router_mode_wght),
			
			//Interface with North
			//Source ports
			.north_data_i_wght(north_data_i_wght),
			.north_enable_i_wght(north_enable_i_wght),
			
			//Destination ports
			.north_data_o_wght(north_data_o_wght),
			.north_enable_o_wght(north_enable_o_wght),
			
			
			//Interface with South
			//Source ports
			.south_data_i_wght(south_data_i_wght),
			.south_enable_i_wght(south_enable_i_wght),
			
			//Destination ports
			.south_data_o_wght(south_data_o_wght),
			.south_enable_o_wght(south_enable_o_wght),
			
			
			//Interface with West
			//Source ports
			.west_data_i_wght(GLB_cluster_0.r_data_wght),
			.west_enable_i_wght(west_enable_i_wght),
			
			//Destination ports
			.west_data_o_wght(pe_cluster_0.filt_in),
			.west_enable_o_wght(west_enable_o_wght),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_wght(east_data_i_wght),
			.east_enable_i_wght(east_enable_i_wght),
	        
			//Destination ports
	        .east_data_o_wght(east_data_o_wght),
            .east_enable_o_wght(east_enable_o_wght),
			
		////////////////////////////////////////////
			
		//Ports for IACT router
			.router_mode_iact(router_mode_iact),
			
			//Interface with North
			//Source ports
			.north_data_i_iact(north_data_i_iact),
			.north_enable_i_iact(north_enable_i_iact),
			
			//Destination ports
			.north_data_o_iact(north_data_o_iact),
			.north_enable_o_iact(north_enable_o_iact),
			
			
			//Interface with South
			//Source ports
			.south_data_i_iact(south_data_i_iact),
			.south_enable_i_iact(south_enable_i_iact),
			
			//Destination ports
			.south_data_o_iact(south_data_o_iact),
			.south_enable_o_iact(south_enable_o_iact),
			
			
			//Interface with West
			//Source ports
			.west_data_i_iact(GLB_cluster_0.r_data_iact),
			.west_enable_i_iact(west_enable_i_iact),
			
			//Destination ports
			.west_data_o_iact(pe_cluster_0.act_in),
			.west_enable_o_iact(west_enable_o_iact),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_iact(east_data_i_iact),
			.east_enable_i_iact(east_enable_i_iact),
	        
			//Destination ports
	        .east_data_o_iact(east_data_o_iact),
            .east_enable_o_iact(east_enable_o_iact),
			
			
		////////////////////////////////////////////
			
		//Ports for PSUM router
			.router_mode_psum(router_mode_psum),
			
			//Interface with North
			//Source ports
			.north_data_i_psum(north_data_i_psum),
			.north_enable_i_psum(north_enable_i_psum),
			
			//Destination ports
			.north_data_o_psum(north_data_o_psum),
			.north_enable_o_psum(north_enable_o_psum),
			
			
			//Interface with South
			//Source ports
			.south_data_i_psum(south_data_i_psum),
			.south_enable_i_psum(south_enable_i_psum),
			
			//Destination ports
			.south_data_o_psum(south_data_o_psum),
			.south_enable_o_psum(south_enable_o_psum),
			
			
			//Interface with West
			//Source ports
			.west_data_i_psum(west_data_i_psum),
			.west_enable_i_psum(west_enable_i_psum),
			
			//Destination ports
			.west_data_o_psum(GLB_cluster_0.w_data_psum),
			.west_enable_o_psum(GLB_cluster_0.write_en_psum),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_psum(east_data_i_psum),
			.east_enable_i_psum(east_enable_i_psum),
	        
			//Destination ports
	        .east_data_o_psum(east_data_o_psum),
            .east_enable_o_psum(east_enable_o_psum)	
	);
	
	
    parameter DATA_BITWIDTH = 16;
	parameter ADDR_BITWIDTH = 10;
    parameter NUM_GLB_IACT = 1;
    parameter NUM_GLB_PSUM = 1;
	parameter NUM_GLB_WGHT = 1;
	
    logic clk;
    logic reset;

    logic read_req_iact; //[NUM_GLB_IACT-1:0];
	logic read_req_psum; //[NUM_GLB_PSUM-1:0];
	logic read_req_wght; //[NUM_GLB_WGHT-1:0];
	                    //
    logic write_en_iact; //[NUM_GLB_IACT-1:0];
	logic write_en_psum; //[NUM_GLB_PSUM-1:0];
	logic write_en_wght; //[NUM_GLB_WGHT-1:0];
	
    logic [ADDR_BITWIDTH-1 : 0] r_addr_iact; //[NUM_GLB_IACT-1:0];
    logic [ADDR_BITWIDTH-1 : 0] r_addr_psum; //[NUM_GLB_PSUM-1:0];
	logic [ADDR_BITWIDTH-1 : 0] r_addr_wght; //[NUM_GLB_WGHT-1:0];
	                                        //
    logic [ADDR_BITWIDTH-1 : 0] w_addr_iact; //[NUM_GLB_IACT-1:0];
    logic [ADDR_BITWIDTH-1 : 0] w_addr_psum; //[NUM_GLB_PSUM-1:0];
	logic [ADDR_BITWIDTH-1 : 0] w_addr_wght; //[NUM_GLB_WGHT-1:0];
	                                        //
    logic [DATA_BITWIDTH-1 : 0] w_data_iact; //[NUM_GLB_IACT-1:0];
    logic [DATA_BITWIDTH-1 : 0] w_data_psum; //[NUM_GLB_PSUM-1:0];
	logic [DATA_BITWIDTH-1 : 0] w_data_wght; //[NUM_GLB_WGHT-1:0];
	                                        //
    logic [DATA_BITWIDTH-1 : 0] r_data_iact; //[NUM_GLB_IACT-1:0];
    logic [DATA_BITWIDTH-1 : 0] r_data_psum; //[NUM_GLB_PSUM-1:0];
//    logic [DATA_BITWIDTH-1 : 0] r_data_wght[NUM_GLB_WGHT-1:0];

	GLB_cluster 
			#(	.DATA_BITWIDTH(DATA_BITWIDTH),
				.ADDR_BITWIDTH(ADDR_BITWIDTH),
				.NUM_GLB_IACT(NUM_GLB_IACT),
				.NUM_GLB_PSUM(NUM_GLB_PSUM),
				.NUM_GLB_WGHT(NUM_GLB_WGHT)
			)
	GLB_cluster_0
			(
				.clk(clk), 
				.reset(reset),
				
				.read_req_iact(read_req_iact),
				.read_req_psum(read_req_psum),
				.read_req_wght(read_req_wght),
				
				.write_en_iact(write_en_iact),
				.write_en_psum(router_cluster_0.west_enable_o_psum),
				.write_en_wght(write_en_wght),
				
				.r_addr_iact(r_addr_iact),
			    .r_addr_psum(r_addr_psum),
				.r_addr_wght(r_addr_wght),

			    .w_addr_iact(w_addr_iact),
			    .w_addr_psum(w_addr_psum),
				.w_addr_wght(w_addr_wght),

			    .w_data_iact(w_data_iact),
			    .w_data_psum(router_cluster_0.west_data_o_psum),
				.w_data_wght(w_data_wght),

			    .r_data_iact(router_cluster_0.west_data_i_iact),
			    .r_data_psum(r_data_psum),
				.r_data_wght(router_cluster_0.west_data_i_wght)
			);
			
	//	parameter DATA_WIDTH = 16;
    parameter ADDR_WIDTH = 9;
    
    parameter int X_dim = 5;
    parameter int Y_dim = 5;
    
    parameter int kernel_size = 5;
    parameter int act_size = 7;
    
    parameter W_READ_ADDR = 0;  
    parameter A_READ_ADDR = 100;
    
    parameter W_LOAD_ADDR = 0;  
    parameter A_LOAD_ADDR = 100;
    
    parameter PSUM_ADDR = 500;
	
    logic [DATA_WIDTH-1:0] act_in;
    logic [DATA_WIDTH-1:0] filt_in;

	logic start;
	logic load_en_wght, load_en_act;

    logic [DATA_WIDTH-1:0] pe_out[X_dim-1:0];
  
	logic compute_done;
	
	
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_0
    			(
					.clk(clk),
				    .reset(reset),
				    .act_in(router_cluster_0.west_data_o_iact),
				    .filt_in(router_cluster_0.west_data_o_wght),
					.load_en_wght(load_en_wght),
					.load_en_act(load_en_act),
					.start(start),
                    .pe_out(pe_out),
					.compute_done(compute_done),
					.load_done(load_done)
    			);

				
	integer clk_prd = 10;
	
	always begin
		clk = 0; #(clk_prd/2);
		clk = 1; #(clk_prd/2);
		//0.1GHz
	end
	
	integer kernel_1,act_1,psum_1;
	integer w_addr = 0;
	int args;
	
	logic [DATA_WIDTH-1:0] cluster_out_1[0:8];
	
	initial begin
		reset = 1; #30;
		reset = 0;
		start = 0;
		
		//Write weights to weight glb
/* 		write_en_wght = 1;
		kernel_1 = $fopen("kernel_3x3.txt","r");		
		while(!$feof(kernel_1))begin
			w_addr_wght = w_addr;
			args = $fscanf(kernel_1,"%d\n",w_data_wght);
			$display("Writing value %0d to address %0d in weight glb",w_data_wght,w_addr);
			w_addr++;
			#(clk_prd);
		end
		write_en_wght = 0;
		$fclose(kernel_1); 
		
		
		//Write activations to weight glb
		write_en_iact = 1;
		w_addr = 0;
		act_1 = $fopen("act_5x5.txt","r");
		while(!$feof(act_1))begin
			w_addr_iact = w_addr;
			args = $fscanf(act_1,"%d\n",w_data_iact);
			$display("Writing value %0d to address %0d in iact glb",w_data_iact,w_addr);
			w_addr++;
			#(clk_prd);
		end
		write_en_iact = 0;
		$fclose(act_1);  */
		
			//Write weights to weight glb
 		write_en_wght = 1;		
		for(int i=0; i<kernel_size**2;i++) begin
			w_data_wght = 1;
			w_addr_wght = i;
			#(clk_prd);
		end
		write_en_wght = 0;
	
		//Write activations to weight glb
		write_en_iact = 1;
		for(int i=0; i<act_size**2;i++) begin
			w_data_iact = i+1;
			w_addr_iact = i;
			#(clk_prd);
		end
		write_en_iact = 0;

		
	#(clk_prd);
	
	assign west_data_o_wght = router_cluster_0.west_data_o_wght;
	
	$display("\n\nLoading Begins: Weights.....\n\n");
		read_req_wght = 1;
		r_addr_wght	= 0;
		#(clk_prd);
		
		west_enable_i_wght = 1;
		router_mode_wght = WEST;
		
		
	//Filter
		load_en_wght = 1;
		for(int i=1; i<=kernel_size**2; i++) begin
			r_addr_wght = i; #(clk_prd);
			$display("Weight Read: %d",west_data_o_wght);
			load_en_wght = 0;
		end
	
	read_req_wght = 0;
	west_enable_i_wght = 0;
	
	#(clk_prd);
	
	
	$display("\n\nLoading Begins: Activations.....\n\n");
		
		read_req_iact = 1;
		r_addr_iact	= 0;
		#(clk_prd);
		
		west_enable_i_iact = 1;
		router_mode_iact = WEST;
		load_en_act = 1;
		
	//Filter
		for(int i=1; i<=act_size**2; i++) begin
			r_addr_iact = i; #(clk_prd);
			load_en_act = 0;
		end
	
	read_req_iact = 0;	
	west_enable_i_iact = 0;
	
	#(clk_prd);
		
		
	
// Control for PE cluster Computations
	
	
	//logic   [31:0] dpsram[0:16383]
		
		start = 1; #25; 
		$display("\n\nReading & Computing Begins.....\n\n");
		start = 0;
		
		wait (compute_done == 1);
		
		$display("\n\nFinal PSUM of Iteration 1");
 		for(int i=0; i<X_dim; i++) begin
			cluster_out_1[i] = pe_out[X_dim-i-1];
			$display("\npsum from column %d is:%d",i+1,pe_out[X_dim-i-1]);
		end
		
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 2.....\n\n");
		start = 0;
		
				wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 2:");
 		for(int i=0; i<X_dim; i++) begin
			cluster_out_1[i+5] = pe_out[X_dim-i-1];
			$display("\npsum from column %d is:%d",i+1,pe_out[X_dim-i-1]);
		end
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 3.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 3:");
 		for(int i=0; i<X_dim; i++) begin
		cluster_out_1[i+10] = pe_out[X_dim-i-1];
			$display("\npsum from column %d is:%d",i+1,pe_out[X_dim-i-1]);
		end
		
			#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 4.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 4:");
 		for(int i=0; i<X_dim; i++) begin
		cluster_out_1[i+15] = pe_out[X_dim-i-1];
			$display("\npsum from column %d is:%d",i+1,pe_out[X_dim-i-1]);
		end
		
			#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 5.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 5:");
 		for(int i=0; i<X_dim; i++) begin
		cluster_out_1[i+20] = pe_out[X_dim-i-1];
			$display("\npsum from column %d is:%d",i+1,pe_out[X_dim-i-1]);
		end
		
		
		$display("\tFinal psums of Cluster 1:\n");
		for(int a=0; a<kernel_size**2; a++) begin
			$display("\t\t %d \n",cluster_out_1[a]);
		end
		
		$display("\tTotal #cycles taken: %d",cycles);
		$stop;
	end

		int cycles;
		// track # of cycles
	always @(posedge clk)
	begin
		if (reset)
			cycles = 0;
		else
			cycles = cycles + 1;
end

endmodule


================================================
FILE: testbench/router_cluster_pe_cluster_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/10/2019 08:31:24 AM
// Design Name: 
// Module Name: router_cluster_pe_cluster_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_cluster_pe_cluster_tb();

	parameter DATA_WIDTH = 16;
	
	
//Logic for WGHTs
	
	logic [3:0] router_mode_wght;
	
	//Interface with North
	//Source ports
	logic [DATA_WIDTH-1:0] north_data_i_wght;
	logic north_enable_i_wght;

	//Destination ports
	logic  [DATA_WIDTH-1:0] north_data_o_wght;
	logic  north_enable_o_wght;
	
	
	//Interface with South
	//Source ports
	logic [DATA_WIDTH-1:0] south_data_i_wght;
	logic south_enable_i_wght;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] south_data_o_wght;
	logic south_enable_o_wght;
	
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i_wght;
	logic west_enable_i_wght;
	
	//Destination ports
	logic  [DATA_WIDTH-1:0] west_data_o_wght;
	logic  west_enable_o_wght;
	

    //Interface with East - Devices
    //Source ports
    logic [DATA_WIDTH-1:0] east_data_i_wght;
    logic east_enable_i_wght;

    //Destination ports
    logic  [DATA_WIDTH-1:0] east_data_o_wght;
    logic  east_enable_o_wght;
	
	
//Logic for IACTs
	logic [3:0] router_mode_iact;
	
	//Interface with North
	//Source ports
	logic [DATA_WIDTH-1:0] north_data_i_iact;
	logic north_enable_i_iact;

	//Destination ports
	logic  [DATA_WIDTH-1:0] north_data_o_iact;
	logic  north_enable_o_iact;
	
	
	//Interface with South
	//Source ports
	logic [DATA_WIDTH-1:0] south_data_i_iact;
	logic south_enable_i_iact;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] south_data_o_iact;
	logic south_enable_o_iact;
	
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i_iact;
	logic west_enable_i_iact;
	
	//Destination ports
	logic  [DATA_WIDTH-1:0] west_data_o_iact;
	logic  west_enable_o_iact;
	

    //Interface with East - Devices
    //Source ports
    logic [DATA_WIDTH-1:0] east_data_i_iact;
    logic east_enable_i_iact;

    //Destination ports
    logic  [DATA_WIDTH-1:0] east_data_o_iact;
    logic  east_enable_o_iact;
	
	
//Logic for PSUM
	
	logic [3:0] router_mode_psum;
	
	//Interface with North
	//Source ports
	logic [DATA_WIDTH-1:0] north_data_i_psum;
	logic north_enable_i_psum;

	//Destination ports
	logic  [DATA_WIDTH-1:0] north_data_o_psum;
	logic  north_enable_o_psum;
	
	
	//Interface with South
	//Source ports
	logic [DATA_WIDTH-1:0] south_data_i_psum;
	logic south_enable_i_psum;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] south_data_o_psum;
	logic south_enable_o_psum;
	
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i_psum;
	logic west_enable_i_psum;
	
	//Destination ports
	logic  [DATA_WIDTH-1:0] west_data_o_psum;
	logic  west_enable_o_psum;
	

    //Interface with East - Devices
    //Source ports
    logic [DATA_WIDTH-1:0] east_data_i_psum;
    logic east_enable_i_psum;

    //Destination ports
    logic  [DATA_WIDTH-1:0] east_data_o_psum;
    logic  east_enable_o_psum;
	
	
	//Other logic
	//Instantiation
	enum logic [3:0] {ALL=0, NORTH=1, SOUTH=2, WEST=3, EAST=4,
						EASTNORTH=5, EASTSOUTH=6, EASTWEST=7,
						WESTNORTH=8, WESTSOUTH=9, WESTEAST=10} direction;
	
	router_cluster
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_cluster_0
		(
		
		//Ports for WGHT router
			.router_mode_wght(router_mode_wght),
			
			//Interface with North
			//Source ports
			.north_data_i_wght(north_data_i_wght),
			.north_enable_i_wght(north_enable_i_wght),
			
			//Destination ports
			.north_data_o_wght(north_data_o_wght),
			.north_enable_o_wght(north_enable_o_wght),
			
			
			//Interface with South
			//Source ports
			.south_data_i_wght(south_data_i_wght),
			.south_enable_i_wght(south_enable_i_wght),
			
			//Destination ports
			.south_data_o_wght(south_data_o_wght),
			.south_enable_o_wght(south_enable_o_wght),
			
			
			//Interface with West
			//Source ports
			.west_data_i_wght(GLB_cluster_0.r_data_wght),
			.west_enable_i_wght(west_enable_i_wght),
			
			//Destination ports
			.west_data_o_wght(pe_cluster_0.filt_in),
			.west_enable_o_wght(west_enable_o_wght),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_wght(east_data_i_wght),
			.east_enable_i_wght(east_enable_i_wght),
	        
			//Destination ports
	        .east_data_o_wght(east_data_o_wght),
            .east_enable_o_wght(east_enable_o_wght),
			
		////////////////////////////////////////////
			
		//Ports for IACT router
			.router_mode_iact(router_mode_iact),
			
			//Interface with North
			//Source ports
			.north_data_i_iact(north_data_i_iact),
			.north_enable_i_iact(north_enable_i_iact),
			
			//Destination ports
			.north_data_o_iact(north_data_o_iact),
			.north_enable_o_iact(north_enable_o_iact),
			
			
			//Interface with South
			//Source ports
			.south_data_i_iact(south_data_i_iact),
			.south_enable_i_iact(south_enable_i_iact),
			
			//Destination ports
			.south_data_o_iact(south_data_o_iact),
			.south_enable_o_iact(south_enable_o_iact),
			
			
			//Interface with West
			//Source ports
			.west_data_i_iact(GLB_cluster_0.r_data_iact),
			.west_enable_i_iact(west_enable_i_iact),
			
			//Destination ports
			.west_data_o_iact(pe_cluster_0.act_in),
			.west_enable_o_iact(west_enable_o_iact),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_iact(east_data_i_iact),
			.east_enable_i_iact(east_enable_i_iact),
	        
			//Destination ports
	        .east_data_o_iact(east_data_o_iact),
            .east_enable_o_iact(east_enable_o_iact),
			
			
		////////////////////////////////////////////
			
		//Ports for PSUM router
			.router_mode_psum(router_mode_psum),
			
			//Interface with North
			//Source ports
			.north_data_i_psum(north_data_i_psum),
			.north_enable_i_psum(north_enable_i_psum),
			
			//Destination ports
			.north_data_o_psum(north_data_o_psum),
			.north_enable_o_psum(north_enable_o_psum),
			
			
			//Interface with South
			//Source ports
			.south_data_i_psum(south_data_i_psum),
			.south_enable_i_psum(south_enable_i_psum),
			
			//Destination ports
			.south_data_o_psum(south_data_o_psum),
			.south_enable_o_psum(south_enable_o_psum),
			
			
			//Interface with West
			//Source ports
			.west_data_i_psum(west_data_i_psum),
			.west_enable_i_psum(west_enable_i_psum),
			
			//Destination ports
			.west_data_o_psum(GLB_cluster_0.w_data_psum),
			.west_enable_o_psum(GLB_cluster_0.write_en_psum),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i_psum(east_data_i_psum),
			.east_enable_i_psum(east_enable_i_psum),
	        
			//Destination ports
	        .east_data_o_psum(east_data_o_psum),
            .east_enable_o_psum(east_enable_o_psum)	
	);
	
	
    parameter DATA_BITWIDTH = 16;
	parameter ADDR_BITWIDTH = 10;
    parameter NUM_GLB_IACT = 1;
    parameter NUM_GLB_PSUM = 1;
	parameter NUM_GLB_WGHT = 1;
	
    logic clk;
    logic reset;

    logic read_req_iact; //[NUM_GLB_IACT-1:0];
	logic read_req_psum; //[NUM_GLB_PSUM-1:0];
	logic read_req_wght; //[NUM_GLB_WGHT-1:0];
	                    //
    logic write_en_iact; //[NUM_GLB_IACT-1:0];
	logic write_en_psum; //[NUM_GLB_PSUM-1:0];
	logic write_en_wght; //[NUM_GLB_WGHT-1:0];
	
    logic [ADDR_BITWIDTH-1 : 0] r_addr_iact; //[NUM_GLB_IACT-1:0];
    logic [ADDR_BITWIDTH-1 : 0] r_addr_psum; //[NUM_GLB_PSUM-1:0];
	logic [ADDR_BITWIDTH-1 : 0] r_addr_wght; //[NUM_GLB_WGHT-1:0];
	                                        //
    logic [ADDR_BITWIDTH-1 : 0] w_addr_iact; //[NUM_GLB_IACT-1:0];
    logic [ADDR_BITWIDTH-1 : 0] w_addr_psum; //[NUM_GLB_PSUM-1:0];
	logic [ADDR_BITWIDTH-1 : 0] w_addr_wght; //[NUM_GLB_WGHT-1:0];
	                                        //
    logic [DATA_BITWIDTH-1 : 0] w_data_iact; //[NUM_GLB_IACT-1:0];
    logic [DATA_BITWIDTH-1 : 0] w_data_psum; //[NUM_GLB_PSUM-1:0];
	logic [DATA_BITWIDTH-1 : 0] w_data_wght; //[NUM_GLB_WGHT-1:0];
	                                        //
    logic [DATA_BITWIDTH-1 : 0] r_data_iact; //[NUM_GLB_IACT-1:0];
    logic [DATA_BITWIDTH-1 : 0] r_data_psum; //[NUM_GLB_PSUM-1:0];
//    logic [DATA_BITWIDTH-1 : 0] r_data_wght[NUM_GLB_WGHT-1:0];

	GLB_cluster 
			#(	.DATA_BITWIDTH(DATA_BITWIDTH),
				.ADDR_BITWIDTH(ADDR_BITWIDTH),
				.NUM_GLB_IACT(NUM_GLB_IACT),
				.NUM_GLB_PSUM(NUM_GLB_PSUM),
				.NUM_GLB_WGHT(NUM_GLB_WGHT)
			)
	GLB_cluster_0
			(
				.clk(clk), 
				.reset(reset),
				
				.read_req_iact(read_req_iact),
				.read_req_psum(read_req_psum),
				.read_req_wght(read_req_wght),
				
				.write_en_iact(write_en_iact),
				.write_en_psum(router_cluster_0.west_enable_o_psum),
				.write_en_wght(write_en_wght),
				
				.r_addr_iact(r_addr_iact),
			    .r_addr_psum(r_addr_psum),
				.r_addr_wght(r_addr_wght),

			    .w_addr_iact(w_addr_iact),
			    .w_addr_psum(w_addr_psum),
				.w_addr_wght(w_addr_wght),

			    .w_data_iact(w_data_iact),
			    .w_data_psum(router_cluster_0.west_data_o_psum),
				.w_data_wght(w_data_wght),

			    .r_data_iact(router_cluster_0.west_data_i_iact),
			    .r_data_psum(r_data_psum),
				.r_data_wght(router_cluster_0.west_data_i_wght)
			);
			
	//	parameter DATA_WIDTH = 16;
    parameter ADDR_WIDTH = 9;
    
    parameter int X_dim = 3;
    parameter int Y_dim = 3;
    
    parameter int kernel_size = 3;
    parameter int act_size = 5;
    
    parameter W_READ_ADDR = 0;  
    parameter A_READ_ADDR = 100;
    
    parameter W_LOAD_ADDR = 0;  
    parameter A_LOAD_ADDR = 100;
    
    parameter PSUM_ADDR = 500;
	
    logic [DATA_WIDTH-1:0] act_in;
    logic [DATA_WIDTH-1:0] filt_in;

	logic start;
	logic load_en_wght, load_en_act;

    logic [DATA_WIDTH-1:0] pe_out[X_dim-1:0];
  
	logic compute_done;
	
	
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_0
    			(
					.clk(clk),
				    .reset(reset),
				    .act_in(router_cluster_0.west_data_o_iact),
				    .filt_in(router_cluster_0.west_data_o_wght),
					.load_en_wght(load_en_wght),
					.load_en_act(load_en_act),
					.start(start),
                    .pe_out(pe_out),
					.compute_done(compute_done),
					.load_done(load_done)
    			);

				
	integer clk_prd = 10;
	
	always begin
		clk = 0; #(clk_prd/2);
		clk = 1; #(clk_prd/2);
		//0.1GHz
	end
	
	integer kernel_1,act_1,psum_1;
	integer w_addr = 0;
	int args;
	
	logic [DATA_WIDTH-1:0] cluster_out_1[0:8];
	
	initial begin
		reset = 1; #30;
		reset = 0;
		start = 0;
		
		//Write weights to weight glb
/* 		write_en_wght = 1;
		kernel_1 = $fopen("kernel_3x3.txt","r");		
		while(!$feof(kernel_1))begin
			w_addr_wght = w_addr;
			args = $fscanf(kernel_1,"%d\n",w_data_wght);
			$display("Writing value %0d to address %0d in weight glb",w_data_wght,w_addr);
			w_addr++;
			#(clk_prd);
		end
		write_en_wght = 0;
		$fclose(kernel_1); 
		
		
		//Write activations to weight glb
		write_en_iact = 1;
		w_addr = 0;
		act_1 = $fopen("act_5x5.txt","r");
		while(!$feof(act_1))begin
			w_addr_iact = w_addr;
			args = $fscanf(act_1,"%d\n",w_data_iact);
			$display("Writing value %0d to address %0d in iact glb",w_data_iact,w_addr);
			w_addr++;
			#(clk_prd);
		end
		write_en_iact = 0;
		$fclose(act_1);  */
		
			//Write weights to weight glb
 		write_en_wght = 1;		
		for(int i=0; i<kernel_size**2;i++) begin
			w_data_wght = 1;
			w_addr_wght = i;
			#(clk_prd);
		end
		write_en_wght = 0;
	
		//Write activations to weight glb
		write_en_iact = 1;
		for(int i=0; i<act_size**2;i++) begin
			w_data_iact = i+1;
			w_addr_iact = i;
			#(clk_prd);
		end
		write_en_iact = 0;

		
	#(clk_prd);
	
	assign west_data_o_wght = router_cluster_0.west_data_o_wght;
	
	$display("\n\nLoading Begins: Weights.....\n\n");
		read_req_wght = 1;
		r_addr_wght	= 0;
		#(clk_prd);
		
		west_enable_i_wght = 1;
		router_mode_wght = WEST;
		
		
	//Filter
		load_en_wght = 1;
		for(int i=1; i<=kernel_size**2; i++) begin
			r_addr_wght = i; #(clk_prd);
			$display("Weight Read: %d",west_data_o_wght);
			load_en_wght = 0;
		end
	
	read_req_wght = 0;
	west_enable_i_wght = 0;
	
	#(clk_prd);
	
	
	$display("\n\nLoading Begins: Activations.....\n\n");
		
		read_req_iact = 1;
		r_addr_iact	= 0;
		#(clk_prd);
		
		west_enable_i_iact = 1;
		router_mode_iact = WEST;
		load_en_act = 1;
		
	//Filter
		for(int i=1; i<=act_size**2; i++) begin
			r_addr_iact = i; #(clk_prd);
			load_en_act = 0;
		end
	
	read_req_iact = 0;	
	west_enable_i_iact = 0;
	
	#(clk_prd);
		
		
	
// Control for PE cluster Computations
	
	
	//logic   [31:0] dpsram[0:16383]
		
		start = 1; #25; 
		$display("\n\nReading & Computing Begins.....\n\n");
		start = 0;
		
		wait (compute_done == 1);
		
		$display("\n\nFinal PSUM of Iteration 1");
 		for(int i=0; i<X_dim; i++) begin
			cluster_out_1[i] = pe_out[X_dim-i-1];
			$display("\npsum from column %d is:%d",i+1,pe_out[X_dim-i-1]);
		end
		
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 2.....\n\n");
		start = 0;
		
				wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 2:");
 		for(int i=0; i<X_dim; i++) begin
			cluster_out_1[i+3] = pe_out[X_dim-i-1];
			$display("\npsum from column %d is:%d",i+1,pe_out[X_dim-i-1]);
		end
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 3.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 3:");
 		for(int i=0; i<X_dim; i++) begin
		cluster_out_1[i+6] = pe_out[X_dim-i-1];
			$display("\npsum from column %d is:%d",i+1,pe_out[X_dim-i-1]);
		end
		 
		
		$display("\tFinal psums of Cluster 1:\n");
		for(int a=0; a<kernel_size**2; a++) begin
			$display("\t\t %d \n",cluster_out_1[a]);
		end
		
		$display("\tTotal #cycles taken: %d",cycles);
		$stop;
	end

	int cycles;
	// track # of cycles
always @(posedge clk)
begin
    if (reset)
        cycles = 0;
    else
        cycles = cycles + 1;
end

endmodule


================================================
FILE: testbench/router_cluster_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/03/2019 03:07:28 PM
// Design Name: 
// Module Name: router_cluster_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_cluster_tb();
	
	parameter DATA_BITWIDTH = 16;
	parameter ADDR_BITWIDTH = 10;
	
	parameter DATA_WIDTH = 16;
    parameter ADDR_WIDTH = 9;
	
	// GLB Cluster parameters. This TestBench uses only 1 of each
    parameter NUM_GLB_IACT = 1;
    parameter NUM_GLB_PSUM = 1;
	parameter NUM_GLB_WGHT = 1;
	
	parameter ADDR_BITWIDTH_GLB = 10;
	parameter ADDR_BITWIDTH_SPAD = 9;
	
	parameter NUM_ROUTER_PSUM = 1;
	parameter NUM_ROUTER_IACT = 1;
	parameter NUM_ROUTER_WGHT = 1;
			
	parameter int kernel_size = 3;
    parameter int act_size = 5;
	
	parameter int X_dim = 3;
    parameter int Y_dim = 3;
	
	//Used inside PEs
/* 	parameter W_READ_ADDR = 0;  
    parameter A_READ_ADDR_PE = 100;
    
    parameter W_LOAD_ADDR = 0;  
    parameter A_LOAD_ADDR_PE = 100;
    
    parameter PSUM_ADDR = 500; */
	
	parameter W_READ_ADDR = 0;  
    parameter A_READ_ADDR = 0;
    
    parameter W_LOAD_ADDR = 0;  
    parameter A_LOAD_ADDR = 0;
	
	parameter PSUM_READ_ADDR = 0;
	parameter PSUM_LOAD_ADDR = 0;
	
	int cycles, pe_cycles;
	
    logic clk;
    logic reset;

	//logic for GLB cluster
//    logic read_req_iact;
	logic read_req_psum;
//	logic read_req_wght;
	
    logic write_en_iact;
//	logic write_en_psum;
	logic write_en_wght;
	
			
	logic load_spad_ctrl_wght;
	logic load_spad_ctrl_iact;
		
//    logic [ADDR_BITWIDTH-1 : 0] r_addr_iact;
    logic [ADDR_BITWIDTH-1 : 0] r_addr_psum;
//	logic [ADDR_BITWIDTH-1 : 0] r_addr_wght;
	
    logic [ADDR_BITWIDTH-1 : 0] w_addr_iact;
    logic [ADDR_BITWIDTH-1 : 0] w_addr_psum;
	logic [ADDR_BITWIDTH-1 : 0] w_addr_wght;
	
    logic [DATA_BITWIDTH-1 : 0] w_data_iact;
    logic [DATA_BITWIDTH-1 : 0] w_data_psum;
	logic [DATA_BITWIDTH-1 : 0] w_data_wght;
	
//    logic [DATA_BITWIDTH-1 : 0] r_data_iact;
    logic [DATA_BITWIDTH-1 : 0] r_data_psum;
//   logic [DATA_BITWIDTH-1 : 0] r_data_wght;
	
	logic compute_done;
	
	
	//GLB cluster initialization
	GLB_cluster 
			#(	.DATA_BITWIDTH(DATA_BITWIDTH),
				.ADDR_BITWIDTH(ADDR_BITWIDTH),
				.NUM_GLB_IACT(NUM_GLB_IACT),
				.NUM_GLB_PSUM(NUM_GLB_PSUM),
				.NUM_GLB_WGHT(NUM_GLB_WGHT)
			)
	GLB_cluster_0
			(
				.clk(clk),   //TestBench/Controller
				.reset(reset),  //TestBench/Controller
				
				//Signals for reading from GLB
				.read_req_iact(router_cluster.read_req_glb_iact),
				.read_req_psum(read_req_psum), //Read by testbench/controller
				.read_req_wght(router_cluster_0.read_req_glb_wght),
				
			    .r_data_iact(router_cluster_0.r_data_glb_iact),
			    .r_data_psum(r_data_psum), //Read by testbench/controller
				.r_data_wght(router_cluster_0.r_data_glb_wght),
				
				.r_addr_iact(router_cluster_0.r_addr_glb_iact),
			    .r_addr_psum(r_addr_psum), //testbench for reading final psums
				.r_addr_wght(router_cluster_0.r_addr_glb_wght),

				
				//Signals for writing to GLB
			    .w_addr_iact(w_addr_iact), //testbench for writing
			    .w_addr_psum(router_cluster_0.w_addr_glb_psum),
				.w_addr_wght(w_addr_wght), //testbench for writing
 
			    .w_data_iact(w_data_iact), //testbench for writing
			    .w_data_psum(router_cluster_0.w_data_glb_psum),
				.w_data_wght(w_data_wght), //testbench for writing

				.write_en_iact(write_en_iact), //testbench for writing
				.write_en_psum(router_cluster_0.write_en_glb_psum),
				.write_en_wght(write_en_wght) //testbench for writing
			
			);

			
	logic [DATA_BITWIDTH-1 : 0] r_data_spad_psum[0:kernel_size-1];		
	
	//Router Cluster Instantiation
	router_cluster#(.DATA_BITWIDTH(DATA_BITWIDTH),
	                .ADDR_BITWIDTH_GLB(ADDR_BITWIDTH_GLB),
	                .ADDR_BITWIDTH_SPAD(ADDR_BITWIDTH_SPAD),

	                .kernel_size(kernel_size),
	                .act_size(act_size),

	                .NUM_ROUTER_PSUM(NUM_ROUTER_PSUM),
	                .NUM_ROUTER_IACT(NUM_ROUTER_IACT),
	                .NUM_ROUTER_WGHT(NUM_ROUTER_WGHT),

	                .A_READ_ADDR(A_READ_ADDR), 
	                .A_LOAD_ADDR(A_LOAD_ADDR),

	                .W_READ_ADDR(W_READ_ADDR), 
	                .W_LOAD_ADDR(W_LOAD_ADDR),

	                .PSUM_READ_ADDR(PSUM_READ_ADDR),
	                .PSUM_LOAD_ADDR(PSUM_LOAD_ADDR)
					)
	router_cluster_0
					(
					.clk(clk),  //TestBench/Controller
					.reset(reset),  //TestBench/Controller
					
					//Signals for activation router
					.r_data_glb_iact(GLB_cluster_0.r_data_iact),
					.r_addr_glb_iact(GLB_cluster_0.r_addr_iact),
					.read_req_glb_iact(GLB_cluster_0.read_req_iact),

					.w_data_spad_iact(pe_cluster_0.act_in),
					.load_en_spad_iact(pe_cluster_0.load_en_act),
					
					.load_spad_ctrl_iact(load_spad_ctrl_iact), //TestBench/Controller
					
					
					//Signals for weight router
					.r_data_glb_wght(GLB_cluster_0.r_data_wght),
					.r_addr_glb_wght(GLB_cluster_0.r_addr_wght),
					.read_req_glb_wght(GLB_cluster_0.read_req_wght),
					
					.w_data_spad_wght(pe_cluster_0.filt_in),
					.load_en_spad_wght(pe_cluster_0.load_en_wght),

					.load_spad_ctrl_wght(load_spad_ctrl_wght), //TestBench/Controller

					
					//Signals for psum router
					.r_data_spad_psum(pe_cluster_0.pe_out),
					
					.w_addr_glb_psum(GLB_cluster_0.w_addr_psum),
					.write_en_glb_psum(GLB_cluster_0.write_en_psum),
					.w_data_glb_psum(GLB_cluster_0.w_data_psum),
					
					.write_psum_ctrl(pe_cluster_0.compute_done) //Connected to compute done of PE
					);
	

//Declarations for PE_cluster
				

	
	logic [DATA_WIDTH-1:0] act_in;
    logic [DATA_WIDTH-1:0] filt_in;

	logic start;
	logic load_en_wght, load_en_act;

    logic [DATA_WIDTH-1:0] pe_out[X_dim-1:0];
  
	logic load_done; //TestBench/Controller
	
//PE_cluster Instantiation
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_0
    			(
					.clk(clk), 	   //TestBench/Controller
				    .reset(reset), //TestBench/Controller
					.start(start), //TestBench/Controller
					
				    .act_in(router_cluster_0.w_data_spad_iact),
					.filt_in(router_cluster_0.w_data_spad_wght),
					
					.load_en_wght(router_cluster_0.load_en_spad_wght),
					.load_en_act(router_cluster_0.load_en_spad_iact),
					
                    .pe_out(router_cluster_0.r_data_spad_psum),
					.compute_done(router_cluster_0.write_psum_ctrl),
					.load_done(load_done) //TestBench/Controller
    			);
				

	
	integer clk_prd = 10;
	
	always begin
		clk = 0; #(clk_prd/2);
		clk = 1; #(clk_prd/2);
		//0.1GHz
	end
	
	integer kernel_1,act_1,psum_1;
	integer w_addr = 0;
	int args;
	
	initial begin
		reset = 1; #30;
		reset = 0;
		

		//Write weights to weight glb
		write_en_wght = 1;
		kernel_1 = $fopen("kernel_3x3.txt","r");		
		while(!$feof(kernel_1))begin
			w_addr_wght = w_addr;
			args = $fscanf(kernel_1,"%d\n",w_data_wght);
			$display("Writing value %0d to address %0d in weight glb",w_data_wght,w_addr);
			w_addr++;
			#(clk_prd);
		end
		write_en_wght = 0;
		$fclose(kernel_1); 
		
		
		//Write activations to weight glb
		write_en_iact = 1;
		w_addr = 0;
		act_1 = $fopen("act_5x5.txt","r");
		while(!$feof(act_1))begin
			w_addr_iact = w_addr;
			args = $fscanf(act_1,"%d\n",w_data_iact);
			$display("Writing value %0d to address %0d in iact glb",w_data_iact,w_addr);
			w_addr++;
			#(clk_prd);
		end
		write_en_iact = 0;
		$fclose(act_1); 
		
		
		assign pe_out = pe_cluster_0.pe_out;
		assign compute_done = pe_cluster_0.compute_done;
		
		#(clk_prd);
		load_spad_ctrl_wght = 1; #15;
		load_spad_ctrl_wght = 0;
		
		wait (load_done == 1);
		
		#(clk_prd);
		load_spad_ctrl_iact = 1; #15;
		load_spad_ctrl_iact = 0;
	
		wait (load_done == 1);
	
		#(clk_prd);
		
		start = 1; 
		pe_cycles = cycles;
		#25; 
		$display("\n\nReading & Computing Begins.....\n\n");
		start = 0;
		
		wait (compute_done == 1);
		pe_cycles = cycles - pe_cycles;
		
		$display("\n\nPE_OUT from cluster is:%d\n,%d\n,%d\n",pe_cluster_0.pe_out[0],pe_cluster_0.pe_out[1],pe_cluster_0.pe_out[2]);
		#40
		$display("\n\nFinal PSUM of Iteration 1");
 		for(int i=0; i<X_dim; i++) begin
			$display("\npsum from column %d is:%d",i+1,pe_out[i]);
		end
		
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 2.....\n\n");
		start = 0;
		
				wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 2:");
 		for(int i=0; i<X_dim; i++) begin
			$display("\npsum from column %d is:%d",i+1,pe_out[i]);
		end
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 3.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 3:");
 		for(int i=0; i<X_dim; i++) begin
			$display("\npsum from column %d is:%d",i+1,pe_out[i]);
		end

		
		//Write Outputs to file
		
		$display("Total Cycles taken(including data transfer): %0d", cycles);
		$display("Total Cycle taken for computation: %0d", pe_cycles*3);
		$finish;
		
		#100;
		read_req_psum = 1;
		psum_1 = $fopen("./psum_3x3.txt","w");
		if (psum_1)  $display("File was opened successfully : %0d", psum_1);
		else     $display("File was NOT opened successfully : %0d", psum_1);
		for(int p=0; p<kernel_size**2; p++) begin
			r_addr_psum = p;
//			$fwrite(psum_1,"%d\n",r_data_psum);
			$fwrite(psum_1,"Hello\n");
			$display("Writing value %0d from address %0d GLB_psum to output text file",r_data_psum,p);
			#(clk_prd);
		end
		read_req_psum = 0;
		$fclose(psum_1);
		
		
	end

		
		// track # of cycles
		always @(posedge clk)
		begin
			if (reset)
				cycles = 0;
			else
				cycles = cycles + 1;
		end
		
endmodule


================================================
FILE: testbench/router_east_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/09/2019 11:53:15 PM
// Design Name: 
// Module Name: router_east_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_east_tb();

	parameter DATA_WIDTH = 16;
	
	logic [2:0] router_mode;
	
	//Interface with North
	//Source ports
	logic [DATA_WIDTH-1:0] north_data_i;
	logic north_enable_i;
	logic  north_ready_o;
	
	//Destination ports
	logic  [DATA_WIDTH-1:0] north_data_o;
	logic  north_enable_o;
	logic north_ready_i;
	
	
	//Interface with South
	//Source ports
	logic [DATA_WIDTH-1:0] south_data_i;
	logic south_enable_i;
	logic  south_ready_o;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] south_data_o;
	logic south_enable_o;
	logic south_ready_i;
	
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i;
	logic west_enable_i;
	logic  west_ready_o;
	
	//Destination ports
	logic  [DATA_WIDTH-1:0] west_data_o;
	logic  west_enable_o;
    logic west_ready_i;

    //Interface with East - Devices
    //Source ports
    logic [DATA_WIDTH-1:0] east_data_i;
    logic east_enable_i;
    logic  east_ready_o;
    
    //Destination ports
    logic  [DATA_WIDTH-1:0] east_data_o;
    logic  east_enable_o;
    logic east_ready_i;
	
	
	//Other logic

	//Instantiation
	
	router_east 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_east_0
		(
			.router_mode(router_mode),
			
			//Interface with North
			//Source ports
			.north_data_i(north_data_i),
			.north_enable_i(north_enable_i),
			.north_ready_o(north_ready_o),
			
			//Destination ports
			.north_data_o(north_data_o),
			.north_enable_o(north_enable_o),
			.north_ready_i(north_ready_i),
			
			
			//Interface with South
			//Source ports
			.south_data_i(south_data_i),
			.south_enable_i(south_enable_i),
			.south_ready_o(south_ready_o),
			
			//Destination ports
			.south_data_o(south_data_o),
			.south_enable_o(south_enable_o),
			.south_ready_i(south_ready_i),
			
			//Interface with West
			//Source ports
			.west_data_i(west_data_i),
			.west_enable_i(west_enable_i),
			.west_ready_o(west_ready_o),
			
			//Destination ports
			.west_data_o(west_data_o),
			.west_enable_o(west_enable_o),
			.west_ready_i(west_ready_i),
			
			
			//Interface with East - Devices
			//Source ports
			.east_data_i(east_data_i),
			.east_enable_i(east_enable_i),
			.east_ready_o(east_ready_o),
	        
			//Destination ports
	        .east_data_o(east_data_o),
            .east_enable_o(east_enable_o),
            .east_ready_i(east_ready_i)
	);
	
	initial begin
		for(int i=0; i<20; i++) begin
			north_data_i = i;
			south_data_i = i*2;
			west_data_i = i*5;
			east_data_i = i*100;
			#50;
		end
	end
	
	enum logic [2:0] {ALL=0, NORTH=1, SOUTH=2, WEST=3, EAST=4} direction;
	
	initial begin
		router_mode = ALL;
		north_enable_i = 1;
		#100;
		
		router_mode = SOUTH;
		east_enable_i = 1;
		north_enable_i = 0;
		#100;
		
		router_mode = EAST;
		east_enable_i = 1;
		north_enable_i = 0;
		#100;
		
		router_mode = WEST;
		east_enable_i = 1;
		north_enable_i = 0;
		#100;
	end
	
endmodule

================================================
FILE: testbench/router_glb_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/10/2019 01:39:48 AM
// Design Name: 
// Module Name: router_glb_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_glb_tb();

	parameter DATA_WIDTH = 16;
	
	logic [3:0] router_mode;
	
	//Interface with North
	//Source ports
	logic [DATA_WIDTH-1:0] north_data_i;
	logic north_enable_i;
//	logic  north_ready_o;
	
	//Destination ports
	logic  [DATA_WIDTH-1:0] north_data_o;
	logic  north_enable_o;
//	logic north_ready_i;
	
	
	//Interface with South
	//Source ports
	logic [DATA_WIDTH-1:0] south_data_i;
	logic south_enable_i;
//	logic  south_ready_o;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] south_data_o;
	logic south_enable_o;
//	logic south_ready_i;
	
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i;
	logic west_enable_i;
//	logic  west_ready_o;
	
	//Destination ports
	logic  [DATA_WIDTH-1:0] west_data_o;
	logic  west_enable_o;
 //   logic west_ready_i;

    //Interface with East - Devices
    //Source ports
    logic [DATA_WIDTH-1:0] east_data_i;
    logic east_enable_i;
 //   logic  east_ready_o;
    
    //Destination ports
    logic  [DATA_WIDTH-1:0] east_data_o;
    logic  east_enable_o;
 //  logic east_ready_i;
	
	
	//Other logic

	//Instantiation
		enum logic [3:0] {ALL=0, NORTH=1, SOUTH=2, WEST=3, EAST=4,
						EASTNORTH=5, EASTSOUTH=6, EASTWEST=7,
						WESTNORTH=8, WESTSOUTH=9, WESTEAST=10} direction;
	
	router_east 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_east_0
		(
			.router_mode(router_mode),
			
			//Interface with North
			//Source ports
			.north_data_i(north_data_i),
			.north_enable_i(north_enable_i),
//			.north_ready_o(north_ready_o),
			
			//Destination ports
			.north_data_o(north_data_o),
			.north_enable_o(north_enable_o),
//			.north_ready_i(north_ready_i),
			
			
			//Interface with South
			//Source ports
			.south_data_i(south_data_i),
			.south_enable_i(south_enable_i),
//			.south_ready_o(south_ready_o),
			
			//Destination ports
			.south_data_o(south_data_o),
			.south_enable_o(south_enable_o),
//			.south_ready_i(south_ready_i),
			
			//Interface with West
			//Source ports
			.west_data_i(west_data_i),
			.west_enable_i(west_enable_i),
	//		.west_ready_o(west_ready_o),
			
			//Destination ports
			.west_data_o(west_data_o),
			.west_enable_o(west_enable_o),
	//		.west_ready_i(west_ready_i),
			
			
			//Interface with East - Devices
			//Source ports
//			.east_data_i(east_data_i),
			.east_data_i(GLB_cluster_0.r_data_wght),
			.east_enable_i(east_enable_i),
	//		.east_ready_o(east_ready_o),
	        
			//Destination ports
	        .east_data_o(east_data_o),
            .east_enable_o(east_enable_o)
     //       .east_ready_i(east_ready_i)
	);
	
	
    parameter DATA_BITWIDTH = 16;
	parameter ADDR_BITWIDTH = 10;
    parameter NUM_GLB_IACT = 1;
    parameter NUM_GLB_PSUM = 1;
	parameter NUM_GLB_WGHT = 1;
	
    logic clk;
    logic reset;

    logic read_req_iact; //[NUM_GLB_IACT-1:0];
	logic read_req_psum; //[NUM_GLB_PSUM-1:0];
	logic read_req_wght; //[NUM_GLB_WGHT-1:0];
	                    //
    logic write_en_iact; //[NUM_GLB_IACT-1:0];
	logic write_en_psum; //[NUM_GLB_PSUM-1:0];
	logic write_en_wght; //[NUM_GLB_WGHT-1:0];
	
    logic [ADDR_BITWIDTH-1 : 0] r_addr_iact; //[NUM_GLB_IACT-1:0];
    logic [ADDR_BITWIDTH-1 : 0] r_addr_psum; //[NUM_GLB_PSUM-1:0];
	logic [ADDR_BITWIDTH-1 : 0] r_addr_wght; //[NUM_GLB_WGHT-1:0];
	                                        //
    logic [ADDR_BITWIDTH-1 : 0] w_addr_iact; //[NUM_GLB_IACT-1:0];
    logic [ADDR_BITWIDTH-1 : 0] w_addr_psum; //[NUM_GLB_PSUM-1:0];
	logic [ADDR_BITWIDTH-1 : 0] w_addr_wght; //[NUM_GLB_WGHT-1:0];
	                                        //
    logic [DATA_BITWIDTH-1 : 0] w_data_iact; //[NUM_GLB_IACT-1:0];
    logic [DATA_BITWIDTH-1 : 0] w_data_psum; //[NUM_GLB_PSUM-1:0];
	logic [DATA_BITWIDTH-1 : 0] w_data_wght; //[NUM_GLB_WGHT-1:0];
	                                        //
    logic [DATA_BITWIDTH-1 : 0] r_data_iact; //[NUM_GLB_IACT-1:0];
    logic [DATA_BITWIDTH-1 : 0] r_data_psum; //[NUM_GLB_PSUM-1:0];
//    logic [DATA_BITWIDTH-1 : 0] r_data_wght[NUM_GLB_WGHT-1:0];

	GLB_cluster 
			#(	.DATA_BITWIDTH(DATA_BITWIDTH),
				.ADDR_BITWIDTH(ADDR_BITWIDTH),
				.NUM_GLB_IACT(NUM_GLB_IACT),
				.NUM_GLB_PSUM(NUM_GLB_PSUM),
				.NUM_GLB_WGHT(NUM_GLB_WGHT)
			)
	GLB_cluster_0
			(
				.clk(clk), 
				.reset(reset),
				
				.read_req_iact(read_req_iact),
				.read_req_psum(read_req_psum),
				.read_req_wght(read_req_wght),
				
				.write_en_iact(write_en_iact),
				.write_en_psum(write_en_psum),
				.write_en_wght(write_en_wght),
				
				.r_addr_iact(r_addr_iact),
			    .r_addr_psum(r_addr_psum),
				.r_addr_wght(r_addr_wght),

			    .w_addr_iact(w_addr_iact),
			    .w_addr_psum(w_addr_psum),
				.w_addr_wght(w_addr_wght),

			    .w_data_iact(w_data_iact),
			    .w_data_psum(w_data_psum),
				.w_data_wght(w_data_wght),

			    .r_data_iact(r_data_iact),
			    .r_data_psum(r_data_psum),
				.r_data_wght(east_data_i)
			);

				always begin
		clk = 0; #10;
		clk = 1; #10;
	end

	
	initial begin
		reset = 1; #30;
		reset = 0;
	
		write_en_iact = 1;
		write_en_psum = 1;
		write_en_wght = 1;
		
		for(int i=0; i<25; i++) begin
			w_addr_iact = i;
			w_data_iact = i*2;

			w_addr_psum = i;
			w_data_psum = i;
			
			w_addr_wght = i;
			w_data_wght = i*3;
			
			#20;
		end
		
		write_en_iact = 0;
		write_en_psum = 0;
		write_en_wght = 0;
		
		for(int i=0; i<2; i++) begin
			w_addr_iact = i;
			w_data_iact = i*200;

			w_addr_psum = i;
			w_data_psum = i*200;
			
			w_addr_wght = i;
			w_data_wght = i*200;			
			
			#20;
		end
		
		
		read_req_iact = 1;
		read_req_psum = 1;
		read_req_wght = 1;
		
		east_enable_i = 1;
		router_mode = EAST;
		
		for(int i=0; i<4; i++  ) begin
			r_addr_iact = i;

			r_addr_psum = i;
			
			r_addr_wght = i;
			#20;
		end
	
		east_enable_i = 1;
		router_mode = NORTH;
		
		for(int i=4; i<8; i++  ) begin
			r_addr_iact = i;

			r_addr_psum = i;
			
			r_addr_wght = i;
			#20;
		end
		
		east_enable_i = 1;
		router_mode = ALL;
		
		for(int i=8; i<12; i++  ) begin
			r_addr_iact = i;

			r_addr_psum = i;
			
			r_addr_wght = i;
			#20;
		end
		
				east_enable_i = 1;
		router_mode = EASTSOUTH;
		
		for(int i=12; i<16; i++  ) begin
			r_addr_iact = i;

			r_addr_psum = i;
			
			r_addr_wght = i;
			#20;
		end
		
				east_enable_i = 1;
		router_mode = EASTWEST;
		
		for(int i=16; i<20; i++  ) begin
			r_addr_iact = i;

			r_addr_psum = i;
			
			r_addr_wght = i;
			#20;
		end
		
		read_req_iact = 0;
		read_req_psum = 0;
		read_req_wght = 0;
		
		for(int i=0; i<2; i++) begin
			r_addr_iact = i;

			r_addr_psum = i;
			
			r_addr_wght = i;
			
			#20;
		end
		
	end
		
endmodule


================================================
FILE: testbench/router_iact.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/02/2019 03:12:11 PM
// Design Name: 
// Module Name: router_act
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_iact #( parameter DATA_BITWIDTH = 16,
						parameter ADDR_BITWIDTH_GLB = 10,
						parameter ADDR_BITWIDTH_SPAD = 9,
						
						parameter int X_dim = 5,
                        parameter int Y_dim = 3,
                        parameter int kernel_size = 3,
                        parameter int act_size = 5,
						
						parameter W_READ_ADDR = 0, 
                        
                        parameter W_LOAD_ADDR = 0,
						
						parameter PSUM_READ_ADDR = 500,
						parameter PSUM_LOAD_ADDR = 0
					)
					
					(	input clk,
						input reset,
						
						//for reading glb
						input [DATA_BITWIDTH-1 : 0] r_data_glb_wght,
						output logic [ADDR_BITWIDTH_GLB-1 : 0] r_addr_glb_wght,
						output logic read_req_glb_wght,
						
						//for writing to spad
						output logic [DATA_BITWIDTH-1 : 0] w_data_spad,
						output logic load_en_spad,
						
						//Input from control unit to load weights to spad
						input load_spad_ctrl
			
					);
				
					
		enum logic [2:0] {IDLE=3'b000, READ_GLB=3'b001, WRITE_SPAD=3'b010, READ_GLB_0=3'b011} state;
		
		logic [4:0] filt_count;
		
		always@(posedge clk) begin
			$display("State: %s", state.name());
			if(reset) begin
				read_req_glb_wght <= 0;
				r_addr_glb_wght <= 0;
				load_en_spad <= 0;
				filt_count <= 0;
				state <= IDLE;
			end else begin
				case(state)
					IDLE:begin
						if(load_spad_ctrl) begin
							read_req_glb_wght <= 1;
							r_addr_glb_wght <= W_READ_ADDR;
							state <= READ_GLB;
						end else begin
							read_req_glb_wght = 0;
							load_en_spad = 0;
							state <= IDLE;
						end
					end
					
					READ_GLB:begin
						load_en_spad <= 1;
						filt_count <= filt_count + 1;
						r_addr_glb_wght <= r_addr_glb_wght + 1;
						w_data_spad <= r_data_glb_wght;
						state <= WRITE_SPAD;
					end
					
					WRITE_SPAD:begin
						if(filt_count == (kernel_size**2)) begin
							w_data_spad <= r_data_glb_wght;
							filt_count <= 0;
							r_addr_glb_wght <= W_READ_ADDR;
							
							state <= IDLE;
						end else begin
							w_data_spad <= r_data_glb_wght;
							filt_count <= filt_count + 1;
							r_addr_glb_wght <= r_addr_glb_wght + 1;
							state <= WRITE_SPAD;
						end
					end
				endcase
			end
		end
 
endmodule



================================================
FILE: testbench/router_iact_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/03/2019 07:08:42 AM
// Design Name: 
// Module Name: router_iact_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////



module router_iact_tb();

	parameter DATA_BITWIDTH = 16;
	parameter ADDR_BITWIDTH = 10;
	
	// GLB Cluster parameters. This TestBench uses only 1 of each
    parameter NUM_GLB_IACT = 1;
    parameter NUM_GLB_PSUM = 1;
	parameter NUM_GLB_WGHT = 1;
	
	
    logic clk;
    logic reset;

	//logic for GLB cluster
//    logic read_req_iact;
	logic read_req_psum;
//	logic read_req_wght;
	
    logic write_en_iact;
	logic write_en_psum;
	logic write_en_wght;
	
//    logic [ADDR_BITWIDTH-1 : 0] r_addr_iact;
    logic [ADDR_BITWIDTH-1 : 0] r_addr_psum;
//	logic [ADDR_BITWIDTH-1 : 0] r_addr_wght;
	
    logic [ADDR_BITWIDTH-1 : 0] w_addr_iact;
    logic [ADDR_BITWIDTH-1 : 0] w_addr_psum;
	logic [ADDR_BITWIDTH-1 : 0] w_addr_wght;
	
    logic [DATA_BITWIDTH-1 : 0] w_data_iact;
    logic [DATA_BITWIDTH-1 : 0] w_data_psum;
	logic [DATA_BITWIDTH-1 : 0] w_data_wght;
	
//    logic [DATA_BITWIDTH-1 : 0] r_data_iact;
    logic [DATA_BITWIDTH-1 : 0] r_data_psum;
//   logic [DATA_BITWIDTH-1 : 0] r_data_wght;

	
	//GLB cluster initialization
	GLB_cluster 
			#(	.DATA_BITWIDTH(DATA_BITWIDTH),
				.ADDR_BITWIDTH(ADDR_BITWIDTH),
				.NUM_GLB_IACT(NUM_GLB_IACT),
				.NUM_GLB_PSUM(NUM_GLB_PSUM),
				.NUM_GLB_WGHT(NUM_GLB_WGHT)
			)
	GLB_cluster_0
			(
				.clk(clk), 
				.reset(reset),
				
				.read_req_iact(router_iact_0.read_req_glb_iact),
				.read_req_psum(read_req_psum),
//				.read_req_wght(read_req_wght),
				.read_req_wght(router_weight_0.read_req_glb_wght),
				
				.write_en_iact(write_en_iact),
				.write_en_psum(write_en_psum),
				.write_en_wght(write_en_wght),
				
				.r_addr_iact(router_iact_0.r_addr_glb_iact),
			    .r_addr_psum(r_addr_psum),
//				.r_addr_wght(r_addr_wght),
				.r_addr_wght(router_weight_0.r_addr_glb_wght),

			    .w_addr_iact(w_addr_iact),
			    .w_addr_psum(w_addr_psum),
				.w_addr_wght(w_addr_wght),

			    .w_data_iact(w_data_iact),
			    .w_data_psum(w_data_psum),
				.w_data_wght(w_data_wght),

			    .r_data_iact(router_iact_0.r_data_glb_iact),
			    .r_data_psum(r_data_psum),
//				.r_data_wght(r_data_wght)
				.r_data_wght(router_weight_0.r_data_glb_wght)
			);

			
	//Declarations for weight router
	parameter ADDR_BITWIDTH_GLB = 10;
	parameter ADDR_BITWIDTH_SPAD = 9;
	
	parameter int kernel_size = 3;
	parameter int act_size = 5;
	
	parameter W_READ_ADDR = 0;
	
	parameter W_LOAD_ADDR = 0;
	
	parameter PSUM_READ_ADDR = 500;
	parameter PSUM_LOAD_ADDR = 0;
	
//	logic [ADDR_BITWIDTH_SPAD-1 : 0] w_addr_spad;
	logic [DATA_BITWIDTH-1 : 0] w_data_spad_wght;
	
	logic [DATA_BITWIDTH-1 : 0] r_data_glb_wght;
	
	logic load_en_spad_wght;
	
	logic load_spad_ctrl;
	
			
	//Weight Router Instantiation
	router_weight #(.DATA_BITWIDTH(DATA_BITWIDTH),
					.ADDR_BITWIDTH_GLB(ADDR_BITWIDTH_GLB),
					.ADDR_BITWIDTH_SPAD(ADDR_BITWIDTH_SPAD),
//					X_dim = 5,
//	                Y_dim = 3,
	                .kernel_size(kernel_size),
	                .act_size(act_size),
					
					.W_READ_ADDR(W_READ_ADDR), 
	                .W_LOAD_ADDR(W_LOAD_ADDR),
					
					.PSUM_READ_ADDR(PSUM_READ_ADDR),
					.PSUM_LOAD_ADDR(PSUM_LOAD_ADDR)
				)
	router_weight_0
				(	.clk(clk),
					.reset(reset),
					
					.r_data_glb_wght(GLB_cluster_0.r_data_wght),
//					read_wght_ctrl,
					 .r_addr_glb_wght(GLB_cluster_0.r_addr_wght),
					 .read_req_glb_wght(GLB_cluster_0.read_req_wght),
					
					//for writing to spad
//					write_wght_ctrl,
//					.w_addr_spad(w_addr_spad),
					.w_data_spad(w_data_spad_wght),
					.load_en_spad(load_en_spad_wght),
					
					//Input from control unit to load weights to spad
					.load_spad_ctrl(load_spad_ctrl)
				);
	
	
	parameter A_READ_ADDR = 0;
	parameter A_LOAD_ADDR = 100;
	
//	logic [ADDR_BITWIDTH_SPAD-1 : 0] w_addr_spad_iact;
	logic [DATA_BITWIDTH-1 : 0] w_data_spad_iact;
	
	logic [DATA_BITWIDTH-1 : 0] r_data_glb_iact;
	
	logic load_en_spad_iact;
	
	logic load_spad_ctrl_iact;
			
	//Activation Router Instantiation
	router_iact #(.DATA_BITWIDTH(DATA_BITWIDTH),
					.ADDR_BITWIDTH_GLB(ADDR_BITWIDTH_GLB),
					.ADDR_BITWIDTH_SPAD(ADDR_BITWIDTH_SPAD),
//					X_dim = 5,
//	                Y_dim = 3,
	                .kernel_size(kernel_size),
	                .act_size(act_size),
					
					.A_READ_ADDR(A_READ_ADDR), 
	                .A_LOAD_ADDR(A_LOAD_ADDR)
				)
	router_iact_0
				(	.clk(clk),
					.reset(reset),
					
					.r_data_glb_iact(GLB_cluster_0.r_data_iact),
//					read_wght_ctrl,
					 .r_addr_glb_iact(GLB_cluster_0.r_addr_iact),
					 .read_req_glb_iact(GLB_cluster_0.read_req_iact),
					
					//for writing to spad
//					write_wght_ctrl,
//					.w_addr_spad(w_addr_spad),
					.w_data_spad(w_data_spad_iact),
					.load_en_spad(load_en_spad_iact),
					
					//Input from control unit to load weights to spad
					.load_spad_ctrl(load_spad_ctrl_iact)
				);	
	
	parameter DATA_WIDTH = 16;
    parameter ADDR_WIDTH = 9;
	parameter int X_dim = 3;
    parameter int Y_dim = 3;
	
	logic [DATA_WIDTH-1:0] act_in;
    logic [DATA_WIDTH-1:0] filt_in;
//    logic load_en;
	logic start;
	logic load_en_wght, load_en_act;

    logic [DATA_WIDTH-1:0] pe_out[X_dim-1:0];
  
	logic compute_done;
	logic load_done;
	
//	logic [DATA_WIDTH-1:0] psum_out[0 : X_dim*Y_dim-1];
	
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_0
    			(
					.clk(clk),
				    .reset(reset),
				    .act_in(w_data_spad_iact),
//				    .filt_in(filt_in),
					.filt_in(w_data_spad_wght),
//				    .load_en(load_en),
					.load_en_wght(load_en_spad_wght),
					.load_en_act(load_en_spad_iact),
					.start(start),
                    .pe_out(pe_out),
					.compute_done(compute_done),
					.load_done(load_done)
					
		//extra
//					.psum_out(psum_out)
    			);
				
	
	
	
	integer clk_prd = 10;
	
	always begin
		clk = 0; #(clk_prd/2);
		clk = 1; #(clk_prd/2);
		//0.1GHz
	end
	
	integer kernel_1,act_1;
	integer w_addr = 0;
	int args;
	
	initial begin
		reset = 1; #30;
		reset = 0;
		

		//Write weights to weight glb
		write_en_wght = 1;
		kernel_1 = $fopen("kernel_3x3.txt","r");		
		while(!$feof(kernel_1))begin
			w_addr_wght = w_addr;
			args = $fscanf(kernel_1,"%d\n",w_data_wght);
			$display("Writing value %0d to address %0d in weight glb",w_data_wght,w_addr);
			w_addr++;
			#(clk_prd);
		end
		write_en_wght = 0;
		$fclose(kernel_1); 
		
		
		//Write activations to weight glb
		write_en_iact = 1;
		w_addr = 0;
		act_1 = $fopen("act_5x5.txt","r");
		while(!$feof(act_1))begin
			w_addr_iact = w_addr;
			args = $fscanf(act_1,"%d\n",w_data_iact);
			$display("Writing value %0d to address %0d in iact glb",w_data_iact,w_addr);
			w_addr++;
			#(clk_prd);
		end
		write_en_iact = 0;
		$fclose(act_1); 
		
		
		
		#300;
		load_spad_ctrl = 1; #15;
		load_spad_ctrl = 0;
		
		wait (load_done == 1);
		
		#50;
		load_spad_ctrl_iact = 1; #15;
		load_spad_ctrl_iact = 0;
	
		wait (load_done == 1);
	
		#100;
		
		start = 1; #25; 
		$display("\n\nReading & Computing Begins.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		#40
		$display("\n\nFinal PSUM of Iteration 1");
 		for(int i=0; i<X_dim; i++) begin
			$display("\npsum from column %d is:%d",i+1,pe_out[i]);
		end
		
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 2.....\n\n");
		start = 0;
		
				wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 2:");
 		for(int i=0; i<X_dim; i++) begin
			$display("\npsum from column %d is:%d",i+1,pe_out[i]);
		end
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 3.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 3:");
 		for(int i=0; i<X_dim; i++) begin
			$display("\npsum from column %d is:%d",i+1,pe_out[i]);
		end

	end
	
endmodule




================================================
FILE: testbench/router_multicast_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/11/2019 07:50:20 PM
// Design Name: 
// Module Name: router_multicast_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_multicast_tb();


	parameter DATA_WIDTH = 16;
	
	
	///////////////      ROUTER WEST 0      ///////////////////////////////////
	
	logic [3:0] router_mode_west_0;
	
	
	//Interface with North
	//Source ports
	logic [DATA_WIDTH-1:0] north_data_i_west_0;
	logic north_enable_i_west_0;

	//Destination ports
	logic [DATA_WIDTH-1:0] north_data_o_west_0;
	logic north_enable_o_west_0;

	
	
	//Interface with South
	//Source ports
	logic [DATA_WIDTH-1:0] south_data_i_west_0;
	logic south_enable_i_west_0;

	//Destination ports
	logic [DATA_WIDTH-1:0] south_data_o_west_0;
	logic south_enable_o_west_0;

	
	
	//Interface with West
	//Source ports
 logic [DATA_WIDTH-1:0] west_data_i_west_0;
	logic west_enable_i_west_0;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] west_data_o_west_0;
	logic west_enable_o_west_0;

	
	
	//Interface with East
	//Source ports
//	logic [DATA_WIDTH-1:0] east_data_i_west_0;
//	logic east_enable_i_west_0;

	//Destination ports
//	logic [DATA_WIDTH-1:0] east_data_o_west_0;
//	logic east_enable_o_west_0;

	
	
	router 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_west_0
		(
			.router_mode(router_mode_west_0),
			
			
			//Interface with North
			//Source ports
			.north_data_i(north_data_i_west_0),
			.north_enable_i(north_enable_i_west_0),
			
			//Destination ports
			.north_data_o(north_data_o_west_0),
			.north_enable_o(north_enable_o_west_0),
			
			
			//Interface with South
			//Source ports
			.south_data_i(south_data_i_west_0),
			.south_enable_i(south_enable_i_west_0),
			
			//Destination ports
			.south_data_o(south_data_o_west_0),
			.south_enable_o(south_enable_o_west_0),
			
			
			//Interface with West
			//Source ports
			.west_data_i(west_data_i_west_0),
			.west_enable_i(west_enable_i_west_0),
			
			//Destination ports
			.west_data_o(west_data_0_west_0),
			.west_enable_o(west_enable_o_west_0),
			
			
			//Interface with East
			//Source ports
			.east_data_i(router_east_0.west_data_o),
			.east_enable_i(router_east_0.west_enable_o),
	        
			//Destination ports
	        .east_data_o(router_east_0.west_data_i),
            .east_enable_o(router_east_0.west_enable_i)
		);
	
	
	
	///////////////      ROUTER EAST 0      ///////////////////////////////////
		
		
	logic [3:0] router_mode_east_0;
	

	//Interface with North
	//Source ports
	logic [DATA_WIDTH-1:0] north_data_i_east_0;
	logic north_enable_i_east_0;

	//Destination ports
	logic [DATA_WIDTH-1:0] north_data_o_east_0;
	logic north_enable_o_east_0;

	
	
	//Interface with South
	//Source ports
	logic [DATA_WIDTH-1:0] south_data_i_east_0;
	logic south_enable_i_east_0;

	//Destination ports
	logic [DATA_WIDTH-1:0] south_data_o_east_0;
	logic south_enable_o_east_0;

	
	
	//Interface with West
	//Source ports
//	logic [DATA_WIDTH-1:0] west_data_i_east_0;
//	logic west_enable_i_east_0;
	
	//Destination ports
//	logic [DATA_WIDTH-1:0] west_data_o_east_0;
//	logic west_enable_o_east_0;

	
	
	//Interface with East
	//Source ports
	logic [DATA_WIDTH-1:0] east_data_i_east_0;
	logic east_enable_i_east_0;

	//Destination ports
	logic [DATA_WIDTH-1:0] east_data_o_east_0;
	logic east_enable_o_east_0;

	
	
	router 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_east_0
		(
			.router_mode(router_mode_east_0),
			
			
			//Interface with North
			//Source ports
			.north_data_i(north_data_i_east_0),
			.north_enable_i(north_enable_i_east_0),
			
			//Destination ports
			.north_data_o(north_data_o_east_0),
			.north_enable_o(north_enable_o_east_0),
			
			
			//Interface with South
			//Source ports
			.south_data_i(south_data_i_east_0),
			.south_enable_i(south_enable_i_east_0),
			
			//Destination ports
			.south_data_o(south_data_o_east_0),
			.south_enable_o(south_enable_o_east_0),
			
			
			//Interface with West
			//Source ports
			.west_data_i(router_west_0.east_data_o),
			.west_enable_i(router_west_0.east_enable_o),
			
			//Destination ports
			.west_data_o(router_west_0.east_data_i),
			.west_enable_o(router_west_0.east_enable_i),
			
			
			//Interface with East
			//Source ports
			.east_data_i(east_data_i_east_0),
			.east_enable_i(east_enable_i_east_0),
	        
			//Destination ports
	        .east_data_o(east_data_o_east_0),
            .east_enable_o(east_enable_o_east_0)
		);


		
		
	////////////// ROUTER WEST 1 /////////////////////////	
		
	logic [3:0] router_mode_west_1;
	
	
	//Interface with North
	//Source ports
	logic [DATA_WIDTH-1:0] north_data_i_west_1;
	logic north_enable_i_west_1;

	//Destination ports
	logic [DATA_WIDTH-1:0] north_data_o_west_1;
	logic north_enable_o_west_1;

	
	
	//Interface with South
	//Source ports
	logic [DATA_WIDTH-1:0] south_data_i_west_1;
	logic south_enable_i_west_1;

	//Destination ports
	logic [DATA_WIDTH-1:0] south_data_o_west_1;
	logic south_enable_o_west_1;

	
	
	//Interface with West
	//Source ports
 logic [DATA_WIDTH-1:0] west_data_i_west_1;
	logic west_enable_i_west_1;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] west_data_o_west_1;
	logic west_enable_o_west_1;

	
	
	//Interface with East
	//Source ports
//	logic [DATA_WIDTH-1:0] east_data_i_west_1;
//	logic east_enable_i_west_1;

	//Destination ports
//	logic [DATA_WIDTH-1:0] east_data_o_west_1;
//	logic east_enable_o_west_1;

	
	
	router 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_west_1
		(
			.router_mode(router_mode_west_1),
			
			
			//Interface with North
			//Source ports
			.north_data_i(north_data_i_west_1),
			.north_enable_i(north_enable_i_west_1),
			
			//Destination ports
			.north_data_o(north_data_o_west_1),
			.north_enable_o(north_enable_o_west_1),
			
			
			//Interface with South
			//Source ports
			.south_data_i(south_data_i_west_1),
			.south_enable_i(south_enable_i_west_1),
			
			//Destination ports
			.south_data_o(south_data_o_west_1),
			.south_enable_o(south_enable_o_west_1),
			
			
			//Interface with West
			//Source ports
			.west_data_i(west_data_i_west_1),
			.west_enable_i(west_enable_i_west_1),
			
			//Destination ports
			.west_data_o(west_data_0_west_1),
			.west_enable_o(west_enable_o_west_1),
			
			
			//Interface with East
			//Source ports
			.east_data_i(router_east_1.west_data_o),
			.east_enable_i(router_east_1.west_enable_o),
	        
			//Destination ports
	        .east_data_o(router_east_1.west_data_i),
            .east_enable_o(router_east_1.west_enable_i)
		);
	
	
	
	///////////////      ROUTER EAST 1      ///////////////////////////////////
		
		
	logic [3:0] router_mode_east_1;
	

	//Interface with North
	//Source ports
	logic [DATA_WIDTH-1:0] north_data_i_east_1;
	logic north_enable_i_east_1;

	//Destination ports
	logic [DATA_WIDTH-1:0] north_data_o_east_1;
	logic north_enable_o_east_1;

	
	
	//Interface with South
	//Source ports
	logic [DATA_WIDTH-1:0] south_data_i_east_1;
	logic south_enable_i_east_1;

	//Destination ports
	logic [DATA_WIDTH-1:0] south_data_o_east_1;
	logic south_enable_o_east_1;

	
	
	//Interface with West
	//Source ports
//	logic [DATA_WIDTH-1:0] west_data_i_east_1;
//	logic west_enable_i_east_1;
	
	//Destination ports
//	logic [DATA_WIDTH-1:0] west_data_o_east_1;
//	logic west_enable_o_east_1;

	
	
	//Interface with East
	//Source ports
	logic [DATA_WIDTH-1:0] east_data_i_east_1;
	logic east_enable_i_east_1;

	//Destination ports
	logic [DATA_WIDTH-1:0] east_data_o_east_1;
	logic east_enable_o_east_1;

	
	
	router 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_east_1
		(
			.router_mode(router_mode_east_1),
			
			
			//Interface with North
			//Source ports
			.north_data_i(north_data_i_east_1),
			.north_enable_i(north_enable_i_east_1),
			
			//Destination ports
			.north_data_o(north_data_o_east_1),
			.north_enable_o(north_enable_o_east_1),
			
			
			//Interface with South
			//Source ports
			.south_data_i(south_data_i_east_1),
			.south_enable_i(south_enable_i_east_1),
			
			//Destination ports
			.south_data_o(south_data_o_east_1),
			.south_enable_o(south_enable_o_east_1),
			
			
			//Interface with West
			//Source ports
			.west_data_i(router_west_1.east_data_o),
			.west_enable_i(router_west_1.east_enable_o),
			
			//Destination ports
			.west_data_o(router_west_1.east_data_i),
			.west_enable_o(router_west_1.east_enable_i),
			
			
			//Interface with East
			//Source ports
			.east_data_i(east_data_i_east_1),
			.east_enable_i(east_enable_i_east_1),
	        
			//Destination ports
	        .east_data_o(east_data_o_east_1),
            .east_enable_o(east_enable_o_east_1)
		);
		
		
		
		 	initial begin
		for(int i=0; i<20; i++) begin
			north_data_i_west_0 = i;
			north_data_i_west_1 = i*10;
			#50;
		end
	end
	
	enum logic [3:0] {ALL=0, NORTH=1, SOUTH=2, WEST=3, EAST=4,
						EASTNORTH=5, EASTSOUTH=6, EASTWEST=7,
						WESTNORTH=8, WESTSOUTH=9, WESTEAST=10} direction;
	
	initial begin
		#100;

		router_mode_west_0 = EASTSOUTH;
		north_enable_i_west_0 = 1;
		#100;
		router_mode_east_0 = NORTH;
		
		
		
		#300;
		
		
		router_mode_west_1 = EASTSOUTH;
		north_enable_i_west_1 = 1;
		#100;
		router_mode_east_1 = SOUTH;
		
	end 

endmodule


================================================
FILE: testbench/router_pe_4_clusters_5x5_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/13/2019 04:47:06 AM
// Design Name: 
// Module Name: router_pe_4_clusters
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_pe_4_clusters_5x5_tb();

	parameter DATA_WIDTH = 16;
	
	
	///////////////      WGHT ROUTER WEST 0      ///////////////////////////////////
	
	logic [3:0] router_mode_west_0_whgt;
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i_west_0_whgt;
	logic west_enable_i_west_0_whgt;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] west_data_o_west_0_whgt;
	logic west_enable_o_west_0_whgt;

	
	
		///////////////      WGHT ROUTER WEST 1     ///////////////////////////////////
	
	logic [3:0] router_mode_west_1_whgt;
	
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i_west_1_whgt;
	logic west_enable_i_west_1_whgt;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] west_data_o_west_1_whgt;
	logic west_enable_o_west_1_whgt;

		
			///////////////      WGHT ROUTER EAST 0    ///////////////////////////////////
	
	logic [3:0] router_mode_east_0_whgt;
	
	
	//Interface with East
	//Source ports
	logic [DATA_WIDTH-1:0] east_data_i_east_0_whgt;
	logic east_enable_i_east_0_whgt;

	//Destination ports
	logic [DATA_WIDTH-1:0] east_data_o_east_0_whgt;
	logic east_enable_o_east_0_whgt;

		
		
			///////////////      WGHT ROUTER EAST 1     ///////////////////////////////////
	
	logic [3:0] router_mode_east_1_whgt;
	
	
	//Interface with East
	//Source ports
	logic [DATA_WIDTH-1:0] east_data_i_east_1_whgt;
	logic east_enable_i_east_1_whgt;

	//Destination ports
	logic [DATA_WIDTH-1:0] east_data_o_east_1_whgt;
	logic east_enable_o_east_1_whgt;

	
	
	router_network4 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	network_wght
		(
			.router_mode_west_0(router_mode_west_0_whgt),
			.router_mode_west_1(router_mode_west_1_whgt),
			.router_mode_east_0(router_mode_east_0_whgt),
			.router_mode_east_1(router_mode_east_1_whgt),
			
			
			//WEST 0
			//Source Ports
			.west_data_i_west_0(west_data_i_west_0_whgt),
			.west_enable_i_west_0(west_enable_i_west_0_whgt),
			
			//Destination ports
			.west_data_o_west_0(west_data_o_west_0_whgt),
			.west_enable_o_west_0(west_enable_o_west_0_whgt),
			
			
			
			//WEST 1
			//Source Ports
			.west_data_i_west_1(west_data_i_west_1_whgt),
			.west_enable_i_west_1(west_enable_i_west_1_whgt),
			
			//Destination ports
			.west_data_o_west_1(west_data_o_west_1_whgt),
			.west_enable_o_west_1(west_enable_o_west_1_whgt),
			
			
			
			//EAST 0
			//Source Ports
			.east_data_i_east_0(east_data_i_east_0_whgt),
			.east_enable_i_east_0(east_enable_i_east_0_whgt),
			
			//Destination ports
			.east_data_o_east_0(east_data_o_east_0_whgt),
			.east_enable_o_east_0(east_enable_o_east_0_whgt),
			
			
			//east 1
			//Source Ports
			.east_data_i_east_1(east_data_i_east_1_whgt),
			.east_enable_i_east_1(east_enable_i_east_1_whgt),
			
			//Destination ports
			.east_data_o_east_1(east_data_o_east_1_whgt),
			.east_enable_o_east_1(east_enable_o_east_1_whgt)
			
		);

	
	
	
		///////////////      IACT ROUTER WEST 0      ///////////////////////////////////
	
	logic [3:0] router_mode_west_0_iact;
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i_west_0_iact;
	logic west_enable_i_west_0_iact;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] west_data_o_west_0_iact;
	logic west_enable_o_west_0_iact;

	
	
		///////////////      IACT ROUTER WEST 1     ///////////////////////////////////
	
	logic [3:0] router_mode_west_1_iact;
	
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i_west_1_iact;
	logic west_enable_i_west_1_iact;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] west_data_o_west_1_iact;
	logic west_enable_o_west_1_iact;

		
			///////////////      IACT ROUTER EAST 0    ///////////////////////////////////
	
	logic [3:0] router_mode_east_0_iact;
	
	
	//Interface with East
	//Source ports
	logic [DATA_WIDTH-1:0] east_data_i_east_0_iact;
	logic east_enable_i_east_0_iact;

	//Destination ports
	logic [DATA_WIDTH-1:0] east_data_o_east_0_iact;
	logic east_enable_o_east_0_iact;

		
		
			///////////////      IACT ROUTER EAST 1     ///////////////////////////////////
	
	logic [3:0] router_mode_east_1_iact;
	
	
	//Interface with East
	//Source ports
	logic [DATA_WIDTH-1:0] east_data_i_east_1_iact;
	logic east_enable_i_east_1_iact;

	//Destination ports
	logic [DATA_WIDTH-1:0] east_data_o_east_1_iact;
	logic east_enable_o_east_1_iact;

	
	
	router_network4 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	network_iact
		(
			.router_mode_west_0(router_mode_west_0_iact),
			.router_mode_west_1(router_mode_west_1_iact),
			.router_mode_east_0(router_mode_east_0_iact),
			.router_mode_east_1(router_mode_east_1_iact),
			
			
			//WEST 0
			//Source Ports
			.west_data_i_west_0(west_data_i_west_0_iact),
			.west_enable_i_west_0(west_enable_i_west_0_iact),
			
			//Destination ports
			.west_data_o_west_0(west_data_o_west_0_iact),
			.west_enable_o_west_0(west_enable_o_west_0_iact),
			
			
			
			//WEST 1
			//Source Ports
			.west_data_i_west_1(west_data_i_west_1_iact),
			.west_enable_i_west_1(west_enable_i_west_1_iact),
			
			//Destination ports
			.west_data_o_west_1(west_data_o_west_1_iact),
			.west_enable_o_west_1(west_enable_o_west_1_iact),
			
			
			
			//EAST 0
			//Source Ports
			.east_data_i_east_0(east_data_i_east_0_iact),
			.east_enable_i_east_0(east_enable_i_east_0_iact),
			
			//Destination ports
			.east_data_o_east_0(east_data_o_east_0_iact),
			.east_enable_o_east_0(east_enable_o_east_0_iact),
			
			
			//east 1
			//Source Ports
			.east_data_i_east_1(east_data_i_east_1_iact),
			.east_enable_i_east_1(east_enable_i_east_1_iact),
			
			//Destination ports
			.east_data_o_east_1(east_data_o_east_1_iact),
			.east_enable_o_east_1(east_enable_o_east_1_iact)
			
		);
		
		
	
	logic clk, reset;
	
	
	/////// INST PE CLUSTER
	parameter ADDR_WIDTH = 9;
    
    parameter int X_dim = 5;
    parameter int Y_dim = 5;
    
    parameter int kernel_size = 5;
    parameter int act_size = 7;
		
//    logic [DATA_WIDTH-1:0] act_in;
//    logic [DATA_WIDTH-1:0] filt_in;

	logic start;
	logic load_en_wght, load_en_iact;
  
	logic compute_done;
	logic load_done;
	
	
	logic [DATA_WIDTH-1:0] pe_out[X_dim-1:0];
	logic [DATA_WIDTH-1:0] pe_out_west_0[X_dim-1:0];
	logic [DATA_WIDTH-1:0] pe_out_west_1[X_dim-1:0];
	logic [DATA_WIDTH-1:0] pe_out_east_0[X_dim-1:0];
	logic [DATA_WIDTH-1:0] pe_out_east_1[X_dim-1:0];
	
	// PE CLUSTER WEST 0	
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_west_0
    			(
					.clk(clk),
				    .reset(reset),
					
				    .act_in(network_iact.west_data_o_west_0),
				    .filt_in(network_wght.west_data_o_west_0),
					
					.load_en_wght(load_en_wght),
					.load_en_act(load_en_iact),
					
					.start(start),
                    .pe_out(pe_out_west_0),
					.compute_done(compute_done),
					.load_done(load_done)
    			);
		
	
	// PE CLUSTER WEST 1
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_west_1
    			(
					.clk(clk),
				    .reset(reset),
					
				    .act_in(network_iact.west_data_o_west_1),
				    .filt_in(network_wght.west_data_o_west_1),
					
					.load_en_wght(load_en_wght),
					.load_en_act(load_en_iact),
					
					.start(start),
                    .pe_out(pe_out_west_1),
					.compute_done(),
					.load_done()
    			);
				
	
	// PE CLUSTER EAST 0
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_east_0
    			(
					.clk(clk),
				    .reset(reset),
					
				    .act_in(network_iact.east_data_o_east_0),
				    .filt_in(network_wght.east_data_o_east_0),
					
					.load_en_wght(load_en_wght),
					.load_en_act(load_en_iact),
					
					.start(start),
                    .pe_out(pe_out_east_0),
					.compute_done(),
					.load_done()
    			);
				
			
	// PE CLUSTER EAST 1	
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_east_1
    			(
					.clk(clk),
				    .reset(reset),
					
				    .act_in(network_iact.east_data_o_east_1),
				    .filt_in(network_wght.east_data_o_east_1),
					
					.load_en_wght(load_en_wght),
					.load_en_act(load_en_iact),
					
					.start(start),
                    .pe_out(pe_out_east_1),
					.compute_done(),
					.load_done()
    			);
		
/* 	logic [DATA_WIDTH-1:0] temp;
	assign temp = wght_router_east_0.south_data_o;
	
	logic temp_en;
	assign temp_en = wght_router_east_0.south_enable_o; */
	
		
/* 	initial begin
		for(int i=0; i<20; i++) begin
			west_data_i_west_0 = i;
//			south_data_i = i*2;
//			west_data_i = i*5;
//			east_data_i = i*100;
			#50;
		end
	end */
	
	
	integer clk_prd = 10;
	logic [DATA_WIDTH-1:0] cluster_out_1[0:8];
	
	always begin
		clk = 0; #(clk_prd/2);
		clk = 1; #(clk_prd/2);
		//0.1GHz
	end
	
	
	enum logic [3:0] {ALL=0, NORTH=1, SOUTH=2, WEST=3, EAST=4,
						EASTNORTH=5, EASTSOUTH=6, EASTWEST=7,
						WESTNORTH=8, WESTSOUTH=9, WESTEAST=10} direction;
	
	initial begin
	
		reset = 1; #30;
		reset = 0;
		start = 0;
		
		
		router_mode_west_0_whgt = ALL;

		router_mode_east_0_whgt = EASTSOUTH;
		
		router_mode_west_1_whgt = WEST;
		
		router_mode_east_1_whgt = EAST;
		
		

		#100;
		
		$display("\n\nLoading Begins: Weights.....\n\n");
		
		load_en_wght = 1;
		west_enable_i_west_0_whgt = 1;
		
		for(int i=0; i<kernel_size**2; i++) begin
			west_data_i_west_0_whgt = 1;
			#(clk_prd);
			load_en_wght = 0;
		end
		
		
		
		
		
		router_mode_east_0_iact = EAST;
		router_mode_east_1_iact = EAST;
		
		router_mode_west_0_iact = WEST;
		router_mode_west_1_iact = WEST;
		
		#100;
		
		$display("\n\nLoading Begins: Iacts.....\n\n");
		
		load_en_iact = 1;
		
		east_enable_i_east_0_iact = 1;
		east_enable_i_east_1_iact = 1;
		
		west_enable_i_west_0_iact = 1;
		west_enable_i_west_1_iact = 1;
		
		for(int i=1; i<act_size**2+1; i++) begin
			east_data_i_east_0_iact = i;
			east_data_i_east_1_iact = i+1;
			west_data_i_west_0_iact = i+2;
			west_data_i_west_1_iact = i+3;
			#(clk_prd);	
			load_en_iact = 0;
		end
		
		
		
		
		#50;
		
		assign pe_out = pe_out_east_0;
		
		start = 1; #25; 
		$display("\n\nReading & Computing Begins.....\n\n");
		start = 0;
		
		wait (compute_done == 1);
		
		$display("\n\nFinal PSUM of Iteration 1");
 		for(int i=0; i<X_dim; i++) begin
			cluster_out_1[i] = pe_out[X_dim-i-1];
			$display("\npsum from column %d is:%d",i+1,pe_out[X_dim-i-1]);
		end
		
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 2.....\n\n");
		start = 0;
		
				wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 2:");
 		for(int i=0; i<X_dim; i++) begin
			cluster_out_1[i+5] = pe_out[X_dim-i-1];
			$display("\npsum from column %d is:%d",i+1,pe_out[X_dim-i-1]);
		end
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 3.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 3:");
 		for(int i=0; i<X_dim; i++) begin
		cluster_out_1[i+10] = pe_out[X_dim-i-1];
			$display("\npsum from column %d is:%d",i+1,pe_out[X_dim-i-1]);
		end
		 
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 4.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 4:");
 		for(int i=0; i<X_dim; i++) begin
		cluster_out_1[i+15] = pe_out[X_dim-i-1];
			$display("\npsum from column %d is:%d",i+1,pe_out[X_dim-i-1]);
		end
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 5.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 5:");
 		for(int i=0; i<X_dim; i++) begin
		cluster_out_1[i+20] = pe_out[X_dim-i-1];
			$display("\npsum from column %d is:%d",i+1,pe_out[X_dim-i-1]);
		end
		
		
		$display("\tFinal psums of Cluster 1:\n");
		for(int a=0; a<kernel_size**2; a++) begin
			$display("\t\t %d \n",cluster_out_1[a]);
		end
		
		$display("\tTotal #cycles taken: %d",cycles);
		$stop;
		
		
	end 
	
		int cycles;
		// track # of cycles
	always @(posedge clk)
	begin
		if (reset)
			cycles = 0;
		else
			cycles = cycles + 1;
	end


endmodule


================================================
FILE: testbench/router_pe_4_clusters_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/13/2019 04:47:06 AM
// Design Name: 
// Module Name: router_pe_4_clusters
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_pe_4_clusters_tb();

	parameter DATA_WIDTH = 16;
	
	
	///////////////      WGHT ROUTER WEST 0      ///////////////////////////////////
	
	logic [3:0] router_mode_west_0_whgt;
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i_west_0_whgt;
	logic west_enable_i_west_0_whgt;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] west_data_o_west_0_whgt;
	logic west_enable_o_west_0_whgt;

	
	
		///////////////      WGHT ROUTER WEST 1     ///////////////////////////////////
	
	logic [3:0] router_mode_west_1_whgt;
	
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i_west_1_whgt;
	logic west_enable_i_west_1_whgt;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] west_data_o_west_1_whgt;
	logic west_enable_o_west_1_whgt;

		
			///////////////      WGHT ROUTER EAST 0    ///////////////////////////////////
	
	logic [3:0] router_mode_east_0_whgt;
	
	
	//Interface with East
	//Source ports
	logic [DATA_WIDTH-1:0] east_data_i_east_0_whgt;
	logic east_enable_i_east_0_whgt;

	//Destination ports
	logic [DATA_WIDTH-1:0] east_data_o_east_0_whgt;
	logic east_enable_o_east_0_whgt;

		
		
			///////////////      WGHT ROUTER EAST 1     ///////////////////////////////////
	
	logic [3:0] router_mode_east_1_whgt;
	
	
	//Interface with East
	//Source ports
	logic [DATA_WIDTH-1:0] east_data_i_east_1_whgt;
	logic east_enable_i_east_1_whgt;

	//Destination ports
	logic [DATA_WIDTH-1:0] east_data_o_east_1_whgt;
	logic east_enable_o_east_1_whgt;

	
	
	router_network4 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	network_wght
		(
			.router_mode_west_0(router_mode_west_0_whgt),
			.router_mode_west_1(router_mode_west_1_whgt),
			.router_mode_east_0(router_mode_east_0_whgt),
			.router_mode_east_1(router_mode_east_1_whgt),
			
			
			//WEST 0
			//Source Ports
			.west_data_i_west_0(west_data_i_west_0_whgt),
			.west_enable_i_west_0(west_enable_i_west_0_whgt),
			
			//Destination ports
			.west_data_o_west_0(west_data_o_west_0_whgt),
			.west_enable_o_west_0(west_enable_o_west_0_whgt),
			
			
			
			//WEST 1
			//Source Ports
			.west_data_i_west_1(west_data_i_west_1_whgt),
			.west_enable_i_west_1(west_enable_i_west_1_whgt),
			
			//Destination ports
			.west_data_o_west_1(west_data_o_west_1_whgt),
			.west_enable_o_west_1(west_enable_o_west_1_whgt),
			
			
			
			//EAST 0
			//Source Ports
			.east_data_i_east_0(east_data_i_east_0_whgt),
			.east_enable_i_east_0(east_enable_i_east_0_whgt),
			
			//Destination ports
			.east_data_o_east_0(east_data_o_east_0_whgt),
			.east_enable_o_east_0(east_enable_o_east_0_whgt),
			
			
			//east 1
			//Source Ports
			.east_data_i_east_1(east_data_i_east_1_whgt),
			.east_enable_i_east_1(east_enable_i_east_1_whgt),
			
			//Destination ports
			.east_data_o_east_1(east_data_o_east_1_whgt),
			.east_enable_o_east_1(east_enable_o_east_1_whgt)
			
		);

	
	
	
		///////////////      IACT ROUTER WEST 0      ///////////////////////////////////
	
	logic [3:0] router_mode_west_0_iact;
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i_west_0_iact;
	logic west_enable_i_west_0_iact;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] west_data_o_west_0_iact;
	logic west_enable_o_west_0_iact;

	
	
		///////////////      IACT ROUTER WEST 1     ///////////////////////////////////
	
	logic [3:0] router_mode_west_1_iact;
	
	
	//Interface with West
	//Source ports
	logic [DATA_WIDTH-1:0] west_data_i_west_1_iact;
	logic west_enable_i_west_1_iact;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] west_data_o_west_1_iact;
	logic west_enable_o_west_1_iact;

		
			///////////////      IACT ROUTER EAST 0    ///////////////////////////////////
	
	logic [3:0] router_mode_east_0_iact;
	
	
	//Interface with East
	//Source ports
	logic [DATA_WIDTH-1:0] east_data_i_east_0_iact;
	logic east_enable_i_east_0_iact;

	//Destination ports
	logic [DATA_WIDTH-1:0] east_data_o_east_0_iact;
	logic east_enable_o_east_0_iact;

		
		
			///////////////      IACT ROUTER EAST 1     ///////////////////////////////////
	
	logic [3:0] router_mode_east_1_iact;
	
	
	//Interface with East
	//Source ports
	logic [DATA_WIDTH-1:0] east_data_i_east_1_iact;
	logic east_enable_i_east_1_iact;

	//Destination ports
	logic [DATA_WIDTH-1:0] east_data_o_east_1_iact;
	logic east_enable_o_east_1_iact;

	
	
	router_network4 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	network_iact
		(
			.router_mode_west_0(router_mode_west_0_iact),
			.router_mode_west_1(router_mode_west_1_iact),
			.router_mode_east_0(router_mode_east_0_iact),
			.router_mode_east_1(router_mode_east_1_iact),
			
			
			//WEST 0
			//Source Ports
			.west_data_i_west_0(west_data_i_west_0_iact),
			.west_enable_i_west_0(west_enable_i_west_0_iact),
			
			//Destination ports
			.west_data_o_west_0(west_data_o_west_0_iact),
			.west_enable_o_west_0(west_enable_o_west_0_iact),
			
			
			
			//WEST 1
			//Source Ports
			.west_data_i_west_1(west_data_i_west_1_iact),
			.west_enable_i_west_1(west_enable_i_west_1_iact),
			
			//Destination ports
			.west_data_o_west_1(west_data_o_west_1_iact),
			.west_enable_o_west_1(west_enable_o_west_1_iact),
			
			
			
			//EAST 0
			//Source Ports
			.east_data_i_east_0(east_data_i_east_0_iact),
			.east_enable_i_east_0(east_enable_i_east_0_iact),
			
			//Destination ports
			.east_data_o_east_0(east_data_o_east_0_iact),
			.east_enable_o_east_0(east_enable_o_east_0_iact),
			
			
			//east 1
			//Source Ports
			.east_data_i_east_1(east_data_i_east_1_iact),
			.east_enable_i_east_1(east_enable_i_east_1_iact),
			
			//Destination ports
			.east_data_o_east_1(east_data_o_east_1_iact),
			.east_enable_o_east_1(east_enable_o_east_1_iact)
			
		);
		
		
	
	logic clk, reset;
	
	
	/////// INST PE CLUSTER
	parameter ADDR_WIDTH = 9;
    
    parameter int X_dim = 3;
    parameter int Y_dim = 3;
    
    parameter int kernel_size = 3;
    parameter int act_size = 5;
		
//    logic [DATA_WIDTH-1:0] act_in;
//    logic [DATA_WIDTH-1:0] filt_in;

	logic start;
	logic load_en_wght, load_en_iact;
  
	logic compute_done;
	logic load_done;
	
	
	logic [DATA_WIDTH-1:0] pe_out[X_dim-1:0];
	logic [DATA_WIDTH-1:0] pe_out_west_0[X_dim-1:0];
	logic [DATA_WIDTH-1:0] pe_out_west_1[X_dim-1:0];
	logic [DATA_WIDTH-1:0] pe_out_east_0[X_dim-1:0];
	logic [DATA_WIDTH-1:0] pe_out_east_1[X_dim-1:0];
	
	// PE CLUSTER WEST 0	
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_west_0
    			(
					.clk(clk),
				    .reset(reset),
					
				    .act_in(network_iact.west_data_o_west_0),
				    .filt_in(network_wght.west_data_o_west_0),
					
					.load_en_wght(load_en_wght),
					.load_en_act(load_en_iact),
					
					.start(start),
                    .pe_out(pe_out_west_0),
					.compute_done(compute_done),
					.load_done(load_done)
    			);
		
	
	// PE CLUSTER WEST 1
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_west_1
    			(
					.clk(clk),
				    .reset(reset),
					
				    .act_in(network_iact.west_data_o_west_1),
				    .filt_in(network_wght.west_data_o_west_1),
					
					.load_en_wght(load_en_wght),
					.load_en_act(load_en_iact),
					
					.start(start),
                    .pe_out(pe_out_west_1),
					.compute_done(),
					.load_done()
    			);
				
	
	// PE CLUSTER EAST 0
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_east_0
    			(
					.clk(clk),
				    .reset(reset),
					
				    .act_in(network_iact.east_data_o_east_0),
				    .filt_in(network_wght.east_data_o_east_0),
					
					.load_en_wght(load_en_wght),
					.load_en_act(load_en_iact),
					
					.start(start),
                    .pe_out(pe_out_east_0),
					.compute_done(),
					.load_done()
    			);
				
			
	// PE CLUSTER EAST 1	
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_east_1
    			(
					.clk(clk),
				    .reset(reset),
					
				    .act_in(network_iact.east_data_o_east_1),
				    .filt_in(network_wght.east_data_o_east_1),
					
					.load_en_wght(load_en_wght),
					.load_en_act(load_en_iact),
					
					.start(start),
                    .pe_out(pe_out_east_1),
					.compute_done(),
					.load_done()
    			);
		
/* 	logic [DATA_WIDTH-1:0] temp;
	assign temp = wght_router_east_0.south_data_o;
	
	logic temp_en;
	assign temp_en = wght_router_east_0.south_enable_o; */
	
		
/* 	initial begin
		for(int i=0; i<20; i++) begin
			west_data_i_west_0 = i;
//			south_data_i = i*2;
//			west_data_i = i*5;
//			east_data_i = i*100;
			#50;
		end
	end */
	
	
	integer clk_prd = 10;
	logic [DATA_WIDTH-1:0] cluster_out_1[0:8];
	
	always begin
		clk = 0; #(clk_prd/2);
		clk = 1; #(clk_prd/2);
		//0.1GHz
	end
	
	
	enum logic [3:0] {ALL=0, NORTH=1, SOUTH=2, WEST=3, EAST=4,
						EASTNORTH=5, EASTSOUTH=6, EASTWEST=7,
						WESTNORTH=8, WESTSOUTH=9, WESTEAST=10} direction;
	
	initial begin
	
		reset = 1; #30;
		reset = 0;
		start = 0;
		
		
		router_mode_west_0_whgt = ALL;

		router_mode_east_0_whgt = EASTSOUTH;
		
		router_mode_west_1_whgt = WEST;
		
		router_mode_east_1_whgt = EAST;
		
		

		#100;
		
		$display("\n\nLoading Begins: Weights.....\n\n");
		
		load_en_wght = 1;
		west_enable_i_west_0_whgt = 1;
		
		for(int i=0; i<kernel_size**2; i++) begin
			west_data_i_west_0_whgt = i+1;
			#(clk_prd);
			load_en_wght = 0;
		end
		
		
		
		
		
		router_mode_east_0_iact = EAST;
		router_mode_east_1_iact = EAST;
		
		router_mode_west_0_iact = WEST;
		router_mode_west_1_iact = WEST;
		
		#100;
		
		$display("\n\nLoading Begins: Iacts.....\n\n");
		
		load_en_iact = 1;
		
		east_enable_i_east_0_iact = 1;
		east_enable_i_east_1_iact = 1;
		
		west_enable_i_west_0_iact = 1;
		west_enable_i_west_1_iact = 1;
		
		for(int i=1; i<act_size**2+1; i++) begin
			east_data_i_east_0_iact = i;
			east_data_i_east_1_iact = i+2;
			west_data_i_west_0_iact = i*5;
			west_data_i_west_1_iact = i+3;
			#(clk_prd);
			load_en_iact = 0;
		end
		
		
		
		
		#50;
		
		assign pe_out = pe_out_east_0;
		
		start = 1; #25; 
		$display("\n\nReading & Computing Begins.....\n\n");
		start = 0;
		
		wait (compute_done == 1);
		
		$display("\n\nFinal PSUM of Iteration 1");
 		for(int i=0; i<X_dim; i++) begin
			cluster_out_1[i] = pe_out[X_dim-i-1];
			$display("\npsum from column %d is:%d",i+1,pe_out[X_dim-i-1]);
		end
		
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 2.....\n\n");
		start = 0;
		
				wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 2:");
 		for(int i=0; i<X_dim; i++) begin
			cluster_out_1[i+3] = pe_out[X_dim-i-1];
			$display("\npsum from column %d is:%d",i+1,pe_out[X_dim-i-1]);
		end
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 3.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 3:");
 		for(int i=0; i<X_dim; i++) begin
		cluster_out_1[i+6] = pe_out[X_dim-i-1];
			$display("\npsum from column %d is:%d",i+1,pe_out[X_dim-i-1]);
		end
		 
		
		$display("\tFinal psums of Cluster 1:\n");
		for(int a=0; a<kernel_size**2; a++) begin
			$display("\t\t %d \n",cluster_out_1[a]);
		end
		
		$display("\tTotal #cycles taken: %d",cycles);
		$stop;
		
		
	end 
	
		int cycles;
		// track # of cycles
	always @(posedge clk)
	begin
		if (reset)
			cycles = 0;
		else
			cycles = cycles + 1;
	end


endmodule


================================================
FILE: testbench/router_psum_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/03/2019 01:09:58 PM
// Design Name: 
// Module Name: router_psum_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_psum_tb();

	parameter DATA_BITWIDTH = 16;
	parameter ADDR_BITWIDTH = 10;
	
	// GLB Cluster parameters. This TestBench uses only 1 of each
    parameter NUM_GLB_IACT = 1;
    parameter NUM_GLB_PSUM = 1;
	parameter NUM_GLB_WGHT = 1;
	
	
    logic clk;
    logic reset;

	//logic for GLB cluster
//    logic read_req_iact;
	logic read_req_psum;
//	logic read_req_wght;
	
    logic write_en_iact;
	logic write_en_psum;
	logic write_en_wght;
	
//    logic [ADDR_BITWIDTH-1 : 0] r_addr_iact;
    logic [ADDR_BITWIDTH-1 : 0] r_addr_psum;
//	logic [ADDR_BITWIDTH-1 : 0] r_addr_wght;
	
    logic [ADDR_BITWIDTH-1 : 0] w_addr_iact;
    logic [ADDR_BITWIDTH-1 : 0] w_addr_psum;
	logic [ADDR_BITWIDTH-1 : 0] w_addr_wght;
	
    logic [DATA_BITWIDTH-1 : 0] w_data_iact;
    logic [DATA_BITWIDTH-1 : 0] w_data_psum;
	logic [DATA_BITWIDTH-1 : 0] w_data_wght;
	
//    logic [DATA_BITWIDTH-1 : 0] r_data_iact;
    logic [DATA_BITWIDTH-1 : 0] r_data_psum;
//   logic [DATA_BITWIDTH-1 : 0] r_data_wght;
	
	logic compute_done;
	
	//GLB cluster initialization
	GLB_cluster 
			#(	.DATA_BITWIDTH(DATA_BITWIDTH),
				.ADDR_BITWIDTH(ADDR_BITWIDTH),
				.NUM_GLB_IACT(NUM_GLB_IACT),
				.NUM_GLB_PSUM(NUM_GLB_PSUM),
				.NUM_GLB_WGHT(NUM_GLB_WGHT)
			)
	GLB_cluster_0
			(
				.clk(clk), 
				.reset(reset),
				
				.read_req_iact(router_iact_0.read_req_glb_iact),
				.read_req_psum(read_req_psum),
//				.read_req_wght(read_req_wght),
				.read_req_wght(router_weight_0.read_req_glb_wght),
				
				.write_en_iact(write_en_iact),
				.write_en_psum(write_en_psum),
				.write_en_wght(write_en_wght),
				
				.r_addr_iact(router_iact_0.r_addr_glb_iact),
			    .r_addr_psum(r_addr_psum),
//				.r_addr_wght(r_addr_wght),
				.r_addr_wght(router_weight_0.r_addr_glb_wght),

			    .w_addr_iact(w_addr_iact),
			    .w_addr_psum(w_addr_psum),
				.w_addr_wght(w_addr_wght),

			    .w_data_iact(w_data_iact),
			    .w_data_psum(w_data_psum),
				.w_data_wght(w_data_wght),

			    .r_data_iact(router_iact_0.r_data_glb_iact),
			    .r_data_psum(r_data_psum),
//				.r_data_wght(r_data_wght)
				.r_data_wght(router_weight_0.r_data_glb_wght)
			);

			
	//Declarations for weight router
	parameter ADDR_BITWIDTH_GLB = 10;
	parameter ADDR_BITWIDTH_SPAD = 9;
	
	parameter int kernel_size = 3;
	parameter int act_size = 5;
	
	parameter W_READ_ADDR = 0;
	
	parameter W_LOAD_ADDR = 0;
	
	parameter PSUM_READ_ADDR = 500;
	parameter PSUM_LOAD_ADDR = 0;
	
//	logic [ADDR_BITWIDTH_SPAD-1 : 0] w_addr_spad;
	logic [DATA_BITWIDTH-1 : 0] w_data_spad_wght;
	
	logic [DATA_BITWIDTH-1 : 0] r_data_glb_wght;
	
	logic load_en_spad_wght;
	
	logic load_spad_ctrl;
	
			
	//Weight Router Instantiation
	router_weight #(.DATA_BITWIDTH(DATA_BITWIDTH),
					.ADDR_BITWIDTH_GLB(ADDR_BITWIDTH_GLB),
					.ADDR_BITWIDTH_SPAD(ADDR_BITWIDTH_SPAD),
//					X_dim = 5,
//	                Y_dim = 3,
	                .kernel_size(kernel_size),
	                .act_size(act_size),
					
					.W_READ_ADDR(W_READ_ADDR), 
	                .W_LOAD_ADDR(W_LOAD_ADDR),
					
					.PSUM_READ_ADDR(PSUM_READ_ADDR),
					.PSUM_LOAD_ADDR(PSUM_LOAD_ADDR)
				)
	router_weight_0
				(	.clk(clk),
					.reset(reset),
					
					.r_data_glb_wght(GLB_cluster_0.r_data_wght),
//					read_wght_ctrl,
					 .r_addr_glb_wght(GLB_cluster_0.r_addr_wght),
					 .read_req_glb_wght(GLB_cluster_0.read_req_wght),
					
					//for writing to spad
//					write_wght_ctrl,
//					.w_addr_spad(w_addr_spad),
					.w_data_spad(w_data_spad_wght),
					.load_en_spad(load_en_spad_wght),
					
					//Input from control unit to load weights to spad
					.load_spad_ctrl(load_spad_ctrl)
				);
	
	
	parameter A_READ_ADDR = 0;
	parameter A_LOAD_ADDR = 100;
	
//	logic [ADDR_BITWIDTH_SPAD-1 : 0] w_addr_spad_iact;
	logic [DATA_BITWIDTH-1 : 0] w_data_spad_iact;
	
	logic [DATA_BITWIDTH-1 : 0] r_data_glb_iact;
	
	logic load_en_spad_iact;
	
	logic load_spad_ctrl_iact;
			
	//Activation Router Instantiation
	router_iact #(.DATA_BITWIDTH(DATA_BITWIDTH),
					.ADDR_BITWIDTH_GLB(ADDR_BITWIDTH_GLB),
					.ADDR_BITWIDTH_SPAD(ADDR_BITWIDTH_SPAD),
//					X_dim = 5,
//	                Y_dim = 3,
	                .kernel_size(kernel_size),
	                .act_size(act_size),
					
					.A_READ_ADDR(A_READ_ADDR), 
	                .A_LOAD_ADDR(A_LOAD_ADDR),
					
					.PSUM_READ_ADDR(PSUM_READ_ADDR),
					.PSUM_LOAD_ADDR(PSUM_LOAD_ADDR)
				)
	router_iact_0
				(	.clk(clk),
					.reset(reset),
					
					.r_data_glb_iact(GLB_cluster_0.r_data_iact),
//					read_wght_ctrl,
					 .r_addr_glb_iact(GLB_cluster_0.r_addr_iact),
					 .read_req_glb_iact(GLB_cluster_0.read_req_iact),
					
					//for writing to spad
//					write_wght_ctrl,
//					.w_addr_spad(w_addr_spad),
					.w_data_spad(w_data_spad_iact),
					.load_en_spad(load_en_spad_iact),
					
					//Input from control unit to load weights to spad
					.load_spad_ctrl(load_spad_ctrl_iact)
				);	
	
		//psum Router Instantiation
	router_psum #(.DATA_BITWIDTH(DATA_BITWIDTH),
					.ADDR_BITWIDTH_GLB(ADDR_BITWIDTH_GLB),
					.ADDR_BITWIDTH_SPAD(ADDR_BITWIDTH_SPAD),
//					X_dim = 5,
//	                Y_dim = 3,
	                .kernel_size(kernel_size),
	                .act_size(act_size),
					
					.PSUM_LOAD_ADDR(PSUM_LOAD_ADDR)
				)
	router_psum_0
				(	.clk(clk),
					.reset(reset),
					
					.r_data_spad_psum(pe_cluster_0.pe_out),
//					read_wght_ctrl,
//					.r_addr_glb_iact(GLB_cluster_0.r_addr_iact),
//					 .read_req_glb_iact(GLB_cluster_0.read_req_iact),
					
					//for writing to spad
//					write_wght_ctrl,
					.w_addr_glb_psum(w_addr_psum),
					.w_data_glb_psum(w_data_psum),
					.write_en_glb_psum(write_en_psum),
					
					//Input from control unit to load weights to spad
					.write_psum_ctrl(compute_done)
				);	
				
	parameter DATA_WIDTH = 16;
    parameter ADDR_WIDTH = 9;
	parameter int X_dim = 3;
    parameter int Y_dim = 3;
	
	logic [DATA_WIDTH-1:0] act_in;
    logic [DATA_WIDTH-1:0] filt_in;
//    logic load_en;
	logic start;
	logic load_en_wght, load_en_act;

    logic [DATA_WIDTH-1:0] pe_out[X_dim-1:0];
  

	logic load_done;
	
//	logic [DATA_WIDTH-1:0] psum_out[0 : X_dim*Y_dim-1];
	
	PE_cluster #(
					.DATA_WIDTH(DATA_WIDTH),
					.ADDR_WIDTH(ADDR_WIDTH),
					
					.kernel_size(kernel_size),
					.act_size(act_size),
					
					.X_dim(X_dim),
					.Y_dim(Y_dim)
    			)
	pe_cluster_0
    			(
					.clk(clk),
				    .reset(reset),
				    .act_in(w_data_spad_iact),
//				    .filt_in(filt_in),
					.filt_in(w_data_spad_wght),
//				    .load_en(load_en),
					.load_en_wght(load_en_spad_wght),
					.load_en_act(load_en_spad_iact),
					.start(start),
                    .pe_out(router_psum_0.r_data_spad_psum),
					.compute_done(compute_done),
					.load_done(load_done)
					
		//extra
//					.psum_out(psum_out)
    			);
				

	
	integer clk_prd = 10;
	
	always begin
		clk = 0; #(clk_prd/2);
		clk = 1; #(clk_prd/2);
		//0.1GHz
	end
	
	integer kernel_1,act_1;
	integer w_addr = 0;
	int args;
	
	initial begin
		reset = 1; #30;
		reset = 0;
		

		//Write weights to weight glb
		write_en_wght = 1;
		kernel_1 = $fopen("kernel_3x3.txt","r");		
		while(!$feof(kernel_1))begin
			w_addr_wght = w_addr;
			args = $fscanf(kernel_1,"%d\n",w_data_wght);
			$display("Writing value %0d to address %0d in weight glb",w_data_wght,w_addr);
			w_addr++;
			#(clk_prd);
		end
		write_en_wght = 0;
		$fclose(kernel_1); 
		
		
		//Write activations to weight glb
		write_en_iact = 1;
		w_addr = 0;
		act_1 = $fopen("act_5x5.txt","r");
		while(!$feof(act_1))begin
			w_addr_iact = w_addr;
			args = $fscanf(act_1,"%d\n",w_data_iact);
			$display("Writing value %0d to address %0d in iact glb",w_data_iact,w_addr);
			w_addr++;
			#(clk_prd);
		end
		write_en_iact = 0;
		$fclose(act_1); 
		
		
		
		#300;
		load_spad_ctrl = 1; #15;
		load_spad_ctrl = 0;
		
		wait (load_done == 1);
		
		#50;
		load_spad_ctrl_iact = 1; #15;
		load_spad_ctrl_iact = 0;
	
		wait (load_done == 1);
	
		#100;
		
		start = 1; #25; 
		$display("\n\nReading & Computing Begins.....\n\n");
		start = 0;
		
		wait (compute_done == 1);
		$display("\n\nPE_OUT from cluster is:%d\n,%d\n,%d\n",pe_cluster_0.pe_out[0],pe_cluster_0.pe_out[1],pe_cluster_0.pe_out[2]);
		#40
		$display("\n\nFinal PSUM of Iteration 1");
 		for(int i=0; i<X_dim; i++) begin
			$display("\npsum from column %d is:%d",i+1,pe_out[i]);
		end
		
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 2.....\n\n");
		start = 0;
		
				wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 2:");
 		for(int i=0; i<X_dim; i++) begin
			$display("\npsum from column %d is:%d",i+1,pe_out[i]);
		end
		
		#40;
		start = 1; #25; 
		$display("\n\nReading & Computing Begins for iter 3.....\n\n");
		start = 0;
		
		wait (compute_done == 1);	
		$display("\n\nFinal PSUM of Iteration 3:");
 		for(int i=0; i<X_dim; i++) begin
			$display("\npsum from column %d is:%d",i+1,pe_out[i]);
		end

	end
	
endmodule







================================================
FILE: testbench/router_unicast_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/11/2019 07:36:26 PM
// Design Name: 
// Module Name: router_unicast_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_unicast_tb();

	parameter DATA_WIDTH = 16;
	
	
	///////////////      ROUTER WEST 0      ///////////////////////////////////
	
	logic [3:0] router_mode_west_0;
	
	
	//Interface with North
	//Source ports
	logic [DATA_WIDTH-1:0] north_data_i_west_0;
	logic north_enable_i_west_0;

	//Destination ports
	logic [DATA_WIDTH-1:0] north_data_o_west_0;
	logic north_enable_o_west_0;

	
	
	//Interface with South
	//Source ports
	logic [DATA_WIDTH-1:0] south_data_i_west_0;
	logic south_enable_i_west_0;

	//Destination ports
	logic [DATA_WIDTH-1:0] south_data_o_west_0;
	logic south_enable_o_west_0;

	
	
	//Interface with West
	//Source ports
 logic [DATA_WIDTH-1:0] west_data_i_west_0;
	logic west_enable_i_west_0;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] west_data_o_west_0;
	logic west_enable_o_west_0;

	
	
	//Interface with East
	//Source ports
//	logic [DATA_WIDTH-1:0] east_data_i_west_0;
//	logic east_enable_i_west_0;

	//Destination ports
//	logic [DATA_WIDTH-1:0] east_data_o_west_0;
//	logic east_enable_o_west_0;

	
	
	router 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_west_0
		(
			.router_mode(router_mode_west_0),
			
			
			//Interface with North
			//Source ports
			.north_data_i(north_data_i_west_0),
			.north_enable_i(north_enable_i_west_0),
			
			//Destination ports
			.north_data_o(north_data_o_west_0),
			.north_enable_o(north_enable_o_west_0),
			
			
			//Interface with South
			//Source ports
			.south_data_i(south_data_i_west_0),
			.south_enable_i(south_enable_i_west_0),
			
			//Destination ports
			.south_data_o(south_data_o_west_0),
			.south_enable_o(south_enable_o_west_0),
			
			
			//Interface with West
			//Source ports
			.west_data_i(west_data_i_west_0),
			.west_enable_i(west_enable_i_west_0),
			
			//Destination ports
			.west_data_o(west_data_0_west_0),
			.west_enable_o(west_enable_o_west_0),
			
			
			//Interface with East
			//Source ports
			.east_data_i(router_east_0.west_data_o),
			.east_enable_i(router_east_0.west_enable_o),
	        
			//Destination ports
	        .east_data_o(router_east_0.west_data_i),
            .east_enable_o(router_east_0.west_enable_i)
		);
	
	
	
	///////////////      ROUTER EAST 0      ///////////////////////////////////
		
		
	logic [3:0] router_mode_east_0;
	

	//Interface with North
	//Source ports
	logic [DATA_WIDTH-1:0] north_data_i_east_0;
	logic north_enable_i_east_0;

	//Destination ports
	logic [DATA_WIDTH-1:0] north_data_o_east_0;
	logic north_enable_o_east_0;

	
	
	//Interface with South
	//Source ports
	logic [DATA_WIDTH-1:0] south_data_i_east_0;
	logic south_enable_i_east_0;

	//Destination ports
	logic [DATA_WIDTH-1:0] south_data_o_east_0;
	logic south_enable_o_east_0;

	
	
	//Interface with West
	//Source ports
//	logic [DATA_WIDTH-1:0] west_data_i_east_0;
//	logic west_enable_i_east_0;
	
	//Destination ports
//	logic [DATA_WIDTH-1:0] west_data_o_east_0;
//	logic west_enable_o_east_0;

	
	
	//Interface with East
	//Source ports
	logic [DATA_WIDTH-1:0] east_data_i_east_0;
	logic east_enable_i_east_0;

	//Destination ports
	logic [DATA_WIDTH-1:0] east_data_o_east_0;
	logic east_enable_o_east_0;

	
	
	router 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_east_0
		(
			.router_mode(router_mode_east_0),
			
			
			//Interface with North
			//Source ports
			.north_data_i(north_data_i_east_0),
			.north_enable_i(north_enable_i_east_0),
			
			//Destination ports
			.north_data_o(north_data_o_east_0),
			.north_enable_o(north_enable_o_east_0),
			
			
			//Interface with South
			//Source ports
			.south_data_i(south_data_i_east_0),
			.south_enable_i(south_enable_i_east_0),
			
			//Destination ports
			.south_data_o(south_data_o_east_0),
			.south_enable_o(south_enable_o_east_0),
			
			
			//Interface with West
			//Source ports
			.west_data_i(router_west_0.east_data_o),
			.west_enable_i(router_west_0.east_enable_o),
			
			//Destination ports
			.west_data_o(router_west_0.east_data_i),
			.west_enable_o(router_west_0.east_enable_i),
			
			
			//Interface with East
			//Source ports
			.east_data_i(east_data_i_east_0),
			.east_enable_i(east_enable_i_east_0),
	        
			//Destination ports
	        .east_data_o(east_data_o_east_0),
            .east_enable_o(east_enable_o_east_0)
		);


		
		
	////////////// ROUTER WEST 1 /////////////////////////	
		
	logic [3:0] router_mode_west_1;
	
	
	//Interface with North
	//Source ports
	logic [DATA_WIDTH-1:0] north_data_i_west_1;
	logic north_enable_i_west_1;

	//Destination ports
	logic [DATA_WIDTH-1:0] north_data_o_west_1;
	logic north_enable_o_west_1;

	
	
	//Interface with South
	//Source ports
	logic [DATA_WIDTH-1:0] south_data_i_west_1;
	logic south_enable_i_west_1;

	//Destination ports
	logic [DATA_WIDTH-1:0] south_data_o_west_1;
	logic south_enable_o_west_1;

	
	
	//Interface with West
	//Source ports
 logic [DATA_WIDTH-1:0] west_data_i_west_1;
	logic west_enable_i_west_1;
	
	//Destination ports
	logic [DATA_WIDTH-1:0] west_data_o_west_1;
	logic west_enable_o_west_1;

	
	
	//Interface with East
	//Source ports
//	logic [DATA_WIDTH-1:0] east_data_i_west_1;
//	logic east_enable_i_west_1;

	//Destination ports
//	logic [DATA_WIDTH-1:0] east_data_o_west_1;
//	logic east_enable_o_west_1;

	
	
	router 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_west_1
		(
			.router_mode(router_mode_west_1),
			
			
			//Interface with North
			//Source ports
			.north_data_i(north_data_i_west_1),
			.north_enable_i(north_enable_i_west_1),
			
			//Destination ports
			.north_data_o(north_data_o_west_1),
			.north_enable_o(north_enable_o_west_1),
			
			
			//Interface with South
			//Source ports
			.south_data_i(south_data_i_west_1),
			.south_enable_i(south_enable_i_west_1),
			
			//Destination ports
			.south_data_o(south_data_o_west_1),
			.south_enable_o(south_enable_o_west_1),
			
			
			//Interface with West
			//Source ports
			.west_data_i(west_data_i_west_1),
			.west_enable_i(west_enable_i_west_1),
			
			//Destination ports
			.west_data_o(west_data_0_west_1),
			.west_enable_o(west_enable_o_west_1),
			
			
			//Interface with East
			//Source ports
			.east_data_i(router_east_0.west_data_o),
			.east_enable_i(router_east_0.west_enable_o),
	        
			//Destination ports
	        .east_data_o(router_east_0.west_data_i),
            .east_enable_o(router_east_0.west_enable_i)
		);
	
	
	
	///////////////      ROUTER EAST 1      ///////////////////////////////////
		
		
	logic [3:0] router_mode_east_1;
	

	//Interface with North
	//Source ports
	logic [DATA_WIDTH-1:0] north_data_i_east_1;
	logic north_enable_i_east_1;

	//Destination ports
	logic [DATA_WIDTH-1:0] north_data_o_east_1;
	logic north_enable_o_east_1;

	
	
	//Interface with South
	//Source ports
	logic [DATA_WIDTH-1:0] south_data_i_east_1;
	logic south_enable_i_east_1;

	//Destination ports
	logic [DATA_WIDTH-1:0] south_data_o_east_1;
	logic south_enable_o_east_1;

	
	
	//Interface with West
	//Source ports
//	logic [DATA_WIDTH-1:0] west_data_i_east_1;
//	logic west_enable_i_east_1;
	
	//Destination ports
//	logic [DATA_WIDTH-1:0] west_data_o_east_1;
//	logic west_enable_o_east_1;

	
	
	//Interface with East
	//Source ports
	logic [DATA_WIDTH-1:0] east_data_i_east_1;
	logic east_enable_i_east_1;

	//Destination ports
	logic [DATA_WIDTH-1:0] east_data_o_east_1;
	logic east_enable_o_east_1;

	
	
	router 
		#(
			.DATA_WIDTH(DATA_WIDTH)
		)
	router_east_1
		(
			.router_mode(router_mode_east_1),
			
			
			//Interface with North
			//Source ports
			.north_data_i(north_data_i_east_1),
			.north_enable_i(north_enable_i_east_1),
			
			//Destination ports
			.north_data_o(north_data_o_east_1),
			.north_enable_o(north_enable_o_east_1),
			
			
			//Interface with South
			//Source ports
			.south_data_i(south_data_i_east_1),
			.south_enable_i(south_enable_i_east_1),
			
			//Destination ports
			.south_data_o(south_data_o_east_1),
			.south_enable_o(south_enable_o_east_1),
			
			
			//Interface with West
			//Source ports
			.west_data_i(router_west_1.east_data_o),
			.west_enable_i(router_west_1.east_enable_o),
			
			//Destination ports
			.west_data_o(router_west_1.east_data_i),
			.west_enable_o(router_west_1.east_enable_i),
			
			
			//Interface with East
			//Source ports
			.east_data_i(east_data_i_east_1),
			.east_enable_i(east_enable_i_east_1),
	        
			//Destination ports
	        .east_data_o(east_data_o_east_1),
            .east_enable_o(east_enable_o_east_1)
		);
		
		
		
		 	initial begin
		for(int i=0; i<20; i++) begin
			north_data_i_west_0 = i;
			north_data_i_west_1 = i*2;
			north_data_i_east_0 = i*10;
			north_data_i_east_1 = i*100;
			
			#50;
		end
	end
	
	enum logic [3:0] {ALL=0, NORTH=1, SOUTH=2, WEST=3, EAST=4,
						EASTNORTH=5, EASTSOUTH=6, EASTWEST=7,
						WESTNORTH=8, WESTSOUTH=9, WESTEAST=10} direction;
	
	initial begin
		router_mode_west_0 = SOUTH;
		north_enable_i_west_0 = 1;

		#100;
		router_mode_east_0 = SOUTH;
		north_enable_i_east_0 = 1;
		
		#100;
		router_mode_west_1 = SOUTH;
		north_enable_i_west_1 = 1;
		
		#100;
		router_mode_east_1 = SOUTH;
		north_enable_i_east_1 = 1;
		
	end 
	
		
endmodule


================================================
FILE: testbench/router_weight.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/01/2019 03:50:08 PM
// Design Name: 
// Module Name: router_weight
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_weight #( parameter DATA_BITWIDTH = 16,
						parameter ADDR_BITWIDTH_GLB = 10,
						parameter ADDR_BITWIDTH_SPAD = 9,
						
						parameter int X_dim = 5,
                        parameter int Y_dim = 3,
                        parameter int kernel_size = 3,
                        parameter int act_size = 5,
						
						parameter W_READ_ADDR = 0, 
                        
                        parameter W_LOAD_ADDR = 0,
						
						parameter PSUM_READ_ADDR = 500,
						parameter PSUM_LOAD_ADDR = 0
					)
					
					(	input clk,
						input reset,
						
						//for reading glb
						input [DATA_BITWIDTH-1 : 0] r_data_glb_wght,
						output logic [ADDR_BITWIDTH_GLB-1 : 0] r_addr_glb_wght,
						output logic read_req_glb_wght,
						
						//for writing to spad
						output logic [DATA_BITWIDTH-1 : 0] w_data_spad,
						output logic load_en_spad,
						
						//Input from control unit to load weights to spad
						input load_spad_ctrl
			
					);
				
					
		enum logic [2:0] {IDLE=3'b000, READ_GLB=3'b001, WRITE_SPAD=3'b010, READ_GLB_0=3'b011} state;
		
		logic [4:0] filt_count;
		
		always@(posedge clk) begin
//			$display("State: %s", state.name());
			if(reset) begin
				read_req_glb_wght <= 0;
				r_addr_glb_wght <= 0;
				load_en_spad <= 0;
				filt_count <= 0;
				state <= IDLE;
			end else begin
				case(state)
					IDLE:begin
						if(load_spad_ctrl) begin
							read_req_glb_wght <= 1;
							r_addr_glb_wght <= W_READ_ADDR;
							state <= READ_GLB;
						end else begin
							read_req_glb_wght = 0;
							load_en_spad = 0;
							state <= IDLE;
						end
					end
					
					READ_GLB:begin
						load_en_spad <= 1;
						filt_count <= filt_count + 1;
						r_addr_glb_wght <= r_addr_glb_wght + 1;
						w_data_spad <= r_data_glb_wght;
						state <= WRITE_SPAD;
					end
					
					WRITE_SPAD:begin
						if(filt_count == (kernel_size**2)) begin
							w_data_spad <= r_data_glb_wght;
							filt_count <= 0;
							r_addr_glb_wght <= W_READ_ADDR;
							
							state <= IDLE;
						end else begin
							w_data_spad <= r_data_glb_wght;
							filt_count <= filt_count + 1;
							r_addr_glb_wght <= r_addr_glb_wght + 1;
							state <= WRITE_SPAD;
						end
					end
				endcase
			end
		end
 
endmodule


================================================
FILE: testbench/router_weight_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/01/2019 07:02:07 PM
// Design Name: 
// Module Name: router_weight_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module router_weight_tb();

	parameter DATA_BITWIDTH = 16;
	parameter ADDR_BITWIDTH = 10;
	
	// GLB Cluster parameters. This TestBench uses only 1 of each
    parameter NUM_GLB_IACT = 1;
    parameter NUM_GLB_PSUM = 1;
	parameter NUM_GLB_WGHT = 1;
	
	
    logic clk;
    logic reset;

	//logic for GLB cluster
    logic read_req_iact;
	logic read_req_psum;
	logic read_req_wght;
	
    logic write_en_iact;
	logic write_en_psum;
	logic write_en_wght;
	
    logic [ADDR_BITWIDTH-1 : 0] r_addr_iact;
    logic [ADDR_BITWIDTH-1 : 0] r_addr_psum;
	logic [ADDR_BITWIDTH-1 : 0] r_addr_wght;
	
    logic [ADDR_BITWIDTH-1 : 0] w_addr_iact;
    logic [ADDR_BITWIDTH-1 : 0] w_addr_psum;
	logic [ADDR_BITWIDTH-1 : 0] w_addr_wght;
	
    logic [DATA_BITWIDTH-1 : 0] w_data_iact;
    logic [DATA_BITWIDTH-1 : 0] w_data_psum;
	logic [DATA_BITWIDTH-1 : 0] w_data_wght;
	
    logic [DATA_BITWIDTH-1 : 0] r_data_iact;
    logic [DATA_BITWIDTH-1 : 0] r_data_psum;
    logic [DATA_BITWIDTH-1 : 0] r_data_wght;

	
	//GLB cluster initialization
	GLB_cluster 
			#(	.DATA_BITWIDTH(DATA_BITWIDTH),
				.ADDR_BITWIDTH(ADDR_BITWIDTH),
				.NUM_GLB_IACT(NUM_GLB_IACT),
				.NUM_GLB_PSUM(NUM_GLB_PSUM),
				.NUM_GLB_WGHT(NUM_GLB_WGHT)
			)
	GLB_cluster_0
			(
				.clk(clk), 
				.reset(reset),
				
				.read_req_iact(read_req_iact),
				.read_req_psum(read_req_psum),
//				.read_req_wght(read_req_wght),
				.read_req_wght(router_weight_0.read_req_glb_wght),
				
				.write_en_iact(write_en_iact),
				.write_en_psum(write_en_psum),
				.write_en_wght(write_en_wght),
				
				.r_addr_iact(r_addr_iact),
			    .r_addr_psum(r_addr_psum),
//				.r_addr_wght(r_addr_wght),
				.r_addr_wght(router_weight_0.r_addr_glb_wght),

			    .w_addr_iact(w_addr_iact),
			    .w_addr_psum(w_addr_psum),
				.w_addr_wght(w_addr_wght),

			    .w_data_iact(w_data_iact),
			    .w_data_psum(w_data_psum),
				.w_data_wght(w_data_wght),

			    .r_data_iact(r_data_iact),
			    .r_data_psum(r_data_psum),
//				.r_data_wght(r_data_wght)
				.r_data_wght(router_weight_0.r_data_glb_wght)
			);

			
	//Declarations for weight router
	parameter ADDR_BITWIDTH_GLB = 10;
	parameter ADDR_BITWIDTH_SPAD = 9;
	
	parameter int kernel_size = 3;
	parameter int act_size = 5;
	
	parameter W_READ_ADDR = 0;
	
	parameter W_LOAD_ADDR = 0;
	
	parameter PSUM_READ_ADDR = 500;
	parameter PSUM_LOAD_ADDR = 0;
	
	logic [ADDR_BITWIDTH_SPAD-1 : 0] w_addr_spad;
	logic [DATA_BITWIDTH-1 : 0] w_data_spad;
	
	logic [DATA_BITWIDTH-1 : 0] r_data_glb_wght;
	
	logic load_en_spad;
	
	logic load_spad_ctrl;
	
			
	//Weight Router Instantiation
	router_weight #(.DATA_BITWIDTH(DATA_BITWIDTH),
					.ADDR_BITWIDTH_GLB(ADDR_BITWIDTH_GLB),
					.ADDR_BITWIDTH_SPAD(ADDR_BITWIDTH_SPAD),
//					X_dim = 5,
//	                Y_dim = 3,
	                .kernel_size(kernel_size),
	                .act_size(act_size),
					
					.W_READ_ADDR(W_READ_ADDR), 
	                .W_LOAD_ADDR(W_LOAD_ADDR),
					
					.PSUM_READ_ADDR(PSUM_READ_ADDR),
					.PSUM_LOAD_ADDR(PSUM_LOAD_ADDR)
				)
	router_weight_0
				(	.clk(clk),
					.reset(reset),
					
					.r_data_glb_wght(GLB_cluster_0.r_data_wght),
//					read_wght_ctrl,
					 .r_addr_glb_wght(GLB_cluster_0.r_addr_wght),
					 .read_req_glb_wght(GLB_cluster_0.read_req_wght),
					
					//for writing to spad
//					write_wght_ctrl,
//					.w_addr_spad(w_addr_spad),
					.w_data_spad(w_data_spad),
					.load_en_spad(load_en_spad),
					
					//Input from control unit to load weights to spad
					.load_spad_ctrl(load_spad_ctrl)
				);
	
	
	
	integer clk_prd = 10;
	
	always begin
		clk = 0; #(clk_prd/2);
		clk = 1; #(clk_prd/2);
		//0.1GHz
	end
	
	integer kernel_1,act_1;
	integer w_addr = 0;
	int args;
	
	initial begin
		reset = 1; #30;
		reset = 0;
		

		//Write weights to weight glb
		write_en_wght = 1;
		kernel_1 = $fopen("kernel_3x3.txt","r");		
		while(!$feof(kernel_1))begin
			w_addr_wght = w_addr;
			args = $fscanf(kernel_1,"%d\n",w_data_wght);
			$display("Writing value %0d to address %0d in weight glb",w_data_wght,w_addr);
			w_addr++;
			#(clk_prd);
		end
		write_en_wght = 0;
		$fclose(kernel_1); 
		
		
		//Write activations to weight glb
		write_en_iact = 1;
		w_addr = 0;
		act_1 = $fopen("act_5x5.txt","r");
		while(!$feof(act_1))begin
			w_addr_iact = w_addr;
			args = $fscanf(act_1,"%d\n",w_data_iact);
			$display("Writing value %0d to address %0d in iact glb",w_data_iact,w_addr);
			w_addr++;
			#(clk_prd);
		end
		write_en_iact = 0;
		$fclose(act_1); 
		
		#30;
		load_spad_ctrl = 1; #15;
		load_spad_ctrl = 0;
	
	end
	
endmodule



================================================
FILE: testbench/switch_tb.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 12/09/2019 07:38:58 AM
// Design Name: 
// Module Name: switch_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module switch_tb();

	parameter DATA_WIDTH = 16;
	
	logic [DATA_WIDTH-1:0] a, b, c, d;
	
	logic [3:0] s;
//	logic [1:0] sel;
	
	logic [DATA_WIDTH-1:0] out;

	
/* 	lookup_mux4 lookup_0 ( .in(s), .out(sel) );
	mux_4x1 mux_0 ( .sel(sel), .a(a), .b(b), .c(c), .d(d), .out(out) ); */
	
	switch switch_0 ( .a(a), .b(b), .c(c), .d(d), .out(out), .sel(s) );

	initial begin
		for(int i=0; i<10; i++) begin
			a = i;
			#50;
		end
	end
	
	initial begin
		for(int i=10; i<20; i++) begin
			b = i;
			#50;
		end
	end
	
	initial begin
		for(int i=20; i<30; i++) begin
			c = i;
			#50;
		end
	end
	
		initial begin
		for(int i=30; i<40; i++) begin
			d = i;
			#50;
		end
	end
	
	initial begin
		s = 4'b0000;
		#100;
		
		s = 4'b1000;
		#100;
		
		s = 4'b0010;
		#100;
		
		s = 4'b0100;
		#100;
			
		s = 4'b1100;
		#100;
		
	end
	
endmodule